1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * R8A77965 processor support - PFC hardware block. 4 * 5 * Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org> 6 * Copyright (C) 2016-2019 Renesas Electronics Corp. 7 * 8 * This file is based on the drivers/pinctrl/renesas/pfc-r8a7796.c 9 * 10 * R-Car Gen3 processor support - PFC hardware block. 11 * 12 * Copyright (C) 2015 Renesas Electronics Corporation 13 */ 14 15 #include <linux/errno.h> 16 #include <linux/kernel.h> 17 18 #include "core.h" 19 #include "sh_pfc.h" 20 21 #define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN) 22 23 #define CPU_ALL_GP(fn, sfx) \ 24 PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \ 25 PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \ 26 PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \ 27 PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \ 28 PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \ 29 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \ 30 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \ 31 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \ 32 PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \ 33 PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \ 34 PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \ 35 PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS) 36 37 #define CPU_ALL_NOGP(fn) \ 38 PIN_NOGP_CFG(ASEBRK, "ASEBRK", fn, CFG_FLAGS), \ 39 PIN_NOGP_CFG(AVB_MDIO, "AVB_MDIO", fn, CFG_FLAGS), \ 40 PIN_NOGP_CFG(AVB_RD0, "AVB_RD0", fn, CFG_FLAGS), \ 41 PIN_NOGP_CFG(AVB_RD1, "AVB_RD1", fn, CFG_FLAGS), \ 42 PIN_NOGP_CFG(AVB_RD2, "AVB_RD2", fn, CFG_FLAGS), \ 43 PIN_NOGP_CFG(AVB_RD3, "AVB_RD3", fn, CFG_FLAGS), \ 44 PIN_NOGP_CFG(AVB_RXC, "AVB_RXC", fn, CFG_FLAGS), \ 45 PIN_NOGP_CFG(AVB_RX_CTL, "AVB_RX_CTL", fn, CFG_FLAGS), \ 46 PIN_NOGP_CFG(AVB_TD0, "AVB_TD0", fn, CFG_FLAGS), \ 47 PIN_NOGP_CFG(AVB_TD1, "AVB_TD1", fn, CFG_FLAGS), \ 48 PIN_NOGP_CFG(AVB_TD2, "AVB_TD2", fn, CFG_FLAGS), \ 49 PIN_NOGP_CFG(AVB_TD3, "AVB_TD3", fn, CFG_FLAGS), \ 50 PIN_NOGP_CFG(AVB_TXC, "AVB_TXC", fn, CFG_FLAGS), \ 51 PIN_NOGP_CFG(AVB_TXCREFCLK, "AVB_TXCREFCLK", fn, CFG_FLAGS), \ 52 PIN_NOGP_CFG(AVB_TX_CTL, "AVB_TX_CTL", fn, CFG_FLAGS), \ 53 PIN_NOGP_CFG(DU_DOTCLKIN0, "DU_DOTCLKIN0", fn, CFG_FLAGS), \ 54 PIN_NOGP_CFG(DU_DOTCLKIN1, "DU_DOTCLKIN1", fn, CFG_FLAGS), \ 55 PIN_NOGP_CFG(DU_DOTCLKIN3, "DU_DOTCLKIN3", fn, CFG_FLAGS), \ 56 PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),\ 57 PIN_NOGP_CFG(FSCLKST, "FSCLKST", fn, CFG_FLAGS), \ 58 PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS), \ 59 PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, CFG_FLAGS), \ 60 PIN_NOGP_CFG(QSPI0_IO2, "QSPI0_IO2", fn, CFG_FLAGS), \ 61 PIN_NOGP_CFG(QSPI0_IO3, "QSPI0_IO3", fn, CFG_FLAGS), \ 62 PIN_NOGP_CFG(QSPI0_MISO_IO1, "QSPI0_MISO_IO1", fn, CFG_FLAGS), \ 63 PIN_NOGP_CFG(QSPI0_MOSI_IO0, "QSPI0_MOSI_IO0", fn, CFG_FLAGS), \ 64 PIN_NOGP_CFG(QSPI0_SPCLK, "QSPI0_SPCLK", fn, CFG_FLAGS), \ 65 PIN_NOGP_CFG(QSPI0_SSL, "QSPI0_SSL", fn, CFG_FLAGS), \ 66 PIN_NOGP_CFG(QSPI1_IO2, "QSPI1_IO2", fn, CFG_FLAGS), \ 67 PIN_NOGP_CFG(QSPI1_IO3, "QSPI1_IO3", fn, CFG_FLAGS), \ 68 PIN_NOGP_CFG(QSPI1_MISO_IO1, "QSPI1_MISO_IO1", fn, CFG_FLAGS), \ 69 PIN_NOGP_CFG(QSPI1_MOSI_IO0, "QSPI1_MOSI_IO0", fn, CFG_FLAGS), \ 70 PIN_NOGP_CFG(QSPI1_SPCLK, "QSPI1_SPCLK", fn, CFG_FLAGS), \ 71 PIN_NOGP_CFG(QSPI1_SSL, "QSPI1_SSL", fn, CFG_FLAGS), \ 72 PIN_NOGP_CFG(RPC_INT_N, "RPC_INT#", fn, CFG_FLAGS), \ 73 PIN_NOGP_CFG(RPC_RESET_N, "RPC_RESET#", fn, CFG_FLAGS), \ 74 PIN_NOGP_CFG(RPC_WP_N, "RPC_WP#", fn, CFG_FLAGS), \ 75 PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ 76 PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ 77 PIN_NOGP_CFG(TDO, "TDO", fn, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \ 78 PIN_NOGP_CFG(TMS, "TMS", fn, CFG_FLAGS), \ 79 PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN) 80 81 /* 82 * F_() : just information 83 * FM() : macro for FN_xxx / xxx_MARK 84 */ 85 86 /* GPSR0 */ 87 #define GPSR0_15 F_(D15, IP7_11_8) 88 #define GPSR0_14 F_(D14, IP7_7_4) 89 #define GPSR0_13 F_(D13, IP7_3_0) 90 #define GPSR0_12 F_(D12, IP6_31_28) 91 #define GPSR0_11 F_(D11, IP6_27_24) 92 #define GPSR0_10 F_(D10, IP6_23_20) 93 #define GPSR0_9 F_(D9, IP6_19_16) 94 #define GPSR0_8 F_(D8, IP6_15_12) 95 #define GPSR0_7 F_(D7, IP6_11_8) 96 #define GPSR0_6 F_(D6, IP6_7_4) 97 #define GPSR0_5 F_(D5, IP6_3_0) 98 #define GPSR0_4 F_(D4, IP5_31_28) 99 #define GPSR0_3 F_(D3, IP5_27_24) 100 #define GPSR0_2 F_(D2, IP5_23_20) 101 #define GPSR0_1 F_(D1, IP5_19_16) 102 #define GPSR0_0 F_(D0, IP5_15_12) 103 104 /* GPSR1 */ 105 #define GPSR1_28 FM(CLKOUT) 106 #define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8) 107 #define GPSR1_26 F_(WE1_N, IP5_7_4) 108 #define GPSR1_25 F_(WE0_N, IP5_3_0) 109 #define GPSR1_24 F_(RD_WR_N, IP4_31_28) 110 #define GPSR1_23 F_(RD_N, IP4_27_24) 111 #define GPSR1_22 F_(BS_N, IP4_23_20) 112 #define GPSR1_21 F_(CS1_N, IP4_19_16) 113 #define GPSR1_20 F_(CS0_N, IP4_15_12) 114 #define GPSR1_19 F_(A19, IP4_11_8) 115 #define GPSR1_18 F_(A18, IP4_7_4) 116 #define GPSR1_17 F_(A17, IP4_3_0) 117 #define GPSR1_16 F_(A16, IP3_31_28) 118 #define GPSR1_15 F_(A15, IP3_27_24) 119 #define GPSR1_14 F_(A14, IP3_23_20) 120 #define GPSR1_13 F_(A13, IP3_19_16) 121 #define GPSR1_12 F_(A12, IP3_15_12) 122 #define GPSR1_11 F_(A11, IP3_11_8) 123 #define GPSR1_10 F_(A10, IP3_7_4) 124 #define GPSR1_9 F_(A9, IP3_3_0) 125 #define GPSR1_8 F_(A8, IP2_31_28) 126 #define GPSR1_7 F_(A7, IP2_27_24) 127 #define GPSR1_6 F_(A6, IP2_23_20) 128 #define GPSR1_5 F_(A5, IP2_19_16) 129 #define GPSR1_4 F_(A4, IP2_15_12) 130 #define GPSR1_3 F_(A3, IP2_11_8) 131 #define GPSR1_2 F_(A2, IP2_7_4) 132 #define GPSR1_1 F_(A1, IP2_3_0) 133 #define GPSR1_0 F_(A0, IP1_31_28) 134 135 /* GPSR2 */ 136 #define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20) 137 #define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16) 138 #define GPSR2_12 F_(AVB_LINK, IP0_15_12) 139 #define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8) 140 #define GPSR2_10 F_(AVB_MAGIC, IP0_7_4) 141 #define GPSR2_9 F_(AVB_MDC, IP0_3_0) 142 #define GPSR2_8 F_(PWM2_A, IP1_27_24) 143 #define GPSR2_7 F_(PWM1_A, IP1_23_20) 144 #define GPSR2_6 F_(PWM0, IP1_19_16) 145 #define GPSR2_5 F_(IRQ5, IP1_15_12) 146 #define GPSR2_4 F_(IRQ4, IP1_11_8) 147 #define GPSR2_3 F_(IRQ3, IP1_7_4) 148 #define GPSR2_2 F_(IRQ2, IP1_3_0) 149 #define GPSR2_1 F_(IRQ1, IP0_31_28) 150 #define GPSR2_0 F_(IRQ0, IP0_27_24) 151 152 /* GPSR3 */ 153 #define GPSR3_15 F_(SD1_WP, IP11_23_20) 154 #define GPSR3_14 F_(SD1_CD, IP11_19_16) 155 #define GPSR3_13 F_(SD0_WP, IP11_15_12) 156 #define GPSR3_12 F_(SD0_CD, IP11_11_8) 157 #define GPSR3_11 F_(SD1_DAT3, IP8_31_28) 158 #define GPSR3_10 F_(SD1_DAT2, IP8_27_24) 159 #define GPSR3_9 F_(SD1_DAT1, IP8_23_20) 160 #define GPSR3_8 F_(SD1_DAT0, IP8_19_16) 161 #define GPSR3_7 F_(SD1_CMD, IP8_15_12) 162 #define GPSR3_6 F_(SD1_CLK, IP8_11_8) 163 #define GPSR3_5 F_(SD0_DAT3, IP8_7_4) 164 #define GPSR3_4 F_(SD0_DAT2, IP8_3_0) 165 #define GPSR3_3 F_(SD0_DAT1, IP7_31_28) 166 #define GPSR3_2 F_(SD0_DAT0, IP7_27_24) 167 #define GPSR3_1 F_(SD0_CMD, IP7_23_20) 168 #define GPSR3_0 F_(SD0_CLK, IP7_19_16) 169 170 /* GPSR4 */ 171 #define GPSR4_17 F_(SD3_DS, IP11_7_4) 172 #define GPSR4_16 F_(SD3_DAT7, IP11_3_0) 173 #define GPSR4_15 F_(SD3_DAT6, IP10_31_28) 174 #define GPSR4_14 F_(SD3_DAT5, IP10_27_24) 175 #define GPSR4_13 F_(SD3_DAT4, IP10_23_20) 176 #define GPSR4_12 F_(SD3_DAT3, IP10_19_16) 177 #define GPSR4_11 F_(SD3_DAT2, IP10_15_12) 178 #define GPSR4_10 F_(SD3_DAT1, IP10_11_8) 179 #define GPSR4_9 F_(SD3_DAT0, IP10_7_4) 180 #define GPSR4_8 F_(SD3_CMD, IP10_3_0) 181 #define GPSR4_7 F_(SD3_CLK, IP9_31_28) 182 #define GPSR4_6 F_(SD2_DS, IP9_27_24) 183 #define GPSR4_5 F_(SD2_DAT3, IP9_23_20) 184 #define GPSR4_4 F_(SD2_DAT2, IP9_19_16) 185 #define GPSR4_3 F_(SD2_DAT1, IP9_15_12) 186 #define GPSR4_2 F_(SD2_DAT0, IP9_11_8) 187 #define GPSR4_1 F_(SD2_CMD, IP9_7_4) 188 #define GPSR4_0 F_(SD2_CLK, IP9_3_0) 189 190 /* GPSR5 */ 191 #define GPSR5_25 F_(MLB_DAT, IP14_19_16) 192 #define GPSR5_24 F_(MLB_SIG, IP14_15_12) 193 #define GPSR5_23 F_(MLB_CLK, IP14_11_8) 194 #define GPSR5_22 FM(MSIOF0_RXD) 195 #define GPSR5_21 F_(MSIOF0_SS2, IP14_7_4) 196 #define GPSR5_20 FM(MSIOF0_TXD) 197 #define GPSR5_19 F_(MSIOF0_SS1, IP14_3_0) 198 #define GPSR5_18 F_(MSIOF0_SYNC, IP13_31_28) 199 #define GPSR5_17 FM(MSIOF0_SCK) 200 #define GPSR5_16 F_(HRTS0_N, IP13_27_24) 201 #define GPSR5_15 F_(HCTS0_N, IP13_23_20) 202 #define GPSR5_14 F_(HTX0, IP13_19_16) 203 #define GPSR5_13 F_(HRX0, IP13_15_12) 204 #define GPSR5_12 F_(HSCK0, IP13_11_8) 205 #define GPSR5_11 F_(RX2_A, IP13_7_4) 206 #define GPSR5_10 F_(TX2_A, IP13_3_0) 207 #define GPSR5_9 F_(SCK2, IP12_31_28) 208 #define GPSR5_8 F_(RTS1_N, IP12_27_24) 209 #define GPSR5_7 F_(CTS1_N, IP12_23_20) 210 #define GPSR5_6 F_(TX1_A, IP12_19_16) 211 #define GPSR5_5 F_(RX1_A, IP12_15_12) 212 #define GPSR5_4 F_(RTS0_N, IP12_11_8) 213 #define GPSR5_3 F_(CTS0_N, IP12_7_4) 214 #define GPSR5_2 F_(TX0, IP12_3_0) 215 #define GPSR5_1 F_(RX0, IP11_31_28) 216 #define GPSR5_0 F_(SCK0, IP11_27_24) 217 218 /* GPSR6 */ 219 #define GPSR6_31 F_(GP6_31, IP18_7_4) 220 #define GPSR6_30 F_(GP6_30, IP18_3_0) 221 #define GPSR6_29 F_(USB30_OVC, IP17_31_28) 222 #define GPSR6_28 F_(USB30_PWEN, IP17_27_24) 223 #define GPSR6_27 F_(USB1_OVC, IP17_23_20) 224 #define GPSR6_26 F_(USB1_PWEN, IP17_19_16) 225 #define GPSR6_25 F_(USB0_OVC, IP17_15_12) 226 #define GPSR6_24 F_(USB0_PWEN, IP17_11_8) 227 #define GPSR6_23 F_(AUDIO_CLKB_B, IP17_7_4) 228 #define GPSR6_22 F_(AUDIO_CLKA_A, IP17_3_0) 229 #define GPSR6_21 F_(SSI_SDATA9_A, IP16_31_28) 230 #define GPSR6_20 F_(SSI_SDATA8, IP16_27_24) 231 #define GPSR6_19 F_(SSI_SDATA7, IP16_23_20) 232 #define GPSR6_18 F_(SSI_WS78, IP16_19_16) 233 #define GPSR6_17 F_(SSI_SCK78, IP16_15_12) 234 #define GPSR6_16 F_(SSI_SDATA6, IP16_11_8) 235 #define GPSR6_15 F_(SSI_WS6, IP16_7_4) 236 #define GPSR6_14 F_(SSI_SCK6, IP16_3_0) 237 #define GPSR6_13 FM(SSI_SDATA5) 238 #define GPSR6_12 FM(SSI_WS5) 239 #define GPSR6_11 FM(SSI_SCK5) 240 #define GPSR6_10 F_(SSI_SDATA4, IP15_31_28) 241 #define GPSR6_9 F_(SSI_WS4, IP15_27_24) 242 #define GPSR6_8 F_(SSI_SCK4, IP15_23_20) 243 #define GPSR6_7 F_(SSI_SDATA3, IP15_19_16) 244 #define GPSR6_6 F_(SSI_WS349, IP15_15_12) 245 #define GPSR6_5 F_(SSI_SCK349, IP15_11_8) 246 #define GPSR6_4 F_(SSI_SDATA2_A, IP15_7_4) 247 #define GPSR6_3 F_(SSI_SDATA1_A, IP15_3_0) 248 #define GPSR6_2 F_(SSI_SDATA0, IP14_31_28) 249 #define GPSR6_1 F_(SSI_WS01239, IP14_27_24) 250 #define GPSR6_0 F_(SSI_SCK01239, IP14_23_20) 251 252 /* GPSR7 */ 253 #define GPSR7_3 FM(GP7_03) 254 #define GPSR7_2 FM(GP7_02) 255 #define GPSR7_1 FM(AVS2) 256 #define GPSR7_0 FM(AVS1) 257 258 259 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ 260 #define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 261 #define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 262 #define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 263 #define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 264 #define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) FM(FSCLKST2_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 265 #define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 266 #define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 267 #define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 268 #define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 269 #define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) F_(0, 0) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 270 #define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) F_(0, 0) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 271 #define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) F_(0, 0) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) FM(FSCLKST2_N_B) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 272 #define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)F_(0, 0) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 273 #define IP1_23_20 FM(PWM1_A) F_(0, 0) F_(0, 0) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 274 #define IP1_27_24 FM(PWM2_A) F_(0, 0) F_(0, 0) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 275 #define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 276 #define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 277 #define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 278 #define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 279 #define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 280 #define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 281 #define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 282 #define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 283 #define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 284 #define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 285 #define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 286 #define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 287 288 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ 289 #define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 290 #define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 291 #define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 292 #define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 293 #define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 294 #define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 295 #define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 296 #define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 297 #define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 298 #define IP4_19_16 FM(CS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 299 #define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 300 #define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 301 #define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 302 #define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 303 #define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 304 #define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 305 #define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 306 #define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 307 #define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 308 #define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 309 #define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 310 #define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 311 #define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 312 #define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 313 #define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 314 #define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 315 #define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 316 #define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_C) FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 317 #define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 318 319 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ 320 #define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 321 #define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 322 #define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 323 #define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 324 #define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 325 #define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 326 #define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 327 #define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 328 #define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 329 #define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 330 #define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) FM(NFCE_N_B) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 331 #define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) FM(NFWP_N_B) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 332 #define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) FM(NFDATA14_B) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 333 #define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) FM(NFDATA15_B) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 334 #define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) FM(NFRB_N_B) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 335 #define IP9_3_0 FM(SD2_CLK) F_(0, 0) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 336 #define IP9_7_4 FM(SD2_CMD) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 337 #define IP9_11_8 FM(SD2_DAT0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 338 #define IP9_15_12 FM(SD2_DAT1) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 339 #define IP9_19_16 FM(SD2_DAT2) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 340 #define IP9_23_20 FM(SD2_DAT3) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 341 #define IP9_27_24 FM(SD2_DS) F_(0, 0) FM(NFALE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 342 #define IP9_31_28 FM(SD3_CLK) F_(0, 0) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 343 #define IP10_3_0 FM(SD3_CMD) F_(0, 0) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 344 #define IP10_7_4 FM(SD3_DAT0) F_(0, 0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 345 #define IP10_11_8 FM(SD3_DAT1) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 346 #define IP10_15_12 FM(SD3_DAT2) F_(0, 0) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 347 #define IP10_19_16 FM(SD3_DAT3) F_(0, 0) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 348 #define IP10_23_20 FM(SD3_DAT4) FM(SD2_CD_A) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 349 #define IP10_27_24 FM(SD3_DAT5) FM(SD2_WP_A) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 350 #define IP10_31_28 FM(SD3_DAT6) FM(SD3_CD) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 351 #define IP11_3_0 FM(SD3_DAT7) FM(SD3_WP) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 352 #define IP11_7_4 FM(SD3_DS) F_(0, 0) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 353 #define IP11_11_8 FM(SD0_CD) F_(0, 0) FM(NFDATA14_A) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 354 355 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ 356 #define IP11_15_12 FM(SD0_WP) F_(0, 0) FM(NFDATA15_A) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 357 #define IP11_19_16 FM(SD1_CD) F_(0, 0) FM(NFRB_N_A) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 358 #define IP11_23_20 FM(SD1_WP) F_(0, 0) FM(NFCE_N_A) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 359 #define IP11_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 360 #define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 361 #define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 362 #define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 363 #define IP12_11_8 FM(RTS0_N) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 364 #define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 365 #define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 366 #define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 367 #define IP12_27_24 FM(RTS1_N) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 368 #define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 369 #define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 370 #define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 371 #define IP13_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 372 #define IP13_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 373 #define IP13_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 374 #define IP13_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 375 #define IP13_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 376 #define IP13_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) FM(TX5_B) F_(0, 0) F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0) 377 #define IP14_3_0 FM(MSIOF0_SS1) FM(RX5_A) FM(NFWP_N_A) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 378 #define IP14_7_4 FM(MSIOF0_SS2) FM(TX5_A) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 379 #define IP14_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 380 #define IP14_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 381 #define IP14_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 382 #define IP14_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 383 #define IP14_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 384 385 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ 386 #define IP14_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 387 #define IP15_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 388 #define IP15_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 389 #define IP15_11_8 FM(SSI_SCK349) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 390 #define IP15_15_12 FM(SSI_WS349) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 391 #define IP15_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 392 #define IP15_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 393 #define IP15_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 394 #define IP15_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 395 #define IP16_3_0 FM(SSI_SCK6) F_(0, 0) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 396 #define IP16_7_4 FM(SSI_WS6) F_(0, 0) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 397 #define IP16_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 398 #define IP16_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 399 #define IP16_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 400 #define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 401 #define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 402 #define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 403 #define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 404 #define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 405 #define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0) 406 #define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0) 407 #define IP17_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0) 408 #define IP17_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0) 409 #define IP17_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0) 410 #define IP17_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_N) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 411 #define IP18_3_0 FM(GP6_30) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0) 412 #define IP18_7_4 FM(GP6_31) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0) 413 414 #define PINMUX_GPSR \ 415 \ 416 GPSR6_31 \ 417 GPSR6_30 \ 418 GPSR6_29 \ 419 GPSR1_28 GPSR6_28 \ 420 GPSR1_27 GPSR6_27 \ 421 GPSR1_26 GPSR6_26 \ 422 GPSR1_25 GPSR5_25 GPSR6_25 \ 423 GPSR1_24 GPSR5_24 GPSR6_24 \ 424 GPSR1_23 GPSR5_23 GPSR6_23 \ 425 GPSR1_22 GPSR5_22 GPSR6_22 \ 426 GPSR1_21 GPSR5_21 GPSR6_21 \ 427 GPSR1_20 GPSR5_20 GPSR6_20 \ 428 GPSR1_19 GPSR5_19 GPSR6_19 \ 429 GPSR1_18 GPSR5_18 GPSR6_18 \ 430 GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \ 431 GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \ 432 GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \ 433 GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \ 434 GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \ 435 GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \ 436 GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \ 437 GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \ 438 GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \ 439 GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \ 440 GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \ 441 GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \ 442 GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \ 443 GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \ 444 GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \ 445 GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \ 446 GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \ 447 GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0 448 449 #define PINMUX_IPSR \ 450 \ 451 FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \ 452 FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \ 453 FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \ 454 FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \ 455 FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \ 456 FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \ 457 FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \ 458 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \ 459 \ 460 FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \ 461 FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \ 462 FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \ 463 FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 \ 464 FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \ 465 FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \ 466 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \ 467 FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \ 468 \ 469 FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \ 470 FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \ 471 FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \ 472 FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \ 473 FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \ 474 FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \ 475 FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \ 476 FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \ 477 \ 478 FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \ 479 FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \ 480 FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \ 481 FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \ 482 FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \ 483 FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \ 484 FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \ 485 FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \ 486 \ 487 FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 FM(IP18_3_0) IP18_3_0 \ 488 FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 FM(IP18_7_4) IP18_7_4 \ 489 FM(IP16_11_8) IP16_11_8 FM(IP17_11_8) IP17_11_8 \ 490 FM(IP16_15_12) IP16_15_12 FM(IP17_15_12) IP17_15_12 \ 491 FM(IP16_19_16) IP16_19_16 FM(IP17_19_16) IP17_19_16 \ 492 FM(IP16_23_20) IP16_23_20 FM(IP17_23_20) IP17_23_20 \ 493 FM(IP16_27_24) IP16_27_24 FM(IP17_27_24) IP17_27_24 \ 494 FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28 495 496 /* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ 497 #define MOD_SEL0_31_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3) FM(SEL_MSIOF3_4) F_(0, 0) F_(0, 0) F_(0, 0) 498 #define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3) 499 #define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0) 500 #define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1) 501 #define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1) 502 #define MOD_SEL0_21 FM(SEL_I2C2_0) FM(SEL_I2C2_1) 503 #define MOD_SEL0_20 FM(SEL_I2C1_0) FM(SEL_I2C1_1) 504 #define MOD_SEL0_19 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1) 505 #define MOD_SEL0_18_17 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3) 506 #define MOD_SEL0_16 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1) 507 #define MOD_SEL0_14_13 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) FM(SEL_HSCIF2_2) F_(0, 0) 508 #define MOD_SEL0_12 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1) 509 #define MOD_SEL0_11 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1) 510 #define MOD_SEL0_10 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1) 511 #define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0) 512 #define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0) 513 #define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1) 514 #define MOD_SEL0_4_3 FM(SEL_ADGA_0) FM(SEL_ADGA_1) FM(SEL_ADGA_2) FM(SEL_ADGA_3) 515 516 /* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ 517 #define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3) 518 #define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0) 519 #define MOD_SEL1_26 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1) 520 #define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3) 521 #define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0) 522 #define MOD_SEL1_20 FM(SEL_SSI1_0) FM(SEL_SSI1_1) 523 #define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1) 524 #define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3) 525 #define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1) 526 #define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0) 527 #define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1) 528 #define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1) 529 #define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1) 530 #define MOD_SEL1_10 FM(SEL_SCIF_0) FM(SEL_SCIF_1) 531 #define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1) 532 #define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1) 533 #define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1) 534 #define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1) 535 #define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1) 536 #define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1) 537 #define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1) 538 #define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1) 539 540 /* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ 541 #define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1) 542 #define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1) 543 #define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1) 544 #define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3) 545 #define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1) 546 #define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 547 #define MOD_SEL2_22 FM(SEL_NDF_0) FM(SEL_NDF_1) 548 #define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1) 549 #define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1) 550 #define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1) 551 #define MOD_SEL2_18 FM(SEL_ADGB_0) FM(SEL_ADGB_1) 552 #define MOD_SEL2_17 FM(SEL_ADGC_0) FM(SEL_ADGC_1) 553 #define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1) 554 555 #define PINMUX_MOD_SELS \ 556 \ 557 MOD_SEL0_31_30_29 MOD_SEL1_31_30 MOD_SEL2_31 \ 558 MOD_SEL2_30 \ 559 MOD_SEL1_29_28_27 MOD_SEL2_29 \ 560 MOD_SEL0_28_27 MOD_SEL2_28_27 \ 561 MOD_SEL0_26_25_24 MOD_SEL1_26 MOD_SEL2_26 \ 562 MOD_SEL1_25_24 MOD_SEL2_25_24_23 \ 563 MOD_SEL0_23 MOD_SEL1_23_22_21 \ 564 MOD_SEL0_22 MOD_SEL2_22 \ 565 MOD_SEL0_21 MOD_SEL2_21 \ 566 MOD_SEL0_20 MOD_SEL1_20 MOD_SEL2_20 \ 567 MOD_SEL0_19 MOD_SEL1_19 MOD_SEL2_19 \ 568 MOD_SEL0_18_17 MOD_SEL1_18_17 MOD_SEL2_18 \ 569 MOD_SEL2_17 \ 570 MOD_SEL0_16 MOD_SEL1_16 \ 571 MOD_SEL1_15_14 \ 572 MOD_SEL0_14_13 \ 573 MOD_SEL1_13 \ 574 MOD_SEL0_12 MOD_SEL1_12 \ 575 MOD_SEL0_11 MOD_SEL1_11 \ 576 MOD_SEL0_10 MOD_SEL1_10 \ 577 MOD_SEL0_9_8 MOD_SEL1_9 \ 578 MOD_SEL0_7_6 \ 579 MOD_SEL1_6 \ 580 MOD_SEL0_5 MOD_SEL1_5 \ 581 MOD_SEL0_4_3 MOD_SEL1_4 \ 582 MOD_SEL1_3 \ 583 MOD_SEL1_2 \ 584 MOD_SEL1_1 \ 585 MOD_SEL1_0 MOD_SEL2_0 586 587 /* 588 * These pins are not able to be muxed but have other properties 589 * that can be set, such as drive-strength or pull-up/pull-down enable. 590 */ 591 #define PINMUX_STATIC \ 592 FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \ 593 FM(QSPI0_IO2) FM(QSPI0_IO3) \ 594 FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \ 595 FM(QSPI1_IO2) FM(QSPI1_IO3) \ 596 FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \ 597 FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \ 598 FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \ 599 FM(AVB_TXCREFCLK) FM(AVB_MDIO) \ 600 FM(PRESETOUT) \ 601 FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN3) \ 602 FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR) 603 604 #define PINMUX_PHYS \ 605 FM(SCL0) FM(SDA0) FM(SCL3) FM(SDA3) FM(SCL5) FM(SDA5) 606 607 enum { 608 PINMUX_RESERVED = 0, 609 610 PINMUX_DATA_BEGIN, 611 GP_ALL(DATA), 612 PINMUX_DATA_END, 613 614 #define F_(x, y) 615 #define FM(x) FN_##x, 616 PINMUX_FUNCTION_BEGIN, 617 GP_ALL(FN), 618 PINMUX_GPSR 619 PINMUX_IPSR 620 PINMUX_MOD_SELS 621 PINMUX_FUNCTION_END, 622 #undef F_ 623 #undef FM 624 625 #define F_(x, y) 626 #define FM(x) x##_MARK, 627 PINMUX_MARK_BEGIN, 628 PINMUX_GPSR 629 PINMUX_IPSR 630 PINMUX_MOD_SELS 631 PINMUX_STATIC 632 PINMUX_PHYS 633 PINMUX_MARK_END, 634 #undef F_ 635 #undef FM 636 }; 637 638 static const u16 pinmux_data[] = { 639 PINMUX_DATA_GP_ALL(), 640 641 PINMUX_SINGLE(AVS1), 642 PINMUX_SINGLE(AVS2), 643 PINMUX_SINGLE(CLKOUT), 644 PINMUX_SINGLE(GP7_03), 645 PINMUX_SINGLE(GP7_02), 646 PINMUX_SINGLE(MSIOF0_RXD), 647 PINMUX_SINGLE(MSIOF0_SCK), 648 PINMUX_SINGLE(MSIOF0_TXD), 649 PINMUX_SINGLE(SSI_SCK5), 650 PINMUX_SINGLE(SSI_SDATA5), 651 PINMUX_SINGLE(SSI_WS5), 652 653 /* IPSR0 */ 654 PINMUX_IPSR_GPSR(IP0_3_0, AVB_MDC), 655 PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2), 656 657 PINMUX_IPSR_GPSR(IP0_7_4, AVB_MAGIC), 658 PINMUX_IPSR_MSEL(IP0_7_4, MSIOF2_SS1_C, SEL_MSIOF2_2), 659 PINMUX_IPSR_MSEL(IP0_7_4, SCK4_A, SEL_SCIF4_0), 660 661 PINMUX_IPSR_GPSR(IP0_11_8, AVB_PHY_INT), 662 PINMUX_IPSR_MSEL(IP0_11_8, MSIOF2_SYNC_C, SEL_MSIOF2_2), 663 PINMUX_IPSR_MSEL(IP0_11_8, RX4_A, SEL_SCIF4_0), 664 665 PINMUX_IPSR_GPSR(IP0_15_12, AVB_LINK), 666 PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2), 667 PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0), 668 PINMUX_IPSR_GPSR(IP0_19_16, FSCLKST2_N_A), 669 670 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, I2C_SEL_5_0, SEL_ETHERAVB_0), 671 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, MSIOF2_RXD_C, I2C_SEL_5_0, SEL_MSIOF2_2), 672 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, CTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0), 673 PINMUX_IPSR_PHYS(IP0_19_16, SCL5, I2C_SEL_5_1), 674 675 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, I2C_SEL_5_0, SEL_ETHERAVB_0), 676 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C, I2C_SEL_5_0, SEL_MSIOF2_2), 677 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0), 678 PINMUX_IPSR_PHYS(IP0_23_20, SDA5, I2C_SEL_5_1), 679 680 PINMUX_IPSR_GPSR(IP0_27_24, IRQ0), 681 PINMUX_IPSR_GPSR(IP0_27_24, QPOLB), 682 PINMUX_IPSR_GPSR(IP0_27_24, DU_CDE), 683 PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1), 684 PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1), 685 PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_B, SEL_CANFD0_1), 686 PINMUX_IPSR_MSEL(IP0_27_24, MSIOF3_SS2_E, SEL_MSIOF3_4), 687 688 PINMUX_IPSR_GPSR(IP0_31_28, IRQ1), 689 PINMUX_IPSR_GPSR(IP0_31_28, QPOLA), 690 PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP), 691 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1), 692 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1), 693 PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1), 694 PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_SS1_E, SEL_MSIOF3_4), 695 696 /* IPSR1 */ 697 PINMUX_IPSR_GPSR(IP1_3_0, IRQ2), 698 PINMUX_IPSR_GPSR(IP1_3_0, QCPV_QDE), 699 PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE), 700 PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1), 701 PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1), 702 PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_SYNC_E, SEL_MSIOF3_4), 703 704 PINMUX_IPSR_GPSR(IP1_7_4, IRQ3), 705 PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE), 706 PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1), 707 PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1), 708 PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1), 709 PINMUX_IPSR_MSEL(IP1_7_4, MSIOF3_SCK_E, SEL_MSIOF3_4), 710 711 PINMUX_IPSR_GPSR(IP1_11_8, IRQ4), 712 PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS), 713 PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC), 714 PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1), 715 PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1), 716 PINMUX_IPSR_MSEL(IP1_11_8, MSIOF3_RXD_E, SEL_MSIOF3_4), 717 718 PINMUX_IPSR_GPSR(IP1_15_12, IRQ5), 719 PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE), 720 PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC), 721 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1), 722 PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1), 723 PINMUX_IPSR_GPSR(IP1_15_12, FSCLKST2_N_B), 724 PINMUX_IPSR_MSEL(IP1_15_12, MSIOF3_TXD_E, SEL_MSIOF3_4), 725 726 PINMUX_IPSR_GPSR(IP1_19_16, PWM0), 727 PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS), 728 PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1), 729 PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1), 730 731 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, PWM1_A, I2C_SEL_3_0, SEL_PWM1_0), 732 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3), 733 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1), 734 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1), 735 PINMUX_IPSR_PHYS(IP1_23_20, SCL3, I2C_SEL_3_1), 736 737 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0), 738 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D, I2C_SEL_3_0, SEL_HSCIF3_3), 739 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, IETX_B, I2C_SEL_3_0, SEL_IEBUS_1), 740 PINMUX_IPSR_PHYS(IP1_27_24, SDA3, I2C_SEL_3_1), 741 742 PINMUX_IPSR_GPSR(IP1_31_28, A0), 743 PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16), 744 PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SYNC_B, SEL_MSIOF3_1), 745 PINMUX_IPSR_GPSR(IP1_31_28, VI4_DATA8), 746 PINMUX_IPSR_GPSR(IP1_31_28, DU_DB0), 747 PINMUX_IPSR_MSEL(IP1_31_28, PWM3_A, SEL_PWM3_0), 748 749 /* IPSR2 */ 750 PINMUX_IPSR_GPSR(IP2_3_0, A1), 751 PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT17), 752 PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_TXD_B, SEL_MSIOF3_1), 753 PINMUX_IPSR_GPSR(IP2_3_0, VI4_DATA9), 754 PINMUX_IPSR_GPSR(IP2_3_0, DU_DB1), 755 PINMUX_IPSR_MSEL(IP2_3_0, PWM4_A, SEL_PWM4_0), 756 757 PINMUX_IPSR_GPSR(IP2_7_4, A2), 758 PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT18), 759 PINMUX_IPSR_MSEL(IP2_7_4, MSIOF3_SCK_B, SEL_MSIOF3_1), 760 PINMUX_IPSR_GPSR(IP2_7_4, VI4_DATA10), 761 PINMUX_IPSR_GPSR(IP2_7_4, DU_DB2), 762 PINMUX_IPSR_MSEL(IP2_7_4, PWM5_A, SEL_PWM5_0), 763 764 PINMUX_IPSR_GPSR(IP2_11_8, A3), 765 PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT19), 766 PINMUX_IPSR_MSEL(IP2_11_8, MSIOF3_RXD_B, SEL_MSIOF3_1), 767 PINMUX_IPSR_GPSR(IP2_11_8, VI4_DATA11), 768 PINMUX_IPSR_GPSR(IP2_11_8, DU_DB3), 769 PINMUX_IPSR_MSEL(IP2_11_8, PWM6_A, SEL_PWM6_0), 770 771 PINMUX_IPSR_GPSR(IP2_15_12, A4), 772 PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT20), 773 PINMUX_IPSR_MSEL(IP2_15_12, MSIOF3_SS1_B, SEL_MSIOF3_1), 774 PINMUX_IPSR_GPSR(IP2_15_12, VI4_DATA12), 775 PINMUX_IPSR_GPSR(IP2_15_12, VI5_DATA12), 776 PINMUX_IPSR_GPSR(IP2_15_12, DU_DB4), 777 778 PINMUX_IPSR_GPSR(IP2_19_16, A5), 779 PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT21), 780 PINMUX_IPSR_MSEL(IP2_19_16, MSIOF3_SS2_B, SEL_MSIOF3_1), 781 PINMUX_IPSR_MSEL(IP2_19_16, SCK4_B, SEL_SCIF4_1), 782 PINMUX_IPSR_GPSR(IP2_19_16, VI4_DATA13), 783 PINMUX_IPSR_GPSR(IP2_19_16, VI5_DATA13), 784 PINMUX_IPSR_GPSR(IP2_19_16, DU_DB5), 785 786 PINMUX_IPSR_GPSR(IP2_23_20, A6), 787 PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT22), 788 PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_SS1_A, SEL_MSIOF2_0), 789 PINMUX_IPSR_MSEL(IP2_23_20, RX4_B, SEL_SCIF4_1), 790 PINMUX_IPSR_GPSR(IP2_23_20, VI4_DATA14), 791 PINMUX_IPSR_GPSR(IP2_23_20, VI5_DATA14), 792 PINMUX_IPSR_GPSR(IP2_23_20, DU_DB6), 793 794 PINMUX_IPSR_GPSR(IP2_27_24, A7), 795 PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT23), 796 PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SS2_A, SEL_MSIOF2_0), 797 PINMUX_IPSR_MSEL(IP2_27_24, TX4_B, SEL_SCIF4_1), 798 PINMUX_IPSR_GPSR(IP2_27_24, VI4_DATA15), 799 PINMUX_IPSR_GPSR(IP2_27_24, VI5_DATA15), 800 PINMUX_IPSR_GPSR(IP2_27_24, DU_DB7), 801 802 PINMUX_IPSR_GPSR(IP2_31_28, A8), 803 PINMUX_IPSR_MSEL(IP2_31_28, RX3_B, SEL_SCIF3_1), 804 PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0), 805 PINMUX_IPSR_MSEL(IP2_31_28, HRX4_B, SEL_HSCIF4_1), 806 PINMUX_IPSR_MSEL(IP2_31_28, SDA6_A, SEL_I2C6_0), 807 PINMUX_IPSR_MSEL(IP2_31_28, AVB_AVTP_MATCH_B, SEL_ETHERAVB_1), 808 PINMUX_IPSR_MSEL(IP2_31_28, PWM1_B, SEL_PWM1_1), 809 810 /* IPSR3 */ 811 PINMUX_IPSR_GPSR(IP3_3_0, A9), 812 PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0), 813 PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1), 814 PINMUX_IPSR_GPSR(IP3_3_0, VI5_VSYNC_N), 815 816 PINMUX_IPSR_GPSR(IP3_7_4, A10), 817 PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0), 818 PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_B, SEL_SCIF4_1), 819 PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N), 820 821 PINMUX_IPSR_GPSR(IP3_11_8, A11), 822 PINMUX_IPSR_MSEL(IP3_11_8, TX3_B, SEL_SCIF3_1), 823 PINMUX_IPSR_MSEL(IP3_11_8, MSIOF2_TXD_A, SEL_MSIOF2_0), 824 PINMUX_IPSR_MSEL(IP3_11_8, HTX4_B, SEL_HSCIF4_1), 825 PINMUX_IPSR_GPSR(IP3_11_8, HSCK4), 826 PINMUX_IPSR_GPSR(IP3_11_8, VI5_FIELD), 827 PINMUX_IPSR_MSEL(IP3_11_8, SCL6_A, SEL_I2C6_0), 828 PINMUX_IPSR_MSEL(IP3_11_8, AVB_AVTP_CAPTURE_B, SEL_ETHERAVB_1), 829 PINMUX_IPSR_MSEL(IP3_11_8, PWM2_B, SEL_PWM2_1), 830 831 PINMUX_IPSR_GPSR(IP3_15_12, A12), 832 PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT12), 833 PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SCK_C, SEL_MSIOF3_2), 834 PINMUX_IPSR_MSEL(IP3_15_12, HRX4_A, SEL_HSCIF4_0), 835 PINMUX_IPSR_GPSR(IP3_15_12, VI5_DATA8), 836 PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4), 837 838 PINMUX_IPSR_GPSR(IP3_19_16, A13), 839 PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT13), 840 PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SYNC_C, SEL_MSIOF3_2), 841 PINMUX_IPSR_MSEL(IP3_19_16, HTX4_A, SEL_HSCIF4_0), 842 PINMUX_IPSR_GPSR(IP3_19_16, VI5_DATA9), 843 PINMUX_IPSR_GPSR(IP3_19_16, DU_DG5), 844 845 PINMUX_IPSR_GPSR(IP3_23_20, A14), 846 PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT14), 847 PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_C, SEL_MSIOF3_2), 848 PINMUX_IPSR_GPSR(IP3_23_20, HCTS4_N), 849 PINMUX_IPSR_GPSR(IP3_23_20, VI5_DATA10), 850 PINMUX_IPSR_GPSR(IP3_23_20, DU_DG6), 851 852 PINMUX_IPSR_GPSR(IP3_27_24, A15), 853 PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT15), 854 PINMUX_IPSR_MSEL(IP3_27_24, MSIOF3_TXD_C, SEL_MSIOF3_2), 855 PINMUX_IPSR_GPSR(IP3_27_24, HRTS4_N), 856 PINMUX_IPSR_GPSR(IP3_27_24, VI5_DATA11), 857 PINMUX_IPSR_GPSR(IP3_27_24, DU_DG7), 858 859 PINMUX_IPSR_GPSR(IP3_31_28, A16), 860 PINMUX_IPSR_GPSR(IP3_31_28, LCDOUT8), 861 PINMUX_IPSR_GPSR(IP3_31_28, VI4_FIELD), 862 PINMUX_IPSR_GPSR(IP3_31_28, DU_DG0), 863 864 /* IPSR4 */ 865 PINMUX_IPSR_GPSR(IP4_3_0, A17), 866 PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT9), 867 PINMUX_IPSR_GPSR(IP4_3_0, VI4_VSYNC_N), 868 PINMUX_IPSR_GPSR(IP4_3_0, DU_DG1), 869 870 PINMUX_IPSR_GPSR(IP4_7_4, A18), 871 PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT10), 872 PINMUX_IPSR_GPSR(IP4_7_4, VI4_HSYNC_N), 873 PINMUX_IPSR_GPSR(IP4_7_4, DU_DG2), 874 875 PINMUX_IPSR_GPSR(IP4_11_8, A19), 876 PINMUX_IPSR_GPSR(IP4_11_8, LCDOUT11), 877 PINMUX_IPSR_GPSR(IP4_11_8, VI4_CLKENB), 878 PINMUX_IPSR_GPSR(IP4_11_8, DU_DG3), 879 880 PINMUX_IPSR_GPSR(IP4_15_12, CS0_N), 881 PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB), 882 883 PINMUX_IPSR_GPSR(IP4_19_16, CS1_N), 884 PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK), 885 PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1), 886 887 PINMUX_IPSR_GPSR(IP4_23_20, BS_N), 888 PINMUX_IPSR_GPSR(IP4_23_20, QSTVA_QVS), 889 PINMUX_IPSR_MSEL(IP4_23_20, MSIOF3_SCK_D, SEL_MSIOF3_3), 890 PINMUX_IPSR_GPSR(IP4_23_20, SCK3), 891 PINMUX_IPSR_GPSR(IP4_23_20, HSCK3), 892 PINMUX_IPSR_GPSR(IP4_23_20, CAN1_TX), 893 PINMUX_IPSR_GPSR(IP4_23_20, CANFD1_TX), 894 PINMUX_IPSR_MSEL(IP4_23_20, IETX_A, SEL_IEBUS_0), 895 896 PINMUX_IPSR_GPSR(IP4_27_24, RD_N), 897 PINMUX_IPSR_MSEL(IP4_27_24, MSIOF3_SYNC_D, SEL_MSIOF3_3), 898 PINMUX_IPSR_MSEL(IP4_27_24, RX3_A, SEL_SCIF3_0), 899 PINMUX_IPSR_MSEL(IP4_27_24, HRX3_A, SEL_HSCIF3_0), 900 PINMUX_IPSR_MSEL(IP4_27_24, CAN0_TX_A, SEL_RCAN0_0), 901 PINMUX_IPSR_MSEL(IP4_27_24, CANFD0_TX_A, SEL_CANFD0_0), 902 903 PINMUX_IPSR_GPSR(IP4_31_28, RD_WR_N), 904 PINMUX_IPSR_MSEL(IP4_31_28, MSIOF3_RXD_D, SEL_MSIOF3_3), 905 PINMUX_IPSR_MSEL(IP4_31_28, TX3_A, SEL_SCIF3_0), 906 PINMUX_IPSR_MSEL(IP4_31_28, HTX3_A, SEL_HSCIF3_0), 907 PINMUX_IPSR_MSEL(IP4_31_28, CAN0_RX_A, SEL_RCAN0_0), 908 PINMUX_IPSR_MSEL(IP4_31_28, CANFD0_RX_A, SEL_CANFD0_0), 909 910 /* IPSR5 */ 911 PINMUX_IPSR_GPSR(IP5_3_0, WE0_N), 912 PINMUX_IPSR_MSEL(IP5_3_0, MSIOF3_TXD_D, SEL_MSIOF3_3), 913 PINMUX_IPSR_GPSR(IP5_3_0, CTS3_N), 914 PINMUX_IPSR_GPSR(IP5_3_0, HCTS3_N), 915 PINMUX_IPSR_MSEL(IP5_3_0, SCL6_B, SEL_I2C6_1), 916 PINMUX_IPSR_GPSR(IP5_3_0, CAN_CLK), 917 PINMUX_IPSR_MSEL(IP5_3_0, IECLK_A, SEL_IEBUS_0), 918 919 PINMUX_IPSR_GPSR(IP5_7_4, WE1_N), 920 PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3), 921 PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N), 922 PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N), 923 PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1), 924 PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX), 925 PINMUX_IPSR_GPSR(IP5_7_4, CANFD1_RX), 926 PINMUX_IPSR_MSEL(IP5_7_4, IERX_A, SEL_IEBUS_0), 927 928 PINMUX_IPSR_MSEL(IP5_11_8, EX_WAIT0_A, SEL_LBSC_0), 929 PINMUX_IPSR_GPSR(IP5_11_8, QCLK), 930 PINMUX_IPSR_GPSR(IP5_11_8, VI4_CLK), 931 PINMUX_IPSR_GPSR(IP5_11_8, DU_DOTCLKOUT0), 932 933 PINMUX_IPSR_GPSR(IP5_15_12, D0), 934 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF2_SS1_B, SEL_MSIOF2_1), 935 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF3_SCK_A, SEL_MSIOF3_0), 936 PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA16), 937 PINMUX_IPSR_GPSR(IP5_15_12, VI5_DATA0), 938 939 PINMUX_IPSR_GPSR(IP5_19_16, D1), 940 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF2_SS2_B, SEL_MSIOF2_1), 941 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF3_SYNC_A, SEL_MSIOF3_0), 942 PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA17), 943 PINMUX_IPSR_GPSR(IP5_19_16, VI5_DATA1), 944 945 PINMUX_IPSR_GPSR(IP5_23_20, D2), 946 PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_RXD_A, SEL_MSIOF3_0), 947 PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA18), 948 PINMUX_IPSR_GPSR(IP5_23_20, VI5_DATA2), 949 950 PINMUX_IPSR_GPSR(IP5_27_24, D3), 951 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0), 952 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19), 953 PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3), 954 955 PINMUX_IPSR_GPSR(IP5_31_28, D4), 956 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF2_SCK_B, SEL_MSIOF2_1), 957 PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA20), 958 PINMUX_IPSR_GPSR(IP5_31_28, VI5_DATA4), 959 960 /* IPSR6 */ 961 PINMUX_IPSR_GPSR(IP6_3_0, D5), 962 PINMUX_IPSR_MSEL(IP6_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1), 963 PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA21), 964 PINMUX_IPSR_GPSR(IP6_3_0, VI5_DATA5), 965 966 PINMUX_IPSR_GPSR(IP6_7_4, D6), 967 PINMUX_IPSR_MSEL(IP6_7_4, MSIOF2_RXD_B, SEL_MSIOF2_1), 968 PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA22), 969 PINMUX_IPSR_GPSR(IP6_7_4, VI5_DATA6), 970 971 PINMUX_IPSR_GPSR(IP6_11_8, D7), 972 PINMUX_IPSR_MSEL(IP6_11_8, MSIOF2_TXD_B, SEL_MSIOF2_1), 973 PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA23), 974 PINMUX_IPSR_GPSR(IP6_11_8, VI5_DATA7), 975 976 PINMUX_IPSR_GPSR(IP6_15_12, D8), 977 PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT0), 978 PINMUX_IPSR_MSEL(IP6_15_12, MSIOF2_SCK_D, SEL_MSIOF2_3), 979 PINMUX_IPSR_MSEL(IP6_15_12, SCK4_C, SEL_SCIF4_2), 980 PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA0_A, SEL_VIN4_0), 981 PINMUX_IPSR_GPSR(IP6_15_12, DU_DR0), 982 983 PINMUX_IPSR_GPSR(IP6_19_16, D9), 984 PINMUX_IPSR_GPSR(IP6_19_16, LCDOUT1), 985 PINMUX_IPSR_MSEL(IP6_19_16, MSIOF2_SYNC_D, SEL_MSIOF2_3), 986 PINMUX_IPSR_MSEL(IP6_19_16, VI4_DATA1_A, SEL_VIN4_0), 987 PINMUX_IPSR_GPSR(IP6_19_16, DU_DR1), 988 989 PINMUX_IPSR_GPSR(IP6_23_20, D10), 990 PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT2), 991 PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_RXD_D, SEL_MSIOF2_3), 992 PINMUX_IPSR_MSEL(IP6_23_20, HRX3_B, SEL_HSCIF3_1), 993 PINMUX_IPSR_MSEL(IP6_23_20, VI4_DATA2_A, SEL_VIN4_0), 994 PINMUX_IPSR_MSEL(IP6_23_20, CTS4_N_C, SEL_SCIF4_2), 995 PINMUX_IPSR_GPSR(IP6_23_20, DU_DR2), 996 997 PINMUX_IPSR_GPSR(IP6_27_24, D11), 998 PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT3), 999 PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3), 1000 PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1), 1001 PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0), 1002 PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_C, SEL_SCIF4_2), 1003 PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3), 1004 1005 PINMUX_IPSR_GPSR(IP6_31_28, D12), 1006 PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT4), 1007 PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3), 1008 PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2), 1009 PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0), 1010 PINMUX_IPSR_GPSR(IP6_31_28, DU_DR4), 1011 1012 /* IPSR7 */ 1013 PINMUX_IPSR_GPSR(IP7_3_0, D13), 1014 PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT5), 1015 PINMUX_IPSR_MSEL(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3), 1016 PINMUX_IPSR_MSEL(IP7_3_0, TX4_C, SEL_SCIF4_2), 1017 PINMUX_IPSR_MSEL(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0), 1018 PINMUX_IPSR_GPSR(IP7_3_0, DU_DR5), 1019 1020 PINMUX_IPSR_GPSR(IP7_7_4, D14), 1021 PINMUX_IPSR_GPSR(IP7_7_4, LCDOUT6), 1022 PINMUX_IPSR_MSEL(IP7_7_4, MSIOF3_SS1_A, SEL_MSIOF3_0), 1023 PINMUX_IPSR_MSEL(IP7_7_4, HRX3_C, SEL_HSCIF3_2), 1024 PINMUX_IPSR_MSEL(IP7_7_4, VI4_DATA6_A, SEL_VIN4_0), 1025 PINMUX_IPSR_GPSR(IP7_7_4, DU_DR6), 1026 PINMUX_IPSR_MSEL(IP7_7_4, SCL6_C, SEL_I2C6_2), 1027 1028 PINMUX_IPSR_GPSR(IP7_11_8, D15), 1029 PINMUX_IPSR_GPSR(IP7_11_8, LCDOUT7), 1030 PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SS2_A, SEL_MSIOF3_0), 1031 PINMUX_IPSR_MSEL(IP7_11_8, HTX3_C, SEL_HSCIF3_2), 1032 PINMUX_IPSR_MSEL(IP7_11_8, VI4_DATA7_A, SEL_VIN4_0), 1033 PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7), 1034 PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2), 1035 1036 PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK), 1037 PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4), 1038 PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1), 1039 1040 PINMUX_IPSR_GPSR(IP7_23_20, SD0_CMD), 1041 PINMUX_IPSR_MSEL(IP7_23_20, MSIOF1_SYNC_E, SEL_MSIOF1_4), 1042 PINMUX_IPSR_MSEL(IP7_23_20, STP_IVCXO27_0_B, SEL_SSP1_0_1), 1043 1044 PINMUX_IPSR_GPSR(IP7_27_24, SD0_DAT0), 1045 PINMUX_IPSR_MSEL(IP7_27_24, MSIOF1_RXD_E, SEL_MSIOF1_4), 1046 PINMUX_IPSR_MSEL(IP7_27_24, TS_SCK0_B, SEL_TSIF0_1), 1047 PINMUX_IPSR_MSEL(IP7_27_24, STP_ISCLK_0_B, SEL_SSP1_0_1), 1048 1049 PINMUX_IPSR_GPSR(IP7_31_28, SD0_DAT1), 1050 PINMUX_IPSR_MSEL(IP7_31_28, MSIOF1_TXD_E, SEL_MSIOF1_4), 1051 PINMUX_IPSR_MSEL(IP7_31_28, TS_SPSYNC0_B, SEL_TSIF0_1), 1052 PINMUX_IPSR_MSEL(IP7_31_28, STP_ISSYNC_0_B, SEL_SSP1_0_1), 1053 1054 /* IPSR8 */ 1055 PINMUX_IPSR_GPSR(IP8_3_0, SD0_DAT2), 1056 PINMUX_IPSR_MSEL(IP8_3_0, MSIOF1_SS1_E, SEL_MSIOF1_4), 1057 PINMUX_IPSR_MSEL(IP8_3_0, TS_SDAT0_B, SEL_TSIF0_1), 1058 PINMUX_IPSR_MSEL(IP8_3_0, STP_ISD_0_B, SEL_SSP1_0_1), 1059 1060 PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT3), 1061 PINMUX_IPSR_MSEL(IP8_7_4, MSIOF1_SS2_E, SEL_MSIOF1_4), 1062 PINMUX_IPSR_MSEL(IP8_7_4, TS_SDEN0_B, SEL_TSIF0_1), 1063 PINMUX_IPSR_MSEL(IP8_7_4, STP_ISEN_0_B, SEL_SSP1_0_1), 1064 1065 PINMUX_IPSR_GPSR(IP8_11_8, SD1_CLK), 1066 PINMUX_IPSR_MSEL(IP8_11_8, MSIOF1_SCK_G, SEL_MSIOF1_6), 1067 PINMUX_IPSR_MSEL(IP8_11_8, SIM0_CLK_A, SEL_SIMCARD_0), 1068 1069 PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD), 1070 PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6), 1071 PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDF_1), 1072 PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0), 1073 PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1), 1074 1075 PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0), 1076 PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4), 1077 PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6), 1078 PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDF_1), 1079 PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1), 1080 PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1), 1081 1082 PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1), 1083 PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5), 1084 PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6), 1085 PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDF_1), 1086 PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1), 1087 PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1), 1088 1089 PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2), 1090 PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6), 1091 PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6), 1092 PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDF_1), 1093 PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1), 1094 PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1), 1095 1096 PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3), 1097 PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7), 1098 PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6), 1099 PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDF_1), 1100 PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1), 1101 PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1), 1102 1103 /* IPSR9 */ 1104 PINMUX_IPSR_GPSR(IP9_3_0, SD2_CLK), 1105 PINMUX_IPSR_GPSR(IP9_3_0, NFDATA8), 1106 1107 PINMUX_IPSR_GPSR(IP9_7_4, SD2_CMD), 1108 PINMUX_IPSR_GPSR(IP9_7_4, NFDATA9), 1109 1110 PINMUX_IPSR_GPSR(IP9_11_8, SD2_DAT0), 1111 PINMUX_IPSR_GPSR(IP9_11_8, NFDATA10), 1112 1113 PINMUX_IPSR_GPSR(IP9_15_12, SD2_DAT1), 1114 PINMUX_IPSR_GPSR(IP9_15_12, NFDATA11), 1115 1116 PINMUX_IPSR_GPSR(IP9_19_16, SD2_DAT2), 1117 PINMUX_IPSR_GPSR(IP9_19_16, NFDATA12), 1118 1119 PINMUX_IPSR_GPSR(IP9_23_20, SD2_DAT3), 1120 PINMUX_IPSR_GPSR(IP9_23_20, NFDATA13), 1121 1122 PINMUX_IPSR_GPSR(IP9_27_24, SD2_DS), 1123 PINMUX_IPSR_GPSR(IP9_27_24, NFALE), 1124 PINMUX_IPSR_GPSR(IP9_27_24, SATA_DEVSLP_B), 1125 1126 PINMUX_IPSR_GPSR(IP9_31_28, SD3_CLK), 1127 PINMUX_IPSR_GPSR(IP9_31_28, NFWE_N), 1128 1129 /* IPSR10 */ 1130 PINMUX_IPSR_GPSR(IP10_3_0, SD3_CMD), 1131 PINMUX_IPSR_GPSR(IP10_3_0, NFRE_N), 1132 1133 PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT0), 1134 PINMUX_IPSR_GPSR(IP10_7_4, NFDATA0), 1135 1136 PINMUX_IPSR_GPSR(IP10_11_8, SD3_DAT1), 1137 PINMUX_IPSR_GPSR(IP10_11_8, NFDATA1), 1138 1139 PINMUX_IPSR_GPSR(IP10_15_12, SD3_DAT2), 1140 PINMUX_IPSR_GPSR(IP10_15_12, NFDATA2), 1141 1142 PINMUX_IPSR_GPSR(IP10_19_16, SD3_DAT3), 1143 PINMUX_IPSR_GPSR(IP10_19_16, NFDATA3), 1144 1145 PINMUX_IPSR_GPSR(IP10_23_20, SD3_DAT4), 1146 PINMUX_IPSR_MSEL(IP10_23_20, SD2_CD_A, SEL_SDHI2_0), 1147 PINMUX_IPSR_GPSR(IP10_23_20, NFDATA4), 1148 1149 PINMUX_IPSR_GPSR(IP10_27_24, SD3_DAT5), 1150 PINMUX_IPSR_MSEL(IP10_27_24, SD2_WP_A, SEL_SDHI2_0), 1151 PINMUX_IPSR_GPSR(IP10_27_24, NFDATA5), 1152 1153 PINMUX_IPSR_GPSR(IP10_31_28, SD3_DAT6), 1154 PINMUX_IPSR_GPSR(IP10_31_28, SD3_CD), 1155 PINMUX_IPSR_GPSR(IP10_31_28, NFDATA6), 1156 1157 /* IPSR11 */ 1158 PINMUX_IPSR_GPSR(IP11_3_0, SD3_DAT7), 1159 PINMUX_IPSR_GPSR(IP11_3_0, SD3_WP), 1160 PINMUX_IPSR_GPSR(IP11_3_0, NFDATA7), 1161 1162 PINMUX_IPSR_GPSR(IP11_7_4, SD3_DS), 1163 PINMUX_IPSR_GPSR(IP11_7_4, NFCLE), 1164 1165 PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD), 1166 PINMUX_IPSR_MSEL(IP11_11_8, NFDATA14_A, SEL_NDF_0), 1167 PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1), 1168 PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0), 1169 1170 PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP), 1171 PINMUX_IPSR_MSEL(IP11_15_12, NFDATA15_A, SEL_NDF_0), 1172 PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1), 1173 1174 PINMUX_IPSR_MSEL(IP11_19_16, SD1_CD, I2C_SEL_0_0), 1175 PINMUX_IPSR_PHYS_MSEL(IP11_19_16, NFRB_N_A, I2C_SEL_0_0, SEL_NDF_0), 1176 PINMUX_IPSR_PHYS_MSEL(IP11_19_16, SIM0_CLK_B, I2C_SEL_0_0, SEL_SIMCARD_1), 1177 PINMUX_IPSR_PHYS(IP11_19_16, SCL0, I2C_SEL_0_1), 1178 1179 PINMUX_IPSR_MSEL(IP11_23_20, SD1_WP, I2C_SEL_0_0), 1180 PINMUX_IPSR_PHYS_MSEL(IP11_23_20, NFCE_N_A, I2C_SEL_0_0, SEL_NDF_0), 1181 PINMUX_IPSR_PHYS_MSEL(IP11_23_20, SIM0_D_B, I2C_SEL_0_0, SEL_SIMCARD_1), 1182 PINMUX_IPSR_PHYS(IP11_23_20, SDA0, I2C_SEL_0_1), 1183 1184 PINMUX_IPSR_GPSR(IP11_27_24, SCK0), 1185 PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1), 1186 PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1), 1187 PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADGC_1), 1188 PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0), 1189 PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1), 1190 PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2), 1191 PINMUX_IPSR_MSEL(IP11_27_24, RIF0_CLK_B, SEL_DRIF0_1), 1192 PINMUX_IPSR_GPSR(IP11_27_24, ADICHS2), 1193 PINMUX_IPSR_MSEL(IP11_27_24, SCK5_B, SEL_SCIF5_1), 1194 1195 PINMUX_IPSR_GPSR(IP11_31_28, RX0), 1196 PINMUX_IPSR_MSEL(IP11_31_28, HRX1_B, SEL_HSCIF1_1), 1197 PINMUX_IPSR_MSEL(IP11_31_28, TS_SCK0_C, SEL_TSIF0_2), 1198 PINMUX_IPSR_MSEL(IP11_31_28, STP_ISCLK_0_C, SEL_SSP1_0_2), 1199 PINMUX_IPSR_MSEL(IP11_31_28, RIF0_D0_B, SEL_DRIF0_1), 1200 1201 /* IPSR12 */ 1202 PINMUX_IPSR_GPSR(IP12_3_0, TX0), 1203 PINMUX_IPSR_MSEL(IP12_3_0, HTX1_B, SEL_HSCIF1_1), 1204 PINMUX_IPSR_MSEL(IP12_3_0, TS_SPSYNC0_C, SEL_TSIF0_2), 1205 PINMUX_IPSR_MSEL(IP12_3_0, STP_ISSYNC_0_C, SEL_SSP1_0_2), 1206 PINMUX_IPSR_MSEL(IP12_3_0, RIF0_D1_B, SEL_DRIF0_1), 1207 1208 PINMUX_IPSR_GPSR(IP12_7_4, CTS0_N), 1209 PINMUX_IPSR_MSEL(IP12_7_4, HCTS1_N_B, SEL_HSCIF1_1), 1210 PINMUX_IPSR_MSEL(IP12_7_4, MSIOF1_SYNC_B, SEL_MSIOF1_1), 1211 PINMUX_IPSR_MSEL(IP12_7_4, TS_SPSYNC1_C, SEL_TSIF1_2), 1212 PINMUX_IPSR_MSEL(IP12_7_4, STP_ISSYNC_1_C, SEL_SSP1_1_2), 1213 PINMUX_IPSR_MSEL(IP12_7_4, RIF1_SYNC_B, SEL_DRIF1_1), 1214 PINMUX_IPSR_GPSR(IP12_7_4, AUDIO_CLKOUT_C), 1215 PINMUX_IPSR_GPSR(IP12_7_4, ADICS_SAMP), 1216 1217 PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N), 1218 PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1), 1219 PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1), 1220 PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADGA_1), 1221 PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0), 1222 PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2), 1223 PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1), 1224 PINMUX_IPSR_GPSR(IP12_11_8, ADICHS1), 1225 1226 PINMUX_IPSR_MSEL(IP12_15_12, RX1_A, SEL_SCIF1_0), 1227 PINMUX_IPSR_MSEL(IP12_15_12, HRX1_A, SEL_HSCIF1_0), 1228 PINMUX_IPSR_MSEL(IP12_15_12, TS_SDAT0_C, SEL_TSIF0_2), 1229 PINMUX_IPSR_MSEL(IP12_15_12, STP_ISD_0_C, SEL_SSP1_0_2), 1230 PINMUX_IPSR_MSEL(IP12_15_12, RIF1_CLK_C, SEL_DRIF1_2), 1231 1232 PINMUX_IPSR_MSEL(IP12_19_16, TX1_A, SEL_SCIF1_0), 1233 PINMUX_IPSR_MSEL(IP12_19_16, HTX1_A, SEL_HSCIF1_0), 1234 PINMUX_IPSR_MSEL(IP12_19_16, TS_SDEN0_C, SEL_TSIF0_2), 1235 PINMUX_IPSR_MSEL(IP12_19_16, STP_ISEN_0_C, SEL_SSP1_0_2), 1236 PINMUX_IPSR_MSEL(IP12_19_16, RIF1_D0_C, SEL_DRIF1_2), 1237 1238 PINMUX_IPSR_GPSR(IP12_23_20, CTS1_N), 1239 PINMUX_IPSR_MSEL(IP12_23_20, HCTS1_N_A, SEL_HSCIF1_0), 1240 PINMUX_IPSR_MSEL(IP12_23_20, MSIOF1_RXD_B, SEL_MSIOF1_1), 1241 PINMUX_IPSR_MSEL(IP12_23_20, TS_SDEN1_C, SEL_TSIF1_2), 1242 PINMUX_IPSR_MSEL(IP12_23_20, STP_ISEN_1_C, SEL_SSP1_1_2), 1243 PINMUX_IPSR_MSEL(IP12_23_20, RIF1_D0_B, SEL_DRIF1_1), 1244 PINMUX_IPSR_GPSR(IP12_23_20, ADIDATA), 1245 1246 PINMUX_IPSR_GPSR(IP12_27_24, RTS1_N), 1247 PINMUX_IPSR_MSEL(IP12_27_24, HRTS1_N_A, SEL_HSCIF1_0), 1248 PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1), 1249 PINMUX_IPSR_MSEL(IP12_27_24, TS_SDAT1_C, SEL_TSIF1_2), 1250 PINMUX_IPSR_MSEL(IP12_27_24, STP_ISD_1_C, SEL_SSP1_1_2), 1251 PINMUX_IPSR_MSEL(IP12_27_24, RIF1_D1_B, SEL_DRIF1_1), 1252 PINMUX_IPSR_GPSR(IP12_27_24, ADICHS0), 1253 1254 PINMUX_IPSR_GPSR(IP12_31_28, SCK2), 1255 PINMUX_IPSR_MSEL(IP12_31_28, SCIF_CLK_B, SEL_SCIF_1), 1256 PINMUX_IPSR_MSEL(IP12_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1), 1257 PINMUX_IPSR_MSEL(IP12_31_28, TS_SCK1_C, SEL_TSIF1_2), 1258 PINMUX_IPSR_MSEL(IP12_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2), 1259 PINMUX_IPSR_MSEL(IP12_31_28, RIF1_CLK_B, SEL_DRIF1_1), 1260 PINMUX_IPSR_GPSR(IP12_31_28, ADICLK), 1261 1262 /* IPSR13 */ 1263 PINMUX_IPSR_MSEL(IP13_3_0, TX2_A, SEL_SCIF2_0), 1264 PINMUX_IPSR_MSEL(IP13_3_0, SD2_CD_B, SEL_SDHI2_1), 1265 PINMUX_IPSR_MSEL(IP13_3_0, SCL1_A, SEL_I2C1_0), 1266 PINMUX_IPSR_MSEL(IP13_3_0, FMCLK_A, SEL_FM_0), 1267 PINMUX_IPSR_MSEL(IP13_3_0, RIF1_D1_C, SEL_DRIF1_2), 1268 PINMUX_IPSR_GPSR(IP13_3_0, FSO_CFE_0_N), 1269 1270 PINMUX_IPSR_MSEL(IP13_7_4, RX2_A, SEL_SCIF2_0), 1271 PINMUX_IPSR_MSEL(IP13_7_4, SD2_WP_B, SEL_SDHI2_1), 1272 PINMUX_IPSR_MSEL(IP13_7_4, SDA1_A, SEL_I2C1_0), 1273 PINMUX_IPSR_MSEL(IP13_7_4, FMIN_A, SEL_FM_0), 1274 PINMUX_IPSR_MSEL(IP13_7_4, RIF1_SYNC_C, SEL_DRIF1_2), 1275 PINMUX_IPSR_GPSR(IP13_7_4, FSO_CFE_1_N), 1276 1277 PINMUX_IPSR_GPSR(IP13_11_8, HSCK0), 1278 PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3), 1279 PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADGB_0), 1280 PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI1_1), 1281 PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3), 1282 PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3), 1283 PINMUX_IPSR_MSEL(IP13_11_8, RIF0_CLK_C, SEL_DRIF0_2), 1284 PINMUX_IPSR_MSEL(IP13_11_8, RX5_B, SEL_SCIF5_1), 1285 1286 PINMUX_IPSR_GPSR(IP13_15_12, HRX0), 1287 PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3), 1288 PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA2_B, SEL_SSI2_1), 1289 PINMUX_IPSR_MSEL(IP13_15_12, TS_SDEN0_D, SEL_TSIF0_3), 1290 PINMUX_IPSR_MSEL(IP13_15_12, STP_ISEN_0_D, SEL_SSP1_0_3), 1291 PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_C, SEL_DRIF0_2), 1292 1293 PINMUX_IPSR_GPSR(IP13_19_16, HTX0), 1294 PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3), 1295 PINMUX_IPSR_MSEL(IP13_19_16, SSI_SDATA9_B, SEL_SSI9_1), 1296 PINMUX_IPSR_MSEL(IP13_19_16, TS_SDAT0_D, SEL_TSIF0_3), 1297 PINMUX_IPSR_MSEL(IP13_19_16, STP_ISD_0_D, SEL_SSP1_0_3), 1298 PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_C, SEL_DRIF0_2), 1299 1300 PINMUX_IPSR_GPSR(IP13_23_20, HCTS0_N), 1301 PINMUX_IPSR_MSEL(IP13_23_20, RX2_B, SEL_SCIF2_1), 1302 PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3), 1303 PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK9_A, SEL_SSI9_0), 1304 PINMUX_IPSR_MSEL(IP13_23_20, TS_SPSYNC0_D, SEL_TSIF0_3), 1305 PINMUX_IPSR_MSEL(IP13_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3), 1306 PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_C, SEL_DRIF0_2), 1307 PINMUX_IPSR_GPSR(IP13_23_20, AUDIO_CLKOUT1_A), 1308 1309 PINMUX_IPSR_GPSR(IP13_27_24, HRTS0_N), 1310 PINMUX_IPSR_MSEL(IP13_27_24, TX2_B, SEL_SCIF2_1), 1311 PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3), 1312 PINMUX_IPSR_MSEL(IP13_27_24, SSI_WS9_A, SEL_SSI9_0), 1313 PINMUX_IPSR_MSEL(IP13_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3), 1314 PINMUX_IPSR_MSEL(IP13_27_24, BPFCLK_A, SEL_FM_0), 1315 PINMUX_IPSR_GPSR(IP13_27_24, AUDIO_CLKOUT2_A), 1316 1317 PINMUX_IPSR_GPSR(IP13_31_28, MSIOF0_SYNC), 1318 PINMUX_IPSR_GPSR(IP13_31_28, AUDIO_CLKOUT_A), 1319 PINMUX_IPSR_MSEL(IP13_31_28, TX5_B, SEL_SCIF5_1), 1320 PINMUX_IPSR_MSEL(IP13_31_28, BPFCLK_D, SEL_FM_3), 1321 1322 /* IPSR14 */ 1323 PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1), 1324 PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0), 1325 PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDF_0), 1326 PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADGA_2), 1327 PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0), 1328 PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2), 1329 PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A), 1330 PINMUX_IPSR_MSEL(IP14_3_0, TCLK1_B, SEL_TIMER_TMU_1), 1331 1332 PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2), 1333 PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0), 1334 PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3), 1335 PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADGC_0), 1336 PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI2_0), 1337 PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3), 1338 PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D), 1339 PINMUX_IPSR_MSEL(IP14_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1), 1340 1341 PINMUX_IPSR_GPSR(IP14_11_8, MLB_CLK), 1342 PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SCK_F, SEL_MSIOF1_5), 1343 PINMUX_IPSR_MSEL(IP14_11_8, SCL1_B, SEL_I2C1_1), 1344 1345 PINMUX_IPSR_GPSR(IP14_15_12, MLB_SIG), 1346 PINMUX_IPSR_MSEL(IP14_15_12, RX1_B, SEL_SCIF1_1), 1347 PINMUX_IPSR_MSEL(IP14_15_12, MSIOF1_SYNC_F, SEL_MSIOF1_5), 1348 PINMUX_IPSR_MSEL(IP14_15_12, SDA1_B, SEL_I2C1_1), 1349 1350 PINMUX_IPSR_GPSR(IP14_19_16, MLB_DAT), 1351 PINMUX_IPSR_MSEL(IP14_19_16, TX1_B, SEL_SCIF1_1), 1352 PINMUX_IPSR_MSEL(IP14_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5), 1353 1354 PINMUX_IPSR_GPSR(IP14_23_20, SSI_SCK01239), 1355 PINMUX_IPSR_MSEL(IP14_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5), 1356 1357 PINMUX_IPSR_GPSR(IP14_27_24, SSI_WS01239), 1358 PINMUX_IPSR_MSEL(IP14_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5), 1359 1360 PINMUX_IPSR_GPSR(IP14_31_28, SSI_SDATA0), 1361 PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5), 1362 1363 /* IPSR15 */ 1364 PINMUX_IPSR_MSEL(IP15_3_0, SSI_SDATA1_A, SEL_SSI1_0), 1365 1366 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SDATA2_A, SEL_SSI2_0), 1367 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SCK1_B, SEL_SSI1_1), 1368 1369 PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK349), 1370 PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0), 1371 PINMUX_IPSR_MSEL(IP15_11_8, STP_OPWM_0_A, SEL_SSP1_0_0), 1372 1373 PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS349), 1374 PINMUX_IPSR_MSEL(IP15_15_12, HCTS2_N_A, SEL_HSCIF2_0), 1375 PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0), 1376 PINMUX_IPSR_MSEL(IP15_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0), 1377 1378 PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA3), 1379 PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0), 1380 PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_TXD_A, SEL_MSIOF1_0), 1381 PINMUX_IPSR_MSEL(IP15_19_16, TS_SCK0_A, SEL_TSIF0_0), 1382 PINMUX_IPSR_MSEL(IP15_19_16, STP_ISCLK_0_A, SEL_SSP1_0_0), 1383 PINMUX_IPSR_MSEL(IP15_19_16, RIF0_D1_A, SEL_DRIF0_0), 1384 PINMUX_IPSR_MSEL(IP15_19_16, RIF2_D0_A, SEL_DRIF2_0), 1385 1386 PINMUX_IPSR_GPSR(IP15_23_20, SSI_SCK4), 1387 PINMUX_IPSR_MSEL(IP15_23_20, HRX2_A, SEL_HSCIF2_0), 1388 PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_SCK_A, SEL_MSIOF1_0), 1389 PINMUX_IPSR_MSEL(IP15_23_20, TS_SDAT0_A, SEL_TSIF0_0), 1390 PINMUX_IPSR_MSEL(IP15_23_20, STP_ISD_0_A, SEL_SSP1_0_0), 1391 PINMUX_IPSR_MSEL(IP15_23_20, RIF0_CLK_A, SEL_DRIF0_0), 1392 PINMUX_IPSR_MSEL(IP15_23_20, RIF2_CLK_A, SEL_DRIF2_0), 1393 1394 PINMUX_IPSR_GPSR(IP15_27_24, SSI_WS4), 1395 PINMUX_IPSR_MSEL(IP15_27_24, HTX2_A, SEL_HSCIF2_0), 1396 PINMUX_IPSR_MSEL(IP15_27_24, MSIOF1_SYNC_A, SEL_MSIOF1_0), 1397 PINMUX_IPSR_MSEL(IP15_27_24, TS_SDEN0_A, SEL_TSIF0_0), 1398 PINMUX_IPSR_MSEL(IP15_27_24, STP_ISEN_0_A, SEL_SSP1_0_0), 1399 PINMUX_IPSR_MSEL(IP15_27_24, RIF0_SYNC_A, SEL_DRIF0_0), 1400 PINMUX_IPSR_MSEL(IP15_27_24, RIF2_SYNC_A, SEL_DRIF2_0), 1401 1402 PINMUX_IPSR_GPSR(IP15_31_28, SSI_SDATA4), 1403 PINMUX_IPSR_MSEL(IP15_31_28, HSCK2_A, SEL_HSCIF2_0), 1404 PINMUX_IPSR_MSEL(IP15_31_28, MSIOF1_RXD_A, SEL_MSIOF1_0), 1405 PINMUX_IPSR_MSEL(IP15_31_28, TS_SPSYNC0_A, SEL_TSIF0_0), 1406 PINMUX_IPSR_MSEL(IP15_31_28, STP_ISSYNC_0_A, SEL_SSP1_0_0), 1407 PINMUX_IPSR_MSEL(IP15_31_28, RIF0_D0_A, SEL_DRIF0_0), 1408 PINMUX_IPSR_MSEL(IP15_31_28, RIF2_D1_A, SEL_DRIF2_0), 1409 1410 /* IPSR16 */ 1411 PINMUX_IPSR_GPSR(IP16_3_0, SSI_SCK6), 1412 PINMUX_IPSR_MSEL(IP16_3_0, SIM0_RST_D, SEL_SIMCARD_3), 1413 1414 PINMUX_IPSR_GPSR(IP16_7_4, SSI_WS6), 1415 PINMUX_IPSR_MSEL(IP16_7_4, SIM0_D_D, SEL_SIMCARD_3), 1416 1417 PINMUX_IPSR_GPSR(IP16_11_8, SSI_SDATA6), 1418 PINMUX_IPSR_MSEL(IP16_11_8, SIM0_CLK_D, SEL_SIMCARD_3), 1419 PINMUX_IPSR_GPSR(IP16_11_8, SATA_DEVSLP_A), 1420 1421 PINMUX_IPSR_GPSR(IP16_15_12, SSI_SCK78), 1422 PINMUX_IPSR_MSEL(IP16_15_12, HRX2_B, SEL_HSCIF2_1), 1423 PINMUX_IPSR_MSEL(IP16_15_12, MSIOF1_SCK_C, SEL_MSIOF1_2), 1424 PINMUX_IPSR_MSEL(IP16_15_12, TS_SCK1_A, SEL_TSIF1_0), 1425 PINMUX_IPSR_MSEL(IP16_15_12, STP_ISCLK_1_A, SEL_SSP1_1_0), 1426 PINMUX_IPSR_MSEL(IP16_15_12, RIF1_CLK_A, SEL_DRIF1_0), 1427 PINMUX_IPSR_MSEL(IP16_15_12, RIF3_CLK_A, SEL_DRIF3_0), 1428 1429 PINMUX_IPSR_GPSR(IP16_19_16, SSI_WS78), 1430 PINMUX_IPSR_MSEL(IP16_19_16, HTX2_B, SEL_HSCIF2_1), 1431 PINMUX_IPSR_MSEL(IP16_19_16, MSIOF1_SYNC_C, SEL_MSIOF1_2), 1432 PINMUX_IPSR_MSEL(IP16_19_16, TS_SDAT1_A, SEL_TSIF1_0), 1433 PINMUX_IPSR_MSEL(IP16_19_16, STP_ISD_1_A, SEL_SSP1_1_0), 1434 PINMUX_IPSR_MSEL(IP16_19_16, RIF1_SYNC_A, SEL_DRIF1_0), 1435 PINMUX_IPSR_MSEL(IP16_19_16, RIF3_SYNC_A, SEL_DRIF3_0), 1436 1437 PINMUX_IPSR_GPSR(IP16_23_20, SSI_SDATA7), 1438 PINMUX_IPSR_MSEL(IP16_23_20, HCTS2_N_B, SEL_HSCIF2_1), 1439 PINMUX_IPSR_MSEL(IP16_23_20, MSIOF1_RXD_C, SEL_MSIOF1_2), 1440 PINMUX_IPSR_MSEL(IP16_23_20, TS_SDEN1_A, SEL_TSIF1_0), 1441 PINMUX_IPSR_MSEL(IP16_23_20, STP_ISEN_1_A, SEL_SSP1_1_0), 1442 PINMUX_IPSR_MSEL(IP16_23_20, RIF1_D0_A, SEL_DRIF1_0), 1443 PINMUX_IPSR_MSEL(IP16_23_20, RIF3_D0_A, SEL_DRIF3_0), 1444 PINMUX_IPSR_MSEL(IP16_23_20, TCLK2_A, SEL_TIMER_TMU2_0), 1445 1446 PINMUX_IPSR_GPSR(IP16_27_24, SSI_SDATA8), 1447 PINMUX_IPSR_MSEL(IP16_27_24, HRTS2_N_B, SEL_HSCIF2_1), 1448 PINMUX_IPSR_MSEL(IP16_27_24, MSIOF1_TXD_C, SEL_MSIOF1_2), 1449 PINMUX_IPSR_MSEL(IP16_27_24, TS_SPSYNC1_A, SEL_TSIF1_0), 1450 PINMUX_IPSR_MSEL(IP16_27_24, STP_ISSYNC_1_A, SEL_SSP1_1_0), 1451 PINMUX_IPSR_MSEL(IP16_27_24, RIF1_D1_A, SEL_DRIF1_0), 1452 PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D1_A, SEL_DRIF3_0), 1453 1454 PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA9_A, SEL_SSI9_0), 1455 PINMUX_IPSR_MSEL(IP16_31_28, HSCK2_B, SEL_HSCIF2_1), 1456 PINMUX_IPSR_MSEL(IP16_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2), 1457 PINMUX_IPSR_MSEL(IP16_31_28, HSCK1_A, SEL_HSCIF1_0), 1458 PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI1_1), 1459 PINMUX_IPSR_GPSR(IP16_31_28, SCK1), 1460 PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0), 1461 PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0), 1462 1463 /* IPSR17 */ 1464 PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADGA_0), 1465 1466 PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADGB_1), 1467 PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0), 1468 PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3), 1469 PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0), 1470 PINMUX_IPSR_MSEL(IP17_7_4, TCLK1_A, SEL_TIMER_TMU_0), 1471 1472 PINMUX_IPSR_GPSR(IP17_11_8, USB0_PWEN), 1473 PINMUX_IPSR_MSEL(IP17_11_8, SIM0_RST_C, SEL_SIMCARD_2), 1474 PINMUX_IPSR_MSEL(IP17_11_8, TS_SCK1_D, SEL_TSIF1_3), 1475 PINMUX_IPSR_MSEL(IP17_11_8, STP_ISCLK_1_D, SEL_SSP1_1_3), 1476 PINMUX_IPSR_MSEL(IP17_11_8, BPFCLK_B, SEL_FM_1), 1477 PINMUX_IPSR_MSEL(IP17_11_8, RIF3_CLK_B, SEL_DRIF3_1), 1478 PINMUX_IPSR_MSEL(IP17_11_8, HSCK2_C, SEL_HSCIF2_2), 1479 1480 PINMUX_IPSR_GPSR(IP17_15_12, USB0_OVC), 1481 PINMUX_IPSR_MSEL(IP17_15_12, SIM0_D_C, SEL_SIMCARD_2), 1482 PINMUX_IPSR_MSEL(IP17_15_12, TS_SDAT1_D, SEL_TSIF1_3), 1483 PINMUX_IPSR_MSEL(IP17_15_12, STP_ISD_1_D, SEL_SSP1_1_3), 1484 PINMUX_IPSR_MSEL(IP17_15_12, RIF3_SYNC_B, SEL_DRIF3_1), 1485 PINMUX_IPSR_MSEL(IP17_15_12, HRX2_C, SEL_HSCIF2_2), 1486 1487 PINMUX_IPSR_GPSR(IP17_19_16, USB1_PWEN), 1488 PINMUX_IPSR_MSEL(IP17_19_16, SIM0_CLK_C, SEL_SIMCARD_2), 1489 PINMUX_IPSR_MSEL(IP17_19_16, SSI_SCK1_A, SEL_SSI1_0), 1490 PINMUX_IPSR_MSEL(IP17_19_16, TS_SCK0_E, SEL_TSIF0_4), 1491 PINMUX_IPSR_MSEL(IP17_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4), 1492 PINMUX_IPSR_MSEL(IP17_19_16, FMCLK_B, SEL_FM_1), 1493 PINMUX_IPSR_MSEL(IP17_19_16, RIF2_CLK_B, SEL_DRIF2_1), 1494 PINMUX_IPSR_MSEL(IP17_19_16, SPEEDIN_A, SEL_SPEED_PULSE_0), 1495 PINMUX_IPSR_MSEL(IP17_19_16, HTX2_C, SEL_HSCIF2_2), 1496 1497 PINMUX_IPSR_GPSR(IP17_23_20, USB1_OVC), 1498 PINMUX_IPSR_MSEL(IP17_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2), 1499 PINMUX_IPSR_MSEL(IP17_23_20, SSI_WS1_A, SEL_SSI1_0), 1500 PINMUX_IPSR_MSEL(IP17_23_20, TS_SDAT0_E, SEL_TSIF0_4), 1501 PINMUX_IPSR_MSEL(IP17_23_20, STP_ISD_0_E, SEL_SSP1_0_4), 1502 PINMUX_IPSR_MSEL(IP17_23_20, FMIN_B, SEL_FM_1), 1503 PINMUX_IPSR_MSEL(IP17_23_20, RIF2_SYNC_B, SEL_DRIF2_1), 1504 PINMUX_IPSR_MSEL(IP17_23_20, REMOCON_B, SEL_REMOCON_1), 1505 PINMUX_IPSR_MSEL(IP17_23_20, HCTS2_N_C, SEL_HSCIF2_2), 1506 1507 PINMUX_IPSR_GPSR(IP17_27_24, USB30_PWEN), 1508 PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_B), 1509 PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI2_1), 1510 PINMUX_IPSR_MSEL(IP17_27_24, TS_SDEN1_D, SEL_TSIF1_3), 1511 PINMUX_IPSR_MSEL(IP17_27_24, STP_ISEN_1_D, SEL_SSP1_1_3), 1512 PINMUX_IPSR_MSEL(IP17_27_24, STP_OPWM_0_E, SEL_SSP1_0_4), 1513 PINMUX_IPSR_MSEL(IP17_27_24, RIF3_D0_B, SEL_DRIF3_1), 1514 PINMUX_IPSR_MSEL(IP17_27_24, TCLK2_B, SEL_TIMER_TMU2_1), 1515 PINMUX_IPSR_GPSR(IP17_27_24, TPU0TO0), 1516 PINMUX_IPSR_MSEL(IP17_27_24, BPFCLK_C, SEL_FM_2), 1517 PINMUX_IPSR_MSEL(IP17_27_24, HRTS2_N_C, SEL_HSCIF2_2), 1518 1519 PINMUX_IPSR_GPSR(IP17_31_28, USB30_OVC), 1520 PINMUX_IPSR_GPSR(IP17_31_28, AUDIO_CLKOUT1_B), 1521 PINMUX_IPSR_MSEL(IP17_31_28, SSI_WS2_B, SEL_SSI2_1), 1522 PINMUX_IPSR_MSEL(IP17_31_28, TS_SPSYNC1_D, SEL_TSIF1_3), 1523 PINMUX_IPSR_MSEL(IP17_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3), 1524 PINMUX_IPSR_MSEL(IP17_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4), 1525 PINMUX_IPSR_MSEL(IP17_31_28, RIF3_D1_B, SEL_DRIF3_1), 1526 PINMUX_IPSR_GPSR(IP17_31_28, FSO_TOE_N), 1527 PINMUX_IPSR_GPSR(IP17_31_28, TPU0TO1), 1528 1529 /* IPSR18 */ 1530 PINMUX_IPSR_GPSR(IP18_3_0, GP6_30), 1531 PINMUX_IPSR_GPSR(IP18_3_0, AUDIO_CLKOUT2_B), 1532 PINMUX_IPSR_MSEL(IP18_3_0, SSI_SCK9_B, SEL_SSI9_1), 1533 PINMUX_IPSR_MSEL(IP18_3_0, TS_SDEN0_E, SEL_TSIF0_4), 1534 PINMUX_IPSR_MSEL(IP18_3_0, STP_ISEN_0_E, SEL_SSP1_0_4), 1535 PINMUX_IPSR_MSEL(IP18_3_0, RIF2_D0_B, SEL_DRIF2_1), 1536 PINMUX_IPSR_GPSR(IP18_3_0, TPU0TO2), 1537 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_C, SEL_FM_2), 1538 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_D, SEL_FM_3), 1539 1540 PINMUX_IPSR_GPSR(IP18_7_4, GP6_31), 1541 PINMUX_IPSR_GPSR(IP18_7_4, AUDIO_CLKOUT3_B), 1542 PINMUX_IPSR_MSEL(IP18_7_4, SSI_WS9_B, SEL_SSI9_1), 1543 PINMUX_IPSR_MSEL(IP18_7_4, TS_SPSYNC0_E, SEL_TSIF0_4), 1544 PINMUX_IPSR_MSEL(IP18_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4), 1545 PINMUX_IPSR_MSEL(IP18_7_4, RIF2_D1_B, SEL_DRIF2_1), 1546 PINMUX_IPSR_GPSR(IP18_7_4, TPU0TO3), 1547 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_C, SEL_FM_2), 1548 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_D, SEL_FM_3), 1549 1550 /* 1551 * Static pins can not be muxed between different functions but 1552 * still need mark entries in the pinmux list. Add each static 1553 * pin to the list without an associated function. The sh-pfc 1554 * core will do the right thing and skip trying to mux the pin 1555 * while still applying configuration to it. 1556 */ 1557 #define FM(x) PINMUX_DATA(x##_MARK, 0), 1558 PINMUX_STATIC 1559 #undef FM 1560 }; 1561 1562 /* 1563 * Pins not associated with a GPIO port. 1564 */ 1565 enum { 1566 GP_ASSIGN_LAST(), 1567 NOGP_ALL(), 1568 }; 1569 1570 static const struct sh_pfc_pin pinmux_pins[] = { 1571 PINMUX_GPIO_GP_ALL(), 1572 PINMUX_NOGP_ALL(), 1573 }; 1574 1575 /* - AUDIO CLOCK ------------------------------------------------------------ */ 1576 static const unsigned int audio_clk_a_a_pins[] = { 1577 /* CLK A */ 1578 RCAR_GP_PIN(6, 22), 1579 }; 1580 static const unsigned int audio_clk_a_a_mux[] = { 1581 AUDIO_CLKA_A_MARK, 1582 }; 1583 static const unsigned int audio_clk_a_b_pins[] = { 1584 /* CLK A */ 1585 RCAR_GP_PIN(5, 4), 1586 }; 1587 static const unsigned int audio_clk_a_b_mux[] = { 1588 AUDIO_CLKA_B_MARK, 1589 }; 1590 static const unsigned int audio_clk_a_c_pins[] = { 1591 /* CLK A */ 1592 RCAR_GP_PIN(5, 19), 1593 }; 1594 static const unsigned int audio_clk_a_c_mux[] = { 1595 AUDIO_CLKA_C_MARK, 1596 }; 1597 static const unsigned int audio_clk_b_a_pins[] = { 1598 /* CLK B */ 1599 RCAR_GP_PIN(5, 12), 1600 }; 1601 static const unsigned int audio_clk_b_a_mux[] = { 1602 AUDIO_CLKB_A_MARK, 1603 }; 1604 static const unsigned int audio_clk_b_b_pins[] = { 1605 /* CLK B */ 1606 RCAR_GP_PIN(6, 23), 1607 }; 1608 static const unsigned int audio_clk_b_b_mux[] = { 1609 AUDIO_CLKB_B_MARK, 1610 }; 1611 static const unsigned int audio_clk_c_a_pins[] = { 1612 /* CLK C */ 1613 RCAR_GP_PIN(5, 21), 1614 }; 1615 static const unsigned int audio_clk_c_a_mux[] = { 1616 AUDIO_CLKC_A_MARK, 1617 }; 1618 static const unsigned int audio_clk_c_b_pins[] = { 1619 /* CLK C */ 1620 RCAR_GP_PIN(5, 0), 1621 }; 1622 static const unsigned int audio_clk_c_b_mux[] = { 1623 AUDIO_CLKC_B_MARK, 1624 }; 1625 static const unsigned int audio_clkout_a_pins[] = { 1626 /* CLKOUT */ 1627 RCAR_GP_PIN(5, 18), 1628 }; 1629 static const unsigned int audio_clkout_a_mux[] = { 1630 AUDIO_CLKOUT_A_MARK, 1631 }; 1632 static const unsigned int audio_clkout_b_pins[] = { 1633 /* CLKOUT */ 1634 RCAR_GP_PIN(6, 28), 1635 }; 1636 static const unsigned int audio_clkout_b_mux[] = { 1637 AUDIO_CLKOUT_B_MARK, 1638 }; 1639 static const unsigned int audio_clkout_c_pins[] = { 1640 /* CLKOUT */ 1641 RCAR_GP_PIN(5, 3), 1642 }; 1643 static const unsigned int audio_clkout_c_mux[] = { 1644 AUDIO_CLKOUT_C_MARK, 1645 }; 1646 static const unsigned int audio_clkout_d_pins[] = { 1647 /* CLKOUT */ 1648 RCAR_GP_PIN(5, 21), 1649 }; 1650 static const unsigned int audio_clkout_d_mux[] = { 1651 AUDIO_CLKOUT_D_MARK, 1652 }; 1653 static const unsigned int audio_clkout1_a_pins[] = { 1654 /* CLKOUT1 */ 1655 RCAR_GP_PIN(5, 15), 1656 }; 1657 static const unsigned int audio_clkout1_a_mux[] = { 1658 AUDIO_CLKOUT1_A_MARK, 1659 }; 1660 static const unsigned int audio_clkout1_b_pins[] = { 1661 /* CLKOUT1 */ 1662 RCAR_GP_PIN(6, 29), 1663 }; 1664 static const unsigned int audio_clkout1_b_mux[] = { 1665 AUDIO_CLKOUT1_B_MARK, 1666 }; 1667 static const unsigned int audio_clkout2_a_pins[] = { 1668 /* CLKOUT2 */ 1669 RCAR_GP_PIN(5, 16), 1670 }; 1671 static const unsigned int audio_clkout2_a_mux[] = { 1672 AUDIO_CLKOUT2_A_MARK, 1673 }; 1674 static const unsigned int audio_clkout2_b_pins[] = { 1675 /* CLKOUT2 */ 1676 RCAR_GP_PIN(6, 30), 1677 }; 1678 static const unsigned int audio_clkout2_b_mux[] = { 1679 AUDIO_CLKOUT2_B_MARK, 1680 }; 1681 1682 static const unsigned int audio_clkout3_a_pins[] = { 1683 /* CLKOUT3 */ 1684 RCAR_GP_PIN(5, 19), 1685 }; 1686 static const unsigned int audio_clkout3_a_mux[] = { 1687 AUDIO_CLKOUT3_A_MARK, 1688 }; 1689 static const unsigned int audio_clkout3_b_pins[] = { 1690 /* CLKOUT3 */ 1691 RCAR_GP_PIN(6, 31), 1692 }; 1693 static const unsigned int audio_clkout3_b_mux[] = { 1694 AUDIO_CLKOUT3_B_MARK, 1695 }; 1696 1697 /* - EtherAVB --------------------------------------------------------------- */ 1698 static const unsigned int avb_link_pins[] = { 1699 /* AVB_LINK */ 1700 RCAR_GP_PIN(2, 12), 1701 }; 1702 static const unsigned int avb_link_mux[] = { 1703 AVB_LINK_MARK, 1704 }; 1705 static const unsigned int avb_magic_pins[] = { 1706 /* AVB_MAGIC_ */ 1707 RCAR_GP_PIN(2, 10), 1708 }; 1709 static const unsigned int avb_magic_mux[] = { 1710 AVB_MAGIC_MARK, 1711 }; 1712 static const unsigned int avb_phy_int_pins[] = { 1713 /* AVB_PHY_INT */ 1714 RCAR_GP_PIN(2, 11), 1715 }; 1716 static const unsigned int avb_phy_int_mux[] = { 1717 AVB_PHY_INT_MARK, 1718 }; 1719 static const unsigned int avb_mdio_pins[] = { 1720 /* AVB_MDC, AVB_MDIO */ 1721 RCAR_GP_PIN(2, 9), PIN_AVB_MDIO, 1722 }; 1723 static const unsigned int avb_mdio_mux[] = { 1724 AVB_MDC_MARK, AVB_MDIO_MARK, 1725 }; 1726 static const unsigned int avb_mii_pins[] = { 1727 /* 1728 * AVB_TX_CTL, AVB_TXC, AVB_TD0, 1729 * AVB_TD1, AVB_TD2, AVB_TD3, 1730 * AVB_RX_CTL, AVB_RXC, AVB_RD0, 1731 * AVB_RD1, AVB_RD2, AVB_RD3, 1732 * AVB_TXCREFCLK 1733 */ 1734 PIN_AVB_TX_CTL, PIN_AVB_TXC, PIN_AVB_TD0, 1735 PIN_AVB_TD1, PIN_AVB_TD2, PIN_AVB_TD3, 1736 PIN_AVB_RX_CTL, PIN_AVB_RXC, PIN_AVB_RD0, 1737 PIN_AVB_RD1, PIN_AVB_RD2, PIN_AVB_RD3, 1738 PIN_AVB_TXCREFCLK, 1739 }; 1740 static const unsigned int avb_mii_mux[] = { 1741 AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK, 1742 AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK, 1743 AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK, 1744 AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK, 1745 AVB_TXCREFCLK_MARK, 1746 }; 1747 static const unsigned int avb_avtp_pps_pins[] = { 1748 /* AVB_AVTP_PPS */ 1749 RCAR_GP_PIN(2, 6), 1750 }; 1751 static const unsigned int avb_avtp_pps_mux[] = { 1752 AVB_AVTP_PPS_MARK, 1753 }; 1754 static const unsigned int avb_avtp_match_a_pins[] = { 1755 /* AVB_AVTP_MATCH_A */ 1756 RCAR_GP_PIN(2, 13), 1757 }; 1758 static const unsigned int avb_avtp_match_a_mux[] = { 1759 AVB_AVTP_MATCH_A_MARK, 1760 }; 1761 static const unsigned int avb_avtp_capture_a_pins[] = { 1762 /* AVB_AVTP_CAPTURE_A */ 1763 RCAR_GP_PIN(2, 14), 1764 }; 1765 static const unsigned int avb_avtp_capture_a_mux[] = { 1766 AVB_AVTP_CAPTURE_A_MARK, 1767 }; 1768 static const unsigned int avb_avtp_match_b_pins[] = { 1769 /* AVB_AVTP_MATCH_B */ 1770 RCAR_GP_PIN(1, 8), 1771 }; 1772 static const unsigned int avb_avtp_match_b_mux[] = { 1773 AVB_AVTP_MATCH_B_MARK, 1774 }; 1775 static const unsigned int avb_avtp_capture_b_pins[] = { 1776 /* AVB_AVTP_CAPTURE_B */ 1777 RCAR_GP_PIN(1, 11), 1778 }; 1779 static const unsigned int avb_avtp_capture_b_mux[] = { 1780 AVB_AVTP_CAPTURE_B_MARK, 1781 }; 1782 1783 /* - CAN ------------------------------------------------------------------ */ 1784 static const unsigned int can0_data_a_pins[] = { 1785 /* TX, RX */ 1786 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24), 1787 }; 1788 1789 static const unsigned int can0_data_a_mux[] = { 1790 CAN0_TX_A_MARK, CAN0_RX_A_MARK, 1791 }; 1792 1793 static const unsigned int can0_data_b_pins[] = { 1794 /* TX, RX */ 1795 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), 1796 }; 1797 1798 static const unsigned int can0_data_b_mux[] = { 1799 CAN0_TX_B_MARK, CAN0_RX_B_MARK, 1800 }; 1801 1802 static const unsigned int can1_data_pins[] = { 1803 /* TX, RX */ 1804 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26), 1805 }; 1806 1807 static const unsigned int can1_data_mux[] = { 1808 CAN1_TX_MARK, CAN1_RX_MARK, 1809 }; 1810 1811 /* - CAN Clock -------------------------------------------------------------- */ 1812 static const unsigned int can_clk_pins[] = { 1813 /* CLK */ 1814 RCAR_GP_PIN(1, 25), 1815 }; 1816 1817 static const unsigned int can_clk_mux[] = { 1818 CAN_CLK_MARK, 1819 }; 1820 1821 /* - CAN FD --------------------------------------------------------------- */ 1822 static const unsigned int canfd0_data_a_pins[] = { 1823 /* TX, RX */ 1824 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24), 1825 }; 1826 1827 static const unsigned int canfd0_data_a_mux[] = { 1828 CANFD0_TX_A_MARK, CANFD0_RX_A_MARK, 1829 }; 1830 1831 static const unsigned int canfd0_data_b_pins[] = { 1832 /* TX, RX */ 1833 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), 1834 }; 1835 1836 static const unsigned int canfd0_data_b_mux[] = { 1837 CANFD0_TX_B_MARK, CANFD0_RX_B_MARK, 1838 }; 1839 1840 static const unsigned int canfd1_data_pins[] = { 1841 /* TX, RX */ 1842 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26), 1843 }; 1844 1845 static const unsigned int canfd1_data_mux[] = { 1846 CANFD1_TX_MARK, CANFD1_RX_MARK, 1847 }; 1848 1849 /* - DRIF0 --------------------------------------------------------------- */ 1850 static const unsigned int drif0_ctrl_a_pins[] = { 1851 /* CLK, SYNC */ 1852 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), 1853 }; 1854 1855 static const unsigned int drif0_ctrl_a_mux[] = { 1856 RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK, 1857 }; 1858 1859 static const unsigned int drif0_data0_a_pins[] = { 1860 /* D0 */ 1861 RCAR_GP_PIN(6, 10), 1862 }; 1863 1864 static const unsigned int drif0_data0_a_mux[] = { 1865 RIF0_D0_A_MARK, 1866 }; 1867 1868 static const unsigned int drif0_data1_a_pins[] = { 1869 /* D1 */ 1870 RCAR_GP_PIN(6, 7), 1871 }; 1872 1873 static const unsigned int drif0_data1_a_mux[] = { 1874 RIF0_D1_A_MARK, 1875 }; 1876 1877 static const unsigned int drif0_ctrl_b_pins[] = { 1878 /* CLK, SYNC */ 1879 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4), 1880 }; 1881 1882 static const unsigned int drif0_ctrl_b_mux[] = { 1883 RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK, 1884 }; 1885 1886 static const unsigned int drif0_data0_b_pins[] = { 1887 /* D0 */ 1888 RCAR_GP_PIN(5, 1), 1889 }; 1890 1891 static const unsigned int drif0_data0_b_mux[] = { 1892 RIF0_D0_B_MARK, 1893 }; 1894 1895 static const unsigned int drif0_data1_b_pins[] = { 1896 /* D1 */ 1897 RCAR_GP_PIN(5, 2), 1898 }; 1899 1900 static const unsigned int drif0_data1_b_mux[] = { 1901 RIF0_D1_B_MARK, 1902 }; 1903 1904 static const unsigned int drif0_ctrl_c_pins[] = { 1905 /* CLK, SYNC */ 1906 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15), 1907 }; 1908 1909 static const unsigned int drif0_ctrl_c_mux[] = { 1910 RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK, 1911 }; 1912 1913 static const unsigned int drif0_data0_c_pins[] = { 1914 /* D0 */ 1915 RCAR_GP_PIN(5, 13), 1916 }; 1917 1918 static const unsigned int drif0_data0_c_mux[] = { 1919 RIF0_D0_C_MARK, 1920 }; 1921 1922 static const unsigned int drif0_data1_c_pins[] = { 1923 /* D1 */ 1924 RCAR_GP_PIN(5, 14), 1925 }; 1926 1927 static const unsigned int drif0_data1_c_mux[] = { 1928 RIF0_D1_C_MARK, 1929 }; 1930 1931 /* - DRIF1 --------------------------------------------------------------- */ 1932 static const unsigned int drif1_ctrl_a_pins[] = { 1933 /* CLK, SYNC */ 1934 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18), 1935 }; 1936 1937 static const unsigned int drif1_ctrl_a_mux[] = { 1938 RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK, 1939 }; 1940 1941 static const unsigned int drif1_data0_a_pins[] = { 1942 /* D0 */ 1943 RCAR_GP_PIN(6, 19), 1944 }; 1945 1946 static const unsigned int drif1_data0_a_mux[] = { 1947 RIF1_D0_A_MARK, 1948 }; 1949 1950 static const unsigned int drif1_data1_a_pins[] = { 1951 /* D1 */ 1952 RCAR_GP_PIN(6, 20), 1953 }; 1954 1955 static const unsigned int drif1_data1_a_mux[] = { 1956 RIF1_D1_A_MARK, 1957 }; 1958 1959 static const unsigned int drif1_ctrl_b_pins[] = { 1960 /* CLK, SYNC */ 1961 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3), 1962 }; 1963 1964 static const unsigned int drif1_ctrl_b_mux[] = { 1965 RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK, 1966 }; 1967 1968 static const unsigned int drif1_data0_b_pins[] = { 1969 /* D0 */ 1970 RCAR_GP_PIN(5, 7), 1971 }; 1972 1973 static const unsigned int drif1_data0_b_mux[] = { 1974 RIF1_D0_B_MARK, 1975 }; 1976 1977 static const unsigned int drif1_data1_b_pins[] = { 1978 /* D1 */ 1979 RCAR_GP_PIN(5, 8), 1980 }; 1981 1982 static const unsigned int drif1_data1_b_mux[] = { 1983 RIF1_D1_B_MARK, 1984 }; 1985 1986 static const unsigned int drif1_ctrl_c_pins[] = { 1987 /* CLK, SYNC */ 1988 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11), 1989 }; 1990 1991 static const unsigned int drif1_ctrl_c_mux[] = { 1992 RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK, 1993 }; 1994 1995 static const unsigned int drif1_data0_c_pins[] = { 1996 /* D0 */ 1997 RCAR_GP_PIN(5, 6), 1998 }; 1999 2000 static const unsigned int drif1_data0_c_mux[] = { 2001 RIF1_D0_C_MARK, 2002 }; 2003 2004 static const unsigned int drif1_data1_c_pins[] = { 2005 /* D1 */ 2006 RCAR_GP_PIN(5, 10), 2007 }; 2008 2009 static const unsigned int drif1_data1_c_mux[] = { 2010 RIF1_D1_C_MARK, 2011 }; 2012 2013 /* - DRIF2 --------------------------------------------------------------- */ 2014 static const unsigned int drif2_ctrl_a_pins[] = { 2015 /* CLK, SYNC */ 2016 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), 2017 }; 2018 2019 static const unsigned int drif2_ctrl_a_mux[] = { 2020 RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK, 2021 }; 2022 2023 static const unsigned int drif2_data0_a_pins[] = { 2024 /* D0 */ 2025 RCAR_GP_PIN(6, 7), 2026 }; 2027 2028 static const unsigned int drif2_data0_a_mux[] = { 2029 RIF2_D0_A_MARK, 2030 }; 2031 2032 static const unsigned int drif2_data1_a_pins[] = { 2033 /* D1 */ 2034 RCAR_GP_PIN(6, 10), 2035 }; 2036 2037 static const unsigned int drif2_data1_a_mux[] = { 2038 RIF2_D1_A_MARK, 2039 }; 2040 2041 static const unsigned int drif2_ctrl_b_pins[] = { 2042 /* CLK, SYNC */ 2043 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27), 2044 }; 2045 2046 static const unsigned int drif2_ctrl_b_mux[] = { 2047 RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK, 2048 }; 2049 2050 static const unsigned int drif2_data0_b_pins[] = { 2051 /* D0 */ 2052 RCAR_GP_PIN(6, 30), 2053 }; 2054 2055 static const unsigned int drif2_data0_b_mux[] = { 2056 RIF2_D0_B_MARK, 2057 }; 2058 2059 static const unsigned int drif2_data1_b_pins[] = { 2060 /* D1 */ 2061 RCAR_GP_PIN(6, 31), 2062 }; 2063 2064 static const unsigned int drif2_data1_b_mux[] = { 2065 RIF2_D1_B_MARK, 2066 }; 2067 2068 /* - DRIF3 --------------------------------------------------------------- */ 2069 static const unsigned int drif3_ctrl_a_pins[] = { 2070 /* CLK, SYNC */ 2071 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18), 2072 }; 2073 2074 static const unsigned int drif3_ctrl_a_mux[] = { 2075 RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK, 2076 }; 2077 2078 static const unsigned int drif3_data0_a_pins[] = { 2079 /* D0 */ 2080 RCAR_GP_PIN(6, 19), 2081 }; 2082 2083 static const unsigned int drif3_data0_a_mux[] = { 2084 RIF3_D0_A_MARK, 2085 }; 2086 2087 static const unsigned int drif3_data1_a_pins[] = { 2088 /* D1 */ 2089 RCAR_GP_PIN(6, 20), 2090 }; 2091 2092 static const unsigned int drif3_data1_a_mux[] = { 2093 RIF3_D1_A_MARK, 2094 }; 2095 2096 static const unsigned int drif3_ctrl_b_pins[] = { 2097 /* CLK, SYNC */ 2098 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25), 2099 }; 2100 2101 static const unsigned int drif3_ctrl_b_mux[] = { 2102 RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK, 2103 }; 2104 2105 static const unsigned int drif3_data0_b_pins[] = { 2106 /* D0 */ 2107 RCAR_GP_PIN(6, 28), 2108 }; 2109 2110 static const unsigned int drif3_data0_b_mux[] = { 2111 RIF3_D0_B_MARK, 2112 }; 2113 2114 static const unsigned int drif3_data1_b_pins[] = { 2115 /* D1 */ 2116 RCAR_GP_PIN(6, 29), 2117 }; 2118 2119 static const unsigned int drif3_data1_b_mux[] = { 2120 RIF3_D1_B_MARK, 2121 }; 2122 2123 /* - DU --------------------------------------------------------------------- */ 2124 static const unsigned int du_rgb666_pins[] = { 2125 /* R[7:2], G[7:2], B[7:2] */ 2126 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), 2127 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), 2128 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), 2129 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18), 2130 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5), 2131 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2), 2132 }; 2133 2134 static const unsigned int du_rgb666_mux[] = { 2135 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK, 2136 DU_DR3_MARK, DU_DR2_MARK, 2137 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK, 2138 DU_DG3_MARK, DU_DG2_MARK, 2139 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK, 2140 DU_DB3_MARK, DU_DB2_MARK, 2141 }; 2142 2143 static const unsigned int du_rgb888_pins[] = { 2144 /* R[7:0], G[7:0], B[7:0] */ 2145 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), 2146 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), 2147 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8), 2148 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), 2149 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18), 2150 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16), 2151 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5), 2152 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2), 2153 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0), 2154 }; 2155 2156 static const unsigned int du_rgb888_mux[] = { 2157 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK, 2158 DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK, 2159 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK, 2160 DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK, 2161 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK, 2162 DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK, 2163 }; 2164 2165 static const unsigned int du_clk_out_0_pins[] = { 2166 /* CLKOUT */ 2167 RCAR_GP_PIN(1, 27), 2168 }; 2169 2170 static const unsigned int du_clk_out_0_mux[] = { 2171 DU_DOTCLKOUT0_MARK 2172 }; 2173 2174 static const unsigned int du_clk_out_1_pins[] = { 2175 /* CLKOUT */ 2176 RCAR_GP_PIN(2, 3), 2177 }; 2178 2179 static const unsigned int du_clk_out_1_mux[] = { 2180 DU_DOTCLKOUT1_MARK 2181 }; 2182 2183 static const unsigned int du_sync_pins[] = { 2184 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */ 2185 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4), 2186 }; 2187 2188 static const unsigned int du_sync_mux[] = { 2189 DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK 2190 }; 2191 2192 static const unsigned int du_oddf_pins[] = { 2193 /* EXDISP/EXODDF/EXCDE */ 2194 RCAR_GP_PIN(2, 2), 2195 }; 2196 2197 static const unsigned int du_oddf_mux[] = { 2198 DU_EXODDF_DU_ODDF_DISP_CDE_MARK, 2199 }; 2200 2201 static const unsigned int du_cde_pins[] = { 2202 /* CDE */ 2203 RCAR_GP_PIN(2, 0), 2204 }; 2205 2206 static const unsigned int du_cde_mux[] = { 2207 DU_CDE_MARK, 2208 }; 2209 2210 static const unsigned int du_disp_pins[] = { 2211 /* DISP */ 2212 RCAR_GP_PIN(2, 1), 2213 }; 2214 2215 static const unsigned int du_disp_mux[] = { 2216 DU_DISP_MARK, 2217 }; 2218 2219 /* - HSCIF0 ----------------------------------------------------------------- */ 2220 static const unsigned int hscif0_data_pins[] = { 2221 /* RX, TX */ 2222 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14), 2223 }; 2224 2225 static const unsigned int hscif0_data_mux[] = { 2226 HRX0_MARK, HTX0_MARK, 2227 }; 2228 2229 static const unsigned int hscif0_clk_pins[] = { 2230 /* SCK */ 2231 RCAR_GP_PIN(5, 12), 2232 }; 2233 2234 static const unsigned int hscif0_clk_mux[] = { 2235 HSCK0_MARK, 2236 }; 2237 2238 static const unsigned int hscif0_ctrl_pins[] = { 2239 /* RTS, CTS */ 2240 RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15), 2241 }; 2242 2243 static const unsigned int hscif0_ctrl_mux[] = { 2244 HRTS0_N_MARK, HCTS0_N_MARK, 2245 }; 2246 2247 /* - HSCIF1 ----------------------------------------------------------------- */ 2248 static const unsigned int hscif1_data_a_pins[] = { 2249 /* RX, TX */ 2250 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6), 2251 }; 2252 2253 static const unsigned int hscif1_data_a_mux[] = { 2254 HRX1_A_MARK, HTX1_A_MARK, 2255 }; 2256 2257 static const unsigned int hscif1_clk_a_pins[] = { 2258 /* SCK */ 2259 RCAR_GP_PIN(6, 21), 2260 }; 2261 2262 static const unsigned int hscif1_clk_a_mux[] = { 2263 HSCK1_A_MARK, 2264 }; 2265 2266 static const unsigned int hscif1_ctrl_a_pins[] = { 2267 /* RTS, CTS */ 2268 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7), 2269 }; 2270 2271 static const unsigned int hscif1_ctrl_a_mux[] = { 2272 HRTS1_N_A_MARK, HCTS1_N_A_MARK, 2273 }; 2274 2275 static const unsigned int hscif1_data_b_pins[] = { 2276 /* RX, TX */ 2277 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), 2278 }; 2279 2280 static const unsigned int hscif1_data_b_mux[] = { 2281 HRX1_B_MARK, HTX1_B_MARK, 2282 }; 2283 2284 static const unsigned int hscif1_clk_b_pins[] = { 2285 /* SCK */ 2286 RCAR_GP_PIN(5, 0), 2287 }; 2288 2289 static const unsigned int hscif1_clk_b_mux[] = { 2290 HSCK1_B_MARK, 2291 }; 2292 2293 static const unsigned int hscif1_ctrl_b_pins[] = { 2294 /* RTS, CTS */ 2295 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3), 2296 }; 2297 2298 static const unsigned int hscif1_ctrl_b_mux[] = { 2299 HRTS1_N_B_MARK, HCTS1_N_B_MARK, 2300 }; 2301 2302 /* - HSCIF2 ----------------------------------------------------------------- */ 2303 static const unsigned int hscif2_data_a_pins[] = { 2304 /* RX, TX */ 2305 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), 2306 }; 2307 2308 static const unsigned int hscif2_data_a_mux[] = { 2309 HRX2_A_MARK, HTX2_A_MARK, 2310 }; 2311 2312 static const unsigned int hscif2_clk_a_pins[] = { 2313 /* SCK */ 2314 RCAR_GP_PIN(6, 10), 2315 }; 2316 2317 static const unsigned int hscif2_clk_a_mux[] = { 2318 HSCK2_A_MARK, 2319 }; 2320 2321 static const unsigned int hscif2_ctrl_a_pins[] = { 2322 /* RTS, CTS */ 2323 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6), 2324 }; 2325 2326 static const unsigned int hscif2_ctrl_a_mux[] = { 2327 HRTS2_N_A_MARK, HCTS2_N_A_MARK, 2328 }; 2329 2330 static const unsigned int hscif2_data_b_pins[] = { 2331 /* RX, TX */ 2332 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18), 2333 }; 2334 2335 static const unsigned int hscif2_data_b_mux[] = { 2336 HRX2_B_MARK, HTX2_B_MARK, 2337 }; 2338 2339 static const unsigned int hscif2_clk_b_pins[] = { 2340 /* SCK */ 2341 RCAR_GP_PIN(6, 21), 2342 }; 2343 2344 static const unsigned int hscif2_clk_b_mux[] = { 2345 HSCK2_B_MARK, 2346 }; 2347 2348 static const unsigned int hscif2_ctrl_b_pins[] = { 2349 /* RTS, CTS */ 2350 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19), 2351 }; 2352 2353 static const unsigned int hscif2_ctrl_b_mux[] = { 2354 HRTS2_N_B_MARK, HCTS2_N_B_MARK, 2355 }; 2356 2357 static const unsigned int hscif2_data_c_pins[] = { 2358 /* RX, TX */ 2359 RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26), 2360 }; 2361 2362 static const unsigned int hscif2_data_c_mux[] = { 2363 HRX2_C_MARK, HTX2_C_MARK, 2364 }; 2365 2366 static const unsigned int hscif2_clk_c_pins[] = { 2367 /* SCK */ 2368 RCAR_GP_PIN(6, 24), 2369 }; 2370 2371 static const unsigned int hscif2_clk_c_mux[] = { 2372 HSCK2_C_MARK, 2373 }; 2374 2375 static const unsigned int hscif2_ctrl_c_pins[] = { 2376 /* RTS, CTS */ 2377 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 27), 2378 }; 2379 2380 static const unsigned int hscif2_ctrl_c_mux[] = { 2381 HRTS2_N_C_MARK, HCTS2_N_C_MARK, 2382 }; 2383 2384 /* - HSCIF3 ----------------------------------------------------------------- */ 2385 static const unsigned int hscif3_data_a_pins[] = { 2386 /* RX, TX */ 2387 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24), 2388 }; 2389 2390 static const unsigned int hscif3_data_a_mux[] = { 2391 HRX3_A_MARK, HTX3_A_MARK, 2392 }; 2393 2394 static const unsigned int hscif3_clk_pins[] = { 2395 /* SCK */ 2396 RCAR_GP_PIN(1, 22), 2397 }; 2398 2399 static const unsigned int hscif3_clk_mux[] = { 2400 HSCK3_MARK, 2401 }; 2402 2403 static const unsigned int hscif3_ctrl_pins[] = { 2404 /* RTS, CTS */ 2405 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25), 2406 }; 2407 2408 static const unsigned int hscif3_ctrl_mux[] = { 2409 HRTS3_N_MARK, HCTS3_N_MARK, 2410 }; 2411 2412 static const unsigned int hscif3_data_b_pins[] = { 2413 /* RX, TX */ 2414 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), 2415 }; 2416 2417 static const unsigned int hscif3_data_b_mux[] = { 2418 HRX3_B_MARK, HTX3_B_MARK, 2419 }; 2420 2421 static const unsigned int hscif3_data_c_pins[] = { 2422 /* RX, TX */ 2423 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), 2424 }; 2425 2426 static const unsigned int hscif3_data_c_mux[] = { 2427 HRX3_C_MARK, HTX3_C_MARK, 2428 }; 2429 2430 static const unsigned int hscif3_data_d_pins[] = { 2431 /* RX, TX */ 2432 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), 2433 }; 2434 2435 static const unsigned int hscif3_data_d_mux[] = { 2436 HRX3_D_MARK, HTX3_D_MARK, 2437 }; 2438 2439 /* - HSCIF4 ----------------------------------------------------------------- */ 2440 static const unsigned int hscif4_data_a_pins[] = { 2441 /* RX, TX */ 2442 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), 2443 }; 2444 2445 static const unsigned int hscif4_data_a_mux[] = { 2446 HRX4_A_MARK, HTX4_A_MARK, 2447 }; 2448 2449 static const unsigned int hscif4_clk_pins[] = { 2450 /* SCK */ 2451 RCAR_GP_PIN(1, 11), 2452 }; 2453 2454 static const unsigned int hscif4_clk_mux[] = { 2455 HSCK4_MARK, 2456 }; 2457 2458 static const unsigned int hscif4_ctrl_pins[] = { 2459 /* RTS, CTS */ 2460 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), 2461 }; 2462 2463 static const unsigned int hscif4_ctrl_mux[] = { 2464 HRTS4_N_MARK, HCTS4_N_MARK, 2465 }; 2466 2467 static const unsigned int hscif4_data_b_pins[] = { 2468 /* RX, TX */ 2469 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), 2470 }; 2471 2472 static const unsigned int hscif4_data_b_mux[] = { 2473 HRX4_B_MARK, HTX4_B_MARK, 2474 }; 2475 2476 /* - I2C -------------------------------------------------------------------- */ 2477 static const unsigned int i2c0_pins[] = { 2478 /* SCL, SDA */ 2479 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), 2480 }; 2481 2482 static const unsigned int i2c0_mux[] = { 2483 SCL0_MARK, SDA0_MARK, 2484 }; 2485 2486 static const unsigned int i2c1_a_pins[] = { 2487 /* SDA, SCL */ 2488 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10), 2489 }; 2490 2491 static const unsigned int i2c1_a_mux[] = { 2492 SDA1_A_MARK, SCL1_A_MARK, 2493 }; 2494 2495 static const unsigned int i2c1_b_pins[] = { 2496 /* SDA, SCL */ 2497 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23), 2498 }; 2499 2500 static const unsigned int i2c1_b_mux[] = { 2501 SDA1_B_MARK, SCL1_B_MARK, 2502 }; 2503 2504 static const unsigned int i2c2_a_pins[] = { 2505 /* SDA, SCL */ 2506 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4), 2507 }; 2508 2509 static const unsigned int i2c2_a_mux[] = { 2510 SDA2_A_MARK, SCL2_A_MARK, 2511 }; 2512 2513 static const unsigned int i2c2_b_pins[] = { 2514 /* SDA, SCL */ 2515 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12), 2516 }; 2517 2518 static const unsigned int i2c2_b_mux[] = { 2519 SDA2_B_MARK, SCL2_B_MARK, 2520 }; 2521 2522 static const unsigned int i2c3_pins[] = { 2523 /* SCL, SDA */ 2524 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), 2525 }; 2526 2527 static const unsigned int i2c3_mux[] = { 2528 SCL3_MARK, SDA3_MARK, 2529 }; 2530 2531 static const unsigned int i2c5_pins[] = { 2532 /* SCL, SDA */ 2533 RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14), 2534 }; 2535 2536 static const unsigned int i2c5_mux[] = { 2537 SCL5_MARK, SDA5_MARK, 2538 }; 2539 2540 static const unsigned int i2c6_a_pins[] = { 2541 /* SDA, SCL */ 2542 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), 2543 }; 2544 2545 static const unsigned int i2c6_a_mux[] = { 2546 SDA6_A_MARK, SCL6_A_MARK, 2547 }; 2548 2549 static const unsigned int i2c6_b_pins[] = { 2550 /* SDA, SCL */ 2551 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25), 2552 }; 2553 2554 static const unsigned int i2c6_b_mux[] = { 2555 SDA6_B_MARK, SCL6_B_MARK, 2556 }; 2557 2558 static const unsigned int i2c6_c_pins[] = { 2559 /* SDA, SCL */ 2560 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), 2561 }; 2562 2563 static const unsigned int i2c6_c_mux[] = { 2564 SDA6_C_MARK, SCL6_C_MARK, 2565 }; 2566 2567 /* - INTC-EX ---------------------------------------------------------------- */ 2568 static const unsigned int intc_ex_irq0_pins[] = { 2569 /* IRQ0 */ 2570 RCAR_GP_PIN(2, 0), 2571 }; 2572 static const unsigned int intc_ex_irq0_mux[] = { 2573 IRQ0_MARK, 2574 }; 2575 static const unsigned int intc_ex_irq1_pins[] = { 2576 /* IRQ1 */ 2577 RCAR_GP_PIN(2, 1), 2578 }; 2579 static const unsigned int intc_ex_irq1_mux[] = { 2580 IRQ1_MARK, 2581 }; 2582 static const unsigned int intc_ex_irq2_pins[] = { 2583 /* IRQ2 */ 2584 RCAR_GP_PIN(2, 2), 2585 }; 2586 static const unsigned int intc_ex_irq2_mux[] = { 2587 IRQ2_MARK, 2588 }; 2589 static const unsigned int intc_ex_irq3_pins[] = { 2590 /* IRQ3 */ 2591 RCAR_GP_PIN(2, 3), 2592 }; 2593 static const unsigned int intc_ex_irq3_mux[] = { 2594 IRQ3_MARK, 2595 }; 2596 static const unsigned int intc_ex_irq4_pins[] = { 2597 /* IRQ4 */ 2598 RCAR_GP_PIN(2, 4), 2599 }; 2600 static const unsigned int intc_ex_irq4_mux[] = { 2601 IRQ4_MARK, 2602 }; 2603 static const unsigned int intc_ex_irq5_pins[] = { 2604 /* IRQ5 */ 2605 RCAR_GP_PIN(2, 5), 2606 }; 2607 static const unsigned int intc_ex_irq5_mux[] = { 2608 IRQ5_MARK, 2609 }; 2610 2611 /* - MSIOF0 ----------------------------------------------------------------- */ 2612 static const unsigned int msiof0_clk_pins[] = { 2613 /* SCK */ 2614 RCAR_GP_PIN(5, 17), 2615 }; 2616 static const unsigned int msiof0_clk_mux[] = { 2617 MSIOF0_SCK_MARK, 2618 }; 2619 static const unsigned int msiof0_sync_pins[] = { 2620 /* SYNC */ 2621 RCAR_GP_PIN(5, 18), 2622 }; 2623 static const unsigned int msiof0_sync_mux[] = { 2624 MSIOF0_SYNC_MARK, 2625 }; 2626 static const unsigned int msiof0_ss1_pins[] = { 2627 /* SS1 */ 2628 RCAR_GP_PIN(5, 19), 2629 }; 2630 static const unsigned int msiof0_ss1_mux[] = { 2631 MSIOF0_SS1_MARK, 2632 }; 2633 static const unsigned int msiof0_ss2_pins[] = { 2634 /* SS2 */ 2635 RCAR_GP_PIN(5, 21), 2636 }; 2637 static const unsigned int msiof0_ss2_mux[] = { 2638 MSIOF0_SS2_MARK, 2639 }; 2640 static const unsigned int msiof0_txd_pins[] = { 2641 /* TXD */ 2642 RCAR_GP_PIN(5, 20), 2643 }; 2644 static const unsigned int msiof0_txd_mux[] = { 2645 MSIOF0_TXD_MARK, 2646 }; 2647 static const unsigned int msiof0_rxd_pins[] = { 2648 /* RXD */ 2649 RCAR_GP_PIN(5, 22), 2650 }; 2651 static const unsigned int msiof0_rxd_mux[] = { 2652 MSIOF0_RXD_MARK, 2653 }; 2654 /* - MSIOF1 ----------------------------------------------------------------- */ 2655 static const unsigned int msiof1_clk_a_pins[] = { 2656 /* SCK */ 2657 RCAR_GP_PIN(6, 8), 2658 }; 2659 static const unsigned int msiof1_clk_a_mux[] = { 2660 MSIOF1_SCK_A_MARK, 2661 }; 2662 static const unsigned int msiof1_sync_a_pins[] = { 2663 /* SYNC */ 2664 RCAR_GP_PIN(6, 9), 2665 }; 2666 static const unsigned int msiof1_sync_a_mux[] = { 2667 MSIOF1_SYNC_A_MARK, 2668 }; 2669 static const unsigned int msiof1_ss1_a_pins[] = { 2670 /* SS1 */ 2671 RCAR_GP_PIN(6, 5), 2672 }; 2673 static const unsigned int msiof1_ss1_a_mux[] = { 2674 MSIOF1_SS1_A_MARK, 2675 }; 2676 static const unsigned int msiof1_ss2_a_pins[] = { 2677 /* SS2 */ 2678 RCAR_GP_PIN(6, 6), 2679 }; 2680 static const unsigned int msiof1_ss2_a_mux[] = { 2681 MSIOF1_SS2_A_MARK, 2682 }; 2683 static const unsigned int msiof1_txd_a_pins[] = { 2684 /* TXD */ 2685 RCAR_GP_PIN(6, 7), 2686 }; 2687 static const unsigned int msiof1_txd_a_mux[] = { 2688 MSIOF1_TXD_A_MARK, 2689 }; 2690 static const unsigned int msiof1_rxd_a_pins[] = { 2691 /* RXD */ 2692 RCAR_GP_PIN(6, 10), 2693 }; 2694 static const unsigned int msiof1_rxd_a_mux[] = { 2695 MSIOF1_RXD_A_MARK, 2696 }; 2697 static const unsigned int msiof1_clk_b_pins[] = { 2698 /* SCK */ 2699 RCAR_GP_PIN(5, 9), 2700 }; 2701 static const unsigned int msiof1_clk_b_mux[] = { 2702 MSIOF1_SCK_B_MARK, 2703 }; 2704 static const unsigned int msiof1_sync_b_pins[] = { 2705 /* SYNC */ 2706 RCAR_GP_PIN(5, 3), 2707 }; 2708 static const unsigned int msiof1_sync_b_mux[] = { 2709 MSIOF1_SYNC_B_MARK, 2710 }; 2711 static const unsigned int msiof1_ss1_b_pins[] = { 2712 /* SS1 */ 2713 RCAR_GP_PIN(5, 4), 2714 }; 2715 static const unsigned int msiof1_ss1_b_mux[] = { 2716 MSIOF1_SS1_B_MARK, 2717 }; 2718 static const unsigned int msiof1_ss2_b_pins[] = { 2719 /* SS2 */ 2720 RCAR_GP_PIN(5, 0), 2721 }; 2722 static const unsigned int msiof1_ss2_b_mux[] = { 2723 MSIOF1_SS2_B_MARK, 2724 }; 2725 static const unsigned int msiof1_txd_b_pins[] = { 2726 /* TXD */ 2727 RCAR_GP_PIN(5, 8), 2728 }; 2729 static const unsigned int msiof1_txd_b_mux[] = { 2730 MSIOF1_TXD_B_MARK, 2731 }; 2732 static const unsigned int msiof1_rxd_b_pins[] = { 2733 /* RXD */ 2734 RCAR_GP_PIN(5, 7), 2735 }; 2736 static const unsigned int msiof1_rxd_b_mux[] = { 2737 MSIOF1_RXD_B_MARK, 2738 }; 2739 static const unsigned int msiof1_clk_c_pins[] = { 2740 /* SCK */ 2741 RCAR_GP_PIN(6, 17), 2742 }; 2743 static const unsigned int msiof1_clk_c_mux[] = { 2744 MSIOF1_SCK_C_MARK, 2745 }; 2746 static const unsigned int msiof1_sync_c_pins[] = { 2747 /* SYNC */ 2748 RCAR_GP_PIN(6, 18), 2749 }; 2750 static const unsigned int msiof1_sync_c_mux[] = { 2751 MSIOF1_SYNC_C_MARK, 2752 }; 2753 static const unsigned int msiof1_ss1_c_pins[] = { 2754 /* SS1 */ 2755 RCAR_GP_PIN(6, 21), 2756 }; 2757 static const unsigned int msiof1_ss1_c_mux[] = { 2758 MSIOF1_SS1_C_MARK, 2759 }; 2760 static const unsigned int msiof1_ss2_c_pins[] = { 2761 /* SS2 */ 2762 RCAR_GP_PIN(6, 27), 2763 }; 2764 static const unsigned int msiof1_ss2_c_mux[] = { 2765 MSIOF1_SS2_C_MARK, 2766 }; 2767 static const unsigned int msiof1_txd_c_pins[] = { 2768 /* TXD */ 2769 RCAR_GP_PIN(6, 20), 2770 }; 2771 static const unsigned int msiof1_txd_c_mux[] = { 2772 MSIOF1_TXD_C_MARK, 2773 }; 2774 static const unsigned int msiof1_rxd_c_pins[] = { 2775 /* RXD */ 2776 RCAR_GP_PIN(6, 19), 2777 }; 2778 static const unsigned int msiof1_rxd_c_mux[] = { 2779 MSIOF1_RXD_C_MARK, 2780 }; 2781 static const unsigned int msiof1_clk_d_pins[] = { 2782 /* SCK */ 2783 RCAR_GP_PIN(5, 12), 2784 }; 2785 static const unsigned int msiof1_clk_d_mux[] = { 2786 MSIOF1_SCK_D_MARK, 2787 }; 2788 static const unsigned int msiof1_sync_d_pins[] = { 2789 /* SYNC */ 2790 RCAR_GP_PIN(5, 15), 2791 }; 2792 static const unsigned int msiof1_sync_d_mux[] = { 2793 MSIOF1_SYNC_D_MARK, 2794 }; 2795 static const unsigned int msiof1_ss1_d_pins[] = { 2796 /* SS1 */ 2797 RCAR_GP_PIN(5, 16), 2798 }; 2799 static const unsigned int msiof1_ss1_d_mux[] = { 2800 MSIOF1_SS1_D_MARK, 2801 }; 2802 static const unsigned int msiof1_ss2_d_pins[] = { 2803 /* SS2 */ 2804 RCAR_GP_PIN(5, 21), 2805 }; 2806 static const unsigned int msiof1_ss2_d_mux[] = { 2807 MSIOF1_SS2_D_MARK, 2808 }; 2809 static const unsigned int msiof1_txd_d_pins[] = { 2810 /* TXD */ 2811 RCAR_GP_PIN(5, 14), 2812 }; 2813 static const unsigned int msiof1_txd_d_mux[] = { 2814 MSIOF1_TXD_D_MARK, 2815 }; 2816 static const unsigned int msiof1_rxd_d_pins[] = { 2817 /* RXD */ 2818 RCAR_GP_PIN(5, 13), 2819 }; 2820 static const unsigned int msiof1_rxd_d_mux[] = { 2821 MSIOF1_RXD_D_MARK, 2822 }; 2823 static const unsigned int msiof1_clk_e_pins[] = { 2824 /* SCK */ 2825 RCAR_GP_PIN(3, 0), 2826 }; 2827 static const unsigned int msiof1_clk_e_mux[] = { 2828 MSIOF1_SCK_E_MARK, 2829 }; 2830 static const unsigned int msiof1_sync_e_pins[] = { 2831 /* SYNC */ 2832 RCAR_GP_PIN(3, 1), 2833 }; 2834 static const unsigned int msiof1_sync_e_mux[] = { 2835 MSIOF1_SYNC_E_MARK, 2836 }; 2837 static const unsigned int msiof1_ss1_e_pins[] = { 2838 /* SS1 */ 2839 RCAR_GP_PIN(3, 4), 2840 }; 2841 static const unsigned int msiof1_ss1_e_mux[] = { 2842 MSIOF1_SS1_E_MARK, 2843 }; 2844 static const unsigned int msiof1_ss2_e_pins[] = { 2845 /* SS2 */ 2846 RCAR_GP_PIN(3, 5), 2847 }; 2848 static const unsigned int msiof1_ss2_e_mux[] = { 2849 MSIOF1_SS2_E_MARK, 2850 }; 2851 static const unsigned int msiof1_txd_e_pins[] = { 2852 /* TXD */ 2853 RCAR_GP_PIN(3, 3), 2854 }; 2855 static const unsigned int msiof1_txd_e_mux[] = { 2856 MSIOF1_TXD_E_MARK, 2857 }; 2858 static const unsigned int msiof1_rxd_e_pins[] = { 2859 /* RXD */ 2860 RCAR_GP_PIN(3, 2), 2861 }; 2862 static const unsigned int msiof1_rxd_e_mux[] = { 2863 MSIOF1_RXD_E_MARK, 2864 }; 2865 static const unsigned int msiof1_clk_f_pins[] = { 2866 /* SCK */ 2867 RCAR_GP_PIN(5, 23), 2868 }; 2869 static const unsigned int msiof1_clk_f_mux[] = { 2870 MSIOF1_SCK_F_MARK, 2871 }; 2872 static const unsigned int msiof1_sync_f_pins[] = { 2873 /* SYNC */ 2874 RCAR_GP_PIN(5, 24), 2875 }; 2876 static const unsigned int msiof1_sync_f_mux[] = { 2877 MSIOF1_SYNC_F_MARK, 2878 }; 2879 static const unsigned int msiof1_ss1_f_pins[] = { 2880 /* SS1 */ 2881 RCAR_GP_PIN(6, 1), 2882 }; 2883 static const unsigned int msiof1_ss1_f_mux[] = { 2884 MSIOF1_SS1_F_MARK, 2885 }; 2886 static const unsigned int msiof1_ss2_f_pins[] = { 2887 /* SS2 */ 2888 RCAR_GP_PIN(6, 2), 2889 }; 2890 static const unsigned int msiof1_ss2_f_mux[] = { 2891 MSIOF1_SS2_F_MARK, 2892 }; 2893 static const unsigned int msiof1_txd_f_pins[] = { 2894 /* TXD */ 2895 RCAR_GP_PIN(6, 0), 2896 }; 2897 static const unsigned int msiof1_txd_f_mux[] = { 2898 MSIOF1_TXD_F_MARK, 2899 }; 2900 static const unsigned int msiof1_rxd_f_pins[] = { 2901 /* RXD */ 2902 RCAR_GP_PIN(5, 25), 2903 }; 2904 static const unsigned int msiof1_rxd_f_mux[] = { 2905 MSIOF1_RXD_F_MARK, 2906 }; 2907 static const unsigned int msiof1_clk_g_pins[] = { 2908 /* SCK */ 2909 RCAR_GP_PIN(3, 6), 2910 }; 2911 static const unsigned int msiof1_clk_g_mux[] = { 2912 MSIOF1_SCK_G_MARK, 2913 }; 2914 static const unsigned int msiof1_sync_g_pins[] = { 2915 /* SYNC */ 2916 RCAR_GP_PIN(3, 7), 2917 }; 2918 static const unsigned int msiof1_sync_g_mux[] = { 2919 MSIOF1_SYNC_G_MARK, 2920 }; 2921 static const unsigned int msiof1_ss1_g_pins[] = { 2922 /* SS1 */ 2923 RCAR_GP_PIN(3, 10), 2924 }; 2925 static const unsigned int msiof1_ss1_g_mux[] = { 2926 MSIOF1_SS1_G_MARK, 2927 }; 2928 static const unsigned int msiof1_ss2_g_pins[] = { 2929 /* SS2 */ 2930 RCAR_GP_PIN(3, 11), 2931 }; 2932 static const unsigned int msiof1_ss2_g_mux[] = { 2933 MSIOF1_SS2_G_MARK, 2934 }; 2935 static const unsigned int msiof1_txd_g_pins[] = { 2936 /* TXD */ 2937 RCAR_GP_PIN(3, 9), 2938 }; 2939 static const unsigned int msiof1_txd_g_mux[] = { 2940 MSIOF1_TXD_G_MARK, 2941 }; 2942 static const unsigned int msiof1_rxd_g_pins[] = { 2943 /* RXD */ 2944 RCAR_GP_PIN(3, 8), 2945 }; 2946 static const unsigned int msiof1_rxd_g_mux[] = { 2947 MSIOF1_RXD_G_MARK, 2948 }; 2949 /* - MSIOF2 ----------------------------------------------------------------- */ 2950 static const unsigned int msiof2_clk_a_pins[] = { 2951 /* SCK */ 2952 RCAR_GP_PIN(1, 9), 2953 }; 2954 static const unsigned int msiof2_clk_a_mux[] = { 2955 MSIOF2_SCK_A_MARK, 2956 }; 2957 static const unsigned int msiof2_sync_a_pins[] = { 2958 /* SYNC */ 2959 RCAR_GP_PIN(1, 8), 2960 }; 2961 static const unsigned int msiof2_sync_a_mux[] = { 2962 MSIOF2_SYNC_A_MARK, 2963 }; 2964 static const unsigned int msiof2_ss1_a_pins[] = { 2965 /* SS1 */ 2966 RCAR_GP_PIN(1, 6), 2967 }; 2968 static const unsigned int msiof2_ss1_a_mux[] = { 2969 MSIOF2_SS1_A_MARK, 2970 }; 2971 static const unsigned int msiof2_ss2_a_pins[] = { 2972 /* SS2 */ 2973 RCAR_GP_PIN(1, 7), 2974 }; 2975 static const unsigned int msiof2_ss2_a_mux[] = { 2976 MSIOF2_SS2_A_MARK, 2977 }; 2978 static const unsigned int msiof2_txd_a_pins[] = { 2979 /* TXD */ 2980 RCAR_GP_PIN(1, 11), 2981 }; 2982 static const unsigned int msiof2_txd_a_mux[] = { 2983 MSIOF2_TXD_A_MARK, 2984 }; 2985 static const unsigned int msiof2_rxd_a_pins[] = { 2986 /* RXD */ 2987 RCAR_GP_PIN(1, 10), 2988 }; 2989 static const unsigned int msiof2_rxd_a_mux[] = { 2990 MSIOF2_RXD_A_MARK, 2991 }; 2992 static const unsigned int msiof2_clk_b_pins[] = { 2993 /* SCK */ 2994 RCAR_GP_PIN(0, 4), 2995 }; 2996 static const unsigned int msiof2_clk_b_mux[] = { 2997 MSIOF2_SCK_B_MARK, 2998 }; 2999 static const unsigned int msiof2_sync_b_pins[] = { 3000 /* SYNC */ 3001 RCAR_GP_PIN(0, 5), 3002 }; 3003 static const unsigned int msiof2_sync_b_mux[] = { 3004 MSIOF2_SYNC_B_MARK, 3005 }; 3006 static const unsigned int msiof2_ss1_b_pins[] = { 3007 /* SS1 */ 3008 RCAR_GP_PIN(0, 0), 3009 }; 3010 static const unsigned int msiof2_ss1_b_mux[] = { 3011 MSIOF2_SS1_B_MARK, 3012 }; 3013 static const unsigned int msiof2_ss2_b_pins[] = { 3014 /* SS2 */ 3015 RCAR_GP_PIN(0, 1), 3016 }; 3017 static const unsigned int msiof2_ss2_b_mux[] = { 3018 MSIOF2_SS2_B_MARK, 3019 }; 3020 static const unsigned int msiof2_txd_b_pins[] = { 3021 /* TXD */ 3022 RCAR_GP_PIN(0, 7), 3023 }; 3024 static const unsigned int msiof2_txd_b_mux[] = { 3025 MSIOF2_TXD_B_MARK, 3026 }; 3027 static const unsigned int msiof2_rxd_b_pins[] = { 3028 /* RXD */ 3029 RCAR_GP_PIN(0, 6), 3030 }; 3031 static const unsigned int msiof2_rxd_b_mux[] = { 3032 MSIOF2_RXD_B_MARK, 3033 }; 3034 static const unsigned int msiof2_clk_c_pins[] = { 3035 /* SCK */ 3036 RCAR_GP_PIN(2, 12), 3037 }; 3038 static const unsigned int msiof2_clk_c_mux[] = { 3039 MSIOF2_SCK_C_MARK, 3040 }; 3041 static const unsigned int msiof2_sync_c_pins[] = { 3042 /* SYNC */ 3043 RCAR_GP_PIN(2, 11), 3044 }; 3045 static const unsigned int msiof2_sync_c_mux[] = { 3046 MSIOF2_SYNC_C_MARK, 3047 }; 3048 static const unsigned int msiof2_ss1_c_pins[] = { 3049 /* SS1 */ 3050 RCAR_GP_PIN(2, 10), 3051 }; 3052 static const unsigned int msiof2_ss1_c_mux[] = { 3053 MSIOF2_SS1_C_MARK, 3054 }; 3055 static const unsigned int msiof2_ss2_c_pins[] = { 3056 /* SS2 */ 3057 RCAR_GP_PIN(2, 9), 3058 }; 3059 static const unsigned int msiof2_ss2_c_mux[] = { 3060 MSIOF2_SS2_C_MARK, 3061 }; 3062 static const unsigned int msiof2_txd_c_pins[] = { 3063 /* TXD */ 3064 RCAR_GP_PIN(2, 14), 3065 }; 3066 static const unsigned int msiof2_txd_c_mux[] = { 3067 MSIOF2_TXD_C_MARK, 3068 }; 3069 static const unsigned int msiof2_rxd_c_pins[] = { 3070 /* RXD */ 3071 RCAR_GP_PIN(2, 13), 3072 }; 3073 static const unsigned int msiof2_rxd_c_mux[] = { 3074 MSIOF2_RXD_C_MARK, 3075 }; 3076 static const unsigned int msiof2_clk_d_pins[] = { 3077 /* SCK */ 3078 RCAR_GP_PIN(0, 8), 3079 }; 3080 static const unsigned int msiof2_clk_d_mux[] = { 3081 MSIOF2_SCK_D_MARK, 3082 }; 3083 static const unsigned int msiof2_sync_d_pins[] = { 3084 /* SYNC */ 3085 RCAR_GP_PIN(0, 9), 3086 }; 3087 static const unsigned int msiof2_sync_d_mux[] = { 3088 MSIOF2_SYNC_D_MARK, 3089 }; 3090 static const unsigned int msiof2_ss1_d_pins[] = { 3091 /* SS1 */ 3092 RCAR_GP_PIN(0, 12), 3093 }; 3094 static const unsigned int msiof2_ss1_d_mux[] = { 3095 MSIOF2_SS1_D_MARK, 3096 }; 3097 static const unsigned int msiof2_ss2_d_pins[] = { 3098 /* SS2 */ 3099 RCAR_GP_PIN(0, 13), 3100 }; 3101 static const unsigned int msiof2_ss2_d_mux[] = { 3102 MSIOF2_SS2_D_MARK, 3103 }; 3104 static const unsigned int msiof2_txd_d_pins[] = { 3105 /* TXD */ 3106 RCAR_GP_PIN(0, 11), 3107 }; 3108 static const unsigned int msiof2_txd_d_mux[] = { 3109 MSIOF2_TXD_D_MARK, 3110 }; 3111 static const unsigned int msiof2_rxd_d_pins[] = { 3112 /* RXD */ 3113 RCAR_GP_PIN(0, 10), 3114 }; 3115 static const unsigned int msiof2_rxd_d_mux[] = { 3116 MSIOF2_RXD_D_MARK, 3117 }; 3118 /* - MSIOF3 ----------------------------------------------------------------- */ 3119 static const unsigned int msiof3_clk_a_pins[] = { 3120 /* SCK */ 3121 RCAR_GP_PIN(0, 0), 3122 }; 3123 static const unsigned int msiof3_clk_a_mux[] = { 3124 MSIOF3_SCK_A_MARK, 3125 }; 3126 static const unsigned int msiof3_sync_a_pins[] = { 3127 /* SYNC */ 3128 RCAR_GP_PIN(0, 1), 3129 }; 3130 static const unsigned int msiof3_sync_a_mux[] = { 3131 MSIOF3_SYNC_A_MARK, 3132 }; 3133 static const unsigned int msiof3_ss1_a_pins[] = { 3134 /* SS1 */ 3135 RCAR_GP_PIN(0, 14), 3136 }; 3137 static const unsigned int msiof3_ss1_a_mux[] = { 3138 MSIOF3_SS1_A_MARK, 3139 }; 3140 static const unsigned int msiof3_ss2_a_pins[] = { 3141 /* SS2 */ 3142 RCAR_GP_PIN(0, 15), 3143 }; 3144 static const unsigned int msiof3_ss2_a_mux[] = { 3145 MSIOF3_SS2_A_MARK, 3146 }; 3147 static const unsigned int msiof3_txd_a_pins[] = { 3148 /* TXD */ 3149 RCAR_GP_PIN(0, 3), 3150 }; 3151 static const unsigned int msiof3_txd_a_mux[] = { 3152 MSIOF3_TXD_A_MARK, 3153 }; 3154 static const unsigned int msiof3_rxd_a_pins[] = { 3155 /* RXD */ 3156 RCAR_GP_PIN(0, 2), 3157 }; 3158 static const unsigned int msiof3_rxd_a_mux[] = { 3159 MSIOF3_RXD_A_MARK, 3160 }; 3161 static const unsigned int msiof3_clk_b_pins[] = { 3162 /* SCK */ 3163 RCAR_GP_PIN(1, 2), 3164 }; 3165 static const unsigned int msiof3_clk_b_mux[] = { 3166 MSIOF3_SCK_B_MARK, 3167 }; 3168 static const unsigned int msiof3_sync_b_pins[] = { 3169 /* SYNC */ 3170 RCAR_GP_PIN(1, 0), 3171 }; 3172 static const unsigned int msiof3_sync_b_mux[] = { 3173 MSIOF3_SYNC_B_MARK, 3174 }; 3175 static const unsigned int msiof3_ss1_b_pins[] = { 3176 /* SS1 */ 3177 RCAR_GP_PIN(1, 4), 3178 }; 3179 static const unsigned int msiof3_ss1_b_mux[] = { 3180 MSIOF3_SS1_B_MARK, 3181 }; 3182 static const unsigned int msiof3_ss2_b_pins[] = { 3183 /* SS2 */ 3184 RCAR_GP_PIN(1, 5), 3185 }; 3186 static const unsigned int msiof3_ss2_b_mux[] = { 3187 MSIOF3_SS2_B_MARK, 3188 }; 3189 static const unsigned int msiof3_txd_b_pins[] = { 3190 /* TXD */ 3191 RCAR_GP_PIN(1, 1), 3192 }; 3193 static const unsigned int msiof3_txd_b_mux[] = { 3194 MSIOF3_TXD_B_MARK, 3195 }; 3196 static const unsigned int msiof3_rxd_b_pins[] = { 3197 /* RXD */ 3198 RCAR_GP_PIN(1, 3), 3199 }; 3200 static const unsigned int msiof3_rxd_b_mux[] = { 3201 MSIOF3_RXD_B_MARK, 3202 }; 3203 static const unsigned int msiof3_clk_c_pins[] = { 3204 /* SCK */ 3205 RCAR_GP_PIN(1, 12), 3206 }; 3207 static const unsigned int msiof3_clk_c_mux[] = { 3208 MSIOF3_SCK_C_MARK, 3209 }; 3210 static const unsigned int msiof3_sync_c_pins[] = { 3211 /* SYNC */ 3212 RCAR_GP_PIN(1, 13), 3213 }; 3214 static const unsigned int msiof3_sync_c_mux[] = { 3215 MSIOF3_SYNC_C_MARK, 3216 }; 3217 static const unsigned int msiof3_txd_c_pins[] = { 3218 /* TXD */ 3219 RCAR_GP_PIN(1, 15), 3220 }; 3221 static const unsigned int msiof3_txd_c_mux[] = { 3222 MSIOF3_TXD_C_MARK, 3223 }; 3224 static const unsigned int msiof3_rxd_c_pins[] = { 3225 /* RXD */ 3226 RCAR_GP_PIN(1, 14), 3227 }; 3228 static const unsigned int msiof3_rxd_c_mux[] = { 3229 MSIOF3_RXD_C_MARK, 3230 }; 3231 static const unsigned int msiof3_clk_d_pins[] = { 3232 /* SCK */ 3233 RCAR_GP_PIN(1, 22), 3234 }; 3235 static const unsigned int msiof3_clk_d_mux[] = { 3236 MSIOF3_SCK_D_MARK, 3237 }; 3238 static const unsigned int msiof3_sync_d_pins[] = { 3239 /* SYNC */ 3240 RCAR_GP_PIN(1, 23), 3241 }; 3242 static const unsigned int msiof3_sync_d_mux[] = { 3243 MSIOF3_SYNC_D_MARK, 3244 }; 3245 static const unsigned int msiof3_ss1_d_pins[] = { 3246 /* SS1 */ 3247 RCAR_GP_PIN(1, 26), 3248 }; 3249 static const unsigned int msiof3_ss1_d_mux[] = { 3250 MSIOF3_SS1_D_MARK, 3251 }; 3252 static const unsigned int msiof3_txd_d_pins[] = { 3253 /* TXD */ 3254 RCAR_GP_PIN(1, 25), 3255 }; 3256 static const unsigned int msiof3_txd_d_mux[] = { 3257 MSIOF3_TXD_D_MARK, 3258 }; 3259 static const unsigned int msiof3_rxd_d_pins[] = { 3260 /* RXD */ 3261 RCAR_GP_PIN(1, 24), 3262 }; 3263 static const unsigned int msiof3_rxd_d_mux[] = { 3264 MSIOF3_RXD_D_MARK, 3265 }; 3266 static const unsigned int msiof3_clk_e_pins[] = { 3267 /* SCK */ 3268 RCAR_GP_PIN(2, 3), 3269 }; 3270 static const unsigned int msiof3_clk_e_mux[] = { 3271 MSIOF3_SCK_E_MARK, 3272 }; 3273 static const unsigned int msiof3_sync_e_pins[] = { 3274 /* SYNC */ 3275 RCAR_GP_PIN(2, 2), 3276 }; 3277 static const unsigned int msiof3_sync_e_mux[] = { 3278 MSIOF3_SYNC_E_MARK, 3279 }; 3280 static const unsigned int msiof3_ss1_e_pins[] = { 3281 /* SS1 */ 3282 RCAR_GP_PIN(2, 1), 3283 }; 3284 static const unsigned int msiof3_ss1_e_mux[] = { 3285 MSIOF3_SS1_E_MARK, 3286 }; 3287 static const unsigned int msiof3_ss2_e_pins[] = { 3288 /* SS2 */ 3289 RCAR_GP_PIN(2, 0), 3290 }; 3291 static const unsigned int msiof3_ss2_e_mux[] = { 3292 MSIOF3_SS2_E_MARK, 3293 }; 3294 static const unsigned int msiof3_txd_e_pins[] = { 3295 /* TXD */ 3296 RCAR_GP_PIN(2, 5), 3297 }; 3298 static const unsigned int msiof3_txd_e_mux[] = { 3299 MSIOF3_TXD_E_MARK, 3300 }; 3301 static const unsigned int msiof3_rxd_e_pins[] = { 3302 /* RXD */ 3303 RCAR_GP_PIN(2, 4), 3304 }; 3305 static const unsigned int msiof3_rxd_e_mux[] = { 3306 MSIOF3_RXD_E_MARK, 3307 }; 3308 3309 /* - PWM0 --------------------------------------------------------------------*/ 3310 static const unsigned int pwm0_pins[] = { 3311 /* PWM */ 3312 RCAR_GP_PIN(2, 6), 3313 }; 3314 static const unsigned int pwm0_mux[] = { 3315 PWM0_MARK, 3316 }; 3317 /* - PWM1 --------------------------------------------------------------------*/ 3318 static const unsigned int pwm1_a_pins[] = { 3319 /* PWM */ 3320 RCAR_GP_PIN(2, 7), 3321 }; 3322 static const unsigned int pwm1_a_mux[] = { 3323 PWM1_A_MARK, 3324 }; 3325 static const unsigned int pwm1_b_pins[] = { 3326 /* PWM */ 3327 RCAR_GP_PIN(1, 8), 3328 }; 3329 static const unsigned int pwm1_b_mux[] = { 3330 PWM1_B_MARK, 3331 }; 3332 /* - PWM2 --------------------------------------------------------------------*/ 3333 static const unsigned int pwm2_a_pins[] = { 3334 /* PWM */ 3335 RCAR_GP_PIN(2, 8), 3336 }; 3337 static const unsigned int pwm2_a_mux[] = { 3338 PWM2_A_MARK, 3339 }; 3340 static const unsigned int pwm2_b_pins[] = { 3341 /* PWM */ 3342 RCAR_GP_PIN(1, 11), 3343 }; 3344 static const unsigned int pwm2_b_mux[] = { 3345 PWM2_B_MARK, 3346 }; 3347 /* - PWM3 --------------------------------------------------------------------*/ 3348 static const unsigned int pwm3_a_pins[] = { 3349 /* PWM */ 3350 RCAR_GP_PIN(1, 0), 3351 }; 3352 static const unsigned int pwm3_a_mux[] = { 3353 PWM3_A_MARK, 3354 }; 3355 static const unsigned int pwm3_b_pins[] = { 3356 /* PWM */ 3357 RCAR_GP_PIN(2, 2), 3358 }; 3359 static const unsigned int pwm3_b_mux[] = { 3360 PWM3_B_MARK, 3361 }; 3362 /* - PWM4 --------------------------------------------------------------------*/ 3363 static const unsigned int pwm4_a_pins[] = { 3364 /* PWM */ 3365 RCAR_GP_PIN(1, 1), 3366 }; 3367 static const unsigned int pwm4_a_mux[] = { 3368 PWM4_A_MARK, 3369 }; 3370 static const unsigned int pwm4_b_pins[] = { 3371 /* PWM */ 3372 RCAR_GP_PIN(2, 3), 3373 }; 3374 static const unsigned int pwm4_b_mux[] = { 3375 PWM4_B_MARK, 3376 }; 3377 /* - PWM5 --------------------------------------------------------------------*/ 3378 static const unsigned int pwm5_a_pins[] = { 3379 /* PWM */ 3380 RCAR_GP_PIN(1, 2), 3381 }; 3382 static const unsigned int pwm5_a_mux[] = { 3383 PWM5_A_MARK, 3384 }; 3385 static const unsigned int pwm5_b_pins[] = { 3386 /* PWM */ 3387 RCAR_GP_PIN(2, 4), 3388 }; 3389 static const unsigned int pwm5_b_mux[] = { 3390 PWM5_B_MARK, 3391 }; 3392 /* - PWM6 --------------------------------------------------------------------*/ 3393 static const unsigned int pwm6_a_pins[] = { 3394 /* PWM */ 3395 RCAR_GP_PIN(1, 3), 3396 }; 3397 static const unsigned int pwm6_a_mux[] = { 3398 PWM6_A_MARK, 3399 }; 3400 static const unsigned int pwm6_b_pins[] = { 3401 /* PWM */ 3402 RCAR_GP_PIN(2, 5), 3403 }; 3404 static const unsigned int pwm6_b_mux[] = { 3405 PWM6_B_MARK, 3406 }; 3407 3408 /* - SATA --------------------------------------------------------------------*/ 3409 static const unsigned int sata0_devslp_a_pins[] = { 3410 /* DEVSLP */ 3411 RCAR_GP_PIN(6, 16), 3412 }; 3413 3414 static const unsigned int sata0_devslp_a_mux[] = { 3415 SATA_DEVSLP_A_MARK, 3416 }; 3417 3418 static const unsigned int sata0_devslp_b_pins[] = { 3419 /* DEVSLP */ 3420 RCAR_GP_PIN(4, 6), 3421 }; 3422 3423 static const unsigned int sata0_devslp_b_mux[] = { 3424 SATA_DEVSLP_B_MARK, 3425 }; 3426 3427 /* - SCIF0 ------------------------------------------------------------------ */ 3428 static const unsigned int scif0_data_pins[] = { 3429 /* RX, TX */ 3430 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), 3431 }; 3432 static const unsigned int scif0_data_mux[] = { 3433 RX0_MARK, TX0_MARK, 3434 }; 3435 static const unsigned int scif0_clk_pins[] = { 3436 /* SCK */ 3437 RCAR_GP_PIN(5, 0), 3438 }; 3439 static const unsigned int scif0_clk_mux[] = { 3440 SCK0_MARK, 3441 }; 3442 static const unsigned int scif0_ctrl_pins[] = { 3443 /* RTS, CTS */ 3444 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3), 3445 }; 3446 static const unsigned int scif0_ctrl_mux[] = { 3447 RTS0_N_MARK, CTS0_N_MARK, 3448 }; 3449 /* - SCIF1 ------------------------------------------------------------------ */ 3450 static const unsigned int scif1_data_a_pins[] = { 3451 /* RX, TX */ 3452 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6), 3453 }; 3454 static const unsigned int scif1_data_a_mux[] = { 3455 RX1_A_MARK, TX1_A_MARK, 3456 }; 3457 static const unsigned int scif1_clk_pins[] = { 3458 /* SCK */ 3459 RCAR_GP_PIN(6, 21), 3460 }; 3461 static const unsigned int scif1_clk_mux[] = { 3462 SCK1_MARK, 3463 }; 3464 static const unsigned int scif1_ctrl_pins[] = { 3465 /* RTS, CTS */ 3466 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7), 3467 }; 3468 static const unsigned int scif1_ctrl_mux[] = { 3469 RTS1_N_MARK, CTS1_N_MARK, 3470 }; 3471 static const unsigned int scif1_data_b_pins[] = { 3472 /* RX, TX */ 3473 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25), 3474 }; 3475 static const unsigned int scif1_data_b_mux[] = { 3476 RX1_B_MARK, TX1_B_MARK, 3477 }; 3478 /* - SCIF2 ------------------------------------------------------------------ */ 3479 static const unsigned int scif2_data_a_pins[] = { 3480 /* RX, TX */ 3481 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10), 3482 }; 3483 static const unsigned int scif2_data_a_mux[] = { 3484 RX2_A_MARK, TX2_A_MARK, 3485 }; 3486 static const unsigned int scif2_clk_pins[] = { 3487 /* SCK */ 3488 RCAR_GP_PIN(5, 9), 3489 }; 3490 static const unsigned int scif2_clk_mux[] = { 3491 SCK2_MARK, 3492 }; 3493 static const unsigned int scif2_data_b_pins[] = { 3494 /* RX, TX */ 3495 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16), 3496 }; 3497 static const unsigned int scif2_data_b_mux[] = { 3498 RX2_B_MARK, TX2_B_MARK, 3499 }; 3500 /* - SCIF3 ------------------------------------------------------------------ */ 3501 static const unsigned int scif3_data_a_pins[] = { 3502 /* RX, TX */ 3503 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24), 3504 }; 3505 static const unsigned int scif3_data_a_mux[] = { 3506 RX3_A_MARK, TX3_A_MARK, 3507 }; 3508 static const unsigned int scif3_clk_pins[] = { 3509 /* SCK */ 3510 RCAR_GP_PIN(1, 22), 3511 }; 3512 static const unsigned int scif3_clk_mux[] = { 3513 SCK3_MARK, 3514 }; 3515 static const unsigned int scif3_ctrl_pins[] = { 3516 /* RTS, CTS */ 3517 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25), 3518 }; 3519 static const unsigned int scif3_ctrl_mux[] = { 3520 RTS3_N_MARK, CTS3_N_MARK, 3521 }; 3522 static const unsigned int scif3_data_b_pins[] = { 3523 /* RX, TX */ 3524 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), 3525 }; 3526 static const unsigned int scif3_data_b_mux[] = { 3527 RX3_B_MARK, TX3_B_MARK, 3528 }; 3529 /* - SCIF4 ------------------------------------------------------------------ */ 3530 static const unsigned int scif4_data_a_pins[] = { 3531 /* RX, TX */ 3532 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12), 3533 }; 3534 static const unsigned int scif4_data_a_mux[] = { 3535 RX4_A_MARK, TX4_A_MARK, 3536 }; 3537 static const unsigned int scif4_clk_a_pins[] = { 3538 /* SCK */ 3539 RCAR_GP_PIN(2, 10), 3540 }; 3541 static const unsigned int scif4_clk_a_mux[] = { 3542 SCK4_A_MARK, 3543 }; 3544 static const unsigned int scif4_ctrl_a_pins[] = { 3545 /* RTS, CTS */ 3546 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13), 3547 }; 3548 static const unsigned int scif4_ctrl_a_mux[] = { 3549 RTS4_N_A_MARK, CTS4_N_A_MARK, 3550 }; 3551 static const unsigned int scif4_data_b_pins[] = { 3552 /* RX, TX */ 3553 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 3554 }; 3555 static const unsigned int scif4_data_b_mux[] = { 3556 RX4_B_MARK, TX4_B_MARK, 3557 }; 3558 static const unsigned int scif4_clk_b_pins[] = { 3559 /* SCK */ 3560 RCAR_GP_PIN(1, 5), 3561 }; 3562 static const unsigned int scif4_clk_b_mux[] = { 3563 SCK4_B_MARK, 3564 }; 3565 static const unsigned int scif4_ctrl_b_pins[] = { 3566 /* RTS, CTS */ 3567 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9), 3568 }; 3569 static const unsigned int scif4_ctrl_b_mux[] = { 3570 RTS4_N_B_MARK, CTS4_N_B_MARK, 3571 }; 3572 static const unsigned int scif4_data_c_pins[] = { 3573 /* RX, TX */ 3574 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), 3575 }; 3576 static const unsigned int scif4_data_c_mux[] = { 3577 RX4_C_MARK, TX4_C_MARK, 3578 }; 3579 static const unsigned int scif4_clk_c_pins[] = { 3580 /* SCK */ 3581 RCAR_GP_PIN(0, 8), 3582 }; 3583 static const unsigned int scif4_clk_c_mux[] = { 3584 SCK4_C_MARK, 3585 }; 3586 static const unsigned int scif4_ctrl_c_pins[] = { 3587 /* RTS, CTS */ 3588 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), 3589 }; 3590 static const unsigned int scif4_ctrl_c_mux[] = { 3591 RTS4_N_C_MARK, CTS4_N_C_MARK, 3592 }; 3593 /* - SCIF5 ------------------------------------------------------------------ */ 3594 static const unsigned int scif5_data_a_pins[] = { 3595 /* RX, TX */ 3596 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21), 3597 }; 3598 static const unsigned int scif5_data_a_mux[] = { 3599 RX5_A_MARK, TX5_A_MARK, 3600 }; 3601 static const unsigned int scif5_clk_a_pins[] = { 3602 /* SCK */ 3603 RCAR_GP_PIN(6, 21), 3604 }; 3605 static const unsigned int scif5_clk_a_mux[] = { 3606 SCK5_A_MARK, 3607 }; 3608 static const unsigned int scif5_data_b_pins[] = { 3609 /* RX, TX */ 3610 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18), 3611 }; 3612 static const unsigned int scif5_data_b_mux[] = { 3613 RX5_B_MARK, TX5_B_MARK, 3614 }; 3615 static const unsigned int scif5_clk_b_pins[] = { 3616 /* SCK */ 3617 RCAR_GP_PIN(5, 0), 3618 }; 3619 static const unsigned int scif5_clk_b_mux[] = { 3620 SCK5_B_MARK, 3621 }; 3622 /* - SCIF Clock ------------------------------------------------------------- */ 3623 static const unsigned int scif_clk_a_pins[] = { 3624 /* SCIF_CLK */ 3625 RCAR_GP_PIN(6, 23), 3626 }; 3627 static const unsigned int scif_clk_a_mux[] = { 3628 SCIF_CLK_A_MARK, 3629 }; 3630 static const unsigned int scif_clk_b_pins[] = { 3631 /* SCIF_CLK */ 3632 RCAR_GP_PIN(5, 9), 3633 }; 3634 static const unsigned int scif_clk_b_mux[] = { 3635 SCIF_CLK_B_MARK, 3636 }; 3637 3638 /* - SDHI0 ------------------------------------------------------------------ */ 3639 static const unsigned int sdhi0_data1_pins[] = { 3640 /* D0 */ 3641 RCAR_GP_PIN(3, 2), 3642 }; 3643 3644 static const unsigned int sdhi0_data1_mux[] = { 3645 SD0_DAT0_MARK, 3646 }; 3647 3648 static const unsigned int sdhi0_data4_pins[] = { 3649 /* D[0:3] */ 3650 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), 3651 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), 3652 }; 3653 3654 static const unsigned int sdhi0_data4_mux[] = { 3655 SD0_DAT0_MARK, SD0_DAT1_MARK, 3656 SD0_DAT2_MARK, SD0_DAT3_MARK, 3657 }; 3658 3659 static const unsigned int sdhi0_ctrl_pins[] = { 3660 /* CLK, CMD */ 3661 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1), 3662 }; 3663 3664 static const unsigned int sdhi0_ctrl_mux[] = { 3665 SD0_CLK_MARK, SD0_CMD_MARK, 3666 }; 3667 3668 static const unsigned int sdhi0_cd_pins[] = { 3669 /* CD */ 3670 RCAR_GP_PIN(3, 12), 3671 }; 3672 3673 static const unsigned int sdhi0_cd_mux[] = { 3674 SD0_CD_MARK, 3675 }; 3676 3677 static const unsigned int sdhi0_wp_pins[] = { 3678 /* WP */ 3679 RCAR_GP_PIN(3, 13), 3680 }; 3681 3682 static const unsigned int sdhi0_wp_mux[] = { 3683 SD0_WP_MARK, 3684 }; 3685 3686 /* - SDHI1 ------------------------------------------------------------------ */ 3687 static const unsigned int sdhi1_data1_pins[] = { 3688 /* D0 */ 3689 RCAR_GP_PIN(3, 8), 3690 }; 3691 3692 static const unsigned int sdhi1_data1_mux[] = { 3693 SD1_DAT0_MARK, 3694 }; 3695 3696 static const unsigned int sdhi1_data4_pins[] = { 3697 /* D[0:3] */ 3698 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), 3699 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), 3700 }; 3701 3702 static const unsigned int sdhi1_data4_mux[] = { 3703 SD1_DAT0_MARK, SD1_DAT1_MARK, 3704 SD1_DAT2_MARK, SD1_DAT3_MARK, 3705 }; 3706 3707 static const unsigned int sdhi1_ctrl_pins[] = { 3708 /* CLK, CMD */ 3709 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), 3710 }; 3711 3712 static const unsigned int sdhi1_ctrl_mux[] = { 3713 SD1_CLK_MARK, SD1_CMD_MARK, 3714 }; 3715 3716 static const unsigned int sdhi1_cd_pins[] = { 3717 /* CD */ 3718 RCAR_GP_PIN(3, 14), 3719 }; 3720 3721 static const unsigned int sdhi1_cd_mux[] = { 3722 SD1_CD_MARK, 3723 }; 3724 3725 static const unsigned int sdhi1_wp_pins[] = { 3726 /* WP */ 3727 RCAR_GP_PIN(3, 15), 3728 }; 3729 3730 static const unsigned int sdhi1_wp_mux[] = { 3731 SD1_WP_MARK, 3732 }; 3733 3734 /* - SDHI2 ------------------------------------------------------------------ */ 3735 static const unsigned int sdhi2_data1_pins[] = { 3736 /* D0 */ 3737 RCAR_GP_PIN(4, 2), 3738 }; 3739 3740 static const unsigned int sdhi2_data1_mux[] = { 3741 SD2_DAT0_MARK, 3742 }; 3743 3744 static const unsigned int sdhi2_data4_pins[] = { 3745 /* D[0:3] */ 3746 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), 3747 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), 3748 }; 3749 3750 static const unsigned int sdhi2_data4_mux[] = { 3751 SD2_DAT0_MARK, SD2_DAT1_MARK, 3752 SD2_DAT2_MARK, SD2_DAT3_MARK, 3753 }; 3754 3755 static const unsigned int sdhi2_data8_pins[] = { 3756 /* D[0:7] */ 3757 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), 3758 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), 3759 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), 3760 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), 3761 }; 3762 3763 static const unsigned int sdhi2_data8_mux[] = { 3764 SD2_DAT0_MARK, SD2_DAT1_MARK, 3765 SD2_DAT2_MARK, SD2_DAT3_MARK, 3766 SD2_DAT4_MARK, SD2_DAT5_MARK, 3767 SD2_DAT6_MARK, SD2_DAT7_MARK, 3768 }; 3769 3770 static const unsigned int sdhi2_ctrl_pins[] = { 3771 /* CLK, CMD */ 3772 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1), 3773 }; 3774 3775 static const unsigned int sdhi2_ctrl_mux[] = { 3776 SD2_CLK_MARK, SD2_CMD_MARK, 3777 }; 3778 3779 static const unsigned int sdhi2_cd_a_pins[] = { 3780 /* CD */ 3781 RCAR_GP_PIN(4, 13), 3782 }; 3783 3784 static const unsigned int sdhi2_cd_a_mux[] = { 3785 SD2_CD_A_MARK, 3786 }; 3787 3788 static const unsigned int sdhi2_cd_b_pins[] = { 3789 /* CD */ 3790 RCAR_GP_PIN(5, 10), 3791 }; 3792 3793 static const unsigned int sdhi2_cd_b_mux[] = { 3794 SD2_CD_B_MARK, 3795 }; 3796 3797 static const unsigned int sdhi2_wp_a_pins[] = { 3798 /* WP */ 3799 RCAR_GP_PIN(4, 14), 3800 }; 3801 3802 static const unsigned int sdhi2_wp_a_mux[] = { 3803 SD2_WP_A_MARK, 3804 }; 3805 3806 static const unsigned int sdhi2_wp_b_pins[] = { 3807 /* WP */ 3808 RCAR_GP_PIN(5, 11), 3809 }; 3810 3811 static const unsigned int sdhi2_wp_b_mux[] = { 3812 SD2_WP_B_MARK, 3813 }; 3814 3815 static const unsigned int sdhi2_ds_pins[] = { 3816 /* DS */ 3817 RCAR_GP_PIN(4, 6), 3818 }; 3819 3820 static const unsigned int sdhi2_ds_mux[] = { 3821 SD2_DS_MARK, 3822 }; 3823 3824 /* - SDHI3 ------------------------------------------------------------------ */ 3825 static const unsigned int sdhi3_data1_pins[] = { 3826 /* D0 */ 3827 RCAR_GP_PIN(4, 9), 3828 }; 3829 3830 static const unsigned int sdhi3_data1_mux[] = { 3831 SD3_DAT0_MARK, 3832 }; 3833 3834 static const unsigned int sdhi3_data4_pins[] = { 3835 /* D[0:3] */ 3836 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10), 3837 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12), 3838 }; 3839 3840 static const unsigned int sdhi3_data4_mux[] = { 3841 SD3_DAT0_MARK, SD3_DAT1_MARK, 3842 SD3_DAT2_MARK, SD3_DAT3_MARK, 3843 }; 3844 3845 static const unsigned int sdhi3_data8_pins[] = { 3846 /* D[0:7] */ 3847 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10), 3848 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12), 3849 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14), 3850 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16), 3851 }; 3852 3853 static const unsigned int sdhi3_data8_mux[] = { 3854 SD3_DAT0_MARK, SD3_DAT1_MARK, 3855 SD3_DAT2_MARK, SD3_DAT3_MARK, 3856 SD3_DAT4_MARK, SD3_DAT5_MARK, 3857 SD3_DAT6_MARK, SD3_DAT7_MARK, 3858 }; 3859 3860 static const unsigned int sdhi3_ctrl_pins[] = { 3861 /* CLK, CMD */ 3862 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8), 3863 }; 3864 3865 static const unsigned int sdhi3_ctrl_mux[] = { 3866 SD3_CLK_MARK, SD3_CMD_MARK, 3867 }; 3868 3869 static const unsigned int sdhi3_cd_pins[] = { 3870 /* CD */ 3871 RCAR_GP_PIN(4, 15), 3872 }; 3873 3874 static const unsigned int sdhi3_cd_mux[] = { 3875 SD3_CD_MARK, 3876 }; 3877 3878 static const unsigned int sdhi3_wp_pins[] = { 3879 /* WP */ 3880 RCAR_GP_PIN(4, 16), 3881 }; 3882 3883 static const unsigned int sdhi3_wp_mux[] = { 3884 SD3_WP_MARK, 3885 }; 3886 3887 static const unsigned int sdhi3_ds_pins[] = { 3888 /* DS */ 3889 RCAR_GP_PIN(4, 17), 3890 }; 3891 3892 static const unsigned int sdhi3_ds_mux[] = { 3893 SD3_DS_MARK, 3894 }; 3895 3896 /* - SSI -------------------------------------------------------------------- */ 3897 static const unsigned int ssi0_data_pins[] = { 3898 /* SDATA */ 3899 RCAR_GP_PIN(6, 2), 3900 }; 3901 static const unsigned int ssi0_data_mux[] = { 3902 SSI_SDATA0_MARK, 3903 }; 3904 static const unsigned int ssi01239_ctrl_pins[] = { 3905 /* SCK, WS */ 3906 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1), 3907 }; 3908 static const unsigned int ssi01239_ctrl_mux[] = { 3909 SSI_SCK01239_MARK, SSI_WS01239_MARK, 3910 }; 3911 static const unsigned int ssi1_data_a_pins[] = { 3912 /* SDATA */ 3913 RCAR_GP_PIN(6, 3), 3914 }; 3915 static const unsigned int ssi1_data_a_mux[] = { 3916 SSI_SDATA1_A_MARK, 3917 }; 3918 static const unsigned int ssi1_data_b_pins[] = { 3919 /* SDATA */ 3920 RCAR_GP_PIN(5, 12), 3921 }; 3922 static const unsigned int ssi1_data_b_mux[] = { 3923 SSI_SDATA1_B_MARK, 3924 }; 3925 static const unsigned int ssi1_ctrl_a_pins[] = { 3926 /* SCK, WS */ 3927 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27), 3928 }; 3929 static const unsigned int ssi1_ctrl_a_mux[] = { 3930 SSI_SCK1_A_MARK, SSI_WS1_A_MARK, 3931 }; 3932 static const unsigned int ssi1_ctrl_b_pins[] = { 3933 /* SCK, WS */ 3934 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21), 3935 }; 3936 static const unsigned int ssi1_ctrl_b_mux[] = { 3937 SSI_SCK1_B_MARK, SSI_WS1_B_MARK, 3938 }; 3939 static const unsigned int ssi2_data_a_pins[] = { 3940 /* SDATA */ 3941 RCAR_GP_PIN(6, 4), 3942 }; 3943 static const unsigned int ssi2_data_a_mux[] = { 3944 SSI_SDATA2_A_MARK, 3945 }; 3946 static const unsigned int ssi2_data_b_pins[] = { 3947 /* SDATA */ 3948 RCAR_GP_PIN(5, 13), 3949 }; 3950 static const unsigned int ssi2_data_b_mux[] = { 3951 SSI_SDATA2_B_MARK, 3952 }; 3953 static const unsigned int ssi2_ctrl_a_pins[] = { 3954 /* SCK, WS */ 3955 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21), 3956 }; 3957 static const unsigned int ssi2_ctrl_a_mux[] = { 3958 SSI_SCK2_A_MARK, SSI_WS2_A_MARK, 3959 }; 3960 static const unsigned int ssi2_ctrl_b_pins[] = { 3961 /* SCK, WS */ 3962 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29), 3963 }; 3964 static const unsigned int ssi2_ctrl_b_mux[] = { 3965 SSI_SCK2_B_MARK, SSI_WS2_B_MARK, 3966 }; 3967 static const unsigned int ssi3_data_pins[] = { 3968 /* SDATA */ 3969 RCAR_GP_PIN(6, 7), 3970 }; 3971 static const unsigned int ssi3_data_mux[] = { 3972 SSI_SDATA3_MARK, 3973 }; 3974 static const unsigned int ssi349_ctrl_pins[] = { 3975 /* SCK, WS */ 3976 RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6), 3977 }; 3978 static const unsigned int ssi349_ctrl_mux[] = { 3979 SSI_SCK349_MARK, SSI_WS349_MARK, 3980 }; 3981 static const unsigned int ssi4_data_pins[] = { 3982 /* SDATA */ 3983 RCAR_GP_PIN(6, 10), 3984 }; 3985 static const unsigned int ssi4_data_mux[] = { 3986 SSI_SDATA4_MARK, 3987 }; 3988 static const unsigned int ssi4_ctrl_pins[] = { 3989 /* SCK, WS */ 3990 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), 3991 }; 3992 static const unsigned int ssi4_ctrl_mux[] = { 3993 SSI_SCK4_MARK, SSI_WS4_MARK, 3994 }; 3995 static const unsigned int ssi5_data_pins[] = { 3996 /* SDATA */ 3997 RCAR_GP_PIN(6, 13), 3998 }; 3999 static const unsigned int ssi5_data_mux[] = { 4000 SSI_SDATA5_MARK, 4001 }; 4002 static const unsigned int ssi5_ctrl_pins[] = { 4003 /* SCK, WS */ 4004 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12), 4005 }; 4006 static const unsigned int ssi5_ctrl_mux[] = { 4007 SSI_SCK5_MARK, SSI_WS5_MARK, 4008 }; 4009 static const unsigned int ssi6_data_pins[] = { 4010 /* SDATA */ 4011 RCAR_GP_PIN(6, 16), 4012 }; 4013 static const unsigned int ssi6_data_mux[] = { 4014 SSI_SDATA6_MARK, 4015 }; 4016 static const unsigned int ssi6_ctrl_pins[] = { 4017 /* SCK, WS */ 4018 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15), 4019 }; 4020 static const unsigned int ssi6_ctrl_mux[] = { 4021 SSI_SCK6_MARK, SSI_WS6_MARK, 4022 }; 4023 static const unsigned int ssi7_data_pins[] = { 4024 /* SDATA */ 4025 RCAR_GP_PIN(6, 19), 4026 }; 4027 static const unsigned int ssi7_data_mux[] = { 4028 SSI_SDATA7_MARK, 4029 }; 4030 static const unsigned int ssi78_ctrl_pins[] = { 4031 /* SCK, WS */ 4032 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18), 4033 }; 4034 static const unsigned int ssi78_ctrl_mux[] = { 4035 SSI_SCK78_MARK, SSI_WS78_MARK, 4036 }; 4037 static const unsigned int ssi8_data_pins[] = { 4038 /* SDATA */ 4039 RCAR_GP_PIN(6, 20), 4040 }; 4041 static const unsigned int ssi8_data_mux[] = { 4042 SSI_SDATA8_MARK, 4043 }; 4044 static const unsigned int ssi9_data_a_pins[] = { 4045 /* SDATA */ 4046 RCAR_GP_PIN(6, 21), 4047 }; 4048 static const unsigned int ssi9_data_a_mux[] = { 4049 SSI_SDATA9_A_MARK, 4050 }; 4051 static const unsigned int ssi9_data_b_pins[] = { 4052 /* SDATA */ 4053 RCAR_GP_PIN(5, 14), 4054 }; 4055 static const unsigned int ssi9_data_b_mux[] = { 4056 SSI_SDATA9_B_MARK, 4057 }; 4058 static const unsigned int ssi9_ctrl_a_pins[] = { 4059 /* SCK, WS */ 4060 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16), 4061 }; 4062 static const unsigned int ssi9_ctrl_a_mux[] = { 4063 SSI_SCK9_A_MARK, SSI_WS9_A_MARK, 4064 }; 4065 static const unsigned int ssi9_ctrl_b_pins[] = { 4066 /* SCK, WS */ 4067 RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31), 4068 }; 4069 static const unsigned int ssi9_ctrl_b_mux[] = { 4070 SSI_SCK9_B_MARK, SSI_WS9_B_MARK, 4071 }; 4072 4073 /* - TMU -------------------------------------------------------------------- */ 4074 static const unsigned int tmu_tclk1_a_pins[] = { 4075 /* TCLK */ 4076 RCAR_GP_PIN(6, 23), 4077 }; 4078 4079 static const unsigned int tmu_tclk1_a_mux[] = { 4080 TCLK1_A_MARK, 4081 }; 4082 4083 static const unsigned int tmu_tclk1_b_pins[] = { 4084 /* TCLK */ 4085 RCAR_GP_PIN(5, 19), 4086 }; 4087 4088 static const unsigned int tmu_tclk1_b_mux[] = { 4089 TCLK1_B_MARK, 4090 }; 4091 4092 static const unsigned int tmu_tclk2_a_pins[] = { 4093 /* TCLK */ 4094 RCAR_GP_PIN(6, 19), 4095 }; 4096 4097 static const unsigned int tmu_tclk2_a_mux[] = { 4098 TCLK2_A_MARK, 4099 }; 4100 4101 static const unsigned int tmu_tclk2_b_pins[] = { 4102 /* TCLK */ 4103 RCAR_GP_PIN(6, 28), 4104 }; 4105 4106 static const unsigned int tmu_tclk2_b_mux[] = { 4107 TCLK2_B_MARK, 4108 }; 4109 4110 /* - TPU ------------------------------------------------------------------- */ 4111 static const unsigned int tpu_to0_pins[] = { 4112 /* TPU0TO0 */ 4113 RCAR_GP_PIN(6, 28), 4114 }; 4115 static const unsigned int tpu_to0_mux[] = { 4116 TPU0TO0_MARK, 4117 }; 4118 static const unsigned int tpu_to1_pins[] = { 4119 /* TPU0TO1 */ 4120 RCAR_GP_PIN(6, 29), 4121 }; 4122 static const unsigned int tpu_to1_mux[] = { 4123 TPU0TO1_MARK, 4124 }; 4125 static const unsigned int tpu_to2_pins[] = { 4126 /* TPU0TO2 */ 4127 RCAR_GP_PIN(6, 30), 4128 }; 4129 static const unsigned int tpu_to2_mux[] = { 4130 TPU0TO2_MARK, 4131 }; 4132 static const unsigned int tpu_to3_pins[] = { 4133 /* TPU0TO3 */ 4134 RCAR_GP_PIN(6, 31), 4135 }; 4136 static const unsigned int tpu_to3_mux[] = { 4137 TPU0TO3_MARK, 4138 }; 4139 4140 /* - USB0 ------------------------------------------------------------------- */ 4141 static const unsigned int usb0_pins[] = { 4142 /* PWEN, OVC */ 4143 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25), 4144 }; 4145 4146 static const unsigned int usb0_mux[] = { 4147 USB0_PWEN_MARK, USB0_OVC_MARK, 4148 }; 4149 4150 /* - USB1 ------------------------------------------------------------------- */ 4151 static const unsigned int usb1_pins[] = { 4152 /* PWEN, OVC */ 4153 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27), 4154 }; 4155 4156 static const unsigned int usb1_mux[] = { 4157 USB1_PWEN_MARK, USB1_OVC_MARK, 4158 }; 4159 4160 /* - USB30 ------------------------------------------------------------------ */ 4161 static const unsigned int usb30_pins[] = { 4162 /* PWEN, OVC */ 4163 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29), 4164 }; 4165 4166 static const unsigned int usb30_mux[] = { 4167 USB30_PWEN_MARK, USB30_OVC_MARK, 4168 }; 4169 4170 /* - VIN4 ------------------------------------------------------------------- */ 4171 static const unsigned int vin4_data18_a_pins[] = { 4172 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), 4173 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), 4174 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), 4175 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), 4176 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), 4177 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 4178 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), 4179 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), 4180 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), 4181 }; 4182 4183 static const unsigned int vin4_data18_a_mux[] = { 4184 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK, 4185 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK, 4186 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK, 4187 VI4_DATA10_MARK, VI4_DATA11_MARK, 4188 VI4_DATA12_MARK, VI4_DATA13_MARK, 4189 VI4_DATA14_MARK, VI4_DATA15_MARK, 4190 VI4_DATA18_MARK, VI4_DATA19_MARK, 4191 VI4_DATA20_MARK, VI4_DATA21_MARK, 4192 VI4_DATA22_MARK, VI4_DATA23_MARK, 4193 }; 4194 4195 static const union vin_data vin4_data_a_pins = { 4196 .data24 = { 4197 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), 4198 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), 4199 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), 4200 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), 4201 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), 4202 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), 4203 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), 4204 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 4205 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), 4206 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), 4207 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), 4208 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), 4209 }, 4210 }; 4211 4212 static const union vin_data vin4_data_a_mux = { 4213 .data24 = { 4214 VI4_DATA0_A_MARK, VI4_DATA1_A_MARK, 4215 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK, 4216 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK, 4217 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK, 4218 VI4_DATA8_MARK, VI4_DATA9_MARK, 4219 VI4_DATA10_MARK, VI4_DATA11_MARK, 4220 VI4_DATA12_MARK, VI4_DATA13_MARK, 4221 VI4_DATA14_MARK, VI4_DATA15_MARK, 4222 VI4_DATA16_MARK, VI4_DATA17_MARK, 4223 VI4_DATA18_MARK, VI4_DATA19_MARK, 4224 VI4_DATA20_MARK, VI4_DATA21_MARK, 4225 VI4_DATA22_MARK, VI4_DATA23_MARK, 4226 }, 4227 }; 4228 4229 static const unsigned int vin4_data18_b_pins[] = { 4230 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), 4231 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), 4232 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), 4233 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), 4234 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), 4235 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 4236 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), 4237 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), 4238 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), 4239 }; 4240 4241 static const unsigned int vin4_data18_b_mux[] = { 4242 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK, 4243 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK, 4244 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK, 4245 VI4_DATA10_MARK, VI4_DATA11_MARK, 4246 VI4_DATA12_MARK, VI4_DATA13_MARK, 4247 VI4_DATA14_MARK, VI4_DATA15_MARK, 4248 VI4_DATA18_MARK, VI4_DATA19_MARK, 4249 VI4_DATA20_MARK, VI4_DATA21_MARK, 4250 VI4_DATA22_MARK, VI4_DATA23_MARK, 4251 }; 4252 4253 static const union vin_data vin4_data_b_pins = { 4254 .data24 = { 4255 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), 4256 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), 4257 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), 4258 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), 4259 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), 4260 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), 4261 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), 4262 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 4263 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), 4264 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), 4265 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), 4266 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), 4267 }, 4268 }; 4269 4270 static const union vin_data vin4_data_b_mux = { 4271 .data24 = { 4272 VI4_DATA0_B_MARK, VI4_DATA1_B_MARK, 4273 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK, 4274 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK, 4275 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK, 4276 VI4_DATA8_MARK, VI4_DATA9_MARK, 4277 VI4_DATA10_MARK, VI4_DATA11_MARK, 4278 VI4_DATA12_MARK, VI4_DATA13_MARK, 4279 VI4_DATA14_MARK, VI4_DATA15_MARK, 4280 VI4_DATA16_MARK, VI4_DATA17_MARK, 4281 VI4_DATA18_MARK, VI4_DATA19_MARK, 4282 VI4_DATA20_MARK, VI4_DATA21_MARK, 4283 VI4_DATA22_MARK, VI4_DATA23_MARK, 4284 }, 4285 }; 4286 4287 static const unsigned int vin4_sync_pins[] = { 4288 /* VSYNC_N, HSYNC_N */ 4289 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18), 4290 }; 4291 4292 static const unsigned int vin4_sync_mux[] = { 4293 VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK, 4294 }; 4295 4296 static const unsigned int vin4_field_pins[] = { 4297 RCAR_GP_PIN(1, 16), 4298 }; 4299 4300 static const unsigned int vin4_field_mux[] = { 4301 VI4_FIELD_MARK, 4302 }; 4303 4304 static const unsigned int vin4_clkenb_pins[] = { 4305 RCAR_GP_PIN(1, 19), 4306 }; 4307 4308 static const unsigned int vin4_clkenb_mux[] = { 4309 VI4_CLKENB_MARK, 4310 }; 4311 4312 static const unsigned int vin4_clk_pins[] = { 4313 RCAR_GP_PIN(1, 27), 4314 }; 4315 4316 static const unsigned int vin4_clk_mux[] = { 4317 VI4_CLK_MARK, 4318 }; 4319 4320 /* - VIN5 ------------------------------------------------------------------- */ 4321 static const union vin_data16 vin5_data_pins = { 4322 .data16 = { 4323 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), 4324 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), 4325 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), 4326 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), 4327 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), 4328 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), 4329 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), 4330 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 4331 }, 4332 }; 4333 4334 static const union vin_data16 vin5_data_mux = { 4335 .data16 = { 4336 VI5_DATA0_MARK, VI5_DATA1_MARK, 4337 VI5_DATA2_MARK, VI5_DATA3_MARK, 4338 VI5_DATA4_MARK, VI5_DATA5_MARK, 4339 VI5_DATA6_MARK, VI5_DATA7_MARK, 4340 VI5_DATA8_MARK, VI5_DATA9_MARK, 4341 VI5_DATA10_MARK, VI5_DATA11_MARK, 4342 VI5_DATA12_MARK, VI5_DATA13_MARK, 4343 VI5_DATA14_MARK, VI5_DATA15_MARK, 4344 }, 4345 }; 4346 4347 static const unsigned int vin5_sync_pins[] = { 4348 /* VSYNC_N, HSYNC_N */ 4349 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 10), 4350 }; 4351 4352 static const unsigned int vin5_sync_mux[] = { 4353 VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK, 4354 }; 4355 4356 static const unsigned int vin5_field_pins[] = { 4357 RCAR_GP_PIN(1, 11), 4358 }; 4359 4360 static const unsigned int vin5_field_mux[] = { 4361 VI5_FIELD_MARK, 4362 }; 4363 4364 static const unsigned int vin5_clkenb_pins[] = { 4365 RCAR_GP_PIN(1, 20), 4366 }; 4367 4368 static const unsigned int vin5_clkenb_mux[] = { 4369 VI5_CLKENB_MARK, 4370 }; 4371 4372 static const unsigned int vin5_clk_pins[] = { 4373 RCAR_GP_PIN(1, 21), 4374 }; 4375 4376 static const unsigned int vin5_clk_mux[] = { 4377 VI5_CLK_MARK, 4378 }; 4379 4380 static const struct { 4381 struct sh_pfc_pin_group common[318]; 4382 struct sh_pfc_pin_group automotive[30]; 4383 } pinmux_groups = { 4384 .common = { 4385 SH_PFC_PIN_GROUP(audio_clk_a_a), 4386 SH_PFC_PIN_GROUP(audio_clk_a_b), 4387 SH_PFC_PIN_GROUP(audio_clk_a_c), 4388 SH_PFC_PIN_GROUP(audio_clk_b_a), 4389 SH_PFC_PIN_GROUP(audio_clk_b_b), 4390 SH_PFC_PIN_GROUP(audio_clk_c_a), 4391 SH_PFC_PIN_GROUP(audio_clk_c_b), 4392 SH_PFC_PIN_GROUP(audio_clkout_a), 4393 SH_PFC_PIN_GROUP(audio_clkout_b), 4394 SH_PFC_PIN_GROUP(audio_clkout_c), 4395 SH_PFC_PIN_GROUP(audio_clkout_d), 4396 SH_PFC_PIN_GROUP(audio_clkout1_a), 4397 SH_PFC_PIN_GROUP(audio_clkout1_b), 4398 SH_PFC_PIN_GROUP(audio_clkout2_a), 4399 SH_PFC_PIN_GROUP(audio_clkout2_b), 4400 SH_PFC_PIN_GROUP(audio_clkout3_a), 4401 SH_PFC_PIN_GROUP(audio_clkout3_b), 4402 SH_PFC_PIN_GROUP(avb_link), 4403 SH_PFC_PIN_GROUP(avb_magic), 4404 SH_PFC_PIN_GROUP(avb_phy_int), 4405 SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio), /* Deprecated */ 4406 SH_PFC_PIN_GROUP(avb_mdio), 4407 SH_PFC_PIN_GROUP(avb_mii), 4408 SH_PFC_PIN_GROUP(avb_avtp_pps), 4409 SH_PFC_PIN_GROUP(avb_avtp_match_a), 4410 SH_PFC_PIN_GROUP(avb_avtp_capture_a), 4411 SH_PFC_PIN_GROUP(avb_avtp_match_b), 4412 SH_PFC_PIN_GROUP(avb_avtp_capture_b), 4413 SH_PFC_PIN_GROUP(can0_data_a), 4414 SH_PFC_PIN_GROUP(can0_data_b), 4415 SH_PFC_PIN_GROUP(can1_data), 4416 SH_PFC_PIN_GROUP(can_clk), 4417 SH_PFC_PIN_GROUP(canfd0_data_a), 4418 SH_PFC_PIN_GROUP(canfd0_data_b), 4419 SH_PFC_PIN_GROUP(canfd1_data), 4420 SH_PFC_PIN_GROUP(du_rgb666), 4421 SH_PFC_PIN_GROUP(du_rgb888), 4422 SH_PFC_PIN_GROUP(du_clk_out_0), 4423 SH_PFC_PIN_GROUP(du_clk_out_1), 4424 SH_PFC_PIN_GROUP(du_sync), 4425 SH_PFC_PIN_GROUP(du_oddf), 4426 SH_PFC_PIN_GROUP(du_cde), 4427 SH_PFC_PIN_GROUP(du_disp), 4428 SH_PFC_PIN_GROUP(hscif0_data), 4429 SH_PFC_PIN_GROUP(hscif0_clk), 4430 SH_PFC_PIN_GROUP(hscif0_ctrl), 4431 SH_PFC_PIN_GROUP(hscif1_data_a), 4432 SH_PFC_PIN_GROUP(hscif1_clk_a), 4433 SH_PFC_PIN_GROUP(hscif1_ctrl_a), 4434 SH_PFC_PIN_GROUP(hscif1_data_b), 4435 SH_PFC_PIN_GROUP(hscif1_clk_b), 4436 SH_PFC_PIN_GROUP(hscif1_ctrl_b), 4437 SH_PFC_PIN_GROUP(hscif2_data_a), 4438 SH_PFC_PIN_GROUP(hscif2_clk_a), 4439 SH_PFC_PIN_GROUP(hscif2_ctrl_a), 4440 SH_PFC_PIN_GROUP(hscif2_data_b), 4441 SH_PFC_PIN_GROUP(hscif2_clk_b), 4442 SH_PFC_PIN_GROUP(hscif2_ctrl_b), 4443 SH_PFC_PIN_GROUP(hscif2_data_c), 4444 SH_PFC_PIN_GROUP(hscif2_clk_c), 4445 SH_PFC_PIN_GROUP(hscif2_ctrl_c), 4446 SH_PFC_PIN_GROUP(hscif3_data_a), 4447 SH_PFC_PIN_GROUP(hscif3_clk), 4448 SH_PFC_PIN_GROUP(hscif3_ctrl), 4449 SH_PFC_PIN_GROUP(hscif3_data_b), 4450 SH_PFC_PIN_GROUP(hscif3_data_c), 4451 SH_PFC_PIN_GROUP(hscif3_data_d), 4452 SH_PFC_PIN_GROUP(hscif4_data_a), 4453 SH_PFC_PIN_GROUP(hscif4_clk), 4454 SH_PFC_PIN_GROUP(hscif4_ctrl), 4455 SH_PFC_PIN_GROUP(hscif4_data_b), 4456 SH_PFC_PIN_GROUP(i2c0), 4457 SH_PFC_PIN_GROUP(i2c1_a), 4458 SH_PFC_PIN_GROUP(i2c1_b), 4459 SH_PFC_PIN_GROUP(i2c2_a), 4460 SH_PFC_PIN_GROUP(i2c2_b), 4461 SH_PFC_PIN_GROUP(i2c3), 4462 SH_PFC_PIN_GROUP(i2c5), 4463 SH_PFC_PIN_GROUP(i2c6_a), 4464 SH_PFC_PIN_GROUP(i2c6_b), 4465 SH_PFC_PIN_GROUP(i2c6_c), 4466 SH_PFC_PIN_GROUP(intc_ex_irq0), 4467 SH_PFC_PIN_GROUP(intc_ex_irq1), 4468 SH_PFC_PIN_GROUP(intc_ex_irq2), 4469 SH_PFC_PIN_GROUP(intc_ex_irq3), 4470 SH_PFC_PIN_GROUP(intc_ex_irq4), 4471 SH_PFC_PIN_GROUP(intc_ex_irq5), 4472 SH_PFC_PIN_GROUP(msiof0_clk), 4473 SH_PFC_PIN_GROUP(msiof0_sync), 4474 SH_PFC_PIN_GROUP(msiof0_ss1), 4475 SH_PFC_PIN_GROUP(msiof0_ss2), 4476 SH_PFC_PIN_GROUP(msiof0_txd), 4477 SH_PFC_PIN_GROUP(msiof0_rxd), 4478 SH_PFC_PIN_GROUP(msiof1_clk_a), 4479 SH_PFC_PIN_GROUP(msiof1_sync_a), 4480 SH_PFC_PIN_GROUP(msiof1_ss1_a), 4481 SH_PFC_PIN_GROUP(msiof1_ss2_a), 4482 SH_PFC_PIN_GROUP(msiof1_txd_a), 4483 SH_PFC_PIN_GROUP(msiof1_rxd_a), 4484 SH_PFC_PIN_GROUP(msiof1_clk_b), 4485 SH_PFC_PIN_GROUP(msiof1_sync_b), 4486 SH_PFC_PIN_GROUP(msiof1_ss1_b), 4487 SH_PFC_PIN_GROUP(msiof1_ss2_b), 4488 SH_PFC_PIN_GROUP(msiof1_txd_b), 4489 SH_PFC_PIN_GROUP(msiof1_rxd_b), 4490 SH_PFC_PIN_GROUP(msiof1_clk_c), 4491 SH_PFC_PIN_GROUP(msiof1_sync_c), 4492 SH_PFC_PIN_GROUP(msiof1_ss1_c), 4493 SH_PFC_PIN_GROUP(msiof1_ss2_c), 4494 SH_PFC_PIN_GROUP(msiof1_txd_c), 4495 SH_PFC_PIN_GROUP(msiof1_rxd_c), 4496 SH_PFC_PIN_GROUP(msiof1_clk_d), 4497 SH_PFC_PIN_GROUP(msiof1_sync_d), 4498 SH_PFC_PIN_GROUP(msiof1_ss1_d), 4499 SH_PFC_PIN_GROUP(msiof1_ss2_d), 4500 SH_PFC_PIN_GROUP(msiof1_txd_d), 4501 SH_PFC_PIN_GROUP(msiof1_rxd_d), 4502 SH_PFC_PIN_GROUP(msiof1_clk_e), 4503 SH_PFC_PIN_GROUP(msiof1_sync_e), 4504 SH_PFC_PIN_GROUP(msiof1_ss1_e), 4505 SH_PFC_PIN_GROUP(msiof1_ss2_e), 4506 SH_PFC_PIN_GROUP(msiof1_txd_e), 4507 SH_PFC_PIN_GROUP(msiof1_rxd_e), 4508 SH_PFC_PIN_GROUP(msiof1_clk_f), 4509 SH_PFC_PIN_GROUP(msiof1_sync_f), 4510 SH_PFC_PIN_GROUP(msiof1_ss1_f), 4511 SH_PFC_PIN_GROUP(msiof1_ss2_f), 4512 SH_PFC_PIN_GROUP(msiof1_txd_f), 4513 SH_PFC_PIN_GROUP(msiof1_rxd_f), 4514 SH_PFC_PIN_GROUP(msiof1_clk_g), 4515 SH_PFC_PIN_GROUP(msiof1_sync_g), 4516 SH_PFC_PIN_GROUP(msiof1_ss1_g), 4517 SH_PFC_PIN_GROUP(msiof1_ss2_g), 4518 SH_PFC_PIN_GROUP(msiof1_txd_g), 4519 SH_PFC_PIN_GROUP(msiof1_rxd_g), 4520 SH_PFC_PIN_GROUP(msiof2_clk_a), 4521 SH_PFC_PIN_GROUP(msiof2_sync_a), 4522 SH_PFC_PIN_GROUP(msiof2_ss1_a), 4523 SH_PFC_PIN_GROUP(msiof2_ss2_a), 4524 SH_PFC_PIN_GROUP(msiof2_txd_a), 4525 SH_PFC_PIN_GROUP(msiof2_rxd_a), 4526 SH_PFC_PIN_GROUP(msiof2_clk_b), 4527 SH_PFC_PIN_GROUP(msiof2_sync_b), 4528 SH_PFC_PIN_GROUP(msiof2_ss1_b), 4529 SH_PFC_PIN_GROUP(msiof2_ss2_b), 4530 SH_PFC_PIN_GROUP(msiof2_txd_b), 4531 SH_PFC_PIN_GROUP(msiof2_rxd_b), 4532 SH_PFC_PIN_GROUP(msiof2_clk_c), 4533 SH_PFC_PIN_GROUP(msiof2_sync_c), 4534 SH_PFC_PIN_GROUP(msiof2_ss1_c), 4535 SH_PFC_PIN_GROUP(msiof2_ss2_c), 4536 SH_PFC_PIN_GROUP(msiof2_txd_c), 4537 SH_PFC_PIN_GROUP(msiof2_rxd_c), 4538 SH_PFC_PIN_GROUP(msiof2_clk_d), 4539 SH_PFC_PIN_GROUP(msiof2_sync_d), 4540 SH_PFC_PIN_GROUP(msiof2_ss1_d), 4541 SH_PFC_PIN_GROUP(msiof2_ss2_d), 4542 SH_PFC_PIN_GROUP(msiof2_txd_d), 4543 SH_PFC_PIN_GROUP(msiof2_rxd_d), 4544 SH_PFC_PIN_GROUP(msiof3_clk_a), 4545 SH_PFC_PIN_GROUP(msiof3_sync_a), 4546 SH_PFC_PIN_GROUP(msiof3_ss1_a), 4547 SH_PFC_PIN_GROUP(msiof3_ss2_a), 4548 SH_PFC_PIN_GROUP(msiof3_txd_a), 4549 SH_PFC_PIN_GROUP(msiof3_rxd_a), 4550 SH_PFC_PIN_GROUP(msiof3_clk_b), 4551 SH_PFC_PIN_GROUP(msiof3_sync_b), 4552 SH_PFC_PIN_GROUP(msiof3_ss1_b), 4553 SH_PFC_PIN_GROUP(msiof3_ss2_b), 4554 SH_PFC_PIN_GROUP(msiof3_txd_b), 4555 SH_PFC_PIN_GROUP(msiof3_rxd_b), 4556 SH_PFC_PIN_GROUP(msiof3_clk_c), 4557 SH_PFC_PIN_GROUP(msiof3_sync_c), 4558 SH_PFC_PIN_GROUP(msiof3_txd_c), 4559 SH_PFC_PIN_GROUP(msiof3_rxd_c), 4560 SH_PFC_PIN_GROUP(msiof3_clk_d), 4561 SH_PFC_PIN_GROUP(msiof3_sync_d), 4562 SH_PFC_PIN_GROUP(msiof3_ss1_d), 4563 SH_PFC_PIN_GROUP(msiof3_txd_d), 4564 SH_PFC_PIN_GROUP(msiof3_rxd_d), 4565 SH_PFC_PIN_GROUP(msiof3_clk_e), 4566 SH_PFC_PIN_GROUP(msiof3_sync_e), 4567 SH_PFC_PIN_GROUP(msiof3_ss1_e), 4568 SH_PFC_PIN_GROUP(msiof3_ss2_e), 4569 SH_PFC_PIN_GROUP(msiof3_txd_e), 4570 SH_PFC_PIN_GROUP(msiof3_rxd_e), 4571 SH_PFC_PIN_GROUP(pwm0), 4572 SH_PFC_PIN_GROUP(pwm1_a), 4573 SH_PFC_PIN_GROUP(pwm1_b), 4574 SH_PFC_PIN_GROUP(pwm2_a), 4575 SH_PFC_PIN_GROUP(pwm2_b), 4576 SH_PFC_PIN_GROUP(pwm3_a), 4577 SH_PFC_PIN_GROUP(pwm3_b), 4578 SH_PFC_PIN_GROUP(pwm4_a), 4579 SH_PFC_PIN_GROUP(pwm4_b), 4580 SH_PFC_PIN_GROUP(pwm5_a), 4581 SH_PFC_PIN_GROUP(pwm5_b), 4582 SH_PFC_PIN_GROUP(pwm6_a), 4583 SH_PFC_PIN_GROUP(pwm6_b), 4584 SH_PFC_PIN_GROUP(sata0_devslp_a), 4585 SH_PFC_PIN_GROUP(sata0_devslp_b), 4586 SH_PFC_PIN_GROUP(scif0_data), 4587 SH_PFC_PIN_GROUP(scif0_clk), 4588 SH_PFC_PIN_GROUP(scif0_ctrl), 4589 SH_PFC_PIN_GROUP(scif1_data_a), 4590 SH_PFC_PIN_GROUP(scif1_clk), 4591 SH_PFC_PIN_GROUP(scif1_ctrl), 4592 SH_PFC_PIN_GROUP(scif1_data_b), 4593 SH_PFC_PIN_GROUP(scif2_data_a), 4594 SH_PFC_PIN_GROUP(scif2_clk), 4595 SH_PFC_PIN_GROUP(scif2_data_b), 4596 SH_PFC_PIN_GROUP(scif3_data_a), 4597 SH_PFC_PIN_GROUP(scif3_clk), 4598 SH_PFC_PIN_GROUP(scif3_ctrl), 4599 SH_PFC_PIN_GROUP(scif3_data_b), 4600 SH_PFC_PIN_GROUP(scif4_data_a), 4601 SH_PFC_PIN_GROUP(scif4_clk_a), 4602 SH_PFC_PIN_GROUP(scif4_ctrl_a), 4603 SH_PFC_PIN_GROUP(scif4_data_b), 4604 SH_PFC_PIN_GROUP(scif4_clk_b), 4605 SH_PFC_PIN_GROUP(scif4_ctrl_b), 4606 SH_PFC_PIN_GROUP(scif4_data_c), 4607 SH_PFC_PIN_GROUP(scif4_clk_c), 4608 SH_PFC_PIN_GROUP(scif4_ctrl_c), 4609 SH_PFC_PIN_GROUP(scif5_data_a), 4610 SH_PFC_PIN_GROUP(scif5_clk_a), 4611 SH_PFC_PIN_GROUP(scif5_data_b), 4612 SH_PFC_PIN_GROUP(scif5_clk_b), 4613 SH_PFC_PIN_GROUP(scif_clk_a), 4614 SH_PFC_PIN_GROUP(scif_clk_b), 4615 SH_PFC_PIN_GROUP(sdhi0_data1), 4616 SH_PFC_PIN_GROUP(sdhi0_data4), 4617 SH_PFC_PIN_GROUP(sdhi0_ctrl), 4618 SH_PFC_PIN_GROUP(sdhi0_cd), 4619 SH_PFC_PIN_GROUP(sdhi0_wp), 4620 SH_PFC_PIN_GROUP(sdhi1_data1), 4621 SH_PFC_PIN_GROUP(sdhi1_data4), 4622 SH_PFC_PIN_GROUP(sdhi1_ctrl), 4623 SH_PFC_PIN_GROUP(sdhi1_cd), 4624 SH_PFC_PIN_GROUP(sdhi1_wp), 4625 SH_PFC_PIN_GROUP(sdhi2_data1), 4626 SH_PFC_PIN_GROUP(sdhi2_data4), 4627 SH_PFC_PIN_GROUP(sdhi2_data8), 4628 SH_PFC_PIN_GROUP(sdhi2_ctrl), 4629 SH_PFC_PIN_GROUP(sdhi2_cd_a), 4630 SH_PFC_PIN_GROUP(sdhi2_wp_a), 4631 SH_PFC_PIN_GROUP(sdhi2_cd_b), 4632 SH_PFC_PIN_GROUP(sdhi2_wp_b), 4633 SH_PFC_PIN_GROUP(sdhi2_ds), 4634 SH_PFC_PIN_GROUP(sdhi3_data1), 4635 SH_PFC_PIN_GROUP(sdhi3_data4), 4636 SH_PFC_PIN_GROUP(sdhi3_data8), 4637 SH_PFC_PIN_GROUP(sdhi3_ctrl), 4638 SH_PFC_PIN_GROUP(sdhi3_cd), 4639 SH_PFC_PIN_GROUP(sdhi3_wp), 4640 SH_PFC_PIN_GROUP(sdhi3_ds), 4641 SH_PFC_PIN_GROUP(ssi0_data), 4642 SH_PFC_PIN_GROUP(ssi01239_ctrl), 4643 SH_PFC_PIN_GROUP(ssi1_data_a), 4644 SH_PFC_PIN_GROUP(ssi1_data_b), 4645 SH_PFC_PIN_GROUP(ssi1_ctrl_a), 4646 SH_PFC_PIN_GROUP(ssi1_ctrl_b), 4647 SH_PFC_PIN_GROUP(ssi2_data_a), 4648 SH_PFC_PIN_GROUP(ssi2_data_b), 4649 SH_PFC_PIN_GROUP(ssi2_ctrl_a), 4650 SH_PFC_PIN_GROUP(ssi2_ctrl_b), 4651 SH_PFC_PIN_GROUP(ssi3_data), 4652 SH_PFC_PIN_GROUP(ssi349_ctrl), 4653 SH_PFC_PIN_GROUP(ssi4_data), 4654 SH_PFC_PIN_GROUP(ssi4_ctrl), 4655 SH_PFC_PIN_GROUP(ssi5_data), 4656 SH_PFC_PIN_GROUP(ssi5_ctrl), 4657 SH_PFC_PIN_GROUP(ssi6_data), 4658 SH_PFC_PIN_GROUP(ssi6_ctrl), 4659 SH_PFC_PIN_GROUP(ssi7_data), 4660 SH_PFC_PIN_GROUP(ssi78_ctrl), 4661 SH_PFC_PIN_GROUP(ssi8_data), 4662 SH_PFC_PIN_GROUP(ssi9_data_a), 4663 SH_PFC_PIN_GROUP(ssi9_data_b), 4664 SH_PFC_PIN_GROUP(ssi9_ctrl_a), 4665 SH_PFC_PIN_GROUP(ssi9_ctrl_b), 4666 SH_PFC_PIN_GROUP(tmu_tclk1_a), 4667 SH_PFC_PIN_GROUP(tmu_tclk1_b), 4668 SH_PFC_PIN_GROUP(tmu_tclk2_a), 4669 SH_PFC_PIN_GROUP(tmu_tclk2_b), 4670 SH_PFC_PIN_GROUP(tpu_to0), 4671 SH_PFC_PIN_GROUP(tpu_to1), 4672 SH_PFC_PIN_GROUP(tpu_to2), 4673 SH_PFC_PIN_GROUP(tpu_to3), 4674 SH_PFC_PIN_GROUP(usb0), 4675 SH_PFC_PIN_GROUP(usb1), 4676 SH_PFC_PIN_GROUP(usb30), 4677 VIN_DATA_PIN_GROUP(vin4_data, 8, _a), 4678 VIN_DATA_PIN_GROUP(vin4_data, 10, _a), 4679 VIN_DATA_PIN_GROUP(vin4_data, 12, _a), 4680 VIN_DATA_PIN_GROUP(vin4_data, 16, _a), 4681 SH_PFC_PIN_GROUP(vin4_data18_a), 4682 VIN_DATA_PIN_GROUP(vin4_data, 20, _a), 4683 VIN_DATA_PIN_GROUP(vin4_data, 24, _a), 4684 VIN_DATA_PIN_GROUP(vin4_data, 8, _b), 4685 VIN_DATA_PIN_GROUP(vin4_data, 10, _b), 4686 VIN_DATA_PIN_GROUP(vin4_data, 12, _b), 4687 VIN_DATA_PIN_GROUP(vin4_data, 16, _b), 4688 SH_PFC_PIN_GROUP(vin4_data18_b), 4689 VIN_DATA_PIN_GROUP(vin4_data, 20, _b), 4690 VIN_DATA_PIN_GROUP(vin4_data, 24, _b), 4691 SH_PFC_PIN_GROUP(vin4_sync), 4692 SH_PFC_PIN_GROUP(vin4_field), 4693 SH_PFC_PIN_GROUP(vin4_clkenb), 4694 SH_PFC_PIN_GROUP(vin4_clk), 4695 VIN_DATA_PIN_GROUP(vin5_data, 8), 4696 VIN_DATA_PIN_GROUP(vin5_data, 10), 4697 VIN_DATA_PIN_GROUP(vin5_data, 12), 4698 VIN_DATA_PIN_GROUP(vin5_data, 16), 4699 SH_PFC_PIN_GROUP(vin5_sync), 4700 SH_PFC_PIN_GROUP(vin5_field), 4701 SH_PFC_PIN_GROUP(vin5_clkenb), 4702 SH_PFC_PIN_GROUP(vin5_clk), 4703 }, 4704 .automotive = { 4705 SH_PFC_PIN_GROUP(drif0_ctrl_a), 4706 SH_PFC_PIN_GROUP(drif0_data0_a), 4707 SH_PFC_PIN_GROUP(drif0_data1_a), 4708 SH_PFC_PIN_GROUP(drif0_ctrl_b), 4709 SH_PFC_PIN_GROUP(drif0_data0_b), 4710 SH_PFC_PIN_GROUP(drif0_data1_b), 4711 SH_PFC_PIN_GROUP(drif0_ctrl_c), 4712 SH_PFC_PIN_GROUP(drif0_data0_c), 4713 SH_PFC_PIN_GROUP(drif0_data1_c), 4714 SH_PFC_PIN_GROUP(drif1_ctrl_a), 4715 SH_PFC_PIN_GROUP(drif1_data0_a), 4716 SH_PFC_PIN_GROUP(drif1_data1_a), 4717 SH_PFC_PIN_GROUP(drif1_ctrl_b), 4718 SH_PFC_PIN_GROUP(drif1_data0_b), 4719 SH_PFC_PIN_GROUP(drif1_data1_b), 4720 SH_PFC_PIN_GROUP(drif1_ctrl_c), 4721 SH_PFC_PIN_GROUP(drif1_data0_c), 4722 SH_PFC_PIN_GROUP(drif1_data1_c), 4723 SH_PFC_PIN_GROUP(drif2_ctrl_a), 4724 SH_PFC_PIN_GROUP(drif2_data0_a), 4725 SH_PFC_PIN_GROUP(drif2_data1_a), 4726 SH_PFC_PIN_GROUP(drif2_ctrl_b), 4727 SH_PFC_PIN_GROUP(drif2_data0_b), 4728 SH_PFC_PIN_GROUP(drif2_data1_b), 4729 SH_PFC_PIN_GROUP(drif3_ctrl_a), 4730 SH_PFC_PIN_GROUP(drif3_data0_a), 4731 SH_PFC_PIN_GROUP(drif3_data1_a), 4732 SH_PFC_PIN_GROUP(drif3_ctrl_b), 4733 SH_PFC_PIN_GROUP(drif3_data0_b), 4734 SH_PFC_PIN_GROUP(drif3_data1_b), 4735 } 4736 }; 4737 4738 static const char * const audio_clk_groups[] = { 4739 "audio_clk_a_a", 4740 "audio_clk_a_b", 4741 "audio_clk_a_c", 4742 "audio_clk_b_a", 4743 "audio_clk_b_b", 4744 "audio_clk_c_a", 4745 "audio_clk_c_b", 4746 "audio_clkout_a", 4747 "audio_clkout_b", 4748 "audio_clkout_c", 4749 "audio_clkout_d", 4750 "audio_clkout1_a", 4751 "audio_clkout1_b", 4752 "audio_clkout2_a", 4753 "audio_clkout2_b", 4754 "audio_clkout3_a", 4755 "audio_clkout3_b", 4756 }; 4757 4758 static const char * const avb_groups[] = { 4759 "avb_link", 4760 "avb_magic", 4761 "avb_phy_int", 4762 "avb_mdc", /* Deprecated, please use "avb_mdio" instead */ 4763 "avb_mdio", 4764 "avb_mii", 4765 "avb_avtp_pps", 4766 "avb_avtp_match_a", 4767 "avb_avtp_capture_a", 4768 "avb_avtp_match_b", 4769 "avb_avtp_capture_b", 4770 }; 4771 4772 static const char * const can0_groups[] = { 4773 "can0_data_a", 4774 "can0_data_b", 4775 }; 4776 4777 static const char * const can1_groups[] = { 4778 "can1_data", 4779 }; 4780 4781 static const char * const can_clk_groups[] = { 4782 "can_clk", 4783 }; 4784 4785 static const char * const canfd0_groups[] = { 4786 "canfd0_data_a", 4787 "canfd0_data_b", 4788 }; 4789 4790 static const char * const canfd1_groups[] = { 4791 "canfd1_data", 4792 }; 4793 4794 static const char * const drif0_groups[] = { 4795 "drif0_ctrl_a", 4796 "drif0_data0_a", 4797 "drif0_data1_a", 4798 "drif0_ctrl_b", 4799 "drif0_data0_b", 4800 "drif0_data1_b", 4801 "drif0_ctrl_c", 4802 "drif0_data0_c", 4803 "drif0_data1_c", 4804 }; 4805 4806 static const char * const drif1_groups[] = { 4807 "drif1_ctrl_a", 4808 "drif1_data0_a", 4809 "drif1_data1_a", 4810 "drif1_ctrl_b", 4811 "drif1_data0_b", 4812 "drif1_data1_b", 4813 "drif1_ctrl_c", 4814 "drif1_data0_c", 4815 "drif1_data1_c", 4816 }; 4817 4818 static const char * const drif2_groups[] = { 4819 "drif2_ctrl_a", 4820 "drif2_data0_a", 4821 "drif2_data1_a", 4822 "drif2_ctrl_b", 4823 "drif2_data0_b", 4824 "drif2_data1_b", 4825 }; 4826 4827 static const char * const drif3_groups[] = { 4828 "drif3_ctrl_a", 4829 "drif3_data0_a", 4830 "drif3_data1_a", 4831 "drif3_ctrl_b", 4832 "drif3_data0_b", 4833 "drif3_data1_b", 4834 }; 4835 4836 static const char * const du_groups[] = { 4837 "du_rgb666", 4838 "du_rgb888", 4839 "du_clk_out_0", 4840 "du_clk_out_1", 4841 "du_sync", 4842 "du_oddf", 4843 "du_cde", 4844 "du_disp", 4845 }; 4846 4847 static const char * const hscif0_groups[] = { 4848 "hscif0_data", 4849 "hscif0_clk", 4850 "hscif0_ctrl", 4851 }; 4852 4853 static const char * const hscif1_groups[] = { 4854 "hscif1_data_a", 4855 "hscif1_clk_a", 4856 "hscif1_ctrl_a", 4857 "hscif1_data_b", 4858 "hscif1_clk_b", 4859 "hscif1_ctrl_b", 4860 }; 4861 4862 static const char * const hscif2_groups[] = { 4863 "hscif2_data_a", 4864 "hscif2_clk_a", 4865 "hscif2_ctrl_a", 4866 "hscif2_data_b", 4867 "hscif2_clk_b", 4868 "hscif2_ctrl_b", 4869 "hscif2_data_c", 4870 "hscif2_clk_c", 4871 "hscif2_ctrl_c", 4872 }; 4873 4874 static const char * const hscif3_groups[] = { 4875 "hscif3_data_a", 4876 "hscif3_clk", 4877 "hscif3_ctrl", 4878 "hscif3_data_b", 4879 "hscif3_data_c", 4880 "hscif3_data_d", 4881 }; 4882 4883 static const char * const hscif4_groups[] = { 4884 "hscif4_data_a", 4885 "hscif4_clk", 4886 "hscif4_ctrl", 4887 "hscif4_data_b", 4888 }; 4889 4890 static const char * const i2c0_groups[] = { 4891 "i2c0", 4892 }; 4893 4894 static const char * const i2c1_groups[] = { 4895 "i2c1_a", 4896 "i2c1_b", 4897 }; 4898 4899 static const char * const i2c2_groups[] = { 4900 "i2c2_a", 4901 "i2c2_b", 4902 }; 4903 4904 static const char * const i2c3_groups[] = { 4905 "i2c3", 4906 }; 4907 4908 static const char * const i2c5_groups[] = { 4909 "i2c5", 4910 }; 4911 4912 static const char * const i2c6_groups[] = { 4913 "i2c6_a", 4914 "i2c6_b", 4915 "i2c6_c", 4916 }; 4917 4918 static const char * const intc_ex_groups[] = { 4919 "intc_ex_irq0", 4920 "intc_ex_irq1", 4921 "intc_ex_irq2", 4922 "intc_ex_irq3", 4923 "intc_ex_irq4", 4924 "intc_ex_irq5", 4925 }; 4926 4927 static const char * const msiof0_groups[] = { 4928 "msiof0_clk", 4929 "msiof0_sync", 4930 "msiof0_ss1", 4931 "msiof0_ss2", 4932 "msiof0_txd", 4933 "msiof0_rxd", 4934 }; 4935 4936 static const char * const msiof1_groups[] = { 4937 "msiof1_clk_a", 4938 "msiof1_sync_a", 4939 "msiof1_ss1_a", 4940 "msiof1_ss2_a", 4941 "msiof1_txd_a", 4942 "msiof1_rxd_a", 4943 "msiof1_clk_b", 4944 "msiof1_sync_b", 4945 "msiof1_ss1_b", 4946 "msiof1_ss2_b", 4947 "msiof1_txd_b", 4948 "msiof1_rxd_b", 4949 "msiof1_clk_c", 4950 "msiof1_sync_c", 4951 "msiof1_ss1_c", 4952 "msiof1_ss2_c", 4953 "msiof1_txd_c", 4954 "msiof1_rxd_c", 4955 "msiof1_clk_d", 4956 "msiof1_sync_d", 4957 "msiof1_ss1_d", 4958 "msiof1_ss2_d", 4959 "msiof1_txd_d", 4960 "msiof1_rxd_d", 4961 "msiof1_clk_e", 4962 "msiof1_sync_e", 4963 "msiof1_ss1_e", 4964 "msiof1_ss2_e", 4965 "msiof1_txd_e", 4966 "msiof1_rxd_e", 4967 "msiof1_clk_f", 4968 "msiof1_sync_f", 4969 "msiof1_ss1_f", 4970 "msiof1_ss2_f", 4971 "msiof1_txd_f", 4972 "msiof1_rxd_f", 4973 "msiof1_clk_g", 4974 "msiof1_sync_g", 4975 "msiof1_ss1_g", 4976 "msiof1_ss2_g", 4977 "msiof1_txd_g", 4978 "msiof1_rxd_g", 4979 }; 4980 4981 static const char * const msiof2_groups[] = { 4982 "msiof2_clk_a", 4983 "msiof2_sync_a", 4984 "msiof2_ss1_a", 4985 "msiof2_ss2_a", 4986 "msiof2_txd_a", 4987 "msiof2_rxd_a", 4988 "msiof2_clk_b", 4989 "msiof2_sync_b", 4990 "msiof2_ss1_b", 4991 "msiof2_ss2_b", 4992 "msiof2_txd_b", 4993 "msiof2_rxd_b", 4994 "msiof2_clk_c", 4995 "msiof2_sync_c", 4996 "msiof2_ss1_c", 4997 "msiof2_ss2_c", 4998 "msiof2_txd_c", 4999 "msiof2_rxd_c", 5000 "msiof2_clk_d", 5001 "msiof2_sync_d", 5002 "msiof2_ss1_d", 5003 "msiof2_ss2_d", 5004 "msiof2_txd_d", 5005 "msiof2_rxd_d", 5006 }; 5007 5008 static const char * const msiof3_groups[] = { 5009 "msiof3_clk_a", 5010 "msiof3_sync_a", 5011 "msiof3_ss1_a", 5012 "msiof3_ss2_a", 5013 "msiof3_txd_a", 5014 "msiof3_rxd_a", 5015 "msiof3_clk_b", 5016 "msiof3_sync_b", 5017 "msiof3_ss1_b", 5018 "msiof3_ss2_b", 5019 "msiof3_txd_b", 5020 "msiof3_rxd_b", 5021 "msiof3_clk_c", 5022 "msiof3_sync_c", 5023 "msiof3_txd_c", 5024 "msiof3_rxd_c", 5025 "msiof3_clk_d", 5026 "msiof3_sync_d", 5027 "msiof3_ss1_d", 5028 "msiof3_txd_d", 5029 "msiof3_rxd_d", 5030 "msiof3_clk_e", 5031 "msiof3_sync_e", 5032 "msiof3_ss1_e", 5033 "msiof3_ss2_e", 5034 "msiof3_txd_e", 5035 "msiof3_rxd_e", 5036 }; 5037 5038 static const char * const pwm0_groups[] = { 5039 "pwm0", 5040 }; 5041 5042 static const char * const pwm1_groups[] = { 5043 "pwm1_a", 5044 "pwm1_b", 5045 }; 5046 5047 static const char * const pwm2_groups[] = { 5048 "pwm2_a", 5049 "pwm2_b", 5050 }; 5051 5052 static const char * const pwm3_groups[] = { 5053 "pwm3_a", 5054 "pwm3_b", 5055 }; 5056 5057 static const char * const pwm4_groups[] = { 5058 "pwm4_a", 5059 "pwm4_b", 5060 }; 5061 5062 static const char * const pwm5_groups[] = { 5063 "pwm5_a", 5064 "pwm5_b", 5065 }; 5066 5067 static const char * const pwm6_groups[] = { 5068 "pwm6_a", 5069 "pwm6_b", 5070 }; 5071 5072 static const char * const sata0_groups[] = { 5073 "sata0_devslp_a", 5074 "sata0_devslp_b", 5075 }; 5076 5077 static const char * const scif0_groups[] = { 5078 "scif0_data", 5079 "scif0_clk", 5080 "scif0_ctrl", 5081 }; 5082 5083 static const char * const scif1_groups[] = { 5084 "scif1_data_a", 5085 "scif1_clk", 5086 "scif1_ctrl", 5087 "scif1_data_b", 5088 }; 5089 static const char * const scif2_groups[] = { 5090 "scif2_data_a", 5091 "scif2_clk", 5092 "scif2_data_b", 5093 }; 5094 5095 static const char * const scif3_groups[] = { 5096 "scif3_data_a", 5097 "scif3_clk", 5098 "scif3_ctrl", 5099 "scif3_data_b", 5100 }; 5101 5102 static const char * const scif4_groups[] = { 5103 "scif4_data_a", 5104 "scif4_clk_a", 5105 "scif4_ctrl_a", 5106 "scif4_data_b", 5107 "scif4_clk_b", 5108 "scif4_ctrl_b", 5109 "scif4_data_c", 5110 "scif4_clk_c", 5111 "scif4_ctrl_c", 5112 }; 5113 5114 static const char * const scif5_groups[] = { 5115 "scif5_data_a", 5116 "scif5_clk_a", 5117 "scif5_data_b", 5118 "scif5_clk_b", 5119 }; 5120 5121 static const char * const scif_clk_groups[] = { 5122 "scif_clk_a", 5123 "scif_clk_b", 5124 }; 5125 5126 static const char * const sdhi0_groups[] = { 5127 "sdhi0_data1", 5128 "sdhi0_data4", 5129 "sdhi0_ctrl", 5130 "sdhi0_cd", 5131 "sdhi0_wp", 5132 }; 5133 5134 static const char * const sdhi1_groups[] = { 5135 "sdhi1_data1", 5136 "sdhi1_data4", 5137 "sdhi1_ctrl", 5138 "sdhi1_cd", 5139 "sdhi1_wp", 5140 }; 5141 5142 static const char * const sdhi2_groups[] = { 5143 "sdhi2_data1", 5144 "sdhi2_data4", 5145 "sdhi2_data8", 5146 "sdhi2_ctrl", 5147 "sdhi2_cd_a", 5148 "sdhi2_wp_a", 5149 "sdhi2_cd_b", 5150 "sdhi2_wp_b", 5151 "sdhi2_ds", 5152 }; 5153 5154 static const char * const sdhi3_groups[] = { 5155 "sdhi3_data1", 5156 "sdhi3_data4", 5157 "sdhi3_data8", 5158 "sdhi3_ctrl", 5159 "sdhi3_cd", 5160 "sdhi3_wp", 5161 "sdhi3_ds", 5162 }; 5163 5164 static const char * const ssi_groups[] = { 5165 "ssi0_data", 5166 "ssi01239_ctrl", 5167 "ssi1_data_a", 5168 "ssi1_data_b", 5169 "ssi1_ctrl_a", 5170 "ssi1_ctrl_b", 5171 "ssi2_data_a", 5172 "ssi2_data_b", 5173 "ssi2_ctrl_a", 5174 "ssi2_ctrl_b", 5175 "ssi3_data", 5176 "ssi349_ctrl", 5177 "ssi4_data", 5178 "ssi4_ctrl", 5179 "ssi5_data", 5180 "ssi5_ctrl", 5181 "ssi6_data", 5182 "ssi6_ctrl", 5183 "ssi7_data", 5184 "ssi78_ctrl", 5185 "ssi8_data", 5186 "ssi9_data_a", 5187 "ssi9_data_b", 5188 "ssi9_ctrl_a", 5189 "ssi9_ctrl_b", 5190 }; 5191 5192 static const char * const tmu_groups[] = { 5193 "tmu_tclk1_a", 5194 "tmu_tclk1_b", 5195 "tmu_tclk2_a", 5196 "tmu_tclk2_b", 5197 }; 5198 5199 static const char * const tpu_groups[] = { 5200 "tpu_to0", 5201 "tpu_to1", 5202 "tpu_to2", 5203 "tpu_to3", 5204 }; 5205 5206 static const char * const usb0_groups[] = { 5207 "usb0", 5208 }; 5209 5210 static const char * const usb1_groups[] = { 5211 "usb1", 5212 }; 5213 5214 static const char * const usb30_groups[] = { 5215 "usb30", 5216 }; 5217 5218 static const char * const vin4_groups[] = { 5219 "vin4_data8_a", 5220 "vin4_data10_a", 5221 "vin4_data12_a", 5222 "vin4_data16_a", 5223 "vin4_data18_a", 5224 "vin4_data20_a", 5225 "vin4_data24_a", 5226 "vin4_data8_b", 5227 "vin4_data10_b", 5228 "vin4_data12_b", 5229 "vin4_data16_b", 5230 "vin4_data18_b", 5231 "vin4_data20_b", 5232 "vin4_data24_b", 5233 "vin4_sync", 5234 "vin4_field", 5235 "vin4_clkenb", 5236 "vin4_clk", 5237 }; 5238 5239 static const char * const vin5_groups[] = { 5240 "vin5_data8", 5241 "vin5_data10", 5242 "vin5_data12", 5243 "vin5_data16", 5244 "vin5_sync", 5245 "vin5_field", 5246 "vin5_clkenb", 5247 "vin5_clk", 5248 }; 5249 5250 static const struct { 5251 struct sh_pfc_function common[51]; 5252 struct sh_pfc_function automotive[4]; 5253 } pinmux_functions = { 5254 .common = { 5255 SH_PFC_FUNCTION(audio_clk), 5256 SH_PFC_FUNCTION(avb), 5257 SH_PFC_FUNCTION(can0), 5258 SH_PFC_FUNCTION(can1), 5259 SH_PFC_FUNCTION(can_clk), 5260 SH_PFC_FUNCTION(canfd0), 5261 SH_PFC_FUNCTION(canfd1), 5262 SH_PFC_FUNCTION(du), 5263 SH_PFC_FUNCTION(hscif0), 5264 SH_PFC_FUNCTION(hscif1), 5265 SH_PFC_FUNCTION(hscif2), 5266 SH_PFC_FUNCTION(hscif3), 5267 SH_PFC_FUNCTION(hscif4), 5268 SH_PFC_FUNCTION(i2c0), 5269 SH_PFC_FUNCTION(i2c1), 5270 SH_PFC_FUNCTION(i2c2), 5271 SH_PFC_FUNCTION(i2c3), 5272 SH_PFC_FUNCTION(i2c5), 5273 SH_PFC_FUNCTION(i2c6), 5274 SH_PFC_FUNCTION(intc_ex), 5275 SH_PFC_FUNCTION(msiof0), 5276 SH_PFC_FUNCTION(msiof1), 5277 SH_PFC_FUNCTION(msiof2), 5278 SH_PFC_FUNCTION(msiof3), 5279 SH_PFC_FUNCTION(pwm0), 5280 SH_PFC_FUNCTION(pwm1), 5281 SH_PFC_FUNCTION(pwm2), 5282 SH_PFC_FUNCTION(pwm3), 5283 SH_PFC_FUNCTION(pwm4), 5284 SH_PFC_FUNCTION(pwm5), 5285 SH_PFC_FUNCTION(pwm6), 5286 SH_PFC_FUNCTION(sata0), 5287 SH_PFC_FUNCTION(scif0), 5288 SH_PFC_FUNCTION(scif1), 5289 SH_PFC_FUNCTION(scif2), 5290 SH_PFC_FUNCTION(scif3), 5291 SH_PFC_FUNCTION(scif4), 5292 SH_PFC_FUNCTION(scif5), 5293 SH_PFC_FUNCTION(scif_clk), 5294 SH_PFC_FUNCTION(sdhi0), 5295 SH_PFC_FUNCTION(sdhi1), 5296 SH_PFC_FUNCTION(sdhi2), 5297 SH_PFC_FUNCTION(sdhi3), 5298 SH_PFC_FUNCTION(ssi), 5299 SH_PFC_FUNCTION(tmu), 5300 SH_PFC_FUNCTION(tpu), 5301 SH_PFC_FUNCTION(usb0), 5302 SH_PFC_FUNCTION(usb1), 5303 SH_PFC_FUNCTION(usb30), 5304 SH_PFC_FUNCTION(vin4), 5305 SH_PFC_FUNCTION(vin5), 5306 }, 5307 .automotive = { 5308 SH_PFC_FUNCTION(drif0), 5309 SH_PFC_FUNCTION(drif1), 5310 SH_PFC_FUNCTION(drif2), 5311 SH_PFC_FUNCTION(drif3), 5312 } 5313 }; 5314 5315 static const struct pinmux_cfg_reg pinmux_config_regs[] = { 5316 #define F_(x, y) FN_##y 5317 #define FM(x) FN_##x 5318 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP( 5319 0, 0, 5320 0, 0, 5321 0, 0, 5322 0, 0, 5323 0, 0, 5324 0, 0, 5325 0, 0, 5326 0, 0, 5327 0, 0, 5328 0, 0, 5329 0, 0, 5330 0, 0, 5331 0, 0, 5332 0, 0, 5333 0, 0, 5334 0, 0, 5335 GP_0_15_FN, GPSR0_15, 5336 GP_0_14_FN, GPSR0_14, 5337 GP_0_13_FN, GPSR0_13, 5338 GP_0_12_FN, GPSR0_12, 5339 GP_0_11_FN, GPSR0_11, 5340 GP_0_10_FN, GPSR0_10, 5341 GP_0_9_FN, GPSR0_9, 5342 GP_0_8_FN, GPSR0_8, 5343 GP_0_7_FN, GPSR0_7, 5344 GP_0_6_FN, GPSR0_6, 5345 GP_0_5_FN, GPSR0_5, 5346 GP_0_4_FN, GPSR0_4, 5347 GP_0_3_FN, GPSR0_3, 5348 GP_0_2_FN, GPSR0_2, 5349 GP_0_1_FN, GPSR0_1, 5350 GP_0_0_FN, GPSR0_0, )) 5351 }, 5352 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP( 5353 0, 0, 5354 0, 0, 5355 0, 0, 5356 GP_1_28_FN, GPSR1_28, 5357 GP_1_27_FN, GPSR1_27, 5358 GP_1_26_FN, GPSR1_26, 5359 GP_1_25_FN, GPSR1_25, 5360 GP_1_24_FN, GPSR1_24, 5361 GP_1_23_FN, GPSR1_23, 5362 GP_1_22_FN, GPSR1_22, 5363 GP_1_21_FN, GPSR1_21, 5364 GP_1_20_FN, GPSR1_20, 5365 GP_1_19_FN, GPSR1_19, 5366 GP_1_18_FN, GPSR1_18, 5367 GP_1_17_FN, GPSR1_17, 5368 GP_1_16_FN, GPSR1_16, 5369 GP_1_15_FN, GPSR1_15, 5370 GP_1_14_FN, GPSR1_14, 5371 GP_1_13_FN, GPSR1_13, 5372 GP_1_12_FN, GPSR1_12, 5373 GP_1_11_FN, GPSR1_11, 5374 GP_1_10_FN, GPSR1_10, 5375 GP_1_9_FN, GPSR1_9, 5376 GP_1_8_FN, GPSR1_8, 5377 GP_1_7_FN, GPSR1_7, 5378 GP_1_6_FN, GPSR1_6, 5379 GP_1_5_FN, GPSR1_5, 5380 GP_1_4_FN, GPSR1_4, 5381 GP_1_3_FN, GPSR1_3, 5382 GP_1_2_FN, GPSR1_2, 5383 GP_1_1_FN, GPSR1_1, 5384 GP_1_0_FN, GPSR1_0, )) 5385 }, 5386 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP( 5387 0, 0, 5388 0, 0, 5389 0, 0, 5390 0, 0, 5391 0, 0, 5392 0, 0, 5393 0, 0, 5394 0, 0, 5395 0, 0, 5396 0, 0, 5397 0, 0, 5398 0, 0, 5399 0, 0, 5400 0, 0, 5401 0, 0, 5402 0, 0, 5403 0, 0, 5404 GP_2_14_FN, GPSR2_14, 5405 GP_2_13_FN, GPSR2_13, 5406 GP_2_12_FN, GPSR2_12, 5407 GP_2_11_FN, GPSR2_11, 5408 GP_2_10_FN, GPSR2_10, 5409 GP_2_9_FN, GPSR2_9, 5410 GP_2_8_FN, GPSR2_8, 5411 GP_2_7_FN, GPSR2_7, 5412 GP_2_6_FN, GPSR2_6, 5413 GP_2_5_FN, GPSR2_5, 5414 GP_2_4_FN, GPSR2_4, 5415 GP_2_3_FN, GPSR2_3, 5416 GP_2_2_FN, GPSR2_2, 5417 GP_2_1_FN, GPSR2_1, 5418 GP_2_0_FN, GPSR2_0, )) 5419 }, 5420 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP( 5421 0, 0, 5422 0, 0, 5423 0, 0, 5424 0, 0, 5425 0, 0, 5426 0, 0, 5427 0, 0, 5428 0, 0, 5429 0, 0, 5430 0, 0, 5431 0, 0, 5432 0, 0, 5433 0, 0, 5434 0, 0, 5435 0, 0, 5436 0, 0, 5437 GP_3_15_FN, GPSR3_15, 5438 GP_3_14_FN, GPSR3_14, 5439 GP_3_13_FN, GPSR3_13, 5440 GP_3_12_FN, GPSR3_12, 5441 GP_3_11_FN, GPSR3_11, 5442 GP_3_10_FN, GPSR3_10, 5443 GP_3_9_FN, GPSR3_9, 5444 GP_3_8_FN, GPSR3_8, 5445 GP_3_7_FN, GPSR3_7, 5446 GP_3_6_FN, GPSR3_6, 5447 GP_3_5_FN, GPSR3_5, 5448 GP_3_4_FN, GPSR3_4, 5449 GP_3_3_FN, GPSR3_3, 5450 GP_3_2_FN, GPSR3_2, 5451 GP_3_1_FN, GPSR3_1, 5452 GP_3_0_FN, GPSR3_0, )) 5453 }, 5454 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP( 5455 0, 0, 5456 0, 0, 5457 0, 0, 5458 0, 0, 5459 0, 0, 5460 0, 0, 5461 0, 0, 5462 0, 0, 5463 0, 0, 5464 0, 0, 5465 0, 0, 5466 0, 0, 5467 0, 0, 5468 0, 0, 5469 GP_4_17_FN, GPSR4_17, 5470 GP_4_16_FN, GPSR4_16, 5471 GP_4_15_FN, GPSR4_15, 5472 GP_4_14_FN, GPSR4_14, 5473 GP_4_13_FN, GPSR4_13, 5474 GP_4_12_FN, GPSR4_12, 5475 GP_4_11_FN, GPSR4_11, 5476 GP_4_10_FN, GPSR4_10, 5477 GP_4_9_FN, GPSR4_9, 5478 GP_4_8_FN, GPSR4_8, 5479 GP_4_7_FN, GPSR4_7, 5480 GP_4_6_FN, GPSR4_6, 5481 GP_4_5_FN, GPSR4_5, 5482 GP_4_4_FN, GPSR4_4, 5483 GP_4_3_FN, GPSR4_3, 5484 GP_4_2_FN, GPSR4_2, 5485 GP_4_1_FN, GPSR4_1, 5486 GP_4_0_FN, GPSR4_0, )) 5487 }, 5488 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP( 5489 0, 0, 5490 0, 0, 5491 0, 0, 5492 0, 0, 5493 0, 0, 5494 0, 0, 5495 GP_5_25_FN, GPSR5_25, 5496 GP_5_24_FN, GPSR5_24, 5497 GP_5_23_FN, GPSR5_23, 5498 GP_5_22_FN, GPSR5_22, 5499 GP_5_21_FN, GPSR5_21, 5500 GP_5_20_FN, GPSR5_20, 5501 GP_5_19_FN, GPSR5_19, 5502 GP_5_18_FN, GPSR5_18, 5503 GP_5_17_FN, GPSR5_17, 5504 GP_5_16_FN, GPSR5_16, 5505 GP_5_15_FN, GPSR5_15, 5506 GP_5_14_FN, GPSR5_14, 5507 GP_5_13_FN, GPSR5_13, 5508 GP_5_12_FN, GPSR5_12, 5509 GP_5_11_FN, GPSR5_11, 5510 GP_5_10_FN, GPSR5_10, 5511 GP_5_9_FN, GPSR5_9, 5512 GP_5_8_FN, GPSR5_8, 5513 GP_5_7_FN, GPSR5_7, 5514 GP_5_6_FN, GPSR5_6, 5515 GP_5_5_FN, GPSR5_5, 5516 GP_5_4_FN, GPSR5_4, 5517 GP_5_3_FN, GPSR5_3, 5518 GP_5_2_FN, GPSR5_2, 5519 GP_5_1_FN, GPSR5_1, 5520 GP_5_0_FN, GPSR5_0, )) 5521 }, 5522 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP( 5523 GP_6_31_FN, GPSR6_31, 5524 GP_6_30_FN, GPSR6_30, 5525 GP_6_29_FN, GPSR6_29, 5526 GP_6_28_FN, GPSR6_28, 5527 GP_6_27_FN, GPSR6_27, 5528 GP_6_26_FN, GPSR6_26, 5529 GP_6_25_FN, GPSR6_25, 5530 GP_6_24_FN, GPSR6_24, 5531 GP_6_23_FN, GPSR6_23, 5532 GP_6_22_FN, GPSR6_22, 5533 GP_6_21_FN, GPSR6_21, 5534 GP_6_20_FN, GPSR6_20, 5535 GP_6_19_FN, GPSR6_19, 5536 GP_6_18_FN, GPSR6_18, 5537 GP_6_17_FN, GPSR6_17, 5538 GP_6_16_FN, GPSR6_16, 5539 GP_6_15_FN, GPSR6_15, 5540 GP_6_14_FN, GPSR6_14, 5541 GP_6_13_FN, GPSR6_13, 5542 GP_6_12_FN, GPSR6_12, 5543 GP_6_11_FN, GPSR6_11, 5544 GP_6_10_FN, GPSR6_10, 5545 GP_6_9_FN, GPSR6_9, 5546 GP_6_8_FN, GPSR6_8, 5547 GP_6_7_FN, GPSR6_7, 5548 GP_6_6_FN, GPSR6_6, 5549 GP_6_5_FN, GPSR6_5, 5550 GP_6_4_FN, GPSR6_4, 5551 GP_6_3_FN, GPSR6_3, 5552 GP_6_2_FN, GPSR6_2, 5553 GP_6_1_FN, GPSR6_1, 5554 GP_6_0_FN, GPSR6_0, )) 5555 }, 5556 { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1, GROUP( 5557 0, 0, 5558 0, 0, 5559 0, 0, 5560 0, 0, 5561 0, 0, 5562 0, 0, 5563 0, 0, 5564 0, 0, 5565 0, 0, 5566 0, 0, 5567 0, 0, 5568 0, 0, 5569 0, 0, 5570 0, 0, 5571 0, 0, 5572 0, 0, 5573 0, 0, 5574 0, 0, 5575 0, 0, 5576 0, 0, 5577 0, 0, 5578 0, 0, 5579 0, 0, 5580 0, 0, 5581 0, 0, 5582 0, 0, 5583 0, 0, 5584 0, 0, 5585 GP_7_3_FN, GPSR7_3, 5586 GP_7_2_FN, GPSR7_2, 5587 GP_7_1_FN, GPSR7_1, 5588 GP_7_0_FN, GPSR7_0, )) 5589 }, 5590 #undef F_ 5591 #undef FM 5592 5593 #define F_(x, y) x, 5594 #define FM(x) FN_##x, 5595 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP( 5596 IP0_31_28 5597 IP0_27_24 5598 IP0_23_20 5599 IP0_19_16 5600 IP0_15_12 5601 IP0_11_8 5602 IP0_7_4 5603 IP0_3_0 )) 5604 }, 5605 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP( 5606 IP1_31_28 5607 IP1_27_24 5608 IP1_23_20 5609 IP1_19_16 5610 IP1_15_12 5611 IP1_11_8 5612 IP1_7_4 5613 IP1_3_0 )) 5614 }, 5615 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP( 5616 IP2_31_28 5617 IP2_27_24 5618 IP2_23_20 5619 IP2_19_16 5620 IP2_15_12 5621 IP2_11_8 5622 IP2_7_4 5623 IP2_3_0 )) 5624 }, 5625 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP( 5626 IP3_31_28 5627 IP3_27_24 5628 IP3_23_20 5629 IP3_19_16 5630 IP3_15_12 5631 IP3_11_8 5632 IP3_7_4 5633 IP3_3_0 )) 5634 }, 5635 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP( 5636 IP4_31_28 5637 IP4_27_24 5638 IP4_23_20 5639 IP4_19_16 5640 IP4_15_12 5641 IP4_11_8 5642 IP4_7_4 5643 IP4_3_0 )) 5644 }, 5645 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP( 5646 IP5_31_28 5647 IP5_27_24 5648 IP5_23_20 5649 IP5_19_16 5650 IP5_15_12 5651 IP5_11_8 5652 IP5_7_4 5653 IP5_3_0 )) 5654 }, 5655 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP( 5656 IP6_31_28 5657 IP6_27_24 5658 IP6_23_20 5659 IP6_19_16 5660 IP6_15_12 5661 IP6_11_8 5662 IP6_7_4 5663 IP6_3_0 )) 5664 }, 5665 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP( 5666 IP7_31_28 5667 IP7_27_24 5668 IP7_23_20 5669 IP7_19_16 5670 /* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5671 IP7_11_8 5672 IP7_7_4 5673 IP7_3_0 )) 5674 }, 5675 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP( 5676 IP8_31_28 5677 IP8_27_24 5678 IP8_23_20 5679 IP8_19_16 5680 IP8_15_12 5681 IP8_11_8 5682 IP8_7_4 5683 IP8_3_0 )) 5684 }, 5685 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP( 5686 IP9_31_28 5687 IP9_27_24 5688 IP9_23_20 5689 IP9_19_16 5690 IP9_15_12 5691 IP9_11_8 5692 IP9_7_4 5693 IP9_3_0 )) 5694 }, 5695 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP( 5696 IP10_31_28 5697 IP10_27_24 5698 IP10_23_20 5699 IP10_19_16 5700 IP10_15_12 5701 IP10_11_8 5702 IP10_7_4 5703 IP10_3_0 )) 5704 }, 5705 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP( 5706 IP11_31_28 5707 IP11_27_24 5708 IP11_23_20 5709 IP11_19_16 5710 IP11_15_12 5711 IP11_11_8 5712 IP11_7_4 5713 IP11_3_0 )) 5714 }, 5715 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP( 5716 IP12_31_28 5717 IP12_27_24 5718 IP12_23_20 5719 IP12_19_16 5720 IP12_15_12 5721 IP12_11_8 5722 IP12_7_4 5723 IP12_3_0 )) 5724 }, 5725 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP( 5726 IP13_31_28 5727 IP13_27_24 5728 IP13_23_20 5729 IP13_19_16 5730 IP13_15_12 5731 IP13_11_8 5732 IP13_7_4 5733 IP13_3_0 )) 5734 }, 5735 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP( 5736 IP14_31_28 5737 IP14_27_24 5738 IP14_23_20 5739 IP14_19_16 5740 IP14_15_12 5741 IP14_11_8 5742 IP14_7_4 5743 IP14_3_0 )) 5744 }, 5745 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP( 5746 IP15_31_28 5747 IP15_27_24 5748 IP15_23_20 5749 IP15_19_16 5750 IP15_15_12 5751 IP15_11_8 5752 IP15_7_4 5753 IP15_3_0 )) 5754 }, 5755 { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4, GROUP( 5756 IP16_31_28 5757 IP16_27_24 5758 IP16_23_20 5759 IP16_19_16 5760 IP16_15_12 5761 IP16_11_8 5762 IP16_7_4 5763 IP16_3_0 )) 5764 }, 5765 { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4, GROUP( 5766 IP17_31_28 5767 IP17_27_24 5768 IP17_23_20 5769 IP17_19_16 5770 IP17_15_12 5771 IP17_11_8 5772 IP17_7_4 5773 IP17_3_0 )) 5774 }, 5775 { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4, GROUP( 5776 /* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5777 /* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5778 /* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5779 /* IP18_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5780 /* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5781 /* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5782 IP18_7_4 5783 IP18_3_0 )) 5784 }, 5785 #undef F_ 5786 #undef FM 5787 5788 #define F_(x, y) x, 5789 #define FM(x) FN_##x, 5790 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32, 5791 GROUP(3, 2, 3, 1, 1, 1, 1, 1, 2, 1, 1, 2, 5792 1, 1, 1, 2, 2, 1, 2, 3), 5793 GROUP( 5794 MOD_SEL0_31_30_29 5795 MOD_SEL0_28_27 5796 MOD_SEL0_26_25_24 5797 MOD_SEL0_23 5798 MOD_SEL0_22 5799 MOD_SEL0_21 5800 MOD_SEL0_20 5801 MOD_SEL0_19 5802 MOD_SEL0_18_17 5803 MOD_SEL0_16 5804 0, 0, /* RESERVED 15 */ 5805 MOD_SEL0_14_13 5806 MOD_SEL0_12 5807 MOD_SEL0_11 5808 MOD_SEL0_10 5809 MOD_SEL0_9_8 5810 MOD_SEL0_7_6 5811 MOD_SEL0_5 5812 MOD_SEL0_4_3 5813 /* RESERVED 2, 1, 0 */ 5814 0, 0, 0, 0, 0, 0, 0, 0 )) 5815 }, 5816 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32, 5817 GROUP(2, 3, 1, 2, 3, 1, 1, 2, 1, 2, 1, 1, 5818 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1), 5819 GROUP( 5820 MOD_SEL1_31_30 5821 MOD_SEL1_29_28_27 5822 MOD_SEL1_26 5823 MOD_SEL1_25_24 5824 MOD_SEL1_23_22_21 5825 MOD_SEL1_20 5826 MOD_SEL1_19 5827 MOD_SEL1_18_17 5828 MOD_SEL1_16 5829 MOD_SEL1_15_14 5830 MOD_SEL1_13 5831 MOD_SEL1_12 5832 MOD_SEL1_11 5833 MOD_SEL1_10 5834 MOD_SEL1_9 5835 0, 0, 0, 0, /* RESERVED 8, 7 */ 5836 MOD_SEL1_6 5837 MOD_SEL1_5 5838 MOD_SEL1_4 5839 MOD_SEL1_3 5840 MOD_SEL1_2 5841 MOD_SEL1_1 5842 MOD_SEL1_0 )) 5843 }, 5844 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32, 5845 GROUP(1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, 5846 1, 4, 4, 4, 3, 1), 5847 GROUP( 5848 MOD_SEL2_31 5849 MOD_SEL2_30 5850 MOD_SEL2_29 5851 MOD_SEL2_28_27 5852 MOD_SEL2_26 5853 MOD_SEL2_25_24_23 5854 MOD_SEL2_22 5855 MOD_SEL2_21 5856 MOD_SEL2_20 5857 MOD_SEL2_19 5858 MOD_SEL2_18 5859 MOD_SEL2_17 5860 /* RESERVED 16 */ 5861 0, 0, 5862 /* RESERVED 15, 14, 13, 12 */ 5863 0, 0, 0, 0, 0, 0, 0, 0, 5864 0, 0, 0, 0, 0, 0, 0, 0, 5865 /* RESERVED 11, 10, 9, 8 */ 5866 0, 0, 0, 0, 0, 0, 0, 0, 5867 0, 0, 0, 0, 0, 0, 0, 0, 5868 /* RESERVED 7, 6, 5, 4 */ 5869 0, 0, 0, 0, 0, 0, 0, 0, 5870 0, 0, 0, 0, 0, 0, 0, 0, 5871 /* RESERVED 3, 2, 1 */ 5872 0, 0, 0, 0, 0, 0, 0, 0, 5873 MOD_SEL2_0 )) 5874 }, 5875 { }, 5876 }; 5877 5878 static const struct pinmux_drive_reg pinmux_drive_regs[] = { 5879 { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) { 5880 { PIN_QSPI0_SPCLK, 28, 2 }, /* QSPI0_SPCLK */ 5881 { PIN_QSPI0_MOSI_IO0, 24, 2 }, /* QSPI0_MOSI_IO0 */ 5882 { PIN_QSPI0_MISO_IO1, 20, 2 }, /* QSPI0_MISO_IO1 */ 5883 { PIN_QSPI0_IO2, 16, 2 }, /* QSPI0_IO2 */ 5884 { PIN_QSPI0_IO3, 12, 2 }, /* QSPI0_IO3 */ 5885 { PIN_QSPI0_SSL, 8, 2 }, /* QSPI0_SSL */ 5886 { PIN_QSPI1_SPCLK, 4, 2 }, /* QSPI1_SPCLK */ 5887 { PIN_QSPI1_MOSI_IO0, 0, 2 }, /* QSPI1_MOSI_IO0 */ 5888 } }, 5889 { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) { 5890 { PIN_QSPI1_MISO_IO1, 28, 2 }, /* QSPI1_MISO_IO1 */ 5891 { PIN_QSPI1_IO2, 24, 2 }, /* QSPI1_IO2 */ 5892 { PIN_QSPI1_IO3, 20, 2 }, /* QSPI1_IO3 */ 5893 { PIN_QSPI1_SSL, 16, 2 }, /* QSPI1_SSL */ 5894 { PIN_RPC_INT_N, 12, 2 }, /* RPC_INT# */ 5895 { PIN_RPC_WP_N, 8, 2 }, /* RPC_WP# */ 5896 { PIN_RPC_RESET_N, 4, 2 }, /* RPC_RESET# */ 5897 { PIN_AVB_RX_CTL, 0, 3 }, /* AVB_RX_CTL */ 5898 } }, 5899 { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) { 5900 { PIN_AVB_RXC, 28, 3 }, /* AVB_RXC */ 5901 { PIN_AVB_RD0, 24, 3 }, /* AVB_RD0 */ 5902 { PIN_AVB_RD1, 20, 3 }, /* AVB_RD1 */ 5903 { PIN_AVB_RD2, 16, 3 }, /* AVB_RD2 */ 5904 { PIN_AVB_RD3, 12, 3 }, /* AVB_RD3 */ 5905 { PIN_AVB_TX_CTL, 8, 3 }, /* AVB_TX_CTL */ 5906 { PIN_AVB_TXC, 4, 3 }, /* AVB_TXC */ 5907 { PIN_AVB_TD0, 0, 3 }, /* AVB_TD0 */ 5908 } }, 5909 { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) { 5910 { PIN_AVB_TD1, 28, 3 }, /* AVB_TD1 */ 5911 { PIN_AVB_TD2, 24, 3 }, /* AVB_TD2 */ 5912 { PIN_AVB_TD3, 20, 3 }, /* AVB_TD3 */ 5913 { PIN_AVB_TXCREFCLK, 16, 3 }, /* AVB_TXCREFCLK */ 5914 { PIN_AVB_MDIO, 12, 3 }, /* AVB_MDIO */ 5915 { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */ 5916 { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */ 5917 { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */ 5918 } }, 5919 { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) { 5920 { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */ 5921 { RCAR_GP_PIN(2, 13), 24, 3 }, /* AVB_AVTP_MATCH */ 5922 { RCAR_GP_PIN(2, 14), 20, 3 }, /* AVB_AVTP_CAPTURE */ 5923 { RCAR_GP_PIN(2, 0), 16, 3 }, /* IRQ0 */ 5924 { RCAR_GP_PIN(2, 1), 12, 3 }, /* IRQ1 */ 5925 { RCAR_GP_PIN(2, 2), 8, 3 }, /* IRQ2 */ 5926 { RCAR_GP_PIN(2, 3), 4, 3 }, /* IRQ3 */ 5927 { RCAR_GP_PIN(2, 4), 0, 3 }, /* IRQ4 */ 5928 } }, 5929 { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) { 5930 { RCAR_GP_PIN(2, 5), 28, 3 }, /* IRQ5 */ 5931 { RCAR_GP_PIN(2, 6), 24, 3 }, /* PWM0 */ 5932 { RCAR_GP_PIN(2, 7), 20, 3 }, /* PWM1 */ 5933 { RCAR_GP_PIN(2, 8), 16, 3 }, /* PWM2 */ 5934 { RCAR_GP_PIN(1, 0), 12, 3 }, /* A0 */ 5935 { RCAR_GP_PIN(1, 1), 8, 3 }, /* A1 */ 5936 { RCAR_GP_PIN(1, 2), 4, 3 }, /* A2 */ 5937 { RCAR_GP_PIN(1, 3), 0, 3 }, /* A3 */ 5938 } }, 5939 { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) { 5940 { RCAR_GP_PIN(1, 4), 28, 3 }, /* A4 */ 5941 { RCAR_GP_PIN(1, 5), 24, 3 }, /* A5 */ 5942 { RCAR_GP_PIN(1, 6), 20, 3 }, /* A6 */ 5943 { RCAR_GP_PIN(1, 7), 16, 3 }, /* A7 */ 5944 { RCAR_GP_PIN(1, 8), 12, 3 }, /* A8 */ 5945 { RCAR_GP_PIN(1, 9), 8, 3 }, /* A9 */ 5946 { RCAR_GP_PIN(1, 10), 4, 3 }, /* A10 */ 5947 { RCAR_GP_PIN(1, 11), 0, 3 }, /* A11 */ 5948 } }, 5949 { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) { 5950 { RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */ 5951 { RCAR_GP_PIN(1, 13), 24, 3 }, /* A13 */ 5952 { RCAR_GP_PIN(1, 14), 20, 3 }, /* A14 */ 5953 { RCAR_GP_PIN(1, 15), 16, 3 }, /* A15 */ 5954 { RCAR_GP_PIN(1, 16), 12, 3 }, /* A16 */ 5955 { RCAR_GP_PIN(1, 17), 8, 3 }, /* A17 */ 5956 { RCAR_GP_PIN(1, 18), 4, 3 }, /* A18 */ 5957 { RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */ 5958 } }, 5959 { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) { 5960 { RCAR_GP_PIN(1, 28), 28, 3 }, /* CLKOUT */ 5961 { RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */ 5962 { RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */ 5963 { RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */ 5964 { RCAR_GP_PIN(1, 23), 12, 3 }, /* RD */ 5965 { RCAR_GP_PIN(1, 24), 8, 3 }, /* RD_WR */ 5966 { RCAR_GP_PIN(1, 25), 4, 3 }, /* WE0 */ 5967 { RCAR_GP_PIN(1, 26), 0, 3 }, /* WE1 */ 5968 } }, 5969 { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) { 5970 { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */ 5971 { PIN_PRESETOUT_N, 24, 3 }, /* PRESETOUT# */ 5972 { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */ 5973 { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */ 5974 { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */ 5975 { RCAR_GP_PIN(0, 3), 8, 3 }, /* D3 */ 5976 { RCAR_GP_PIN(0, 4), 4, 3 }, /* D4 */ 5977 { RCAR_GP_PIN(0, 5), 0, 3 }, /* D5 */ 5978 } }, 5979 { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) { 5980 { RCAR_GP_PIN(0, 6), 28, 3 }, /* D6 */ 5981 { RCAR_GP_PIN(0, 7), 24, 3 }, /* D7 */ 5982 { RCAR_GP_PIN(0, 8), 20, 3 }, /* D8 */ 5983 { RCAR_GP_PIN(0, 9), 16, 3 }, /* D9 */ 5984 { RCAR_GP_PIN(0, 10), 12, 3 }, /* D10 */ 5985 { RCAR_GP_PIN(0, 11), 8, 3 }, /* D11 */ 5986 { RCAR_GP_PIN(0, 12), 4, 3 }, /* D12 */ 5987 { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */ 5988 } }, 5989 { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) { 5990 { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */ 5991 { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */ 5992 { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */ 5993 { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */ 5994 { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */ 5995 { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */ 5996 { PIN_DU_DOTCLKIN0, 4, 2 }, /* DU_DOTCLKIN0 */ 5997 { PIN_DU_DOTCLKIN1, 0, 2 }, /* DU_DOTCLKIN1 */ 5998 } }, 5999 { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) { 6000 { PIN_DU_DOTCLKIN3, 24, 2 }, /* DU_DOTCLKIN3 */ 6001 { PIN_FSCLKST, 20, 2 }, /* FSCLKST */ 6002 { PIN_TMS, 4, 2 }, /* TMS */ 6003 } }, 6004 { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) { 6005 { PIN_TDO, 28, 2 }, /* TDO */ 6006 { PIN_ASEBRK, 24, 2 }, /* ASEBRK */ 6007 { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */ 6008 { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */ 6009 { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */ 6010 { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */ 6011 { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */ 6012 { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */ 6013 } }, 6014 { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) { 6015 { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */ 6016 { RCAR_GP_PIN(3, 7), 24, 3 }, /* SD1_CMD */ 6017 { RCAR_GP_PIN(3, 8), 20, 3 }, /* SD1_DAT0 */ 6018 { RCAR_GP_PIN(3, 9), 16, 3 }, /* SD1_DAT1 */ 6019 { RCAR_GP_PIN(3, 10), 12, 3 }, /* SD1_DAT2 */ 6020 { RCAR_GP_PIN(3, 11), 8, 3 }, /* SD1_DAT3 */ 6021 { RCAR_GP_PIN(4, 0), 4, 3 }, /* SD2_CLK */ 6022 { RCAR_GP_PIN(4, 1), 0, 3 }, /* SD2_CMD */ 6023 } }, 6024 { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) { 6025 { RCAR_GP_PIN(4, 2), 28, 3 }, /* SD2_DAT0 */ 6026 { RCAR_GP_PIN(4, 3), 24, 3 }, /* SD2_DAT1 */ 6027 { RCAR_GP_PIN(4, 4), 20, 3 }, /* SD2_DAT2 */ 6028 { RCAR_GP_PIN(4, 5), 16, 3 }, /* SD2_DAT3 */ 6029 { RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */ 6030 { RCAR_GP_PIN(4, 7), 8, 3 }, /* SD3_CLK */ 6031 { RCAR_GP_PIN(4, 8), 4, 3 }, /* SD3_CMD */ 6032 { RCAR_GP_PIN(4, 9), 0, 3 }, /* SD3_DAT0 */ 6033 } }, 6034 { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) { 6035 { RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */ 6036 { RCAR_GP_PIN(4, 11), 24, 3 }, /* SD3_DAT2 */ 6037 { RCAR_GP_PIN(4, 12), 20, 3 }, /* SD3_DAT3 */ 6038 { RCAR_GP_PIN(4, 13), 16, 3 }, /* SD3_DAT4 */ 6039 { RCAR_GP_PIN(4, 14), 12, 3 }, /* SD3_DAT5 */ 6040 { RCAR_GP_PIN(4, 15), 8, 3 }, /* SD3_DAT6 */ 6041 { RCAR_GP_PIN(4, 16), 4, 3 }, /* SD3_DAT7 */ 6042 { RCAR_GP_PIN(4, 17), 0, 3 }, /* SD3_DS */ 6043 } }, 6044 { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) { 6045 { RCAR_GP_PIN(3, 12), 28, 3 }, /* SD0_CD */ 6046 { RCAR_GP_PIN(3, 13), 24, 3 }, /* SD0_WP */ 6047 { RCAR_GP_PIN(3, 14), 20, 3 }, /* SD1_CD */ 6048 { RCAR_GP_PIN(3, 15), 16, 3 }, /* SD1_WP */ 6049 { RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */ 6050 { RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */ 6051 { RCAR_GP_PIN(5, 2), 4, 3 }, /* TX0 */ 6052 { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */ 6053 } }, 6054 { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) { 6055 { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0 */ 6056 { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */ 6057 { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */ 6058 { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */ 6059 { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1 */ 6060 { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */ 6061 { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */ 6062 { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */ 6063 } }, 6064 { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) { 6065 { RCAR_GP_PIN(5, 12), 28, 3 }, /* HSCK0 */ 6066 { RCAR_GP_PIN(5, 13), 24, 3 }, /* HRX0 */ 6067 { RCAR_GP_PIN(5, 14), 20, 3 }, /* HTX0 */ 6068 { RCAR_GP_PIN(5, 15), 16, 3 }, /* HCTS0 */ 6069 { RCAR_GP_PIN(5, 16), 12, 3 }, /* HRTS0 */ 6070 { RCAR_GP_PIN(5, 17), 8, 3 }, /* MSIOF0_SCK */ 6071 { RCAR_GP_PIN(5, 18), 4, 3 }, /* MSIOF0_SYNC */ 6072 { RCAR_GP_PIN(5, 19), 0, 3 }, /* MSIOF0_SS1 */ 6073 } }, 6074 { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) { 6075 { RCAR_GP_PIN(5, 20), 28, 3 }, /* MSIOF0_TXD */ 6076 { RCAR_GP_PIN(5, 21), 24, 3 }, /* MSIOF0_SS2 */ 6077 { RCAR_GP_PIN(5, 22), 20, 3 }, /* MSIOF0_RXD */ 6078 { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */ 6079 { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */ 6080 { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */ 6081 { PIN_MLB_REF, 4, 3 }, /* MLB_REF */ 6082 { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */ 6083 } }, 6084 { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) { 6085 { RCAR_GP_PIN(6, 1), 28, 3 }, /* SSI_WS01239 */ 6086 { RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */ 6087 { RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */ 6088 { RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */ 6089 { RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK349 */ 6090 { RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS349 */ 6091 { RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */ 6092 { RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */ 6093 } }, 6094 { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) { 6095 { RCAR_GP_PIN(6, 9), 28, 3 }, /* SSI_WS4 */ 6096 { RCAR_GP_PIN(6, 10), 24, 3 }, /* SSI_SDATA4 */ 6097 { RCAR_GP_PIN(6, 11), 20, 3 }, /* SSI_SCK5 */ 6098 { RCAR_GP_PIN(6, 12), 16, 3 }, /* SSI_WS5 */ 6099 { RCAR_GP_PIN(6, 13), 12, 3 }, /* SSI_SDATA5 */ 6100 { RCAR_GP_PIN(6, 14), 8, 3 }, /* SSI_SCK6 */ 6101 { RCAR_GP_PIN(6, 15), 4, 3 }, /* SSI_WS6 */ 6102 { RCAR_GP_PIN(6, 16), 0, 3 }, /* SSI_SDATA6 */ 6103 } }, 6104 { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) { 6105 { RCAR_GP_PIN(6, 17), 28, 3 }, /* SSI_SCK78 */ 6106 { RCAR_GP_PIN(6, 18), 24, 3 }, /* SSI_WS78 */ 6107 { RCAR_GP_PIN(6, 19), 20, 3 }, /* SSI_SDATA7 */ 6108 { RCAR_GP_PIN(6, 20), 16, 3 }, /* SSI_SDATA8 */ 6109 { RCAR_GP_PIN(6, 21), 12, 3 }, /* SSI_SDATA9 */ 6110 { RCAR_GP_PIN(6, 22), 8, 3 }, /* AUDIO_CLKA */ 6111 { RCAR_GP_PIN(6, 23), 4, 3 }, /* AUDIO_CLKB */ 6112 { RCAR_GP_PIN(6, 24), 0, 3 }, /* USB0_PWEN */ 6113 } }, 6114 { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) { 6115 { RCAR_GP_PIN(6, 25), 28, 3 }, /* USB0_OVC */ 6116 { RCAR_GP_PIN(6, 26), 24, 3 }, /* USB1_PWEN */ 6117 { RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */ 6118 { RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */ 6119 { RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */ 6120 { RCAR_GP_PIN(6, 30), 8, 3 }, /* GP6_30 */ 6121 { RCAR_GP_PIN(6, 31), 4, 3 }, /* GP6_31 */ 6122 } }, 6123 { }, 6124 }; 6125 6126 enum ioctrl_regs { 6127 POCCTRL, 6128 TDSELCTRL, 6129 }; 6130 6131 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { 6132 [POCCTRL] = { 0xe6060380, }, 6133 [TDSELCTRL] = { 0xe60603c0, }, 6134 { /* sentinel */ }, 6135 }; 6136 6137 static int r8a77965_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl) 6138 { 6139 int bit = -EINVAL; 6140 6141 *pocctrl = pinmux_ioctrl_regs[POCCTRL].reg; 6142 6143 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11)) 6144 bit = pin & 0x1f; 6145 6146 if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17)) 6147 bit = (pin & 0x1f) + 12; 6148 6149 return bit; 6150 } 6151 6152 static const struct pinmux_bias_reg pinmux_bias_regs[] = { 6153 { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) { 6154 [ 0] = PIN_QSPI0_SPCLK, /* QSPI0_SPCLK */ 6155 [ 1] = PIN_QSPI0_MOSI_IO0, /* QSPI0_MOSI_IO0 */ 6156 [ 2] = PIN_QSPI0_MISO_IO1, /* QSPI0_MISO_IO1 */ 6157 [ 3] = PIN_QSPI0_IO2, /* QSPI0_IO2 */ 6158 [ 4] = PIN_QSPI0_IO3, /* QSPI0_IO3 */ 6159 [ 5] = PIN_QSPI0_SSL, /* QSPI0_SSL */ 6160 [ 6] = PIN_QSPI1_SPCLK, /* QSPI1_SPCLK */ 6161 [ 7] = PIN_QSPI1_MOSI_IO0, /* QSPI1_MOSI_IO0 */ 6162 [ 8] = PIN_QSPI1_MISO_IO1, /* QSPI1_MISO_IO1 */ 6163 [ 9] = PIN_QSPI1_IO2, /* QSPI1_IO2 */ 6164 [10] = PIN_QSPI1_IO3, /* QSPI1_IO3 */ 6165 [11] = PIN_QSPI1_SSL, /* QSPI1_SSL */ 6166 [12] = PIN_RPC_INT_N, /* RPC_INT# */ 6167 [13] = PIN_RPC_WP_N, /* RPC_WP# */ 6168 [14] = PIN_RPC_RESET_N, /* RPC_RESET# */ 6169 [15] = PIN_AVB_RX_CTL, /* AVB_RX_CTL */ 6170 [16] = PIN_AVB_RXC, /* AVB_RXC */ 6171 [17] = PIN_AVB_RD0, /* AVB_RD0 */ 6172 [18] = PIN_AVB_RD1, /* AVB_RD1 */ 6173 [19] = PIN_AVB_RD2, /* AVB_RD2 */ 6174 [20] = PIN_AVB_RD3, /* AVB_RD3 */ 6175 [21] = PIN_AVB_TX_CTL, /* AVB_TX_CTL */ 6176 [22] = PIN_AVB_TXC, /* AVB_TXC */ 6177 [23] = PIN_AVB_TD0, /* AVB_TD0 */ 6178 [24] = PIN_AVB_TD1, /* AVB_TD1 */ 6179 [25] = PIN_AVB_TD2, /* AVB_TD2 */ 6180 [26] = PIN_AVB_TD3, /* AVB_TD3 */ 6181 [27] = PIN_AVB_TXCREFCLK, /* AVB_TXCREFCLK */ 6182 [28] = PIN_AVB_MDIO, /* AVB_MDIO */ 6183 [29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */ 6184 [30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */ 6185 [31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */ 6186 } }, 6187 { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) { 6188 [ 0] = RCAR_GP_PIN(2, 12), /* AVB_LINK */ 6189 [ 1] = RCAR_GP_PIN(2, 13), /* AVB_AVTP_MATCH_A */ 6190 [ 2] = RCAR_GP_PIN(2, 14), /* AVB_AVTP_CAPTURE_A */ 6191 [ 3] = RCAR_GP_PIN(2, 0), /* IRQ0 */ 6192 [ 4] = RCAR_GP_PIN(2, 1), /* IRQ1 */ 6193 [ 5] = RCAR_GP_PIN(2, 2), /* IRQ2 */ 6194 [ 6] = RCAR_GP_PIN(2, 3), /* IRQ3 */ 6195 [ 7] = RCAR_GP_PIN(2, 4), /* IRQ4 */ 6196 [ 8] = RCAR_GP_PIN(2, 5), /* IRQ5 */ 6197 [ 9] = RCAR_GP_PIN(2, 6), /* PWM0 */ 6198 [10] = RCAR_GP_PIN(2, 7), /* PWM1_A */ 6199 [11] = RCAR_GP_PIN(2, 8), /* PWM2_A */ 6200 [12] = RCAR_GP_PIN(1, 0), /* A0 */ 6201 [13] = RCAR_GP_PIN(1, 1), /* A1 */ 6202 [14] = RCAR_GP_PIN(1, 2), /* A2 */ 6203 [15] = RCAR_GP_PIN(1, 3), /* A3 */ 6204 [16] = RCAR_GP_PIN(1, 4), /* A4 */ 6205 [17] = RCAR_GP_PIN(1, 5), /* A5 */ 6206 [18] = RCAR_GP_PIN(1, 6), /* A6 */ 6207 [19] = RCAR_GP_PIN(1, 7), /* A7 */ 6208 [20] = RCAR_GP_PIN(1, 8), /* A8 */ 6209 [21] = RCAR_GP_PIN(1, 9), /* A9 */ 6210 [22] = RCAR_GP_PIN(1, 10), /* A10 */ 6211 [23] = RCAR_GP_PIN(1, 11), /* A11 */ 6212 [24] = RCAR_GP_PIN(1, 12), /* A12 */ 6213 [25] = RCAR_GP_PIN(1, 13), /* A13 */ 6214 [26] = RCAR_GP_PIN(1, 14), /* A14 */ 6215 [27] = RCAR_GP_PIN(1, 15), /* A15 */ 6216 [28] = RCAR_GP_PIN(1, 16), /* A16 */ 6217 [29] = RCAR_GP_PIN(1, 17), /* A17 */ 6218 [30] = RCAR_GP_PIN(1, 18), /* A18 */ 6219 [31] = RCAR_GP_PIN(1, 19), /* A19 */ 6220 } }, 6221 { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) { 6222 [ 0] = RCAR_GP_PIN(1, 28), /* CLKOUT */ 6223 [ 1] = RCAR_GP_PIN(1, 20), /* CS0_N */ 6224 [ 2] = RCAR_GP_PIN(1, 21), /* CS1_N */ 6225 [ 3] = RCAR_GP_PIN(1, 22), /* BS_N */ 6226 [ 4] = RCAR_GP_PIN(1, 23), /* RD_N */ 6227 [ 5] = RCAR_GP_PIN(1, 24), /* RD_WR_N */ 6228 [ 6] = RCAR_GP_PIN(1, 25), /* WE0_N */ 6229 [ 7] = RCAR_GP_PIN(1, 26), /* WE1_N */ 6230 [ 8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */ 6231 [ 9] = PIN_PRESETOUT_N, /* PRESETOUT# */ 6232 [10] = RCAR_GP_PIN(0, 0), /* D0 */ 6233 [11] = RCAR_GP_PIN(0, 1), /* D1 */ 6234 [12] = RCAR_GP_PIN(0, 2), /* D2 */ 6235 [13] = RCAR_GP_PIN(0, 3), /* D3 */ 6236 [14] = RCAR_GP_PIN(0, 4), /* D4 */ 6237 [15] = RCAR_GP_PIN(0, 5), /* D5 */ 6238 [16] = RCAR_GP_PIN(0, 6), /* D6 */ 6239 [17] = RCAR_GP_PIN(0, 7), /* D7 */ 6240 [18] = RCAR_GP_PIN(0, 8), /* D8 */ 6241 [19] = RCAR_GP_PIN(0, 9), /* D9 */ 6242 [20] = RCAR_GP_PIN(0, 10), /* D10 */ 6243 [21] = RCAR_GP_PIN(0, 11), /* D11 */ 6244 [22] = RCAR_GP_PIN(0, 12), /* D12 */ 6245 [23] = RCAR_GP_PIN(0, 13), /* D13 */ 6246 [24] = RCAR_GP_PIN(0, 14), /* D14 */ 6247 [25] = RCAR_GP_PIN(0, 15), /* D15 */ 6248 [26] = RCAR_GP_PIN(7, 0), /* AVS1 */ 6249 [27] = RCAR_GP_PIN(7, 1), /* AVS2 */ 6250 [28] = RCAR_GP_PIN(7, 2), /* GP7_02 */ 6251 [29] = RCAR_GP_PIN(7, 3), /* GP7_03 */ 6252 [30] = PIN_DU_DOTCLKIN0, /* DU_DOTCLKIN0 */ 6253 [31] = PIN_DU_DOTCLKIN1, /* DU_DOTCLKIN1 */ 6254 } }, 6255 { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) { 6256 [ 0] = SH_PFC_PIN_NONE, 6257 [ 1] = PIN_DU_DOTCLKIN3, /* DU_DOTCLKIN3 */ 6258 [ 2] = PIN_FSCLKST, /* FSCLKST */ 6259 [ 3] = PIN_EXTALR, /* EXTALR*/ 6260 [ 4] = PIN_TRST_N, /* TRST# */ 6261 [ 5] = PIN_TCK, /* TCK */ 6262 [ 6] = PIN_TMS, /* TMS */ 6263 [ 7] = PIN_TDI, /* TDI */ 6264 [ 8] = SH_PFC_PIN_NONE, 6265 [ 9] = PIN_ASEBRK, /* ASEBRK */ 6266 [10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */ 6267 [11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */ 6268 [12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */ 6269 [13] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */ 6270 [14] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */ 6271 [15] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */ 6272 [16] = RCAR_GP_PIN(3, 6), /* SD1_CLK */ 6273 [17] = RCAR_GP_PIN(3, 7), /* SD1_CMD */ 6274 [18] = RCAR_GP_PIN(3, 8), /* SD1_DAT0 */ 6275 [19] = RCAR_GP_PIN(3, 9), /* SD1_DAT1 */ 6276 [20] = RCAR_GP_PIN(3, 10), /* SD1_DAT2 */ 6277 [21] = RCAR_GP_PIN(3, 11), /* SD1_DAT3 */ 6278 [22] = RCAR_GP_PIN(4, 0), /* SD2_CLK */ 6279 [23] = RCAR_GP_PIN(4, 1), /* SD2_CMD */ 6280 [24] = RCAR_GP_PIN(4, 2), /* SD2_DAT0 */ 6281 [25] = RCAR_GP_PIN(4, 3), /* SD2_DAT1 */ 6282 [26] = RCAR_GP_PIN(4, 4), /* SD2_DAT2 */ 6283 [27] = RCAR_GP_PIN(4, 5), /* SD2_DAT3 */ 6284 [28] = RCAR_GP_PIN(4, 6), /* SD2_DS */ 6285 [29] = RCAR_GP_PIN(4, 7), /* SD3_CLK */ 6286 [30] = RCAR_GP_PIN(4, 8), /* SD3_CMD */ 6287 [31] = RCAR_GP_PIN(4, 9), /* SD3_DAT0 */ 6288 } }, 6289 { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) { 6290 [ 0] = RCAR_GP_PIN(4, 10), /* SD3_DAT1 */ 6291 [ 1] = RCAR_GP_PIN(4, 11), /* SD3_DAT2 */ 6292 [ 2] = RCAR_GP_PIN(4, 12), /* SD3_DAT3 */ 6293 [ 3] = RCAR_GP_PIN(4, 13), /* SD3_DAT4 */ 6294 [ 4] = RCAR_GP_PIN(4, 14), /* SD3_DAT5 */ 6295 [ 5] = RCAR_GP_PIN(4, 15), /* SD3_DAT6 */ 6296 [ 6] = RCAR_GP_PIN(4, 16), /* SD3_DAT7 */ 6297 [ 7] = RCAR_GP_PIN(4, 17), /* SD3_DS */ 6298 [ 8] = RCAR_GP_PIN(3, 12), /* SD0_CD */ 6299 [ 9] = RCAR_GP_PIN(3, 13), /* SD0_WP */ 6300 [10] = RCAR_GP_PIN(3, 14), /* SD1_CD */ 6301 [11] = RCAR_GP_PIN(3, 15), /* SD1_WP */ 6302 [12] = RCAR_GP_PIN(5, 0), /* SCK0 */ 6303 [13] = RCAR_GP_PIN(5, 1), /* RX0 */ 6304 [14] = RCAR_GP_PIN(5, 2), /* TX0 */ 6305 [15] = RCAR_GP_PIN(5, 3), /* CTS0_N */ 6306 [16] = RCAR_GP_PIN(5, 4), /* RTS0_N */ 6307 [17] = RCAR_GP_PIN(5, 5), /* RX1_A */ 6308 [18] = RCAR_GP_PIN(5, 6), /* TX1_A */ 6309 [19] = RCAR_GP_PIN(5, 7), /* CTS1_N */ 6310 [20] = RCAR_GP_PIN(5, 8), /* RTS1_N */ 6311 [21] = RCAR_GP_PIN(5, 9), /* SCK2 */ 6312 [22] = RCAR_GP_PIN(5, 10), /* TX2_A */ 6313 [23] = RCAR_GP_PIN(5, 11), /* RX2_A */ 6314 [24] = RCAR_GP_PIN(5, 12), /* HSCK0 */ 6315 [25] = RCAR_GP_PIN(5, 13), /* HRX0 */ 6316 [26] = RCAR_GP_PIN(5, 14), /* HTX0 */ 6317 [27] = RCAR_GP_PIN(5, 15), /* HCTS0_N */ 6318 [28] = RCAR_GP_PIN(5, 16), /* HRTS0_N */ 6319 [29] = RCAR_GP_PIN(5, 17), /* MSIOF0_SCK */ 6320 [30] = RCAR_GP_PIN(5, 18), /* MSIOF0_SYNC */ 6321 [31] = RCAR_GP_PIN(5, 19), /* MSIOF0_SS1 */ 6322 } }, 6323 { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) { 6324 [ 0] = RCAR_GP_PIN(5, 20), /* MSIOF0_TXD */ 6325 [ 1] = RCAR_GP_PIN(5, 21), /* MSIOF0_SS2 */ 6326 [ 2] = RCAR_GP_PIN(5, 22), /* MSIOF0_RXD */ 6327 [ 3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */ 6328 [ 4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */ 6329 [ 5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */ 6330 [ 6] = PIN_MLB_REF, /* MLB_REF */ 6331 [ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */ 6332 [ 8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */ 6333 [ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */ 6334 [10] = RCAR_GP_PIN(6, 3), /* SSI_SDATA1_A */ 6335 [11] = RCAR_GP_PIN(6, 4), /* SSI_SDATA2_A */ 6336 [12] = RCAR_GP_PIN(6, 5), /* SSI_SCK349 */ 6337 [13] = RCAR_GP_PIN(6, 6), /* SSI_WS349 */ 6338 [14] = RCAR_GP_PIN(6, 7), /* SSI_SDATA3 */ 6339 [15] = RCAR_GP_PIN(6, 8), /* SSI_SCK4 */ 6340 [16] = RCAR_GP_PIN(6, 9), /* SSI_WS4 */ 6341 [17] = RCAR_GP_PIN(6, 10), /* SSI_SDATA4 */ 6342 [18] = RCAR_GP_PIN(6, 11), /* SSI_SCK5 */ 6343 [19] = RCAR_GP_PIN(6, 12), /* SSI_WS5 */ 6344 [20] = RCAR_GP_PIN(6, 13), /* SSI_SDATA5 */ 6345 [21] = RCAR_GP_PIN(6, 14), /* SSI_SCK6 */ 6346 [22] = RCAR_GP_PIN(6, 15), /* SSI_WS6 */ 6347 [23] = RCAR_GP_PIN(6, 16), /* SSI_SDATA6 */ 6348 [24] = RCAR_GP_PIN(6, 17), /* SSI_SCK78 */ 6349 [25] = RCAR_GP_PIN(6, 18), /* SSI_WS78 */ 6350 [26] = RCAR_GP_PIN(6, 19), /* SSI_SDATA7 */ 6351 [27] = RCAR_GP_PIN(6, 20), /* SSI_SDATA8 */ 6352 [28] = RCAR_GP_PIN(6, 21), /* SSI_SDATA9_A */ 6353 [29] = RCAR_GP_PIN(6, 22), /* AUDIO_CLKA_A */ 6354 [30] = RCAR_GP_PIN(6, 23), /* AUDIO_CLKB_B */ 6355 [31] = RCAR_GP_PIN(6, 24), /* USB0_PWEN */ 6356 } }, 6357 { PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) { 6358 [ 0] = RCAR_GP_PIN(6, 25), /* USB0_OVC */ 6359 [ 1] = RCAR_GP_PIN(6, 26), /* USB1_PWEN */ 6360 [ 2] = RCAR_GP_PIN(6, 27), /* USB1_OVC */ 6361 [ 3] = RCAR_GP_PIN(6, 28), /* USB30_PWEN */ 6362 [ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */ 6363 [ 5] = RCAR_GP_PIN(6, 30), /* GP6_30 */ 6364 [ 6] = RCAR_GP_PIN(6, 31), /* GP6_31 */ 6365 [ 7] = SH_PFC_PIN_NONE, 6366 [ 8] = SH_PFC_PIN_NONE, 6367 [ 9] = SH_PFC_PIN_NONE, 6368 [10] = SH_PFC_PIN_NONE, 6369 [11] = SH_PFC_PIN_NONE, 6370 [12] = SH_PFC_PIN_NONE, 6371 [13] = SH_PFC_PIN_NONE, 6372 [14] = SH_PFC_PIN_NONE, 6373 [15] = SH_PFC_PIN_NONE, 6374 [16] = SH_PFC_PIN_NONE, 6375 [17] = SH_PFC_PIN_NONE, 6376 [18] = SH_PFC_PIN_NONE, 6377 [19] = SH_PFC_PIN_NONE, 6378 [20] = SH_PFC_PIN_NONE, 6379 [21] = SH_PFC_PIN_NONE, 6380 [22] = SH_PFC_PIN_NONE, 6381 [23] = SH_PFC_PIN_NONE, 6382 [24] = SH_PFC_PIN_NONE, 6383 [25] = SH_PFC_PIN_NONE, 6384 [26] = SH_PFC_PIN_NONE, 6385 [27] = SH_PFC_PIN_NONE, 6386 [28] = SH_PFC_PIN_NONE, 6387 [29] = SH_PFC_PIN_NONE, 6388 [30] = SH_PFC_PIN_NONE, 6389 [31] = SH_PFC_PIN_NONE, 6390 } }, 6391 { /* sentinel */ }, 6392 }; 6393 6394 static unsigned int r8a77965_pinmux_get_bias(struct sh_pfc *pfc, 6395 unsigned int pin) 6396 { 6397 const struct pinmux_bias_reg *reg; 6398 unsigned int bit; 6399 6400 reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit); 6401 if (!reg) 6402 return PIN_CONFIG_BIAS_DISABLE; 6403 6404 if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit))) 6405 return PIN_CONFIG_BIAS_DISABLE; 6406 else if (sh_pfc_read(pfc, reg->pud) & BIT(bit)) 6407 return PIN_CONFIG_BIAS_PULL_UP; 6408 else 6409 return PIN_CONFIG_BIAS_PULL_DOWN; 6410 } 6411 6412 static void r8a77965_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, 6413 unsigned int bias) 6414 { 6415 const struct pinmux_bias_reg *reg; 6416 u32 enable, updown; 6417 unsigned int bit; 6418 6419 reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit); 6420 if (!reg) 6421 return; 6422 6423 enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit); 6424 if (bias != PIN_CONFIG_BIAS_DISABLE) 6425 enable |= BIT(bit); 6426 6427 updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit); 6428 if (bias == PIN_CONFIG_BIAS_PULL_UP) 6429 updown |= BIT(bit); 6430 6431 sh_pfc_write(pfc, reg->pud, updown); 6432 sh_pfc_write(pfc, reg->puen, enable); 6433 } 6434 6435 static const struct sh_pfc_soc_operations r8a77965_pinmux_ops = { 6436 .pin_to_pocctrl = r8a77965_pin_to_pocctrl, 6437 .get_bias = r8a77965_pinmux_get_bias, 6438 .set_bias = r8a77965_pinmux_set_bias, 6439 }; 6440 6441 #ifdef CONFIG_PINCTRL_PFC_R8A774B1 6442 const struct sh_pfc_soc_info r8a774b1_pinmux_info = { 6443 .name = "r8a774b1_pfc", 6444 .ops = &r8a77965_pinmux_ops, 6445 .unlock_reg = 0xe6060000, /* PMMR */ 6446 6447 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 6448 6449 .pins = pinmux_pins, 6450 .nr_pins = ARRAY_SIZE(pinmux_pins), 6451 .groups = pinmux_groups.common, 6452 .nr_groups = ARRAY_SIZE(pinmux_groups.common), 6453 .functions = pinmux_functions.common, 6454 .nr_functions = ARRAY_SIZE(pinmux_functions.common), 6455 6456 .cfg_regs = pinmux_config_regs, 6457 .drive_regs = pinmux_drive_regs, 6458 .bias_regs = pinmux_bias_regs, 6459 .ioctrl_regs = pinmux_ioctrl_regs, 6460 6461 .pinmux_data = pinmux_data, 6462 .pinmux_data_size = ARRAY_SIZE(pinmux_data), 6463 }; 6464 #endif 6465 6466 #ifdef CONFIG_PINCTRL_PFC_R8A77965 6467 const struct sh_pfc_soc_info r8a77965_pinmux_info = { 6468 .name = "r8a77965_pfc", 6469 .ops = &r8a77965_pinmux_ops, 6470 .unlock_reg = 0xe6060000, /* PMMR */ 6471 6472 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 6473 6474 .pins = pinmux_pins, 6475 .nr_pins = ARRAY_SIZE(pinmux_pins), 6476 .groups = pinmux_groups.common, 6477 .nr_groups = ARRAY_SIZE(pinmux_groups.common) + 6478 ARRAY_SIZE(pinmux_groups.automotive), 6479 .functions = pinmux_functions.common, 6480 .nr_functions = ARRAY_SIZE(pinmux_functions.common) + 6481 ARRAY_SIZE(pinmux_functions.automotive), 6482 6483 .cfg_regs = pinmux_config_regs, 6484 .drive_regs = pinmux_drive_regs, 6485 .bias_regs = pinmux_bias_regs, 6486 .ioctrl_regs = pinmux_ioctrl_regs, 6487 6488 .pinmux_data = pinmux_data, 6489 .pinmux_data_size = ARRAY_SIZE(pinmux_data), 6490 }; 6491 #endif 6492