1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * R8A77965 processor support - PFC hardware block. 4 * 5 * Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org> 6 * Copyright (C) 2016-2019 Renesas Electronics Corp. 7 * 8 * This file is based on the drivers/pinctrl/renesas/pfc-r8a7796.c 9 * 10 * R-Car Gen3 processor support - PFC hardware block. 11 * 12 * Copyright (C) 2015 Renesas Electronics Corporation 13 */ 14 15 #include <linux/errno.h> 16 #include <linux/kernel.h> 17 18 #include "core.h" 19 #include "sh_pfc.h" 20 21 #define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN) 22 23 #define CPU_ALL_GP(fn, sfx) \ 24 PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \ 25 PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \ 26 PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \ 27 PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \ 28 PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \ 29 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \ 30 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \ 31 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \ 32 PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \ 33 PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \ 34 PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \ 35 PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS) 36 37 #define CPU_ALL_NOGP(fn) \ 38 PIN_NOGP_CFG(ASEBRK, "ASEBRK", fn, CFG_FLAGS), \ 39 PIN_NOGP_CFG(AVB_MDIO, "AVB_MDIO", fn, CFG_FLAGS), \ 40 PIN_NOGP_CFG(AVB_RD0, "AVB_RD0", fn, CFG_FLAGS), \ 41 PIN_NOGP_CFG(AVB_RD1, "AVB_RD1", fn, CFG_FLAGS), \ 42 PIN_NOGP_CFG(AVB_RD2, "AVB_RD2", fn, CFG_FLAGS), \ 43 PIN_NOGP_CFG(AVB_RD3, "AVB_RD3", fn, CFG_FLAGS), \ 44 PIN_NOGP_CFG(AVB_RXC, "AVB_RXC", fn, CFG_FLAGS), \ 45 PIN_NOGP_CFG(AVB_RX_CTL, "AVB_RX_CTL", fn, CFG_FLAGS), \ 46 PIN_NOGP_CFG(AVB_TD0, "AVB_TD0", fn, CFG_FLAGS), \ 47 PIN_NOGP_CFG(AVB_TD1, "AVB_TD1", fn, CFG_FLAGS), \ 48 PIN_NOGP_CFG(AVB_TD2, "AVB_TD2", fn, CFG_FLAGS), \ 49 PIN_NOGP_CFG(AVB_TD3, "AVB_TD3", fn, CFG_FLAGS), \ 50 PIN_NOGP_CFG(AVB_TXC, "AVB_TXC", fn, CFG_FLAGS), \ 51 PIN_NOGP_CFG(AVB_TXCREFCLK, "AVB_TXCREFCLK", fn, CFG_FLAGS), \ 52 PIN_NOGP_CFG(AVB_TX_CTL, "AVB_TX_CTL", fn, CFG_FLAGS), \ 53 PIN_NOGP_CFG(DU_DOTCLKIN0, "DU_DOTCLKIN0", fn, CFG_FLAGS), \ 54 PIN_NOGP_CFG(DU_DOTCLKIN1, "DU_DOTCLKIN1", fn, CFG_FLAGS), \ 55 PIN_NOGP_CFG(DU_DOTCLKIN3, "DU_DOTCLKIN3", fn, CFG_FLAGS), \ 56 PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),\ 57 PIN_NOGP_CFG(FSCLKST, "FSCLKST", fn, CFG_FLAGS), \ 58 PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS), \ 59 PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, CFG_FLAGS), \ 60 PIN_NOGP_CFG(QSPI0_IO2, "QSPI0_IO2", fn, CFG_FLAGS), \ 61 PIN_NOGP_CFG(QSPI0_IO3, "QSPI0_IO3", fn, CFG_FLAGS), \ 62 PIN_NOGP_CFG(QSPI0_MISO_IO1, "QSPI0_MISO_IO1", fn, CFG_FLAGS), \ 63 PIN_NOGP_CFG(QSPI0_MOSI_IO0, "QSPI0_MOSI_IO0", fn, CFG_FLAGS), \ 64 PIN_NOGP_CFG(QSPI0_SPCLK, "QSPI0_SPCLK", fn, CFG_FLAGS), \ 65 PIN_NOGP_CFG(QSPI0_SSL, "QSPI0_SSL", fn, CFG_FLAGS), \ 66 PIN_NOGP_CFG(QSPI1_IO2, "QSPI1_IO2", fn, CFG_FLAGS), \ 67 PIN_NOGP_CFG(QSPI1_IO3, "QSPI1_IO3", fn, CFG_FLAGS), \ 68 PIN_NOGP_CFG(QSPI1_MISO_IO1, "QSPI1_MISO_IO1", fn, CFG_FLAGS), \ 69 PIN_NOGP_CFG(QSPI1_MOSI_IO0, "QSPI1_MOSI_IO0", fn, CFG_FLAGS), \ 70 PIN_NOGP_CFG(QSPI1_SPCLK, "QSPI1_SPCLK", fn, CFG_FLAGS), \ 71 PIN_NOGP_CFG(QSPI1_SSL, "QSPI1_SSL", fn, CFG_FLAGS), \ 72 PIN_NOGP_CFG(RPC_INT_N, "RPC_INT#", fn, CFG_FLAGS), \ 73 PIN_NOGP_CFG(RPC_RESET_N, "RPC_RESET#", fn, CFG_FLAGS), \ 74 PIN_NOGP_CFG(RPC_WP_N, "RPC_WP#", fn, CFG_FLAGS), \ 75 PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ 76 PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ 77 PIN_NOGP_CFG(TDO, "TDO", fn, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \ 78 PIN_NOGP_CFG(TMS, "TMS", fn, CFG_FLAGS), \ 79 PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN) 80 81 /* 82 * F_() : just information 83 * FM() : macro for FN_xxx / xxx_MARK 84 */ 85 86 /* GPSR0 */ 87 #define GPSR0_15 F_(D15, IP7_11_8) 88 #define GPSR0_14 F_(D14, IP7_7_4) 89 #define GPSR0_13 F_(D13, IP7_3_0) 90 #define GPSR0_12 F_(D12, IP6_31_28) 91 #define GPSR0_11 F_(D11, IP6_27_24) 92 #define GPSR0_10 F_(D10, IP6_23_20) 93 #define GPSR0_9 F_(D9, IP6_19_16) 94 #define GPSR0_8 F_(D8, IP6_15_12) 95 #define GPSR0_7 F_(D7, IP6_11_8) 96 #define GPSR0_6 F_(D6, IP6_7_4) 97 #define GPSR0_5 F_(D5, IP6_3_0) 98 #define GPSR0_4 F_(D4, IP5_31_28) 99 #define GPSR0_3 F_(D3, IP5_27_24) 100 #define GPSR0_2 F_(D2, IP5_23_20) 101 #define GPSR0_1 F_(D1, IP5_19_16) 102 #define GPSR0_0 F_(D0, IP5_15_12) 103 104 /* GPSR1 */ 105 #define GPSR1_28 FM(CLKOUT) 106 #define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8) 107 #define GPSR1_26 F_(WE1_N, IP5_7_4) 108 #define GPSR1_25 F_(WE0_N, IP5_3_0) 109 #define GPSR1_24 F_(RD_WR_N, IP4_31_28) 110 #define GPSR1_23 F_(RD_N, IP4_27_24) 111 #define GPSR1_22 F_(BS_N, IP4_23_20) 112 #define GPSR1_21 F_(CS1_N, IP4_19_16) 113 #define GPSR1_20 F_(CS0_N, IP4_15_12) 114 #define GPSR1_19 F_(A19, IP4_11_8) 115 #define GPSR1_18 F_(A18, IP4_7_4) 116 #define GPSR1_17 F_(A17, IP4_3_0) 117 #define GPSR1_16 F_(A16, IP3_31_28) 118 #define GPSR1_15 F_(A15, IP3_27_24) 119 #define GPSR1_14 F_(A14, IP3_23_20) 120 #define GPSR1_13 F_(A13, IP3_19_16) 121 #define GPSR1_12 F_(A12, IP3_15_12) 122 #define GPSR1_11 F_(A11, IP3_11_8) 123 #define GPSR1_10 F_(A10, IP3_7_4) 124 #define GPSR1_9 F_(A9, IP3_3_0) 125 #define GPSR1_8 F_(A8, IP2_31_28) 126 #define GPSR1_7 F_(A7, IP2_27_24) 127 #define GPSR1_6 F_(A6, IP2_23_20) 128 #define GPSR1_5 F_(A5, IP2_19_16) 129 #define GPSR1_4 F_(A4, IP2_15_12) 130 #define GPSR1_3 F_(A3, IP2_11_8) 131 #define GPSR1_2 F_(A2, IP2_7_4) 132 #define GPSR1_1 F_(A1, IP2_3_0) 133 #define GPSR1_0 F_(A0, IP1_31_28) 134 135 /* GPSR2 */ 136 #define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20) 137 #define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16) 138 #define GPSR2_12 F_(AVB_LINK, IP0_15_12) 139 #define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8) 140 #define GPSR2_10 F_(AVB_MAGIC, IP0_7_4) 141 #define GPSR2_9 F_(AVB_MDC, IP0_3_0) 142 #define GPSR2_8 F_(PWM2_A, IP1_27_24) 143 #define GPSR2_7 F_(PWM1_A, IP1_23_20) 144 #define GPSR2_6 F_(PWM0, IP1_19_16) 145 #define GPSR2_5 F_(IRQ5, IP1_15_12) 146 #define GPSR2_4 F_(IRQ4, IP1_11_8) 147 #define GPSR2_3 F_(IRQ3, IP1_7_4) 148 #define GPSR2_2 F_(IRQ2, IP1_3_0) 149 #define GPSR2_1 F_(IRQ1, IP0_31_28) 150 #define GPSR2_0 F_(IRQ0, IP0_27_24) 151 152 /* GPSR3 */ 153 #define GPSR3_15 F_(SD1_WP, IP11_23_20) 154 #define GPSR3_14 F_(SD1_CD, IP11_19_16) 155 #define GPSR3_13 F_(SD0_WP, IP11_15_12) 156 #define GPSR3_12 F_(SD0_CD, IP11_11_8) 157 #define GPSR3_11 F_(SD1_DAT3, IP8_31_28) 158 #define GPSR3_10 F_(SD1_DAT2, IP8_27_24) 159 #define GPSR3_9 F_(SD1_DAT1, IP8_23_20) 160 #define GPSR3_8 F_(SD1_DAT0, IP8_19_16) 161 #define GPSR3_7 F_(SD1_CMD, IP8_15_12) 162 #define GPSR3_6 F_(SD1_CLK, IP8_11_8) 163 #define GPSR3_5 F_(SD0_DAT3, IP8_7_4) 164 #define GPSR3_4 F_(SD0_DAT2, IP8_3_0) 165 #define GPSR3_3 F_(SD0_DAT1, IP7_31_28) 166 #define GPSR3_2 F_(SD0_DAT0, IP7_27_24) 167 #define GPSR3_1 F_(SD0_CMD, IP7_23_20) 168 #define GPSR3_0 F_(SD0_CLK, IP7_19_16) 169 170 /* GPSR4 */ 171 #define GPSR4_17 F_(SD3_DS, IP11_7_4) 172 #define GPSR4_16 F_(SD3_DAT7, IP11_3_0) 173 #define GPSR4_15 F_(SD3_DAT6, IP10_31_28) 174 #define GPSR4_14 F_(SD3_DAT5, IP10_27_24) 175 #define GPSR4_13 F_(SD3_DAT4, IP10_23_20) 176 #define GPSR4_12 F_(SD3_DAT3, IP10_19_16) 177 #define GPSR4_11 F_(SD3_DAT2, IP10_15_12) 178 #define GPSR4_10 F_(SD3_DAT1, IP10_11_8) 179 #define GPSR4_9 F_(SD3_DAT0, IP10_7_4) 180 #define GPSR4_8 F_(SD3_CMD, IP10_3_0) 181 #define GPSR4_7 F_(SD3_CLK, IP9_31_28) 182 #define GPSR4_6 F_(SD2_DS, IP9_27_24) 183 #define GPSR4_5 F_(SD2_DAT3, IP9_23_20) 184 #define GPSR4_4 F_(SD2_DAT2, IP9_19_16) 185 #define GPSR4_3 F_(SD2_DAT1, IP9_15_12) 186 #define GPSR4_2 F_(SD2_DAT0, IP9_11_8) 187 #define GPSR4_1 F_(SD2_CMD, IP9_7_4) 188 #define GPSR4_0 F_(SD2_CLK, IP9_3_0) 189 190 /* GPSR5 */ 191 #define GPSR5_25 F_(MLB_DAT, IP14_19_16) 192 #define GPSR5_24 F_(MLB_SIG, IP14_15_12) 193 #define GPSR5_23 F_(MLB_CLK, IP14_11_8) 194 #define GPSR5_22 FM(MSIOF0_RXD) 195 #define GPSR5_21 F_(MSIOF0_SS2, IP14_7_4) 196 #define GPSR5_20 FM(MSIOF0_TXD) 197 #define GPSR5_19 F_(MSIOF0_SS1, IP14_3_0) 198 #define GPSR5_18 F_(MSIOF0_SYNC, IP13_31_28) 199 #define GPSR5_17 FM(MSIOF0_SCK) 200 #define GPSR5_16 F_(HRTS0_N, IP13_27_24) 201 #define GPSR5_15 F_(HCTS0_N, IP13_23_20) 202 #define GPSR5_14 F_(HTX0, IP13_19_16) 203 #define GPSR5_13 F_(HRX0, IP13_15_12) 204 #define GPSR5_12 F_(HSCK0, IP13_11_8) 205 #define GPSR5_11 F_(RX2_A, IP13_7_4) 206 #define GPSR5_10 F_(TX2_A, IP13_3_0) 207 #define GPSR5_9 F_(SCK2, IP12_31_28) 208 #define GPSR5_8 F_(RTS1_N, IP12_27_24) 209 #define GPSR5_7 F_(CTS1_N, IP12_23_20) 210 #define GPSR5_6 F_(TX1_A, IP12_19_16) 211 #define GPSR5_5 F_(RX1_A, IP12_15_12) 212 #define GPSR5_4 F_(RTS0_N, IP12_11_8) 213 #define GPSR5_3 F_(CTS0_N, IP12_7_4) 214 #define GPSR5_2 F_(TX0, IP12_3_0) 215 #define GPSR5_1 F_(RX0, IP11_31_28) 216 #define GPSR5_0 F_(SCK0, IP11_27_24) 217 218 /* GPSR6 */ 219 #define GPSR6_31 F_(GP6_31, IP18_7_4) 220 #define GPSR6_30 F_(GP6_30, IP18_3_0) 221 #define GPSR6_29 F_(USB30_OVC, IP17_31_28) 222 #define GPSR6_28 F_(USB30_PWEN, IP17_27_24) 223 #define GPSR6_27 F_(USB1_OVC, IP17_23_20) 224 #define GPSR6_26 F_(USB1_PWEN, IP17_19_16) 225 #define GPSR6_25 F_(USB0_OVC, IP17_15_12) 226 #define GPSR6_24 F_(USB0_PWEN, IP17_11_8) 227 #define GPSR6_23 F_(AUDIO_CLKB_B, IP17_7_4) 228 #define GPSR6_22 F_(AUDIO_CLKA_A, IP17_3_0) 229 #define GPSR6_21 F_(SSI_SDATA9_A, IP16_31_28) 230 #define GPSR6_20 F_(SSI_SDATA8, IP16_27_24) 231 #define GPSR6_19 F_(SSI_SDATA7, IP16_23_20) 232 #define GPSR6_18 F_(SSI_WS78, IP16_19_16) 233 #define GPSR6_17 F_(SSI_SCK78, IP16_15_12) 234 #define GPSR6_16 F_(SSI_SDATA6, IP16_11_8) 235 #define GPSR6_15 F_(SSI_WS6, IP16_7_4) 236 #define GPSR6_14 F_(SSI_SCK6, IP16_3_0) 237 #define GPSR6_13 FM(SSI_SDATA5) 238 #define GPSR6_12 FM(SSI_WS5) 239 #define GPSR6_11 FM(SSI_SCK5) 240 #define GPSR6_10 F_(SSI_SDATA4, IP15_31_28) 241 #define GPSR6_9 F_(SSI_WS4, IP15_27_24) 242 #define GPSR6_8 F_(SSI_SCK4, IP15_23_20) 243 #define GPSR6_7 F_(SSI_SDATA3, IP15_19_16) 244 #define GPSR6_6 F_(SSI_WS349, IP15_15_12) 245 #define GPSR6_5 F_(SSI_SCK349, IP15_11_8) 246 #define GPSR6_4 F_(SSI_SDATA2_A, IP15_7_4) 247 #define GPSR6_3 F_(SSI_SDATA1_A, IP15_3_0) 248 #define GPSR6_2 F_(SSI_SDATA0, IP14_31_28) 249 #define GPSR6_1 F_(SSI_WS01239, IP14_27_24) 250 #define GPSR6_0 F_(SSI_SCK01239, IP14_23_20) 251 252 /* GPSR7 */ 253 #define GPSR7_3 FM(GP7_03) 254 #define GPSR7_2 FM(GP7_02) 255 #define GPSR7_1 FM(AVS2) 256 #define GPSR7_0 FM(AVS1) 257 258 259 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ 260 #define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 261 #define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 262 #define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 263 #define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 264 #define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) FM(FSCLKST2_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 265 #define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 266 #define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 267 #define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 268 #define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 269 #define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) F_(0, 0) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 270 #define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) F_(0, 0) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 271 #define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) F_(0, 0) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) FM(FSCLKST2_N_B) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 272 #define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)F_(0, 0) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 273 #define IP1_23_20 FM(PWM1_A) F_(0, 0) F_(0, 0) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 274 #define IP1_27_24 FM(PWM2_A) F_(0, 0) F_(0, 0) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 275 #define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 276 #define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 277 #define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 278 #define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 279 #define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 280 #define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 281 #define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 282 #define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 283 #define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 284 #define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 285 #define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 286 #define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 287 288 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ 289 #define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 290 #define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 291 #define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 292 #define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 293 #define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 294 #define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 295 #define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 296 #define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 297 #define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 298 #define IP4_19_16 FM(CS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 299 #define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 300 #define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 301 #define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 302 #define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 303 #define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 304 #define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 305 #define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 306 #define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 307 #define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 308 #define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 309 #define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 310 #define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 311 #define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 312 #define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 313 #define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 314 #define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 315 #define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 316 #define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_C) FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 317 #define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 318 319 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ 320 #define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 321 #define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 322 #define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 323 #define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 324 #define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 325 #define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 326 #define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 327 #define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 328 #define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 329 #define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 330 #define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) FM(NFCE_N_B) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 331 #define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) FM(NFWP_N_B) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 332 #define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) FM(NFDATA14_B) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 333 #define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) FM(NFDATA15_B) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 334 #define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) FM(NFRB_N_B) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 335 #define IP9_3_0 FM(SD2_CLK) F_(0, 0) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 336 #define IP9_7_4 FM(SD2_CMD) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 337 #define IP9_11_8 FM(SD2_DAT0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 338 #define IP9_15_12 FM(SD2_DAT1) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 339 #define IP9_19_16 FM(SD2_DAT2) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 340 #define IP9_23_20 FM(SD2_DAT3) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 341 #define IP9_27_24 FM(SD2_DS) F_(0, 0) FM(NFALE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 342 #define IP9_31_28 FM(SD3_CLK) F_(0, 0) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 343 #define IP10_3_0 FM(SD3_CMD) F_(0, 0) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 344 #define IP10_7_4 FM(SD3_DAT0) F_(0, 0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 345 #define IP10_11_8 FM(SD3_DAT1) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 346 #define IP10_15_12 FM(SD3_DAT2) F_(0, 0) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 347 #define IP10_19_16 FM(SD3_DAT3) F_(0, 0) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 348 #define IP10_23_20 FM(SD3_DAT4) FM(SD2_CD_A) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 349 #define IP10_27_24 FM(SD3_DAT5) FM(SD2_WP_A) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 350 #define IP10_31_28 FM(SD3_DAT6) FM(SD3_CD) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 351 #define IP11_3_0 FM(SD3_DAT7) FM(SD3_WP) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 352 #define IP11_7_4 FM(SD3_DS) F_(0, 0) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 353 #define IP11_11_8 FM(SD0_CD) F_(0, 0) FM(NFDATA14_A) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 354 355 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ 356 #define IP11_15_12 FM(SD0_WP) F_(0, 0) FM(NFDATA15_A) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 357 #define IP11_19_16 FM(SD1_CD) F_(0, 0) FM(NFRB_N_A) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 358 #define IP11_23_20 FM(SD1_WP) F_(0, 0) FM(NFCE_N_A) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 359 #define IP11_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 360 #define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 361 #define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 362 #define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 363 #define IP12_11_8 FM(RTS0_N) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 364 #define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 365 #define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 366 #define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 367 #define IP12_27_24 FM(RTS1_N) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 368 #define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 369 #define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 370 #define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 371 #define IP13_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 372 #define IP13_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 373 #define IP13_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 374 #define IP13_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 375 #define IP13_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 376 #define IP13_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) FM(TX5_B) F_(0, 0) F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0) 377 #define IP14_3_0 FM(MSIOF0_SS1) FM(RX5_A) FM(NFWP_N_A) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 378 #define IP14_7_4 FM(MSIOF0_SS2) FM(TX5_A) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 379 #define IP14_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 380 #define IP14_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 381 #define IP14_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 382 #define IP14_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 383 #define IP14_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 384 385 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ 386 #define IP14_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 387 #define IP15_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 388 #define IP15_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 389 #define IP15_11_8 FM(SSI_SCK349) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 390 #define IP15_15_12 FM(SSI_WS349) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 391 #define IP15_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 392 #define IP15_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 393 #define IP15_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 394 #define IP15_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 395 #define IP16_3_0 FM(SSI_SCK6) F_(0, 0) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 396 #define IP16_7_4 FM(SSI_WS6) F_(0, 0) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 397 #define IP16_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 398 #define IP16_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 399 #define IP16_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 400 #define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 401 #define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 402 #define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 403 #define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 404 #define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 405 #define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0) 406 #define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0) 407 #define IP17_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0) 408 #define IP17_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0) 409 #define IP17_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0) 410 #define IP17_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_N) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 411 #define IP18_3_0 FM(GP6_30) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0) 412 #define IP18_7_4 FM(GP6_31) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0) 413 414 #define PINMUX_GPSR \ 415 \ 416 GPSR6_31 \ 417 GPSR6_30 \ 418 GPSR6_29 \ 419 GPSR1_28 GPSR6_28 \ 420 GPSR1_27 GPSR6_27 \ 421 GPSR1_26 GPSR6_26 \ 422 GPSR1_25 GPSR5_25 GPSR6_25 \ 423 GPSR1_24 GPSR5_24 GPSR6_24 \ 424 GPSR1_23 GPSR5_23 GPSR6_23 \ 425 GPSR1_22 GPSR5_22 GPSR6_22 \ 426 GPSR1_21 GPSR5_21 GPSR6_21 \ 427 GPSR1_20 GPSR5_20 GPSR6_20 \ 428 GPSR1_19 GPSR5_19 GPSR6_19 \ 429 GPSR1_18 GPSR5_18 GPSR6_18 \ 430 GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \ 431 GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \ 432 GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \ 433 GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \ 434 GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \ 435 GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \ 436 GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \ 437 GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \ 438 GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \ 439 GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \ 440 GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \ 441 GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \ 442 GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \ 443 GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \ 444 GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \ 445 GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \ 446 GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \ 447 GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0 448 449 #define PINMUX_IPSR \ 450 \ 451 FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \ 452 FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \ 453 FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \ 454 FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \ 455 FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \ 456 FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \ 457 FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \ 458 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \ 459 \ 460 FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \ 461 FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \ 462 FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \ 463 FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 \ 464 FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \ 465 FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \ 466 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \ 467 FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \ 468 \ 469 FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \ 470 FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \ 471 FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \ 472 FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \ 473 FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \ 474 FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \ 475 FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \ 476 FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \ 477 \ 478 FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \ 479 FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \ 480 FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \ 481 FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \ 482 FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \ 483 FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \ 484 FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \ 485 FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \ 486 \ 487 FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 FM(IP18_3_0) IP18_3_0 \ 488 FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 FM(IP18_7_4) IP18_7_4 \ 489 FM(IP16_11_8) IP16_11_8 FM(IP17_11_8) IP17_11_8 \ 490 FM(IP16_15_12) IP16_15_12 FM(IP17_15_12) IP17_15_12 \ 491 FM(IP16_19_16) IP16_19_16 FM(IP17_19_16) IP17_19_16 \ 492 FM(IP16_23_20) IP16_23_20 FM(IP17_23_20) IP17_23_20 \ 493 FM(IP16_27_24) IP16_27_24 FM(IP17_27_24) IP17_27_24 \ 494 FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28 495 496 /* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ 497 #define MOD_SEL0_31_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3) FM(SEL_MSIOF3_4) F_(0, 0) F_(0, 0) F_(0, 0) 498 #define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3) 499 #define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0) 500 #define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1) 501 #define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1) 502 #define MOD_SEL0_21 FM(SEL_I2C2_0) FM(SEL_I2C2_1) 503 #define MOD_SEL0_20 FM(SEL_I2C1_0) FM(SEL_I2C1_1) 504 #define MOD_SEL0_19 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1) 505 #define MOD_SEL0_18_17 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3) 506 #define MOD_SEL0_16 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1) 507 #define MOD_SEL0_14_13 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) FM(SEL_HSCIF2_2) F_(0, 0) 508 #define MOD_SEL0_12 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1) 509 #define MOD_SEL0_11 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1) 510 #define MOD_SEL0_10 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1) 511 #define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0) 512 #define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0) 513 #define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1) 514 #define MOD_SEL0_4_3 FM(SEL_ADGA_0) FM(SEL_ADGA_1) FM(SEL_ADGA_2) FM(SEL_ADGA_3) 515 516 /* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ 517 #define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3) 518 #define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0) 519 #define MOD_SEL1_26 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1) 520 #define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3) 521 #define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0) 522 #define MOD_SEL1_20 FM(SEL_SSI1_0) FM(SEL_SSI1_1) 523 #define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1) 524 #define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3) 525 #define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1) 526 #define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0) 527 #define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1) 528 #define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1) 529 #define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1) 530 #define MOD_SEL1_10 FM(SEL_SCIF_0) FM(SEL_SCIF_1) 531 #define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1) 532 #define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1) 533 #define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1) 534 #define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1) 535 #define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1) 536 #define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1) 537 #define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1) 538 #define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1) 539 540 /* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ 541 #define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1) 542 #define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1) 543 #define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1) 544 #define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3) 545 #define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1) 546 #define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 547 #define MOD_SEL2_22 FM(SEL_NDF_0) FM(SEL_NDF_1) 548 #define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1) 549 #define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1) 550 #define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1) 551 #define MOD_SEL2_18 FM(SEL_ADGB_0) FM(SEL_ADGB_1) 552 #define MOD_SEL2_17 FM(SEL_ADGC_0) FM(SEL_ADGC_1) 553 #define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1) 554 555 #define PINMUX_MOD_SELS \ 556 \ 557 MOD_SEL0_31_30_29 MOD_SEL1_31_30 MOD_SEL2_31 \ 558 MOD_SEL2_30 \ 559 MOD_SEL1_29_28_27 MOD_SEL2_29 \ 560 MOD_SEL0_28_27 MOD_SEL2_28_27 \ 561 MOD_SEL0_26_25_24 MOD_SEL1_26 MOD_SEL2_26 \ 562 MOD_SEL1_25_24 MOD_SEL2_25_24_23 \ 563 MOD_SEL0_23 MOD_SEL1_23_22_21 \ 564 MOD_SEL0_22 MOD_SEL2_22 \ 565 MOD_SEL0_21 MOD_SEL2_21 \ 566 MOD_SEL0_20 MOD_SEL1_20 MOD_SEL2_20 \ 567 MOD_SEL0_19 MOD_SEL1_19 MOD_SEL2_19 \ 568 MOD_SEL0_18_17 MOD_SEL1_18_17 MOD_SEL2_18 \ 569 MOD_SEL2_17 \ 570 MOD_SEL0_16 MOD_SEL1_16 \ 571 MOD_SEL1_15_14 \ 572 MOD_SEL0_14_13 \ 573 MOD_SEL1_13 \ 574 MOD_SEL0_12 MOD_SEL1_12 \ 575 MOD_SEL0_11 MOD_SEL1_11 \ 576 MOD_SEL0_10 MOD_SEL1_10 \ 577 MOD_SEL0_9_8 MOD_SEL1_9 \ 578 MOD_SEL0_7_6 \ 579 MOD_SEL1_6 \ 580 MOD_SEL0_5 MOD_SEL1_5 \ 581 MOD_SEL0_4_3 MOD_SEL1_4 \ 582 MOD_SEL1_3 \ 583 MOD_SEL1_2 \ 584 MOD_SEL1_1 \ 585 MOD_SEL1_0 MOD_SEL2_0 586 587 /* 588 * These pins are not able to be muxed but have other properties 589 * that can be set, such as drive-strength or pull-up/pull-down enable. 590 */ 591 #define PINMUX_STATIC \ 592 FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \ 593 FM(QSPI0_IO2) FM(QSPI0_IO3) \ 594 FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \ 595 FM(QSPI1_IO2) FM(QSPI1_IO3) \ 596 FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \ 597 FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \ 598 FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \ 599 FM(AVB_TXCREFCLK) FM(AVB_MDIO) \ 600 FM(PRESETOUT) \ 601 FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN3) \ 602 FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR) 603 604 #define PINMUX_PHYS \ 605 FM(SCL0) FM(SDA0) FM(SCL3) FM(SDA3) FM(SCL5) FM(SDA5) 606 607 enum { 608 PINMUX_RESERVED = 0, 609 610 PINMUX_DATA_BEGIN, 611 GP_ALL(DATA), 612 PINMUX_DATA_END, 613 614 #define F_(x, y) 615 #define FM(x) FN_##x, 616 PINMUX_FUNCTION_BEGIN, 617 GP_ALL(FN), 618 PINMUX_GPSR 619 PINMUX_IPSR 620 PINMUX_MOD_SELS 621 PINMUX_FUNCTION_END, 622 #undef F_ 623 #undef FM 624 625 #define F_(x, y) 626 #define FM(x) x##_MARK, 627 PINMUX_MARK_BEGIN, 628 PINMUX_GPSR 629 PINMUX_IPSR 630 PINMUX_MOD_SELS 631 PINMUX_STATIC 632 PINMUX_PHYS 633 PINMUX_MARK_END, 634 #undef F_ 635 #undef FM 636 }; 637 638 static const u16 pinmux_data[] = { 639 PINMUX_DATA_GP_ALL(), 640 641 PINMUX_SINGLE(AVS1), 642 PINMUX_SINGLE(AVS2), 643 PINMUX_SINGLE(CLKOUT), 644 PINMUX_SINGLE(GP7_03), 645 PINMUX_SINGLE(GP7_02), 646 PINMUX_SINGLE(MSIOF0_RXD), 647 PINMUX_SINGLE(MSIOF0_SCK), 648 PINMUX_SINGLE(MSIOF0_TXD), 649 PINMUX_SINGLE(SSI_SCK5), 650 PINMUX_SINGLE(SSI_SDATA5), 651 PINMUX_SINGLE(SSI_WS5), 652 653 /* IPSR0 */ 654 PINMUX_IPSR_GPSR(IP0_3_0, AVB_MDC), 655 PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2), 656 657 PINMUX_IPSR_GPSR(IP0_7_4, AVB_MAGIC), 658 PINMUX_IPSR_MSEL(IP0_7_4, MSIOF2_SS1_C, SEL_MSIOF2_2), 659 PINMUX_IPSR_MSEL(IP0_7_4, SCK4_A, SEL_SCIF4_0), 660 661 PINMUX_IPSR_GPSR(IP0_11_8, AVB_PHY_INT), 662 PINMUX_IPSR_MSEL(IP0_11_8, MSIOF2_SYNC_C, SEL_MSIOF2_2), 663 PINMUX_IPSR_MSEL(IP0_11_8, RX4_A, SEL_SCIF4_0), 664 665 PINMUX_IPSR_GPSR(IP0_15_12, AVB_LINK), 666 PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2), 667 PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0), 668 PINMUX_IPSR_GPSR(IP0_19_16, FSCLKST2_N_A), 669 670 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, I2C_SEL_5_0, SEL_ETHERAVB_0), 671 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, MSIOF2_RXD_C, I2C_SEL_5_0, SEL_MSIOF2_2), 672 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, CTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0), 673 PINMUX_IPSR_PHYS(IP0_19_16, SCL5, I2C_SEL_5_1), 674 675 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, I2C_SEL_5_0, SEL_ETHERAVB_0), 676 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C, I2C_SEL_5_0, SEL_MSIOF2_2), 677 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0), 678 PINMUX_IPSR_PHYS(IP0_23_20, SDA5, I2C_SEL_5_1), 679 680 PINMUX_IPSR_GPSR(IP0_27_24, IRQ0), 681 PINMUX_IPSR_GPSR(IP0_27_24, QPOLB), 682 PINMUX_IPSR_GPSR(IP0_27_24, DU_CDE), 683 PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1), 684 PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1), 685 PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_B, SEL_CANFD0_1), 686 PINMUX_IPSR_MSEL(IP0_27_24, MSIOF3_SS2_E, SEL_MSIOF3_4), 687 688 PINMUX_IPSR_GPSR(IP0_31_28, IRQ1), 689 PINMUX_IPSR_GPSR(IP0_31_28, QPOLA), 690 PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP), 691 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1), 692 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1), 693 PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1), 694 PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_SS1_E, SEL_MSIOF3_4), 695 696 /* IPSR1 */ 697 PINMUX_IPSR_GPSR(IP1_3_0, IRQ2), 698 PINMUX_IPSR_GPSR(IP1_3_0, QCPV_QDE), 699 PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE), 700 PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1), 701 PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1), 702 PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_SYNC_E, SEL_MSIOF3_4), 703 704 PINMUX_IPSR_GPSR(IP1_7_4, IRQ3), 705 PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE), 706 PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1), 707 PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1), 708 PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1), 709 PINMUX_IPSR_MSEL(IP1_7_4, MSIOF3_SCK_E, SEL_MSIOF3_4), 710 711 PINMUX_IPSR_GPSR(IP1_11_8, IRQ4), 712 PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS), 713 PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC), 714 PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1), 715 PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1), 716 PINMUX_IPSR_MSEL(IP1_11_8, MSIOF3_RXD_E, SEL_MSIOF3_4), 717 718 PINMUX_IPSR_GPSR(IP1_15_12, IRQ5), 719 PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE), 720 PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC), 721 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1), 722 PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1), 723 PINMUX_IPSR_GPSR(IP1_15_12, FSCLKST2_N_B), 724 PINMUX_IPSR_MSEL(IP1_15_12, MSIOF3_TXD_E, SEL_MSIOF3_4), 725 726 PINMUX_IPSR_GPSR(IP1_19_16, PWM0), 727 PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS), 728 PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1), 729 PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1), 730 731 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, PWM1_A, I2C_SEL_3_0, SEL_PWM1_0), 732 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3), 733 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1), 734 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1), 735 PINMUX_IPSR_PHYS(IP1_23_20, SCL3, I2C_SEL_3_1), 736 737 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0), 738 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D, I2C_SEL_3_0, SEL_HSCIF3_3), 739 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, IETX_B, I2C_SEL_3_0, SEL_IEBUS_1), 740 PINMUX_IPSR_PHYS(IP1_27_24, SDA3, I2C_SEL_3_1), 741 742 PINMUX_IPSR_GPSR(IP1_31_28, A0), 743 PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16), 744 PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SYNC_B, SEL_MSIOF3_1), 745 PINMUX_IPSR_GPSR(IP1_31_28, VI4_DATA8), 746 PINMUX_IPSR_GPSR(IP1_31_28, DU_DB0), 747 PINMUX_IPSR_MSEL(IP1_31_28, PWM3_A, SEL_PWM3_0), 748 749 /* IPSR2 */ 750 PINMUX_IPSR_GPSR(IP2_3_0, A1), 751 PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT17), 752 PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_TXD_B, SEL_MSIOF3_1), 753 PINMUX_IPSR_GPSR(IP2_3_0, VI4_DATA9), 754 PINMUX_IPSR_GPSR(IP2_3_0, DU_DB1), 755 PINMUX_IPSR_MSEL(IP2_3_0, PWM4_A, SEL_PWM4_0), 756 757 PINMUX_IPSR_GPSR(IP2_7_4, A2), 758 PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT18), 759 PINMUX_IPSR_MSEL(IP2_7_4, MSIOF3_SCK_B, SEL_MSIOF3_1), 760 PINMUX_IPSR_GPSR(IP2_7_4, VI4_DATA10), 761 PINMUX_IPSR_GPSR(IP2_7_4, DU_DB2), 762 PINMUX_IPSR_MSEL(IP2_7_4, PWM5_A, SEL_PWM5_0), 763 764 PINMUX_IPSR_GPSR(IP2_11_8, A3), 765 PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT19), 766 PINMUX_IPSR_MSEL(IP2_11_8, MSIOF3_RXD_B, SEL_MSIOF3_1), 767 PINMUX_IPSR_GPSR(IP2_11_8, VI4_DATA11), 768 PINMUX_IPSR_GPSR(IP2_11_8, DU_DB3), 769 PINMUX_IPSR_MSEL(IP2_11_8, PWM6_A, SEL_PWM6_0), 770 771 PINMUX_IPSR_GPSR(IP2_15_12, A4), 772 PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT20), 773 PINMUX_IPSR_MSEL(IP2_15_12, MSIOF3_SS1_B, SEL_MSIOF3_1), 774 PINMUX_IPSR_GPSR(IP2_15_12, VI4_DATA12), 775 PINMUX_IPSR_GPSR(IP2_15_12, VI5_DATA12), 776 PINMUX_IPSR_GPSR(IP2_15_12, DU_DB4), 777 778 PINMUX_IPSR_GPSR(IP2_19_16, A5), 779 PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT21), 780 PINMUX_IPSR_MSEL(IP2_19_16, MSIOF3_SS2_B, SEL_MSIOF3_1), 781 PINMUX_IPSR_MSEL(IP2_19_16, SCK4_B, SEL_SCIF4_1), 782 PINMUX_IPSR_GPSR(IP2_19_16, VI4_DATA13), 783 PINMUX_IPSR_GPSR(IP2_19_16, VI5_DATA13), 784 PINMUX_IPSR_GPSR(IP2_19_16, DU_DB5), 785 786 PINMUX_IPSR_GPSR(IP2_23_20, A6), 787 PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT22), 788 PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_SS1_A, SEL_MSIOF2_0), 789 PINMUX_IPSR_MSEL(IP2_23_20, RX4_B, SEL_SCIF4_1), 790 PINMUX_IPSR_GPSR(IP2_23_20, VI4_DATA14), 791 PINMUX_IPSR_GPSR(IP2_23_20, VI5_DATA14), 792 PINMUX_IPSR_GPSR(IP2_23_20, DU_DB6), 793 794 PINMUX_IPSR_GPSR(IP2_27_24, A7), 795 PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT23), 796 PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SS2_A, SEL_MSIOF2_0), 797 PINMUX_IPSR_MSEL(IP2_27_24, TX4_B, SEL_SCIF4_1), 798 PINMUX_IPSR_GPSR(IP2_27_24, VI4_DATA15), 799 PINMUX_IPSR_GPSR(IP2_27_24, VI5_DATA15), 800 PINMUX_IPSR_GPSR(IP2_27_24, DU_DB7), 801 802 PINMUX_IPSR_GPSR(IP2_31_28, A8), 803 PINMUX_IPSR_MSEL(IP2_31_28, RX3_B, SEL_SCIF3_1), 804 PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0), 805 PINMUX_IPSR_MSEL(IP2_31_28, HRX4_B, SEL_HSCIF4_1), 806 PINMUX_IPSR_MSEL(IP2_31_28, SDA6_A, SEL_I2C6_0), 807 PINMUX_IPSR_MSEL(IP2_31_28, AVB_AVTP_MATCH_B, SEL_ETHERAVB_1), 808 PINMUX_IPSR_MSEL(IP2_31_28, PWM1_B, SEL_PWM1_1), 809 810 /* IPSR3 */ 811 PINMUX_IPSR_GPSR(IP3_3_0, A9), 812 PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0), 813 PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1), 814 PINMUX_IPSR_GPSR(IP3_3_0, VI5_VSYNC_N), 815 816 PINMUX_IPSR_GPSR(IP3_7_4, A10), 817 PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0), 818 PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_B, SEL_SCIF4_1), 819 PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N), 820 821 PINMUX_IPSR_GPSR(IP3_11_8, A11), 822 PINMUX_IPSR_MSEL(IP3_11_8, TX3_B, SEL_SCIF3_1), 823 PINMUX_IPSR_MSEL(IP3_11_8, MSIOF2_TXD_A, SEL_MSIOF2_0), 824 PINMUX_IPSR_MSEL(IP3_11_8, HTX4_B, SEL_HSCIF4_1), 825 PINMUX_IPSR_GPSR(IP3_11_8, HSCK4), 826 PINMUX_IPSR_GPSR(IP3_11_8, VI5_FIELD), 827 PINMUX_IPSR_MSEL(IP3_11_8, SCL6_A, SEL_I2C6_0), 828 PINMUX_IPSR_MSEL(IP3_11_8, AVB_AVTP_CAPTURE_B, SEL_ETHERAVB_1), 829 PINMUX_IPSR_MSEL(IP3_11_8, PWM2_B, SEL_PWM2_1), 830 831 PINMUX_IPSR_GPSR(IP3_15_12, A12), 832 PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT12), 833 PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SCK_C, SEL_MSIOF3_2), 834 PINMUX_IPSR_MSEL(IP3_15_12, HRX4_A, SEL_HSCIF4_0), 835 PINMUX_IPSR_GPSR(IP3_15_12, VI5_DATA8), 836 PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4), 837 838 PINMUX_IPSR_GPSR(IP3_19_16, A13), 839 PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT13), 840 PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SYNC_C, SEL_MSIOF3_2), 841 PINMUX_IPSR_MSEL(IP3_19_16, HTX4_A, SEL_HSCIF4_0), 842 PINMUX_IPSR_GPSR(IP3_19_16, VI5_DATA9), 843 PINMUX_IPSR_GPSR(IP3_19_16, DU_DG5), 844 845 PINMUX_IPSR_GPSR(IP3_23_20, A14), 846 PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT14), 847 PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_C, SEL_MSIOF3_2), 848 PINMUX_IPSR_GPSR(IP3_23_20, HCTS4_N), 849 PINMUX_IPSR_GPSR(IP3_23_20, VI5_DATA10), 850 PINMUX_IPSR_GPSR(IP3_23_20, DU_DG6), 851 852 PINMUX_IPSR_GPSR(IP3_27_24, A15), 853 PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT15), 854 PINMUX_IPSR_MSEL(IP3_27_24, MSIOF3_TXD_C, SEL_MSIOF3_2), 855 PINMUX_IPSR_GPSR(IP3_27_24, HRTS4_N), 856 PINMUX_IPSR_GPSR(IP3_27_24, VI5_DATA11), 857 PINMUX_IPSR_GPSR(IP3_27_24, DU_DG7), 858 859 PINMUX_IPSR_GPSR(IP3_31_28, A16), 860 PINMUX_IPSR_GPSR(IP3_31_28, LCDOUT8), 861 PINMUX_IPSR_GPSR(IP3_31_28, VI4_FIELD), 862 PINMUX_IPSR_GPSR(IP3_31_28, DU_DG0), 863 864 /* IPSR4 */ 865 PINMUX_IPSR_GPSR(IP4_3_0, A17), 866 PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT9), 867 PINMUX_IPSR_GPSR(IP4_3_0, VI4_VSYNC_N), 868 PINMUX_IPSR_GPSR(IP4_3_0, DU_DG1), 869 870 PINMUX_IPSR_GPSR(IP4_7_4, A18), 871 PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT10), 872 PINMUX_IPSR_GPSR(IP4_7_4, VI4_HSYNC_N), 873 PINMUX_IPSR_GPSR(IP4_7_4, DU_DG2), 874 875 PINMUX_IPSR_GPSR(IP4_11_8, A19), 876 PINMUX_IPSR_GPSR(IP4_11_8, LCDOUT11), 877 PINMUX_IPSR_GPSR(IP4_11_8, VI4_CLKENB), 878 PINMUX_IPSR_GPSR(IP4_11_8, DU_DG3), 879 880 PINMUX_IPSR_GPSR(IP4_15_12, CS0_N), 881 PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB), 882 883 PINMUX_IPSR_GPSR(IP4_19_16, CS1_N), 884 PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK), 885 PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1), 886 887 PINMUX_IPSR_GPSR(IP4_23_20, BS_N), 888 PINMUX_IPSR_GPSR(IP4_23_20, QSTVA_QVS), 889 PINMUX_IPSR_MSEL(IP4_23_20, MSIOF3_SCK_D, SEL_MSIOF3_3), 890 PINMUX_IPSR_GPSR(IP4_23_20, SCK3), 891 PINMUX_IPSR_GPSR(IP4_23_20, HSCK3), 892 PINMUX_IPSR_GPSR(IP4_23_20, CAN1_TX), 893 PINMUX_IPSR_GPSR(IP4_23_20, CANFD1_TX), 894 PINMUX_IPSR_MSEL(IP4_23_20, IETX_A, SEL_IEBUS_0), 895 896 PINMUX_IPSR_GPSR(IP4_27_24, RD_N), 897 PINMUX_IPSR_MSEL(IP4_27_24, MSIOF3_SYNC_D, SEL_MSIOF3_3), 898 PINMUX_IPSR_MSEL(IP4_27_24, RX3_A, SEL_SCIF3_0), 899 PINMUX_IPSR_MSEL(IP4_27_24, HRX3_A, SEL_HSCIF3_0), 900 PINMUX_IPSR_MSEL(IP4_27_24, CAN0_TX_A, SEL_RCAN0_0), 901 PINMUX_IPSR_MSEL(IP4_27_24, CANFD0_TX_A, SEL_CANFD0_0), 902 903 PINMUX_IPSR_GPSR(IP4_31_28, RD_WR_N), 904 PINMUX_IPSR_MSEL(IP4_31_28, MSIOF3_RXD_D, SEL_MSIOF3_3), 905 PINMUX_IPSR_MSEL(IP4_31_28, TX3_A, SEL_SCIF3_0), 906 PINMUX_IPSR_MSEL(IP4_31_28, HTX3_A, SEL_HSCIF3_0), 907 PINMUX_IPSR_MSEL(IP4_31_28, CAN0_RX_A, SEL_RCAN0_0), 908 PINMUX_IPSR_MSEL(IP4_31_28, CANFD0_RX_A, SEL_CANFD0_0), 909 910 /* IPSR5 */ 911 PINMUX_IPSR_GPSR(IP5_3_0, WE0_N), 912 PINMUX_IPSR_MSEL(IP5_3_0, MSIOF3_TXD_D, SEL_MSIOF3_3), 913 PINMUX_IPSR_GPSR(IP5_3_0, CTS3_N), 914 PINMUX_IPSR_GPSR(IP5_3_0, HCTS3_N), 915 PINMUX_IPSR_MSEL(IP5_3_0, SCL6_B, SEL_I2C6_1), 916 PINMUX_IPSR_GPSR(IP5_3_0, CAN_CLK), 917 PINMUX_IPSR_MSEL(IP5_3_0, IECLK_A, SEL_IEBUS_0), 918 919 PINMUX_IPSR_GPSR(IP5_7_4, WE1_N), 920 PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3), 921 PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N), 922 PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N), 923 PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1), 924 PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX), 925 PINMUX_IPSR_GPSR(IP5_7_4, CANFD1_RX), 926 PINMUX_IPSR_MSEL(IP5_7_4, IERX_A, SEL_IEBUS_0), 927 928 PINMUX_IPSR_MSEL(IP5_11_8, EX_WAIT0_A, SEL_LBSC_0), 929 PINMUX_IPSR_GPSR(IP5_11_8, QCLK), 930 PINMUX_IPSR_GPSR(IP5_11_8, VI4_CLK), 931 PINMUX_IPSR_GPSR(IP5_11_8, DU_DOTCLKOUT0), 932 933 PINMUX_IPSR_GPSR(IP5_15_12, D0), 934 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF2_SS1_B, SEL_MSIOF2_1), 935 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF3_SCK_A, SEL_MSIOF3_0), 936 PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA16), 937 PINMUX_IPSR_GPSR(IP5_15_12, VI5_DATA0), 938 939 PINMUX_IPSR_GPSR(IP5_19_16, D1), 940 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF2_SS2_B, SEL_MSIOF2_1), 941 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF3_SYNC_A, SEL_MSIOF3_0), 942 PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA17), 943 PINMUX_IPSR_GPSR(IP5_19_16, VI5_DATA1), 944 945 PINMUX_IPSR_GPSR(IP5_23_20, D2), 946 PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_RXD_A, SEL_MSIOF3_0), 947 PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA18), 948 PINMUX_IPSR_GPSR(IP5_23_20, VI5_DATA2), 949 950 PINMUX_IPSR_GPSR(IP5_27_24, D3), 951 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0), 952 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19), 953 PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3), 954 955 PINMUX_IPSR_GPSR(IP5_31_28, D4), 956 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF2_SCK_B, SEL_MSIOF2_1), 957 PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA20), 958 PINMUX_IPSR_GPSR(IP5_31_28, VI5_DATA4), 959 960 /* IPSR6 */ 961 PINMUX_IPSR_GPSR(IP6_3_0, D5), 962 PINMUX_IPSR_MSEL(IP6_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1), 963 PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA21), 964 PINMUX_IPSR_GPSR(IP6_3_0, VI5_DATA5), 965 966 PINMUX_IPSR_GPSR(IP6_7_4, D6), 967 PINMUX_IPSR_MSEL(IP6_7_4, MSIOF2_RXD_B, SEL_MSIOF2_1), 968 PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA22), 969 PINMUX_IPSR_GPSR(IP6_7_4, VI5_DATA6), 970 971 PINMUX_IPSR_GPSR(IP6_11_8, D7), 972 PINMUX_IPSR_MSEL(IP6_11_8, MSIOF2_TXD_B, SEL_MSIOF2_1), 973 PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA23), 974 PINMUX_IPSR_GPSR(IP6_11_8, VI5_DATA7), 975 976 PINMUX_IPSR_GPSR(IP6_15_12, D8), 977 PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT0), 978 PINMUX_IPSR_MSEL(IP6_15_12, MSIOF2_SCK_D, SEL_MSIOF2_3), 979 PINMUX_IPSR_MSEL(IP6_15_12, SCK4_C, SEL_SCIF4_2), 980 PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA0_A, SEL_VIN4_0), 981 PINMUX_IPSR_GPSR(IP6_15_12, DU_DR0), 982 983 PINMUX_IPSR_GPSR(IP6_19_16, D9), 984 PINMUX_IPSR_GPSR(IP6_19_16, LCDOUT1), 985 PINMUX_IPSR_MSEL(IP6_19_16, MSIOF2_SYNC_D, SEL_MSIOF2_3), 986 PINMUX_IPSR_MSEL(IP6_19_16, VI4_DATA1_A, SEL_VIN4_0), 987 PINMUX_IPSR_GPSR(IP6_19_16, DU_DR1), 988 989 PINMUX_IPSR_GPSR(IP6_23_20, D10), 990 PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT2), 991 PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_RXD_D, SEL_MSIOF2_3), 992 PINMUX_IPSR_MSEL(IP6_23_20, HRX3_B, SEL_HSCIF3_1), 993 PINMUX_IPSR_MSEL(IP6_23_20, VI4_DATA2_A, SEL_VIN4_0), 994 PINMUX_IPSR_MSEL(IP6_23_20, CTS4_N_C, SEL_SCIF4_2), 995 PINMUX_IPSR_GPSR(IP6_23_20, DU_DR2), 996 997 PINMUX_IPSR_GPSR(IP6_27_24, D11), 998 PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT3), 999 PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3), 1000 PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1), 1001 PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0), 1002 PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_C, SEL_SCIF4_2), 1003 PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3), 1004 1005 PINMUX_IPSR_GPSR(IP6_31_28, D12), 1006 PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT4), 1007 PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3), 1008 PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2), 1009 PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0), 1010 PINMUX_IPSR_GPSR(IP6_31_28, DU_DR4), 1011 1012 /* IPSR7 */ 1013 PINMUX_IPSR_GPSR(IP7_3_0, D13), 1014 PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT5), 1015 PINMUX_IPSR_MSEL(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3), 1016 PINMUX_IPSR_MSEL(IP7_3_0, TX4_C, SEL_SCIF4_2), 1017 PINMUX_IPSR_MSEL(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0), 1018 PINMUX_IPSR_GPSR(IP7_3_0, DU_DR5), 1019 1020 PINMUX_IPSR_GPSR(IP7_7_4, D14), 1021 PINMUX_IPSR_GPSR(IP7_7_4, LCDOUT6), 1022 PINMUX_IPSR_MSEL(IP7_7_4, MSIOF3_SS1_A, SEL_MSIOF3_0), 1023 PINMUX_IPSR_MSEL(IP7_7_4, HRX3_C, SEL_HSCIF3_2), 1024 PINMUX_IPSR_MSEL(IP7_7_4, VI4_DATA6_A, SEL_VIN4_0), 1025 PINMUX_IPSR_GPSR(IP7_7_4, DU_DR6), 1026 PINMUX_IPSR_MSEL(IP7_7_4, SCL6_C, SEL_I2C6_2), 1027 1028 PINMUX_IPSR_GPSR(IP7_11_8, D15), 1029 PINMUX_IPSR_GPSR(IP7_11_8, LCDOUT7), 1030 PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SS2_A, SEL_MSIOF3_0), 1031 PINMUX_IPSR_MSEL(IP7_11_8, HTX3_C, SEL_HSCIF3_2), 1032 PINMUX_IPSR_MSEL(IP7_11_8, VI4_DATA7_A, SEL_VIN4_0), 1033 PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7), 1034 PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2), 1035 1036 PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK), 1037 PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4), 1038 PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1), 1039 1040 PINMUX_IPSR_GPSR(IP7_23_20, SD0_CMD), 1041 PINMUX_IPSR_MSEL(IP7_23_20, MSIOF1_SYNC_E, SEL_MSIOF1_4), 1042 PINMUX_IPSR_MSEL(IP7_23_20, STP_IVCXO27_0_B, SEL_SSP1_0_1), 1043 1044 PINMUX_IPSR_GPSR(IP7_27_24, SD0_DAT0), 1045 PINMUX_IPSR_MSEL(IP7_27_24, MSIOF1_RXD_E, SEL_MSIOF1_4), 1046 PINMUX_IPSR_MSEL(IP7_27_24, TS_SCK0_B, SEL_TSIF0_1), 1047 PINMUX_IPSR_MSEL(IP7_27_24, STP_ISCLK_0_B, SEL_SSP1_0_1), 1048 1049 PINMUX_IPSR_GPSR(IP7_31_28, SD0_DAT1), 1050 PINMUX_IPSR_MSEL(IP7_31_28, MSIOF1_TXD_E, SEL_MSIOF1_4), 1051 PINMUX_IPSR_MSEL(IP7_31_28, TS_SPSYNC0_B, SEL_TSIF0_1), 1052 PINMUX_IPSR_MSEL(IP7_31_28, STP_ISSYNC_0_B, SEL_SSP1_0_1), 1053 1054 /* IPSR8 */ 1055 PINMUX_IPSR_GPSR(IP8_3_0, SD0_DAT2), 1056 PINMUX_IPSR_MSEL(IP8_3_0, MSIOF1_SS1_E, SEL_MSIOF1_4), 1057 PINMUX_IPSR_MSEL(IP8_3_0, TS_SDAT0_B, SEL_TSIF0_1), 1058 PINMUX_IPSR_MSEL(IP8_3_0, STP_ISD_0_B, SEL_SSP1_0_1), 1059 1060 PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT3), 1061 PINMUX_IPSR_MSEL(IP8_7_4, MSIOF1_SS2_E, SEL_MSIOF1_4), 1062 PINMUX_IPSR_MSEL(IP8_7_4, TS_SDEN0_B, SEL_TSIF0_1), 1063 PINMUX_IPSR_MSEL(IP8_7_4, STP_ISEN_0_B, SEL_SSP1_0_1), 1064 1065 PINMUX_IPSR_GPSR(IP8_11_8, SD1_CLK), 1066 PINMUX_IPSR_MSEL(IP8_11_8, MSIOF1_SCK_G, SEL_MSIOF1_6), 1067 PINMUX_IPSR_MSEL(IP8_11_8, SIM0_CLK_A, SEL_SIMCARD_0), 1068 1069 PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD), 1070 PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6), 1071 PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDF_1), 1072 PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0), 1073 PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1), 1074 1075 PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0), 1076 PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4), 1077 PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6), 1078 PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDF_1), 1079 PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1), 1080 PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1), 1081 1082 PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1), 1083 PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5), 1084 PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6), 1085 PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDF_1), 1086 PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1), 1087 PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1), 1088 1089 PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2), 1090 PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6), 1091 PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6), 1092 PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDF_1), 1093 PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1), 1094 PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1), 1095 1096 PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3), 1097 PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7), 1098 PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6), 1099 PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDF_1), 1100 PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1), 1101 PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1), 1102 1103 /* IPSR9 */ 1104 PINMUX_IPSR_GPSR(IP9_3_0, SD2_CLK), 1105 PINMUX_IPSR_GPSR(IP9_3_0, NFDATA8), 1106 1107 PINMUX_IPSR_GPSR(IP9_7_4, SD2_CMD), 1108 PINMUX_IPSR_GPSR(IP9_7_4, NFDATA9), 1109 1110 PINMUX_IPSR_GPSR(IP9_11_8, SD2_DAT0), 1111 PINMUX_IPSR_GPSR(IP9_11_8, NFDATA10), 1112 1113 PINMUX_IPSR_GPSR(IP9_15_12, SD2_DAT1), 1114 PINMUX_IPSR_GPSR(IP9_15_12, NFDATA11), 1115 1116 PINMUX_IPSR_GPSR(IP9_19_16, SD2_DAT2), 1117 PINMUX_IPSR_GPSR(IP9_19_16, NFDATA12), 1118 1119 PINMUX_IPSR_GPSR(IP9_23_20, SD2_DAT3), 1120 PINMUX_IPSR_GPSR(IP9_23_20, NFDATA13), 1121 1122 PINMUX_IPSR_GPSR(IP9_27_24, SD2_DS), 1123 PINMUX_IPSR_GPSR(IP9_27_24, NFALE), 1124 PINMUX_IPSR_GPSR(IP9_27_24, SATA_DEVSLP_B), 1125 1126 PINMUX_IPSR_GPSR(IP9_31_28, SD3_CLK), 1127 PINMUX_IPSR_GPSR(IP9_31_28, NFWE_N), 1128 1129 /* IPSR10 */ 1130 PINMUX_IPSR_GPSR(IP10_3_0, SD3_CMD), 1131 PINMUX_IPSR_GPSR(IP10_3_0, NFRE_N), 1132 1133 PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT0), 1134 PINMUX_IPSR_GPSR(IP10_7_4, NFDATA0), 1135 1136 PINMUX_IPSR_GPSR(IP10_11_8, SD3_DAT1), 1137 PINMUX_IPSR_GPSR(IP10_11_8, NFDATA1), 1138 1139 PINMUX_IPSR_GPSR(IP10_15_12, SD3_DAT2), 1140 PINMUX_IPSR_GPSR(IP10_15_12, NFDATA2), 1141 1142 PINMUX_IPSR_GPSR(IP10_19_16, SD3_DAT3), 1143 PINMUX_IPSR_GPSR(IP10_19_16, NFDATA3), 1144 1145 PINMUX_IPSR_GPSR(IP10_23_20, SD3_DAT4), 1146 PINMUX_IPSR_MSEL(IP10_23_20, SD2_CD_A, SEL_SDHI2_0), 1147 PINMUX_IPSR_GPSR(IP10_23_20, NFDATA4), 1148 1149 PINMUX_IPSR_GPSR(IP10_27_24, SD3_DAT5), 1150 PINMUX_IPSR_MSEL(IP10_27_24, SD2_WP_A, SEL_SDHI2_0), 1151 PINMUX_IPSR_GPSR(IP10_27_24, NFDATA5), 1152 1153 PINMUX_IPSR_GPSR(IP10_31_28, SD3_DAT6), 1154 PINMUX_IPSR_GPSR(IP10_31_28, SD3_CD), 1155 PINMUX_IPSR_GPSR(IP10_31_28, NFDATA6), 1156 1157 /* IPSR11 */ 1158 PINMUX_IPSR_GPSR(IP11_3_0, SD3_DAT7), 1159 PINMUX_IPSR_GPSR(IP11_3_0, SD3_WP), 1160 PINMUX_IPSR_GPSR(IP11_3_0, NFDATA7), 1161 1162 PINMUX_IPSR_GPSR(IP11_7_4, SD3_DS), 1163 PINMUX_IPSR_GPSR(IP11_7_4, NFCLE), 1164 1165 PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD), 1166 PINMUX_IPSR_MSEL(IP11_11_8, NFDATA14_A, SEL_NDF_0), 1167 PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1), 1168 PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0), 1169 1170 PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP), 1171 PINMUX_IPSR_MSEL(IP11_15_12, NFDATA15_A, SEL_NDF_0), 1172 PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1), 1173 1174 PINMUX_IPSR_MSEL(IP11_19_16, SD1_CD, I2C_SEL_0_0), 1175 PINMUX_IPSR_PHYS_MSEL(IP11_19_16, NFRB_N_A, I2C_SEL_0_0, SEL_NDF_0), 1176 PINMUX_IPSR_PHYS_MSEL(IP11_19_16, SIM0_CLK_B, I2C_SEL_0_0, SEL_SIMCARD_1), 1177 PINMUX_IPSR_PHYS(IP11_19_16, SCL0, I2C_SEL_0_1), 1178 1179 PINMUX_IPSR_MSEL(IP11_23_20, SD1_WP, I2C_SEL_0_0), 1180 PINMUX_IPSR_PHYS_MSEL(IP11_23_20, NFCE_N_A, I2C_SEL_0_0, SEL_NDF_0), 1181 PINMUX_IPSR_PHYS_MSEL(IP11_23_20, SIM0_D_B, I2C_SEL_0_0, SEL_SIMCARD_1), 1182 PINMUX_IPSR_PHYS(IP11_23_20, SDA0, I2C_SEL_0_1), 1183 1184 PINMUX_IPSR_GPSR(IP11_27_24, SCK0), 1185 PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1), 1186 PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1), 1187 PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADGC_1), 1188 PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0), 1189 PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1), 1190 PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2), 1191 PINMUX_IPSR_MSEL(IP11_27_24, RIF0_CLK_B, SEL_DRIF0_1), 1192 PINMUX_IPSR_GPSR(IP11_27_24, ADICHS2), 1193 PINMUX_IPSR_MSEL(IP11_27_24, SCK5_B, SEL_SCIF5_1), 1194 1195 PINMUX_IPSR_GPSR(IP11_31_28, RX0), 1196 PINMUX_IPSR_MSEL(IP11_31_28, HRX1_B, SEL_HSCIF1_1), 1197 PINMUX_IPSR_MSEL(IP11_31_28, TS_SCK0_C, SEL_TSIF0_2), 1198 PINMUX_IPSR_MSEL(IP11_31_28, STP_ISCLK_0_C, SEL_SSP1_0_2), 1199 PINMUX_IPSR_MSEL(IP11_31_28, RIF0_D0_B, SEL_DRIF0_1), 1200 1201 /* IPSR12 */ 1202 PINMUX_IPSR_GPSR(IP12_3_0, TX0), 1203 PINMUX_IPSR_MSEL(IP12_3_0, HTX1_B, SEL_HSCIF1_1), 1204 PINMUX_IPSR_MSEL(IP12_3_0, TS_SPSYNC0_C, SEL_TSIF0_2), 1205 PINMUX_IPSR_MSEL(IP12_3_0, STP_ISSYNC_0_C, SEL_SSP1_0_2), 1206 PINMUX_IPSR_MSEL(IP12_3_0, RIF0_D1_B, SEL_DRIF0_1), 1207 1208 PINMUX_IPSR_GPSR(IP12_7_4, CTS0_N), 1209 PINMUX_IPSR_MSEL(IP12_7_4, HCTS1_N_B, SEL_HSCIF1_1), 1210 PINMUX_IPSR_MSEL(IP12_7_4, MSIOF1_SYNC_B, SEL_MSIOF1_1), 1211 PINMUX_IPSR_MSEL(IP12_7_4, TS_SPSYNC1_C, SEL_TSIF1_2), 1212 PINMUX_IPSR_MSEL(IP12_7_4, STP_ISSYNC_1_C, SEL_SSP1_1_2), 1213 PINMUX_IPSR_MSEL(IP12_7_4, RIF1_SYNC_B, SEL_DRIF1_1), 1214 PINMUX_IPSR_GPSR(IP12_7_4, AUDIO_CLKOUT_C), 1215 PINMUX_IPSR_GPSR(IP12_7_4, ADICS_SAMP), 1216 1217 PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N), 1218 PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1), 1219 PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1), 1220 PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADGA_1), 1221 PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0), 1222 PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2), 1223 PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1), 1224 PINMUX_IPSR_GPSR(IP12_11_8, ADICHS1), 1225 1226 PINMUX_IPSR_MSEL(IP12_15_12, RX1_A, SEL_SCIF1_0), 1227 PINMUX_IPSR_MSEL(IP12_15_12, HRX1_A, SEL_HSCIF1_0), 1228 PINMUX_IPSR_MSEL(IP12_15_12, TS_SDAT0_C, SEL_TSIF0_2), 1229 PINMUX_IPSR_MSEL(IP12_15_12, STP_ISD_0_C, SEL_SSP1_0_2), 1230 PINMUX_IPSR_MSEL(IP12_15_12, RIF1_CLK_C, SEL_DRIF1_2), 1231 1232 PINMUX_IPSR_MSEL(IP12_19_16, TX1_A, SEL_SCIF1_0), 1233 PINMUX_IPSR_MSEL(IP12_19_16, HTX1_A, SEL_HSCIF1_0), 1234 PINMUX_IPSR_MSEL(IP12_19_16, TS_SDEN0_C, SEL_TSIF0_2), 1235 PINMUX_IPSR_MSEL(IP12_19_16, STP_ISEN_0_C, SEL_SSP1_0_2), 1236 PINMUX_IPSR_MSEL(IP12_19_16, RIF1_D0_C, SEL_DRIF1_2), 1237 1238 PINMUX_IPSR_GPSR(IP12_23_20, CTS1_N), 1239 PINMUX_IPSR_MSEL(IP12_23_20, HCTS1_N_A, SEL_HSCIF1_0), 1240 PINMUX_IPSR_MSEL(IP12_23_20, MSIOF1_RXD_B, SEL_MSIOF1_1), 1241 PINMUX_IPSR_MSEL(IP12_23_20, TS_SDEN1_C, SEL_TSIF1_2), 1242 PINMUX_IPSR_MSEL(IP12_23_20, STP_ISEN_1_C, SEL_SSP1_1_2), 1243 PINMUX_IPSR_MSEL(IP12_23_20, RIF1_D0_B, SEL_DRIF1_1), 1244 PINMUX_IPSR_GPSR(IP12_23_20, ADIDATA), 1245 1246 PINMUX_IPSR_GPSR(IP12_27_24, RTS1_N), 1247 PINMUX_IPSR_MSEL(IP12_27_24, HRTS1_N_A, SEL_HSCIF1_0), 1248 PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1), 1249 PINMUX_IPSR_MSEL(IP12_27_24, TS_SDAT1_C, SEL_TSIF1_2), 1250 PINMUX_IPSR_MSEL(IP12_27_24, STP_ISD_1_C, SEL_SSP1_1_2), 1251 PINMUX_IPSR_MSEL(IP12_27_24, RIF1_D1_B, SEL_DRIF1_1), 1252 PINMUX_IPSR_GPSR(IP12_27_24, ADICHS0), 1253 1254 PINMUX_IPSR_GPSR(IP12_31_28, SCK2), 1255 PINMUX_IPSR_MSEL(IP12_31_28, SCIF_CLK_B, SEL_SCIF_1), 1256 PINMUX_IPSR_MSEL(IP12_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1), 1257 PINMUX_IPSR_MSEL(IP12_31_28, TS_SCK1_C, SEL_TSIF1_2), 1258 PINMUX_IPSR_MSEL(IP12_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2), 1259 PINMUX_IPSR_MSEL(IP12_31_28, RIF1_CLK_B, SEL_DRIF1_1), 1260 PINMUX_IPSR_GPSR(IP12_31_28, ADICLK), 1261 1262 /* IPSR13 */ 1263 PINMUX_IPSR_MSEL(IP13_3_0, TX2_A, SEL_SCIF2_0), 1264 PINMUX_IPSR_MSEL(IP13_3_0, SD2_CD_B, SEL_SDHI2_1), 1265 PINMUX_IPSR_MSEL(IP13_3_0, SCL1_A, SEL_I2C1_0), 1266 PINMUX_IPSR_MSEL(IP13_3_0, FMCLK_A, SEL_FM_0), 1267 PINMUX_IPSR_MSEL(IP13_3_0, RIF1_D1_C, SEL_DRIF1_2), 1268 PINMUX_IPSR_GPSR(IP13_3_0, FSO_CFE_0_N), 1269 1270 PINMUX_IPSR_MSEL(IP13_7_4, RX2_A, SEL_SCIF2_0), 1271 PINMUX_IPSR_MSEL(IP13_7_4, SD2_WP_B, SEL_SDHI2_1), 1272 PINMUX_IPSR_MSEL(IP13_7_4, SDA1_A, SEL_I2C1_0), 1273 PINMUX_IPSR_MSEL(IP13_7_4, FMIN_A, SEL_FM_0), 1274 PINMUX_IPSR_MSEL(IP13_7_4, RIF1_SYNC_C, SEL_DRIF1_2), 1275 PINMUX_IPSR_GPSR(IP13_7_4, FSO_CFE_1_N), 1276 1277 PINMUX_IPSR_GPSR(IP13_11_8, HSCK0), 1278 PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3), 1279 PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADGB_0), 1280 PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI1_1), 1281 PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3), 1282 PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3), 1283 PINMUX_IPSR_MSEL(IP13_11_8, RIF0_CLK_C, SEL_DRIF0_2), 1284 PINMUX_IPSR_MSEL(IP13_11_8, RX5_B, SEL_SCIF5_1), 1285 1286 PINMUX_IPSR_GPSR(IP13_15_12, HRX0), 1287 PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3), 1288 PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA2_B, SEL_SSI2_1), 1289 PINMUX_IPSR_MSEL(IP13_15_12, TS_SDEN0_D, SEL_TSIF0_3), 1290 PINMUX_IPSR_MSEL(IP13_15_12, STP_ISEN_0_D, SEL_SSP1_0_3), 1291 PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_C, SEL_DRIF0_2), 1292 1293 PINMUX_IPSR_GPSR(IP13_19_16, HTX0), 1294 PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3), 1295 PINMUX_IPSR_MSEL(IP13_19_16, SSI_SDATA9_B, SEL_SSI9_1), 1296 PINMUX_IPSR_MSEL(IP13_19_16, TS_SDAT0_D, SEL_TSIF0_3), 1297 PINMUX_IPSR_MSEL(IP13_19_16, STP_ISD_0_D, SEL_SSP1_0_3), 1298 PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_C, SEL_DRIF0_2), 1299 1300 PINMUX_IPSR_GPSR(IP13_23_20, HCTS0_N), 1301 PINMUX_IPSR_MSEL(IP13_23_20, RX2_B, SEL_SCIF2_1), 1302 PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3), 1303 PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK9_A, SEL_SSI9_0), 1304 PINMUX_IPSR_MSEL(IP13_23_20, TS_SPSYNC0_D, SEL_TSIF0_3), 1305 PINMUX_IPSR_MSEL(IP13_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3), 1306 PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_C, SEL_DRIF0_2), 1307 PINMUX_IPSR_GPSR(IP13_23_20, AUDIO_CLKOUT1_A), 1308 1309 PINMUX_IPSR_GPSR(IP13_27_24, HRTS0_N), 1310 PINMUX_IPSR_MSEL(IP13_27_24, TX2_B, SEL_SCIF2_1), 1311 PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3), 1312 PINMUX_IPSR_MSEL(IP13_27_24, SSI_WS9_A, SEL_SSI9_0), 1313 PINMUX_IPSR_MSEL(IP13_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3), 1314 PINMUX_IPSR_MSEL(IP13_27_24, BPFCLK_A, SEL_FM_0), 1315 PINMUX_IPSR_GPSR(IP13_27_24, AUDIO_CLKOUT2_A), 1316 1317 PINMUX_IPSR_GPSR(IP13_31_28, MSIOF0_SYNC), 1318 PINMUX_IPSR_GPSR(IP13_31_28, AUDIO_CLKOUT_A), 1319 PINMUX_IPSR_MSEL(IP13_31_28, TX5_B, SEL_SCIF5_1), 1320 PINMUX_IPSR_MSEL(IP13_31_28, BPFCLK_D, SEL_FM_3), 1321 1322 /* IPSR14 */ 1323 PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1), 1324 PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0), 1325 PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDF_0), 1326 PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADGA_2), 1327 PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0), 1328 PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2), 1329 PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A), 1330 PINMUX_IPSR_MSEL(IP14_3_0, TCLK1_B, SEL_TIMER_TMU_1), 1331 1332 PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2), 1333 PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0), 1334 PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3), 1335 PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADGC_0), 1336 PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI2_0), 1337 PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3), 1338 PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D), 1339 PINMUX_IPSR_MSEL(IP14_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1), 1340 1341 PINMUX_IPSR_GPSR(IP14_11_8, MLB_CLK), 1342 PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SCK_F, SEL_MSIOF1_5), 1343 PINMUX_IPSR_MSEL(IP14_11_8, SCL1_B, SEL_I2C1_1), 1344 1345 PINMUX_IPSR_GPSR(IP14_15_12, MLB_SIG), 1346 PINMUX_IPSR_MSEL(IP14_15_12, RX1_B, SEL_SCIF1_1), 1347 PINMUX_IPSR_MSEL(IP14_15_12, MSIOF1_SYNC_F, SEL_MSIOF1_5), 1348 PINMUX_IPSR_MSEL(IP14_15_12, SDA1_B, SEL_I2C1_1), 1349 1350 PINMUX_IPSR_GPSR(IP14_19_16, MLB_DAT), 1351 PINMUX_IPSR_MSEL(IP14_19_16, TX1_B, SEL_SCIF1_1), 1352 PINMUX_IPSR_MSEL(IP14_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5), 1353 1354 PINMUX_IPSR_GPSR(IP14_23_20, SSI_SCK01239), 1355 PINMUX_IPSR_MSEL(IP14_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5), 1356 1357 PINMUX_IPSR_GPSR(IP14_27_24, SSI_WS01239), 1358 PINMUX_IPSR_MSEL(IP14_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5), 1359 1360 PINMUX_IPSR_GPSR(IP14_31_28, SSI_SDATA0), 1361 PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5), 1362 1363 /* IPSR15 */ 1364 PINMUX_IPSR_MSEL(IP15_3_0, SSI_SDATA1_A, SEL_SSI1_0), 1365 1366 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SDATA2_A, SEL_SSI2_0), 1367 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SCK1_B, SEL_SSI1_1), 1368 1369 PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK349), 1370 PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0), 1371 PINMUX_IPSR_MSEL(IP15_11_8, STP_OPWM_0_A, SEL_SSP1_0_0), 1372 1373 PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS349), 1374 PINMUX_IPSR_MSEL(IP15_15_12, HCTS2_N_A, SEL_HSCIF2_0), 1375 PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0), 1376 PINMUX_IPSR_MSEL(IP15_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0), 1377 1378 PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA3), 1379 PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0), 1380 PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_TXD_A, SEL_MSIOF1_0), 1381 PINMUX_IPSR_MSEL(IP15_19_16, TS_SCK0_A, SEL_TSIF0_0), 1382 PINMUX_IPSR_MSEL(IP15_19_16, STP_ISCLK_0_A, SEL_SSP1_0_0), 1383 PINMUX_IPSR_MSEL(IP15_19_16, RIF0_D1_A, SEL_DRIF0_0), 1384 PINMUX_IPSR_MSEL(IP15_19_16, RIF2_D0_A, SEL_DRIF2_0), 1385 1386 PINMUX_IPSR_GPSR(IP15_23_20, SSI_SCK4), 1387 PINMUX_IPSR_MSEL(IP15_23_20, HRX2_A, SEL_HSCIF2_0), 1388 PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_SCK_A, SEL_MSIOF1_0), 1389 PINMUX_IPSR_MSEL(IP15_23_20, TS_SDAT0_A, SEL_TSIF0_0), 1390 PINMUX_IPSR_MSEL(IP15_23_20, STP_ISD_0_A, SEL_SSP1_0_0), 1391 PINMUX_IPSR_MSEL(IP15_23_20, RIF0_CLK_A, SEL_DRIF0_0), 1392 PINMUX_IPSR_MSEL(IP15_23_20, RIF2_CLK_A, SEL_DRIF2_0), 1393 1394 PINMUX_IPSR_GPSR(IP15_27_24, SSI_WS4), 1395 PINMUX_IPSR_MSEL(IP15_27_24, HTX2_A, SEL_HSCIF2_0), 1396 PINMUX_IPSR_MSEL(IP15_27_24, MSIOF1_SYNC_A, SEL_MSIOF1_0), 1397 PINMUX_IPSR_MSEL(IP15_27_24, TS_SDEN0_A, SEL_TSIF0_0), 1398 PINMUX_IPSR_MSEL(IP15_27_24, STP_ISEN_0_A, SEL_SSP1_0_0), 1399 PINMUX_IPSR_MSEL(IP15_27_24, RIF0_SYNC_A, SEL_DRIF0_0), 1400 PINMUX_IPSR_MSEL(IP15_27_24, RIF2_SYNC_A, SEL_DRIF2_0), 1401 1402 PINMUX_IPSR_GPSR(IP15_31_28, SSI_SDATA4), 1403 PINMUX_IPSR_MSEL(IP15_31_28, HSCK2_A, SEL_HSCIF2_0), 1404 PINMUX_IPSR_MSEL(IP15_31_28, MSIOF1_RXD_A, SEL_MSIOF1_0), 1405 PINMUX_IPSR_MSEL(IP15_31_28, TS_SPSYNC0_A, SEL_TSIF0_0), 1406 PINMUX_IPSR_MSEL(IP15_31_28, STP_ISSYNC_0_A, SEL_SSP1_0_0), 1407 PINMUX_IPSR_MSEL(IP15_31_28, RIF0_D0_A, SEL_DRIF0_0), 1408 PINMUX_IPSR_MSEL(IP15_31_28, RIF2_D1_A, SEL_DRIF2_0), 1409 1410 /* IPSR16 */ 1411 PINMUX_IPSR_GPSR(IP16_3_0, SSI_SCK6), 1412 PINMUX_IPSR_MSEL(IP16_3_0, SIM0_RST_D, SEL_SIMCARD_3), 1413 1414 PINMUX_IPSR_GPSR(IP16_7_4, SSI_WS6), 1415 PINMUX_IPSR_MSEL(IP16_7_4, SIM0_D_D, SEL_SIMCARD_3), 1416 1417 PINMUX_IPSR_GPSR(IP16_11_8, SSI_SDATA6), 1418 PINMUX_IPSR_MSEL(IP16_11_8, SIM0_CLK_D, SEL_SIMCARD_3), 1419 PINMUX_IPSR_GPSR(IP16_11_8, SATA_DEVSLP_A), 1420 1421 PINMUX_IPSR_GPSR(IP16_15_12, SSI_SCK78), 1422 PINMUX_IPSR_MSEL(IP16_15_12, HRX2_B, SEL_HSCIF2_1), 1423 PINMUX_IPSR_MSEL(IP16_15_12, MSIOF1_SCK_C, SEL_MSIOF1_2), 1424 PINMUX_IPSR_MSEL(IP16_15_12, TS_SCK1_A, SEL_TSIF1_0), 1425 PINMUX_IPSR_MSEL(IP16_15_12, STP_ISCLK_1_A, SEL_SSP1_1_0), 1426 PINMUX_IPSR_MSEL(IP16_15_12, RIF1_CLK_A, SEL_DRIF1_0), 1427 PINMUX_IPSR_MSEL(IP16_15_12, RIF3_CLK_A, SEL_DRIF3_0), 1428 1429 PINMUX_IPSR_GPSR(IP16_19_16, SSI_WS78), 1430 PINMUX_IPSR_MSEL(IP16_19_16, HTX2_B, SEL_HSCIF2_1), 1431 PINMUX_IPSR_MSEL(IP16_19_16, MSIOF1_SYNC_C, SEL_MSIOF1_2), 1432 PINMUX_IPSR_MSEL(IP16_19_16, TS_SDAT1_A, SEL_TSIF1_0), 1433 PINMUX_IPSR_MSEL(IP16_19_16, STP_ISD_1_A, SEL_SSP1_1_0), 1434 PINMUX_IPSR_MSEL(IP16_19_16, RIF1_SYNC_A, SEL_DRIF1_0), 1435 PINMUX_IPSR_MSEL(IP16_19_16, RIF3_SYNC_A, SEL_DRIF3_0), 1436 1437 PINMUX_IPSR_GPSR(IP16_23_20, SSI_SDATA7), 1438 PINMUX_IPSR_MSEL(IP16_23_20, HCTS2_N_B, SEL_HSCIF2_1), 1439 PINMUX_IPSR_MSEL(IP16_23_20, MSIOF1_RXD_C, SEL_MSIOF1_2), 1440 PINMUX_IPSR_MSEL(IP16_23_20, TS_SDEN1_A, SEL_TSIF1_0), 1441 PINMUX_IPSR_MSEL(IP16_23_20, STP_ISEN_1_A, SEL_SSP1_1_0), 1442 PINMUX_IPSR_MSEL(IP16_23_20, RIF1_D0_A, SEL_DRIF1_0), 1443 PINMUX_IPSR_MSEL(IP16_23_20, RIF3_D0_A, SEL_DRIF3_0), 1444 PINMUX_IPSR_MSEL(IP16_23_20, TCLK2_A, SEL_TIMER_TMU2_0), 1445 1446 PINMUX_IPSR_GPSR(IP16_27_24, SSI_SDATA8), 1447 PINMUX_IPSR_MSEL(IP16_27_24, HRTS2_N_B, SEL_HSCIF2_1), 1448 PINMUX_IPSR_MSEL(IP16_27_24, MSIOF1_TXD_C, SEL_MSIOF1_2), 1449 PINMUX_IPSR_MSEL(IP16_27_24, TS_SPSYNC1_A, SEL_TSIF1_0), 1450 PINMUX_IPSR_MSEL(IP16_27_24, STP_ISSYNC_1_A, SEL_SSP1_1_0), 1451 PINMUX_IPSR_MSEL(IP16_27_24, RIF1_D1_A, SEL_DRIF1_0), 1452 PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D1_A, SEL_DRIF3_0), 1453 1454 PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA9_A, SEL_SSI9_0), 1455 PINMUX_IPSR_MSEL(IP16_31_28, HSCK2_B, SEL_HSCIF2_1), 1456 PINMUX_IPSR_MSEL(IP16_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2), 1457 PINMUX_IPSR_MSEL(IP16_31_28, HSCK1_A, SEL_HSCIF1_0), 1458 PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI1_1), 1459 PINMUX_IPSR_GPSR(IP16_31_28, SCK1), 1460 PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0), 1461 PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0), 1462 1463 /* IPSR17 */ 1464 PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADGA_0), 1465 1466 PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADGB_1), 1467 PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0), 1468 PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3), 1469 PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0), 1470 PINMUX_IPSR_MSEL(IP17_7_4, TCLK1_A, SEL_TIMER_TMU_0), 1471 1472 PINMUX_IPSR_GPSR(IP17_11_8, USB0_PWEN), 1473 PINMUX_IPSR_MSEL(IP17_11_8, SIM0_RST_C, SEL_SIMCARD_2), 1474 PINMUX_IPSR_MSEL(IP17_11_8, TS_SCK1_D, SEL_TSIF1_3), 1475 PINMUX_IPSR_MSEL(IP17_11_8, STP_ISCLK_1_D, SEL_SSP1_1_3), 1476 PINMUX_IPSR_MSEL(IP17_11_8, BPFCLK_B, SEL_FM_1), 1477 PINMUX_IPSR_MSEL(IP17_11_8, RIF3_CLK_B, SEL_DRIF3_1), 1478 PINMUX_IPSR_MSEL(IP17_11_8, HSCK2_C, SEL_HSCIF2_2), 1479 1480 PINMUX_IPSR_GPSR(IP17_15_12, USB0_OVC), 1481 PINMUX_IPSR_MSEL(IP17_15_12, SIM0_D_C, SEL_SIMCARD_2), 1482 PINMUX_IPSR_MSEL(IP17_15_12, TS_SDAT1_D, SEL_TSIF1_3), 1483 PINMUX_IPSR_MSEL(IP17_15_12, STP_ISD_1_D, SEL_SSP1_1_3), 1484 PINMUX_IPSR_MSEL(IP17_15_12, RIF3_SYNC_B, SEL_DRIF3_1), 1485 PINMUX_IPSR_MSEL(IP17_15_12, HRX2_C, SEL_HSCIF2_2), 1486 1487 PINMUX_IPSR_GPSR(IP17_19_16, USB1_PWEN), 1488 PINMUX_IPSR_MSEL(IP17_19_16, SIM0_CLK_C, SEL_SIMCARD_2), 1489 PINMUX_IPSR_MSEL(IP17_19_16, SSI_SCK1_A, SEL_SSI1_0), 1490 PINMUX_IPSR_MSEL(IP17_19_16, TS_SCK0_E, SEL_TSIF0_4), 1491 PINMUX_IPSR_MSEL(IP17_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4), 1492 PINMUX_IPSR_MSEL(IP17_19_16, FMCLK_B, SEL_FM_1), 1493 PINMUX_IPSR_MSEL(IP17_19_16, RIF2_CLK_B, SEL_DRIF2_1), 1494 PINMUX_IPSR_MSEL(IP17_19_16, SPEEDIN_A, SEL_SPEED_PULSE_0), 1495 PINMUX_IPSR_MSEL(IP17_19_16, HTX2_C, SEL_HSCIF2_2), 1496 1497 PINMUX_IPSR_GPSR(IP17_23_20, USB1_OVC), 1498 PINMUX_IPSR_MSEL(IP17_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2), 1499 PINMUX_IPSR_MSEL(IP17_23_20, SSI_WS1_A, SEL_SSI1_0), 1500 PINMUX_IPSR_MSEL(IP17_23_20, TS_SDAT0_E, SEL_TSIF0_4), 1501 PINMUX_IPSR_MSEL(IP17_23_20, STP_ISD_0_E, SEL_SSP1_0_4), 1502 PINMUX_IPSR_MSEL(IP17_23_20, FMIN_B, SEL_FM_1), 1503 PINMUX_IPSR_MSEL(IP17_23_20, RIF2_SYNC_B, SEL_DRIF2_1), 1504 PINMUX_IPSR_MSEL(IP17_23_20, REMOCON_B, SEL_REMOCON_1), 1505 PINMUX_IPSR_MSEL(IP17_23_20, HCTS2_N_C, SEL_HSCIF2_2), 1506 1507 PINMUX_IPSR_GPSR(IP17_27_24, USB30_PWEN), 1508 PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_B), 1509 PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI2_1), 1510 PINMUX_IPSR_MSEL(IP17_27_24, TS_SDEN1_D, SEL_TSIF1_3), 1511 PINMUX_IPSR_MSEL(IP17_27_24, STP_ISEN_1_D, SEL_SSP1_1_3), 1512 PINMUX_IPSR_MSEL(IP17_27_24, STP_OPWM_0_E, SEL_SSP1_0_4), 1513 PINMUX_IPSR_MSEL(IP17_27_24, RIF3_D0_B, SEL_DRIF3_1), 1514 PINMUX_IPSR_MSEL(IP17_27_24, TCLK2_B, SEL_TIMER_TMU2_1), 1515 PINMUX_IPSR_GPSR(IP17_27_24, TPU0TO0), 1516 PINMUX_IPSR_MSEL(IP17_27_24, BPFCLK_C, SEL_FM_2), 1517 PINMUX_IPSR_MSEL(IP17_27_24, HRTS2_N_C, SEL_HSCIF2_2), 1518 1519 PINMUX_IPSR_GPSR(IP17_31_28, USB30_OVC), 1520 PINMUX_IPSR_GPSR(IP17_31_28, AUDIO_CLKOUT1_B), 1521 PINMUX_IPSR_MSEL(IP17_31_28, SSI_WS2_B, SEL_SSI2_1), 1522 PINMUX_IPSR_MSEL(IP17_31_28, TS_SPSYNC1_D, SEL_TSIF1_3), 1523 PINMUX_IPSR_MSEL(IP17_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3), 1524 PINMUX_IPSR_MSEL(IP17_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4), 1525 PINMUX_IPSR_MSEL(IP17_31_28, RIF3_D1_B, SEL_DRIF3_1), 1526 PINMUX_IPSR_GPSR(IP17_31_28, FSO_TOE_N), 1527 PINMUX_IPSR_GPSR(IP17_31_28, TPU0TO1), 1528 1529 /* IPSR18 */ 1530 PINMUX_IPSR_GPSR(IP18_3_0, GP6_30), 1531 PINMUX_IPSR_GPSR(IP18_3_0, AUDIO_CLKOUT2_B), 1532 PINMUX_IPSR_MSEL(IP18_3_0, SSI_SCK9_B, SEL_SSI9_1), 1533 PINMUX_IPSR_MSEL(IP18_3_0, TS_SDEN0_E, SEL_TSIF0_4), 1534 PINMUX_IPSR_MSEL(IP18_3_0, STP_ISEN_0_E, SEL_SSP1_0_4), 1535 PINMUX_IPSR_MSEL(IP18_3_0, RIF2_D0_B, SEL_DRIF2_1), 1536 PINMUX_IPSR_GPSR(IP18_3_0, TPU0TO2), 1537 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_C, SEL_FM_2), 1538 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_D, SEL_FM_3), 1539 1540 PINMUX_IPSR_GPSR(IP18_7_4, GP6_31), 1541 PINMUX_IPSR_GPSR(IP18_7_4, AUDIO_CLKOUT3_B), 1542 PINMUX_IPSR_MSEL(IP18_7_4, SSI_WS9_B, SEL_SSI9_1), 1543 PINMUX_IPSR_MSEL(IP18_7_4, TS_SPSYNC0_E, SEL_TSIF0_4), 1544 PINMUX_IPSR_MSEL(IP18_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4), 1545 PINMUX_IPSR_MSEL(IP18_7_4, RIF2_D1_B, SEL_DRIF2_1), 1546 PINMUX_IPSR_GPSR(IP18_7_4, TPU0TO3), 1547 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_C, SEL_FM_2), 1548 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_D, SEL_FM_3), 1549 1550 /* 1551 * Static pins can not be muxed between different functions but 1552 * still need mark entries in the pinmux list. Add each static 1553 * pin to the list without an associated function. The sh-pfc 1554 * core will do the right thing and skip trying to mux the pin 1555 * while still applying configuration to it. 1556 */ 1557 #define FM(x) PINMUX_DATA(x##_MARK, 0), 1558 PINMUX_STATIC 1559 #undef FM 1560 }; 1561 1562 /* 1563 * Pins not associated with a GPIO port. 1564 */ 1565 enum { 1566 GP_ASSIGN_LAST(), 1567 NOGP_ALL(), 1568 }; 1569 1570 static const struct sh_pfc_pin pinmux_pins[] = { 1571 PINMUX_GPIO_GP_ALL(), 1572 PINMUX_NOGP_ALL(), 1573 }; 1574 1575 /* - AUDIO CLOCK ------------------------------------------------------------ */ 1576 static const unsigned int audio_clk_a_a_pins[] = { 1577 /* CLK A */ 1578 RCAR_GP_PIN(6, 22), 1579 }; 1580 static const unsigned int audio_clk_a_a_mux[] = { 1581 AUDIO_CLKA_A_MARK, 1582 }; 1583 static const unsigned int audio_clk_a_b_pins[] = { 1584 /* CLK A */ 1585 RCAR_GP_PIN(5, 4), 1586 }; 1587 static const unsigned int audio_clk_a_b_mux[] = { 1588 AUDIO_CLKA_B_MARK, 1589 }; 1590 static const unsigned int audio_clk_a_c_pins[] = { 1591 /* CLK A */ 1592 RCAR_GP_PIN(5, 19), 1593 }; 1594 static const unsigned int audio_clk_a_c_mux[] = { 1595 AUDIO_CLKA_C_MARK, 1596 }; 1597 static const unsigned int audio_clk_b_a_pins[] = { 1598 /* CLK B */ 1599 RCAR_GP_PIN(5, 12), 1600 }; 1601 static const unsigned int audio_clk_b_a_mux[] = { 1602 AUDIO_CLKB_A_MARK, 1603 }; 1604 static const unsigned int audio_clk_b_b_pins[] = { 1605 /* CLK B */ 1606 RCAR_GP_PIN(6, 23), 1607 }; 1608 static const unsigned int audio_clk_b_b_mux[] = { 1609 AUDIO_CLKB_B_MARK, 1610 }; 1611 static const unsigned int audio_clk_c_a_pins[] = { 1612 /* CLK C */ 1613 RCAR_GP_PIN(5, 21), 1614 }; 1615 static const unsigned int audio_clk_c_a_mux[] = { 1616 AUDIO_CLKC_A_MARK, 1617 }; 1618 static const unsigned int audio_clk_c_b_pins[] = { 1619 /* CLK C */ 1620 RCAR_GP_PIN(5, 0), 1621 }; 1622 static const unsigned int audio_clk_c_b_mux[] = { 1623 AUDIO_CLKC_B_MARK, 1624 }; 1625 static const unsigned int audio_clkout_a_pins[] = { 1626 /* CLKOUT */ 1627 RCAR_GP_PIN(5, 18), 1628 }; 1629 static const unsigned int audio_clkout_a_mux[] = { 1630 AUDIO_CLKOUT_A_MARK, 1631 }; 1632 static const unsigned int audio_clkout_b_pins[] = { 1633 /* CLKOUT */ 1634 RCAR_GP_PIN(6, 28), 1635 }; 1636 static const unsigned int audio_clkout_b_mux[] = { 1637 AUDIO_CLKOUT_B_MARK, 1638 }; 1639 static const unsigned int audio_clkout_c_pins[] = { 1640 /* CLKOUT */ 1641 RCAR_GP_PIN(5, 3), 1642 }; 1643 static const unsigned int audio_clkout_c_mux[] = { 1644 AUDIO_CLKOUT_C_MARK, 1645 }; 1646 static const unsigned int audio_clkout_d_pins[] = { 1647 /* CLKOUT */ 1648 RCAR_GP_PIN(5, 21), 1649 }; 1650 static const unsigned int audio_clkout_d_mux[] = { 1651 AUDIO_CLKOUT_D_MARK, 1652 }; 1653 static const unsigned int audio_clkout1_a_pins[] = { 1654 /* CLKOUT1 */ 1655 RCAR_GP_PIN(5, 15), 1656 }; 1657 static const unsigned int audio_clkout1_a_mux[] = { 1658 AUDIO_CLKOUT1_A_MARK, 1659 }; 1660 static const unsigned int audio_clkout1_b_pins[] = { 1661 /* CLKOUT1 */ 1662 RCAR_GP_PIN(6, 29), 1663 }; 1664 static const unsigned int audio_clkout1_b_mux[] = { 1665 AUDIO_CLKOUT1_B_MARK, 1666 }; 1667 static const unsigned int audio_clkout2_a_pins[] = { 1668 /* CLKOUT2 */ 1669 RCAR_GP_PIN(5, 16), 1670 }; 1671 static const unsigned int audio_clkout2_a_mux[] = { 1672 AUDIO_CLKOUT2_A_MARK, 1673 }; 1674 static const unsigned int audio_clkout2_b_pins[] = { 1675 /* CLKOUT2 */ 1676 RCAR_GP_PIN(6, 30), 1677 }; 1678 static const unsigned int audio_clkout2_b_mux[] = { 1679 AUDIO_CLKOUT2_B_MARK, 1680 }; 1681 1682 static const unsigned int audio_clkout3_a_pins[] = { 1683 /* CLKOUT3 */ 1684 RCAR_GP_PIN(5, 19), 1685 }; 1686 static const unsigned int audio_clkout3_a_mux[] = { 1687 AUDIO_CLKOUT3_A_MARK, 1688 }; 1689 static const unsigned int audio_clkout3_b_pins[] = { 1690 /* CLKOUT3 */ 1691 RCAR_GP_PIN(6, 31), 1692 }; 1693 static const unsigned int audio_clkout3_b_mux[] = { 1694 AUDIO_CLKOUT3_B_MARK, 1695 }; 1696 1697 /* - EtherAVB --------------------------------------------------------------- */ 1698 static const unsigned int avb_link_pins[] = { 1699 /* AVB_LINK */ 1700 RCAR_GP_PIN(2, 12), 1701 }; 1702 static const unsigned int avb_link_mux[] = { 1703 AVB_LINK_MARK, 1704 }; 1705 static const unsigned int avb_magic_pins[] = { 1706 /* AVB_MAGIC_ */ 1707 RCAR_GP_PIN(2, 10), 1708 }; 1709 static const unsigned int avb_magic_mux[] = { 1710 AVB_MAGIC_MARK, 1711 }; 1712 static const unsigned int avb_phy_int_pins[] = { 1713 /* AVB_PHY_INT */ 1714 RCAR_GP_PIN(2, 11), 1715 }; 1716 static const unsigned int avb_phy_int_mux[] = { 1717 AVB_PHY_INT_MARK, 1718 }; 1719 static const unsigned int avb_mdio_pins[] = { 1720 /* AVB_MDC, AVB_MDIO */ 1721 RCAR_GP_PIN(2, 9), PIN_AVB_MDIO, 1722 }; 1723 static const unsigned int avb_mdio_mux[] = { 1724 AVB_MDC_MARK, AVB_MDIO_MARK, 1725 }; 1726 static const unsigned int avb_mii_pins[] = { 1727 /* 1728 * AVB_TX_CTL, AVB_TXC, AVB_TD0, 1729 * AVB_TD1, AVB_TD2, AVB_TD3, 1730 * AVB_RX_CTL, AVB_RXC, AVB_RD0, 1731 * AVB_RD1, AVB_RD2, AVB_RD3, 1732 * AVB_TXCREFCLK 1733 */ 1734 PIN_AVB_TX_CTL, PIN_AVB_TXC, PIN_AVB_TD0, 1735 PIN_AVB_TD1, PIN_AVB_TD2, PIN_AVB_TD3, 1736 PIN_AVB_RX_CTL, PIN_AVB_RXC, PIN_AVB_RD0, 1737 PIN_AVB_RD1, PIN_AVB_RD2, PIN_AVB_RD3, 1738 PIN_AVB_TXCREFCLK, 1739 1740 }; 1741 static const unsigned int avb_mii_mux[] = { 1742 AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK, 1743 AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK, 1744 AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK, 1745 AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK, 1746 AVB_TXCREFCLK_MARK, 1747 }; 1748 static const unsigned int avb_avtp_pps_pins[] = { 1749 /* AVB_AVTP_PPS */ 1750 RCAR_GP_PIN(2, 6), 1751 }; 1752 static const unsigned int avb_avtp_pps_mux[] = { 1753 AVB_AVTP_PPS_MARK, 1754 }; 1755 static const unsigned int avb_avtp_match_a_pins[] = { 1756 /* AVB_AVTP_MATCH_A */ 1757 RCAR_GP_PIN(2, 13), 1758 }; 1759 static const unsigned int avb_avtp_match_a_mux[] = { 1760 AVB_AVTP_MATCH_A_MARK, 1761 }; 1762 static const unsigned int avb_avtp_capture_a_pins[] = { 1763 /* AVB_AVTP_CAPTURE_A */ 1764 RCAR_GP_PIN(2, 14), 1765 }; 1766 static const unsigned int avb_avtp_capture_a_mux[] = { 1767 AVB_AVTP_CAPTURE_A_MARK, 1768 }; 1769 static const unsigned int avb_avtp_match_b_pins[] = { 1770 /* AVB_AVTP_MATCH_B */ 1771 RCAR_GP_PIN(1, 8), 1772 }; 1773 static const unsigned int avb_avtp_match_b_mux[] = { 1774 AVB_AVTP_MATCH_B_MARK, 1775 }; 1776 static const unsigned int avb_avtp_capture_b_pins[] = { 1777 /* AVB_AVTP_CAPTURE_B */ 1778 RCAR_GP_PIN(1, 11), 1779 }; 1780 static const unsigned int avb_avtp_capture_b_mux[] = { 1781 AVB_AVTP_CAPTURE_B_MARK, 1782 }; 1783 1784 /* - CAN ------------------------------------------------------------------ */ 1785 static const unsigned int can0_data_a_pins[] = { 1786 /* TX, RX */ 1787 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24), 1788 }; 1789 1790 static const unsigned int can0_data_a_mux[] = { 1791 CAN0_TX_A_MARK, CAN0_RX_A_MARK, 1792 }; 1793 1794 static const unsigned int can0_data_b_pins[] = { 1795 /* TX, RX */ 1796 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), 1797 }; 1798 1799 static const unsigned int can0_data_b_mux[] = { 1800 CAN0_TX_B_MARK, CAN0_RX_B_MARK, 1801 }; 1802 1803 static const unsigned int can1_data_pins[] = { 1804 /* TX, RX */ 1805 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26), 1806 }; 1807 1808 static const unsigned int can1_data_mux[] = { 1809 CAN1_TX_MARK, CAN1_RX_MARK, 1810 }; 1811 1812 /* - CAN Clock -------------------------------------------------------------- */ 1813 static const unsigned int can_clk_pins[] = { 1814 /* CLK */ 1815 RCAR_GP_PIN(1, 25), 1816 }; 1817 1818 static const unsigned int can_clk_mux[] = { 1819 CAN_CLK_MARK, 1820 }; 1821 1822 /* - CAN FD --------------------------------------------------------------- */ 1823 static const unsigned int canfd0_data_a_pins[] = { 1824 /* TX, RX */ 1825 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24), 1826 }; 1827 1828 static const unsigned int canfd0_data_a_mux[] = { 1829 CANFD0_TX_A_MARK, CANFD0_RX_A_MARK, 1830 }; 1831 1832 static const unsigned int canfd0_data_b_pins[] = { 1833 /* TX, RX */ 1834 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), 1835 }; 1836 1837 static const unsigned int canfd0_data_b_mux[] = { 1838 CANFD0_TX_B_MARK, CANFD0_RX_B_MARK, 1839 }; 1840 1841 static const unsigned int canfd1_data_pins[] = { 1842 /* TX, RX */ 1843 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26), 1844 }; 1845 1846 static const unsigned int canfd1_data_mux[] = { 1847 CANFD1_TX_MARK, CANFD1_RX_MARK, 1848 }; 1849 1850 #ifdef CONFIG_PINCTRL_PFC_R8A77965 1851 /* - DRIF0 --------------------------------------------------------------- */ 1852 static const unsigned int drif0_ctrl_a_pins[] = { 1853 /* CLK, SYNC */ 1854 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), 1855 }; 1856 1857 static const unsigned int drif0_ctrl_a_mux[] = { 1858 RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK, 1859 }; 1860 1861 static const unsigned int drif0_data0_a_pins[] = { 1862 /* D0 */ 1863 RCAR_GP_PIN(6, 10), 1864 }; 1865 1866 static const unsigned int drif0_data0_a_mux[] = { 1867 RIF0_D0_A_MARK, 1868 }; 1869 1870 static const unsigned int drif0_data1_a_pins[] = { 1871 /* D1 */ 1872 RCAR_GP_PIN(6, 7), 1873 }; 1874 1875 static const unsigned int drif0_data1_a_mux[] = { 1876 RIF0_D1_A_MARK, 1877 }; 1878 1879 static const unsigned int drif0_ctrl_b_pins[] = { 1880 /* CLK, SYNC */ 1881 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4), 1882 }; 1883 1884 static const unsigned int drif0_ctrl_b_mux[] = { 1885 RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK, 1886 }; 1887 1888 static const unsigned int drif0_data0_b_pins[] = { 1889 /* D0 */ 1890 RCAR_GP_PIN(5, 1), 1891 }; 1892 1893 static const unsigned int drif0_data0_b_mux[] = { 1894 RIF0_D0_B_MARK, 1895 }; 1896 1897 static const unsigned int drif0_data1_b_pins[] = { 1898 /* D1 */ 1899 RCAR_GP_PIN(5, 2), 1900 }; 1901 1902 static const unsigned int drif0_data1_b_mux[] = { 1903 RIF0_D1_B_MARK, 1904 }; 1905 1906 static const unsigned int drif0_ctrl_c_pins[] = { 1907 /* CLK, SYNC */ 1908 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15), 1909 }; 1910 1911 static const unsigned int drif0_ctrl_c_mux[] = { 1912 RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK, 1913 }; 1914 1915 static const unsigned int drif0_data0_c_pins[] = { 1916 /* D0 */ 1917 RCAR_GP_PIN(5, 13), 1918 }; 1919 1920 static const unsigned int drif0_data0_c_mux[] = { 1921 RIF0_D0_C_MARK, 1922 }; 1923 1924 static const unsigned int drif0_data1_c_pins[] = { 1925 /* D1 */ 1926 RCAR_GP_PIN(5, 14), 1927 }; 1928 1929 static const unsigned int drif0_data1_c_mux[] = { 1930 RIF0_D1_C_MARK, 1931 }; 1932 1933 /* - DRIF1 --------------------------------------------------------------- */ 1934 static const unsigned int drif1_ctrl_a_pins[] = { 1935 /* CLK, SYNC */ 1936 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18), 1937 }; 1938 1939 static const unsigned int drif1_ctrl_a_mux[] = { 1940 RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK, 1941 }; 1942 1943 static const unsigned int drif1_data0_a_pins[] = { 1944 /* D0 */ 1945 RCAR_GP_PIN(6, 19), 1946 }; 1947 1948 static const unsigned int drif1_data0_a_mux[] = { 1949 RIF1_D0_A_MARK, 1950 }; 1951 1952 static const unsigned int drif1_data1_a_pins[] = { 1953 /* D1 */ 1954 RCAR_GP_PIN(6, 20), 1955 }; 1956 1957 static const unsigned int drif1_data1_a_mux[] = { 1958 RIF1_D1_A_MARK, 1959 }; 1960 1961 static const unsigned int drif1_ctrl_b_pins[] = { 1962 /* CLK, SYNC */ 1963 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3), 1964 }; 1965 1966 static const unsigned int drif1_ctrl_b_mux[] = { 1967 RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK, 1968 }; 1969 1970 static const unsigned int drif1_data0_b_pins[] = { 1971 /* D0 */ 1972 RCAR_GP_PIN(5, 7), 1973 }; 1974 1975 static const unsigned int drif1_data0_b_mux[] = { 1976 RIF1_D0_B_MARK, 1977 }; 1978 1979 static const unsigned int drif1_data1_b_pins[] = { 1980 /* D1 */ 1981 RCAR_GP_PIN(5, 8), 1982 }; 1983 1984 static const unsigned int drif1_data1_b_mux[] = { 1985 RIF1_D1_B_MARK, 1986 }; 1987 1988 static const unsigned int drif1_ctrl_c_pins[] = { 1989 /* CLK, SYNC */ 1990 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11), 1991 }; 1992 1993 static const unsigned int drif1_ctrl_c_mux[] = { 1994 RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK, 1995 }; 1996 1997 static const unsigned int drif1_data0_c_pins[] = { 1998 /* D0 */ 1999 RCAR_GP_PIN(5, 6), 2000 }; 2001 2002 static const unsigned int drif1_data0_c_mux[] = { 2003 RIF1_D0_C_MARK, 2004 }; 2005 2006 static const unsigned int drif1_data1_c_pins[] = { 2007 /* D1 */ 2008 RCAR_GP_PIN(5, 10), 2009 }; 2010 2011 static const unsigned int drif1_data1_c_mux[] = { 2012 RIF1_D1_C_MARK, 2013 }; 2014 2015 /* - DRIF2 --------------------------------------------------------------- */ 2016 static const unsigned int drif2_ctrl_a_pins[] = { 2017 /* CLK, SYNC */ 2018 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), 2019 }; 2020 2021 static const unsigned int drif2_ctrl_a_mux[] = { 2022 RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK, 2023 }; 2024 2025 static const unsigned int drif2_data0_a_pins[] = { 2026 /* D0 */ 2027 RCAR_GP_PIN(6, 7), 2028 }; 2029 2030 static const unsigned int drif2_data0_a_mux[] = { 2031 RIF2_D0_A_MARK, 2032 }; 2033 2034 static const unsigned int drif2_data1_a_pins[] = { 2035 /* D1 */ 2036 RCAR_GP_PIN(6, 10), 2037 }; 2038 2039 static const unsigned int drif2_data1_a_mux[] = { 2040 RIF2_D1_A_MARK, 2041 }; 2042 2043 static const unsigned int drif2_ctrl_b_pins[] = { 2044 /* CLK, SYNC */ 2045 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27), 2046 }; 2047 2048 static const unsigned int drif2_ctrl_b_mux[] = { 2049 RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK, 2050 }; 2051 2052 static const unsigned int drif2_data0_b_pins[] = { 2053 /* D0 */ 2054 RCAR_GP_PIN(6, 30), 2055 }; 2056 2057 static const unsigned int drif2_data0_b_mux[] = { 2058 RIF2_D0_B_MARK, 2059 }; 2060 2061 static const unsigned int drif2_data1_b_pins[] = { 2062 /* D1 */ 2063 RCAR_GP_PIN(6, 31), 2064 }; 2065 2066 static const unsigned int drif2_data1_b_mux[] = { 2067 RIF2_D1_B_MARK, 2068 }; 2069 2070 /* - DRIF3 --------------------------------------------------------------- */ 2071 static const unsigned int drif3_ctrl_a_pins[] = { 2072 /* CLK, SYNC */ 2073 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18), 2074 }; 2075 2076 static const unsigned int drif3_ctrl_a_mux[] = { 2077 RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK, 2078 }; 2079 2080 static const unsigned int drif3_data0_a_pins[] = { 2081 /* D0 */ 2082 RCAR_GP_PIN(6, 19), 2083 }; 2084 2085 static const unsigned int drif3_data0_a_mux[] = { 2086 RIF3_D0_A_MARK, 2087 }; 2088 2089 static const unsigned int drif3_data1_a_pins[] = { 2090 /* D1 */ 2091 RCAR_GP_PIN(6, 20), 2092 }; 2093 2094 static const unsigned int drif3_data1_a_mux[] = { 2095 RIF3_D1_A_MARK, 2096 }; 2097 2098 static const unsigned int drif3_ctrl_b_pins[] = { 2099 /* CLK, SYNC */ 2100 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25), 2101 }; 2102 2103 static const unsigned int drif3_ctrl_b_mux[] = { 2104 RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK, 2105 }; 2106 2107 static const unsigned int drif3_data0_b_pins[] = { 2108 /* D0 */ 2109 RCAR_GP_PIN(6, 28), 2110 }; 2111 2112 static const unsigned int drif3_data0_b_mux[] = { 2113 RIF3_D0_B_MARK, 2114 }; 2115 2116 static const unsigned int drif3_data1_b_pins[] = { 2117 /* D1 */ 2118 RCAR_GP_PIN(6, 29), 2119 }; 2120 2121 static const unsigned int drif3_data1_b_mux[] = { 2122 RIF3_D1_B_MARK, 2123 }; 2124 #endif /* CONFIG_PINCTRL_PFC_R8A77965 */ 2125 2126 /* - DU --------------------------------------------------------------------- */ 2127 static const unsigned int du_rgb666_pins[] = { 2128 /* R[7:2], G[7:2], B[7:2] */ 2129 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), 2130 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), 2131 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), 2132 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18), 2133 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5), 2134 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2), 2135 }; 2136 2137 static const unsigned int du_rgb666_mux[] = { 2138 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK, 2139 DU_DR3_MARK, DU_DR2_MARK, 2140 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK, 2141 DU_DG3_MARK, DU_DG2_MARK, 2142 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK, 2143 DU_DB3_MARK, DU_DB2_MARK, 2144 }; 2145 2146 static const unsigned int du_rgb888_pins[] = { 2147 /* R[7:0], G[7:0], B[7:0] */ 2148 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), 2149 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), 2150 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8), 2151 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), 2152 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18), 2153 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16), 2154 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5), 2155 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2), 2156 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0), 2157 }; 2158 2159 static const unsigned int du_rgb888_mux[] = { 2160 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK, 2161 DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK, 2162 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK, 2163 DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK, 2164 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK, 2165 DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK, 2166 }; 2167 2168 static const unsigned int du_clk_out_0_pins[] = { 2169 /* CLKOUT */ 2170 RCAR_GP_PIN(1, 27), 2171 }; 2172 2173 static const unsigned int du_clk_out_0_mux[] = { 2174 DU_DOTCLKOUT0_MARK 2175 }; 2176 2177 static const unsigned int du_clk_out_1_pins[] = { 2178 /* CLKOUT */ 2179 RCAR_GP_PIN(2, 3), 2180 }; 2181 2182 static const unsigned int du_clk_out_1_mux[] = { 2183 DU_DOTCLKOUT1_MARK 2184 }; 2185 2186 static const unsigned int du_sync_pins[] = { 2187 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */ 2188 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4), 2189 }; 2190 2191 static const unsigned int du_sync_mux[] = { 2192 DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK 2193 }; 2194 2195 static const unsigned int du_oddf_pins[] = { 2196 /* EXDISP/EXODDF/EXCDE */ 2197 RCAR_GP_PIN(2, 2), 2198 }; 2199 2200 static const unsigned int du_oddf_mux[] = { 2201 DU_EXODDF_DU_ODDF_DISP_CDE_MARK, 2202 }; 2203 2204 static const unsigned int du_cde_pins[] = { 2205 /* CDE */ 2206 RCAR_GP_PIN(2, 0), 2207 }; 2208 2209 static const unsigned int du_cde_mux[] = { 2210 DU_CDE_MARK, 2211 }; 2212 2213 static const unsigned int du_disp_pins[] = { 2214 /* DISP */ 2215 RCAR_GP_PIN(2, 1), 2216 }; 2217 2218 static const unsigned int du_disp_mux[] = { 2219 DU_DISP_MARK, 2220 }; 2221 2222 /* - HSCIF0 ----------------------------------------------------------------- */ 2223 static const unsigned int hscif0_data_pins[] = { 2224 /* RX, TX */ 2225 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14), 2226 }; 2227 2228 static const unsigned int hscif0_data_mux[] = { 2229 HRX0_MARK, HTX0_MARK, 2230 }; 2231 2232 static const unsigned int hscif0_clk_pins[] = { 2233 /* SCK */ 2234 RCAR_GP_PIN(5, 12), 2235 }; 2236 2237 static const unsigned int hscif0_clk_mux[] = { 2238 HSCK0_MARK, 2239 }; 2240 2241 static const unsigned int hscif0_ctrl_pins[] = { 2242 /* RTS, CTS */ 2243 RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15), 2244 }; 2245 2246 static const unsigned int hscif0_ctrl_mux[] = { 2247 HRTS0_N_MARK, HCTS0_N_MARK, 2248 }; 2249 2250 /* - HSCIF1 ----------------------------------------------------------------- */ 2251 static const unsigned int hscif1_data_a_pins[] = { 2252 /* RX, TX */ 2253 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6), 2254 }; 2255 2256 static const unsigned int hscif1_data_a_mux[] = { 2257 HRX1_A_MARK, HTX1_A_MARK, 2258 }; 2259 2260 static const unsigned int hscif1_clk_a_pins[] = { 2261 /* SCK */ 2262 RCAR_GP_PIN(6, 21), 2263 }; 2264 2265 static const unsigned int hscif1_clk_a_mux[] = { 2266 HSCK1_A_MARK, 2267 }; 2268 2269 static const unsigned int hscif1_ctrl_a_pins[] = { 2270 /* RTS, CTS */ 2271 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7), 2272 }; 2273 2274 static const unsigned int hscif1_ctrl_a_mux[] = { 2275 HRTS1_N_A_MARK, HCTS1_N_A_MARK, 2276 }; 2277 2278 static const unsigned int hscif1_data_b_pins[] = { 2279 /* RX, TX */ 2280 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), 2281 }; 2282 2283 static const unsigned int hscif1_data_b_mux[] = { 2284 HRX1_B_MARK, HTX1_B_MARK, 2285 }; 2286 2287 static const unsigned int hscif1_clk_b_pins[] = { 2288 /* SCK */ 2289 RCAR_GP_PIN(5, 0), 2290 }; 2291 2292 static const unsigned int hscif1_clk_b_mux[] = { 2293 HSCK1_B_MARK, 2294 }; 2295 2296 static const unsigned int hscif1_ctrl_b_pins[] = { 2297 /* RTS, CTS */ 2298 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3), 2299 }; 2300 2301 static const unsigned int hscif1_ctrl_b_mux[] = { 2302 HRTS1_N_B_MARK, HCTS1_N_B_MARK, 2303 }; 2304 2305 /* - HSCIF2 ----------------------------------------------------------------- */ 2306 static const unsigned int hscif2_data_a_pins[] = { 2307 /* RX, TX */ 2308 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), 2309 }; 2310 2311 static const unsigned int hscif2_data_a_mux[] = { 2312 HRX2_A_MARK, HTX2_A_MARK, 2313 }; 2314 2315 static const unsigned int hscif2_clk_a_pins[] = { 2316 /* SCK */ 2317 RCAR_GP_PIN(6, 10), 2318 }; 2319 2320 static const unsigned int hscif2_clk_a_mux[] = { 2321 HSCK2_A_MARK, 2322 }; 2323 2324 static const unsigned int hscif2_ctrl_a_pins[] = { 2325 /* RTS, CTS */ 2326 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6), 2327 }; 2328 2329 static const unsigned int hscif2_ctrl_a_mux[] = { 2330 HRTS2_N_A_MARK, HCTS2_N_A_MARK, 2331 }; 2332 2333 static const unsigned int hscif2_data_b_pins[] = { 2334 /* RX, TX */ 2335 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18), 2336 }; 2337 2338 static const unsigned int hscif2_data_b_mux[] = { 2339 HRX2_B_MARK, HTX2_B_MARK, 2340 }; 2341 2342 static const unsigned int hscif2_clk_b_pins[] = { 2343 /* SCK */ 2344 RCAR_GP_PIN(6, 21), 2345 }; 2346 2347 static const unsigned int hscif2_clk_b_mux[] = { 2348 HSCK2_B_MARK, 2349 }; 2350 2351 static const unsigned int hscif2_ctrl_b_pins[] = { 2352 /* RTS, CTS */ 2353 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19), 2354 }; 2355 2356 static const unsigned int hscif2_ctrl_b_mux[] = { 2357 HRTS2_N_B_MARK, HCTS2_N_B_MARK, 2358 }; 2359 2360 static const unsigned int hscif2_data_c_pins[] = { 2361 /* RX, TX */ 2362 RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26), 2363 }; 2364 2365 static const unsigned int hscif2_data_c_mux[] = { 2366 HRX2_C_MARK, HTX2_C_MARK, 2367 }; 2368 2369 static const unsigned int hscif2_clk_c_pins[] = { 2370 /* SCK */ 2371 RCAR_GP_PIN(6, 24), 2372 }; 2373 2374 static const unsigned int hscif2_clk_c_mux[] = { 2375 HSCK2_C_MARK, 2376 }; 2377 2378 static const unsigned int hscif2_ctrl_c_pins[] = { 2379 /* RTS, CTS */ 2380 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 27), 2381 }; 2382 2383 static const unsigned int hscif2_ctrl_c_mux[] = { 2384 HRTS2_N_C_MARK, HCTS2_N_C_MARK, 2385 }; 2386 2387 /* - HSCIF3 ----------------------------------------------------------------- */ 2388 static const unsigned int hscif3_data_a_pins[] = { 2389 /* RX, TX */ 2390 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24), 2391 }; 2392 2393 static const unsigned int hscif3_data_a_mux[] = { 2394 HRX3_A_MARK, HTX3_A_MARK, 2395 }; 2396 2397 static const unsigned int hscif3_clk_pins[] = { 2398 /* SCK */ 2399 RCAR_GP_PIN(1, 22), 2400 }; 2401 2402 static const unsigned int hscif3_clk_mux[] = { 2403 HSCK3_MARK, 2404 }; 2405 2406 static const unsigned int hscif3_ctrl_pins[] = { 2407 /* RTS, CTS */ 2408 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25), 2409 }; 2410 2411 static const unsigned int hscif3_ctrl_mux[] = { 2412 HRTS3_N_MARK, HCTS3_N_MARK, 2413 }; 2414 2415 static const unsigned int hscif3_data_b_pins[] = { 2416 /* RX, TX */ 2417 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), 2418 }; 2419 2420 static const unsigned int hscif3_data_b_mux[] = { 2421 HRX3_B_MARK, HTX3_B_MARK, 2422 }; 2423 2424 static const unsigned int hscif3_data_c_pins[] = { 2425 /* RX, TX */ 2426 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), 2427 }; 2428 2429 static const unsigned int hscif3_data_c_mux[] = { 2430 HRX3_C_MARK, HTX3_C_MARK, 2431 }; 2432 2433 static const unsigned int hscif3_data_d_pins[] = { 2434 /* RX, TX */ 2435 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), 2436 }; 2437 2438 static const unsigned int hscif3_data_d_mux[] = { 2439 HRX3_D_MARK, HTX3_D_MARK, 2440 }; 2441 2442 /* - HSCIF4 ----------------------------------------------------------------- */ 2443 static const unsigned int hscif4_data_a_pins[] = { 2444 /* RX, TX */ 2445 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), 2446 }; 2447 2448 static const unsigned int hscif4_data_a_mux[] = { 2449 HRX4_A_MARK, HTX4_A_MARK, 2450 }; 2451 2452 static const unsigned int hscif4_clk_pins[] = { 2453 /* SCK */ 2454 RCAR_GP_PIN(1, 11), 2455 }; 2456 2457 static const unsigned int hscif4_clk_mux[] = { 2458 HSCK4_MARK, 2459 }; 2460 2461 static const unsigned int hscif4_ctrl_pins[] = { 2462 /* RTS, CTS */ 2463 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), 2464 }; 2465 2466 static const unsigned int hscif4_ctrl_mux[] = { 2467 HRTS4_N_MARK, HCTS4_N_MARK, 2468 }; 2469 2470 static const unsigned int hscif4_data_b_pins[] = { 2471 /* RX, TX */ 2472 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), 2473 }; 2474 2475 static const unsigned int hscif4_data_b_mux[] = { 2476 HRX4_B_MARK, HTX4_B_MARK, 2477 }; 2478 2479 /* - I2C -------------------------------------------------------------------- */ 2480 static const unsigned int i2c0_pins[] = { 2481 /* SCL, SDA */ 2482 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), 2483 }; 2484 2485 static const unsigned int i2c0_mux[] = { 2486 SCL0_MARK, SDA0_MARK, 2487 }; 2488 2489 static const unsigned int i2c1_a_pins[] = { 2490 /* SDA, SCL */ 2491 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10), 2492 }; 2493 2494 static const unsigned int i2c1_a_mux[] = { 2495 SDA1_A_MARK, SCL1_A_MARK, 2496 }; 2497 2498 static const unsigned int i2c1_b_pins[] = { 2499 /* SDA, SCL */ 2500 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23), 2501 }; 2502 2503 static const unsigned int i2c1_b_mux[] = { 2504 SDA1_B_MARK, SCL1_B_MARK, 2505 }; 2506 2507 static const unsigned int i2c2_a_pins[] = { 2508 /* SDA, SCL */ 2509 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4), 2510 }; 2511 2512 static const unsigned int i2c2_a_mux[] = { 2513 SDA2_A_MARK, SCL2_A_MARK, 2514 }; 2515 2516 static const unsigned int i2c2_b_pins[] = { 2517 /* SDA, SCL */ 2518 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12), 2519 }; 2520 2521 static const unsigned int i2c2_b_mux[] = { 2522 SDA2_B_MARK, SCL2_B_MARK, 2523 }; 2524 2525 static const unsigned int i2c3_pins[] = { 2526 /* SCL, SDA */ 2527 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), 2528 }; 2529 2530 static const unsigned int i2c3_mux[] = { 2531 SCL3_MARK, SDA3_MARK, 2532 }; 2533 2534 static const unsigned int i2c5_pins[] = { 2535 /* SCL, SDA */ 2536 RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14), 2537 }; 2538 2539 static const unsigned int i2c5_mux[] = { 2540 SCL5_MARK, SDA5_MARK, 2541 }; 2542 2543 static const unsigned int i2c6_a_pins[] = { 2544 /* SDA, SCL */ 2545 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), 2546 }; 2547 2548 static const unsigned int i2c6_a_mux[] = { 2549 SDA6_A_MARK, SCL6_A_MARK, 2550 }; 2551 2552 static const unsigned int i2c6_b_pins[] = { 2553 /* SDA, SCL */ 2554 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25), 2555 }; 2556 2557 static const unsigned int i2c6_b_mux[] = { 2558 SDA6_B_MARK, SCL6_B_MARK, 2559 }; 2560 2561 static const unsigned int i2c6_c_pins[] = { 2562 /* SDA, SCL */ 2563 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), 2564 }; 2565 2566 static const unsigned int i2c6_c_mux[] = { 2567 SDA6_C_MARK, SCL6_C_MARK, 2568 }; 2569 2570 /* - INTC-EX ---------------------------------------------------------------- */ 2571 static const unsigned int intc_ex_irq0_pins[] = { 2572 /* IRQ0 */ 2573 RCAR_GP_PIN(2, 0), 2574 }; 2575 static const unsigned int intc_ex_irq0_mux[] = { 2576 IRQ0_MARK, 2577 }; 2578 static const unsigned int intc_ex_irq1_pins[] = { 2579 /* IRQ1 */ 2580 RCAR_GP_PIN(2, 1), 2581 }; 2582 static const unsigned int intc_ex_irq1_mux[] = { 2583 IRQ1_MARK, 2584 }; 2585 static const unsigned int intc_ex_irq2_pins[] = { 2586 /* IRQ2 */ 2587 RCAR_GP_PIN(2, 2), 2588 }; 2589 static const unsigned int intc_ex_irq2_mux[] = { 2590 IRQ2_MARK, 2591 }; 2592 static const unsigned int intc_ex_irq3_pins[] = { 2593 /* IRQ3 */ 2594 RCAR_GP_PIN(2, 3), 2595 }; 2596 static const unsigned int intc_ex_irq3_mux[] = { 2597 IRQ3_MARK, 2598 }; 2599 static const unsigned int intc_ex_irq4_pins[] = { 2600 /* IRQ4 */ 2601 RCAR_GP_PIN(2, 4), 2602 }; 2603 static const unsigned int intc_ex_irq4_mux[] = { 2604 IRQ4_MARK, 2605 }; 2606 static const unsigned int intc_ex_irq5_pins[] = { 2607 /* IRQ5 */ 2608 RCAR_GP_PIN(2, 5), 2609 }; 2610 static const unsigned int intc_ex_irq5_mux[] = { 2611 IRQ5_MARK, 2612 }; 2613 2614 /* - MSIOF0 ----------------------------------------------------------------- */ 2615 static const unsigned int msiof0_clk_pins[] = { 2616 /* SCK */ 2617 RCAR_GP_PIN(5, 17), 2618 }; 2619 static const unsigned int msiof0_clk_mux[] = { 2620 MSIOF0_SCK_MARK, 2621 }; 2622 static const unsigned int msiof0_sync_pins[] = { 2623 /* SYNC */ 2624 RCAR_GP_PIN(5, 18), 2625 }; 2626 static const unsigned int msiof0_sync_mux[] = { 2627 MSIOF0_SYNC_MARK, 2628 }; 2629 static const unsigned int msiof0_ss1_pins[] = { 2630 /* SS1 */ 2631 RCAR_GP_PIN(5, 19), 2632 }; 2633 static const unsigned int msiof0_ss1_mux[] = { 2634 MSIOF0_SS1_MARK, 2635 }; 2636 static const unsigned int msiof0_ss2_pins[] = { 2637 /* SS2 */ 2638 RCAR_GP_PIN(5, 21), 2639 }; 2640 static const unsigned int msiof0_ss2_mux[] = { 2641 MSIOF0_SS2_MARK, 2642 }; 2643 static const unsigned int msiof0_txd_pins[] = { 2644 /* TXD */ 2645 RCAR_GP_PIN(5, 20), 2646 }; 2647 static const unsigned int msiof0_txd_mux[] = { 2648 MSIOF0_TXD_MARK, 2649 }; 2650 static const unsigned int msiof0_rxd_pins[] = { 2651 /* RXD */ 2652 RCAR_GP_PIN(5, 22), 2653 }; 2654 static const unsigned int msiof0_rxd_mux[] = { 2655 MSIOF0_RXD_MARK, 2656 }; 2657 /* - MSIOF1 ----------------------------------------------------------------- */ 2658 static const unsigned int msiof1_clk_a_pins[] = { 2659 /* SCK */ 2660 RCAR_GP_PIN(6, 8), 2661 }; 2662 static const unsigned int msiof1_clk_a_mux[] = { 2663 MSIOF1_SCK_A_MARK, 2664 }; 2665 static const unsigned int msiof1_sync_a_pins[] = { 2666 /* SYNC */ 2667 RCAR_GP_PIN(6, 9), 2668 }; 2669 static const unsigned int msiof1_sync_a_mux[] = { 2670 MSIOF1_SYNC_A_MARK, 2671 }; 2672 static const unsigned int msiof1_ss1_a_pins[] = { 2673 /* SS1 */ 2674 RCAR_GP_PIN(6, 5), 2675 }; 2676 static const unsigned int msiof1_ss1_a_mux[] = { 2677 MSIOF1_SS1_A_MARK, 2678 }; 2679 static const unsigned int msiof1_ss2_a_pins[] = { 2680 /* SS2 */ 2681 RCAR_GP_PIN(6, 6), 2682 }; 2683 static const unsigned int msiof1_ss2_a_mux[] = { 2684 MSIOF1_SS2_A_MARK, 2685 }; 2686 static const unsigned int msiof1_txd_a_pins[] = { 2687 /* TXD */ 2688 RCAR_GP_PIN(6, 7), 2689 }; 2690 static const unsigned int msiof1_txd_a_mux[] = { 2691 MSIOF1_TXD_A_MARK, 2692 }; 2693 static const unsigned int msiof1_rxd_a_pins[] = { 2694 /* RXD */ 2695 RCAR_GP_PIN(6, 10), 2696 }; 2697 static const unsigned int msiof1_rxd_a_mux[] = { 2698 MSIOF1_RXD_A_MARK, 2699 }; 2700 static const unsigned int msiof1_clk_b_pins[] = { 2701 /* SCK */ 2702 RCAR_GP_PIN(5, 9), 2703 }; 2704 static const unsigned int msiof1_clk_b_mux[] = { 2705 MSIOF1_SCK_B_MARK, 2706 }; 2707 static const unsigned int msiof1_sync_b_pins[] = { 2708 /* SYNC */ 2709 RCAR_GP_PIN(5, 3), 2710 }; 2711 static const unsigned int msiof1_sync_b_mux[] = { 2712 MSIOF1_SYNC_B_MARK, 2713 }; 2714 static const unsigned int msiof1_ss1_b_pins[] = { 2715 /* SS1 */ 2716 RCAR_GP_PIN(5, 4), 2717 }; 2718 static const unsigned int msiof1_ss1_b_mux[] = { 2719 MSIOF1_SS1_B_MARK, 2720 }; 2721 static const unsigned int msiof1_ss2_b_pins[] = { 2722 /* SS2 */ 2723 RCAR_GP_PIN(5, 0), 2724 }; 2725 static const unsigned int msiof1_ss2_b_mux[] = { 2726 MSIOF1_SS2_B_MARK, 2727 }; 2728 static const unsigned int msiof1_txd_b_pins[] = { 2729 /* TXD */ 2730 RCAR_GP_PIN(5, 8), 2731 }; 2732 static const unsigned int msiof1_txd_b_mux[] = { 2733 MSIOF1_TXD_B_MARK, 2734 }; 2735 static const unsigned int msiof1_rxd_b_pins[] = { 2736 /* RXD */ 2737 RCAR_GP_PIN(5, 7), 2738 }; 2739 static const unsigned int msiof1_rxd_b_mux[] = { 2740 MSIOF1_RXD_B_MARK, 2741 }; 2742 static const unsigned int msiof1_clk_c_pins[] = { 2743 /* SCK */ 2744 RCAR_GP_PIN(6, 17), 2745 }; 2746 static const unsigned int msiof1_clk_c_mux[] = { 2747 MSIOF1_SCK_C_MARK, 2748 }; 2749 static const unsigned int msiof1_sync_c_pins[] = { 2750 /* SYNC */ 2751 RCAR_GP_PIN(6, 18), 2752 }; 2753 static const unsigned int msiof1_sync_c_mux[] = { 2754 MSIOF1_SYNC_C_MARK, 2755 }; 2756 static const unsigned int msiof1_ss1_c_pins[] = { 2757 /* SS1 */ 2758 RCAR_GP_PIN(6, 21), 2759 }; 2760 static const unsigned int msiof1_ss1_c_mux[] = { 2761 MSIOF1_SS1_C_MARK, 2762 }; 2763 static const unsigned int msiof1_ss2_c_pins[] = { 2764 /* SS2 */ 2765 RCAR_GP_PIN(6, 27), 2766 }; 2767 static const unsigned int msiof1_ss2_c_mux[] = { 2768 MSIOF1_SS2_C_MARK, 2769 }; 2770 static const unsigned int msiof1_txd_c_pins[] = { 2771 /* TXD */ 2772 RCAR_GP_PIN(6, 20), 2773 }; 2774 static const unsigned int msiof1_txd_c_mux[] = { 2775 MSIOF1_TXD_C_MARK, 2776 }; 2777 static const unsigned int msiof1_rxd_c_pins[] = { 2778 /* RXD */ 2779 RCAR_GP_PIN(6, 19), 2780 }; 2781 static const unsigned int msiof1_rxd_c_mux[] = { 2782 MSIOF1_RXD_C_MARK, 2783 }; 2784 static const unsigned int msiof1_clk_d_pins[] = { 2785 /* SCK */ 2786 RCAR_GP_PIN(5, 12), 2787 }; 2788 static const unsigned int msiof1_clk_d_mux[] = { 2789 MSIOF1_SCK_D_MARK, 2790 }; 2791 static const unsigned int msiof1_sync_d_pins[] = { 2792 /* SYNC */ 2793 RCAR_GP_PIN(5, 15), 2794 }; 2795 static const unsigned int msiof1_sync_d_mux[] = { 2796 MSIOF1_SYNC_D_MARK, 2797 }; 2798 static const unsigned int msiof1_ss1_d_pins[] = { 2799 /* SS1 */ 2800 RCAR_GP_PIN(5, 16), 2801 }; 2802 static const unsigned int msiof1_ss1_d_mux[] = { 2803 MSIOF1_SS1_D_MARK, 2804 }; 2805 static const unsigned int msiof1_ss2_d_pins[] = { 2806 /* SS2 */ 2807 RCAR_GP_PIN(5, 21), 2808 }; 2809 static const unsigned int msiof1_ss2_d_mux[] = { 2810 MSIOF1_SS2_D_MARK, 2811 }; 2812 static const unsigned int msiof1_txd_d_pins[] = { 2813 /* TXD */ 2814 RCAR_GP_PIN(5, 14), 2815 }; 2816 static const unsigned int msiof1_txd_d_mux[] = { 2817 MSIOF1_TXD_D_MARK, 2818 }; 2819 static const unsigned int msiof1_rxd_d_pins[] = { 2820 /* RXD */ 2821 RCAR_GP_PIN(5, 13), 2822 }; 2823 static const unsigned int msiof1_rxd_d_mux[] = { 2824 MSIOF1_RXD_D_MARK, 2825 }; 2826 static const unsigned int msiof1_clk_e_pins[] = { 2827 /* SCK */ 2828 RCAR_GP_PIN(3, 0), 2829 }; 2830 static const unsigned int msiof1_clk_e_mux[] = { 2831 MSIOF1_SCK_E_MARK, 2832 }; 2833 static const unsigned int msiof1_sync_e_pins[] = { 2834 /* SYNC */ 2835 RCAR_GP_PIN(3, 1), 2836 }; 2837 static const unsigned int msiof1_sync_e_mux[] = { 2838 MSIOF1_SYNC_E_MARK, 2839 }; 2840 static const unsigned int msiof1_ss1_e_pins[] = { 2841 /* SS1 */ 2842 RCAR_GP_PIN(3, 4), 2843 }; 2844 static const unsigned int msiof1_ss1_e_mux[] = { 2845 MSIOF1_SS1_E_MARK, 2846 }; 2847 static const unsigned int msiof1_ss2_e_pins[] = { 2848 /* SS2 */ 2849 RCAR_GP_PIN(3, 5), 2850 }; 2851 static const unsigned int msiof1_ss2_e_mux[] = { 2852 MSIOF1_SS2_E_MARK, 2853 }; 2854 static const unsigned int msiof1_txd_e_pins[] = { 2855 /* TXD */ 2856 RCAR_GP_PIN(3, 3), 2857 }; 2858 static const unsigned int msiof1_txd_e_mux[] = { 2859 MSIOF1_TXD_E_MARK, 2860 }; 2861 static const unsigned int msiof1_rxd_e_pins[] = { 2862 /* RXD */ 2863 RCAR_GP_PIN(3, 2), 2864 }; 2865 static const unsigned int msiof1_rxd_e_mux[] = { 2866 MSIOF1_RXD_E_MARK, 2867 }; 2868 static const unsigned int msiof1_clk_f_pins[] = { 2869 /* SCK */ 2870 RCAR_GP_PIN(5, 23), 2871 }; 2872 static const unsigned int msiof1_clk_f_mux[] = { 2873 MSIOF1_SCK_F_MARK, 2874 }; 2875 static const unsigned int msiof1_sync_f_pins[] = { 2876 /* SYNC */ 2877 RCAR_GP_PIN(5, 24), 2878 }; 2879 static const unsigned int msiof1_sync_f_mux[] = { 2880 MSIOF1_SYNC_F_MARK, 2881 }; 2882 static const unsigned int msiof1_ss1_f_pins[] = { 2883 /* SS1 */ 2884 RCAR_GP_PIN(6, 1), 2885 }; 2886 static const unsigned int msiof1_ss1_f_mux[] = { 2887 MSIOF1_SS1_F_MARK, 2888 }; 2889 static const unsigned int msiof1_ss2_f_pins[] = { 2890 /* SS2 */ 2891 RCAR_GP_PIN(6, 2), 2892 }; 2893 static const unsigned int msiof1_ss2_f_mux[] = { 2894 MSIOF1_SS2_F_MARK, 2895 }; 2896 static const unsigned int msiof1_txd_f_pins[] = { 2897 /* TXD */ 2898 RCAR_GP_PIN(6, 0), 2899 }; 2900 static const unsigned int msiof1_txd_f_mux[] = { 2901 MSIOF1_TXD_F_MARK, 2902 }; 2903 static const unsigned int msiof1_rxd_f_pins[] = { 2904 /* RXD */ 2905 RCAR_GP_PIN(5, 25), 2906 }; 2907 static const unsigned int msiof1_rxd_f_mux[] = { 2908 MSIOF1_RXD_F_MARK, 2909 }; 2910 static const unsigned int msiof1_clk_g_pins[] = { 2911 /* SCK */ 2912 RCAR_GP_PIN(3, 6), 2913 }; 2914 static const unsigned int msiof1_clk_g_mux[] = { 2915 MSIOF1_SCK_G_MARK, 2916 }; 2917 static const unsigned int msiof1_sync_g_pins[] = { 2918 /* SYNC */ 2919 RCAR_GP_PIN(3, 7), 2920 }; 2921 static const unsigned int msiof1_sync_g_mux[] = { 2922 MSIOF1_SYNC_G_MARK, 2923 }; 2924 static const unsigned int msiof1_ss1_g_pins[] = { 2925 /* SS1 */ 2926 RCAR_GP_PIN(3, 10), 2927 }; 2928 static const unsigned int msiof1_ss1_g_mux[] = { 2929 MSIOF1_SS1_G_MARK, 2930 }; 2931 static const unsigned int msiof1_ss2_g_pins[] = { 2932 /* SS2 */ 2933 RCAR_GP_PIN(3, 11), 2934 }; 2935 static const unsigned int msiof1_ss2_g_mux[] = { 2936 MSIOF1_SS2_G_MARK, 2937 }; 2938 static const unsigned int msiof1_txd_g_pins[] = { 2939 /* TXD */ 2940 RCAR_GP_PIN(3, 9), 2941 }; 2942 static const unsigned int msiof1_txd_g_mux[] = { 2943 MSIOF1_TXD_G_MARK, 2944 }; 2945 static const unsigned int msiof1_rxd_g_pins[] = { 2946 /* RXD */ 2947 RCAR_GP_PIN(3, 8), 2948 }; 2949 static const unsigned int msiof1_rxd_g_mux[] = { 2950 MSIOF1_RXD_G_MARK, 2951 }; 2952 /* - MSIOF2 ----------------------------------------------------------------- */ 2953 static const unsigned int msiof2_clk_a_pins[] = { 2954 /* SCK */ 2955 RCAR_GP_PIN(1, 9), 2956 }; 2957 static const unsigned int msiof2_clk_a_mux[] = { 2958 MSIOF2_SCK_A_MARK, 2959 }; 2960 static const unsigned int msiof2_sync_a_pins[] = { 2961 /* SYNC */ 2962 RCAR_GP_PIN(1, 8), 2963 }; 2964 static const unsigned int msiof2_sync_a_mux[] = { 2965 MSIOF2_SYNC_A_MARK, 2966 }; 2967 static const unsigned int msiof2_ss1_a_pins[] = { 2968 /* SS1 */ 2969 RCAR_GP_PIN(1, 6), 2970 }; 2971 static const unsigned int msiof2_ss1_a_mux[] = { 2972 MSIOF2_SS1_A_MARK, 2973 }; 2974 static const unsigned int msiof2_ss2_a_pins[] = { 2975 /* SS2 */ 2976 RCAR_GP_PIN(1, 7), 2977 }; 2978 static const unsigned int msiof2_ss2_a_mux[] = { 2979 MSIOF2_SS2_A_MARK, 2980 }; 2981 static const unsigned int msiof2_txd_a_pins[] = { 2982 /* TXD */ 2983 RCAR_GP_PIN(1, 11), 2984 }; 2985 static const unsigned int msiof2_txd_a_mux[] = { 2986 MSIOF2_TXD_A_MARK, 2987 }; 2988 static const unsigned int msiof2_rxd_a_pins[] = { 2989 /* RXD */ 2990 RCAR_GP_PIN(1, 10), 2991 }; 2992 static const unsigned int msiof2_rxd_a_mux[] = { 2993 MSIOF2_RXD_A_MARK, 2994 }; 2995 static const unsigned int msiof2_clk_b_pins[] = { 2996 /* SCK */ 2997 RCAR_GP_PIN(0, 4), 2998 }; 2999 static const unsigned int msiof2_clk_b_mux[] = { 3000 MSIOF2_SCK_B_MARK, 3001 }; 3002 static const unsigned int msiof2_sync_b_pins[] = { 3003 /* SYNC */ 3004 RCAR_GP_PIN(0, 5), 3005 }; 3006 static const unsigned int msiof2_sync_b_mux[] = { 3007 MSIOF2_SYNC_B_MARK, 3008 }; 3009 static const unsigned int msiof2_ss1_b_pins[] = { 3010 /* SS1 */ 3011 RCAR_GP_PIN(0, 0), 3012 }; 3013 static const unsigned int msiof2_ss1_b_mux[] = { 3014 MSIOF2_SS1_B_MARK, 3015 }; 3016 static const unsigned int msiof2_ss2_b_pins[] = { 3017 /* SS2 */ 3018 RCAR_GP_PIN(0, 1), 3019 }; 3020 static const unsigned int msiof2_ss2_b_mux[] = { 3021 MSIOF2_SS2_B_MARK, 3022 }; 3023 static const unsigned int msiof2_txd_b_pins[] = { 3024 /* TXD */ 3025 RCAR_GP_PIN(0, 7), 3026 }; 3027 static const unsigned int msiof2_txd_b_mux[] = { 3028 MSIOF2_TXD_B_MARK, 3029 }; 3030 static const unsigned int msiof2_rxd_b_pins[] = { 3031 /* RXD */ 3032 RCAR_GP_PIN(0, 6), 3033 }; 3034 static const unsigned int msiof2_rxd_b_mux[] = { 3035 MSIOF2_RXD_B_MARK, 3036 }; 3037 static const unsigned int msiof2_clk_c_pins[] = { 3038 /* SCK */ 3039 RCAR_GP_PIN(2, 12), 3040 }; 3041 static const unsigned int msiof2_clk_c_mux[] = { 3042 MSIOF2_SCK_C_MARK, 3043 }; 3044 static const unsigned int msiof2_sync_c_pins[] = { 3045 /* SYNC */ 3046 RCAR_GP_PIN(2, 11), 3047 }; 3048 static const unsigned int msiof2_sync_c_mux[] = { 3049 MSIOF2_SYNC_C_MARK, 3050 }; 3051 static const unsigned int msiof2_ss1_c_pins[] = { 3052 /* SS1 */ 3053 RCAR_GP_PIN(2, 10), 3054 }; 3055 static const unsigned int msiof2_ss1_c_mux[] = { 3056 MSIOF2_SS1_C_MARK, 3057 }; 3058 static const unsigned int msiof2_ss2_c_pins[] = { 3059 /* SS2 */ 3060 RCAR_GP_PIN(2, 9), 3061 }; 3062 static const unsigned int msiof2_ss2_c_mux[] = { 3063 MSIOF2_SS2_C_MARK, 3064 }; 3065 static const unsigned int msiof2_txd_c_pins[] = { 3066 /* TXD */ 3067 RCAR_GP_PIN(2, 14), 3068 }; 3069 static const unsigned int msiof2_txd_c_mux[] = { 3070 MSIOF2_TXD_C_MARK, 3071 }; 3072 static const unsigned int msiof2_rxd_c_pins[] = { 3073 /* RXD */ 3074 RCAR_GP_PIN(2, 13), 3075 }; 3076 static const unsigned int msiof2_rxd_c_mux[] = { 3077 MSIOF2_RXD_C_MARK, 3078 }; 3079 static const unsigned int msiof2_clk_d_pins[] = { 3080 /* SCK */ 3081 RCAR_GP_PIN(0, 8), 3082 }; 3083 static const unsigned int msiof2_clk_d_mux[] = { 3084 MSIOF2_SCK_D_MARK, 3085 }; 3086 static const unsigned int msiof2_sync_d_pins[] = { 3087 /* SYNC */ 3088 RCAR_GP_PIN(0, 9), 3089 }; 3090 static const unsigned int msiof2_sync_d_mux[] = { 3091 MSIOF2_SYNC_D_MARK, 3092 }; 3093 static const unsigned int msiof2_ss1_d_pins[] = { 3094 /* SS1 */ 3095 RCAR_GP_PIN(0, 12), 3096 }; 3097 static const unsigned int msiof2_ss1_d_mux[] = { 3098 MSIOF2_SS1_D_MARK, 3099 }; 3100 static const unsigned int msiof2_ss2_d_pins[] = { 3101 /* SS2 */ 3102 RCAR_GP_PIN(0, 13), 3103 }; 3104 static const unsigned int msiof2_ss2_d_mux[] = { 3105 MSIOF2_SS2_D_MARK, 3106 }; 3107 static const unsigned int msiof2_txd_d_pins[] = { 3108 /* TXD */ 3109 RCAR_GP_PIN(0, 11), 3110 }; 3111 static const unsigned int msiof2_txd_d_mux[] = { 3112 MSIOF2_TXD_D_MARK, 3113 }; 3114 static const unsigned int msiof2_rxd_d_pins[] = { 3115 /* RXD */ 3116 RCAR_GP_PIN(0, 10), 3117 }; 3118 static const unsigned int msiof2_rxd_d_mux[] = { 3119 MSIOF2_RXD_D_MARK, 3120 }; 3121 /* - MSIOF3 ----------------------------------------------------------------- */ 3122 static const unsigned int msiof3_clk_a_pins[] = { 3123 /* SCK */ 3124 RCAR_GP_PIN(0, 0), 3125 }; 3126 static const unsigned int msiof3_clk_a_mux[] = { 3127 MSIOF3_SCK_A_MARK, 3128 }; 3129 static const unsigned int msiof3_sync_a_pins[] = { 3130 /* SYNC */ 3131 RCAR_GP_PIN(0, 1), 3132 }; 3133 static const unsigned int msiof3_sync_a_mux[] = { 3134 MSIOF3_SYNC_A_MARK, 3135 }; 3136 static const unsigned int msiof3_ss1_a_pins[] = { 3137 /* SS1 */ 3138 RCAR_GP_PIN(0, 14), 3139 }; 3140 static const unsigned int msiof3_ss1_a_mux[] = { 3141 MSIOF3_SS1_A_MARK, 3142 }; 3143 static const unsigned int msiof3_ss2_a_pins[] = { 3144 /* SS2 */ 3145 RCAR_GP_PIN(0, 15), 3146 }; 3147 static const unsigned int msiof3_ss2_a_mux[] = { 3148 MSIOF3_SS2_A_MARK, 3149 }; 3150 static const unsigned int msiof3_txd_a_pins[] = { 3151 /* TXD */ 3152 RCAR_GP_PIN(0, 3), 3153 }; 3154 static const unsigned int msiof3_txd_a_mux[] = { 3155 MSIOF3_TXD_A_MARK, 3156 }; 3157 static const unsigned int msiof3_rxd_a_pins[] = { 3158 /* RXD */ 3159 RCAR_GP_PIN(0, 2), 3160 }; 3161 static const unsigned int msiof3_rxd_a_mux[] = { 3162 MSIOF3_RXD_A_MARK, 3163 }; 3164 static const unsigned int msiof3_clk_b_pins[] = { 3165 /* SCK */ 3166 RCAR_GP_PIN(1, 2), 3167 }; 3168 static const unsigned int msiof3_clk_b_mux[] = { 3169 MSIOF3_SCK_B_MARK, 3170 }; 3171 static const unsigned int msiof3_sync_b_pins[] = { 3172 /* SYNC */ 3173 RCAR_GP_PIN(1, 0), 3174 }; 3175 static const unsigned int msiof3_sync_b_mux[] = { 3176 MSIOF3_SYNC_B_MARK, 3177 }; 3178 static const unsigned int msiof3_ss1_b_pins[] = { 3179 /* SS1 */ 3180 RCAR_GP_PIN(1, 4), 3181 }; 3182 static const unsigned int msiof3_ss1_b_mux[] = { 3183 MSIOF3_SS1_B_MARK, 3184 }; 3185 static const unsigned int msiof3_ss2_b_pins[] = { 3186 /* SS2 */ 3187 RCAR_GP_PIN(1, 5), 3188 }; 3189 static const unsigned int msiof3_ss2_b_mux[] = { 3190 MSIOF3_SS2_B_MARK, 3191 }; 3192 static const unsigned int msiof3_txd_b_pins[] = { 3193 /* TXD */ 3194 RCAR_GP_PIN(1, 1), 3195 }; 3196 static const unsigned int msiof3_txd_b_mux[] = { 3197 MSIOF3_TXD_B_MARK, 3198 }; 3199 static const unsigned int msiof3_rxd_b_pins[] = { 3200 /* RXD */ 3201 RCAR_GP_PIN(1, 3), 3202 }; 3203 static const unsigned int msiof3_rxd_b_mux[] = { 3204 MSIOF3_RXD_B_MARK, 3205 }; 3206 static const unsigned int msiof3_clk_c_pins[] = { 3207 /* SCK */ 3208 RCAR_GP_PIN(1, 12), 3209 }; 3210 static const unsigned int msiof3_clk_c_mux[] = { 3211 MSIOF3_SCK_C_MARK, 3212 }; 3213 static const unsigned int msiof3_sync_c_pins[] = { 3214 /* SYNC */ 3215 RCAR_GP_PIN(1, 13), 3216 }; 3217 static const unsigned int msiof3_sync_c_mux[] = { 3218 MSIOF3_SYNC_C_MARK, 3219 }; 3220 static const unsigned int msiof3_txd_c_pins[] = { 3221 /* TXD */ 3222 RCAR_GP_PIN(1, 15), 3223 }; 3224 static const unsigned int msiof3_txd_c_mux[] = { 3225 MSIOF3_TXD_C_MARK, 3226 }; 3227 static const unsigned int msiof3_rxd_c_pins[] = { 3228 /* RXD */ 3229 RCAR_GP_PIN(1, 14), 3230 }; 3231 static const unsigned int msiof3_rxd_c_mux[] = { 3232 MSIOF3_RXD_C_MARK, 3233 }; 3234 static const unsigned int msiof3_clk_d_pins[] = { 3235 /* SCK */ 3236 RCAR_GP_PIN(1, 22), 3237 }; 3238 static const unsigned int msiof3_clk_d_mux[] = { 3239 MSIOF3_SCK_D_MARK, 3240 }; 3241 static const unsigned int msiof3_sync_d_pins[] = { 3242 /* SYNC */ 3243 RCAR_GP_PIN(1, 23), 3244 }; 3245 static const unsigned int msiof3_sync_d_mux[] = { 3246 MSIOF3_SYNC_D_MARK, 3247 }; 3248 static const unsigned int msiof3_ss1_d_pins[] = { 3249 /* SS1 */ 3250 RCAR_GP_PIN(1, 26), 3251 }; 3252 static const unsigned int msiof3_ss1_d_mux[] = { 3253 MSIOF3_SS1_D_MARK, 3254 }; 3255 static const unsigned int msiof3_txd_d_pins[] = { 3256 /* TXD */ 3257 RCAR_GP_PIN(1, 25), 3258 }; 3259 static const unsigned int msiof3_txd_d_mux[] = { 3260 MSIOF3_TXD_D_MARK, 3261 }; 3262 static const unsigned int msiof3_rxd_d_pins[] = { 3263 /* RXD */ 3264 RCAR_GP_PIN(1, 24), 3265 }; 3266 static const unsigned int msiof3_rxd_d_mux[] = { 3267 MSIOF3_RXD_D_MARK, 3268 }; 3269 static const unsigned int msiof3_clk_e_pins[] = { 3270 /* SCK */ 3271 RCAR_GP_PIN(2, 3), 3272 }; 3273 static const unsigned int msiof3_clk_e_mux[] = { 3274 MSIOF3_SCK_E_MARK, 3275 }; 3276 static const unsigned int msiof3_sync_e_pins[] = { 3277 /* SYNC */ 3278 RCAR_GP_PIN(2, 2), 3279 }; 3280 static const unsigned int msiof3_sync_e_mux[] = { 3281 MSIOF3_SYNC_E_MARK, 3282 }; 3283 static const unsigned int msiof3_ss1_e_pins[] = { 3284 /* SS1 */ 3285 RCAR_GP_PIN(2, 1), 3286 }; 3287 static const unsigned int msiof3_ss1_e_mux[] = { 3288 MSIOF3_SS1_E_MARK, 3289 }; 3290 static const unsigned int msiof3_ss2_e_pins[] = { 3291 /* SS2 */ 3292 RCAR_GP_PIN(2, 0), 3293 }; 3294 static const unsigned int msiof3_ss2_e_mux[] = { 3295 MSIOF3_SS2_E_MARK, 3296 }; 3297 static const unsigned int msiof3_txd_e_pins[] = { 3298 /* TXD */ 3299 RCAR_GP_PIN(2, 5), 3300 }; 3301 static const unsigned int msiof3_txd_e_mux[] = { 3302 MSIOF3_TXD_E_MARK, 3303 }; 3304 static const unsigned int msiof3_rxd_e_pins[] = { 3305 /* RXD */ 3306 RCAR_GP_PIN(2, 4), 3307 }; 3308 static const unsigned int msiof3_rxd_e_mux[] = { 3309 MSIOF3_RXD_E_MARK, 3310 }; 3311 3312 /* - PWM0 --------------------------------------------------------------------*/ 3313 static const unsigned int pwm0_pins[] = { 3314 /* PWM */ 3315 RCAR_GP_PIN(2, 6), 3316 }; 3317 static const unsigned int pwm0_mux[] = { 3318 PWM0_MARK, 3319 }; 3320 /* - PWM1 --------------------------------------------------------------------*/ 3321 static const unsigned int pwm1_a_pins[] = { 3322 /* PWM */ 3323 RCAR_GP_PIN(2, 7), 3324 }; 3325 static const unsigned int pwm1_a_mux[] = { 3326 PWM1_A_MARK, 3327 }; 3328 static const unsigned int pwm1_b_pins[] = { 3329 /* PWM */ 3330 RCAR_GP_PIN(1, 8), 3331 }; 3332 static const unsigned int pwm1_b_mux[] = { 3333 PWM1_B_MARK, 3334 }; 3335 /* - PWM2 --------------------------------------------------------------------*/ 3336 static const unsigned int pwm2_a_pins[] = { 3337 /* PWM */ 3338 RCAR_GP_PIN(2, 8), 3339 }; 3340 static const unsigned int pwm2_a_mux[] = { 3341 PWM2_A_MARK, 3342 }; 3343 static const unsigned int pwm2_b_pins[] = { 3344 /* PWM */ 3345 RCAR_GP_PIN(1, 11), 3346 }; 3347 static const unsigned int pwm2_b_mux[] = { 3348 PWM2_B_MARK, 3349 }; 3350 /* - PWM3 --------------------------------------------------------------------*/ 3351 static const unsigned int pwm3_a_pins[] = { 3352 /* PWM */ 3353 RCAR_GP_PIN(1, 0), 3354 }; 3355 static const unsigned int pwm3_a_mux[] = { 3356 PWM3_A_MARK, 3357 }; 3358 static const unsigned int pwm3_b_pins[] = { 3359 /* PWM */ 3360 RCAR_GP_PIN(2, 2), 3361 }; 3362 static const unsigned int pwm3_b_mux[] = { 3363 PWM3_B_MARK, 3364 }; 3365 /* - PWM4 --------------------------------------------------------------------*/ 3366 static const unsigned int pwm4_a_pins[] = { 3367 /* PWM */ 3368 RCAR_GP_PIN(1, 1), 3369 }; 3370 static const unsigned int pwm4_a_mux[] = { 3371 PWM4_A_MARK, 3372 }; 3373 static const unsigned int pwm4_b_pins[] = { 3374 /* PWM */ 3375 RCAR_GP_PIN(2, 3), 3376 }; 3377 static const unsigned int pwm4_b_mux[] = { 3378 PWM4_B_MARK, 3379 }; 3380 /* - PWM5 --------------------------------------------------------------------*/ 3381 static const unsigned int pwm5_a_pins[] = { 3382 /* PWM */ 3383 RCAR_GP_PIN(1, 2), 3384 }; 3385 static const unsigned int pwm5_a_mux[] = { 3386 PWM5_A_MARK, 3387 }; 3388 static const unsigned int pwm5_b_pins[] = { 3389 /* PWM */ 3390 RCAR_GP_PIN(2, 4), 3391 }; 3392 static const unsigned int pwm5_b_mux[] = { 3393 PWM5_B_MARK, 3394 }; 3395 /* - PWM6 --------------------------------------------------------------------*/ 3396 static const unsigned int pwm6_a_pins[] = { 3397 /* PWM */ 3398 RCAR_GP_PIN(1, 3), 3399 }; 3400 static const unsigned int pwm6_a_mux[] = { 3401 PWM6_A_MARK, 3402 }; 3403 static const unsigned int pwm6_b_pins[] = { 3404 /* PWM */ 3405 RCAR_GP_PIN(2, 5), 3406 }; 3407 static const unsigned int pwm6_b_mux[] = { 3408 PWM6_B_MARK, 3409 }; 3410 3411 /* - SATA --------------------------------------------------------------------*/ 3412 static const unsigned int sata0_devslp_a_pins[] = { 3413 /* DEVSLP */ 3414 RCAR_GP_PIN(6, 16), 3415 }; 3416 3417 static const unsigned int sata0_devslp_a_mux[] = { 3418 SATA_DEVSLP_A_MARK, 3419 }; 3420 3421 static const unsigned int sata0_devslp_b_pins[] = { 3422 /* DEVSLP */ 3423 RCAR_GP_PIN(4, 6), 3424 }; 3425 3426 static const unsigned int sata0_devslp_b_mux[] = { 3427 SATA_DEVSLP_B_MARK, 3428 }; 3429 3430 /* - SCIF0 ------------------------------------------------------------------ */ 3431 static const unsigned int scif0_data_pins[] = { 3432 /* RX, TX */ 3433 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), 3434 }; 3435 static const unsigned int scif0_data_mux[] = { 3436 RX0_MARK, TX0_MARK, 3437 }; 3438 static const unsigned int scif0_clk_pins[] = { 3439 /* SCK */ 3440 RCAR_GP_PIN(5, 0), 3441 }; 3442 static const unsigned int scif0_clk_mux[] = { 3443 SCK0_MARK, 3444 }; 3445 static const unsigned int scif0_ctrl_pins[] = { 3446 /* RTS, CTS */ 3447 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3), 3448 }; 3449 static const unsigned int scif0_ctrl_mux[] = { 3450 RTS0_N_MARK, CTS0_N_MARK, 3451 }; 3452 /* - SCIF1 ------------------------------------------------------------------ */ 3453 static const unsigned int scif1_data_a_pins[] = { 3454 /* RX, TX */ 3455 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6), 3456 }; 3457 static const unsigned int scif1_data_a_mux[] = { 3458 RX1_A_MARK, TX1_A_MARK, 3459 }; 3460 static const unsigned int scif1_clk_pins[] = { 3461 /* SCK */ 3462 RCAR_GP_PIN(6, 21), 3463 }; 3464 static const unsigned int scif1_clk_mux[] = { 3465 SCK1_MARK, 3466 }; 3467 static const unsigned int scif1_ctrl_pins[] = { 3468 /* RTS, CTS */ 3469 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7), 3470 }; 3471 static const unsigned int scif1_ctrl_mux[] = { 3472 RTS1_N_MARK, CTS1_N_MARK, 3473 }; 3474 static const unsigned int scif1_data_b_pins[] = { 3475 /* RX, TX */ 3476 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25), 3477 }; 3478 static const unsigned int scif1_data_b_mux[] = { 3479 RX1_B_MARK, TX1_B_MARK, 3480 }; 3481 /* - SCIF2 ------------------------------------------------------------------ */ 3482 static const unsigned int scif2_data_a_pins[] = { 3483 /* RX, TX */ 3484 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10), 3485 }; 3486 static const unsigned int scif2_data_a_mux[] = { 3487 RX2_A_MARK, TX2_A_MARK, 3488 }; 3489 static const unsigned int scif2_clk_pins[] = { 3490 /* SCK */ 3491 RCAR_GP_PIN(5, 9), 3492 }; 3493 static const unsigned int scif2_clk_mux[] = { 3494 SCK2_MARK, 3495 }; 3496 static const unsigned int scif2_data_b_pins[] = { 3497 /* RX, TX */ 3498 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16), 3499 }; 3500 static const unsigned int scif2_data_b_mux[] = { 3501 RX2_B_MARK, TX2_B_MARK, 3502 }; 3503 /* - SCIF3 ------------------------------------------------------------------ */ 3504 static const unsigned int scif3_data_a_pins[] = { 3505 /* RX, TX */ 3506 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24), 3507 }; 3508 static const unsigned int scif3_data_a_mux[] = { 3509 RX3_A_MARK, TX3_A_MARK, 3510 }; 3511 static const unsigned int scif3_clk_pins[] = { 3512 /* SCK */ 3513 RCAR_GP_PIN(1, 22), 3514 }; 3515 static const unsigned int scif3_clk_mux[] = { 3516 SCK3_MARK, 3517 }; 3518 static const unsigned int scif3_ctrl_pins[] = { 3519 /* RTS, CTS */ 3520 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25), 3521 }; 3522 static const unsigned int scif3_ctrl_mux[] = { 3523 RTS3_N_MARK, CTS3_N_MARK, 3524 }; 3525 static const unsigned int scif3_data_b_pins[] = { 3526 /* RX, TX */ 3527 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), 3528 }; 3529 static const unsigned int scif3_data_b_mux[] = { 3530 RX3_B_MARK, TX3_B_MARK, 3531 }; 3532 /* - SCIF4 ------------------------------------------------------------------ */ 3533 static const unsigned int scif4_data_a_pins[] = { 3534 /* RX, TX */ 3535 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12), 3536 }; 3537 static const unsigned int scif4_data_a_mux[] = { 3538 RX4_A_MARK, TX4_A_MARK, 3539 }; 3540 static const unsigned int scif4_clk_a_pins[] = { 3541 /* SCK */ 3542 RCAR_GP_PIN(2, 10), 3543 }; 3544 static const unsigned int scif4_clk_a_mux[] = { 3545 SCK4_A_MARK, 3546 }; 3547 static const unsigned int scif4_ctrl_a_pins[] = { 3548 /* RTS, CTS */ 3549 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13), 3550 }; 3551 static const unsigned int scif4_ctrl_a_mux[] = { 3552 RTS4_N_A_MARK, CTS4_N_A_MARK, 3553 }; 3554 static const unsigned int scif4_data_b_pins[] = { 3555 /* RX, TX */ 3556 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 3557 }; 3558 static const unsigned int scif4_data_b_mux[] = { 3559 RX4_B_MARK, TX4_B_MARK, 3560 }; 3561 static const unsigned int scif4_clk_b_pins[] = { 3562 /* SCK */ 3563 RCAR_GP_PIN(1, 5), 3564 }; 3565 static const unsigned int scif4_clk_b_mux[] = { 3566 SCK4_B_MARK, 3567 }; 3568 static const unsigned int scif4_ctrl_b_pins[] = { 3569 /* RTS, CTS */ 3570 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9), 3571 }; 3572 static const unsigned int scif4_ctrl_b_mux[] = { 3573 RTS4_N_B_MARK, CTS4_N_B_MARK, 3574 }; 3575 static const unsigned int scif4_data_c_pins[] = { 3576 /* RX, TX */ 3577 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), 3578 }; 3579 static const unsigned int scif4_data_c_mux[] = { 3580 RX4_C_MARK, TX4_C_MARK, 3581 }; 3582 static const unsigned int scif4_clk_c_pins[] = { 3583 /* SCK */ 3584 RCAR_GP_PIN(0, 8), 3585 }; 3586 static const unsigned int scif4_clk_c_mux[] = { 3587 SCK4_C_MARK, 3588 }; 3589 static const unsigned int scif4_ctrl_c_pins[] = { 3590 /* RTS, CTS */ 3591 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), 3592 }; 3593 static const unsigned int scif4_ctrl_c_mux[] = { 3594 RTS4_N_C_MARK, CTS4_N_C_MARK, 3595 }; 3596 /* - SCIF5 ------------------------------------------------------------------ */ 3597 static const unsigned int scif5_data_a_pins[] = { 3598 /* RX, TX */ 3599 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21), 3600 }; 3601 static const unsigned int scif5_data_a_mux[] = { 3602 RX5_A_MARK, TX5_A_MARK, 3603 }; 3604 static const unsigned int scif5_clk_a_pins[] = { 3605 /* SCK */ 3606 RCAR_GP_PIN(6, 21), 3607 }; 3608 static const unsigned int scif5_clk_a_mux[] = { 3609 SCK5_A_MARK, 3610 }; 3611 static const unsigned int scif5_data_b_pins[] = { 3612 /* RX, TX */ 3613 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18), 3614 }; 3615 static const unsigned int scif5_data_b_mux[] = { 3616 RX5_B_MARK, TX5_B_MARK, 3617 }; 3618 static const unsigned int scif5_clk_b_pins[] = { 3619 /* SCK */ 3620 RCAR_GP_PIN(5, 0), 3621 }; 3622 static const unsigned int scif5_clk_b_mux[] = { 3623 SCK5_B_MARK, 3624 }; 3625 /* - SCIF Clock ------------------------------------------------------------- */ 3626 static const unsigned int scif_clk_a_pins[] = { 3627 /* SCIF_CLK */ 3628 RCAR_GP_PIN(6, 23), 3629 }; 3630 static const unsigned int scif_clk_a_mux[] = { 3631 SCIF_CLK_A_MARK, 3632 }; 3633 static const unsigned int scif_clk_b_pins[] = { 3634 /* SCIF_CLK */ 3635 RCAR_GP_PIN(5, 9), 3636 }; 3637 static const unsigned int scif_clk_b_mux[] = { 3638 SCIF_CLK_B_MARK, 3639 }; 3640 3641 /* - SDHI0 ------------------------------------------------------------------ */ 3642 static const unsigned int sdhi0_data1_pins[] = { 3643 /* D0 */ 3644 RCAR_GP_PIN(3, 2), 3645 }; 3646 3647 static const unsigned int sdhi0_data1_mux[] = { 3648 SD0_DAT0_MARK, 3649 }; 3650 3651 static const unsigned int sdhi0_data4_pins[] = { 3652 /* D[0:3] */ 3653 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), 3654 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), 3655 }; 3656 3657 static const unsigned int sdhi0_data4_mux[] = { 3658 SD0_DAT0_MARK, SD0_DAT1_MARK, 3659 SD0_DAT2_MARK, SD0_DAT3_MARK, 3660 }; 3661 3662 static const unsigned int sdhi0_ctrl_pins[] = { 3663 /* CLK, CMD */ 3664 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1), 3665 }; 3666 3667 static const unsigned int sdhi0_ctrl_mux[] = { 3668 SD0_CLK_MARK, SD0_CMD_MARK, 3669 }; 3670 3671 static const unsigned int sdhi0_cd_pins[] = { 3672 /* CD */ 3673 RCAR_GP_PIN(3, 12), 3674 }; 3675 3676 static const unsigned int sdhi0_cd_mux[] = { 3677 SD0_CD_MARK, 3678 }; 3679 3680 static const unsigned int sdhi0_wp_pins[] = { 3681 /* WP */ 3682 RCAR_GP_PIN(3, 13), 3683 }; 3684 3685 static const unsigned int sdhi0_wp_mux[] = { 3686 SD0_WP_MARK, 3687 }; 3688 3689 /* - SDHI1 ------------------------------------------------------------------ */ 3690 static const unsigned int sdhi1_data1_pins[] = { 3691 /* D0 */ 3692 RCAR_GP_PIN(3, 8), 3693 }; 3694 3695 static const unsigned int sdhi1_data1_mux[] = { 3696 SD1_DAT0_MARK, 3697 }; 3698 3699 static const unsigned int sdhi1_data4_pins[] = { 3700 /* D[0:3] */ 3701 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), 3702 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), 3703 }; 3704 3705 static const unsigned int sdhi1_data4_mux[] = { 3706 SD1_DAT0_MARK, SD1_DAT1_MARK, 3707 SD1_DAT2_MARK, SD1_DAT3_MARK, 3708 }; 3709 3710 static const unsigned int sdhi1_ctrl_pins[] = { 3711 /* CLK, CMD */ 3712 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), 3713 }; 3714 3715 static const unsigned int sdhi1_ctrl_mux[] = { 3716 SD1_CLK_MARK, SD1_CMD_MARK, 3717 }; 3718 3719 static const unsigned int sdhi1_cd_pins[] = { 3720 /* CD */ 3721 RCAR_GP_PIN(3, 14), 3722 }; 3723 3724 static const unsigned int sdhi1_cd_mux[] = { 3725 SD1_CD_MARK, 3726 }; 3727 3728 static const unsigned int sdhi1_wp_pins[] = { 3729 /* WP */ 3730 RCAR_GP_PIN(3, 15), 3731 }; 3732 3733 static const unsigned int sdhi1_wp_mux[] = { 3734 SD1_WP_MARK, 3735 }; 3736 3737 /* - SDHI2 ------------------------------------------------------------------ */ 3738 static const unsigned int sdhi2_data1_pins[] = { 3739 /* D0 */ 3740 RCAR_GP_PIN(4, 2), 3741 }; 3742 3743 static const unsigned int sdhi2_data1_mux[] = { 3744 SD2_DAT0_MARK, 3745 }; 3746 3747 static const unsigned int sdhi2_data4_pins[] = { 3748 /* D[0:3] */ 3749 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), 3750 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), 3751 }; 3752 3753 static const unsigned int sdhi2_data4_mux[] = { 3754 SD2_DAT0_MARK, SD2_DAT1_MARK, 3755 SD2_DAT2_MARK, SD2_DAT3_MARK, 3756 }; 3757 3758 static const unsigned int sdhi2_data8_pins[] = { 3759 /* D[0:7] */ 3760 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), 3761 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), 3762 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), 3763 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), 3764 }; 3765 3766 static const unsigned int sdhi2_data8_mux[] = { 3767 SD2_DAT0_MARK, SD2_DAT1_MARK, 3768 SD2_DAT2_MARK, SD2_DAT3_MARK, 3769 SD2_DAT4_MARK, SD2_DAT5_MARK, 3770 SD2_DAT6_MARK, SD2_DAT7_MARK, 3771 }; 3772 3773 static const unsigned int sdhi2_ctrl_pins[] = { 3774 /* CLK, CMD */ 3775 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1), 3776 }; 3777 3778 static const unsigned int sdhi2_ctrl_mux[] = { 3779 SD2_CLK_MARK, SD2_CMD_MARK, 3780 }; 3781 3782 static const unsigned int sdhi2_cd_a_pins[] = { 3783 /* CD */ 3784 RCAR_GP_PIN(4, 13), 3785 }; 3786 3787 static const unsigned int sdhi2_cd_a_mux[] = { 3788 SD2_CD_A_MARK, 3789 }; 3790 3791 static const unsigned int sdhi2_cd_b_pins[] = { 3792 /* CD */ 3793 RCAR_GP_PIN(5, 10), 3794 }; 3795 3796 static const unsigned int sdhi2_cd_b_mux[] = { 3797 SD2_CD_B_MARK, 3798 }; 3799 3800 static const unsigned int sdhi2_wp_a_pins[] = { 3801 /* WP */ 3802 RCAR_GP_PIN(4, 14), 3803 }; 3804 3805 static const unsigned int sdhi2_wp_a_mux[] = { 3806 SD2_WP_A_MARK, 3807 }; 3808 3809 static const unsigned int sdhi2_wp_b_pins[] = { 3810 /* WP */ 3811 RCAR_GP_PIN(5, 11), 3812 }; 3813 3814 static const unsigned int sdhi2_wp_b_mux[] = { 3815 SD2_WP_B_MARK, 3816 }; 3817 3818 static const unsigned int sdhi2_ds_pins[] = { 3819 /* DS */ 3820 RCAR_GP_PIN(4, 6), 3821 }; 3822 3823 static const unsigned int sdhi2_ds_mux[] = { 3824 SD2_DS_MARK, 3825 }; 3826 3827 /* - SDHI3 ------------------------------------------------------------------ */ 3828 static const unsigned int sdhi3_data1_pins[] = { 3829 /* D0 */ 3830 RCAR_GP_PIN(4, 9), 3831 }; 3832 3833 static const unsigned int sdhi3_data1_mux[] = { 3834 SD3_DAT0_MARK, 3835 }; 3836 3837 static const unsigned int sdhi3_data4_pins[] = { 3838 /* D[0:3] */ 3839 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10), 3840 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12), 3841 }; 3842 3843 static const unsigned int sdhi3_data4_mux[] = { 3844 SD3_DAT0_MARK, SD3_DAT1_MARK, 3845 SD3_DAT2_MARK, SD3_DAT3_MARK, 3846 }; 3847 3848 static const unsigned int sdhi3_data8_pins[] = { 3849 /* D[0:7] */ 3850 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10), 3851 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12), 3852 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14), 3853 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16), 3854 }; 3855 3856 static const unsigned int sdhi3_data8_mux[] = { 3857 SD3_DAT0_MARK, SD3_DAT1_MARK, 3858 SD3_DAT2_MARK, SD3_DAT3_MARK, 3859 SD3_DAT4_MARK, SD3_DAT5_MARK, 3860 SD3_DAT6_MARK, SD3_DAT7_MARK, 3861 }; 3862 3863 static const unsigned int sdhi3_ctrl_pins[] = { 3864 /* CLK, CMD */ 3865 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8), 3866 }; 3867 3868 static const unsigned int sdhi3_ctrl_mux[] = { 3869 SD3_CLK_MARK, SD3_CMD_MARK, 3870 }; 3871 3872 static const unsigned int sdhi3_cd_pins[] = { 3873 /* CD */ 3874 RCAR_GP_PIN(4, 15), 3875 }; 3876 3877 static const unsigned int sdhi3_cd_mux[] = { 3878 SD3_CD_MARK, 3879 }; 3880 3881 static const unsigned int sdhi3_wp_pins[] = { 3882 /* WP */ 3883 RCAR_GP_PIN(4, 16), 3884 }; 3885 3886 static const unsigned int sdhi3_wp_mux[] = { 3887 SD3_WP_MARK, 3888 }; 3889 3890 static const unsigned int sdhi3_ds_pins[] = { 3891 /* DS */ 3892 RCAR_GP_PIN(4, 17), 3893 }; 3894 3895 static const unsigned int sdhi3_ds_mux[] = { 3896 SD3_DS_MARK, 3897 }; 3898 3899 /* - SSI -------------------------------------------------------------------- */ 3900 static const unsigned int ssi0_data_pins[] = { 3901 /* SDATA */ 3902 RCAR_GP_PIN(6, 2), 3903 }; 3904 static const unsigned int ssi0_data_mux[] = { 3905 SSI_SDATA0_MARK, 3906 }; 3907 static const unsigned int ssi01239_ctrl_pins[] = { 3908 /* SCK, WS */ 3909 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1), 3910 }; 3911 static const unsigned int ssi01239_ctrl_mux[] = { 3912 SSI_SCK01239_MARK, SSI_WS01239_MARK, 3913 }; 3914 static const unsigned int ssi1_data_a_pins[] = { 3915 /* SDATA */ 3916 RCAR_GP_PIN(6, 3), 3917 }; 3918 static const unsigned int ssi1_data_a_mux[] = { 3919 SSI_SDATA1_A_MARK, 3920 }; 3921 static const unsigned int ssi1_data_b_pins[] = { 3922 /* SDATA */ 3923 RCAR_GP_PIN(5, 12), 3924 }; 3925 static const unsigned int ssi1_data_b_mux[] = { 3926 SSI_SDATA1_B_MARK, 3927 }; 3928 static const unsigned int ssi1_ctrl_a_pins[] = { 3929 /* SCK, WS */ 3930 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27), 3931 }; 3932 static const unsigned int ssi1_ctrl_a_mux[] = { 3933 SSI_SCK1_A_MARK, SSI_WS1_A_MARK, 3934 }; 3935 static const unsigned int ssi1_ctrl_b_pins[] = { 3936 /* SCK, WS */ 3937 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21), 3938 }; 3939 static const unsigned int ssi1_ctrl_b_mux[] = { 3940 SSI_SCK1_B_MARK, SSI_WS1_B_MARK, 3941 }; 3942 static const unsigned int ssi2_data_a_pins[] = { 3943 /* SDATA */ 3944 RCAR_GP_PIN(6, 4), 3945 }; 3946 static const unsigned int ssi2_data_a_mux[] = { 3947 SSI_SDATA2_A_MARK, 3948 }; 3949 static const unsigned int ssi2_data_b_pins[] = { 3950 /* SDATA */ 3951 RCAR_GP_PIN(5, 13), 3952 }; 3953 static const unsigned int ssi2_data_b_mux[] = { 3954 SSI_SDATA2_B_MARK, 3955 }; 3956 static const unsigned int ssi2_ctrl_a_pins[] = { 3957 /* SCK, WS */ 3958 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21), 3959 }; 3960 static const unsigned int ssi2_ctrl_a_mux[] = { 3961 SSI_SCK2_A_MARK, SSI_WS2_A_MARK, 3962 }; 3963 static const unsigned int ssi2_ctrl_b_pins[] = { 3964 /* SCK, WS */ 3965 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29), 3966 }; 3967 static const unsigned int ssi2_ctrl_b_mux[] = { 3968 SSI_SCK2_B_MARK, SSI_WS2_B_MARK, 3969 }; 3970 static const unsigned int ssi3_data_pins[] = { 3971 /* SDATA */ 3972 RCAR_GP_PIN(6, 7), 3973 }; 3974 static const unsigned int ssi3_data_mux[] = { 3975 SSI_SDATA3_MARK, 3976 }; 3977 static const unsigned int ssi349_ctrl_pins[] = { 3978 /* SCK, WS */ 3979 RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6), 3980 }; 3981 static const unsigned int ssi349_ctrl_mux[] = { 3982 SSI_SCK349_MARK, SSI_WS349_MARK, 3983 }; 3984 static const unsigned int ssi4_data_pins[] = { 3985 /* SDATA */ 3986 RCAR_GP_PIN(6, 10), 3987 }; 3988 static const unsigned int ssi4_data_mux[] = { 3989 SSI_SDATA4_MARK, 3990 }; 3991 static const unsigned int ssi4_ctrl_pins[] = { 3992 /* SCK, WS */ 3993 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), 3994 }; 3995 static const unsigned int ssi4_ctrl_mux[] = { 3996 SSI_SCK4_MARK, SSI_WS4_MARK, 3997 }; 3998 static const unsigned int ssi5_data_pins[] = { 3999 /* SDATA */ 4000 RCAR_GP_PIN(6, 13), 4001 }; 4002 static const unsigned int ssi5_data_mux[] = { 4003 SSI_SDATA5_MARK, 4004 }; 4005 static const unsigned int ssi5_ctrl_pins[] = { 4006 /* SCK, WS */ 4007 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12), 4008 }; 4009 static const unsigned int ssi5_ctrl_mux[] = { 4010 SSI_SCK5_MARK, SSI_WS5_MARK, 4011 }; 4012 static const unsigned int ssi6_data_pins[] = { 4013 /* SDATA */ 4014 RCAR_GP_PIN(6, 16), 4015 }; 4016 static const unsigned int ssi6_data_mux[] = { 4017 SSI_SDATA6_MARK, 4018 }; 4019 static const unsigned int ssi6_ctrl_pins[] = { 4020 /* SCK, WS */ 4021 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15), 4022 }; 4023 static const unsigned int ssi6_ctrl_mux[] = { 4024 SSI_SCK6_MARK, SSI_WS6_MARK, 4025 }; 4026 static const unsigned int ssi7_data_pins[] = { 4027 /* SDATA */ 4028 RCAR_GP_PIN(6, 19), 4029 }; 4030 static const unsigned int ssi7_data_mux[] = { 4031 SSI_SDATA7_MARK, 4032 }; 4033 static const unsigned int ssi78_ctrl_pins[] = { 4034 /* SCK, WS */ 4035 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18), 4036 }; 4037 static const unsigned int ssi78_ctrl_mux[] = { 4038 SSI_SCK78_MARK, SSI_WS78_MARK, 4039 }; 4040 static const unsigned int ssi8_data_pins[] = { 4041 /* SDATA */ 4042 RCAR_GP_PIN(6, 20), 4043 }; 4044 static const unsigned int ssi8_data_mux[] = { 4045 SSI_SDATA8_MARK, 4046 }; 4047 static const unsigned int ssi9_data_a_pins[] = { 4048 /* SDATA */ 4049 RCAR_GP_PIN(6, 21), 4050 }; 4051 static const unsigned int ssi9_data_a_mux[] = { 4052 SSI_SDATA9_A_MARK, 4053 }; 4054 static const unsigned int ssi9_data_b_pins[] = { 4055 /* SDATA */ 4056 RCAR_GP_PIN(5, 14), 4057 }; 4058 static const unsigned int ssi9_data_b_mux[] = { 4059 SSI_SDATA9_B_MARK, 4060 }; 4061 static const unsigned int ssi9_ctrl_a_pins[] = { 4062 /* SCK, WS */ 4063 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16), 4064 }; 4065 static const unsigned int ssi9_ctrl_a_mux[] = { 4066 SSI_SCK9_A_MARK, SSI_WS9_A_MARK, 4067 }; 4068 static const unsigned int ssi9_ctrl_b_pins[] = { 4069 /* SCK, WS */ 4070 RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31), 4071 }; 4072 static const unsigned int ssi9_ctrl_b_mux[] = { 4073 SSI_SCK9_B_MARK, SSI_WS9_B_MARK, 4074 }; 4075 4076 /* - TMU -------------------------------------------------------------------- */ 4077 static const unsigned int tmu_tclk1_a_pins[] = { 4078 /* TCLK */ 4079 RCAR_GP_PIN(6, 23), 4080 }; 4081 4082 static const unsigned int tmu_tclk1_a_mux[] = { 4083 TCLK1_A_MARK, 4084 }; 4085 4086 static const unsigned int tmu_tclk1_b_pins[] = { 4087 /* TCLK */ 4088 RCAR_GP_PIN(5, 19), 4089 }; 4090 4091 static const unsigned int tmu_tclk1_b_mux[] = { 4092 TCLK1_B_MARK, 4093 }; 4094 4095 static const unsigned int tmu_tclk2_a_pins[] = { 4096 /* TCLK */ 4097 RCAR_GP_PIN(6, 19), 4098 }; 4099 4100 static const unsigned int tmu_tclk2_a_mux[] = { 4101 TCLK2_A_MARK, 4102 }; 4103 4104 static const unsigned int tmu_tclk2_b_pins[] = { 4105 /* TCLK */ 4106 RCAR_GP_PIN(6, 28), 4107 }; 4108 4109 static const unsigned int tmu_tclk2_b_mux[] = { 4110 TCLK2_B_MARK, 4111 }; 4112 4113 /* - TPU ------------------------------------------------------------------- */ 4114 static const unsigned int tpu_to0_pins[] = { 4115 /* TPU0TO0 */ 4116 RCAR_GP_PIN(6, 28), 4117 }; 4118 static const unsigned int tpu_to0_mux[] = { 4119 TPU0TO0_MARK, 4120 }; 4121 static const unsigned int tpu_to1_pins[] = { 4122 /* TPU0TO1 */ 4123 RCAR_GP_PIN(6, 29), 4124 }; 4125 static const unsigned int tpu_to1_mux[] = { 4126 TPU0TO1_MARK, 4127 }; 4128 static const unsigned int tpu_to2_pins[] = { 4129 /* TPU0TO2 */ 4130 RCAR_GP_PIN(6, 30), 4131 }; 4132 static const unsigned int tpu_to2_mux[] = { 4133 TPU0TO2_MARK, 4134 }; 4135 static const unsigned int tpu_to3_pins[] = { 4136 /* TPU0TO3 */ 4137 RCAR_GP_PIN(6, 31), 4138 }; 4139 static const unsigned int tpu_to3_mux[] = { 4140 TPU0TO3_MARK, 4141 }; 4142 4143 /* - USB0 ------------------------------------------------------------------- */ 4144 static const unsigned int usb0_pins[] = { 4145 /* PWEN, OVC */ 4146 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25), 4147 }; 4148 4149 static const unsigned int usb0_mux[] = { 4150 USB0_PWEN_MARK, USB0_OVC_MARK, 4151 }; 4152 4153 /* - USB1 ------------------------------------------------------------------- */ 4154 static const unsigned int usb1_pins[] = { 4155 /* PWEN, OVC */ 4156 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27), 4157 }; 4158 4159 static const unsigned int usb1_mux[] = { 4160 USB1_PWEN_MARK, USB1_OVC_MARK, 4161 }; 4162 4163 /* - USB30 ------------------------------------------------------------------ */ 4164 static const unsigned int usb30_pins[] = { 4165 /* PWEN, OVC */ 4166 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29), 4167 }; 4168 4169 static const unsigned int usb30_mux[] = { 4170 USB30_PWEN_MARK, USB30_OVC_MARK, 4171 }; 4172 4173 /* - VIN4 ------------------------------------------------------------------- */ 4174 static const unsigned int vin4_data18_a_pins[] = { 4175 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), 4176 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), 4177 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), 4178 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), 4179 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), 4180 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 4181 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), 4182 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), 4183 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), 4184 }; 4185 4186 static const unsigned int vin4_data18_a_mux[] = { 4187 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK, 4188 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK, 4189 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK, 4190 VI4_DATA10_MARK, VI4_DATA11_MARK, 4191 VI4_DATA12_MARK, VI4_DATA13_MARK, 4192 VI4_DATA14_MARK, VI4_DATA15_MARK, 4193 VI4_DATA18_MARK, VI4_DATA19_MARK, 4194 VI4_DATA20_MARK, VI4_DATA21_MARK, 4195 VI4_DATA22_MARK, VI4_DATA23_MARK, 4196 }; 4197 4198 static const union vin_data vin4_data_a_pins = { 4199 .data24 = { 4200 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), 4201 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), 4202 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), 4203 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), 4204 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), 4205 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), 4206 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), 4207 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 4208 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), 4209 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), 4210 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), 4211 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), 4212 }, 4213 }; 4214 4215 static const union vin_data vin4_data_a_mux = { 4216 .data24 = { 4217 VI4_DATA0_A_MARK, VI4_DATA1_A_MARK, 4218 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK, 4219 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK, 4220 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK, 4221 VI4_DATA8_MARK, VI4_DATA9_MARK, 4222 VI4_DATA10_MARK, VI4_DATA11_MARK, 4223 VI4_DATA12_MARK, VI4_DATA13_MARK, 4224 VI4_DATA14_MARK, VI4_DATA15_MARK, 4225 VI4_DATA16_MARK, VI4_DATA17_MARK, 4226 VI4_DATA18_MARK, VI4_DATA19_MARK, 4227 VI4_DATA20_MARK, VI4_DATA21_MARK, 4228 VI4_DATA22_MARK, VI4_DATA23_MARK, 4229 }, 4230 }; 4231 4232 static const unsigned int vin4_data18_b_pins[] = { 4233 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), 4234 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), 4235 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), 4236 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), 4237 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), 4238 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 4239 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), 4240 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), 4241 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), 4242 }; 4243 4244 static const unsigned int vin4_data18_b_mux[] = { 4245 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK, 4246 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK, 4247 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK, 4248 VI4_DATA10_MARK, VI4_DATA11_MARK, 4249 VI4_DATA12_MARK, VI4_DATA13_MARK, 4250 VI4_DATA14_MARK, VI4_DATA15_MARK, 4251 VI4_DATA18_MARK, VI4_DATA19_MARK, 4252 VI4_DATA20_MARK, VI4_DATA21_MARK, 4253 VI4_DATA22_MARK, VI4_DATA23_MARK, 4254 }; 4255 4256 static const union vin_data vin4_data_b_pins = { 4257 .data24 = { 4258 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), 4259 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), 4260 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), 4261 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), 4262 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), 4263 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), 4264 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), 4265 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 4266 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), 4267 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), 4268 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), 4269 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), 4270 }, 4271 }; 4272 4273 static const union vin_data vin4_data_b_mux = { 4274 .data24 = { 4275 VI4_DATA0_B_MARK, VI4_DATA1_B_MARK, 4276 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK, 4277 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK, 4278 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK, 4279 VI4_DATA8_MARK, VI4_DATA9_MARK, 4280 VI4_DATA10_MARK, VI4_DATA11_MARK, 4281 VI4_DATA12_MARK, VI4_DATA13_MARK, 4282 VI4_DATA14_MARK, VI4_DATA15_MARK, 4283 VI4_DATA16_MARK, VI4_DATA17_MARK, 4284 VI4_DATA18_MARK, VI4_DATA19_MARK, 4285 VI4_DATA20_MARK, VI4_DATA21_MARK, 4286 VI4_DATA22_MARK, VI4_DATA23_MARK, 4287 }, 4288 }; 4289 4290 static const unsigned int vin4_sync_pins[] = { 4291 /* VSYNC_N, HSYNC_N */ 4292 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18), 4293 }; 4294 4295 static const unsigned int vin4_sync_mux[] = { 4296 VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK, 4297 }; 4298 4299 static const unsigned int vin4_field_pins[] = { 4300 RCAR_GP_PIN(1, 16), 4301 }; 4302 4303 static const unsigned int vin4_field_mux[] = { 4304 VI4_FIELD_MARK, 4305 }; 4306 4307 static const unsigned int vin4_clkenb_pins[] = { 4308 RCAR_GP_PIN(1, 19), 4309 }; 4310 4311 static const unsigned int vin4_clkenb_mux[] = { 4312 VI4_CLKENB_MARK, 4313 }; 4314 4315 static const unsigned int vin4_clk_pins[] = { 4316 RCAR_GP_PIN(1, 27), 4317 }; 4318 4319 static const unsigned int vin4_clk_mux[] = { 4320 VI4_CLK_MARK, 4321 }; 4322 4323 /* - VIN5 ------------------------------------------------------------------- */ 4324 static const union vin_data16 vin5_data_pins = { 4325 .data16 = { 4326 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), 4327 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), 4328 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), 4329 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), 4330 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), 4331 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), 4332 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), 4333 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 4334 }, 4335 }; 4336 4337 static const union vin_data16 vin5_data_mux = { 4338 .data16 = { 4339 VI5_DATA0_MARK, VI5_DATA1_MARK, 4340 VI5_DATA2_MARK, VI5_DATA3_MARK, 4341 VI5_DATA4_MARK, VI5_DATA5_MARK, 4342 VI5_DATA6_MARK, VI5_DATA7_MARK, 4343 VI5_DATA8_MARK, VI5_DATA9_MARK, 4344 VI5_DATA10_MARK, VI5_DATA11_MARK, 4345 VI5_DATA12_MARK, VI5_DATA13_MARK, 4346 VI5_DATA14_MARK, VI5_DATA15_MARK, 4347 }, 4348 }; 4349 4350 static const unsigned int vin5_sync_pins[] = { 4351 /* VSYNC_N, HSYNC_N */ 4352 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 10), 4353 }; 4354 4355 static const unsigned int vin5_sync_mux[] = { 4356 VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK, 4357 }; 4358 4359 static const unsigned int vin5_field_pins[] = { 4360 RCAR_GP_PIN(1, 11), 4361 }; 4362 4363 static const unsigned int vin5_field_mux[] = { 4364 VI5_FIELD_MARK, 4365 }; 4366 4367 static const unsigned int vin5_clkenb_pins[] = { 4368 RCAR_GP_PIN(1, 20), 4369 }; 4370 4371 static const unsigned int vin5_clkenb_mux[] = { 4372 VI5_CLKENB_MARK, 4373 }; 4374 4375 static const unsigned int vin5_clk_pins[] = { 4376 RCAR_GP_PIN(1, 21), 4377 }; 4378 4379 static const unsigned int vin5_clk_mux[] = { 4380 VI5_CLK_MARK, 4381 }; 4382 4383 static const struct { 4384 struct sh_pfc_pin_group common[318]; 4385 #ifdef CONFIG_PINCTRL_PFC_R8A77965 4386 struct sh_pfc_pin_group automotive[30]; 4387 #endif 4388 } pinmux_groups = { 4389 .common = { 4390 SH_PFC_PIN_GROUP(audio_clk_a_a), 4391 SH_PFC_PIN_GROUP(audio_clk_a_b), 4392 SH_PFC_PIN_GROUP(audio_clk_a_c), 4393 SH_PFC_PIN_GROUP(audio_clk_b_a), 4394 SH_PFC_PIN_GROUP(audio_clk_b_b), 4395 SH_PFC_PIN_GROUP(audio_clk_c_a), 4396 SH_PFC_PIN_GROUP(audio_clk_c_b), 4397 SH_PFC_PIN_GROUP(audio_clkout_a), 4398 SH_PFC_PIN_GROUP(audio_clkout_b), 4399 SH_PFC_PIN_GROUP(audio_clkout_c), 4400 SH_PFC_PIN_GROUP(audio_clkout_d), 4401 SH_PFC_PIN_GROUP(audio_clkout1_a), 4402 SH_PFC_PIN_GROUP(audio_clkout1_b), 4403 SH_PFC_PIN_GROUP(audio_clkout2_a), 4404 SH_PFC_PIN_GROUP(audio_clkout2_b), 4405 SH_PFC_PIN_GROUP(audio_clkout3_a), 4406 SH_PFC_PIN_GROUP(audio_clkout3_b), 4407 SH_PFC_PIN_GROUP(avb_link), 4408 SH_PFC_PIN_GROUP(avb_magic), 4409 SH_PFC_PIN_GROUP(avb_phy_int), 4410 SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio), /* Deprecated */ 4411 SH_PFC_PIN_GROUP(avb_mdio), 4412 SH_PFC_PIN_GROUP(avb_mii), 4413 SH_PFC_PIN_GROUP(avb_avtp_pps), 4414 SH_PFC_PIN_GROUP(avb_avtp_match_a), 4415 SH_PFC_PIN_GROUP(avb_avtp_capture_a), 4416 SH_PFC_PIN_GROUP(avb_avtp_match_b), 4417 SH_PFC_PIN_GROUP(avb_avtp_capture_b), 4418 SH_PFC_PIN_GROUP(can0_data_a), 4419 SH_PFC_PIN_GROUP(can0_data_b), 4420 SH_PFC_PIN_GROUP(can1_data), 4421 SH_PFC_PIN_GROUP(can_clk), 4422 SH_PFC_PIN_GROUP(canfd0_data_a), 4423 SH_PFC_PIN_GROUP(canfd0_data_b), 4424 SH_PFC_PIN_GROUP(canfd1_data), 4425 SH_PFC_PIN_GROUP(du_rgb666), 4426 SH_PFC_PIN_GROUP(du_rgb888), 4427 SH_PFC_PIN_GROUP(du_clk_out_0), 4428 SH_PFC_PIN_GROUP(du_clk_out_1), 4429 SH_PFC_PIN_GROUP(du_sync), 4430 SH_PFC_PIN_GROUP(du_oddf), 4431 SH_PFC_PIN_GROUP(du_cde), 4432 SH_PFC_PIN_GROUP(du_disp), 4433 SH_PFC_PIN_GROUP(hscif0_data), 4434 SH_PFC_PIN_GROUP(hscif0_clk), 4435 SH_PFC_PIN_GROUP(hscif0_ctrl), 4436 SH_PFC_PIN_GROUP(hscif1_data_a), 4437 SH_PFC_PIN_GROUP(hscif1_clk_a), 4438 SH_PFC_PIN_GROUP(hscif1_ctrl_a), 4439 SH_PFC_PIN_GROUP(hscif1_data_b), 4440 SH_PFC_PIN_GROUP(hscif1_clk_b), 4441 SH_PFC_PIN_GROUP(hscif1_ctrl_b), 4442 SH_PFC_PIN_GROUP(hscif2_data_a), 4443 SH_PFC_PIN_GROUP(hscif2_clk_a), 4444 SH_PFC_PIN_GROUP(hscif2_ctrl_a), 4445 SH_PFC_PIN_GROUP(hscif2_data_b), 4446 SH_PFC_PIN_GROUP(hscif2_clk_b), 4447 SH_PFC_PIN_GROUP(hscif2_ctrl_b), 4448 SH_PFC_PIN_GROUP(hscif2_data_c), 4449 SH_PFC_PIN_GROUP(hscif2_clk_c), 4450 SH_PFC_PIN_GROUP(hscif2_ctrl_c), 4451 SH_PFC_PIN_GROUP(hscif3_data_a), 4452 SH_PFC_PIN_GROUP(hscif3_clk), 4453 SH_PFC_PIN_GROUP(hscif3_ctrl), 4454 SH_PFC_PIN_GROUP(hscif3_data_b), 4455 SH_PFC_PIN_GROUP(hscif3_data_c), 4456 SH_PFC_PIN_GROUP(hscif3_data_d), 4457 SH_PFC_PIN_GROUP(hscif4_data_a), 4458 SH_PFC_PIN_GROUP(hscif4_clk), 4459 SH_PFC_PIN_GROUP(hscif4_ctrl), 4460 SH_PFC_PIN_GROUP(hscif4_data_b), 4461 SH_PFC_PIN_GROUP(i2c0), 4462 SH_PFC_PIN_GROUP(i2c1_a), 4463 SH_PFC_PIN_GROUP(i2c1_b), 4464 SH_PFC_PIN_GROUP(i2c2_a), 4465 SH_PFC_PIN_GROUP(i2c2_b), 4466 SH_PFC_PIN_GROUP(i2c3), 4467 SH_PFC_PIN_GROUP(i2c5), 4468 SH_PFC_PIN_GROUP(i2c6_a), 4469 SH_PFC_PIN_GROUP(i2c6_b), 4470 SH_PFC_PIN_GROUP(i2c6_c), 4471 SH_PFC_PIN_GROUP(intc_ex_irq0), 4472 SH_PFC_PIN_GROUP(intc_ex_irq1), 4473 SH_PFC_PIN_GROUP(intc_ex_irq2), 4474 SH_PFC_PIN_GROUP(intc_ex_irq3), 4475 SH_PFC_PIN_GROUP(intc_ex_irq4), 4476 SH_PFC_PIN_GROUP(intc_ex_irq5), 4477 SH_PFC_PIN_GROUP(msiof0_clk), 4478 SH_PFC_PIN_GROUP(msiof0_sync), 4479 SH_PFC_PIN_GROUP(msiof0_ss1), 4480 SH_PFC_PIN_GROUP(msiof0_ss2), 4481 SH_PFC_PIN_GROUP(msiof0_txd), 4482 SH_PFC_PIN_GROUP(msiof0_rxd), 4483 SH_PFC_PIN_GROUP(msiof1_clk_a), 4484 SH_PFC_PIN_GROUP(msiof1_sync_a), 4485 SH_PFC_PIN_GROUP(msiof1_ss1_a), 4486 SH_PFC_PIN_GROUP(msiof1_ss2_a), 4487 SH_PFC_PIN_GROUP(msiof1_txd_a), 4488 SH_PFC_PIN_GROUP(msiof1_rxd_a), 4489 SH_PFC_PIN_GROUP(msiof1_clk_b), 4490 SH_PFC_PIN_GROUP(msiof1_sync_b), 4491 SH_PFC_PIN_GROUP(msiof1_ss1_b), 4492 SH_PFC_PIN_GROUP(msiof1_ss2_b), 4493 SH_PFC_PIN_GROUP(msiof1_txd_b), 4494 SH_PFC_PIN_GROUP(msiof1_rxd_b), 4495 SH_PFC_PIN_GROUP(msiof1_clk_c), 4496 SH_PFC_PIN_GROUP(msiof1_sync_c), 4497 SH_PFC_PIN_GROUP(msiof1_ss1_c), 4498 SH_PFC_PIN_GROUP(msiof1_ss2_c), 4499 SH_PFC_PIN_GROUP(msiof1_txd_c), 4500 SH_PFC_PIN_GROUP(msiof1_rxd_c), 4501 SH_PFC_PIN_GROUP(msiof1_clk_d), 4502 SH_PFC_PIN_GROUP(msiof1_sync_d), 4503 SH_PFC_PIN_GROUP(msiof1_ss1_d), 4504 SH_PFC_PIN_GROUP(msiof1_ss2_d), 4505 SH_PFC_PIN_GROUP(msiof1_txd_d), 4506 SH_PFC_PIN_GROUP(msiof1_rxd_d), 4507 SH_PFC_PIN_GROUP(msiof1_clk_e), 4508 SH_PFC_PIN_GROUP(msiof1_sync_e), 4509 SH_PFC_PIN_GROUP(msiof1_ss1_e), 4510 SH_PFC_PIN_GROUP(msiof1_ss2_e), 4511 SH_PFC_PIN_GROUP(msiof1_txd_e), 4512 SH_PFC_PIN_GROUP(msiof1_rxd_e), 4513 SH_PFC_PIN_GROUP(msiof1_clk_f), 4514 SH_PFC_PIN_GROUP(msiof1_sync_f), 4515 SH_PFC_PIN_GROUP(msiof1_ss1_f), 4516 SH_PFC_PIN_GROUP(msiof1_ss2_f), 4517 SH_PFC_PIN_GROUP(msiof1_txd_f), 4518 SH_PFC_PIN_GROUP(msiof1_rxd_f), 4519 SH_PFC_PIN_GROUP(msiof1_clk_g), 4520 SH_PFC_PIN_GROUP(msiof1_sync_g), 4521 SH_PFC_PIN_GROUP(msiof1_ss1_g), 4522 SH_PFC_PIN_GROUP(msiof1_ss2_g), 4523 SH_PFC_PIN_GROUP(msiof1_txd_g), 4524 SH_PFC_PIN_GROUP(msiof1_rxd_g), 4525 SH_PFC_PIN_GROUP(msiof2_clk_a), 4526 SH_PFC_PIN_GROUP(msiof2_sync_a), 4527 SH_PFC_PIN_GROUP(msiof2_ss1_a), 4528 SH_PFC_PIN_GROUP(msiof2_ss2_a), 4529 SH_PFC_PIN_GROUP(msiof2_txd_a), 4530 SH_PFC_PIN_GROUP(msiof2_rxd_a), 4531 SH_PFC_PIN_GROUP(msiof2_clk_b), 4532 SH_PFC_PIN_GROUP(msiof2_sync_b), 4533 SH_PFC_PIN_GROUP(msiof2_ss1_b), 4534 SH_PFC_PIN_GROUP(msiof2_ss2_b), 4535 SH_PFC_PIN_GROUP(msiof2_txd_b), 4536 SH_PFC_PIN_GROUP(msiof2_rxd_b), 4537 SH_PFC_PIN_GROUP(msiof2_clk_c), 4538 SH_PFC_PIN_GROUP(msiof2_sync_c), 4539 SH_PFC_PIN_GROUP(msiof2_ss1_c), 4540 SH_PFC_PIN_GROUP(msiof2_ss2_c), 4541 SH_PFC_PIN_GROUP(msiof2_txd_c), 4542 SH_PFC_PIN_GROUP(msiof2_rxd_c), 4543 SH_PFC_PIN_GROUP(msiof2_clk_d), 4544 SH_PFC_PIN_GROUP(msiof2_sync_d), 4545 SH_PFC_PIN_GROUP(msiof2_ss1_d), 4546 SH_PFC_PIN_GROUP(msiof2_ss2_d), 4547 SH_PFC_PIN_GROUP(msiof2_txd_d), 4548 SH_PFC_PIN_GROUP(msiof2_rxd_d), 4549 SH_PFC_PIN_GROUP(msiof3_clk_a), 4550 SH_PFC_PIN_GROUP(msiof3_sync_a), 4551 SH_PFC_PIN_GROUP(msiof3_ss1_a), 4552 SH_PFC_PIN_GROUP(msiof3_ss2_a), 4553 SH_PFC_PIN_GROUP(msiof3_txd_a), 4554 SH_PFC_PIN_GROUP(msiof3_rxd_a), 4555 SH_PFC_PIN_GROUP(msiof3_clk_b), 4556 SH_PFC_PIN_GROUP(msiof3_sync_b), 4557 SH_PFC_PIN_GROUP(msiof3_ss1_b), 4558 SH_PFC_PIN_GROUP(msiof3_ss2_b), 4559 SH_PFC_PIN_GROUP(msiof3_txd_b), 4560 SH_PFC_PIN_GROUP(msiof3_rxd_b), 4561 SH_PFC_PIN_GROUP(msiof3_clk_c), 4562 SH_PFC_PIN_GROUP(msiof3_sync_c), 4563 SH_PFC_PIN_GROUP(msiof3_txd_c), 4564 SH_PFC_PIN_GROUP(msiof3_rxd_c), 4565 SH_PFC_PIN_GROUP(msiof3_clk_d), 4566 SH_PFC_PIN_GROUP(msiof3_sync_d), 4567 SH_PFC_PIN_GROUP(msiof3_ss1_d), 4568 SH_PFC_PIN_GROUP(msiof3_txd_d), 4569 SH_PFC_PIN_GROUP(msiof3_rxd_d), 4570 SH_PFC_PIN_GROUP(msiof3_clk_e), 4571 SH_PFC_PIN_GROUP(msiof3_sync_e), 4572 SH_PFC_PIN_GROUP(msiof3_ss1_e), 4573 SH_PFC_PIN_GROUP(msiof3_ss2_e), 4574 SH_PFC_PIN_GROUP(msiof3_txd_e), 4575 SH_PFC_PIN_GROUP(msiof3_rxd_e), 4576 SH_PFC_PIN_GROUP(pwm0), 4577 SH_PFC_PIN_GROUP(pwm1_a), 4578 SH_PFC_PIN_GROUP(pwm1_b), 4579 SH_PFC_PIN_GROUP(pwm2_a), 4580 SH_PFC_PIN_GROUP(pwm2_b), 4581 SH_PFC_PIN_GROUP(pwm3_a), 4582 SH_PFC_PIN_GROUP(pwm3_b), 4583 SH_PFC_PIN_GROUP(pwm4_a), 4584 SH_PFC_PIN_GROUP(pwm4_b), 4585 SH_PFC_PIN_GROUP(pwm5_a), 4586 SH_PFC_PIN_GROUP(pwm5_b), 4587 SH_PFC_PIN_GROUP(pwm6_a), 4588 SH_PFC_PIN_GROUP(pwm6_b), 4589 SH_PFC_PIN_GROUP(sata0_devslp_a), 4590 SH_PFC_PIN_GROUP(sata0_devslp_b), 4591 SH_PFC_PIN_GROUP(scif0_data), 4592 SH_PFC_PIN_GROUP(scif0_clk), 4593 SH_PFC_PIN_GROUP(scif0_ctrl), 4594 SH_PFC_PIN_GROUP(scif1_data_a), 4595 SH_PFC_PIN_GROUP(scif1_clk), 4596 SH_PFC_PIN_GROUP(scif1_ctrl), 4597 SH_PFC_PIN_GROUP(scif1_data_b), 4598 SH_PFC_PIN_GROUP(scif2_data_a), 4599 SH_PFC_PIN_GROUP(scif2_clk), 4600 SH_PFC_PIN_GROUP(scif2_data_b), 4601 SH_PFC_PIN_GROUP(scif3_data_a), 4602 SH_PFC_PIN_GROUP(scif3_clk), 4603 SH_PFC_PIN_GROUP(scif3_ctrl), 4604 SH_PFC_PIN_GROUP(scif3_data_b), 4605 SH_PFC_PIN_GROUP(scif4_data_a), 4606 SH_PFC_PIN_GROUP(scif4_clk_a), 4607 SH_PFC_PIN_GROUP(scif4_ctrl_a), 4608 SH_PFC_PIN_GROUP(scif4_data_b), 4609 SH_PFC_PIN_GROUP(scif4_clk_b), 4610 SH_PFC_PIN_GROUP(scif4_ctrl_b), 4611 SH_PFC_PIN_GROUP(scif4_data_c), 4612 SH_PFC_PIN_GROUP(scif4_clk_c), 4613 SH_PFC_PIN_GROUP(scif4_ctrl_c), 4614 SH_PFC_PIN_GROUP(scif5_data_a), 4615 SH_PFC_PIN_GROUP(scif5_clk_a), 4616 SH_PFC_PIN_GROUP(scif5_data_b), 4617 SH_PFC_PIN_GROUP(scif5_clk_b), 4618 SH_PFC_PIN_GROUP(scif_clk_a), 4619 SH_PFC_PIN_GROUP(scif_clk_b), 4620 SH_PFC_PIN_GROUP(sdhi0_data1), 4621 SH_PFC_PIN_GROUP(sdhi0_data4), 4622 SH_PFC_PIN_GROUP(sdhi0_ctrl), 4623 SH_PFC_PIN_GROUP(sdhi0_cd), 4624 SH_PFC_PIN_GROUP(sdhi0_wp), 4625 SH_PFC_PIN_GROUP(sdhi1_data1), 4626 SH_PFC_PIN_GROUP(sdhi1_data4), 4627 SH_PFC_PIN_GROUP(sdhi1_ctrl), 4628 SH_PFC_PIN_GROUP(sdhi1_cd), 4629 SH_PFC_PIN_GROUP(sdhi1_wp), 4630 SH_PFC_PIN_GROUP(sdhi2_data1), 4631 SH_PFC_PIN_GROUP(sdhi2_data4), 4632 SH_PFC_PIN_GROUP(sdhi2_data8), 4633 SH_PFC_PIN_GROUP(sdhi2_ctrl), 4634 SH_PFC_PIN_GROUP(sdhi2_cd_a), 4635 SH_PFC_PIN_GROUP(sdhi2_wp_a), 4636 SH_PFC_PIN_GROUP(sdhi2_cd_b), 4637 SH_PFC_PIN_GROUP(sdhi2_wp_b), 4638 SH_PFC_PIN_GROUP(sdhi2_ds), 4639 SH_PFC_PIN_GROUP(sdhi3_data1), 4640 SH_PFC_PIN_GROUP(sdhi3_data4), 4641 SH_PFC_PIN_GROUP(sdhi3_data8), 4642 SH_PFC_PIN_GROUP(sdhi3_ctrl), 4643 SH_PFC_PIN_GROUP(sdhi3_cd), 4644 SH_PFC_PIN_GROUP(sdhi3_wp), 4645 SH_PFC_PIN_GROUP(sdhi3_ds), 4646 SH_PFC_PIN_GROUP(ssi0_data), 4647 SH_PFC_PIN_GROUP(ssi01239_ctrl), 4648 SH_PFC_PIN_GROUP(ssi1_data_a), 4649 SH_PFC_PIN_GROUP(ssi1_data_b), 4650 SH_PFC_PIN_GROUP(ssi1_ctrl_a), 4651 SH_PFC_PIN_GROUP(ssi1_ctrl_b), 4652 SH_PFC_PIN_GROUP(ssi2_data_a), 4653 SH_PFC_PIN_GROUP(ssi2_data_b), 4654 SH_PFC_PIN_GROUP(ssi2_ctrl_a), 4655 SH_PFC_PIN_GROUP(ssi2_ctrl_b), 4656 SH_PFC_PIN_GROUP(ssi3_data), 4657 SH_PFC_PIN_GROUP(ssi349_ctrl), 4658 SH_PFC_PIN_GROUP(ssi4_data), 4659 SH_PFC_PIN_GROUP(ssi4_ctrl), 4660 SH_PFC_PIN_GROUP(ssi5_data), 4661 SH_PFC_PIN_GROUP(ssi5_ctrl), 4662 SH_PFC_PIN_GROUP(ssi6_data), 4663 SH_PFC_PIN_GROUP(ssi6_ctrl), 4664 SH_PFC_PIN_GROUP(ssi7_data), 4665 SH_PFC_PIN_GROUP(ssi78_ctrl), 4666 SH_PFC_PIN_GROUP(ssi8_data), 4667 SH_PFC_PIN_GROUP(ssi9_data_a), 4668 SH_PFC_PIN_GROUP(ssi9_data_b), 4669 SH_PFC_PIN_GROUP(ssi9_ctrl_a), 4670 SH_PFC_PIN_GROUP(ssi9_ctrl_b), 4671 SH_PFC_PIN_GROUP(tmu_tclk1_a), 4672 SH_PFC_PIN_GROUP(tmu_tclk1_b), 4673 SH_PFC_PIN_GROUP(tmu_tclk2_a), 4674 SH_PFC_PIN_GROUP(tmu_tclk2_b), 4675 SH_PFC_PIN_GROUP(tpu_to0), 4676 SH_PFC_PIN_GROUP(tpu_to1), 4677 SH_PFC_PIN_GROUP(tpu_to2), 4678 SH_PFC_PIN_GROUP(tpu_to3), 4679 SH_PFC_PIN_GROUP(usb0), 4680 SH_PFC_PIN_GROUP(usb1), 4681 SH_PFC_PIN_GROUP(usb30), 4682 VIN_DATA_PIN_GROUP(vin4_data, 8, _a), 4683 VIN_DATA_PIN_GROUP(vin4_data, 10, _a), 4684 VIN_DATA_PIN_GROUP(vin4_data, 12, _a), 4685 VIN_DATA_PIN_GROUP(vin4_data, 16, _a), 4686 SH_PFC_PIN_GROUP(vin4_data18_a), 4687 VIN_DATA_PIN_GROUP(vin4_data, 20, _a), 4688 VIN_DATA_PIN_GROUP(vin4_data, 24, _a), 4689 VIN_DATA_PIN_GROUP(vin4_data, 8, _b), 4690 VIN_DATA_PIN_GROUP(vin4_data, 10, _b), 4691 VIN_DATA_PIN_GROUP(vin4_data, 12, _b), 4692 VIN_DATA_PIN_GROUP(vin4_data, 16, _b), 4693 SH_PFC_PIN_GROUP(vin4_data18_b), 4694 VIN_DATA_PIN_GROUP(vin4_data, 20, _b), 4695 VIN_DATA_PIN_GROUP(vin4_data, 24, _b), 4696 SH_PFC_PIN_GROUP(vin4_sync), 4697 SH_PFC_PIN_GROUP(vin4_field), 4698 SH_PFC_PIN_GROUP(vin4_clkenb), 4699 SH_PFC_PIN_GROUP(vin4_clk), 4700 VIN_DATA_PIN_GROUP(vin5_data, 8), 4701 VIN_DATA_PIN_GROUP(vin5_data, 10), 4702 VIN_DATA_PIN_GROUP(vin5_data, 12), 4703 VIN_DATA_PIN_GROUP(vin5_data, 16), 4704 SH_PFC_PIN_GROUP(vin5_sync), 4705 SH_PFC_PIN_GROUP(vin5_field), 4706 SH_PFC_PIN_GROUP(vin5_clkenb), 4707 SH_PFC_PIN_GROUP(vin5_clk), 4708 }, 4709 #ifdef CONFIG_PINCTRL_PFC_R8A77965 4710 .automotive = { 4711 SH_PFC_PIN_GROUP(drif0_ctrl_a), 4712 SH_PFC_PIN_GROUP(drif0_data0_a), 4713 SH_PFC_PIN_GROUP(drif0_data1_a), 4714 SH_PFC_PIN_GROUP(drif0_ctrl_b), 4715 SH_PFC_PIN_GROUP(drif0_data0_b), 4716 SH_PFC_PIN_GROUP(drif0_data1_b), 4717 SH_PFC_PIN_GROUP(drif0_ctrl_c), 4718 SH_PFC_PIN_GROUP(drif0_data0_c), 4719 SH_PFC_PIN_GROUP(drif0_data1_c), 4720 SH_PFC_PIN_GROUP(drif1_ctrl_a), 4721 SH_PFC_PIN_GROUP(drif1_data0_a), 4722 SH_PFC_PIN_GROUP(drif1_data1_a), 4723 SH_PFC_PIN_GROUP(drif1_ctrl_b), 4724 SH_PFC_PIN_GROUP(drif1_data0_b), 4725 SH_PFC_PIN_GROUP(drif1_data1_b), 4726 SH_PFC_PIN_GROUP(drif1_ctrl_c), 4727 SH_PFC_PIN_GROUP(drif1_data0_c), 4728 SH_PFC_PIN_GROUP(drif1_data1_c), 4729 SH_PFC_PIN_GROUP(drif2_ctrl_a), 4730 SH_PFC_PIN_GROUP(drif2_data0_a), 4731 SH_PFC_PIN_GROUP(drif2_data1_a), 4732 SH_PFC_PIN_GROUP(drif2_ctrl_b), 4733 SH_PFC_PIN_GROUP(drif2_data0_b), 4734 SH_PFC_PIN_GROUP(drif2_data1_b), 4735 SH_PFC_PIN_GROUP(drif3_ctrl_a), 4736 SH_PFC_PIN_GROUP(drif3_data0_a), 4737 SH_PFC_PIN_GROUP(drif3_data1_a), 4738 SH_PFC_PIN_GROUP(drif3_ctrl_b), 4739 SH_PFC_PIN_GROUP(drif3_data0_b), 4740 SH_PFC_PIN_GROUP(drif3_data1_b), 4741 } 4742 #endif /* CONFIG_PINCTRL_PFC_R8A77965 */ 4743 }; 4744 4745 static const char * const audio_clk_groups[] = { 4746 "audio_clk_a_a", 4747 "audio_clk_a_b", 4748 "audio_clk_a_c", 4749 "audio_clk_b_a", 4750 "audio_clk_b_b", 4751 "audio_clk_c_a", 4752 "audio_clk_c_b", 4753 "audio_clkout_a", 4754 "audio_clkout_b", 4755 "audio_clkout_c", 4756 "audio_clkout_d", 4757 "audio_clkout1_a", 4758 "audio_clkout1_b", 4759 "audio_clkout2_a", 4760 "audio_clkout2_b", 4761 "audio_clkout3_a", 4762 "audio_clkout3_b", 4763 }; 4764 4765 static const char * const avb_groups[] = { 4766 "avb_link", 4767 "avb_magic", 4768 "avb_phy_int", 4769 "avb_mdc", /* Deprecated, please use "avb_mdio" instead */ 4770 "avb_mdio", 4771 "avb_mii", 4772 "avb_avtp_pps", 4773 "avb_avtp_match_a", 4774 "avb_avtp_capture_a", 4775 "avb_avtp_match_b", 4776 "avb_avtp_capture_b", 4777 }; 4778 4779 static const char * const can0_groups[] = { 4780 "can0_data_a", 4781 "can0_data_b", 4782 }; 4783 4784 static const char * const can1_groups[] = { 4785 "can1_data", 4786 }; 4787 4788 static const char * const can_clk_groups[] = { 4789 "can_clk", 4790 }; 4791 4792 static const char * const canfd0_groups[] = { 4793 "canfd0_data_a", 4794 "canfd0_data_b", 4795 }; 4796 4797 static const char * const canfd1_groups[] = { 4798 "canfd1_data", 4799 }; 4800 4801 #ifdef CONFIG_PINCTRL_PFC_R8A77965 4802 static const char * const drif0_groups[] = { 4803 "drif0_ctrl_a", 4804 "drif0_data0_a", 4805 "drif0_data1_a", 4806 "drif0_ctrl_b", 4807 "drif0_data0_b", 4808 "drif0_data1_b", 4809 "drif0_ctrl_c", 4810 "drif0_data0_c", 4811 "drif0_data1_c", 4812 }; 4813 4814 static const char * const drif1_groups[] = { 4815 "drif1_ctrl_a", 4816 "drif1_data0_a", 4817 "drif1_data1_a", 4818 "drif1_ctrl_b", 4819 "drif1_data0_b", 4820 "drif1_data1_b", 4821 "drif1_ctrl_c", 4822 "drif1_data0_c", 4823 "drif1_data1_c", 4824 }; 4825 4826 static const char * const drif2_groups[] = { 4827 "drif2_ctrl_a", 4828 "drif2_data0_a", 4829 "drif2_data1_a", 4830 "drif2_ctrl_b", 4831 "drif2_data0_b", 4832 "drif2_data1_b", 4833 }; 4834 4835 static const char * const drif3_groups[] = { 4836 "drif3_ctrl_a", 4837 "drif3_data0_a", 4838 "drif3_data1_a", 4839 "drif3_ctrl_b", 4840 "drif3_data0_b", 4841 "drif3_data1_b", 4842 }; 4843 #endif /* CONFIG_PINCTRL_PFC_R8A77965 */ 4844 4845 static const char * const du_groups[] = { 4846 "du_rgb666", 4847 "du_rgb888", 4848 "du_clk_out_0", 4849 "du_clk_out_1", 4850 "du_sync", 4851 "du_oddf", 4852 "du_cde", 4853 "du_disp", 4854 }; 4855 4856 static const char * const hscif0_groups[] = { 4857 "hscif0_data", 4858 "hscif0_clk", 4859 "hscif0_ctrl", 4860 }; 4861 4862 static const char * const hscif1_groups[] = { 4863 "hscif1_data_a", 4864 "hscif1_clk_a", 4865 "hscif1_ctrl_a", 4866 "hscif1_data_b", 4867 "hscif1_clk_b", 4868 "hscif1_ctrl_b", 4869 }; 4870 4871 static const char * const hscif2_groups[] = { 4872 "hscif2_data_a", 4873 "hscif2_clk_a", 4874 "hscif2_ctrl_a", 4875 "hscif2_data_b", 4876 "hscif2_clk_b", 4877 "hscif2_ctrl_b", 4878 "hscif2_data_c", 4879 "hscif2_clk_c", 4880 "hscif2_ctrl_c", 4881 }; 4882 4883 static const char * const hscif3_groups[] = { 4884 "hscif3_data_a", 4885 "hscif3_clk", 4886 "hscif3_ctrl", 4887 "hscif3_data_b", 4888 "hscif3_data_c", 4889 "hscif3_data_d", 4890 }; 4891 4892 static const char * const hscif4_groups[] = { 4893 "hscif4_data_a", 4894 "hscif4_clk", 4895 "hscif4_ctrl", 4896 "hscif4_data_b", 4897 }; 4898 4899 static const char * const i2c0_groups[] = { 4900 "i2c0", 4901 }; 4902 4903 static const char * const i2c1_groups[] = { 4904 "i2c1_a", 4905 "i2c1_b", 4906 }; 4907 4908 static const char * const i2c2_groups[] = { 4909 "i2c2_a", 4910 "i2c2_b", 4911 }; 4912 4913 static const char * const i2c3_groups[] = { 4914 "i2c3", 4915 }; 4916 4917 static const char * const i2c5_groups[] = { 4918 "i2c5", 4919 }; 4920 4921 static const char * const i2c6_groups[] = { 4922 "i2c6_a", 4923 "i2c6_b", 4924 "i2c6_c", 4925 }; 4926 4927 static const char * const intc_ex_groups[] = { 4928 "intc_ex_irq0", 4929 "intc_ex_irq1", 4930 "intc_ex_irq2", 4931 "intc_ex_irq3", 4932 "intc_ex_irq4", 4933 "intc_ex_irq5", 4934 }; 4935 4936 static const char * const msiof0_groups[] = { 4937 "msiof0_clk", 4938 "msiof0_sync", 4939 "msiof0_ss1", 4940 "msiof0_ss2", 4941 "msiof0_txd", 4942 "msiof0_rxd", 4943 }; 4944 4945 static const char * const msiof1_groups[] = { 4946 "msiof1_clk_a", 4947 "msiof1_sync_a", 4948 "msiof1_ss1_a", 4949 "msiof1_ss2_a", 4950 "msiof1_txd_a", 4951 "msiof1_rxd_a", 4952 "msiof1_clk_b", 4953 "msiof1_sync_b", 4954 "msiof1_ss1_b", 4955 "msiof1_ss2_b", 4956 "msiof1_txd_b", 4957 "msiof1_rxd_b", 4958 "msiof1_clk_c", 4959 "msiof1_sync_c", 4960 "msiof1_ss1_c", 4961 "msiof1_ss2_c", 4962 "msiof1_txd_c", 4963 "msiof1_rxd_c", 4964 "msiof1_clk_d", 4965 "msiof1_sync_d", 4966 "msiof1_ss1_d", 4967 "msiof1_ss2_d", 4968 "msiof1_txd_d", 4969 "msiof1_rxd_d", 4970 "msiof1_clk_e", 4971 "msiof1_sync_e", 4972 "msiof1_ss1_e", 4973 "msiof1_ss2_e", 4974 "msiof1_txd_e", 4975 "msiof1_rxd_e", 4976 "msiof1_clk_f", 4977 "msiof1_sync_f", 4978 "msiof1_ss1_f", 4979 "msiof1_ss2_f", 4980 "msiof1_txd_f", 4981 "msiof1_rxd_f", 4982 "msiof1_clk_g", 4983 "msiof1_sync_g", 4984 "msiof1_ss1_g", 4985 "msiof1_ss2_g", 4986 "msiof1_txd_g", 4987 "msiof1_rxd_g", 4988 }; 4989 4990 static const char * const msiof2_groups[] = { 4991 "msiof2_clk_a", 4992 "msiof2_sync_a", 4993 "msiof2_ss1_a", 4994 "msiof2_ss2_a", 4995 "msiof2_txd_a", 4996 "msiof2_rxd_a", 4997 "msiof2_clk_b", 4998 "msiof2_sync_b", 4999 "msiof2_ss1_b", 5000 "msiof2_ss2_b", 5001 "msiof2_txd_b", 5002 "msiof2_rxd_b", 5003 "msiof2_clk_c", 5004 "msiof2_sync_c", 5005 "msiof2_ss1_c", 5006 "msiof2_ss2_c", 5007 "msiof2_txd_c", 5008 "msiof2_rxd_c", 5009 "msiof2_clk_d", 5010 "msiof2_sync_d", 5011 "msiof2_ss1_d", 5012 "msiof2_ss2_d", 5013 "msiof2_txd_d", 5014 "msiof2_rxd_d", 5015 }; 5016 5017 static const char * const msiof3_groups[] = { 5018 "msiof3_clk_a", 5019 "msiof3_sync_a", 5020 "msiof3_ss1_a", 5021 "msiof3_ss2_a", 5022 "msiof3_txd_a", 5023 "msiof3_rxd_a", 5024 "msiof3_clk_b", 5025 "msiof3_sync_b", 5026 "msiof3_ss1_b", 5027 "msiof3_ss2_b", 5028 "msiof3_txd_b", 5029 "msiof3_rxd_b", 5030 "msiof3_clk_c", 5031 "msiof3_sync_c", 5032 "msiof3_txd_c", 5033 "msiof3_rxd_c", 5034 "msiof3_clk_d", 5035 "msiof3_sync_d", 5036 "msiof3_ss1_d", 5037 "msiof3_txd_d", 5038 "msiof3_rxd_d", 5039 "msiof3_clk_e", 5040 "msiof3_sync_e", 5041 "msiof3_ss1_e", 5042 "msiof3_ss2_e", 5043 "msiof3_txd_e", 5044 "msiof3_rxd_e", 5045 }; 5046 5047 static const char * const pwm0_groups[] = { 5048 "pwm0", 5049 }; 5050 5051 static const char * const pwm1_groups[] = { 5052 "pwm1_a", 5053 "pwm1_b", 5054 }; 5055 5056 static const char * const pwm2_groups[] = { 5057 "pwm2_a", 5058 "pwm2_b", 5059 }; 5060 5061 static const char * const pwm3_groups[] = { 5062 "pwm3_a", 5063 "pwm3_b", 5064 }; 5065 5066 static const char * const pwm4_groups[] = { 5067 "pwm4_a", 5068 "pwm4_b", 5069 }; 5070 5071 static const char * const pwm5_groups[] = { 5072 "pwm5_a", 5073 "pwm5_b", 5074 }; 5075 5076 static const char * const pwm6_groups[] = { 5077 "pwm6_a", 5078 "pwm6_b", 5079 }; 5080 5081 static const char * const sata0_groups[] = { 5082 "sata0_devslp_a", 5083 "sata0_devslp_b", 5084 }; 5085 5086 static const char * const scif0_groups[] = { 5087 "scif0_data", 5088 "scif0_clk", 5089 "scif0_ctrl", 5090 }; 5091 5092 static const char * const scif1_groups[] = { 5093 "scif1_data_a", 5094 "scif1_clk", 5095 "scif1_ctrl", 5096 "scif1_data_b", 5097 }; 5098 static const char * const scif2_groups[] = { 5099 "scif2_data_a", 5100 "scif2_clk", 5101 "scif2_data_b", 5102 }; 5103 5104 static const char * const scif3_groups[] = { 5105 "scif3_data_a", 5106 "scif3_clk", 5107 "scif3_ctrl", 5108 "scif3_data_b", 5109 }; 5110 5111 static const char * const scif4_groups[] = { 5112 "scif4_data_a", 5113 "scif4_clk_a", 5114 "scif4_ctrl_a", 5115 "scif4_data_b", 5116 "scif4_clk_b", 5117 "scif4_ctrl_b", 5118 "scif4_data_c", 5119 "scif4_clk_c", 5120 "scif4_ctrl_c", 5121 }; 5122 5123 static const char * const scif5_groups[] = { 5124 "scif5_data_a", 5125 "scif5_clk_a", 5126 "scif5_data_b", 5127 "scif5_clk_b", 5128 }; 5129 5130 static const char * const scif_clk_groups[] = { 5131 "scif_clk_a", 5132 "scif_clk_b", 5133 }; 5134 5135 static const char * const sdhi0_groups[] = { 5136 "sdhi0_data1", 5137 "sdhi0_data4", 5138 "sdhi0_ctrl", 5139 "sdhi0_cd", 5140 "sdhi0_wp", 5141 }; 5142 5143 static const char * const sdhi1_groups[] = { 5144 "sdhi1_data1", 5145 "sdhi1_data4", 5146 "sdhi1_ctrl", 5147 "sdhi1_cd", 5148 "sdhi1_wp", 5149 }; 5150 5151 static const char * const sdhi2_groups[] = { 5152 "sdhi2_data1", 5153 "sdhi2_data4", 5154 "sdhi2_data8", 5155 "sdhi2_ctrl", 5156 "sdhi2_cd_a", 5157 "sdhi2_wp_a", 5158 "sdhi2_cd_b", 5159 "sdhi2_wp_b", 5160 "sdhi2_ds", 5161 }; 5162 5163 static const char * const sdhi3_groups[] = { 5164 "sdhi3_data1", 5165 "sdhi3_data4", 5166 "sdhi3_data8", 5167 "sdhi3_ctrl", 5168 "sdhi3_cd", 5169 "sdhi3_wp", 5170 "sdhi3_ds", 5171 }; 5172 5173 static const char * const ssi_groups[] = { 5174 "ssi0_data", 5175 "ssi01239_ctrl", 5176 "ssi1_data_a", 5177 "ssi1_data_b", 5178 "ssi1_ctrl_a", 5179 "ssi1_ctrl_b", 5180 "ssi2_data_a", 5181 "ssi2_data_b", 5182 "ssi2_ctrl_a", 5183 "ssi2_ctrl_b", 5184 "ssi3_data", 5185 "ssi349_ctrl", 5186 "ssi4_data", 5187 "ssi4_ctrl", 5188 "ssi5_data", 5189 "ssi5_ctrl", 5190 "ssi6_data", 5191 "ssi6_ctrl", 5192 "ssi7_data", 5193 "ssi78_ctrl", 5194 "ssi8_data", 5195 "ssi9_data_a", 5196 "ssi9_data_b", 5197 "ssi9_ctrl_a", 5198 "ssi9_ctrl_b", 5199 }; 5200 5201 static const char * const tmu_groups[] = { 5202 "tmu_tclk1_a", 5203 "tmu_tclk1_b", 5204 "tmu_tclk2_a", 5205 "tmu_tclk2_b", 5206 }; 5207 5208 static const char * const tpu_groups[] = { 5209 "tpu_to0", 5210 "tpu_to1", 5211 "tpu_to2", 5212 "tpu_to3", 5213 }; 5214 5215 static const char * const usb0_groups[] = { 5216 "usb0", 5217 }; 5218 5219 static const char * const usb1_groups[] = { 5220 "usb1", 5221 }; 5222 5223 static const char * const usb30_groups[] = { 5224 "usb30", 5225 }; 5226 5227 static const char * const vin4_groups[] = { 5228 "vin4_data8_a", 5229 "vin4_data10_a", 5230 "vin4_data12_a", 5231 "vin4_data16_a", 5232 "vin4_data18_a", 5233 "vin4_data20_a", 5234 "vin4_data24_a", 5235 "vin4_data8_b", 5236 "vin4_data10_b", 5237 "vin4_data12_b", 5238 "vin4_data16_b", 5239 "vin4_data18_b", 5240 "vin4_data20_b", 5241 "vin4_data24_b", 5242 "vin4_sync", 5243 "vin4_field", 5244 "vin4_clkenb", 5245 "vin4_clk", 5246 }; 5247 5248 static const char * const vin5_groups[] = { 5249 "vin5_data8", 5250 "vin5_data10", 5251 "vin5_data12", 5252 "vin5_data16", 5253 "vin5_sync", 5254 "vin5_field", 5255 "vin5_clkenb", 5256 "vin5_clk", 5257 }; 5258 5259 static const struct { 5260 struct sh_pfc_function common[51]; 5261 #ifdef CONFIG_PINCTRL_PFC_R8A77965 5262 struct sh_pfc_function automotive[4]; 5263 #endif 5264 } pinmux_functions = { 5265 .common = { 5266 SH_PFC_FUNCTION(audio_clk), 5267 SH_PFC_FUNCTION(avb), 5268 SH_PFC_FUNCTION(can0), 5269 SH_PFC_FUNCTION(can1), 5270 SH_PFC_FUNCTION(can_clk), 5271 SH_PFC_FUNCTION(canfd0), 5272 SH_PFC_FUNCTION(canfd1), 5273 SH_PFC_FUNCTION(du), 5274 SH_PFC_FUNCTION(hscif0), 5275 SH_PFC_FUNCTION(hscif1), 5276 SH_PFC_FUNCTION(hscif2), 5277 SH_PFC_FUNCTION(hscif3), 5278 SH_PFC_FUNCTION(hscif4), 5279 SH_PFC_FUNCTION(i2c0), 5280 SH_PFC_FUNCTION(i2c1), 5281 SH_PFC_FUNCTION(i2c2), 5282 SH_PFC_FUNCTION(i2c3), 5283 SH_PFC_FUNCTION(i2c5), 5284 SH_PFC_FUNCTION(i2c6), 5285 SH_PFC_FUNCTION(intc_ex), 5286 SH_PFC_FUNCTION(msiof0), 5287 SH_PFC_FUNCTION(msiof1), 5288 SH_PFC_FUNCTION(msiof2), 5289 SH_PFC_FUNCTION(msiof3), 5290 SH_PFC_FUNCTION(pwm0), 5291 SH_PFC_FUNCTION(pwm1), 5292 SH_PFC_FUNCTION(pwm2), 5293 SH_PFC_FUNCTION(pwm3), 5294 SH_PFC_FUNCTION(pwm4), 5295 SH_PFC_FUNCTION(pwm5), 5296 SH_PFC_FUNCTION(pwm6), 5297 SH_PFC_FUNCTION(sata0), 5298 SH_PFC_FUNCTION(scif0), 5299 SH_PFC_FUNCTION(scif1), 5300 SH_PFC_FUNCTION(scif2), 5301 SH_PFC_FUNCTION(scif3), 5302 SH_PFC_FUNCTION(scif4), 5303 SH_PFC_FUNCTION(scif5), 5304 SH_PFC_FUNCTION(scif_clk), 5305 SH_PFC_FUNCTION(sdhi0), 5306 SH_PFC_FUNCTION(sdhi1), 5307 SH_PFC_FUNCTION(sdhi2), 5308 SH_PFC_FUNCTION(sdhi3), 5309 SH_PFC_FUNCTION(ssi), 5310 SH_PFC_FUNCTION(tmu), 5311 SH_PFC_FUNCTION(tpu), 5312 SH_PFC_FUNCTION(usb0), 5313 SH_PFC_FUNCTION(usb1), 5314 SH_PFC_FUNCTION(usb30), 5315 SH_PFC_FUNCTION(vin4), 5316 SH_PFC_FUNCTION(vin5), 5317 }, 5318 #ifdef CONFIG_PINCTRL_PFC_R8A77965 5319 .automotive = { 5320 SH_PFC_FUNCTION(drif0), 5321 SH_PFC_FUNCTION(drif1), 5322 SH_PFC_FUNCTION(drif2), 5323 SH_PFC_FUNCTION(drif3), 5324 } 5325 #endif /* CONFIG_PINCTRL_PFC_R8A77965 */ 5326 }; 5327 5328 static const struct pinmux_cfg_reg pinmux_config_regs[] = { 5329 #define F_(x, y) FN_##y 5330 #define FM(x) FN_##x 5331 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP( 5332 0, 0, 5333 0, 0, 5334 0, 0, 5335 0, 0, 5336 0, 0, 5337 0, 0, 5338 0, 0, 5339 0, 0, 5340 0, 0, 5341 0, 0, 5342 0, 0, 5343 0, 0, 5344 0, 0, 5345 0, 0, 5346 0, 0, 5347 0, 0, 5348 GP_0_15_FN, GPSR0_15, 5349 GP_0_14_FN, GPSR0_14, 5350 GP_0_13_FN, GPSR0_13, 5351 GP_0_12_FN, GPSR0_12, 5352 GP_0_11_FN, GPSR0_11, 5353 GP_0_10_FN, GPSR0_10, 5354 GP_0_9_FN, GPSR0_9, 5355 GP_0_8_FN, GPSR0_8, 5356 GP_0_7_FN, GPSR0_7, 5357 GP_0_6_FN, GPSR0_6, 5358 GP_0_5_FN, GPSR0_5, 5359 GP_0_4_FN, GPSR0_4, 5360 GP_0_3_FN, GPSR0_3, 5361 GP_0_2_FN, GPSR0_2, 5362 GP_0_1_FN, GPSR0_1, 5363 GP_0_0_FN, GPSR0_0, )) 5364 }, 5365 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP( 5366 0, 0, 5367 0, 0, 5368 0, 0, 5369 GP_1_28_FN, GPSR1_28, 5370 GP_1_27_FN, GPSR1_27, 5371 GP_1_26_FN, GPSR1_26, 5372 GP_1_25_FN, GPSR1_25, 5373 GP_1_24_FN, GPSR1_24, 5374 GP_1_23_FN, GPSR1_23, 5375 GP_1_22_FN, GPSR1_22, 5376 GP_1_21_FN, GPSR1_21, 5377 GP_1_20_FN, GPSR1_20, 5378 GP_1_19_FN, GPSR1_19, 5379 GP_1_18_FN, GPSR1_18, 5380 GP_1_17_FN, GPSR1_17, 5381 GP_1_16_FN, GPSR1_16, 5382 GP_1_15_FN, GPSR1_15, 5383 GP_1_14_FN, GPSR1_14, 5384 GP_1_13_FN, GPSR1_13, 5385 GP_1_12_FN, GPSR1_12, 5386 GP_1_11_FN, GPSR1_11, 5387 GP_1_10_FN, GPSR1_10, 5388 GP_1_9_FN, GPSR1_9, 5389 GP_1_8_FN, GPSR1_8, 5390 GP_1_7_FN, GPSR1_7, 5391 GP_1_6_FN, GPSR1_6, 5392 GP_1_5_FN, GPSR1_5, 5393 GP_1_4_FN, GPSR1_4, 5394 GP_1_3_FN, GPSR1_3, 5395 GP_1_2_FN, GPSR1_2, 5396 GP_1_1_FN, GPSR1_1, 5397 GP_1_0_FN, GPSR1_0, )) 5398 }, 5399 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP( 5400 0, 0, 5401 0, 0, 5402 0, 0, 5403 0, 0, 5404 0, 0, 5405 0, 0, 5406 0, 0, 5407 0, 0, 5408 0, 0, 5409 0, 0, 5410 0, 0, 5411 0, 0, 5412 0, 0, 5413 0, 0, 5414 0, 0, 5415 0, 0, 5416 0, 0, 5417 GP_2_14_FN, GPSR2_14, 5418 GP_2_13_FN, GPSR2_13, 5419 GP_2_12_FN, GPSR2_12, 5420 GP_2_11_FN, GPSR2_11, 5421 GP_2_10_FN, GPSR2_10, 5422 GP_2_9_FN, GPSR2_9, 5423 GP_2_8_FN, GPSR2_8, 5424 GP_2_7_FN, GPSR2_7, 5425 GP_2_6_FN, GPSR2_6, 5426 GP_2_5_FN, GPSR2_5, 5427 GP_2_4_FN, GPSR2_4, 5428 GP_2_3_FN, GPSR2_3, 5429 GP_2_2_FN, GPSR2_2, 5430 GP_2_1_FN, GPSR2_1, 5431 GP_2_0_FN, GPSR2_0, )) 5432 }, 5433 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP( 5434 0, 0, 5435 0, 0, 5436 0, 0, 5437 0, 0, 5438 0, 0, 5439 0, 0, 5440 0, 0, 5441 0, 0, 5442 0, 0, 5443 0, 0, 5444 0, 0, 5445 0, 0, 5446 0, 0, 5447 0, 0, 5448 0, 0, 5449 0, 0, 5450 GP_3_15_FN, GPSR3_15, 5451 GP_3_14_FN, GPSR3_14, 5452 GP_3_13_FN, GPSR3_13, 5453 GP_3_12_FN, GPSR3_12, 5454 GP_3_11_FN, GPSR3_11, 5455 GP_3_10_FN, GPSR3_10, 5456 GP_3_9_FN, GPSR3_9, 5457 GP_3_8_FN, GPSR3_8, 5458 GP_3_7_FN, GPSR3_7, 5459 GP_3_6_FN, GPSR3_6, 5460 GP_3_5_FN, GPSR3_5, 5461 GP_3_4_FN, GPSR3_4, 5462 GP_3_3_FN, GPSR3_3, 5463 GP_3_2_FN, GPSR3_2, 5464 GP_3_1_FN, GPSR3_1, 5465 GP_3_0_FN, GPSR3_0, )) 5466 }, 5467 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP( 5468 0, 0, 5469 0, 0, 5470 0, 0, 5471 0, 0, 5472 0, 0, 5473 0, 0, 5474 0, 0, 5475 0, 0, 5476 0, 0, 5477 0, 0, 5478 0, 0, 5479 0, 0, 5480 0, 0, 5481 0, 0, 5482 GP_4_17_FN, GPSR4_17, 5483 GP_4_16_FN, GPSR4_16, 5484 GP_4_15_FN, GPSR4_15, 5485 GP_4_14_FN, GPSR4_14, 5486 GP_4_13_FN, GPSR4_13, 5487 GP_4_12_FN, GPSR4_12, 5488 GP_4_11_FN, GPSR4_11, 5489 GP_4_10_FN, GPSR4_10, 5490 GP_4_9_FN, GPSR4_9, 5491 GP_4_8_FN, GPSR4_8, 5492 GP_4_7_FN, GPSR4_7, 5493 GP_4_6_FN, GPSR4_6, 5494 GP_4_5_FN, GPSR4_5, 5495 GP_4_4_FN, GPSR4_4, 5496 GP_4_3_FN, GPSR4_3, 5497 GP_4_2_FN, GPSR4_2, 5498 GP_4_1_FN, GPSR4_1, 5499 GP_4_0_FN, GPSR4_0, )) 5500 }, 5501 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP( 5502 0, 0, 5503 0, 0, 5504 0, 0, 5505 0, 0, 5506 0, 0, 5507 0, 0, 5508 GP_5_25_FN, GPSR5_25, 5509 GP_5_24_FN, GPSR5_24, 5510 GP_5_23_FN, GPSR5_23, 5511 GP_5_22_FN, GPSR5_22, 5512 GP_5_21_FN, GPSR5_21, 5513 GP_5_20_FN, GPSR5_20, 5514 GP_5_19_FN, GPSR5_19, 5515 GP_5_18_FN, GPSR5_18, 5516 GP_5_17_FN, GPSR5_17, 5517 GP_5_16_FN, GPSR5_16, 5518 GP_5_15_FN, GPSR5_15, 5519 GP_5_14_FN, GPSR5_14, 5520 GP_5_13_FN, GPSR5_13, 5521 GP_5_12_FN, GPSR5_12, 5522 GP_5_11_FN, GPSR5_11, 5523 GP_5_10_FN, GPSR5_10, 5524 GP_5_9_FN, GPSR5_9, 5525 GP_5_8_FN, GPSR5_8, 5526 GP_5_7_FN, GPSR5_7, 5527 GP_5_6_FN, GPSR5_6, 5528 GP_5_5_FN, GPSR5_5, 5529 GP_5_4_FN, GPSR5_4, 5530 GP_5_3_FN, GPSR5_3, 5531 GP_5_2_FN, GPSR5_2, 5532 GP_5_1_FN, GPSR5_1, 5533 GP_5_0_FN, GPSR5_0, )) 5534 }, 5535 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP( 5536 GP_6_31_FN, GPSR6_31, 5537 GP_6_30_FN, GPSR6_30, 5538 GP_6_29_FN, GPSR6_29, 5539 GP_6_28_FN, GPSR6_28, 5540 GP_6_27_FN, GPSR6_27, 5541 GP_6_26_FN, GPSR6_26, 5542 GP_6_25_FN, GPSR6_25, 5543 GP_6_24_FN, GPSR6_24, 5544 GP_6_23_FN, GPSR6_23, 5545 GP_6_22_FN, GPSR6_22, 5546 GP_6_21_FN, GPSR6_21, 5547 GP_6_20_FN, GPSR6_20, 5548 GP_6_19_FN, GPSR6_19, 5549 GP_6_18_FN, GPSR6_18, 5550 GP_6_17_FN, GPSR6_17, 5551 GP_6_16_FN, GPSR6_16, 5552 GP_6_15_FN, GPSR6_15, 5553 GP_6_14_FN, GPSR6_14, 5554 GP_6_13_FN, GPSR6_13, 5555 GP_6_12_FN, GPSR6_12, 5556 GP_6_11_FN, GPSR6_11, 5557 GP_6_10_FN, GPSR6_10, 5558 GP_6_9_FN, GPSR6_9, 5559 GP_6_8_FN, GPSR6_8, 5560 GP_6_7_FN, GPSR6_7, 5561 GP_6_6_FN, GPSR6_6, 5562 GP_6_5_FN, GPSR6_5, 5563 GP_6_4_FN, GPSR6_4, 5564 GP_6_3_FN, GPSR6_3, 5565 GP_6_2_FN, GPSR6_2, 5566 GP_6_1_FN, GPSR6_1, 5567 GP_6_0_FN, GPSR6_0, )) 5568 }, 5569 { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1, GROUP( 5570 0, 0, 5571 0, 0, 5572 0, 0, 5573 0, 0, 5574 0, 0, 5575 0, 0, 5576 0, 0, 5577 0, 0, 5578 0, 0, 5579 0, 0, 5580 0, 0, 5581 0, 0, 5582 0, 0, 5583 0, 0, 5584 0, 0, 5585 0, 0, 5586 0, 0, 5587 0, 0, 5588 0, 0, 5589 0, 0, 5590 0, 0, 5591 0, 0, 5592 0, 0, 5593 0, 0, 5594 0, 0, 5595 0, 0, 5596 0, 0, 5597 0, 0, 5598 GP_7_3_FN, GPSR7_3, 5599 GP_7_2_FN, GPSR7_2, 5600 GP_7_1_FN, GPSR7_1, 5601 GP_7_0_FN, GPSR7_0, )) 5602 }, 5603 #undef F_ 5604 #undef FM 5605 5606 #define F_(x, y) x, 5607 #define FM(x) FN_##x, 5608 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP( 5609 IP0_31_28 5610 IP0_27_24 5611 IP0_23_20 5612 IP0_19_16 5613 IP0_15_12 5614 IP0_11_8 5615 IP0_7_4 5616 IP0_3_0 )) 5617 }, 5618 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP( 5619 IP1_31_28 5620 IP1_27_24 5621 IP1_23_20 5622 IP1_19_16 5623 IP1_15_12 5624 IP1_11_8 5625 IP1_7_4 5626 IP1_3_0 )) 5627 }, 5628 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP( 5629 IP2_31_28 5630 IP2_27_24 5631 IP2_23_20 5632 IP2_19_16 5633 IP2_15_12 5634 IP2_11_8 5635 IP2_7_4 5636 IP2_3_0 )) 5637 }, 5638 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP( 5639 IP3_31_28 5640 IP3_27_24 5641 IP3_23_20 5642 IP3_19_16 5643 IP3_15_12 5644 IP3_11_8 5645 IP3_7_4 5646 IP3_3_0 )) 5647 }, 5648 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP( 5649 IP4_31_28 5650 IP4_27_24 5651 IP4_23_20 5652 IP4_19_16 5653 IP4_15_12 5654 IP4_11_8 5655 IP4_7_4 5656 IP4_3_0 )) 5657 }, 5658 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP( 5659 IP5_31_28 5660 IP5_27_24 5661 IP5_23_20 5662 IP5_19_16 5663 IP5_15_12 5664 IP5_11_8 5665 IP5_7_4 5666 IP5_3_0 )) 5667 }, 5668 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP( 5669 IP6_31_28 5670 IP6_27_24 5671 IP6_23_20 5672 IP6_19_16 5673 IP6_15_12 5674 IP6_11_8 5675 IP6_7_4 5676 IP6_3_0 )) 5677 }, 5678 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP( 5679 IP7_31_28 5680 IP7_27_24 5681 IP7_23_20 5682 IP7_19_16 5683 /* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5684 IP7_11_8 5685 IP7_7_4 5686 IP7_3_0 )) 5687 }, 5688 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP( 5689 IP8_31_28 5690 IP8_27_24 5691 IP8_23_20 5692 IP8_19_16 5693 IP8_15_12 5694 IP8_11_8 5695 IP8_7_4 5696 IP8_3_0 )) 5697 }, 5698 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP( 5699 IP9_31_28 5700 IP9_27_24 5701 IP9_23_20 5702 IP9_19_16 5703 IP9_15_12 5704 IP9_11_8 5705 IP9_7_4 5706 IP9_3_0 )) 5707 }, 5708 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP( 5709 IP10_31_28 5710 IP10_27_24 5711 IP10_23_20 5712 IP10_19_16 5713 IP10_15_12 5714 IP10_11_8 5715 IP10_7_4 5716 IP10_3_0 )) 5717 }, 5718 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP( 5719 IP11_31_28 5720 IP11_27_24 5721 IP11_23_20 5722 IP11_19_16 5723 IP11_15_12 5724 IP11_11_8 5725 IP11_7_4 5726 IP11_3_0 )) 5727 }, 5728 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP( 5729 IP12_31_28 5730 IP12_27_24 5731 IP12_23_20 5732 IP12_19_16 5733 IP12_15_12 5734 IP12_11_8 5735 IP12_7_4 5736 IP12_3_0 )) 5737 }, 5738 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP( 5739 IP13_31_28 5740 IP13_27_24 5741 IP13_23_20 5742 IP13_19_16 5743 IP13_15_12 5744 IP13_11_8 5745 IP13_7_4 5746 IP13_3_0 )) 5747 }, 5748 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP( 5749 IP14_31_28 5750 IP14_27_24 5751 IP14_23_20 5752 IP14_19_16 5753 IP14_15_12 5754 IP14_11_8 5755 IP14_7_4 5756 IP14_3_0 )) 5757 }, 5758 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP( 5759 IP15_31_28 5760 IP15_27_24 5761 IP15_23_20 5762 IP15_19_16 5763 IP15_15_12 5764 IP15_11_8 5765 IP15_7_4 5766 IP15_3_0 )) 5767 }, 5768 { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4, GROUP( 5769 IP16_31_28 5770 IP16_27_24 5771 IP16_23_20 5772 IP16_19_16 5773 IP16_15_12 5774 IP16_11_8 5775 IP16_7_4 5776 IP16_3_0 )) 5777 }, 5778 { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4, GROUP( 5779 IP17_31_28 5780 IP17_27_24 5781 IP17_23_20 5782 IP17_19_16 5783 IP17_15_12 5784 IP17_11_8 5785 IP17_7_4 5786 IP17_3_0 )) 5787 }, 5788 { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4, GROUP( 5789 /* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5790 /* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5791 /* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5792 /* IP18_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5793 /* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5794 /* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5795 IP18_7_4 5796 IP18_3_0 )) 5797 }, 5798 #undef F_ 5799 #undef FM 5800 5801 #define F_(x, y) x, 5802 #define FM(x) FN_##x, 5803 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32, 5804 GROUP(3, 2, 3, 1, 1, 1, 1, 1, 2, 1, 1, 2, 5805 1, 1, 1, 2, 2, 1, 2, 3), 5806 GROUP( 5807 MOD_SEL0_31_30_29 5808 MOD_SEL0_28_27 5809 MOD_SEL0_26_25_24 5810 MOD_SEL0_23 5811 MOD_SEL0_22 5812 MOD_SEL0_21 5813 MOD_SEL0_20 5814 MOD_SEL0_19 5815 MOD_SEL0_18_17 5816 MOD_SEL0_16 5817 0, 0, /* RESERVED 15 */ 5818 MOD_SEL0_14_13 5819 MOD_SEL0_12 5820 MOD_SEL0_11 5821 MOD_SEL0_10 5822 MOD_SEL0_9_8 5823 MOD_SEL0_7_6 5824 MOD_SEL0_5 5825 MOD_SEL0_4_3 5826 /* RESERVED 2, 1, 0 */ 5827 0, 0, 0, 0, 0, 0, 0, 0 )) 5828 }, 5829 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32, 5830 GROUP(2, 3, 1, 2, 3, 1, 1, 2, 1, 2, 1, 1, 5831 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1), 5832 GROUP( 5833 MOD_SEL1_31_30 5834 MOD_SEL1_29_28_27 5835 MOD_SEL1_26 5836 MOD_SEL1_25_24 5837 MOD_SEL1_23_22_21 5838 MOD_SEL1_20 5839 MOD_SEL1_19 5840 MOD_SEL1_18_17 5841 MOD_SEL1_16 5842 MOD_SEL1_15_14 5843 MOD_SEL1_13 5844 MOD_SEL1_12 5845 MOD_SEL1_11 5846 MOD_SEL1_10 5847 MOD_SEL1_9 5848 0, 0, 0, 0, /* RESERVED 8, 7 */ 5849 MOD_SEL1_6 5850 MOD_SEL1_5 5851 MOD_SEL1_4 5852 MOD_SEL1_3 5853 MOD_SEL1_2 5854 MOD_SEL1_1 5855 MOD_SEL1_0 )) 5856 }, 5857 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32, 5858 GROUP(1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, 5859 1, 4, 4, 4, 3, 1), 5860 GROUP( 5861 MOD_SEL2_31 5862 MOD_SEL2_30 5863 MOD_SEL2_29 5864 MOD_SEL2_28_27 5865 MOD_SEL2_26 5866 MOD_SEL2_25_24_23 5867 MOD_SEL2_22 5868 MOD_SEL2_21 5869 MOD_SEL2_20 5870 MOD_SEL2_19 5871 MOD_SEL2_18 5872 MOD_SEL2_17 5873 /* RESERVED 16 */ 5874 0, 0, 5875 /* RESERVED 15, 14, 13, 12 */ 5876 0, 0, 0, 0, 0, 0, 0, 0, 5877 0, 0, 0, 0, 0, 0, 0, 0, 5878 /* RESERVED 11, 10, 9, 8 */ 5879 0, 0, 0, 0, 0, 0, 0, 0, 5880 0, 0, 0, 0, 0, 0, 0, 0, 5881 /* RESERVED 7, 6, 5, 4 */ 5882 0, 0, 0, 0, 0, 0, 0, 0, 5883 0, 0, 0, 0, 0, 0, 0, 0, 5884 /* RESERVED 3, 2, 1 */ 5885 0, 0, 0, 0, 0, 0, 0, 0, 5886 MOD_SEL2_0 )) 5887 }, 5888 { }, 5889 }; 5890 5891 static const struct pinmux_drive_reg pinmux_drive_regs[] = { 5892 { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) { 5893 { PIN_QSPI0_SPCLK, 28, 2 }, /* QSPI0_SPCLK */ 5894 { PIN_QSPI0_MOSI_IO0, 24, 2 }, /* QSPI0_MOSI_IO0 */ 5895 { PIN_QSPI0_MISO_IO1, 20, 2 }, /* QSPI0_MISO_IO1 */ 5896 { PIN_QSPI0_IO2, 16, 2 }, /* QSPI0_IO2 */ 5897 { PIN_QSPI0_IO3, 12, 2 }, /* QSPI0_IO3 */ 5898 { PIN_QSPI0_SSL, 8, 2 }, /* QSPI0_SSL */ 5899 { PIN_QSPI1_SPCLK, 4, 2 }, /* QSPI1_SPCLK */ 5900 { PIN_QSPI1_MOSI_IO0, 0, 2 }, /* QSPI1_MOSI_IO0 */ 5901 } }, 5902 { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) { 5903 { PIN_QSPI1_MISO_IO1, 28, 2 }, /* QSPI1_MISO_IO1 */ 5904 { PIN_QSPI1_IO2, 24, 2 }, /* QSPI1_IO2 */ 5905 { PIN_QSPI1_IO3, 20, 2 }, /* QSPI1_IO3 */ 5906 { PIN_QSPI1_SSL, 16, 2 }, /* QSPI1_SSL */ 5907 { PIN_RPC_INT_N, 12, 2 }, /* RPC_INT# */ 5908 { PIN_RPC_WP_N, 8, 2 }, /* RPC_WP# */ 5909 { PIN_RPC_RESET_N, 4, 2 }, /* RPC_RESET# */ 5910 { PIN_AVB_RX_CTL, 0, 3 }, /* AVB_RX_CTL */ 5911 } }, 5912 { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) { 5913 { PIN_AVB_RXC, 28, 3 }, /* AVB_RXC */ 5914 { PIN_AVB_RD0, 24, 3 }, /* AVB_RD0 */ 5915 { PIN_AVB_RD1, 20, 3 }, /* AVB_RD1 */ 5916 { PIN_AVB_RD2, 16, 3 }, /* AVB_RD2 */ 5917 { PIN_AVB_RD3, 12, 3 }, /* AVB_RD3 */ 5918 { PIN_AVB_TX_CTL, 8, 3 }, /* AVB_TX_CTL */ 5919 { PIN_AVB_TXC, 4, 3 }, /* AVB_TXC */ 5920 { PIN_AVB_TD0, 0, 3 }, /* AVB_TD0 */ 5921 } }, 5922 { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) { 5923 { PIN_AVB_TD1, 28, 3 }, /* AVB_TD1 */ 5924 { PIN_AVB_TD2, 24, 3 }, /* AVB_TD2 */ 5925 { PIN_AVB_TD3, 20, 3 }, /* AVB_TD3 */ 5926 { PIN_AVB_TXCREFCLK, 16, 3 }, /* AVB_TXCREFCLK */ 5927 { PIN_AVB_MDIO, 12, 3 }, /* AVB_MDIO */ 5928 { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */ 5929 { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */ 5930 { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */ 5931 } }, 5932 { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) { 5933 { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */ 5934 { RCAR_GP_PIN(2, 13), 24, 3 }, /* AVB_AVTP_MATCH */ 5935 { RCAR_GP_PIN(2, 14), 20, 3 }, /* AVB_AVTP_CAPTURE */ 5936 { RCAR_GP_PIN(2, 0), 16, 3 }, /* IRQ0 */ 5937 { RCAR_GP_PIN(2, 1), 12, 3 }, /* IRQ1 */ 5938 { RCAR_GP_PIN(2, 2), 8, 3 }, /* IRQ2 */ 5939 { RCAR_GP_PIN(2, 3), 4, 3 }, /* IRQ3 */ 5940 { RCAR_GP_PIN(2, 4), 0, 3 }, /* IRQ4 */ 5941 } }, 5942 { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) { 5943 { RCAR_GP_PIN(2, 5), 28, 3 }, /* IRQ5 */ 5944 { RCAR_GP_PIN(2, 6), 24, 3 }, /* PWM0 */ 5945 { RCAR_GP_PIN(2, 7), 20, 3 }, /* PWM1 */ 5946 { RCAR_GP_PIN(2, 8), 16, 3 }, /* PWM2 */ 5947 { RCAR_GP_PIN(1, 0), 12, 3 }, /* A0 */ 5948 { RCAR_GP_PIN(1, 1), 8, 3 }, /* A1 */ 5949 { RCAR_GP_PIN(1, 2), 4, 3 }, /* A2 */ 5950 { RCAR_GP_PIN(1, 3), 0, 3 }, /* A3 */ 5951 } }, 5952 { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) { 5953 { RCAR_GP_PIN(1, 4), 28, 3 }, /* A4 */ 5954 { RCAR_GP_PIN(1, 5), 24, 3 }, /* A5 */ 5955 { RCAR_GP_PIN(1, 6), 20, 3 }, /* A6 */ 5956 { RCAR_GP_PIN(1, 7), 16, 3 }, /* A7 */ 5957 { RCAR_GP_PIN(1, 8), 12, 3 }, /* A8 */ 5958 { RCAR_GP_PIN(1, 9), 8, 3 }, /* A9 */ 5959 { RCAR_GP_PIN(1, 10), 4, 3 }, /* A10 */ 5960 { RCAR_GP_PIN(1, 11), 0, 3 }, /* A11 */ 5961 } }, 5962 { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) { 5963 { RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */ 5964 { RCAR_GP_PIN(1, 13), 24, 3 }, /* A13 */ 5965 { RCAR_GP_PIN(1, 14), 20, 3 }, /* A14 */ 5966 { RCAR_GP_PIN(1, 15), 16, 3 }, /* A15 */ 5967 { RCAR_GP_PIN(1, 16), 12, 3 }, /* A16 */ 5968 { RCAR_GP_PIN(1, 17), 8, 3 }, /* A17 */ 5969 { RCAR_GP_PIN(1, 18), 4, 3 }, /* A18 */ 5970 { RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */ 5971 } }, 5972 { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) { 5973 { RCAR_GP_PIN(1, 28), 28, 3 }, /* CLKOUT */ 5974 { RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */ 5975 { RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */ 5976 { RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */ 5977 { RCAR_GP_PIN(1, 23), 12, 3 }, /* RD */ 5978 { RCAR_GP_PIN(1, 24), 8, 3 }, /* RD_WR */ 5979 { RCAR_GP_PIN(1, 25), 4, 3 }, /* WE0 */ 5980 { RCAR_GP_PIN(1, 26), 0, 3 }, /* WE1 */ 5981 } }, 5982 { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) { 5983 { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */ 5984 { PIN_PRESETOUT_N, 24, 3 }, /* PRESETOUT# */ 5985 { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */ 5986 { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */ 5987 { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */ 5988 { RCAR_GP_PIN(0, 3), 8, 3 }, /* D3 */ 5989 { RCAR_GP_PIN(0, 4), 4, 3 }, /* D4 */ 5990 { RCAR_GP_PIN(0, 5), 0, 3 }, /* D5 */ 5991 } }, 5992 { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) { 5993 { RCAR_GP_PIN(0, 6), 28, 3 }, /* D6 */ 5994 { RCAR_GP_PIN(0, 7), 24, 3 }, /* D7 */ 5995 { RCAR_GP_PIN(0, 8), 20, 3 }, /* D8 */ 5996 { RCAR_GP_PIN(0, 9), 16, 3 }, /* D9 */ 5997 { RCAR_GP_PIN(0, 10), 12, 3 }, /* D10 */ 5998 { RCAR_GP_PIN(0, 11), 8, 3 }, /* D11 */ 5999 { RCAR_GP_PIN(0, 12), 4, 3 }, /* D12 */ 6000 { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */ 6001 } }, 6002 { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) { 6003 { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */ 6004 { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */ 6005 { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */ 6006 { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */ 6007 { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */ 6008 { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */ 6009 { PIN_DU_DOTCLKIN0, 4, 2 }, /* DU_DOTCLKIN0 */ 6010 { PIN_DU_DOTCLKIN1, 0, 2 }, /* DU_DOTCLKIN1 */ 6011 } }, 6012 { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) { 6013 { PIN_DU_DOTCLKIN3, 24, 2 }, /* DU_DOTCLKIN3 */ 6014 { PIN_FSCLKST, 20, 2 }, /* FSCLKST */ 6015 { PIN_TMS, 4, 2 }, /* TMS */ 6016 } }, 6017 { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) { 6018 { PIN_TDO, 28, 2 }, /* TDO */ 6019 { PIN_ASEBRK, 24, 2 }, /* ASEBRK */ 6020 { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */ 6021 { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */ 6022 { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */ 6023 { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */ 6024 { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */ 6025 { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */ 6026 } }, 6027 { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) { 6028 { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */ 6029 { RCAR_GP_PIN(3, 7), 24, 3 }, /* SD1_CMD */ 6030 { RCAR_GP_PIN(3, 8), 20, 3 }, /* SD1_DAT0 */ 6031 { RCAR_GP_PIN(3, 9), 16, 3 }, /* SD1_DAT1 */ 6032 { RCAR_GP_PIN(3, 10), 12, 3 }, /* SD1_DAT2 */ 6033 { RCAR_GP_PIN(3, 11), 8, 3 }, /* SD1_DAT3 */ 6034 { RCAR_GP_PIN(4, 0), 4, 3 }, /* SD2_CLK */ 6035 { RCAR_GP_PIN(4, 1), 0, 3 }, /* SD2_CMD */ 6036 } }, 6037 { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) { 6038 { RCAR_GP_PIN(4, 2), 28, 3 }, /* SD2_DAT0 */ 6039 { RCAR_GP_PIN(4, 3), 24, 3 }, /* SD2_DAT1 */ 6040 { RCAR_GP_PIN(4, 4), 20, 3 }, /* SD2_DAT2 */ 6041 { RCAR_GP_PIN(4, 5), 16, 3 }, /* SD2_DAT3 */ 6042 { RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */ 6043 { RCAR_GP_PIN(4, 7), 8, 3 }, /* SD3_CLK */ 6044 { RCAR_GP_PIN(4, 8), 4, 3 }, /* SD3_CMD */ 6045 { RCAR_GP_PIN(4, 9), 0, 3 }, /* SD3_DAT0 */ 6046 } }, 6047 { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) { 6048 { RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */ 6049 { RCAR_GP_PIN(4, 11), 24, 3 }, /* SD3_DAT2 */ 6050 { RCAR_GP_PIN(4, 12), 20, 3 }, /* SD3_DAT3 */ 6051 { RCAR_GP_PIN(4, 13), 16, 3 }, /* SD3_DAT4 */ 6052 { RCAR_GP_PIN(4, 14), 12, 3 }, /* SD3_DAT5 */ 6053 { RCAR_GP_PIN(4, 15), 8, 3 }, /* SD3_DAT6 */ 6054 { RCAR_GP_PIN(4, 16), 4, 3 }, /* SD3_DAT7 */ 6055 { RCAR_GP_PIN(4, 17), 0, 3 }, /* SD3_DS */ 6056 } }, 6057 { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) { 6058 { RCAR_GP_PIN(3, 12), 28, 3 }, /* SD0_CD */ 6059 { RCAR_GP_PIN(3, 13), 24, 3 }, /* SD0_WP */ 6060 { RCAR_GP_PIN(3, 14), 20, 3 }, /* SD1_CD */ 6061 { RCAR_GP_PIN(3, 15), 16, 3 }, /* SD1_WP */ 6062 { RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */ 6063 { RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */ 6064 { RCAR_GP_PIN(5, 2), 4, 3 }, /* TX0 */ 6065 { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */ 6066 } }, 6067 { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) { 6068 { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0 */ 6069 { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */ 6070 { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */ 6071 { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */ 6072 { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1 */ 6073 { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */ 6074 { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */ 6075 { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */ 6076 } }, 6077 { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) { 6078 { RCAR_GP_PIN(5, 12), 28, 3 }, /* HSCK0 */ 6079 { RCAR_GP_PIN(5, 13), 24, 3 }, /* HRX0 */ 6080 { RCAR_GP_PIN(5, 14), 20, 3 }, /* HTX0 */ 6081 { RCAR_GP_PIN(5, 15), 16, 3 }, /* HCTS0 */ 6082 { RCAR_GP_PIN(5, 16), 12, 3 }, /* HRTS0 */ 6083 { RCAR_GP_PIN(5, 17), 8, 3 }, /* MSIOF0_SCK */ 6084 { RCAR_GP_PIN(5, 18), 4, 3 }, /* MSIOF0_SYNC */ 6085 { RCAR_GP_PIN(5, 19), 0, 3 }, /* MSIOF0_SS1 */ 6086 } }, 6087 { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) { 6088 { RCAR_GP_PIN(5, 20), 28, 3 }, /* MSIOF0_TXD */ 6089 { RCAR_GP_PIN(5, 21), 24, 3 }, /* MSIOF0_SS2 */ 6090 { RCAR_GP_PIN(5, 22), 20, 3 }, /* MSIOF0_RXD */ 6091 { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */ 6092 { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */ 6093 { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */ 6094 { PIN_MLB_REF, 4, 3 }, /* MLB_REF */ 6095 { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */ 6096 } }, 6097 { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) { 6098 { RCAR_GP_PIN(6, 1), 28, 3 }, /* SSI_WS01239 */ 6099 { RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */ 6100 { RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */ 6101 { RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */ 6102 { RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK349 */ 6103 { RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS349 */ 6104 { RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */ 6105 { RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */ 6106 } }, 6107 { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) { 6108 { RCAR_GP_PIN(6, 9), 28, 3 }, /* SSI_WS4 */ 6109 { RCAR_GP_PIN(6, 10), 24, 3 }, /* SSI_SDATA4 */ 6110 { RCAR_GP_PIN(6, 11), 20, 3 }, /* SSI_SCK5 */ 6111 { RCAR_GP_PIN(6, 12), 16, 3 }, /* SSI_WS5 */ 6112 { RCAR_GP_PIN(6, 13), 12, 3 }, /* SSI_SDATA5 */ 6113 { RCAR_GP_PIN(6, 14), 8, 3 }, /* SSI_SCK6 */ 6114 { RCAR_GP_PIN(6, 15), 4, 3 }, /* SSI_WS6 */ 6115 { RCAR_GP_PIN(6, 16), 0, 3 }, /* SSI_SDATA6 */ 6116 } }, 6117 { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) { 6118 { RCAR_GP_PIN(6, 17), 28, 3 }, /* SSI_SCK78 */ 6119 { RCAR_GP_PIN(6, 18), 24, 3 }, /* SSI_WS78 */ 6120 { RCAR_GP_PIN(6, 19), 20, 3 }, /* SSI_SDATA7 */ 6121 { RCAR_GP_PIN(6, 20), 16, 3 }, /* SSI_SDATA8 */ 6122 { RCAR_GP_PIN(6, 21), 12, 3 }, /* SSI_SDATA9 */ 6123 { RCAR_GP_PIN(6, 22), 8, 3 }, /* AUDIO_CLKA */ 6124 { RCAR_GP_PIN(6, 23), 4, 3 }, /* AUDIO_CLKB */ 6125 { RCAR_GP_PIN(6, 24), 0, 3 }, /* USB0_PWEN */ 6126 } }, 6127 { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) { 6128 { RCAR_GP_PIN(6, 25), 28, 3 }, /* USB0_OVC */ 6129 { RCAR_GP_PIN(6, 26), 24, 3 }, /* USB1_PWEN */ 6130 { RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */ 6131 { RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */ 6132 { RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */ 6133 { RCAR_GP_PIN(6, 30), 8, 3 }, /* GP6_30 */ 6134 { RCAR_GP_PIN(6, 31), 4, 3 }, /* GP6_31 */ 6135 } }, 6136 { }, 6137 }; 6138 6139 enum ioctrl_regs { 6140 POCCTRL, 6141 TDSELCTRL, 6142 }; 6143 6144 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { 6145 [POCCTRL] = { 0xe6060380, }, 6146 [TDSELCTRL] = { 0xe60603c0, }, 6147 { /* sentinel */ }, 6148 }; 6149 6150 static int r8a77965_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl) 6151 { 6152 int bit = -EINVAL; 6153 6154 *pocctrl = pinmux_ioctrl_regs[POCCTRL].reg; 6155 6156 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11)) 6157 bit = pin & 0x1f; 6158 6159 if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17)) 6160 bit = (pin & 0x1f) + 12; 6161 6162 return bit; 6163 } 6164 6165 static const struct pinmux_bias_reg pinmux_bias_regs[] = { 6166 { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) { 6167 [ 0] = PIN_QSPI0_SPCLK, /* QSPI0_SPCLK */ 6168 [ 1] = PIN_QSPI0_MOSI_IO0, /* QSPI0_MOSI_IO0 */ 6169 [ 2] = PIN_QSPI0_MISO_IO1, /* QSPI0_MISO_IO1 */ 6170 [ 3] = PIN_QSPI0_IO2, /* QSPI0_IO2 */ 6171 [ 4] = PIN_QSPI0_IO3, /* QSPI0_IO3 */ 6172 [ 5] = PIN_QSPI0_SSL, /* QSPI0_SSL */ 6173 [ 6] = PIN_QSPI1_SPCLK, /* QSPI1_SPCLK */ 6174 [ 7] = PIN_QSPI1_MOSI_IO0, /* QSPI1_MOSI_IO0 */ 6175 [ 8] = PIN_QSPI1_MISO_IO1, /* QSPI1_MISO_IO1 */ 6176 [ 9] = PIN_QSPI1_IO2, /* QSPI1_IO2 */ 6177 [10] = PIN_QSPI1_IO3, /* QSPI1_IO3 */ 6178 [11] = PIN_QSPI1_SSL, /* QSPI1_SSL */ 6179 [12] = PIN_RPC_INT_N, /* RPC_INT# */ 6180 [13] = PIN_RPC_WP_N, /* RPC_WP# */ 6181 [14] = PIN_RPC_RESET_N, /* RPC_RESET# */ 6182 [15] = PIN_AVB_RX_CTL, /* AVB_RX_CTL */ 6183 [16] = PIN_AVB_RXC, /* AVB_RXC */ 6184 [17] = PIN_AVB_RD0, /* AVB_RD0 */ 6185 [18] = PIN_AVB_RD1, /* AVB_RD1 */ 6186 [19] = PIN_AVB_RD2, /* AVB_RD2 */ 6187 [20] = PIN_AVB_RD3, /* AVB_RD3 */ 6188 [21] = PIN_AVB_TX_CTL, /* AVB_TX_CTL */ 6189 [22] = PIN_AVB_TXC, /* AVB_TXC */ 6190 [23] = PIN_AVB_TD0, /* AVB_TD0 */ 6191 [24] = PIN_AVB_TD1, /* AVB_TD1 */ 6192 [25] = PIN_AVB_TD2, /* AVB_TD2 */ 6193 [26] = PIN_AVB_TD3, /* AVB_TD3 */ 6194 [27] = PIN_AVB_TXCREFCLK, /* AVB_TXCREFCLK */ 6195 [28] = PIN_AVB_MDIO, /* AVB_MDIO */ 6196 [29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */ 6197 [30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */ 6198 [31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */ 6199 } }, 6200 { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) { 6201 [ 0] = RCAR_GP_PIN(2, 12), /* AVB_LINK */ 6202 [ 1] = RCAR_GP_PIN(2, 13), /* AVB_AVTP_MATCH_A */ 6203 [ 2] = RCAR_GP_PIN(2, 14), /* AVB_AVTP_CAPTURE_A */ 6204 [ 3] = RCAR_GP_PIN(2, 0), /* IRQ0 */ 6205 [ 4] = RCAR_GP_PIN(2, 1), /* IRQ1 */ 6206 [ 5] = RCAR_GP_PIN(2, 2), /* IRQ2 */ 6207 [ 6] = RCAR_GP_PIN(2, 3), /* IRQ3 */ 6208 [ 7] = RCAR_GP_PIN(2, 4), /* IRQ4 */ 6209 [ 8] = RCAR_GP_PIN(2, 5), /* IRQ5 */ 6210 [ 9] = RCAR_GP_PIN(2, 6), /* PWM0 */ 6211 [10] = RCAR_GP_PIN(2, 7), /* PWM1_A */ 6212 [11] = RCAR_GP_PIN(2, 8), /* PWM2_A */ 6213 [12] = RCAR_GP_PIN(1, 0), /* A0 */ 6214 [13] = RCAR_GP_PIN(1, 1), /* A1 */ 6215 [14] = RCAR_GP_PIN(1, 2), /* A2 */ 6216 [15] = RCAR_GP_PIN(1, 3), /* A3 */ 6217 [16] = RCAR_GP_PIN(1, 4), /* A4 */ 6218 [17] = RCAR_GP_PIN(1, 5), /* A5 */ 6219 [18] = RCAR_GP_PIN(1, 6), /* A6 */ 6220 [19] = RCAR_GP_PIN(1, 7), /* A7 */ 6221 [20] = RCAR_GP_PIN(1, 8), /* A8 */ 6222 [21] = RCAR_GP_PIN(1, 9), /* A9 */ 6223 [22] = RCAR_GP_PIN(1, 10), /* A10 */ 6224 [23] = RCAR_GP_PIN(1, 11), /* A11 */ 6225 [24] = RCAR_GP_PIN(1, 12), /* A12 */ 6226 [25] = RCAR_GP_PIN(1, 13), /* A13 */ 6227 [26] = RCAR_GP_PIN(1, 14), /* A14 */ 6228 [27] = RCAR_GP_PIN(1, 15), /* A15 */ 6229 [28] = RCAR_GP_PIN(1, 16), /* A16 */ 6230 [29] = RCAR_GP_PIN(1, 17), /* A17 */ 6231 [30] = RCAR_GP_PIN(1, 18), /* A18 */ 6232 [31] = RCAR_GP_PIN(1, 19), /* A19 */ 6233 } }, 6234 { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) { 6235 [ 0] = RCAR_GP_PIN(1, 28), /* CLKOUT */ 6236 [ 1] = RCAR_GP_PIN(1, 20), /* CS0_N */ 6237 [ 2] = RCAR_GP_PIN(1, 21), /* CS1_N */ 6238 [ 3] = RCAR_GP_PIN(1, 22), /* BS_N */ 6239 [ 4] = RCAR_GP_PIN(1, 23), /* RD_N */ 6240 [ 5] = RCAR_GP_PIN(1, 24), /* RD_WR_N */ 6241 [ 6] = RCAR_GP_PIN(1, 25), /* WE0_N */ 6242 [ 7] = RCAR_GP_PIN(1, 26), /* WE1_N */ 6243 [ 8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */ 6244 [ 9] = PIN_PRESETOUT_N, /* PRESETOUT# */ 6245 [10] = RCAR_GP_PIN(0, 0), /* D0 */ 6246 [11] = RCAR_GP_PIN(0, 1), /* D1 */ 6247 [12] = RCAR_GP_PIN(0, 2), /* D2 */ 6248 [13] = RCAR_GP_PIN(0, 3), /* D3 */ 6249 [14] = RCAR_GP_PIN(0, 4), /* D4 */ 6250 [15] = RCAR_GP_PIN(0, 5), /* D5 */ 6251 [16] = RCAR_GP_PIN(0, 6), /* D6 */ 6252 [17] = RCAR_GP_PIN(0, 7), /* D7 */ 6253 [18] = RCAR_GP_PIN(0, 8), /* D8 */ 6254 [19] = RCAR_GP_PIN(0, 9), /* D9 */ 6255 [20] = RCAR_GP_PIN(0, 10), /* D10 */ 6256 [21] = RCAR_GP_PIN(0, 11), /* D11 */ 6257 [22] = RCAR_GP_PIN(0, 12), /* D12 */ 6258 [23] = RCAR_GP_PIN(0, 13), /* D13 */ 6259 [24] = RCAR_GP_PIN(0, 14), /* D14 */ 6260 [25] = RCAR_GP_PIN(0, 15), /* D15 */ 6261 [26] = RCAR_GP_PIN(7, 0), /* AVS1 */ 6262 [27] = RCAR_GP_PIN(7, 1), /* AVS2 */ 6263 [28] = RCAR_GP_PIN(7, 2), /* GP7_02 */ 6264 [29] = RCAR_GP_PIN(7, 3), /* GP7_03 */ 6265 [30] = PIN_DU_DOTCLKIN0, /* DU_DOTCLKIN0 */ 6266 [31] = PIN_DU_DOTCLKIN1, /* DU_DOTCLKIN1 */ 6267 } }, 6268 { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) { 6269 [ 0] = SH_PFC_PIN_NONE, 6270 [ 1] = PIN_DU_DOTCLKIN3, /* DU_DOTCLKIN3 */ 6271 [ 2] = PIN_FSCLKST, /* FSCLKST */ 6272 [ 3] = PIN_EXTALR, /* EXTALR*/ 6273 [ 4] = PIN_TRST_N, /* TRST# */ 6274 [ 5] = PIN_TCK, /* TCK */ 6275 [ 6] = PIN_TMS, /* TMS */ 6276 [ 7] = PIN_TDI, /* TDI */ 6277 [ 8] = SH_PFC_PIN_NONE, 6278 [ 9] = PIN_ASEBRK, /* ASEBRK */ 6279 [10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */ 6280 [11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */ 6281 [12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */ 6282 [13] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */ 6283 [14] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */ 6284 [15] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */ 6285 [16] = RCAR_GP_PIN(3, 6), /* SD1_CLK */ 6286 [17] = RCAR_GP_PIN(3, 7), /* SD1_CMD */ 6287 [18] = RCAR_GP_PIN(3, 8), /* SD1_DAT0 */ 6288 [19] = RCAR_GP_PIN(3, 9), /* SD1_DAT1 */ 6289 [20] = RCAR_GP_PIN(3, 10), /* SD1_DAT2 */ 6290 [21] = RCAR_GP_PIN(3, 11), /* SD1_DAT3 */ 6291 [22] = RCAR_GP_PIN(4, 0), /* SD2_CLK */ 6292 [23] = RCAR_GP_PIN(4, 1), /* SD2_CMD */ 6293 [24] = RCAR_GP_PIN(4, 2), /* SD2_DAT0 */ 6294 [25] = RCAR_GP_PIN(4, 3), /* SD2_DAT1 */ 6295 [26] = RCAR_GP_PIN(4, 4), /* SD2_DAT2 */ 6296 [27] = RCAR_GP_PIN(4, 5), /* SD2_DAT3 */ 6297 [28] = RCAR_GP_PIN(4, 6), /* SD2_DS */ 6298 [29] = RCAR_GP_PIN(4, 7), /* SD3_CLK */ 6299 [30] = RCAR_GP_PIN(4, 8), /* SD3_CMD */ 6300 [31] = RCAR_GP_PIN(4, 9), /* SD3_DAT0 */ 6301 } }, 6302 { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) { 6303 [ 0] = RCAR_GP_PIN(4, 10), /* SD3_DAT1 */ 6304 [ 1] = RCAR_GP_PIN(4, 11), /* SD3_DAT2 */ 6305 [ 2] = RCAR_GP_PIN(4, 12), /* SD3_DAT3 */ 6306 [ 3] = RCAR_GP_PIN(4, 13), /* SD3_DAT4 */ 6307 [ 4] = RCAR_GP_PIN(4, 14), /* SD3_DAT5 */ 6308 [ 5] = RCAR_GP_PIN(4, 15), /* SD3_DAT6 */ 6309 [ 6] = RCAR_GP_PIN(4, 16), /* SD3_DAT7 */ 6310 [ 7] = RCAR_GP_PIN(4, 17), /* SD3_DS */ 6311 [ 8] = RCAR_GP_PIN(3, 12), /* SD0_CD */ 6312 [ 9] = RCAR_GP_PIN(3, 13), /* SD0_WP */ 6313 [10] = RCAR_GP_PIN(3, 14), /* SD1_CD */ 6314 [11] = RCAR_GP_PIN(3, 15), /* SD1_WP */ 6315 [12] = RCAR_GP_PIN(5, 0), /* SCK0 */ 6316 [13] = RCAR_GP_PIN(5, 1), /* RX0 */ 6317 [14] = RCAR_GP_PIN(5, 2), /* TX0 */ 6318 [15] = RCAR_GP_PIN(5, 3), /* CTS0_N */ 6319 [16] = RCAR_GP_PIN(5, 4), /* RTS0_N */ 6320 [17] = RCAR_GP_PIN(5, 5), /* RX1_A */ 6321 [18] = RCAR_GP_PIN(5, 6), /* TX1_A */ 6322 [19] = RCAR_GP_PIN(5, 7), /* CTS1_N */ 6323 [20] = RCAR_GP_PIN(5, 8), /* RTS1_N */ 6324 [21] = RCAR_GP_PIN(5, 9), /* SCK2 */ 6325 [22] = RCAR_GP_PIN(5, 10), /* TX2_A */ 6326 [23] = RCAR_GP_PIN(5, 11), /* RX2_A */ 6327 [24] = RCAR_GP_PIN(5, 12), /* HSCK0 */ 6328 [25] = RCAR_GP_PIN(5, 13), /* HRX0 */ 6329 [26] = RCAR_GP_PIN(5, 14), /* HTX0 */ 6330 [27] = RCAR_GP_PIN(5, 15), /* HCTS0_N */ 6331 [28] = RCAR_GP_PIN(5, 16), /* HRTS0_N */ 6332 [29] = RCAR_GP_PIN(5, 17), /* MSIOF0_SCK */ 6333 [30] = RCAR_GP_PIN(5, 18), /* MSIOF0_SYNC */ 6334 [31] = RCAR_GP_PIN(5, 19), /* MSIOF0_SS1 */ 6335 } }, 6336 { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) { 6337 [ 0] = RCAR_GP_PIN(5, 20), /* MSIOF0_TXD */ 6338 [ 1] = RCAR_GP_PIN(5, 21), /* MSIOF0_SS2 */ 6339 [ 2] = RCAR_GP_PIN(5, 22), /* MSIOF0_RXD */ 6340 [ 3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */ 6341 [ 4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */ 6342 [ 5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */ 6343 [ 6] = PIN_MLB_REF, /* MLB_REF */ 6344 [ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */ 6345 [ 8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */ 6346 [ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */ 6347 [10] = RCAR_GP_PIN(6, 3), /* SSI_SDATA1_A */ 6348 [11] = RCAR_GP_PIN(6, 4), /* SSI_SDATA2_A */ 6349 [12] = RCAR_GP_PIN(6, 5), /* SSI_SCK349 */ 6350 [13] = RCAR_GP_PIN(6, 6), /* SSI_WS349 */ 6351 [14] = RCAR_GP_PIN(6, 7), /* SSI_SDATA3 */ 6352 [15] = RCAR_GP_PIN(6, 8), /* SSI_SCK4 */ 6353 [16] = RCAR_GP_PIN(6, 9), /* SSI_WS4 */ 6354 [17] = RCAR_GP_PIN(6, 10), /* SSI_SDATA4 */ 6355 [18] = RCAR_GP_PIN(6, 11), /* SSI_SCK5 */ 6356 [19] = RCAR_GP_PIN(6, 12), /* SSI_WS5 */ 6357 [20] = RCAR_GP_PIN(6, 13), /* SSI_SDATA5 */ 6358 [21] = RCAR_GP_PIN(6, 14), /* SSI_SCK6 */ 6359 [22] = RCAR_GP_PIN(6, 15), /* SSI_WS6 */ 6360 [23] = RCAR_GP_PIN(6, 16), /* SSI_SDATA6 */ 6361 [24] = RCAR_GP_PIN(6, 17), /* SSI_SCK78 */ 6362 [25] = RCAR_GP_PIN(6, 18), /* SSI_WS78 */ 6363 [26] = RCAR_GP_PIN(6, 19), /* SSI_SDATA7 */ 6364 [27] = RCAR_GP_PIN(6, 20), /* SSI_SDATA8 */ 6365 [28] = RCAR_GP_PIN(6, 21), /* SSI_SDATA9_A */ 6366 [29] = RCAR_GP_PIN(6, 22), /* AUDIO_CLKA_A */ 6367 [30] = RCAR_GP_PIN(6, 23), /* AUDIO_CLKB_B */ 6368 [31] = RCAR_GP_PIN(6, 24), /* USB0_PWEN */ 6369 } }, 6370 { PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) { 6371 [ 0] = RCAR_GP_PIN(6, 25), /* USB0_OVC */ 6372 [ 1] = RCAR_GP_PIN(6, 26), /* USB1_PWEN */ 6373 [ 2] = RCAR_GP_PIN(6, 27), /* USB1_OVC */ 6374 [ 3] = RCAR_GP_PIN(6, 28), /* USB30_PWEN */ 6375 [ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */ 6376 [ 5] = RCAR_GP_PIN(6, 30), /* GP6_30 */ 6377 [ 6] = RCAR_GP_PIN(6, 31), /* GP6_31 */ 6378 [ 7] = SH_PFC_PIN_NONE, 6379 [ 8] = SH_PFC_PIN_NONE, 6380 [ 9] = SH_PFC_PIN_NONE, 6381 [10] = SH_PFC_PIN_NONE, 6382 [11] = SH_PFC_PIN_NONE, 6383 [12] = SH_PFC_PIN_NONE, 6384 [13] = SH_PFC_PIN_NONE, 6385 [14] = SH_PFC_PIN_NONE, 6386 [15] = SH_PFC_PIN_NONE, 6387 [16] = SH_PFC_PIN_NONE, 6388 [17] = SH_PFC_PIN_NONE, 6389 [18] = SH_PFC_PIN_NONE, 6390 [19] = SH_PFC_PIN_NONE, 6391 [20] = SH_PFC_PIN_NONE, 6392 [21] = SH_PFC_PIN_NONE, 6393 [22] = SH_PFC_PIN_NONE, 6394 [23] = SH_PFC_PIN_NONE, 6395 [24] = SH_PFC_PIN_NONE, 6396 [25] = SH_PFC_PIN_NONE, 6397 [26] = SH_PFC_PIN_NONE, 6398 [27] = SH_PFC_PIN_NONE, 6399 [28] = SH_PFC_PIN_NONE, 6400 [29] = SH_PFC_PIN_NONE, 6401 [30] = SH_PFC_PIN_NONE, 6402 [31] = SH_PFC_PIN_NONE, 6403 } }, 6404 { /* sentinel */ }, 6405 }; 6406 6407 static const struct sh_pfc_soc_operations r8a77965_pinmux_ops = { 6408 .pin_to_pocctrl = r8a77965_pin_to_pocctrl, 6409 .get_bias = rcar_pinmux_get_bias, 6410 .set_bias = rcar_pinmux_set_bias, 6411 }; 6412 6413 #ifdef CONFIG_PINCTRL_PFC_R8A774B1 6414 const struct sh_pfc_soc_info r8a774b1_pinmux_info = { 6415 .name = "r8a774b1_pfc", 6416 .ops = &r8a77965_pinmux_ops, 6417 .unlock_reg = 0xe6060000, /* PMMR */ 6418 6419 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 6420 6421 .pins = pinmux_pins, 6422 .nr_pins = ARRAY_SIZE(pinmux_pins), 6423 .groups = pinmux_groups.common, 6424 .nr_groups = ARRAY_SIZE(pinmux_groups.common), 6425 .functions = pinmux_functions.common, 6426 .nr_functions = ARRAY_SIZE(pinmux_functions.common), 6427 6428 .cfg_regs = pinmux_config_regs, 6429 .drive_regs = pinmux_drive_regs, 6430 .bias_regs = pinmux_bias_regs, 6431 .ioctrl_regs = pinmux_ioctrl_regs, 6432 6433 .pinmux_data = pinmux_data, 6434 .pinmux_data_size = ARRAY_SIZE(pinmux_data), 6435 }; 6436 #endif 6437 6438 #ifdef CONFIG_PINCTRL_PFC_R8A77965 6439 const struct sh_pfc_soc_info r8a77965_pinmux_info = { 6440 .name = "r8a77965_pfc", 6441 .ops = &r8a77965_pinmux_ops, 6442 .unlock_reg = 0xe6060000, /* PMMR */ 6443 6444 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 6445 6446 .pins = pinmux_pins, 6447 .nr_pins = ARRAY_SIZE(pinmux_pins), 6448 .groups = pinmux_groups.common, 6449 .nr_groups = ARRAY_SIZE(pinmux_groups.common) + 6450 ARRAY_SIZE(pinmux_groups.automotive), 6451 .functions = pinmux_functions.common, 6452 .nr_functions = ARRAY_SIZE(pinmux_functions.common) + 6453 ARRAY_SIZE(pinmux_functions.automotive), 6454 6455 .cfg_regs = pinmux_config_regs, 6456 .drive_regs = pinmux_drive_regs, 6457 .bias_regs = pinmux_bias_regs, 6458 .ioctrl_regs = pinmux_ioctrl_regs, 6459 6460 .pinmux_data = pinmux_data, 6461 .pinmux_data_size = ARRAY_SIZE(pinmux_data), 6462 }; 6463 #endif 6464