1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * R8A7796 (R-Car M3-W/W+) support - PFC hardware block.
4  *
5  * Copyright (C) 2016-2019 Renesas Electronics Corp.
6  *
7  * This file is based on the drivers/pinctrl/renesas/pfc-r8a7795.c
8  *
9  * R-Car Gen3 processor support - PFC hardware block.
10  *
11  * Copyright (C) 2015  Renesas Electronics Corporation
12  */
13 
14 #include <linux/errno.h>
15 #include <linux/kernel.h>
16 
17 #include "core.h"
18 #include "sh_pfc.h"
19 
20 #define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN)
21 
22 #define CPU_ALL_GP(fn, sfx)						\
23 	PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS),	\
24 	PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS),	\
25 	PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS),	\
26 	PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE),	\
27 	PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS),	\
28 	PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS),	\
29 	PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS),	\
30 	PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS),	\
31 	PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE),	\
32 	PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS),	\
33 	PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS),	\
34 	PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
35 
36 #define CPU_ALL_NOGP(fn)						\
37 	PIN_NOGP_CFG(ASEBRK, "ASEBRK", fn, CFG_FLAGS),			\
38 	PIN_NOGP_CFG(AVB_MDIO, "AVB_MDIO", fn, CFG_FLAGS),		\
39 	PIN_NOGP_CFG(AVB_RD0, "AVB_RD0", fn, CFG_FLAGS),		\
40 	PIN_NOGP_CFG(AVB_RD1, "AVB_RD1", fn, CFG_FLAGS),		\
41 	PIN_NOGP_CFG(AVB_RD2, "AVB_RD2", fn, CFG_FLAGS),		\
42 	PIN_NOGP_CFG(AVB_RD3, "AVB_RD3", fn, CFG_FLAGS),		\
43 	PIN_NOGP_CFG(AVB_RXC, "AVB_RXC", fn, CFG_FLAGS),		\
44 	PIN_NOGP_CFG(AVB_RX_CTL, "AVB_RX_CTL", fn, CFG_FLAGS),		\
45 	PIN_NOGP_CFG(AVB_TD0, "AVB_TD0", fn, CFG_FLAGS),		\
46 	PIN_NOGP_CFG(AVB_TD1, "AVB_TD1", fn, CFG_FLAGS),		\
47 	PIN_NOGP_CFG(AVB_TD2, "AVB_TD2", fn, CFG_FLAGS),		\
48 	PIN_NOGP_CFG(AVB_TD3, "AVB_TD3", fn, CFG_FLAGS),		\
49 	PIN_NOGP_CFG(AVB_TXC, "AVB_TXC", fn, CFG_FLAGS),		\
50 	PIN_NOGP_CFG(AVB_TXCREFCLK, "AVB_TXCREFCLK", fn, CFG_FLAGS),	\
51 	PIN_NOGP_CFG(AVB_TX_CTL, "AVB_TX_CTL", fn, CFG_FLAGS),		\
52 	PIN_NOGP_CFG(DU_DOTCLKIN0, "DU_DOTCLKIN0", fn, CFG_FLAGS),	\
53 	PIN_NOGP_CFG(DU_DOTCLKIN1, "DU_DOTCLKIN1", fn, CFG_FLAGS),	\
54 	PIN_NOGP_CFG(DU_DOTCLKIN2, "DU_DOTCLKIN2", fn, CFG_FLAGS),	\
55 	PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),\
56 	PIN_NOGP_CFG(FSCLKST, "FSCLKST", fn, CFG_FLAGS),		\
57 	PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS),		\
58 	PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, CFG_FLAGS),		\
59 	PIN_NOGP_CFG(QSPI0_IO2, "QSPI0_IO2", fn, CFG_FLAGS),		\
60 	PIN_NOGP_CFG(QSPI0_IO3, "QSPI0_IO3", fn, CFG_FLAGS),		\
61 	PIN_NOGP_CFG(QSPI0_MISO_IO1, "QSPI0_MISO_IO1", fn, CFG_FLAGS),	\
62 	PIN_NOGP_CFG(QSPI0_MOSI_IO0, "QSPI0_MOSI_IO0", fn, CFG_FLAGS),	\
63 	PIN_NOGP_CFG(QSPI0_SPCLK, "QSPI0_SPCLK", fn, CFG_FLAGS),	\
64 	PIN_NOGP_CFG(QSPI0_SSL, "QSPI0_SSL", fn, CFG_FLAGS),		\
65 	PIN_NOGP_CFG(QSPI1_IO2, "QSPI1_IO2", fn, CFG_FLAGS),		\
66 	PIN_NOGP_CFG(QSPI1_IO3, "QSPI1_IO3", fn, CFG_FLAGS),		\
67 	PIN_NOGP_CFG(QSPI1_MISO_IO1, "QSPI1_MISO_IO1", fn, CFG_FLAGS),	\
68 	PIN_NOGP_CFG(QSPI1_MOSI_IO0, "QSPI1_MOSI_IO0", fn, CFG_FLAGS),	\
69 	PIN_NOGP_CFG(QSPI1_SPCLK, "QSPI1_SPCLK", fn, CFG_FLAGS),	\
70 	PIN_NOGP_CFG(QSPI1_SSL, "QSPI1_SSL", fn, CFG_FLAGS),		\
71 	PIN_NOGP_CFG(RPC_INT_N, "RPC_INT#", fn, CFG_FLAGS),		\
72 	PIN_NOGP_CFG(RPC_RESET_N, "RPC_RESET#", fn, CFG_FLAGS),		\
73 	PIN_NOGP_CFG(RPC_WP_N, "RPC_WP#", fn, CFG_FLAGS),		\
74 	PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),	\
75 	PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),	\
76 	PIN_NOGP_CFG(TDO, "TDO", fn, SH_PFC_PIN_CFG_DRIVE_STRENGTH),	\
77 	PIN_NOGP_CFG(TMS, "TMS", fn, CFG_FLAGS),			\
78 	PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN)
79 
80 /*
81  * F_() : just information
82  * FM() : macro for FN_xxx / xxx_MARK
83  */
84 
85 /* GPSR0 */
86 #define GPSR0_15	F_(D15,			IP7_11_8)
87 #define GPSR0_14	F_(D14,			IP7_7_4)
88 #define GPSR0_13	F_(D13,			IP7_3_0)
89 #define GPSR0_12	F_(D12,			IP6_31_28)
90 #define GPSR0_11	F_(D11,			IP6_27_24)
91 #define GPSR0_10	F_(D10,			IP6_23_20)
92 #define GPSR0_9		F_(D9,			IP6_19_16)
93 #define GPSR0_8		F_(D8,			IP6_15_12)
94 #define GPSR0_7		F_(D7,			IP6_11_8)
95 #define GPSR0_6		F_(D6,			IP6_7_4)
96 #define GPSR0_5		F_(D5,			IP6_3_0)
97 #define GPSR0_4		F_(D4,			IP5_31_28)
98 #define GPSR0_3		F_(D3,			IP5_27_24)
99 #define GPSR0_2		F_(D2,			IP5_23_20)
100 #define GPSR0_1		F_(D1,			IP5_19_16)
101 #define GPSR0_0		F_(D0,			IP5_15_12)
102 
103 /* GPSR1 */
104 #define GPSR1_28	FM(CLKOUT)
105 #define GPSR1_27	F_(EX_WAIT0_A,		IP5_11_8)
106 #define GPSR1_26	F_(WE1_N,		IP5_7_4)
107 #define GPSR1_25	F_(WE0_N,		IP5_3_0)
108 #define GPSR1_24	F_(RD_WR_N,		IP4_31_28)
109 #define GPSR1_23	F_(RD_N,		IP4_27_24)
110 #define GPSR1_22	F_(BS_N,		IP4_23_20)
111 #define GPSR1_21	F_(CS1_N,		IP4_19_16)
112 #define GPSR1_20	F_(CS0_N,		IP4_15_12)
113 #define GPSR1_19	F_(A19,			IP4_11_8)
114 #define GPSR1_18	F_(A18,			IP4_7_4)
115 #define GPSR1_17	F_(A17,			IP4_3_0)
116 #define GPSR1_16	F_(A16,			IP3_31_28)
117 #define GPSR1_15	F_(A15,			IP3_27_24)
118 #define GPSR1_14	F_(A14,			IP3_23_20)
119 #define GPSR1_13	F_(A13,			IP3_19_16)
120 #define GPSR1_12	F_(A12,			IP3_15_12)
121 #define GPSR1_11	F_(A11,			IP3_11_8)
122 #define GPSR1_10	F_(A10,			IP3_7_4)
123 #define GPSR1_9		F_(A9,			IP3_3_0)
124 #define GPSR1_8		F_(A8,			IP2_31_28)
125 #define GPSR1_7		F_(A7,			IP2_27_24)
126 #define GPSR1_6		F_(A6,			IP2_23_20)
127 #define GPSR1_5		F_(A5,			IP2_19_16)
128 #define GPSR1_4		F_(A4,			IP2_15_12)
129 #define GPSR1_3		F_(A3,			IP2_11_8)
130 #define GPSR1_2		F_(A2,			IP2_7_4)
131 #define GPSR1_1		F_(A1,			IP2_3_0)
132 #define GPSR1_0		F_(A0,			IP1_31_28)
133 
134 /* GPSR2 */
135 #define GPSR2_14	F_(AVB_AVTP_CAPTURE_A,	IP0_23_20)
136 #define GPSR2_13	F_(AVB_AVTP_MATCH_A,	IP0_19_16)
137 #define GPSR2_12	F_(AVB_LINK,		IP0_15_12)
138 #define GPSR2_11	F_(AVB_PHY_INT,		IP0_11_8)
139 #define GPSR2_10	F_(AVB_MAGIC,		IP0_7_4)
140 #define GPSR2_9		F_(AVB_MDC,		IP0_3_0)
141 #define GPSR2_8		F_(PWM2_A,		IP1_27_24)
142 #define GPSR2_7		F_(PWM1_A,		IP1_23_20)
143 #define GPSR2_6		F_(PWM0,		IP1_19_16)
144 #define GPSR2_5		F_(IRQ5,		IP1_15_12)
145 #define GPSR2_4		F_(IRQ4,		IP1_11_8)
146 #define GPSR2_3		F_(IRQ3,		IP1_7_4)
147 #define GPSR2_2		F_(IRQ2,		IP1_3_0)
148 #define GPSR2_1		F_(IRQ1,		IP0_31_28)
149 #define GPSR2_0		F_(IRQ0,		IP0_27_24)
150 
151 /* GPSR3 */
152 #define GPSR3_15	F_(SD1_WP,		IP11_23_20)
153 #define GPSR3_14	F_(SD1_CD,		IP11_19_16)
154 #define GPSR3_13	F_(SD0_WP,		IP11_15_12)
155 #define GPSR3_12	F_(SD0_CD,		IP11_11_8)
156 #define GPSR3_11	F_(SD1_DAT3,		IP8_31_28)
157 #define GPSR3_10	F_(SD1_DAT2,		IP8_27_24)
158 #define GPSR3_9		F_(SD1_DAT1,		IP8_23_20)
159 #define GPSR3_8		F_(SD1_DAT0,		IP8_19_16)
160 #define GPSR3_7		F_(SD1_CMD,		IP8_15_12)
161 #define GPSR3_6		F_(SD1_CLK,		IP8_11_8)
162 #define GPSR3_5		F_(SD0_DAT3,		IP8_7_4)
163 #define GPSR3_4		F_(SD0_DAT2,		IP8_3_0)
164 #define GPSR3_3		F_(SD0_DAT1,		IP7_31_28)
165 #define GPSR3_2		F_(SD0_DAT0,		IP7_27_24)
166 #define GPSR3_1		F_(SD0_CMD,		IP7_23_20)
167 #define GPSR3_0		F_(SD0_CLK,		IP7_19_16)
168 
169 /* GPSR4 */
170 #define GPSR4_17	F_(SD3_DS,		IP11_7_4)
171 #define GPSR4_16	F_(SD3_DAT7,		IP11_3_0)
172 #define GPSR4_15	F_(SD3_DAT6,		IP10_31_28)
173 #define GPSR4_14	F_(SD3_DAT5,		IP10_27_24)
174 #define GPSR4_13	F_(SD3_DAT4,		IP10_23_20)
175 #define GPSR4_12	F_(SD3_DAT3,		IP10_19_16)
176 #define GPSR4_11	F_(SD3_DAT2,		IP10_15_12)
177 #define GPSR4_10	F_(SD3_DAT1,		IP10_11_8)
178 #define GPSR4_9		F_(SD3_DAT0,		IP10_7_4)
179 #define GPSR4_8		F_(SD3_CMD,		IP10_3_0)
180 #define GPSR4_7		F_(SD3_CLK,		IP9_31_28)
181 #define GPSR4_6		F_(SD2_DS,		IP9_27_24)
182 #define GPSR4_5		F_(SD2_DAT3,		IP9_23_20)
183 #define GPSR4_4		F_(SD2_DAT2,		IP9_19_16)
184 #define GPSR4_3		F_(SD2_DAT1,		IP9_15_12)
185 #define GPSR4_2		F_(SD2_DAT0,		IP9_11_8)
186 #define GPSR4_1		F_(SD2_CMD,		IP9_7_4)
187 #define GPSR4_0		F_(SD2_CLK,		IP9_3_0)
188 
189 /* GPSR5 */
190 #define GPSR5_25	F_(MLB_DAT,		IP14_19_16)
191 #define GPSR5_24	F_(MLB_SIG,		IP14_15_12)
192 #define GPSR5_23	F_(MLB_CLK,		IP14_11_8)
193 #define GPSR5_22	FM(MSIOF0_RXD)
194 #define GPSR5_21	F_(MSIOF0_SS2,		IP14_7_4)
195 #define GPSR5_20	FM(MSIOF0_TXD)
196 #define GPSR5_19	F_(MSIOF0_SS1,		IP14_3_0)
197 #define GPSR5_18	F_(MSIOF0_SYNC,		IP13_31_28)
198 #define GPSR5_17	FM(MSIOF0_SCK)
199 #define GPSR5_16	F_(HRTS0_N,		IP13_27_24)
200 #define GPSR5_15	F_(HCTS0_N,		IP13_23_20)
201 #define GPSR5_14	F_(HTX0,		IP13_19_16)
202 #define GPSR5_13	F_(HRX0,		IP13_15_12)
203 #define GPSR5_12	F_(HSCK0,		IP13_11_8)
204 #define GPSR5_11	F_(RX2_A,		IP13_7_4)
205 #define GPSR5_10	F_(TX2_A,		IP13_3_0)
206 #define GPSR5_9		F_(SCK2,		IP12_31_28)
207 #define GPSR5_8		F_(RTS1_N,		IP12_27_24)
208 #define GPSR5_7		F_(CTS1_N,		IP12_23_20)
209 #define GPSR5_6		F_(TX1_A,		IP12_19_16)
210 #define GPSR5_5		F_(RX1_A,		IP12_15_12)
211 #define GPSR5_4		F_(RTS0_N,		IP12_11_8)
212 #define GPSR5_3		F_(CTS0_N,		IP12_7_4)
213 #define GPSR5_2		F_(TX0,			IP12_3_0)
214 #define GPSR5_1		F_(RX0,			IP11_31_28)
215 #define GPSR5_0		F_(SCK0,		IP11_27_24)
216 
217 /* GPSR6 */
218 #define GPSR6_31	F_(GP6_31,		IP18_7_4)
219 #define GPSR6_30	F_(GP6_30,		IP18_3_0)
220 #define GPSR6_29	F_(USB30_OVC,		IP17_31_28)
221 #define GPSR6_28	F_(USB30_PWEN,		IP17_27_24)
222 #define GPSR6_27	F_(USB1_OVC,		IP17_23_20)
223 #define GPSR6_26	F_(USB1_PWEN,		IP17_19_16)
224 #define GPSR6_25	F_(USB0_OVC,		IP17_15_12)
225 #define GPSR6_24	F_(USB0_PWEN,		IP17_11_8)
226 #define GPSR6_23	F_(AUDIO_CLKB_B,	IP17_7_4)
227 #define GPSR6_22	F_(AUDIO_CLKA_A,	IP17_3_0)
228 #define GPSR6_21	F_(SSI_SDATA9_A,	IP16_31_28)
229 #define GPSR6_20	F_(SSI_SDATA8,		IP16_27_24)
230 #define GPSR6_19	F_(SSI_SDATA7,		IP16_23_20)
231 #define GPSR6_18	F_(SSI_WS78,		IP16_19_16)
232 #define GPSR6_17	F_(SSI_SCK78,		IP16_15_12)
233 #define GPSR6_16	F_(SSI_SDATA6,		IP16_11_8)
234 #define GPSR6_15	F_(SSI_WS6,		IP16_7_4)
235 #define GPSR6_14	F_(SSI_SCK6,		IP16_3_0)
236 #define GPSR6_13	FM(SSI_SDATA5)
237 #define GPSR6_12	FM(SSI_WS5)
238 #define GPSR6_11	FM(SSI_SCK5)
239 #define GPSR6_10	F_(SSI_SDATA4,		IP15_31_28)
240 #define GPSR6_9		F_(SSI_WS4,		IP15_27_24)
241 #define GPSR6_8		F_(SSI_SCK4,		IP15_23_20)
242 #define GPSR6_7		F_(SSI_SDATA3,		IP15_19_16)
243 #define GPSR6_6		F_(SSI_WS349,		IP15_15_12)
244 #define GPSR6_5		F_(SSI_SCK349,		IP15_11_8)
245 #define GPSR6_4		F_(SSI_SDATA2_A,	IP15_7_4)
246 #define GPSR6_3		F_(SSI_SDATA1_A,	IP15_3_0)
247 #define GPSR6_2		F_(SSI_SDATA0,		IP14_31_28)
248 #define GPSR6_1		F_(SSI_WS01239,		IP14_27_24)
249 #define GPSR6_0		F_(SSI_SCK01239,	IP14_23_20)
250 
251 /* GPSR7 */
252 #define GPSR7_3		FM(GP7_03)
253 #define GPSR7_2		FM(GP7_02)
254 #define GPSR7_1		FM(AVS2)
255 #define GPSR7_0		FM(AVS1)
256 
257 
258 /* IPSRx */		/* 0 */			/* 1 */		/* 2 */			/* 3 */				/* 4 */		/* 5 */		/* 6 */			/* 7 */		/* 8 */			/* 9 */		/* A */		/* B */		/* C - F */
259 #define IP0_3_0		FM(AVB_MDC)		F_(0, 0)	FM(MSIOF2_SS2_C)	F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
260 #define IP0_7_4		FM(AVB_MAGIC)		F_(0, 0)	FM(MSIOF2_SS1_C)	FM(SCK4_A)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
261 #define IP0_11_8	FM(AVB_PHY_INT)		F_(0, 0)	FM(MSIOF2_SYNC_C)	FM(RX4_A)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
262 #define IP0_15_12	FM(AVB_LINK)		F_(0, 0)	FM(MSIOF2_SCK_C)	FM(TX4_A)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263 #define IP0_19_16	FM(AVB_AVTP_MATCH_A)	F_(0, 0)	FM(MSIOF2_RXD_C)	FM(CTS4_N_A)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264 #define IP0_23_20	FM(AVB_AVTP_CAPTURE_A)	F_(0, 0)	FM(MSIOF2_TXD_C)	FM(RTS4_N_A)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
265 #define IP0_27_24	FM(IRQ0)		FM(QPOLB)	F_(0, 0)		FM(DU_CDE)			FM(VI4_DATA0_B) FM(CAN0_TX_B)	FM(CANFD0_TX_B)		FM(MSIOF3_SS2_E) F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
266 #define IP0_31_28	FM(IRQ1)		FM(QPOLA)	F_(0, 0)		FM(DU_DISP)			FM(VI4_DATA1_B) FM(CAN0_RX_B)	FM(CANFD0_RX_B)		FM(MSIOF3_SS1_E) F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
267 #define IP1_3_0		FM(IRQ2)		FM(QCPV_QDE)	F_(0, 0)		FM(DU_EXODDF_DU_ODDF_DISP_CDE)	FM(VI4_DATA2_B) F_(0, 0)	F_(0, 0)		FM(MSIOF3_SYNC_E) F_(0, 0)		FM(PWM3_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
268 #define IP1_7_4		FM(IRQ3)		FM(QSTVB_QVE)	F_(0, 0)		FM(DU_DOTCLKOUT1)		FM(VI4_DATA3_B) F_(0, 0)	F_(0, 0)		FM(MSIOF3_SCK_E) F_(0, 0)		FM(PWM4_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
269 #define IP1_11_8	FM(IRQ4)		FM(QSTH_QHS)	F_(0, 0)		FM(DU_EXHSYNC_DU_HSYNC)		FM(VI4_DATA4_B) F_(0, 0)	F_(0, 0)		FM(MSIOF3_RXD_E) F_(0, 0)		FM(PWM5_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270 #define IP1_15_12	FM(IRQ5)		FM(QSTB_QHE)	F_(0, 0)		FM(DU_EXVSYNC_DU_VSYNC)		FM(VI4_DATA5_B) F_(0, 0)	F_(0, 0)		FM(MSIOF3_TXD_E) F_(0, 0)		FM(PWM6_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271 #define IP1_19_16	FM(PWM0)		FM(AVB_AVTP_PPS)F_(0, 0)		F_(0, 0)			FM(VI4_DATA6_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		FM(IECLK_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
272 #define IP1_23_20	FM(PWM1_A)		F_(0, 0)	F_(0, 0)		FM(HRX3_D)			FM(VI4_DATA7_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		FM(IERX_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273 #define IP1_27_24	FM(PWM2_A)		F_(0, 0)	F_(0, 0)		FM(HTX3_D)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		FM(IETX_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
274 #define IP1_31_28	FM(A0)			FM(LCDOUT16)	FM(MSIOF3_SYNC_B)	F_(0, 0)			FM(VI4_DATA8)	F_(0, 0)	FM(DU_DB0)		F_(0, 0)	F_(0, 0)		FM(PWM3_A)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
275 #define IP2_3_0		FM(A1)			FM(LCDOUT17)	FM(MSIOF3_TXD_B)	F_(0, 0)			FM(VI4_DATA9)	F_(0, 0)	FM(DU_DB1)		F_(0, 0)	F_(0, 0)		FM(PWM4_A)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
276 #define IP2_7_4		FM(A2)			FM(LCDOUT18)	FM(MSIOF3_SCK_B)	F_(0, 0)			FM(VI4_DATA10)	F_(0, 0)	FM(DU_DB2)		F_(0, 0)	F_(0, 0)		FM(PWM5_A)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
277 #define IP2_11_8	FM(A3)			FM(LCDOUT19)	FM(MSIOF3_RXD_B)	F_(0, 0)			FM(VI4_DATA11)	F_(0, 0)	FM(DU_DB3)		F_(0, 0)	F_(0, 0)		FM(PWM6_A)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
278 #define IP2_15_12	FM(A4)			FM(LCDOUT20)	FM(MSIOF3_SS1_B)	F_(0, 0)			FM(VI4_DATA12)	FM(VI5_DATA12)	FM(DU_DB4)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279 #define IP2_19_16	FM(A5)			FM(LCDOUT21)	FM(MSIOF3_SS2_B)	FM(SCK4_B)			FM(VI4_DATA13)	FM(VI5_DATA13)	FM(DU_DB5)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280 #define IP2_23_20	FM(A6)			FM(LCDOUT22)	FM(MSIOF2_SS1_A)	FM(RX4_B)			FM(VI4_DATA14)	FM(VI5_DATA14)	FM(DU_DB6)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281 #define IP2_27_24	FM(A7)			FM(LCDOUT23)	FM(MSIOF2_SS2_A)	FM(TX4_B)			FM(VI4_DATA15)	FM(VI5_DATA15)	FM(DU_DB7)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
282 #define IP2_31_28	FM(A8)			FM(RX3_B)	FM(MSIOF2_SYNC_A)	FM(HRX4_B)			F_(0, 0)	F_(0, 0)	F_(0, 0)		FM(SDA6_A)	FM(AVB_AVTP_MATCH_B)	FM(PWM1_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283 #define IP3_3_0		FM(A9)			F_(0, 0)	FM(MSIOF2_SCK_A)	FM(CTS4_N_B)			F_(0, 0)	FM(VI5_VSYNC_N)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284 #define IP3_7_4		FM(A10)			F_(0, 0)	FM(MSIOF2_RXD_A)	FM(RTS4_N_B)			F_(0, 0)	FM(VI5_HSYNC_N)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
285 #define IP3_11_8	FM(A11)			FM(TX3_B)	FM(MSIOF2_TXD_A)	FM(HTX4_B)			FM(HSCK4)	FM(VI5_FIELD)	F_(0, 0)		FM(SCL6_A)	FM(AVB_AVTP_CAPTURE_B)	FM(PWM2_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
286 
287 /* IPSRx */		/* 0 */			/* 1 */		/* 2 */			/* 3 */				/* 4 */		/* 5 */		/* 6 */			/* 7 */		/* 8 */			/* 9 */		/* A */		/* B */		/* C - F */
288 #define IP3_15_12	FM(A12)			FM(LCDOUT12)	FM(MSIOF3_SCK_C)	F_(0, 0)			FM(HRX4_A)	FM(VI5_DATA8)	FM(DU_DG4)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
289 #define IP3_19_16	FM(A13)			FM(LCDOUT13)	FM(MSIOF3_SYNC_C)	F_(0, 0)			FM(HTX4_A)	FM(VI5_DATA9)	FM(DU_DG5)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
290 #define IP3_23_20	FM(A14)			FM(LCDOUT14)	FM(MSIOF3_RXD_C)	F_(0, 0)			FM(HCTS4_N)	FM(VI5_DATA10)	FM(DU_DG6)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291 #define IP3_27_24	FM(A15)			FM(LCDOUT15)	FM(MSIOF3_TXD_C)	F_(0, 0)			FM(HRTS4_N)	FM(VI5_DATA11)	FM(DU_DG7)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292 #define IP3_31_28	FM(A16)			FM(LCDOUT8)	F_(0, 0)		F_(0, 0)			FM(VI4_FIELD)	F_(0, 0)	FM(DU_DG0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293 #define IP4_3_0		FM(A17)			FM(LCDOUT9)	F_(0, 0)		F_(0, 0)			FM(VI4_VSYNC_N)	F_(0, 0)	FM(DU_DG1)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294 #define IP4_7_4		FM(A18)			FM(LCDOUT10)	F_(0, 0)		F_(0, 0)			FM(VI4_HSYNC_N)	F_(0, 0)	FM(DU_DG2)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295 #define IP4_11_8	FM(A19)			FM(LCDOUT11)	F_(0, 0)		F_(0, 0)			FM(VI4_CLKENB)	F_(0, 0)	FM(DU_DG3)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296 #define IP4_15_12	FM(CS0_N)		F_(0, 0)	F_(0, 0)		F_(0, 0)			F_(0, 0)	FM(VI5_CLKENB)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
297 #define IP4_19_16	FM(CS1_N)		F_(0, 0)	F_(0, 0)		F_(0, 0)			F_(0, 0)	FM(VI5_CLK)	F_(0, 0)		FM(EX_WAIT0_B)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
298 #define IP4_23_20	FM(BS_N)		FM(QSTVA_QVS)	FM(MSIOF3_SCK_D)	FM(SCK3)			FM(HSCK3)	F_(0, 0)	F_(0, 0)		F_(0, 0)	FM(CAN1_TX)		FM(CANFD1_TX)	FM(IETX_A)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299 #define IP4_27_24	FM(RD_N)		F_(0, 0)	FM(MSIOF3_SYNC_D)	FM(RX3_A)			FM(HRX3_A)	F_(0, 0)	F_(0, 0)		F_(0, 0)	FM(CAN0_TX_A)		FM(CANFD0_TX_A)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300 #define IP4_31_28	FM(RD_WR_N)		F_(0, 0)	FM(MSIOF3_RXD_D)	FM(TX3_A)			FM(HTX3_A)	F_(0, 0)	F_(0, 0)		F_(0, 0)	FM(CAN0_RX_A)		FM(CANFD0_RX_A)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301 #define IP5_3_0		FM(WE0_N)		F_(0, 0)	FM(MSIOF3_TXD_D)	FM(CTS3_N)			FM(HCTS3_N)	F_(0, 0)	F_(0, 0)		FM(SCL6_B)	FM(CAN_CLK)		F_(0, 0)	FM(IECLK_A)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
302 #define IP5_7_4		FM(WE1_N)		F_(0, 0)	FM(MSIOF3_SS1_D)	FM(RTS3_N)			FM(HRTS3_N)	F_(0, 0)	F_(0, 0)		FM(SDA6_B)	FM(CAN1_RX)		FM(CANFD1_RX)	FM(IERX_A)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
303 #define IP5_11_8	FM(EX_WAIT0_A)		FM(QCLK)	F_(0, 0)		F_(0, 0)			FM(VI4_CLK)	F_(0, 0)	FM(DU_DOTCLKOUT0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304 #define IP5_15_12	FM(D0)			FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A)	F_(0, 0)			FM(VI4_DATA16)	FM(VI5_DATA0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305 #define IP5_19_16	FM(D1)			FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A)	F_(0, 0)			FM(VI4_DATA17)	FM(VI5_DATA1)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306 #define IP5_23_20	FM(D2)			F_(0, 0)	FM(MSIOF3_RXD_A)	F_(0, 0)			FM(VI4_DATA18)	FM(VI5_DATA2)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
307 #define IP5_27_24	FM(D3)			F_(0, 0)	FM(MSIOF3_TXD_A)	F_(0, 0)			FM(VI4_DATA19)	FM(VI5_DATA3)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
308 #define IP5_31_28	FM(D4)			FM(MSIOF2_SCK_B)F_(0, 0)		F_(0, 0)			FM(VI4_DATA20)	FM(VI5_DATA4)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
309 #define IP6_3_0		FM(D5)			FM(MSIOF2_SYNC_B)F_(0, 0)		F_(0, 0)			FM(VI4_DATA21)	FM(VI5_DATA5)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310 #define IP6_7_4		FM(D6)			FM(MSIOF2_RXD_B)F_(0, 0)		F_(0, 0)			FM(VI4_DATA22)	FM(VI5_DATA6)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
311 #define IP6_11_8	FM(D7)			FM(MSIOF2_TXD_B)F_(0, 0)		F_(0, 0)			FM(VI4_DATA23)	FM(VI5_DATA7)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
312 #define IP6_15_12	FM(D8)			FM(LCDOUT0)	FM(MSIOF2_SCK_D)	FM(SCK4_C)			FM(VI4_DATA0_A)	F_(0, 0)	FM(DU_DR0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
313 #define IP6_19_16	FM(D9)			FM(LCDOUT1)	FM(MSIOF2_SYNC_D)	F_(0, 0)			FM(VI4_DATA1_A)	F_(0, 0)	FM(DU_DR1)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
314 #define IP6_23_20	FM(D10)			FM(LCDOUT2)	FM(MSIOF2_RXD_D)	FM(HRX3_B)			FM(VI4_DATA2_A)	FM(CTS4_N_C)	FM(DU_DR2)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
315 #define IP6_27_24	FM(D11)			FM(LCDOUT3)	FM(MSIOF2_TXD_D)	FM(HTX3_B)			FM(VI4_DATA3_A)	FM(RTS4_N_C)	FM(DU_DR3)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
316 #define IP6_31_28	FM(D12)			FM(LCDOUT4)	FM(MSIOF2_SS1_D)	FM(RX4_C)			FM(VI4_DATA4_A)	F_(0, 0)	FM(DU_DR4)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
317 
318 /* IPSRx */		/* 0 */			/* 1 */		/* 2 */			/* 3 */				/* 4 */		/* 5 */		/* 6 */			/* 7 */		/* 8 */			/* 9 */		/* A */		/* B */		/* C - F */
319 #define IP7_3_0		FM(D13)			FM(LCDOUT5)	FM(MSIOF2_SS2_D)	FM(TX4_C)			FM(VI4_DATA5_A)	F_(0, 0)	FM(DU_DR5)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
320 #define IP7_7_4		FM(D14)			FM(LCDOUT6)	FM(MSIOF3_SS1_A)	FM(HRX3_C)			FM(VI4_DATA6_A)	F_(0, 0)	FM(DU_DR6)		FM(SCL6_C)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
321 #define IP7_11_8	FM(D15)			FM(LCDOUT7)	FM(MSIOF3_SS2_A)	FM(HTX3_C)			FM(VI4_DATA7_A)	F_(0, 0)	FM(DU_DR7)		FM(SDA6_C)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
322 #define IP7_19_16	FM(SD0_CLK)		F_(0, 0)	FM(MSIOF1_SCK_E)	F_(0, 0)			F_(0, 0)	F_(0, 0)	FM(STP_OPWM_0_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
323 #define IP7_23_20	FM(SD0_CMD)		F_(0, 0)	FM(MSIOF1_SYNC_E)	F_(0, 0)			F_(0, 0)	F_(0, 0)	FM(STP_IVCXO27_0_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
324 #define IP7_27_24	FM(SD0_DAT0)		F_(0, 0)	FM(MSIOF1_RXD_E)	F_(0, 0)			F_(0, 0)	FM(TS_SCK0_B)	FM(STP_ISCLK_0_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
325 #define IP7_31_28	FM(SD0_DAT1)		F_(0, 0)	FM(MSIOF1_TXD_E)	F_(0, 0)			F_(0, 0)	FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
326 #define IP8_3_0		FM(SD0_DAT2)		F_(0, 0)	FM(MSIOF1_SS1_E)	F_(0, 0)			F_(0, 0)	FM(TS_SDAT0_B)	FM(STP_ISD_0_B)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
327 #define IP8_7_4		FM(SD0_DAT3)		F_(0, 0)	FM(MSIOF1_SS2_E)	F_(0, 0)			F_(0, 0)	FM(TS_SDEN0_B)	FM(STP_ISEN_0_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
328 #define IP8_11_8	FM(SD1_CLK)		F_(0, 0)	FM(MSIOF1_SCK_G)	F_(0, 0)			F_(0, 0)	FM(SIM0_CLK_A)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
329 #define IP8_15_12	FM(SD1_CMD)		F_(0, 0)	FM(MSIOF1_SYNC_G)	FM(NFCE_N_B)			F_(0, 0)	FM(SIM0_D_A)	FM(STP_IVCXO27_1_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
330 #define IP8_19_16	FM(SD1_DAT0)		FM(SD2_DAT4)	FM(MSIOF1_RXD_G)	FM(NFWP_N_B)			F_(0, 0)	FM(TS_SCK1_B)	FM(STP_ISCLK_1_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
331 #define IP8_23_20	FM(SD1_DAT1)		FM(SD2_DAT5)	FM(MSIOF1_TXD_G)	FM(NFDATA14_B)			F_(0, 0)	FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
332 #define IP8_27_24	FM(SD1_DAT2)		FM(SD2_DAT6)	FM(MSIOF1_SS1_G)	FM(NFDATA15_B)			F_(0, 0)	FM(TS_SDAT1_B)	FM(STP_ISD_1_B)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
333 #define IP8_31_28	FM(SD1_DAT3)		FM(SD2_DAT7)	FM(MSIOF1_SS2_G)	FM(NFRB_N_B)			F_(0, 0)	FM(TS_SDEN1_B)	FM(STP_ISEN_1_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
334 #define IP9_3_0		FM(SD2_CLK)		F_(0, 0)	FM(NFDATA8)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
335 #define IP9_7_4		FM(SD2_CMD)		F_(0, 0)	FM(NFDATA9)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
336 #define IP9_11_8	FM(SD2_DAT0)		F_(0, 0)	FM(NFDATA10)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
337 #define IP9_15_12	FM(SD2_DAT1)		F_(0, 0)	FM(NFDATA11)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
338 #define IP9_19_16	FM(SD2_DAT2)		F_(0, 0)	FM(NFDATA12)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
339 #define IP9_23_20	FM(SD2_DAT3)		F_(0, 0)	FM(NFDATA13)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
340 #define IP9_27_24	FM(SD2_DS)		F_(0, 0)	FM(NFALE)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
341 #define IP9_31_28	FM(SD3_CLK)		F_(0, 0)	FM(NFWE_N)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
342 #define IP10_3_0	FM(SD3_CMD)		F_(0, 0)	FM(NFRE_N)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
343 #define IP10_7_4	FM(SD3_DAT0)		F_(0, 0)	FM(NFDATA0)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
344 #define IP10_11_8	FM(SD3_DAT1)		F_(0, 0)	FM(NFDATA1)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
345 #define IP10_15_12	FM(SD3_DAT2)		F_(0, 0)	FM(NFDATA2)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
346 #define IP10_19_16	FM(SD3_DAT3)		F_(0, 0)	FM(NFDATA3)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
347 #define IP10_23_20	FM(SD3_DAT4)		FM(SD2_CD_A)	FM(NFDATA4)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
348 #define IP10_27_24	FM(SD3_DAT5)		FM(SD2_WP_A)	FM(NFDATA5)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
349 #define IP10_31_28	FM(SD3_DAT6)		FM(SD3_CD)	FM(NFDATA6)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
350 #define IP11_3_0	FM(SD3_DAT7)		FM(SD3_WP)	FM(NFDATA7)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
351 #define IP11_7_4	FM(SD3_DS)		F_(0, 0)	FM(NFCLE)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
352 #define IP11_11_8	FM(SD0_CD)		F_(0, 0)	FM(NFDATA14_A)		F_(0, 0)			FM(SCL2_B)	FM(SIM0_RST_A)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
353 
354 /* IPSRx */		/* 0 */			/* 1 */		/* 2 */			/* 3 */				/* 4 */		/* 5 */		/* 6 */			/* 7 */		/* 8 */			/* 9 */		/* A */		/* B */		/* C - F */
355 #define IP11_15_12	FM(SD0_WP)		F_(0, 0)	FM(NFDATA15_A)		F_(0, 0)			FM(SDA2_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
356 #define IP11_19_16	FM(SD1_CD)		F_(0, 0)	FM(NFRB_N_A)		F_(0, 0)			F_(0, 0)	FM(SIM0_CLK_B)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
357 #define IP11_23_20	FM(SD1_WP)		F_(0, 0)	FM(NFCE_N_A)		F_(0, 0)			F_(0, 0)	FM(SIM0_D_B)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
358 #define IP11_27_24	FM(SCK0)		FM(HSCK1_B)	FM(MSIOF1_SS2_B)	FM(AUDIO_CLKC_B)		FM(SDA2_A)	FM(SIM0_RST_B)	FM(STP_OPWM_0_C)	FM(RIF0_CLK_B)	F_(0, 0)		FM(ADICHS2)	FM(SCK5_B)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
359 #define IP11_31_28	FM(RX0)			FM(HRX1_B)	F_(0, 0)		F_(0, 0)			F_(0, 0)	FM(TS_SCK0_C)	FM(STP_ISCLK_0_C)	FM(RIF0_D0_B)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
360 #define IP12_3_0	FM(TX0)			FM(HTX1_B)	F_(0, 0)		F_(0, 0)			F_(0, 0)	FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C)	FM(RIF0_D1_B)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
361 #define IP12_7_4	FM(CTS0_N)		FM(HCTS1_N_B)	FM(MSIOF1_SYNC_B)	F_(0, 0)			F_(0, 0)	FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C)	FM(RIF1_SYNC_B)	FM(AUDIO_CLKOUT_C)	FM(ADICS_SAMP)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
362 #define IP12_11_8	FM(RTS0_N)		FM(HRTS1_N_B)	FM(MSIOF1_SS1_B)	FM(AUDIO_CLKA_B)		FM(SCL2_A)	F_(0, 0)	FM(STP_IVCXO27_1_C)	FM(RIF0_SYNC_B)	F_(0, 0)		FM(ADICHS1)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
363 #define IP12_15_12	FM(RX1_A)		FM(HRX1_A)	F_(0, 0)		F_(0, 0)			F_(0, 0)	FM(TS_SDAT0_C)	FM(STP_ISD_0_C)		FM(RIF1_CLK_C)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
364 #define IP12_19_16	FM(TX1_A)		FM(HTX1_A)	F_(0, 0)		F_(0, 0)			F_(0, 0)	FM(TS_SDEN0_C)	FM(STP_ISEN_0_C)	FM(RIF1_D0_C)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
365 #define IP12_23_20	FM(CTS1_N)		FM(HCTS1_N_A)	FM(MSIOF1_RXD_B)	F_(0, 0)			F_(0, 0)	FM(TS_SDEN1_C)	FM(STP_ISEN_1_C)	FM(RIF1_D0_B)	F_(0, 0)		FM(ADIDATA)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
366 #define IP12_27_24	FM(RTS1_N)		FM(HRTS1_N_A)	FM(MSIOF1_TXD_B)	F_(0, 0)			F_(0, 0)	FM(TS_SDAT1_C)	FM(STP_ISD_1_C)		FM(RIF1_D1_B)	F_(0, 0)		FM(ADICHS0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
367 #define IP12_31_28	FM(SCK2)		FM(SCIF_CLK_B)	FM(MSIOF1_SCK_B)	F_(0, 0)			F_(0, 0)	FM(TS_SCK1_C)	FM(STP_ISCLK_1_C)	FM(RIF1_CLK_B)	F_(0, 0)		FM(ADICLK)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
368 #define IP13_3_0	FM(TX2_A)		F_(0, 0)	F_(0, 0)		FM(SD2_CD_B)			FM(SCL1_A)	F_(0, 0)	FM(FMCLK_A)		FM(RIF1_D1_C)	F_(0, 0)		FM(FSO_CFE_0_N)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
369 #define IP13_7_4	FM(RX2_A)		F_(0, 0)	F_(0, 0)		FM(SD2_WP_B)			FM(SDA1_A)	F_(0, 0)	FM(FMIN_A)		FM(RIF1_SYNC_C)	F_(0, 0)		FM(FSO_CFE_1_N)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
370 #define IP13_11_8	FM(HSCK0)		F_(0, 0)	FM(MSIOF1_SCK_D)	FM(AUDIO_CLKB_A)		FM(SSI_SDATA1_B)FM(TS_SCK0_D)	FM(STP_ISCLK_0_D)	FM(RIF0_CLK_C)	F_(0, 0)		F_(0, 0)	FM(RX5_B)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
371 #define IP13_15_12	FM(HRX0)		F_(0, 0)	FM(MSIOF1_RXD_D)	F_(0, 0)			FM(SSI_SDATA2_B)FM(TS_SDEN0_D)	FM(STP_ISEN_0_D)	FM(RIF0_D0_C)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
372 #define IP13_19_16	FM(HTX0)		F_(0, 0)	FM(MSIOF1_TXD_D)	F_(0, 0)			FM(SSI_SDATA9_B)FM(TS_SDAT0_D)	FM(STP_ISD_0_D)		FM(RIF0_D1_C)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
373 #define IP13_23_20	FM(HCTS0_N)		FM(RX2_B)	FM(MSIOF1_SYNC_D)	F_(0, 0)			FM(SSI_SCK9_A)	FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D)	FM(RIF0_SYNC_C)	FM(AUDIO_CLKOUT1_A)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
374 #define IP13_27_24	FM(HRTS0_N)		FM(TX2_B)	FM(MSIOF1_SS1_D)	F_(0, 0)			FM(SSI_WS9_A)	F_(0, 0)	FM(STP_IVCXO27_0_D)	FM(BPFCLK_A)	FM(AUDIO_CLKOUT2_A)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
375 #define IP13_31_28	FM(MSIOF0_SYNC)		F_(0, 0)	F_(0, 0)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	FM(AUDIO_CLKOUT_A)	F_(0, 0)	FM(TX5_B)	F_(0, 0)	F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0)
376 #define IP14_3_0	FM(MSIOF0_SS1)		FM(RX5_A)	FM(NFWP_N_A)		FM(AUDIO_CLKA_C)		FM(SSI_SCK2_A)	F_(0, 0)	FM(STP_IVCXO27_0_C)	F_(0, 0)	FM(AUDIO_CLKOUT3_A)	F_(0, 0)	FM(TCLK1_B)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
377 #define IP14_7_4	FM(MSIOF0_SS2)		FM(TX5_A)	FM(MSIOF1_SS2_D)	FM(AUDIO_CLKC_A)		FM(SSI_WS2_A)	F_(0, 0)	FM(STP_OPWM_0_D)	F_(0, 0)	FM(AUDIO_CLKOUT_D)	F_(0, 0)	FM(SPEEDIN_B)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
378 #define IP14_11_8	FM(MLB_CLK)		F_(0, 0)	FM(MSIOF1_SCK_F)	F_(0, 0)			FM(SCL1_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
379 #define IP14_15_12	FM(MLB_SIG)		FM(RX1_B)	FM(MSIOF1_SYNC_F)	F_(0, 0)			FM(SDA1_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
380 #define IP14_19_16	FM(MLB_DAT)		FM(TX1_B)	FM(MSIOF1_RXD_F)	F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
381 #define IP14_23_20	FM(SSI_SCK01239)	F_(0, 0)	FM(MSIOF1_TXD_F)	F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
382 #define IP14_27_24	FM(SSI_WS01239)		F_(0, 0)	FM(MSIOF1_SS1_F)	F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
383 
384 /* IPSRx */		/* 0 */			/* 1 */		/* 2 */			/* 3 */				/* 4 */		/* 5 */		/* 6 */			/* 7 */		/* 8 */			/* 9 */		/* A */		/* B */		/* C - F */
385 #define IP14_31_28	FM(SSI_SDATA0)		F_(0, 0)	FM(MSIOF1_SS2_F)	F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
386 #define IP15_3_0	FM(SSI_SDATA1_A)	F_(0, 0)	F_(0, 0)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
387 #define IP15_7_4	FM(SSI_SDATA2_A)	F_(0, 0)	F_(0, 0)		F_(0, 0)			FM(SSI_SCK1_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
388 #define IP15_11_8	FM(SSI_SCK349)		F_(0, 0)	FM(MSIOF1_SS1_A)	F_(0, 0)			F_(0, 0)	F_(0, 0)	FM(STP_OPWM_0_A)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
389 #define IP15_15_12	FM(SSI_WS349)		FM(HCTS2_N_A)	FM(MSIOF1_SS2_A)	F_(0, 0)			F_(0, 0)	F_(0, 0)	FM(STP_IVCXO27_0_A)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
390 #define IP15_19_16	FM(SSI_SDATA3)		FM(HRTS2_N_A)	FM(MSIOF1_TXD_A)	F_(0, 0)			F_(0, 0)	FM(TS_SCK0_A)	FM(STP_ISCLK_0_A)	FM(RIF0_D1_A)	FM(RIF2_D0_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
391 #define IP15_23_20	FM(SSI_SCK4)		FM(HRX2_A)	FM(MSIOF1_SCK_A)	F_(0, 0)			F_(0, 0)	FM(TS_SDAT0_A)	FM(STP_ISD_0_A)		FM(RIF0_CLK_A)	FM(RIF2_CLK_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
392 #define IP15_27_24	FM(SSI_WS4)		FM(HTX2_A)	FM(MSIOF1_SYNC_A)	F_(0, 0)			F_(0, 0)	FM(TS_SDEN0_A)	FM(STP_ISEN_0_A)	FM(RIF0_SYNC_A)	FM(RIF2_SYNC_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
393 #define IP15_31_28	FM(SSI_SDATA4)		FM(HSCK2_A)	FM(MSIOF1_RXD_A)	F_(0, 0)			F_(0, 0)	FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A)	FM(RIF0_D0_A)	FM(RIF2_D1_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
394 #define IP16_3_0	FM(SSI_SCK6)		F_(0, 0)	F_(0, 0)		FM(SIM0_RST_D)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
395 #define IP16_7_4	FM(SSI_WS6)		F_(0, 0)	F_(0, 0)		FM(SIM0_D_D)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
396 #define IP16_11_8	FM(SSI_SDATA6)		F_(0, 0)	F_(0, 0)		FM(SIM0_CLK_D)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
397 #define IP16_15_12	FM(SSI_SCK78)		FM(HRX2_B)	FM(MSIOF1_SCK_C)	F_(0, 0)			F_(0, 0)	FM(TS_SCK1_A)	FM(STP_ISCLK_1_A)	FM(RIF1_CLK_A)	FM(RIF3_CLK_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
398 #define IP16_19_16	FM(SSI_WS78)		FM(HTX2_B)	FM(MSIOF1_SYNC_C)	F_(0, 0)			F_(0, 0)	FM(TS_SDAT1_A)	FM(STP_ISD_1_A)		FM(RIF1_SYNC_A)	FM(RIF3_SYNC_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
399 #define IP16_23_20	FM(SSI_SDATA7)		FM(HCTS2_N_B)	FM(MSIOF1_RXD_C)	F_(0, 0)			F_(0, 0)	FM(TS_SDEN1_A)	FM(STP_ISEN_1_A)	FM(RIF1_D0_A)	FM(RIF3_D0_A)		F_(0, 0)	FM(TCLK2_A)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
400 #define IP16_27_24	FM(SSI_SDATA8)		FM(HRTS2_N_B)	FM(MSIOF1_TXD_C)	F_(0, 0)			F_(0, 0)	FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A)	FM(RIF1_D1_A)	FM(RIF3_D1_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
401 #define IP16_31_28	FM(SSI_SDATA9_A)	FM(HSCK2_B)	FM(MSIOF1_SS1_C)	FM(HSCK1_A)			FM(SSI_WS1_B)	FM(SCK1)	FM(STP_IVCXO27_1_A)	FM(SCK5_A)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
402 #define IP17_3_0	FM(AUDIO_CLKA_A)	F_(0, 0)	F_(0, 0)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
403 #define IP17_7_4	FM(AUDIO_CLKB_B)	FM(SCIF_CLK_A)	F_(0, 0)		F_(0, 0)			F_(0, 0)	F_(0, 0)	FM(STP_IVCXO27_1_D)	FM(REMOCON_A)	F_(0, 0)		F_(0, 0)	FM(TCLK1_A)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
404 #define IP17_11_8	FM(USB0_PWEN)		F_(0, 0)	F_(0, 0)		FM(SIM0_RST_C)			F_(0, 0)	FM(TS_SCK1_D)	FM(STP_ISCLK_1_D)	FM(BPFCLK_B)	FM(RIF3_CLK_B)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
405 #define IP17_15_12	FM(USB0_OVC)		F_(0, 0)	F_(0, 0)		FM(SIM0_D_C)			F_(0, 0)	FM(TS_SDAT1_D)	FM(STP_ISD_1_D)		F_(0, 0)	FM(RIF3_SYNC_B)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
406 #define IP17_19_16	FM(USB1_PWEN)		F_(0, 0)	F_(0, 0)		FM(SIM0_CLK_C)			FM(SSI_SCK1_A)	FM(TS_SCK0_E)	FM(STP_ISCLK_0_E)	FM(FMCLK_B)	FM(RIF2_CLK_B)		F_(0, 0)	FM(SPEEDIN_A)	F_(0, 0)	F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0)
407 #define IP17_23_20	FM(USB1_OVC)		F_(0, 0)	FM(MSIOF1_SS2_C)	F_(0, 0)			FM(SSI_WS1_A)	FM(TS_SDAT0_E)	FM(STP_ISD_0_E)		FM(FMIN_B)	FM(RIF2_SYNC_B)		F_(0, 0)	FM(REMOCON_B)	F_(0, 0)	F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0)
408 #define IP17_27_24	FM(USB30_PWEN)		F_(0, 0)	F_(0, 0)		FM(AUDIO_CLKOUT_B)		FM(SSI_SCK2_B)	FM(TS_SDEN1_D)	FM(STP_ISEN_1_D)	FM(STP_OPWM_0_E)FM(RIF3_D0_B)		F_(0, 0)	FM(TCLK2_B)	FM(TPU0TO0)	FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0)
409 #define IP17_31_28	FM(USB30_OVC)		F_(0, 0)	F_(0, 0)		FM(AUDIO_CLKOUT1_B)		FM(SSI_WS2_B)	FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D)	FM(STP_IVCXO27_0_E)FM(RIF3_D1_B)	F_(0, 0)	FM(FSO_TOE_N)	FM(TPU0TO1)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
410 #define IP18_3_0	FM(GP6_30)		F_(0, 0)	F_(0, 0)		FM(AUDIO_CLKOUT2_B)		FM(SSI_SCK9_B)	FM(TS_SDEN0_E)	FM(STP_ISEN_0_E)	F_(0, 0)	FM(RIF2_D0_B)		F_(0, 0)	F_(0, 0)	FM(TPU0TO2)	FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0)
411 #define IP18_7_4	FM(GP6_31)		F_(0, 0)	F_(0, 0)		FM(AUDIO_CLKOUT3_B)		FM(SSI_WS9_B)	FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E)	F_(0, 0)	FM(RIF2_D1_B)		F_(0, 0)	F_(0, 0)	FM(TPU0TO3)	FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0)
412 
413 #define PINMUX_GPSR	\
414 \
415 												GPSR6_31 \
416 												GPSR6_30 \
417 												GPSR6_29 \
418 		GPSR1_28									GPSR6_28 \
419 		GPSR1_27									GPSR6_27 \
420 		GPSR1_26									GPSR6_26 \
421 		GPSR1_25							GPSR5_25	GPSR6_25 \
422 		GPSR1_24							GPSR5_24	GPSR6_24 \
423 		GPSR1_23							GPSR5_23	GPSR6_23 \
424 		GPSR1_22							GPSR5_22	GPSR6_22 \
425 		GPSR1_21							GPSR5_21	GPSR6_21 \
426 		GPSR1_20							GPSR5_20	GPSR6_20 \
427 		GPSR1_19							GPSR5_19	GPSR6_19 \
428 		GPSR1_18							GPSR5_18	GPSR6_18 \
429 		GPSR1_17					GPSR4_17	GPSR5_17	GPSR6_17 \
430 		GPSR1_16					GPSR4_16	GPSR5_16	GPSR6_16 \
431 GPSR0_15	GPSR1_15			GPSR3_15	GPSR4_15	GPSR5_15	GPSR6_15 \
432 GPSR0_14	GPSR1_14	GPSR2_14	GPSR3_14	GPSR4_14	GPSR5_14	GPSR6_14 \
433 GPSR0_13	GPSR1_13	GPSR2_13	GPSR3_13	GPSR4_13	GPSR5_13	GPSR6_13 \
434 GPSR0_12	GPSR1_12	GPSR2_12	GPSR3_12	GPSR4_12	GPSR5_12	GPSR6_12 \
435 GPSR0_11	GPSR1_11	GPSR2_11	GPSR3_11	GPSR4_11	GPSR5_11	GPSR6_11 \
436 GPSR0_10	GPSR1_10	GPSR2_10	GPSR3_10	GPSR4_10	GPSR5_10	GPSR6_10 \
437 GPSR0_9		GPSR1_9		GPSR2_9		GPSR3_9		GPSR4_9		GPSR5_9		GPSR6_9 \
438 GPSR0_8		GPSR1_8		GPSR2_8		GPSR3_8		GPSR4_8		GPSR5_8		GPSR6_8 \
439 GPSR0_7		GPSR1_7		GPSR2_7		GPSR3_7		GPSR4_7		GPSR5_7		GPSR6_7 \
440 GPSR0_6		GPSR1_6		GPSR2_6		GPSR3_6		GPSR4_6		GPSR5_6		GPSR6_6 \
441 GPSR0_5		GPSR1_5		GPSR2_5		GPSR3_5		GPSR4_5		GPSR5_5		GPSR6_5 \
442 GPSR0_4		GPSR1_4		GPSR2_4		GPSR3_4		GPSR4_4		GPSR5_4		GPSR6_4 \
443 GPSR0_3		GPSR1_3		GPSR2_3		GPSR3_3		GPSR4_3		GPSR5_3		GPSR6_3		GPSR7_3 \
444 GPSR0_2		GPSR1_2		GPSR2_2		GPSR3_2		GPSR4_2		GPSR5_2		GPSR6_2		GPSR7_2 \
445 GPSR0_1		GPSR1_1		GPSR2_1		GPSR3_1		GPSR4_1		GPSR5_1		GPSR6_1		GPSR7_1 \
446 GPSR0_0		GPSR1_0		GPSR2_0		GPSR3_0		GPSR4_0		GPSR5_0		GPSR6_0		GPSR7_0
447 
448 #define PINMUX_IPSR				\
449 \
450 FM(IP0_3_0)	IP0_3_0		FM(IP1_3_0)	IP1_3_0		FM(IP2_3_0)	IP2_3_0		FM(IP3_3_0)	IP3_3_0 \
451 FM(IP0_7_4)	IP0_7_4		FM(IP1_7_4)	IP1_7_4		FM(IP2_7_4)	IP2_7_4		FM(IP3_7_4)	IP3_7_4 \
452 FM(IP0_11_8)	IP0_11_8	FM(IP1_11_8)	IP1_11_8	FM(IP2_11_8)	IP2_11_8	FM(IP3_11_8)	IP3_11_8 \
453 FM(IP0_15_12)	IP0_15_12	FM(IP1_15_12)	IP1_15_12	FM(IP2_15_12)	IP2_15_12	FM(IP3_15_12)	IP3_15_12 \
454 FM(IP0_19_16)	IP0_19_16	FM(IP1_19_16)	IP1_19_16	FM(IP2_19_16)	IP2_19_16	FM(IP3_19_16)	IP3_19_16 \
455 FM(IP0_23_20)	IP0_23_20	FM(IP1_23_20)	IP1_23_20	FM(IP2_23_20)	IP2_23_20	FM(IP3_23_20)	IP3_23_20 \
456 FM(IP0_27_24)	IP0_27_24	FM(IP1_27_24)	IP1_27_24	FM(IP2_27_24)	IP2_27_24	FM(IP3_27_24)	IP3_27_24 \
457 FM(IP0_31_28)	IP0_31_28	FM(IP1_31_28)	IP1_31_28	FM(IP2_31_28)	IP2_31_28	FM(IP3_31_28)	IP3_31_28 \
458 \
459 FM(IP4_3_0)	IP4_3_0		FM(IP5_3_0)	IP5_3_0		FM(IP6_3_0)	IP6_3_0		FM(IP7_3_0)	IP7_3_0 \
460 FM(IP4_7_4)	IP4_7_4		FM(IP5_7_4)	IP5_7_4		FM(IP6_7_4)	IP6_7_4		FM(IP7_7_4)	IP7_7_4 \
461 FM(IP4_11_8)	IP4_11_8	FM(IP5_11_8)	IP5_11_8	FM(IP6_11_8)	IP6_11_8	FM(IP7_11_8)	IP7_11_8 \
462 FM(IP4_15_12)	IP4_15_12	FM(IP5_15_12)	IP5_15_12	FM(IP6_15_12)	IP6_15_12 \
463 FM(IP4_19_16)	IP4_19_16	FM(IP5_19_16)	IP5_19_16	FM(IP6_19_16)	IP6_19_16	FM(IP7_19_16)	IP7_19_16 \
464 FM(IP4_23_20)	IP4_23_20	FM(IP5_23_20)	IP5_23_20	FM(IP6_23_20)	IP6_23_20	FM(IP7_23_20)	IP7_23_20 \
465 FM(IP4_27_24)	IP4_27_24	FM(IP5_27_24)	IP5_27_24	FM(IP6_27_24)	IP6_27_24	FM(IP7_27_24)	IP7_27_24 \
466 FM(IP4_31_28)	IP4_31_28	FM(IP5_31_28)	IP5_31_28	FM(IP6_31_28)	IP6_31_28	FM(IP7_31_28)	IP7_31_28 \
467 \
468 FM(IP8_3_0)	IP8_3_0		FM(IP9_3_0)	IP9_3_0		FM(IP10_3_0)	IP10_3_0	FM(IP11_3_0)	IP11_3_0 \
469 FM(IP8_7_4)	IP8_7_4		FM(IP9_7_4)	IP9_7_4		FM(IP10_7_4)	IP10_7_4	FM(IP11_7_4)	IP11_7_4 \
470 FM(IP8_11_8)	IP8_11_8	FM(IP9_11_8)	IP9_11_8	FM(IP10_11_8)	IP10_11_8	FM(IP11_11_8)	IP11_11_8 \
471 FM(IP8_15_12)	IP8_15_12	FM(IP9_15_12)	IP9_15_12	FM(IP10_15_12)	IP10_15_12	FM(IP11_15_12)	IP11_15_12 \
472 FM(IP8_19_16)	IP8_19_16	FM(IP9_19_16)	IP9_19_16	FM(IP10_19_16)	IP10_19_16	FM(IP11_19_16)	IP11_19_16 \
473 FM(IP8_23_20)	IP8_23_20	FM(IP9_23_20)	IP9_23_20	FM(IP10_23_20)	IP10_23_20	FM(IP11_23_20)	IP11_23_20 \
474 FM(IP8_27_24)	IP8_27_24	FM(IP9_27_24)	IP9_27_24	FM(IP10_27_24)	IP10_27_24	FM(IP11_27_24)	IP11_27_24 \
475 FM(IP8_31_28)	IP8_31_28	FM(IP9_31_28)	IP9_31_28	FM(IP10_31_28)	IP10_31_28	FM(IP11_31_28)	IP11_31_28 \
476 \
477 FM(IP12_3_0)	IP12_3_0	FM(IP13_3_0)	IP13_3_0	FM(IP14_3_0)	IP14_3_0	FM(IP15_3_0)	IP15_3_0 \
478 FM(IP12_7_4)	IP12_7_4	FM(IP13_7_4)	IP13_7_4	FM(IP14_7_4)	IP14_7_4	FM(IP15_7_4)	IP15_7_4 \
479 FM(IP12_11_8)	IP12_11_8	FM(IP13_11_8)	IP13_11_8	FM(IP14_11_8)	IP14_11_8	FM(IP15_11_8)	IP15_11_8 \
480 FM(IP12_15_12)	IP12_15_12	FM(IP13_15_12)	IP13_15_12	FM(IP14_15_12)	IP14_15_12	FM(IP15_15_12)	IP15_15_12 \
481 FM(IP12_19_16)	IP12_19_16	FM(IP13_19_16)	IP13_19_16	FM(IP14_19_16)	IP14_19_16	FM(IP15_19_16)	IP15_19_16 \
482 FM(IP12_23_20)	IP12_23_20	FM(IP13_23_20)	IP13_23_20	FM(IP14_23_20)	IP14_23_20	FM(IP15_23_20)	IP15_23_20 \
483 FM(IP12_27_24)	IP12_27_24	FM(IP13_27_24)	IP13_27_24	FM(IP14_27_24)	IP14_27_24	FM(IP15_27_24)	IP15_27_24 \
484 FM(IP12_31_28)	IP12_31_28	FM(IP13_31_28)	IP13_31_28	FM(IP14_31_28)	IP14_31_28	FM(IP15_31_28)	IP15_31_28 \
485 \
486 FM(IP16_3_0)	IP16_3_0	FM(IP17_3_0)	IP17_3_0	FM(IP18_3_0)	IP18_3_0 \
487 FM(IP16_7_4)	IP16_7_4	FM(IP17_7_4)	IP17_7_4	FM(IP18_7_4)	IP18_7_4 \
488 FM(IP16_11_8)	IP16_11_8	FM(IP17_11_8)	IP17_11_8 \
489 FM(IP16_15_12)	IP16_15_12	FM(IP17_15_12)	IP17_15_12 \
490 FM(IP16_19_16)	IP16_19_16	FM(IP17_19_16)	IP17_19_16 \
491 FM(IP16_23_20)	IP16_23_20	FM(IP17_23_20)	IP17_23_20 \
492 FM(IP16_27_24)	IP16_27_24	FM(IP17_27_24)	IP17_27_24 \
493 FM(IP16_31_28)	IP16_31_28	FM(IP17_31_28)	IP17_31_28
494 
495 /* MOD_SEL0 */			/* 0 */			/* 1 */			/* 2 */			/* 3 */			/* 4 */			/* 5 */			/* 6 */			/* 7 */
496 #define MOD_SEL0_31_30_29	FM(SEL_MSIOF3_0)	FM(SEL_MSIOF3_1)	FM(SEL_MSIOF3_2)	FM(SEL_MSIOF3_3)	FM(SEL_MSIOF3_4)	F_(0, 0)		F_(0, 0)		F_(0, 0)
497 #define MOD_SEL0_28_27		FM(SEL_MSIOF2_0)	FM(SEL_MSIOF2_1)	FM(SEL_MSIOF2_2)	FM(SEL_MSIOF2_3)
498 #define MOD_SEL0_26_25_24	FM(SEL_MSIOF1_0)	FM(SEL_MSIOF1_1)	FM(SEL_MSIOF1_2)	FM(SEL_MSIOF1_3)	FM(SEL_MSIOF1_4)	FM(SEL_MSIOF1_5)	FM(SEL_MSIOF1_6)	F_(0, 0)
499 #define MOD_SEL0_23		FM(SEL_LBSC_0)		FM(SEL_LBSC_1)
500 #define MOD_SEL0_22		FM(SEL_IEBUS_0)		FM(SEL_IEBUS_1)
501 #define MOD_SEL0_21		FM(SEL_I2C2_0)		FM(SEL_I2C2_1)
502 #define MOD_SEL0_20		FM(SEL_I2C1_0)		FM(SEL_I2C1_1)
503 #define MOD_SEL0_19		FM(SEL_HSCIF4_0)	FM(SEL_HSCIF4_1)
504 #define MOD_SEL0_18_17		FM(SEL_HSCIF3_0)	FM(SEL_HSCIF3_1)	FM(SEL_HSCIF3_2)	FM(SEL_HSCIF3_3)
505 #define MOD_SEL0_16		FM(SEL_HSCIF1_0)	FM(SEL_HSCIF1_1)
506 #define MOD_SEL0_14_13		FM(SEL_HSCIF2_0)	FM(SEL_HSCIF2_1)	FM(SEL_HSCIF2_2)	F_(0, 0)
507 #define MOD_SEL0_12		FM(SEL_ETHERAVB_0)	FM(SEL_ETHERAVB_1)
508 #define MOD_SEL0_11		FM(SEL_DRIF3_0)		FM(SEL_DRIF3_1)
509 #define MOD_SEL0_10		FM(SEL_DRIF2_0)		FM(SEL_DRIF2_1)
510 #define MOD_SEL0_9_8		FM(SEL_DRIF1_0)		FM(SEL_DRIF1_1)		FM(SEL_DRIF1_2)		F_(0, 0)
511 #define MOD_SEL0_7_6		FM(SEL_DRIF0_0)		FM(SEL_DRIF0_1)		FM(SEL_DRIF0_2)		F_(0, 0)
512 #define MOD_SEL0_5		FM(SEL_CANFD0_0)	FM(SEL_CANFD0_1)
513 #define MOD_SEL0_4_3		FM(SEL_ADGA_0)		FM(SEL_ADGA_1)		FM(SEL_ADGA_2)		FM(SEL_ADGA_3)
514 
515 /* MOD_SEL1 */			/* 0 */			/* 1 */			/* 2 */			/* 3 */			/* 4 */			/* 5 */			/* 6 */			/* 7 */
516 #define MOD_SEL1_31_30		FM(SEL_TSIF1_0)		FM(SEL_TSIF1_1)		FM(SEL_TSIF1_2)		FM(SEL_TSIF1_3)
517 #define MOD_SEL1_29_28_27	FM(SEL_TSIF0_0)		FM(SEL_TSIF0_1)		FM(SEL_TSIF0_2)		FM(SEL_TSIF0_3)		FM(SEL_TSIF0_4)		F_(0, 0)		F_(0, 0)		F_(0, 0)
518 #define MOD_SEL1_26		FM(SEL_TIMER_TMU_0)	FM(SEL_TIMER_TMU_1)
519 #define MOD_SEL1_25_24		FM(SEL_SSP1_1_0)	FM(SEL_SSP1_1_1)	FM(SEL_SSP1_1_2)	FM(SEL_SSP1_1_3)
520 #define MOD_SEL1_23_22_21	FM(SEL_SSP1_0_0)	FM(SEL_SSP1_0_1)	FM(SEL_SSP1_0_2)	FM(SEL_SSP1_0_3)	FM(SEL_SSP1_0_4)	F_(0, 0)		F_(0, 0)		F_(0, 0)
521 #define MOD_SEL1_20		FM(SEL_SSI1_0)		FM(SEL_SSI1_1)
522 #define MOD_SEL1_19		FM(SEL_SPEED_PULSE_0)	FM(SEL_SPEED_PULSE_1)
523 #define MOD_SEL1_18_17		FM(SEL_SIMCARD_0)	FM(SEL_SIMCARD_1)	FM(SEL_SIMCARD_2)	FM(SEL_SIMCARD_3)
524 #define MOD_SEL1_16		FM(SEL_SDHI2_0)		FM(SEL_SDHI2_1)
525 #define MOD_SEL1_15_14		FM(SEL_SCIF4_0)		FM(SEL_SCIF4_1)		FM(SEL_SCIF4_2)		F_(0, 0)
526 #define MOD_SEL1_13		FM(SEL_SCIF3_0)		FM(SEL_SCIF3_1)
527 #define MOD_SEL1_12		FM(SEL_SCIF2_0)		FM(SEL_SCIF2_1)
528 #define MOD_SEL1_11		FM(SEL_SCIF1_0)		FM(SEL_SCIF1_1)
529 #define MOD_SEL1_10		FM(SEL_SCIF_0)		FM(SEL_SCIF_1)
530 #define MOD_SEL1_9		FM(SEL_REMOCON_0)	FM(SEL_REMOCON_1)
531 #define MOD_SEL1_6		FM(SEL_RCAN0_0)		FM(SEL_RCAN0_1)
532 #define MOD_SEL1_5		FM(SEL_PWM6_0)		FM(SEL_PWM6_1)
533 #define MOD_SEL1_4		FM(SEL_PWM5_0)		FM(SEL_PWM5_1)
534 #define MOD_SEL1_3		FM(SEL_PWM4_0)		FM(SEL_PWM4_1)
535 #define MOD_SEL1_2		FM(SEL_PWM3_0)		FM(SEL_PWM3_1)
536 #define MOD_SEL1_1		FM(SEL_PWM2_0)		FM(SEL_PWM2_1)
537 #define MOD_SEL1_0		FM(SEL_PWM1_0)		FM(SEL_PWM1_1)
538 
539 /* MOD_SEL2 */			/* 0 */			/* 1 */			/* 2 */			/* 3 */			/* 4 */			/* 5 */			/* 6 */			/* 7 */
540 #define MOD_SEL2_31		FM(I2C_SEL_5_0)		FM(I2C_SEL_5_1)
541 #define MOD_SEL2_30		FM(I2C_SEL_3_0)		FM(I2C_SEL_3_1)
542 #define MOD_SEL2_29		FM(I2C_SEL_0_0)		FM(I2C_SEL_0_1)
543 #define MOD_SEL2_28_27		FM(SEL_FM_0)		FM(SEL_FM_1)		FM(SEL_FM_2)		FM(SEL_FM_3)
544 #define MOD_SEL2_26		FM(SEL_SCIF5_0)		FM(SEL_SCIF5_1)
545 #define MOD_SEL2_25_24_23	FM(SEL_I2C6_0)		FM(SEL_I2C6_1)		FM(SEL_I2C6_2)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)
546 #define MOD_SEL2_22		FM(SEL_NDF_0)		FM(SEL_NDF_1)
547 #define MOD_SEL2_21		FM(SEL_SSI2_0)		FM(SEL_SSI2_1)
548 #define MOD_SEL2_20		FM(SEL_SSI9_0)		FM(SEL_SSI9_1)
549 #define MOD_SEL2_19		FM(SEL_TIMER_TMU2_0)	FM(SEL_TIMER_TMU2_1)
550 #define MOD_SEL2_18		FM(SEL_ADGB_0)		FM(SEL_ADGB_1)
551 #define MOD_SEL2_17		FM(SEL_ADGC_0)		FM(SEL_ADGC_1)
552 #define MOD_SEL2_0		FM(SEL_VIN4_0)		FM(SEL_VIN4_1)
553 
554 #define PINMUX_MOD_SELS	\
555 \
556 MOD_SEL0_31_30_29	MOD_SEL1_31_30		MOD_SEL2_31 \
557 						MOD_SEL2_30 \
558 			MOD_SEL1_29_28_27	MOD_SEL2_29 \
559 MOD_SEL0_28_27					MOD_SEL2_28_27 \
560 MOD_SEL0_26_25_24	MOD_SEL1_26		MOD_SEL2_26 \
561 			MOD_SEL1_25_24		MOD_SEL2_25_24_23 \
562 MOD_SEL0_23		MOD_SEL1_23_22_21 \
563 MOD_SEL0_22					MOD_SEL2_22 \
564 MOD_SEL0_21					MOD_SEL2_21 \
565 MOD_SEL0_20		MOD_SEL1_20		MOD_SEL2_20 \
566 MOD_SEL0_19		MOD_SEL1_19		MOD_SEL2_19 \
567 MOD_SEL0_18_17		MOD_SEL1_18_17		MOD_SEL2_18 \
568 						MOD_SEL2_17 \
569 MOD_SEL0_16		MOD_SEL1_16 \
570 			MOD_SEL1_15_14 \
571 MOD_SEL0_14_13 \
572 			MOD_SEL1_13 \
573 MOD_SEL0_12		MOD_SEL1_12 \
574 MOD_SEL0_11		MOD_SEL1_11 \
575 MOD_SEL0_10		MOD_SEL1_10 \
576 MOD_SEL0_9_8		MOD_SEL1_9 \
577 MOD_SEL0_7_6 \
578 			MOD_SEL1_6 \
579 MOD_SEL0_5		MOD_SEL1_5 \
580 MOD_SEL0_4_3		MOD_SEL1_4 \
581 			MOD_SEL1_3 \
582 			MOD_SEL1_2 \
583 			MOD_SEL1_1 \
584 			MOD_SEL1_0		MOD_SEL2_0
585 
586 /*
587  * These pins are not able to be muxed but have other properties
588  * that can be set, such as drive-strength or pull-up/pull-down enable.
589  */
590 #define PINMUX_STATIC \
591 	FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
592 	FM(QSPI0_IO2) FM(QSPI0_IO3) \
593 	FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
594 	FM(QSPI1_IO2) FM(QSPI1_IO3) \
595 	FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
596 	FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
597 	FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
598 	FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
599 	FM(PRESETOUT) \
600 	FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) \
601 	FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
602 
603 #define PINMUX_PHYS \
604 	FM(SCL0) FM(SDA0) FM(SCL3) FM(SDA3) FM(SCL5) FM(SDA5)
605 
606 enum {
607 	PINMUX_RESERVED = 0,
608 
609 	PINMUX_DATA_BEGIN,
610 	GP_ALL(DATA),
611 	PINMUX_DATA_END,
612 
613 #define F_(x, y)
614 #define FM(x)	FN_##x,
615 	PINMUX_FUNCTION_BEGIN,
616 	GP_ALL(FN),
617 	PINMUX_GPSR
618 	PINMUX_IPSR
619 	PINMUX_MOD_SELS
620 	PINMUX_FUNCTION_END,
621 #undef F_
622 #undef FM
623 
624 #define F_(x, y)
625 #define FM(x)	x##_MARK,
626 	PINMUX_MARK_BEGIN,
627 	PINMUX_GPSR
628 	PINMUX_IPSR
629 	PINMUX_MOD_SELS
630 	PINMUX_STATIC
631 	PINMUX_PHYS
632 	PINMUX_MARK_END,
633 #undef F_
634 #undef FM
635 };
636 
637 static const u16 pinmux_data[] = {
638 	PINMUX_DATA_GP_ALL(),
639 
640 	PINMUX_SINGLE(AVS1),
641 	PINMUX_SINGLE(AVS2),
642 	PINMUX_SINGLE(CLKOUT),
643 	PINMUX_SINGLE(GP7_03),
644 	PINMUX_SINGLE(GP7_02),
645 	PINMUX_SINGLE(MSIOF0_RXD),
646 	PINMUX_SINGLE(MSIOF0_SCK),
647 	PINMUX_SINGLE(MSIOF0_TXD),
648 	PINMUX_SINGLE(SSI_SCK5),
649 	PINMUX_SINGLE(SSI_SDATA5),
650 	PINMUX_SINGLE(SSI_WS5),
651 
652 	/* IPSR0 */
653 	PINMUX_IPSR_GPSR(IP0_3_0,	AVB_MDC),
654 	PINMUX_IPSR_MSEL(IP0_3_0,	MSIOF2_SS2_C,		SEL_MSIOF2_2),
655 
656 	PINMUX_IPSR_GPSR(IP0_7_4,	AVB_MAGIC),
657 	PINMUX_IPSR_MSEL(IP0_7_4,	MSIOF2_SS1_C,		SEL_MSIOF2_2),
658 	PINMUX_IPSR_MSEL(IP0_7_4,	SCK4_A,			SEL_SCIF4_0),
659 
660 	PINMUX_IPSR_GPSR(IP0_11_8,	AVB_PHY_INT),
661 	PINMUX_IPSR_MSEL(IP0_11_8,	MSIOF2_SYNC_C,		SEL_MSIOF2_2),
662 	PINMUX_IPSR_MSEL(IP0_11_8,	RX4_A,			SEL_SCIF4_0),
663 
664 	PINMUX_IPSR_GPSR(IP0_15_12,	AVB_LINK),
665 	PINMUX_IPSR_MSEL(IP0_15_12,	MSIOF2_SCK_C,		SEL_MSIOF2_2),
666 	PINMUX_IPSR_MSEL(IP0_15_12,	TX4_A,			SEL_SCIF4_0),
667 
668 	PINMUX_IPSR_PHYS_MSEL(IP0_19_16, AVB_AVTP_MATCH_A,	I2C_SEL_5_0,	SEL_ETHERAVB_0),
669 	PINMUX_IPSR_PHYS_MSEL(IP0_19_16, MSIOF2_RXD_C,		I2C_SEL_5_0,	SEL_MSIOF2_2),
670 	PINMUX_IPSR_PHYS_MSEL(IP0_19_16, CTS4_N_A,		I2C_SEL_5_0,	SEL_SCIF4_0),
671 	PINMUX_IPSR_PHYS(IP0_19_16,	SCL5,			I2C_SEL_5_1),
672 
673 	PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A,	I2C_SEL_5_0,	SEL_ETHERAVB_0),
674 	PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C,		I2C_SEL_5_0,	SEL_MSIOF2_2),
675 	PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A,		I2C_SEL_5_0,	SEL_SCIF4_0),
676 	PINMUX_IPSR_PHYS(IP0_23_20,	SDA5,			I2C_SEL_5_1),
677 
678 	PINMUX_IPSR_GPSR(IP0_27_24,	IRQ0),
679 	PINMUX_IPSR_GPSR(IP0_27_24,	QPOLB),
680 	PINMUX_IPSR_GPSR(IP0_27_24,	DU_CDE),
681 	PINMUX_IPSR_MSEL(IP0_27_24,	VI4_DATA0_B,		SEL_VIN4_1),
682 	PINMUX_IPSR_MSEL(IP0_27_24,	CAN0_TX_B,		SEL_RCAN0_1),
683 	PINMUX_IPSR_MSEL(IP0_27_24,	CANFD0_TX_B,		SEL_CANFD0_1),
684 	PINMUX_IPSR_MSEL(IP0_27_24,	MSIOF3_SS2_E,		SEL_MSIOF3_4),
685 
686 	PINMUX_IPSR_GPSR(IP0_31_28,	IRQ1),
687 	PINMUX_IPSR_GPSR(IP0_31_28,	QPOLA),
688 	PINMUX_IPSR_GPSR(IP0_31_28,	DU_DISP),
689 	PINMUX_IPSR_MSEL(IP0_31_28,	VI4_DATA1_B,		SEL_VIN4_1),
690 	PINMUX_IPSR_MSEL(IP0_31_28,	CAN0_RX_B,		SEL_RCAN0_1),
691 	PINMUX_IPSR_MSEL(IP0_31_28,	CANFD0_RX_B,		SEL_CANFD0_1),
692 	PINMUX_IPSR_MSEL(IP0_31_28,	MSIOF3_SS1_E,		SEL_MSIOF3_4),
693 
694 	/* IPSR1 */
695 	PINMUX_IPSR_GPSR(IP1_3_0,	IRQ2),
696 	PINMUX_IPSR_GPSR(IP1_3_0,	QCPV_QDE),
697 	PINMUX_IPSR_GPSR(IP1_3_0,	DU_EXODDF_DU_ODDF_DISP_CDE),
698 	PINMUX_IPSR_MSEL(IP1_3_0,	VI4_DATA2_B,		SEL_VIN4_1),
699 	PINMUX_IPSR_MSEL(IP1_3_0,	PWM3_B,			SEL_PWM3_1),
700 	PINMUX_IPSR_MSEL(IP1_3_0,	MSIOF3_SYNC_E,		SEL_MSIOF3_4),
701 
702 	PINMUX_IPSR_GPSR(IP1_7_4,	IRQ3),
703 	PINMUX_IPSR_GPSR(IP1_7_4,	QSTVB_QVE),
704 	PINMUX_IPSR_GPSR(IP1_7_4,	DU_DOTCLKOUT1),
705 	PINMUX_IPSR_MSEL(IP1_7_4,	VI4_DATA3_B,		SEL_VIN4_1),
706 	PINMUX_IPSR_MSEL(IP1_7_4,	PWM4_B,			SEL_PWM4_1),
707 	PINMUX_IPSR_MSEL(IP1_7_4,	MSIOF3_SCK_E,		SEL_MSIOF3_4),
708 
709 	PINMUX_IPSR_GPSR(IP1_11_8,	IRQ4),
710 	PINMUX_IPSR_GPSR(IP1_11_8,	QSTH_QHS),
711 	PINMUX_IPSR_GPSR(IP1_11_8,	DU_EXHSYNC_DU_HSYNC),
712 	PINMUX_IPSR_MSEL(IP1_11_8,	VI4_DATA4_B,		SEL_VIN4_1),
713 	PINMUX_IPSR_MSEL(IP1_11_8,	PWM5_B,			SEL_PWM5_1),
714 	PINMUX_IPSR_MSEL(IP1_11_8,	MSIOF3_RXD_E,		SEL_MSIOF3_4),
715 
716 	PINMUX_IPSR_GPSR(IP1_15_12,	IRQ5),
717 	PINMUX_IPSR_GPSR(IP1_15_12,	QSTB_QHE),
718 	PINMUX_IPSR_GPSR(IP1_15_12,	DU_EXVSYNC_DU_VSYNC),
719 	PINMUX_IPSR_MSEL(IP1_15_12,	VI4_DATA5_B,		SEL_VIN4_1),
720 	PINMUX_IPSR_MSEL(IP1_15_12,	PWM6_B,			SEL_PWM6_1),
721 	PINMUX_IPSR_MSEL(IP1_15_12,	MSIOF3_TXD_E,		SEL_MSIOF3_4),
722 
723 	PINMUX_IPSR_GPSR(IP1_19_16,	PWM0),
724 	PINMUX_IPSR_GPSR(IP1_19_16,	AVB_AVTP_PPS),
725 	PINMUX_IPSR_MSEL(IP1_19_16,	VI4_DATA6_B,		SEL_VIN4_1),
726 	PINMUX_IPSR_MSEL(IP1_19_16,	IECLK_B,		SEL_IEBUS_1),
727 
728 	PINMUX_IPSR_PHYS_MSEL(IP1_23_20, PWM1_A,		I2C_SEL_3_0,	SEL_PWM1_0),
729 	PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D,		I2C_SEL_3_0,	SEL_HSCIF3_3),
730 	PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B,		I2C_SEL_3_0,	SEL_VIN4_1),
731 	PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B,		I2C_SEL_3_0,	SEL_IEBUS_1),
732 	PINMUX_IPSR_PHYS(IP1_23_20,	SCL3,			I2C_SEL_3_1),
733 
734 	PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A,		I2C_SEL_3_0,	SEL_PWM2_0),
735 	PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D,		I2C_SEL_3_0,	SEL_HSCIF3_3),
736 	PINMUX_IPSR_PHYS_MSEL(IP1_27_24, IETX_B,		I2C_SEL_3_0,	SEL_IEBUS_1),
737 	PINMUX_IPSR_PHYS(IP1_27_24,	SDA3,			I2C_SEL_3_1),
738 
739 	PINMUX_IPSR_GPSR(IP1_31_28,	A0),
740 	PINMUX_IPSR_GPSR(IP1_31_28,	LCDOUT16),
741 	PINMUX_IPSR_MSEL(IP1_31_28,	MSIOF3_SYNC_B,		SEL_MSIOF3_1),
742 	PINMUX_IPSR_GPSR(IP1_31_28,	VI4_DATA8),
743 	PINMUX_IPSR_GPSR(IP1_31_28,	DU_DB0),
744 	PINMUX_IPSR_MSEL(IP1_31_28,	PWM3_A,			SEL_PWM3_0),
745 
746 	/* IPSR2 */
747 	PINMUX_IPSR_GPSR(IP2_3_0,	A1),
748 	PINMUX_IPSR_GPSR(IP2_3_0,	LCDOUT17),
749 	PINMUX_IPSR_MSEL(IP2_3_0,	MSIOF3_TXD_B,		SEL_MSIOF3_1),
750 	PINMUX_IPSR_GPSR(IP2_3_0,	VI4_DATA9),
751 	PINMUX_IPSR_GPSR(IP2_3_0,	DU_DB1),
752 	PINMUX_IPSR_MSEL(IP2_3_0,	PWM4_A,			SEL_PWM4_0),
753 
754 	PINMUX_IPSR_GPSR(IP2_7_4,	A2),
755 	PINMUX_IPSR_GPSR(IP2_7_4,	LCDOUT18),
756 	PINMUX_IPSR_MSEL(IP2_7_4,	MSIOF3_SCK_B,		SEL_MSIOF3_1),
757 	PINMUX_IPSR_GPSR(IP2_7_4,	VI4_DATA10),
758 	PINMUX_IPSR_GPSR(IP2_7_4,	DU_DB2),
759 	PINMUX_IPSR_MSEL(IP2_7_4,	PWM5_A,			SEL_PWM5_0),
760 
761 	PINMUX_IPSR_GPSR(IP2_11_8,	A3),
762 	PINMUX_IPSR_GPSR(IP2_11_8,	LCDOUT19),
763 	PINMUX_IPSR_MSEL(IP2_11_8,	MSIOF3_RXD_B,		SEL_MSIOF3_1),
764 	PINMUX_IPSR_GPSR(IP2_11_8,	VI4_DATA11),
765 	PINMUX_IPSR_GPSR(IP2_11_8,	DU_DB3),
766 	PINMUX_IPSR_MSEL(IP2_11_8,	PWM6_A,			SEL_PWM6_0),
767 
768 	PINMUX_IPSR_GPSR(IP2_15_12,	A4),
769 	PINMUX_IPSR_GPSR(IP2_15_12,	LCDOUT20),
770 	PINMUX_IPSR_MSEL(IP2_15_12,	MSIOF3_SS1_B,		SEL_MSIOF3_1),
771 	PINMUX_IPSR_GPSR(IP2_15_12,	VI4_DATA12),
772 	PINMUX_IPSR_GPSR(IP2_15_12,	VI5_DATA12),
773 	PINMUX_IPSR_GPSR(IP2_15_12,	DU_DB4),
774 
775 	PINMUX_IPSR_GPSR(IP2_19_16,	A5),
776 	PINMUX_IPSR_GPSR(IP2_19_16,	LCDOUT21),
777 	PINMUX_IPSR_MSEL(IP2_19_16,	MSIOF3_SS2_B,		SEL_MSIOF3_1),
778 	PINMUX_IPSR_MSEL(IP2_19_16,	SCK4_B,			SEL_SCIF4_1),
779 	PINMUX_IPSR_GPSR(IP2_19_16,	VI4_DATA13),
780 	PINMUX_IPSR_GPSR(IP2_19_16,	VI5_DATA13),
781 	PINMUX_IPSR_GPSR(IP2_19_16,	DU_DB5),
782 
783 	PINMUX_IPSR_GPSR(IP2_23_20,	A6),
784 	PINMUX_IPSR_GPSR(IP2_23_20,	LCDOUT22),
785 	PINMUX_IPSR_MSEL(IP2_23_20,	MSIOF2_SS1_A,		SEL_MSIOF2_0),
786 	PINMUX_IPSR_MSEL(IP2_23_20,	RX4_B,			SEL_SCIF4_1),
787 	PINMUX_IPSR_GPSR(IP2_23_20,	VI4_DATA14),
788 	PINMUX_IPSR_GPSR(IP2_23_20,	VI5_DATA14),
789 	PINMUX_IPSR_GPSR(IP2_23_20,	DU_DB6),
790 
791 	PINMUX_IPSR_GPSR(IP2_27_24,	A7),
792 	PINMUX_IPSR_GPSR(IP2_27_24,	LCDOUT23),
793 	PINMUX_IPSR_MSEL(IP2_27_24,	MSIOF2_SS2_A,		SEL_MSIOF2_0),
794 	PINMUX_IPSR_MSEL(IP2_27_24,	TX4_B,			SEL_SCIF4_1),
795 	PINMUX_IPSR_GPSR(IP2_27_24,	VI4_DATA15),
796 	PINMUX_IPSR_GPSR(IP2_27_24,	VI5_DATA15),
797 	PINMUX_IPSR_GPSR(IP2_27_24,	DU_DB7),
798 
799 	PINMUX_IPSR_GPSR(IP2_31_28,	A8),
800 	PINMUX_IPSR_MSEL(IP2_31_28,	RX3_B,			SEL_SCIF3_1),
801 	PINMUX_IPSR_MSEL(IP2_31_28,	MSIOF2_SYNC_A,		SEL_MSIOF2_0),
802 	PINMUX_IPSR_MSEL(IP2_31_28,	HRX4_B,			SEL_HSCIF4_1),
803 	PINMUX_IPSR_MSEL(IP2_31_28,	SDA6_A,			SEL_I2C6_0),
804 	PINMUX_IPSR_MSEL(IP2_31_28,	AVB_AVTP_MATCH_B,	SEL_ETHERAVB_1),
805 	PINMUX_IPSR_MSEL(IP2_31_28,	PWM1_B,			SEL_PWM1_1),
806 
807 	/* IPSR3 */
808 	PINMUX_IPSR_GPSR(IP3_3_0,	A9),
809 	PINMUX_IPSR_MSEL(IP3_3_0,	MSIOF2_SCK_A,		SEL_MSIOF2_0),
810 	PINMUX_IPSR_MSEL(IP3_3_0,	CTS4_N_B,		SEL_SCIF4_1),
811 	PINMUX_IPSR_GPSR(IP3_3_0,	VI5_VSYNC_N),
812 
813 	PINMUX_IPSR_GPSR(IP3_7_4,	A10),
814 	PINMUX_IPSR_MSEL(IP3_7_4,	MSIOF2_RXD_A,		SEL_MSIOF2_0),
815 	PINMUX_IPSR_MSEL(IP3_7_4,	RTS4_N_B,		SEL_SCIF4_1),
816 	PINMUX_IPSR_GPSR(IP3_7_4,	VI5_HSYNC_N),
817 
818 	PINMUX_IPSR_GPSR(IP3_11_8,	A11),
819 	PINMUX_IPSR_MSEL(IP3_11_8,	TX3_B,			SEL_SCIF3_1),
820 	PINMUX_IPSR_MSEL(IP3_11_8,	MSIOF2_TXD_A,		SEL_MSIOF2_0),
821 	PINMUX_IPSR_MSEL(IP3_11_8,	HTX4_B,			SEL_HSCIF4_1),
822 	PINMUX_IPSR_GPSR(IP3_11_8,	HSCK4),
823 	PINMUX_IPSR_GPSR(IP3_11_8,	VI5_FIELD),
824 	PINMUX_IPSR_MSEL(IP3_11_8,	SCL6_A,			SEL_I2C6_0),
825 	PINMUX_IPSR_MSEL(IP3_11_8,	AVB_AVTP_CAPTURE_B,	SEL_ETHERAVB_1),
826 	PINMUX_IPSR_MSEL(IP3_11_8,	PWM2_B,			SEL_PWM2_1),
827 
828 	PINMUX_IPSR_GPSR(IP3_15_12,	A12),
829 	PINMUX_IPSR_GPSR(IP3_15_12,	LCDOUT12),
830 	PINMUX_IPSR_MSEL(IP3_15_12,	MSIOF3_SCK_C,		SEL_MSIOF3_2),
831 	PINMUX_IPSR_MSEL(IP3_15_12,	HRX4_A,			SEL_HSCIF4_0),
832 	PINMUX_IPSR_GPSR(IP3_15_12,	VI5_DATA8),
833 	PINMUX_IPSR_GPSR(IP3_15_12,	DU_DG4),
834 
835 	PINMUX_IPSR_GPSR(IP3_19_16,	A13),
836 	PINMUX_IPSR_GPSR(IP3_19_16,	LCDOUT13),
837 	PINMUX_IPSR_MSEL(IP3_19_16,	MSIOF3_SYNC_C,		SEL_MSIOF3_2),
838 	PINMUX_IPSR_MSEL(IP3_19_16,	HTX4_A,			SEL_HSCIF4_0),
839 	PINMUX_IPSR_GPSR(IP3_19_16,	VI5_DATA9),
840 	PINMUX_IPSR_GPSR(IP3_19_16,	DU_DG5),
841 
842 	PINMUX_IPSR_GPSR(IP3_23_20,	A14),
843 	PINMUX_IPSR_GPSR(IP3_23_20,	LCDOUT14),
844 	PINMUX_IPSR_MSEL(IP3_23_20,	MSIOF3_RXD_C,		SEL_MSIOF3_2),
845 	PINMUX_IPSR_GPSR(IP3_23_20,	HCTS4_N),
846 	PINMUX_IPSR_GPSR(IP3_23_20,	VI5_DATA10),
847 	PINMUX_IPSR_GPSR(IP3_23_20,	DU_DG6),
848 
849 	PINMUX_IPSR_GPSR(IP3_27_24,	A15),
850 	PINMUX_IPSR_GPSR(IP3_27_24,	LCDOUT15),
851 	PINMUX_IPSR_MSEL(IP3_27_24,	MSIOF3_TXD_C,		SEL_MSIOF3_2),
852 	PINMUX_IPSR_GPSR(IP3_27_24,	HRTS4_N),
853 	PINMUX_IPSR_GPSR(IP3_27_24,	VI5_DATA11),
854 	PINMUX_IPSR_GPSR(IP3_27_24,	DU_DG7),
855 
856 	PINMUX_IPSR_GPSR(IP3_31_28,	A16),
857 	PINMUX_IPSR_GPSR(IP3_31_28,	LCDOUT8),
858 	PINMUX_IPSR_GPSR(IP3_31_28,	VI4_FIELD),
859 	PINMUX_IPSR_GPSR(IP3_31_28,	DU_DG0),
860 
861 	/* IPSR4 */
862 	PINMUX_IPSR_GPSR(IP4_3_0,	A17),
863 	PINMUX_IPSR_GPSR(IP4_3_0,	LCDOUT9),
864 	PINMUX_IPSR_GPSR(IP4_3_0,	VI4_VSYNC_N),
865 	PINMUX_IPSR_GPSR(IP4_3_0,	DU_DG1),
866 
867 	PINMUX_IPSR_GPSR(IP4_7_4,	A18),
868 	PINMUX_IPSR_GPSR(IP4_7_4,	LCDOUT10),
869 	PINMUX_IPSR_GPSR(IP4_7_4,	VI4_HSYNC_N),
870 	PINMUX_IPSR_GPSR(IP4_7_4,	DU_DG2),
871 
872 	PINMUX_IPSR_GPSR(IP4_11_8,	A19),
873 	PINMUX_IPSR_GPSR(IP4_11_8,	LCDOUT11),
874 	PINMUX_IPSR_GPSR(IP4_11_8,	VI4_CLKENB),
875 	PINMUX_IPSR_GPSR(IP4_11_8,	DU_DG3),
876 
877 	PINMUX_IPSR_GPSR(IP4_15_12,	CS0_N),
878 	PINMUX_IPSR_GPSR(IP4_15_12,	VI5_CLKENB),
879 
880 	PINMUX_IPSR_GPSR(IP4_19_16,	CS1_N),
881 	PINMUX_IPSR_GPSR(IP4_19_16,	VI5_CLK),
882 	PINMUX_IPSR_MSEL(IP4_19_16,	EX_WAIT0_B,		SEL_LBSC_1),
883 
884 	PINMUX_IPSR_GPSR(IP4_23_20,	BS_N),
885 	PINMUX_IPSR_GPSR(IP4_23_20,	QSTVA_QVS),
886 	PINMUX_IPSR_MSEL(IP4_23_20,	MSIOF3_SCK_D,		SEL_MSIOF3_3),
887 	PINMUX_IPSR_GPSR(IP4_23_20,	SCK3),
888 	PINMUX_IPSR_GPSR(IP4_23_20,	HSCK3),
889 	PINMUX_IPSR_GPSR(IP4_23_20,	CAN1_TX),
890 	PINMUX_IPSR_GPSR(IP4_23_20,	CANFD1_TX),
891 	PINMUX_IPSR_MSEL(IP4_23_20,	IETX_A,			SEL_IEBUS_0),
892 
893 	PINMUX_IPSR_GPSR(IP4_27_24,	RD_N),
894 	PINMUX_IPSR_MSEL(IP4_27_24,	MSIOF3_SYNC_D,		SEL_MSIOF3_3),
895 	PINMUX_IPSR_MSEL(IP4_27_24,	RX3_A,			SEL_SCIF3_0),
896 	PINMUX_IPSR_MSEL(IP4_27_24,	HRX3_A,			SEL_HSCIF3_0),
897 	PINMUX_IPSR_MSEL(IP4_27_24,	CAN0_TX_A,		SEL_RCAN0_0),
898 	PINMUX_IPSR_MSEL(IP4_27_24,	CANFD0_TX_A,		SEL_CANFD0_0),
899 
900 	PINMUX_IPSR_GPSR(IP4_31_28,	RD_WR_N),
901 	PINMUX_IPSR_MSEL(IP4_31_28,	MSIOF3_RXD_D,		SEL_MSIOF3_3),
902 	PINMUX_IPSR_MSEL(IP4_31_28,	TX3_A,			SEL_SCIF3_0),
903 	PINMUX_IPSR_MSEL(IP4_31_28,	HTX3_A,			SEL_HSCIF3_0),
904 	PINMUX_IPSR_MSEL(IP4_31_28,	CAN0_RX_A,		SEL_RCAN0_0),
905 	PINMUX_IPSR_MSEL(IP4_31_28,	CANFD0_RX_A,		SEL_CANFD0_0),
906 
907 	/* IPSR5 */
908 	PINMUX_IPSR_GPSR(IP5_3_0,	WE0_N),
909 	PINMUX_IPSR_MSEL(IP5_3_0,	MSIOF3_TXD_D,		SEL_MSIOF3_3),
910 	PINMUX_IPSR_GPSR(IP5_3_0,	CTS3_N),
911 	PINMUX_IPSR_GPSR(IP5_3_0,	HCTS3_N),
912 	PINMUX_IPSR_MSEL(IP5_3_0,	SCL6_B,			SEL_I2C6_1),
913 	PINMUX_IPSR_GPSR(IP5_3_0,	CAN_CLK),
914 	PINMUX_IPSR_MSEL(IP5_3_0,	IECLK_A,		SEL_IEBUS_0),
915 
916 	PINMUX_IPSR_GPSR(IP5_7_4,	WE1_N),
917 	PINMUX_IPSR_MSEL(IP5_7_4,	MSIOF3_SS1_D,		SEL_MSIOF3_3),
918 	PINMUX_IPSR_GPSR(IP5_7_4,	RTS3_N),
919 	PINMUX_IPSR_GPSR(IP5_7_4,	HRTS3_N),
920 	PINMUX_IPSR_MSEL(IP5_7_4,	SDA6_B,			SEL_I2C6_1),
921 	PINMUX_IPSR_GPSR(IP5_7_4,	CAN1_RX),
922 	PINMUX_IPSR_GPSR(IP5_7_4,	CANFD1_RX),
923 	PINMUX_IPSR_MSEL(IP5_7_4,	IERX_A,			SEL_IEBUS_0),
924 
925 	PINMUX_IPSR_MSEL(IP5_11_8,	EX_WAIT0_A,		SEL_LBSC_0),
926 	PINMUX_IPSR_GPSR(IP5_11_8,	QCLK),
927 	PINMUX_IPSR_GPSR(IP5_11_8,	VI4_CLK),
928 	PINMUX_IPSR_GPSR(IP5_11_8,	DU_DOTCLKOUT0),
929 
930 	PINMUX_IPSR_GPSR(IP5_15_12,	D0),
931 	PINMUX_IPSR_MSEL(IP5_15_12,	MSIOF2_SS1_B,		SEL_MSIOF2_1),
932 	PINMUX_IPSR_MSEL(IP5_15_12,	MSIOF3_SCK_A,		SEL_MSIOF3_0),
933 	PINMUX_IPSR_GPSR(IP5_15_12,	VI4_DATA16),
934 	PINMUX_IPSR_GPSR(IP5_15_12,	VI5_DATA0),
935 
936 	PINMUX_IPSR_GPSR(IP5_19_16,	D1),
937 	PINMUX_IPSR_MSEL(IP5_19_16,	MSIOF2_SS2_B,		SEL_MSIOF2_1),
938 	PINMUX_IPSR_MSEL(IP5_19_16,	MSIOF3_SYNC_A,		SEL_MSIOF3_0),
939 	PINMUX_IPSR_GPSR(IP5_19_16,	VI4_DATA17),
940 	PINMUX_IPSR_GPSR(IP5_19_16,	VI5_DATA1),
941 
942 	PINMUX_IPSR_GPSR(IP5_23_20,	D2),
943 	PINMUX_IPSR_MSEL(IP5_23_20,	MSIOF3_RXD_A,		SEL_MSIOF3_0),
944 	PINMUX_IPSR_GPSR(IP5_23_20,	VI4_DATA18),
945 	PINMUX_IPSR_GPSR(IP5_23_20,	VI5_DATA2),
946 
947 	PINMUX_IPSR_GPSR(IP5_27_24,	D3),
948 	PINMUX_IPSR_MSEL(IP5_27_24,	MSIOF3_TXD_A,		SEL_MSIOF3_0),
949 	PINMUX_IPSR_GPSR(IP5_27_24,	VI4_DATA19),
950 	PINMUX_IPSR_GPSR(IP5_27_24,	VI5_DATA3),
951 
952 	PINMUX_IPSR_GPSR(IP5_31_28,	D4),
953 	PINMUX_IPSR_MSEL(IP5_31_28,	MSIOF2_SCK_B,		SEL_MSIOF2_1),
954 	PINMUX_IPSR_GPSR(IP5_31_28,	VI4_DATA20),
955 	PINMUX_IPSR_GPSR(IP5_31_28,	VI5_DATA4),
956 
957 	/* IPSR6 */
958 	PINMUX_IPSR_GPSR(IP6_3_0,	D5),
959 	PINMUX_IPSR_MSEL(IP6_3_0,	MSIOF2_SYNC_B,		SEL_MSIOF2_1),
960 	PINMUX_IPSR_GPSR(IP6_3_0,	VI4_DATA21),
961 	PINMUX_IPSR_GPSR(IP6_3_0,	VI5_DATA5),
962 
963 	PINMUX_IPSR_GPSR(IP6_7_4,	D6),
964 	PINMUX_IPSR_MSEL(IP6_7_4,	MSIOF2_RXD_B,		SEL_MSIOF2_1),
965 	PINMUX_IPSR_GPSR(IP6_7_4,	VI4_DATA22),
966 	PINMUX_IPSR_GPSR(IP6_7_4,	VI5_DATA6),
967 
968 	PINMUX_IPSR_GPSR(IP6_11_8,	D7),
969 	PINMUX_IPSR_MSEL(IP6_11_8,	MSIOF2_TXD_B,		SEL_MSIOF2_1),
970 	PINMUX_IPSR_GPSR(IP6_11_8,	VI4_DATA23),
971 	PINMUX_IPSR_GPSR(IP6_11_8,	VI5_DATA7),
972 
973 	PINMUX_IPSR_GPSR(IP6_15_12,	D8),
974 	PINMUX_IPSR_GPSR(IP6_15_12,	LCDOUT0),
975 	PINMUX_IPSR_MSEL(IP6_15_12,	MSIOF2_SCK_D,		SEL_MSIOF2_3),
976 	PINMUX_IPSR_MSEL(IP6_15_12,	SCK4_C,			SEL_SCIF4_2),
977 	PINMUX_IPSR_MSEL(IP6_15_12,	VI4_DATA0_A,		SEL_VIN4_0),
978 	PINMUX_IPSR_GPSR(IP6_15_12,	DU_DR0),
979 
980 	PINMUX_IPSR_GPSR(IP6_19_16,	D9),
981 	PINMUX_IPSR_GPSR(IP6_19_16,	LCDOUT1),
982 	PINMUX_IPSR_MSEL(IP6_19_16,	MSIOF2_SYNC_D,		SEL_MSIOF2_3),
983 	PINMUX_IPSR_MSEL(IP6_19_16,	VI4_DATA1_A,		SEL_VIN4_0),
984 	PINMUX_IPSR_GPSR(IP6_19_16,	DU_DR1),
985 
986 	PINMUX_IPSR_GPSR(IP6_23_20,	D10),
987 	PINMUX_IPSR_GPSR(IP6_23_20,	LCDOUT2),
988 	PINMUX_IPSR_MSEL(IP6_23_20,	MSIOF2_RXD_D,		SEL_MSIOF2_3),
989 	PINMUX_IPSR_MSEL(IP6_23_20,	HRX3_B,			SEL_HSCIF3_1),
990 	PINMUX_IPSR_MSEL(IP6_23_20,	VI4_DATA2_A,		SEL_VIN4_0),
991 	PINMUX_IPSR_MSEL(IP6_23_20,	CTS4_N_C,		SEL_SCIF4_2),
992 	PINMUX_IPSR_GPSR(IP6_23_20,	DU_DR2),
993 
994 	PINMUX_IPSR_GPSR(IP6_27_24,	D11),
995 	PINMUX_IPSR_GPSR(IP6_27_24,	LCDOUT3),
996 	PINMUX_IPSR_MSEL(IP6_27_24,	MSIOF2_TXD_D,		SEL_MSIOF2_3),
997 	PINMUX_IPSR_MSEL(IP6_27_24,	HTX3_B,			SEL_HSCIF3_1),
998 	PINMUX_IPSR_MSEL(IP6_27_24,	VI4_DATA3_A,		SEL_VIN4_0),
999 	PINMUX_IPSR_MSEL(IP6_27_24,	RTS4_N_C,		SEL_SCIF4_2),
1000 	PINMUX_IPSR_GPSR(IP6_27_24,	DU_DR3),
1001 
1002 	PINMUX_IPSR_GPSR(IP6_31_28,	D12),
1003 	PINMUX_IPSR_GPSR(IP6_31_28,	LCDOUT4),
1004 	PINMUX_IPSR_MSEL(IP6_31_28,	MSIOF2_SS1_D,		SEL_MSIOF2_3),
1005 	PINMUX_IPSR_MSEL(IP6_31_28,	RX4_C,			SEL_SCIF4_2),
1006 	PINMUX_IPSR_MSEL(IP6_31_28,	VI4_DATA4_A,		SEL_VIN4_0),
1007 	PINMUX_IPSR_GPSR(IP6_31_28,	DU_DR4),
1008 
1009 	/* IPSR7 */
1010 	PINMUX_IPSR_GPSR(IP7_3_0,	D13),
1011 	PINMUX_IPSR_GPSR(IP7_3_0,	LCDOUT5),
1012 	PINMUX_IPSR_MSEL(IP7_3_0,	MSIOF2_SS2_D,		SEL_MSIOF2_3),
1013 	PINMUX_IPSR_MSEL(IP7_3_0,	TX4_C,			SEL_SCIF4_2),
1014 	PINMUX_IPSR_MSEL(IP7_3_0,	VI4_DATA5_A,		SEL_VIN4_0),
1015 	PINMUX_IPSR_GPSR(IP7_3_0,	DU_DR5),
1016 
1017 	PINMUX_IPSR_GPSR(IP7_7_4,	D14),
1018 	PINMUX_IPSR_GPSR(IP7_7_4,	LCDOUT6),
1019 	PINMUX_IPSR_MSEL(IP7_7_4,	MSIOF3_SS1_A,		SEL_MSIOF3_0),
1020 	PINMUX_IPSR_MSEL(IP7_7_4,	HRX3_C,			SEL_HSCIF3_2),
1021 	PINMUX_IPSR_MSEL(IP7_7_4,	VI4_DATA6_A,		SEL_VIN4_0),
1022 	PINMUX_IPSR_GPSR(IP7_7_4,	DU_DR6),
1023 	PINMUX_IPSR_MSEL(IP7_7_4,	SCL6_C,			SEL_I2C6_2),
1024 
1025 	PINMUX_IPSR_GPSR(IP7_11_8,	D15),
1026 	PINMUX_IPSR_GPSR(IP7_11_8,	LCDOUT7),
1027 	PINMUX_IPSR_MSEL(IP7_11_8,	MSIOF3_SS2_A,		SEL_MSIOF3_0),
1028 	PINMUX_IPSR_MSEL(IP7_11_8,	HTX3_C,			SEL_HSCIF3_2),
1029 	PINMUX_IPSR_MSEL(IP7_11_8,	VI4_DATA7_A,		SEL_VIN4_0),
1030 	PINMUX_IPSR_GPSR(IP7_11_8,	DU_DR7),
1031 	PINMUX_IPSR_MSEL(IP7_11_8,	SDA6_C,			SEL_I2C6_2),
1032 
1033 	PINMUX_IPSR_GPSR(IP7_19_16,	SD0_CLK),
1034 	PINMUX_IPSR_MSEL(IP7_19_16,	MSIOF1_SCK_E,		SEL_MSIOF1_4),
1035 	PINMUX_IPSR_MSEL(IP7_19_16,	STP_OPWM_0_B,		SEL_SSP1_0_1),
1036 
1037 	PINMUX_IPSR_GPSR(IP7_23_20,	SD0_CMD),
1038 	PINMUX_IPSR_MSEL(IP7_23_20,	MSIOF1_SYNC_E,		SEL_MSIOF1_4),
1039 	PINMUX_IPSR_MSEL(IP7_23_20,	STP_IVCXO27_0_B,	SEL_SSP1_0_1),
1040 
1041 	PINMUX_IPSR_GPSR(IP7_27_24,	SD0_DAT0),
1042 	PINMUX_IPSR_MSEL(IP7_27_24,	MSIOF1_RXD_E,		SEL_MSIOF1_4),
1043 	PINMUX_IPSR_MSEL(IP7_27_24,	TS_SCK0_B,		SEL_TSIF0_1),
1044 	PINMUX_IPSR_MSEL(IP7_27_24,	STP_ISCLK_0_B,		SEL_SSP1_0_1),
1045 
1046 	PINMUX_IPSR_GPSR(IP7_31_28,	SD0_DAT1),
1047 	PINMUX_IPSR_MSEL(IP7_31_28,	MSIOF1_TXD_E,		SEL_MSIOF1_4),
1048 	PINMUX_IPSR_MSEL(IP7_31_28,	TS_SPSYNC0_B,		SEL_TSIF0_1),
1049 	PINMUX_IPSR_MSEL(IP7_31_28,	STP_ISSYNC_0_B,		SEL_SSP1_0_1),
1050 
1051 	/* IPSR8 */
1052 	PINMUX_IPSR_GPSR(IP8_3_0,	SD0_DAT2),
1053 	PINMUX_IPSR_MSEL(IP8_3_0,	MSIOF1_SS1_E,		SEL_MSIOF1_4),
1054 	PINMUX_IPSR_MSEL(IP8_3_0,	TS_SDAT0_B,		SEL_TSIF0_1),
1055 	PINMUX_IPSR_MSEL(IP8_3_0,	STP_ISD_0_B,		SEL_SSP1_0_1),
1056 
1057 	PINMUX_IPSR_GPSR(IP8_7_4,	SD0_DAT3),
1058 	PINMUX_IPSR_MSEL(IP8_7_4,	MSIOF1_SS2_E,		SEL_MSIOF1_4),
1059 	PINMUX_IPSR_MSEL(IP8_7_4,	TS_SDEN0_B,		SEL_TSIF0_1),
1060 	PINMUX_IPSR_MSEL(IP8_7_4,	STP_ISEN_0_B,		SEL_SSP1_0_1),
1061 
1062 	PINMUX_IPSR_GPSR(IP8_11_8,	SD1_CLK),
1063 	PINMUX_IPSR_MSEL(IP8_11_8,	MSIOF1_SCK_G,		SEL_MSIOF1_6),
1064 	PINMUX_IPSR_MSEL(IP8_11_8,	SIM0_CLK_A,		SEL_SIMCARD_0),
1065 
1066 	PINMUX_IPSR_GPSR(IP8_15_12,	SD1_CMD),
1067 	PINMUX_IPSR_MSEL(IP8_15_12,	MSIOF1_SYNC_G,		SEL_MSIOF1_6),
1068 	PINMUX_IPSR_MSEL(IP8_15_12,	NFCE_N_B,		SEL_NDF_1),
1069 	PINMUX_IPSR_MSEL(IP8_15_12,	SIM0_D_A,		SEL_SIMCARD_0),
1070 	PINMUX_IPSR_MSEL(IP8_15_12,	STP_IVCXO27_1_B,	SEL_SSP1_1_1),
1071 
1072 	PINMUX_IPSR_GPSR(IP8_19_16,	SD1_DAT0),
1073 	PINMUX_IPSR_GPSR(IP8_19_16,	SD2_DAT4),
1074 	PINMUX_IPSR_MSEL(IP8_19_16,	MSIOF1_RXD_G,		SEL_MSIOF1_6),
1075 	PINMUX_IPSR_MSEL(IP8_19_16,	NFWP_N_B,		SEL_NDF_1),
1076 	PINMUX_IPSR_MSEL(IP8_19_16,	TS_SCK1_B,		SEL_TSIF1_1),
1077 	PINMUX_IPSR_MSEL(IP8_19_16,	STP_ISCLK_1_B,		SEL_SSP1_1_1),
1078 
1079 	PINMUX_IPSR_GPSR(IP8_23_20,	SD1_DAT1),
1080 	PINMUX_IPSR_GPSR(IP8_23_20,	SD2_DAT5),
1081 	PINMUX_IPSR_MSEL(IP8_23_20,	MSIOF1_TXD_G,		SEL_MSIOF1_6),
1082 	PINMUX_IPSR_MSEL(IP8_23_20,	NFDATA14_B,		SEL_NDF_1),
1083 	PINMUX_IPSR_MSEL(IP8_23_20,	TS_SPSYNC1_B,		SEL_TSIF1_1),
1084 	PINMUX_IPSR_MSEL(IP8_23_20,	STP_ISSYNC_1_B,		SEL_SSP1_1_1),
1085 
1086 	PINMUX_IPSR_GPSR(IP8_27_24,	SD1_DAT2),
1087 	PINMUX_IPSR_GPSR(IP8_27_24,	SD2_DAT6),
1088 	PINMUX_IPSR_MSEL(IP8_27_24,	MSIOF1_SS1_G,		SEL_MSIOF1_6),
1089 	PINMUX_IPSR_MSEL(IP8_27_24,	NFDATA15_B,		SEL_NDF_1),
1090 	PINMUX_IPSR_MSEL(IP8_27_24,	TS_SDAT1_B,		SEL_TSIF1_1),
1091 	PINMUX_IPSR_MSEL(IP8_27_24,	STP_ISD_1_B,		SEL_SSP1_1_1),
1092 
1093 	PINMUX_IPSR_GPSR(IP8_31_28,	SD1_DAT3),
1094 	PINMUX_IPSR_GPSR(IP8_31_28,	SD2_DAT7),
1095 	PINMUX_IPSR_MSEL(IP8_31_28,	MSIOF1_SS2_G,		SEL_MSIOF1_6),
1096 	PINMUX_IPSR_MSEL(IP8_31_28,	NFRB_N_B,		SEL_NDF_1),
1097 	PINMUX_IPSR_MSEL(IP8_31_28,	TS_SDEN1_B,		SEL_TSIF1_1),
1098 	PINMUX_IPSR_MSEL(IP8_31_28,	STP_ISEN_1_B,		SEL_SSP1_1_1),
1099 
1100 	/* IPSR9 */
1101 	PINMUX_IPSR_GPSR(IP9_3_0,	SD2_CLK),
1102 	PINMUX_IPSR_GPSR(IP9_3_0,	NFDATA8),
1103 
1104 	PINMUX_IPSR_GPSR(IP9_7_4,	SD2_CMD),
1105 	PINMUX_IPSR_GPSR(IP9_7_4,	NFDATA9),
1106 
1107 	PINMUX_IPSR_GPSR(IP9_11_8,	SD2_DAT0),
1108 	PINMUX_IPSR_GPSR(IP9_11_8,	NFDATA10),
1109 
1110 	PINMUX_IPSR_GPSR(IP9_15_12,	SD2_DAT1),
1111 	PINMUX_IPSR_GPSR(IP9_15_12,	NFDATA11),
1112 
1113 	PINMUX_IPSR_GPSR(IP9_19_16,	SD2_DAT2),
1114 	PINMUX_IPSR_GPSR(IP9_19_16,	NFDATA12),
1115 
1116 	PINMUX_IPSR_GPSR(IP9_23_20,	SD2_DAT3),
1117 	PINMUX_IPSR_GPSR(IP9_23_20,	NFDATA13),
1118 
1119 	PINMUX_IPSR_GPSR(IP9_27_24,	SD2_DS),
1120 	PINMUX_IPSR_GPSR(IP9_27_24,	NFALE),
1121 
1122 	PINMUX_IPSR_GPSR(IP9_31_28,	SD3_CLK),
1123 	PINMUX_IPSR_GPSR(IP9_31_28,	NFWE_N),
1124 
1125 	/* IPSR10 */
1126 	PINMUX_IPSR_GPSR(IP10_3_0,	SD3_CMD),
1127 	PINMUX_IPSR_GPSR(IP10_3_0,	NFRE_N),
1128 
1129 	PINMUX_IPSR_GPSR(IP10_7_4,	SD3_DAT0),
1130 	PINMUX_IPSR_GPSR(IP10_7_4,	NFDATA0),
1131 
1132 	PINMUX_IPSR_GPSR(IP10_11_8,	SD3_DAT1),
1133 	PINMUX_IPSR_GPSR(IP10_11_8,	NFDATA1),
1134 
1135 	PINMUX_IPSR_GPSR(IP10_15_12,	SD3_DAT2),
1136 	PINMUX_IPSR_GPSR(IP10_15_12,	NFDATA2),
1137 
1138 	PINMUX_IPSR_GPSR(IP10_19_16,	SD3_DAT3),
1139 	PINMUX_IPSR_GPSR(IP10_19_16,	NFDATA3),
1140 
1141 	PINMUX_IPSR_GPSR(IP10_23_20,	SD3_DAT4),
1142 	PINMUX_IPSR_MSEL(IP10_23_20,	SD2_CD_A,		SEL_SDHI2_0),
1143 	PINMUX_IPSR_GPSR(IP10_23_20,	NFDATA4),
1144 
1145 	PINMUX_IPSR_GPSR(IP10_27_24,	SD3_DAT5),
1146 	PINMUX_IPSR_MSEL(IP10_27_24,	SD2_WP_A,		SEL_SDHI2_0),
1147 	PINMUX_IPSR_GPSR(IP10_27_24,	NFDATA5),
1148 
1149 	PINMUX_IPSR_GPSR(IP10_31_28,	SD3_DAT6),
1150 	PINMUX_IPSR_GPSR(IP10_31_28,	SD3_CD),
1151 	PINMUX_IPSR_GPSR(IP10_31_28,	NFDATA6),
1152 
1153 	/* IPSR11 */
1154 	PINMUX_IPSR_GPSR(IP11_3_0,	SD3_DAT7),
1155 	PINMUX_IPSR_GPSR(IP11_3_0,	SD3_WP),
1156 	PINMUX_IPSR_GPSR(IP11_3_0,	NFDATA7),
1157 
1158 	PINMUX_IPSR_GPSR(IP11_7_4,	SD3_DS),
1159 	PINMUX_IPSR_GPSR(IP11_7_4,	NFCLE),
1160 
1161 	PINMUX_IPSR_GPSR(IP11_11_8,	SD0_CD),
1162 	PINMUX_IPSR_MSEL(IP11_11_8,	NFDATA14_A,		SEL_NDF_0),
1163 	PINMUX_IPSR_MSEL(IP11_11_8,	SCL2_B,			SEL_I2C2_1),
1164 	PINMUX_IPSR_MSEL(IP11_11_8,	SIM0_RST_A,		SEL_SIMCARD_0),
1165 
1166 	PINMUX_IPSR_GPSR(IP11_15_12,	SD0_WP),
1167 	PINMUX_IPSR_MSEL(IP11_15_12,	NFDATA15_A,		SEL_NDF_0),
1168 	PINMUX_IPSR_MSEL(IP11_15_12,	SDA2_B,			SEL_I2C2_1),
1169 
1170 	PINMUX_IPSR_MSEL(IP11_19_16,	SD1_CD,			I2C_SEL_0_0),
1171 	PINMUX_IPSR_PHYS_MSEL(IP11_19_16, NFRB_N_A,		I2C_SEL_0_0,	SEL_NDF_0),
1172 	PINMUX_IPSR_PHYS_MSEL(IP11_19_16, SIM0_CLK_B,		I2C_SEL_0_0,	SEL_SIMCARD_1),
1173 	PINMUX_IPSR_PHYS(IP11_19_16,	SCL0,			I2C_SEL_0_1),
1174 
1175 	PINMUX_IPSR_MSEL(IP11_23_20,	SD1_WP,			I2C_SEL_0_0),
1176 	PINMUX_IPSR_PHYS_MSEL(IP11_23_20, NFCE_N_A,		I2C_SEL_0_0,	SEL_NDF_0),
1177 	PINMUX_IPSR_PHYS_MSEL(IP11_23_20, SIM0_D_B,		I2C_SEL_0_0,	SEL_SIMCARD_1),
1178 	PINMUX_IPSR_PHYS(IP11_23_20,	SDA0,			I2C_SEL_0_1),
1179 
1180 	PINMUX_IPSR_GPSR(IP11_27_24,	SCK0),
1181 	PINMUX_IPSR_MSEL(IP11_27_24,	HSCK1_B,		SEL_HSCIF1_1),
1182 	PINMUX_IPSR_MSEL(IP11_27_24,	MSIOF1_SS2_B,		SEL_MSIOF1_1),
1183 	PINMUX_IPSR_MSEL(IP11_27_24,	AUDIO_CLKC_B,		SEL_ADGC_1),
1184 	PINMUX_IPSR_MSEL(IP11_27_24,	SDA2_A,			SEL_I2C2_0),
1185 	PINMUX_IPSR_MSEL(IP11_27_24,	SIM0_RST_B,		SEL_SIMCARD_1),
1186 	PINMUX_IPSR_MSEL(IP11_27_24,	STP_OPWM_0_C,		SEL_SSP1_0_2),
1187 	PINMUX_IPSR_MSEL(IP11_27_24,	RIF0_CLK_B,		SEL_DRIF0_1),
1188 	PINMUX_IPSR_GPSR(IP11_27_24,	ADICHS2),
1189 	PINMUX_IPSR_MSEL(IP11_27_24,	SCK5_B,			SEL_SCIF5_1),
1190 
1191 	PINMUX_IPSR_GPSR(IP11_31_28,	RX0),
1192 	PINMUX_IPSR_MSEL(IP11_31_28,	HRX1_B,			SEL_HSCIF1_1),
1193 	PINMUX_IPSR_MSEL(IP11_31_28,	TS_SCK0_C,		SEL_TSIF0_2),
1194 	PINMUX_IPSR_MSEL(IP11_31_28,	STP_ISCLK_0_C,		SEL_SSP1_0_2),
1195 	PINMUX_IPSR_MSEL(IP11_31_28,	RIF0_D0_B,		SEL_DRIF0_1),
1196 
1197 	/* IPSR12 */
1198 	PINMUX_IPSR_GPSR(IP12_3_0,	TX0),
1199 	PINMUX_IPSR_MSEL(IP12_3_0,	HTX1_B,			SEL_HSCIF1_1),
1200 	PINMUX_IPSR_MSEL(IP12_3_0,	TS_SPSYNC0_C,		SEL_TSIF0_2),
1201 	PINMUX_IPSR_MSEL(IP12_3_0,	STP_ISSYNC_0_C,		SEL_SSP1_0_2),
1202 	PINMUX_IPSR_MSEL(IP12_3_0,	RIF0_D1_B,		SEL_DRIF0_1),
1203 
1204 	PINMUX_IPSR_GPSR(IP12_7_4,	CTS0_N),
1205 	PINMUX_IPSR_MSEL(IP12_7_4,	HCTS1_N_B,		SEL_HSCIF1_1),
1206 	PINMUX_IPSR_MSEL(IP12_7_4,	MSIOF1_SYNC_B,		SEL_MSIOF1_1),
1207 	PINMUX_IPSR_MSEL(IP12_7_4,	TS_SPSYNC1_C,		SEL_TSIF1_2),
1208 	PINMUX_IPSR_MSEL(IP12_7_4,	STP_ISSYNC_1_C,		SEL_SSP1_1_2),
1209 	PINMUX_IPSR_MSEL(IP12_7_4,	RIF1_SYNC_B,		SEL_DRIF1_1),
1210 	PINMUX_IPSR_GPSR(IP12_7_4,	AUDIO_CLKOUT_C),
1211 	PINMUX_IPSR_GPSR(IP12_7_4,	ADICS_SAMP),
1212 
1213 	PINMUX_IPSR_GPSR(IP12_11_8,	RTS0_N),
1214 	PINMUX_IPSR_MSEL(IP12_11_8,	HRTS1_N_B,		SEL_HSCIF1_1),
1215 	PINMUX_IPSR_MSEL(IP12_11_8,	MSIOF1_SS1_B,		SEL_MSIOF1_1),
1216 	PINMUX_IPSR_MSEL(IP12_11_8,	AUDIO_CLKA_B,		SEL_ADGA_1),
1217 	PINMUX_IPSR_MSEL(IP12_11_8,	SCL2_A,			SEL_I2C2_0),
1218 	PINMUX_IPSR_MSEL(IP12_11_8,	STP_IVCXO27_1_C,	SEL_SSP1_1_2),
1219 	PINMUX_IPSR_MSEL(IP12_11_8,	RIF0_SYNC_B,		SEL_DRIF0_1),
1220 	PINMUX_IPSR_GPSR(IP12_11_8,	ADICHS1),
1221 
1222 	PINMUX_IPSR_MSEL(IP12_15_12,	RX1_A,			SEL_SCIF1_0),
1223 	PINMUX_IPSR_MSEL(IP12_15_12,	HRX1_A,			SEL_HSCIF1_0),
1224 	PINMUX_IPSR_MSEL(IP12_15_12,	TS_SDAT0_C,		SEL_TSIF0_2),
1225 	PINMUX_IPSR_MSEL(IP12_15_12,	STP_ISD_0_C,		SEL_SSP1_0_2),
1226 	PINMUX_IPSR_MSEL(IP12_15_12,	RIF1_CLK_C,		SEL_DRIF1_2),
1227 
1228 	PINMUX_IPSR_MSEL(IP12_19_16,	TX1_A,			SEL_SCIF1_0),
1229 	PINMUX_IPSR_MSEL(IP12_19_16,	HTX1_A,			SEL_HSCIF1_0),
1230 	PINMUX_IPSR_MSEL(IP12_19_16,	TS_SDEN0_C,		SEL_TSIF0_2),
1231 	PINMUX_IPSR_MSEL(IP12_19_16,	STP_ISEN_0_C,		SEL_SSP1_0_2),
1232 	PINMUX_IPSR_MSEL(IP12_19_16,	RIF1_D0_C,		SEL_DRIF1_2),
1233 
1234 	PINMUX_IPSR_GPSR(IP12_23_20,	CTS1_N),
1235 	PINMUX_IPSR_MSEL(IP12_23_20,	HCTS1_N_A,		SEL_HSCIF1_0),
1236 	PINMUX_IPSR_MSEL(IP12_23_20,	MSIOF1_RXD_B,		SEL_MSIOF1_1),
1237 	PINMUX_IPSR_MSEL(IP12_23_20,	TS_SDEN1_C,		SEL_TSIF1_2),
1238 	PINMUX_IPSR_MSEL(IP12_23_20,	STP_ISEN_1_C,		SEL_SSP1_1_2),
1239 	PINMUX_IPSR_MSEL(IP12_23_20,	RIF1_D0_B,		SEL_DRIF1_1),
1240 	PINMUX_IPSR_GPSR(IP12_23_20,	ADIDATA),
1241 
1242 	PINMUX_IPSR_GPSR(IP12_27_24,	RTS1_N),
1243 	PINMUX_IPSR_MSEL(IP12_27_24,	HRTS1_N_A,		SEL_HSCIF1_0),
1244 	PINMUX_IPSR_MSEL(IP12_27_24,	MSIOF1_TXD_B,		SEL_MSIOF1_1),
1245 	PINMUX_IPSR_MSEL(IP12_27_24,	TS_SDAT1_C,		SEL_TSIF1_2),
1246 	PINMUX_IPSR_MSEL(IP12_27_24,	STP_ISD_1_C,		SEL_SSP1_1_2),
1247 	PINMUX_IPSR_MSEL(IP12_27_24,	RIF1_D1_B,		SEL_DRIF1_1),
1248 	PINMUX_IPSR_GPSR(IP12_27_24,	ADICHS0),
1249 
1250 	PINMUX_IPSR_GPSR(IP12_31_28,	SCK2),
1251 	PINMUX_IPSR_MSEL(IP12_31_28,	SCIF_CLK_B,		SEL_SCIF_1),
1252 	PINMUX_IPSR_MSEL(IP12_31_28,	MSIOF1_SCK_B,		SEL_MSIOF1_1),
1253 	PINMUX_IPSR_MSEL(IP12_31_28,	TS_SCK1_C,		SEL_TSIF1_2),
1254 	PINMUX_IPSR_MSEL(IP12_31_28,	STP_ISCLK_1_C,		SEL_SSP1_1_2),
1255 	PINMUX_IPSR_MSEL(IP12_31_28,	RIF1_CLK_B,		SEL_DRIF1_1),
1256 	PINMUX_IPSR_GPSR(IP12_31_28,	ADICLK),
1257 
1258 	/* IPSR13 */
1259 	PINMUX_IPSR_MSEL(IP13_3_0,	TX2_A,			SEL_SCIF2_0),
1260 	PINMUX_IPSR_MSEL(IP13_3_0,	SD2_CD_B,		SEL_SDHI2_1),
1261 	PINMUX_IPSR_MSEL(IP13_3_0,	SCL1_A,			SEL_I2C1_0),
1262 	PINMUX_IPSR_MSEL(IP13_3_0,	FMCLK_A,		SEL_FM_0),
1263 	PINMUX_IPSR_MSEL(IP13_3_0,	RIF1_D1_C,		SEL_DRIF1_2),
1264 	PINMUX_IPSR_GPSR(IP13_3_0,	FSO_CFE_0_N),
1265 
1266 	PINMUX_IPSR_MSEL(IP13_7_4,	RX2_A,			SEL_SCIF2_0),
1267 	PINMUX_IPSR_MSEL(IP13_7_4,	SD2_WP_B,		SEL_SDHI2_1),
1268 	PINMUX_IPSR_MSEL(IP13_7_4,	SDA1_A,			SEL_I2C1_0),
1269 	PINMUX_IPSR_MSEL(IP13_7_4,	FMIN_A,			SEL_FM_0),
1270 	PINMUX_IPSR_MSEL(IP13_7_4,	RIF1_SYNC_C,		SEL_DRIF1_2),
1271 	PINMUX_IPSR_GPSR(IP13_7_4,	FSO_CFE_1_N),
1272 
1273 	PINMUX_IPSR_GPSR(IP13_11_8,	HSCK0),
1274 	PINMUX_IPSR_MSEL(IP13_11_8,	MSIOF1_SCK_D,		SEL_MSIOF1_3),
1275 	PINMUX_IPSR_MSEL(IP13_11_8,	AUDIO_CLKB_A,		SEL_ADGB_0),
1276 	PINMUX_IPSR_MSEL(IP13_11_8,	SSI_SDATA1_B,		SEL_SSI1_1),
1277 	PINMUX_IPSR_MSEL(IP13_11_8,	TS_SCK0_D,		SEL_TSIF0_3),
1278 	PINMUX_IPSR_MSEL(IP13_11_8,	STP_ISCLK_0_D,		SEL_SSP1_0_3),
1279 	PINMUX_IPSR_MSEL(IP13_11_8,	RIF0_CLK_C,		SEL_DRIF0_2),
1280 	PINMUX_IPSR_MSEL(IP13_11_8,	RX5_B,			SEL_SCIF5_1),
1281 
1282 	PINMUX_IPSR_GPSR(IP13_15_12,	HRX0),
1283 	PINMUX_IPSR_MSEL(IP13_15_12,	MSIOF1_RXD_D,		SEL_MSIOF1_3),
1284 	PINMUX_IPSR_MSEL(IP13_15_12,	SSI_SDATA2_B,		SEL_SSI2_1),
1285 	PINMUX_IPSR_MSEL(IP13_15_12,	TS_SDEN0_D,		SEL_TSIF0_3),
1286 	PINMUX_IPSR_MSEL(IP13_15_12,	STP_ISEN_0_D,		SEL_SSP1_0_3),
1287 	PINMUX_IPSR_MSEL(IP13_15_12,	RIF0_D0_C,		SEL_DRIF0_2),
1288 
1289 	PINMUX_IPSR_GPSR(IP13_19_16,	HTX0),
1290 	PINMUX_IPSR_MSEL(IP13_19_16,	MSIOF1_TXD_D,		SEL_MSIOF1_3),
1291 	PINMUX_IPSR_MSEL(IP13_19_16,	SSI_SDATA9_B,		SEL_SSI9_1),
1292 	PINMUX_IPSR_MSEL(IP13_19_16,	TS_SDAT0_D,		SEL_TSIF0_3),
1293 	PINMUX_IPSR_MSEL(IP13_19_16,	STP_ISD_0_D,		SEL_SSP1_0_3),
1294 	PINMUX_IPSR_MSEL(IP13_19_16,	RIF0_D1_C,		SEL_DRIF0_2),
1295 
1296 	PINMUX_IPSR_GPSR(IP13_23_20,	HCTS0_N),
1297 	PINMUX_IPSR_MSEL(IP13_23_20,	RX2_B,			SEL_SCIF2_1),
1298 	PINMUX_IPSR_MSEL(IP13_23_20,	MSIOF1_SYNC_D,		SEL_MSIOF1_3),
1299 	PINMUX_IPSR_MSEL(IP13_23_20,	SSI_SCK9_A,		SEL_SSI9_0),
1300 	PINMUX_IPSR_MSEL(IP13_23_20,	TS_SPSYNC0_D,		SEL_TSIF0_3),
1301 	PINMUX_IPSR_MSEL(IP13_23_20,	STP_ISSYNC_0_D,		SEL_SSP1_0_3),
1302 	PINMUX_IPSR_MSEL(IP13_23_20,	RIF0_SYNC_C,		SEL_DRIF0_2),
1303 	PINMUX_IPSR_GPSR(IP13_23_20,	AUDIO_CLKOUT1_A),
1304 
1305 	PINMUX_IPSR_GPSR(IP13_27_24,	HRTS0_N),
1306 	PINMUX_IPSR_MSEL(IP13_27_24,	TX2_B,			SEL_SCIF2_1),
1307 	PINMUX_IPSR_MSEL(IP13_27_24,	MSIOF1_SS1_D,		SEL_MSIOF1_3),
1308 	PINMUX_IPSR_MSEL(IP13_27_24,	SSI_WS9_A,		SEL_SSI9_0),
1309 	PINMUX_IPSR_MSEL(IP13_27_24,	STP_IVCXO27_0_D,	SEL_SSP1_0_3),
1310 	PINMUX_IPSR_MSEL(IP13_27_24,	BPFCLK_A,		SEL_FM_0),
1311 	PINMUX_IPSR_GPSR(IP13_27_24,	AUDIO_CLKOUT2_A),
1312 
1313 	PINMUX_IPSR_GPSR(IP13_31_28,	MSIOF0_SYNC),
1314 	PINMUX_IPSR_GPSR(IP13_31_28,	AUDIO_CLKOUT_A),
1315 	PINMUX_IPSR_MSEL(IP13_31_28,	TX5_B,			SEL_SCIF5_1),
1316 	PINMUX_IPSR_MSEL(IP13_31_28,	BPFCLK_D,		SEL_FM_3),
1317 
1318 	/* IPSR14 */
1319 	PINMUX_IPSR_GPSR(IP14_3_0,	MSIOF0_SS1),
1320 	PINMUX_IPSR_MSEL(IP14_3_0,	RX5_A,			SEL_SCIF5_0),
1321 	PINMUX_IPSR_MSEL(IP14_3_0,	NFWP_N_A,		SEL_NDF_0),
1322 	PINMUX_IPSR_MSEL(IP14_3_0,	AUDIO_CLKA_C,		SEL_ADGA_2),
1323 	PINMUX_IPSR_MSEL(IP14_3_0,	SSI_SCK2_A,		SEL_SSI2_0),
1324 	PINMUX_IPSR_MSEL(IP14_3_0,	STP_IVCXO27_0_C,	SEL_SSP1_0_2),
1325 	PINMUX_IPSR_GPSR(IP14_3_0,	AUDIO_CLKOUT3_A),
1326 	PINMUX_IPSR_MSEL(IP14_3_0,	TCLK1_B,		SEL_TIMER_TMU_1),
1327 
1328 	PINMUX_IPSR_GPSR(IP14_7_4,	MSIOF0_SS2),
1329 	PINMUX_IPSR_MSEL(IP14_7_4,	TX5_A,			SEL_SCIF5_0),
1330 	PINMUX_IPSR_MSEL(IP14_7_4,	MSIOF1_SS2_D,		SEL_MSIOF1_3),
1331 	PINMUX_IPSR_MSEL(IP14_7_4,	AUDIO_CLKC_A,		SEL_ADGC_0),
1332 	PINMUX_IPSR_MSEL(IP14_7_4,	SSI_WS2_A,		SEL_SSI2_0),
1333 	PINMUX_IPSR_MSEL(IP14_7_4,	STP_OPWM_0_D,		SEL_SSP1_0_3),
1334 	PINMUX_IPSR_GPSR(IP14_7_4,	AUDIO_CLKOUT_D),
1335 	PINMUX_IPSR_MSEL(IP14_7_4,	SPEEDIN_B,		SEL_SPEED_PULSE_1),
1336 
1337 	PINMUX_IPSR_GPSR(IP14_11_8,	MLB_CLK),
1338 	PINMUX_IPSR_MSEL(IP14_11_8,	MSIOF1_SCK_F,		SEL_MSIOF1_5),
1339 	PINMUX_IPSR_MSEL(IP14_11_8,	SCL1_B,			SEL_I2C1_1),
1340 
1341 	PINMUX_IPSR_GPSR(IP14_15_12,	MLB_SIG),
1342 	PINMUX_IPSR_MSEL(IP14_15_12,	RX1_B,			SEL_SCIF1_1),
1343 	PINMUX_IPSR_MSEL(IP14_15_12,	MSIOF1_SYNC_F,		SEL_MSIOF1_5),
1344 	PINMUX_IPSR_MSEL(IP14_15_12,	SDA1_B,			SEL_I2C1_1),
1345 
1346 	PINMUX_IPSR_GPSR(IP14_19_16,	MLB_DAT),
1347 	PINMUX_IPSR_MSEL(IP14_19_16,	TX1_B,			SEL_SCIF1_1),
1348 	PINMUX_IPSR_MSEL(IP14_19_16,	MSIOF1_RXD_F,		SEL_MSIOF1_5),
1349 
1350 	PINMUX_IPSR_GPSR(IP14_23_20,	SSI_SCK01239),
1351 	PINMUX_IPSR_MSEL(IP14_23_20,	MSIOF1_TXD_F,		SEL_MSIOF1_5),
1352 
1353 	PINMUX_IPSR_GPSR(IP14_27_24,	SSI_WS01239),
1354 	PINMUX_IPSR_MSEL(IP14_27_24,	MSIOF1_SS1_F,		SEL_MSIOF1_5),
1355 
1356 	PINMUX_IPSR_GPSR(IP14_31_28,	SSI_SDATA0),
1357 	PINMUX_IPSR_MSEL(IP14_31_28,	MSIOF1_SS2_F,		SEL_MSIOF1_5),
1358 
1359 	/* IPSR15 */
1360 	PINMUX_IPSR_MSEL(IP15_3_0,	SSI_SDATA1_A,		SEL_SSI1_0),
1361 
1362 	PINMUX_IPSR_MSEL(IP15_7_4,	SSI_SDATA2_A,		SEL_SSI2_0),
1363 	PINMUX_IPSR_MSEL(IP15_7_4,	SSI_SCK1_B,		SEL_SSI1_1),
1364 
1365 	PINMUX_IPSR_GPSR(IP15_11_8,	SSI_SCK349),
1366 	PINMUX_IPSR_MSEL(IP15_11_8,	MSIOF1_SS1_A,		SEL_MSIOF1_0),
1367 	PINMUX_IPSR_MSEL(IP15_11_8,	STP_OPWM_0_A,		SEL_SSP1_0_0),
1368 
1369 	PINMUX_IPSR_GPSR(IP15_15_12,	SSI_WS349),
1370 	PINMUX_IPSR_MSEL(IP15_15_12,	HCTS2_N_A,		SEL_HSCIF2_0),
1371 	PINMUX_IPSR_MSEL(IP15_15_12,	MSIOF1_SS2_A,		SEL_MSIOF1_0),
1372 	PINMUX_IPSR_MSEL(IP15_15_12,	STP_IVCXO27_0_A,	SEL_SSP1_0_0),
1373 
1374 	PINMUX_IPSR_GPSR(IP15_19_16,	SSI_SDATA3),
1375 	PINMUX_IPSR_MSEL(IP15_19_16,	HRTS2_N_A,		SEL_HSCIF2_0),
1376 	PINMUX_IPSR_MSEL(IP15_19_16,	MSIOF1_TXD_A,		SEL_MSIOF1_0),
1377 	PINMUX_IPSR_MSEL(IP15_19_16,	TS_SCK0_A,		SEL_TSIF0_0),
1378 	PINMUX_IPSR_MSEL(IP15_19_16,	STP_ISCLK_0_A,		SEL_SSP1_0_0),
1379 	PINMUX_IPSR_MSEL(IP15_19_16,	RIF0_D1_A,		SEL_DRIF0_0),
1380 	PINMUX_IPSR_MSEL(IP15_19_16,	RIF2_D0_A,		SEL_DRIF2_0),
1381 
1382 	PINMUX_IPSR_GPSR(IP15_23_20,	SSI_SCK4),
1383 	PINMUX_IPSR_MSEL(IP15_23_20,	HRX2_A,			SEL_HSCIF2_0),
1384 	PINMUX_IPSR_MSEL(IP15_23_20,	MSIOF1_SCK_A,		SEL_MSIOF1_0),
1385 	PINMUX_IPSR_MSEL(IP15_23_20,	TS_SDAT0_A,		SEL_TSIF0_0),
1386 	PINMUX_IPSR_MSEL(IP15_23_20,	STP_ISD_0_A,		SEL_SSP1_0_0),
1387 	PINMUX_IPSR_MSEL(IP15_23_20,	RIF0_CLK_A,		SEL_DRIF0_0),
1388 	PINMUX_IPSR_MSEL(IP15_23_20,	RIF2_CLK_A,		SEL_DRIF2_0),
1389 
1390 	PINMUX_IPSR_GPSR(IP15_27_24,	SSI_WS4),
1391 	PINMUX_IPSR_MSEL(IP15_27_24,	HTX2_A,			SEL_HSCIF2_0),
1392 	PINMUX_IPSR_MSEL(IP15_27_24,	MSIOF1_SYNC_A,		SEL_MSIOF1_0),
1393 	PINMUX_IPSR_MSEL(IP15_27_24,	TS_SDEN0_A,		SEL_TSIF0_0),
1394 	PINMUX_IPSR_MSEL(IP15_27_24,	STP_ISEN_0_A,		SEL_SSP1_0_0),
1395 	PINMUX_IPSR_MSEL(IP15_27_24,	RIF0_SYNC_A,		SEL_DRIF0_0),
1396 	PINMUX_IPSR_MSEL(IP15_27_24,	RIF2_SYNC_A,		SEL_DRIF2_0),
1397 
1398 	PINMUX_IPSR_GPSR(IP15_31_28,	SSI_SDATA4),
1399 	PINMUX_IPSR_MSEL(IP15_31_28,	HSCK2_A,		SEL_HSCIF2_0),
1400 	PINMUX_IPSR_MSEL(IP15_31_28,	MSIOF1_RXD_A,		SEL_MSIOF1_0),
1401 	PINMUX_IPSR_MSEL(IP15_31_28,	TS_SPSYNC0_A,		SEL_TSIF0_0),
1402 	PINMUX_IPSR_MSEL(IP15_31_28,	STP_ISSYNC_0_A,		SEL_SSP1_0_0),
1403 	PINMUX_IPSR_MSEL(IP15_31_28,	RIF0_D0_A,		SEL_DRIF0_0),
1404 	PINMUX_IPSR_MSEL(IP15_31_28,	RIF2_D1_A,		SEL_DRIF2_0),
1405 
1406 	/* IPSR16 */
1407 	PINMUX_IPSR_GPSR(IP16_3_0,	SSI_SCK6),
1408 	PINMUX_IPSR_MSEL(IP16_3_0,	SIM0_RST_D,		SEL_SIMCARD_3),
1409 
1410 	PINMUX_IPSR_GPSR(IP16_7_4,	SSI_WS6),
1411 	PINMUX_IPSR_MSEL(IP16_7_4,	SIM0_D_D,		SEL_SIMCARD_3),
1412 
1413 	PINMUX_IPSR_GPSR(IP16_11_8,	SSI_SDATA6),
1414 	PINMUX_IPSR_MSEL(IP16_11_8,	SIM0_CLK_D,		SEL_SIMCARD_3),
1415 
1416 	PINMUX_IPSR_GPSR(IP16_15_12,	SSI_SCK78),
1417 	PINMUX_IPSR_MSEL(IP16_15_12,	HRX2_B,			SEL_HSCIF2_1),
1418 	PINMUX_IPSR_MSEL(IP16_15_12,	MSIOF1_SCK_C,		SEL_MSIOF1_2),
1419 	PINMUX_IPSR_MSEL(IP16_15_12,	TS_SCK1_A,		SEL_TSIF1_0),
1420 	PINMUX_IPSR_MSEL(IP16_15_12,	STP_ISCLK_1_A,		SEL_SSP1_1_0),
1421 	PINMUX_IPSR_MSEL(IP16_15_12,	RIF1_CLK_A,		SEL_DRIF1_0),
1422 	PINMUX_IPSR_MSEL(IP16_15_12,	RIF3_CLK_A,		SEL_DRIF3_0),
1423 
1424 	PINMUX_IPSR_GPSR(IP16_19_16,	SSI_WS78),
1425 	PINMUX_IPSR_MSEL(IP16_19_16,	HTX2_B,			SEL_HSCIF2_1),
1426 	PINMUX_IPSR_MSEL(IP16_19_16,	MSIOF1_SYNC_C,		SEL_MSIOF1_2),
1427 	PINMUX_IPSR_MSEL(IP16_19_16,	TS_SDAT1_A,		SEL_TSIF1_0),
1428 	PINMUX_IPSR_MSEL(IP16_19_16,	STP_ISD_1_A,		SEL_SSP1_1_0),
1429 	PINMUX_IPSR_MSEL(IP16_19_16,	RIF1_SYNC_A,		SEL_DRIF1_0),
1430 	PINMUX_IPSR_MSEL(IP16_19_16,	RIF3_SYNC_A,		SEL_DRIF3_0),
1431 
1432 	PINMUX_IPSR_GPSR(IP16_23_20,	SSI_SDATA7),
1433 	PINMUX_IPSR_MSEL(IP16_23_20,	HCTS2_N_B,		SEL_HSCIF2_1),
1434 	PINMUX_IPSR_MSEL(IP16_23_20,	MSIOF1_RXD_C,		SEL_MSIOF1_2),
1435 	PINMUX_IPSR_MSEL(IP16_23_20,	TS_SDEN1_A,		SEL_TSIF1_0),
1436 	PINMUX_IPSR_MSEL(IP16_23_20,	STP_ISEN_1_A,		SEL_SSP1_1_0),
1437 	PINMUX_IPSR_MSEL(IP16_23_20,	RIF1_D0_A,		SEL_DRIF1_0),
1438 	PINMUX_IPSR_MSEL(IP16_23_20,	RIF3_D0_A,		SEL_DRIF3_0),
1439 	PINMUX_IPSR_MSEL(IP16_23_20,	TCLK2_A,		SEL_TIMER_TMU2_0),
1440 
1441 	PINMUX_IPSR_GPSR(IP16_27_24,	SSI_SDATA8),
1442 	PINMUX_IPSR_MSEL(IP16_27_24,	HRTS2_N_B,		SEL_HSCIF2_1),
1443 	PINMUX_IPSR_MSEL(IP16_27_24,	MSIOF1_TXD_C,		SEL_MSIOF1_2),
1444 	PINMUX_IPSR_MSEL(IP16_27_24,	TS_SPSYNC1_A,		SEL_TSIF1_0),
1445 	PINMUX_IPSR_MSEL(IP16_27_24,	STP_ISSYNC_1_A,		SEL_SSP1_1_0),
1446 	PINMUX_IPSR_MSEL(IP16_27_24,	RIF1_D1_A,		SEL_DRIF1_0),
1447 	PINMUX_IPSR_MSEL(IP16_27_24,	RIF3_D1_A,		SEL_DRIF3_0),
1448 
1449 	PINMUX_IPSR_MSEL(IP16_31_28,	SSI_SDATA9_A,		SEL_SSI9_0),
1450 	PINMUX_IPSR_MSEL(IP16_31_28,	HSCK2_B,		SEL_HSCIF2_1),
1451 	PINMUX_IPSR_MSEL(IP16_31_28,	MSIOF1_SS1_C,		SEL_MSIOF1_2),
1452 	PINMUX_IPSR_MSEL(IP16_31_28,	HSCK1_A,		SEL_HSCIF1_0),
1453 	PINMUX_IPSR_MSEL(IP16_31_28,	SSI_WS1_B,		SEL_SSI1_1),
1454 	PINMUX_IPSR_GPSR(IP16_31_28,	SCK1),
1455 	PINMUX_IPSR_MSEL(IP16_31_28,	STP_IVCXO27_1_A,	SEL_SSP1_1_0),
1456 	PINMUX_IPSR_MSEL(IP16_31_28,	SCK5_A,			SEL_SCIF5_0),
1457 
1458 	/* IPSR17 */
1459 	PINMUX_IPSR_MSEL(IP17_3_0,	AUDIO_CLKA_A,		SEL_ADGA_0),
1460 
1461 	PINMUX_IPSR_MSEL(IP17_7_4,	AUDIO_CLKB_B,		SEL_ADGB_1),
1462 	PINMUX_IPSR_MSEL(IP17_7_4,	SCIF_CLK_A,		SEL_SCIF_0),
1463 	PINMUX_IPSR_MSEL(IP17_7_4,	STP_IVCXO27_1_D,	SEL_SSP1_1_3),
1464 	PINMUX_IPSR_MSEL(IP17_7_4,	REMOCON_A,		SEL_REMOCON_0),
1465 	PINMUX_IPSR_MSEL(IP17_7_4,	TCLK1_A,		SEL_TIMER_TMU_0),
1466 
1467 	PINMUX_IPSR_GPSR(IP17_11_8,	USB0_PWEN),
1468 	PINMUX_IPSR_MSEL(IP17_11_8,	SIM0_RST_C,		SEL_SIMCARD_2),
1469 	PINMUX_IPSR_MSEL(IP17_11_8,	TS_SCK1_D,		SEL_TSIF1_3),
1470 	PINMUX_IPSR_MSEL(IP17_11_8,	STP_ISCLK_1_D,		SEL_SSP1_1_3),
1471 	PINMUX_IPSR_MSEL(IP17_11_8,	BPFCLK_B,		SEL_FM_1),
1472 	PINMUX_IPSR_MSEL(IP17_11_8,	RIF3_CLK_B,		SEL_DRIF3_1),
1473 	PINMUX_IPSR_MSEL(IP17_11_8,	HSCK2_C,		SEL_HSCIF2_2),
1474 
1475 	PINMUX_IPSR_GPSR(IP17_15_12,	USB0_OVC),
1476 	PINMUX_IPSR_MSEL(IP17_15_12,	SIM0_D_C,		SEL_SIMCARD_2),
1477 	PINMUX_IPSR_MSEL(IP17_15_12,	TS_SDAT1_D,		SEL_TSIF1_3),
1478 	PINMUX_IPSR_MSEL(IP17_15_12,	STP_ISD_1_D,		SEL_SSP1_1_3),
1479 	PINMUX_IPSR_MSEL(IP17_15_12,	RIF3_SYNC_B,		SEL_DRIF3_1),
1480 	PINMUX_IPSR_MSEL(IP17_15_12,	HRX2_C,			SEL_HSCIF2_2),
1481 
1482 	PINMUX_IPSR_GPSR(IP17_19_16,	USB1_PWEN),
1483 	PINMUX_IPSR_MSEL(IP17_19_16,	SIM0_CLK_C,		SEL_SIMCARD_2),
1484 	PINMUX_IPSR_MSEL(IP17_19_16,	SSI_SCK1_A,		SEL_SSI1_0),
1485 	PINMUX_IPSR_MSEL(IP17_19_16,	TS_SCK0_E,		SEL_TSIF0_4),
1486 	PINMUX_IPSR_MSEL(IP17_19_16,	STP_ISCLK_0_E,		SEL_SSP1_0_4),
1487 	PINMUX_IPSR_MSEL(IP17_19_16,	FMCLK_B,		SEL_FM_1),
1488 	PINMUX_IPSR_MSEL(IP17_19_16,	RIF2_CLK_B,		SEL_DRIF2_1),
1489 	PINMUX_IPSR_MSEL(IP17_19_16,	SPEEDIN_A,		SEL_SPEED_PULSE_0),
1490 	PINMUX_IPSR_MSEL(IP17_19_16,	HTX2_C,			SEL_HSCIF2_2),
1491 
1492 	PINMUX_IPSR_GPSR(IP17_23_20,	USB1_OVC),
1493 	PINMUX_IPSR_MSEL(IP17_23_20,	MSIOF1_SS2_C,		SEL_MSIOF1_2),
1494 	PINMUX_IPSR_MSEL(IP17_23_20,	SSI_WS1_A,		SEL_SSI1_0),
1495 	PINMUX_IPSR_MSEL(IP17_23_20,	TS_SDAT0_E,		SEL_TSIF0_4),
1496 	PINMUX_IPSR_MSEL(IP17_23_20,	STP_ISD_0_E,		SEL_SSP1_0_4),
1497 	PINMUX_IPSR_MSEL(IP17_23_20,	FMIN_B,			SEL_FM_1),
1498 	PINMUX_IPSR_MSEL(IP17_23_20,	RIF2_SYNC_B,		SEL_DRIF2_1),
1499 	PINMUX_IPSR_MSEL(IP17_23_20,	REMOCON_B,		SEL_REMOCON_1),
1500 	PINMUX_IPSR_MSEL(IP17_23_20,	HCTS2_N_C,		SEL_HSCIF2_2),
1501 
1502 	PINMUX_IPSR_GPSR(IP17_27_24,	USB30_PWEN),
1503 	PINMUX_IPSR_GPSR(IP17_27_24,	AUDIO_CLKOUT_B),
1504 	PINMUX_IPSR_MSEL(IP17_27_24,	SSI_SCK2_B,		SEL_SSI2_1),
1505 	PINMUX_IPSR_MSEL(IP17_27_24,	TS_SDEN1_D,		SEL_TSIF1_3),
1506 	PINMUX_IPSR_MSEL(IP17_27_24,	STP_ISEN_1_D,		SEL_SSP1_1_3),
1507 	PINMUX_IPSR_MSEL(IP17_27_24,	STP_OPWM_0_E,		SEL_SSP1_0_4),
1508 	PINMUX_IPSR_MSEL(IP17_27_24,	RIF3_D0_B,		SEL_DRIF3_1),
1509 	PINMUX_IPSR_MSEL(IP17_27_24,	TCLK2_B,		SEL_TIMER_TMU2_1),
1510 	PINMUX_IPSR_GPSR(IP17_27_24,	TPU0TO0),
1511 	PINMUX_IPSR_MSEL(IP17_27_24,	BPFCLK_C,		SEL_FM_2),
1512 	PINMUX_IPSR_MSEL(IP17_27_24,	HRTS2_N_C,		SEL_HSCIF2_2),
1513 
1514 	PINMUX_IPSR_GPSR(IP17_31_28,	USB30_OVC),
1515 	PINMUX_IPSR_GPSR(IP17_31_28,	AUDIO_CLKOUT1_B),
1516 	PINMUX_IPSR_MSEL(IP17_31_28,	SSI_WS2_B,		SEL_SSI2_1),
1517 	PINMUX_IPSR_MSEL(IP17_31_28,	TS_SPSYNC1_D,		SEL_TSIF1_3),
1518 	PINMUX_IPSR_MSEL(IP17_31_28,	STP_ISSYNC_1_D,		SEL_SSP1_1_3),
1519 	PINMUX_IPSR_MSEL(IP17_31_28,	STP_IVCXO27_0_E,	SEL_SSP1_0_4),
1520 	PINMUX_IPSR_MSEL(IP17_31_28,	RIF3_D1_B,		SEL_DRIF3_1),
1521 	PINMUX_IPSR_GPSR(IP17_31_28,	FSO_TOE_N),
1522 	PINMUX_IPSR_GPSR(IP17_31_28,	TPU0TO1),
1523 
1524 	/* IPSR18 */
1525 	PINMUX_IPSR_GPSR(IP18_3_0,	GP6_30),
1526 	PINMUX_IPSR_GPSR(IP18_3_0,	AUDIO_CLKOUT2_B),
1527 	PINMUX_IPSR_MSEL(IP18_3_0,	SSI_SCK9_B,		SEL_SSI9_1),
1528 	PINMUX_IPSR_MSEL(IP18_3_0,	TS_SDEN0_E,		SEL_TSIF0_4),
1529 	PINMUX_IPSR_MSEL(IP18_3_0,	STP_ISEN_0_E,		SEL_SSP1_0_4),
1530 	PINMUX_IPSR_MSEL(IP18_3_0,	RIF2_D0_B,		SEL_DRIF2_1),
1531 	PINMUX_IPSR_GPSR(IP18_3_0,	TPU0TO2),
1532 	PINMUX_IPSR_MSEL(IP18_3_0,	FMCLK_C,		SEL_FM_2),
1533 	PINMUX_IPSR_MSEL(IP18_3_0,	FMCLK_D,		SEL_FM_3),
1534 
1535 	PINMUX_IPSR_GPSR(IP18_7_4,	GP6_31),
1536 	PINMUX_IPSR_GPSR(IP18_7_4,	AUDIO_CLKOUT3_B),
1537 	PINMUX_IPSR_MSEL(IP18_7_4,	SSI_WS9_B,		SEL_SSI9_1),
1538 	PINMUX_IPSR_MSEL(IP18_7_4,	TS_SPSYNC0_E,		SEL_TSIF0_4),
1539 	PINMUX_IPSR_MSEL(IP18_7_4,	STP_ISSYNC_0_E,		SEL_SSP1_0_4),
1540 	PINMUX_IPSR_MSEL(IP18_7_4,	RIF2_D1_B,		SEL_DRIF2_1),
1541 	PINMUX_IPSR_GPSR(IP18_7_4,	TPU0TO3),
1542 	PINMUX_IPSR_MSEL(IP18_7_4,	FMIN_C,			SEL_FM_2),
1543 	PINMUX_IPSR_MSEL(IP18_7_4,	FMIN_D,			SEL_FM_3),
1544 
1545 /*
1546  * Static pins can not be muxed between different functions but
1547  * still need mark entries in the pinmux list. Add each static
1548  * pin to the list without an associated function. The sh-pfc
1549  * core will do the right thing and skip trying to mux the pin
1550  * while still applying configuration to it.
1551  */
1552 #define FM(x)   PINMUX_DATA(x##_MARK, 0),
1553 	PINMUX_STATIC
1554 #undef FM
1555 };
1556 
1557 /*
1558  * Pins not associated with a GPIO port.
1559  */
1560 enum {
1561 	GP_ASSIGN_LAST(),
1562 	NOGP_ALL(),
1563 };
1564 
1565 static const struct sh_pfc_pin pinmux_pins[] = {
1566 	PINMUX_GPIO_GP_ALL(),
1567 	PINMUX_NOGP_ALL(),
1568 };
1569 
1570 /* - AUDIO CLOCK ------------------------------------------------------------ */
1571 static const unsigned int audio_clk_a_a_pins[] = {
1572 	/* CLK A */
1573 	RCAR_GP_PIN(6, 22),
1574 };
1575 static const unsigned int audio_clk_a_a_mux[] = {
1576 	AUDIO_CLKA_A_MARK,
1577 };
1578 static const unsigned int audio_clk_a_b_pins[] = {
1579 	/* CLK A */
1580 	RCAR_GP_PIN(5, 4),
1581 };
1582 static const unsigned int audio_clk_a_b_mux[] = {
1583 	AUDIO_CLKA_B_MARK,
1584 };
1585 static const unsigned int audio_clk_a_c_pins[] = {
1586 	/* CLK A */
1587 	RCAR_GP_PIN(5, 19),
1588 };
1589 static const unsigned int audio_clk_a_c_mux[] = {
1590 	AUDIO_CLKA_C_MARK,
1591 };
1592 static const unsigned int audio_clk_b_a_pins[] = {
1593 	/* CLK B */
1594 	RCAR_GP_PIN(5, 12),
1595 };
1596 static const unsigned int audio_clk_b_a_mux[] = {
1597 	AUDIO_CLKB_A_MARK,
1598 };
1599 static const unsigned int audio_clk_b_b_pins[] = {
1600 	/* CLK B */
1601 	RCAR_GP_PIN(6, 23),
1602 };
1603 static const unsigned int audio_clk_b_b_mux[] = {
1604 	AUDIO_CLKB_B_MARK,
1605 };
1606 static const unsigned int audio_clk_c_a_pins[] = {
1607 	/* CLK C */
1608 	RCAR_GP_PIN(5, 21),
1609 };
1610 static const unsigned int audio_clk_c_a_mux[] = {
1611 	AUDIO_CLKC_A_MARK,
1612 };
1613 static const unsigned int audio_clk_c_b_pins[] = {
1614 	/* CLK C */
1615 	RCAR_GP_PIN(5, 0),
1616 };
1617 static const unsigned int audio_clk_c_b_mux[] = {
1618 	AUDIO_CLKC_B_MARK,
1619 };
1620 static const unsigned int audio_clkout_a_pins[] = {
1621 	/* CLKOUT */
1622 	RCAR_GP_PIN(5, 18),
1623 };
1624 static const unsigned int audio_clkout_a_mux[] = {
1625 	AUDIO_CLKOUT_A_MARK,
1626 };
1627 static const unsigned int audio_clkout_b_pins[] = {
1628 	/* CLKOUT */
1629 	RCAR_GP_PIN(6, 28),
1630 };
1631 static const unsigned int audio_clkout_b_mux[] = {
1632 	AUDIO_CLKOUT_B_MARK,
1633 };
1634 static const unsigned int audio_clkout_c_pins[] = {
1635 	/* CLKOUT */
1636 	RCAR_GP_PIN(5, 3),
1637 };
1638 static const unsigned int audio_clkout_c_mux[] = {
1639 	AUDIO_CLKOUT_C_MARK,
1640 };
1641 static const unsigned int audio_clkout_d_pins[] = {
1642 	/* CLKOUT */
1643 	RCAR_GP_PIN(5, 21),
1644 };
1645 static const unsigned int audio_clkout_d_mux[] = {
1646 	AUDIO_CLKOUT_D_MARK,
1647 };
1648 static const unsigned int audio_clkout1_a_pins[] = {
1649 	/* CLKOUT1 */
1650 	RCAR_GP_PIN(5, 15),
1651 };
1652 static const unsigned int audio_clkout1_a_mux[] = {
1653 	AUDIO_CLKOUT1_A_MARK,
1654 };
1655 static const unsigned int audio_clkout1_b_pins[] = {
1656 	/* CLKOUT1 */
1657 	RCAR_GP_PIN(6, 29),
1658 };
1659 static const unsigned int audio_clkout1_b_mux[] = {
1660 	AUDIO_CLKOUT1_B_MARK,
1661 };
1662 static const unsigned int audio_clkout2_a_pins[] = {
1663 	/* CLKOUT2 */
1664 	RCAR_GP_PIN(5, 16),
1665 };
1666 static const unsigned int audio_clkout2_a_mux[] = {
1667 	AUDIO_CLKOUT2_A_MARK,
1668 };
1669 static const unsigned int audio_clkout2_b_pins[] = {
1670 	/* CLKOUT2 */
1671 	RCAR_GP_PIN(6, 30),
1672 };
1673 static const unsigned int audio_clkout2_b_mux[] = {
1674 	AUDIO_CLKOUT2_B_MARK,
1675 };
1676 
1677 static const unsigned int audio_clkout3_a_pins[] = {
1678 	/* CLKOUT3 */
1679 	RCAR_GP_PIN(5, 19),
1680 };
1681 static const unsigned int audio_clkout3_a_mux[] = {
1682 	AUDIO_CLKOUT3_A_MARK,
1683 };
1684 static const unsigned int audio_clkout3_b_pins[] = {
1685 	/* CLKOUT3 */
1686 	RCAR_GP_PIN(6, 31),
1687 };
1688 static const unsigned int audio_clkout3_b_mux[] = {
1689 	AUDIO_CLKOUT3_B_MARK,
1690 };
1691 
1692 /* - EtherAVB --------------------------------------------------------------- */
1693 static const unsigned int avb_link_pins[] = {
1694 	/* AVB_LINK */
1695 	RCAR_GP_PIN(2, 12),
1696 };
1697 static const unsigned int avb_link_mux[] = {
1698 	AVB_LINK_MARK,
1699 };
1700 static const unsigned int avb_magic_pins[] = {
1701 	/* AVB_MAGIC_ */
1702 	RCAR_GP_PIN(2, 10),
1703 };
1704 static const unsigned int avb_magic_mux[] = {
1705 	AVB_MAGIC_MARK,
1706 };
1707 static const unsigned int avb_phy_int_pins[] = {
1708 	/* AVB_PHY_INT */
1709 	RCAR_GP_PIN(2, 11),
1710 };
1711 static const unsigned int avb_phy_int_mux[] = {
1712 	AVB_PHY_INT_MARK,
1713 };
1714 static const unsigned int avb_mdio_pins[] = {
1715 	/* AVB_MDC, AVB_MDIO */
1716 	RCAR_GP_PIN(2, 9), PIN_AVB_MDIO,
1717 };
1718 static const unsigned int avb_mdio_mux[] = {
1719 	AVB_MDC_MARK, AVB_MDIO_MARK,
1720 };
1721 static const unsigned int avb_mii_pins[] = {
1722 	/*
1723 	 * AVB_TX_CTL, AVB_TXC, AVB_TD0,
1724 	 * AVB_TD1, AVB_TD2, AVB_TD3,
1725 	 * AVB_RX_CTL, AVB_RXC, AVB_RD0,
1726 	 * AVB_RD1, AVB_RD2, AVB_RD3,
1727 	 * AVB_TXCREFCLK
1728 	 */
1729 	PIN_AVB_TX_CTL, PIN_AVB_TXC, PIN_AVB_TD0,
1730 	PIN_AVB_TD1, PIN_AVB_TD2, PIN_AVB_TD3,
1731 	PIN_AVB_RX_CTL, PIN_AVB_RXC, PIN_AVB_RD0,
1732 	PIN_AVB_RD1, PIN_AVB_RD2, PIN_AVB_RD3,
1733 	PIN_AVB_TXCREFCLK,
1734 };
1735 static const unsigned int avb_mii_mux[] = {
1736 	AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
1737 	AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
1738 	AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
1739 	AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
1740 	AVB_TXCREFCLK_MARK,
1741 };
1742 static const unsigned int avb_avtp_pps_pins[] = {
1743 	/* AVB_AVTP_PPS */
1744 	RCAR_GP_PIN(2, 6),
1745 };
1746 static const unsigned int avb_avtp_pps_mux[] = {
1747 	AVB_AVTP_PPS_MARK,
1748 };
1749 static const unsigned int avb_avtp_match_a_pins[] = {
1750 	/* AVB_AVTP_MATCH_A */
1751 	RCAR_GP_PIN(2, 13),
1752 };
1753 static const unsigned int avb_avtp_match_a_mux[] = {
1754 	AVB_AVTP_MATCH_A_MARK,
1755 };
1756 static const unsigned int avb_avtp_capture_a_pins[] = {
1757 	/* AVB_AVTP_CAPTURE_A */
1758 	RCAR_GP_PIN(2, 14),
1759 };
1760 static const unsigned int avb_avtp_capture_a_mux[] = {
1761 	AVB_AVTP_CAPTURE_A_MARK,
1762 };
1763 static const unsigned int avb_avtp_match_b_pins[] = {
1764 	/*  AVB_AVTP_MATCH_B */
1765 	RCAR_GP_PIN(1, 8),
1766 };
1767 static const unsigned int avb_avtp_match_b_mux[] = {
1768 	AVB_AVTP_MATCH_B_MARK,
1769 };
1770 static const unsigned int avb_avtp_capture_b_pins[] = {
1771 	/* AVB_AVTP_CAPTURE_B */
1772 	RCAR_GP_PIN(1, 11),
1773 };
1774 static const unsigned int avb_avtp_capture_b_mux[] = {
1775 	AVB_AVTP_CAPTURE_B_MARK,
1776 };
1777 
1778 /* - CAN ------------------------------------------------------------------ */
1779 static const unsigned int can0_data_a_pins[] = {
1780 	/* TX, RX */
1781 	RCAR_GP_PIN(1, 23),	RCAR_GP_PIN(1, 24),
1782 };
1783 static const unsigned int can0_data_a_mux[] = {
1784 	CAN0_TX_A_MARK,		CAN0_RX_A_MARK,
1785 };
1786 static const unsigned int can0_data_b_pins[] = {
1787 	/* TX, RX */
1788 	RCAR_GP_PIN(2, 0),	RCAR_GP_PIN(2, 1),
1789 };
1790 static const unsigned int can0_data_b_mux[] = {
1791 	CAN0_TX_B_MARK,		CAN0_RX_B_MARK,
1792 };
1793 static const unsigned int can1_data_pins[] = {
1794 	/* TX, RX */
1795 	RCAR_GP_PIN(1, 22),	RCAR_GP_PIN(1, 26),
1796 };
1797 static const unsigned int can1_data_mux[] = {
1798 	CAN1_TX_MARK,		CAN1_RX_MARK,
1799 };
1800 
1801 /* - CAN Clock -------------------------------------------------------------- */
1802 static const unsigned int can_clk_pins[] = {
1803 	/* CLK */
1804 	RCAR_GP_PIN(1, 25),
1805 };
1806 static const unsigned int can_clk_mux[] = {
1807 	CAN_CLK_MARK,
1808 };
1809 
1810 /* - CAN FD --------------------------------------------------------------- */
1811 static const unsigned int canfd0_data_a_pins[] = {
1812 	/* TX, RX */
1813 	RCAR_GP_PIN(1, 23),     RCAR_GP_PIN(1, 24),
1814 };
1815 static const unsigned int canfd0_data_a_mux[] = {
1816 	CANFD0_TX_A_MARK,       CANFD0_RX_A_MARK,
1817 };
1818 static const unsigned int canfd0_data_b_pins[] = {
1819 	/* TX, RX */
1820 	RCAR_GP_PIN(2, 0),      RCAR_GP_PIN(2, 1),
1821 };
1822 static const unsigned int canfd0_data_b_mux[] = {
1823 	CANFD0_TX_B_MARK,       CANFD0_RX_B_MARK,
1824 };
1825 static const unsigned int canfd1_data_pins[] = {
1826 	/* TX, RX */
1827 	RCAR_GP_PIN(1, 22),     RCAR_GP_PIN(1, 26),
1828 };
1829 static const unsigned int canfd1_data_mux[] = {
1830 	CANFD1_TX_MARK,         CANFD1_RX_MARK,
1831 };
1832 
1833 #if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
1834 /* - DRIF0 --------------------------------------------------------------- */
1835 static const unsigned int drif0_ctrl_a_pins[] = {
1836 	/* CLK, SYNC */
1837 	RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1838 };
1839 static const unsigned int drif0_ctrl_a_mux[] = {
1840 	RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
1841 };
1842 static const unsigned int drif0_data0_a_pins[] = {
1843 	/* D0 */
1844 	RCAR_GP_PIN(6, 10),
1845 };
1846 static const unsigned int drif0_data0_a_mux[] = {
1847 	RIF0_D0_A_MARK,
1848 };
1849 static const unsigned int drif0_data1_a_pins[] = {
1850 	/* D1 */
1851 	RCAR_GP_PIN(6, 7),
1852 };
1853 static const unsigned int drif0_data1_a_mux[] = {
1854 	RIF0_D1_A_MARK,
1855 };
1856 static const unsigned int drif0_ctrl_b_pins[] = {
1857 	/* CLK, SYNC */
1858 	RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
1859 };
1860 static const unsigned int drif0_ctrl_b_mux[] = {
1861 	RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
1862 };
1863 static const unsigned int drif0_data0_b_pins[] = {
1864 	/* D0 */
1865 	RCAR_GP_PIN(5, 1),
1866 };
1867 static const unsigned int drif0_data0_b_mux[] = {
1868 	RIF0_D0_B_MARK,
1869 };
1870 static const unsigned int drif0_data1_b_pins[] = {
1871 	/* D1 */
1872 	RCAR_GP_PIN(5, 2),
1873 };
1874 static const unsigned int drif0_data1_b_mux[] = {
1875 	RIF0_D1_B_MARK,
1876 };
1877 static const unsigned int drif0_ctrl_c_pins[] = {
1878 	/* CLK, SYNC */
1879 	RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15),
1880 };
1881 static const unsigned int drif0_ctrl_c_mux[] = {
1882 	RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK,
1883 };
1884 static const unsigned int drif0_data0_c_pins[] = {
1885 	/* D0 */
1886 	RCAR_GP_PIN(5, 13),
1887 };
1888 static const unsigned int drif0_data0_c_mux[] = {
1889 	RIF0_D0_C_MARK,
1890 };
1891 static const unsigned int drif0_data1_c_pins[] = {
1892 	/* D1 */
1893 	RCAR_GP_PIN(5, 14),
1894 };
1895 static const unsigned int drif0_data1_c_mux[] = {
1896 	RIF0_D1_C_MARK,
1897 };
1898 /* - DRIF1 --------------------------------------------------------------- */
1899 static const unsigned int drif1_ctrl_a_pins[] = {
1900 	/* CLK, SYNC */
1901 	RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
1902 };
1903 static const unsigned int drif1_ctrl_a_mux[] = {
1904 	RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK,
1905 };
1906 static const unsigned int drif1_data0_a_pins[] = {
1907 	/* D0 */
1908 	RCAR_GP_PIN(6, 19),
1909 };
1910 static const unsigned int drif1_data0_a_mux[] = {
1911 	RIF1_D0_A_MARK,
1912 };
1913 static const unsigned int drif1_data1_a_pins[] = {
1914 	/* D1 */
1915 	RCAR_GP_PIN(6, 20),
1916 };
1917 static const unsigned int drif1_data1_a_mux[] = {
1918 	RIF1_D1_A_MARK,
1919 };
1920 static const unsigned int drif1_ctrl_b_pins[] = {
1921 	/* CLK, SYNC */
1922 	RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3),
1923 };
1924 static const unsigned int drif1_ctrl_b_mux[] = {
1925 	RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK,
1926 };
1927 static const unsigned int drif1_data0_b_pins[] = {
1928 	/* D0 */
1929 	RCAR_GP_PIN(5, 7),
1930 };
1931 static const unsigned int drif1_data0_b_mux[] = {
1932 	RIF1_D0_B_MARK,
1933 };
1934 static const unsigned int drif1_data1_b_pins[] = {
1935 	/* D1 */
1936 	RCAR_GP_PIN(5, 8),
1937 };
1938 static const unsigned int drif1_data1_b_mux[] = {
1939 	RIF1_D1_B_MARK,
1940 };
1941 static const unsigned int drif1_ctrl_c_pins[] = {
1942 	/* CLK, SYNC */
1943 	RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
1944 };
1945 static const unsigned int drif1_ctrl_c_mux[] = {
1946 	RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK,
1947 };
1948 static const unsigned int drif1_data0_c_pins[] = {
1949 	/* D0 */
1950 	RCAR_GP_PIN(5, 6),
1951 };
1952 static const unsigned int drif1_data0_c_mux[] = {
1953 	RIF1_D0_C_MARK,
1954 };
1955 static const unsigned int drif1_data1_c_pins[] = {
1956 	/* D1 */
1957 	RCAR_GP_PIN(5, 10),
1958 };
1959 static const unsigned int drif1_data1_c_mux[] = {
1960 	RIF1_D1_C_MARK,
1961 };
1962 /* - DRIF2 --------------------------------------------------------------- */
1963 static const unsigned int drif2_ctrl_a_pins[] = {
1964 	/* CLK, SYNC */
1965 	RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1966 };
1967 static const unsigned int drif2_ctrl_a_mux[] = {
1968 	RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
1969 };
1970 static const unsigned int drif2_data0_a_pins[] = {
1971 	/* D0 */
1972 	RCAR_GP_PIN(6, 7),
1973 };
1974 static const unsigned int drif2_data0_a_mux[] = {
1975 	RIF2_D0_A_MARK,
1976 };
1977 static const unsigned int drif2_data1_a_pins[] = {
1978 	/* D1 */
1979 	RCAR_GP_PIN(6, 10),
1980 };
1981 static const unsigned int drif2_data1_a_mux[] = {
1982 	RIF2_D1_A_MARK,
1983 };
1984 static const unsigned int drif2_ctrl_b_pins[] = {
1985 	/* CLK, SYNC */
1986 	RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
1987 };
1988 static const unsigned int drif2_ctrl_b_mux[] = {
1989 	RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
1990 };
1991 static const unsigned int drif2_data0_b_pins[] = {
1992 	/* D0 */
1993 	RCAR_GP_PIN(6, 30),
1994 };
1995 static const unsigned int drif2_data0_b_mux[] = {
1996 	RIF2_D0_B_MARK,
1997 };
1998 static const unsigned int drif2_data1_b_pins[] = {
1999 	/* D1 */
2000 	RCAR_GP_PIN(6, 31),
2001 };
2002 static const unsigned int drif2_data1_b_mux[] = {
2003 	RIF2_D1_B_MARK,
2004 };
2005 /* - DRIF3 --------------------------------------------------------------- */
2006 static const unsigned int drif3_ctrl_a_pins[] = {
2007 	/* CLK, SYNC */
2008 	RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2009 };
2010 static const unsigned int drif3_ctrl_a_mux[] = {
2011 	RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
2012 };
2013 static const unsigned int drif3_data0_a_pins[] = {
2014 	/* D0 */
2015 	RCAR_GP_PIN(6, 19),
2016 };
2017 static const unsigned int drif3_data0_a_mux[] = {
2018 	RIF3_D0_A_MARK,
2019 };
2020 static const unsigned int drif3_data1_a_pins[] = {
2021 	/* D1 */
2022 	RCAR_GP_PIN(6, 20),
2023 };
2024 static const unsigned int drif3_data1_a_mux[] = {
2025 	RIF3_D1_A_MARK,
2026 };
2027 static const unsigned int drif3_ctrl_b_pins[] = {
2028 	/* CLK, SYNC */
2029 	RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
2030 };
2031 static const unsigned int drif3_ctrl_b_mux[] = {
2032 	RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
2033 };
2034 static const unsigned int drif3_data0_b_pins[] = {
2035 	/* D0 */
2036 	RCAR_GP_PIN(6, 28),
2037 };
2038 static const unsigned int drif3_data0_b_mux[] = {
2039 	RIF3_D0_B_MARK,
2040 };
2041 static const unsigned int drif3_data1_b_pins[] = {
2042 	/* D1 */
2043 	RCAR_GP_PIN(6, 29),
2044 };
2045 static const unsigned int drif3_data1_b_mux[] = {
2046 	RIF3_D1_B_MARK,
2047 };
2048 #endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */
2049 
2050 /* - DU --------------------------------------------------------------------- */
2051 static const unsigned int du_rgb666_pins[] = {
2052 	/* R[7:2], G[7:2], B[7:2] */
2053 	RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2054 	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2055 	RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2056 	RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2057 	RCAR_GP_PIN(1, 7),  RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 5),
2058 	RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 2),
2059 };
2060 static const unsigned int du_rgb666_mux[] = {
2061 	DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2062 	DU_DR3_MARK, DU_DR2_MARK,
2063 	DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2064 	DU_DG3_MARK, DU_DG2_MARK,
2065 	DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2066 	DU_DB3_MARK, DU_DB2_MARK,
2067 };
2068 static const unsigned int du_rgb888_pins[] = {
2069 	/* R[7:0], G[7:0], B[7:0] */
2070 	RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2071 	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2072 	RCAR_GP_PIN(0, 9),  RCAR_GP_PIN(0, 8),
2073 	RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2074 	RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2075 	RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
2076 	RCAR_GP_PIN(1, 7),  RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 5),
2077 	RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 2),
2078 	RCAR_GP_PIN(1, 1),  RCAR_GP_PIN(1, 0),
2079 };
2080 static const unsigned int du_rgb888_mux[] = {
2081 	DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2082 	DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
2083 	DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2084 	DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
2085 	DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2086 	DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
2087 };
2088 static const unsigned int du_clk_out_0_pins[] = {
2089 	/* CLKOUT */
2090 	RCAR_GP_PIN(1, 27),
2091 };
2092 static const unsigned int du_clk_out_0_mux[] = {
2093 	DU_DOTCLKOUT0_MARK
2094 };
2095 static const unsigned int du_clk_out_1_pins[] = {
2096 	/* CLKOUT */
2097 	RCAR_GP_PIN(2, 3),
2098 };
2099 static const unsigned int du_clk_out_1_mux[] = {
2100 	DU_DOTCLKOUT1_MARK
2101 };
2102 static const unsigned int du_sync_pins[] = {
2103 	/* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
2104 	RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
2105 };
2106 static const unsigned int du_sync_mux[] = {
2107 	DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
2108 };
2109 static const unsigned int du_oddf_pins[] = {
2110 	/* EXDISP/EXODDF/EXCDE */
2111 	RCAR_GP_PIN(2, 2),
2112 };
2113 static const unsigned int du_oddf_mux[] = {
2114 	DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
2115 };
2116 static const unsigned int du_cde_pins[] = {
2117 	/* CDE */
2118 	RCAR_GP_PIN(2, 0),
2119 };
2120 static const unsigned int du_cde_mux[] = {
2121 	DU_CDE_MARK,
2122 };
2123 static const unsigned int du_disp_pins[] = {
2124 	/* DISP */
2125 	RCAR_GP_PIN(2, 1),
2126 };
2127 static const unsigned int du_disp_mux[] = {
2128 	DU_DISP_MARK,
2129 };
2130 
2131 /* - HSCIF0 ----------------------------------------------------------------- */
2132 static const unsigned int hscif0_data_pins[] = {
2133 	/* RX, TX */
2134 	RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
2135 };
2136 static const unsigned int hscif0_data_mux[] = {
2137 	HRX0_MARK, HTX0_MARK,
2138 };
2139 static const unsigned int hscif0_clk_pins[] = {
2140 	/* SCK */
2141 	RCAR_GP_PIN(5, 12),
2142 };
2143 static const unsigned int hscif0_clk_mux[] = {
2144 	HSCK0_MARK,
2145 };
2146 static const unsigned int hscif0_ctrl_pins[] = {
2147 	/* RTS, CTS */
2148 	RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
2149 };
2150 static const unsigned int hscif0_ctrl_mux[] = {
2151 	HRTS0_N_MARK, HCTS0_N_MARK,
2152 };
2153 /* - HSCIF1 ----------------------------------------------------------------- */
2154 static const unsigned int hscif1_data_a_pins[] = {
2155 	/* RX, TX */
2156 	RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2157 };
2158 static const unsigned int hscif1_data_a_mux[] = {
2159 	HRX1_A_MARK, HTX1_A_MARK,
2160 };
2161 static const unsigned int hscif1_clk_a_pins[] = {
2162 	/* SCK */
2163 	RCAR_GP_PIN(6, 21),
2164 };
2165 static const unsigned int hscif1_clk_a_mux[] = {
2166 	HSCK1_A_MARK,
2167 };
2168 static const unsigned int hscif1_ctrl_a_pins[] = {
2169 	/* RTS, CTS */
2170 	RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
2171 };
2172 static const unsigned int hscif1_ctrl_a_mux[] = {
2173 	HRTS1_N_A_MARK, HCTS1_N_A_MARK,
2174 };
2175 
2176 static const unsigned int hscif1_data_b_pins[] = {
2177 	/* RX, TX */
2178 	RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2179 };
2180 static const unsigned int hscif1_data_b_mux[] = {
2181 	HRX1_B_MARK, HTX1_B_MARK,
2182 };
2183 static const unsigned int hscif1_clk_b_pins[] = {
2184 	/* SCK */
2185 	RCAR_GP_PIN(5, 0),
2186 };
2187 static const unsigned int hscif1_clk_b_mux[] = {
2188 	HSCK1_B_MARK,
2189 };
2190 static const unsigned int hscif1_ctrl_b_pins[] = {
2191 	/* RTS, CTS */
2192 	RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
2193 };
2194 static const unsigned int hscif1_ctrl_b_mux[] = {
2195 	HRTS1_N_B_MARK, HCTS1_N_B_MARK,
2196 };
2197 /* - HSCIF2 ----------------------------------------------------------------- */
2198 static const unsigned int hscif2_data_a_pins[] = {
2199 	/* RX, TX */
2200 	RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
2201 };
2202 static const unsigned int hscif2_data_a_mux[] = {
2203 	HRX2_A_MARK, HTX2_A_MARK,
2204 };
2205 static const unsigned int hscif2_clk_a_pins[] = {
2206 	/* SCK */
2207 	RCAR_GP_PIN(6, 10),
2208 };
2209 static const unsigned int hscif2_clk_a_mux[] = {
2210 	HSCK2_A_MARK,
2211 };
2212 static const unsigned int hscif2_ctrl_a_pins[] = {
2213 	/* RTS, CTS */
2214 	RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
2215 };
2216 static const unsigned int hscif2_ctrl_a_mux[] = {
2217 	HRTS2_N_A_MARK, HCTS2_N_A_MARK,
2218 };
2219 
2220 static const unsigned int hscif2_data_b_pins[] = {
2221 	/* RX, TX */
2222 	RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2223 };
2224 static const unsigned int hscif2_data_b_mux[] = {
2225 	HRX2_B_MARK, HTX2_B_MARK,
2226 };
2227 static const unsigned int hscif2_clk_b_pins[] = {
2228 	/* SCK */
2229 	RCAR_GP_PIN(6, 21),
2230 };
2231 static const unsigned int hscif2_clk_b_mux[] = {
2232 	HSCK2_B_MARK,
2233 };
2234 static const unsigned int hscif2_ctrl_b_pins[] = {
2235 	/* RTS, CTS */
2236 	RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19),
2237 };
2238 static const unsigned int hscif2_ctrl_b_mux[] = {
2239 	HRTS2_N_B_MARK, HCTS2_N_B_MARK,
2240 };
2241 
2242 static const unsigned int hscif2_data_c_pins[] = {
2243 	/* RX, TX */
2244 	RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26),
2245 };
2246 static const unsigned int hscif2_data_c_mux[] = {
2247 	HRX2_C_MARK, HTX2_C_MARK,
2248 };
2249 static const unsigned int hscif2_clk_c_pins[] = {
2250 	/* SCK */
2251 	RCAR_GP_PIN(6, 24),
2252 };
2253 static const unsigned int hscif2_clk_c_mux[] = {
2254 	HSCK2_C_MARK,
2255 };
2256 static const unsigned int hscif2_ctrl_c_pins[] = {
2257 	/* RTS, CTS */
2258 	RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 27),
2259 };
2260 static const unsigned int hscif2_ctrl_c_mux[] = {
2261 	HRTS2_N_C_MARK, HCTS2_N_C_MARK,
2262 };
2263 /* - HSCIF3 ----------------------------------------------------------------- */
2264 static const unsigned int hscif3_data_a_pins[] = {
2265 	/* RX, TX */
2266 	RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
2267 };
2268 static const unsigned int hscif3_data_a_mux[] = {
2269 	HRX3_A_MARK, HTX3_A_MARK,
2270 };
2271 static const unsigned int hscif3_clk_pins[] = {
2272 	/* SCK */
2273 	RCAR_GP_PIN(1, 22),
2274 };
2275 static const unsigned int hscif3_clk_mux[] = {
2276 	HSCK3_MARK,
2277 };
2278 static const unsigned int hscif3_ctrl_pins[] = {
2279 	/* RTS, CTS */
2280 	RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2281 };
2282 static const unsigned int hscif3_ctrl_mux[] = {
2283 	HRTS3_N_MARK, HCTS3_N_MARK,
2284 };
2285 
2286 static const unsigned int hscif3_data_b_pins[] = {
2287 	/* RX, TX */
2288 	RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
2289 };
2290 static const unsigned int hscif3_data_b_mux[] = {
2291 	HRX3_B_MARK, HTX3_B_MARK,
2292 };
2293 static const unsigned int hscif3_data_c_pins[] = {
2294 	/* RX, TX */
2295 	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2296 };
2297 static const unsigned int hscif3_data_c_mux[] = {
2298 	HRX3_C_MARK, HTX3_C_MARK,
2299 };
2300 static const unsigned int hscif3_data_d_pins[] = {
2301 	/* RX, TX */
2302 	RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2303 };
2304 static const unsigned int hscif3_data_d_mux[] = {
2305 	HRX3_D_MARK, HTX3_D_MARK,
2306 };
2307 /* - HSCIF4 ----------------------------------------------------------------- */
2308 static const unsigned int hscif4_data_a_pins[] = {
2309 	/* RX, TX */
2310 	RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
2311 };
2312 static const unsigned int hscif4_data_a_mux[] = {
2313 	HRX4_A_MARK, HTX4_A_MARK,
2314 };
2315 static const unsigned int hscif4_clk_pins[] = {
2316 	/* SCK */
2317 	RCAR_GP_PIN(1, 11),
2318 };
2319 static const unsigned int hscif4_clk_mux[] = {
2320 	HSCK4_MARK,
2321 };
2322 static const unsigned int hscif4_ctrl_pins[] = {
2323 	/* RTS, CTS */
2324 	RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
2325 };
2326 static const unsigned int hscif4_ctrl_mux[] = {
2327 	HRTS4_N_MARK, HCTS4_N_MARK,
2328 };
2329 
2330 static const unsigned int hscif4_data_b_pins[] = {
2331 	/* RX, TX */
2332 	RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2333 };
2334 static const unsigned int hscif4_data_b_mux[] = {
2335 	HRX4_B_MARK, HTX4_B_MARK,
2336 };
2337 
2338 /* - I2C -------------------------------------------------------------------- */
2339 static const unsigned int i2c0_pins[] = {
2340 	/* SCL, SDA */
2341 	RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
2342 };
2343 
2344 static const unsigned int i2c0_mux[] = {
2345 	SCL0_MARK, SDA0_MARK,
2346 };
2347 
2348 static const unsigned int i2c1_a_pins[] = {
2349 	/* SDA, SCL */
2350 	RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
2351 };
2352 static const unsigned int i2c1_a_mux[] = {
2353 	SDA1_A_MARK, SCL1_A_MARK,
2354 };
2355 static const unsigned int i2c1_b_pins[] = {
2356 	/* SDA, SCL */
2357 	RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
2358 };
2359 static const unsigned int i2c1_b_mux[] = {
2360 	SDA1_B_MARK, SCL1_B_MARK,
2361 };
2362 static const unsigned int i2c2_a_pins[] = {
2363 	/* SDA, SCL */
2364 	RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
2365 };
2366 static const unsigned int i2c2_a_mux[] = {
2367 	SDA2_A_MARK, SCL2_A_MARK,
2368 };
2369 static const unsigned int i2c2_b_pins[] = {
2370 	/* SDA, SCL */
2371 	RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
2372 };
2373 static const unsigned int i2c2_b_mux[] = {
2374 	SDA2_B_MARK, SCL2_B_MARK,
2375 };
2376 
2377 static const unsigned int i2c3_pins[] = {
2378 	/* SCL, SDA */
2379 	RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2380 };
2381 
2382 static const unsigned int i2c3_mux[] = {
2383 	SCL3_MARK, SDA3_MARK,
2384 };
2385 
2386 static const unsigned int i2c5_pins[] = {
2387 	/* SCL, SDA */
2388 	RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
2389 };
2390 
2391 static const unsigned int i2c5_mux[] = {
2392 	SCL5_MARK, SDA5_MARK,
2393 };
2394 
2395 static const unsigned int i2c6_a_pins[] = {
2396 	/* SDA, SCL */
2397 	RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2398 };
2399 static const unsigned int i2c6_a_mux[] = {
2400 	SDA6_A_MARK, SCL6_A_MARK,
2401 };
2402 static const unsigned int i2c6_b_pins[] = {
2403 	/* SDA, SCL */
2404 	RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2405 };
2406 static const unsigned int i2c6_b_mux[] = {
2407 	SDA6_B_MARK, SCL6_B_MARK,
2408 };
2409 static const unsigned int i2c6_c_pins[] = {
2410 	/* SDA, SCL */
2411 	RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
2412 };
2413 static const unsigned int i2c6_c_mux[] = {
2414 	SDA6_C_MARK, SCL6_C_MARK,
2415 };
2416 
2417 /* - INTC-EX ---------------------------------------------------------------- */
2418 static const unsigned int intc_ex_irq0_pins[] = {
2419 	/* IRQ0 */
2420 	RCAR_GP_PIN(2, 0),
2421 };
2422 static const unsigned int intc_ex_irq0_mux[] = {
2423 	IRQ0_MARK,
2424 };
2425 static const unsigned int intc_ex_irq1_pins[] = {
2426 	/* IRQ1 */
2427 	RCAR_GP_PIN(2, 1),
2428 };
2429 static const unsigned int intc_ex_irq1_mux[] = {
2430 	IRQ1_MARK,
2431 };
2432 static const unsigned int intc_ex_irq2_pins[] = {
2433 	/* IRQ2 */
2434 	RCAR_GP_PIN(2, 2),
2435 };
2436 static const unsigned int intc_ex_irq2_mux[] = {
2437 	IRQ2_MARK,
2438 };
2439 static const unsigned int intc_ex_irq3_pins[] = {
2440 	/* IRQ3 */
2441 	RCAR_GP_PIN(2, 3),
2442 };
2443 static const unsigned int intc_ex_irq3_mux[] = {
2444 	IRQ3_MARK,
2445 };
2446 static const unsigned int intc_ex_irq4_pins[] = {
2447 	/* IRQ4 */
2448 	RCAR_GP_PIN(2, 4),
2449 };
2450 static const unsigned int intc_ex_irq4_mux[] = {
2451 	IRQ4_MARK,
2452 };
2453 static const unsigned int intc_ex_irq5_pins[] = {
2454 	/* IRQ5 */
2455 	RCAR_GP_PIN(2, 5),
2456 };
2457 static const unsigned int intc_ex_irq5_mux[] = {
2458 	IRQ5_MARK,
2459 };
2460 
2461 /* - MSIOF0 ----------------------------------------------------------------- */
2462 static const unsigned int msiof0_clk_pins[] = {
2463 	/* SCK */
2464 	RCAR_GP_PIN(5, 17),
2465 };
2466 static const unsigned int msiof0_clk_mux[] = {
2467 	MSIOF0_SCK_MARK,
2468 };
2469 static const unsigned int msiof0_sync_pins[] = {
2470 	/* SYNC */
2471 	RCAR_GP_PIN(5, 18),
2472 };
2473 static const unsigned int msiof0_sync_mux[] = {
2474 	MSIOF0_SYNC_MARK,
2475 };
2476 static const unsigned int msiof0_ss1_pins[] = {
2477 	/* SS1 */
2478 	RCAR_GP_PIN(5, 19),
2479 };
2480 static const unsigned int msiof0_ss1_mux[] = {
2481 	MSIOF0_SS1_MARK,
2482 };
2483 static const unsigned int msiof0_ss2_pins[] = {
2484 	/* SS2 */
2485 	RCAR_GP_PIN(5, 21),
2486 };
2487 static const unsigned int msiof0_ss2_mux[] = {
2488 	MSIOF0_SS2_MARK,
2489 };
2490 static const unsigned int msiof0_txd_pins[] = {
2491 	/* TXD */
2492 	RCAR_GP_PIN(5, 20),
2493 };
2494 static const unsigned int msiof0_txd_mux[] = {
2495 	MSIOF0_TXD_MARK,
2496 };
2497 static const unsigned int msiof0_rxd_pins[] = {
2498 	/* RXD */
2499 	RCAR_GP_PIN(5, 22),
2500 };
2501 static const unsigned int msiof0_rxd_mux[] = {
2502 	MSIOF0_RXD_MARK,
2503 };
2504 /* - MSIOF1 ----------------------------------------------------------------- */
2505 static const unsigned int msiof1_clk_a_pins[] = {
2506 	/* SCK */
2507 	RCAR_GP_PIN(6, 8),
2508 };
2509 static const unsigned int msiof1_clk_a_mux[] = {
2510 	MSIOF1_SCK_A_MARK,
2511 };
2512 static const unsigned int msiof1_sync_a_pins[] = {
2513 	/* SYNC */
2514 	RCAR_GP_PIN(6, 9),
2515 };
2516 static const unsigned int msiof1_sync_a_mux[] = {
2517 	MSIOF1_SYNC_A_MARK,
2518 };
2519 static const unsigned int msiof1_ss1_a_pins[] = {
2520 	/* SS1 */
2521 	RCAR_GP_PIN(6, 5),
2522 };
2523 static const unsigned int msiof1_ss1_a_mux[] = {
2524 	MSIOF1_SS1_A_MARK,
2525 };
2526 static const unsigned int msiof1_ss2_a_pins[] = {
2527 	/* SS2 */
2528 	RCAR_GP_PIN(6, 6),
2529 };
2530 static const unsigned int msiof1_ss2_a_mux[] = {
2531 	MSIOF1_SS2_A_MARK,
2532 };
2533 static const unsigned int msiof1_txd_a_pins[] = {
2534 	/* TXD */
2535 	RCAR_GP_PIN(6, 7),
2536 };
2537 static const unsigned int msiof1_txd_a_mux[] = {
2538 	MSIOF1_TXD_A_MARK,
2539 };
2540 static const unsigned int msiof1_rxd_a_pins[] = {
2541 	/* RXD */
2542 	RCAR_GP_PIN(6, 10),
2543 };
2544 static const unsigned int msiof1_rxd_a_mux[] = {
2545 	MSIOF1_RXD_A_MARK,
2546 };
2547 static const unsigned int msiof1_clk_b_pins[] = {
2548 	/* SCK */
2549 	RCAR_GP_PIN(5, 9),
2550 };
2551 static const unsigned int msiof1_clk_b_mux[] = {
2552 	MSIOF1_SCK_B_MARK,
2553 };
2554 static const unsigned int msiof1_sync_b_pins[] = {
2555 	/* SYNC */
2556 	RCAR_GP_PIN(5, 3),
2557 };
2558 static const unsigned int msiof1_sync_b_mux[] = {
2559 	MSIOF1_SYNC_B_MARK,
2560 };
2561 static const unsigned int msiof1_ss1_b_pins[] = {
2562 	/* SS1 */
2563 	RCAR_GP_PIN(5, 4),
2564 };
2565 static const unsigned int msiof1_ss1_b_mux[] = {
2566 	MSIOF1_SS1_B_MARK,
2567 };
2568 static const unsigned int msiof1_ss2_b_pins[] = {
2569 	/* SS2 */
2570 	RCAR_GP_PIN(5, 0),
2571 };
2572 static const unsigned int msiof1_ss2_b_mux[] = {
2573 	MSIOF1_SS2_B_MARK,
2574 };
2575 static const unsigned int msiof1_txd_b_pins[] = {
2576 	/* TXD */
2577 	RCAR_GP_PIN(5, 8),
2578 };
2579 static const unsigned int msiof1_txd_b_mux[] = {
2580 	MSIOF1_TXD_B_MARK,
2581 };
2582 static const unsigned int msiof1_rxd_b_pins[] = {
2583 	/* RXD */
2584 	RCAR_GP_PIN(5, 7),
2585 };
2586 static const unsigned int msiof1_rxd_b_mux[] = {
2587 	MSIOF1_RXD_B_MARK,
2588 };
2589 static const unsigned int msiof1_clk_c_pins[] = {
2590 	/* SCK */
2591 	RCAR_GP_PIN(6, 17),
2592 };
2593 static const unsigned int msiof1_clk_c_mux[] = {
2594 	MSIOF1_SCK_C_MARK,
2595 };
2596 static const unsigned int msiof1_sync_c_pins[] = {
2597 	/* SYNC */
2598 	RCAR_GP_PIN(6, 18),
2599 };
2600 static const unsigned int msiof1_sync_c_mux[] = {
2601 	MSIOF1_SYNC_C_MARK,
2602 };
2603 static const unsigned int msiof1_ss1_c_pins[] = {
2604 	/* SS1 */
2605 	RCAR_GP_PIN(6, 21),
2606 };
2607 static const unsigned int msiof1_ss1_c_mux[] = {
2608 	MSIOF1_SS1_C_MARK,
2609 };
2610 static const unsigned int msiof1_ss2_c_pins[] = {
2611 	/* SS2 */
2612 	RCAR_GP_PIN(6, 27),
2613 };
2614 static const unsigned int msiof1_ss2_c_mux[] = {
2615 	MSIOF1_SS2_C_MARK,
2616 };
2617 static const unsigned int msiof1_txd_c_pins[] = {
2618 	/* TXD */
2619 	RCAR_GP_PIN(6, 20),
2620 };
2621 static const unsigned int msiof1_txd_c_mux[] = {
2622 	MSIOF1_TXD_C_MARK,
2623 };
2624 static const unsigned int msiof1_rxd_c_pins[] = {
2625 	/* RXD */
2626 	RCAR_GP_PIN(6, 19),
2627 };
2628 static const unsigned int msiof1_rxd_c_mux[] = {
2629 	MSIOF1_RXD_C_MARK,
2630 };
2631 static const unsigned int msiof1_clk_d_pins[] = {
2632 	/* SCK */
2633 	RCAR_GP_PIN(5, 12),
2634 };
2635 static const unsigned int msiof1_clk_d_mux[] = {
2636 	MSIOF1_SCK_D_MARK,
2637 };
2638 static const unsigned int msiof1_sync_d_pins[] = {
2639 	/* SYNC */
2640 	RCAR_GP_PIN(5, 15),
2641 };
2642 static const unsigned int msiof1_sync_d_mux[] = {
2643 	MSIOF1_SYNC_D_MARK,
2644 };
2645 static const unsigned int msiof1_ss1_d_pins[] = {
2646 	/* SS1 */
2647 	RCAR_GP_PIN(5, 16),
2648 };
2649 static const unsigned int msiof1_ss1_d_mux[] = {
2650 	MSIOF1_SS1_D_MARK,
2651 };
2652 static const unsigned int msiof1_ss2_d_pins[] = {
2653 	/* SS2 */
2654 	RCAR_GP_PIN(5, 21),
2655 };
2656 static const unsigned int msiof1_ss2_d_mux[] = {
2657 	MSIOF1_SS2_D_MARK,
2658 };
2659 static const unsigned int msiof1_txd_d_pins[] = {
2660 	/* TXD */
2661 	RCAR_GP_PIN(5, 14),
2662 };
2663 static const unsigned int msiof1_txd_d_mux[] = {
2664 	MSIOF1_TXD_D_MARK,
2665 };
2666 static const unsigned int msiof1_rxd_d_pins[] = {
2667 	/* RXD */
2668 	RCAR_GP_PIN(5, 13),
2669 };
2670 static const unsigned int msiof1_rxd_d_mux[] = {
2671 	MSIOF1_RXD_D_MARK,
2672 };
2673 static const unsigned int msiof1_clk_e_pins[] = {
2674 	/* SCK */
2675 	RCAR_GP_PIN(3, 0),
2676 };
2677 static const unsigned int msiof1_clk_e_mux[] = {
2678 	MSIOF1_SCK_E_MARK,
2679 };
2680 static const unsigned int msiof1_sync_e_pins[] = {
2681 	/* SYNC */
2682 	RCAR_GP_PIN(3, 1),
2683 };
2684 static const unsigned int msiof1_sync_e_mux[] = {
2685 	MSIOF1_SYNC_E_MARK,
2686 };
2687 static const unsigned int msiof1_ss1_e_pins[] = {
2688 	/* SS1 */
2689 	RCAR_GP_PIN(3, 4),
2690 };
2691 static const unsigned int msiof1_ss1_e_mux[] = {
2692 	MSIOF1_SS1_E_MARK,
2693 };
2694 static const unsigned int msiof1_ss2_e_pins[] = {
2695 	/* SS2 */
2696 	RCAR_GP_PIN(3, 5),
2697 };
2698 static const unsigned int msiof1_ss2_e_mux[] = {
2699 	MSIOF1_SS2_E_MARK,
2700 };
2701 static const unsigned int msiof1_txd_e_pins[] = {
2702 	/* TXD */
2703 	RCAR_GP_PIN(3, 3),
2704 };
2705 static const unsigned int msiof1_txd_e_mux[] = {
2706 	MSIOF1_TXD_E_MARK,
2707 };
2708 static const unsigned int msiof1_rxd_e_pins[] = {
2709 	/* RXD */
2710 	RCAR_GP_PIN(3, 2),
2711 };
2712 static const unsigned int msiof1_rxd_e_mux[] = {
2713 	MSIOF1_RXD_E_MARK,
2714 };
2715 static const unsigned int msiof1_clk_f_pins[] = {
2716 	/* SCK */
2717 	RCAR_GP_PIN(5, 23),
2718 };
2719 static const unsigned int msiof1_clk_f_mux[] = {
2720 	MSIOF1_SCK_F_MARK,
2721 };
2722 static const unsigned int msiof1_sync_f_pins[] = {
2723 	/* SYNC */
2724 	RCAR_GP_PIN(5, 24),
2725 };
2726 static const unsigned int msiof1_sync_f_mux[] = {
2727 	MSIOF1_SYNC_F_MARK,
2728 };
2729 static const unsigned int msiof1_ss1_f_pins[] = {
2730 	/* SS1 */
2731 	RCAR_GP_PIN(6, 1),
2732 };
2733 static const unsigned int msiof1_ss1_f_mux[] = {
2734 	MSIOF1_SS1_F_MARK,
2735 };
2736 static const unsigned int msiof1_ss2_f_pins[] = {
2737 	/* SS2 */
2738 	RCAR_GP_PIN(6, 2),
2739 };
2740 static const unsigned int msiof1_ss2_f_mux[] = {
2741 	MSIOF1_SS2_F_MARK,
2742 };
2743 static const unsigned int msiof1_txd_f_pins[] = {
2744 	/* TXD */
2745 	RCAR_GP_PIN(6, 0),
2746 };
2747 static const unsigned int msiof1_txd_f_mux[] = {
2748 	MSIOF1_TXD_F_MARK,
2749 };
2750 static const unsigned int msiof1_rxd_f_pins[] = {
2751 	/* RXD */
2752 	RCAR_GP_PIN(5, 25),
2753 };
2754 static const unsigned int msiof1_rxd_f_mux[] = {
2755 	MSIOF1_RXD_F_MARK,
2756 };
2757 static const unsigned int msiof1_clk_g_pins[] = {
2758 	/* SCK */
2759 	RCAR_GP_PIN(3, 6),
2760 };
2761 static const unsigned int msiof1_clk_g_mux[] = {
2762 	MSIOF1_SCK_G_MARK,
2763 };
2764 static const unsigned int msiof1_sync_g_pins[] = {
2765 	/* SYNC */
2766 	RCAR_GP_PIN(3, 7),
2767 };
2768 static const unsigned int msiof1_sync_g_mux[] = {
2769 	MSIOF1_SYNC_G_MARK,
2770 };
2771 static const unsigned int msiof1_ss1_g_pins[] = {
2772 	/* SS1 */
2773 	RCAR_GP_PIN(3, 10),
2774 };
2775 static const unsigned int msiof1_ss1_g_mux[] = {
2776 	MSIOF1_SS1_G_MARK,
2777 };
2778 static const unsigned int msiof1_ss2_g_pins[] = {
2779 	/* SS2 */
2780 	RCAR_GP_PIN(3, 11),
2781 };
2782 static const unsigned int msiof1_ss2_g_mux[] = {
2783 	MSIOF1_SS2_G_MARK,
2784 };
2785 static const unsigned int msiof1_txd_g_pins[] = {
2786 	/* TXD */
2787 	RCAR_GP_PIN(3, 9),
2788 };
2789 static const unsigned int msiof1_txd_g_mux[] = {
2790 	MSIOF1_TXD_G_MARK,
2791 };
2792 static const unsigned int msiof1_rxd_g_pins[] = {
2793 	/* RXD */
2794 	RCAR_GP_PIN(3, 8),
2795 };
2796 static const unsigned int msiof1_rxd_g_mux[] = {
2797 	MSIOF1_RXD_G_MARK,
2798 };
2799 /* - MSIOF2 ----------------------------------------------------------------- */
2800 static const unsigned int msiof2_clk_a_pins[] = {
2801 	/* SCK */
2802 	RCAR_GP_PIN(1, 9),
2803 };
2804 static const unsigned int msiof2_clk_a_mux[] = {
2805 	MSIOF2_SCK_A_MARK,
2806 };
2807 static const unsigned int msiof2_sync_a_pins[] = {
2808 	/* SYNC */
2809 	RCAR_GP_PIN(1, 8),
2810 };
2811 static const unsigned int msiof2_sync_a_mux[] = {
2812 	MSIOF2_SYNC_A_MARK,
2813 };
2814 static const unsigned int msiof2_ss1_a_pins[] = {
2815 	/* SS1 */
2816 	RCAR_GP_PIN(1, 6),
2817 };
2818 static const unsigned int msiof2_ss1_a_mux[] = {
2819 	MSIOF2_SS1_A_MARK,
2820 };
2821 static const unsigned int msiof2_ss2_a_pins[] = {
2822 	/* SS2 */
2823 	RCAR_GP_PIN(1, 7),
2824 };
2825 static const unsigned int msiof2_ss2_a_mux[] = {
2826 	MSIOF2_SS2_A_MARK,
2827 };
2828 static const unsigned int msiof2_txd_a_pins[] = {
2829 	/* TXD */
2830 	RCAR_GP_PIN(1, 11),
2831 };
2832 static const unsigned int msiof2_txd_a_mux[] = {
2833 	MSIOF2_TXD_A_MARK,
2834 };
2835 static const unsigned int msiof2_rxd_a_pins[] = {
2836 	/* RXD */
2837 	RCAR_GP_PIN(1, 10),
2838 };
2839 static const unsigned int msiof2_rxd_a_mux[] = {
2840 	MSIOF2_RXD_A_MARK,
2841 };
2842 static const unsigned int msiof2_clk_b_pins[] = {
2843 	/* SCK */
2844 	RCAR_GP_PIN(0, 4),
2845 };
2846 static const unsigned int msiof2_clk_b_mux[] = {
2847 	MSIOF2_SCK_B_MARK,
2848 };
2849 static const unsigned int msiof2_sync_b_pins[] = {
2850 	/* SYNC */
2851 	RCAR_GP_PIN(0, 5),
2852 };
2853 static const unsigned int msiof2_sync_b_mux[] = {
2854 	MSIOF2_SYNC_B_MARK,
2855 };
2856 static const unsigned int msiof2_ss1_b_pins[] = {
2857 	/* SS1 */
2858 	RCAR_GP_PIN(0, 0),
2859 };
2860 static const unsigned int msiof2_ss1_b_mux[] = {
2861 	MSIOF2_SS1_B_MARK,
2862 };
2863 static const unsigned int msiof2_ss2_b_pins[] = {
2864 	/* SS2 */
2865 	RCAR_GP_PIN(0, 1),
2866 };
2867 static const unsigned int msiof2_ss2_b_mux[] = {
2868 	MSIOF2_SS2_B_MARK,
2869 };
2870 static const unsigned int msiof2_txd_b_pins[] = {
2871 	/* TXD */
2872 	RCAR_GP_PIN(0, 7),
2873 };
2874 static const unsigned int msiof2_txd_b_mux[] = {
2875 	MSIOF2_TXD_B_MARK,
2876 };
2877 static const unsigned int msiof2_rxd_b_pins[] = {
2878 	/* RXD */
2879 	RCAR_GP_PIN(0, 6),
2880 };
2881 static const unsigned int msiof2_rxd_b_mux[] = {
2882 	MSIOF2_RXD_B_MARK,
2883 };
2884 static const unsigned int msiof2_clk_c_pins[] = {
2885 	/* SCK */
2886 	RCAR_GP_PIN(2, 12),
2887 };
2888 static const unsigned int msiof2_clk_c_mux[] = {
2889 	MSIOF2_SCK_C_MARK,
2890 };
2891 static const unsigned int msiof2_sync_c_pins[] = {
2892 	/* SYNC */
2893 	RCAR_GP_PIN(2, 11),
2894 };
2895 static const unsigned int msiof2_sync_c_mux[] = {
2896 	MSIOF2_SYNC_C_MARK,
2897 };
2898 static const unsigned int msiof2_ss1_c_pins[] = {
2899 	/* SS1 */
2900 	RCAR_GP_PIN(2, 10),
2901 };
2902 static const unsigned int msiof2_ss1_c_mux[] = {
2903 	MSIOF2_SS1_C_MARK,
2904 };
2905 static const unsigned int msiof2_ss2_c_pins[] = {
2906 	/* SS2 */
2907 	RCAR_GP_PIN(2, 9),
2908 };
2909 static const unsigned int msiof2_ss2_c_mux[] = {
2910 	MSIOF2_SS2_C_MARK,
2911 };
2912 static const unsigned int msiof2_txd_c_pins[] = {
2913 	/* TXD */
2914 	RCAR_GP_PIN(2, 14),
2915 };
2916 static const unsigned int msiof2_txd_c_mux[] = {
2917 	MSIOF2_TXD_C_MARK,
2918 };
2919 static const unsigned int msiof2_rxd_c_pins[] = {
2920 	/* RXD */
2921 	RCAR_GP_PIN(2, 13),
2922 };
2923 static const unsigned int msiof2_rxd_c_mux[] = {
2924 	MSIOF2_RXD_C_MARK,
2925 };
2926 static const unsigned int msiof2_clk_d_pins[] = {
2927 	/* SCK */
2928 	RCAR_GP_PIN(0, 8),
2929 };
2930 static const unsigned int msiof2_clk_d_mux[] = {
2931 	MSIOF2_SCK_D_MARK,
2932 };
2933 static const unsigned int msiof2_sync_d_pins[] = {
2934 	/* SYNC */
2935 	RCAR_GP_PIN(0, 9),
2936 };
2937 static const unsigned int msiof2_sync_d_mux[] = {
2938 	MSIOF2_SYNC_D_MARK,
2939 };
2940 static const unsigned int msiof2_ss1_d_pins[] = {
2941 	/* SS1 */
2942 	RCAR_GP_PIN(0, 12),
2943 };
2944 static const unsigned int msiof2_ss1_d_mux[] = {
2945 	MSIOF2_SS1_D_MARK,
2946 };
2947 static const unsigned int msiof2_ss2_d_pins[] = {
2948 	/* SS2 */
2949 	RCAR_GP_PIN(0, 13),
2950 };
2951 static const unsigned int msiof2_ss2_d_mux[] = {
2952 	MSIOF2_SS2_D_MARK,
2953 };
2954 static const unsigned int msiof2_txd_d_pins[] = {
2955 	/* TXD */
2956 	RCAR_GP_PIN(0, 11),
2957 };
2958 static const unsigned int msiof2_txd_d_mux[] = {
2959 	MSIOF2_TXD_D_MARK,
2960 };
2961 static const unsigned int msiof2_rxd_d_pins[] = {
2962 	/* RXD */
2963 	RCAR_GP_PIN(0, 10),
2964 };
2965 static const unsigned int msiof2_rxd_d_mux[] = {
2966 	MSIOF2_RXD_D_MARK,
2967 };
2968 /* - MSIOF3 ----------------------------------------------------------------- */
2969 static const unsigned int msiof3_clk_a_pins[] = {
2970 	/* SCK */
2971 	RCAR_GP_PIN(0, 0),
2972 };
2973 static const unsigned int msiof3_clk_a_mux[] = {
2974 	MSIOF3_SCK_A_MARK,
2975 };
2976 static const unsigned int msiof3_sync_a_pins[] = {
2977 	/* SYNC */
2978 	RCAR_GP_PIN(0, 1),
2979 };
2980 static const unsigned int msiof3_sync_a_mux[] = {
2981 	MSIOF3_SYNC_A_MARK,
2982 };
2983 static const unsigned int msiof3_ss1_a_pins[] = {
2984 	/* SS1 */
2985 	RCAR_GP_PIN(0, 14),
2986 };
2987 static const unsigned int msiof3_ss1_a_mux[] = {
2988 	MSIOF3_SS1_A_MARK,
2989 };
2990 static const unsigned int msiof3_ss2_a_pins[] = {
2991 	/* SS2 */
2992 	RCAR_GP_PIN(0, 15),
2993 };
2994 static const unsigned int msiof3_ss2_a_mux[] = {
2995 	MSIOF3_SS2_A_MARK,
2996 };
2997 static const unsigned int msiof3_txd_a_pins[] = {
2998 	/* TXD */
2999 	RCAR_GP_PIN(0, 3),
3000 };
3001 static const unsigned int msiof3_txd_a_mux[] = {
3002 	MSIOF3_TXD_A_MARK,
3003 };
3004 static const unsigned int msiof3_rxd_a_pins[] = {
3005 	/* RXD */
3006 	RCAR_GP_PIN(0, 2),
3007 };
3008 static const unsigned int msiof3_rxd_a_mux[] = {
3009 	MSIOF3_RXD_A_MARK,
3010 };
3011 static const unsigned int msiof3_clk_b_pins[] = {
3012 	/* SCK */
3013 	RCAR_GP_PIN(1, 2),
3014 };
3015 static const unsigned int msiof3_clk_b_mux[] = {
3016 	MSIOF3_SCK_B_MARK,
3017 };
3018 static const unsigned int msiof3_sync_b_pins[] = {
3019 	/* SYNC */
3020 	RCAR_GP_PIN(1, 0),
3021 };
3022 static const unsigned int msiof3_sync_b_mux[] = {
3023 	MSIOF3_SYNC_B_MARK,
3024 };
3025 static const unsigned int msiof3_ss1_b_pins[] = {
3026 	/* SS1 */
3027 	RCAR_GP_PIN(1, 4),
3028 };
3029 static const unsigned int msiof3_ss1_b_mux[] = {
3030 	MSIOF3_SS1_B_MARK,
3031 };
3032 static const unsigned int msiof3_ss2_b_pins[] = {
3033 	/* SS2 */
3034 	RCAR_GP_PIN(1, 5),
3035 };
3036 static const unsigned int msiof3_ss2_b_mux[] = {
3037 	MSIOF3_SS2_B_MARK,
3038 };
3039 static const unsigned int msiof3_txd_b_pins[] = {
3040 	/* TXD */
3041 	RCAR_GP_PIN(1, 1),
3042 };
3043 static const unsigned int msiof3_txd_b_mux[] = {
3044 	MSIOF3_TXD_B_MARK,
3045 };
3046 static const unsigned int msiof3_rxd_b_pins[] = {
3047 	/* RXD */
3048 	RCAR_GP_PIN(1, 3),
3049 };
3050 static const unsigned int msiof3_rxd_b_mux[] = {
3051 	MSIOF3_RXD_B_MARK,
3052 };
3053 static const unsigned int msiof3_clk_c_pins[] = {
3054 	/* SCK */
3055 	RCAR_GP_PIN(1, 12),
3056 };
3057 static const unsigned int msiof3_clk_c_mux[] = {
3058 	MSIOF3_SCK_C_MARK,
3059 };
3060 static const unsigned int msiof3_sync_c_pins[] = {
3061 	/* SYNC */
3062 	RCAR_GP_PIN(1, 13),
3063 };
3064 static const unsigned int msiof3_sync_c_mux[] = {
3065 	MSIOF3_SYNC_C_MARK,
3066 };
3067 static const unsigned int msiof3_txd_c_pins[] = {
3068 	/* TXD */
3069 	RCAR_GP_PIN(1, 15),
3070 };
3071 static const unsigned int msiof3_txd_c_mux[] = {
3072 	MSIOF3_TXD_C_MARK,
3073 };
3074 static const unsigned int msiof3_rxd_c_pins[] = {
3075 	/* RXD */
3076 	RCAR_GP_PIN(1, 14),
3077 };
3078 static const unsigned int msiof3_rxd_c_mux[] = {
3079 	MSIOF3_RXD_C_MARK,
3080 };
3081 static const unsigned int msiof3_clk_d_pins[] = {
3082 	/* SCK */
3083 	RCAR_GP_PIN(1, 22),
3084 };
3085 static const unsigned int msiof3_clk_d_mux[] = {
3086 	MSIOF3_SCK_D_MARK,
3087 };
3088 static const unsigned int msiof3_sync_d_pins[] = {
3089 	/* SYNC */
3090 	RCAR_GP_PIN(1, 23),
3091 };
3092 static const unsigned int msiof3_sync_d_mux[] = {
3093 	MSIOF3_SYNC_D_MARK,
3094 };
3095 static const unsigned int msiof3_ss1_d_pins[] = {
3096 	/* SS1 */
3097 	RCAR_GP_PIN(1, 26),
3098 };
3099 static const unsigned int msiof3_ss1_d_mux[] = {
3100 	MSIOF3_SS1_D_MARK,
3101 };
3102 static const unsigned int msiof3_txd_d_pins[] = {
3103 	/* TXD */
3104 	RCAR_GP_PIN(1, 25),
3105 };
3106 static const unsigned int msiof3_txd_d_mux[] = {
3107 	MSIOF3_TXD_D_MARK,
3108 };
3109 static const unsigned int msiof3_rxd_d_pins[] = {
3110 	/* RXD */
3111 	RCAR_GP_PIN(1, 24),
3112 };
3113 static const unsigned int msiof3_rxd_d_mux[] = {
3114 	MSIOF3_RXD_D_MARK,
3115 };
3116 
3117 static const unsigned int msiof3_clk_e_pins[] = {
3118 	/* SCK */
3119 	RCAR_GP_PIN(2, 3),
3120 };
3121 static const unsigned int msiof3_clk_e_mux[] = {
3122 	MSIOF3_SCK_E_MARK,
3123 };
3124 static const unsigned int msiof3_sync_e_pins[] = {
3125 	/* SYNC */
3126 	RCAR_GP_PIN(2, 2),
3127 };
3128 static const unsigned int msiof3_sync_e_mux[] = {
3129 	MSIOF3_SYNC_E_MARK,
3130 };
3131 static const unsigned int msiof3_ss1_e_pins[] = {
3132 	/* SS1 */
3133 	RCAR_GP_PIN(2, 1),
3134 };
3135 static const unsigned int msiof3_ss1_e_mux[] = {
3136 	MSIOF3_SS1_E_MARK,
3137 };
3138 static const unsigned int msiof3_ss2_e_pins[] = {
3139 	/* SS2 */
3140 	RCAR_GP_PIN(2, 0),
3141 };
3142 static const unsigned int msiof3_ss2_e_mux[] = {
3143 	MSIOF3_SS2_E_MARK,
3144 };
3145 static const unsigned int msiof3_txd_e_pins[] = {
3146 	/* TXD */
3147 	RCAR_GP_PIN(2, 5),
3148 };
3149 static const unsigned int msiof3_txd_e_mux[] = {
3150 	MSIOF3_TXD_E_MARK,
3151 };
3152 static const unsigned int msiof3_rxd_e_pins[] = {
3153 	/* RXD */
3154 	RCAR_GP_PIN(2, 4),
3155 };
3156 static const unsigned int msiof3_rxd_e_mux[] = {
3157 	MSIOF3_RXD_E_MARK,
3158 };
3159 
3160 /* - PWM0 --------------------------------------------------------------------*/
3161 static const unsigned int pwm0_pins[] = {
3162 	/* PWM */
3163 	RCAR_GP_PIN(2, 6),
3164 };
3165 static const unsigned int pwm0_mux[] = {
3166 	PWM0_MARK,
3167 };
3168 /* - PWM1 --------------------------------------------------------------------*/
3169 static const unsigned int pwm1_a_pins[] = {
3170 	/* PWM */
3171 	RCAR_GP_PIN(2, 7),
3172 };
3173 static const unsigned int pwm1_a_mux[] = {
3174 	PWM1_A_MARK,
3175 };
3176 static const unsigned int pwm1_b_pins[] = {
3177 	/* PWM */
3178 	RCAR_GP_PIN(1, 8),
3179 };
3180 static const unsigned int pwm1_b_mux[] = {
3181 	PWM1_B_MARK,
3182 };
3183 /* - PWM2 --------------------------------------------------------------------*/
3184 static const unsigned int pwm2_a_pins[] = {
3185 	/* PWM */
3186 	RCAR_GP_PIN(2, 8),
3187 };
3188 static const unsigned int pwm2_a_mux[] = {
3189 	PWM2_A_MARK,
3190 };
3191 static const unsigned int pwm2_b_pins[] = {
3192 	/* PWM */
3193 	RCAR_GP_PIN(1, 11),
3194 };
3195 static const unsigned int pwm2_b_mux[] = {
3196 	PWM2_B_MARK,
3197 };
3198 /* - PWM3 --------------------------------------------------------------------*/
3199 static const unsigned int pwm3_a_pins[] = {
3200 	/* PWM */
3201 	RCAR_GP_PIN(1, 0),
3202 };
3203 static const unsigned int pwm3_a_mux[] = {
3204 	PWM3_A_MARK,
3205 };
3206 static const unsigned int pwm3_b_pins[] = {
3207 	/* PWM */
3208 	RCAR_GP_PIN(2, 2),
3209 };
3210 static const unsigned int pwm3_b_mux[] = {
3211 	PWM3_B_MARK,
3212 };
3213 /* - PWM4 --------------------------------------------------------------------*/
3214 static const unsigned int pwm4_a_pins[] = {
3215 	/* PWM */
3216 	RCAR_GP_PIN(1, 1),
3217 };
3218 static const unsigned int pwm4_a_mux[] = {
3219 	PWM4_A_MARK,
3220 };
3221 static const unsigned int pwm4_b_pins[] = {
3222 	/* PWM */
3223 	RCAR_GP_PIN(2, 3),
3224 };
3225 static const unsigned int pwm4_b_mux[] = {
3226 	PWM4_B_MARK,
3227 };
3228 /* - PWM5 --------------------------------------------------------------------*/
3229 static const unsigned int pwm5_a_pins[] = {
3230 	/* PWM */
3231 	RCAR_GP_PIN(1, 2),
3232 };
3233 static const unsigned int pwm5_a_mux[] = {
3234 	PWM5_A_MARK,
3235 };
3236 static const unsigned int pwm5_b_pins[] = {
3237 	/* PWM */
3238 	RCAR_GP_PIN(2, 4),
3239 };
3240 static const unsigned int pwm5_b_mux[] = {
3241 	PWM5_B_MARK,
3242 };
3243 /* - PWM6 --------------------------------------------------------------------*/
3244 static const unsigned int pwm6_a_pins[] = {
3245 	/* PWM */
3246 	RCAR_GP_PIN(1, 3),
3247 };
3248 static const unsigned int pwm6_a_mux[] = {
3249 	PWM6_A_MARK,
3250 };
3251 static const unsigned int pwm6_b_pins[] = {
3252 	/* PWM */
3253 	RCAR_GP_PIN(2, 5),
3254 };
3255 static const unsigned int pwm6_b_mux[] = {
3256 	PWM6_B_MARK,
3257 };
3258 
3259 /* - QSPI0 ------------------------------------------------------------------ */
3260 static const unsigned int qspi0_ctrl_pins[] = {
3261 	/* QSPI0_SPCLK, QSPI0_SSL */
3262 	PIN_QSPI0_SPCLK, PIN_QSPI0_SSL,
3263 };
3264 static const unsigned int qspi0_ctrl_mux[] = {
3265 	QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
3266 };
3267 static const unsigned int qspi0_data2_pins[] = {
3268 	/* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
3269 	PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,
3270 };
3271 static const unsigned int qspi0_data2_mux[] = {
3272 	QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
3273 };
3274 static const unsigned int qspi0_data4_pins[] = {
3275 	/* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
3276 	PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,
3277 	/* QSPI0_IO2, QSPI0_IO3 */
3278 	PIN_QSPI0_IO2, PIN_QSPI0_IO3,
3279 };
3280 static const unsigned int qspi0_data4_mux[] = {
3281 	QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
3282 	QSPI0_IO2_MARK, QSPI0_IO3_MARK,
3283 };
3284 /* - QSPI1 ------------------------------------------------------------------ */
3285 static const unsigned int qspi1_ctrl_pins[] = {
3286 	/* QSPI1_SPCLK, QSPI1_SSL */
3287 	PIN_QSPI1_SPCLK, PIN_QSPI1_SSL,
3288 };
3289 static const unsigned int qspi1_ctrl_mux[] = {
3290 	QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
3291 };
3292 static const unsigned int qspi1_data2_pins[] = {
3293 	/* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
3294 	PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,
3295 };
3296 static const unsigned int qspi1_data2_mux[] = {
3297 	QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
3298 };
3299 static const unsigned int qspi1_data4_pins[] = {
3300 	/* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
3301 	PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,
3302 	/* QSPI1_IO2, QSPI1_IO3 */
3303 	PIN_QSPI1_IO2, PIN_QSPI1_IO3,
3304 };
3305 static const unsigned int qspi1_data4_mux[] = {
3306 	QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
3307 	QSPI1_IO2_MARK, QSPI1_IO3_MARK,
3308 };
3309 
3310 /* - SCIF0 ------------------------------------------------------------------ */
3311 static const unsigned int scif0_data_pins[] = {
3312 	/* RX, TX */
3313 	RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
3314 };
3315 static const unsigned int scif0_data_mux[] = {
3316 	RX0_MARK, TX0_MARK,
3317 };
3318 static const unsigned int scif0_clk_pins[] = {
3319 	/* SCK */
3320 	RCAR_GP_PIN(5, 0),
3321 };
3322 static const unsigned int scif0_clk_mux[] = {
3323 	SCK0_MARK,
3324 };
3325 static const unsigned int scif0_ctrl_pins[] = {
3326 	/* RTS, CTS */
3327 	RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
3328 };
3329 static const unsigned int scif0_ctrl_mux[] = {
3330 	RTS0_N_MARK, CTS0_N_MARK,
3331 };
3332 /* - SCIF1 ------------------------------------------------------------------ */
3333 static const unsigned int scif1_data_a_pins[] = {
3334 	/* RX, TX */
3335 	RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
3336 };
3337 static const unsigned int scif1_data_a_mux[] = {
3338 	RX1_A_MARK, TX1_A_MARK,
3339 };
3340 static const unsigned int scif1_clk_pins[] = {
3341 	/* SCK */
3342 	RCAR_GP_PIN(6, 21),
3343 };
3344 static const unsigned int scif1_clk_mux[] = {
3345 	SCK1_MARK,
3346 };
3347 static const unsigned int scif1_ctrl_pins[] = {
3348 	/* RTS, CTS */
3349 	RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
3350 };
3351 static const unsigned int scif1_ctrl_mux[] = {
3352 	RTS1_N_MARK, CTS1_N_MARK,
3353 };
3354 
3355 static const unsigned int scif1_data_b_pins[] = {
3356 	/* RX, TX */
3357 	RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
3358 };
3359 static const unsigned int scif1_data_b_mux[] = {
3360 	RX1_B_MARK, TX1_B_MARK,
3361 };
3362 /* - SCIF2 ------------------------------------------------------------------ */
3363 static const unsigned int scif2_data_a_pins[] = {
3364 	/* RX, TX */
3365 	RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
3366 };
3367 static const unsigned int scif2_data_a_mux[] = {
3368 	RX2_A_MARK, TX2_A_MARK,
3369 };
3370 static const unsigned int scif2_clk_pins[] = {
3371 	/* SCK */
3372 	RCAR_GP_PIN(5, 9),
3373 };
3374 static const unsigned int scif2_clk_mux[] = {
3375 	SCK2_MARK,
3376 };
3377 static const unsigned int scif2_data_b_pins[] = {
3378 	/* RX, TX */
3379 	RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3380 };
3381 static const unsigned int scif2_data_b_mux[] = {
3382 	RX2_B_MARK, TX2_B_MARK,
3383 };
3384 /* - SCIF3 ------------------------------------------------------------------ */
3385 static const unsigned int scif3_data_a_pins[] = {
3386 	/* RX, TX */
3387 	RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
3388 };
3389 static const unsigned int scif3_data_a_mux[] = {
3390 	RX3_A_MARK, TX3_A_MARK,
3391 };
3392 static const unsigned int scif3_clk_pins[] = {
3393 	/* SCK */
3394 	RCAR_GP_PIN(1, 22),
3395 };
3396 static const unsigned int scif3_clk_mux[] = {
3397 	SCK3_MARK,
3398 };
3399 static const unsigned int scif3_ctrl_pins[] = {
3400 	/* RTS, CTS */
3401 	RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
3402 };
3403 static const unsigned int scif3_ctrl_mux[] = {
3404 	RTS3_N_MARK, CTS3_N_MARK,
3405 };
3406 static const unsigned int scif3_data_b_pins[] = {
3407 	/* RX, TX */
3408 	RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
3409 };
3410 static const unsigned int scif3_data_b_mux[] = {
3411 	RX3_B_MARK, TX3_B_MARK,
3412 };
3413 /* - SCIF4 ------------------------------------------------------------------ */
3414 static const unsigned int scif4_data_a_pins[] = {
3415 	/* RX, TX */
3416 	RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
3417 };
3418 static const unsigned int scif4_data_a_mux[] = {
3419 	RX4_A_MARK, TX4_A_MARK,
3420 };
3421 static const unsigned int scif4_clk_a_pins[] = {
3422 	/* SCK */
3423 	RCAR_GP_PIN(2, 10),
3424 };
3425 static const unsigned int scif4_clk_a_mux[] = {
3426 	SCK4_A_MARK,
3427 };
3428 static const unsigned int scif4_ctrl_a_pins[] = {
3429 	/* RTS, CTS */
3430 	RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
3431 };
3432 static const unsigned int scif4_ctrl_a_mux[] = {
3433 	RTS4_N_A_MARK, CTS4_N_A_MARK,
3434 };
3435 static const unsigned int scif4_data_b_pins[] = {
3436 	/* RX, TX */
3437 	RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3438 };
3439 static const unsigned int scif4_data_b_mux[] = {
3440 	RX4_B_MARK, TX4_B_MARK,
3441 };
3442 static const unsigned int scif4_clk_b_pins[] = {
3443 	/* SCK */
3444 	RCAR_GP_PIN(1, 5),
3445 };
3446 static const unsigned int scif4_clk_b_mux[] = {
3447 	SCK4_B_MARK,
3448 };
3449 static const unsigned int scif4_ctrl_b_pins[] = {
3450 	/* RTS, CTS */
3451 	RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
3452 };
3453 static const unsigned int scif4_ctrl_b_mux[] = {
3454 	RTS4_N_B_MARK, CTS4_N_B_MARK,
3455 };
3456 static const unsigned int scif4_data_c_pins[] = {
3457 	/* RX, TX */
3458 	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3459 };
3460 static const unsigned int scif4_data_c_mux[] = {
3461 	RX4_C_MARK, TX4_C_MARK,
3462 };
3463 static const unsigned int scif4_clk_c_pins[] = {
3464 	/* SCK */
3465 	RCAR_GP_PIN(0, 8),
3466 };
3467 static const unsigned int scif4_clk_c_mux[] = {
3468 	SCK4_C_MARK,
3469 };
3470 static const unsigned int scif4_ctrl_c_pins[] = {
3471 	/* RTS, CTS */
3472 	RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
3473 };
3474 static const unsigned int scif4_ctrl_c_mux[] = {
3475 	RTS4_N_C_MARK, CTS4_N_C_MARK,
3476 };
3477 /* - SCIF5 ------------------------------------------------------------------ */
3478 static const unsigned int scif5_data_a_pins[] = {
3479 	/* RX, TX */
3480 	RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3481 };
3482 static const unsigned int scif5_data_a_mux[] = {
3483 	RX5_A_MARK, TX5_A_MARK,
3484 };
3485 static const unsigned int scif5_clk_a_pins[] = {
3486 	/* SCK */
3487 	RCAR_GP_PIN(6, 21),
3488 };
3489 static const unsigned int scif5_clk_a_mux[] = {
3490 	SCK5_A_MARK,
3491 };
3492 
3493 static const unsigned int scif5_data_b_pins[] = {
3494 	/* RX, TX */
3495 	RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18),
3496 };
3497 static const unsigned int scif5_data_b_mux[] = {
3498 	RX5_B_MARK, TX5_B_MARK,
3499 };
3500 static const unsigned int scif5_clk_b_pins[] = {
3501 	/* SCK */
3502 	RCAR_GP_PIN(5, 0),
3503 };
3504 static const unsigned int scif5_clk_b_mux[] = {
3505 	SCK5_B_MARK,
3506 };
3507 
3508 /* - SCIF Clock ------------------------------------------------------------- */
3509 static const unsigned int scif_clk_a_pins[] = {
3510 	/* SCIF_CLK */
3511 	RCAR_GP_PIN(6, 23),
3512 };
3513 static const unsigned int scif_clk_a_mux[] = {
3514 	SCIF_CLK_A_MARK,
3515 };
3516 static const unsigned int scif_clk_b_pins[] = {
3517 	/* SCIF_CLK */
3518 	RCAR_GP_PIN(5, 9),
3519 };
3520 static const unsigned int scif_clk_b_mux[] = {
3521 	SCIF_CLK_B_MARK,
3522 };
3523 
3524 /* - SDHI0 ------------------------------------------------------------------ */
3525 static const unsigned int sdhi0_data1_pins[] = {
3526 	/* D0 */
3527 	RCAR_GP_PIN(3, 2),
3528 };
3529 static const unsigned int sdhi0_data1_mux[] = {
3530 	SD0_DAT0_MARK,
3531 };
3532 static const unsigned int sdhi0_data4_pins[] = {
3533 	/* D[0:3] */
3534 	RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3535 	RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3536 };
3537 static const unsigned int sdhi0_data4_mux[] = {
3538 	SD0_DAT0_MARK, SD0_DAT1_MARK,
3539 	SD0_DAT2_MARK, SD0_DAT3_MARK,
3540 };
3541 static const unsigned int sdhi0_ctrl_pins[] = {
3542 	/* CLK, CMD */
3543 	RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3544 };
3545 static const unsigned int sdhi0_ctrl_mux[] = {
3546 	SD0_CLK_MARK, SD0_CMD_MARK,
3547 };
3548 static const unsigned int sdhi0_cd_pins[] = {
3549 	/* CD */
3550 	RCAR_GP_PIN(3, 12),
3551 };
3552 static const unsigned int sdhi0_cd_mux[] = {
3553 	SD0_CD_MARK,
3554 };
3555 static const unsigned int sdhi0_wp_pins[] = {
3556 	/* WP */
3557 	RCAR_GP_PIN(3, 13),
3558 };
3559 static const unsigned int sdhi0_wp_mux[] = {
3560 	SD0_WP_MARK,
3561 };
3562 /* - SDHI1 ------------------------------------------------------------------ */
3563 static const unsigned int sdhi1_data1_pins[] = {
3564 	/* D0 */
3565 	RCAR_GP_PIN(3, 8),
3566 };
3567 static const unsigned int sdhi1_data1_mux[] = {
3568 	SD1_DAT0_MARK,
3569 };
3570 static const unsigned int sdhi1_data4_pins[] = {
3571 	/* D[0:3] */
3572 	RCAR_GP_PIN(3, 8),  RCAR_GP_PIN(3, 9),
3573 	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3574 };
3575 static const unsigned int sdhi1_data4_mux[] = {
3576 	SD1_DAT0_MARK, SD1_DAT1_MARK,
3577 	SD1_DAT2_MARK, SD1_DAT3_MARK,
3578 };
3579 static const unsigned int sdhi1_ctrl_pins[] = {
3580 	/* CLK, CMD */
3581 	RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
3582 };
3583 static const unsigned int sdhi1_ctrl_mux[] = {
3584 	SD1_CLK_MARK, SD1_CMD_MARK,
3585 };
3586 static const unsigned int sdhi1_cd_pins[] = {
3587 	/* CD */
3588 	RCAR_GP_PIN(3, 14),
3589 };
3590 static const unsigned int sdhi1_cd_mux[] = {
3591 	SD1_CD_MARK,
3592 };
3593 static const unsigned int sdhi1_wp_pins[] = {
3594 	/* WP */
3595 	RCAR_GP_PIN(3, 15),
3596 };
3597 static const unsigned int sdhi1_wp_mux[] = {
3598 	SD1_WP_MARK,
3599 };
3600 /* - SDHI2 ------------------------------------------------------------------ */
3601 static const unsigned int sdhi2_data1_pins[] = {
3602 	/* D0 */
3603 	RCAR_GP_PIN(4, 2),
3604 };
3605 static const unsigned int sdhi2_data1_mux[] = {
3606 	SD2_DAT0_MARK,
3607 };
3608 static const unsigned int sdhi2_data4_pins[] = {
3609 	/* D[0:3] */
3610 	RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3611 	RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3612 };
3613 static const unsigned int sdhi2_data4_mux[] = {
3614 	SD2_DAT0_MARK, SD2_DAT1_MARK,
3615 	SD2_DAT2_MARK, SD2_DAT3_MARK,
3616 };
3617 static const unsigned int sdhi2_data8_pins[] = {
3618 	/* D[0:7] */
3619 	RCAR_GP_PIN(4, 2),  RCAR_GP_PIN(4, 3),
3620 	RCAR_GP_PIN(4, 4),  RCAR_GP_PIN(4, 5),
3621 	RCAR_GP_PIN(3, 8),  RCAR_GP_PIN(3, 9),
3622 	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3623 };
3624 static const unsigned int sdhi2_data8_mux[] = {
3625 	SD2_DAT0_MARK, SD2_DAT1_MARK,
3626 	SD2_DAT2_MARK, SD2_DAT3_MARK,
3627 	SD2_DAT4_MARK, SD2_DAT5_MARK,
3628 	SD2_DAT6_MARK, SD2_DAT7_MARK,
3629 };
3630 static const unsigned int sdhi2_ctrl_pins[] = {
3631 	/* CLK, CMD */
3632 	RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
3633 };
3634 static const unsigned int sdhi2_ctrl_mux[] = {
3635 	SD2_CLK_MARK, SD2_CMD_MARK,
3636 };
3637 static const unsigned int sdhi2_cd_a_pins[] = {
3638 	/* CD */
3639 	RCAR_GP_PIN(4, 13),
3640 };
3641 static const unsigned int sdhi2_cd_a_mux[] = {
3642 	SD2_CD_A_MARK,
3643 };
3644 static const unsigned int sdhi2_cd_b_pins[] = {
3645 	/* CD */
3646 	RCAR_GP_PIN(5, 10),
3647 };
3648 static const unsigned int sdhi2_cd_b_mux[] = {
3649 	SD2_CD_B_MARK,
3650 };
3651 static const unsigned int sdhi2_wp_a_pins[] = {
3652 	/* WP */
3653 	RCAR_GP_PIN(4, 14),
3654 };
3655 static const unsigned int sdhi2_wp_a_mux[] = {
3656 	SD2_WP_A_MARK,
3657 };
3658 static const unsigned int sdhi2_wp_b_pins[] = {
3659 	/* WP */
3660 	RCAR_GP_PIN(5, 11),
3661 };
3662 static const unsigned int sdhi2_wp_b_mux[] = {
3663 	SD2_WP_B_MARK,
3664 };
3665 static const unsigned int sdhi2_ds_pins[] = {
3666 	/* DS */
3667 	RCAR_GP_PIN(4, 6),
3668 };
3669 static const unsigned int sdhi2_ds_mux[] = {
3670 	SD2_DS_MARK,
3671 };
3672 /* - SDHI3 ------------------------------------------------------------------ */
3673 static const unsigned int sdhi3_data1_pins[] = {
3674 	/* D0 */
3675 	RCAR_GP_PIN(4, 9),
3676 };
3677 static const unsigned int sdhi3_data1_mux[] = {
3678 	SD3_DAT0_MARK,
3679 };
3680 static const unsigned int sdhi3_data4_pins[] = {
3681 	/* D[0:3] */
3682 	RCAR_GP_PIN(4, 9),  RCAR_GP_PIN(4, 10),
3683 	RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3684 };
3685 static const unsigned int sdhi3_data4_mux[] = {
3686 	SD3_DAT0_MARK, SD3_DAT1_MARK,
3687 	SD3_DAT2_MARK, SD3_DAT3_MARK,
3688 };
3689 static const unsigned int sdhi3_data8_pins[] = {
3690 	/* D[0:7] */
3691 	RCAR_GP_PIN(4, 9),  RCAR_GP_PIN(4, 10),
3692 	RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3693 	RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
3694 	RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
3695 };
3696 static const unsigned int sdhi3_data8_mux[] = {
3697 	SD3_DAT0_MARK, SD3_DAT1_MARK,
3698 	SD3_DAT2_MARK, SD3_DAT3_MARK,
3699 	SD3_DAT4_MARK, SD3_DAT5_MARK,
3700 	SD3_DAT6_MARK, SD3_DAT7_MARK,
3701 };
3702 static const unsigned int sdhi3_ctrl_pins[] = {
3703 	/* CLK, CMD */
3704 	RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
3705 };
3706 static const unsigned int sdhi3_ctrl_mux[] = {
3707 	SD3_CLK_MARK, SD3_CMD_MARK,
3708 };
3709 static const unsigned int sdhi3_cd_pins[] = {
3710 	/* CD */
3711 	RCAR_GP_PIN(4, 15),
3712 };
3713 static const unsigned int sdhi3_cd_mux[] = {
3714 	SD3_CD_MARK,
3715 };
3716 static const unsigned int sdhi3_wp_pins[] = {
3717 	/* WP */
3718 	RCAR_GP_PIN(4, 16),
3719 };
3720 static const unsigned int sdhi3_wp_mux[] = {
3721 	SD3_WP_MARK,
3722 };
3723 static const unsigned int sdhi3_ds_pins[] = {
3724 	/* DS */
3725 	RCAR_GP_PIN(4, 17),
3726 };
3727 static const unsigned int sdhi3_ds_mux[] = {
3728 	SD3_DS_MARK,
3729 };
3730 
3731 /* - SSI -------------------------------------------------------------------- */
3732 static const unsigned int ssi0_data_pins[] = {
3733 	/* SDATA */
3734 	RCAR_GP_PIN(6, 2),
3735 };
3736 static const unsigned int ssi0_data_mux[] = {
3737 	SSI_SDATA0_MARK,
3738 };
3739 static const unsigned int ssi01239_ctrl_pins[] = {
3740 	/* SCK, WS */
3741 	RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3742 };
3743 static const unsigned int ssi01239_ctrl_mux[] = {
3744 	SSI_SCK01239_MARK, SSI_WS01239_MARK,
3745 };
3746 static const unsigned int ssi1_data_a_pins[] = {
3747 	/* SDATA */
3748 	RCAR_GP_PIN(6, 3),
3749 };
3750 static const unsigned int ssi1_data_a_mux[] = {
3751 	SSI_SDATA1_A_MARK,
3752 };
3753 static const unsigned int ssi1_data_b_pins[] = {
3754 	/* SDATA */
3755 	RCAR_GP_PIN(5, 12),
3756 };
3757 static const unsigned int ssi1_data_b_mux[] = {
3758 	SSI_SDATA1_B_MARK,
3759 };
3760 static const unsigned int ssi1_ctrl_a_pins[] = {
3761 	/* SCK, WS */
3762 	RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3763 };
3764 static const unsigned int ssi1_ctrl_a_mux[] = {
3765 	SSI_SCK1_A_MARK, SSI_WS1_A_MARK,
3766 };
3767 static const unsigned int ssi1_ctrl_b_pins[] = {
3768 	/* SCK, WS */
3769 	RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21),
3770 };
3771 static const unsigned int ssi1_ctrl_b_mux[] = {
3772 	SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
3773 };
3774 static const unsigned int ssi2_data_a_pins[] = {
3775 	/* SDATA */
3776 	RCAR_GP_PIN(6, 4),
3777 };
3778 static const unsigned int ssi2_data_a_mux[] = {
3779 	SSI_SDATA2_A_MARK,
3780 };
3781 static const unsigned int ssi2_data_b_pins[] = {
3782 	/* SDATA */
3783 	RCAR_GP_PIN(5, 13),
3784 };
3785 static const unsigned int ssi2_data_b_mux[] = {
3786 	SSI_SDATA2_B_MARK,
3787 };
3788 static const unsigned int ssi2_ctrl_a_pins[] = {
3789 	/* SCK, WS */
3790 	RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3791 };
3792 static const unsigned int ssi2_ctrl_a_mux[] = {
3793 	SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
3794 };
3795 static const unsigned int ssi2_ctrl_b_pins[] = {
3796 	/* SCK, WS */
3797 	RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3798 };
3799 static const unsigned int ssi2_ctrl_b_mux[] = {
3800 	SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
3801 };
3802 static const unsigned int ssi3_data_pins[] = {
3803 	/* SDATA */
3804 	RCAR_GP_PIN(6, 7),
3805 };
3806 static const unsigned int ssi3_data_mux[] = {
3807 	SSI_SDATA3_MARK,
3808 };
3809 static const unsigned int ssi349_ctrl_pins[] = {
3810 	/* SCK, WS */
3811 	RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
3812 };
3813 static const unsigned int ssi349_ctrl_mux[] = {
3814 	SSI_SCK349_MARK, SSI_WS349_MARK,
3815 };
3816 static const unsigned int ssi4_data_pins[] = {
3817 	/* SDATA */
3818 	RCAR_GP_PIN(6, 10),
3819 };
3820 static const unsigned int ssi4_data_mux[] = {
3821 	SSI_SDATA4_MARK,
3822 };
3823 static const unsigned int ssi4_ctrl_pins[] = {
3824 	/* SCK, WS */
3825 	RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
3826 };
3827 static const unsigned int ssi4_ctrl_mux[] = {
3828 	SSI_SCK4_MARK, SSI_WS4_MARK,
3829 };
3830 static const unsigned int ssi5_data_pins[] = {
3831 	/* SDATA */
3832 	RCAR_GP_PIN(6, 13),
3833 };
3834 static const unsigned int ssi5_data_mux[] = {
3835 	SSI_SDATA5_MARK,
3836 };
3837 static const unsigned int ssi5_ctrl_pins[] = {
3838 	/* SCK, WS */
3839 	RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
3840 };
3841 static const unsigned int ssi5_ctrl_mux[] = {
3842 	SSI_SCK5_MARK, SSI_WS5_MARK,
3843 };
3844 static const unsigned int ssi6_data_pins[] = {
3845 	/* SDATA */
3846 	RCAR_GP_PIN(6, 16),
3847 };
3848 static const unsigned int ssi6_data_mux[] = {
3849 	SSI_SDATA6_MARK,
3850 };
3851 static const unsigned int ssi6_ctrl_pins[] = {
3852 	/* SCK, WS */
3853 	RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3854 };
3855 static const unsigned int ssi6_ctrl_mux[] = {
3856 	SSI_SCK6_MARK, SSI_WS6_MARK,
3857 };
3858 static const unsigned int ssi7_data_pins[] = {
3859 	/* SDATA */
3860 	RCAR_GP_PIN(6, 19),
3861 };
3862 static const unsigned int ssi7_data_mux[] = {
3863 	SSI_SDATA7_MARK,
3864 };
3865 static const unsigned int ssi78_ctrl_pins[] = {
3866 	/* SCK, WS */
3867 	RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
3868 };
3869 static const unsigned int ssi78_ctrl_mux[] = {
3870 	SSI_SCK78_MARK, SSI_WS78_MARK,
3871 };
3872 static const unsigned int ssi8_data_pins[] = {
3873 	/* SDATA */
3874 	RCAR_GP_PIN(6, 20),
3875 };
3876 static const unsigned int ssi8_data_mux[] = {
3877 	SSI_SDATA8_MARK,
3878 };
3879 static const unsigned int ssi9_data_a_pins[] = {
3880 	/* SDATA */
3881 	RCAR_GP_PIN(6, 21),
3882 };
3883 static const unsigned int ssi9_data_a_mux[] = {
3884 	SSI_SDATA9_A_MARK,
3885 };
3886 static const unsigned int ssi9_data_b_pins[] = {
3887 	/* SDATA */
3888 	RCAR_GP_PIN(5, 14),
3889 };
3890 static const unsigned int ssi9_data_b_mux[] = {
3891 	SSI_SDATA9_B_MARK,
3892 };
3893 static const unsigned int ssi9_ctrl_a_pins[] = {
3894 	/* SCK, WS */
3895 	RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3896 };
3897 static const unsigned int ssi9_ctrl_a_mux[] = {
3898 	SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
3899 };
3900 static const unsigned int ssi9_ctrl_b_pins[] = {
3901 	/* SCK, WS */
3902 	RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
3903 };
3904 static const unsigned int ssi9_ctrl_b_mux[] = {
3905 	SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
3906 };
3907 
3908 /* - TMU -------------------------------------------------------------------- */
3909 static const unsigned int tmu_tclk1_a_pins[] = {
3910 	/* TCLK */
3911 	RCAR_GP_PIN(6, 23),
3912 };
3913 static const unsigned int tmu_tclk1_a_mux[] = {
3914 	TCLK1_A_MARK,
3915 };
3916 static const unsigned int tmu_tclk1_b_pins[] = {
3917 	/* TCLK */
3918 	RCAR_GP_PIN(5, 19),
3919 };
3920 static const unsigned int tmu_tclk1_b_mux[] = {
3921 	TCLK1_B_MARK,
3922 };
3923 static const unsigned int tmu_tclk2_a_pins[] = {
3924 	/* TCLK */
3925 	RCAR_GP_PIN(6, 19),
3926 };
3927 static const unsigned int tmu_tclk2_a_mux[] = {
3928 	TCLK2_A_MARK,
3929 };
3930 static const unsigned int tmu_tclk2_b_pins[] = {
3931 	/* TCLK */
3932 	RCAR_GP_PIN(6, 28),
3933 };
3934 static const unsigned int tmu_tclk2_b_mux[] = {
3935 	TCLK2_B_MARK,
3936 };
3937 
3938 /* - TPU ------------------------------------------------------------------- */
3939 static const unsigned int tpu_to0_pins[] = {
3940 	/* TPU0TO0 */
3941 	RCAR_GP_PIN(6, 28),
3942 };
3943 static const unsigned int tpu_to0_mux[] = {
3944 	TPU0TO0_MARK,
3945 };
3946 static const unsigned int tpu_to1_pins[] = {
3947 	/* TPU0TO1 */
3948 	RCAR_GP_PIN(6, 29),
3949 };
3950 static const unsigned int tpu_to1_mux[] = {
3951 	TPU0TO1_MARK,
3952 };
3953 static const unsigned int tpu_to2_pins[] = {
3954 	/* TPU0TO2 */
3955 	RCAR_GP_PIN(6, 30),
3956 };
3957 static const unsigned int tpu_to2_mux[] = {
3958 	TPU0TO2_MARK,
3959 };
3960 static const unsigned int tpu_to3_pins[] = {
3961 	/* TPU0TO3 */
3962 	RCAR_GP_PIN(6, 31),
3963 };
3964 static const unsigned int tpu_to3_mux[] = {
3965 	TPU0TO3_MARK,
3966 };
3967 
3968 /* - USB0 ------------------------------------------------------------------- */
3969 static const unsigned int usb0_pins[] = {
3970 	/* PWEN, OVC */
3971 	RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
3972 };
3973 static const unsigned int usb0_mux[] = {
3974 	USB0_PWEN_MARK, USB0_OVC_MARK,
3975 };
3976 /* - USB1 ------------------------------------------------------------------- */
3977 static const unsigned int usb1_pins[] = {
3978 	/* PWEN, OVC */
3979 	RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3980 };
3981 static const unsigned int usb1_mux[] = {
3982 	USB1_PWEN_MARK, USB1_OVC_MARK,
3983 };
3984 
3985 /* - USB30 ------------------------------------------------------------------ */
3986 static const unsigned int usb30_pins[] = {
3987 	/* PWEN, OVC */
3988 	RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3989 };
3990 static const unsigned int usb30_mux[] = {
3991 	USB30_PWEN_MARK, USB30_OVC_MARK,
3992 };
3993 
3994 /* - VIN4 ------------------------------------------------------------------- */
3995 static const unsigned int vin4_data18_a_pins[] = {
3996 	RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3997 	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3998 	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3999 	RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4000 	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4001 	RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4002 	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4003 	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4004 	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4005 };
4006 static const unsigned int vin4_data18_a_mux[] = {
4007 	VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
4008 	VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
4009 	VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
4010 	VI4_DATA10_MARK, VI4_DATA11_MARK,
4011 	VI4_DATA12_MARK, VI4_DATA13_MARK,
4012 	VI4_DATA14_MARK, VI4_DATA15_MARK,
4013 	VI4_DATA18_MARK, VI4_DATA19_MARK,
4014 	VI4_DATA20_MARK, VI4_DATA21_MARK,
4015 	VI4_DATA22_MARK, VI4_DATA23_MARK,
4016 };
4017 static const unsigned int vin4_data18_b_pins[] = {
4018 	RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
4019 	RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
4020 	RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
4021 	RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4022 	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4023 	RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4024 	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4025 	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4026 	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4027 };
4028 static const unsigned int vin4_data18_b_mux[] = {
4029 	VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
4030 	VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
4031 	VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
4032 	VI4_DATA10_MARK, VI4_DATA11_MARK,
4033 	VI4_DATA12_MARK, VI4_DATA13_MARK,
4034 	VI4_DATA14_MARK, VI4_DATA15_MARK,
4035 	VI4_DATA18_MARK, VI4_DATA19_MARK,
4036 	VI4_DATA20_MARK, VI4_DATA21_MARK,
4037 	VI4_DATA22_MARK, VI4_DATA23_MARK,
4038 };
4039 static const union vin_data vin4_data_a_pins = {
4040 	.data24 = {
4041 		RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
4042 		RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
4043 		RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
4044 		RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
4045 		RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
4046 		RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4047 		RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4048 		RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4049 		RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4050 		RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4051 		RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4052 		RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4053 	},
4054 };
4055 static const union vin_data vin4_data_a_mux = {
4056 	.data24 = {
4057 		VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
4058 		VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
4059 		VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
4060 		VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
4061 		VI4_DATA8_MARK,  VI4_DATA9_MARK,
4062 		VI4_DATA10_MARK, VI4_DATA11_MARK,
4063 		VI4_DATA12_MARK, VI4_DATA13_MARK,
4064 		VI4_DATA14_MARK, VI4_DATA15_MARK,
4065 		VI4_DATA16_MARK, VI4_DATA17_MARK,
4066 		VI4_DATA18_MARK, VI4_DATA19_MARK,
4067 		VI4_DATA20_MARK, VI4_DATA21_MARK,
4068 		VI4_DATA22_MARK, VI4_DATA23_MARK,
4069 	},
4070 };
4071 static const union vin_data vin4_data_b_pins = {
4072 	.data24 = {
4073 		RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
4074 		RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
4075 		RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
4076 		RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
4077 		RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
4078 		RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4079 		RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4080 		RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4081 		RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4082 		RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4083 		RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4084 		RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4085 	},
4086 };
4087 static const union vin_data vin4_data_b_mux = {
4088 	.data24 = {
4089 		VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
4090 		VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
4091 		VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
4092 		VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
4093 		VI4_DATA8_MARK,  VI4_DATA9_MARK,
4094 		VI4_DATA10_MARK, VI4_DATA11_MARK,
4095 		VI4_DATA12_MARK, VI4_DATA13_MARK,
4096 		VI4_DATA14_MARK, VI4_DATA15_MARK,
4097 		VI4_DATA16_MARK, VI4_DATA17_MARK,
4098 		VI4_DATA18_MARK, VI4_DATA19_MARK,
4099 		VI4_DATA20_MARK, VI4_DATA21_MARK,
4100 		VI4_DATA22_MARK, VI4_DATA23_MARK,
4101 	},
4102 };
4103 static const unsigned int vin4_sync_pins[] = {
4104 	/* HSYNC#, VSYNC# */
4105 	RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 17),
4106 };
4107 static const unsigned int vin4_sync_mux[] = {
4108 	VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
4109 };
4110 static const unsigned int vin4_field_pins[] = {
4111 	/* FIELD */
4112 	RCAR_GP_PIN(1, 16),
4113 };
4114 static const unsigned int vin4_field_mux[] = {
4115 	VI4_FIELD_MARK,
4116 };
4117 static const unsigned int vin4_clkenb_pins[] = {
4118 	/* CLKENB */
4119 	RCAR_GP_PIN(1, 19),
4120 };
4121 static const unsigned int vin4_clkenb_mux[] = {
4122 	VI4_CLKENB_MARK,
4123 };
4124 static const unsigned int vin4_clk_pins[] = {
4125 	/* CLK */
4126 	RCAR_GP_PIN(1, 27),
4127 };
4128 static const unsigned int vin4_clk_mux[] = {
4129 	VI4_CLK_MARK,
4130 };
4131 
4132 /* - VIN5 ------------------------------------------------------------------- */
4133 static const union vin_data16 vin5_data_pins = {
4134 	.data16 = {
4135 		RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4136 		RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4137 		RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4138 		RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4139 		RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
4140 		RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
4141 		RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4142 		RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4143 	},
4144 };
4145 static const union vin_data16 vin5_data_mux = {
4146 	.data16 = {
4147 		VI5_DATA0_MARK, VI5_DATA1_MARK,
4148 		VI5_DATA2_MARK, VI5_DATA3_MARK,
4149 		VI5_DATA4_MARK, VI5_DATA5_MARK,
4150 		VI5_DATA6_MARK, VI5_DATA7_MARK,
4151 		VI5_DATA8_MARK,  VI5_DATA9_MARK,
4152 		VI5_DATA10_MARK, VI5_DATA11_MARK,
4153 		VI5_DATA12_MARK, VI5_DATA13_MARK,
4154 		VI5_DATA14_MARK, VI5_DATA15_MARK,
4155 	},
4156 };
4157 static const unsigned int vin5_sync_pins[] = {
4158 	/* HSYNC#, VSYNC# */
4159 	RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
4160 };
4161 static const unsigned int vin5_sync_mux[] = {
4162 	VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK,
4163 };
4164 static const unsigned int vin5_field_pins[] = {
4165 	RCAR_GP_PIN(1, 11),
4166 };
4167 static const unsigned int vin5_field_mux[] = {
4168 	/* FIELD */
4169 	VI5_FIELD_MARK,
4170 };
4171 static const unsigned int vin5_clkenb_pins[] = {
4172 	RCAR_GP_PIN(1, 20),
4173 };
4174 static const unsigned int vin5_clkenb_mux[] = {
4175 	/* CLKENB */
4176 	VI5_CLKENB_MARK,
4177 };
4178 static const unsigned int vin5_clk_pins[] = {
4179 	RCAR_GP_PIN(1, 21),
4180 };
4181 static const unsigned int vin5_clk_mux[] = {
4182 	/* CLK */
4183 	VI5_CLK_MARK,
4184 };
4185 
4186 static const struct {
4187 	struct sh_pfc_pin_group common[322];
4188 #if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
4189 	struct sh_pfc_pin_group automotive[30];
4190 #endif
4191 } pinmux_groups = {
4192 	.common = {
4193 		SH_PFC_PIN_GROUP(audio_clk_a_a),
4194 		SH_PFC_PIN_GROUP(audio_clk_a_b),
4195 		SH_PFC_PIN_GROUP(audio_clk_a_c),
4196 		SH_PFC_PIN_GROUP(audio_clk_b_a),
4197 		SH_PFC_PIN_GROUP(audio_clk_b_b),
4198 		SH_PFC_PIN_GROUP(audio_clk_c_a),
4199 		SH_PFC_PIN_GROUP(audio_clk_c_b),
4200 		SH_PFC_PIN_GROUP(audio_clkout_a),
4201 		SH_PFC_PIN_GROUP(audio_clkout_b),
4202 		SH_PFC_PIN_GROUP(audio_clkout_c),
4203 		SH_PFC_PIN_GROUP(audio_clkout_d),
4204 		SH_PFC_PIN_GROUP(audio_clkout1_a),
4205 		SH_PFC_PIN_GROUP(audio_clkout1_b),
4206 		SH_PFC_PIN_GROUP(audio_clkout2_a),
4207 		SH_PFC_PIN_GROUP(audio_clkout2_b),
4208 		SH_PFC_PIN_GROUP(audio_clkout3_a),
4209 		SH_PFC_PIN_GROUP(audio_clkout3_b),
4210 		SH_PFC_PIN_GROUP(avb_link),
4211 		SH_PFC_PIN_GROUP(avb_magic),
4212 		SH_PFC_PIN_GROUP(avb_phy_int),
4213 		SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio), /* Deprecated */
4214 		SH_PFC_PIN_GROUP(avb_mdio),
4215 		SH_PFC_PIN_GROUP(avb_mii),
4216 		SH_PFC_PIN_GROUP(avb_avtp_pps),
4217 		SH_PFC_PIN_GROUP(avb_avtp_match_a),
4218 		SH_PFC_PIN_GROUP(avb_avtp_capture_a),
4219 		SH_PFC_PIN_GROUP(avb_avtp_match_b),
4220 		SH_PFC_PIN_GROUP(avb_avtp_capture_b),
4221 		SH_PFC_PIN_GROUP(can0_data_a),
4222 		SH_PFC_PIN_GROUP(can0_data_b),
4223 		SH_PFC_PIN_GROUP(can1_data),
4224 		SH_PFC_PIN_GROUP(can_clk),
4225 		SH_PFC_PIN_GROUP(canfd0_data_a),
4226 		SH_PFC_PIN_GROUP(canfd0_data_b),
4227 		SH_PFC_PIN_GROUP(canfd1_data),
4228 		SH_PFC_PIN_GROUP(du_rgb666),
4229 		SH_PFC_PIN_GROUP(du_rgb888),
4230 		SH_PFC_PIN_GROUP(du_clk_out_0),
4231 		SH_PFC_PIN_GROUP(du_clk_out_1),
4232 		SH_PFC_PIN_GROUP(du_sync),
4233 		SH_PFC_PIN_GROUP(du_oddf),
4234 		SH_PFC_PIN_GROUP(du_cde),
4235 		SH_PFC_PIN_GROUP(du_disp),
4236 		SH_PFC_PIN_GROUP(hscif0_data),
4237 		SH_PFC_PIN_GROUP(hscif0_clk),
4238 		SH_PFC_PIN_GROUP(hscif0_ctrl),
4239 		SH_PFC_PIN_GROUP(hscif1_data_a),
4240 		SH_PFC_PIN_GROUP(hscif1_clk_a),
4241 		SH_PFC_PIN_GROUP(hscif1_ctrl_a),
4242 		SH_PFC_PIN_GROUP(hscif1_data_b),
4243 		SH_PFC_PIN_GROUP(hscif1_clk_b),
4244 		SH_PFC_PIN_GROUP(hscif1_ctrl_b),
4245 		SH_PFC_PIN_GROUP(hscif2_data_a),
4246 		SH_PFC_PIN_GROUP(hscif2_clk_a),
4247 		SH_PFC_PIN_GROUP(hscif2_ctrl_a),
4248 		SH_PFC_PIN_GROUP(hscif2_data_b),
4249 		SH_PFC_PIN_GROUP(hscif2_clk_b),
4250 		SH_PFC_PIN_GROUP(hscif2_ctrl_b),
4251 		SH_PFC_PIN_GROUP(hscif2_data_c),
4252 		SH_PFC_PIN_GROUP(hscif2_clk_c),
4253 		SH_PFC_PIN_GROUP(hscif2_ctrl_c),
4254 		SH_PFC_PIN_GROUP(hscif3_data_a),
4255 		SH_PFC_PIN_GROUP(hscif3_clk),
4256 		SH_PFC_PIN_GROUP(hscif3_ctrl),
4257 		SH_PFC_PIN_GROUP(hscif3_data_b),
4258 		SH_PFC_PIN_GROUP(hscif3_data_c),
4259 		SH_PFC_PIN_GROUP(hscif3_data_d),
4260 		SH_PFC_PIN_GROUP(hscif4_data_a),
4261 		SH_PFC_PIN_GROUP(hscif4_clk),
4262 		SH_PFC_PIN_GROUP(hscif4_ctrl),
4263 		SH_PFC_PIN_GROUP(hscif4_data_b),
4264 		SH_PFC_PIN_GROUP(i2c0),
4265 		SH_PFC_PIN_GROUP(i2c1_a),
4266 		SH_PFC_PIN_GROUP(i2c1_b),
4267 		SH_PFC_PIN_GROUP(i2c2_a),
4268 		SH_PFC_PIN_GROUP(i2c2_b),
4269 		SH_PFC_PIN_GROUP(i2c3),
4270 		SH_PFC_PIN_GROUP(i2c5),
4271 		SH_PFC_PIN_GROUP(i2c6_a),
4272 		SH_PFC_PIN_GROUP(i2c6_b),
4273 		SH_PFC_PIN_GROUP(i2c6_c),
4274 		SH_PFC_PIN_GROUP(intc_ex_irq0),
4275 		SH_PFC_PIN_GROUP(intc_ex_irq1),
4276 		SH_PFC_PIN_GROUP(intc_ex_irq2),
4277 		SH_PFC_PIN_GROUP(intc_ex_irq3),
4278 		SH_PFC_PIN_GROUP(intc_ex_irq4),
4279 		SH_PFC_PIN_GROUP(intc_ex_irq5),
4280 		SH_PFC_PIN_GROUP(msiof0_clk),
4281 		SH_PFC_PIN_GROUP(msiof0_sync),
4282 		SH_PFC_PIN_GROUP(msiof0_ss1),
4283 		SH_PFC_PIN_GROUP(msiof0_ss2),
4284 		SH_PFC_PIN_GROUP(msiof0_txd),
4285 		SH_PFC_PIN_GROUP(msiof0_rxd),
4286 		SH_PFC_PIN_GROUP(msiof1_clk_a),
4287 		SH_PFC_PIN_GROUP(msiof1_sync_a),
4288 		SH_PFC_PIN_GROUP(msiof1_ss1_a),
4289 		SH_PFC_PIN_GROUP(msiof1_ss2_a),
4290 		SH_PFC_PIN_GROUP(msiof1_txd_a),
4291 		SH_PFC_PIN_GROUP(msiof1_rxd_a),
4292 		SH_PFC_PIN_GROUP(msiof1_clk_b),
4293 		SH_PFC_PIN_GROUP(msiof1_sync_b),
4294 		SH_PFC_PIN_GROUP(msiof1_ss1_b),
4295 		SH_PFC_PIN_GROUP(msiof1_ss2_b),
4296 		SH_PFC_PIN_GROUP(msiof1_txd_b),
4297 		SH_PFC_PIN_GROUP(msiof1_rxd_b),
4298 		SH_PFC_PIN_GROUP(msiof1_clk_c),
4299 		SH_PFC_PIN_GROUP(msiof1_sync_c),
4300 		SH_PFC_PIN_GROUP(msiof1_ss1_c),
4301 		SH_PFC_PIN_GROUP(msiof1_ss2_c),
4302 		SH_PFC_PIN_GROUP(msiof1_txd_c),
4303 		SH_PFC_PIN_GROUP(msiof1_rxd_c),
4304 		SH_PFC_PIN_GROUP(msiof1_clk_d),
4305 		SH_PFC_PIN_GROUP(msiof1_sync_d),
4306 		SH_PFC_PIN_GROUP(msiof1_ss1_d),
4307 		SH_PFC_PIN_GROUP(msiof1_ss2_d),
4308 		SH_PFC_PIN_GROUP(msiof1_txd_d),
4309 		SH_PFC_PIN_GROUP(msiof1_rxd_d),
4310 		SH_PFC_PIN_GROUP(msiof1_clk_e),
4311 		SH_PFC_PIN_GROUP(msiof1_sync_e),
4312 		SH_PFC_PIN_GROUP(msiof1_ss1_e),
4313 		SH_PFC_PIN_GROUP(msiof1_ss2_e),
4314 		SH_PFC_PIN_GROUP(msiof1_txd_e),
4315 		SH_PFC_PIN_GROUP(msiof1_rxd_e),
4316 		SH_PFC_PIN_GROUP(msiof1_clk_f),
4317 		SH_PFC_PIN_GROUP(msiof1_sync_f),
4318 		SH_PFC_PIN_GROUP(msiof1_ss1_f),
4319 		SH_PFC_PIN_GROUP(msiof1_ss2_f),
4320 		SH_PFC_PIN_GROUP(msiof1_txd_f),
4321 		SH_PFC_PIN_GROUP(msiof1_rxd_f),
4322 		SH_PFC_PIN_GROUP(msiof1_clk_g),
4323 		SH_PFC_PIN_GROUP(msiof1_sync_g),
4324 		SH_PFC_PIN_GROUP(msiof1_ss1_g),
4325 		SH_PFC_PIN_GROUP(msiof1_ss2_g),
4326 		SH_PFC_PIN_GROUP(msiof1_txd_g),
4327 		SH_PFC_PIN_GROUP(msiof1_rxd_g),
4328 		SH_PFC_PIN_GROUP(msiof2_clk_a),
4329 		SH_PFC_PIN_GROUP(msiof2_sync_a),
4330 		SH_PFC_PIN_GROUP(msiof2_ss1_a),
4331 		SH_PFC_PIN_GROUP(msiof2_ss2_a),
4332 		SH_PFC_PIN_GROUP(msiof2_txd_a),
4333 		SH_PFC_PIN_GROUP(msiof2_rxd_a),
4334 		SH_PFC_PIN_GROUP(msiof2_clk_b),
4335 		SH_PFC_PIN_GROUP(msiof2_sync_b),
4336 		SH_PFC_PIN_GROUP(msiof2_ss1_b),
4337 		SH_PFC_PIN_GROUP(msiof2_ss2_b),
4338 		SH_PFC_PIN_GROUP(msiof2_txd_b),
4339 		SH_PFC_PIN_GROUP(msiof2_rxd_b),
4340 		SH_PFC_PIN_GROUP(msiof2_clk_c),
4341 		SH_PFC_PIN_GROUP(msiof2_sync_c),
4342 		SH_PFC_PIN_GROUP(msiof2_ss1_c),
4343 		SH_PFC_PIN_GROUP(msiof2_ss2_c),
4344 		SH_PFC_PIN_GROUP(msiof2_txd_c),
4345 		SH_PFC_PIN_GROUP(msiof2_rxd_c),
4346 		SH_PFC_PIN_GROUP(msiof2_clk_d),
4347 		SH_PFC_PIN_GROUP(msiof2_sync_d),
4348 		SH_PFC_PIN_GROUP(msiof2_ss1_d),
4349 		SH_PFC_PIN_GROUP(msiof2_ss2_d),
4350 		SH_PFC_PIN_GROUP(msiof2_txd_d),
4351 		SH_PFC_PIN_GROUP(msiof2_rxd_d),
4352 		SH_PFC_PIN_GROUP(msiof3_clk_a),
4353 		SH_PFC_PIN_GROUP(msiof3_sync_a),
4354 		SH_PFC_PIN_GROUP(msiof3_ss1_a),
4355 		SH_PFC_PIN_GROUP(msiof3_ss2_a),
4356 		SH_PFC_PIN_GROUP(msiof3_txd_a),
4357 		SH_PFC_PIN_GROUP(msiof3_rxd_a),
4358 		SH_PFC_PIN_GROUP(msiof3_clk_b),
4359 		SH_PFC_PIN_GROUP(msiof3_sync_b),
4360 		SH_PFC_PIN_GROUP(msiof3_ss1_b),
4361 		SH_PFC_PIN_GROUP(msiof3_ss2_b),
4362 		SH_PFC_PIN_GROUP(msiof3_txd_b),
4363 		SH_PFC_PIN_GROUP(msiof3_rxd_b),
4364 		SH_PFC_PIN_GROUP(msiof3_clk_c),
4365 		SH_PFC_PIN_GROUP(msiof3_sync_c),
4366 		SH_PFC_PIN_GROUP(msiof3_txd_c),
4367 		SH_PFC_PIN_GROUP(msiof3_rxd_c),
4368 		SH_PFC_PIN_GROUP(msiof3_clk_d),
4369 		SH_PFC_PIN_GROUP(msiof3_sync_d),
4370 		SH_PFC_PIN_GROUP(msiof3_ss1_d),
4371 		SH_PFC_PIN_GROUP(msiof3_txd_d),
4372 		SH_PFC_PIN_GROUP(msiof3_rxd_d),
4373 		SH_PFC_PIN_GROUP(msiof3_clk_e),
4374 		SH_PFC_PIN_GROUP(msiof3_sync_e),
4375 		SH_PFC_PIN_GROUP(msiof3_ss1_e),
4376 		SH_PFC_PIN_GROUP(msiof3_ss2_e),
4377 		SH_PFC_PIN_GROUP(msiof3_txd_e),
4378 		SH_PFC_PIN_GROUP(msiof3_rxd_e),
4379 		SH_PFC_PIN_GROUP(pwm0),
4380 		SH_PFC_PIN_GROUP(pwm1_a),
4381 		SH_PFC_PIN_GROUP(pwm1_b),
4382 		SH_PFC_PIN_GROUP(pwm2_a),
4383 		SH_PFC_PIN_GROUP(pwm2_b),
4384 		SH_PFC_PIN_GROUP(pwm3_a),
4385 		SH_PFC_PIN_GROUP(pwm3_b),
4386 		SH_PFC_PIN_GROUP(pwm4_a),
4387 		SH_PFC_PIN_GROUP(pwm4_b),
4388 		SH_PFC_PIN_GROUP(pwm5_a),
4389 		SH_PFC_PIN_GROUP(pwm5_b),
4390 		SH_PFC_PIN_GROUP(pwm6_a),
4391 		SH_PFC_PIN_GROUP(pwm6_b),
4392 		SH_PFC_PIN_GROUP(qspi0_ctrl),
4393 		SH_PFC_PIN_GROUP(qspi0_data2),
4394 		SH_PFC_PIN_GROUP(qspi0_data4),
4395 		SH_PFC_PIN_GROUP(qspi1_ctrl),
4396 		SH_PFC_PIN_GROUP(qspi1_data2),
4397 		SH_PFC_PIN_GROUP(qspi1_data4),
4398 		SH_PFC_PIN_GROUP(scif0_data),
4399 		SH_PFC_PIN_GROUP(scif0_clk),
4400 		SH_PFC_PIN_GROUP(scif0_ctrl),
4401 		SH_PFC_PIN_GROUP(scif1_data_a),
4402 		SH_PFC_PIN_GROUP(scif1_clk),
4403 		SH_PFC_PIN_GROUP(scif1_ctrl),
4404 		SH_PFC_PIN_GROUP(scif1_data_b),
4405 		SH_PFC_PIN_GROUP(scif2_data_a),
4406 		SH_PFC_PIN_GROUP(scif2_clk),
4407 		SH_PFC_PIN_GROUP(scif2_data_b),
4408 		SH_PFC_PIN_GROUP(scif3_data_a),
4409 		SH_PFC_PIN_GROUP(scif3_clk),
4410 		SH_PFC_PIN_GROUP(scif3_ctrl),
4411 		SH_PFC_PIN_GROUP(scif3_data_b),
4412 		SH_PFC_PIN_GROUP(scif4_data_a),
4413 		SH_PFC_PIN_GROUP(scif4_clk_a),
4414 		SH_PFC_PIN_GROUP(scif4_ctrl_a),
4415 		SH_PFC_PIN_GROUP(scif4_data_b),
4416 		SH_PFC_PIN_GROUP(scif4_clk_b),
4417 		SH_PFC_PIN_GROUP(scif4_ctrl_b),
4418 		SH_PFC_PIN_GROUP(scif4_data_c),
4419 		SH_PFC_PIN_GROUP(scif4_clk_c),
4420 		SH_PFC_PIN_GROUP(scif4_ctrl_c),
4421 		SH_PFC_PIN_GROUP(scif5_data_a),
4422 		SH_PFC_PIN_GROUP(scif5_clk_a),
4423 		SH_PFC_PIN_GROUP(scif5_data_b),
4424 		SH_PFC_PIN_GROUP(scif5_clk_b),
4425 		SH_PFC_PIN_GROUP(scif_clk_a),
4426 		SH_PFC_PIN_GROUP(scif_clk_b),
4427 		SH_PFC_PIN_GROUP(sdhi0_data1),
4428 		SH_PFC_PIN_GROUP(sdhi0_data4),
4429 		SH_PFC_PIN_GROUP(sdhi0_ctrl),
4430 		SH_PFC_PIN_GROUP(sdhi0_cd),
4431 		SH_PFC_PIN_GROUP(sdhi0_wp),
4432 		SH_PFC_PIN_GROUP(sdhi1_data1),
4433 		SH_PFC_PIN_GROUP(sdhi1_data4),
4434 		SH_PFC_PIN_GROUP(sdhi1_ctrl),
4435 		SH_PFC_PIN_GROUP(sdhi1_cd),
4436 		SH_PFC_PIN_GROUP(sdhi1_wp),
4437 		SH_PFC_PIN_GROUP(sdhi2_data1),
4438 		SH_PFC_PIN_GROUP(sdhi2_data4),
4439 		SH_PFC_PIN_GROUP(sdhi2_data8),
4440 		SH_PFC_PIN_GROUP(sdhi2_ctrl),
4441 		SH_PFC_PIN_GROUP(sdhi2_cd_a),
4442 		SH_PFC_PIN_GROUP(sdhi2_wp_a),
4443 		SH_PFC_PIN_GROUP(sdhi2_cd_b),
4444 		SH_PFC_PIN_GROUP(sdhi2_wp_b),
4445 		SH_PFC_PIN_GROUP(sdhi2_ds),
4446 		SH_PFC_PIN_GROUP(sdhi3_data1),
4447 		SH_PFC_PIN_GROUP(sdhi3_data4),
4448 		SH_PFC_PIN_GROUP(sdhi3_data8),
4449 		SH_PFC_PIN_GROUP(sdhi3_ctrl),
4450 		SH_PFC_PIN_GROUP(sdhi3_cd),
4451 		SH_PFC_PIN_GROUP(sdhi3_wp),
4452 		SH_PFC_PIN_GROUP(sdhi3_ds),
4453 		SH_PFC_PIN_GROUP(ssi0_data),
4454 		SH_PFC_PIN_GROUP(ssi01239_ctrl),
4455 		SH_PFC_PIN_GROUP(ssi1_data_a),
4456 		SH_PFC_PIN_GROUP(ssi1_data_b),
4457 		SH_PFC_PIN_GROUP(ssi1_ctrl_a),
4458 		SH_PFC_PIN_GROUP(ssi1_ctrl_b),
4459 		SH_PFC_PIN_GROUP(ssi2_data_a),
4460 		SH_PFC_PIN_GROUP(ssi2_data_b),
4461 		SH_PFC_PIN_GROUP(ssi2_ctrl_a),
4462 		SH_PFC_PIN_GROUP(ssi2_ctrl_b),
4463 		SH_PFC_PIN_GROUP(ssi3_data),
4464 		SH_PFC_PIN_GROUP(ssi349_ctrl),
4465 		SH_PFC_PIN_GROUP(ssi4_data),
4466 		SH_PFC_PIN_GROUP(ssi4_ctrl),
4467 		SH_PFC_PIN_GROUP(ssi5_data),
4468 		SH_PFC_PIN_GROUP(ssi5_ctrl),
4469 		SH_PFC_PIN_GROUP(ssi6_data),
4470 		SH_PFC_PIN_GROUP(ssi6_ctrl),
4471 		SH_PFC_PIN_GROUP(ssi7_data),
4472 		SH_PFC_PIN_GROUP(ssi78_ctrl),
4473 		SH_PFC_PIN_GROUP(ssi8_data),
4474 		SH_PFC_PIN_GROUP(ssi9_data_a),
4475 		SH_PFC_PIN_GROUP(ssi9_data_b),
4476 		SH_PFC_PIN_GROUP(ssi9_ctrl_a),
4477 		SH_PFC_PIN_GROUP(ssi9_ctrl_b),
4478 		SH_PFC_PIN_GROUP(tmu_tclk1_a),
4479 		SH_PFC_PIN_GROUP(tmu_tclk1_b),
4480 		SH_PFC_PIN_GROUP(tmu_tclk2_a),
4481 		SH_PFC_PIN_GROUP(tmu_tclk2_b),
4482 		SH_PFC_PIN_GROUP(tpu_to0),
4483 		SH_PFC_PIN_GROUP(tpu_to1),
4484 		SH_PFC_PIN_GROUP(tpu_to2),
4485 		SH_PFC_PIN_GROUP(tpu_to3),
4486 		SH_PFC_PIN_GROUP(usb0),
4487 		SH_PFC_PIN_GROUP(usb1),
4488 		SH_PFC_PIN_GROUP(usb30),
4489 		VIN_DATA_PIN_GROUP(vin4_data, 8, _a),
4490 		VIN_DATA_PIN_GROUP(vin4_data, 10, _a),
4491 		VIN_DATA_PIN_GROUP(vin4_data, 12, _a),
4492 		VIN_DATA_PIN_GROUP(vin4_data, 16, _a),
4493 		SH_PFC_PIN_GROUP(vin4_data18_a),
4494 		VIN_DATA_PIN_GROUP(vin4_data, 20, _a),
4495 		VIN_DATA_PIN_GROUP(vin4_data, 24, _a),
4496 		VIN_DATA_PIN_GROUP(vin4_data, 8, _b),
4497 		VIN_DATA_PIN_GROUP(vin4_data, 10, _b),
4498 		VIN_DATA_PIN_GROUP(vin4_data, 12, _b),
4499 		VIN_DATA_PIN_GROUP(vin4_data, 16, _b),
4500 		SH_PFC_PIN_GROUP(vin4_data18_b),
4501 		VIN_DATA_PIN_GROUP(vin4_data, 20, _b),
4502 		VIN_DATA_PIN_GROUP(vin4_data, 24, _b),
4503 		SH_PFC_PIN_GROUP(vin4_sync),
4504 		SH_PFC_PIN_GROUP(vin4_field),
4505 		SH_PFC_PIN_GROUP(vin4_clkenb),
4506 		SH_PFC_PIN_GROUP(vin4_clk),
4507 		VIN_DATA_PIN_GROUP(vin5_data, 8),
4508 		VIN_DATA_PIN_GROUP(vin5_data, 10),
4509 		VIN_DATA_PIN_GROUP(vin5_data, 12),
4510 		VIN_DATA_PIN_GROUP(vin5_data, 16),
4511 		SH_PFC_PIN_GROUP(vin5_sync),
4512 		SH_PFC_PIN_GROUP(vin5_field),
4513 		SH_PFC_PIN_GROUP(vin5_clkenb),
4514 		SH_PFC_PIN_GROUP(vin5_clk),
4515 	},
4516 #if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
4517 	.automotive = {
4518 		SH_PFC_PIN_GROUP(drif0_ctrl_a),
4519 		SH_PFC_PIN_GROUP(drif0_data0_a),
4520 		SH_PFC_PIN_GROUP(drif0_data1_a),
4521 		SH_PFC_PIN_GROUP(drif0_ctrl_b),
4522 		SH_PFC_PIN_GROUP(drif0_data0_b),
4523 		SH_PFC_PIN_GROUP(drif0_data1_b),
4524 		SH_PFC_PIN_GROUP(drif0_ctrl_c),
4525 		SH_PFC_PIN_GROUP(drif0_data0_c),
4526 		SH_PFC_PIN_GROUP(drif0_data1_c),
4527 		SH_PFC_PIN_GROUP(drif1_ctrl_a),
4528 		SH_PFC_PIN_GROUP(drif1_data0_a),
4529 		SH_PFC_PIN_GROUP(drif1_data1_a),
4530 		SH_PFC_PIN_GROUP(drif1_ctrl_b),
4531 		SH_PFC_PIN_GROUP(drif1_data0_b),
4532 		SH_PFC_PIN_GROUP(drif1_data1_b),
4533 		SH_PFC_PIN_GROUP(drif1_ctrl_c),
4534 		SH_PFC_PIN_GROUP(drif1_data0_c),
4535 		SH_PFC_PIN_GROUP(drif1_data1_c),
4536 		SH_PFC_PIN_GROUP(drif2_ctrl_a),
4537 		SH_PFC_PIN_GROUP(drif2_data0_a),
4538 		SH_PFC_PIN_GROUP(drif2_data1_a),
4539 		SH_PFC_PIN_GROUP(drif2_ctrl_b),
4540 		SH_PFC_PIN_GROUP(drif2_data0_b),
4541 		SH_PFC_PIN_GROUP(drif2_data1_b),
4542 		SH_PFC_PIN_GROUP(drif3_ctrl_a),
4543 		SH_PFC_PIN_GROUP(drif3_data0_a),
4544 		SH_PFC_PIN_GROUP(drif3_data1_a),
4545 		SH_PFC_PIN_GROUP(drif3_ctrl_b),
4546 		SH_PFC_PIN_GROUP(drif3_data0_b),
4547 		SH_PFC_PIN_GROUP(drif3_data1_b),
4548 	}
4549 #endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */
4550 };
4551 
4552 static const char * const audio_clk_groups[] = {
4553 	"audio_clk_a_a",
4554 	"audio_clk_a_b",
4555 	"audio_clk_a_c",
4556 	"audio_clk_b_a",
4557 	"audio_clk_b_b",
4558 	"audio_clk_c_a",
4559 	"audio_clk_c_b",
4560 	"audio_clkout_a",
4561 	"audio_clkout_b",
4562 	"audio_clkout_c",
4563 	"audio_clkout_d",
4564 	"audio_clkout1_a",
4565 	"audio_clkout1_b",
4566 	"audio_clkout2_a",
4567 	"audio_clkout2_b",
4568 	"audio_clkout3_a",
4569 	"audio_clkout3_b",
4570 };
4571 
4572 static const char * const avb_groups[] = {
4573 	"avb_link",
4574 	"avb_magic",
4575 	"avb_phy_int",
4576 	"avb_mdc",	/* Deprecated, please use "avb_mdio" instead */
4577 	"avb_mdio",
4578 	"avb_mii",
4579 	"avb_avtp_pps",
4580 	"avb_avtp_match_a",
4581 	"avb_avtp_capture_a",
4582 	"avb_avtp_match_b",
4583 	"avb_avtp_capture_b",
4584 };
4585 
4586 static const char * const can0_groups[] = {
4587 	"can0_data_a",
4588 	"can0_data_b",
4589 };
4590 
4591 static const char * const can1_groups[] = {
4592 	"can1_data",
4593 };
4594 
4595 static const char * const can_clk_groups[] = {
4596 	"can_clk",
4597 };
4598 
4599 static const char * const canfd0_groups[] = {
4600 	"canfd0_data_a",
4601 	"canfd0_data_b",
4602 };
4603 
4604 static const char * const canfd1_groups[] = {
4605 	"canfd1_data",
4606 };
4607 
4608 #if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
4609 static const char * const drif0_groups[] = {
4610 	"drif0_ctrl_a",
4611 	"drif0_data0_a",
4612 	"drif0_data1_a",
4613 	"drif0_ctrl_b",
4614 	"drif0_data0_b",
4615 	"drif0_data1_b",
4616 	"drif0_ctrl_c",
4617 	"drif0_data0_c",
4618 	"drif0_data1_c",
4619 };
4620 
4621 static const char * const drif1_groups[] = {
4622 	"drif1_ctrl_a",
4623 	"drif1_data0_a",
4624 	"drif1_data1_a",
4625 	"drif1_ctrl_b",
4626 	"drif1_data0_b",
4627 	"drif1_data1_b",
4628 	"drif1_ctrl_c",
4629 	"drif1_data0_c",
4630 	"drif1_data1_c",
4631 };
4632 
4633 static const char * const drif2_groups[] = {
4634 	"drif2_ctrl_a",
4635 	"drif2_data0_a",
4636 	"drif2_data1_a",
4637 	"drif2_ctrl_b",
4638 	"drif2_data0_b",
4639 	"drif2_data1_b",
4640 };
4641 
4642 static const char * const drif3_groups[] = {
4643 	"drif3_ctrl_a",
4644 	"drif3_data0_a",
4645 	"drif3_data1_a",
4646 	"drif3_ctrl_b",
4647 	"drif3_data0_b",
4648 	"drif3_data1_b",
4649 };
4650 #endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */
4651 
4652 static const char * const du_groups[] = {
4653 	"du_rgb666",
4654 	"du_rgb888",
4655 	"du_clk_out_0",
4656 	"du_clk_out_1",
4657 	"du_sync",
4658 	"du_oddf",
4659 	"du_cde",
4660 	"du_disp",
4661 };
4662 
4663 static const char * const hscif0_groups[] = {
4664 	"hscif0_data",
4665 	"hscif0_clk",
4666 	"hscif0_ctrl",
4667 };
4668 
4669 static const char * const hscif1_groups[] = {
4670 	"hscif1_data_a",
4671 	"hscif1_clk_a",
4672 	"hscif1_ctrl_a",
4673 	"hscif1_data_b",
4674 	"hscif1_clk_b",
4675 	"hscif1_ctrl_b",
4676 };
4677 
4678 static const char * const hscif2_groups[] = {
4679 	"hscif2_data_a",
4680 	"hscif2_clk_a",
4681 	"hscif2_ctrl_a",
4682 	"hscif2_data_b",
4683 	"hscif2_clk_b",
4684 	"hscif2_ctrl_b",
4685 	"hscif2_data_c",
4686 	"hscif2_clk_c",
4687 	"hscif2_ctrl_c",
4688 };
4689 
4690 static const char * const hscif3_groups[] = {
4691 	"hscif3_data_a",
4692 	"hscif3_clk",
4693 	"hscif3_ctrl",
4694 	"hscif3_data_b",
4695 	"hscif3_data_c",
4696 	"hscif3_data_d",
4697 };
4698 
4699 static const char * const hscif4_groups[] = {
4700 	"hscif4_data_a",
4701 	"hscif4_clk",
4702 	"hscif4_ctrl",
4703 	"hscif4_data_b",
4704 };
4705 
4706 static const char * const i2c0_groups[] = {
4707 	"i2c0",
4708 };
4709 
4710 static const char * const i2c1_groups[] = {
4711 	"i2c1_a",
4712 	"i2c1_b",
4713 };
4714 
4715 static const char * const i2c2_groups[] = {
4716 	"i2c2_a",
4717 	"i2c2_b",
4718 };
4719 
4720 static const char * const i2c3_groups[] = {
4721 	"i2c3",
4722 };
4723 
4724 static const char * const i2c5_groups[] = {
4725 	"i2c5",
4726 };
4727 
4728 static const char * const i2c6_groups[] = {
4729 	"i2c6_a",
4730 	"i2c6_b",
4731 	"i2c6_c",
4732 };
4733 
4734 static const char * const intc_ex_groups[] = {
4735 	"intc_ex_irq0",
4736 	"intc_ex_irq1",
4737 	"intc_ex_irq2",
4738 	"intc_ex_irq3",
4739 	"intc_ex_irq4",
4740 	"intc_ex_irq5",
4741 };
4742 
4743 static const char * const msiof0_groups[] = {
4744 	"msiof0_clk",
4745 	"msiof0_sync",
4746 	"msiof0_ss1",
4747 	"msiof0_ss2",
4748 	"msiof0_txd",
4749 	"msiof0_rxd",
4750 };
4751 
4752 static const char * const msiof1_groups[] = {
4753 	"msiof1_clk_a",
4754 	"msiof1_sync_a",
4755 	"msiof1_ss1_a",
4756 	"msiof1_ss2_a",
4757 	"msiof1_txd_a",
4758 	"msiof1_rxd_a",
4759 	"msiof1_clk_b",
4760 	"msiof1_sync_b",
4761 	"msiof1_ss1_b",
4762 	"msiof1_ss2_b",
4763 	"msiof1_txd_b",
4764 	"msiof1_rxd_b",
4765 	"msiof1_clk_c",
4766 	"msiof1_sync_c",
4767 	"msiof1_ss1_c",
4768 	"msiof1_ss2_c",
4769 	"msiof1_txd_c",
4770 	"msiof1_rxd_c",
4771 	"msiof1_clk_d",
4772 	"msiof1_sync_d",
4773 	"msiof1_ss1_d",
4774 	"msiof1_ss2_d",
4775 	"msiof1_txd_d",
4776 	"msiof1_rxd_d",
4777 	"msiof1_clk_e",
4778 	"msiof1_sync_e",
4779 	"msiof1_ss1_e",
4780 	"msiof1_ss2_e",
4781 	"msiof1_txd_e",
4782 	"msiof1_rxd_e",
4783 	"msiof1_clk_f",
4784 	"msiof1_sync_f",
4785 	"msiof1_ss1_f",
4786 	"msiof1_ss2_f",
4787 	"msiof1_txd_f",
4788 	"msiof1_rxd_f",
4789 	"msiof1_clk_g",
4790 	"msiof1_sync_g",
4791 	"msiof1_ss1_g",
4792 	"msiof1_ss2_g",
4793 	"msiof1_txd_g",
4794 	"msiof1_rxd_g",
4795 };
4796 
4797 static const char * const msiof2_groups[] = {
4798 	"msiof2_clk_a",
4799 	"msiof2_sync_a",
4800 	"msiof2_ss1_a",
4801 	"msiof2_ss2_a",
4802 	"msiof2_txd_a",
4803 	"msiof2_rxd_a",
4804 	"msiof2_clk_b",
4805 	"msiof2_sync_b",
4806 	"msiof2_ss1_b",
4807 	"msiof2_ss2_b",
4808 	"msiof2_txd_b",
4809 	"msiof2_rxd_b",
4810 	"msiof2_clk_c",
4811 	"msiof2_sync_c",
4812 	"msiof2_ss1_c",
4813 	"msiof2_ss2_c",
4814 	"msiof2_txd_c",
4815 	"msiof2_rxd_c",
4816 	"msiof2_clk_d",
4817 	"msiof2_sync_d",
4818 	"msiof2_ss1_d",
4819 	"msiof2_ss2_d",
4820 	"msiof2_txd_d",
4821 	"msiof2_rxd_d",
4822 };
4823 
4824 static const char * const msiof3_groups[] = {
4825 	"msiof3_clk_a",
4826 	"msiof3_sync_a",
4827 	"msiof3_ss1_a",
4828 	"msiof3_ss2_a",
4829 	"msiof3_txd_a",
4830 	"msiof3_rxd_a",
4831 	"msiof3_clk_b",
4832 	"msiof3_sync_b",
4833 	"msiof3_ss1_b",
4834 	"msiof3_ss2_b",
4835 	"msiof3_txd_b",
4836 	"msiof3_rxd_b",
4837 	"msiof3_clk_c",
4838 	"msiof3_sync_c",
4839 	"msiof3_txd_c",
4840 	"msiof3_rxd_c",
4841 	"msiof3_clk_d",
4842 	"msiof3_sync_d",
4843 	"msiof3_ss1_d",
4844 	"msiof3_txd_d",
4845 	"msiof3_rxd_d",
4846 	"msiof3_clk_e",
4847 	"msiof3_sync_e",
4848 	"msiof3_ss1_e",
4849 	"msiof3_ss2_e",
4850 	"msiof3_txd_e",
4851 	"msiof3_rxd_e",
4852 };
4853 
4854 static const char * const pwm0_groups[] = {
4855 	"pwm0",
4856 };
4857 
4858 static const char * const pwm1_groups[] = {
4859 	"pwm1_a",
4860 	"pwm1_b",
4861 };
4862 
4863 static const char * const pwm2_groups[] = {
4864 	"pwm2_a",
4865 	"pwm2_b",
4866 };
4867 
4868 static const char * const pwm3_groups[] = {
4869 	"pwm3_a",
4870 	"pwm3_b",
4871 };
4872 
4873 static const char * const pwm4_groups[] = {
4874 	"pwm4_a",
4875 	"pwm4_b",
4876 };
4877 
4878 static const char * const pwm5_groups[] = {
4879 	"pwm5_a",
4880 	"pwm5_b",
4881 };
4882 
4883 static const char * const pwm6_groups[] = {
4884 	"pwm6_a",
4885 	"pwm6_b",
4886 };
4887 
4888 static const char * const qspi0_groups[] = {
4889 	"qspi0_ctrl",
4890 	"qspi0_data2",
4891 	"qspi0_data4",
4892 };
4893 
4894 static const char * const qspi1_groups[] = {
4895 	"qspi1_ctrl",
4896 	"qspi1_data2",
4897 	"qspi1_data4",
4898 };
4899 
4900 static const char * const scif0_groups[] = {
4901 	"scif0_data",
4902 	"scif0_clk",
4903 	"scif0_ctrl",
4904 };
4905 
4906 static const char * const scif1_groups[] = {
4907 	"scif1_data_a",
4908 	"scif1_clk",
4909 	"scif1_ctrl",
4910 	"scif1_data_b",
4911 };
4912 
4913 static const char * const scif2_groups[] = {
4914 	"scif2_data_a",
4915 	"scif2_clk",
4916 	"scif2_data_b",
4917 };
4918 
4919 static const char * const scif3_groups[] = {
4920 	"scif3_data_a",
4921 	"scif3_clk",
4922 	"scif3_ctrl",
4923 	"scif3_data_b",
4924 };
4925 
4926 static const char * const scif4_groups[] = {
4927 	"scif4_data_a",
4928 	"scif4_clk_a",
4929 	"scif4_ctrl_a",
4930 	"scif4_data_b",
4931 	"scif4_clk_b",
4932 	"scif4_ctrl_b",
4933 	"scif4_data_c",
4934 	"scif4_clk_c",
4935 	"scif4_ctrl_c",
4936 };
4937 
4938 static const char * const scif5_groups[] = {
4939 	"scif5_data_a",
4940 	"scif5_clk_a",
4941 	"scif5_data_b",
4942 	"scif5_clk_b",
4943 };
4944 
4945 static const char * const scif_clk_groups[] = {
4946 	"scif_clk_a",
4947 	"scif_clk_b",
4948 };
4949 
4950 static const char * const sdhi0_groups[] = {
4951 	"sdhi0_data1",
4952 	"sdhi0_data4",
4953 	"sdhi0_ctrl",
4954 	"sdhi0_cd",
4955 	"sdhi0_wp",
4956 };
4957 
4958 static const char * const sdhi1_groups[] = {
4959 	"sdhi1_data1",
4960 	"sdhi1_data4",
4961 	"sdhi1_ctrl",
4962 	"sdhi1_cd",
4963 	"sdhi1_wp",
4964 };
4965 
4966 static const char * const sdhi2_groups[] = {
4967 	"sdhi2_data1",
4968 	"sdhi2_data4",
4969 	"sdhi2_data8",
4970 	"sdhi2_ctrl",
4971 	"sdhi2_cd_a",
4972 	"sdhi2_wp_a",
4973 	"sdhi2_cd_b",
4974 	"sdhi2_wp_b",
4975 	"sdhi2_ds",
4976 };
4977 
4978 static const char * const sdhi3_groups[] = {
4979 	"sdhi3_data1",
4980 	"sdhi3_data4",
4981 	"sdhi3_data8",
4982 	"sdhi3_ctrl",
4983 	"sdhi3_cd",
4984 	"sdhi3_wp",
4985 	"sdhi3_ds",
4986 };
4987 
4988 static const char * const ssi_groups[] = {
4989 	"ssi0_data",
4990 	"ssi01239_ctrl",
4991 	"ssi1_data_a",
4992 	"ssi1_data_b",
4993 	"ssi1_ctrl_a",
4994 	"ssi1_ctrl_b",
4995 	"ssi2_data_a",
4996 	"ssi2_data_b",
4997 	"ssi2_ctrl_a",
4998 	"ssi2_ctrl_b",
4999 	"ssi3_data",
5000 	"ssi349_ctrl",
5001 	"ssi4_data",
5002 	"ssi4_ctrl",
5003 	"ssi5_data",
5004 	"ssi5_ctrl",
5005 	"ssi6_data",
5006 	"ssi6_ctrl",
5007 	"ssi7_data",
5008 	"ssi78_ctrl",
5009 	"ssi8_data",
5010 	"ssi9_data_a",
5011 	"ssi9_data_b",
5012 	"ssi9_ctrl_a",
5013 	"ssi9_ctrl_b",
5014 };
5015 
5016 static const char * const tmu_groups[] = {
5017 	"tmu_tclk1_a",
5018 	"tmu_tclk1_b",
5019 	"tmu_tclk2_a",
5020 	"tmu_tclk2_b",
5021 };
5022 
5023 static const char * const tpu_groups[] = {
5024 	"tpu_to0",
5025 	"tpu_to1",
5026 	"tpu_to2",
5027 	"tpu_to3",
5028 };
5029 
5030 static const char * const usb0_groups[] = {
5031 	"usb0",
5032 };
5033 
5034 static const char * const usb1_groups[] = {
5035 	"usb1",
5036 };
5037 
5038 static const char * const usb30_groups[] = {
5039 	"usb30",
5040 };
5041 
5042 static const char * const vin4_groups[] = {
5043 	"vin4_data8_a",
5044 	"vin4_data10_a",
5045 	"vin4_data12_a",
5046 	"vin4_data16_a",
5047 	"vin4_data18_a",
5048 	"vin4_data20_a",
5049 	"vin4_data24_a",
5050 	"vin4_data8_b",
5051 	"vin4_data10_b",
5052 	"vin4_data12_b",
5053 	"vin4_data16_b",
5054 	"vin4_data18_b",
5055 	"vin4_data20_b",
5056 	"vin4_data24_b",
5057 	"vin4_sync",
5058 	"vin4_field",
5059 	"vin4_clkenb",
5060 	"vin4_clk",
5061 };
5062 
5063 static const char * const vin5_groups[] = {
5064 	"vin5_data8",
5065 	"vin5_data10",
5066 	"vin5_data12",
5067 	"vin5_data16",
5068 	"vin5_sync",
5069 	"vin5_field",
5070 	"vin5_clkenb",
5071 	"vin5_clk",
5072 };
5073 
5074 static const struct {
5075 	struct sh_pfc_function common[52];
5076 #if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
5077 	struct sh_pfc_function automotive[4];
5078 #endif
5079 } pinmux_functions = {
5080 	.common = {
5081 		SH_PFC_FUNCTION(audio_clk),
5082 		SH_PFC_FUNCTION(avb),
5083 		SH_PFC_FUNCTION(can0),
5084 		SH_PFC_FUNCTION(can1),
5085 		SH_PFC_FUNCTION(can_clk),
5086 		SH_PFC_FUNCTION(canfd0),
5087 		SH_PFC_FUNCTION(canfd1),
5088 		SH_PFC_FUNCTION(du),
5089 		SH_PFC_FUNCTION(hscif0),
5090 		SH_PFC_FUNCTION(hscif1),
5091 		SH_PFC_FUNCTION(hscif2),
5092 		SH_PFC_FUNCTION(hscif3),
5093 		SH_PFC_FUNCTION(hscif4),
5094 		SH_PFC_FUNCTION(i2c0),
5095 		SH_PFC_FUNCTION(i2c1),
5096 		SH_PFC_FUNCTION(i2c2),
5097 		SH_PFC_FUNCTION(i2c3),
5098 		SH_PFC_FUNCTION(i2c5),
5099 		SH_PFC_FUNCTION(i2c6),
5100 		SH_PFC_FUNCTION(intc_ex),
5101 		SH_PFC_FUNCTION(msiof0),
5102 		SH_PFC_FUNCTION(msiof1),
5103 		SH_PFC_FUNCTION(msiof2),
5104 		SH_PFC_FUNCTION(msiof3),
5105 		SH_PFC_FUNCTION(pwm0),
5106 		SH_PFC_FUNCTION(pwm1),
5107 		SH_PFC_FUNCTION(pwm2),
5108 		SH_PFC_FUNCTION(pwm3),
5109 		SH_PFC_FUNCTION(pwm4),
5110 		SH_PFC_FUNCTION(pwm5),
5111 		SH_PFC_FUNCTION(pwm6),
5112 		SH_PFC_FUNCTION(qspi0),
5113 		SH_PFC_FUNCTION(qspi1),
5114 		SH_PFC_FUNCTION(scif0),
5115 		SH_PFC_FUNCTION(scif1),
5116 		SH_PFC_FUNCTION(scif2),
5117 		SH_PFC_FUNCTION(scif3),
5118 		SH_PFC_FUNCTION(scif4),
5119 		SH_PFC_FUNCTION(scif5),
5120 		SH_PFC_FUNCTION(scif_clk),
5121 		SH_PFC_FUNCTION(sdhi0),
5122 		SH_PFC_FUNCTION(sdhi1),
5123 		SH_PFC_FUNCTION(sdhi2),
5124 		SH_PFC_FUNCTION(sdhi3),
5125 		SH_PFC_FUNCTION(ssi),
5126 		SH_PFC_FUNCTION(tmu),
5127 		SH_PFC_FUNCTION(tpu),
5128 		SH_PFC_FUNCTION(usb0),
5129 		SH_PFC_FUNCTION(usb1),
5130 		SH_PFC_FUNCTION(usb30),
5131 		SH_PFC_FUNCTION(vin4),
5132 		SH_PFC_FUNCTION(vin5),
5133 	},
5134 #if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
5135 	.automotive = {
5136 		SH_PFC_FUNCTION(drif0),
5137 		SH_PFC_FUNCTION(drif1),
5138 		SH_PFC_FUNCTION(drif2),
5139 		SH_PFC_FUNCTION(drif3),
5140 	}
5141 #endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */
5142 };
5143 
5144 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5145 #define F_(x, y)	FN_##y
5146 #define FM(x)		FN_##x
5147 	{ PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
5148 		0, 0,
5149 		0, 0,
5150 		0, 0,
5151 		0, 0,
5152 		0, 0,
5153 		0, 0,
5154 		0, 0,
5155 		0, 0,
5156 		0, 0,
5157 		0, 0,
5158 		0, 0,
5159 		0, 0,
5160 		0, 0,
5161 		0, 0,
5162 		0, 0,
5163 		0, 0,
5164 		GP_0_15_FN,	GPSR0_15,
5165 		GP_0_14_FN,	GPSR0_14,
5166 		GP_0_13_FN,	GPSR0_13,
5167 		GP_0_12_FN,	GPSR0_12,
5168 		GP_0_11_FN,	GPSR0_11,
5169 		GP_0_10_FN,	GPSR0_10,
5170 		GP_0_9_FN,	GPSR0_9,
5171 		GP_0_8_FN,	GPSR0_8,
5172 		GP_0_7_FN,	GPSR0_7,
5173 		GP_0_6_FN,	GPSR0_6,
5174 		GP_0_5_FN,	GPSR0_5,
5175 		GP_0_4_FN,	GPSR0_4,
5176 		GP_0_3_FN,	GPSR0_3,
5177 		GP_0_2_FN,	GPSR0_2,
5178 		GP_0_1_FN,	GPSR0_1,
5179 		GP_0_0_FN,	GPSR0_0, ))
5180 	},
5181 	{ PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
5182 		0, 0,
5183 		0, 0,
5184 		0, 0,
5185 		GP_1_28_FN,	GPSR1_28,
5186 		GP_1_27_FN,	GPSR1_27,
5187 		GP_1_26_FN,	GPSR1_26,
5188 		GP_1_25_FN,	GPSR1_25,
5189 		GP_1_24_FN,	GPSR1_24,
5190 		GP_1_23_FN,	GPSR1_23,
5191 		GP_1_22_FN,	GPSR1_22,
5192 		GP_1_21_FN,	GPSR1_21,
5193 		GP_1_20_FN,	GPSR1_20,
5194 		GP_1_19_FN,	GPSR1_19,
5195 		GP_1_18_FN,	GPSR1_18,
5196 		GP_1_17_FN,	GPSR1_17,
5197 		GP_1_16_FN,	GPSR1_16,
5198 		GP_1_15_FN,	GPSR1_15,
5199 		GP_1_14_FN,	GPSR1_14,
5200 		GP_1_13_FN,	GPSR1_13,
5201 		GP_1_12_FN,	GPSR1_12,
5202 		GP_1_11_FN,	GPSR1_11,
5203 		GP_1_10_FN,	GPSR1_10,
5204 		GP_1_9_FN,	GPSR1_9,
5205 		GP_1_8_FN,	GPSR1_8,
5206 		GP_1_7_FN,	GPSR1_7,
5207 		GP_1_6_FN,	GPSR1_6,
5208 		GP_1_5_FN,	GPSR1_5,
5209 		GP_1_4_FN,	GPSR1_4,
5210 		GP_1_3_FN,	GPSR1_3,
5211 		GP_1_2_FN,	GPSR1_2,
5212 		GP_1_1_FN,	GPSR1_1,
5213 		GP_1_0_FN,	GPSR1_0, ))
5214 	},
5215 	{ PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
5216 		0, 0,
5217 		0, 0,
5218 		0, 0,
5219 		0, 0,
5220 		0, 0,
5221 		0, 0,
5222 		0, 0,
5223 		0, 0,
5224 		0, 0,
5225 		0, 0,
5226 		0, 0,
5227 		0, 0,
5228 		0, 0,
5229 		0, 0,
5230 		0, 0,
5231 		0, 0,
5232 		0, 0,
5233 		GP_2_14_FN,	GPSR2_14,
5234 		GP_2_13_FN,	GPSR2_13,
5235 		GP_2_12_FN,	GPSR2_12,
5236 		GP_2_11_FN,	GPSR2_11,
5237 		GP_2_10_FN,	GPSR2_10,
5238 		GP_2_9_FN,	GPSR2_9,
5239 		GP_2_8_FN,	GPSR2_8,
5240 		GP_2_7_FN,	GPSR2_7,
5241 		GP_2_6_FN,	GPSR2_6,
5242 		GP_2_5_FN,	GPSR2_5,
5243 		GP_2_4_FN,	GPSR2_4,
5244 		GP_2_3_FN,	GPSR2_3,
5245 		GP_2_2_FN,	GPSR2_2,
5246 		GP_2_1_FN,	GPSR2_1,
5247 		GP_2_0_FN,	GPSR2_0, ))
5248 	},
5249 	{ PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
5250 		0, 0,
5251 		0, 0,
5252 		0, 0,
5253 		0, 0,
5254 		0, 0,
5255 		0, 0,
5256 		0, 0,
5257 		0, 0,
5258 		0, 0,
5259 		0, 0,
5260 		0, 0,
5261 		0, 0,
5262 		0, 0,
5263 		0, 0,
5264 		0, 0,
5265 		0, 0,
5266 		GP_3_15_FN,	GPSR3_15,
5267 		GP_3_14_FN,	GPSR3_14,
5268 		GP_3_13_FN,	GPSR3_13,
5269 		GP_3_12_FN,	GPSR3_12,
5270 		GP_3_11_FN,	GPSR3_11,
5271 		GP_3_10_FN,	GPSR3_10,
5272 		GP_3_9_FN,	GPSR3_9,
5273 		GP_3_8_FN,	GPSR3_8,
5274 		GP_3_7_FN,	GPSR3_7,
5275 		GP_3_6_FN,	GPSR3_6,
5276 		GP_3_5_FN,	GPSR3_5,
5277 		GP_3_4_FN,	GPSR3_4,
5278 		GP_3_3_FN,	GPSR3_3,
5279 		GP_3_2_FN,	GPSR3_2,
5280 		GP_3_1_FN,	GPSR3_1,
5281 		GP_3_0_FN,	GPSR3_0, ))
5282 	},
5283 	{ PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
5284 		0, 0,
5285 		0, 0,
5286 		0, 0,
5287 		0, 0,
5288 		0, 0,
5289 		0, 0,
5290 		0, 0,
5291 		0, 0,
5292 		0, 0,
5293 		0, 0,
5294 		0, 0,
5295 		0, 0,
5296 		0, 0,
5297 		0, 0,
5298 		GP_4_17_FN,	GPSR4_17,
5299 		GP_4_16_FN,	GPSR4_16,
5300 		GP_4_15_FN,	GPSR4_15,
5301 		GP_4_14_FN,	GPSR4_14,
5302 		GP_4_13_FN,	GPSR4_13,
5303 		GP_4_12_FN,	GPSR4_12,
5304 		GP_4_11_FN,	GPSR4_11,
5305 		GP_4_10_FN,	GPSR4_10,
5306 		GP_4_9_FN,	GPSR4_9,
5307 		GP_4_8_FN,	GPSR4_8,
5308 		GP_4_7_FN,	GPSR4_7,
5309 		GP_4_6_FN,	GPSR4_6,
5310 		GP_4_5_FN,	GPSR4_5,
5311 		GP_4_4_FN,	GPSR4_4,
5312 		GP_4_3_FN,	GPSR4_3,
5313 		GP_4_2_FN,	GPSR4_2,
5314 		GP_4_1_FN,	GPSR4_1,
5315 		GP_4_0_FN,	GPSR4_0, ))
5316 	},
5317 	{ PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
5318 		0, 0,
5319 		0, 0,
5320 		0, 0,
5321 		0, 0,
5322 		0, 0,
5323 		0, 0,
5324 		GP_5_25_FN,	GPSR5_25,
5325 		GP_5_24_FN,	GPSR5_24,
5326 		GP_5_23_FN,	GPSR5_23,
5327 		GP_5_22_FN,	GPSR5_22,
5328 		GP_5_21_FN,	GPSR5_21,
5329 		GP_5_20_FN,	GPSR5_20,
5330 		GP_5_19_FN,	GPSR5_19,
5331 		GP_5_18_FN,	GPSR5_18,
5332 		GP_5_17_FN,	GPSR5_17,
5333 		GP_5_16_FN,	GPSR5_16,
5334 		GP_5_15_FN,	GPSR5_15,
5335 		GP_5_14_FN,	GPSR5_14,
5336 		GP_5_13_FN,	GPSR5_13,
5337 		GP_5_12_FN,	GPSR5_12,
5338 		GP_5_11_FN,	GPSR5_11,
5339 		GP_5_10_FN,	GPSR5_10,
5340 		GP_5_9_FN,	GPSR5_9,
5341 		GP_5_8_FN,	GPSR5_8,
5342 		GP_5_7_FN,	GPSR5_7,
5343 		GP_5_6_FN,	GPSR5_6,
5344 		GP_5_5_FN,	GPSR5_5,
5345 		GP_5_4_FN,	GPSR5_4,
5346 		GP_5_3_FN,	GPSR5_3,
5347 		GP_5_2_FN,	GPSR5_2,
5348 		GP_5_1_FN,	GPSR5_1,
5349 		GP_5_0_FN,	GPSR5_0, ))
5350 	},
5351 	{ PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP(
5352 		GP_6_31_FN,	GPSR6_31,
5353 		GP_6_30_FN,	GPSR6_30,
5354 		GP_6_29_FN,	GPSR6_29,
5355 		GP_6_28_FN,	GPSR6_28,
5356 		GP_6_27_FN,	GPSR6_27,
5357 		GP_6_26_FN,	GPSR6_26,
5358 		GP_6_25_FN,	GPSR6_25,
5359 		GP_6_24_FN,	GPSR6_24,
5360 		GP_6_23_FN,	GPSR6_23,
5361 		GP_6_22_FN,	GPSR6_22,
5362 		GP_6_21_FN,	GPSR6_21,
5363 		GP_6_20_FN,	GPSR6_20,
5364 		GP_6_19_FN,	GPSR6_19,
5365 		GP_6_18_FN,	GPSR6_18,
5366 		GP_6_17_FN,	GPSR6_17,
5367 		GP_6_16_FN,	GPSR6_16,
5368 		GP_6_15_FN,	GPSR6_15,
5369 		GP_6_14_FN,	GPSR6_14,
5370 		GP_6_13_FN,	GPSR6_13,
5371 		GP_6_12_FN,	GPSR6_12,
5372 		GP_6_11_FN,	GPSR6_11,
5373 		GP_6_10_FN,	GPSR6_10,
5374 		GP_6_9_FN,	GPSR6_9,
5375 		GP_6_8_FN,	GPSR6_8,
5376 		GP_6_7_FN,	GPSR6_7,
5377 		GP_6_6_FN,	GPSR6_6,
5378 		GP_6_5_FN,	GPSR6_5,
5379 		GP_6_4_FN,	GPSR6_4,
5380 		GP_6_3_FN,	GPSR6_3,
5381 		GP_6_2_FN,	GPSR6_2,
5382 		GP_6_1_FN,	GPSR6_1,
5383 		GP_6_0_FN,	GPSR6_0, ))
5384 	},
5385 	{ PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1, GROUP(
5386 		0, 0,
5387 		0, 0,
5388 		0, 0,
5389 		0, 0,
5390 		0, 0,
5391 		0, 0,
5392 		0, 0,
5393 		0, 0,
5394 		0, 0,
5395 		0, 0,
5396 		0, 0,
5397 		0, 0,
5398 		0, 0,
5399 		0, 0,
5400 		0, 0,
5401 		0, 0,
5402 		0, 0,
5403 		0, 0,
5404 		0, 0,
5405 		0, 0,
5406 		0, 0,
5407 		0, 0,
5408 		0, 0,
5409 		0, 0,
5410 		0, 0,
5411 		0, 0,
5412 		0, 0,
5413 		0, 0,
5414 		GP_7_3_FN, GPSR7_3,
5415 		GP_7_2_FN, GPSR7_2,
5416 		GP_7_1_FN, GPSR7_1,
5417 		GP_7_0_FN, GPSR7_0, ))
5418 	},
5419 #undef F_
5420 #undef FM
5421 
5422 #define F_(x, y)	x,
5423 #define FM(x)		FN_##x,
5424 	{ PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
5425 		IP0_31_28
5426 		IP0_27_24
5427 		IP0_23_20
5428 		IP0_19_16
5429 		IP0_15_12
5430 		IP0_11_8
5431 		IP0_7_4
5432 		IP0_3_0 ))
5433 	},
5434 	{ PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
5435 		IP1_31_28
5436 		IP1_27_24
5437 		IP1_23_20
5438 		IP1_19_16
5439 		IP1_15_12
5440 		IP1_11_8
5441 		IP1_7_4
5442 		IP1_3_0 ))
5443 	},
5444 	{ PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
5445 		IP2_31_28
5446 		IP2_27_24
5447 		IP2_23_20
5448 		IP2_19_16
5449 		IP2_15_12
5450 		IP2_11_8
5451 		IP2_7_4
5452 		IP2_3_0 ))
5453 	},
5454 	{ PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
5455 		IP3_31_28
5456 		IP3_27_24
5457 		IP3_23_20
5458 		IP3_19_16
5459 		IP3_15_12
5460 		IP3_11_8
5461 		IP3_7_4
5462 		IP3_3_0 ))
5463 	},
5464 	{ PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
5465 		IP4_31_28
5466 		IP4_27_24
5467 		IP4_23_20
5468 		IP4_19_16
5469 		IP4_15_12
5470 		IP4_11_8
5471 		IP4_7_4
5472 		IP4_3_0 ))
5473 	},
5474 	{ PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
5475 		IP5_31_28
5476 		IP5_27_24
5477 		IP5_23_20
5478 		IP5_19_16
5479 		IP5_15_12
5480 		IP5_11_8
5481 		IP5_7_4
5482 		IP5_3_0 ))
5483 	},
5484 	{ PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
5485 		IP6_31_28
5486 		IP6_27_24
5487 		IP6_23_20
5488 		IP6_19_16
5489 		IP6_15_12
5490 		IP6_11_8
5491 		IP6_7_4
5492 		IP6_3_0 ))
5493 	},
5494 	{ PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
5495 		IP7_31_28
5496 		IP7_27_24
5497 		IP7_23_20
5498 		IP7_19_16
5499 		/* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5500 		IP7_11_8
5501 		IP7_7_4
5502 		IP7_3_0 ))
5503 	},
5504 	{ PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
5505 		IP8_31_28
5506 		IP8_27_24
5507 		IP8_23_20
5508 		IP8_19_16
5509 		IP8_15_12
5510 		IP8_11_8
5511 		IP8_7_4
5512 		IP8_3_0 ))
5513 	},
5514 	{ PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
5515 		IP9_31_28
5516 		IP9_27_24
5517 		IP9_23_20
5518 		IP9_19_16
5519 		IP9_15_12
5520 		IP9_11_8
5521 		IP9_7_4
5522 		IP9_3_0 ))
5523 	},
5524 	{ PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
5525 		IP10_31_28
5526 		IP10_27_24
5527 		IP10_23_20
5528 		IP10_19_16
5529 		IP10_15_12
5530 		IP10_11_8
5531 		IP10_7_4
5532 		IP10_3_0 ))
5533 	},
5534 	{ PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP(
5535 		IP11_31_28
5536 		IP11_27_24
5537 		IP11_23_20
5538 		IP11_19_16
5539 		IP11_15_12
5540 		IP11_11_8
5541 		IP11_7_4
5542 		IP11_3_0 ))
5543 	},
5544 	{ PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP(
5545 		IP12_31_28
5546 		IP12_27_24
5547 		IP12_23_20
5548 		IP12_19_16
5549 		IP12_15_12
5550 		IP12_11_8
5551 		IP12_7_4
5552 		IP12_3_0 ))
5553 	},
5554 	{ PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP(
5555 		IP13_31_28
5556 		IP13_27_24
5557 		IP13_23_20
5558 		IP13_19_16
5559 		IP13_15_12
5560 		IP13_11_8
5561 		IP13_7_4
5562 		IP13_3_0 ))
5563 	},
5564 	{ PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP(
5565 		IP14_31_28
5566 		IP14_27_24
5567 		IP14_23_20
5568 		IP14_19_16
5569 		IP14_15_12
5570 		IP14_11_8
5571 		IP14_7_4
5572 		IP14_3_0 ))
5573 	},
5574 	{ PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP(
5575 		IP15_31_28
5576 		IP15_27_24
5577 		IP15_23_20
5578 		IP15_19_16
5579 		IP15_15_12
5580 		IP15_11_8
5581 		IP15_7_4
5582 		IP15_3_0 ))
5583 	},
5584 	{ PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4, GROUP(
5585 		IP16_31_28
5586 		IP16_27_24
5587 		IP16_23_20
5588 		IP16_19_16
5589 		IP16_15_12
5590 		IP16_11_8
5591 		IP16_7_4
5592 		IP16_3_0 ))
5593 	},
5594 	{ PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4, GROUP(
5595 		IP17_31_28
5596 		IP17_27_24
5597 		IP17_23_20
5598 		IP17_19_16
5599 		IP17_15_12
5600 		IP17_11_8
5601 		IP17_7_4
5602 		IP17_3_0 ))
5603 	},
5604 	{ PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4, GROUP(
5605 		/* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5606 		/* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5607 		/* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5608 		/* IP18_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5609 		/* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5610 		/* IP18_11_8  */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5611 		IP18_7_4
5612 		IP18_3_0 ))
5613 	},
5614 #undef F_
5615 #undef FM
5616 
5617 #define F_(x, y)	x,
5618 #define FM(x)		FN_##x,
5619 	{ PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
5620 			     GROUP(3, 2, 3, 1, 1, 1, 1, 1, 2, 1, 1, 2,
5621 				   1, 1, 1, 2, 2, 1, 2, 3),
5622 			     GROUP(
5623 		MOD_SEL0_31_30_29
5624 		MOD_SEL0_28_27
5625 		MOD_SEL0_26_25_24
5626 		MOD_SEL0_23
5627 		MOD_SEL0_22
5628 		MOD_SEL0_21
5629 		MOD_SEL0_20
5630 		MOD_SEL0_19
5631 		MOD_SEL0_18_17
5632 		MOD_SEL0_16
5633 		0, 0, /* RESERVED 15 */
5634 		MOD_SEL0_14_13
5635 		MOD_SEL0_12
5636 		MOD_SEL0_11
5637 		MOD_SEL0_10
5638 		MOD_SEL0_9_8
5639 		MOD_SEL0_7_6
5640 		MOD_SEL0_5
5641 		MOD_SEL0_4_3
5642 		/* RESERVED 2, 1, 0 */
5643 		0, 0, 0, 0, 0, 0, 0, 0 ))
5644 	},
5645 	{ PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
5646 			     GROUP(2, 3, 1, 2, 3, 1, 1, 2, 1, 2, 1, 1,
5647 				   1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1),
5648 			     GROUP(
5649 		MOD_SEL1_31_30
5650 		MOD_SEL1_29_28_27
5651 		MOD_SEL1_26
5652 		MOD_SEL1_25_24
5653 		MOD_SEL1_23_22_21
5654 		MOD_SEL1_20
5655 		MOD_SEL1_19
5656 		MOD_SEL1_18_17
5657 		MOD_SEL1_16
5658 		MOD_SEL1_15_14
5659 		MOD_SEL1_13
5660 		MOD_SEL1_12
5661 		MOD_SEL1_11
5662 		MOD_SEL1_10
5663 		MOD_SEL1_9
5664 		0, 0, 0, 0, /* RESERVED 8, 7 */
5665 		MOD_SEL1_6
5666 		MOD_SEL1_5
5667 		MOD_SEL1_4
5668 		MOD_SEL1_3
5669 		MOD_SEL1_2
5670 		MOD_SEL1_1
5671 		MOD_SEL1_0 ))
5672 	},
5673 	{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
5674 			     GROUP(1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1,
5675 				   1, 4, 4, 4, 3, 1),
5676 			     GROUP(
5677 		MOD_SEL2_31
5678 		MOD_SEL2_30
5679 		MOD_SEL2_29
5680 		MOD_SEL2_28_27
5681 		MOD_SEL2_26
5682 		MOD_SEL2_25_24_23
5683 		MOD_SEL2_22
5684 		MOD_SEL2_21
5685 		MOD_SEL2_20
5686 		MOD_SEL2_19
5687 		MOD_SEL2_18
5688 		MOD_SEL2_17
5689 		/* RESERVED 16 */
5690 		0, 0,
5691 		/* RESERVED 15, 14, 13, 12 */
5692 		0, 0, 0, 0, 0, 0, 0, 0,
5693 		0, 0, 0, 0, 0, 0, 0, 0,
5694 		/* RESERVED 11, 10, 9, 8 */
5695 		0, 0, 0, 0, 0, 0, 0, 0,
5696 		0, 0, 0, 0, 0, 0, 0, 0,
5697 		/* RESERVED 7, 6, 5, 4 */
5698 		0, 0, 0, 0, 0, 0, 0, 0,
5699 		0, 0, 0, 0, 0, 0, 0, 0,
5700 		/* RESERVED 3, 2, 1 */
5701 		0, 0, 0, 0, 0, 0, 0, 0,
5702 		MOD_SEL2_0 ))
5703 	},
5704 	{ },
5705 };
5706 
5707 static const struct pinmux_drive_reg pinmux_drive_regs[] = {
5708 	{ PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
5709 		{ PIN_QSPI0_SPCLK,    28, 2 },	/* QSPI0_SPCLK */
5710 		{ PIN_QSPI0_MOSI_IO0, 24, 2 },	/* QSPI0_MOSI_IO0 */
5711 		{ PIN_QSPI0_MISO_IO1, 20, 2 },	/* QSPI0_MISO_IO1 */
5712 		{ PIN_QSPI0_IO2,      16, 2 },	/* QSPI0_IO2 */
5713 		{ PIN_QSPI0_IO3,      12, 2 },	/* QSPI0_IO3 */
5714 		{ PIN_QSPI0_SSL,       8, 2 },	/* QSPI0_SSL */
5715 		{ PIN_QSPI1_SPCLK,     4, 2 },	/* QSPI1_SPCLK */
5716 		{ PIN_QSPI1_MOSI_IO0,  0, 2 },	/* QSPI1_MOSI_IO0 */
5717 	} },
5718 	{ PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
5719 		{ PIN_QSPI1_MISO_IO1, 28, 2 },	/* QSPI1_MISO_IO1 */
5720 		{ PIN_QSPI1_IO2,      24, 2 },	/* QSPI1_IO2 */
5721 		{ PIN_QSPI1_IO3,      20, 2 },	/* QSPI1_IO3 */
5722 		{ PIN_QSPI1_SSL,      16, 2 },	/* QSPI1_SSL */
5723 		{ PIN_RPC_INT_N,      12, 2 },	/* RPC_INT# */
5724 		{ PIN_RPC_WP_N,        8, 2 },	/* RPC_WP# */
5725 		{ PIN_RPC_RESET_N,     4, 2 },	/* RPC_RESET# */
5726 		{ PIN_AVB_RX_CTL,      0, 3 },	/* AVB_RX_CTL */
5727 	} },
5728 	{ PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
5729 		{ PIN_AVB_RXC,        28, 3 },	/* AVB_RXC */
5730 		{ PIN_AVB_RD0,        24, 3 },	/* AVB_RD0 */
5731 		{ PIN_AVB_RD1,        20, 3 },	/* AVB_RD1 */
5732 		{ PIN_AVB_RD2,        16, 3 },	/* AVB_RD2 */
5733 		{ PIN_AVB_RD3,        12, 3 },	/* AVB_RD3 */
5734 		{ PIN_AVB_TX_CTL,      8, 3 },	/* AVB_TX_CTL */
5735 		{ PIN_AVB_TXC,         4, 3 },	/* AVB_TXC */
5736 		{ PIN_AVB_TD0,         0, 3 },	/* AVB_TD0 */
5737 	} },
5738 	{ PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
5739 		{ PIN_AVB_TD1,        28, 3 },	/* AVB_TD1 */
5740 		{ PIN_AVB_TD2,        24, 3 },	/* AVB_TD2 */
5741 		{ PIN_AVB_TD3,        20, 3 },	/* AVB_TD3 */
5742 		{ PIN_AVB_TXCREFCLK,  16, 3 },	/* AVB_TXCREFCLK */
5743 		{ PIN_AVB_MDIO,       12, 3 },	/* AVB_MDIO */
5744 		{ RCAR_GP_PIN(2,  9),  8, 3 },	/* AVB_MDC */
5745 		{ RCAR_GP_PIN(2, 10),  4, 3 },	/* AVB_MAGIC */
5746 		{ RCAR_GP_PIN(2, 11),  0, 3 },	/* AVB_PHY_INT */
5747 	} },
5748 	{ PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
5749 		{ RCAR_GP_PIN(2, 12), 28, 3 },	/* AVB_LINK */
5750 		{ RCAR_GP_PIN(2, 13), 24, 3 },	/* AVB_AVTP_MATCH */
5751 		{ RCAR_GP_PIN(2, 14), 20, 3 },	/* AVB_AVTP_CAPTURE */
5752 		{ RCAR_GP_PIN(2,  0), 16, 3 },	/* IRQ0 */
5753 		{ RCAR_GP_PIN(2,  1), 12, 3 },	/* IRQ1 */
5754 		{ RCAR_GP_PIN(2,  2),  8, 3 },	/* IRQ2 */
5755 		{ RCAR_GP_PIN(2,  3),  4, 3 },	/* IRQ3 */
5756 		{ RCAR_GP_PIN(2,  4),  0, 3 },	/* IRQ4 */
5757 	} },
5758 	{ PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) {
5759 		{ RCAR_GP_PIN(2,  5), 28, 3 },	/* IRQ5 */
5760 		{ RCAR_GP_PIN(2,  6), 24, 3 },	/* PWM0 */
5761 		{ RCAR_GP_PIN(2,  7), 20, 3 },	/* PWM1 */
5762 		{ RCAR_GP_PIN(2,  8), 16, 3 },	/* PWM2 */
5763 		{ RCAR_GP_PIN(1,  0), 12, 3 },	/* A0 */
5764 		{ RCAR_GP_PIN(1,  1),  8, 3 },	/* A1 */
5765 		{ RCAR_GP_PIN(1,  2),  4, 3 },	/* A2 */
5766 		{ RCAR_GP_PIN(1,  3),  0, 3 },	/* A3 */
5767 	} },
5768 	{ PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) {
5769 		{ RCAR_GP_PIN(1,  4), 28, 3 },	/* A4 */
5770 		{ RCAR_GP_PIN(1,  5), 24, 3 },	/* A5 */
5771 		{ RCAR_GP_PIN(1,  6), 20, 3 },	/* A6 */
5772 		{ RCAR_GP_PIN(1,  7), 16, 3 },	/* A7 */
5773 		{ RCAR_GP_PIN(1,  8), 12, 3 },	/* A8 */
5774 		{ RCAR_GP_PIN(1,  9),  8, 3 },	/* A9 */
5775 		{ RCAR_GP_PIN(1, 10),  4, 3 },	/* A10 */
5776 		{ RCAR_GP_PIN(1, 11),  0, 3 },	/* A11 */
5777 	} },
5778 	{ PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) {
5779 		{ RCAR_GP_PIN(1, 12), 28, 3 },	/* A12 */
5780 		{ RCAR_GP_PIN(1, 13), 24, 3 },	/* A13 */
5781 		{ RCAR_GP_PIN(1, 14), 20, 3 },	/* A14 */
5782 		{ RCAR_GP_PIN(1, 15), 16, 3 },	/* A15 */
5783 		{ RCAR_GP_PIN(1, 16), 12, 3 },	/* A16 */
5784 		{ RCAR_GP_PIN(1, 17),  8, 3 },	/* A17 */
5785 		{ RCAR_GP_PIN(1, 18),  4, 3 },	/* A18 */
5786 		{ RCAR_GP_PIN(1, 19),  0, 3 },	/* A19 */
5787 	} },
5788 	{ PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
5789 		{ RCAR_GP_PIN(1, 28), 28, 3 },	/* CLKOUT */
5790 		{ RCAR_GP_PIN(1, 20), 24, 3 },	/* CS0 */
5791 		{ RCAR_GP_PIN(1, 21), 20, 3 },	/* CS1_A26 */
5792 		{ RCAR_GP_PIN(1, 22), 16, 3 },	/* BS */
5793 		{ RCAR_GP_PIN(1, 23), 12, 3 },	/* RD */
5794 		{ RCAR_GP_PIN(1, 24),  8, 3 },	/* RD_WR */
5795 		{ RCAR_GP_PIN(1, 25),  4, 3 },	/* WE0 */
5796 		{ RCAR_GP_PIN(1, 26),  0, 3 },	/* WE1 */
5797 	} },
5798 	{ PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
5799 		{ RCAR_GP_PIN(1, 27), 28, 3 },	/* EX_WAIT0 */
5800 		{ PIN_PRESETOUT_N,    24, 3 },	/* PRESETOUT# */
5801 		{ RCAR_GP_PIN(0,  0), 20, 3 },	/* D0 */
5802 		{ RCAR_GP_PIN(0,  1), 16, 3 },	/* D1 */
5803 		{ RCAR_GP_PIN(0,  2), 12, 3 },	/* D2 */
5804 		{ RCAR_GP_PIN(0,  3),  8, 3 },	/* D3 */
5805 		{ RCAR_GP_PIN(0,  4),  4, 3 },	/* D4 */
5806 		{ RCAR_GP_PIN(0,  5),  0, 3 },	/* D5 */
5807 	} },
5808 	{ PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
5809 		{ RCAR_GP_PIN(0,  6), 28, 3 },	/* D6 */
5810 		{ RCAR_GP_PIN(0,  7), 24, 3 },	/* D7 */
5811 		{ RCAR_GP_PIN(0,  8), 20, 3 },	/* D8 */
5812 		{ RCAR_GP_PIN(0,  9), 16, 3 },	/* D9 */
5813 		{ RCAR_GP_PIN(0, 10), 12, 3 },	/* D10 */
5814 		{ RCAR_GP_PIN(0, 11),  8, 3 },	/* D11 */
5815 		{ RCAR_GP_PIN(0, 12),  4, 3 },	/* D12 */
5816 		{ RCAR_GP_PIN(0, 13),  0, 3 },	/* D13 */
5817 	} },
5818 	{ PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
5819 		{ RCAR_GP_PIN(0, 14), 28, 3 },	/* D14 */
5820 		{ RCAR_GP_PIN(0, 15), 24, 3 },	/* D15 */
5821 		{ RCAR_GP_PIN(7,  0), 20, 3 },	/* AVS1 */
5822 		{ RCAR_GP_PIN(7,  1), 16, 3 },	/* AVS2 */
5823 		{ RCAR_GP_PIN(7,  2), 12, 3 },	/* GP7_02 */
5824 		{ RCAR_GP_PIN(7,  3),  8, 3 },	/* GP7_03 */
5825 		{ PIN_DU_DOTCLKIN0,    4, 2 },	/* DU_DOTCLKIN0 */
5826 		{ PIN_DU_DOTCLKIN1,    0, 2 },	/* DU_DOTCLKIN1 */
5827 	} },
5828 	{ PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
5829 		{ PIN_DU_DOTCLKIN2,   28, 2 },	/* DU_DOTCLKIN2 */
5830 		{ PIN_FSCLKST,        20, 2 },	/* FSCLKST */
5831 		{ PIN_TMS,             4, 2 },	/* TMS */
5832 	} },
5833 	{ PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
5834 		{ PIN_TDO,            28, 2 },	/* TDO */
5835 		{ PIN_ASEBRK,         24, 2 },	/* ASEBRK */
5836 		{ RCAR_GP_PIN(3,  0), 20, 3 },	/* SD0_CLK */
5837 		{ RCAR_GP_PIN(3,  1), 16, 3 },	/* SD0_CMD */
5838 		{ RCAR_GP_PIN(3,  2), 12, 3 },	/* SD0_DAT0 */
5839 		{ RCAR_GP_PIN(3,  3),  8, 3 },	/* SD0_DAT1 */
5840 		{ RCAR_GP_PIN(3,  4),  4, 3 },	/* SD0_DAT2 */
5841 		{ RCAR_GP_PIN(3,  5),  0, 3 },	/* SD0_DAT3 */
5842 	} },
5843 	{ PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
5844 		{ RCAR_GP_PIN(3,  6), 28, 3 },	/* SD1_CLK */
5845 		{ RCAR_GP_PIN(3,  7), 24, 3 },	/* SD1_CMD */
5846 		{ RCAR_GP_PIN(3,  8), 20, 3 },	/* SD1_DAT0 */
5847 		{ RCAR_GP_PIN(3,  9), 16, 3 },	/* SD1_DAT1 */
5848 		{ RCAR_GP_PIN(3, 10), 12, 3 },	/* SD1_DAT2 */
5849 		{ RCAR_GP_PIN(3, 11),  8, 3 },	/* SD1_DAT3 */
5850 		{ RCAR_GP_PIN(4,  0),  4, 3 },	/* SD2_CLK */
5851 		{ RCAR_GP_PIN(4,  1),  0, 3 },	/* SD2_CMD */
5852 	} },
5853 	{ PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) {
5854 		{ RCAR_GP_PIN(4,  2), 28, 3 },	/* SD2_DAT0 */
5855 		{ RCAR_GP_PIN(4,  3), 24, 3 },	/* SD2_DAT1 */
5856 		{ RCAR_GP_PIN(4,  4), 20, 3 },	/* SD2_DAT2 */
5857 		{ RCAR_GP_PIN(4,  5), 16, 3 },	/* SD2_DAT3 */
5858 		{ RCAR_GP_PIN(4,  6), 12, 3 },	/* SD2_DS */
5859 		{ RCAR_GP_PIN(4,  7),  8, 3 },	/* SD3_CLK */
5860 		{ RCAR_GP_PIN(4,  8),  4, 3 },	/* SD3_CMD */
5861 		{ RCAR_GP_PIN(4,  9),  0, 3 },	/* SD3_DAT0 */
5862 	} },
5863 	{ PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) {
5864 		{ RCAR_GP_PIN(4, 10), 28, 3 },	/* SD3_DAT1 */
5865 		{ RCAR_GP_PIN(4, 11), 24, 3 },	/* SD3_DAT2 */
5866 		{ RCAR_GP_PIN(4, 12), 20, 3 },	/* SD3_DAT3 */
5867 		{ RCAR_GP_PIN(4, 13), 16, 3 },	/* SD3_DAT4 */
5868 		{ RCAR_GP_PIN(4, 14), 12, 3 },	/* SD3_DAT5 */
5869 		{ RCAR_GP_PIN(4, 15),  8, 3 },	/* SD3_DAT6 */
5870 		{ RCAR_GP_PIN(4, 16),  4, 3 },	/* SD3_DAT7 */
5871 		{ RCAR_GP_PIN(4, 17),  0, 3 },	/* SD3_DS */
5872 	} },
5873 	{ PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) {
5874 		{ RCAR_GP_PIN(3, 12), 28, 3 },	/* SD0_CD */
5875 		{ RCAR_GP_PIN(3, 13), 24, 3 },	/* SD0_WP */
5876 		{ RCAR_GP_PIN(3, 14), 20, 3 },	/* SD1_CD */
5877 		{ RCAR_GP_PIN(3, 15), 16, 3 },	/* SD1_WP */
5878 		{ RCAR_GP_PIN(5,  0), 12, 3 },	/* SCK0 */
5879 		{ RCAR_GP_PIN(5,  1),  8, 3 },	/* RX0 */
5880 		{ RCAR_GP_PIN(5,  2),  4, 3 },	/* TX0 */
5881 		{ RCAR_GP_PIN(5,  3),  0, 3 },	/* CTS0 */
5882 	} },
5883 	{ PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
5884 		{ RCAR_GP_PIN(5,  4), 28, 3 },	/* RTS0 */
5885 		{ RCAR_GP_PIN(5,  5), 24, 3 },	/* RX1 */
5886 		{ RCAR_GP_PIN(5,  6), 20, 3 },	/* TX1 */
5887 		{ RCAR_GP_PIN(5,  7), 16, 3 },	/* CTS1 */
5888 		{ RCAR_GP_PIN(5,  8), 12, 3 },	/* RTS1 */
5889 		{ RCAR_GP_PIN(5,  9),  8, 3 },	/* SCK2 */
5890 		{ RCAR_GP_PIN(5, 10),  4, 3 },	/* TX2 */
5891 		{ RCAR_GP_PIN(5, 11),  0, 3 },	/* RX2 */
5892 	} },
5893 	{ PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) {
5894 		{ RCAR_GP_PIN(5, 12), 28, 3 },	/* HSCK0 */
5895 		{ RCAR_GP_PIN(5, 13), 24, 3 },	/* HRX0 */
5896 		{ RCAR_GP_PIN(5, 14), 20, 3 },	/* HTX0 */
5897 		{ RCAR_GP_PIN(5, 15), 16, 3 },	/* HCTS0 */
5898 		{ RCAR_GP_PIN(5, 16), 12, 3 },	/* HRTS0 */
5899 		{ RCAR_GP_PIN(5, 17),  8, 3 },	/* MSIOF0_SCK */
5900 		{ RCAR_GP_PIN(5, 18),  4, 3 },	/* MSIOF0_SYNC */
5901 		{ RCAR_GP_PIN(5, 19),  0, 3 },	/* MSIOF0_SS1 */
5902 	} },
5903 	{ PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) {
5904 		{ RCAR_GP_PIN(5, 20), 28, 3 },	/* MSIOF0_TXD */
5905 		{ RCAR_GP_PIN(5, 21), 24, 3 },	/* MSIOF0_SS2 */
5906 		{ RCAR_GP_PIN(5, 22), 20, 3 },	/* MSIOF0_RXD */
5907 		{ RCAR_GP_PIN(5, 23), 16, 3 },	/* MLB_CLK */
5908 		{ RCAR_GP_PIN(5, 24), 12, 3 },	/* MLB_SIG */
5909 		{ RCAR_GP_PIN(5, 25),  8, 3 },	/* MLB_DAT */
5910 		{ PIN_MLB_REF,         4, 3 },	/* MLB_REF */
5911 		{ RCAR_GP_PIN(6,  0),  0, 3 },	/* SSI_SCK01239 */
5912 	} },
5913 	{ PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
5914 		{ RCAR_GP_PIN(6,  1), 28, 3 },	/* SSI_WS01239 */
5915 		{ RCAR_GP_PIN(6,  2), 24, 3 },	/* SSI_SDATA0 */
5916 		{ RCAR_GP_PIN(6,  3), 20, 3 },	/* SSI_SDATA1 */
5917 		{ RCAR_GP_PIN(6,  4), 16, 3 },	/* SSI_SDATA2 */
5918 		{ RCAR_GP_PIN(6,  5), 12, 3 },	/* SSI_SCK349 */
5919 		{ RCAR_GP_PIN(6,  6),  8, 3 },	/* SSI_WS349 */
5920 		{ RCAR_GP_PIN(6,  7),  4, 3 },	/* SSI_SDATA3 */
5921 		{ RCAR_GP_PIN(6,  8),  0, 3 },	/* SSI_SCK4 */
5922 	} },
5923 	{ PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) {
5924 		{ RCAR_GP_PIN(6,  9), 28, 3 },	/* SSI_WS4 */
5925 		{ RCAR_GP_PIN(6, 10), 24, 3 },	/* SSI_SDATA4 */
5926 		{ RCAR_GP_PIN(6, 11), 20, 3 },	/* SSI_SCK5 */
5927 		{ RCAR_GP_PIN(6, 12), 16, 3 },	/* SSI_WS5 */
5928 		{ RCAR_GP_PIN(6, 13), 12, 3 },	/* SSI_SDATA5 */
5929 		{ RCAR_GP_PIN(6, 14),  8, 3 },	/* SSI_SCK6 */
5930 		{ RCAR_GP_PIN(6, 15),  4, 3 },	/* SSI_WS6 */
5931 		{ RCAR_GP_PIN(6, 16),  0, 3 },	/* SSI_SDATA6 */
5932 	} },
5933 	{ PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) {
5934 		{ RCAR_GP_PIN(6, 17), 28, 3 },	/* SSI_SCK78 */
5935 		{ RCAR_GP_PIN(6, 18), 24, 3 },	/* SSI_WS78 */
5936 		{ RCAR_GP_PIN(6, 19), 20, 3 },	/* SSI_SDATA7 */
5937 		{ RCAR_GP_PIN(6, 20), 16, 3 },	/* SSI_SDATA8 */
5938 		{ RCAR_GP_PIN(6, 21), 12, 3 },	/* SSI_SDATA9 */
5939 		{ RCAR_GP_PIN(6, 22),  8, 3 },	/* AUDIO_CLKA */
5940 		{ RCAR_GP_PIN(6, 23),  4, 3 },	/* AUDIO_CLKB */
5941 		{ RCAR_GP_PIN(6, 24),  0, 3 },	/* USB0_PWEN */
5942 	} },
5943 	{ PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) {
5944 		{ RCAR_GP_PIN(6, 25), 28, 3 },	/* USB0_OVC */
5945 		{ RCAR_GP_PIN(6, 26), 24, 3 },	/* USB1_PWEN */
5946 		{ RCAR_GP_PIN(6, 27), 20, 3 },	/* USB1_OVC */
5947 		{ RCAR_GP_PIN(6, 28), 16, 3 },	/* USB30_PWEN */
5948 		{ RCAR_GP_PIN(6, 29), 12, 3 },	/* USB30_OVC */
5949 		{ RCAR_GP_PIN(6, 30),  8, 3 },	/* GP6_30 */
5950 		{ RCAR_GP_PIN(6, 31),  4, 3 },	/* GP6_31 */
5951 	} },
5952 	{ },
5953 };
5954 
5955 enum ioctrl_regs {
5956 	POCCTRL,
5957 	TDSELCTRL,
5958 };
5959 
5960 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
5961 	[POCCTRL] = { 0xe6060380, },
5962 	[TDSELCTRL] = { 0xe60603c0, },
5963 	{ /* sentinel */ },
5964 };
5965 
5966 static int r8a7796_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
5967 {
5968 	int bit = -EINVAL;
5969 
5970 	*pocctrl = pinmux_ioctrl_regs[POCCTRL].reg;
5971 
5972 	if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
5973 		bit = pin & 0x1f;
5974 
5975 	if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
5976 		bit = (pin & 0x1f) + 12;
5977 
5978 	return bit;
5979 }
5980 
5981 static const struct pinmux_bias_reg pinmux_bias_regs[] = {
5982 	{ PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
5983 		[ 0] = PIN_QSPI0_SPCLK,		/* QSPI0_SPCLK */
5984 		[ 1] = PIN_QSPI0_MOSI_IO0,	/* QSPI0_MOSI_IO0 */
5985 		[ 2] = PIN_QSPI0_MISO_IO1,	/* QSPI0_MISO_IO1 */
5986 		[ 3] = PIN_QSPI0_IO2,		/* QSPI0_IO2 */
5987 		[ 4] = PIN_QSPI0_IO3,		/* QSPI0_IO3 */
5988 		[ 5] = PIN_QSPI0_SSL,		/* QSPI0_SSL */
5989 		[ 6] = PIN_QSPI1_SPCLK,		/* QSPI1_SPCLK */
5990 		[ 7] = PIN_QSPI1_MOSI_IO0,	/* QSPI1_MOSI_IO0 */
5991 		[ 8] = PIN_QSPI1_MISO_IO1,	/* QSPI1_MISO_IO1 */
5992 		[ 9] = PIN_QSPI1_IO2,		/* QSPI1_IO2 */
5993 		[10] = PIN_QSPI1_IO3,		/* QSPI1_IO3 */
5994 		[11] = PIN_QSPI1_SSL,		/* QSPI1_SSL */
5995 		[12] = PIN_RPC_INT_N,		/* RPC_INT# */
5996 		[13] = PIN_RPC_WP_N,		/* RPC_WP# */
5997 		[14] = PIN_RPC_RESET_N,		/* RPC_RESET# */
5998 		[15] = PIN_AVB_RX_CTL,		/* AVB_RX_CTL */
5999 		[16] = PIN_AVB_RXC,		/* AVB_RXC */
6000 		[17] = PIN_AVB_RD0,		/* AVB_RD0 */
6001 		[18] = PIN_AVB_RD1,		/* AVB_RD1 */
6002 		[19] = PIN_AVB_RD2,		/* AVB_RD2 */
6003 		[20] = PIN_AVB_RD3,		/* AVB_RD3 */
6004 		[21] = PIN_AVB_TX_CTL,		/* AVB_TX_CTL */
6005 		[22] = PIN_AVB_TXC,		/* AVB_TXC */
6006 		[23] = PIN_AVB_TD0,		/* AVB_TD0 */
6007 		[24] = PIN_AVB_TD1,		/* AVB_TD1 */
6008 		[25] = PIN_AVB_TD2,		/* AVB_TD2 */
6009 		[26] = PIN_AVB_TD3,		/* AVB_TD3 */
6010 		[27] = PIN_AVB_TXCREFCLK,	/* AVB_TXCREFCLK */
6011 		[28] = PIN_AVB_MDIO,		/* AVB_MDIO */
6012 		[29] = RCAR_GP_PIN(2,  9),	/* AVB_MDC */
6013 		[30] = RCAR_GP_PIN(2, 10),	/* AVB_MAGIC */
6014 		[31] = RCAR_GP_PIN(2, 11),	/* AVB_PHY_INT */
6015 	} },
6016 	{ PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
6017 		[ 0] = RCAR_GP_PIN(2, 12),	/* AVB_LINK */
6018 		[ 1] = RCAR_GP_PIN(2, 13),	/* AVB_AVTP_MATCH_A */
6019 		[ 2] = RCAR_GP_PIN(2, 14),	/* AVB_AVTP_CAPTURE_A */
6020 		[ 3] = RCAR_GP_PIN(2,  0),	/* IRQ0 */
6021 		[ 4] = RCAR_GP_PIN(2,  1),	/* IRQ1 */
6022 		[ 5] = RCAR_GP_PIN(2,  2),	/* IRQ2 */
6023 		[ 6] = RCAR_GP_PIN(2,  3),	/* IRQ3 */
6024 		[ 7] = RCAR_GP_PIN(2,  4),	/* IRQ4 */
6025 		[ 8] = RCAR_GP_PIN(2,  5),	/* IRQ5 */
6026 		[ 9] = RCAR_GP_PIN(2,  6),	/* PWM0 */
6027 		[10] = RCAR_GP_PIN(2,  7),	/* PWM1_A */
6028 		[11] = RCAR_GP_PIN(2,  8),	/* PWM2_A */
6029 		[12] = RCAR_GP_PIN(1,  0),	/* A0 */
6030 		[13] = RCAR_GP_PIN(1,  1),	/* A1 */
6031 		[14] = RCAR_GP_PIN(1,  2),	/* A2 */
6032 		[15] = RCAR_GP_PIN(1,  3),	/* A3 */
6033 		[16] = RCAR_GP_PIN(1,  4),	/* A4 */
6034 		[17] = RCAR_GP_PIN(1,  5),	/* A5 */
6035 		[18] = RCAR_GP_PIN(1,  6),	/* A6 */
6036 		[19] = RCAR_GP_PIN(1,  7),	/* A7 */
6037 		[20] = RCAR_GP_PIN(1,  8),	/* A8 */
6038 		[21] = RCAR_GP_PIN(1,  9),	/* A9 */
6039 		[22] = RCAR_GP_PIN(1, 10),	/* A10 */
6040 		[23] = RCAR_GP_PIN(1, 11),	/* A11 */
6041 		[24] = RCAR_GP_PIN(1, 12),	/* A12 */
6042 		[25] = RCAR_GP_PIN(1, 13),	/* A13 */
6043 		[26] = RCAR_GP_PIN(1, 14),	/* A14 */
6044 		[27] = RCAR_GP_PIN(1, 15),	/* A15 */
6045 		[28] = RCAR_GP_PIN(1, 16),	/* A16 */
6046 		[29] = RCAR_GP_PIN(1, 17),	/* A17 */
6047 		[30] = RCAR_GP_PIN(1, 18),	/* A18 */
6048 		[31] = RCAR_GP_PIN(1, 19),	/* A19 */
6049 	} },
6050 	{ PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
6051 		[ 0] = RCAR_GP_PIN(1, 28),	/* CLKOUT */
6052 		[ 1] = RCAR_GP_PIN(1, 20),	/* CS0_N */
6053 		[ 2] = RCAR_GP_PIN(1, 21),	/* CS1_N */
6054 		[ 3] = RCAR_GP_PIN(1, 22),	/* BS_N */
6055 		[ 4] = RCAR_GP_PIN(1, 23),	/* RD_N */
6056 		[ 5] = RCAR_GP_PIN(1, 24),	/* RD_WR_N */
6057 		[ 6] = RCAR_GP_PIN(1, 25),	/* WE0_N */
6058 		[ 7] = RCAR_GP_PIN(1, 26),	/* WE1_N */
6059 		[ 8] = RCAR_GP_PIN(1, 27),	/* EX_WAIT0_A */
6060 		[ 9] = PIN_PRESETOUT_N,		/* PRESETOUT# */
6061 		[10] = RCAR_GP_PIN(0,  0),	/* D0 */
6062 		[11] = RCAR_GP_PIN(0,  1),	/* D1 */
6063 		[12] = RCAR_GP_PIN(0,  2),	/* D2 */
6064 		[13] = RCAR_GP_PIN(0,  3),	/* D3 */
6065 		[14] = RCAR_GP_PIN(0,  4),	/* D4 */
6066 		[15] = RCAR_GP_PIN(0,  5),	/* D5 */
6067 		[16] = RCAR_GP_PIN(0,  6),	/* D6 */
6068 		[17] = RCAR_GP_PIN(0,  7),	/* D7 */
6069 		[18] = RCAR_GP_PIN(0,  8),	/* D8 */
6070 		[19] = RCAR_GP_PIN(0,  9),	/* D9 */
6071 		[20] = RCAR_GP_PIN(0, 10),	/* D10 */
6072 		[21] = RCAR_GP_PIN(0, 11),	/* D11 */
6073 		[22] = RCAR_GP_PIN(0, 12),	/* D12 */
6074 		[23] = RCAR_GP_PIN(0, 13),	/* D13 */
6075 		[24] = RCAR_GP_PIN(0, 14),	/* D14 */
6076 		[25] = RCAR_GP_PIN(0, 15),	/* D15 */
6077 		[26] = RCAR_GP_PIN(7,  0),	/* AVS1 */
6078 		[27] = RCAR_GP_PIN(7,  1),	/* AVS2 */
6079 		[28] = RCAR_GP_PIN(7,  2),	/* GP7_02 */
6080 		[29] = RCAR_GP_PIN(7,  3),	/* GP7_03 */
6081 		[30] = PIN_DU_DOTCLKIN0,	/* DU_DOTCLKIN0 */
6082 		[31] = PIN_DU_DOTCLKIN1,	/* DU_DOTCLKIN1 */
6083 	} },
6084 	{ PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
6085 		[ 0] = PIN_DU_DOTCLKIN2,	/* DU_DOTCLKIN2 */
6086 		[ 1] = SH_PFC_PIN_NONE,
6087 		[ 2] = PIN_FSCLKST,		/* FSCLKST */
6088 		[ 3] = PIN_EXTALR,		/* EXTALR*/
6089 		[ 4] = PIN_TRST_N,		/* TRST# */
6090 		[ 5] = PIN_TCK,			/* TCK */
6091 		[ 6] = PIN_TMS,			/* TMS */
6092 		[ 7] = PIN_TDI,			/* TDI */
6093 		[ 8] = SH_PFC_PIN_NONE,
6094 		[ 9] = PIN_ASEBRK,		/* ASEBRK */
6095 		[10] = RCAR_GP_PIN(3,  0),	/* SD0_CLK */
6096 		[11] = RCAR_GP_PIN(3,  1),	/* SD0_CMD */
6097 		[12] = RCAR_GP_PIN(3,  2),	/* SD0_DAT0 */
6098 		[13] = RCAR_GP_PIN(3,  3),	/* SD0_DAT1 */
6099 		[14] = RCAR_GP_PIN(3,  4),	/* SD0_DAT2 */
6100 		[15] = RCAR_GP_PIN(3,  5),	/* SD0_DAT3 */
6101 		[16] = RCAR_GP_PIN(3,  6),	/* SD1_CLK */
6102 		[17] = RCAR_GP_PIN(3,  7),	/* SD1_CMD */
6103 		[18] = RCAR_GP_PIN(3,  8),	/* SD1_DAT0 */
6104 		[19] = RCAR_GP_PIN(3,  9),	/* SD1_DAT1 */
6105 		[20] = RCAR_GP_PIN(3, 10),	/* SD1_DAT2 */
6106 		[21] = RCAR_GP_PIN(3, 11),	/* SD1_DAT3 */
6107 		[22] = RCAR_GP_PIN(4,  0),	/* SD2_CLK */
6108 		[23] = RCAR_GP_PIN(4,  1),	/* SD2_CMD */
6109 		[24] = RCAR_GP_PIN(4,  2),	/* SD2_DAT0 */
6110 		[25] = RCAR_GP_PIN(4,  3),	/* SD2_DAT1 */
6111 		[26] = RCAR_GP_PIN(4,  4),	/* SD2_DAT2 */
6112 		[27] = RCAR_GP_PIN(4,  5),	/* SD2_DAT3 */
6113 		[28] = RCAR_GP_PIN(4,  6),	/* SD2_DS */
6114 		[29] = RCAR_GP_PIN(4,  7),	/* SD3_CLK */
6115 		[30] = RCAR_GP_PIN(4,  8),	/* SD3_CMD */
6116 		[31] = RCAR_GP_PIN(4,  9),	/* SD3_DAT0 */
6117 	} },
6118 	{ PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
6119 		[ 0] = RCAR_GP_PIN(4, 10),	/* SD3_DAT1 */
6120 		[ 1] = RCAR_GP_PIN(4, 11),	/* SD3_DAT2 */
6121 		[ 2] = RCAR_GP_PIN(4, 12),	/* SD3_DAT3 */
6122 		[ 3] = RCAR_GP_PIN(4, 13),	/* SD3_DAT4 */
6123 		[ 4] = RCAR_GP_PIN(4, 14),	/* SD3_DAT5 */
6124 		[ 5] = RCAR_GP_PIN(4, 15),	/* SD3_DAT6 */
6125 		[ 6] = RCAR_GP_PIN(4, 16),	/* SD3_DAT7 */
6126 		[ 7] = RCAR_GP_PIN(4, 17),	/* SD3_DS */
6127 		[ 8] = RCAR_GP_PIN(3, 12),	/* SD0_CD */
6128 		[ 9] = RCAR_GP_PIN(3, 13),	/* SD0_WP */
6129 		[10] = RCAR_GP_PIN(3, 14),	/* SD1_CD */
6130 		[11] = RCAR_GP_PIN(3, 15),	/* SD1_WP */
6131 		[12] = RCAR_GP_PIN(5,  0),	/* SCK0 */
6132 		[13] = RCAR_GP_PIN(5,  1),	/* RX0 */
6133 		[14] = RCAR_GP_PIN(5,  2),	/* TX0 */
6134 		[15] = RCAR_GP_PIN(5,  3),	/* CTS0_N */
6135 		[16] = RCAR_GP_PIN(5,  4),	/* RTS0_N */
6136 		[17] = RCAR_GP_PIN(5,  5),	/* RX1_A */
6137 		[18] = RCAR_GP_PIN(5,  6),	/* TX1_A */
6138 		[19] = RCAR_GP_PIN(5,  7),	/* CTS1_N */
6139 		[20] = RCAR_GP_PIN(5,  8),	/* RTS1_N */
6140 		[21] = RCAR_GP_PIN(5,  9),	/* SCK2 */
6141 		[22] = RCAR_GP_PIN(5, 10),	/* TX2_A */
6142 		[23] = RCAR_GP_PIN(5, 11),	/* RX2_A */
6143 		[24] = RCAR_GP_PIN(5, 12),	/* HSCK0 */
6144 		[25] = RCAR_GP_PIN(5, 13),	/* HRX0 */
6145 		[26] = RCAR_GP_PIN(5, 14),	/* HTX0 */
6146 		[27] = RCAR_GP_PIN(5, 15),	/* HCTS0_N */
6147 		[28] = RCAR_GP_PIN(5, 16),	/* HRTS0_N */
6148 		[29] = RCAR_GP_PIN(5, 17),	/* MSIOF0_SCK */
6149 		[30] = RCAR_GP_PIN(5, 18),	/* MSIOF0_SYNC */
6150 		[31] = RCAR_GP_PIN(5, 19),	/* MSIOF0_SS1 */
6151 	} },
6152 	{ PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
6153 		[ 0] = RCAR_GP_PIN(5, 20),	/* MSIOF0_TXD */
6154 		[ 1] = RCAR_GP_PIN(5, 21),	/* MSIOF0_SS2 */
6155 		[ 2] = RCAR_GP_PIN(5, 22),	/* MSIOF0_RXD */
6156 		[ 3] = RCAR_GP_PIN(5, 23),	/* MLB_CLK */
6157 		[ 4] = RCAR_GP_PIN(5, 24),	/* MLB_SIG */
6158 		[ 5] = RCAR_GP_PIN(5, 25),	/* MLB_DAT */
6159 		[ 6] = PIN_MLB_REF,		/* MLB_REF */
6160 		[ 7] = RCAR_GP_PIN(6,  0),	/* SSI_SCK01239 */
6161 		[ 8] = RCAR_GP_PIN(6,  1),	/* SSI_WS01239 */
6162 		[ 9] = RCAR_GP_PIN(6,  2),	/* SSI_SDATA0 */
6163 		[10] = RCAR_GP_PIN(6,  3),	/* SSI_SDATA1_A */
6164 		[11] = RCAR_GP_PIN(6,  4),	/* SSI_SDATA2_A */
6165 		[12] = RCAR_GP_PIN(6,  5),	/* SSI_SCK349 */
6166 		[13] = RCAR_GP_PIN(6,  6),	/* SSI_WS349 */
6167 		[14] = RCAR_GP_PIN(6,  7),	/* SSI_SDATA3 */
6168 		[15] = RCAR_GP_PIN(6,  8),	/* SSI_SCK4 */
6169 		[16] = RCAR_GP_PIN(6,  9),	/* SSI_WS4 */
6170 		[17] = RCAR_GP_PIN(6, 10),	/* SSI_SDATA4 */
6171 		[18] = RCAR_GP_PIN(6, 11),	/* SSI_SCK5 */
6172 		[19] = RCAR_GP_PIN(6, 12),	/* SSI_WS5 */
6173 		[20] = RCAR_GP_PIN(6, 13),	/* SSI_SDATA5 */
6174 		[21] = RCAR_GP_PIN(6, 14),	/* SSI_SCK6 */
6175 		[22] = RCAR_GP_PIN(6, 15),	/* SSI_WS6 */
6176 		[23] = RCAR_GP_PIN(6, 16),	/* SSI_SDATA6 */
6177 		[24] = RCAR_GP_PIN(6, 17),	/* SSI_SCK78 */
6178 		[25] = RCAR_GP_PIN(6, 18),	/* SSI_WS78 */
6179 		[26] = RCAR_GP_PIN(6, 19),	/* SSI_SDATA7 */
6180 		[27] = RCAR_GP_PIN(6, 20),	/* SSI_SDATA8 */
6181 		[28] = RCAR_GP_PIN(6, 21),	/* SSI_SDATA9_A */
6182 		[29] = RCAR_GP_PIN(6, 22),	/* AUDIO_CLKA_A */
6183 		[30] = RCAR_GP_PIN(6, 23),	/* AUDIO_CLKB_B */
6184 		[31] = RCAR_GP_PIN(6, 24),	/* USB0_PWEN */
6185 	} },
6186 	{ PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) {
6187 		[ 0] = RCAR_GP_PIN(6, 25),	/* USB0_OVC */
6188 		[ 1] = RCAR_GP_PIN(6, 26),	/* USB1_PWEN */
6189 		[ 2] = RCAR_GP_PIN(6, 27),	/* USB1_OVC */
6190 		[ 3] = RCAR_GP_PIN(6, 28),	/* USB30_PWEN */
6191 		[ 4] = RCAR_GP_PIN(6, 29),	/* USB30_OVC */
6192 		[ 5] = RCAR_GP_PIN(6, 30),	/* GP6_30 */
6193 		[ 6] = RCAR_GP_PIN(6, 31),	/* GP6_31 */
6194 		[ 7] = SH_PFC_PIN_NONE,
6195 		[ 8] = SH_PFC_PIN_NONE,
6196 		[ 9] = SH_PFC_PIN_NONE,
6197 		[10] = SH_PFC_PIN_NONE,
6198 		[11] = SH_PFC_PIN_NONE,
6199 		[12] = SH_PFC_PIN_NONE,
6200 		[13] = SH_PFC_PIN_NONE,
6201 		[14] = SH_PFC_PIN_NONE,
6202 		[15] = SH_PFC_PIN_NONE,
6203 		[16] = SH_PFC_PIN_NONE,
6204 		[17] = SH_PFC_PIN_NONE,
6205 		[18] = SH_PFC_PIN_NONE,
6206 		[19] = SH_PFC_PIN_NONE,
6207 		[20] = SH_PFC_PIN_NONE,
6208 		[21] = SH_PFC_PIN_NONE,
6209 		[22] = SH_PFC_PIN_NONE,
6210 		[23] = SH_PFC_PIN_NONE,
6211 		[24] = SH_PFC_PIN_NONE,
6212 		[25] = SH_PFC_PIN_NONE,
6213 		[26] = SH_PFC_PIN_NONE,
6214 		[27] = SH_PFC_PIN_NONE,
6215 		[28] = SH_PFC_PIN_NONE,
6216 		[29] = SH_PFC_PIN_NONE,
6217 		[30] = SH_PFC_PIN_NONE,
6218 		[31] = SH_PFC_PIN_NONE,
6219 	} },
6220 	{ /* sentinel */ },
6221 };
6222 
6223 static const struct sh_pfc_soc_operations r8a7796_pinmux_ops = {
6224 	.pin_to_pocctrl = r8a7796_pin_to_pocctrl,
6225 	.get_bias = rcar_pinmux_get_bias,
6226 	.set_bias = rcar_pinmux_set_bias,
6227 };
6228 
6229 #ifdef CONFIG_PINCTRL_PFC_R8A774A1
6230 const struct sh_pfc_soc_info r8a774a1_pinmux_info = {
6231 	.name = "r8a774a1_pfc",
6232 	.ops = &r8a7796_pinmux_ops,
6233 	.unlock_reg = 0xe6060000, /* PMMR */
6234 
6235 	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6236 
6237 	.pins = pinmux_pins,
6238 	.nr_pins = ARRAY_SIZE(pinmux_pins),
6239 	.groups = pinmux_groups.common,
6240 	.nr_groups = ARRAY_SIZE(pinmux_groups.common),
6241 	.functions = pinmux_functions.common,
6242 	.nr_functions = ARRAY_SIZE(pinmux_functions.common),
6243 
6244 	.cfg_regs = pinmux_config_regs,
6245 	.drive_regs = pinmux_drive_regs,
6246 	.bias_regs = pinmux_bias_regs,
6247 	.ioctrl_regs = pinmux_ioctrl_regs,
6248 
6249 	.pinmux_data = pinmux_data,
6250 	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
6251 };
6252 #endif
6253 
6254 #ifdef CONFIG_PINCTRL_PFC_R8A77960
6255 const struct sh_pfc_soc_info r8a77960_pinmux_info = {
6256 	.name = "r8a77960_pfc",
6257 	.ops = &r8a7796_pinmux_ops,
6258 	.unlock_reg = 0xe6060000, /* PMMR */
6259 
6260 	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6261 
6262 	.pins = pinmux_pins,
6263 	.nr_pins = ARRAY_SIZE(pinmux_pins),
6264 	.groups = pinmux_groups.common,
6265 	.nr_groups = ARRAY_SIZE(pinmux_groups.common) +
6266 		ARRAY_SIZE(pinmux_groups.automotive),
6267 	.functions = pinmux_functions.common,
6268 	.nr_functions = ARRAY_SIZE(pinmux_functions.common) +
6269 		ARRAY_SIZE(pinmux_functions.automotive),
6270 
6271 	.cfg_regs = pinmux_config_regs,
6272 	.drive_regs = pinmux_drive_regs,
6273 	.bias_regs = pinmux_bias_regs,
6274 	.ioctrl_regs = pinmux_ioctrl_regs,
6275 
6276 	.pinmux_data = pinmux_data,
6277 	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
6278 };
6279 #endif
6280 
6281 #ifdef CONFIG_PINCTRL_PFC_R8A77961
6282 const struct sh_pfc_soc_info r8a77961_pinmux_info = {
6283 	.name = "r8a77961_pfc",
6284 	.ops = &r8a7796_pinmux_ops,
6285 	.unlock_reg = 0xe6060000, /* PMMR */
6286 
6287 	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6288 
6289 	.pins = pinmux_pins,
6290 	.nr_pins = ARRAY_SIZE(pinmux_pins),
6291 	.groups = pinmux_groups.common,
6292 	.nr_groups = ARRAY_SIZE(pinmux_groups.common) +
6293 		ARRAY_SIZE(pinmux_groups.automotive),
6294 	.functions = pinmux_functions.common,
6295 	.nr_functions = ARRAY_SIZE(pinmux_functions.common) +
6296 		ARRAY_SIZE(pinmux_functions.automotive),
6297 
6298 	.cfg_regs = pinmux_config_regs,
6299 	.drive_regs = pinmux_drive_regs,
6300 	.bias_regs = pinmux_bias_regs,
6301 	.ioctrl_regs = pinmux_ioctrl_regs,
6302 
6303 	.pinmux_data = pinmux_data,
6304 	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
6305 };
6306 #endif
6307