1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * R8A7796 (R-Car M3-W/W+) support - PFC hardware block. 4 * 5 * Copyright (C) 2016-2019 Renesas Electronics Corp. 6 * 7 * This file is based on the drivers/pinctrl/renesas/pfc-r8a7795.c 8 * 9 * R-Car Gen3 processor support - PFC hardware block. 10 * 11 * Copyright (C) 2015 Renesas Electronics Corporation 12 */ 13 14 #include <linux/errno.h> 15 #include <linux/kernel.h> 16 17 #include "core.h" 18 #include "sh_pfc.h" 19 20 #define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN) 21 22 #define CPU_ALL_GP(fn, sfx) \ 23 PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \ 24 PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \ 25 PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \ 26 PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \ 27 PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \ 28 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \ 29 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \ 30 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \ 31 PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \ 32 PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \ 33 PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \ 34 PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS) 35 36 #define CPU_ALL_NOGP(fn) \ 37 PIN_NOGP_CFG(ASEBRK, "ASEBRK", fn, CFG_FLAGS), \ 38 PIN_NOGP_CFG(AVB_MDIO, "AVB_MDIO", fn, CFG_FLAGS), \ 39 PIN_NOGP_CFG(AVB_RD0, "AVB_RD0", fn, CFG_FLAGS), \ 40 PIN_NOGP_CFG(AVB_RD1, "AVB_RD1", fn, CFG_FLAGS), \ 41 PIN_NOGP_CFG(AVB_RD2, "AVB_RD2", fn, CFG_FLAGS), \ 42 PIN_NOGP_CFG(AVB_RD3, "AVB_RD3", fn, CFG_FLAGS), \ 43 PIN_NOGP_CFG(AVB_RXC, "AVB_RXC", fn, CFG_FLAGS), \ 44 PIN_NOGP_CFG(AVB_RX_CTL, "AVB_RX_CTL", fn, CFG_FLAGS), \ 45 PIN_NOGP_CFG(AVB_TD0, "AVB_TD0", fn, CFG_FLAGS), \ 46 PIN_NOGP_CFG(AVB_TD1, "AVB_TD1", fn, CFG_FLAGS), \ 47 PIN_NOGP_CFG(AVB_TD2, "AVB_TD2", fn, CFG_FLAGS), \ 48 PIN_NOGP_CFG(AVB_TD3, "AVB_TD3", fn, CFG_FLAGS), \ 49 PIN_NOGP_CFG(AVB_TXC, "AVB_TXC", fn, CFG_FLAGS), \ 50 PIN_NOGP_CFG(AVB_TXCREFCLK, "AVB_TXCREFCLK", fn, CFG_FLAGS), \ 51 PIN_NOGP_CFG(AVB_TX_CTL, "AVB_TX_CTL", fn, CFG_FLAGS), \ 52 PIN_NOGP_CFG(DU_DOTCLKIN0, "DU_DOTCLKIN0", fn, CFG_FLAGS), \ 53 PIN_NOGP_CFG(DU_DOTCLKIN1, "DU_DOTCLKIN1", fn, CFG_FLAGS), \ 54 PIN_NOGP_CFG(DU_DOTCLKIN2, "DU_DOTCLKIN2", fn, CFG_FLAGS), \ 55 PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),\ 56 PIN_NOGP_CFG(FSCLKST, "FSCLKST", fn, CFG_FLAGS), \ 57 PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS), \ 58 PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, CFG_FLAGS), \ 59 PIN_NOGP_CFG(QSPI0_IO2, "QSPI0_IO2", fn, CFG_FLAGS), \ 60 PIN_NOGP_CFG(QSPI0_IO3, "QSPI0_IO3", fn, CFG_FLAGS), \ 61 PIN_NOGP_CFG(QSPI0_MISO_IO1, "QSPI0_MISO_IO1", fn, CFG_FLAGS), \ 62 PIN_NOGP_CFG(QSPI0_MOSI_IO0, "QSPI0_MOSI_IO0", fn, CFG_FLAGS), \ 63 PIN_NOGP_CFG(QSPI0_SPCLK, "QSPI0_SPCLK", fn, CFG_FLAGS), \ 64 PIN_NOGP_CFG(QSPI0_SSL, "QSPI0_SSL", fn, CFG_FLAGS), \ 65 PIN_NOGP_CFG(QSPI1_IO2, "QSPI1_IO2", fn, CFG_FLAGS), \ 66 PIN_NOGP_CFG(QSPI1_IO3, "QSPI1_IO3", fn, CFG_FLAGS), \ 67 PIN_NOGP_CFG(QSPI1_MISO_IO1, "QSPI1_MISO_IO1", fn, CFG_FLAGS), \ 68 PIN_NOGP_CFG(QSPI1_MOSI_IO0, "QSPI1_MOSI_IO0", fn, CFG_FLAGS), \ 69 PIN_NOGP_CFG(QSPI1_SPCLK, "QSPI1_SPCLK", fn, CFG_FLAGS), \ 70 PIN_NOGP_CFG(QSPI1_SSL, "QSPI1_SSL", fn, CFG_FLAGS), \ 71 PIN_NOGP_CFG(PRESET_N, "PRESET#", fn, SH_PFC_PIN_CFG_PULL_DOWN),\ 72 PIN_NOGP_CFG(RPC_INT_N, "RPC_INT#", fn, CFG_FLAGS), \ 73 PIN_NOGP_CFG(RPC_RESET_N, "RPC_RESET#", fn, CFG_FLAGS), \ 74 PIN_NOGP_CFG(RPC_WP_N, "RPC_WP#", fn, CFG_FLAGS), \ 75 PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ 76 PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ 77 PIN_NOGP_CFG(TDO, "TDO", fn, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \ 78 PIN_NOGP_CFG(TMS, "TMS", fn, CFG_FLAGS), \ 79 PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN) 80 81 /* 82 * F_() : just information 83 * FM() : macro for FN_xxx / xxx_MARK 84 */ 85 86 /* GPSR0 */ 87 #define GPSR0_15 F_(D15, IP7_11_8) 88 #define GPSR0_14 F_(D14, IP7_7_4) 89 #define GPSR0_13 F_(D13, IP7_3_0) 90 #define GPSR0_12 F_(D12, IP6_31_28) 91 #define GPSR0_11 F_(D11, IP6_27_24) 92 #define GPSR0_10 F_(D10, IP6_23_20) 93 #define GPSR0_9 F_(D9, IP6_19_16) 94 #define GPSR0_8 F_(D8, IP6_15_12) 95 #define GPSR0_7 F_(D7, IP6_11_8) 96 #define GPSR0_6 F_(D6, IP6_7_4) 97 #define GPSR0_5 F_(D5, IP6_3_0) 98 #define GPSR0_4 F_(D4, IP5_31_28) 99 #define GPSR0_3 F_(D3, IP5_27_24) 100 #define GPSR0_2 F_(D2, IP5_23_20) 101 #define GPSR0_1 F_(D1, IP5_19_16) 102 #define GPSR0_0 F_(D0, IP5_15_12) 103 104 /* GPSR1 */ 105 #define GPSR1_28 FM(CLKOUT) 106 #define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8) 107 #define GPSR1_26 F_(WE1_N, IP5_7_4) 108 #define GPSR1_25 F_(WE0_N, IP5_3_0) 109 #define GPSR1_24 F_(RD_WR_N, IP4_31_28) 110 #define GPSR1_23 F_(RD_N, IP4_27_24) 111 #define GPSR1_22 F_(BS_N, IP4_23_20) 112 #define GPSR1_21 F_(CS1_N, IP4_19_16) 113 #define GPSR1_20 F_(CS0_N, IP4_15_12) 114 #define GPSR1_19 F_(A19, IP4_11_8) 115 #define GPSR1_18 F_(A18, IP4_7_4) 116 #define GPSR1_17 F_(A17, IP4_3_0) 117 #define GPSR1_16 F_(A16, IP3_31_28) 118 #define GPSR1_15 F_(A15, IP3_27_24) 119 #define GPSR1_14 F_(A14, IP3_23_20) 120 #define GPSR1_13 F_(A13, IP3_19_16) 121 #define GPSR1_12 F_(A12, IP3_15_12) 122 #define GPSR1_11 F_(A11, IP3_11_8) 123 #define GPSR1_10 F_(A10, IP3_7_4) 124 #define GPSR1_9 F_(A9, IP3_3_0) 125 #define GPSR1_8 F_(A8, IP2_31_28) 126 #define GPSR1_7 F_(A7, IP2_27_24) 127 #define GPSR1_6 F_(A6, IP2_23_20) 128 #define GPSR1_5 F_(A5, IP2_19_16) 129 #define GPSR1_4 F_(A4, IP2_15_12) 130 #define GPSR1_3 F_(A3, IP2_11_8) 131 #define GPSR1_2 F_(A2, IP2_7_4) 132 #define GPSR1_1 F_(A1, IP2_3_0) 133 #define GPSR1_0 F_(A0, IP1_31_28) 134 135 /* GPSR2 */ 136 #define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20) 137 #define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16) 138 #define GPSR2_12 F_(AVB_LINK, IP0_15_12) 139 #define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8) 140 #define GPSR2_10 F_(AVB_MAGIC, IP0_7_4) 141 #define GPSR2_9 F_(AVB_MDC, IP0_3_0) 142 #define GPSR2_8 F_(PWM2_A, IP1_27_24) 143 #define GPSR2_7 F_(PWM1_A, IP1_23_20) 144 #define GPSR2_6 F_(PWM0, IP1_19_16) 145 #define GPSR2_5 F_(IRQ5, IP1_15_12) 146 #define GPSR2_4 F_(IRQ4, IP1_11_8) 147 #define GPSR2_3 F_(IRQ3, IP1_7_4) 148 #define GPSR2_2 F_(IRQ2, IP1_3_0) 149 #define GPSR2_1 F_(IRQ1, IP0_31_28) 150 #define GPSR2_0 F_(IRQ0, IP0_27_24) 151 152 /* GPSR3 */ 153 #define GPSR3_15 F_(SD1_WP, IP11_23_20) 154 #define GPSR3_14 F_(SD1_CD, IP11_19_16) 155 #define GPSR3_13 F_(SD0_WP, IP11_15_12) 156 #define GPSR3_12 F_(SD0_CD, IP11_11_8) 157 #define GPSR3_11 F_(SD1_DAT3, IP8_31_28) 158 #define GPSR3_10 F_(SD1_DAT2, IP8_27_24) 159 #define GPSR3_9 F_(SD1_DAT1, IP8_23_20) 160 #define GPSR3_8 F_(SD1_DAT0, IP8_19_16) 161 #define GPSR3_7 F_(SD1_CMD, IP8_15_12) 162 #define GPSR3_6 F_(SD1_CLK, IP8_11_8) 163 #define GPSR3_5 F_(SD0_DAT3, IP8_7_4) 164 #define GPSR3_4 F_(SD0_DAT2, IP8_3_0) 165 #define GPSR3_3 F_(SD0_DAT1, IP7_31_28) 166 #define GPSR3_2 F_(SD0_DAT0, IP7_27_24) 167 #define GPSR3_1 F_(SD0_CMD, IP7_23_20) 168 #define GPSR3_0 F_(SD0_CLK, IP7_19_16) 169 170 /* GPSR4 */ 171 #define GPSR4_17 F_(SD3_DS, IP11_7_4) 172 #define GPSR4_16 F_(SD3_DAT7, IP11_3_0) 173 #define GPSR4_15 F_(SD3_DAT6, IP10_31_28) 174 #define GPSR4_14 F_(SD3_DAT5, IP10_27_24) 175 #define GPSR4_13 F_(SD3_DAT4, IP10_23_20) 176 #define GPSR4_12 F_(SD3_DAT3, IP10_19_16) 177 #define GPSR4_11 F_(SD3_DAT2, IP10_15_12) 178 #define GPSR4_10 F_(SD3_DAT1, IP10_11_8) 179 #define GPSR4_9 F_(SD3_DAT0, IP10_7_4) 180 #define GPSR4_8 F_(SD3_CMD, IP10_3_0) 181 #define GPSR4_7 F_(SD3_CLK, IP9_31_28) 182 #define GPSR4_6 F_(SD2_DS, IP9_27_24) 183 #define GPSR4_5 F_(SD2_DAT3, IP9_23_20) 184 #define GPSR4_4 F_(SD2_DAT2, IP9_19_16) 185 #define GPSR4_3 F_(SD2_DAT1, IP9_15_12) 186 #define GPSR4_2 F_(SD2_DAT0, IP9_11_8) 187 #define GPSR4_1 F_(SD2_CMD, IP9_7_4) 188 #define GPSR4_0 F_(SD2_CLK, IP9_3_0) 189 190 /* GPSR5 */ 191 #define GPSR5_25 F_(MLB_DAT, IP14_19_16) 192 #define GPSR5_24 F_(MLB_SIG, IP14_15_12) 193 #define GPSR5_23 F_(MLB_CLK, IP14_11_8) 194 #define GPSR5_22 FM(MSIOF0_RXD) 195 #define GPSR5_21 F_(MSIOF0_SS2, IP14_7_4) 196 #define GPSR5_20 FM(MSIOF0_TXD) 197 #define GPSR5_19 F_(MSIOF0_SS1, IP14_3_0) 198 #define GPSR5_18 F_(MSIOF0_SYNC, IP13_31_28) 199 #define GPSR5_17 FM(MSIOF0_SCK) 200 #define GPSR5_16 F_(HRTS0_N, IP13_27_24) 201 #define GPSR5_15 F_(HCTS0_N, IP13_23_20) 202 #define GPSR5_14 F_(HTX0, IP13_19_16) 203 #define GPSR5_13 F_(HRX0, IP13_15_12) 204 #define GPSR5_12 F_(HSCK0, IP13_11_8) 205 #define GPSR5_11 F_(RX2_A, IP13_7_4) 206 #define GPSR5_10 F_(TX2_A, IP13_3_0) 207 #define GPSR5_9 F_(SCK2, IP12_31_28) 208 #define GPSR5_8 F_(RTS1_N, IP12_27_24) 209 #define GPSR5_7 F_(CTS1_N, IP12_23_20) 210 #define GPSR5_6 F_(TX1_A, IP12_19_16) 211 #define GPSR5_5 F_(RX1_A, IP12_15_12) 212 #define GPSR5_4 F_(RTS0_N, IP12_11_8) 213 #define GPSR5_3 F_(CTS0_N, IP12_7_4) 214 #define GPSR5_2 F_(TX0, IP12_3_0) 215 #define GPSR5_1 F_(RX0, IP11_31_28) 216 #define GPSR5_0 F_(SCK0, IP11_27_24) 217 218 /* GPSR6 */ 219 #define GPSR6_31 F_(GP6_31, IP18_7_4) 220 #define GPSR6_30 F_(GP6_30, IP18_3_0) 221 #define GPSR6_29 F_(USB30_OVC, IP17_31_28) 222 #define GPSR6_28 F_(USB30_PWEN, IP17_27_24) 223 #define GPSR6_27 F_(USB1_OVC, IP17_23_20) 224 #define GPSR6_26 F_(USB1_PWEN, IP17_19_16) 225 #define GPSR6_25 F_(USB0_OVC, IP17_15_12) 226 #define GPSR6_24 F_(USB0_PWEN, IP17_11_8) 227 #define GPSR6_23 F_(AUDIO_CLKB_B, IP17_7_4) 228 #define GPSR6_22 F_(AUDIO_CLKA_A, IP17_3_0) 229 #define GPSR6_21 F_(SSI_SDATA9_A, IP16_31_28) 230 #define GPSR6_20 F_(SSI_SDATA8, IP16_27_24) 231 #define GPSR6_19 F_(SSI_SDATA7, IP16_23_20) 232 #define GPSR6_18 F_(SSI_WS78, IP16_19_16) 233 #define GPSR6_17 F_(SSI_SCK78, IP16_15_12) 234 #define GPSR6_16 F_(SSI_SDATA6, IP16_11_8) 235 #define GPSR6_15 F_(SSI_WS6, IP16_7_4) 236 #define GPSR6_14 F_(SSI_SCK6, IP16_3_0) 237 #define GPSR6_13 FM(SSI_SDATA5) 238 #define GPSR6_12 FM(SSI_WS5) 239 #define GPSR6_11 FM(SSI_SCK5) 240 #define GPSR6_10 F_(SSI_SDATA4, IP15_31_28) 241 #define GPSR6_9 F_(SSI_WS4, IP15_27_24) 242 #define GPSR6_8 F_(SSI_SCK4, IP15_23_20) 243 #define GPSR6_7 F_(SSI_SDATA3, IP15_19_16) 244 #define GPSR6_6 F_(SSI_WS349, IP15_15_12) 245 #define GPSR6_5 F_(SSI_SCK349, IP15_11_8) 246 #define GPSR6_4 F_(SSI_SDATA2_A, IP15_7_4) 247 #define GPSR6_3 F_(SSI_SDATA1_A, IP15_3_0) 248 #define GPSR6_2 F_(SSI_SDATA0, IP14_31_28) 249 #define GPSR6_1 F_(SSI_WS01239, IP14_27_24) 250 #define GPSR6_0 F_(SSI_SCK01239, IP14_23_20) 251 252 /* GPSR7 */ 253 #define GPSR7_3 FM(GP7_03) 254 #define GPSR7_2 FM(GP7_02) 255 #define GPSR7_1 FM(AVS2) 256 #define GPSR7_0 FM(AVS1) 257 258 259 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ 260 #define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 261 #define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 262 #define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 263 #define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 264 #define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 265 #define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 266 #define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 267 #define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 268 #define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 269 #define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) F_(0, 0) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 270 #define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) F_(0, 0) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 271 #define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) F_(0, 0) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) F_(0, 0) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 272 #define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)F_(0, 0) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 273 #define IP1_23_20 FM(PWM1_A) F_(0, 0) F_(0, 0) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 274 #define IP1_27_24 FM(PWM2_A) F_(0, 0) F_(0, 0) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 275 #define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 276 #define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 277 #define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 278 #define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 279 #define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 280 #define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 281 #define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 282 #define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 283 #define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 284 #define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 285 #define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 286 #define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 287 288 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ 289 #define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 290 #define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 291 #define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 292 #define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 293 #define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 294 #define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 295 #define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 296 #define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 297 #define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 298 #define IP4_19_16 FM(CS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 299 #define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 300 #define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 301 #define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 302 #define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 303 #define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 304 #define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 305 #define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 306 #define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 307 #define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 308 #define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 309 #define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 310 #define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 311 #define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 312 #define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 313 #define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 314 #define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 315 #define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 316 #define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_C) FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 317 #define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 318 319 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ 320 #define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 321 #define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 322 #define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 323 #define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 324 #define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 325 #define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 326 #define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 327 #define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 328 #define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 329 #define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 330 #define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) FM(NFCE_N_B) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 331 #define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) FM(NFWP_N_B) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 332 #define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) FM(NFDATA14_B) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 333 #define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) FM(NFDATA15_B) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 334 #define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) FM(NFRB_N_B) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 335 #define IP9_3_0 FM(SD2_CLK) F_(0, 0) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 336 #define IP9_7_4 FM(SD2_CMD) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 337 #define IP9_11_8 FM(SD2_DAT0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 338 #define IP9_15_12 FM(SD2_DAT1) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 339 #define IP9_19_16 FM(SD2_DAT2) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 340 #define IP9_23_20 FM(SD2_DAT3) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 341 #define IP9_27_24 FM(SD2_DS) F_(0, 0) FM(NFALE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 342 #define IP9_31_28 FM(SD3_CLK) F_(0, 0) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 343 #define IP10_3_0 FM(SD3_CMD) F_(0, 0) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 344 #define IP10_7_4 FM(SD3_DAT0) F_(0, 0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 345 #define IP10_11_8 FM(SD3_DAT1) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 346 #define IP10_15_12 FM(SD3_DAT2) F_(0, 0) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 347 #define IP10_19_16 FM(SD3_DAT3) F_(0, 0) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 348 #define IP10_23_20 FM(SD3_DAT4) FM(SD2_CD_A) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 349 #define IP10_27_24 FM(SD3_DAT5) FM(SD2_WP_A) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 350 #define IP10_31_28 FM(SD3_DAT6) FM(SD3_CD) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 351 #define IP11_3_0 FM(SD3_DAT7) FM(SD3_WP) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 352 #define IP11_7_4 FM(SD3_DS) F_(0, 0) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 353 #define IP11_11_8 FM(SD0_CD) F_(0, 0) FM(NFDATA14_A) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 354 355 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ 356 #define IP11_15_12 FM(SD0_WP) F_(0, 0) FM(NFDATA15_A) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 357 #define IP11_19_16 FM(SD1_CD) F_(0, 0) FM(NFRB_N_A) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 358 #define IP11_23_20 FM(SD1_WP) F_(0, 0) FM(NFCE_N_A) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 359 #define IP11_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 360 #define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 361 #define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 362 #define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 363 #define IP12_11_8 FM(RTS0_N) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 364 #define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 365 #define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 366 #define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 367 #define IP12_27_24 FM(RTS1_N) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 368 #define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 369 #define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 370 #define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 371 #define IP13_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 372 #define IP13_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 373 #define IP13_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 374 #define IP13_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 375 #define IP13_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 376 #define IP13_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) FM(TX5_B) F_(0, 0) F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0) 377 #define IP14_3_0 FM(MSIOF0_SS1) FM(RX5_A) FM(NFWP_N_A) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 378 #define IP14_7_4 FM(MSIOF0_SS2) FM(TX5_A) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 379 #define IP14_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 380 #define IP14_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 381 #define IP14_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 382 #define IP14_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 383 #define IP14_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 384 385 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ 386 #define IP14_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 387 #define IP15_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 388 #define IP15_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 389 #define IP15_11_8 FM(SSI_SCK349) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 390 #define IP15_15_12 FM(SSI_WS349) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 391 #define IP15_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 392 #define IP15_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 393 #define IP15_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 394 #define IP15_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 395 #define IP16_3_0 FM(SSI_SCK6) F_(0, 0) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 396 #define IP16_7_4 FM(SSI_WS6) F_(0, 0) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 397 #define IP16_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 398 #define IP16_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 399 #define IP16_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 400 #define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 401 #define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 402 #define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 403 #define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 404 #define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 405 #define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0) 406 #define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0) 407 #define IP17_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0) 408 #define IP17_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0) 409 #define IP17_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0) 410 #define IP17_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_N) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 411 #define IP18_3_0 FM(GP6_30) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0) 412 #define IP18_7_4 FM(GP6_31) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0) 413 414 #define PINMUX_GPSR \ 415 \ 416 GPSR6_31 \ 417 GPSR6_30 \ 418 GPSR6_29 \ 419 GPSR1_28 GPSR6_28 \ 420 GPSR1_27 GPSR6_27 \ 421 GPSR1_26 GPSR6_26 \ 422 GPSR1_25 GPSR5_25 GPSR6_25 \ 423 GPSR1_24 GPSR5_24 GPSR6_24 \ 424 GPSR1_23 GPSR5_23 GPSR6_23 \ 425 GPSR1_22 GPSR5_22 GPSR6_22 \ 426 GPSR1_21 GPSR5_21 GPSR6_21 \ 427 GPSR1_20 GPSR5_20 GPSR6_20 \ 428 GPSR1_19 GPSR5_19 GPSR6_19 \ 429 GPSR1_18 GPSR5_18 GPSR6_18 \ 430 GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \ 431 GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \ 432 GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \ 433 GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \ 434 GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \ 435 GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \ 436 GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \ 437 GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \ 438 GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \ 439 GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \ 440 GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \ 441 GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \ 442 GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \ 443 GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \ 444 GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \ 445 GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \ 446 GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \ 447 GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0 448 449 #define PINMUX_IPSR \ 450 \ 451 FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \ 452 FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \ 453 FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \ 454 FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \ 455 FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \ 456 FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \ 457 FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \ 458 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \ 459 \ 460 FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \ 461 FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \ 462 FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \ 463 FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 \ 464 FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \ 465 FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \ 466 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \ 467 FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \ 468 \ 469 FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \ 470 FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \ 471 FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \ 472 FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \ 473 FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \ 474 FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \ 475 FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \ 476 FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \ 477 \ 478 FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \ 479 FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \ 480 FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \ 481 FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \ 482 FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \ 483 FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \ 484 FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \ 485 FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \ 486 \ 487 FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 FM(IP18_3_0) IP18_3_0 \ 488 FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 FM(IP18_7_4) IP18_7_4 \ 489 FM(IP16_11_8) IP16_11_8 FM(IP17_11_8) IP17_11_8 \ 490 FM(IP16_15_12) IP16_15_12 FM(IP17_15_12) IP17_15_12 \ 491 FM(IP16_19_16) IP16_19_16 FM(IP17_19_16) IP17_19_16 \ 492 FM(IP16_23_20) IP16_23_20 FM(IP17_23_20) IP17_23_20 \ 493 FM(IP16_27_24) IP16_27_24 FM(IP17_27_24) IP17_27_24 \ 494 FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28 495 496 /* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ 497 #define MOD_SEL0_31_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3) FM(SEL_MSIOF3_4) F_(0, 0) F_(0, 0) F_(0, 0) 498 #define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3) 499 #define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0) 500 #define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1) 501 #define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1) 502 #define MOD_SEL0_21 FM(SEL_I2C2_0) FM(SEL_I2C2_1) 503 #define MOD_SEL0_20 FM(SEL_I2C1_0) FM(SEL_I2C1_1) 504 #define MOD_SEL0_19 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1) 505 #define MOD_SEL0_18_17 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3) 506 #define MOD_SEL0_16 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1) 507 #define MOD_SEL0_14_13 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) FM(SEL_HSCIF2_2) F_(0, 0) 508 #define MOD_SEL0_12 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1) 509 #define MOD_SEL0_11 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1) 510 #define MOD_SEL0_10 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1) 511 #define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0) 512 #define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0) 513 #define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1) 514 #define MOD_SEL0_4_3 FM(SEL_ADGA_0) FM(SEL_ADGA_1) FM(SEL_ADGA_2) FM(SEL_ADGA_3) 515 516 /* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ 517 #define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3) 518 #define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0) 519 #define MOD_SEL1_26 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1) 520 #define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3) 521 #define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0) 522 #define MOD_SEL1_20 FM(SEL_SSI1_0) FM(SEL_SSI1_1) 523 #define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1) 524 #define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3) 525 #define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1) 526 #define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0) 527 #define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1) 528 #define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1) 529 #define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1) 530 #define MOD_SEL1_10 FM(SEL_SCIF_0) FM(SEL_SCIF_1) 531 #define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1) 532 #define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1) 533 #define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1) 534 #define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1) 535 #define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1) 536 #define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1) 537 #define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1) 538 #define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1) 539 540 /* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ 541 #define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1) 542 #define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1) 543 #define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1) 544 #define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3) 545 #define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1) 546 #define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 547 #define MOD_SEL2_22 FM(SEL_NDF_0) FM(SEL_NDF_1) 548 #define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1) 549 #define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1) 550 #define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1) 551 #define MOD_SEL2_18 FM(SEL_ADGB_0) FM(SEL_ADGB_1) 552 #define MOD_SEL2_17 FM(SEL_ADGC_0) FM(SEL_ADGC_1) 553 #define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1) 554 555 #define PINMUX_MOD_SELS \ 556 \ 557 MOD_SEL0_31_30_29 MOD_SEL1_31_30 MOD_SEL2_31 \ 558 MOD_SEL2_30 \ 559 MOD_SEL1_29_28_27 MOD_SEL2_29 \ 560 MOD_SEL0_28_27 MOD_SEL2_28_27 \ 561 MOD_SEL0_26_25_24 MOD_SEL1_26 MOD_SEL2_26 \ 562 MOD_SEL1_25_24 MOD_SEL2_25_24_23 \ 563 MOD_SEL0_23 MOD_SEL1_23_22_21 \ 564 MOD_SEL0_22 MOD_SEL2_22 \ 565 MOD_SEL0_21 MOD_SEL2_21 \ 566 MOD_SEL0_20 MOD_SEL1_20 MOD_SEL2_20 \ 567 MOD_SEL0_19 MOD_SEL1_19 MOD_SEL2_19 \ 568 MOD_SEL0_18_17 MOD_SEL1_18_17 MOD_SEL2_18 \ 569 MOD_SEL2_17 \ 570 MOD_SEL0_16 MOD_SEL1_16 \ 571 MOD_SEL1_15_14 \ 572 MOD_SEL0_14_13 \ 573 MOD_SEL1_13 \ 574 MOD_SEL0_12 MOD_SEL1_12 \ 575 MOD_SEL0_11 MOD_SEL1_11 \ 576 MOD_SEL0_10 MOD_SEL1_10 \ 577 MOD_SEL0_9_8 MOD_SEL1_9 \ 578 MOD_SEL0_7_6 \ 579 MOD_SEL1_6 \ 580 MOD_SEL0_5 MOD_SEL1_5 \ 581 MOD_SEL0_4_3 MOD_SEL1_4 \ 582 MOD_SEL1_3 \ 583 MOD_SEL1_2 \ 584 MOD_SEL1_1 \ 585 MOD_SEL1_0 MOD_SEL2_0 586 587 /* 588 * These pins are not able to be muxed but have other properties 589 * that can be set, such as drive-strength or pull-up/pull-down enable. 590 */ 591 #define PINMUX_STATIC \ 592 FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \ 593 FM(QSPI0_IO2) FM(QSPI0_IO3) \ 594 FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \ 595 FM(QSPI1_IO2) FM(QSPI1_IO3) \ 596 FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \ 597 FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \ 598 FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \ 599 FM(AVB_TXCREFCLK) FM(AVB_MDIO) \ 600 FM(PRESETOUT) \ 601 FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) \ 602 FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR) 603 604 #define PINMUX_PHYS \ 605 FM(SCL0) FM(SDA0) FM(SCL3) FM(SDA3) FM(SCL5) FM(SDA5) 606 607 enum { 608 PINMUX_RESERVED = 0, 609 610 PINMUX_DATA_BEGIN, 611 GP_ALL(DATA), 612 PINMUX_DATA_END, 613 614 #define F_(x, y) 615 #define FM(x) FN_##x, 616 PINMUX_FUNCTION_BEGIN, 617 GP_ALL(FN), 618 PINMUX_GPSR 619 PINMUX_IPSR 620 PINMUX_MOD_SELS 621 PINMUX_FUNCTION_END, 622 #undef F_ 623 #undef FM 624 625 #define F_(x, y) 626 #define FM(x) x##_MARK, 627 PINMUX_MARK_BEGIN, 628 PINMUX_GPSR 629 PINMUX_IPSR 630 PINMUX_MOD_SELS 631 PINMUX_STATIC 632 PINMUX_PHYS 633 PINMUX_MARK_END, 634 #undef F_ 635 #undef FM 636 }; 637 638 static const u16 pinmux_data[] = { 639 PINMUX_DATA_GP_ALL(), 640 641 PINMUX_SINGLE(AVS1), 642 PINMUX_SINGLE(AVS2), 643 PINMUX_SINGLE(CLKOUT), 644 PINMUX_SINGLE(GP7_03), 645 PINMUX_SINGLE(GP7_02), 646 PINMUX_SINGLE(MSIOF0_RXD), 647 PINMUX_SINGLE(MSIOF0_SCK), 648 PINMUX_SINGLE(MSIOF0_TXD), 649 PINMUX_SINGLE(SSI_SCK5), 650 PINMUX_SINGLE(SSI_SDATA5), 651 PINMUX_SINGLE(SSI_WS5), 652 653 /* IPSR0 */ 654 PINMUX_IPSR_GPSR(IP0_3_0, AVB_MDC), 655 PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2), 656 657 PINMUX_IPSR_GPSR(IP0_7_4, AVB_MAGIC), 658 PINMUX_IPSR_MSEL(IP0_7_4, MSIOF2_SS1_C, SEL_MSIOF2_2), 659 PINMUX_IPSR_MSEL(IP0_7_4, SCK4_A, SEL_SCIF4_0), 660 661 PINMUX_IPSR_GPSR(IP0_11_8, AVB_PHY_INT), 662 PINMUX_IPSR_MSEL(IP0_11_8, MSIOF2_SYNC_C, SEL_MSIOF2_2), 663 PINMUX_IPSR_MSEL(IP0_11_8, RX4_A, SEL_SCIF4_0), 664 665 PINMUX_IPSR_GPSR(IP0_15_12, AVB_LINK), 666 PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2), 667 PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0), 668 669 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, I2C_SEL_5_0, SEL_ETHERAVB_0), 670 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, MSIOF2_RXD_C, I2C_SEL_5_0, SEL_MSIOF2_2), 671 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, CTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0), 672 PINMUX_IPSR_PHYS(IP0_19_16, SCL5, I2C_SEL_5_1), 673 674 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, I2C_SEL_5_0, SEL_ETHERAVB_0), 675 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C, I2C_SEL_5_0, SEL_MSIOF2_2), 676 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0), 677 PINMUX_IPSR_PHYS(IP0_23_20, SDA5, I2C_SEL_5_1), 678 679 PINMUX_IPSR_GPSR(IP0_27_24, IRQ0), 680 PINMUX_IPSR_GPSR(IP0_27_24, QPOLB), 681 PINMUX_IPSR_GPSR(IP0_27_24, DU_CDE), 682 PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1), 683 PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1), 684 PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_B, SEL_CANFD0_1), 685 PINMUX_IPSR_MSEL(IP0_27_24, MSIOF3_SS2_E, SEL_MSIOF3_4), 686 687 PINMUX_IPSR_GPSR(IP0_31_28, IRQ1), 688 PINMUX_IPSR_GPSR(IP0_31_28, QPOLA), 689 PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP), 690 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1), 691 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1), 692 PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1), 693 PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_SS1_E, SEL_MSIOF3_4), 694 695 /* IPSR1 */ 696 PINMUX_IPSR_GPSR(IP1_3_0, IRQ2), 697 PINMUX_IPSR_GPSR(IP1_3_0, QCPV_QDE), 698 PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE), 699 PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1), 700 PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1), 701 PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_SYNC_E, SEL_MSIOF3_4), 702 703 PINMUX_IPSR_GPSR(IP1_7_4, IRQ3), 704 PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE), 705 PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1), 706 PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1), 707 PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1), 708 PINMUX_IPSR_MSEL(IP1_7_4, MSIOF3_SCK_E, SEL_MSIOF3_4), 709 710 PINMUX_IPSR_GPSR(IP1_11_8, IRQ4), 711 PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS), 712 PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC), 713 PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1), 714 PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1), 715 PINMUX_IPSR_MSEL(IP1_11_8, MSIOF3_RXD_E, SEL_MSIOF3_4), 716 717 PINMUX_IPSR_GPSR(IP1_15_12, IRQ5), 718 PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE), 719 PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC), 720 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1), 721 PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1), 722 PINMUX_IPSR_MSEL(IP1_15_12, MSIOF3_TXD_E, SEL_MSIOF3_4), 723 724 PINMUX_IPSR_GPSR(IP1_19_16, PWM0), 725 PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS), 726 PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1), 727 PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1), 728 729 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, PWM1_A, I2C_SEL_3_0, SEL_PWM1_0), 730 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3), 731 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1), 732 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1), 733 PINMUX_IPSR_PHYS(IP1_23_20, SCL3, I2C_SEL_3_1), 734 735 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0), 736 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D, I2C_SEL_3_0, SEL_HSCIF3_3), 737 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, IETX_B, I2C_SEL_3_0, SEL_IEBUS_1), 738 PINMUX_IPSR_PHYS(IP1_27_24, SDA3, I2C_SEL_3_1), 739 740 PINMUX_IPSR_GPSR(IP1_31_28, A0), 741 PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16), 742 PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SYNC_B, SEL_MSIOF3_1), 743 PINMUX_IPSR_GPSR(IP1_31_28, VI4_DATA8), 744 PINMUX_IPSR_GPSR(IP1_31_28, DU_DB0), 745 PINMUX_IPSR_MSEL(IP1_31_28, PWM3_A, SEL_PWM3_0), 746 747 /* IPSR2 */ 748 PINMUX_IPSR_GPSR(IP2_3_0, A1), 749 PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT17), 750 PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_TXD_B, SEL_MSIOF3_1), 751 PINMUX_IPSR_GPSR(IP2_3_0, VI4_DATA9), 752 PINMUX_IPSR_GPSR(IP2_3_0, DU_DB1), 753 PINMUX_IPSR_MSEL(IP2_3_0, PWM4_A, SEL_PWM4_0), 754 755 PINMUX_IPSR_GPSR(IP2_7_4, A2), 756 PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT18), 757 PINMUX_IPSR_MSEL(IP2_7_4, MSIOF3_SCK_B, SEL_MSIOF3_1), 758 PINMUX_IPSR_GPSR(IP2_7_4, VI4_DATA10), 759 PINMUX_IPSR_GPSR(IP2_7_4, DU_DB2), 760 PINMUX_IPSR_MSEL(IP2_7_4, PWM5_A, SEL_PWM5_0), 761 762 PINMUX_IPSR_GPSR(IP2_11_8, A3), 763 PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT19), 764 PINMUX_IPSR_MSEL(IP2_11_8, MSIOF3_RXD_B, SEL_MSIOF3_1), 765 PINMUX_IPSR_GPSR(IP2_11_8, VI4_DATA11), 766 PINMUX_IPSR_GPSR(IP2_11_8, DU_DB3), 767 PINMUX_IPSR_MSEL(IP2_11_8, PWM6_A, SEL_PWM6_0), 768 769 PINMUX_IPSR_GPSR(IP2_15_12, A4), 770 PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT20), 771 PINMUX_IPSR_MSEL(IP2_15_12, MSIOF3_SS1_B, SEL_MSIOF3_1), 772 PINMUX_IPSR_GPSR(IP2_15_12, VI4_DATA12), 773 PINMUX_IPSR_GPSR(IP2_15_12, VI5_DATA12), 774 PINMUX_IPSR_GPSR(IP2_15_12, DU_DB4), 775 776 PINMUX_IPSR_GPSR(IP2_19_16, A5), 777 PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT21), 778 PINMUX_IPSR_MSEL(IP2_19_16, MSIOF3_SS2_B, SEL_MSIOF3_1), 779 PINMUX_IPSR_MSEL(IP2_19_16, SCK4_B, SEL_SCIF4_1), 780 PINMUX_IPSR_GPSR(IP2_19_16, VI4_DATA13), 781 PINMUX_IPSR_GPSR(IP2_19_16, VI5_DATA13), 782 PINMUX_IPSR_GPSR(IP2_19_16, DU_DB5), 783 784 PINMUX_IPSR_GPSR(IP2_23_20, A6), 785 PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT22), 786 PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_SS1_A, SEL_MSIOF2_0), 787 PINMUX_IPSR_MSEL(IP2_23_20, RX4_B, SEL_SCIF4_1), 788 PINMUX_IPSR_GPSR(IP2_23_20, VI4_DATA14), 789 PINMUX_IPSR_GPSR(IP2_23_20, VI5_DATA14), 790 PINMUX_IPSR_GPSR(IP2_23_20, DU_DB6), 791 792 PINMUX_IPSR_GPSR(IP2_27_24, A7), 793 PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT23), 794 PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SS2_A, SEL_MSIOF2_0), 795 PINMUX_IPSR_MSEL(IP2_27_24, TX4_B, SEL_SCIF4_1), 796 PINMUX_IPSR_GPSR(IP2_27_24, VI4_DATA15), 797 PINMUX_IPSR_GPSR(IP2_27_24, VI5_DATA15), 798 PINMUX_IPSR_GPSR(IP2_27_24, DU_DB7), 799 800 PINMUX_IPSR_GPSR(IP2_31_28, A8), 801 PINMUX_IPSR_MSEL(IP2_31_28, RX3_B, SEL_SCIF3_1), 802 PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0), 803 PINMUX_IPSR_MSEL(IP2_31_28, HRX4_B, SEL_HSCIF4_1), 804 PINMUX_IPSR_MSEL(IP2_31_28, SDA6_A, SEL_I2C6_0), 805 PINMUX_IPSR_MSEL(IP2_31_28, AVB_AVTP_MATCH_B, SEL_ETHERAVB_1), 806 PINMUX_IPSR_MSEL(IP2_31_28, PWM1_B, SEL_PWM1_1), 807 808 /* IPSR3 */ 809 PINMUX_IPSR_GPSR(IP3_3_0, A9), 810 PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0), 811 PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1), 812 PINMUX_IPSR_GPSR(IP3_3_0, VI5_VSYNC_N), 813 814 PINMUX_IPSR_GPSR(IP3_7_4, A10), 815 PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0), 816 PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_B, SEL_SCIF4_1), 817 PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N), 818 819 PINMUX_IPSR_GPSR(IP3_11_8, A11), 820 PINMUX_IPSR_MSEL(IP3_11_8, TX3_B, SEL_SCIF3_1), 821 PINMUX_IPSR_MSEL(IP3_11_8, MSIOF2_TXD_A, SEL_MSIOF2_0), 822 PINMUX_IPSR_MSEL(IP3_11_8, HTX4_B, SEL_HSCIF4_1), 823 PINMUX_IPSR_GPSR(IP3_11_8, HSCK4), 824 PINMUX_IPSR_GPSR(IP3_11_8, VI5_FIELD), 825 PINMUX_IPSR_MSEL(IP3_11_8, SCL6_A, SEL_I2C6_0), 826 PINMUX_IPSR_MSEL(IP3_11_8, AVB_AVTP_CAPTURE_B, SEL_ETHERAVB_1), 827 PINMUX_IPSR_MSEL(IP3_11_8, PWM2_B, SEL_PWM2_1), 828 829 PINMUX_IPSR_GPSR(IP3_15_12, A12), 830 PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT12), 831 PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SCK_C, SEL_MSIOF3_2), 832 PINMUX_IPSR_MSEL(IP3_15_12, HRX4_A, SEL_HSCIF4_0), 833 PINMUX_IPSR_GPSR(IP3_15_12, VI5_DATA8), 834 PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4), 835 836 PINMUX_IPSR_GPSR(IP3_19_16, A13), 837 PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT13), 838 PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SYNC_C, SEL_MSIOF3_2), 839 PINMUX_IPSR_MSEL(IP3_19_16, HTX4_A, SEL_HSCIF4_0), 840 PINMUX_IPSR_GPSR(IP3_19_16, VI5_DATA9), 841 PINMUX_IPSR_GPSR(IP3_19_16, DU_DG5), 842 843 PINMUX_IPSR_GPSR(IP3_23_20, A14), 844 PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT14), 845 PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_C, SEL_MSIOF3_2), 846 PINMUX_IPSR_GPSR(IP3_23_20, HCTS4_N), 847 PINMUX_IPSR_GPSR(IP3_23_20, VI5_DATA10), 848 PINMUX_IPSR_GPSR(IP3_23_20, DU_DG6), 849 850 PINMUX_IPSR_GPSR(IP3_27_24, A15), 851 PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT15), 852 PINMUX_IPSR_MSEL(IP3_27_24, MSIOF3_TXD_C, SEL_MSIOF3_2), 853 PINMUX_IPSR_GPSR(IP3_27_24, HRTS4_N), 854 PINMUX_IPSR_GPSR(IP3_27_24, VI5_DATA11), 855 PINMUX_IPSR_GPSR(IP3_27_24, DU_DG7), 856 857 PINMUX_IPSR_GPSR(IP3_31_28, A16), 858 PINMUX_IPSR_GPSR(IP3_31_28, LCDOUT8), 859 PINMUX_IPSR_GPSR(IP3_31_28, VI4_FIELD), 860 PINMUX_IPSR_GPSR(IP3_31_28, DU_DG0), 861 862 /* IPSR4 */ 863 PINMUX_IPSR_GPSR(IP4_3_0, A17), 864 PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT9), 865 PINMUX_IPSR_GPSR(IP4_3_0, VI4_VSYNC_N), 866 PINMUX_IPSR_GPSR(IP4_3_0, DU_DG1), 867 868 PINMUX_IPSR_GPSR(IP4_7_4, A18), 869 PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT10), 870 PINMUX_IPSR_GPSR(IP4_7_4, VI4_HSYNC_N), 871 PINMUX_IPSR_GPSR(IP4_7_4, DU_DG2), 872 873 PINMUX_IPSR_GPSR(IP4_11_8, A19), 874 PINMUX_IPSR_GPSR(IP4_11_8, LCDOUT11), 875 PINMUX_IPSR_GPSR(IP4_11_8, VI4_CLKENB), 876 PINMUX_IPSR_GPSR(IP4_11_8, DU_DG3), 877 878 PINMUX_IPSR_GPSR(IP4_15_12, CS0_N), 879 PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB), 880 881 PINMUX_IPSR_GPSR(IP4_19_16, CS1_N), 882 PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK), 883 PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1), 884 885 PINMUX_IPSR_GPSR(IP4_23_20, BS_N), 886 PINMUX_IPSR_GPSR(IP4_23_20, QSTVA_QVS), 887 PINMUX_IPSR_MSEL(IP4_23_20, MSIOF3_SCK_D, SEL_MSIOF3_3), 888 PINMUX_IPSR_GPSR(IP4_23_20, SCK3), 889 PINMUX_IPSR_GPSR(IP4_23_20, HSCK3), 890 PINMUX_IPSR_GPSR(IP4_23_20, CAN1_TX), 891 PINMUX_IPSR_GPSR(IP4_23_20, CANFD1_TX), 892 PINMUX_IPSR_MSEL(IP4_23_20, IETX_A, SEL_IEBUS_0), 893 894 PINMUX_IPSR_GPSR(IP4_27_24, RD_N), 895 PINMUX_IPSR_MSEL(IP4_27_24, MSIOF3_SYNC_D, SEL_MSIOF3_3), 896 PINMUX_IPSR_MSEL(IP4_27_24, RX3_A, SEL_SCIF3_0), 897 PINMUX_IPSR_MSEL(IP4_27_24, HRX3_A, SEL_HSCIF3_0), 898 PINMUX_IPSR_MSEL(IP4_27_24, CAN0_TX_A, SEL_RCAN0_0), 899 PINMUX_IPSR_MSEL(IP4_27_24, CANFD0_TX_A, SEL_CANFD0_0), 900 901 PINMUX_IPSR_GPSR(IP4_31_28, RD_WR_N), 902 PINMUX_IPSR_MSEL(IP4_31_28, MSIOF3_RXD_D, SEL_MSIOF3_3), 903 PINMUX_IPSR_MSEL(IP4_31_28, TX3_A, SEL_SCIF3_0), 904 PINMUX_IPSR_MSEL(IP4_31_28, HTX3_A, SEL_HSCIF3_0), 905 PINMUX_IPSR_MSEL(IP4_31_28, CAN0_RX_A, SEL_RCAN0_0), 906 PINMUX_IPSR_MSEL(IP4_31_28, CANFD0_RX_A, SEL_CANFD0_0), 907 908 /* IPSR5 */ 909 PINMUX_IPSR_GPSR(IP5_3_0, WE0_N), 910 PINMUX_IPSR_MSEL(IP5_3_0, MSIOF3_TXD_D, SEL_MSIOF3_3), 911 PINMUX_IPSR_GPSR(IP5_3_0, CTS3_N), 912 PINMUX_IPSR_GPSR(IP5_3_0, HCTS3_N), 913 PINMUX_IPSR_MSEL(IP5_3_0, SCL6_B, SEL_I2C6_1), 914 PINMUX_IPSR_GPSR(IP5_3_0, CAN_CLK), 915 PINMUX_IPSR_MSEL(IP5_3_0, IECLK_A, SEL_IEBUS_0), 916 917 PINMUX_IPSR_GPSR(IP5_7_4, WE1_N), 918 PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3), 919 PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N), 920 PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N), 921 PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1), 922 PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX), 923 PINMUX_IPSR_GPSR(IP5_7_4, CANFD1_RX), 924 PINMUX_IPSR_MSEL(IP5_7_4, IERX_A, SEL_IEBUS_0), 925 926 PINMUX_IPSR_MSEL(IP5_11_8, EX_WAIT0_A, SEL_LBSC_0), 927 PINMUX_IPSR_GPSR(IP5_11_8, QCLK), 928 PINMUX_IPSR_GPSR(IP5_11_8, VI4_CLK), 929 PINMUX_IPSR_GPSR(IP5_11_8, DU_DOTCLKOUT0), 930 931 PINMUX_IPSR_GPSR(IP5_15_12, D0), 932 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF2_SS1_B, SEL_MSIOF2_1), 933 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF3_SCK_A, SEL_MSIOF3_0), 934 PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA16), 935 PINMUX_IPSR_GPSR(IP5_15_12, VI5_DATA0), 936 937 PINMUX_IPSR_GPSR(IP5_19_16, D1), 938 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF2_SS2_B, SEL_MSIOF2_1), 939 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF3_SYNC_A, SEL_MSIOF3_0), 940 PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA17), 941 PINMUX_IPSR_GPSR(IP5_19_16, VI5_DATA1), 942 943 PINMUX_IPSR_GPSR(IP5_23_20, D2), 944 PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_RXD_A, SEL_MSIOF3_0), 945 PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA18), 946 PINMUX_IPSR_GPSR(IP5_23_20, VI5_DATA2), 947 948 PINMUX_IPSR_GPSR(IP5_27_24, D3), 949 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0), 950 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19), 951 PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3), 952 953 PINMUX_IPSR_GPSR(IP5_31_28, D4), 954 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF2_SCK_B, SEL_MSIOF2_1), 955 PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA20), 956 PINMUX_IPSR_GPSR(IP5_31_28, VI5_DATA4), 957 958 /* IPSR6 */ 959 PINMUX_IPSR_GPSR(IP6_3_0, D5), 960 PINMUX_IPSR_MSEL(IP6_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1), 961 PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA21), 962 PINMUX_IPSR_GPSR(IP6_3_0, VI5_DATA5), 963 964 PINMUX_IPSR_GPSR(IP6_7_4, D6), 965 PINMUX_IPSR_MSEL(IP6_7_4, MSIOF2_RXD_B, SEL_MSIOF2_1), 966 PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA22), 967 PINMUX_IPSR_GPSR(IP6_7_4, VI5_DATA6), 968 969 PINMUX_IPSR_GPSR(IP6_11_8, D7), 970 PINMUX_IPSR_MSEL(IP6_11_8, MSIOF2_TXD_B, SEL_MSIOF2_1), 971 PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA23), 972 PINMUX_IPSR_GPSR(IP6_11_8, VI5_DATA7), 973 974 PINMUX_IPSR_GPSR(IP6_15_12, D8), 975 PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT0), 976 PINMUX_IPSR_MSEL(IP6_15_12, MSIOF2_SCK_D, SEL_MSIOF2_3), 977 PINMUX_IPSR_MSEL(IP6_15_12, SCK4_C, SEL_SCIF4_2), 978 PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA0_A, SEL_VIN4_0), 979 PINMUX_IPSR_GPSR(IP6_15_12, DU_DR0), 980 981 PINMUX_IPSR_GPSR(IP6_19_16, D9), 982 PINMUX_IPSR_GPSR(IP6_19_16, LCDOUT1), 983 PINMUX_IPSR_MSEL(IP6_19_16, MSIOF2_SYNC_D, SEL_MSIOF2_3), 984 PINMUX_IPSR_MSEL(IP6_19_16, VI4_DATA1_A, SEL_VIN4_0), 985 PINMUX_IPSR_GPSR(IP6_19_16, DU_DR1), 986 987 PINMUX_IPSR_GPSR(IP6_23_20, D10), 988 PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT2), 989 PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_RXD_D, SEL_MSIOF2_3), 990 PINMUX_IPSR_MSEL(IP6_23_20, HRX3_B, SEL_HSCIF3_1), 991 PINMUX_IPSR_MSEL(IP6_23_20, VI4_DATA2_A, SEL_VIN4_0), 992 PINMUX_IPSR_MSEL(IP6_23_20, CTS4_N_C, SEL_SCIF4_2), 993 PINMUX_IPSR_GPSR(IP6_23_20, DU_DR2), 994 995 PINMUX_IPSR_GPSR(IP6_27_24, D11), 996 PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT3), 997 PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3), 998 PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1), 999 PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0), 1000 PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_C, SEL_SCIF4_2), 1001 PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3), 1002 1003 PINMUX_IPSR_GPSR(IP6_31_28, D12), 1004 PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT4), 1005 PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3), 1006 PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2), 1007 PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0), 1008 PINMUX_IPSR_GPSR(IP6_31_28, DU_DR4), 1009 1010 /* IPSR7 */ 1011 PINMUX_IPSR_GPSR(IP7_3_0, D13), 1012 PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT5), 1013 PINMUX_IPSR_MSEL(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3), 1014 PINMUX_IPSR_MSEL(IP7_3_0, TX4_C, SEL_SCIF4_2), 1015 PINMUX_IPSR_MSEL(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0), 1016 PINMUX_IPSR_GPSR(IP7_3_0, DU_DR5), 1017 1018 PINMUX_IPSR_GPSR(IP7_7_4, D14), 1019 PINMUX_IPSR_GPSR(IP7_7_4, LCDOUT6), 1020 PINMUX_IPSR_MSEL(IP7_7_4, MSIOF3_SS1_A, SEL_MSIOF3_0), 1021 PINMUX_IPSR_MSEL(IP7_7_4, HRX3_C, SEL_HSCIF3_2), 1022 PINMUX_IPSR_MSEL(IP7_7_4, VI4_DATA6_A, SEL_VIN4_0), 1023 PINMUX_IPSR_GPSR(IP7_7_4, DU_DR6), 1024 PINMUX_IPSR_MSEL(IP7_7_4, SCL6_C, SEL_I2C6_2), 1025 1026 PINMUX_IPSR_GPSR(IP7_11_8, D15), 1027 PINMUX_IPSR_GPSR(IP7_11_8, LCDOUT7), 1028 PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SS2_A, SEL_MSIOF3_0), 1029 PINMUX_IPSR_MSEL(IP7_11_8, HTX3_C, SEL_HSCIF3_2), 1030 PINMUX_IPSR_MSEL(IP7_11_8, VI4_DATA7_A, SEL_VIN4_0), 1031 PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7), 1032 PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2), 1033 1034 PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK), 1035 PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4), 1036 PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1), 1037 1038 PINMUX_IPSR_GPSR(IP7_23_20, SD0_CMD), 1039 PINMUX_IPSR_MSEL(IP7_23_20, MSIOF1_SYNC_E, SEL_MSIOF1_4), 1040 PINMUX_IPSR_MSEL(IP7_23_20, STP_IVCXO27_0_B, SEL_SSP1_0_1), 1041 1042 PINMUX_IPSR_GPSR(IP7_27_24, SD0_DAT0), 1043 PINMUX_IPSR_MSEL(IP7_27_24, MSIOF1_RXD_E, SEL_MSIOF1_4), 1044 PINMUX_IPSR_MSEL(IP7_27_24, TS_SCK0_B, SEL_TSIF0_1), 1045 PINMUX_IPSR_MSEL(IP7_27_24, STP_ISCLK_0_B, SEL_SSP1_0_1), 1046 1047 PINMUX_IPSR_GPSR(IP7_31_28, SD0_DAT1), 1048 PINMUX_IPSR_MSEL(IP7_31_28, MSIOF1_TXD_E, SEL_MSIOF1_4), 1049 PINMUX_IPSR_MSEL(IP7_31_28, TS_SPSYNC0_B, SEL_TSIF0_1), 1050 PINMUX_IPSR_MSEL(IP7_31_28, STP_ISSYNC_0_B, SEL_SSP1_0_1), 1051 1052 /* IPSR8 */ 1053 PINMUX_IPSR_GPSR(IP8_3_0, SD0_DAT2), 1054 PINMUX_IPSR_MSEL(IP8_3_0, MSIOF1_SS1_E, SEL_MSIOF1_4), 1055 PINMUX_IPSR_MSEL(IP8_3_0, TS_SDAT0_B, SEL_TSIF0_1), 1056 PINMUX_IPSR_MSEL(IP8_3_0, STP_ISD_0_B, SEL_SSP1_0_1), 1057 1058 PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT3), 1059 PINMUX_IPSR_MSEL(IP8_7_4, MSIOF1_SS2_E, SEL_MSIOF1_4), 1060 PINMUX_IPSR_MSEL(IP8_7_4, TS_SDEN0_B, SEL_TSIF0_1), 1061 PINMUX_IPSR_MSEL(IP8_7_4, STP_ISEN_0_B, SEL_SSP1_0_1), 1062 1063 PINMUX_IPSR_GPSR(IP8_11_8, SD1_CLK), 1064 PINMUX_IPSR_MSEL(IP8_11_8, MSIOF1_SCK_G, SEL_MSIOF1_6), 1065 PINMUX_IPSR_MSEL(IP8_11_8, SIM0_CLK_A, SEL_SIMCARD_0), 1066 1067 PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD), 1068 PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6), 1069 PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDF_1), 1070 PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0), 1071 PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1), 1072 1073 PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0), 1074 PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4), 1075 PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6), 1076 PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDF_1), 1077 PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1), 1078 PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1), 1079 1080 PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1), 1081 PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5), 1082 PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6), 1083 PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDF_1), 1084 PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1), 1085 PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1), 1086 1087 PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2), 1088 PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6), 1089 PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6), 1090 PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDF_1), 1091 PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1), 1092 PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1), 1093 1094 PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3), 1095 PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7), 1096 PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6), 1097 PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDF_1), 1098 PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1), 1099 PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1), 1100 1101 /* IPSR9 */ 1102 PINMUX_IPSR_GPSR(IP9_3_0, SD2_CLK), 1103 PINMUX_IPSR_GPSR(IP9_3_0, NFDATA8), 1104 1105 PINMUX_IPSR_GPSR(IP9_7_4, SD2_CMD), 1106 PINMUX_IPSR_GPSR(IP9_7_4, NFDATA9), 1107 1108 PINMUX_IPSR_GPSR(IP9_11_8, SD2_DAT0), 1109 PINMUX_IPSR_GPSR(IP9_11_8, NFDATA10), 1110 1111 PINMUX_IPSR_GPSR(IP9_15_12, SD2_DAT1), 1112 PINMUX_IPSR_GPSR(IP9_15_12, NFDATA11), 1113 1114 PINMUX_IPSR_GPSR(IP9_19_16, SD2_DAT2), 1115 PINMUX_IPSR_GPSR(IP9_19_16, NFDATA12), 1116 1117 PINMUX_IPSR_GPSR(IP9_23_20, SD2_DAT3), 1118 PINMUX_IPSR_GPSR(IP9_23_20, NFDATA13), 1119 1120 PINMUX_IPSR_GPSR(IP9_27_24, SD2_DS), 1121 PINMUX_IPSR_GPSR(IP9_27_24, NFALE), 1122 1123 PINMUX_IPSR_GPSR(IP9_31_28, SD3_CLK), 1124 PINMUX_IPSR_GPSR(IP9_31_28, NFWE_N), 1125 1126 /* IPSR10 */ 1127 PINMUX_IPSR_GPSR(IP10_3_0, SD3_CMD), 1128 PINMUX_IPSR_GPSR(IP10_3_0, NFRE_N), 1129 1130 PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT0), 1131 PINMUX_IPSR_GPSR(IP10_7_4, NFDATA0), 1132 1133 PINMUX_IPSR_GPSR(IP10_11_8, SD3_DAT1), 1134 PINMUX_IPSR_GPSR(IP10_11_8, NFDATA1), 1135 1136 PINMUX_IPSR_GPSR(IP10_15_12, SD3_DAT2), 1137 PINMUX_IPSR_GPSR(IP10_15_12, NFDATA2), 1138 1139 PINMUX_IPSR_GPSR(IP10_19_16, SD3_DAT3), 1140 PINMUX_IPSR_GPSR(IP10_19_16, NFDATA3), 1141 1142 PINMUX_IPSR_GPSR(IP10_23_20, SD3_DAT4), 1143 PINMUX_IPSR_MSEL(IP10_23_20, SD2_CD_A, SEL_SDHI2_0), 1144 PINMUX_IPSR_GPSR(IP10_23_20, NFDATA4), 1145 1146 PINMUX_IPSR_GPSR(IP10_27_24, SD3_DAT5), 1147 PINMUX_IPSR_MSEL(IP10_27_24, SD2_WP_A, SEL_SDHI2_0), 1148 PINMUX_IPSR_GPSR(IP10_27_24, NFDATA5), 1149 1150 PINMUX_IPSR_GPSR(IP10_31_28, SD3_DAT6), 1151 PINMUX_IPSR_GPSR(IP10_31_28, SD3_CD), 1152 PINMUX_IPSR_GPSR(IP10_31_28, NFDATA6), 1153 1154 /* IPSR11 */ 1155 PINMUX_IPSR_GPSR(IP11_3_0, SD3_DAT7), 1156 PINMUX_IPSR_GPSR(IP11_3_0, SD3_WP), 1157 PINMUX_IPSR_GPSR(IP11_3_0, NFDATA7), 1158 1159 PINMUX_IPSR_GPSR(IP11_7_4, SD3_DS), 1160 PINMUX_IPSR_GPSR(IP11_7_4, NFCLE), 1161 1162 PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD), 1163 PINMUX_IPSR_MSEL(IP11_11_8, NFDATA14_A, SEL_NDF_0), 1164 PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1), 1165 PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0), 1166 1167 PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP), 1168 PINMUX_IPSR_MSEL(IP11_15_12, NFDATA15_A, SEL_NDF_0), 1169 PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1), 1170 1171 PINMUX_IPSR_MSEL(IP11_19_16, SD1_CD, I2C_SEL_0_0), 1172 PINMUX_IPSR_PHYS_MSEL(IP11_19_16, NFRB_N_A, I2C_SEL_0_0, SEL_NDF_0), 1173 PINMUX_IPSR_PHYS_MSEL(IP11_19_16, SIM0_CLK_B, I2C_SEL_0_0, SEL_SIMCARD_1), 1174 PINMUX_IPSR_PHYS(IP11_19_16, SCL0, I2C_SEL_0_1), 1175 1176 PINMUX_IPSR_MSEL(IP11_23_20, SD1_WP, I2C_SEL_0_0), 1177 PINMUX_IPSR_PHYS_MSEL(IP11_23_20, NFCE_N_A, I2C_SEL_0_0, SEL_NDF_0), 1178 PINMUX_IPSR_PHYS_MSEL(IP11_23_20, SIM0_D_B, I2C_SEL_0_0, SEL_SIMCARD_1), 1179 PINMUX_IPSR_PHYS(IP11_23_20, SDA0, I2C_SEL_0_1), 1180 1181 PINMUX_IPSR_GPSR(IP11_27_24, SCK0), 1182 PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1), 1183 PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1), 1184 PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADGC_1), 1185 PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0), 1186 PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1), 1187 PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2), 1188 PINMUX_IPSR_MSEL(IP11_27_24, RIF0_CLK_B, SEL_DRIF0_1), 1189 PINMUX_IPSR_GPSR(IP11_27_24, ADICHS2), 1190 PINMUX_IPSR_MSEL(IP11_27_24, SCK5_B, SEL_SCIF5_1), 1191 1192 PINMUX_IPSR_GPSR(IP11_31_28, RX0), 1193 PINMUX_IPSR_MSEL(IP11_31_28, HRX1_B, SEL_HSCIF1_1), 1194 PINMUX_IPSR_MSEL(IP11_31_28, TS_SCK0_C, SEL_TSIF0_2), 1195 PINMUX_IPSR_MSEL(IP11_31_28, STP_ISCLK_0_C, SEL_SSP1_0_2), 1196 PINMUX_IPSR_MSEL(IP11_31_28, RIF0_D0_B, SEL_DRIF0_1), 1197 1198 /* IPSR12 */ 1199 PINMUX_IPSR_GPSR(IP12_3_0, TX0), 1200 PINMUX_IPSR_MSEL(IP12_3_0, HTX1_B, SEL_HSCIF1_1), 1201 PINMUX_IPSR_MSEL(IP12_3_0, TS_SPSYNC0_C, SEL_TSIF0_2), 1202 PINMUX_IPSR_MSEL(IP12_3_0, STP_ISSYNC_0_C, SEL_SSP1_0_2), 1203 PINMUX_IPSR_MSEL(IP12_3_0, RIF0_D1_B, SEL_DRIF0_1), 1204 1205 PINMUX_IPSR_GPSR(IP12_7_4, CTS0_N), 1206 PINMUX_IPSR_MSEL(IP12_7_4, HCTS1_N_B, SEL_HSCIF1_1), 1207 PINMUX_IPSR_MSEL(IP12_7_4, MSIOF1_SYNC_B, SEL_MSIOF1_1), 1208 PINMUX_IPSR_MSEL(IP12_7_4, TS_SPSYNC1_C, SEL_TSIF1_2), 1209 PINMUX_IPSR_MSEL(IP12_7_4, STP_ISSYNC_1_C, SEL_SSP1_1_2), 1210 PINMUX_IPSR_MSEL(IP12_7_4, RIF1_SYNC_B, SEL_DRIF1_1), 1211 PINMUX_IPSR_GPSR(IP12_7_4, AUDIO_CLKOUT_C), 1212 PINMUX_IPSR_GPSR(IP12_7_4, ADICS_SAMP), 1213 1214 PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N), 1215 PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1), 1216 PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1), 1217 PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADGA_1), 1218 PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0), 1219 PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2), 1220 PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1), 1221 PINMUX_IPSR_GPSR(IP12_11_8, ADICHS1), 1222 1223 PINMUX_IPSR_MSEL(IP12_15_12, RX1_A, SEL_SCIF1_0), 1224 PINMUX_IPSR_MSEL(IP12_15_12, HRX1_A, SEL_HSCIF1_0), 1225 PINMUX_IPSR_MSEL(IP12_15_12, TS_SDAT0_C, SEL_TSIF0_2), 1226 PINMUX_IPSR_MSEL(IP12_15_12, STP_ISD_0_C, SEL_SSP1_0_2), 1227 PINMUX_IPSR_MSEL(IP12_15_12, RIF1_CLK_C, SEL_DRIF1_2), 1228 1229 PINMUX_IPSR_MSEL(IP12_19_16, TX1_A, SEL_SCIF1_0), 1230 PINMUX_IPSR_MSEL(IP12_19_16, HTX1_A, SEL_HSCIF1_0), 1231 PINMUX_IPSR_MSEL(IP12_19_16, TS_SDEN0_C, SEL_TSIF0_2), 1232 PINMUX_IPSR_MSEL(IP12_19_16, STP_ISEN_0_C, SEL_SSP1_0_2), 1233 PINMUX_IPSR_MSEL(IP12_19_16, RIF1_D0_C, SEL_DRIF1_2), 1234 1235 PINMUX_IPSR_GPSR(IP12_23_20, CTS1_N), 1236 PINMUX_IPSR_MSEL(IP12_23_20, HCTS1_N_A, SEL_HSCIF1_0), 1237 PINMUX_IPSR_MSEL(IP12_23_20, MSIOF1_RXD_B, SEL_MSIOF1_1), 1238 PINMUX_IPSR_MSEL(IP12_23_20, TS_SDEN1_C, SEL_TSIF1_2), 1239 PINMUX_IPSR_MSEL(IP12_23_20, STP_ISEN_1_C, SEL_SSP1_1_2), 1240 PINMUX_IPSR_MSEL(IP12_23_20, RIF1_D0_B, SEL_DRIF1_1), 1241 PINMUX_IPSR_GPSR(IP12_23_20, ADIDATA), 1242 1243 PINMUX_IPSR_GPSR(IP12_27_24, RTS1_N), 1244 PINMUX_IPSR_MSEL(IP12_27_24, HRTS1_N_A, SEL_HSCIF1_0), 1245 PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1), 1246 PINMUX_IPSR_MSEL(IP12_27_24, TS_SDAT1_C, SEL_TSIF1_2), 1247 PINMUX_IPSR_MSEL(IP12_27_24, STP_ISD_1_C, SEL_SSP1_1_2), 1248 PINMUX_IPSR_MSEL(IP12_27_24, RIF1_D1_B, SEL_DRIF1_1), 1249 PINMUX_IPSR_GPSR(IP12_27_24, ADICHS0), 1250 1251 PINMUX_IPSR_GPSR(IP12_31_28, SCK2), 1252 PINMUX_IPSR_MSEL(IP12_31_28, SCIF_CLK_B, SEL_SCIF_1), 1253 PINMUX_IPSR_MSEL(IP12_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1), 1254 PINMUX_IPSR_MSEL(IP12_31_28, TS_SCK1_C, SEL_TSIF1_2), 1255 PINMUX_IPSR_MSEL(IP12_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2), 1256 PINMUX_IPSR_MSEL(IP12_31_28, RIF1_CLK_B, SEL_DRIF1_1), 1257 PINMUX_IPSR_GPSR(IP12_31_28, ADICLK), 1258 1259 /* IPSR13 */ 1260 PINMUX_IPSR_MSEL(IP13_3_0, TX2_A, SEL_SCIF2_0), 1261 PINMUX_IPSR_MSEL(IP13_3_0, SD2_CD_B, SEL_SDHI2_1), 1262 PINMUX_IPSR_MSEL(IP13_3_0, SCL1_A, SEL_I2C1_0), 1263 PINMUX_IPSR_MSEL(IP13_3_0, FMCLK_A, SEL_FM_0), 1264 PINMUX_IPSR_MSEL(IP13_3_0, RIF1_D1_C, SEL_DRIF1_2), 1265 PINMUX_IPSR_GPSR(IP13_3_0, FSO_CFE_0_N), 1266 1267 PINMUX_IPSR_MSEL(IP13_7_4, RX2_A, SEL_SCIF2_0), 1268 PINMUX_IPSR_MSEL(IP13_7_4, SD2_WP_B, SEL_SDHI2_1), 1269 PINMUX_IPSR_MSEL(IP13_7_4, SDA1_A, SEL_I2C1_0), 1270 PINMUX_IPSR_MSEL(IP13_7_4, FMIN_A, SEL_FM_0), 1271 PINMUX_IPSR_MSEL(IP13_7_4, RIF1_SYNC_C, SEL_DRIF1_2), 1272 PINMUX_IPSR_GPSR(IP13_7_4, FSO_CFE_1_N), 1273 1274 PINMUX_IPSR_GPSR(IP13_11_8, HSCK0), 1275 PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3), 1276 PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADGB_0), 1277 PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI1_1), 1278 PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3), 1279 PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3), 1280 PINMUX_IPSR_MSEL(IP13_11_8, RIF0_CLK_C, SEL_DRIF0_2), 1281 PINMUX_IPSR_MSEL(IP13_11_8, RX5_B, SEL_SCIF5_1), 1282 1283 PINMUX_IPSR_GPSR(IP13_15_12, HRX0), 1284 PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3), 1285 PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA2_B, SEL_SSI2_1), 1286 PINMUX_IPSR_MSEL(IP13_15_12, TS_SDEN0_D, SEL_TSIF0_3), 1287 PINMUX_IPSR_MSEL(IP13_15_12, STP_ISEN_0_D, SEL_SSP1_0_3), 1288 PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_C, SEL_DRIF0_2), 1289 1290 PINMUX_IPSR_GPSR(IP13_19_16, HTX0), 1291 PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3), 1292 PINMUX_IPSR_MSEL(IP13_19_16, SSI_SDATA9_B, SEL_SSI9_1), 1293 PINMUX_IPSR_MSEL(IP13_19_16, TS_SDAT0_D, SEL_TSIF0_3), 1294 PINMUX_IPSR_MSEL(IP13_19_16, STP_ISD_0_D, SEL_SSP1_0_3), 1295 PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_C, SEL_DRIF0_2), 1296 1297 PINMUX_IPSR_GPSR(IP13_23_20, HCTS0_N), 1298 PINMUX_IPSR_MSEL(IP13_23_20, RX2_B, SEL_SCIF2_1), 1299 PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3), 1300 PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK9_A, SEL_SSI9_0), 1301 PINMUX_IPSR_MSEL(IP13_23_20, TS_SPSYNC0_D, SEL_TSIF0_3), 1302 PINMUX_IPSR_MSEL(IP13_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3), 1303 PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_C, SEL_DRIF0_2), 1304 PINMUX_IPSR_GPSR(IP13_23_20, AUDIO_CLKOUT1_A), 1305 1306 PINMUX_IPSR_GPSR(IP13_27_24, HRTS0_N), 1307 PINMUX_IPSR_MSEL(IP13_27_24, TX2_B, SEL_SCIF2_1), 1308 PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3), 1309 PINMUX_IPSR_MSEL(IP13_27_24, SSI_WS9_A, SEL_SSI9_0), 1310 PINMUX_IPSR_MSEL(IP13_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3), 1311 PINMUX_IPSR_MSEL(IP13_27_24, BPFCLK_A, SEL_FM_0), 1312 PINMUX_IPSR_GPSR(IP13_27_24, AUDIO_CLKOUT2_A), 1313 1314 PINMUX_IPSR_GPSR(IP13_31_28, MSIOF0_SYNC), 1315 PINMUX_IPSR_GPSR(IP13_31_28, AUDIO_CLKOUT_A), 1316 PINMUX_IPSR_MSEL(IP13_31_28, TX5_B, SEL_SCIF5_1), 1317 PINMUX_IPSR_MSEL(IP13_31_28, BPFCLK_D, SEL_FM_3), 1318 1319 /* IPSR14 */ 1320 PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1), 1321 PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0), 1322 PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDF_0), 1323 PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADGA_2), 1324 PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0), 1325 PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2), 1326 PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A), 1327 PINMUX_IPSR_MSEL(IP14_3_0, TCLK1_B, SEL_TIMER_TMU_1), 1328 1329 PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2), 1330 PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0), 1331 PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3), 1332 PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADGC_0), 1333 PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI2_0), 1334 PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3), 1335 PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D), 1336 PINMUX_IPSR_MSEL(IP14_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1), 1337 1338 PINMUX_IPSR_GPSR(IP14_11_8, MLB_CLK), 1339 PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SCK_F, SEL_MSIOF1_5), 1340 PINMUX_IPSR_MSEL(IP14_11_8, SCL1_B, SEL_I2C1_1), 1341 1342 PINMUX_IPSR_GPSR(IP14_15_12, MLB_SIG), 1343 PINMUX_IPSR_MSEL(IP14_15_12, RX1_B, SEL_SCIF1_1), 1344 PINMUX_IPSR_MSEL(IP14_15_12, MSIOF1_SYNC_F, SEL_MSIOF1_5), 1345 PINMUX_IPSR_MSEL(IP14_15_12, SDA1_B, SEL_I2C1_1), 1346 1347 PINMUX_IPSR_GPSR(IP14_19_16, MLB_DAT), 1348 PINMUX_IPSR_MSEL(IP14_19_16, TX1_B, SEL_SCIF1_1), 1349 PINMUX_IPSR_MSEL(IP14_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5), 1350 1351 PINMUX_IPSR_GPSR(IP14_23_20, SSI_SCK01239), 1352 PINMUX_IPSR_MSEL(IP14_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5), 1353 1354 PINMUX_IPSR_GPSR(IP14_27_24, SSI_WS01239), 1355 PINMUX_IPSR_MSEL(IP14_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5), 1356 1357 PINMUX_IPSR_GPSR(IP14_31_28, SSI_SDATA0), 1358 PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5), 1359 1360 /* IPSR15 */ 1361 PINMUX_IPSR_MSEL(IP15_3_0, SSI_SDATA1_A, SEL_SSI1_0), 1362 1363 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SDATA2_A, SEL_SSI2_0), 1364 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SCK1_B, SEL_SSI1_1), 1365 1366 PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK349), 1367 PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0), 1368 PINMUX_IPSR_MSEL(IP15_11_8, STP_OPWM_0_A, SEL_SSP1_0_0), 1369 1370 PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS349), 1371 PINMUX_IPSR_MSEL(IP15_15_12, HCTS2_N_A, SEL_HSCIF2_0), 1372 PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0), 1373 PINMUX_IPSR_MSEL(IP15_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0), 1374 1375 PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA3), 1376 PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0), 1377 PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_TXD_A, SEL_MSIOF1_0), 1378 PINMUX_IPSR_MSEL(IP15_19_16, TS_SCK0_A, SEL_TSIF0_0), 1379 PINMUX_IPSR_MSEL(IP15_19_16, STP_ISCLK_0_A, SEL_SSP1_0_0), 1380 PINMUX_IPSR_MSEL(IP15_19_16, RIF0_D1_A, SEL_DRIF0_0), 1381 PINMUX_IPSR_MSEL(IP15_19_16, RIF2_D0_A, SEL_DRIF2_0), 1382 1383 PINMUX_IPSR_GPSR(IP15_23_20, SSI_SCK4), 1384 PINMUX_IPSR_MSEL(IP15_23_20, HRX2_A, SEL_HSCIF2_0), 1385 PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_SCK_A, SEL_MSIOF1_0), 1386 PINMUX_IPSR_MSEL(IP15_23_20, TS_SDAT0_A, SEL_TSIF0_0), 1387 PINMUX_IPSR_MSEL(IP15_23_20, STP_ISD_0_A, SEL_SSP1_0_0), 1388 PINMUX_IPSR_MSEL(IP15_23_20, RIF0_CLK_A, SEL_DRIF0_0), 1389 PINMUX_IPSR_MSEL(IP15_23_20, RIF2_CLK_A, SEL_DRIF2_0), 1390 1391 PINMUX_IPSR_GPSR(IP15_27_24, SSI_WS4), 1392 PINMUX_IPSR_MSEL(IP15_27_24, HTX2_A, SEL_HSCIF2_0), 1393 PINMUX_IPSR_MSEL(IP15_27_24, MSIOF1_SYNC_A, SEL_MSIOF1_0), 1394 PINMUX_IPSR_MSEL(IP15_27_24, TS_SDEN0_A, SEL_TSIF0_0), 1395 PINMUX_IPSR_MSEL(IP15_27_24, STP_ISEN_0_A, SEL_SSP1_0_0), 1396 PINMUX_IPSR_MSEL(IP15_27_24, RIF0_SYNC_A, SEL_DRIF0_0), 1397 PINMUX_IPSR_MSEL(IP15_27_24, RIF2_SYNC_A, SEL_DRIF2_0), 1398 1399 PINMUX_IPSR_GPSR(IP15_31_28, SSI_SDATA4), 1400 PINMUX_IPSR_MSEL(IP15_31_28, HSCK2_A, SEL_HSCIF2_0), 1401 PINMUX_IPSR_MSEL(IP15_31_28, MSIOF1_RXD_A, SEL_MSIOF1_0), 1402 PINMUX_IPSR_MSEL(IP15_31_28, TS_SPSYNC0_A, SEL_TSIF0_0), 1403 PINMUX_IPSR_MSEL(IP15_31_28, STP_ISSYNC_0_A, SEL_SSP1_0_0), 1404 PINMUX_IPSR_MSEL(IP15_31_28, RIF0_D0_A, SEL_DRIF0_0), 1405 PINMUX_IPSR_MSEL(IP15_31_28, RIF2_D1_A, SEL_DRIF2_0), 1406 1407 /* IPSR16 */ 1408 PINMUX_IPSR_GPSR(IP16_3_0, SSI_SCK6), 1409 PINMUX_IPSR_MSEL(IP16_3_0, SIM0_RST_D, SEL_SIMCARD_3), 1410 1411 PINMUX_IPSR_GPSR(IP16_7_4, SSI_WS6), 1412 PINMUX_IPSR_MSEL(IP16_7_4, SIM0_D_D, SEL_SIMCARD_3), 1413 1414 PINMUX_IPSR_GPSR(IP16_11_8, SSI_SDATA6), 1415 PINMUX_IPSR_MSEL(IP16_11_8, SIM0_CLK_D, SEL_SIMCARD_3), 1416 1417 PINMUX_IPSR_GPSR(IP16_15_12, SSI_SCK78), 1418 PINMUX_IPSR_MSEL(IP16_15_12, HRX2_B, SEL_HSCIF2_1), 1419 PINMUX_IPSR_MSEL(IP16_15_12, MSIOF1_SCK_C, SEL_MSIOF1_2), 1420 PINMUX_IPSR_MSEL(IP16_15_12, TS_SCK1_A, SEL_TSIF1_0), 1421 PINMUX_IPSR_MSEL(IP16_15_12, STP_ISCLK_1_A, SEL_SSP1_1_0), 1422 PINMUX_IPSR_MSEL(IP16_15_12, RIF1_CLK_A, SEL_DRIF1_0), 1423 PINMUX_IPSR_MSEL(IP16_15_12, RIF3_CLK_A, SEL_DRIF3_0), 1424 1425 PINMUX_IPSR_GPSR(IP16_19_16, SSI_WS78), 1426 PINMUX_IPSR_MSEL(IP16_19_16, HTX2_B, SEL_HSCIF2_1), 1427 PINMUX_IPSR_MSEL(IP16_19_16, MSIOF1_SYNC_C, SEL_MSIOF1_2), 1428 PINMUX_IPSR_MSEL(IP16_19_16, TS_SDAT1_A, SEL_TSIF1_0), 1429 PINMUX_IPSR_MSEL(IP16_19_16, STP_ISD_1_A, SEL_SSP1_1_0), 1430 PINMUX_IPSR_MSEL(IP16_19_16, RIF1_SYNC_A, SEL_DRIF1_0), 1431 PINMUX_IPSR_MSEL(IP16_19_16, RIF3_SYNC_A, SEL_DRIF3_0), 1432 1433 PINMUX_IPSR_GPSR(IP16_23_20, SSI_SDATA7), 1434 PINMUX_IPSR_MSEL(IP16_23_20, HCTS2_N_B, SEL_HSCIF2_1), 1435 PINMUX_IPSR_MSEL(IP16_23_20, MSIOF1_RXD_C, SEL_MSIOF1_2), 1436 PINMUX_IPSR_MSEL(IP16_23_20, TS_SDEN1_A, SEL_TSIF1_0), 1437 PINMUX_IPSR_MSEL(IP16_23_20, STP_ISEN_1_A, SEL_SSP1_1_0), 1438 PINMUX_IPSR_MSEL(IP16_23_20, RIF1_D0_A, SEL_DRIF1_0), 1439 PINMUX_IPSR_MSEL(IP16_23_20, RIF3_D0_A, SEL_DRIF3_0), 1440 PINMUX_IPSR_MSEL(IP16_23_20, TCLK2_A, SEL_TIMER_TMU2_0), 1441 1442 PINMUX_IPSR_GPSR(IP16_27_24, SSI_SDATA8), 1443 PINMUX_IPSR_MSEL(IP16_27_24, HRTS2_N_B, SEL_HSCIF2_1), 1444 PINMUX_IPSR_MSEL(IP16_27_24, MSIOF1_TXD_C, SEL_MSIOF1_2), 1445 PINMUX_IPSR_MSEL(IP16_27_24, TS_SPSYNC1_A, SEL_TSIF1_0), 1446 PINMUX_IPSR_MSEL(IP16_27_24, STP_ISSYNC_1_A, SEL_SSP1_1_0), 1447 PINMUX_IPSR_MSEL(IP16_27_24, RIF1_D1_A, SEL_DRIF1_0), 1448 PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D1_A, SEL_DRIF3_0), 1449 1450 PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA9_A, SEL_SSI9_0), 1451 PINMUX_IPSR_MSEL(IP16_31_28, HSCK2_B, SEL_HSCIF2_1), 1452 PINMUX_IPSR_MSEL(IP16_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2), 1453 PINMUX_IPSR_MSEL(IP16_31_28, HSCK1_A, SEL_HSCIF1_0), 1454 PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI1_1), 1455 PINMUX_IPSR_GPSR(IP16_31_28, SCK1), 1456 PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0), 1457 PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0), 1458 1459 /* IPSR17 */ 1460 PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADGA_0), 1461 1462 PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADGB_1), 1463 PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0), 1464 PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3), 1465 PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0), 1466 PINMUX_IPSR_MSEL(IP17_7_4, TCLK1_A, SEL_TIMER_TMU_0), 1467 1468 PINMUX_IPSR_GPSR(IP17_11_8, USB0_PWEN), 1469 PINMUX_IPSR_MSEL(IP17_11_8, SIM0_RST_C, SEL_SIMCARD_2), 1470 PINMUX_IPSR_MSEL(IP17_11_8, TS_SCK1_D, SEL_TSIF1_3), 1471 PINMUX_IPSR_MSEL(IP17_11_8, STP_ISCLK_1_D, SEL_SSP1_1_3), 1472 PINMUX_IPSR_MSEL(IP17_11_8, BPFCLK_B, SEL_FM_1), 1473 PINMUX_IPSR_MSEL(IP17_11_8, RIF3_CLK_B, SEL_DRIF3_1), 1474 PINMUX_IPSR_MSEL(IP17_11_8, HSCK2_C, SEL_HSCIF2_2), 1475 1476 PINMUX_IPSR_GPSR(IP17_15_12, USB0_OVC), 1477 PINMUX_IPSR_MSEL(IP17_15_12, SIM0_D_C, SEL_SIMCARD_2), 1478 PINMUX_IPSR_MSEL(IP17_15_12, TS_SDAT1_D, SEL_TSIF1_3), 1479 PINMUX_IPSR_MSEL(IP17_15_12, STP_ISD_1_D, SEL_SSP1_1_3), 1480 PINMUX_IPSR_MSEL(IP17_15_12, RIF3_SYNC_B, SEL_DRIF3_1), 1481 PINMUX_IPSR_MSEL(IP17_15_12, HRX2_C, SEL_HSCIF2_2), 1482 1483 PINMUX_IPSR_GPSR(IP17_19_16, USB1_PWEN), 1484 PINMUX_IPSR_MSEL(IP17_19_16, SIM0_CLK_C, SEL_SIMCARD_2), 1485 PINMUX_IPSR_MSEL(IP17_19_16, SSI_SCK1_A, SEL_SSI1_0), 1486 PINMUX_IPSR_MSEL(IP17_19_16, TS_SCK0_E, SEL_TSIF0_4), 1487 PINMUX_IPSR_MSEL(IP17_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4), 1488 PINMUX_IPSR_MSEL(IP17_19_16, FMCLK_B, SEL_FM_1), 1489 PINMUX_IPSR_MSEL(IP17_19_16, RIF2_CLK_B, SEL_DRIF2_1), 1490 PINMUX_IPSR_MSEL(IP17_19_16, SPEEDIN_A, SEL_SPEED_PULSE_0), 1491 PINMUX_IPSR_MSEL(IP17_19_16, HTX2_C, SEL_HSCIF2_2), 1492 1493 PINMUX_IPSR_GPSR(IP17_23_20, USB1_OVC), 1494 PINMUX_IPSR_MSEL(IP17_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2), 1495 PINMUX_IPSR_MSEL(IP17_23_20, SSI_WS1_A, SEL_SSI1_0), 1496 PINMUX_IPSR_MSEL(IP17_23_20, TS_SDAT0_E, SEL_TSIF0_4), 1497 PINMUX_IPSR_MSEL(IP17_23_20, STP_ISD_0_E, SEL_SSP1_0_4), 1498 PINMUX_IPSR_MSEL(IP17_23_20, FMIN_B, SEL_FM_1), 1499 PINMUX_IPSR_MSEL(IP17_23_20, RIF2_SYNC_B, SEL_DRIF2_1), 1500 PINMUX_IPSR_MSEL(IP17_23_20, REMOCON_B, SEL_REMOCON_1), 1501 PINMUX_IPSR_MSEL(IP17_23_20, HCTS2_N_C, SEL_HSCIF2_2), 1502 1503 PINMUX_IPSR_GPSR(IP17_27_24, USB30_PWEN), 1504 PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_B), 1505 PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI2_1), 1506 PINMUX_IPSR_MSEL(IP17_27_24, TS_SDEN1_D, SEL_TSIF1_3), 1507 PINMUX_IPSR_MSEL(IP17_27_24, STP_ISEN_1_D, SEL_SSP1_1_3), 1508 PINMUX_IPSR_MSEL(IP17_27_24, STP_OPWM_0_E, SEL_SSP1_0_4), 1509 PINMUX_IPSR_MSEL(IP17_27_24, RIF3_D0_B, SEL_DRIF3_1), 1510 PINMUX_IPSR_MSEL(IP17_27_24, TCLK2_B, SEL_TIMER_TMU2_1), 1511 PINMUX_IPSR_GPSR(IP17_27_24, TPU0TO0), 1512 PINMUX_IPSR_MSEL(IP17_27_24, BPFCLK_C, SEL_FM_2), 1513 PINMUX_IPSR_MSEL(IP17_27_24, HRTS2_N_C, SEL_HSCIF2_2), 1514 1515 PINMUX_IPSR_GPSR(IP17_31_28, USB30_OVC), 1516 PINMUX_IPSR_GPSR(IP17_31_28, AUDIO_CLKOUT1_B), 1517 PINMUX_IPSR_MSEL(IP17_31_28, SSI_WS2_B, SEL_SSI2_1), 1518 PINMUX_IPSR_MSEL(IP17_31_28, TS_SPSYNC1_D, SEL_TSIF1_3), 1519 PINMUX_IPSR_MSEL(IP17_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3), 1520 PINMUX_IPSR_MSEL(IP17_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4), 1521 PINMUX_IPSR_MSEL(IP17_31_28, RIF3_D1_B, SEL_DRIF3_1), 1522 PINMUX_IPSR_GPSR(IP17_31_28, FSO_TOE_N), 1523 PINMUX_IPSR_GPSR(IP17_31_28, TPU0TO1), 1524 1525 /* IPSR18 */ 1526 PINMUX_IPSR_GPSR(IP18_3_0, GP6_30), 1527 PINMUX_IPSR_GPSR(IP18_3_0, AUDIO_CLKOUT2_B), 1528 PINMUX_IPSR_MSEL(IP18_3_0, SSI_SCK9_B, SEL_SSI9_1), 1529 PINMUX_IPSR_MSEL(IP18_3_0, TS_SDEN0_E, SEL_TSIF0_4), 1530 PINMUX_IPSR_MSEL(IP18_3_0, STP_ISEN_0_E, SEL_SSP1_0_4), 1531 PINMUX_IPSR_MSEL(IP18_3_0, RIF2_D0_B, SEL_DRIF2_1), 1532 PINMUX_IPSR_GPSR(IP18_3_0, TPU0TO2), 1533 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_C, SEL_FM_2), 1534 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_D, SEL_FM_3), 1535 1536 PINMUX_IPSR_GPSR(IP18_7_4, GP6_31), 1537 PINMUX_IPSR_GPSR(IP18_7_4, AUDIO_CLKOUT3_B), 1538 PINMUX_IPSR_MSEL(IP18_7_4, SSI_WS9_B, SEL_SSI9_1), 1539 PINMUX_IPSR_MSEL(IP18_7_4, TS_SPSYNC0_E, SEL_TSIF0_4), 1540 PINMUX_IPSR_MSEL(IP18_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4), 1541 PINMUX_IPSR_MSEL(IP18_7_4, RIF2_D1_B, SEL_DRIF2_1), 1542 PINMUX_IPSR_GPSR(IP18_7_4, TPU0TO3), 1543 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_C, SEL_FM_2), 1544 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_D, SEL_FM_3), 1545 1546 /* 1547 * Static pins can not be muxed between different functions but 1548 * still need mark entries in the pinmux list. Add each static 1549 * pin to the list without an associated function. The sh-pfc 1550 * core will do the right thing and skip trying to mux the pin 1551 * while still applying configuration to it. 1552 */ 1553 #define FM(x) PINMUX_DATA(x##_MARK, 0), 1554 PINMUX_STATIC 1555 #undef FM 1556 }; 1557 1558 /* 1559 * Pins not associated with a GPIO port. 1560 */ 1561 enum { 1562 GP_ASSIGN_LAST(), 1563 NOGP_ALL(), 1564 }; 1565 1566 static const struct sh_pfc_pin pinmux_pins[] = { 1567 PINMUX_GPIO_GP_ALL(), 1568 PINMUX_NOGP_ALL(), 1569 }; 1570 1571 /* - AUDIO CLOCK ------------------------------------------------------------ */ 1572 static const unsigned int audio_clk_a_a_pins[] = { 1573 /* CLK A */ 1574 RCAR_GP_PIN(6, 22), 1575 }; 1576 static const unsigned int audio_clk_a_a_mux[] = { 1577 AUDIO_CLKA_A_MARK, 1578 }; 1579 static const unsigned int audio_clk_a_b_pins[] = { 1580 /* CLK A */ 1581 RCAR_GP_PIN(5, 4), 1582 }; 1583 static const unsigned int audio_clk_a_b_mux[] = { 1584 AUDIO_CLKA_B_MARK, 1585 }; 1586 static const unsigned int audio_clk_a_c_pins[] = { 1587 /* CLK A */ 1588 RCAR_GP_PIN(5, 19), 1589 }; 1590 static const unsigned int audio_clk_a_c_mux[] = { 1591 AUDIO_CLKA_C_MARK, 1592 }; 1593 static const unsigned int audio_clk_b_a_pins[] = { 1594 /* CLK B */ 1595 RCAR_GP_PIN(5, 12), 1596 }; 1597 static const unsigned int audio_clk_b_a_mux[] = { 1598 AUDIO_CLKB_A_MARK, 1599 }; 1600 static const unsigned int audio_clk_b_b_pins[] = { 1601 /* CLK B */ 1602 RCAR_GP_PIN(6, 23), 1603 }; 1604 static const unsigned int audio_clk_b_b_mux[] = { 1605 AUDIO_CLKB_B_MARK, 1606 }; 1607 static const unsigned int audio_clk_c_a_pins[] = { 1608 /* CLK C */ 1609 RCAR_GP_PIN(5, 21), 1610 }; 1611 static const unsigned int audio_clk_c_a_mux[] = { 1612 AUDIO_CLKC_A_MARK, 1613 }; 1614 static const unsigned int audio_clk_c_b_pins[] = { 1615 /* CLK C */ 1616 RCAR_GP_PIN(5, 0), 1617 }; 1618 static const unsigned int audio_clk_c_b_mux[] = { 1619 AUDIO_CLKC_B_MARK, 1620 }; 1621 static const unsigned int audio_clkout_a_pins[] = { 1622 /* CLKOUT */ 1623 RCAR_GP_PIN(5, 18), 1624 }; 1625 static const unsigned int audio_clkout_a_mux[] = { 1626 AUDIO_CLKOUT_A_MARK, 1627 }; 1628 static const unsigned int audio_clkout_b_pins[] = { 1629 /* CLKOUT */ 1630 RCAR_GP_PIN(6, 28), 1631 }; 1632 static const unsigned int audio_clkout_b_mux[] = { 1633 AUDIO_CLKOUT_B_MARK, 1634 }; 1635 static const unsigned int audio_clkout_c_pins[] = { 1636 /* CLKOUT */ 1637 RCAR_GP_PIN(5, 3), 1638 }; 1639 static const unsigned int audio_clkout_c_mux[] = { 1640 AUDIO_CLKOUT_C_MARK, 1641 }; 1642 static const unsigned int audio_clkout_d_pins[] = { 1643 /* CLKOUT */ 1644 RCAR_GP_PIN(5, 21), 1645 }; 1646 static const unsigned int audio_clkout_d_mux[] = { 1647 AUDIO_CLKOUT_D_MARK, 1648 }; 1649 static const unsigned int audio_clkout1_a_pins[] = { 1650 /* CLKOUT1 */ 1651 RCAR_GP_PIN(5, 15), 1652 }; 1653 static const unsigned int audio_clkout1_a_mux[] = { 1654 AUDIO_CLKOUT1_A_MARK, 1655 }; 1656 static const unsigned int audio_clkout1_b_pins[] = { 1657 /* CLKOUT1 */ 1658 RCAR_GP_PIN(6, 29), 1659 }; 1660 static const unsigned int audio_clkout1_b_mux[] = { 1661 AUDIO_CLKOUT1_B_MARK, 1662 }; 1663 static const unsigned int audio_clkout2_a_pins[] = { 1664 /* CLKOUT2 */ 1665 RCAR_GP_PIN(5, 16), 1666 }; 1667 static const unsigned int audio_clkout2_a_mux[] = { 1668 AUDIO_CLKOUT2_A_MARK, 1669 }; 1670 static const unsigned int audio_clkout2_b_pins[] = { 1671 /* CLKOUT2 */ 1672 RCAR_GP_PIN(6, 30), 1673 }; 1674 static const unsigned int audio_clkout2_b_mux[] = { 1675 AUDIO_CLKOUT2_B_MARK, 1676 }; 1677 1678 static const unsigned int audio_clkout3_a_pins[] = { 1679 /* CLKOUT3 */ 1680 RCAR_GP_PIN(5, 19), 1681 }; 1682 static const unsigned int audio_clkout3_a_mux[] = { 1683 AUDIO_CLKOUT3_A_MARK, 1684 }; 1685 static const unsigned int audio_clkout3_b_pins[] = { 1686 /* CLKOUT3 */ 1687 RCAR_GP_PIN(6, 31), 1688 }; 1689 static const unsigned int audio_clkout3_b_mux[] = { 1690 AUDIO_CLKOUT3_B_MARK, 1691 }; 1692 1693 /* - EtherAVB --------------------------------------------------------------- */ 1694 static const unsigned int avb_link_pins[] = { 1695 /* AVB_LINK */ 1696 RCAR_GP_PIN(2, 12), 1697 }; 1698 static const unsigned int avb_link_mux[] = { 1699 AVB_LINK_MARK, 1700 }; 1701 static const unsigned int avb_magic_pins[] = { 1702 /* AVB_MAGIC_ */ 1703 RCAR_GP_PIN(2, 10), 1704 }; 1705 static const unsigned int avb_magic_mux[] = { 1706 AVB_MAGIC_MARK, 1707 }; 1708 static const unsigned int avb_phy_int_pins[] = { 1709 /* AVB_PHY_INT */ 1710 RCAR_GP_PIN(2, 11), 1711 }; 1712 static const unsigned int avb_phy_int_mux[] = { 1713 AVB_PHY_INT_MARK, 1714 }; 1715 static const unsigned int avb_mdio_pins[] = { 1716 /* AVB_MDC, AVB_MDIO */ 1717 RCAR_GP_PIN(2, 9), PIN_AVB_MDIO, 1718 }; 1719 static const unsigned int avb_mdio_mux[] = { 1720 AVB_MDC_MARK, AVB_MDIO_MARK, 1721 }; 1722 static const unsigned int avb_mii_pins[] = { 1723 /* 1724 * AVB_TX_CTL, AVB_TXC, AVB_TD0, 1725 * AVB_TD1, AVB_TD2, AVB_TD3, 1726 * AVB_RX_CTL, AVB_RXC, AVB_RD0, 1727 * AVB_RD1, AVB_RD2, AVB_RD3, 1728 * AVB_TXCREFCLK 1729 */ 1730 PIN_AVB_TX_CTL, PIN_AVB_TXC, PIN_AVB_TD0, 1731 PIN_AVB_TD1, PIN_AVB_TD2, PIN_AVB_TD3, 1732 PIN_AVB_RX_CTL, PIN_AVB_RXC, PIN_AVB_RD0, 1733 PIN_AVB_RD1, PIN_AVB_RD2, PIN_AVB_RD3, 1734 PIN_AVB_TXCREFCLK, 1735 1736 }; 1737 static const unsigned int avb_mii_mux[] = { 1738 AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK, 1739 AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK, 1740 AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK, 1741 AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK, 1742 AVB_TXCREFCLK_MARK, 1743 }; 1744 static const unsigned int avb_avtp_pps_pins[] = { 1745 /* AVB_AVTP_PPS */ 1746 RCAR_GP_PIN(2, 6), 1747 }; 1748 static const unsigned int avb_avtp_pps_mux[] = { 1749 AVB_AVTP_PPS_MARK, 1750 }; 1751 static const unsigned int avb_avtp_match_a_pins[] = { 1752 /* AVB_AVTP_MATCH_A */ 1753 RCAR_GP_PIN(2, 13), 1754 }; 1755 static const unsigned int avb_avtp_match_a_mux[] = { 1756 AVB_AVTP_MATCH_A_MARK, 1757 }; 1758 static const unsigned int avb_avtp_capture_a_pins[] = { 1759 /* AVB_AVTP_CAPTURE_A */ 1760 RCAR_GP_PIN(2, 14), 1761 }; 1762 static const unsigned int avb_avtp_capture_a_mux[] = { 1763 AVB_AVTP_CAPTURE_A_MARK, 1764 }; 1765 static const unsigned int avb_avtp_match_b_pins[] = { 1766 /* AVB_AVTP_MATCH_B */ 1767 RCAR_GP_PIN(1, 8), 1768 }; 1769 static const unsigned int avb_avtp_match_b_mux[] = { 1770 AVB_AVTP_MATCH_B_MARK, 1771 }; 1772 static const unsigned int avb_avtp_capture_b_pins[] = { 1773 /* AVB_AVTP_CAPTURE_B */ 1774 RCAR_GP_PIN(1, 11), 1775 }; 1776 static const unsigned int avb_avtp_capture_b_mux[] = { 1777 AVB_AVTP_CAPTURE_B_MARK, 1778 }; 1779 1780 /* - CAN ------------------------------------------------------------------ */ 1781 static const unsigned int can0_data_a_pins[] = { 1782 /* TX, RX */ 1783 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24), 1784 }; 1785 static const unsigned int can0_data_a_mux[] = { 1786 CAN0_TX_A_MARK, CAN0_RX_A_MARK, 1787 }; 1788 static const unsigned int can0_data_b_pins[] = { 1789 /* TX, RX */ 1790 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), 1791 }; 1792 static const unsigned int can0_data_b_mux[] = { 1793 CAN0_TX_B_MARK, CAN0_RX_B_MARK, 1794 }; 1795 static const unsigned int can1_data_pins[] = { 1796 /* TX, RX */ 1797 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26), 1798 }; 1799 static const unsigned int can1_data_mux[] = { 1800 CAN1_TX_MARK, CAN1_RX_MARK, 1801 }; 1802 1803 /* - CAN Clock -------------------------------------------------------------- */ 1804 static const unsigned int can_clk_pins[] = { 1805 /* CLK */ 1806 RCAR_GP_PIN(1, 25), 1807 }; 1808 static const unsigned int can_clk_mux[] = { 1809 CAN_CLK_MARK, 1810 }; 1811 1812 /* - CAN FD --------------------------------------------------------------- */ 1813 static const unsigned int canfd0_data_a_pins[] = { 1814 /* TX, RX */ 1815 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24), 1816 }; 1817 static const unsigned int canfd0_data_a_mux[] = { 1818 CANFD0_TX_A_MARK, CANFD0_RX_A_MARK, 1819 }; 1820 static const unsigned int canfd0_data_b_pins[] = { 1821 /* TX, RX */ 1822 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), 1823 }; 1824 static const unsigned int canfd0_data_b_mux[] = { 1825 CANFD0_TX_B_MARK, CANFD0_RX_B_MARK, 1826 }; 1827 static const unsigned int canfd1_data_pins[] = { 1828 /* TX, RX */ 1829 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26), 1830 }; 1831 static const unsigned int canfd1_data_mux[] = { 1832 CANFD1_TX_MARK, CANFD1_RX_MARK, 1833 }; 1834 1835 /* - DRIF0 --------------------------------------------------------------- */ 1836 static const unsigned int drif0_ctrl_a_pins[] = { 1837 /* CLK, SYNC */ 1838 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), 1839 }; 1840 static const unsigned int drif0_ctrl_a_mux[] = { 1841 RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK, 1842 }; 1843 static const unsigned int drif0_data0_a_pins[] = { 1844 /* D0 */ 1845 RCAR_GP_PIN(6, 10), 1846 }; 1847 static const unsigned int drif0_data0_a_mux[] = { 1848 RIF0_D0_A_MARK, 1849 }; 1850 static const unsigned int drif0_data1_a_pins[] = { 1851 /* D1 */ 1852 RCAR_GP_PIN(6, 7), 1853 }; 1854 static const unsigned int drif0_data1_a_mux[] = { 1855 RIF0_D1_A_MARK, 1856 }; 1857 static const unsigned int drif0_ctrl_b_pins[] = { 1858 /* CLK, SYNC */ 1859 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4), 1860 }; 1861 static const unsigned int drif0_ctrl_b_mux[] = { 1862 RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK, 1863 }; 1864 static const unsigned int drif0_data0_b_pins[] = { 1865 /* D0 */ 1866 RCAR_GP_PIN(5, 1), 1867 }; 1868 static const unsigned int drif0_data0_b_mux[] = { 1869 RIF0_D0_B_MARK, 1870 }; 1871 static const unsigned int drif0_data1_b_pins[] = { 1872 /* D1 */ 1873 RCAR_GP_PIN(5, 2), 1874 }; 1875 static const unsigned int drif0_data1_b_mux[] = { 1876 RIF0_D1_B_MARK, 1877 }; 1878 static const unsigned int drif0_ctrl_c_pins[] = { 1879 /* CLK, SYNC */ 1880 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15), 1881 }; 1882 static const unsigned int drif0_ctrl_c_mux[] = { 1883 RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK, 1884 }; 1885 static const unsigned int drif0_data0_c_pins[] = { 1886 /* D0 */ 1887 RCAR_GP_PIN(5, 13), 1888 }; 1889 static const unsigned int drif0_data0_c_mux[] = { 1890 RIF0_D0_C_MARK, 1891 }; 1892 static const unsigned int drif0_data1_c_pins[] = { 1893 /* D1 */ 1894 RCAR_GP_PIN(5, 14), 1895 }; 1896 static const unsigned int drif0_data1_c_mux[] = { 1897 RIF0_D1_C_MARK, 1898 }; 1899 /* - DRIF1 --------------------------------------------------------------- */ 1900 static const unsigned int drif1_ctrl_a_pins[] = { 1901 /* CLK, SYNC */ 1902 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18), 1903 }; 1904 static const unsigned int drif1_ctrl_a_mux[] = { 1905 RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK, 1906 }; 1907 static const unsigned int drif1_data0_a_pins[] = { 1908 /* D0 */ 1909 RCAR_GP_PIN(6, 19), 1910 }; 1911 static const unsigned int drif1_data0_a_mux[] = { 1912 RIF1_D0_A_MARK, 1913 }; 1914 static const unsigned int drif1_data1_a_pins[] = { 1915 /* D1 */ 1916 RCAR_GP_PIN(6, 20), 1917 }; 1918 static const unsigned int drif1_data1_a_mux[] = { 1919 RIF1_D1_A_MARK, 1920 }; 1921 static const unsigned int drif1_ctrl_b_pins[] = { 1922 /* CLK, SYNC */ 1923 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3), 1924 }; 1925 static const unsigned int drif1_ctrl_b_mux[] = { 1926 RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK, 1927 }; 1928 static const unsigned int drif1_data0_b_pins[] = { 1929 /* D0 */ 1930 RCAR_GP_PIN(5, 7), 1931 }; 1932 static const unsigned int drif1_data0_b_mux[] = { 1933 RIF1_D0_B_MARK, 1934 }; 1935 static const unsigned int drif1_data1_b_pins[] = { 1936 /* D1 */ 1937 RCAR_GP_PIN(5, 8), 1938 }; 1939 static const unsigned int drif1_data1_b_mux[] = { 1940 RIF1_D1_B_MARK, 1941 }; 1942 static const unsigned int drif1_ctrl_c_pins[] = { 1943 /* CLK, SYNC */ 1944 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11), 1945 }; 1946 static const unsigned int drif1_ctrl_c_mux[] = { 1947 RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK, 1948 }; 1949 static const unsigned int drif1_data0_c_pins[] = { 1950 /* D0 */ 1951 RCAR_GP_PIN(5, 6), 1952 }; 1953 static const unsigned int drif1_data0_c_mux[] = { 1954 RIF1_D0_C_MARK, 1955 }; 1956 static const unsigned int drif1_data1_c_pins[] = { 1957 /* D1 */ 1958 RCAR_GP_PIN(5, 10), 1959 }; 1960 static const unsigned int drif1_data1_c_mux[] = { 1961 RIF1_D1_C_MARK, 1962 }; 1963 /* - DRIF2 --------------------------------------------------------------- */ 1964 static const unsigned int drif2_ctrl_a_pins[] = { 1965 /* CLK, SYNC */ 1966 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), 1967 }; 1968 static const unsigned int drif2_ctrl_a_mux[] = { 1969 RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK, 1970 }; 1971 static const unsigned int drif2_data0_a_pins[] = { 1972 /* D0 */ 1973 RCAR_GP_PIN(6, 7), 1974 }; 1975 static const unsigned int drif2_data0_a_mux[] = { 1976 RIF2_D0_A_MARK, 1977 }; 1978 static const unsigned int drif2_data1_a_pins[] = { 1979 /* D1 */ 1980 RCAR_GP_PIN(6, 10), 1981 }; 1982 static const unsigned int drif2_data1_a_mux[] = { 1983 RIF2_D1_A_MARK, 1984 }; 1985 static const unsigned int drif2_ctrl_b_pins[] = { 1986 /* CLK, SYNC */ 1987 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27), 1988 }; 1989 static const unsigned int drif2_ctrl_b_mux[] = { 1990 RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK, 1991 }; 1992 static const unsigned int drif2_data0_b_pins[] = { 1993 /* D0 */ 1994 RCAR_GP_PIN(6, 30), 1995 }; 1996 static const unsigned int drif2_data0_b_mux[] = { 1997 RIF2_D0_B_MARK, 1998 }; 1999 static const unsigned int drif2_data1_b_pins[] = { 2000 /* D1 */ 2001 RCAR_GP_PIN(6, 31), 2002 }; 2003 static const unsigned int drif2_data1_b_mux[] = { 2004 RIF2_D1_B_MARK, 2005 }; 2006 /* - DRIF3 --------------------------------------------------------------- */ 2007 static const unsigned int drif3_ctrl_a_pins[] = { 2008 /* CLK, SYNC */ 2009 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18), 2010 }; 2011 static const unsigned int drif3_ctrl_a_mux[] = { 2012 RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK, 2013 }; 2014 static const unsigned int drif3_data0_a_pins[] = { 2015 /* D0 */ 2016 RCAR_GP_PIN(6, 19), 2017 }; 2018 static const unsigned int drif3_data0_a_mux[] = { 2019 RIF3_D0_A_MARK, 2020 }; 2021 static const unsigned int drif3_data1_a_pins[] = { 2022 /* D1 */ 2023 RCAR_GP_PIN(6, 20), 2024 }; 2025 static const unsigned int drif3_data1_a_mux[] = { 2026 RIF3_D1_A_MARK, 2027 }; 2028 static const unsigned int drif3_ctrl_b_pins[] = { 2029 /* CLK, SYNC */ 2030 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25), 2031 }; 2032 static const unsigned int drif3_ctrl_b_mux[] = { 2033 RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK, 2034 }; 2035 static const unsigned int drif3_data0_b_pins[] = { 2036 /* D0 */ 2037 RCAR_GP_PIN(6, 28), 2038 }; 2039 static const unsigned int drif3_data0_b_mux[] = { 2040 RIF3_D0_B_MARK, 2041 }; 2042 static const unsigned int drif3_data1_b_pins[] = { 2043 /* D1 */ 2044 RCAR_GP_PIN(6, 29), 2045 }; 2046 static const unsigned int drif3_data1_b_mux[] = { 2047 RIF3_D1_B_MARK, 2048 }; 2049 2050 /* - DU --------------------------------------------------------------------- */ 2051 static const unsigned int du_rgb666_pins[] = { 2052 /* R[7:2], G[7:2], B[7:2] */ 2053 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), 2054 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), 2055 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), 2056 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18), 2057 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5), 2058 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2), 2059 }; 2060 static const unsigned int du_rgb666_mux[] = { 2061 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK, 2062 DU_DR3_MARK, DU_DR2_MARK, 2063 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK, 2064 DU_DG3_MARK, DU_DG2_MARK, 2065 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK, 2066 DU_DB3_MARK, DU_DB2_MARK, 2067 }; 2068 static const unsigned int du_rgb888_pins[] = { 2069 /* R[7:0], G[7:0], B[7:0] */ 2070 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), 2071 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), 2072 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8), 2073 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), 2074 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18), 2075 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16), 2076 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5), 2077 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2), 2078 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0), 2079 }; 2080 static const unsigned int du_rgb888_mux[] = { 2081 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK, 2082 DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK, 2083 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK, 2084 DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK, 2085 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK, 2086 DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK, 2087 }; 2088 static const unsigned int du_clk_out_0_pins[] = { 2089 /* CLKOUT */ 2090 RCAR_GP_PIN(1, 27), 2091 }; 2092 static const unsigned int du_clk_out_0_mux[] = { 2093 DU_DOTCLKOUT0_MARK 2094 }; 2095 static const unsigned int du_clk_out_1_pins[] = { 2096 /* CLKOUT */ 2097 RCAR_GP_PIN(2, 3), 2098 }; 2099 static const unsigned int du_clk_out_1_mux[] = { 2100 DU_DOTCLKOUT1_MARK 2101 }; 2102 static const unsigned int du_sync_pins[] = { 2103 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */ 2104 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4), 2105 }; 2106 static const unsigned int du_sync_mux[] = { 2107 DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK 2108 }; 2109 static const unsigned int du_oddf_pins[] = { 2110 /* EXDISP/EXODDF/EXCDE */ 2111 RCAR_GP_PIN(2, 2), 2112 }; 2113 static const unsigned int du_oddf_mux[] = { 2114 DU_EXODDF_DU_ODDF_DISP_CDE_MARK, 2115 }; 2116 static const unsigned int du_cde_pins[] = { 2117 /* CDE */ 2118 RCAR_GP_PIN(2, 0), 2119 }; 2120 static const unsigned int du_cde_mux[] = { 2121 DU_CDE_MARK, 2122 }; 2123 static const unsigned int du_disp_pins[] = { 2124 /* DISP */ 2125 RCAR_GP_PIN(2, 1), 2126 }; 2127 static const unsigned int du_disp_mux[] = { 2128 DU_DISP_MARK, 2129 }; 2130 2131 /* - HSCIF0 ----------------------------------------------------------------- */ 2132 static const unsigned int hscif0_data_pins[] = { 2133 /* RX, TX */ 2134 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14), 2135 }; 2136 static const unsigned int hscif0_data_mux[] = { 2137 HRX0_MARK, HTX0_MARK, 2138 }; 2139 static const unsigned int hscif0_clk_pins[] = { 2140 /* SCK */ 2141 RCAR_GP_PIN(5, 12), 2142 }; 2143 static const unsigned int hscif0_clk_mux[] = { 2144 HSCK0_MARK, 2145 }; 2146 static const unsigned int hscif0_ctrl_pins[] = { 2147 /* RTS, CTS */ 2148 RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15), 2149 }; 2150 static const unsigned int hscif0_ctrl_mux[] = { 2151 HRTS0_N_MARK, HCTS0_N_MARK, 2152 }; 2153 /* - HSCIF1 ----------------------------------------------------------------- */ 2154 static const unsigned int hscif1_data_a_pins[] = { 2155 /* RX, TX */ 2156 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6), 2157 }; 2158 static const unsigned int hscif1_data_a_mux[] = { 2159 HRX1_A_MARK, HTX1_A_MARK, 2160 }; 2161 static const unsigned int hscif1_clk_a_pins[] = { 2162 /* SCK */ 2163 RCAR_GP_PIN(6, 21), 2164 }; 2165 static const unsigned int hscif1_clk_a_mux[] = { 2166 HSCK1_A_MARK, 2167 }; 2168 static const unsigned int hscif1_ctrl_a_pins[] = { 2169 /* RTS, CTS */ 2170 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7), 2171 }; 2172 static const unsigned int hscif1_ctrl_a_mux[] = { 2173 HRTS1_N_A_MARK, HCTS1_N_A_MARK, 2174 }; 2175 2176 static const unsigned int hscif1_data_b_pins[] = { 2177 /* RX, TX */ 2178 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), 2179 }; 2180 static const unsigned int hscif1_data_b_mux[] = { 2181 HRX1_B_MARK, HTX1_B_MARK, 2182 }; 2183 static const unsigned int hscif1_clk_b_pins[] = { 2184 /* SCK */ 2185 RCAR_GP_PIN(5, 0), 2186 }; 2187 static const unsigned int hscif1_clk_b_mux[] = { 2188 HSCK1_B_MARK, 2189 }; 2190 static const unsigned int hscif1_ctrl_b_pins[] = { 2191 /* RTS, CTS */ 2192 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3), 2193 }; 2194 static const unsigned int hscif1_ctrl_b_mux[] = { 2195 HRTS1_N_B_MARK, HCTS1_N_B_MARK, 2196 }; 2197 /* - HSCIF2 ----------------------------------------------------------------- */ 2198 static const unsigned int hscif2_data_a_pins[] = { 2199 /* RX, TX */ 2200 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), 2201 }; 2202 static const unsigned int hscif2_data_a_mux[] = { 2203 HRX2_A_MARK, HTX2_A_MARK, 2204 }; 2205 static const unsigned int hscif2_clk_a_pins[] = { 2206 /* SCK */ 2207 RCAR_GP_PIN(6, 10), 2208 }; 2209 static const unsigned int hscif2_clk_a_mux[] = { 2210 HSCK2_A_MARK, 2211 }; 2212 static const unsigned int hscif2_ctrl_a_pins[] = { 2213 /* RTS, CTS */ 2214 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6), 2215 }; 2216 static const unsigned int hscif2_ctrl_a_mux[] = { 2217 HRTS2_N_A_MARK, HCTS2_N_A_MARK, 2218 }; 2219 2220 static const unsigned int hscif2_data_b_pins[] = { 2221 /* RX, TX */ 2222 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18), 2223 }; 2224 static const unsigned int hscif2_data_b_mux[] = { 2225 HRX2_B_MARK, HTX2_B_MARK, 2226 }; 2227 static const unsigned int hscif2_clk_b_pins[] = { 2228 /* SCK */ 2229 RCAR_GP_PIN(6, 21), 2230 }; 2231 static const unsigned int hscif2_clk_b_mux[] = { 2232 HSCK2_B_MARK, 2233 }; 2234 static const unsigned int hscif2_ctrl_b_pins[] = { 2235 /* RTS, CTS */ 2236 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19), 2237 }; 2238 static const unsigned int hscif2_ctrl_b_mux[] = { 2239 HRTS2_N_B_MARK, HCTS2_N_B_MARK, 2240 }; 2241 2242 static const unsigned int hscif2_data_c_pins[] = { 2243 /* RX, TX */ 2244 RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26), 2245 }; 2246 static const unsigned int hscif2_data_c_mux[] = { 2247 HRX2_C_MARK, HTX2_C_MARK, 2248 }; 2249 static const unsigned int hscif2_clk_c_pins[] = { 2250 /* SCK */ 2251 RCAR_GP_PIN(6, 24), 2252 }; 2253 static const unsigned int hscif2_clk_c_mux[] = { 2254 HSCK2_C_MARK, 2255 }; 2256 static const unsigned int hscif2_ctrl_c_pins[] = { 2257 /* RTS, CTS */ 2258 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 27), 2259 }; 2260 static const unsigned int hscif2_ctrl_c_mux[] = { 2261 HRTS2_N_C_MARK, HCTS2_N_C_MARK, 2262 }; 2263 /* - HSCIF3 ----------------------------------------------------------------- */ 2264 static const unsigned int hscif3_data_a_pins[] = { 2265 /* RX, TX */ 2266 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24), 2267 }; 2268 static const unsigned int hscif3_data_a_mux[] = { 2269 HRX3_A_MARK, HTX3_A_MARK, 2270 }; 2271 static const unsigned int hscif3_clk_pins[] = { 2272 /* SCK */ 2273 RCAR_GP_PIN(1, 22), 2274 }; 2275 static const unsigned int hscif3_clk_mux[] = { 2276 HSCK3_MARK, 2277 }; 2278 static const unsigned int hscif3_ctrl_pins[] = { 2279 /* RTS, CTS */ 2280 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25), 2281 }; 2282 static const unsigned int hscif3_ctrl_mux[] = { 2283 HRTS3_N_MARK, HCTS3_N_MARK, 2284 }; 2285 2286 static const unsigned int hscif3_data_b_pins[] = { 2287 /* RX, TX */ 2288 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), 2289 }; 2290 static const unsigned int hscif3_data_b_mux[] = { 2291 HRX3_B_MARK, HTX3_B_MARK, 2292 }; 2293 static const unsigned int hscif3_data_c_pins[] = { 2294 /* RX, TX */ 2295 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), 2296 }; 2297 static const unsigned int hscif3_data_c_mux[] = { 2298 HRX3_C_MARK, HTX3_C_MARK, 2299 }; 2300 static const unsigned int hscif3_data_d_pins[] = { 2301 /* RX, TX */ 2302 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), 2303 }; 2304 static const unsigned int hscif3_data_d_mux[] = { 2305 HRX3_D_MARK, HTX3_D_MARK, 2306 }; 2307 /* - HSCIF4 ----------------------------------------------------------------- */ 2308 static const unsigned int hscif4_data_a_pins[] = { 2309 /* RX, TX */ 2310 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), 2311 }; 2312 static const unsigned int hscif4_data_a_mux[] = { 2313 HRX4_A_MARK, HTX4_A_MARK, 2314 }; 2315 static const unsigned int hscif4_clk_pins[] = { 2316 /* SCK */ 2317 RCAR_GP_PIN(1, 11), 2318 }; 2319 static const unsigned int hscif4_clk_mux[] = { 2320 HSCK4_MARK, 2321 }; 2322 static const unsigned int hscif4_ctrl_pins[] = { 2323 /* RTS, CTS */ 2324 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), 2325 }; 2326 static const unsigned int hscif4_ctrl_mux[] = { 2327 HRTS4_N_MARK, HCTS4_N_MARK, 2328 }; 2329 2330 static const unsigned int hscif4_data_b_pins[] = { 2331 /* RX, TX */ 2332 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), 2333 }; 2334 static const unsigned int hscif4_data_b_mux[] = { 2335 HRX4_B_MARK, HTX4_B_MARK, 2336 }; 2337 2338 /* - I2C -------------------------------------------------------------------- */ 2339 static const unsigned int i2c0_pins[] = { 2340 /* SCL, SDA */ 2341 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), 2342 }; 2343 2344 static const unsigned int i2c0_mux[] = { 2345 SCL0_MARK, SDA0_MARK, 2346 }; 2347 2348 static const unsigned int i2c1_a_pins[] = { 2349 /* SDA, SCL */ 2350 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10), 2351 }; 2352 static const unsigned int i2c1_a_mux[] = { 2353 SDA1_A_MARK, SCL1_A_MARK, 2354 }; 2355 static const unsigned int i2c1_b_pins[] = { 2356 /* SDA, SCL */ 2357 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23), 2358 }; 2359 static const unsigned int i2c1_b_mux[] = { 2360 SDA1_B_MARK, SCL1_B_MARK, 2361 }; 2362 static const unsigned int i2c2_a_pins[] = { 2363 /* SDA, SCL */ 2364 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4), 2365 }; 2366 static const unsigned int i2c2_a_mux[] = { 2367 SDA2_A_MARK, SCL2_A_MARK, 2368 }; 2369 static const unsigned int i2c2_b_pins[] = { 2370 /* SDA, SCL */ 2371 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12), 2372 }; 2373 static const unsigned int i2c2_b_mux[] = { 2374 SDA2_B_MARK, SCL2_B_MARK, 2375 }; 2376 2377 static const unsigned int i2c3_pins[] = { 2378 /* SCL, SDA */ 2379 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), 2380 }; 2381 2382 static const unsigned int i2c3_mux[] = { 2383 SCL3_MARK, SDA3_MARK, 2384 }; 2385 2386 static const unsigned int i2c5_pins[] = { 2387 /* SCL, SDA */ 2388 RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14), 2389 }; 2390 2391 static const unsigned int i2c5_mux[] = { 2392 SCL5_MARK, SDA5_MARK, 2393 }; 2394 2395 static const unsigned int i2c6_a_pins[] = { 2396 /* SDA, SCL */ 2397 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), 2398 }; 2399 static const unsigned int i2c6_a_mux[] = { 2400 SDA6_A_MARK, SCL6_A_MARK, 2401 }; 2402 static const unsigned int i2c6_b_pins[] = { 2403 /* SDA, SCL */ 2404 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25), 2405 }; 2406 static const unsigned int i2c6_b_mux[] = { 2407 SDA6_B_MARK, SCL6_B_MARK, 2408 }; 2409 static const unsigned int i2c6_c_pins[] = { 2410 /* SDA, SCL */ 2411 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), 2412 }; 2413 static const unsigned int i2c6_c_mux[] = { 2414 SDA6_C_MARK, SCL6_C_MARK, 2415 }; 2416 2417 /* - INTC-EX ---------------------------------------------------------------- */ 2418 static const unsigned int intc_ex_irq0_pins[] = { 2419 /* IRQ0 */ 2420 RCAR_GP_PIN(2, 0), 2421 }; 2422 static const unsigned int intc_ex_irq0_mux[] = { 2423 IRQ0_MARK, 2424 }; 2425 static const unsigned int intc_ex_irq1_pins[] = { 2426 /* IRQ1 */ 2427 RCAR_GP_PIN(2, 1), 2428 }; 2429 static const unsigned int intc_ex_irq1_mux[] = { 2430 IRQ1_MARK, 2431 }; 2432 static const unsigned int intc_ex_irq2_pins[] = { 2433 /* IRQ2 */ 2434 RCAR_GP_PIN(2, 2), 2435 }; 2436 static const unsigned int intc_ex_irq2_mux[] = { 2437 IRQ2_MARK, 2438 }; 2439 static const unsigned int intc_ex_irq3_pins[] = { 2440 /* IRQ3 */ 2441 RCAR_GP_PIN(2, 3), 2442 }; 2443 static const unsigned int intc_ex_irq3_mux[] = { 2444 IRQ3_MARK, 2445 }; 2446 static const unsigned int intc_ex_irq4_pins[] = { 2447 /* IRQ4 */ 2448 RCAR_GP_PIN(2, 4), 2449 }; 2450 static const unsigned int intc_ex_irq4_mux[] = { 2451 IRQ4_MARK, 2452 }; 2453 static const unsigned int intc_ex_irq5_pins[] = { 2454 /* IRQ5 */ 2455 RCAR_GP_PIN(2, 5), 2456 }; 2457 static const unsigned int intc_ex_irq5_mux[] = { 2458 IRQ5_MARK, 2459 }; 2460 2461 /* - MSIOF0 ----------------------------------------------------------------- */ 2462 static const unsigned int msiof0_clk_pins[] = { 2463 /* SCK */ 2464 RCAR_GP_PIN(5, 17), 2465 }; 2466 static const unsigned int msiof0_clk_mux[] = { 2467 MSIOF0_SCK_MARK, 2468 }; 2469 static const unsigned int msiof0_sync_pins[] = { 2470 /* SYNC */ 2471 RCAR_GP_PIN(5, 18), 2472 }; 2473 static const unsigned int msiof0_sync_mux[] = { 2474 MSIOF0_SYNC_MARK, 2475 }; 2476 static const unsigned int msiof0_ss1_pins[] = { 2477 /* SS1 */ 2478 RCAR_GP_PIN(5, 19), 2479 }; 2480 static const unsigned int msiof0_ss1_mux[] = { 2481 MSIOF0_SS1_MARK, 2482 }; 2483 static const unsigned int msiof0_ss2_pins[] = { 2484 /* SS2 */ 2485 RCAR_GP_PIN(5, 21), 2486 }; 2487 static const unsigned int msiof0_ss2_mux[] = { 2488 MSIOF0_SS2_MARK, 2489 }; 2490 static const unsigned int msiof0_txd_pins[] = { 2491 /* TXD */ 2492 RCAR_GP_PIN(5, 20), 2493 }; 2494 static const unsigned int msiof0_txd_mux[] = { 2495 MSIOF0_TXD_MARK, 2496 }; 2497 static const unsigned int msiof0_rxd_pins[] = { 2498 /* RXD */ 2499 RCAR_GP_PIN(5, 22), 2500 }; 2501 static const unsigned int msiof0_rxd_mux[] = { 2502 MSIOF0_RXD_MARK, 2503 }; 2504 /* - MSIOF1 ----------------------------------------------------------------- */ 2505 static const unsigned int msiof1_clk_a_pins[] = { 2506 /* SCK */ 2507 RCAR_GP_PIN(6, 8), 2508 }; 2509 static const unsigned int msiof1_clk_a_mux[] = { 2510 MSIOF1_SCK_A_MARK, 2511 }; 2512 static const unsigned int msiof1_sync_a_pins[] = { 2513 /* SYNC */ 2514 RCAR_GP_PIN(6, 9), 2515 }; 2516 static const unsigned int msiof1_sync_a_mux[] = { 2517 MSIOF1_SYNC_A_MARK, 2518 }; 2519 static const unsigned int msiof1_ss1_a_pins[] = { 2520 /* SS1 */ 2521 RCAR_GP_PIN(6, 5), 2522 }; 2523 static const unsigned int msiof1_ss1_a_mux[] = { 2524 MSIOF1_SS1_A_MARK, 2525 }; 2526 static const unsigned int msiof1_ss2_a_pins[] = { 2527 /* SS2 */ 2528 RCAR_GP_PIN(6, 6), 2529 }; 2530 static const unsigned int msiof1_ss2_a_mux[] = { 2531 MSIOF1_SS2_A_MARK, 2532 }; 2533 static const unsigned int msiof1_txd_a_pins[] = { 2534 /* TXD */ 2535 RCAR_GP_PIN(6, 7), 2536 }; 2537 static const unsigned int msiof1_txd_a_mux[] = { 2538 MSIOF1_TXD_A_MARK, 2539 }; 2540 static const unsigned int msiof1_rxd_a_pins[] = { 2541 /* RXD */ 2542 RCAR_GP_PIN(6, 10), 2543 }; 2544 static const unsigned int msiof1_rxd_a_mux[] = { 2545 MSIOF1_RXD_A_MARK, 2546 }; 2547 static const unsigned int msiof1_clk_b_pins[] = { 2548 /* SCK */ 2549 RCAR_GP_PIN(5, 9), 2550 }; 2551 static const unsigned int msiof1_clk_b_mux[] = { 2552 MSIOF1_SCK_B_MARK, 2553 }; 2554 static const unsigned int msiof1_sync_b_pins[] = { 2555 /* SYNC */ 2556 RCAR_GP_PIN(5, 3), 2557 }; 2558 static const unsigned int msiof1_sync_b_mux[] = { 2559 MSIOF1_SYNC_B_MARK, 2560 }; 2561 static const unsigned int msiof1_ss1_b_pins[] = { 2562 /* SS1 */ 2563 RCAR_GP_PIN(5, 4), 2564 }; 2565 static const unsigned int msiof1_ss1_b_mux[] = { 2566 MSIOF1_SS1_B_MARK, 2567 }; 2568 static const unsigned int msiof1_ss2_b_pins[] = { 2569 /* SS2 */ 2570 RCAR_GP_PIN(5, 0), 2571 }; 2572 static const unsigned int msiof1_ss2_b_mux[] = { 2573 MSIOF1_SS2_B_MARK, 2574 }; 2575 static const unsigned int msiof1_txd_b_pins[] = { 2576 /* TXD */ 2577 RCAR_GP_PIN(5, 8), 2578 }; 2579 static const unsigned int msiof1_txd_b_mux[] = { 2580 MSIOF1_TXD_B_MARK, 2581 }; 2582 static const unsigned int msiof1_rxd_b_pins[] = { 2583 /* RXD */ 2584 RCAR_GP_PIN(5, 7), 2585 }; 2586 static const unsigned int msiof1_rxd_b_mux[] = { 2587 MSIOF1_RXD_B_MARK, 2588 }; 2589 static const unsigned int msiof1_clk_c_pins[] = { 2590 /* SCK */ 2591 RCAR_GP_PIN(6, 17), 2592 }; 2593 static const unsigned int msiof1_clk_c_mux[] = { 2594 MSIOF1_SCK_C_MARK, 2595 }; 2596 static const unsigned int msiof1_sync_c_pins[] = { 2597 /* SYNC */ 2598 RCAR_GP_PIN(6, 18), 2599 }; 2600 static const unsigned int msiof1_sync_c_mux[] = { 2601 MSIOF1_SYNC_C_MARK, 2602 }; 2603 static const unsigned int msiof1_ss1_c_pins[] = { 2604 /* SS1 */ 2605 RCAR_GP_PIN(6, 21), 2606 }; 2607 static const unsigned int msiof1_ss1_c_mux[] = { 2608 MSIOF1_SS1_C_MARK, 2609 }; 2610 static const unsigned int msiof1_ss2_c_pins[] = { 2611 /* SS2 */ 2612 RCAR_GP_PIN(6, 27), 2613 }; 2614 static const unsigned int msiof1_ss2_c_mux[] = { 2615 MSIOF1_SS2_C_MARK, 2616 }; 2617 static const unsigned int msiof1_txd_c_pins[] = { 2618 /* TXD */ 2619 RCAR_GP_PIN(6, 20), 2620 }; 2621 static const unsigned int msiof1_txd_c_mux[] = { 2622 MSIOF1_TXD_C_MARK, 2623 }; 2624 static const unsigned int msiof1_rxd_c_pins[] = { 2625 /* RXD */ 2626 RCAR_GP_PIN(6, 19), 2627 }; 2628 static const unsigned int msiof1_rxd_c_mux[] = { 2629 MSIOF1_RXD_C_MARK, 2630 }; 2631 static const unsigned int msiof1_clk_d_pins[] = { 2632 /* SCK */ 2633 RCAR_GP_PIN(5, 12), 2634 }; 2635 static const unsigned int msiof1_clk_d_mux[] = { 2636 MSIOF1_SCK_D_MARK, 2637 }; 2638 static const unsigned int msiof1_sync_d_pins[] = { 2639 /* SYNC */ 2640 RCAR_GP_PIN(5, 15), 2641 }; 2642 static const unsigned int msiof1_sync_d_mux[] = { 2643 MSIOF1_SYNC_D_MARK, 2644 }; 2645 static const unsigned int msiof1_ss1_d_pins[] = { 2646 /* SS1 */ 2647 RCAR_GP_PIN(5, 16), 2648 }; 2649 static const unsigned int msiof1_ss1_d_mux[] = { 2650 MSIOF1_SS1_D_MARK, 2651 }; 2652 static const unsigned int msiof1_ss2_d_pins[] = { 2653 /* SS2 */ 2654 RCAR_GP_PIN(5, 21), 2655 }; 2656 static const unsigned int msiof1_ss2_d_mux[] = { 2657 MSIOF1_SS2_D_MARK, 2658 }; 2659 static const unsigned int msiof1_txd_d_pins[] = { 2660 /* TXD */ 2661 RCAR_GP_PIN(5, 14), 2662 }; 2663 static const unsigned int msiof1_txd_d_mux[] = { 2664 MSIOF1_TXD_D_MARK, 2665 }; 2666 static const unsigned int msiof1_rxd_d_pins[] = { 2667 /* RXD */ 2668 RCAR_GP_PIN(5, 13), 2669 }; 2670 static const unsigned int msiof1_rxd_d_mux[] = { 2671 MSIOF1_RXD_D_MARK, 2672 }; 2673 static const unsigned int msiof1_clk_e_pins[] = { 2674 /* SCK */ 2675 RCAR_GP_PIN(3, 0), 2676 }; 2677 static const unsigned int msiof1_clk_e_mux[] = { 2678 MSIOF1_SCK_E_MARK, 2679 }; 2680 static const unsigned int msiof1_sync_e_pins[] = { 2681 /* SYNC */ 2682 RCAR_GP_PIN(3, 1), 2683 }; 2684 static const unsigned int msiof1_sync_e_mux[] = { 2685 MSIOF1_SYNC_E_MARK, 2686 }; 2687 static const unsigned int msiof1_ss1_e_pins[] = { 2688 /* SS1 */ 2689 RCAR_GP_PIN(3, 4), 2690 }; 2691 static const unsigned int msiof1_ss1_e_mux[] = { 2692 MSIOF1_SS1_E_MARK, 2693 }; 2694 static const unsigned int msiof1_ss2_e_pins[] = { 2695 /* SS2 */ 2696 RCAR_GP_PIN(3, 5), 2697 }; 2698 static const unsigned int msiof1_ss2_e_mux[] = { 2699 MSIOF1_SS2_E_MARK, 2700 }; 2701 static const unsigned int msiof1_txd_e_pins[] = { 2702 /* TXD */ 2703 RCAR_GP_PIN(3, 3), 2704 }; 2705 static const unsigned int msiof1_txd_e_mux[] = { 2706 MSIOF1_TXD_E_MARK, 2707 }; 2708 static const unsigned int msiof1_rxd_e_pins[] = { 2709 /* RXD */ 2710 RCAR_GP_PIN(3, 2), 2711 }; 2712 static const unsigned int msiof1_rxd_e_mux[] = { 2713 MSIOF1_RXD_E_MARK, 2714 }; 2715 static const unsigned int msiof1_clk_f_pins[] = { 2716 /* SCK */ 2717 RCAR_GP_PIN(5, 23), 2718 }; 2719 static const unsigned int msiof1_clk_f_mux[] = { 2720 MSIOF1_SCK_F_MARK, 2721 }; 2722 static const unsigned int msiof1_sync_f_pins[] = { 2723 /* SYNC */ 2724 RCAR_GP_PIN(5, 24), 2725 }; 2726 static const unsigned int msiof1_sync_f_mux[] = { 2727 MSIOF1_SYNC_F_MARK, 2728 }; 2729 static const unsigned int msiof1_ss1_f_pins[] = { 2730 /* SS1 */ 2731 RCAR_GP_PIN(6, 1), 2732 }; 2733 static const unsigned int msiof1_ss1_f_mux[] = { 2734 MSIOF1_SS1_F_MARK, 2735 }; 2736 static const unsigned int msiof1_ss2_f_pins[] = { 2737 /* SS2 */ 2738 RCAR_GP_PIN(6, 2), 2739 }; 2740 static const unsigned int msiof1_ss2_f_mux[] = { 2741 MSIOF1_SS2_F_MARK, 2742 }; 2743 static const unsigned int msiof1_txd_f_pins[] = { 2744 /* TXD */ 2745 RCAR_GP_PIN(6, 0), 2746 }; 2747 static const unsigned int msiof1_txd_f_mux[] = { 2748 MSIOF1_TXD_F_MARK, 2749 }; 2750 static const unsigned int msiof1_rxd_f_pins[] = { 2751 /* RXD */ 2752 RCAR_GP_PIN(5, 25), 2753 }; 2754 static const unsigned int msiof1_rxd_f_mux[] = { 2755 MSIOF1_RXD_F_MARK, 2756 }; 2757 static const unsigned int msiof1_clk_g_pins[] = { 2758 /* SCK */ 2759 RCAR_GP_PIN(3, 6), 2760 }; 2761 static const unsigned int msiof1_clk_g_mux[] = { 2762 MSIOF1_SCK_G_MARK, 2763 }; 2764 static const unsigned int msiof1_sync_g_pins[] = { 2765 /* SYNC */ 2766 RCAR_GP_PIN(3, 7), 2767 }; 2768 static const unsigned int msiof1_sync_g_mux[] = { 2769 MSIOF1_SYNC_G_MARK, 2770 }; 2771 static const unsigned int msiof1_ss1_g_pins[] = { 2772 /* SS1 */ 2773 RCAR_GP_PIN(3, 10), 2774 }; 2775 static const unsigned int msiof1_ss1_g_mux[] = { 2776 MSIOF1_SS1_G_MARK, 2777 }; 2778 static const unsigned int msiof1_ss2_g_pins[] = { 2779 /* SS2 */ 2780 RCAR_GP_PIN(3, 11), 2781 }; 2782 static const unsigned int msiof1_ss2_g_mux[] = { 2783 MSIOF1_SS2_G_MARK, 2784 }; 2785 static const unsigned int msiof1_txd_g_pins[] = { 2786 /* TXD */ 2787 RCAR_GP_PIN(3, 9), 2788 }; 2789 static const unsigned int msiof1_txd_g_mux[] = { 2790 MSIOF1_TXD_G_MARK, 2791 }; 2792 static const unsigned int msiof1_rxd_g_pins[] = { 2793 /* RXD */ 2794 RCAR_GP_PIN(3, 8), 2795 }; 2796 static const unsigned int msiof1_rxd_g_mux[] = { 2797 MSIOF1_RXD_G_MARK, 2798 }; 2799 /* - MSIOF2 ----------------------------------------------------------------- */ 2800 static const unsigned int msiof2_clk_a_pins[] = { 2801 /* SCK */ 2802 RCAR_GP_PIN(1, 9), 2803 }; 2804 static const unsigned int msiof2_clk_a_mux[] = { 2805 MSIOF2_SCK_A_MARK, 2806 }; 2807 static const unsigned int msiof2_sync_a_pins[] = { 2808 /* SYNC */ 2809 RCAR_GP_PIN(1, 8), 2810 }; 2811 static const unsigned int msiof2_sync_a_mux[] = { 2812 MSIOF2_SYNC_A_MARK, 2813 }; 2814 static const unsigned int msiof2_ss1_a_pins[] = { 2815 /* SS1 */ 2816 RCAR_GP_PIN(1, 6), 2817 }; 2818 static const unsigned int msiof2_ss1_a_mux[] = { 2819 MSIOF2_SS1_A_MARK, 2820 }; 2821 static const unsigned int msiof2_ss2_a_pins[] = { 2822 /* SS2 */ 2823 RCAR_GP_PIN(1, 7), 2824 }; 2825 static const unsigned int msiof2_ss2_a_mux[] = { 2826 MSIOF2_SS2_A_MARK, 2827 }; 2828 static const unsigned int msiof2_txd_a_pins[] = { 2829 /* TXD */ 2830 RCAR_GP_PIN(1, 11), 2831 }; 2832 static const unsigned int msiof2_txd_a_mux[] = { 2833 MSIOF2_TXD_A_MARK, 2834 }; 2835 static const unsigned int msiof2_rxd_a_pins[] = { 2836 /* RXD */ 2837 RCAR_GP_PIN(1, 10), 2838 }; 2839 static const unsigned int msiof2_rxd_a_mux[] = { 2840 MSIOF2_RXD_A_MARK, 2841 }; 2842 static const unsigned int msiof2_clk_b_pins[] = { 2843 /* SCK */ 2844 RCAR_GP_PIN(0, 4), 2845 }; 2846 static const unsigned int msiof2_clk_b_mux[] = { 2847 MSIOF2_SCK_B_MARK, 2848 }; 2849 static const unsigned int msiof2_sync_b_pins[] = { 2850 /* SYNC */ 2851 RCAR_GP_PIN(0, 5), 2852 }; 2853 static const unsigned int msiof2_sync_b_mux[] = { 2854 MSIOF2_SYNC_B_MARK, 2855 }; 2856 static const unsigned int msiof2_ss1_b_pins[] = { 2857 /* SS1 */ 2858 RCAR_GP_PIN(0, 0), 2859 }; 2860 static const unsigned int msiof2_ss1_b_mux[] = { 2861 MSIOF2_SS1_B_MARK, 2862 }; 2863 static const unsigned int msiof2_ss2_b_pins[] = { 2864 /* SS2 */ 2865 RCAR_GP_PIN(0, 1), 2866 }; 2867 static const unsigned int msiof2_ss2_b_mux[] = { 2868 MSIOF2_SS2_B_MARK, 2869 }; 2870 static const unsigned int msiof2_txd_b_pins[] = { 2871 /* TXD */ 2872 RCAR_GP_PIN(0, 7), 2873 }; 2874 static const unsigned int msiof2_txd_b_mux[] = { 2875 MSIOF2_TXD_B_MARK, 2876 }; 2877 static const unsigned int msiof2_rxd_b_pins[] = { 2878 /* RXD */ 2879 RCAR_GP_PIN(0, 6), 2880 }; 2881 static const unsigned int msiof2_rxd_b_mux[] = { 2882 MSIOF2_RXD_B_MARK, 2883 }; 2884 static const unsigned int msiof2_clk_c_pins[] = { 2885 /* SCK */ 2886 RCAR_GP_PIN(2, 12), 2887 }; 2888 static const unsigned int msiof2_clk_c_mux[] = { 2889 MSIOF2_SCK_C_MARK, 2890 }; 2891 static const unsigned int msiof2_sync_c_pins[] = { 2892 /* SYNC */ 2893 RCAR_GP_PIN(2, 11), 2894 }; 2895 static const unsigned int msiof2_sync_c_mux[] = { 2896 MSIOF2_SYNC_C_MARK, 2897 }; 2898 static const unsigned int msiof2_ss1_c_pins[] = { 2899 /* SS1 */ 2900 RCAR_GP_PIN(2, 10), 2901 }; 2902 static const unsigned int msiof2_ss1_c_mux[] = { 2903 MSIOF2_SS1_C_MARK, 2904 }; 2905 static const unsigned int msiof2_ss2_c_pins[] = { 2906 /* SS2 */ 2907 RCAR_GP_PIN(2, 9), 2908 }; 2909 static const unsigned int msiof2_ss2_c_mux[] = { 2910 MSIOF2_SS2_C_MARK, 2911 }; 2912 static const unsigned int msiof2_txd_c_pins[] = { 2913 /* TXD */ 2914 RCAR_GP_PIN(2, 14), 2915 }; 2916 static const unsigned int msiof2_txd_c_mux[] = { 2917 MSIOF2_TXD_C_MARK, 2918 }; 2919 static const unsigned int msiof2_rxd_c_pins[] = { 2920 /* RXD */ 2921 RCAR_GP_PIN(2, 13), 2922 }; 2923 static const unsigned int msiof2_rxd_c_mux[] = { 2924 MSIOF2_RXD_C_MARK, 2925 }; 2926 static const unsigned int msiof2_clk_d_pins[] = { 2927 /* SCK */ 2928 RCAR_GP_PIN(0, 8), 2929 }; 2930 static const unsigned int msiof2_clk_d_mux[] = { 2931 MSIOF2_SCK_D_MARK, 2932 }; 2933 static const unsigned int msiof2_sync_d_pins[] = { 2934 /* SYNC */ 2935 RCAR_GP_PIN(0, 9), 2936 }; 2937 static const unsigned int msiof2_sync_d_mux[] = { 2938 MSIOF2_SYNC_D_MARK, 2939 }; 2940 static const unsigned int msiof2_ss1_d_pins[] = { 2941 /* SS1 */ 2942 RCAR_GP_PIN(0, 12), 2943 }; 2944 static const unsigned int msiof2_ss1_d_mux[] = { 2945 MSIOF2_SS1_D_MARK, 2946 }; 2947 static const unsigned int msiof2_ss2_d_pins[] = { 2948 /* SS2 */ 2949 RCAR_GP_PIN(0, 13), 2950 }; 2951 static const unsigned int msiof2_ss2_d_mux[] = { 2952 MSIOF2_SS2_D_MARK, 2953 }; 2954 static const unsigned int msiof2_txd_d_pins[] = { 2955 /* TXD */ 2956 RCAR_GP_PIN(0, 11), 2957 }; 2958 static const unsigned int msiof2_txd_d_mux[] = { 2959 MSIOF2_TXD_D_MARK, 2960 }; 2961 static const unsigned int msiof2_rxd_d_pins[] = { 2962 /* RXD */ 2963 RCAR_GP_PIN(0, 10), 2964 }; 2965 static const unsigned int msiof2_rxd_d_mux[] = { 2966 MSIOF2_RXD_D_MARK, 2967 }; 2968 /* - MSIOF3 ----------------------------------------------------------------- */ 2969 static const unsigned int msiof3_clk_a_pins[] = { 2970 /* SCK */ 2971 RCAR_GP_PIN(0, 0), 2972 }; 2973 static const unsigned int msiof3_clk_a_mux[] = { 2974 MSIOF3_SCK_A_MARK, 2975 }; 2976 static const unsigned int msiof3_sync_a_pins[] = { 2977 /* SYNC */ 2978 RCAR_GP_PIN(0, 1), 2979 }; 2980 static const unsigned int msiof3_sync_a_mux[] = { 2981 MSIOF3_SYNC_A_MARK, 2982 }; 2983 static const unsigned int msiof3_ss1_a_pins[] = { 2984 /* SS1 */ 2985 RCAR_GP_PIN(0, 14), 2986 }; 2987 static const unsigned int msiof3_ss1_a_mux[] = { 2988 MSIOF3_SS1_A_MARK, 2989 }; 2990 static const unsigned int msiof3_ss2_a_pins[] = { 2991 /* SS2 */ 2992 RCAR_GP_PIN(0, 15), 2993 }; 2994 static const unsigned int msiof3_ss2_a_mux[] = { 2995 MSIOF3_SS2_A_MARK, 2996 }; 2997 static const unsigned int msiof3_txd_a_pins[] = { 2998 /* TXD */ 2999 RCAR_GP_PIN(0, 3), 3000 }; 3001 static const unsigned int msiof3_txd_a_mux[] = { 3002 MSIOF3_TXD_A_MARK, 3003 }; 3004 static const unsigned int msiof3_rxd_a_pins[] = { 3005 /* RXD */ 3006 RCAR_GP_PIN(0, 2), 3007 }; 3008 static const unsigned int msiof3_rxd_a_mux[] = { 3009 MSIOF3_RXD_A_MARK, 3010 }; 3011 static const unsigned int msiof3_clk_b_pins[] = { 3012 /* SCK */ 3013 RCAR_GP_PIN(1, 2), 3014 }; 3015 static const unsigned int msiof3_clk_b_mux[] = { 3016 MSIOF3_SCK_B_MARK, 3017 }; 3018 static const unsigned int msiof3_sync_b_pins[] = { 3019 /* SYNC */ 3020 RCAR_GP_PIN(1, 0), 3021 }; 3022 static const unsigned int msiof3_sync_b_mux[] = { 3023 MSIOF3_SYNC_B_MARK, 3024 }; 3025 static const unsigned int msiof3_ss1_b_pins[] = { 3026 /* SS1 */ 3027 RCAR_GP_PIN(1, 4), 3028 }; 3029 static const unsigned int msiof3_ss1_b_mux[] = { 3030 MSIOF3_SS1_B_MARK, 3031 }; 3032 static const unsigned int msiof3_ss2_b_pins[] = { 3033 /* SS2 */ 3034 RCAR_GP_PIN(1, 5), 3035 }; 3036 static const unsigned int msiof3_ss2_b_mux[] = { 3037 MSIOF3_SS2_B_MARK, 3038 }; 3039 static const unsigned int msiof3_txd_b_pins[] = { 3040 /* TXD */ 3041 RCAR_GP_PIN(1, 1), 3042 }; 3043 static const unsigned int msiof3_txd_b_mux[] = { 3044 MSIOF3_TXD_B_MARK, 3045 }; 3046 static const unsigned int msiof3_rxd_b_pins[] = { 3047 /* RXD */ 3048 RCAR_GP_PIN(1, 3), 3049 }; 3050 static const unsigned int msiof3_rxd_b_mux[] = { 3051 MSIOF3_RXD_B_MARK, 3052 }; 3053 static const unsigned int msiof3_clk_c_pins[] = { 3054 /* SCK */ 3055 RCAR_GP_PIN(1, 12), 3056 }; 3057 static const unsigned int msiof3_clk_c_mux[] = { 3058 MSIOF3_SCK_C_MARK, 3059 }; 3060 static const unsigned int msiof3_sync_c_pins[] = { 3061 /* SYNC */ 3062 RCAR_GP_PIN(1, 13), 3063 }; 3064 static const unsigned int msiof3_sync_c_mux[] = { 3065 MSIOF3_SYNC_C_MARK, 3066 }; 3067 static const unsigned int msiof3_txd_c_pins[] = { 3068 /* TXD */ 3069 RCAR_GP_PIN(1, 15), 3070 }; 3071 static const unsigned int msiof3_txd_c_mux[] = { 3072 MSIOF3_TXD_C_MARK, 3073 }; 3074 static const unsigned int msiof3_rxd_c_pins[] = { 3075 /* RXD */ 3076 RCAR_GP_PIN(1, 14), 3077 }; 3078 static const unsigned int msiof3_rxd_c_mux[] = { 3079 MSIOF3_RXD_C_MARK, 3080 }; 3081 static const unsigned int msiof3_clk_d_pins[] = { 3082 /* SCK */ 3083 RCAR_GP_PIN(1, 22), 3084 }; 3085 static const unsigned int msiof3_clk_d_mux[] = { 3086 MSIOF3_SCK_D_MARK, 3087 }; 3088 static const unsigned int msiof3_sync_d_pins[] = { 3089 /* SYNC */ 3090 RCAR_GP_PIN(1, 23), 3091 }; 3092 static const unsigned int msiof3_sync_d_mux[] = { 3093 MSIOF3_SYNC_D_MARK, 3094 }; 3095 static const unsigned int msiof3_ss1_d_pins[] = { 3096 /* SS1 */ 3097 RCAR_GP_PIN(1, 26), 3098 }; 3099 static const unsigned int msiof3_ss1_d_mux[] = { 3100 MSIOF3_SS1_D_MARK, 3101 }; 3102 static const unsigned int msiof3_txd_d_pins[] = { 3103 /* TXD */ 3104 RCAR_GP_PIN(1, 25), 3105 }; 3106 static const unsigned int msiof3_txd_d_mux[] = { 3107 MSIOF3_TXD_D_MARK, 3108 }; 3109 static const unsigned int msiof3_rxd_d_pins[] = { 3110 /* RXD */ 3111 RCAR_GP_PIN(1, 24), 3112 }; 3113 static const unsigned int msiof3_rxd_d_mux[] = { 3114 MSIOF3_RXD_D_MARK, 3115 }; 3116 3117 static const unsigned int msiof3_clk_e_pins[] = { 3118 /* SCK */ 3119 RCAR_GP_PIN(2, 3), 3120 }; 3121 static const unsigned int msiof3_clk_e_mux[] = { 3122 MSIOF3_SCK_E_MARK, 3123 }; 3124 static const unsigned int msiof3_sync_e_pins[] = { 3125 /* SYNC */ 3126 RCAR_GP_PIN(2, 2), 3127 }; 3128 static const unsigned int msiof3_sync_e_mux[] = { 3129 MSIOF3_SYNC_E_MARK, 3130 }; 3131 static const unsigned int msiof3_ss1_e_pins[] = { 3132 /* SS1 */ 3133 RCAR_GP_PIN(2, 1), 3134 }; 3135 static const unsigned int msiof3_ss1_e_mux[] = { 3136 MSIOF3_SS1_E_MARK, 3137 }; 3138 static const unsigned int msiof3_ss2_e_pins[] = { 3139 /* SS2 */ 3140 RCAR_GP_PIN(2, 0), 3141 }; 3142 static const unsigned int msiof3_ss2_e_mux[] = { 3143 MSIOF3_SS2_E_MARK, 3144 }; 3145 static const unsigned int msiof3_txd_e_pins[] = { 3146 /* TXD */ 3147 RCAR_GP_PIN(2, 5), 3148 }; 3149 static const unsigned int msiof3_txd_e_mux[] = { 3150 MSIOF3_TXD_E_MARK, 3151 }; 3152 static const unsigned int msiof3_rxd_e_pins[] = { 3153 /* RXD */ 3154 RCAR_GP_PIN(2, 4), 3155 }; 3156 static const unsigned int msiof3_rxd_e_mux[] = { 3157 MSIOF3_RXD_E_MARK, 3158 }; 3159 3160 /* - PWM0 --------------------------------------------------------------------*/ 3161 static const unsigned int pwm0_pins[] = { 3162 /* PWM */ 3163 RCAR_GP_PIN(2, 6), 3164 }; 3165 static const unsigned int pwm0_mux[] = { 3166 PWM0_MARK, 3167 }; 3168 /* - PWM1 --------------------------------------------------------------------*/ 3169 static const unsigned int pwm1_a_pins[] = { 3170 /* PWM */ 3171 RCAR_GP_PIN(2, 7), 3172 }; 3173 static const unsigned int pwm1_a_mux[] = { 3174 PWM1_A_MARK, 3175 }; 3176 static const unsigned int pwm1_b_pins[] = { 3177 /* PWM */ 3178 RCAR_GP_PIN(1, 8), 3179 }; 3180 static const unsigned int pwm1_b_mux[] = { 3181 PWM1_B_MARK, 3182 }; 3183 /* - PWM2 --------------------------------------------------------------------*/ 3184 static const unsigned int pwm2_a_pins[] = { 3185 /* PWM */ 3186 RCAR_GP_PIN(2, 8), 3187 }; 3188 static const unsigned int pwm2_a_mux[] = { 3189 PWM2_A_MARK, 3190 }; 3191 static const unsigned int pwm2_b_pins[] = { 3192 /* PWM */ 3193 RCAR_GP_PIN(1, 11), 3194 }; 3195 static const unsigned int pwm2_b_mux[] = { 3196 PWM2_B_MARK, 3197 }; 3198 /* - PWM3 --------------------------------------------------------------------*/ 3199 static const unsigned int pwm3_a_pins[] = { 3200 /* PWM */ 3201 RCAR_GP_PIN(1, 0), 3202 }; 3203 static const unsigned int pwm3_a_mux[] = { 3204 PWM3_A_MARK, 3205 }; 3206 static const unsigned int pwm3_b_pins[] = { 3207 /* PWM */ 3208 RCAR_GP_PIN(2, 2), 3209 }; 3210 static const unsigned int pwm3_b_mux[] = { 3211 PWM3_B_MARK, 3212 }; 3213 /* - PWM4 --------------------------------------------------------------------*/ 3214 static const unsigned int pwm4_a_pins[] = { 3215 /* PWM */ 3216 RCAR_GP_PIN(1, 1), 3217 }; 3218 static const unsigned int pwm4_a_mux[] = { 3219 PWM4_A_MARK, 3220 }; 3221 static const unsigned int pwm4_b_pins[] = { 3222 /* PWM */ 3223 RCAR_GP_PIN(2, 3), 3224 }; 3225 static const unsigned int pwm4_b_mux[] = { 3226 PWM4_B_MARK, 3227 }; 3228 /* - PWM5 --------------------------------------------------------------------*/ 3229 static const unsigned int pwm5_a_pins[] = { 3230 /* PWM */ 3231 RCAR_GP_PIN(1, 2), 3232 }; 3233 static const unsigned int pwm5_a_mux[] = { 3234 PWM5_A_MARK, 3235 }; 3236 static const unsigned int pwm5_b_pins[] = { 3237 /* PWM */ 3238 RCAR_GP_PIN(2, 4), 3239 }; 3240 static const unsigned int pwm5_b_mux[] = { 3241 PWM5_B_MARK, 3242 }; 3243 /* - PWM6 --------------------------------------------------------------------*/ 3244 static const unsigned int pwm6_a_pins[] = { 3245 /* PWM */ 3246 RCAR_GP_PIN(1, 3), 3247 }; 3248 static const unsigned int pwm6_a_mux[] = { 3249 PWM6_A_MARK, 3250 }; 3251 static const unsigned int pwm6_b_pins[] = { 3252 /* PWM */ 3253 RCAR_GP_PIN(2, 5), 3254 }; 3255 static const unsigned int pwm6_b_mux[] = { 3256 PWM6_B_MARK, 3257 }; 3258 3259 /* - SCIF0 ------------------------------------------------------------------ */ 3260 static const unsigned int scif0_data_pins[] = { 3261 /* RX, TX */ 3262 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), 3263 }; 3264 static const unsigned int scif0_data_mux[] = { 3265 RX0_MARK, TX0_MARK, 3266 }; 3267 static const unsigned int scif0_clk_pins[] = { 3268 /* SCK */ 3269 RCAR_GP_PIN(5, 0), 3270 }; 3271 static const unsigned int scif0_clk_mux[] = { 3272 SCK0_MARK, 3273 }; 3274 static const unsigned int scif0_ctrl_pins[] = { 3275 /* RTS, CTS */ 3276 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3), 3277 }; 3278 static const unsigned int scif0_ctrl_mux[] = { 3279 RTS0_N_MARK, CTS0_N_MARK, 3280 }; 3281 /* - SCIF1 ------------------------------------------------------------------ */ 3282 static const unsigned int scif1_data_a_pins[] = { 3283 /* RX, TX */ 3284 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6), 3285 }; 3286 static const unsigned int scif1_data_a_mux[] = { 3287 RX1_A_MARK, TX1_A_MARK, 3288 }; 3289 static const unsigned int scif1_clk_pins[] = { 3290 /* SCK */ 3291 RCAR_GP_PIN(6, 21), 3292 }; 3293 static const unsigned int scif1_clk_mux[] = { 3294 SCK1_MARK, 3295 }; 3296 static const unsigned int scif1_ctrl_pins[] = { 3297 /* RTS, CTS */ 3298 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7), 3299 }; 3300 static const unsigned int scif1_ctrl_mux[] = { 3301 RTS1_N_MARK, CTS1_N_MARK, 3302 }; 3303 3304 static const unsigned int scif1_data_b_pins[] = { 3305 /* RX, TX */ 3306 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25), 3307 }; 3308 static const unsigned int scif1_data_b_mux[] = { 3309 RX1_B_MARK, TX1_B_MARK, 3310 }; 3311 /* - SCIF2 ------------------------------------------------------------------ */ 3312 static const unsigned int scif2_data_a_pins[] = { 3313 /* RX, TX */ 3314 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10), 3315 }; 3316 static const unsigned int scif2_data_a_mux[] = { 3317 RX2_A_MARK, TX2_A_MARK, 3318 }; 3319 static const unsigned int scif2_clk_pins[] = { 3320 /* SCK */ 3321 RCAR_GP_PIN(5, 9), 3322 }; 3323 static const unsigned int scif2_clk_mux[] = { 3324 SCK2_MARK, 3325 }; 3326 static const unsigned int scif2_data_b_pins[] = { 3327 /* RX, TX */ 3328 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16), 3329 }; 3330 static const unsigned int scif2_data_b_mux[] = { 3331 RX2_B_MARK, TX2_B_MARK, 3332 }; 3333 /* - SCIF3 ------------------------------------------------------------------ */ 3334 static const unsigned int scif3_data_a_pins[] = { 3335 /* RX, TX */ 3336 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24), 3337 }; 3338 static const unsigned int scif3_data_a_mux[] = { 3339 RX3_A_MARK, TX3_A_MARK, 3340 }; 3341 static const unsigned int scif3_clk_pins[] = { 3342 /* SCK */ 3343 RCAR_GP_PIN(1, 22), 3344 }; 3345 static const unsigned int scif3_clk_mux[] = { 3346 SCK3_MARK, 3347 }; 3348 static const unsigned int scif3_ctrl_pins[] = { 3349 /* RTS, CTS */ 3350 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25), 3351 }; 3352 static const unsigned int scif3_ctrl_mux[] = { 3353 RTS3_N_MARK, CTS3_N_MARK, 3354 }; 3355 static const unsigned int scif3_data_b_pins[] = { 3356 /* RX, TX */ 3357 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), 3358 }; 3359 static const unsigned int scif3_data_b_mux[] = { 3360 RX3_B_MARK, TX3_B_MARK, 3361 }; 3362 /* - SCIF4 ------------------------------------------------------------------ */ 3363 static const unsigned int scif4_data_a_pins[] = { 3364 /* RX, TX */ 3365 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12), 3366 }; 3367 static const unsigned int scif4_data_a_mux[] = { 3368 RX4_A_MARK, TX4_A_MARK, 3369 }; 3370 static const unsigned int scif4_clk_a_pins[] = { 3371 /* SCK */ 3372 RCAR_GP_PIN(2, 10), 3373 }; 3374 static const unsigned int scif4_clk_a_mux[] = { 3375 SCK4_A_MARK, 3376 }; 3377 static const unsigned int scif4_ctrl_a_pins[] = { 3378 /* RTS, CTS */ 3379 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13), 3380 }; 3381 static const unsigned int scif4_ctrl_a_mux[] = { 3382 RTS4_N_A_MARK, CTS4_N_A_MARK, 3383 }; 3384 static const unsigned int scif4_data_b_pins[] = { 3385 /* RX, TX */ 3386 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 3387 }; 3388 static const unsigned int scif4_data_b_mux[] = { 3389 RX4_B_MARK, TX4_B_MARK, 3390 }; 3391 static const unsigned int scif4_clk_b_pins[] = { 3392 /* SCK */ 3393 RCAR_GP_PIN(1, 5), 3394 }; 3395 static const unsigned int scif4_clk_b_mux[] = { 3396 SCK4_B_MARK, 3397 }; 3398 static const unsigned int scif4_ctrl_b_pins[] = { 3399 /* RTS, CTS */ 3400 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9), 3401 }; 3402 static const unsigned int scif4_ctrl_b_mux[] = { 3403 RTS4_N_B_MARK, CTS4_N_B_MARK, 3404 }; 3405 static const unsigned int scif4_data_c_pins[] = { 3406 /* RX, TX */ 3407 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), 3408 }; 3409 static const unsigned int scif4_data_c_mux[] = { 3410 RX4_C_MARK, TX4_C_MARK, 3411 }; 3412 static const unsigned int scif4_clk_c_pins[] = { 3413 /* SCK */ 3414 RCAR_GP_PIN(0, 8), 3415 }; 3416 static const unsigned int scif4_clk_c_mux[] = { 3417 SCK4_C_MARK, 3418 }; 3419 static const unsigned int scif4_ctrl_c_pins[] = { 3420 /* RTS, CTS */ 3421 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), 3422 }; 3423 static const unsigned int scif4_ctrl_c_mux[] = { 3424 RTS4_N_C_MARK, CTS4_N_C_MARK, 3425 }; 3426 /* - SCIF5 ------------------------------------------------------------------ */ 3427 static const unsigned int scif5_data_a_pins[] = { 3428 /* RX, TX */ 3429 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21), 3430 }; 3431 static const unsigned int scif5_data_a_mux[] = { 3432 RX5_A_MARK, TX5_A_MARK, 3433 }; 3434 static const unsigned int scif5_clk_a_pins[] = { 3435 /* SCK */ 3436 RCAR_GP_PIN(6, 21), 3437 }; 3438 static const unsigned int scif5_clk_a_mux[] = { 3439 SCK5_A_MARK, 3440 }; 3441 3442 static const unsigned int scif5_data_b_pins[] = { 3443 /* RX, TX */ 3444 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18), 3445 }; 3446 static const unsigned int scif5_data_b_mux[] = { 3447 RX5_B_MARK, TX5_B_MARK, 3448 }; 3449 static const unsigned int scif5_clk_b_pins[] = { 3450 /* SCK */ 3451 RCAR_GP_PIN(5, 0), 3452 }; 3453 static const unsigned int scif5_clk_b_mux[] = { 3454 SCK5_B_MARK, 3455 }; 3456 3457 /* - SCIF Clock ------------------------------------------------------------- */ 3458 static const unsigned int scif_clk_a_pins[] = { 3459 /* SCIF_CLK */ 3460 RCAR_GP_PIN(6, 23), 3461 }; 3462 static const unsigned int scif_clk_a_mux[] = { 3463 SCIF_CLK_A_MARK, 3464 }; 3465 static const unsigned int scif_clk_b_pins[] = { 3466 /* SCIF_CLK */ 3467 RCAR_GP_PIN(5, 9), 3468 }; 3469 static const unsigned int scif_clk_b_mux[] = { 3470 SCIF_CLK_B_MARK, 3471 }; 3472 3473 /* - SDHI0 ------------------------------------------------------------------ */ 3474 static const unsigned int sdhi0_data1_pins[] = { 3475 /* D0 */ 3476 RCAR_GP_PIN(3, 2), 3477 }; 3478 static const unsigned int sdhi0_data1_mux[] = { 3479 SD0_DAT0_MARK, 3480 }; 3481 static const unsigned int sdhi0_data4_pins[] = { 3482 /* D[0:3] */ 3483 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), 3484 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), 3485 }; 3486 static const unsigned int sdhi0_data4_mux[] = { 3487 SD0_DAT0_MARK, SD0_DAT1_MARK, 3488 SD0_DAT2_MARK, SD0_DAT3_MARK, 3489 }; 3490 static const unsigned int sdhi0_ctrl_pins[] = { 3491 /* CLK, CMD */ 3492 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1), 3493 }; 3494 static const unsigned int sdhi0_ctrl_mux[] = { 3495 SD0_CLK_MARK, SD0_CMD_MARK, 3496 }; 3497 static const unsigned int sdhi0_cd_pins[] = { 3498 /* CD */ 3499 RCAR_GP_PIN(3, 12), 3500 }; 3501 static const unsigned int sdhi0_cd_mux[] = { 3502 SD0_CD_MARK, 3503 }; 3504 static const unsigned int sdhi0_wp_pins[] = { 3505 /* WP */ 3506 RCAR_GP_PIN(3, 13), 3507 }; 3508 static const unsigned int sdhi0_wp_mux[] = { 3509 SD0_WP_MARK, 3510 }; 3511 /* - SDHI1 ------------------------------------------------------------------ */ 3512 static const unsigned int sdhi1_data1_pins[] = { 3513 /* D0 */ 3514 RCAR_GP_PIN(3, 8), 3515 }; 3516 static const unsigned int sdhi1_data1_mux[] = { 3517 SD1_DAT0_MARK, 3518 }; 3519 static const unsigned int sdhi1_data4_pins[] = { 3520 /* D[0:3] */ 3521 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), 3522 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), 3523 }; 3524 static const unsigned int sdhi1_data4_mux[] = { 3525 SD1_DAT0_MARK, SD1_DAT1_MARK, 3526 SD1_DAT2_MARK, SD1_DAT3_MARK, 3527 }; 3528 static const unsigned int sdhi1_ctrl_pins[] = { 3529 /* CLK, CMD */ 3530 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), 3531 }; 3532 static const unsigned int sdhi1_ctrl_mux[] = { 3533 SD1_CLK_MARK, SD1_CMD_MARK, 3534 }; 3535 static const unsigned int sdhi1_cd_pins[] = { 3536 /* CD */ 3537 RCAR_GP_PIN(3, 14), 3538 }; 3539 static const unsigned int sdhi1_cd_mux[] = { 3540 SD1_CD_MARK, 3541 }; 3542 static const unsigned int sdhi1_wp_pins[] = { 3543 /* WP */ 3544 RCAR_GP_PIN(3, 15), 3545 }; 3546 static const unsigned int sdhi1_wp_mux[] = { 3547 SD1_WP_MARK, 3548 }; 3549 /* - SDHI2 ------------------------------------------------------------------ */ 3550 static const unsigned int sdhi2_data1_pins[] = { 3551 /* D0 */ 3552 RCAR_GP_PIN(4, 2), 3553 }; 3554 static const unsigned int sdhi2_data1_mux[] = { 3555 SD2_DAT0_MARK, 3556 }; 3557 static const unsigned int sdhi2_data4_pins[] = { 3558 /* D[0:3] */ 3559 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), 3560 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), 3561 }; 3562 static const unsigned int sdhi2_data4_mux[] = { 3563 SD2_DAT0_MARK, SD2_DAT1_MARK, 3564 SD2_DAT2_MARK, SD2_DAT3_MARK, 3565 }; 3566 static const unsigned int sdhi2_data8_pins[] = { 3567 /* D[0:7] */ 3568 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), 3569 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), 3570 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), 3571 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), 3572 }; 3573 static const unsigned int sdhi2_data8_mux[] = { 3574 SD2_DAT0_MARK, SD2_DAT1_MARK, 3575 SD2_DAT2_MARK, SD2_DAT3_MARK, 3576 SD2_DAT4_MARK, SD2_DAT5_MARK, 3577 SD2_DAT6_MARK, SD2_DAT7_MARK, 3578 }; 3579 static const unsigned int sdhi2_ctrl_pins[] = { 3580 /* CLK, CMD */ 3581 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1), 3582 }; 3583 static const unsigned int sdhi2_ctrl_mux[] = { 3584 SD2_CLK_MARK, SD2_CMD_MARK, 3585 }; 3586 static const unsigned int sdhi2_cd_a_pins[] = { 3587 /* CD */ 3588 RCAR_GP_PIN(4, 13), 3589 }; 3590 static const unsigned int sdhi2_cd_a_mux[] = { 3591 SD2_CD_A_MARK, 3592 }; 3593 static const unsigned int sdhi2_cd_b_pins[] = { 3594 /* CD */ 3595 RCAR_GP_PIN(5, 10), 3596 }; 3597 static const unsigned int sdhi2_cd_b_mux[] = { 3598 SD2_CD_B_MARK, 3599 }; 3600 static const unsigned int sdhi2_wp_a_pins[] = { 3601 /* WP */ 3602 RCAR_GP_PIN(4, 14), 3603 }; 3604 static const unsigned int sdhi2_wp_a_mux[] = { 3605 SD2_WP_A_MARK, 3606 }; 3607 static const unsigned int sdhi2_wp_b_pins[] = { 3608 /* WP */ 3609 RCAR_GP_PIN(5, 11), 3610 }; 3611 static const unsigned int sdhi2_wp_b_mux[] = { 3612 SD2_WP_B_MARK, 3613 }; 3614 static const unsigned int sdhi2_ds_pins[] = { 3615 /* DS */ 3616 RCAR_GP_PIN(4, 6), 3617 }; 3618 static const unsigned int sdhi2_ds_mux[] = { 3619 SD2_DS_MARK, 3620 }; 3621 /* - SDHI3 ------------------------------------------------------------------ */ 3622 static const unsigned int sdhi3_data1_pins[] = { 3623 /* D0 */ 3624 RCAR_GP_PIN(4, 9), 3625 }; 3626 static const unsigned int sdhi3_data1_mux[] = { 3627 SD3_DAT0_MARK, 3628 }; 3629 static const unsigned int sdhi3_data4_pins[] = { 3630 /* D[0:3] */ 3631 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10), 3632 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12), 3633 }; 3634 static const unsigned int sdhi3_data4_mux[] = { 3635 SD3_DAT0_MARK, SD3_DAT1_MARK, 3636 SD3_DAT2_MARK, SD3_DAT3_MARK, 3637 }; 3638 static const unsigned int sdhi3_data8_pins[] = { 3639 /* D[0:7] */ 3640 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10), 3641 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12), 3642 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14), 3643 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16), 3644 }; 3645 static const unsigned int sdhi3_data8_mux[] = { 3646 SD3_DAT0_MARK, SD3_DAT1_MARK, 3647 SD3_DAT2_MARK, SD3_DAT3_MARK, 3648 SD3_DAT4_MARK, SD3_DAT5_MARK, 3649 SD3_DAT6_MARK, SD3_DAT7_MARK, 3650 }; 3651 static const unsigned int sdhi3_ctrl_pins[] = { 3652 /* CLK, CMD */ 3653 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8), 3654 }; 3655 static const unsigned int sdhi3_ctrl_mux[] = { 3656 SD3_CLK_MARK, SD3_CMD_MARK, 3657 }; 3658 static const unsigned int sdhi3_cd_pins[] = { 3659 /* CD */ 3660 RCAR_GP_PIN(4, 15), 3661 }; 3662 static const unsigned int sdhi3_cd_mux[] = { 3663 SD3_CD_MARK, 3664 }; 3665 static const unsigned int sdhi3_wp_pins[] = { 3666 /* WP */ 3667 RCAR_GP_PIN(4, 16), 3668 }; 3669 static const unsigned int sdhi3_wp_mux[] = { 3670 SD3_WP_MARK, 3671 }; 3672 static const unsigned int sdhi3_ds_pins[] = { 3673 /* DS */ 3674 RCAR_GP_PIN(4, 17), 3675 }; 3676 static const unsigned int sdhi3_ds_mux[] = { 3677 SD3_DS_MARK, 3678 }; 3679 3680 /* - SSI -------------------------------------------------------------------- */ 3681 static const unsigned int ssi0_data_pins[] = { 3682 /* SDATA */ 3683 RCAR_GP_PIN(6, 2), 3684 }; 3685 static const unsigned int ssi0_data_mux[] = { 3686 SSI_SDATA0_MARK, 3687 }; 3688 static const unsigned int ssi01239_ctrl_pins[] = { 3689 /* SCK, WS */ 3690 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1), 3691 }; 3692 static const unsigned int ssi01239_ctrl_mux[] = { 3693 SSI_SCK01239_MARK, SSI_WS01239_MARK, 3694 }; 3695 static const unsigned int ssi1_data_a_pins[] = { 3696 /* SDATA */ 3697 RCAR_GP_PIN(6, 3), 3698 }; 3699 static const unsigned int ssi1_data_a_mux[] = { 3700 SSI_SDATA1_A_MARK, 3701 }; 3702 static const unsigned int ssi1_data_b_pins[] = { 3703 /* SDATA */ 3704 RCAR_GP_PIN(5, 12), 3705 }; 3706 static const unsigned int ssi1_data_b_mux[] = { 3707 SSI_SDATA1_B_MARK, 3708 }; 3709 static const unsigned int ssi1_ctrl_a_pins[] = { 3710 /* SCK, WS */ 3711 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27), 3712 }; 3713 static const unsigned int ssi1_ctrl_a_mux[] = { 3714 SSI_SCK1_A_MARK, SSI_WS1_A_MARK, 3715 }; 3716 static const unsigned int ssi1_ctrl_b_pins[] = { 3717 /* SCK, WS */ 3718 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21), 3719 }; 3720 static const unsigned int ssi1_ctrl_b_mux[] = { 3721 SSI_SCK1_B_MARK, SSI_WS1_B_MARK, 3722 }; 3723 static const unsigned int ssi2_data_a_pins[] = { 3724 /* SDATA */ 3725 RCAR_GP_PIN(6, 4), 3726 }; 3727 static const unsigned int ssi2_data_a_mux[] = { 3728 SSI_SDATA2_A_MARK, 3729 }; 3730 static const unsigned int ssi2_data_b_pins[] = { 3731 /* SDATA */ 3732 RCAR_GP_PIN(5, 13), 3733 }; 3734 static const unsigned int ssi2_data_b_mux[] = { 3735 SSI_SDATA2_B_MARK, 3736 }; 3737 static const unsigned int ssi2_ctrl_a_pins[] = { 3738 /* SCK, WS */ 3739 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21), 3740 }; 3741 static const unsigned int ssi2_ctrl_a_mux[] = { 3742 SSI_SCK2_A_MARK, SSI_WS2_A_MARK, 3743 }; 3744 static const unsigned int ssi2_ctrl_b_pins[] = { 3745 /* SCK, WS */ 3746 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29), 3747 }; 3748 static const unsigned int ssi2_ctrl_b_mux[] = { 3749 SSI_SCK2_B_MARK, SSI_WS2_B_MARK, 3750 }; 3751 static const unsigned int ssi3_data_pins[] = { 3752 /* SDATA */ 3753 RCAR_GP_PIN(6, 7), 3754 }; 3755 static const unsigned int ssi3_data_mux[] = { 3756 SSI_SDATA3_MARK, 3757 }; 3758 static const unsigned int ssi349_ctrl_pins[] = { 3759 /* SCK, WS */ 3760 RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6), 3761 }; 3762 static const unsigned int ssi349_ctrl_mux[] = { 3763 SSI_SCK349_MARK, SSI_WS349_MARK, 3764 }; 3765 static const unsigned int ssi4_data_pins[] = { 3766 /* SDATA */ 3767 RCAR_GP_PIN(6, 10), 3768 }; 3769 static const unsigned int ssi4_data_mux[] = { 3770 SSI_SDATA4_MARK, 3771 }; 3772 static const unsigned int ssi4_ctrl_pins[] = { 3773 /* SCK, WS */ 3774 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), 3775 }; 3776 static const unsigned int ssi4_ctrl_mux[] = { 3777 SSI_SCK4_MARK, SSI_WS4_MARK, 3778 }; 3779 static const unsigned int ssi5_data_pins[] = { 3780 /* SDATA */ 3781 RCAR_GP_PIN(6, 13), 3782 }; 3783 static const unsigned int ssi5_data_mux[] = { 3784 SSI_SDATA5_MARK, 3785 }; 3786 static const unsigned int ssi5_ctrl_pins[] = { 3787 /* SCK, WS */ 3788 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12), 3789 }; 3790 static const unsigned int ssi5_ctrl_mux[] = { 3791 SSI_SCK5_MARK, SSI_WS5_MARK, 3792 }; 3793 static const unsigned int ssi6_data_pins[] = { 3794 /* SDATA */ 3795 RCAR_GP_PIN(6, 16), 3796 }; 3797 static const unsigned int ssi6_data_mux[] = { 3798 SSI_SDATA6_MARK, 3799 }; 3800 static const unsigned int ssi6_ctrl_pins[] = { 3801 /* SCK, WS */ 3802 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15), 3803 }; 3804 static const unsigned int ssi6_ctrl_mux[] = { 3805 SSI_SCK6_MARK, SSI_WS6_MARK, 3806 }; 3807 static const unsigned int ssi7_data_pins[] = { 3808 /* SDATA */ 3809 RCAR_GP_PIN(6, 19), 3810 }; 3811 static const unsigned int ssi7_data_mux[] = { 3812 SSI_SDATA7_MARK, 3813 }; 3814 static const unsigned int ssi78_ctrl_pins[] = { 3815 /* SCK, WS */ 3816 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18), 3817 }; 3818 static const unsigned int ssi78_ctrl_mux[] = { 3819 SSI_SCK78_MARK, SSI_WS78_MARK, 3820 }; 3821 static const unsigned int ssi8_data_pins[] = { 3822 /* SDATA */ 3823 RCAR_GP_PIN(6, 20), 3824 }; 3825 static const unsigned int ssi8_data_mux[] = { 3826 SSI_SDATA8_MARK, 3827 }; 3828 static const unsigned int ssi9_data_a_pins[] = { 3829 /* SDATA */ 3830 RCAR_GP_PIN(6, 21), 3831 }; 3832 static const unsigned int ssi9_data_a_mux[] = { 3833 SSI_SDATA9_A_MARK, 3834 }; 3835 static const unsigned int ssi9_data_b_pins[] = { 3836 /* SDATA */ 3837 RCAR_GP_PIN(5, 14), 3838 }; 3839 static const unsigned int ssi9_data_b_mux[] = { 3840 SSI_SDATA9_B_MARK, 3841 }; 3842 static const unsigned int ssi9_ctrl_a_pins[] = { 3843 /* SCK, WS */ 3844 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16), 3845 }; 3846 static const unsigned int ssi9_ctrl_a_mux[] = { 3847 SSI_SCK9_A_MARK, SSI_WS9_A_MARK, 3848 }; 3849 static const unsigned int ssi9_ctrl_b_pins[] = { 3850 /* SCK, WS */ 3851 RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31), 3852 }; 3853 static const unsigned int ssi9_ctrl_b_mux[] = { 3854 SSI_SCK9_B_MARK, SSI_WS9_B_MARK, 3855 }; 3856 3857 /* - TMU -------------------------------------------------------------------- */ 3858 static const unsigned int tmu_tclk1_a_pins[] = { 3859 /* TCLK */ 3860 RCAR_GP_PIN(6, 23), 3861 }; 3862 static const unsigned int tmu_tclk1_a_mux[] = { 3863 TCLK1_A_MARK, 3864 }; 3865 static const unsigned int tmu_tclk1_b_pins[] = { 3866 /* TCLK */ 3867 RCAR_GP_PIN(5, 19), 3868 }; 3869 static const unsigned int tmu_tclk1_b_mux[] = { 3870 TCLK1_B_MARK, 3871 }; 3872 static const unsigned int tmu_tclk2_a_pins[] = { 3873 /* TCLK */ 3874 RCAR_GP_PIN(6, 19), 3875 }; 3876 static const unsigned int tmu_tclk2_a_mux[] = { 3877 TCLK2_A_MARK, 3878 }; 3879 static const unsigned int tmu_tclk2_b_pins[] = { 3880 /* TCLK */ 3881 RCAR_GP_PIN(6, 28), 3882 }; 3883 static const unsigned int tmu_tclk2_b_mux[] = { 3884 TCLK2_B_MARK, 3885 }; 3886 3887 /* - TPU ------------------------------------------------------------------- */ 3888 static const unsigned int tpu_to0_pins[] = { 3889 /* TPU0TO0 */ 3890 RCAR_GP_PIN(6, 28), 3891 }; 3892 static const unsigned int tpu_to0_mux[] = { 3893 TPU0TO0_MARK, 3894 }; 3895 static const unsigned int tpu_to1_pins[] = { 3896 /* TPU0TO1 */ 3897 RCAR_GP_PIN(6, 29), 3898 }; 3899 static const unsigned int tpu_to1_mux[] = { 3900 TPU0TO1_MARK, 3901 }; 3902 static const unsigned int tpu_to2_pins[] = { 3903 /* TPU0TO2 */ 3904 RCAR_GP_PIN(6, 30), 3905 }; 3906 static const unsigned int tpu_to2_mux[] = { 3907 TPU0TO2_MARK, 3908 }; 3909 static const unsigned int tpu_to3_pins[] = { 3910 /* TPU0TO3 */ 3911 RCAR_GP_PIN(6, 31), 3912 }; 3913 static const unsigned int tpu_to3_mux[] = { 3914 TPU0TO3_MARK, 3915 }; 3916 3917 /* - USB0 ------------------------------------------------------------------- */ 3918 static const unsigned int usb0_pins[] = { 3919 /* PWEN, OVC */ 3920 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25), 3921 }; 3922 static const unsigned int usb0_mux[] = { 3923 USB0_PWEN_MARK, USB0_OVC_MARK, 3924 }; 3925 /* - USB1 ------------------------------------------------------------------- */ 3926 static const unsigned int usb1_pins[] = { 3927 /* PWEN, OVC */ 3928 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27), 3929 }; 3930 static const unsigned int usb1_mux[] = { 3931 USB1_PWEN_MARK, USB1_OVC_MARK, 3932 }; 3933 3934 /* - USB30 ------------------------------------------------------------------ */ 3935 static const unsigned int usb30_pins[] = { 3936 /* PWEN, OVC */ 3937 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29), 3938 }; 3939 static const unsigned int usb30_mux[] = { 3940 USB30_PWEN_MARK, USB30_OVC_MARK, 3941 }; 3942 3943 /* - VIN4 ------------------------------------------------------------------- */ 3944 static const unsigned int vin4_data18_a_pins[] = { 3945 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), 3946 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), 3947 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), 3948 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), 3949 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), 3950 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 3951 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), 3952 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), 3953 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), 3954 }; 3955 static const unsigned int vin4_data18_a_mux[] = { 3956 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK, 3957 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK, 3958 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK, 3959 VI4_DATA10_MARK, VI4_DATA11_MARK, 3960 VI4_DATA12_MARK, VI4_DATA13_MARK, 3961 VI4_DATA14_MARK, VI4_DATA15_MARK, 3962 VI4_DATA18_MARK, VI4_DATA19_MARK, 3963 VI4_DATA20_MARK, VI4_DATA21_MARK, 3964 VI4_DATA22_MARK, VI4_DATA23_MARK, 3965 }; 3966 static const unsigned int vin4_data18_b_pins[] = { 3967 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), 3968 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), 3969 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), 3970 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), 3971 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), 3972 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 3973 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), 3974 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), 3975 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), 3976 }; 3977 static const unsigned int vin4_data18_b_mux[] = { 3978 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK, 3979 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK, 3980 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK, 3981 VI4_DATA10_MARK, VI4_DATA11_MARK, 3982 VI4_DATA12_MARK, VI4_DATA13_MARK, 3983 VI4_DATA14_MARK, VI4_DATA15_MARK, 3984 VI4_DATA18_MARK, VI4_DATA19_MARK, 3985 VI4_DATA20_MARK, VI4_DATA21_MARK, 3986 VI4_DATA22_MARK, VI4_DATA23_MARK, 3987 }; 3988 static const union vin_data vin4_data_a_pins = { 3989 .data24 = { 3990 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), 3991 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), 3992 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), 3993 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), 3994 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), 3995 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), 3996 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), 3997 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 3998 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), 3999 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), 4000 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), 4001 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), 4002 }, 4003 }; 4004 static const union vin_data vin4_data_a_mux = { 4005 .data24 = { 4006 VI4_DATA0_A_MARK, VI4_DATA1_A_MARK, 4007 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK, 4008 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK, 4009 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK, 4010 VI4_DATA8_MARK, VI4_DATA9_MARK, 4011 VI4_DATA10_MARK, VI4_DATA11_MARK, 4012 VI4_DATA12_MARK, VI4_DATA13_MARK, 4013 VI4_DATA14_MARK, VI4_DATA15_MARK, 4014 VI4_DATA16_MARK, VI4_DATA17_MARK, 4015 VI4_DATA18_MARK, VI4_DATA19_MARK, 4016 VI4_DATA20_MARK, VI4_DATA21_MARK, 4017 VI4_DATA22_MARK, VI4_DATA23_MARK, 4018 }, 4019 }; 4020 static const union vin_data vin4_data_b_pins = { 4021 .data24 = { 4022 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), 4023 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), 4024 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), 4025 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), 4026 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), 4027 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), 4028 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), 4029 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 4030 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), 4031 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), 4032 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), 4033 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), 4034 }, 4035 }; 4036 static const union vin_data vin4_data_b_mux = { 4037 .data24 = { 4038 VI4_DATA0_B_MARK, VI4_DATA1_B_MARK, 4039 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK, 4040 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK, 4041 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK, 4042 VI4_DATA8_MARK, VI4_DATA9_MARK, 4043 VI4_DATA10_MARK, VI4_DATA11_MARK, 4044 VI4_DATA12_MARK, VI4_DATA13_MARK, 4045 VI4_DATA14_MARK, VI4_DATA15_MARK, 4046 VI4_DATA16_MARK, VI4_DATA17_MARK, 4047 VI4_DATA18_MARK, VI4_DATA19_MARK, 4048 VI4_DATA20_MARK, VI4_DATA21_MARK, 4049 VI4_DATA22_MARK, VI4_DATA23_MARK, 4050 }, 4051 }; 4052 static const unsigned int vin4_sync_pins[] = { 4053 /* HSYNC#, VSYNC# */ 4054 RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 17), 4055 }; 4056 static const unsigned int vin4_sync_mux[] = { 4057 VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK, 4058 }; 4059 static const unsigned int vin4_field_pins[] = { 4060 /* FIELD */ 4061 RCAR_GP_PIN(1, 16), 4062 }; 4063 static const unsigned int vin4_field_mux[] = { 4064 VI4_FIELD_MARK, 4065 }; 4066 static const unsigned int vin4_clkenb_pins[] = { 4067 /* CLKENB */ 4068 RCAR_GP_PIN(1, 19), 4069 }; 4070 static const unsigned int vin4_clkenb_mux[] = { 4071 VI4_CLKENB_MARK, 4072 }; 4073 static const unsigned int vin4_clk_pins[] = { 4074 /* CLK */ 4075 RCAR_GP_PIN(1, 27), 4076 }; 4077 static const unsigned int vin4_clk_mux[] = { 4078 VI4_CLK_MARK, 4079 }; 4080 4081 /* - VIN5 ------------------------------------------------------------------- */ 4082 static const union vin_data16 vin5_data_pins = { 4083 .data16 = { 4084 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), 4085 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), 4086 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), 4087 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), 4088 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), 4089 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), 4090 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), 4091 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 4092 }, 4093 }; 4094 static const union vin_data16 vin5_data_mux = { 4095 .data16 = { 4096 VI5_DATA0_MARK, VI5_DATA1_MARK, 4097 VI5_DATA2_MARK, VI5_DATA3_MARK, 4098 VI5_DATA4_MARK, VI5_DATA5_MARK, 4099 VI5_DATA6_MARK, VI5_DATA7_MARK, 4100 VI5_DATA8_MARK, VI5_DATA9_MARK, 4101 VI5_DATA10_MARK, VI5_DATA11_MARK, 4102 VI5_DATA12_MARK, VI5_DATA13_MARK, 4103 VI5_DATA14_MARK, VI5_DATA15_MARK, 4104 }, 4105 }; 4106 static const unsigned int vin5_sync_pins[] = { 4107 /* HSYNC#, VSYNC# */ 4108 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9), 4109 }; 4110 static const unsigned int vin5_sync_mux[] = { 4111 VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK, 4112 }; 4113 static const unsigned int vin5_field_pins[] = { 4114 RCAR_GP_PIN(1, 11), 4115 }; 4116 static const unsigned int vin5_field_mux[] = { 4117 /* FIELD */ 4118 VI5_FIELD_MARK, 4119 }; 4120 static const unsigned int vin5_clkenb_pins[] = { 4121 RCAR_GP_PIN(1, 20), 4122 }; 4123 static const unsigned int vin5_clkenb_mux[] = { 4124 /* CLKENB */ 4125 VI5_CLKENB_MARK, 4126 }; 4127 static const unsigned int vin5_clk_pins[] = { 4128 RCAR_GP_PIN(1, 21), 4129 }; 4130 static const unsigned int vin5_clk_mux[] = { 4131 /* CLK */ 4132 VI5_CLK_MARK, 4133 }; 4134 4135 static const struct { 4136 struct sh_pfc_pin_group common[316]; 4137 struct sh_pfc_pin_group automotive[30]; 4138 } pinmux_groups = { 4139 .common = { 4140 SH_PFC_PIN_GROUP(audio_clk_a_a), 4141 SH_PFC_PIN_GROUP(audio_clk_a_b), 4142 SH_PFC_PIN_GROUP(audio_clk_a_c), 4143 SH_PFC_PIN_GROUP(audio_clk_b_a), 4144 SH_PFC_PIN_GROUP(audio_clk_b_b), 4145 SH_PFC_PIN_GROUP(audio_clk_c_a), 4146 SH_PFC_PIN_GROUP(audio_clk_c_b), 4147 SH_PFC_PIN_GROUP(audio_clkout_a), 4148 SH_PFC_PIN_GROUP(audio_clkout_b), 4149 SH_PFC_PIN_GROUP(audio_clkout_c), 4150 SH_PFC_PIN_GROUP(audio_clkout_d), 4151 SH_PFC_PIN_GROUP(audio_clkout1_a), 4152 SH_PFC_PIN_GROUP(audio_clkout1_b), 4153 SH_PFC_PIN_GROUP(audio_clkout2_a), 4154 SH_PFC_PIN_GROUP(audio_clkout2_b), 4155 SH_PFC_PIN_GROUP(audio_clkout3_a), 4156 SH_PFC_PIN_GROUP(audio_clkout3_b), 4157 SH_PFC_PIN_GROUP(avb_link), 4158 SH_PFC_PIN_GROUP(avb_magic), 4159 SH_PFC_PIN_GROUP(avb_phy_int), 4160 SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio), /* Deprecated */ 4161 SH_PFC_PIN_GROUP(avb_mdio), 4162 SH_PFC_PIN_GROUP(avb_mii), 4163 SH_PFC_PIN_GROUP(avb_avtp_pps), 4164 SH_PFC_PIN_GROUP(avb_avtp_match_a), 4165 SH_PFC_PIN_GROUP(avb_avtp_capture_a), 4166 SH_PFC_PIN_GROUP(avb_avtp_match_b), 4167 SH_PFC_PIN_GROUP(avb_avtp_capture_b), 4168 SH_PFC_PIN_GROUP(can0_data_a), 4169 SH_PFC_PIN_GROUP(can0_data_b), 4170 SH_PFC_PIN_GROUP(can1_data), 4171 SH_PFC_PIN_GROUP(can_clk), 4172 SH_PFC_PIN_GROUP(canfd0_data_a), 4173 SH_PFC_PIN_GROUP(canfd0_data_b), 4174 SH_PFC_PIN_GROUP(canfd1_data), 4175 SH_PFC_PIN_GROUP(du_rgb666), 4176 SH_PFC_PIN_GROUP(du_rgb888), 4177 SH_PFC_PIN_GROUP(du_clk_out_0), 4178 SH_PFC_PIN_GROUP(du_clk_out_1), 4179 SH_PFC_PIN_GROUP(du_sync), 4180 SH_PFC_PIN_GROUP(du_oddf), 4181 SH_PFC_PIN_GROUP(du_cde), 4182 SH_PFC_PIN_GROUP(du_disp), 4183 SH_PFC_PIN_GROUP(hscif0_data), 4184 SH_PFC_PIN_GROUP(hscif0_clk), 4185 SH_PFC_PIN_GROUP(hscif0_ctrl), 4186 SH_PFC_PIN_GROUP(hscif1_data_a), 4187 SH_PFC_PIN_GROUP(hscif1_clk_a), 4188 SH_PFC_PIN_GROUP(hscif1_ctrl_a), 4189 SH_PFC_PIN_GROUP(hscif1_data_b), 4190 SH_PFC_PIN_GROUP(hscif1_clk_b), 4191 SH_PFC_PIN_GROUP(hscif1_ctrl_b), 4192 SH_PFC_PIN_GROUP(hscif2_data_a), 4193 SH_PFC_PIN_GROUP(hscif2_clk_a), 4194 SH_PFC_PIN_GROUP(hscif2_ctrl_a), 4195 SH_PFC_PIN_GROUP(hscif2_data_b), 4196 SH_PFC_PIN_GROUP(hscif2_clk_b), 4197 SH_PFC_PIN_GROUP(hscif2_ctrl_b), 4198 SH_PFC_PIN_GROUP(hscif2_data_c), 4199 SH_PFC_PIN_GROUP(hscif2_clk_c), 4200 SH_PFC_PIN_GROUP(hscif2_ctrl_c), 4201 SH_PFC_PIN_GROUP(hscif3_data_a), 4202 SH_PFC_PIN_GROUP(hscif3_clk), 4203 SH_PFC_PIN_GROUP(hscif3_ctrl), 4204 SH_PFC_PIN_GROUP(hscif3_data_b), 4205 SH_PFC_PIN_GROUP(hscif3_data_c), 4206 SH_PFC_PIN_GROUP(hscif3_data_d), 4207 SH_PFC_PIN_GROUP(hscif4_data_a), 4208 SH_PFC_PIN_GROUP(hscif4_clk), 4209 SH_PFC_PIN_GROUP(hscif4_ctrl), 4210 SH_PFC_PIN_GROUP(hscif4_data_b), 4211 SH_PFC_PIN_GROUP(i2c0), 4212 SH_PFC_PIN_GROUP(i2c1_a), 4213 SH_PFC_PIN_GROUP(i2c1_b), 4214 SH_PFC_PIN_GROUP(i2c2_a), 4215 SH_PFC_PIN_GROUP(i2c2_b), 4216 SH_PFC_PIN_GROUP(i2c3), 4217 SH_PFC_PIN_GROUP(i2c5), 4218 SH_PFC_PIN_GROUP(i2c6_a), 4219 SH_PFC_PIN_GROUP(i2c6_b), 4220 SH_PFC_PIN_GROUP(i2c6_c), 4221 SH_PFC_PIN_GROUP(intc_ex_irq0), 4222 SH_PFC_PIN_GROUP(intc_ex_irq1), 4223 SH_PFC_PIN_GROUP(intc_ex_irq2), 4224 SH_PFC_PIN_GROUP(intc_ex_irq3), 4225 SH_PFC_PIN_GROUP(intc_ex_irq4), 4226 SH_PFC_PIN_GROUP(intc_ex_irq5), 4227 SH_PFC_PIN_GROUP(msiof0_clk), 4228 SH_PFC_PIN_GROUP(msiof0_sync), 4229 SH_PFC_PIN_GROUP(msiof0_ss1), 4230 SH_PFC_PIN_GROUP(msiof0_ss2), 4231 SH_PFC_PIN_GROUP(msiof0_txd), 4232 SH_PFC_PIN_GROUP(msiof0_rxd), 4233 SH_PFC_PIN_GROUP(msiof1_clk_a), 4234 SH_PFC_PIN_GROUP(msiof1_sync_a), 4235 SH_PFC_PIN_GROUP(msiof1_ss1_a), 4236 SH_PFC_PIN_GROUP(msiof1_ss2_a), 4237 SH_PFC_PIN_GROUP(msiof1_txd_a), 4238 SH_PFC_PIN_GROUP(msiof1_rxd_a), 4239 SH_PFC_PIN_GROUP(msiof1_clk_b), 4240 SH_PFC_PIN_GROUP(msiof1_sync_b), 4241 SH_PFC_PIN_GROUP(msiof1_ss1_b), 4242 SH_PFC_PIN_GROUP(msiof1_ss2_b), 4243 SH_PFC_PIN_GROUP(msiof1_txd_b), 4244 SH_PFC_PIN_GROUP(msiof1_rxd_b), 4245 SH_PFC_PIN_GROUP(msiof1_clk_c), 4246 SH_PFC_PIN_GROUP(msiof1_sync_c), 4247 SH_PFC_PIN_GROUP(msiof1_ss1_c), 4248 SH_PFC_PIN_GROUP(msiof1_ss2_c), 4249 SH_PFC_PIN_GROUP(msiof1_txd_c), 4250 SH_PFC_PIN_GROUP(msiof1_rxd_c), 4251 SH_PFC_PIN_GROUP(msiof1_clk_d), 4252 SH_PFC_PIN_GROUP(msiof1_sync_d), 4253 SH_PFC_PIN_GROUP(msiof1_ss1_d), 4254 SH_PFC_PIN_GROUP(msiof1_ss2_d), 4255 SH_PFC_PIN_GROUP(msiof1_txd_d), 4256 SH_PFC_PIN_GROUP(msiof1_rxd_d), 4257 SH_PFC_PIN_GROUP(msiof1_clk_e), 4258 SH_PFC_PIN_GROUP(msiof1_sync_e), 4259 SH_PFC_PIN_GROUP(msiof1_ss1_e), 4260 SH_PFC_PIN_GROUP(msiof1_ss2_e), 4261 SH_PFC_PIN_GROUP(msiof1_txd_e), 4262 SH_PFC_PIN_GROUP(msiof1_rxd_e), 4263 SH_PFC_PIN_GROUP(msiof1_clk_f), 4264 SH_PFC_PIN_GROUP(msiof1_sync_f), 4265 SH_PFC_PIN_GROUP(msiof1_ss1_f), 4266 SH_PFC_PIN_GROUP(msiof1_ss2_f), 4267 SH_PFC_PIN_GROUP(msiof1_txd_f), 4268 SH_PFC_PIN_GROUP(msiof1_rxd_f), 4269 SH_PFC_PIN_GROUP(msiof1_clk_g), 4270 SH_PFC_PIN_GROUP(msiof1_sync_g), 4271 SH_PFC_PIN_GROUP(msiof1_ss1_g), 4272 SH_PFC_PIN_GROUP(msiof1_ss2_g), 4273 SH_PFC_PIN_GROUP(msiof1_txd_g), 4274 SH_PFC_PIN_GROUP(msiof1_rxd_g), 4275 SH_PFC_PIN_GROUP(msiof2_clk_a), 4276 SH_PFC_PIN_GROUP(msiof2_sync_a), 4277 SH_PFC_PIN_GROUP(msiof2_ss1_a), 4278 SH_PFC_PIN_GROUP(msiof2_ss2_a), 4279 SH_PFC_PIN_GROUP(msiof2_txd_a), 4280 SH_PFC_PIN_GROUP(msiof2_rxd_a), 4281 SH_PFC_PIN_GROUP(msiof2_clk_b), 4282 SH_PFC_PIN_GROUP(msiof2_sync_b), 4283 SH_PFC_PIN_GROUP(msiof2_ss1_b), 4284 SH_PFC_PIN_GROUP(msiof2_ss2_b), 4285 SH_PFC_PIN_GROUP(msiof2_txd_b), 4286 SH_PFC_PIN_GROUP(msiof2_rxd_b), 4287 SH_PFC_PIN_GROUP(msiof2_clk_c), 4288 SH_PFC_PIN_GROUP(msiof2_sync_c), 4289 SH_PFC_PIN_GROUP(msiof2_ss1_c), 4290 SH_PFC_PIN_GROUP(msiof2_ss2_c), 4291 SH_PFC_PIN_GROUP(msiof2_txd_c), 4292 SH_PFC_PIN_GROUP(msiof2_rxd_c), 4293 SH_PFC_PIN_GROUP(msiof2_clk_d), 4294 SH_PFC_PIN_GROUP(msiof2_sync_d), 4295 SH_PFC_PIN_GROUP(msiof2_ss1_d), 4296 SH_PFC_PIN_GROUP(msiof2_ss2_d), 4297 SH_PFC_PIN_GROUP(msiof2_txd_d), 4298 SH_PFC_PIN_GROUP(msiof2_rxd_d), 4299 SH_PFC_PIN_GROUP(msiof3_clk_a), 4300 SH_PFC_PIN_GROUP(msiof3_sync_a), 4301 SH_PFC_PIN_GROUP(msiof3_ss1_a), 4302 SH_PFC_PIN_GROUP(msiof3_ss2_a), 4303 SH_PFC_PIN_GROUP(msiof3_txd_a), 4304 SH_PFC_PIN_GROUP(msiof3_rxd_a), 4305 SH_PFC_PIN_GROUP(msiof3_clk_b), 4306 SH_PFC_PIN_GROUP(msiof3_sync_b), 4307 SH_PFC_PIN_GROUP(msiof3_ss1_b), 4308 SH_PFC_PIN_GROUP(msiof3_ss2_b), 4309 SH_PFC_PIN_GROUP(msiof3_txd_b), 4310 SH_PFC_PIN_GROUP(msiof3_rxd_b), 4311 SH_PFC_PIN_GROUP(msiof3_clk_c), 4312 SH_PFC_PIN_GROUP(msiof3_sync_c), 4313 SH_PFC_PIN_GROUP(msiof3_txd_c), 4314 SH_PFC_PIN_GROUP(msiof3_rxd_c), 4315 SH_PFC_PIN_GROUP(msiof3_clk_d), 4316 SH_PFC_PIN_GROUP(msiof3_sync_d), 4317 SH_PFC_PIN_GROUP(msiof3_ss1_d), 4318 SH_PFC_PIN_GROUP(msiof3_txd_d), 4319 SH_PFC_PIN_GROUP(msiof3_rxd_d), 4320 SH_PFC_PIN_GROUP(msiof3_clk_e), 4321 SH_PFC_PIN_GROUP(msiof3_sync_e), 4322 SH_PFC_PIN_GROUP(msiof3_ss1_e), 4323 SH_PFC_PIN_GROUP(msiof3_ss2_e), 4324 SH_PFC_PIN_GROUP(msiof3_txd_e), 4325 SH_PFC_PIN_GROUP(msiof3_rxd_e), 4326 SH_PFC_PIN_GROUP(pwm0), 4327 SH_PFC_PIN_GROUP(pwm1_a), 4328 SH_PFC_PIN_GROUP(pwm1_b), 4329 SH_PFC_PIN_GROUP(pwm2_a), 4330 SH_PFC_PIN_GROUP(pwm2_b), 4331 SH_PFC_PIN_GROUP(pwm3_a), 4332 SH_PFC_PIN_GROUP(pwm3_b), 4333 SH_PFC_PIN_GROUP(pwm4_a), 4334 SH_PFC_PIN_GROUP(pwm4_b), 4335 SH_PFC_PIN_GROUP(pwm5_a), 4336 SH_PFC_PIN_GROUP(pwm5_b), 4337 SH_PFC_PIN_GROUP(pwm6_a), 4338 SH_PFC_PIN_GROUP(pwm6_b), 4339 SH_PFC_PIN_GROUP(scif0_data), 4340 SH_PFC_PIN_GROUP(scif0_clk), 4341 SH_PFC_PIN_GROUP(scif0_ctrl), 4342 SH_PFC_PIN_GROUP(scif1_data_a), 4343 SH_PFC_PIN_GROUP(scif1_clk), 4344 SH_PFC_PIN_GROUP(scif1_ctrl), 4345 SH_PFC_PIN_GROUP(scif1_data_b), 4346 SH_PFC_PIN_GROUP(scif2_data_a), 4347 SH_PFC_PIN_GROUP(scif2_clk), 4348 SH_PFC_PIN_GROUP(scif2_data_b), 4349 SH_PFC_PIN_GROUP(scif3_data_a), 4350 SH_PFC_PIN_GROUP(scif3_clk), 4351 SH_PFC_PIN_GROUP(scif3_ctrl), 4352 SH_PFC_PIN_GROUP(scif3_data_b), 4353 SH_PFC_PIN_GROUP(scif4_data_a), 4354 SH_PFC_PIN_GROUP(scif4_clk_a), 4355 SH_PFC_PIN_GROUP(scif4_ctrl_a), 4356 SH_PFC_PIN_GROUP(scif4_data_b), 4357 SH_PFC_PIN_GROUP(scif4_clk_b), 4358 SH_PFC_PIN_GROUP(scif4_ctrl_b), 4359 SH_PFC_PIN_GROUP(scif4_data_c), 4360 SH_PFC_PIN_GROUP(scif4_clk_c), 4361 SH_PFC_PIN_GROUP(scif4_ctrl_c), 4362 SH_PFC_PIN_GROUP(scif5_data_a), 4363 SH_PFC_PIN_GROUP(scif5_clk_a), 4364 SH_PFC_PIN_GROUP(scif5_data_b), 4365 SH_PFC_PIN_GROUP(scif5_clk_b), 4366 SH_PFC_PIN_GROUP(scif_clk_a), 4367 SH_PFC_PIN_GROUP(scif_clk_b), 4368 SH_PFC_PIN_GROUP(sdhi0_data1), 4369 SH_PFC_PIN_GROUP(sdhi0_data4), 4370 SH_PFC_PIN_GROUP(sdhi0_ctrl), 4371 SH_PFC_PIN_GROUP(sdhi0_cd), 4372 SH_PFC_PIN_GROUP(sdhi0_wp), 4373 SH_PFC_PIN_GROUP(sdhi1_data1), 4374 SH_PFC_PIN_GROUP(sdhi1_data4), 4375 SH_PFC_PIN_GROUP(sdhi1_ctrl), 4376 SH_PFC_PIN_GROUP(sdhi1_cd), 4377 SH_PFC_PIN_GROUP(sdhi1_wp), 4378 SH_PFC_PIN_GROUP(sdhi2_data1), 4379 SH_PFC_PIN_GROUP(sdhi2_data4), 4380 SH_PFC_PIN_GROUP(sdhi2_data8), 4381 SH_PFC_PIN_GROUP(sdhi2_ctrl), 4382 SH_PFC_PIN_GROUP(sdhi2_cd_a), 4383 SH_PFC_PIN_GROUP(sdhi2_wp_a), 4384 SH_PFC_PIN_GROUP(sdhi2_cd_b), 4385 SH_PFC_PIN_GROUP(sdhi2_wp_b), 4386 SH_PFC_PIN_GROUP(sdhi2_ds), 4387 SH_PFC_PIN_GROUP(sdhi3_data1), 4388 SH_PFC_PIN_GROUP(sdhi3_data4), 4389 SH_PFC_PIN_GROUP(sdhi3_data8), 4390 SH_PFC_PIN_GROUP(sdhi3_ctrl), 4391 SH_PFC_PIN_GROUP(sdhi3_cd), 4392 SH_PFC_PIN_GROUP(sdhi3_wp), 4393 SH_PFC_PIN_GROUP(sdhi3_ds), 4394 SH_PFC_PIN_GROUP(ssi0_data), 4395 SH_PFC_PIN_GROUP(ssi01239_ctrl), 4396 SH_PFC_PIN_GROUP(ssi1_data_a), 4397 SH_PFC_PIN_GROUP(ssi1_data_b), 4398 SH_PFC_PIN_GROUP(ssi1_ctrl_a), 4399 SH_PFC_PIN_GROUP(ssi1_ctrl_b), 4400 SH_PFC_PIN_GROUP(ssi2_data_a), 4401 SH_PFC_PIN_GROUP(ssi2_data_b), 4402 SH_PFC_PIN_GROUP(ssi2_ctrl_a), 4403 SH_PFC_PIN_GROUP(ssi2_ctrl_b), 4404 SH_PFC_PIN_GROUP(ssi3_data), 4405 SH_PFC_PIN_GROUP(ssi349_ctrl), 4406 SH_PFC_PIN_GROUP(ssi4_data), 4407 SH_PFC_PIN_GROUP(ssi4_ctrl), 4408 SH_PFC_PIN_GROUP(ssi5_data), 4409 SH_PFC_PIN_GROUP(ssi5_ctrl), 4410 SH_PFC_PIN_GROUP(ssi6_data), 4411 SH_PFC_PIN_GROUP(ssi6_ctrl), 4412 SH_PFC_PIN_GROUP(ssi7_data), 4413 SH_PFC_PIN_GROUP(ssi78_ctrl), 4414 SH_PFC_PIN_GROUP(ssi8_data), 4415 SH_PFC_PIN_GROUP(ssi9_data_a), 4416 SH_PFC_PIN_GROUP(ssi9_data_b), 4417 SH_PFC_PIN_GROUP(ssi9_ctrl_a), 4418 SH_PFC_PIN_GROUP(ssi9_ctrl_b), 4419 SH_PFC_PIN_GROUP(tmu_tclk1_a), 4420 SH_PFC_PIN_GROUP(tmu_tclk1_b), 4421 SH_PFC_PIN_GROUP(tmu_tclk2_a), 4422 SH_PFC_PIN_GROUP(tmu_tclk2_b), 4423 SH_PFC_PIN_GROUP(tpu_to0), 4424 SH_PFC_PIN_GROUP(tpu_to1), 4425 SH_PFC_PIN_GROUP(tpu_to2), 4426 SH_PFC_PIN_GROUP(tpu_to3), 4427 SH_PFC_PIN_GROUP(usb0), 4428 SH_PFC_PIN_GROUP(usb1), 4429 SH_PFC_PIN_GROUP(usb30), 4430 VIN_DATA_PIN_GROUP(vin4_data, 8, _a), 4431 VIN_DATA_PIN_GROUP(vin4_data, 10, _a), 4432 VIN_DATA_PIN_GROUP(vin4_data, 12, _a), 4433 VIN_DATA_PIN_GROUP(vin4_data, 16, _a), 4434 SH_PFC_PIN_GROUP(vin4_data18_a), 4435 VIN_DATA_PIN_GROUP(vin4_data, 20, _a), 4436 VIN_DATA_PIN_GROUP(vin4_data, 24, _a), 4437 VIN_DATA_PIN_GROUP(vin4_data, 8, _b), 4438 VIN_DATA_PIN_GROUP(vin4_data, 10, _b), 4439 VIN_DATA_PIN_GROUP(vin4_data, 12, _b), 4440 VIN_DATA_PIN_GROUP(vin4_data, 16, _b), 4441 SH_PFC_PIN_GROUP(vin4_data18_b), 4442 VIN_DATA_PIN_GROUP(vin4_data, 20, _b), 4443 VIN_DATA_PIN_GROUP(vin4_data, 24, _b), 4444 SH_PFC_PIN_GROUP(vin4_sync), 4445 SH_PFC_PIN_GROUP(vin4_field), 4446 SH_PFC_PIN_GROUP(vin4_clkenb), 4447 SH_PFC_PIN_GROUP(vin4_clk), 4448 VIN_DATA_PIN_GROUP(vin5_data, 8), 4449 VIN_DATA_PIN_GROUP(vin5_data, 10), 4450 VIN_DATA_PIN_GROUP(vin5_data, 12), 4451 VIN_DATA_PIN_GROUP(vin5_data, 16), 4452 SH_PFC_PIN_GROUP(vin5_sync), 4453 SH_PFC_PIN_GROUP(vin5_field), 4454 SH_PFC_PIN_GROUP(vin5_clkenb), 4455 SH_PFC_PIN_GROUP(vin5_clk), 4456 }, 4457 .automotive = { 4458 SH_PFC_PIN_GROUP(drif0_ctrl_a), 4459 SH_PFC_PIN_GROUP(drif0_data0_a), 4460 SH_PFC_PIN_GROUP(drif0_data1_a), 4461 SH_PFC_PIN_GROUP(drif0_ctrl_b), 4462 SH_PFC_PIN_GROUP(drif0_data0_b), 4463 SH_PFC_PIN_GROUP(drif0_data1_b), 4464 SH_PFC_PIN_GROUP(drif0_ctrl_c), 4465 SH_PFC_PIN_GROUP(drif0_data0_c), 4466 SH_PFC_PIN_GROUP(drif0_data1_c), 4467 SH_PFC_PIN_GROUP(drif1_ctrl_a), 4468 SH_PFC_PIN_GROUP(drif1_data0_a), 4469 SH_PFC_PIN_GROUP(drif1_data1_a), 4470 SH_PFC_PIN_GROUP(drif1_ctrl_b), 4471 SH_PFC_PIN_GROUP(drif1_data0_b), 4472 SH_PFC_PIN_GROUP(drif1_data1_b), 4473 SH_PFC_PIN_GROUP(drif1_ctrl_c), 4474 SH_PFC_PIN_GROUP(drif1_data0_c), 4475 SH_PFC_PIN_GROUP(drif1_data1_c), 4476 SH_PFC_PIN_GROUP(drif2_ctrl_a), 4477 SH_PFC_PIN_GROUP(drif2_data0_a), 4478 SH_PFC_PIN_GROUP(drif2_data1_a), 4479 SH_PFC_PIN_GROUP(drif2_ctrl_b), 4480 SH_PFC_PIN_GROUP(drif2_data0_b), 4481 SH_PFC_PIN_GROUP(drif2_data1_b), 4482 SH_PFC_PIN_GROUP(drif3_ctrl_a), 4483 SH_PFC_PIN_GROUP(drif3_data0_a), 4484 SH_PFC_PIN_GROUP(drif3_data1_a), 4485 SH_PFC_PIN_GROUP(drif3_ctrl_b), 4486 SH_PFC_PIN_GROUP(drif3_data0_b), 4487 SH_PFC_PIN_GROUP(drif3_data1_b), 4488 } 4489 }; 4490 4491 static const char * const audio_clk_groups[] = { 4492 "audio_clk_a_a", 4493 "audio_clk_a_b", 4494 "audio_clk_a_c", 4495 "audio_clk_b_a", 4496 "audio_clk_b_b", 4497 "audio_clk_c_a", 4498 "audio_clk_c_b", 4499 "audio_clkout_a", 4500 "audio_clkout_b", 4501 "audio_clkout_c", 4502 "audio_clkout_d", 4503 "audio_clkout1_a", 4504 "audio_clkout1_b", 4505 "audio_clkout2_a", 4506 "audio_clkout2_b", 4507 "audio_clkout3_a", 4508 "audio_clkout3_b", 4509 }; 4510 4511 static const char * const avb_groups[] = { 4512 "avb_link", 4513 "avb_magic", 4514 "avb_phy_int", 4515 "avb_mdc", /* Deprecated, please use "avb_mdio" instead */ 4516 "avb_mdio", 4517 "avb_mii", 4518 "avb_avtp_pps", 4519 "avb_avtp_match_a", 4520 "avb_avtp_capture_a", 4521 "avb_avtp_match_b", 4522 "avb_avtp_capture_b", 4523 }; 4524 4525 static const char * const can0_groups[] = { 4526 "can0_data_a", 4527 "can0_data_b", 4528 }; 4529 4530 static const char * const can1_groups[] = { 4531 "can1_data", 4532 }; 4533 4534 static const char * const can_clk_groups[] = { 4535 "can_clk", 4536 }; 4537 4538 static const char * const canfd0_groups[] = { 4539 "canfd0_data_a", 4540 "canfd0_data_b", 4541 }; 4542 4543 static const char * const canfd1_groups[] = { 4544 "canfd1_data", 4545 }; 4546 4547 static const char * const drif0_groups[] = { 4548 "drif0_ctrl_a", 4549 "drif0_data0_a", 4550 "drif0_data1_a", 4551 "drif0_ctrl_b", 4552 "drif0_data0_b", 4553 "drif0_data1_b", 4554 "drif0_ctrl_c", 4555 "drif0_data0_c", 4556 "drif0_data1_c", 4557 }; 4558 4559 static const char * const drif1_groups[] = { 4560 "drif1_ctrl_a", 4561 "drif1_data0_a", 4562 "drif1_data1_a", 4563 "drif1_ctrl_b", 4564 "drif1_data0_b", 4565 "drif1_data1_b", 4566 "drif1_ctrl_c", 4567 "drif1_data0_c", 4568 "drif1_data1_c", 4569 }; 4570 4571 static const char * const drif2_groups[] = { 4572 "drif2_ctrl_a", 4573 "drif2_data0_a", 4574 "drif2_data1_a", 4575 "drif2_ctrl_b", 4576 "drif2_data0_b", 4577 "drif2_data1_b", 4578 }; 4579 4580 static const char * const drif3_groups[] = { 4581 "drif3_ctrl_a", 4582 "drif3_data0_a", 4583 "drif3_data1_a", 4584 "drif3_ctrl_b", 4585 "drif3_data0_b", 4586 "drif3_data1_b", 4587 }; 4588 4589 static const char * const du_groups[] = { 4590 "du_rgb666", 4591 "du_rgb888", 4592 "du_clk_out_0", 4593 "du_clk_out_1", 4594 "du_sync", 4595 "du_oddf", 4596 "du_cde", 4597 "du_disp", 4598 }; 4599 4600 static const char * const hscif0_groups[] = { 4601 "hscif0_data", 4602 "hscif0_clk", 4603 "hscif0_ctrl", 4604 }; 4605 4606 static const char * const hscif1_groups[] = { 4607 "hscif1_data_a", 4608 "hscif1_clk_a", 4609 "hscif1_ctrl_a", 4610 "hscif1_data_b", 4611 "hscif1_clk_b", 4612 "hscif1_ctrl_b", 4613 }; 4614 4615 static const char * const hscif2_groups[] = { 4616 "hscif2_data_a", 4617 "hscif2_clk_a", 4618 "hscif2_ctrl_a", 4619 "hscif2_data_b", 4620 "hscif2_clk_b", 4621 "hscif2_ctrl_b", 4622 "hscif2_data_c", 4623 "hscif2_clk_c", 4624 "hscif2_ctrl_c", 4625 }; 4626 4627 static const char * const hscif3_groups[] = { 4628 "hscif3_data_a", 4629 "hscif3_clk", 4630 "hscif3_ctrl", 4631 "hscif3_data_b", 4632 "hscif3_data_c", 4633 "hscif3_data_d", 4634 }; 4635 4636 static const char * const hscif4_groups[] = { 4637 "hscif4_data_a", 4638 "hscif4_clk", 4639 "hscif4_ctrl", 4640 "hscif4_data_b", 4641 }; 4642 4643 static const char * const i2c0_groups[] = { 4644 "i2c0", 4645 }; 4646 4647 static const char * const i2c1_groups[] = { 4648 "i2c1_a", 4649 "i2c1_b", 4650 }; 4651 4652 static const char * const i2c2_groups[] = { 4653 "i2c2_a", 4654 "i2c2_b", 4655 }; 4656 4657 static const char * const i2c3_groups[] = { 4658 "i2c3", 4659 }; 4660 4661 static const char * const i2c5_groups[] = { 4662 "i2c5", 4663 }; 4664 4665 static const char * const i2c6_groups[] = { 4666 "i2c6_a", 4667 "i2c6_b", 4668 "i2c6_c", 4669 }; 4670 4671 static const char * const intc_ex_groups[] = { 4672 "intc_ex_irq0", 4673 "intc_ex_irq1", 4674 "intc_ex_irq2", 4675 "intc_ex_irq3", 4676 "intc_ex_irq4", 4677 "intc_ex_irq5", 4678 }; 4679 4680 static const char * const msiof0_groups[] = { 4681 "msiof0_clk", 4682 "msiof0_sync", 4683 "msiof0_ss1", 4684 "msiof0_ss2", 4685 "msiof0_txd", 4686 "msiof0_rxd", 4687 }; 4688 4689 static const char * const msiof1_groups[] = { 4690 "msiof1_clk_a", 4691 "msiof1_sync_a", 4692 "msiof1_ss1_a", 4693 "msiof1_ss2_a", 4694 "msiof1_txd_a", 4695 "msiof1_rxd_a", 4696 "msiof1_clk_b", 4697 "msiof1_sync_b", 4698 "msiof1_ss1_b", 4699 "msiof1_ss2_b", 4700 "msiof1_txd_b", 4701 "msiof1_rxd_b", 4702 "msiof1_clk_c", 4703 "msiof1_sync_c", 4704 "msiof1_ss1_c", 4705 "msiof1_ss2_c", 4706 "msiof1_txd_c", 4707 "msiof1_rxd_c", 4708 "msiof1_clk_d", 4709 "msiof1_sync_d", 4710 "msiof1_ss1_d", 4711 "msiof1_ss2_d", 4712 "msiof1_txd_d", 4713 "msiof1_rxd_d", 4714 "msiof1_clk_e", 4715 "msiof1_sync_e", 4716 "msiof1_ss1_e", 4717 "msiof1_ss2_e", 4718 "msiof1_txd_e", 4719 "msiof1_rxd_e", 4720 "msiof1_clk_f", 4721 "msiof1_sync_f", 4722 "msiof1_ss1_f", 4723 "msiof1_ss2_f", 4724 "msiof1_txd_f", 4725 "msiof1_rxd_f", 4726 "msiof1_clk_g", 4727 "msiof1_sync_g", 4728 "msiof1_ss1_g", 4729 "msiof1_ss2_g", 4730 "msiof1_txd_g", 4731 "msiof1_rxd_g", 4732 }; 4733 4734 static const char * const msiof2_groups[] = { 4735 "msiof2_clk_a", 4736 "msiof2_sync_a", 4737 "msiof2_ss1_a", 4738 "msiof2_ss2_a", 4739 "msiof2_txd_a", 4740 "msiof2_rxd_a", 4741 "msiof2_clk_b", 4742 "msiof2_sync_b", 4743 "msiof2_ss1_b", 4744 "msiof2_ss2_b", 4745 "msiof2_txd_b", 4746 "msiof2_rxd_b", 4747 "msiof2_clk_c", 4748 "msiof2_sync_c", 4749 "msiof2_ss1_c", 4750 "msiof2_ss2_c", 4751 "msiof2_txd_c", 4752 "msiof2_rxd_c", 4753 "msiof2_clk_d", 4754 "msiof2_sync_d", 4755 "msiof2_ss1_d", 4756 "msiof2_ss2_d", 4757 "msiof2_txd_d", 4758 "msiof2_rxd_d", 4759 }; 4760 4761 static const char * const msiof3_groups[] = { 4762 "msiof3_clk_a", 4763 "msiof3_sync_a", 4764 "msiof3_ss1_a", 4765 "msiof3_ss2_a", 4766 "msiof3_txd_a", 4767 "msiof3_rxd_a", 4768 "msiof3_clk_b", 4769 "msiof3_sync_b", 4770 "msiof3_ss1_b", 4771 "msiof3_ss2_b", 4772 "msiof3_txd_b", 4773 "msiof3_rxd_b", 4774 "msiof3_clk_c", 4775 "msiof3_sync_c", 4776 "msiof3_txd_c", 4777 "msiof3_rxd_c", 4778 "msiof3_clk_d", 4779 "msiof3_sync_d", 4780 "msiof3_ss1_d", 4781 "msiof3_txd_d", 4782 "msiof3_rxd_d", 4783 "msiof3_clk_e", 4784 "msiof3_sync_e", 4785 "msiof3_ss1_e", 4786 "msiof3_ss2_e", 4787 "msiof3_txd_e", 4788 "msiof3_rxd_e", 4789 }; 4790 4791 static const char * const pwm0_groups[] = { 4792 "pwm0", 4793 }; 4794 4795 static const char * const pwm1_groups[] = { 4796 "pwm1_a", 4797 "pwm1_b", 4798 }; 4799 4800 static const char * const pwm2_groups[] = { 4801 "pwm2_a", 4802 "pwm2_b", 4803 }; 4804 4805 static const char * const pwm3_groups[] = { 4806 "pwm3_a", 4807 "pwm3_b", 4808 }; 4809 4810 static const char * const pwm4_groups[] = { 4811 "pwm4_a", 4812 "pwm4_b", 4813 }; 4814 4815 static const char * const pwm5_groups[] = { 4816 "pwm5_a", 4817 "pwm5_b", 4818 }; 4819 4820 static const char * const pwm6_groups[] = { 4821 "pwm6_a", 4822 "pwm6_b", 4823 }; 4824 4825 static const char * const scif0_groups[] = { 4826 "scif0_data", 4827 "scif0_clk", 4828 "scif0_ctrl", 4829 }; 4830 4831 static const char * const scif1_groups[] = { 4832 "scif1_data_a", 4833 "scif1_clk", 4834 "scif1_ctrl", 4835 "scif1_data_b", 4836 }; 4837 4838 static const char * const scif2_groups[] = { 4839 "scif2_data_a", 4840 "scif2_clk", 4841 "scif2_data_b", 4842 }; 4843 4844 static const char * const scif3_groups[] = { 4845 "scif3_data_a", 4846 "scif3_clk", 4847 "scif3_ctrl", 4848 "scif3_data_b", 4849 }; 4850 4851 static const char * const scif4_groups[] = { 4852 "scif4_data_a", 4853 "scif4_clk_a", 4854 "scif4_ctrl_a", 4855 "scif4_data_b", 4856 "scif4_clk_b", 4857 "scif4_ctrl_b", 4858 "scif4_data_c", 4859 "scif4_clk_c", 4860 "scif4_ctrl_c", 4861 }; 4862 4863 static const char * const scif5_groups[] = { 4864 "scif5_data_a", 4865 "scif5_clk_a", 4866 "scif5_data_b", 4867 "scif5_clk_b", 4868 }; 4869 4870 static const char * const scif_clk_groups[] = { 4871 "scif_clk_a", 4872 "scif_clk_b", 4873 }; 4874 4875 static const char * const sdhi0_groups[] = { 4876 "sdhi0_data1", 4877 "sdhi0_data4", 4878 "sdhi0_ctrl", 4879 "sdhi0_cd", 4880 "sdhi0_wp", 4881 }; 4882 4883 static const char * const sdhi1_groups[] = { 4884 "sdhi1_data1", 4885 "sdhi1_data4", 4886 "sdhi1_ctrl", 4887 "sdhi1_cd", 4888 "sdhi1_wp", 4889 }; 4890 4891 static const char * const sdhi2_groups[] = { 4892 "sdhi2_data1", 4893 "sdhi2_data4", 4894 "sdhi2_data8", 4895 "sdhi2_ctrl", 4896 "sdhi2_cd_a", 4897 "sdhi2_wp_a", 4898 "sdhi2_cd_b", 4899 "sdhi2_wp_b", 4900 "sdhi2_ds", 4901 }; 4902 4903 static const char * const sdhi3_groups[] = { 4904 "sdhi3_data1", 4905 "sdhi3_data4", 4906 "sdhi3_data8", 4907 "sdhi3_ctrl", 4908 "sdhi3_cd", 4909 "sdhi3_wp", 4910 "sdhi3_ds", 4911 }; 4912 4913 static const char * const ssi_groups[] = { 4914 "ssi0_data", 4915 "ssi01239_ctrl", 4916 "ssi1_data_a", 4917 "ssi1_data_b", 4918 "ssi1_ctrl_a", 4919 "ssi1_ctrl_b", 4920 "ssi2_data_a", 4921 "ssi2_data_b", 4922 "ssi2_ctrl_a", 4923 "ssi2_ctrl_b", 4924 "ssi3_data", 4925 "ssi349_ctrl", 4926 "ssi4_data", 4927 "ssi4_ctrl", 4928 "ssi5_data", 4929 "ssi5_ctrl", 4930 "ssi6_data", 4931 "ssi6_ctrl", 4932 "ssi7_data", 4933 "ssi78_ctrl", 4934 "ssi8_data", 4935 "ssi9_data_a", 4936 "ssi9_data_b", 4937 "ssi9_ctrl_a", 4938 "ssi9_ctrl_b", 4939 }; 4940 4941 static const char * const tmu_groups[] = { 4942 "tmu_tclk1_a", 4943 "tmu_tclk1_b", 4944 "tmu_tclk2_a", 4945 "tmu_tclk2_b", 4946 }; 4947 4948 static const char * const tpu_groups[] = { 4949 "tpu_to0", 4950 "tpu_to1", 4951 "tpu_to2", 4952 "tpu_to3", 4953 }; 4954 4955 static const char * const usb0_groups[] = { 4956 "usb0", 4957 }; 4958 4959 static const char * const usb1_groups[] = { 4960 "usb1", 4961 }; 4962 4963 static const char * const usb30_groups[] = { 4964 "usb30", 4965 }; 4966 4967 static const char * const vin4_groups[] = { 4968 "vin4_data8_a", 4969 "vin4_data10_a", 4970 "vin4_data12_a", 4971 "vin4_data16_a", 4972 "vin4_data18_a", 4973 "vin4_data20_a", 4974 "vin4_data24_a", 4975 "vin4_data8_b", 4976 "vin4_data10_b", 4977 "vin4_data12_b", 4978 "vin4_data16_b", 4979 "vin4_data18_b", 4980 "vin4_data20_b", 4981 "vin4_data24_b", 4982 "vin4_sync", 4983 "vin4_field", 4984 "vin4_clkenb", 4985 "vin4_clk", 4986 }; 4987 4988 static const char * const vin5_groups[] = { 4989 "vin5_data8", 4990 "vin5_data10", 4991 "vin5_data12", 4992 "vin5_data16", 4993 "vin5_sync", 4994 "vin5_field", 4995 "vin5_clkenb", 4996 "vin5_clk", 4997 }; 4998 4999 static const struct { 5000 struct sh_pfc_function common[50]; 5001 struct sh_pfc_function automotive[4]; 5002 } pinmux_functions = { 5003 .common = { 5004 SH_PFC_FUNCTION(audio_clk), 5005 SH_PFC_FUNCTION(avb), 5006 SH_PFC_FUNCTION(can0), 5007 SH_PFC_FUNCTION(can1), 5008 SH_PFC_FUNCTION(can_clk), 5009 SH_PFC_FUNCTION(canfd0), 5010 SH_PFC_FUNCTION(canfd1), 5011 SH_PFC_FUNCTION(du), 5012 SH_PFC_FUNCTION(hscif0), 5013 SH_PFC_FUNCTION(hscif1), 5014 SH_PFC_FUNCTION(hscif2), 5015 SH_PFC_FUNCTION(hscif3), 5016 SH_PFC_FUNCTION(hscif4), 5017 SH_PFC_FUNCTION(i2c0), 5018 SH_PFC_FUNCTION(i2c1), 5019 SH_PFC_FUNCTION(i2c2), 5020 SH_PFC_FUNCTION(i2c3), 5021 SH_PFC_FUNCTION(i2c5), 5022 SH_PFC_FUNCTION(i2c6), 5023 SH_PFC_FUNCTION(intc_ex), 5024 SH_PFC_FUNCTION(msiof0), 5025 SH_PFC_FUNCTION(msiof1), 5026 SH_PFC_FUNCTION(msiof2), 5027 SH_PFC_FUNCTION(msiof3), 5028 SH_PFC_FUNCTION(pwm0), 5029 SH_PFC_FUNCTION(pwm1), 5030 SH_PFC_FUNCTION(pwm2), 5031 SH_PFC_FUNCTION(pwm3), 5032 SH_PFC_FUNCTION(pwm4), 5033 SH_PFC_FUNCTION(pwm5), 5034 SH_PFC_FUNCTION(pwm6), 5035 SH_PFC_FUNCTION(scif0), 5036 SH_PFC_FUNCTION(scif1), 5037 SH_PFC_FUNCTION(scif2), 5038 SH_PFC_FUNCTION(scif3), 5039 SH_PFC_FUNCTION(scif4), 5040 SH_PFC_FUNCTION(scif5), 5041 SH_PFC_FUNCTION(scif_clk), 5042 SH_PFC_FUNCTION(sdhi0), 5043 SH_PFC_FUNCTION(sdhi1), 5044 SH_PFC_FUNCTION(sdhi2), 5045 SH_PFC_FUNCTION(sdhi3), 5046 SH_PFC_FUNCTION(ssi), 5047 SH_PFC_FUNCTION(tmu), 5048 SH_PFC_FUNCTION(tpu), 5049 SH_PFC_FUNCTION(usb0), 5050 SH_PFC_FUNCTION(usb1), 5051 SH_PFC_FUNCTION(usb30), 5052 SH_PFC_FUNCTION(vin4), 5053 SH_PFC_FUNCTION(vin5), 5054 }, 5055 .automotive = { 5056 SH_PFC_FUNCTION(drif0), 5057 SH_PFC_FUNCTION(drif1), 5058 SH_PFC_FUNCTION(drif2), 5059 SH_PFC_FUNCTION(drif3), 5060 } 5061 }; 5062 5063 static const struct pinmux_cfg_reg pinmux_config_regs[] = { 5064 #define F_(x, y) FN_##y 5065 #define FM(x) FN_##x 5066 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP( 5067 0, 0, 5068 0, 0, 5069 0, 0, 5070 0, 0, 5071 0, 0, 5072 0, 0, 5073 0, 0, 5074 0, 0, 5075 0, 0, 5076 0, 0, 5077 0, 0, 5078 0, 0, 5079 0, 0, 5080 0, 0, 5081 0, 0, 5082 0, 0, 5083 GP_0_15_FN, GPSR0_15, 5084 GP_0_14_FN, GPSR0_14, 5085 GP_0_13_FN, GPSR0_13, 5086 GP_0_12_FN, GPSR0_12, 5087 GP_0_11_FN, GPSR0_11, 5088 GP_0_10_FN, GPSR0_10, 5089 GP_0_9_FN, GPSR0_9, 5090 GP_0_8_FN, GPSR0_8, 5091 GP_0_7_FN, GPSR0_7, 5092 GP_0_6_FN, GPSR0_6, 5093 GP_0_5_FN, GPSR0_5, 5094 GP_0_4_FN, GPSR0_4, 5095 GP_0_3_FN, GPSR0_3, 5096 GP_0_2_FN, GPSR0_2, 5097 GP_0_1_FN, GPSR0_1, 5098 GP_0_0_FN, GPSR0_0, )) 5099 }, 5100 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP( 5101 0, 0, 5102 0, 0, 5103 0, 0, 5104 GP_1_28_FN, GPSR1_28, 5105 GP_1_27_FN, GPSR1_27, 5106 GP_1_26_FN, GPSR1_26, 5107 GP_1_25_FN, GPSR1_25, 5108 GP_1_24_FN, GPSR1_24, 5109 GP_1_23_FN, GPSR1_23, 5110 GP_1_22_FN, GPSR1_22, 5111 GP_1_21_FN, GPSR1_21, 5112 GP_1_20_FN, GPSR1_20, 5113 GP_1_19_FN, GPSR1_19, 5114 GP_1_18_FN, GPSR1_18, 5115 GP_1_17_FN, GPSR1_17, 5116 GP_1_16_FN, GPSR1_16, 5117 GP_1_15_FN, GPSR1_15, 5118 GP_1_14_FN, GPSR1_14, 5119 GP_1_13_FN, GPSR1_13, 5120 GP_1_12_FN, GPSR1_12, 5121 GP_1_11_FN, GPSR1_11, 5122 GP_1_10_FN, GPSR1_10, 5123 GP_1_9_FN, GPSR1_9, 5124 GP_1_8_FN, GPSR1_8, 5125 GP_1_7_FN, GPSR1_7, 5126 GP_1_6_FN, GPSR1_6, 5127 GP_1_5_FN, GPSR1_5, 5128 GP_1_4_FN, GPSR1_4, 5129 GP_1_3_FN, GPSR1_3, 5130 GP_1_2_FN, GPSR1_2, 5131 GP_1_1_FN, GPSR1_1, 5132 GP_1_0_FN, GPSR1_0, )) 5133 }, 5134 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP( 5135 0, 0, 5136 0, 0, 5137 0, 0, 5138 0, 0, 5139 0, 0, 5140 0, 0, 5141 0, 0, 5142 0, 0, 5143 0, 0, 5144 0, 0, 5145 0, 0, 5146 0, 0, 5147 0, 0, 5148 0, 0, 5149 0, 0, 5150 0, 0, 5151 0, 0, 5152 GP_2_14_FN, GPSR2_14, 5153 GP_2_13_FN, GPSR2_13, 5154 GP_2_12_FN, GPSR2_12, 5155 GP_2_11_FN, GPSR2_11, 5156 GP_2_10_FN, GPSR2_10, 5157 GP_2_9_FN, GPSR2_9, 5158 GP_2_8_FN, GPSR2_8, 5159 GP_2_7_FN, GPSR2_7, 5160 GP_2_6_FN, GPSR2_6, 5161 GP_2_5_FN, GPSR2_5, 5162 GP_2_4_FN, GPSR2_4, 5163 GP_2_3_FN, GPSR2_3, 5164 GP_2_2_FN, GPSR2_2, 5165 GP_2_1_FN, GPSR2_1, 5166 GP_2_0_FN, GPSR2_0, )) 5167 }, 5168 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP( 5169 0, 0, 5170 0, 0, 5171 0, 0, 5172 0, 0, 5173 0, 0, 5174 0, 0, 5175 0, 0, 5176 0, 0, 5177 0, 0, 5178 0, 0, 5179 0, 0, 5180 0, 0, 5181 0, 0, 5182 0, 0, 5183 0, 0, 5184 0, 0, 5185 GP_3_15_FN, GPSR3_15, 5186 GP_3_14_FN, GPSR3_14, 5187 GP_3_13_FN, GPSR3_13, 5188 GP_3_12_FN, GPSR3_12, 5189 GP_3_11_FN, GPSR3_11, 5190 GP_3_10_FN, GPSR3_10, 5191 GP_3_9_FN, GPSR3_9, 5192 GP_3_8_FN, GPSR3_8, 5193 GP_3_7_FN, GPSR3_7, 5194 GP_3_6_FN, GPSR3_6, 5195 GP_3_5_FN, GPSR3_5, 5196 GP_3_4_FN, GPSR3_4, 5197 GP_3_3_FN, GPSR3_3, 5198 GP_3_2_FN, GPSR3_2, 5199 GP_3_1_FN, GPSR3_1, 5200 GP_3_0_FN, GPSR3_0, )) 5201 }, 5202 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP( 5203 0, 0, 5204 0, 0, 5205 0, 0, 5206 0, 0, 5207 0, 0, 5208 0, 0, 5209 0, 0, 5210 0, 0, 5211 0, 0, 5212 0, 0, 5213 0, 0, 5214 0, 0, 5215 0, 0, 5216 0, 0, 5217 GP_4_17_FN, GPSR4_17, 5218 GP_4_16_FN, GPSR4_16, 5219 GP_4_15_FN, GPSR4_15, 5220 GP_4_14_FN, GPSR4_14, 5221 GP_4_13_FN, GPSR4_13, 5222 GP_4_12_FN, GPSR4_12, 5223 GP_4_11_FN, GPSR4_11, 5224 GP_4_10_FN, GPSR4_10, 5225 GP_4_9_FN, GPSR4_9, 5226 GP_4_8_FN, GPSR4_8, 5227 GP_4_7_FN, GPSR4_7, 5228 GP_4_6_FN, GPSR4_6, 5229 GP_4_5_FN, GPSR4_5, 5230 GP_4_4_FN, GPSR4_4, 5231 GP_4_3_FN, GPSR4_3, 5232 GP_4_2_FN, GPSR4_2, 5233 GP_4_1_FN, GPSR4_1, 5234 GP_4_0_FN, GPSR4_0, )) 5235 }, 5236 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP( 5237 0, 0, 5238 0, 0, 5239 0, 0, 5240 0, 0, 5241 0, 0, 5242 0, 0, 5243 GP_5_25_FN, GPSR5_25, 5244 GP_5_24_FN, GPSR5_24, 5245 GP_5_23_FN, GPSR5_23, 5246 GP_5_22_FN, GPSR5_22, 5247 GP_5_21_FN, GPSR5_21, 5248 GP_5_20_FN, GPSR5_20, 5249 GP_5_19_FN, GPSR5_19, 5250 GP_5_18_FN, GPSR5_18, 5251 GP_5_17_FN, GPSR5_17, 5252 GP_5_16_FN, GPSR5_16, 5253 GP_5_15_FN, GPSR5_15, 5254 GP_5_14_FN, GPSR5_14, 5255 GP_5_13_FN, GPSR5_13, 5256 GP_5_12_FN, GPSR5_12, 5257 GP_5_11_FN, GPSR5_11, 5258 GP_5_10_FN, GPSR5_10, 5259 GP_5_9_FN, GPSR5_9, 5260 GP_5_8_FN, GPSR5_8, 5261 GP_5_7_FN, GPSR5_7, 5262 GP_5_6_FN, GPSR5_6, 5263 GP_5_5_FN, GPSR5_5, 5264 GP_5_4_FN, GPSR5_4, 5265 GP_5_3_FN, GPSR5_3, 5266 GP_5_2_FN, GPSR5_2, 5267 GP_5_1_FN, GPSR5_1, 5268 GP_5_0_FN, GPSR5_0, )) 5269 }, 5270 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP( 5271 GP_6_31_FN, GPSR6_31, 5272 GP_6_30_FN, GPSR6_30, 5273 GP_6_29_FN, GPSR6_29, 5274 GP_6_28_FN, GPSR6_28, 5275 GP_6_27_FN, GPSR6_27, 5276 GP_6_26_FN, GPSR6_26, 5277 GP_6_25_FN, GPSR6_25, 5278 GP_6_24_FN, GPSR6_24, 5279 GP_6_23_FN, GPSR6_23, 5280 GP_6_22_FN, GPSR6_22, 5281 GP_6_21_FN, GPSR6_21, 5282 GP_6_20_FN, GPSR6_20, 5283 GP_6_19_FN, GPSR6_19, 5284 GP_6_18_FN, GPSR6_18, 5285 GP_6_17_FN, GPSR6_17, 5286 GP_6_16_FN, GPSR6_16, 5287 GP_6_15_FN, GPSR6_15, 5288 GP_6_14_FN, GPSR6_14, 5289 GP_6_13_FN, GPSR6_13, 5290 GP_6_12_FN, GPSR6_12, 5291 GP_6_11_FN, GPSR6_11, 5292 GP_6_10_FN, GPSR6_10, 5293 GP_6_9_FN, GPSR6_9, 5294 GP_6_8_FN, GPSR6_8, 5295 GP_6_7_FN, GPSR6_7, 5296 GP_6_6_FN, GPSR6_6, 5297 GP_6_5_FN, GPSR6_5, 5298 GP_6_4_FN, GPSR6_4, 5299 GP_6_3_FN, GPSR6_3, 5300 GP_6_2_FN, GPSR6_2, 5301 GP_6_1_FN, GPSR6_1, 5302 GP_6_0_FN, GPSR6_0, )) 5303 }, 5304 { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1, GROUP( 5305 0, 0, 5306 0, 0, 5307 0, 0, 5308 0, 0, 5309 0, 0, 5310 0, 0, 5311 0, 0, 5312 0, 0, 5313 0, 0, 5314 0, 0, 5315 0, 0, 5316 0, 0, 5317 0, 0, 5318 0, 0, 5319 0, 0, 5320 0, 0, 5321 0, 0, 5322 0, 0, 5323 0, 0, 5324 0, 0, 5325 0, 0, 5326 0, 0, 5327 0, 0, 5328 0, 0, 5329 0, 0, 5330 0, 0, 5331 0, 0, 5332 0, 0, 5333 GP_7_3_FN, GPSR7_3, 5334 GP_7_2_FN, GPSR7_2, 5335 GP_7_1_FN, GPSR7_1, 5336 GP_7_0_FN, GPSR7_0, )) 5337 }, 5338 #undef F_ 5339 #undef FM 5340 5341 #define F_(x, y) x, 5342 #define FM(x) FN_##x, 5343 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP( 5344 IP0_31_28 5345 IP0_27_24 5346 IP0_23_20 5347 IP0_19_16 5348 IP0_15_12 5349 IP0_11_8 5350 IP0_7_4 5351 IP0_3_0 )) 5352 }, 5353 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP( 5354 IP1_31_28 5355 IP1_27_24 5356 IP1_23_20 5357 IP1_19_16 5358 IP1_15_12 5359 IP1_11_8 5360 IP1_7_4 5361 IP1_3_0 )) 5362 }, 5363 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP( 5364 IP2_31_28 5365 IP2_27_24 5366 IP2_23_20 5367 IP2_19_16 5368 IP2_15_12 5369 IP2_11_8 5370 IP2_7_4 5371 IP2_3_0 )) 5372 }, 5373 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP( 5374 IP3_31_28 5375 IP3_27_24 5376 IP3_23_20 5377 IP3_19_16 5378 IP3_15_12 5379 IP3_11_8 5380 IP3_7_4 5381 IP3_3_0 )) 5382 }, 5383 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP( 5384 IP4_31_28 5385 IP4_27_24 5386 IP4_23_20 5387 IP4_19_16 5388 IP4_15_12 5389 IP4_11_8 5390 IP4_7_4 5391 IP4_3_0 )) 5392 }, 5393 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP( 5394 IP5_31_28 5395 IP5_27_24 5396 IP5_23_20 5397 IP5_19_16 5398 IP5_15_12 5399 IP5_11_8 5400 IP5_7_4 5401 IP5_3_0 )) 5402 }, 5403 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP( 5404 IP6_31_28 5405 IP6_27_24 5406 IP6_23_20 5407 IP6_19_16 5408 IP6_15_12 5409 IP6_11_8 5410 IP6_7_4 5411 IP6_3_0 )) 5412 }, 5413 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP( 5414 IP7_31_28 5415 IP7_27_24 5416 IP7_23_20 5417 IP7_19_16 5418 /* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5419 IP7_11_8 5420 IP7_7_4 5421 IP7_3_0 )) 5422 }, 5423 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP( 5424 IP8_31_28 5425 IP8_27_24 5426 IP8_23_20 5427 IP8_19_16 5428 IP8_15_12 5429 IP8_11_8 5430 IP8_7_4 5431 IP8_3_0 )) 5432 }, 5433 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP( 5434 IP9_31_28 5435 IP9_27_24 5436 IP9_23_20 5437 IP9_19_16 5438 IP9_15_12 5439 IP9_11_8 5440 IP9_7_4 5441 IP9_3_0 )) 5442 }, 5443 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP( 5444 IP10_31_28 5445 IP10_27_24 5446 IP10_23_20 5447 IP10_19_16 5448 IP10_15_12 5449 IP10_11_8 5450 IP10_7_4 5451 IP10_3_0 )) 5452 }, 5453 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP( 5454 IP11_31_28 5455 IP11_27_24 5456 IP11_23_20 5457 IP11_19_16 5458 IP11_15_12 5459 IP11_11_8 5460 IP11_7_4 5461 IP11_3_0 )) 5462 }, 5463 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP( 5464 IP12_31_28 5465 IP12_27_24 5466 IP12_23_20 5467 IP12_19_16 5468 IP12_15_12 5469 IP12_11_8 5470 IP12_7_4 5471 IP12_3_0 )) 5472 }, 5473 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP( 5474 IP13_31_28 5475 IP13_27_24 5476 IP13_23_20 5477 IP13_19_16 5478 IP13_15_12 5479 IP13_11_8 5480 IP13_7_4 5481 IP13_3_0 )) 5482 }, 5483 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP( 5484 IP14_31_28 5485 IP14_27_24 5486 IP14_23_20 5487 IP14_19_16 5488 IP14_15_12 5489 IP14_11_8 5490 IP14_7_4 5491 IP14_3_0 )) 5492 }, 5493 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP( 5494 IP15_31_28 5495 IP15_27_24 5496 IP15_23_20 5497 IP15_19_16 5498 IP15_15_12 5499 IP15_11_8 5500 IP15_7_4 5501 IP15_3_0 )) 5502 }, 5503 { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4, GROUP( 5504 IP16_31_28 5505 IP16_27_24 5506 IP16_23_20 5507 IP16_19_16 5508 IP16_15_12 5509 IP16_11_8 5510 IP16_7_4 5511 IP16_3_0 )) 5512 }, 5513 { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4, GROUP( 5514 IP17_31_28 5515 IP17_27_24 5516 IP17_23_20 5517 IP17_19_16 5518 IP17_15_12 5519 IP17_11_8 5520 IP17_7_4 5521 IP17_3_0 )) 5522 }, 5523 { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4, GROUP( 5524 /* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5525 /* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5526 /* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5527 /* IP18_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5528 /* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5529 /* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5530 IP18_7_4 5531 IP18_3_0 )) 5532 }, 5533 #undef F_ 5534 #undef FM 5535 5536 #define F_(x, y) x, 5537 #define FM(x) FN_##x, 5538 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32, 5539 GROUP(3, 2, 3, 1, 1, 1, 1, 1, 2, 1, 1, 2, 5540 1, 1, 1, 2, 2, 1, 2, 3), 5541 GROUP( 5542 MOD_SEL0_31_30_29 5543 MOD_SEL0_28_27 5544 MOD_SEL0_26_25_24 5545 MOD_SEL0_23 5546 MOD_SEL0_22 5547 MOD_SEL0_21 5548 MOD_SEL0_20 5549 MOD_SEL0_19 5550 MOD_SEL0_18_17 5551 MOD_SEL0_16 5552 0, 0, /* RESERVED 15 */ 5553 MOD_SEL0_14_13 5554 MOD_SEL0_12 5555 MOD_SEL0_11 5556 MOD_SEL0_10 5557 MOD_SEL0_9_8 5558 MOD_SEL0_7_6 5559 MOD_SEL0_5 5560 MOD_SEL0_4_3 5561 /* RESERVED 2, 1, 0 */ 5562 0, 0, 0, 0, 0, 0, 0, 0 )) 5563 }, 5564 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32, 5565 GROUP(2, 3, 1, 2, 3, 1, 1, 2, 1, 2, 1, 1, 5566 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1), 5567 GROUP( 5568 MOD_SEL1_31_30 5569 MOD_SEL1_29_28_27 5570 MOD_SEL1_26 5571 MOD_SEL1_25_24 5572 MOD_SEL1_23_22_21 5573 MOD_SEL1_20 5574 MOD_SEL1_19 5575 MOD_SEL1_18_17 5576 MOD_SEL1_16 5577 MOD_SEL1_15_14 5578 MOD_SEL1_13 5579 MOD_SEL1_12 5580 MOD_SEL1_11 5581 MOD_SEL1_10 5582 MOD_SEL1_9 5583 0, 0, 0, 0, /* RESERVED 8, 7 */ 5584 MOD_SEL1_6 5585 MOD_SEL1_5 5586 MOD_SEL1_4 5587 MOD_SEL1_3 5588 MOD_SEL1_2 5589 MOD_SEL1_1 5590 MOD_SEL1_0 )) 5591 }, 5592 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32, 5593 GROUP(1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, 5594 1, 4, 4, 4, 3, 1), 5595 GROUP( 5596 MOD_SEL2_31 5597 MOD_SEL2_30 5598 MOD_SEL2_29 5599 MOD_SEL2_28_27 5600 MOD_SEL2_26 5601 MOD_SEL2_25_24_23 5602 MOD_SEL2_22 5603 MOD_SEL2_21 5604 MOD_SEL2_20 5605 MOD_SEL2_19 5606 MOD_SEL2_18 5607 MOD_SEL2_17 5608 /* RESERVED 16 */ 5609 0, 0, 5610 /* RESERVED 15, 14, 13, 12 */ 5611 0, 0, 0, 0, 0, 0, 0, 0, 5612 0, 0, 0, 0, 0, 0, 0, 0, 5613 /* RESERVED 11, 10, 9, 8 */ 5614 0, 0, 0, 0, 0, 0, 0, 0, 5615 0, 0, 0, 0, 0, 0, 0, 0, 5616 /* RESERVED 7, 6, 5, 4 */ 5617 0, 0, 0, 0, 0, 0, 0, 0, 5618 0, 0, 0, 0, 0, 0, 0, 0, 5619 /* RESERVED 3, 2, 1 */ 5620 0, 0, 0, 0, 0, 0, 0, 0, 5621 MOD_SEL2_0 )) 5622 }, 5623 { }, 5624 }; 5625 5626 static const struct pinmux_drive_reg pinmux_drive_regs[] = { 5627 { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) { 5628 { PIN_QSPI0_SPCLK, 28, 2 }, /* QSPI0_SPCLK */ 5629 { PIN_QSPI0_MOSI_IO0, 24, 2 }, /* QSPI0_MOSI_IO0 */ 5630 { PIN_QSPI0_MISO_IO1, 20, 2 }, /* QSPI0_MISO_IO1 */ 5631 { PIN_QSPI0_IO2, 16, 2 }, /* QSPI0_IO2 */ 5632 { PIN_QSPI0_IO3, 12, 2 }, /* QSPI0_IO3 */ 5633 { PIN_QSPI0_SSL, 8, 2 }, /* QSPI0_SSL */ 5634 { PIN_QSPI1_SPCLK, 4, 2 }, /* QSPI1_SPCLK */ 5635 { PIN_QSPI1_MOSI_IO0, 0, 2 }, /* QSPI1_MOSI_IO0 */ 5636 } }, 5637 { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) { 5638 { PIN_QSPI1_MISO_IO1, 28, 2 }, /* QSPI1_MISO_IO1 */ 5639 { PIN_QSPI1_IO2, 24, 2 }, /* QSPI1_IO2 */ 5640 { PIN_QSPI1_IO3, 20, 2 }, /* QSPI1_IO3 */ 5641 { PIN_QSPI1_SSL, 16, 2 }, /* QSPI1_SSL */ 5642 { PIN_RPC_INT_N, 12, 2 }, /* RPC_INT# */ 5643 { PIN_RPC_WP_N, 8, 2 }, /* RPC_WP# */ 5644 { PIN_RPC_RESET_N, 4, 2 }, /* RPC_RESET# */ 5645 { PIN_AVB_RX_CTL, 0, 3 }, /* AVB_RX_CTL */ 5646 } }, 5647 { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) { 5648 { PIN_AVB_RXC, 28, 3 }, /* AVB_RXC */ 5649 { PIN_AVB_RD0, 24, 3 }, /* AVB_RD0 */ 5650 { PIN_AVB_RD1, 20, 3 }, /* AVB_RD1 */ 5651 { PIN_AVB_RD2, 16, 3 }, /* AVB_RD2 */ 5652 { PIN_AVB_RD3, 12, 3 }, /* AVB_RD3 */ 5653 { PIN_AVB_TX_CTL, 8, 3 }, /* AVB_TX_CTL */ 5654 { PIN_AVB_TXC, 4, 3 }, /* AVB_TXC */ 5655 { PIN_AVB_TD0, 0, 3 }, /* AVB_TD0 */ 5656 } }, 5657 { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) { 5658 { PIN_AVB_TD1, 28, 3 }, /* AVB_TD1 */ 5659 { PIN_AVB_TD2, 24, 3 }, /* AVB_TD2 */ 5660 { PIN_AVB_TD3, 20, 3 }, /* AVB_TD3 */ 5661 { PIN_AVB_TXCREFCLK, 16, 3 }, /* AVB_TXCREFCLK */ 5662 { PIN_AVB_MDIO, 12, 3 }, /* AVB_MDIO */ 5663 { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */ 5664 { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */ 5665 { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */ 5666 } }, 5667 { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) { 5668 { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */ 5669 { RCAR_GP_PIN(2, 13), 24, 3 }, /* AVB_AVTP_MATCH */ 5670 { RCAR_GP_PIN(2, 14), 20, 3 }, /* AVB_AVTP_CAPTURE */ 5671 { RCAR_GP_PIN(2, 0), 16, 3 }, /* IRQ0 */ 5672 { RCAR_GP_PIN(2, 1), 12, 3 }, /* IRQ1 */ 5673 { RCAR_GP_PIN(2, 2), 8, 3 }, /* IRQ2 */ 5674 { RCAR_GP_PIN(2, 3), 4, 3 }, /* IRQ3 */ 5675 { RCAR_GP_PIN(2, 4), 0, 3 }, /* IRQ4 */ 5676 } }, 5677 { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) { 5678 { RCAR_GP_PIN(2, 5), 28, 3 }, /* IRQ5 */ 5679 { RCAR_GP_PIN(2, 6), 24, 3 }, /* PWM0 */ 5680 { RCAR_GP_PIN(2, 7), 20, 3 }, /* PWM1 */ 5681 { RCAR_GP_PIN(2, 8), 16, 3 }, /* PWM2 */ 5682 { RCAR_GP_PIN(1, 0), 12, 3 }, /* A0 */ 5683 { RCAR_GP_PIN(1, 1), 8, 3 }, /* A1 */ 5684 { RCAR_GP_PIN(1, 2), 4, 3 }, /* A2 */ 5685 { RCAR_GP_PIN(1, 3), 0, 3 }, /* A3 */ 5686 } }, 5687 { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) { 5688 { RCAR_GP_PIN(1, 4), 28, 3 }, /* A4 */ 5689 { RCAR_GP_PIN(1, 5), 24, 3 }, /* A5 */ 5690 { RCAR_GP_PIN(1, 6), 20, 3 }, /* A6 */ 5691 { RCAR_GP_PIN(1, 7), 16, 3 }, /* A7 */ 5692 { RCAR_GP_PIN(1, 8), 12, 3 }, /* A8 */ 5693 { RCAR_GP_PIN(1, 9), 8, 3 }, /* A9 */ 5694 { RCAR_GP_PIN(1, 10), 4, 3 }, /* A10 */ 5695 { RCAR_GP_PIN(1, 11), 0, 3 }, /* A11 */ 5696 } }, 5697 { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) { 5698 { RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */ 5699 { RCAR_GP_PIN(1, 13), 24, 3 }, /* A13 */ 5700 { RCAR_GP_PIN(1, 14), 20, 3 }, /* A14 */ 5701 { RCAR_GP_PIN(1, 15), 16, 3 }, /* A15 */ 5702 { RCAR_GP_PIN(1, 16), 12, 3 }, /* A16 */ 5703 { RCAR_GP_PIN(1, 17), 8, 3 }, /* A17 */ 5704 { RCAR_GP_PIN(1, 18), 4, 3 }, /* A18 */ 5705 { RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */ 5706 } }, 5707 { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) { 5708 { RCAR_GP_PIN(1, 28), 28, 3 }, /* CLKOUT */ 5709 { RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */ 5710 { RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */ 5711 { RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */ 5712 { RCAR_GP_PIN(1, 23), 12, 3 }, /* RD */ 5713 { RCAR_GP_PIN(1, 24), 8, 3 }, /* RD_WR */ 5714 { RCAR_GP_PIN(1, 25), 4, 3 }, /* WE0 */ 5715 { RCAR_GP_PIN(1, 26), 0, 3 }, /* WE1 */ 5716 } }, 5717 { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) { 5718 { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */ 5719 { PIN_PRESETOUT_N, 24, 3 }, /* PRESETOUT# */ 5720 { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */ 5721 { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */ 5722 { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */ 5723 { RCAR_GP_PIN(0, 3), 8, 3 }, /* D3 */ 5724 { RCAR_GP_PIN(0, 4), 4, 3 }, /* D4 */ 5725 { RCAR_GP_PIN(0, 5), 0, 3 }, /* D5 */ 5726 } }, 5727 { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) { 5728 { RCAR_GP_PIN(0, 6), 28, 3 }, /* D6 */ 5729 { RCAR_GP_PIN(0, 7), 24, 3 }, /* D7 */ 5730 { RCAR_GP_PIN(0, 8), 20, 3 }, /* D8 */ 5731 { RCAR_GP_PIN(0, 9), 16, 3 }, /* D9 */ 5732 { RCAR_GP_PIN(0, 10), 12, 3 }, /* D10 */ 5733 { RCAR_GP_PIN(0, 11), 8, 3 }, /* D11 */ 5734 { RCAR_GP_PIN(0, 12), 4, 3 }, /* D12 */ 5735 { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */ 5736 } }, 5737 { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) { 5738 { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */ 5739 { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */ 5740 { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */ 5741 { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */ 5742 { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */ 5743 { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */ 5744 { PIN_DU_DOTCLKIN0, 4, 2 }, /* DU_DOTCLKIN0 */ 5745 { PIN_DU_DOTCLKIN1, 0, 2 }, /* DU_DOTCLKIN1 */ 5746 } }, 5747 { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) { 5748 { PIN_DU_DOTCLKIN2, 28, 2 }, /* DU_DOTCLKIN2 */ 5749 { PIN_FSCLKST, 20, 2 }, /* FSCLKST */ 5750 { PIN_TMS, 4, 2 }, /* TMS */ 5751 } }, 5752 { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) { 5753 { PIN_TDO, 28, 2 }, /* TDO */ 5754 { PIN_ASEBRK, 24, 2 }, /* ASEBRK */ 5755 { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */ 5756 { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */ 5757 { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */ 5758 { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */ 5759 { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */ 5760 { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */ 5761 } }, 5762 { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) { 5763 { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */ 5764 { RCAR_GP_PIN(3, 7), 24, 3 }, /* SD1_CMD */ 5765 { RCAR_GP_PIN(3, 8), 20, 3 }, /* SD1_DAT0 */ 5766 { RCAR_GP_PIN(3, 9), 16, 3 }, /* SD1_DAT1 */ 5767 { RCAR_GP_PIN(3, 10), 12, 3 }, /* SD1_DAT2 */ 5768 { RCAR_GP_PIN(3, 11), 8, 3 }, /* SD1_DAT3 */ 5769 { RCAR_GP_PIN(4, 0), 4, 3 }, /* SD2_CLK */ 5770 { RCAR_GP_PIN(4, 1), 0, 3 }, /* SD2_CMD */ 5771 } }, 5772 { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) { 5773 { RCAR_GP_PIN(4, 2), 28, 3 }, /* SD2_DAT0 */ 5774 { RCAR_GP_PIN(4, 3), 24, 3 }, /* SD2_DAT1 */ 5775 { RCAR_GP_PIN(4, 4), 20, 3 }, /* SD2_DAT2 */ 5776 { RCAR_GP_PIN(4, 5), 16, 3 }, /* SD2_DAT3 */ 5777 { RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */ 5778 { RCAR_GP_PIN(4, 7), 8, 3 }, /* SD3_CLK */ 5779 { RCAR_GP_PIN(4, 8), 4, 3 }, /* SD3_CMD */ 5780 { RCAR_GP_PIN(4, 9), 0, 3 }, /* SD3_DAT0 */ 5781 } }, 5782 { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) { 5783 { RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */ 5784 { RCAR_GP_PIN(4, 11), 24, 3 }, /* SD3_DAT2 */ 5785 { RCAR_GP_PIN(4, 12), 20, 3 }, /* SD3_DAT3 */ 5786 { RCAR_GP_PIN(4, 13), 16, 3 }, /* SD3_DAT4 */ 5787 { RCAR_GP_PIN(4, 14), 12, 3 }, /* SD3_DAT5 */ 5788 { RCAR_GP_PIN(4, 15), 8, 3 }, /* SD3_DAT6 */ 5789 { RCAR_GP_PIN(4, 16), 4, 3 }, /* SD3_DAT7 */ 5790 { RCAR_GP_PIN(4, 17), 0, 3 }, /* SD3_DS */ 5791 } }, 5792 { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) { 5793 { RCAR_GP_PIN(3, 12), 28, 3 }, /* SD0_CD */ 5794 { RCAR_GP_PIN(3, 13), 24, 3 }, /* SD0_WP */ 5795 { RCAR_GP_PIN(3, 14), 20, 3 }, /* SD1_CD */ 5796 { RCAR_GP_PIN(3, 15), 16, 3 }, /* SD1_WP */ 5797 { RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */ 5798 { RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */ 5799 { RCAR_GP_PIN(5, 2), 4, 3 }, /* TX0 */ 5800 { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */ 5801 } }, 5802 { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) { 5803 { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0 */ 5804 { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */ 5805 { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */ 5806 { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */ 5807 { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1 */ 5808 { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */ 5809 { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */ 5810 { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */ 5811 } }, 5812 { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) { 5813 { RCAR_GP_PIN(5, 12), 28, 3 }, /* HSCK0 */ 5814 { RCAR_GP_PIN(5, 13), 24, 3 }, /* HRX0 */ 5815 { RCAR_GP_PIN(5, 14), 20, 3 }, /* HTX0 */ 5816 { RCAR_GP_PIN(5, 15), 16, 3 }, /* HCTS0 */ 5817 { RCAR_GP_PIN(5, 16), 12, 3 }, /* HRTS0 */ 5818 { RCAR_GP_PIN(5, 17), 8, 3 }, /* MSIOF0_SCK */ 5819 { RCAR_GP_PIN(5, 18), 4, 3 }, /* MSIOF0_SYNC */ 5820 { RCAR_GP_PIN(5, 19), 0, 3 }, /* MSIOF0_SS1 */ 5821 } }, 5822 { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) { 5823 { RCAR_GP_PIN(5, 20), 28, 3 }, /* MSIOF0_TXD */ 5824 { RCAR_GP_PIN(5, 21), 24, 3 }, /* MSIOF0_SS2 */ 5825 { RCAR_GP_PIN(5, 22), 20, 3 }, /* MSIOF0_RXD */ 5826 { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */ 5827 { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */ 5828 { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */ 5829 { PIN_MLB_REF, 4, 3 }, /* MLB_REF */ 5830 { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */ 5831 } }, 5832 { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) { 5833 { RCAR_GP_PIN(6, 1), 28, 3 }, /* SSI_WS01239 */ 5834 { RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */ 5835 { RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */ 5836 { RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */ 5837 { RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK349 */ 5838 { RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS349 */ 5839 { RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */ 5840 { RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */ 5841 } }, 5842 { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) { 5843 { RCAR_GP_PIN(6, 9), 28, 3 }, /* SSI_WS4 */ 5844 { RCAR_GP_PIN(6, 10), 24, 3 }, /* SSI_SDATA4 */ 5845 { RCAR_GP_PIN(6, 11), 20, 3 }, /* SSI_SCK5 */ 5846 { RCAR_GP_PIN(6, 12), 16, 3 }, /* SSI_WS5 */ 5847 { RCAR_GP_PIN(6, 13), 12, 3 }, /* SSI_SDATA5 */ 5848 { RCAR_GP_PIN(6, 14), 8, 3 }, /* SSI_SCK6 */ 5849 { RCAR_GP_PIN(6, 15), 4, 3 }, /* SSI_WS6 */ 5850 { RCAR_GP_PIN(6, 16), 0, 3 }, /* SSI_SDATA6 */ 5851 } }, 5852 { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) { 5853 { RCAR_GP_PIN(6, 17), 28, 3 }, /* SSI_SCK78 */ 5854 { RCAR_GP_PIN(6, 18), 24, 3 }, /* SSI_WS78 */ 5855 { RCAR_GP_PIN(6, 19), 20, 3 }, /* SSI_SDATA7 */ 5856 { RCAR_GP_PIN(6, 20), 16, 3 }, /* SSI_SDATA8 */ 5857 { RCAR_GP_PIN(6, 21), 12, 3 }, /* SSI_SDATA9 */ 5858 { RCAR_GP_PIN(6, 22), 8, 3 }, /* AUDIO_CLKA */ 5859 { RCAR_GP_PIN(6, 23), 4, 3 }, /* AUDIO_CLKB */ 5860 { RCAR_GP_PIN(6, 24), 0, 3 }, /* USB0_PWEN */ 5861 } }, 5862 { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) { 5863 { RCAR_GP_PIN(6, 25), 28, 3 }, /* USB0_OVC */ 5864 { RCAR_GP_PIN(6, 26), 24, 3 }, /* USB1_PWEN */ 5865 { RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */ 5866 { RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */ 5867 { RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */ 5868 { RCAR_GP_PIN(6, 30), 8, 3 }, /* GP6_30 */ 5869 { RCAR_GP_PIN(6, 31), 4, 3 }, /* GP6_31 */ 5870 } }, 5871 { }, 5872 }; 5873 5874 enum ioctrl_regs { 5875 POCCTRL, 5876 TDSELCTRL, 5877 }; 5878 5879 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { 5880 [POCCTRL] = { 0xe6060380, }, 5881 [TDSELCTRL] = { 0xe60603c0, }, 5882 { /* sentinel */ }, 5883 }; 5884 5885 static int r8a7796_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl) 5886 { 5887 int bit = -EINVAL; 5888 5889 *pocctrl = pinmux_ioctrl_regs[POCCTRL].reg; 5890 5891 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11)) 5892 bit = pin & 0x1f; 5893 5894 if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17)) 5895 bit = (pin & 0x1f) + 12; 5896 5897 return bit; 5898 } 5899 5900 static const struct pinmux_bias_reg pinmux_bias_regs[] = { 5901 { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) { 5902 [ 0] = PIN_QSPI0_SPCLK, /* QSPI0_SPCLK */ 5903 [ 1] = PIN_QSPI0_MOSI_IO0, /* QSPI0_MOSI_IO0 */ 5904 [ 2] = PIN_QSPI0_MISO_IO1, /* QSPI0_MISO_IO1 */ 5905 [ 3] = PIN_QSPI0_IO2, /* QSPI0_IO2 */ 5906 [ 4] = PIN_QSPI0_IO3, /* QSPI0_IO3 */ 5907 [ 5] = PIN_QSPI0_SSL, /* QSPI0_SSL */ 5908 [ 6] = PIN_QSPI1_SPCLK, /* QSPI1_SPCLK */ 5909 [ 7] = PIN_QSPI1_MOSI_IO0, /* QSPI1_MOSI_IO0 */ 5910 [ 8] = PIN_QSPI1_MISO_IO1, /* QSPI1_MISO_IO1 */ 5911 [ 9] = PIN_QSPI1_IO2, /* QSPI1_IO2 */ 5912 [10] = PIN_QSPI1_IO3, /* QSPI1_IO3 */ 5913 [11] = PIN_QSPI1_SSL, /* QSPI1_SSL */ 5914 [12] = PIN_RPC_INT_N, /* RPC_INT# */ 5915 [13] = PIN_RPC_WP_N, /* RPC_WP# */ 5916 [14] = PIN_RPC_RESET_N, /* RPC_RESET# */ 5917 [15] = PIN_AVB_RX_CTL, /* AVB_RX_CTL */ 5918 [16] = PIN_AVB_RXC, /* AVB_RXC */ 5919 [17] = PIN_AVB_RD0, /* AVB_RD0 */ 5920 [18] = PIN_AVB_RD1, /* AVB_RD1 */ 5921 [19] = PIN_AVB_RD2, /* AVB_RD2 */ 5922 [20] = PIN_AVB_RD3, /* AVB_RD3 */ 5923 [21] = PIN_AVB_TX_CTL, /* AVB_TX_CTL */ 5924 [22] = PIN_AVB_TXC, /* AVB_TXC */ 5925 [23] = PIN_AVB_TD0, /* AVB_TD0 */ 5926 [24] = PIN_AVB_TD1, /* AVB_TD1 */ 5927 [25] = PIN_AVB_TD2, /* AVB_TD2 */ 5928 [26] = PIN_AVB_TD3, /* AVB_TD3 */ 5929 [27] = PIN_AVB_TXCREFCLK, /* AVB_TXCREFCLK */ 5930 [28] = PIN_AVB_MDIO, /* AVB_MDIO */ 5931 [29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */ 5932 [30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */ 5933 [31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */ 5934 } }, 5935 { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) { 5936 [ 0] = RCAR_GP_PIN(2, 12), /* AVB_LINK */ 5937 [ 1] = RCAR_GP_PIN(2, 13), /* AVB_AVTP_MATCH_A */ 5938 [ 2] = RCAR_GP_PIN(2, 14), /* AVB_AVTP_CAPTURE_A */ 5939 [ 3] = RCAR_GP_PIN(2, 0), /* IRQ0 */ 5940 [ 4] = RCAR_GP_PIN(2, 1), /* IRQ1 */ 5941 [ 5] = RCAR_GP_PIN(2, 2), /* IRQ2 */ 5942 [ 6] = RCAR_GP_PIN(2, 3), /* IRQ3 */ 5943 [ 7] = RCAR_GP_PIN(2, 4), /* IRQ4 */ 5944 [ 8] = RCAR_GP_PIN(2, 5), /* IRQ5 */ 5945 [ 9] = RCAR_GP_PIN(2, 6), /* PWM0 */ 5946 [10] = RCAR_GP_PIN(2, 7), /* PWM1_A */ 5947 [11] = RCAR_GP_PIN(2, 8), /* PWM2_A */ 5948 [12] = RCAR_GP_PIN(1, 0), /* A0 */ 5949 [13] = RCAR_GP_PIN(1, 1), /* A1 */ 5950 [14] = RCAR_GP_PIN(1, 2), /* A2 */ 5951 [15] = RCAR_GP_PIN(1, 3), /* A3 */ 5952 [16] = RCAR_GP_PIN(1, 4), /* A4 */ 5953 [17] = RCAR_GP_PIN(1, 5), /* A5 */ 5954 [18] = RCAR_GP_PIN(1, 6), /* A6 */ 5955 [19] = RCAR_GP_PIN(1, 7), /* A7 */ 5956 [20] = RCAR_GP_PIN(1, 8), /* A8 */ 5957 [21] = RCAR_GP_PIN(1, 9), /* A9 */ 5958 [22] = RCAR_GP_PIN(1, 10), /* A10 */ 5959 [23] = RCAR_GP_PIN(1, 11), /* A11 */ 5960 [24] = RCAR_GP_PIN(1, 12), /* A12 */ 5961 [25] = RCAR_GP_PIN(1, 13), /* A13 */ 5962 [26] = RCAR_GP_PIN(1, 14), /* A14 */ 5963 [27] = RCAR_GP_PIN(1, 15), /* A15 */ 5964 [28] = RCAR_GP_PIN(1, 16), /* A16 */ 5965 [29] = RCAR_GP_PIN(1, 17), /* A17 */ 5966 [30] = RCAR_GP_PIN(1, 18), /* A18 */ 5967 [31] = RCAR_GP_PIN(1, 19), /* A19 */ 5968 } }, 5969 { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) { 5970 [ 0] = RCAR_GP_PIN(1, 28), /* CLKOUT */ 5971 [ 1] = RCAR_GP_PIN(1, 20), /* CS0_N */ 5972 [ 2] = RCAR_GP_PIN(1, 21), /* CS1_N */ 5973 [ 3] = RCAR_GP_PIN(1, 22), /* BS_N */ 5974 [ 4] = RCAR_GP_PIN(1, 23), /* RD_N */ 5975 [ 5] = RCAR_GP_PIN(1, 24), /* RD_WR_N */ 5976 [ 6] = RCAR_GP_PIN(1, 25), /* WE0_N */ 5977 [ 7] = RCAR_GP_PIN(1, 26), /* WE1_N */ 5978 [ 8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */ 5979 [ 9] = PIN_PRESETOUT_N, /* PRESETOUT# */ 5980 [10] = RCAR_GP_PIN(0, 0), /* D0 */ 5981 [11] = RCAR_GP_PIN(0, 1), /* D1 */ 5982 [12] = RCAR_GP_PIN(0, 2), /* D2 */ 5983 [13] = RCAR_GP_PIN(0, 3), /* D3 */ 5984 [14] = RCAR_GP_PIN(0, 4), /* D4 */ 5985 [15] = RCAR_GP_PIN(0, 5), /* D5 */ 5986 [16] = RCAR_GP_PIN(0, 6), /* D6 */ 5987 [17] = RCAR_GP_PIN(0, 7), /* D7 */ 5988 [18] = RCAR_GP_PIN(0, 8), /* D8 */ 5989 [19] = RCAR_GP_PIN(0, 9), /* D9 */ 5990 [20] = RCAR_GP_PIN(0, 10), /* D10 */ 5991 [21] = RCAR_GP_PIN(0, 11), /* D11 */ 5992 [22] = RCAR_GP_PIN(0, 12), /* D12 */ 5993 [23] = RCAR_GP_PIN(0, 13), /* D13 */ 5994 [24] = RCAR_GP_PIN(0, 14), /* D14 */ 5995 [25] = RCAR_GP_PIN(0, 15), /* D15 */ 5996 [26] = RCAR_GP_PIN(7, 0), /* AVS1 */ 5997 [27] = RCAR_GP_PIN(7, 1), /* AVS2 */ 5998 [28] = RCAR_GP_PIN(7, 2), /* GP7_02 */ 5999 [29] = RCAR_GP_PIN(7, 3), /* GP7_03 */ 6000 [30] = PIN_DU_DOTCLKIN0, /* DU_DOTCLKIN0 */ 6001 [31] = PIN_DU_DOTCLKIN1, /* DU_DOTCLKIN1 */ 6002 } }, 6003 { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) { 6004 [ 0] = PIN_DU_DOTCLKIN2, /* DU_DOTCLKIN2 */ 6005 [ 1] = SH_PFC_PIN_NONE, 6006 [ 2] = PIN_FSCLKST, /* FSCLKST */ 6007 [ 3] = PIN_EXTALR, /* EXTALR*/ 6008 [ 4] = PIN_TRST_N, /* TRST# */ 6009 [ 5] = PIN_TCK, /* TCK */ 6010 [ 6] = PIN_TMS, /* TMS */ 6011 [ 7] = PIN_TDI, /* TDI */ 6012 [ 8] = SH_PFC_PIN_NONE, 6013 [ 9] = PIN_ASEBRK, /* ASEBRK */ 6014 [10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */ 6015 [11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */ 6016 [12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */ 6017 [13] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */ 6018 [14] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */ 6019 [15] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */ 6020 [16] = RCAR_GP_PIN(3, 6), /* SD1_CLK */ 6021 [17] = RCAR_GP_PIN(3, 7), /* SD1_CMD */ 6022 [18] = RCAR_GP_PIN(3, 8), /* SD1_DAT0 */ 6023 [19] = RCAR_GP_PIN(3, 9), /* SD1_DAT1 */ 6024 [20] = RCAR_GP_PIN(3, 10), /* SD1_DAT2 */ 6025 [21] = RCAR_GP_PIN(3, 11), /* SD1_DAT3 */ 6026 [22] = RCAR_GP_PIN(4, 0), /* SD2_CLK */ 6027 [23] = RCAR_GP_PIN(4, 1), /* SD2_CMD */ 6028 [24] = RCAR_GP_PIN(4, 2), /* SD2_DAT0 */ 6029 [25] = RCAR_GP_PIN(4, 3), /* SD2_DAT1 */ 6030 [26] = RCAR_GP_PIN(4, 4), /* SD2_DAT2 */ 6031 [27] = RCAR_GP_PIN(4, 5), /* SD2_DAT3 */ 6032 [28] = RCAR_GP_PIN(4, 6), /* SD2_DS */ 6033 [29] = RCAR_GP_PIN(4, 7), /* SD3_CLK */ 6034 [30] = RCAR_GP_PIN(4, 8), /* SD3_CMD */ 6035 [31] = RCAR_GP_PIN(4, 9), /* SD3_DAT0 */ 6036 } }, 6037 { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) { 6038 [ 0] = RCAR_GP_PIN(4, 10), /* SD3_DAT1 */ 6039 [ 1] = RCAR_GP_PIN(4, 11), /* SD3_DAT2 */ 6040 [ 2] = RCAR_GP_PIN(4, 12), /* SD3_DAT3 */ 6041 [ 3] = RCAR_GP_PIN(4, 13), /* SD3_DAT4 */ 6042 [ 4] = RCAR_GP_PIN(4, 14), /* SD3_DAT5 */ 6043 [ 5] = RCAR_GP_PIN(4, 15), /* SD3_DAT6 */ 6044 [ 6] = RCAR_GP_PIN(4, 16), /* SD3_DAT7 */ 6045 [ 7] = RCAR_GP_PIN(4, 17), /* SD3_DS */ 6046 [ 8] = RCAR_GP_PIN(3, 12), /* SD0_CD */ 6047 [ 9] = RCAR_GP_PIN(3, 13), /* SD0_WP */ 6048 [10] = RCAR_GP_PIN(3, 14), /* SD1_CD */ 6049 [11] = RCAR_GP_PIN(3, 15), /* SD1_WP */ 6050 [12] = RCAR_GP_PIN(5, 0), /* SCK0 */ 6051 [13] = RCAR_GP_PIN(5, 1), /* RX0 */ 6052 [14] = RCAR_GP_PIN(5, 2), /* TX0 */ 6053 [15] = RCAR_GP_PIN(5, 3), /* CTS0_N */ 6054 [16] = RCAR_GP_PIN(5, 4), /* RTS0_N */ 6055 [17] = RCAR_GP_PIN(5, 5), /* RX1_A */ 6056 [18] = RCAR_GP_PIN(5, 6), /* TX1_A */ 6057 [19] = RCAR_GP_PIN(5, 7), /* CTS1_N */ 6058 [20] = RCAR_GP_PIN(5, 8), /* RTS1_N */ 6059 [21] = RCAR_GP_PIN(5, 9), /* SCK2 */ 6060 [22] = RCAR_GP_PIN(5, 10), /* TX2_A */ 6061 [23] = RCAR_GP_PIN(5, 11), /* RX2_A */ 6062 [24] = RCAR_GP_PIN(5, 12), /* HSCK0 */ 6063 [25] = RCAR_GP_PIN(5, 13), /* HRX0 */ 6064 [26] = RCAR_GP_PIN(5, 14), /* HTX0 */ 6065 [27] = RCAR_GP_PIN(5, 15), /* HCTS0_N */ 6066 [28] = RCAR_GP_PIN(5, 16), /* HRTS0_N */ 6067 [29] = RCAR_GP_PIN(5, 17), /* MSIOF0_SCK */ 6068 [30] = RCAR_GP_PIN(5, 18), /* MSIOF0_SYNC */ 6069 [31] = RCAR_GP_PIN(5, 19), /* MSIOF0_SS1 */ 6070 } }, 6071 { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) { 6072 [ 0] = RCAR_GP_PIN(5, 20), /* MSIOF0_TXD */ 6073 [ 1] = RCAR_GP_PIN(5, 21), /* MSIOF0_SS2 */ 6074 [ 2] = RCAR_GP_PIN(5, 22), /* MSIOF0_RXD */ 6075 [ 3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */ 6076 [ 4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */ 6077 [ 5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */ 6078 [ 6] = PIN_MLB_REF, /* MLB_REF */ 6079 [ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */ 6080 [ 8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */ 6081 [ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */ 6082 [10] = RCAR_GP_PIN(6, 3), /* SSI_SDATA1_A */ 6083 [11] = RCAR_GP_PIN(6, 4), /* SSI_SDATA2_A */ 6084 [12] = RCAR_GP_PIN(6, 5), /* SSI_SCK349 */ 6085 [13] = RCAR_GP_PIN(6, 6), /* SSI_WS349 */ 6086 [14] = RCAR_GP_PIN(6, 7), /* SSI_SDATA3 */ 6087 [15] = RCAR_GP_PIN(6, 8), /* SSI_SCK4 */ 6088 [16] = RCAR_GP_PIN(6, 9), /* SSI_WS4 */ 6089 [17] = RCAR_GP_PIN(6, 10), /* SSI_SDATA4 */ 6090 [18] = RCAR_GP_PIN(6, 11), /* SSI_SCK5 */ 6091 [19] = RCAR_GP_PIN(6, 12), /* SSI_WS5 */ 6092 [20] = RCAR_GP_PIN(6, 13), /* SSI_SDATA5 */ 6093 [21] = RCAR_GP_PIN(6, 14), /* SSI_SCK6 */ 6094 [22] = RCAR_GP_PIN(6, 15), /* SSI_WS6 */ 6095 [23] = RCAR_GP_PIN(6, 16), /* SSI_SDATA6 */ 6096 [24] = RCAR_GP_PIN(6, 17), /* SSI_SCK78 */ 6097 [25] = RCAR_GP_PIN(6, 18), /* SSI_WS78 */ 6098 [26] = RCAR_GP_PIN(6, 19), /* SSI_SDATA7 */ 6099 [27] = RCAR_GP_PIN(6, 20), /* SSI_SDATA8 */ 6100 [28] = RCAR_GP_PIN(6, 21), /* SSI_SDATA9_A */ 6101 [29] = RCAR_GP_PIN(6, 22), /* AUDIO_CLKA_A */ 6102 [30] = RCAR_GP_PIN(6, 23), /* AUDIO_CLKB_B */ 6103 [31] = RCAR_GP_PIN(6, 24), /* USB0_PWEN */ 6104 } }, 6105 { PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) { 6106 [ 0] = RCAR_GP_PIN(6, 25), /* USB0_OVC */ 6107 [ 1] = RCAR_GP_PIN(6, 26), /* USB1_PWEN */ 6108 [ 2] = RCAR_GP_PIN(6, 27), /* USB1_OVC */ 6109 [ 3] = RCAR_GP_PIN(6, 28), /* USB30_PWEN */ 6110 [ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */ 6111 [ 5] = RCAR_GP_PIN(6, 30), /* GP6_30 */ 6112 [ 6] = RCAR_GP_PIN(6, 31), /* GP6_31 */ 6113 [ 7] = PIN_PRESET_N, /* PRESET# */ 6114 [ 8] = SH_PFC_PIN_NONE, 6115 [ 9] = SH_PFC_PIN_NONE, 6116 [10] = SH_PFC_PIN_NONE, 6117 [11] = SH_PFC_PIN_NONE, 6118 [12] = SH_PFC_PIN_NONE, 6119 [13] = SH_PFC_PIN_NONE, 6120 [14] = SH_PFC_PIN_NONE, 6121 [15] = SH_PFC_PIN_NONE, 6122 [16] = SH_PFC_PIN_NONE, 6123 [17] = SH_PFC_PIN_NONE, 6124 [18] = SH_PFC_PIN_NONE, 6125 [19] = SH_PFC_PIN_NONE, 6126 [20] = SH_PFC_PIN_NONE, 6127 [21] = SH_PFC_PIN_NONE, 6128 [22] = SH_PFC_PIN_NONE, 6129 [23] = SH_PFC_PIN_NONE, 6130 [24] = SH_PFC_PIN_NONE, 6131 [25] = SH_PFC_PIN_NONE, 6132 [26] = SH_PFC_PIN_NONE, 6133 [27] = SH_PFC_PIN_NONE, 6134 [28] = SH_PFC_PIN_NONE, 6135 [29] = SH_PFC_PIN_NONE, 6136 [30] = SH_PFC_PIN_NONE, 6137 [31] = SH_PFC_PIN_NONE, 6138 } }, 6139 { /* sentinel */ }, 6140 }; 6141 6142 static unsigned int r8a7796_pinmux_get_bias(struct sh_pfc *pfc, 6143 unsigned int pin) 6144 { 6145 const struct pinmux_bias_reg *reg; 6146 unsigned int bit; 6147 6148 reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit); 6149 if (!reg) 6150 return PIN_CONFIG_BIAS_DISABLE; 6151 6152 if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit))) 6153 return PIN_CONFIG_BIAS_DISABLE; 6154 else if (sh_pfc_read(pfc, reg->pud) & BIT(bit)) 6155 return PIN_CONFIG_BIAS_PULL_UP; 6156 else 6157 return PIN_CONFIG_BIAS_PULL_DOWN; 6158 } 6159 6160 static void r8a7796_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, 6161 unsigned int bias) 6162 { 6163 const struct pinmux_bias_reg *reg; 6164 u32 enable, updown; 6165 unsigned int bit; 6166 6167 reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit); 6168 if (!reg) 6169 return; 6170 6171 enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit); 6172 if (bias != PIN_CONFIG_BIAS_DISABLE) 6173 enable |= BIT(bit); 6174 6175 updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit); 6176 if (bias == PIN_CONFIG_BIAS_PULL_UP) 6177 updown |= BIT(bit); 6178 6179 sh_pfc_write(pfc, reg->pud, updown); 6180 sh_pfc_write(pfc, reg->puen, enable); 6181 } 6182 6183 static const struct sh_pfc_soc_operations r8a7796_pinmux_ops = { 6184 .pin_to_pocctrl = r8a7796_pin_to_pocctrl, 6185 .get_bias = r8a7796_pinmux_get_bias, 6186 .set_bias = r8a7796_pinmux_set_bias, 6187 }; 6188 6189 #ifdef CONFIG_PINCTRL_PFC_R8A774A1 6190 const struct sh_pfc_soc_info r8a774a1_pinmux_info = { 6191 .name = "r8a774a1_pfc", 6192 .ops = &r8a7796_pinmux_ops, 6193 .unlock_reg = 0xe6060000, /* PMMR */ 6194 6195 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 6196 6197 .pins = pinmux_pins, 6198 .nr_pins = ARRAY_SIZE(pinmux_pins), 6199 .groups = pinmux_groups.common, 6200 .nr_groups = ARRAY_SIZE(pinmux_groups.common), 6201 .functions = pinmux_functions.common, 6202 .nr_functions = ARRAY_SIZE(pinmux_functions.common), 6203 6204 .cfg_regs = pinmux_config_regs, 6205 .drive_regs = pinmux_drive_regs, 6206 .bias_regs = pinmux_bias_regs, 6207 .ioctrl_regs = pinmux_ioctrl_regs, 6208 6209 .pinmux_data = pinmux_data, 6210 .pinmux_data_size = ARRAY_SIZE(pinmux_data), 6211 }; 6212 #endif 6213 6214 #ifdef CONFIG_PINCTRL_PFC_R8A77960 6215 const struct sh_pfc_soc_info r8a77960_pinmux_info = { 6216 .name = "r8a77960_pfc", 6217 .ops = &r8a7796_pinmux_ops, 6218 .unlock_reg = 0xe6060000, /* PMMR */ 6219 6220 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 6221 6222 .pins = pinmux_pins, 6223 .nr_pins = ARRAY_SIZE(pinmux_pins), 6224 .groups = pinmux_groups.common, 6225 .nr_groups = ARRAY_SIZE(pinmux_groups.common) + 6226 ARRAY_SIZE(pinmux_groups.automotive), 6227 .functions = pinmux_functions.common, 6228 .nr_functions = ARRAY_SIZE(pinmux_functions.common) + 6229 ARRAY_SIZE(pinmux_functions.automotive), 6230 6231 .cfg_regs = pinmux_config_regs, 6232 .drive_regs = pinmux_drive_regs, 6233 .bias_regs = pinmux_bias_regs, 6234 .ioctrl_regs = pinmux_ioctrl_regs, 6235 6236 .pinmux_data = pinmux_data, 6237 .pinmux_data_size = ARRAY_SIZE(pinmux_data), 6238 }; 6239 #endif 6240 6241 #ifdef CONFIG_PINCTRL_PFC_R8A77961 6242 const struct sh_pfc_soc_info r8a77961_pinmux_info = { 6243 .name = "r8a77961_pfc", 6244 .ops = &r8a7796_pinmux_ops, 6245 .unlock_reg = 0xe6060000, /* PMMR */ 6246 6247 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 6248 6249 .pins = pinmux_pins, 6250 .nr_pins = ARRAY_SIZE(pinmux_pins), 6251 .groups = pinmux_groups.common, 6252 .nr_groups = ARRAY_SIZE(pinmux_groups.common) + 6253 ARRAY_SIZE(pinmux_groups.automotive), 6254 .functions = pinmux_functions.common, 6255 .nr_functions = ARRAY_SIZE(pinmux_functions.common) + 6256 ARRAY_SIZE(pinmux_functions.automotive), 6257 6258 .cfg_regs = pinmux_config_regs, 6259 .drive_regs = pinmux_drive_regs, 6260 .bias_regs = pinmux_bias_regs, 6261 .ioctrl_regs = pinmux_ioctrl_regs, 6262 6263 .pinmux_data = pinmux_data, 6264 .pinmux_data_size = ARRAY_SIZE(pinmux_data), 6265 }; 6266 #endif 6267