1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * R8A7796 (R-Car M3-W/W+) support - PFC hardware block. 4 * 5 * Copyright (C) 2016-2019 Renesas Electronics Corp. 6 * 7 * This file is based on the drivers/pinctrl/renesas/pfc-r8a7795.c 8 * 9 * R-Car Gen3 processor support - PFC hardware block. 10 * 11 * Copyright (C) 2015 Renesas Electronics Corporation 12 */ 13 14 #include <linux/errno.h> 15 #include <linux/kernel.h> 16 17 #include "sh_pfc.h" 18 19 #define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN) 20 21 #define CPU_ALL_GP(fn, sfx) \ 22 PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \ 23 PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \ 24 PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \ 25 PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \ 26 PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \ 27 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \ 28 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \ 29 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \ 30 PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \ 31 PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \ 32 PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \ 33 PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS) 34 35 #define CPU_ALL_NOGP(fn) \ 36 PIN_NOGP_CFG(ASEBRK, "ASEBRK", fn, CFG_FLAGS), \ 37 PIN_NOGP_CFG(AVB_MDIO, "AVB_MDIO", fn, CFG_FLAGS), \ 38 PIN_NOGP_CFG(AVB_RD0, "AVB_RD0", fn, CFG_FLAGS), \ 39 PIN_NOGP_CFG(AVB_RD1, "AVB_RD1", fn, CFG_FLAGS), \ 40 PIN_NOGP_CFG(AVB_RD2, "AVB_RD2", fn, CFG_FLAGS), \ 41 PIN_NOGP_CFG(AVB_RD3, "AVB_RD3", fn, CFG_FLAGS), \ 42 PIN_NOGP_CFG(AVB_RXC, "AVB_RXC", fn, CFG_FLAGS), \ 43 PIN_NOGP_CFG(AVB_RX_CTL, "AVB_RX_CTL", fn, CFG_FLAGS), \ 44 PIN_NOGP_CFG(AVB_TD0, "AVB_TD0", fn, CFG_FLAGS), \ 45 PIN_NOGP_CFG(AVB_TD1, "AVB_TD1", fn, CFG_FLAGS), \ 46 PIN_NOGP_CFG(AVB_TD2, "AVB_TD2", fn, CFG_FLAGS), \ 47 PIN_NOGP_CFG(AVB_TD3, "AVB_TD3", fn, CFG_FLAGS), \ 48 PIN_NOGP_CFG(AVB_TXC, "AVB_TXC", fn, CFG_FLAGS), \ 49 PIN_NOGP_CFG(AVB_TXCREFCLK, "AVB_TXCREFCLK", fn, CFG_FLAGS), \ 50 PIN_NOGP_CFG(AVB_TX_CTL, "AVB_TX_CTL", fn, CFG_FLAGS), \ 51 PIN_NOGP_CFG(DU_DOTCLKIN0, "DU_DOTCLKIN0", fn, CFG_FLAGS), \ 52 PIN_NOGP_CFG(DU_DOTCLKIN1, "DU_DOTCLKIN1", fn, CFG_FLAGS), \ 53 PIN_NOGP_CFG(DU_DOTCLKIN2, "DU_DOTCLKIN2", fn, CFG_FLAGS), \ 54 PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),\ 55 PIN_NOGP_CFG(FSCLKST, "FSCLKST", fn, CFG_FLAGS), \ 56 PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS), \ 57 PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, CFG_FLAGS), \ 58 PIN_NOGP_CFG(QSPI0_IO2, "QSPI0_IO2", fn, CFG_FLAGS), \ 59 PIN_NOGP_CFG(QSPI0_IO3, "QSPI0_IO3", fn, CFG_FLAGS), \ 60 PIN_NOGP_CFG(QSPI0_MISO_IO1, "QSPI0_MISO_IO1", fn, CFG_FLAGS), \ 61 PIN_NOGP_CFG(QSPI0_MOSI_IO0, "QSPI0_MOSI_IO0", fn, CFG_FLAGS), \ 62 PIN_NOGP_CFG(QSPI0_SPCLK, "QSPI0_SPCLK", fn, CFG_FLAGS), \ 63 PIN_NOGP_CFG(QSPI0_SSL, "QSPI0_SSL", fn, CFG_FLAGS), \ 64 PIN_NOGP_CFG(QSPI1_IO2, "QSPI1_IO2", fn, CFG_FLAGS), \ 65 PIN_NOGP_CFG(QSPI1_IO3, "QSPI1_IO3", fn, CFG_FLAGS), \ 66 PIN_NOGP_CFG(QSPI1_MISO_IO1, "QSPI1_MISO_IO1", fn, CFG_FLAGS), \ 67 PIN_NOGP_CFG(QSPI1_MOSI_IO0, "QSPI1_MOSI_IO0", fn, CFG_FLAGS), \ 68 PIN_NOGP_CFG(QSPI1_SPCLK, "QSPI1_SPCLK", fn, CFG_FLAGS), \ 69 PIN_NOGP_CFG(QSPI1_SSL, "QSPI1_SSL", fn, CFG_FLAGS), \ 70 PIN_NOGP_CFG(RPC_INT_N, "RPC_INT#", fn, CFG_FLAGS), \ 71 PIN_NOGP_CFG(RPC_RESET_N, "RPC_RESET#", fn, CFG_FLAGS), \ 72 PIN_NOGP_CFG(RPC_WP_N, "RPC_WP#", fn, CFG_FLAGS), \ 73 PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ 74 PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ 75 PIN_NOGP_CFG(TDO, "TDO", fn, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \ 76 PIN_NOGP_CFG(TMS, "TMS", fn, CFG_FLAGS), \ 77 PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN) 78 79 /* 80 * F_() : just information 81 * FM() : macro for FN_xxx / xxx_MARK 82 */ 83 84 /* GPSR0 */ 85 #define GPSR0_15 F_(D15, IP7_11_8) 86 #define GPSR0_14 F_(D14, IP7_7_4) 87 #define GPSR0_13 F_(D13, IP7_3_0) 88 #define GPSR0_12 F_(D12, IP6_31_28) 89 #define GPSR0_11 F_(D11, IP6_27_24) 90 #define GPSR0_10 F_(D10, IP6_23_20) 91 #define GPSR0_9 F_(D9, IP6_19_16) 92 #define GPSR0_8 F_(D8, IP6_15_12) 93 #define GPSR0_7 F_(D7, IP6_11_8) 94 #define GPSR0_6 F_(D6, IP6_7_4) 95 #define GPSR0_5 F_(D5, IP6_3_0) 96 #define GPSR0_4 F_(D4, IP5_31_28) 97 #define GPSR0_3 F_(D3, IP5_27_24) 98 #define GPSR0_2 F_(D2, IP5_23_20) 99 #define GPSR0_1 F_(D1, IP5_19_16) 100 #define GPSR0_0 F_(D0, IP5_15_12) 101 102 /* GPSR1 */ 103 #define GPSR1_28 FM(CLKOUT) 104 #define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8) 105 #define GPSR1_26 F_(WE1_N, IP5_7_4) 106 #define GPSR1_25 F_(WE0_N, IP5_3_0) 107 #define GPSR1_24 F_(RD_WR_N, IP4_31_28) 108 #define GPSR1_23 F_(RD_N, IP4_27_24) 109 #define GPSR1_22 F_(BS_N, IP4_23_20) 110 #define GPSR1_21 F_(CS1_N, IP4_19_16) 111 #define GPSR1_20 F_(CS0_N, IP4_15_12) 112 #define GPSR1_19 F_(A19, IP4_11_8) 113 #define GPSR1_18 F_(A18, IP4_7_4) 114 #define GPSR1_17 F_(A17, IP4_3_0) 115 #define GPSR1_16 F_(A16, IP3_31_28) 116 #define GPSR1_15 F_(A15, IP3_27_24) 117 #define GPSR1_14 F_(A14, IP3_23_20) 118 #define GPSR1_13 F_(A13, IP3_19_16) 119 #define GPSR1_12 F_(A12, IP3_15_12) 120 #define GPSR1_11 F_(A11, IP3_11_8) 121 #define GPSR1_10 F_(A10, IP3_7_4) 122 #define GPSR1_9 F_(A9, IP3_3_0) 123 #define GPSR1_8 F_(A8, IP2_31_28) 124 #define GPSR1_7 F_(A7, IP2_27_24) 125 #define GPSR1_6 F_(A6, IP2_23_20) 126 #define GPSR1_5 F_(A5, IP2_19_16) 127 #define GPSR1_4 F_(A4, IP2_15_12) 128 #define GPSR1_3 F_(A3, IP2_11_8) 129 #define GPSR1_2 F_(A2, IP2_7_4) 130 #define GPSR1_1 F_(A1, IP2_3_0) 131 #define GPSR1_0 F_(A0, IP1_31_28) 132 133 /* GPSR2 */ 134 #define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20) 135 #define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16) 136 #define GPSR2_12 F_(AVB_LINK, IP0_15_12) 137 #define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8) 138 #define GPSR2_10 F_(AVB_MAGIC, IP0_7_4) 139 #define GPSR2_9 F_(AVB_MDC, IP0_3_0) 140 #define GPSR2_8 F_(PWM2_A, IP1_27_24) 141 #define GPSR2_7 F_(PWM1_A, IP1_23_20) 142 #define GPSR2_6 F_(PWM0, IP1_19_16) 143 #define GPSR2_5 F_(IRQ5, IP1_15_12) 144 #define GPSR2_4 F_(IRQ4, IP1_11_8) 145 #define GPSR2_3 F_(IRQ3, IP1_7_4) 146 #define GPSR2_2 F_(IRQ2, IP1_3_0) 147 #define GPSR2_1 F_(IRQ1, IP0_31_28) 148 #define GPSR2_0 F_(IRQ0, IP0_27_24) 149 150 /* GPSR3 */ 151 #define GPSR3_15 F_(SD1_WP, IP11_23_20) 152 #define GPSR3_14 F_(SD1_CD, IP11_19_16) 153 #define GPSR3_13 F_(SD0_WP, IP11_15_12) 154 #define GPSR3_12 F_(SD0_CD, IP11_11_8) 155 #define GPSR3_11 F_(SD1_DAT3, IP8_31_28) 156 #define GPSR3_10 F_(SD1_DAT2, IP8_27_24) 157 #define GPSR3_9 F_(SD1_DAT1, IP8_23_20) 158 #define GPSR3_8 F_(SD1_DAT0, IP8_19_16) 159 #define GPSR3_7 F_(SD1_CMD, IP8_15_12) 160 #define GPSR3_6 F_(SD1_CLK, IP8_11_8) 161 #define GPSR3_5 F_(SD0_DAT3, IP8_7_4) 162 #define GPSR3_4 F_(SD0_DAT2, IP8_3_0) 163 #define GPSR3_3 F_(SD0_DAT1, IP7_31_28) 164 #define GPSR3_2 F_(SD0_DAT0, IP7_27_24) 165 #define GPSR3_1 F_(SD0_CMD, IP7_23_20) 166 #define GPSR3_0 F_(SD0_CLK, IP7_19_16) 167 168 /* GPSR4 */ 169 #define GPSR4_17 F_(SD3_DS, IP11_7_4) 170 #define GPSR4_16 F_(SD3_DAT7, IP11_3_0) 171 #define GPSR4_15 F_(SD3_DAT6, IP10_31_28) 172 #define GPSR4_14 F_(SD3_DAT5, IP10_27_24) 173 #define GPSR4_13 F_(SD3_DAT4, IP10_23_20) 174 #define GPSR4_12 F_(SD3_DAT3, IP10_19_16) 175 #define GPSR4_11 F_(SD3_DAT2, IP10_15_12) 176 #define GPSR4_10 F_(SD3_DAT1, IP10_11_8) 177 #define GPSR4_9 F_(SD3_DAT0, IP10_7_4) 178 #define GPSR4_8 F_(SD3_CMD, IP10_3_0) 179 #define GPSR4_7 F_(SD3_CLK, IP9_31_28) 180 #define GPSR4_6 F_(SD2_DS, IP9_27_24) 181 #define GPSR4_5 F_(SD2_DAT3, IP9_23_20) 182 #define GPSR4_4 F_(SD2_DAT2, IP9_19_16) 183 #define GPSR4_3 F_(SD2_DAT1, IP9_15_12) 184 #define GPSR4_2 F_(SD2_DAT0, IP9_11_8) 185 #define GPSR4_1 F_(SD2_CMD, IP9_7_4) 186 #define GPSR4_0 F_(SD2_CLK, IP9_3_0) 187 188 /* GPSR5 */ 189 #define GPSR5_25 F_(MLB_DAT, IP14_19_16) 190 #define GPSR5_24 F_(MLB_SIG, IP14_15_12) 191 #define GPSR5_23 F_(MLB_CLK, IP14_11_8) 192 #define GPSR5_22 FM(MSIOF0_RXD) 193 #define GPSR5_21 F_(MSIOF0_SS2, IP14_7_4) 194 #define GPSR5_20 FM(MSIOF0_TXD) 195 #define GPSR5_19 F_(MSIOF0_SS1, IP14_3_0) 196 #define GPSR5_18 F_(MSIOF0_SYNC, IP13_31_28) 197 #define GPSR5_17 FM(MSIOF0_SCK) 198 #define GPSR5_16 F_(HRTS0_N, IP13_27_24) 199 #define GPSR5_15 F_(HCTS0_N, IP13_23_20) 200 #define GPSR5_14 F_(HTX0, IP13_19_16) 201 #define GPSR5_13 F_(HRX0, IP13_15_12) 202 #define GPSR5_12 F_(HSCK0, IP13_11_8) 203 #define GPSR5_11 F_(RX2_A, IP13_7_4) 204 #define GPSR5_10 F_(TX2_A, IP13_3_0) 205 #define GPSR5_9 F_(SCK2, IP12_31_28) 206 #define GPSR5_8 F_(RTS1_N, IP12_27_24) 207 #define GPSR5_7 F_(CTS1_N, IP12_23_20) 208 #define GPSR5_6 F_(TX1_A, IP12_19_16) 209 #define GPSR5_5 F_(RX1_A, IP12_15_12) 210 #define GPSR5_4 F_(RTS0_N, IP12_11_8) 211 #define GPSR5_3 F_(CTS0_N, IP12_7_4) 212 #define GPSR5_2 F_(TX0, IP12_3_0) 213 #define GPSR5_1 F_(RX0, IP11_31_28) 214 #define GPSR5_0 F_(SCK0, IP11_27_24) 215 216 /* GPSR6 */ 217 #define GPSR6_31 F_(GP6_31, IP18_7_4) 218 #define GPSR6_30 F_(GP6_30, IP18_3_0) 219 #define GPSR6_29 F_(USB30_OVC, IP17_31_28) 220 #define GPSR6_28 F_(USB30_PWEN, IP17_27_24) 221 #define GPSR6_27 F_(USB1_OVC, IP17_23_20) 222 #define GPSR6_26 F_(USB1_PWEN, IP17_19_16) 223 #define GPSR6_25 F_(USB0_OVC, IP17_15_12) 224 #define GPSR6_24 F_(USB0_PWEN, IP17_11_8) 225 #define GPSR6_23 F_(AUDIO_CLKB_B, IP17_7_4) 226 #define GPSR6_22 F_(AUDIO_CLKA_A, IP17_3_0) 227 #define GPSR6_21 F_(SSI_SDATA9_A, IP16_31_28) 228 #define GPSR6_20 F_(SSI_SDATA8, IP16_27_24) 229 #define GPSR6_19 F_(SSI_SDATA7, IP16_23_20) 230 #define GPSR6_18 F_(SSI_WS78, IP16_19_16) 231 #define GPSR6_17 F_(SSI_SCK78, IP16_15_12) 232 #define GPSR6_16 F_(SSI_SDATA6, IP16_11_8) 233 #define GPSR6_15 F_(SSI_WS6, IP16_7_4) 234 #define GPSR6_14 F_(SSI_SCK6, IP16_3_0) 235 #define GPSR6_13 FM(SSI_SDATA5) 236 #define GPSR6_12 FM(SSI_WS5) 237 #define GPSR6_11 FM(SSI_SCK5) 238 #define GPSR6_10 F_(SSI_SDATA4, IP15_31_28) 239 #define GPSR6_9 F_(SSI_WS4, IP15_27_24) 240 #define GPSR6_8 F_(SSI_SCK4, IP15_23_20) 241 #define GPSR6_7 F_(SSI_SDATA3, IP15_19_16) 242 #define GPSR6_6 F_(SSI_WS349, IP15_15_12) 243 #define GPSR6_5 F_(SSI_SCK349, IP15_11_8) 244 #define GPSR6_4 F_(SSI_SDATA2_A, IP15_7_4) 245 #define GPSR6_3 F_(SSI_SDATA1_A, IP15_3_0) 246 #define GPSR6_2 F_(SSI_SDATA0, IP14_31_28) 247 #define GPSR6_1 F_(SSI_WS01239, IP14_27_24) 248 #define GPSR6_0 F_(SSI_SCK01239, IP14_23_20) 249 250 /* GPSR7 */ 251 #define GPSR7_3 FM(GP7_03) 252 #define GPSR7_2 FM(GP7_02) 253 #define GPSR7_1 FM(AVS2) 254 #define GPSR7_0 FM(AVS1) 255 256 257 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ 258 #define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 259 #define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 260 #define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 261 #define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 262 #define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 263 #define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 264 #define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 265 #define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 266 #define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 267 #define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) F_(0, 0) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 268 #define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) F_(0, 0) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 269 #define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) F_(0, 0) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) F_(0, 0) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 270 #define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)F_(0, 0) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 271 #define IP1_23_20 FM(PWM1_A) F_(0, 0) F_(0, 0) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 272 #define IP1_27_24 FM(PWM2_A) F_(0, 0) F_(0, 0) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 273 #define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 274 #define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 275 #define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 276 #define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 277 #define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 278 #define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 279 #define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 280 #define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 281 #define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 282 #define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 283 #define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 284 #define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 285 286 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ 287 #define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 288 #define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 289 #define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 290 #define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 291 #define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 292 #define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 293 #define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 294 #define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 295 #define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 296 #define IP4_19_16 FM(CS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 297 #define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 298 #define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 299 #define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 300 #define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 301 #define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 302 #define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 303 #define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 304 #define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 305 #define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 306 #define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 307 #define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 308 #define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 309 #define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 310 #define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 311 #define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 312 #define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 313 #define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 314 #define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_C) FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 315 #define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 316 317 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ 318 #define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 319 #define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 320 #define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 321 #define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 322 #define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 323 #define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 324 #define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 325 #define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 326 #define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 327 #define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 328 #define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) FM(NFCE_N_B) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 329 #define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) FM(NFWP_N_B) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 330 #define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) FM(NFDATA14_B) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 331 #define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) FM(NFDATA15_B) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 332 #define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) FM(NFRB_N_B) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 333 #define IP9_3_0 FM(SD2_CLK) F_(0, 0) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 334 #define IP9_7_4 FM(SD2_CMD) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 335 #define IP9_11_8 FM(SD2_DAT0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 336 #define IP9_15_12 FM(SD2_DAT1) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 337 #define IP9_19_16 FM(SD2_DAT2) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 338 #define IP9_23_20 FM(SD2_DAT3) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 339 #define IP9_27_24 FM(SD2_DS) F_(0, 0) FM(NFALE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 340 #define IP9_31_28 FM(SD3_CLK) F_(0, 0) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 341 #define IP10_3_0 FM(SD3_CMD) F_(0, 0) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 342 #define IP10_7_4 FM(SD3_DAT0) F_(0, 0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 343 #define IP10_11_8 FM(SD3_DAT1) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 344 #define IP10_15_12 FM(SD3_DAT2) F_(0, 0) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 345 #define IP10_19_16 FM(SD3_DAT3) F_(0, 0) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 346 #define IP10_23_20 FM(SD3_DAT4) FM(SD2_CD_A) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 347 #define IP10_27_24 FM(SD3_DAT5) FM(SD2_WP_A) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 348 #define IP10_31_28 FM(SD3_DAT6) FM(SD3_CD) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 349 #define IP11_3_0 FM(SD3_DAT7) FM(SD3_WP) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 350 #define IP11_7_4 FM(SD3_DS) F_(0, 0) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 351 #define IP11_11_8 FM(SD0_CD) F_(0, 0) FM(NFDATA14_A) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 352 353 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ 354 #define IP11_15_12 FM(SD0_WP) F_(0, 0) FM(NFDATA15_A) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 355 #define IP11_19_16 FM(SD1_CD) F_(0, 0) FM(NFRB_N_A) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 356 #define IP11_23_20 FM(SD1_WP) F_(0, 0) FM(NFCE_N_A) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 357 #define IP11_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 358 #define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 359 #define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 360 #define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 361 #define IP12_11_8 FM(RTS0_N) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 362 #define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 363 #define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 364 #define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 365 #define IP12_27_24 FM(RTS1_N) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 366 #define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 367 #define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 368 #define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 369 #define IP13_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 370 #define IP13_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 371 #define IP13_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 372 #define IP13_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 373 #define IP13_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 374 #define IP13_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) FM(TX5_B) F_(0, 0) F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0) 375 #define IP14_3_0 FM(MSIOF0_SS1) FM(RX5_A) FM(NFWP_N_A) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 376 #define IP14_7_4 FM(MSIOF0_SS2) FM(TX5_A) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 377 #define IP14_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 378 #define IP14_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 379 #define IP14_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 380 #define IP14_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 381 #define IP14_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 382 383 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ 384 #define IP14_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 385 #define IP15_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 386 #define IP15_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 387 #define IP15_11_8 FM(SSI_SCK349) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 388 #define IP15_15_12 FM(SSI_WS349) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 389 #define IP15_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 390 #define IP15_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 391 #define IP15_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 392 #define IP15_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 393 #define IP16_3_0 FM(SSI_SCK6) F_(0, 0) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 394 #define IP16_7_4 FM(SSI_WS6) F_(0, 0) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 395 #define IP16_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 396 #define IP16_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 397 #define IP16_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 398 #define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 399 #define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 400 #define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 401 #define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 402 #define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 403 #define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0) 404 #define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0) 405 #define IP17_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0) 406 #define IP17_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0) 407 #define IP17_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0) 408 #define IP17_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_N) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 409 #define IP18_3_0 FM(GP6_30) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0) 410 #define IP18_7_4 FM(GP6_31) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0) 411 412 #define PINMUX_GPSR \ 413 \ 414 GPSR6_31 \ 415 GPSR6_30 \ 416 GPSR6_29 \ 417 GPSR1_28 GPSR6_28 \ 418 GPSR1_27 GPSR6_27 \ 419 GPSR1_26 GPSR6_26 \ 420 GPSR1_25 GPSR5_25 GPSR6_25 \ 421 GPSR1_24 GPSR5_24 GPSR6_24 \ 422 GPSR1_23 GPSR5_23 GPSR6_23 \ 423 GPSR1_22 GPSR5_22 GPSR6_22 \ 424 GPSR1_21 GPSR5_21 GPSR6_21 \ 425 GPSR1_20 GPSR5_20 GPSR6_20 \ 426 GPSR1_19 GPSR5_19 GPSR6_19 \ 427 GPSR1_18 GPSR5_18 GPSR6_18 \ 428 GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \ 429 GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \ 430 GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \ 431 GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \ 432 GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \ 433 GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \ 434 GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \ 435 GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \ 436 GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \ 437 GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \ 438 GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \ 439 GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \ 440 GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \ 441 GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \ 442 GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \ 443 GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \ 444 GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \ 445 GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0 446 447 #define PINMUX_IPSR \ 448 \ 449 FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \ 450 FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \ 451 FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \ 452 FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \ 453 FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \ 454 FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \ 455 FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \ 456 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \ 457 \ 458 FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \ 459 FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \ 460 FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \ 461 FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 \ 462 FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \ 463 FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \ 464 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \ 465 FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \ 466 \ 467 FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \ 468 FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \ 469 FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \ 470 FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \ 471 FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \ 472 FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \ 473 FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \ 474 FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \ 475 \ 476 FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \ 477 FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \ 478 FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \ 479 FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \ 480 FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \ 481 FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \ 482 FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \ 483 FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \ 484 \ 485 FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 FM(IP18_3_0) IP18_3_0 \ 486 FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 FM(IP18_7_4) IP18_7_4 \ 487 FM(IP16_11_8) IP16_11_8 FM(IP17_11_8) IP17_11_8 \ 488 FM(IP16_15_12) IP16_15_12 FM(IP17_15_12) IP17_15_12 \ 489 FM(IP16_19_16) IP16_19_16 FM(IP17_19_16) IP17_19_16 \ 490 FM(IP16_23_20) IP16_23_20 FM(IP17_23_20) IP17_23_20 \ 491 FM(IP16_27_24) IP16_27_24 FM(IP17_27_24) IP17_27_24 \ 492 FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28 493 494 /* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ 495 #define MOD_SEL0_31_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3) FM(SEL_MSIOF3_4) F_(0, 0) F_(0, 0) F_(0, 0) 496 #define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3) 497 #define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0) 498 #define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1) 499 #define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1) 500 #define MOD_SEL0_21 FM(SEL_I2C2_0) FM(SEL_I2C2_1) 501 #define MOD_SEL0_20 FM(SEL_I2C1_0) FM(SEL_I2C1_1) 502 #define MOD_SEL0_19 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1) 503 #define MOD_SEL0_18_17 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3) 504 #define MOD_SEL0_16 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1) 505 #define MOD_SEL0_14_13 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) FM(SEL_HSCIF2_2) F_(0, 0) 506 #define MOD_SEL0_12 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1) 507 #define MOD_SEL0_11 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1) 508 #define MOD_SEL0_10 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1) 509 #define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0) 510 #define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0) 511 #define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1) 512 #define MOD_SEL0_4_3 FM(SEL_ADGA_0) FM(SEL_ADGA_1) FM(SEL_ADGA_2) FM(SEL_ADGA_3) 513 514 /* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ 515 #define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3) 516 #define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0) 517 #define MOD_SEL1_26 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1) 518 #define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3) 519 #define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0) 520 #define MOD_SEL1_20 FM(SEL_SSI1_0) FM(SEL_SSI1_1) 521 #define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1) 522 #define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3) 523 #define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1) 524 #define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0) 525 #define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1) 526 #define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1) 527 #define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1) 528 #define MOD_SEL1_10 FM(SEL_SCIF_0) FM(SEL_SCIF_1) 529 #define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1) 530 #define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1) 531 #define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1) 532 #define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1) 533 #define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1) 534 #define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1) 535 #define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1) 536 #define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1) 537 538 /* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ 539 #define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1) 540 #define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1) 541 #define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1) 542 #define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3) 543 #define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1) 544 #define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 545 #define MOD_SEL2_22 FM(SEL_NDF_0) FM(SEL_NDF_1) 546 #define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1) 547 #define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1) 548 #define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1) 549 #define MOD_SEL2_18 FM(SEL_ADGB_0) FM(SEL_ADGB_1) 550 #define MOD_SEL2_17 FM(SEL_ADGC_0) FM(SEL_ADGC_1) 551 #define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1) 552 553 #define PINMUX_MOD_SELS \ 554 \ 555 MOD_SEL0_31_30_29 MOD_SEL1_31_30 MOD_SEL2_31 \ 556 MOD_SEL2_30 \ 557 MOD_SEL1_29_28_27 MOD_SEL2_29 \ 558 MOD_SEL0_28_27 MOD_SEL2_28_27 \ 559 MOD_SEL0_26_25_24 MOD_SEL1_26 MOD_SEL2_26 \ 560 MOD_SEL1_25_24 MOD_SEL2_25_24_23 \ 561 MOD_SEL0_23 MOD_SEL1_23_22_21 \ 562 MOD_SEL0_22 MOD_SEL2_22 \ 563 MOD_SEL0_21 MOD_SEL2_21 \ 564 MOD_SEL0_20 MOD_SEL1_20 MOD_SEL2_20 \ 565 MOD_SEL0_19 MOD_SEL1_19 MOD_SEL2_19 \ 566 MOD_SEL0_18_17 MOD_SEL1_18_17 MOD_SEL2_18 \ 567 MOD_SEL2_17 \ 568 MOD_SEL0_16 MOD_SEL1_16 \ 569 MOD_SEL1_15_14 \ 570 MOD_SEL0_14_13 \ 571 MOD_SEL1_13 \ 572 MOD_SEL0_12 MOD_SEL1_12 \ 573 MOD_SEL0_11 MOD_SEL1_11 \ 574 MOD_SEL0_10 MOD_SEL1_10 \ 575 MOD_SEL0_9_8 MOD_SEL1_9 \ 576 MOD_SEL0_7_6 \ 577 MOD_SEL1_6 \ 578 MOD_SEL0_5 MOD_SEL1_5 \ 579 MOD_SEL0_4_3 MOD_SEL1_4 \ 580 MOD_SEL1_3 \ 581 MOD_SEL1_2 \ 582 MOD_SEL1_1 \ 583 MOD_SEL1_0 MOD_SEL2_0 584 585 /* 586 * These pins are not able to be muxed but have other properties 587 * that can be set, such as drive-strength or pull-up/pull-down enable. 588 */ 589 #define PINMUX_STATIC \ 590 FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \ 591 FM(QSPI0_IO2) FM(QSPI0_IO3) \ 592 FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \ 593 FM(QSPI1_IO2) FM(QSPI1_IO3) \ 594 FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \ 595 FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \ 596 FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \ 597 FM(AVB_TXCREFCLK) FM(AVB_MDIO) \ 598 FM(PRESETOUT) \ 599 FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) \ 600 FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR) 601 602 #define PINMUX_PHYS \ 603 FM(SCL0) FM(SDA0) FM(SCL3) FM(SDA3) FM(SCL5) FM(SDA5) 604 605 enum { 606 PINMUX_RESERVED = 0, 607 608 PINMUX_DATA_BEGIN, 609 GP_ALL(DATA), 610 PINMUX_DATA_END, 611 612 #define F_(x, y) 613 #define FM(x) FN_##x, 614 PINMUX_FUNCTION_BEGIN, 615 GP_ALL(FN), 616 PINMUX_GPSR 617 PINMUX_IPSR 618 PINMUX_MOD_SELS 619 PINMUX_FUNCTION_END, 620 #undef F_ 621 #undef FM 622 623 #define F_(x, y) 624 #define FM(x) x##_MARK, 625 PINMUX_MARK_BEGIN, 626 PINMUX_GPSR 627 PINMUX_IPSR 628 PINMUX_MOD_SELS 629 PINMUX_STATIC 630 PINMUX_PHYS 631 PINMUX_MARK_END, 632 #undef F_ 633 #undef FM 634 }; 635 636 static const u16 pinmux_data[] = { 637 PINMUX_DATA_GP_ALL(), 638 639 PINMUX_SINGLE(AVS1), 640 PINMUX_SINGLE(AVS2), 641 PINMUX_SINGLE(CLKOUT), 642 PINMUX_SINGLE(GP7_03), 643 PINMUX_SINGLE(GP7_02), 644 PINMUX_SINGLE(MSIOF0_RXD), 645 PINMUX_SINGLE(MSIOF0_SCK), 646 PINMUX_SINGLE(MSIOF0_TXD), 647 PINMUX_SINGLE(SSI_SCK5), 648 PINMUX_SINGLE(SSI_SDATA5), 649 PINMUX_SINGLE(SSI_WS5), 650 651 /* IPSR0 */ 652 PINMUX_IPSR_GPSR(IP0_3_0, AVB_MDC), 653 PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2), 654 655 PINMUX_IPSR_GPSR(IP0_7_4, AVB_MAGIC), 656 PINMUX_IPSR_MSEL(IP0_7_4, MSIOF2_SS1_C, SEL_MSIOF2_2), 657 PINMUX_IPSR_MSEL(IP0_7_4, SCK4_A, SEL_SCIF4_0), 658 659 PINMUX_IPSR_GPSR(IP0_11_8, AVB_PHY_INT), 660 PINMUX_IPSR_MSEL(IP0_11_8, MSIOF2_SYNC_C, SEL_MSIOF2_2), 661 PINMUX_IPSR_MSEL(IP0_11_8, RX4_A, SEL_SCIF4_0), 662 663 PINMUX_IPSR_GPSR(IP0_15_12, AVB_LINK), 664 PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2), 665 PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0), 666 667 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, I2C_SEL_5_0, SEL_ETHERAVB_0), 668 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, MSIOF2_RXD_C, I2C_SEL_5_0, SEL_MSIOF2_2), 669 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, CTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0), 670 PINMUX_IPSR_PHYS(IP0_19_16, SCL5, I2C_SEL_5_1), 671 672 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, I2C_SEL_5_0, SEL_ETHERAVB_0), 673 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C, I2C_SEL_5_0, SEL_MSIOF2_2), 674 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0), 675 PINMUX_IPSR_PHYS(IP0_23_20, SDA5, I2C_SEL_5_1), 676 677 PINMUX_IPSR_GPSR(IP0_27_24, IRQ0), 678 PINMUX_IPSR_GPSR(IP0_27_24, QPOLB), 679 PINMUX_IPSR_GPSR(IP0_27_24, DU_CDE), 680 PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1), 681 PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1), 682 PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_B, SEL_CANFD0_1), 683 PINMUX_IPSR_MSEL(IP0_27_24, MSIOF3_SS2_E, SEL_MSIOF3_4), 684 685 PINMUX_IPSR_GPSR(IP0_31_28, IRQ1), 686 PINMUX_IPSR_GPSR(IP0_31_28, QPOLA), 687 PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP), 688 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1), 689 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1), 690 PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1), 691 PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_SS1_E, SEL_MSIOF3_4), 692 693 /* IPSR1 */ 694 PINMUX_IPSR_GPSR(IP1_3_0, IRQ2), 695 PINMUX_IPSR_GPSR(IP1_3_0, QCPV_QDE), 696 PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE), 697 PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1), 698 PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1), 699 PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_SYNC_E, SEL_MSIOF3_4), 700 701 PINMUX_IPSR_GPSR(IP1_7_4, IRQ3), 702 PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE), 703 PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1), 704 PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1), 705 PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1), 706 PINMUX_IPSR_MSEL(IP1_7_4, MSIOF3_SCK_E, SEL_MSIOF3_4), 707 708 PINMUX_IPSR_GPSR(IP1_11_8, IRQ4), 709 PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS), 710 PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC), 711 PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1), 712 PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1), 713 PINMUX_IPSR_MSEL(IP1_11_8, MSIOF3_RXD_E, SEL_MSIOF3_4), 714 715 PINMUX_IPSR_GPSR(IP1_15_12, IRQ5), 716 PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE), 717 PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC), 718 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1), 719 PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1), 720 PINMUX_IPSR_MSEL(IP1_15_12, MSIOF3_TXD_E, SEL_MSIOF3_4), 721 722 PINMUX_IPSR_GPSR(IP1_19_16, PWM0), 723 PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS), 724 PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1), 725 PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1), 726 727 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, PWM1_A, I2C_SEL_3_0, SEL_PWM1_0), 728 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3), 729 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1), 730 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1), 731 PINMUX_IPSR_PHYS(IP1_23_20, SCL3, I2C_SEL_3_1), 732 733 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0), 734 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D, I2C_SEL_3_0, SEL_HSCIF3_3), 735 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, IETX_B, I2C_SEL_3_0, SEL_IEBUS_1), 736 PINMUX_IPSR_PHYS(IP1_27_24, SDA3, I2C_SEL_3_1), 737 738 PINMUX_IPSR_GPSR(IP1_31_28, A0), 739 PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16), 740 PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SYNC_B, SEL_MSIOF3_1), 741 PINMUX_IPSR_GPSR(IP1_31_28, VI4_DATA8), 742 PINMUX_IPSR_GPSR(IP1_31_28, DU_DB0), 743 PINMUX_IPSR_MSEL(IP1_31_28, PWM3_A, SEL_PWM3_0), 744 745 /* IPSR2 */ 746 PINMUX_IPSR_GPSR(IP2_3_0, A1), 747 PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT17), 748 PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_TXD_B, SEL_MSIOF3_1), 749 PINMUX_IPSR_GPSR(IP2_3_0, VI4_DATA9), 750 PINMUX_IPSR_GPSR(IP2_3_0, DU_DB1), 751 PINMUX_IPSR_MSEL(IP2_3_0, PWM4_A, SEL_PWM4_0), 752 753 PINMUX_IPSR_GPSR(IP2_7_4, A2), 754 PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT18), 755 PINMUX_IPSR_MSEL(IP2_7_4, MSIOF3_SCK_B, SEL_MSIOF3_1), 756 PINMUX_IPSR_GPSR(IP2_7_4, VI4_DATA10), 757 PINMUX_IPSR_GPSR(IP2_7_4, DU_DB2), 758 PINMUX_IPSR_MSEL(IP2_7_4, PWM5_A, SEL_PWM5_0), 759 760 PINMUX_IPSR_GPSR(IP2_11_8, A3), 761 PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT19), 762 PINMUX_IPSR_MSEL(IP2_11_8, MSIOF3_RXD_B, SEL_MSIOF3_1), 763 PINMUX_IPSR_GPSR(IP2_11_8, VI4_DATA11), 764 PINMUX_IPSR_GPSR(IP2_11_8, DU_DB3), 765 PINMUX_IPSR_MSEL(IP2_11_8, PWM6_A, SEL_PWM6_0), 766 767 PINMUX_IPSR_GPSR(IP2_15_12, A4), 768 PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT20), 769 PINMUX_IPSR_MSEL(IP2_15_12, MSIOF3_SS1_B, SEL_MSIOF3_1), 770 PINMUX_IPSR_GPSR(IP2_15_12, VI4_DATA12), 771 PINMUX_IPSR_GPSR(IP2_15_12, VI5_DATA12), 772 PINMUX_IPSR_GPSR(IP2_15_12, DU_DB4), 773 774 PINMUX_IPSR_GPSR(IP2_19_16, A5), 775 PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT21), 776 PINMUX_IPSR_MSEL(IP2_19_16, MSIOF3_SS2_B, SEL_MSIOF3_1), 777 PINMUX_IPSR_MSEL(IP2_19_16, SCK4_B, SEL_SCIF4_1), 778 PINMUX_IPSR_GPSR(IP2_19_16, VI4_DATA13), 779 PINMUX_IPSR_GPSR(IP2_19_16, VI5_DATA13), 780 PINMUX_IPSR_GPSR(IP2_19_16, DU_DB5), 781 782 PINMUX_IPSR_GPSR(IP2_23_20, A6), 783 PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT22), 784 PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_SS1_A, SEL_MSIOF2_0), 785 PINMUX_IPSR_MSEL(IP2_23_20, RX4_B, SEL_SCIF4_1), 786 PINMUX_IPSR_GPSR(IP2_23_20, VI4_DATA14), 787 PINMUX_IPSR_GPSR(IP2_23_20, VI5_DATA14), 788 PINMUX_IPSR_GPSR(IP2_23_20, DU_DB6), 789 790 PINMUX_IPSR_GPSR(IP2_27_24, A7), 791 PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT23), 792 PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SS2_A, SEL_MSIOF2_0), 793 PINMUX_IPSR_MSEL(IP2_27_24, TX4_B, SEL_SCIF4_1), 794 PINMUX_IPSR_GPSR(IP2_27_24, VI4_DATA15), 795 PINMUX_IPSR_GPSR(IP2_27_24, VI5_DATA15), 796 PINMUX_IPSR_GPSR(IP2_27_24, DU_DB7), 797 798 PINMUX_IPSR_GPSR(IP2_31_28, A8), 799 PINMUX_IPSR_MSEL(IP2_31_28, RX3_B, SEL_SCIF3_1), 800 PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0), 801 PINMUX_IPSR_MSEL(IP2_31_28, HRX4_B, SEL_HSCIF4_1), 802 PINMUX_IPSR_MSEL(IP2_31_28, SDA6_A, SEL_I2C6_0), 803 PINMUX_IPSR_MSEL(IP2_31_28, AVB_AVTP_MATCH_B, SEL_ETHERAVB_1), 804 PINMUX_IPSR_MSEL(IP2_31_28, PWM1_B, SEL_PWM1_1), 805 806 /* IPSR3 */ 807 PINMUX_IPSR_GPSR(IP3_3_0, A9), 808 PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0), 809 PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1), 810 PINMUX_IPSR_GPSR(IP3_3_0, VI5_VSYNC_N), 811 812 PINMUX_IPSR_GPSR(IP3_7_4, A10), 813 PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0), 814 PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_B, SEL_SCIF4_1), 815 PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N), 816 817 PINMUX_IPSR_GPSR(IP3_11_8, A11), 818 PINMUX_IPSR_MSEL(IP3_11_8, TX3_B, SEL_SCIF3_1), 819 PINMUX_IPSR_MSEL(IP3_11_8, MSIOF2_TXD_A, SEL_MSIOF2_0), 820 PINMUX_IPSR_MSEL(IP3_11_8, HTX4_B, SEL_HSCIF4_1), 821 PINMUX_IPSR_GPSR(IP3_11_8, HSCK4), 822 PINMUX_IPSR_GPSR(IP3_11_8, VI5_FIELD), 823 PINMUX_IPSR_MSEL(IP3_11_8, SCL6_A, SEL_I2C6_0), 824 PINMUX_IPSR_MSEL(IP3_11_8, AVB_AVTP_CAPTURE_B, SEL_ETHERAVB_1), 825 PINMUX_IPSR_MSEL(IP3_11_8, PWM2_B, SEL_PWM2_1), 826 827 PINMUX_IPSR_GPSR(IP3_15_12, A12), 828 PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT12), 829 PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SCK_C, SEL_MSIOF3_2), 830 PINMUX_IPSR_MSEL(IP3_15_12, HRX4_A, SEL_HSCIF4_0), 831 PINMUX_IPSR_GPSR(IP3_15_12, VI5_DATA8), 832 PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4), 833 834 PINMUX_IPSR_GPSR(IP3_19_16, A13), 835 PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT13), 836 PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SYNC_C, SEL_MSIOF3_2), 837 PINMUX_IPSR_MSEL(IP3_19_16, HTX4_A, SEL_HSCIF4_0), 838 PINMUX_IPSR_GPSR(IP3_19_16, VI5_DATA9), 839 PINMUX_IPSR_GPSR(IP3_19_16, DU_DG5), 840 841 PINMUX_IPSR_GPSR(IP3_23_20, A14), 842 PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT14), 843 PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_C, SEL_MSIOF3_2), 844 PINMUX_IPSR_GPSR(IP3_23_20, HCTS4_N), 845 PINMUX_IPSR_GPSR(IP3_23_20, VI5_DATA10), 846 PINMUX_IPSR_GPSR(IP3_23_20, DU_DG6), 847 848 PINMUX_IPSR_GPSR(IP3_27_24, A15), 849 PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT15), 850 PINMUX_IPSR_MSEL(IP3_27_24, MSIOF3_TXD_C, SEL_MSIOF3_2), 851 PINMUX_IPSR_GPSR(IP3_27_24, HRTS4_N), 852 PINMUX_IPSR_GPSR(IP3_27_24, VI5_DATA11), 853 PINMUX_IPSR_GPSR(IP3_27_24, DU_DG7), 854 855 PINMUX_IPSR_GPSR(IP3_31_28, A16), 856 PINMUX_IPSR_GPSR(IP3_31_28, LCDOUT8), 857 PINMUX_IPSR_GPSR(IP3_31_28, VI4_FIELD), 858 PINMUX_IPSR_GPSR(IP3_31_28, DU_DG0), 859 860 /* IPSR4 */ 861 PINMUX_IPSR_GPSR(IP4_3_0, A17), 862 PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT9), 863 PINMUX_IPSR_GPSR(IP4_3_0, VI4_VSYNC_N), 864 PINMUX_IPSR_GPSR(IP4_3_0, DU_DG1), 865 866 PINMUX_IPSR_GPSR(IP4_7_4, A18), 867 PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT10), 868 PINMUX_IPSR_GPSR(IP4_7_4, VI4_HSYNC_N), 869 PINMUX_IPSR_GPSR(IP4_7_4, DU_DG2), 870 871 PINMUX_IPSR_GPSR(IP4_11_8, A19), 872 PINMUX_IPSR_GPSR(IP4_11_8, LCDOUT11), 873 PINMUX_IPSR_GPSR(IP4_11_8, VI4_CLKENB), 874 PINMUX_IPSR_GPSR(IP4_11_8, DU_DG3), 875 876 PINMUX_IPSR_GPSR(IP4_15_12, CS0_N), 877 PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB), 878 879 PINMUX_IPSR_GPSR(IP4_19_16, CS1_N), 880 PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK), 881 PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1), 882 883 PINMUX_IPSR_GPSR(IP4_23_20, BS_N), 884 PINMUX_IPSR_GPSR(IP4_23_20, QSTVA_QVS), 885 PINMUX_IPSR_MSEL(IP4_23_20, MSIOF3_SCK_D, SEL_MSIOF3_3), 886 PINMUX_IPSR_GPSR(IP4_23_20, SCK3), 887 PINMUX_IPSR_GPSR(IP4_23_20, HSCK3), 888 PINMUX_IPSR_GPSR(IP4_23_20, CAN1_TX), 889 PINMUX_IPSR_GPSR(IP4_23_20, CANFD1_TX), 890 PINMUX_IPSR_MSEL(IP4_23_20, IETX_A, SEL_IEBUS_0), 891 892 PINMUX_IPSR_GPSR(IP4_27_24, RD_N), 893 PINMUX_IPSR_MSEL(IP4_27_24, MSIOF3_SYNC_D, SEL_MSIOF3_3), 894 PINMUX_IPSR_MSEL(IP4_27_24, RX3_A, SEL_SCIF3_0), 895 PINMUX_IPSR_MSEL(IP4_27_24, HRX3_A, SEL_HSCIF3_0), 896 PINMUX_IPSR_MSEL(IP4_27_24, CAN0_TX_A, SEL_RCAN0_0), 897 PINMUX_IPSR_MSEL(IP4_27_24, CANFD0_TX_A, SEL_CANFD0_0), 898 899 PINMUX_IPSR_GPSR(IP4_31_28, RD_WR_N), 900 PINMUX_IPSR_MSEL(IP4_31_28, MSIOF3_RXD_D, SEL_MSIOF3_3), 901 PINMUX_IPSR_MSEL(IP4_31_28, TX3_A, SEL_SCIF3_0), 902 PINMUX_IPSR_MSEL(IP4_31_28, HTX3_A, SEL_HSCIF3_0), 903 PINMUX_IPSR_MSEL(IP4_31_28, CAN0_RX_A, SEL_RCAN0_0), 904 PINMUX_IPSR_MSEL(IP4_31_28, CANFD0_RX_A, SEL_CANFD0_0), 905 906 /* IPSR5 */ 907 PINMUX_IPSR_GPSR(IP5_3_0, WE0_N), 908 PINMUX_IPSR_MSEL(IP5_3_0, MSIOF3_TXD_D, SEL_MSIOF3_3), 909 PINMUX_IPSR_GPSR(IP5_3_0, CTS3_N), 910 PINMUX_IPSR_GPSR(IP5_3_0, HCTS3_N), 911 PINMUX_IPSR_MSEL(IP5_3_0, SCL6_B, SEL_I2C6_1), 912 PINMUX_IPSR_GPSR(IP5_3_0, CAN_CLK), 913 PINMUX_IPSR_MSEL(IP5_3_0, IECLK_A, SEL_IEBUS_0), 914 915 PINMUX_IPSR_GPSR(IP5_7_4, WE1_N), 916 PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3), 917 PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N), 918 PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N), 919 PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1), 920 PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX), 921 PINMUX_IPSR_GPSR(IP5_7_4, CANFD1_RX), 922 PINMUX_IPSR_MSEL(IP5_7_4, IERX_A, SEL_IEBUS_0), 923 924 PINMUX_IPSR_MSEL(IP5_11_8, EX_WAIT0_A, SEL_LBSC_0), 925 PINMUX_IPSR_GPSR(IP5_11_8, QCLK), 926 PINMUX_IPSR_GPSR(IP5_11_8, VI4_CLK), 927 PINMUX_IPSR_GPSR(IP5_11_8, DU_DOTCLKOUT0), 928 929 PINMUX_IPSR_GPSR(IP5_15_12, D0), 930 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF2_SS1_B, SEL_MSIOF2_1), 931 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF3_SCK_A, SEL_MSIOF3_0), 932 PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA16), 933 PINMUX_IPSR_GPSR(IP5_15_12, VI5_DATA0), 934 935 PINMUX_IPSR_GPSR(IP5_19_16, D1), 936 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF2_SS2_B, SEL_MSIOF2_1), 937 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF3_SYNC_A, SEL_MSIOF3_0), 938 PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA17), 939 PINMUX_IPSR_GPSR(IP5_19_16, VI5_DATA1), 940 941 PINMUX_IPSR_GPSR(IP5_23_20, D2), 942 PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_RXD_A, SEL_MSIOF3_0), 943 PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA18), 944 PINMUX_IPSR_GPSR(IP5_23_20, VI5_DATA2), 945 946 PINMUX_IPSR_GPSR(IP5_27_24, D3), 947 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0), 948 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19), 949 PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3), 950 951 PINMUX_IPSR_GPSR(IP5_31_28, D4), 952 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF2_SCK_B, SEL_MSIOF2_1), 953 PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA20), 954 PINMUX_IPSR_GPSR(IP5_31_28, VI5_DATA4), 955 956 /* IPSR6 */ 957 PINMUX_IPSR_GPSR(IP6_3_0, D5), 958 PINMUX_IPSR_MSEL(IP6_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1), 959 PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA21), 960 PINMUX_IPSR_GPSR(IP6_3_0, VI5_DATA5), 961 962 PINMUX_IPSR_GPSR(IP6_7_4, D6), 963 PINMUX_IPSR_MSEL(IP6_7_4, MSIOF2_RXD_B, SEL_MSIOF2_1), 964 PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA22), 965 PINMUX_IPSR_GPSR(IP6_7_4, VI5_DATA6), 966 967 PINMUX_IPSR_GPSR(IP6_11_8, D7), 968 PINMUX_IPSR_MSEL(IP6_11_8, MSIOF2_TXD_B, SEL_MSIOF2_1), 969 PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA23), 970 PINMUX_IPSR_GPSR(IP6_11_8, VI5_DATA7), 971 972 PINMUX_IPSR_GPSR(IP6_15_12, D8), 973 PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT0), 974 PINMUX_IPSR_MSEL(IP6_15_12, MSIOF2_SCK_D, SEL_MSIOF2_3), 975 PINMUX_IPSR_MSEL(IP6_15_12, SCK4_C, SEL_SCIF4_2), 976 PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA0_A, SEL_VIN4_0), 977 PINMUX_IPSR_GPSR(IP6_15_12, DU_DR0), 978 979 PINMUX_IPSR_GPSR(IP6_19_16, D9), 980 PINMUX_IPSR_GPSR(IP6_19_16, LCDOUT1), 981 PINMUX_IPSR_MSEL(IP6_19_16, MSIOF2_SYNC_D, SEL_MSIOF2_3), 982 PINMUX_IPSR_MSEL(IP6_19_16, VI4_DATA1_A, SEL_VIN4_0), 983 PINMUX_IPSR_GPSR(IP6_19_16, DU_DR1), 984 985 PINMUX_IPSR_GPSR(IP6_23_20, D10), 986 PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT2), 987 PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_RXD_D, SEL_MSIOF2_3), 988 PINMUX_IPSR_MSEL(IP6_23_20, HRX3_B, SEL_HSCIF3_1), 989 PINMUX_IPSR_MSEL(IP6_23_20, VI4_DATA2_A, SEL_VIN4_0), 990 PINMUX_IPSR_MSEL(IP6_23_20, CTS4_N_C, SEL_SCIF4_2), 991 PINMUX_IPSR_GPSR(IP6_23_20, DU_DR2), 992 993 PINMUX_IPSR_GPSR(IP6_27_24, D11), 994 PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT3), 995 PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3), 996 PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1), 997 PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0), 998 PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_C, SEL_SCIF4_2), 999 PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3), 1000 1001 PINMUX_IPSR_GPSR(IP6_31_28, D12), 1002 PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT4), 1003 PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3), 1004 PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2), 1005 PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0), 1006 PINMUX_IPSR_GPSR(IP6_31_28, DU_DR4), 1007 1008 /* IPSR7 */ 1009 PINMUX_IPSR_GPSR(IP7_3_0, D13), 1010 PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT5), 1011 PINMUX_IPSR_MSEL(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3), 1012 PINMUX_IPSR_MSEL(IP7_3_0, TX4_C, SEL_SCIF4_2), 1013 PINMUX_IPSR_MSEL(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0), 1014 PINMUX_IPSR_GPSR(IP7_3_0, DU_DR5), 1015 1016 PINMUX_IPSR_GPSR(IP7_7_4, D14), 1017 PINMUX_IPSR_GPSR(IP7_7_4, LCDOUT6), 1018 PINMUX_IPSR_MSEL(IP7_7_4, MSIOF3_SS1_A, SEL_MSIOF3_0), 1019 PINMUX_IPSR_MSEL(IP7_7_4, HRX3_C, SEL_HSCIF3_2), 1020 PINMUX_IPSR_MSEL(IP7_7_4, VI4_DATA6_A, SEL_VIN4_0), 1021 PINMUX_IPSR_GPSR(IP7_7_4, DU_DR6), 1022 PINMUX_IPSR_MSEL(IP7_7_4, SCL6_C, SEL_I2C6_2), 1023 1024 PINMUX_IPSR_GPSR(IP7_11_8, D15), 1025 PINMUX_IPSR_GPSR(IP7_11_8, LCDOUT7), 1026 PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SS2_A, SEL_MSIOF3_0), 1027 PINMUX_IPSR_MSEL(IP7_11_8, HTX3_C, SEL_HSCIF3_2), 1028 PINMUX_IPSR_MSEL(IP7_11_8, VI4_DATA7_A, SEL_VIN4_0), 1029 PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7), 1030 PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2), 1031 1032 PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK), 1033 PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4), 1034 PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1), 1035 1036 PINMUX_IPSR_GPSR(IP7_23_20, SD0_CMD), 1037 PINMUX_IPSR_MSEL(IP7_23_20, MSIOF1_SYNC_E, SEL_MSIOF1_4), 1038 PINMUX_IPSR_MSEL(IP7_23_20, STP_IVCXO27_0_B, SEL_SSP1_0_1), 1039 1040 PINMUX_IPSR_GPSR(IP7_27_24, SD0_DAT0), 1041 PINMUX_IPSR_MSEL(IP7_27_24, MSIOF1_RXD_E, SEL_MSIOF1_4), 1042 PINMUX_IPSR_MSEL(IP7_27_24, TS_SCK0_B, SEL_TSIF0_1), 1043 PINMUX_IPSR_MSEL(IP7_27_24, STP_ISCLK_0_B, SEL_SSP1_0_1), 1044 1045 PINMUX_IPSR_GPSR(IP7_31_28, SD0_DAT1), 1046 PINMUX_IPSR_MSEL(IP7_31_28, MSIOF1_TXD_E, SEL_MSIOF1_4), 1047 PINMUX_IPSR_MSEL(IP7_31_28, TS_SPSYNC0_B, SEL_TSIF0_1), 1048 PINMUX_IPSR_MSEL(IP7_31_28, STP_ISSYNC_0_B, SEL_SSP1_0_1), 1049 1050 /* IPSR8 */ 1051 PINMUX_IPSR_GPSR(IP8_3_0, SD0_DAT2), 1052 PINMUX_IPSR_MSEL(IP8_3_0, MSIOF1_SS1_E, SEL_MSIOF1_4), 1053 PINMUX_IPSR_MSEL(IP8_3_0, TS_SDAT0_B, SEL_TSIF0_1), 1054 PINMUX_IPSR_MSEL(IP8_3_0, STP_ISD_0_B, SEL_SSP1_0_1), 1055 1056 PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT3), 1057 PINMUX_IPSR_MSEL(IP8_7_4, MSIOF1_SS2_E, SEL_MSIOF1_4), 1058 PINMUX_IPSR_MSEL(IP8_7_4, TS_SDEN0_B, SEL_TSIF0_1), 1059 PINMUX_IPSR_MSEL(IP8_7_4, STP_ISEN_0_B, SEL_SSP1_0_1), 1060 1061 PINMUX_IPSR_GPSR(IP8_11_8, SD1_CLK), 1062 PINMUX_IPSR_MSEL(IP8_11_8, MSIOF1_SCK_G, SEL_MSIOF1_6), 1063 PINMUX_IPSR_MSEL(IP8_11_8, SIM0_CLK_A, SEL_SIMCARD_0), 1064 1065 PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD), 1066 PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6), 1067 PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDF_1), 1068 PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0), 1069 PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1), 1070 1071 PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0), 1072 PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4), 1073 PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6), 1074 PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDF_1), 1075 PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1), 1076 PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1), 1077 1078 PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1), 1079 PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5), 1080 PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6), 1081 PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDF_1), 1082 PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1), 1083 PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1), 1084 1085 PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2), 1086 PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6), 1087 PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6), 1088 PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDF_1), 1089 PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1), 1090 PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1), 1091 1092 PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3), 1093 PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7), 1094 PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6), 1095 PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDF_1), 1096 PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1), 1097 PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1), 1098 1099 /* IPSR9 */ 1100 PINMUX_IPSR_GPSR(IP9_3_0, SD2_CLK), 1101 PINMUX_IPSR_GPSR(IP9_3_0, NFDATA8), 1102 1103 PINMUX_IPSR_GPSR(IP9_7_4, SD2_CMD), 1104 PINMUX_IPSR_GPSR(IP9_7_4, NFDATA9), 1105 1106 PINMUX_IPSR_GPSR(IP9_11_8, SD2_DAT0), 1107 PINMUX_IPSR_GPSR(IP9_11_8, NFDATA10), 1108 1109 PINMUX_IPSR_GPSR(IP9_15_12, SD2_DAT1), 1110 PINMUX_IPSR_GPSR(IP9_15_12, NFDATA11), 1111 1112 PINMUX_IPSR_GPSR(IP9_19_16, SD2_DAT2), 1113 PINMUX_IPSR_GPSR(IP9_19_16, NFDATA12), 1114 1115 PINMUX_IPSR_GPSR(IP9_23_20, SD2_DAT3), 1116 PINMUX_IPSR_GPSR(IP9_23_20, NFDATA13), 1117 1118 PINMUX_IPSR_GPSR(IP9_27_24, SD2_DS), 1119 PINMUX_IPSR_GPSR(IP9_27_24, NFALE), 1120 1121 PINMUX_IPSR_GPSR(IP9_31_28, SD3_CLK), 1122 PINMUX_IPSR_GPSR(IP9_31_28, NFWE_N), 1123 1124 /* IPSR10 */ 1125 PINMUX_IPSR_GPSR(IP10_3_0, SD3_CMD), 1126 PINMUX_IPSR_GPSR(IP10_3_0, NFRE_N), 1127 1128 PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT0), 1129 PINMUX_IPSR_GPSR(IP10_7_4, NFDATA0), 1130 1131 PINMUX_IPSR_GPSR(IP10_11_8, SD3_DAT1), 1132 PINMUX_IPSR_GPSR(IP10_11_8, NFDATA1), 1133 1134 PINMUX_IPSR_GPSR(IP10_15_12, SD3_DAT2), 1135 PINMUX_IPSR_GPSR(IP10_15_12, NFDATA2), 1136 1137 PINMUX_IPSR_GPSR(IP10_19_16, SD3_DAT3), 1138 PINMUX_IPSR_GPSR(IP10_19_16, NFDATA3), 1139 1140 PINMUX_IPSR_GPSR(IP10_23_20, SD3_DAT4), 1141 PINMUX_IPSR_MSEL(IP10_23_20, SD2_CD_A, SEL_SDHI2_0), 1142 PINMUX_IPSR_GPSR(IP10_23_20, NFDATA4), 1143 1144 PINMUX_IPSR_GPSR(IP10_27_24, SD3_DAT5), 1145 PINMUX_IPSR_MSEL(IP10_27_24, SD2_WP_A, SEL_SDHI2_0), 1146 PINMUX_IPSR_GPSR(IP10_27_24, NFDATA5), 1147 1148 PINMUX_IPSR_GPSR(IP10_31_28, SD3_DAT6), 1149 PINMUX_IPSR_GPSR(IP10_31_28, SD3_CD), 1150 PINMUX_IPSR_GPSR(IP10_31_28, NFDATA6), 1151 1152 /* IPSR11 */ 1153 PINMUX_IPSR_GPSR(IP11_3_0, SD3_DAT7), 1154 PINMUX_IPSR_GPSR(IP11_3_0, SD3_WP), 1155 PINMUX_IPSR_GPSR(IP11_3_0, NFDATA7), 1156 1157 PINMUX_IPSR_GPSR(IP11_7_4, SD3_DS), 1158 PINMUX_IPSR_GPSR(IP11_7_4, NFCLE), 1159 1160 PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD), 1161 PINMUX_IPSR_MSEL(IP11_11_8, NFDATA14_A, SEL_NDF_0), 1162 PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1), 1163 PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0), 1164 1165 PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP), 1166 PINMUX_IPSR_MSEL(IP11_15_12, NFDATA15_A, SEL_NDF_0), 1167 PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1), 1168 1169 PINMUX_IPSR_MSEL(IP11_19_16, SD1_CD, I2C_SEL_0_0), 1170 PINMUX_IPSR_PHYS_MSEL(IP11_19_16, NFRB_N_A, I2C_SEL_0_0, SEL_NDF_0), 1171 PINMUX_IPSR_PHYS_MSEL(IP11_19_16, SIM0_CLK_B, I2C_SEL_0_0, SEL_SIMCARD_1), 1172 PINMUX_IPSR_PHYS(IP11_19_16, SCL0, I2C_SEL_0_1), 1173 1174 PINMUX_IPSR_MSEL(IP11_23_20, SD1_WP, I2C_SEL_0_0), 1175 PINMUX_IPSR_PHYS_MSEL(IP11_23_20, NFCE_N_A, I2C_SEL_0_0, SEL_NDF_0), 1176 PINMUX_IPSR_PHYS_MSEL(IP11_23_20, SIM0_D_B, I2C_SEL_0_0, SEL_SIMCARD_1), 1177 PINMUX_IPSR_PHYS(IP11_23_20, SDA0, I2C_SEL_0_1), 1178 1179 PINMUX_IPSR_GPSR(IP11_27_24, SCK0), 1180 PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1), 1181 PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1), 1182 PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADGC_1), 1183 PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0), 1184 PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1), 1185 PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2), 1186 PINMUX_IPSR_MSEL(IP11_27_24, RIF0_CLK_B, SEL_DRIF0_1), 1187 PINMUX_IPSR_GPSR(IP11_27_24, ADICHS2), 1188 PINMUX_IPSR_MSEL(IP11_27_24, SCK5_B, SEL_SCIF5_1), 1189 1190 PINMUX_IPSR_GPSR(IP11_31_28, RX0), 1191 PINMUX_IPSR_MSEL(IP11_31_28, HRX1_B, SEL_HSCIF1_1), 1192 PINMUX_IPSR_MSEL(IP11_31_28, TS_SCK0_C, SEL_TSIF0_2), 1193 PINMUX_IPSR_MSEL(IP11_31_28, STP_ISCLK_0_C, SEL_SSP1_0_2), 1194 PINMUX_IPSR_MSEL(IP11_31_28, RIF0_D0_B, SEL_DRIF0_1), 1195 1196 /* IPSR12 */ 1197 PINMUX_IPSR_GPSR(IP12_3_0, TX0), 1198 PINMUX_IPSR_MSEL(IP12_3_0, HTX1_B, SEL_HSCIF1_1), 1199 PINMUX_IPSR_MSEL(IP12_3_0, TS_SPSYNC0_C, SEL_TSIF0_2), 1200 PINMUX_IPSR_MSEL(IP12_3_0, STP_ISSYNC_0_C, SEL_SSP1_0_2), 1201 PINMUX_IPSR_MSEL(IP12_3_0, RIF0_D1_B, SEL_DRIF0_1), 1202 1203 PINMUX_IPSR_GPSR(IP12_7_4, CTS0_N), 1204 PINMUX_IPSR_MSEL(IP12_7_4, HCTS1_N_B, SEL_HSCIF1_1), 1205 PINMUX_IPSR_MSEL(IP12_7_4, MSIOF1_SYNC_B, SEL_MSIOF1_1), 1206 PINMUX_IPSR_MSEL(IP12_7_4, TS_SPSYNC1_C, SEL_TSIF1_2), 1207 PINMUX_IPSR_MSEL(IP12_7_4, STP_ISSYNC_1_C, SEL_SSP1_1_2), 1208 PINMUX_IPSR_MSEL(IP12_7_4, RIF1_SYNC_B, SEL_DRIF1_1), 1209 PINMUX_IPSR_GPSR(IP12_7_4, AUDIO_CLKOUT_C), 1210 PINMUX_IPSR_GPSR(IP12_7_4, ADICS_SAMP), 1211 1212 PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N), 1213 PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1), 1214 PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1), 1215 PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADGA_1), 1216 PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0), 1217 PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2), 1218 PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1), 1219 PINMUX_IPSR_GPSR(IP12_11_8, ADICHS1), 1220 1221 PINMUX_IPSR_MSEL(IP12_15_12, RX1_A, SEL_SCIF1_0), 1222 PINMUX_IPSR_MSEL(IP12_15_12, HRX1_A, SEL_HSCIF1_0), 1223 PINMUX_IPSR_MSEL(IP12_15_12, TS_SDAT0_C, SEL_TSIF0_2), 1224 PINMUX_IPSR_MSEL(IP12_15_12, STP_ISD_0_C, SEL_SSP1_0_2), 1225 PINMUX_IPSR_MSEL(IP12_15_12, RIF1_CLK_C, SEL_DRIF1_2), 1226 1227 PINMUX_IPSR_MSEL(IP12_19_16, TX1_A, SEL_SCIF1_0), 1228 PINMUX_IPSR_MSEL(IP12_19_16, HTX1_A, SEL_HSCIF1_0), 1229 PINMUX_IPSR_MSEL(IP12_19_16, TS_SDEN0_C, SEL_TSIF0_2), 1230 PINMUX_IPSR_MSEL(IP12_19_16, STP_ISEN_0_C, SEL_SSP1_0_2), 1231 PINMUX_IPSR_MSEL(IP12_19_16, RIF1_D0_C, SEL_DRIF1_2), 1232 1233 PINMUX_IPSR_GPSR(IP12_23_20, CTS1_N), 1234 PINMUX_IPSR_MSEL(IP12_23_20, HCTS1_N_A, SEL_HSCIF1_0), 1235 PINMUX_IPSR_MSEL(IP12_23_20, MSIOF1_RXD_B, SEL_MSIOF1_1), 1236 PINMUX_IPSR_MSEL(IP12_23_20, TS_SDEN1_C, SEL_TSIF1_2), 1237 PINMUX_IPSR_MSEL(IP12_23_20, STP_ISEN_1_C, SEL_SSP1_1_2), 1238 PINMUX_IPSR_MSEL(IP12_23_20, RIF1_D0_B, SEL_DRIF1_1), 1239 PINMUX_IPSR_GPSR(IP12_23_20, ADIDATA), 1240 1241 PINMUX_IPSR_GPSR(IP12_27_24, RTS1_N), 1242 PINMUX_IPSR_MSEL(IP12_27_24, HRTS1_N_A, SEL_HSCIF1_0), 1243 PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1), 1244 PINMUX_IPSR_MSEL(IP12_27_24, TS_SDAT1_C, SEL_TSIF1_2), 1245 PINMUX_IPSR_MSEL(IP12_27_24, STP_ISD_1_C, SEL_SSP1_1_2), 1246 PINMUX_IPSR_MSEL(IP12_27_24, RIF1_D1_B, SEL_DRIF1_1), 1247 PINMUX_IPSR_GPSR(IP12_27_24, ADICHS0), 1248 1249 PINMUX_IPSR_GPSR(IP12_31_28, SCK2), 1250 PINMUX_IPSR_MSEL(IP12_31_28, SCIF_CLK_B, SEL_SCIF_1), 1251 PINMUX_IPSR_MSEL(IP12_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1), 1252 PINMUX_IPSR_MSEL(IP12_31_28, TS_SCK1_C, SEL_TSIF1_2), 1253 PINMUX_IPSR_MSEL(IP12_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2), 1254 PINMUX_IPSR_MSEL(IP12_31_28, RIF1_CLK_B, SEL_DRIF1_1), 1255 PINMUX_IPSR_GPSR(IP12_31_28, ADICLK), 1256 1257 /* IPSR13 */ 1258 PINMUX_IPSR_MSEL(IP13_3_0, TX2_A, SEL_SCIF2_0), 1259 PINMUX_IPSR_MSEL(IP13_3_0, SD2_CD_B, SEL_SDHI2_1), 1260 PINMUX_IPSR_MSEL(IP13_3_0, SCL1_A, SEL_I2C1_0), 1261 PINMUX_IPSR_MSEL(IP13_3_0, FMCLK_A, SEL_FM_0), 1262 PINMUX_IPSR_MSEL(IP13_3_0, RIF1_D1_C, SEL_DRIF1_2), 1263 PINMUX_IPSR_GPSR(IP13_3_0, FSO_CFE_0_N), 1264 1265 PINMUX_IPSR_MSEL(IP13_7_4, RX2_A, SEL_SCIF2_0), 1266 PINMUX_IPSR_MSEL(IP13_7_4, SD2_WP_B, SEL_SDHI2_1), 1267 PINMUX_IPSR_MSEL(IP13_7_4, SDA1_A, SEL_I2C1_0), 1268 PINMUX_IPSR_MSEL(IP13_7_4, FMIN_A, SEL_FM_0), 1269 PINMUX_IPSR_MSEL(IP13_7_4, RIF1_SYNC_C, SEL_DRIF1_2), 1270 PINMUX_IPSR_GPSR(IP13_7_4, FSO_CFE_1_N), 1271 1272 PINMUX_IPSR_GPSR(IP13_11_8, HSCK0), 1273 PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3), 1274 PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADGB_0), 1275 PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI1_1), 1276 PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3), 1277 PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3), 1278 PINMUX_IPSR_MSEL(IP13_11_8, RIF0_CLK_C, SEL_DRIF0_2), 1279 PINMUX_IPSR_MSEL(IP13_11_8, RX5_B, SEL_SCIF5_1), 1280 1281 PINMUX_IPSR_GPSR(IP13_15_12, HRX0), 1282 PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3), 1283 PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA2_B, SEL_SSI2_1), 1284 PINMUX_IPSR_MSEL(IP13_15_12, TS_SDEN0_D, SEL_TSIF0_3), 1285 PINMUX_IPSR_MSEL(IP13_15_12, STP_ISEN_0_D, SEL_SSP1_0_3), 1286 PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_C, SEL_DRIF0_2), 1287 1288 PINMUX_IPSR_GPSR(IP13_19_16, HTX0), 1289 PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3), 1290 PINMUX_IPSR_MSEL(IP13_19_16, SSI_SDATA9_B, SEL_SSI9_1), 1291 PINMUX_IPSR_MSEL(IP13_19_16, TS_SDAT0_D, SEL_TSIF0_3), 1292 PINMUX_IPSR_MSEL(IP13_19_16, STP_ISD_0_D, SEL_SSP1_0_3), 1293 PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_C, SEL_DRIF0_2), 1294 1295 PINMUX_IPSR_GPSR(IP13_23_20, HCTS0_N), 1296 PINMUX_IPSR_MSEL(IP13_23_20, RX2_B, SEL_SCIF2_1), 1297 PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3), 1298 PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK9_A, SEL_SSI9_0), 1299 PINMUX_IPSR_MSEL(IP13_23_20, TS_SPSYNC0_D, SEL_TSIF0_3), 1300 PINMUX_IPSR_MSEL(IP13_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3), 1301 PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_C, SEL_DRIF0_2), 1302 PINMUX_IPSR_GPSR(IP13_23_20, AUDIO_CLKOUT1_A), 1303 1304 PINMUX_IPSR_GPSR(IP13_27_24, HRTS0_N), 1305 PINMUX_IPSR_MSEL(IP13_27_24, TX2_B, SEL_SCIF2_1), 1306 PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3), 1307 PINMUX_IPSR_MSEL(IP13_27_24, SSI_WS9_A, SEL_SSI9_0), 1308 PINMUX_IPSR_MSEL(IP13_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3), 1309 PINMUX_IPSR_MSEL(IP13_27_24, BPFCLK_A, SEL_FM_0), 1310 PINMUX_IPSR_GPSR(IP13_27_24, AUDIO_CLKOUT2_A), 1311 1312 PINMUX_IPSR_GPSR(IP13_31_28, MSIOF0_SYNC), 1313 PINMUX_IPSR_GPSR(IP13_31_28, AUDIO_CLKOUT_A), 1314 PINMUX_IPSR_MSEL(IP13_31_28, TX5_B, SEL_SCIF5_1), 1315 PINMUX_IPSR_MSEL(IP13_31_28, BPFCLK_D, SEL_FM_3), 1316 1317 /* IPSR14 */ 1318 PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1), 1319 PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0), 1320 PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDF_0), 1321 PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADGA_2), 1322 PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0), 1323 PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2), 1324 PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A), 1325 PINMUX_IPSR_MSEL(IP14_3_0, TCLK1_B, SEL_TIMER_TMU_1), 1326 1327 PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2), 1328 PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0), 1329 PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3), 1330 PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADGC_0), 1331 PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI2_0), 1332 PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3), 1333 PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D), 1334 PINMUX_IPSR_MSEL(IP14_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1), 1335 1336 PINMUX_IPSR_GPSR(IP14_11_8, MLB_CLK), 1337 PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SCK_F, SEL_MSIOF1_5), 1338 PINMUX_IPSR_MSEL(IP14_11_8, SCL1_B, SEL_I2C1_1), 1339 1340 PINMUX_IPSR_GPSR(IP14_15_12, MLB_SIG), 1341 PINMUX_IPSR_MSEL(IP14_15_12, RX1_B, SEL_SCIF1_1), 1342 PINMUX_IPSR_MSEL(IP14_15_12, MSIOF1_SYNC_F, SEL_MSIOF1_5), 1343 PINMUX_IPSR_MSEL(IP14_15_12, SDA1_B, SEL_I2C1_1), 1344 1345 PINMUX_IPSR_GPSR(IP14_19_16, MLB_DAT), 1346 PINMUX_IPSR_MSEL(IP14_19_16, TX1_B, SEL_SCIF1_1), 1347 PINMUX_IPSR_MSEL(IP14_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5), 1348 1349 PINMUX_IPSR_GPSR(IP14_23_20, SSI_SCK01239), 1350 PINMUX_IPSR_MSEL(IP14_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5), 1351 1352 PINMUX_IPSR_GPSR(IP14_27_24, SSI_WS01239), 1353 PINMUX_IPSR_MSEL(IP14_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5), 1354 1355 PINMUX_IPSR_GPSR(IP14_31_28, SSI_SDATA0), 1356 PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5), 1357 1358 /* IPSR15 */ 1359 PINMUX_IPSR_MSEL(IP15_3_0, SSI_SDATA1_A, SEL_SSI1_0), 1360 1361 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SDATA2_A, SEL_SSI2_0), 1362 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SCK1_B, SEL_SSI1_1), 1363 1364 PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK349), 1365 PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0), 1366 PINMUX_IPSR_MSEL(IP15_11_8, STP_OPWM_0_A, SEL_SSP1_0_0), 1367 1368 PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS349), 1369 PINMUX_IPSR_MSEL(IP15_15_12, HCTS2_N_A, SEL_HSCIF2_0), 1370 PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0), 1371 PINMUX_IPSR_MSEL(IP15_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0), 1372 1373 PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA3), 1374 PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0), 1375 PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_TXD_A, SEL_MSIOF1_0), 1376 PINMUX_IPSR_MSEL(IP15_19_16, TS_SCK0_A, SEL_TSIF0_0), 1377 PINMUX_IPSR_MSEL(IP15_19_16, STP_ISCLK_0_A, SEL_SSP1_0_0), 1378 PINMUX_IPSR_MSEL(IP15_19_16, RIF0_D1_A, SEL_DRIF0_0), 1379 PINMUX_IPSR_MSEL(IP15_19_16, RIF2_D0_A, SEL_DRIF2_0), 1380 1381 PINMUX_IPSR_GPSR(IP15_23_20, SSI_SCK4), 1382 PINMUX_IPSR_MSEL(IP15_23_20, HRX2_A, SEL_HSCIF2_0), 1383 PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_SCK_A, SEL_MSIOF1_0), 1384 PINMUX_IPSR_MSEL(IP15_23_20, TS_SDAT0_A, SEL_TSIF0_0), 1385 PINMUX_IPSR_MSEL(IP15_23_20, STP_ISD_0_A, SEL_SSP1_0_0), 1386 PINMUX_IPSR_MSEL(IP15_23_20, RIF0_CLK_A, SEL_DRIF0_0), 1387 PINMUX_IPSR_MSEL(IP15_23_20, RIF2_CLK_A, SEL_DRIF2_0), 1388 1389 PINMUX_IPSR_GPSR(IP15_27_24, SSI_WS4), 1390 PINMUX_IPSR_MSEL(IP15_27_24, HTX2_A, SEL_HSCIF2_0), 1391 PINMUX_IPSR_MSEL(IP15_27_24, MSIOF1_SYNC_A, SEL_MSIOF1_0), 1392 PINMUX_IPSR_MSEL(IP15_27_24, TS_SDEN0_A, SEL_TSIF0_0), 1393 PINMUX_IPSR_MSEL(IP15_27_24, STP_ISEN_0_A, SEL_SSP1_0_0), 1394 PINMUX_IPSR_MSEL(IP15_27_24, RIF0_SYNC_A, SEL_DRIF0_0), 1395 PINMUX_IPSR_MSEL(IP15_27_24, RIF2_SYNC_A, SEL_DRIF2_0), 1396 1397 PINMUX_IPSR_GPSR(IP15_31_28, SSI_SDATA4), 1398 PINMUX_IPSR_MSEL(IP15_31_28, HSCK2_A, SEL_HSCIF2_0), 1399 PINMUX_IPSR_MSEL(IP15_31_28, MSIOF1_RXD_A, SEL_MSIOF1_0), 1400 PINMUX_IPSR_MSEL(IP15_31_28, TS_SPSYNC0_A, SEL_TSIF0_0), 1401 PINMUX_IPSR_MSEL(IP15_31_28, STP_ISSYNC_0_A, SEL_SSP1_0_0), 1402 PINMUX_IPSR_MSEL(IP15_31_28, RIF0_D0_A, SEL_DRIF0_0), 1403 PINMUX_IPSR_MSEL(IP15_31_28, RIF2_D1_A, SEL_DRIF2_0), 1404 1405 /* IPSR16 */ 1406 PINMUX_IPSR_GPSR(IP16_3_0, SSI_SCK6), 1407 PINMUX_IPSR_MSEL(IP16_3_0, SIM0_RST_D, SEL_SIMCARD_3), 1408 1409 PINMUX_IPSR_GPSR(IP16_7_4, SSI_WS6), 1410 PINMUX_IPSR_MSEL(IP16_7_4, SIM0_D_D, SEL_SIMCARD_3), 1411 1412 PINMUX_IPSR_GPSR(IP16_11_8, SSI_SDATA6), 1413 PINMUX_IPSR_MSEL(IP16_11_8, SIM0_CLK_D, SEL_SIMCARD_3), 1414 1415 PINMUX_IPSR_GPSR(IP16_15_12, SSI_SCK78), 1416 PINMUX_IPSR_MSEL(IP16_15_12, HRX2_B, SEL_HSCIF2_1), 1417 PINMUX_IPSR_MSEL(IP16_15_12, MSIOF1_SCK_C, SEL_MSIOF1_2), 1418 PINMUX_IPSR_MSEL(IP16_15_12, TS_SCK1_A, SEL_TSIF1_0), 1419 PINMUX_IPSR_MSEL(IP16_15_12, STP_ISCLK_1_A, SEL_SSP1_1_0), 1420 PINMUX_IPSR_MSEL(IP16_15_12, RIF1_CLK_A, SEL_DRIF1_0), 1421 PINMUX_IPSR_MSEL(IP16_15_12, RIF3_CLK_A, SEL_DRIF3_0), 1422 1423 PINMUX_IPSR_GPSR(IP16_19_16, SSI_WS78), 1424 PINMUX_IPSR_MSEL(IP16_19_16, HTX2_B, SEL_HSCIF2_1), 1425 PINMUX_IPSR_MSEL(IP16_19_16, MSIOF1_SYNC_C, SEL_MSIOF1_2), 1426 PINMUX_IPSR_MSEL(IP16_19_16, TS_SDAT1_A, SEL_TSIF1_0), 1427 PINMUX_IPSR_MSEL(IP16_19_16, STP_ISD_1_A, SEL_SSP1_1_0), 1428 PINMUX_IPSR_MSEL(IP16_19_16, RIF1_SYNC_A, SEL_DRIF1_0), 1429 PINMUX_IPSR_MSEL(IP16_19_16, RIF3_SYNC_A, SEL_DRIF3_0), 1430 1431 PINMUX_IPSR_GPSR(IP16_23_20, SSI_SDATA7), 1432 PINMUX_IPSR_MSEL(IP16_23_20, HCTS2_N_B, SEL_HSCIF2_1), 1433 PINMUX_IPSR_MSEL(IP16_23_20, MSIOF1_RXD_C, SEL_MSIOF1_2), 1434 PINMUX_IPSR_MSEL(IP16_23_20, TS_SDEN1_A, SEL_TSIF1_0), 1435 PINMUX_IPSR_MSEL(IP16_23_20, STP_ISEN_1_A, SEL_SSP1_1_0), 1436 PINMUX_IPSR_MSEL(IP16_23_20, RIF1_D0_A, SEL_DRIF1_0), 1437 PINMUX_IPSR_MSEL(IP16_23_20, RIF3_D0_A, SEL_DRIF3_0), 1438 PINMUX_IPSR_MSEL(IP16_23_20, TCLK2_A, SEL_TIMER_TMU2_0), 1439 1440 PINMUX_IPSR_GPSR(IP16_27_24, SSI_SDATA8), 1441 PINMUX_IPSR_MSEL(IP16_27_24, HRTS2_N_B, SEL_HSCIF2_1), 1442 PINMUX_IPSR_MSEL(IP16_27_24, MSIOF1_TXD_C, SEL_MSIOF1_2), 1443 PINMUX_IPSR_MSEL(IP16_27_24, TS_SPSYNC1_A, SEL_TSIF1_0), 1444 PINMUX_IPSR_MSEL(IP16_27_24, STP_ISSYNC_1_A, SEL_SSP1_1_0), 1445 PINMUX_IPSR_MSEL(IP16_27_24, RIF1_D1_A, SEL_DRIF1_0), 1446 PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D1_A, SEL_DRIF3_0), 1447 1448 PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA9_A, SEL_SSI9_0), 1449 PINMUX_IPSR_MSEL(IP16_31_28, HSCK2_B, SEL_HSCIF2_1), 1450 PINMUX_IPSR_MSEL(IP16_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2), 1451 PINMUX_IPSR_MSEL(IP16_31_28, HSCK1_A, SEL_HSCIF1_0), 1452 PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI1_1), 1453 PINMUX_IPSR_GPSR(IP16_31_28, SCK1), 1454 PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0), 1455 PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0), 1456 1457 /* IPSR17 */ 1458 PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADGA_0), 1459 1460 PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADGB_1), 1461 PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0), 1462 PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3), 1463 PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0), 1464 PINMUX_IPSR_MSEL(IP17_7_4, TCLK1_A, SEL_TIMER_TMU_0), 1465 1466 PINMUX_IPSR_GPSR(IP17_11_8, USB0_PWEN), 1467 PINMUX_IPSR_MSEL(IP17_11_8, SIM0_RST_C, SEL_SIMCARD_2), 1468 PINMUX_IPSR_MSEL(IP17_11_8, TS_SCK1_D, SEL_TSIF1_3), 1469 PINMUX_IPSR_MSEL(IP17_11_8, STP_ISCLK_1_D, SEL_SSP1_1_3), 1470 PINMUX_IPSR_MSEL(IP17_11_8, BPFCLK_B, SEL_FM_1), 1471 PINMUX_IPSR_MSEL(IP17_11_8, RIF3_CLK_B, SEL_DRIF3_1), 1472 PINMUX_IPSR_MSEL(IP17_11_8, HSCK2_C, SEL_HSCIF2_2), 1473 1474 PINMUX_IPSR_GPSR(IP17_15_12, USB0_OVC), 1475 PINMUX_IPSR_MSEL(IP17_15_12, SIM0_D_C, SEL_SIMCARD_2), 1476 PINMUX_IPSR_MSEL(IP17_15_12, TS_SDAT1_D, SEL_TSIF1_3), 1477 PINMUX_IPSR_MSEL(IP17_15_12, STP_ISD_1_D, SEL_SSP1_1_3), 1478 PINMUX_IPSR_MSEL(IP17_15_12, RIF3_SYNC_B, SEL_DRIF3_1), 1479 PINMUX_IPSR_MSEL(IP17_15_12, HRX2_C, SEL_HSCIF2_2), 1480 1481 PINMUX_IPSR_GPSR(IP17_19_16, USB1_PWEN), 1482 PINMUX_IPSR_MSEL(IP17_19_16, SIM0_CLK_C, SEL_SIMCARD_2), 1483 PINMUX_IPSR_MSEL(IP17_19_16, SSI_SCK1_A, SEL_SSI1_0), 1484 PINMUX_IPSR_MSEL(IP17_19_16, TS_SCK0_E, SEL_TSIF0_4), 1485 PINMUX_IPSR_MSEL(IP17_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4), 1486 PINMUX_IPSR_MSEL(IP17_19_16, FMCLK_B, SEL_FM_1), 1487 PINMUX_IPSR_MSEL(IP17_19_16, RIF2_CLK_B, SEL_DRIF2_1), 1488 PINMUX_IPSR_MSEL(IP17_19_16, SPEEDIN_A, SEL_SPEED_PULSE_0), 1489 PINMUX_IPSR_MSEL(IP17_19_16, HTX2_C, SEL_HSCIF2_2), 1490 1491 PINMUX_IPSR_GPSR(IP17_23_20, USB1_OVC), 1492 PINMUX_IPSR_MSEL(IP17_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2), 1493 PINMUX_IPSR_MSEL(IP17_23_20, SSI_WS1_A, SEL_SSI1_0), 1494 PINMUX_IPSR_MSEL(IP17_23_20, TS_SDAT0_E, SEL_TSIF0_4), 1495 PINMUX_IPSR_MSEL(IP17_23_20, STP_ISD_0_E, SEL_SSP1_0_4), 1496 PINMUX_IPSR_MSEL(IP17_23_20, FMIN_B, SEL_FM_1), 1497 PINMUX_IPSR_MSEL(IP17_23_20, RIF2_SYNC_B, SEL_DRIF2_1), 1498 PINMUX_IPSR_MSEL(IP17_23_20, REMOCON_B, SEL_REMOCON_1), 1499 PINMUX_IPSR_MSEL(IP17_23_20, HCTS2_N_C, SEL_HSCIF2_2), 1500 1501 PINMUX_IPSR_GPSR(IP17_27_24, USB30_PWEN), 1502 PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_B), 1503 PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI2_1), 1504 PINMUX_IPSR_MSEL(IP17_27_24, TS_SDEN1_D, SEL_TSIF1_3), 1505 PINMUX_IPSR_MSEL(IP17_27_24, STP_ISEN_1_D, SEL_SSP1_1_3), 1506 PINMUX_IPSR_MSEL(IP17_27_24, STP_OPWM_0_E, SEL_SSP1_0_4), 1507 PINMUX_IPSR_MSEL(IP17_27_24, RIF3_D0_B, SEL_DRIF3_1), 1508 PINMUX_IPSR_MSEL(IP17_27_24, TCLK2_B, SEL_TIMER_TMU2_1), 1509 PINMUX_IPSR_GPSR(IP17_27_24, TPU0TO0), 1510 PINMUX_IPSR_MSEL(IP17_27_24, BPFCLK_C, SEL_FM_2), 1511 PINMUX_IPSR_MSEL(IP17_27_24, HRTS2_N_C, SEL_HSCIF2_2), 1512 1513 PINMUX_IPSR_GPSR(IP17_31_28, USB30_OVC), 1514 PINMUX_IPSR_GPSR(IP17_31_28, AUDIO_CLKOUT1_B), 1515 PINMUX_IPSR_MSEL(IP17_31_28, SSI_WS2_B, SEL_SSI2_1), 1516 PINMUX_IPSR_MSEL(IP17_31_28, TS_SPSYNC1_D, SEL_TSIF1_3), 1517 PINMUX_IPSR_MSEL(IP17_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3), 1518 PINMUX_IPSR_MSEL(IP17_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4), 1519 PINMUX_IPSR_MSEL(IP17_31_28, RIF3_D1_B, SEL_DRIF3_1), 1520 PINMUX_IPSR_GPSR(IP17_31_28, FSO_TOE_N), 1521 PINMUX_IPSR_GPSR(IP17_31_28, TPU0TO1), 1522 1523 /* IPSR18 */ 1524 PINMUX_IPSR_GPSR(IP18_3_0, GP6_30), 1525 PINMUX_IPSR_GPSR(IP18_3_0, AUDIO_CLKOUT2_B), 1526 PINMUX_IPSR_MSEL(IP18_3_0, SSI_SCK9_B, SEL_SSI9_1), 1527 PINMUX_IPSR_MSEL(IP18_3_0, TS_SDEN0_E, SEL_TSIF0_4), 1528 PINMUX_IPSR_MSEL(IP18_3_0, STP_ISEN_0_E, SEL_SSP1_0_4), 1529 PINMUX_IPSR_MSEL(IP18_3_0, RIF2_D0_B, SEL_DRIF2_1), 1530 PINMUX_IPSR_GPSR(IP18_3_0, TPU0TO2), 1531 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_C, SEL_FM_2), 1532 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_D, SEL_FM_3), 1533 1534 PINMUX_IPSR_GPSR(IP18_7_4, GP6_31), 1535 PINMUX_IPSR_GPSR(IP18_7_4, AUDIO_CLKOUT3_B), 1536 PINMUX_IPSR_MSEL(IP18_7_4, SSI_WS9_B, SEL_SSI9_1), 1537 PINMUX_IPSR_MSEL(IP18_7_4, TS_SPSYNC0_E, SEL_TSIF0_4), 1538 PINMUX_IPSR_MSEL(IP18_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4), 1539 PINMUX_IPSR_MSEL(IP18_7_4, RIF2_D1_B, SEL_DRIF2_1), 1540 PINMUX_IPSR_GPSR(IP18_7_4, TPU0TO3), 1541 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_C, SEL_FM_2), 1542 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_D, SEL_FM_3), 1543 1544 /* 1545 * Static pins can not be muxed between different functions but 1546 * still need mark entries in the pinmux list. Add each static 1547 * pin to the list without an associated function. The sh-pfc 1548 * core will do the right thing and skip trying to mux the pin 1549 * while still applying configuration to it. 1550 */ 1551 #define FM(x) PINMUX_DATA(x##_MARK, 0), 1552 PINMUX_STATIC 1553 #undef FM 1554 }; 1555 1556 /* 1557 * Pins not associated with a GPIO port. 1558 */ 1559 enum { 1560 GP_ASSIGN_LAST(), 1561 NOGP_ALL(), 1562 }; 1563 1564 static const struct sh_pfc_pin pinmux_pins[] = { 1565 PINMUX_GPIO_GP_ALL(), 1566 PINMUX_NOGP_ALL(), 1567 }; 1568 1569 /* - AUDIO CLOCK ------------------------------------------------------------ */ 1570 static const unsigned int audio_clk_a_a_pins[] = { 1571 /* CLK A */ 1572 RCAR_GP_PIN(6, 22), 1573 }; 1574 static const unsigned int audio_clk_a_a_mux[] = { 1575 AUDIO_CLKA_A_MARK, 1576 }; 1577 static const unsigned int audio_clk_a_b_pins[] = { 1578 /* CLK A */ 1579 RCAR_GP_PIN(5, 4), 1580 }; 1581 static const unsigned int audio_clk_a_b_mux[] = { 1582 AUDIO_CLKA_B_MARK, 1583 }; 1584 static const unsigned int audio_clk_a_c_pins[] = { 1585 /* CLK A */ 1586 RCAR_GP_PIN(5, 19), 1587 }; 1588 static const unsigned int audio_clk_a_c_mux[] = { 1589 AUDIO_CLKA_C_MARK, 1590 }; 1591 static const unsigned int audio_clk_b_a_pins[] = { 1592 /* CLK B */ 1593 RCAR_GP_PIN(5, 12), 1594 }; 1595 static const unsigned int audio_clk_b_a_mux[] = { 1596 AUDIO_CLKB_A_MARK, 1597 }; 1598 static const unsigned int audio_clk_b_b_pins[] = { 1599 /* CLK B */ 1600 RCAR_GP_PIN(6, 23), 1601 }; 1602 static const unsigned int audio_clk_b_b_mux[] = { 1603 AUDIO_CLKB_B_MARK, 1604 }; 1605 static const unsigned int audio_clk_c_a_pins[] = { 1606 /* CLK C */ 1607 RCAR_GP_PIN(5, 21), 1608 }; 1609 static const unsigned int audio_clk_c_a_mux[] = { 1610 AUDIO_CLKC_A_MARK, 1611 }; 1612 static const unsigned int audio_clk_c_b_pins[] = { 1613 /* CLK C */ 1614 RCAR_GP_PIN(5, 0), 1615 }; 1616 static const unsigned int audio_clk_c_b_mux[] = { 1617 AUDIO_CLKC_B_MARK, 1618 }; 1619 static const unsigned int audio_clkout_a_pins[] = { 1620 /* CLKOUT */ 1621 RCAR_GP_PIN(5, 18), 1622 }; 1623 static const unsigned int audio_clkout_a_mux[] = { 1624 AUDIO_CLKOUT_A_MARK, 1625 }; 1626 static const unsigned int audio_clkout_b_pins[] = { 1627 /* CLKOUT */ 1628 RCAR_GP_PIN(6, 28), 1629 }; 1630 static const unsigned int audio_clkout_b_mux[] = { 1631 AUDIO_CLKOUT_B_MARK, 1632 }; 1633 static const unsigned int audio_clkout_c_pins[] = { 1634 /* CLKOUT */ 1635 RCAR_GP_PIN(5, 3), 1636 }; 1637 static const unsigned int audio_clkout_c_mux[] = { 1638 AUDIO_CLKOUT_C_MARK, 1639 }; 1640 static const unsigned int audio_clkout_d_pins[] = { 1641 /* CLKOUT */ 1642 RCAR_GP_PIN(5, 21), 1643 }; 1644 static const unsigned int audio_clkout_d_mux[] = { 1645 AUDIO_CLKOUT_D_MARK, 1646 }; 1647 static const unsigned int audio_clkout1_a_pins[] = { 1648 /* CLKOUT1 */ 1649 RCAR_GP_PIN(5, 15), 1650 }; 1651 static const unsigned int audio_clkout1_a_mux[] = { 1652 AUDIO_CLKOUT1_A_MARK, 1653 }; 1654 static const unsigned int audio_clkout1_b_pins[] = { 1655 /* CLKOUT1 */ 1656 RCAR_GP_PIN(6, 29), 1657 }; 1658 static const unsigned int audio_clkout1_b_mux[] = { 1659 AUDIO_CLKOUT1_B_MARK, 1660 }; 1661 static const unsigned int audio_clkout2_a_pins[] = { 1662 /* CLKOUT2 */ 1663 RCAR_GP_PIN(5, 16), 1664 }; 1665 static const unsigned int audio_clkout2_a_mux[] = { 1666 AUDIO_CLKOUT2_A_MARK, 1667 }; 1668 static const unsigned int audio_clkout2_b_pins[] = { 1669 /* CLKOUT2 */ 1670 RCAR_GP_PIN(6, 30), 1671 }; 1672 static const unsigned int audio_clkout2_b_mux[] = { 1673 AUDIO_CLKOUT2_B_MARK, 1674 }; 1675 1676 static const unsigned int audio_clkout3_a_pins[] = { 1677 /* CLKOUT3 */ 1678 RCAR_GP_PIN(5, 19), 1679 }; 1680 static const unsigned int audio_clkout3_a_mux[] = { 1681 AUDIO_CLKOUT3_A_MARK, 1682 }; 1683 static const unsigned int audio_clkout3_b_pins[] = { 1684 /* CLKOUT3 */ 1685 RCAR_GP_PIN(6, 31), 1686 }; 1687 static const unsigned int audio_clkout3_b_mux[] = { 1688 AUDIO_CLKOUT3_B_MARK, 1689 }; 1690 1691 /* - EtherAVB --------------------------------------------------------------- */ 1692 static const unsigned int avb_link_pins[] = { 1693 /* AVB_LINK */ 1694 RCAR_GP_PIN(2, 12), 1695 }; 1696 static const unsigned int avb_link_mux[] = { 1697 AVB_LINK_MARK, 1698 }; 1699 static const unsigned int avb_magic_pins[] = { 1700 /* AVB_MAGIC_ */ 1701 RCAR_GP_PIN(2, 10), 1702 }; 1703 static const unsigned int avb_magic_mux[] = { 1704 AVB_MAGIC_MARK, 1705 }; 1706 static const unsigned int avb_phy_int_pins[] = { 1707 /* AVB_PHY_INT */ 1708 RCAR_GP_PIN(2, 11), 1709 }; 1710 static const unsigned int avb_phy_int_mux[] = { 1711 AVB_PHY_INT_MARK, 1712 }; 1713 static const unsigned int avb_mdio_pins[] = { 1714 /* AVB_MDC, AVB_MDIO */ 1715 RCAR_GP_PIN(2, 9), PIN_AVB_MDIO, 1716 }; 1717 static const unsigned int avb_mdio_mux[] = { 1718 AVB_MDC_MARK, AVB_MDIO_MARK, 1719 }; 1720 static const unsigned int avb_mii_pins[] = { 1721 /* 1722 * AVB_TX_CTL, AVB_TXC, AVB_TD0, 1723 * AVB_TD1, AVB_TD2, AVB_TD3, 1724 * AVB_RX_CTL, AVB_RXC, AVB_RD0, 1725 * AVB_RD1, AVB_RD2, AVB_RD3, 1726 * AVB_TXCREFCLK 1727 */ 1728 PIN_AVB_TX_CTL, PIN_AVB_TXC, PIN_AVB_TD0, 1729 PIN_AVB_TD1, PIN_AVB_TD2, PIN_AVB_TD3, 1730 PIN_AVB_RX_CTL, PIN_AVB_RXC, PIN_AVB_RD0, 1731 PIN_AVB_RD1, PIN_AVB_RD2, PIN_AVB_RD3, 1732 PIN_AVB_TXCREFCLK, 1733 }; 1734 static const unsigned int avb_mii_mux[] = { 1735 AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK, 1736 AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK, 1737 AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK, 1738 AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK, 1739 AVB_TXCREFCLK_MARK, 1740 }; 1741 static const unsigned int avb_avtp_pps_pins[] = { 1742 /* AVB_AVTP_PPS */ 1743 RCAR_GP_PIN(2, 6), 1744 }; 1745 static const unsigned int avb_avtp_pps_mux[] = { 1746 AVB_AVTP_PPS_MARK, 1747 }; 1748 static const unsigned int avb_avtp_match_a_pins[] = { 1749 /* AVB_AVTP_MATCH_A */ 1750 RCAR_GP_PIN(2, 13), 1751 }; 1752 static const unsigned int avb_avtp_match_a_mux[] = { 1753 AVB_AVTP_MATCH_A_MARK, 1754 }; 1755 static const unsigned int avb_avtp_capture_a_pins[] = { 1756 /* AVB_AVTP_CAPTURE_A */ 1757 RCAR_GP_PIN(2, 14), 1758 }; 1759 static const unsigned int avb_avtp_capture_a_mux[] = { 1760 AVB_AVTP_CAPTURE_A_MARK, 1761 }; 1762 static const unsigned int avb_avtp_match_b_pins[] = { 1763 /* AVB_AVTP_MATCH_B */ 1764 RCAR_GP_PIN(1, 8), 1765 }; 1766 static const unsigned int avb_avtp_match_b_mux[] = { 1767 AVB_AVTP_MATCH_B_MARK, 1768 }; 1769 static const unsigned int avb_avtp_capture_b_pins[] = { 1770 /* AVB_AVTP_CAPTURE_B */ 1771 RCAR_GP_PIN(1, 11), 1772 }; 1773 static const unsigned int avb_avtp_capture_b_mux[] = { 1774 AVB_AVTP_CAPTURE_B_MARK, 1775 }; 1776 1777 /* - CAN ------------------------------------------------------------------ */ 1778 static const unsigned int can0_data_a_pins[] = { 1779 /* TX, RX */ 1780 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24), 1781 }; 1782 static const unsigned int can0_data_a_mux[] = { 1783 CAN0_TX_A_MARK, CAN0_RX_A_MARK, 1784 }; 1785 static const unsigned int can0_data_b_pins[] = { 1786 /* TX, RX */ 1787 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), 1788 }; 1789 static const unsigned int can0_data_b_mux[] = { 1790 CAN0_TX_B_MARK, CAN0_RX_B_MARK, 1791 }; 1792 static const unsigned int can1_data_pins[] = { 1793 /* TX, RX */ 1794 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26), 1795 }; 1796 static const unsigned int can1_data_mux[] = { 1797 CAN1_TX_MARK, CAN1_RX_MARK, 1798 }; 1799 1800 /* - CAN Clock -------------------------------------------------------------- */ 1801 static const unsigned int can_clk_pins[] = { 1802 /* CLK */ 1803 RCAR_GP_PIN(1, 25), 1804 }; 1805 static const unsigned int can_clk_mux[] = { 1806 CAN_CLK_MARK, 1807 }; 1808 1809 /* - CAN FD --------------------------------------------------------------- */ 1810 static const unsigned int canfd0_data_a_pins[] = { 1811 /* TX, RX */ 1812 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24), 1813 }; 1814 static const unsigned int canfd0_data_a_mux[] = { 1815 CANFD0_TX_A_MARK, CANFD0_RX_A_MARK, 1816 }; 1817 static const unsigned int canfd0_data_b_pins[] = { 1818 /* TX, RX */ 1819 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), 1820 }; 1821 static const unsigned int canfd0_data_b_mux[] = { 1822 CANFD0_TX_B_MARK, CANFD0_RX_B_MARK, 1823 }; 1824 static const unsigned int canfd1_data_pins[] = { 1825 /* TX, RX */ 1826 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26), 1827 }; 1828 static const unsigned int canfd1_data_mux[] = { 1829 CANFD1_TX_MARK, CANFD1_RX_MARK, 1830 }; 1831 1832 #if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961) 1833 /* - DRIF0 --------------------------------------------------------------- */ 1834 static const unsigned int drif0_ctrl_a_pins[] = { 1835 /* CLK, SYNC */ 1836 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), 1837 }; 1838 static const unsigned int drif0_ctrl_a_mux[] = { 1839 RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK, 1840 }; 1841 static const unsigned int drif0_data0_a_pins[] = { 1842 /* D0 */ 1843 RCAR_GP_PIN(6, 10), 1844 }; 1845 static const unsigned int drif0_data0_a_mux[] = { 1846 RIF0_D0_A_MARK, 1847 }; 1848 static const unsigned int drif0_data1_a_pins[] = { 1849 /* D1 */ 1850 RCAR_GP_PIN(6, 7), 1851 }; 1852 static const unsigned int drif0_data1_a_mux[] = { 1853 RIF0_D1_A_MARK, 1854 }; 1855 static const unsigned int drif0_ctrl_b_pins[] = { 1856 /* CLK, SYNC */ 1857 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4), 1858 }; 1859 static const unsigned int drif0_ctrl_b_mux[] = { 1860 RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK, 1861 }; 1862 static const unsigned int drif0_data0_b_pins[] = { 1863 /* D0 */ 1864 RCAR_GP_PIN(5, 1), 1865 }; 1866 static const unsigned int drif0_data0_b_mux[] = { 1867 RIF0_D0_B_MARK, 1868 }; 1869 static const unsigned int drif0_data1_b_pins[] = { 1870 /* D1 */ 1871 RCAR_GP_PIN(5, 2), 1872 }; 1873 static const unsigned int drif0_data1_b_mux[] = { 1874 RIF0_D1_B_MARK, 1875 }; 1876 static const unsigned int drif0_ctrl_c_pins[] = { 1877 /* CLK, SYNC */ 1878 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15), 1879 }; 1880 static const unsigned int drif0_ctrl_c_mux[] = { 1881 RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK, 1882 }; 1883 static const unsigned int drif0_data0_c_pins[] = { 1884 /* D0 */ 1885 RCAR_GP_PIN(5, 13), 1886 }; 1887 static const unsigned int drif0_data0_c_mux[] = { 1888 RIF0_D0_C_MARK, 1889 }; 1890 static const unsigned int drif0_data1_c_pins[] = { 1891 /* D1 */ 1892 RCAR_GP_PIN(5, 14), 1893 }; 1894 static const unsigned int drif0_data1_c_mux[] = { 1895 RIF0_D1_C_MARK, 1896 }; 1897 /* - DRIF1 --------------------------------------------------------------- */ 1898 static const unsigned int drif1_ctrl_a_pins[] = { 1899 /* CLK, SYNC */ 1900 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18), 1901 }; 1902 static const unsigned int drif1_ctrl_a_mux[] = { 1903 RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK, 1904 }; 1905 static const unsigned int drif1_data0_a_pins[] = { 1906 /* D0 */ 1907 RCAR_GP_PIN(6, 19), 1908 }; 1909 static const unsigned int drif1_data0_a_mux[] = { 1910 RIF1_D0_A_MARK, 1911 }; 1912 static const unsigned int drif1_data1_a_pins[] = { 1913 /* D1 */ 1914 RCAR_GP_PIN(6, 20), 1915 }; 1916 static const unsigned int drif1_data1_a_mux[] = { 1917 RIF1_D1_A_MARK, 1918 }; 1919 static const unsigned int drif1_ctrl_b_pins[] = { 1920 /* CLK, SYNC */ 1921 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3), 1922 }; 1923 static const unsigned int drif1_ctrl_b_mux[] = { 1924 RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK, 1925 }; 1926 static const unsigned int drif1_data0_b_pins[] = { 1927 /* D0 */ 1928 RCAR_GP_PIN(5, 7), 1929 }; 1930 static const unsigned int drif1_data0_b_mux[] = { 1931 RIF1_D0_B_MARK, 1932 }; 1933 static const unsigned int drif1_data1_b_pins[] = { 1934 /* D1 */ 1935 RCAR_GP_PIN(5, 8), 1936 }; 1937 static const unsigned int drif1_data1_b_mux[] = { 1938 RIF1_D1_B_MARK, 1939 }; 1940 static const unsigned int drif1_ctrl_c_pins[] = { 1941 /* CLK, SYNC */ 1942 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11), 1943 }; 1944 static const unsigned int drif1_ctrl_c_mux[] = { 1945 RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK, 1946 }; 1947 static const unsigned int drif1_data0_c_pins[] = { 1948 /* D0 */ 1949 RCAR_GP_PIN(5, 6), 1950 }; 1951 static const unsigned int drif1_data0_c_mux[] = { 1952 RIF1_D0_C_MARK, 1953 }; 1954 static const unsigned int drif1_data1_c_pins[] = { 1955 /* D1 */ 1956 RCAR_GP_PIN(5, 10), 1957 }; 1958 static const unsigned int drif1_data1_c_mux[] = { 1959 RIF1_D1_C_MARK, 1960 }; 1961 /* - DRIF2 --------------------------------------------------------------- */ 1962 static const unsigned int drif2_ctrl_a_pins[] = { 1963 /* CLK, SYNC */ 1964 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), 1965 }; 1966 static const unsigned int drif2_ctrl_a_mux[] = { 1967 RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK, 1968 }; 1969 static const unsigned int drif2_data0_a_pins[] = { 1970 /* D0 */ 1971 RCAR_GP_PIN(6, 7), 1972 }; 1973 static const unsigned int drif2_data0_a_mux[] = { 1974 RIF2_D0_A_MARK, 1975 }; 1976 static const unsigned int drif2_data1_a_pins[] = { 1977 /* D1 */ 1978 RCAR_GP_PIN(6, 10), 1979 }; 1980 static const unsigned int drif2_data1_a_mux[] = { 1981 RIF2_D1_A_MARK, 1982 }; 1983 static const unsigned int drif2_ctrl_b_pins[] = { 1984 /* CLK, SYNC */ 1985 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27), 1986 }; 1987 static const unsigned int drif2_ctrl_b_mux[] = { 1988 RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK, 1989 }; 1990 static const unsigned int drif2_data0_b_pins[] = { 1991 /* D0 */ 1992 RCAR_GP_PIN(6, 30), 1993 }; 1994 static const unsigned int drif2_data0_b_mux[] = { 1995 RIF2_D0_B_MARK, 1996 }; 1997 static const unsigned int drif2_data1_b_pins[] = { 1998 /* D1 */ 1999 RCAR_GP_PIN(6, 31), 2000 }; 2001 static const unsigned int drif2_data1_b_mux[] = { 2002 RIF2_D1_B_MARK, 2003 }; 2004 /* - DRIF3 --------------------------------------------------------------- */ 2005 static const unsigned int drif3_ctrl_a_pins[] = { 2006 /* CLK, SYNC */ 2007 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18), 2008 }; 2009 static const unsigned int drif3_ctrl_a_mux[] = { 2010 RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK, 2011 }; 2012 static const unsigned int drif3_data0_a_pins[] = { 2013 /* D0 */ 2014 RCAR_GP_PIN(6, 19), 2015 }; 2016 static const unsigned int drif3_data0_a_mux[] = { 2017 RIF3_D0_A_MARK, 2018 }; 2019 static const unsigned int drif3_data1_a_pins[] = { 2020 /* D1 */ 2021 RCAR_GP_PIN(6, 20), 2022 }; 2023 static const unsigned int drif3_data1_a_mux[] = { 2024 RIF3_D1_A_MARK, 2025 }; 2026 static const unsigned int drif3_ctrl_b_pins[] = { 2027 /* CLK, SYNC */ 2028 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25), 2029 }; 2030 static const unsigned int drif3_ctrl_b_mux[] = { 2031 RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK, 2032 }; 2033 static const unsigned int drif3_data0_b_pins[] = { 2034 /* D0 */ 2035 RCAR_GP_PIN(6, 28), 2036 }; 2037 static const unsigned int drif3_data0_b_mux[] = { 2038 RIF3_D0_B_MARK, 2039 }; 2040 static const unsigned int drif3_data1_b_pins[] = { 2041 /* D1 */ 2042 RCAR_GP_PIN(6, 29), 2043 }; 2044 static const unsigned int drif3_data1_b_mux[] = { 2045 RIF3_D1_B_MARK, 2046 }; 2047 #endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */ 2048 2049 /* - DU --------------------------------------------------------------------- */ 2050 static const unsigned int du_rgb666_pins[] = { 2051 /* R[7:2], G[7:2], B[7:2] */ 2052 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), 2053 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), 2054 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), 2055 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18), 2056 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5), 2057 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2), 2058 }; 2059 static const unsigned int du_rgb666_mux[] = { 2060 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK, 2061 DU_DR3_MARK, DU_DR2_MARK, 2062 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK, 2063 DU_DG3_MARK, DU_DG2_MARK, 2064 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK, 2065 DU_DB3_MARK, DU_DB2_MARK, 2066 }; 2067 static const unsigned int du_rgb888_pins[] = { 2068 /* R[7:0], G[7:0], B[7:0] */ 2069 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), 2070 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), 2071 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8), 2072 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), 2073 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18), 2074 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16), 2075 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5), 2076 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2), 2077 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0), 2078 }; 2079 static const unsigned int du_rgb888_mux[] = { 2080 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK, 2081 DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK, 2082 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK, 2083 DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK, 2084 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK, 2085 DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK, 2086 }; 2087 static const unsigned int du_clk_out_0_pins[] = { 2088 /* CLKOUT */ 2089 RCAR_GP_PIN(1, 27), 2090 }; 2091 static const unsigned int du_clk_out_0_mux[] = { 2092 DU_DOTCLKOUT0_MARK 2093 }; 2094 static const unsigned int du_clk_out_1_pins[] = { 2095 /* CLKOUT */ 2096 RCAR_GP_PIN(2, 3), 2097 }; 2098 static const unsigned int du_clk_out_1_mux[] = { 2099 DU_DOTCLKOUT1_MARK 2100 }; 2101 static const unsigned int du_sync_pins[] = { 2102 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */ 2103 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4), 2104 }; 2105 static const unsigned int du_sync_mux[] = { 2106 DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK 2107 }; 2108 static const unsigned int du_oddf_pins[] = { 2109 /* EXDISP/EXODDF/EXCDE */ 2110 RCAR_GP_PIN(2, 2), 2111 }; 2112 static const unsigned int du_oddf_mux[] = { 2113 DU_EXODDF_DU_ODDF_DISP_CDE_MARK, 2114 }; 2115 static const unsigned int du_cde_pins[] = { 2116 /* CDE */ 2117 RCAR_GP_PIN(2, 0), 2118 }; 2119 static const unsigned int du_cde_mux[] = { 2120 DU_CDE_MARK, 2121 }; 2122 static const unsigned int du_disp_pins[] = { 2123 /* DISP */ 2124 RCAR_GP_PIN(2, 1), 2125 }; 2126 static const unsigned int du_disp_mux[] = { 2127 DU_DISP_MARK, 2128 }; 2129 2130 /* - HSCIF0 ----------------------------------------------------------------- */ 2131 static const unsigned int hscif0_data_pins[] = { 2132 /* RX, TX */ 2133 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14), 2134 }; 2135 static const unsigned int hscif0_data_mux[] = { 2136 HRX0_MARK, HTX0_MARK, 2137 }; 2138 static const unsigned int hscif0_clk_pins[] = { 2139 /* SCK */ 2140 RCAR_GP_PIN(5, 12), 2141 }; 2142 static const unsigned int hscif0_clk_mux[] = { 2143 HSCK0_MARK, 2144 }; 2145 static const unsigned int hscif0_ctrl_pins[] = { 2146 /* RTS, CTS */ 2147 RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15), 2148 }; 2149 static const unsigned int hscif0_ctrl_mux[] = { 2150 HRTS0_N_MARK, HCTS0_N_MARK, 2151 }; 2152 /* - HSCIF1 ----------------------------------------------------------------- */ 2153 static const unsigned int hscif1_data_a_pins[] = { 2154 /* RX, TX */ 2155 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6), 2156 }; 2157 static const unsigned int hscif1_data_a_mux[] = { 2158 HRX1_A_MARK, HTX1_A_MARK, 2159 }; 2160 static const unsigned int hscif1_clk_a_pins[] = { 2161 /* SCK */ 2162 RCAR_GP_PIN(6, 21), 2163 }; 2164 static const unsigned int hscif1_clk_a_mux[] = { 2165 HSCK1_A_MARK, 2166 }; 2167 static const unsigned int hscif1_ctrl_a_pins[] = { 2168 /* RTS, CTS */ 2169 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7), 2170 }; 2171 static const unsigned int hscif1_ctrl_a_mux[] = { 2172 HRTS1_N_A_MARK, HCTS1_N_A_MARK, 2173 }; 2174 2175 static const unsigned int hscif1_data_b_pins[] = { 2176 /* RX, TX */ 2177 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), 2178 }; 2179 static const unsigned int hscif1_data_b_mux[] = { 2180 HRX1_B_MARK, HTX1_B_MARK, 2181 }; 2182 static const unsigned int hscif1_clk_b_pins[] = { 2183 /* SCK */ 2184 RCAR_GP_PIN(5, 0), 2185 }; 2186 static const unsigned int hscif1_clk_b_mux[] = { 2187 HSCK1_B_MARK, 2188 }; 2189 static const unsigned int hscif1_ctrl_b_pins[] = { 2190 /* RTS, CTS */ 2191 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3), 2192 }; 2193 static const unsigned int hscif1_ctrl_b_mux[] = { 2194 HRTS1_N_B_MARK, HCTS1_N_B_MARK, 2195 }; 2196 /* - HSCIF2 ----------------------------------------------------------------- */ 2197 static const unsigned int hscif2_data_a_pins[] = { 2198 /* RX, TX */ 2199 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), 2200 }; 2201 static const unsigned int hscif2_data_a_mux[] = { 2202 HRX2_A_MARK, HTX2_A_MARK, 2203 }; 2204 static const unsigned int hscif2_clk_a_pins[] = { 2205 /* SCK */ 2206 RCAR_GP_PIN(6, 10), 2207 }; 2208 static const unsigned int hscif2_clk_a_mux[] = { 2209 HSCK2_A_MARK, 2210 }; 2211 static const unsigned int hscif2_ctrl_a_pins[] = { 2212 /* RTS, CTS */ 2213 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6), 2214 }; 2215 static const unsigned int hscif2_ctrl_a_mux[] = { 2216 HRTS2_N_A_MARK, HCTS2_N_A_MARK, 2217 }; 2218 2219 static const unsigned int hscif2_data_b_pins[] = { 2220 /* RX, TX */ 2221 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18), 2222 }; 2223 static const unsigned int hscif2_data_b_mux[] = { 2224 HRX2_B_MARK, HTX2_B_MARK, 2225 }; 2226 static const unsigned int hscif2_clk_b_pins[] = { 2227 /* SCK */ 2228 RCAR_GP_PIN(6, 21), 2229 }; 2230 static const unsigned int hscif2_clk_b_mux[] = { 2231 HSCK2_B_MARK, 2232 }; 2233 static const unsigned int hscif2_ctrl_b_pins[] = { 2234 /* RTS, CTS */ 2235 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19), 2236 }; 2237 static const unsigned int hscif2_ctrl_b_mux[] = { 2238 HRTS2_N_B_MARK, HCTS2_N_B_MARK, 2239 }; 2240 2241 static const unsigned int hscif2_data_c_pins[] = { 2242 /* RX, TX */ 2243 RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26), 2244 }; 2245 static const unsigned int hscif2_data_c_mux[] = { 2246 HRX2_C_MARK, HTX2_C_MARK, 2247 }; 2248 static const unsigned int hscif2_clk_c_pins[] = { 2249 /* SCK */ 2250 RCAR_GP_PIN(6, 24), 2251 }; 2252 static const unsigned int hscif2_clk_c_mux[] = { 2253 HSCK2_C_MARK, 2254 }; 2255 static const unsigned int hscif2_ctrl_c_pins[] = { 2256 /* RTS, CTS */ 2257 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 27), 2258 }; 2259 static const unsigned int hscif2_ctrl_c_mux[] = { 2260 HRTS2_N_C_MARK, HCTS2_N_C_MARK, 2261 }; 2262 /* - HSCIF3 ----------------------------------------------------------------- */ 2263 static const unsigned int hscif3_data_a_pins[] = { 2264 /* RX, TX */ 2265 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24), 2266 }; 2267 static const unsigned int hscif3_data_a_mux[] = { 2268 HRX3_A_MARK, HTX3_A_MARK, 2269 }; 2270 static const unsigned int hscif3_clk_pins[] = { 2271 /* SCK */ 2272 RCAR_GP_PIN(1, 22), 2273 }; 2274 static const unsigned int hscif3_clk_mux[] = { 2275 HSCK3_MARK, 2276 }; 2277 static const unsigned int hscif3_ctrl_pins[] = { 2278 /* RTS, CTS */ 2279 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25), 2280 }; 2281 static const unsigned int hscif3_ctrl_mux[] = { 2282 HRTS3_N_MARK, HCTS3_N_MARK, 2283 }; 2284 2285 static const unsigned int hscif3_data_b_pins[] = { 2286 /* RX, TX */ 2287 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), 2288 }; 2289 static const unsigned int hscif3_data_b_mux[] = { 2290 HRX3_B_MARK, HTX3_B_MARK, 2291 }; 2292 static const unsigned int hscif3_data_c_pins[] = { 2293 /* RX, TX */ 2294 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), 2295 }; 2296 static const unsigned int hscif3_data_c_mux[] = { 2297 HRX3_C_MARK, HTX3_C_MARK, 2298 }; 2299 static const unsigned int hscif3_data_d_pins[] = { 2300 /* RX, TX */ 2301 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), 2302 }; 2303 static const unsigned int hscif3_data_d_mux[] = { 2304 HRX3_D_MARK, HTX3_D_MARK, 2305 }; 2306 /* - HSCIF4 ----------------------------------------------------------------- */ 2307 static const unsigned int hscif4_data_a_pins[] = { 2308 /* RX, TX */ 2309 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), 2310 }; 2311 static const unsigned int hscif4_data_a_mux[] = { 2312 HRX4_A_MARK, HTX4_A_MARK, 2313 }; 2314 static const unsigned int hscif4_clk_pins[] = { 2315 /* SCK */ 2316 RCAR_GP_PIN(1, 11), 2317 }; 2318 static const unsigned int hscif4_clk_mux[] = { 2319 HSCK4_MARK, 2320 }; 2321 static const unsigned int hscif4_ctrl_pins[] = { 2322 /* RTS, CTS */ 2323 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), 2324 }; 2325 static const unsigned int hscif4_ctrl_mux[] = { 2326 HRTS4_N_MARK, HCTS4_N_MARK, 2327 }; 2328 2329 static const unsigned int hscif4_data_b_pins[] = { 2330 /* RX, TX */ 2331 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), 2332 }; 2333 static const unsigned int hscif4_data_b_mux[] = { 2334 HRX4_B_MARK, HTX4_B_MARK, 2335 }; 2336 2337 /* - I2C -------------------------------------------------------------------- */ 2338 static const unsigned int i2c0_pins[] = { 2339 /* SCL, SDA */ 2340 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), 2341 }; 2342 2343 static const unsigned int i2c0_mux[] = { 2344 SCL0_MARK, SDA0_MARK, 2345 }; 2346 2347 static const unsigned int i2c1_a_pins[] = { 2348 /* SDA, SCL */ 2349 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10), 2350 }; 2351 static const unsigned int i2c1_a_mux[] = { 2352 SDA1_A_MARK, SCL1_A_MARK, 2353 }; 2354 static const unsigned int i2c1_b_pins[] = { 2355 /* SDA, SCL */ 2356 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23), 2357 }; 2358 static const unsigned int i2c1_b_mux[] = { 2359 SDA1_B_MARK, SCL1_B_MARK, 2360 }; 2361 static const unsigned int i2c2_a_pins[] = { 2362 /* SDA, SCL */ 2363 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4), 2364 }; 2365 static const unsigned int i2c2_a_mux[] = { 2366 SDA2_A_MARK, SCL2_A_MARK, 2367 }; 2368 static const unsigned int i2c2_b_pins[] = { 2369 /* SDA, SCL */ 2370 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12), 2371 }; 2372 static const unsigned int i2c2_b_mux[] = { 2373 SDA2_B_MARK, SCL2_B_MARK, 2374 }; 2375 2376 static const unsigned int i2c3_pins[] = { 2377 /* SCL, SDA */ 2378 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), 2379 }; 2380 2381 static const unsigned int i2c3_mux[] = { 2382 SCL3_MARK, SDA3_MARK, 2383 }; 2384 2385 static const unsigned int i2c5_pins[] = { 2386 /* SCL, SDA */ 2387 RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14), 2388 }; 2389 2390 static const unsigned int i2c5_mux[] = { 2391 SCL5_MARK, SDA5_MARK, 2392 }; 2393 2394 static const unsigned int i2c6_a_pins[] = { 2395 /* SDA, SCL */ 2396 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), 2397 }; 2398 static const unsigned int i2c6_a_mux[] = { 2399 SDA6_A_MARK, SCL6_A_MARK, 2400 }; 2401 static const unsigned int i2c6_b_pins[] = { 2402 /* SDA, SCL */ 2403 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25), 2404 }; 2405 static const unsigned int i2c6_b_mux[] = { 2406 SDA6_B_MARK, SCL6_B_MARK, 2407 }; 2408 static const unsigned int i2c6_c_pins[] = { 2409 /* SDA, SCL */ 2410 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), 2411 }; 2412 static const unsigned int i2c6_c_mux[] = { 2413 SDA6_C_MARK, SCL6_C_MARK, 2414 }; 2415 2416 /* - INTC-EX ---------------------------------------------------------------- */ 2417 static const unsigned int intc_ex_irq0_pins[] = { 2418 /* IRQ0 */ 2419 RCAR_GP_PIN(2, 0), 2420 }; 2421 static const unsigned int intc_ex_irq0_mux[] = { 2422 IRQ0_MARK, 2423 }; 2424 static const unsigned int intc_ex_irq1_pins[] = { 2425 /* IRQ1 */ 2426 RCAR_GP_PIN(2, 1), 2427 }; 2428 static const unsigned int intc_ex_irq1_mux[] = { 2429 IRQ1_MARK, 2430 }; 2431 static const unsigned int intc_ex_irq2_pins[] = { 2432 /* IRQ2 */ 2433 RCAR_GP_PIN(2, 2), 2434 }; 2435 static const unsigned int intc_ex_irq2_mux[] = { 2436 IRQ2_MARK, 2437 }; 2438 static const unsigned int intc_ex_irq3_pins[] = { 2439 /* IRQ3 */ 2440 RCAR_GP_PIN(2, 3), 2441 }; 2442 static const unsigned int intc_ex_irq3_mux[] = { 2443 IRQ3_MARK, 2444 }; 2445 static const unsigned int intc_ex_irq4_pins[] = { 2446 /* IRQ4 */ 2447 RCAR_GP_PIN(2, 4), 2448 }; 2449 static const unsigned int intc_ex_irq4_mux[] = { 2450 IRQ4_MARK, 2451 }; 2452 static const unsigned int intc_ex_irq5_pins[] = { 2453 /* IRQ5 */ 2454 RCAR_GP_PIN(2, 5), 2455 }; 2456 static const unsigned int intc_ex_irq5_mux[] = { 2457 IRQ5_MARK, 2458 }; 2459 2460 /* - MSIOF0 ----------------------------------------------------------------- */ 2461 static const unsigned int msiof0_clk_pins[] = { 2462 /* SCK */ 2463 RCAR_GP_PIN(5, 17), 2464 }; 2465 static const unsigned int msiof0_clk_mux[] = { 2466 MSIOF0_SCK_MARK, 2467 }; 2468 static const unsigned int msiof0_sync_pins[] = { 2469 /* SYNC */ 2470 RCAR_GP_PIN(5, 18), 2471 }; 2472 static const unsigned int msiof0_sync_mux[] = { 2473 MSIOF0_SYNC_MARK, 2474 }; 2475 static const unsigned int msiof0_ss1_pins[] = { 2476 /* SS1 */ 2477 RCAR_GP_PIN(5, 19), 2478 }; 2479 static const unsigned int msiof0_ss1_mux[] = { 2480 MSIOF0_SS1_MARK, 2481 }; 2482 static const unsigned int msiof0_ss2_pins[] = { 2483 /* SS2 */ 2484 RCAR_GP_PIN(5, 21), 2485 }; 2486 static const unsigned int msiof0_ss2_mux[] = { 2487 MSIOF0_SS2_MARK, 2488 }; 2489 static const unsigned int msiof0_txd_pins[] = { 2490 /* TXD */ 2491 RCAR_GP_PIN(5, 20), 2492 }; 2493 static const unsigned int msiof0_txd_mux[] = { 2494 MSIOF0_TXD_MARK, 2495 }; 2496 static const unsigned int msiof0_rxd_pins[] = { 2497 /* RXD */ 2498 RCAR_GP_PIN(5, 22), 2499 }; 2500 static const unsigned int msiof0_rxd_mux[] = { 2501 MSIOF0_RXD_MARK, 2502 }; 2503 /* - MSIOF1 ----------------------------------------------------------------- */ 2504 static const unsigned int msiof1_clk_a_pins[] = { 2505 /* SCK */ 2506 RCAR_GP_PIN(6, 8), 2507 }; 2508 static const unsigned int msiof1_clk_a_mux[] = { 2509 MSIOF1_SCK_A_MARK, 2510 }; 2511 static const unsigned int msiof1_sync_a_pins[] = { 2512 /* SYNC */ 2513 RCAR_GP_PIN(6, 9), 2514 }; 2515 static const unsigned int msiof1_sync_a_mux[] = { 2516 MSIOF1_SYNC_A_MARK, 2517 }; 2518 static const unsigned int msiof1_ss1_a_pins[] = { 2519 /* SS1 */ 2520 RCAR_GP_PIN(6, 5), 2521 }; 2522 static const unsigned int msiof1_ss1_a_mux[] = { 2523 MSIOF1_SS1_A_MARK, 2524 }; 2525 static const unsigned int msiof1_ss2_a_pins[] = { 2526 /* SS2 */ 2527 RCAR_GP_PIN(6, 6), 2528 }; 2529 static const unsigned int msiof1_ss2_a_mux[] = { 2530 MSIOF1_SS2_A_MARK, 2531 }; 2532 static const unsigned int msiof1_txd_a_pins[] = { 2533 /* TXD */ 2534 RCAR_GP_PIN(6, 7), 2535 }; 2536 static const unsigned int msiof1_txd_a_mux[] = { 2537 MSIOF1_TXD_A_MARK, 2538 }; 2539 static const unsigned int msiof1_rxd_a_pins[] = { 2540 /* RXD */ 2541 RCAR_GP_PIN(6, 10), 2542 }; 2543 static const unsigned int msiof1_rxd_a_mux[] = { 2544 MSIOF1_RXD_A_MARK, 2545 }; 2546 static const unsigned int msiof1_clk_b_pins[] = { 2547 /* SCK */ 2548 RCAR_GP_PIN(5, 9), 2549 }; 2550 static const unsigned int msiof1_clk_b_mux[] = { 2551 MSIOF1_SCK_B_MARK, 2552 }; 2553 static const unsigned int msiof1_sync_b_pins[] = { 2554 /* SYNC */ 2555 RCAR_GP_PIN(5, 3), 2556 }; 2557 static const unsigned int msiof1_sync_b_mux[] = { 2558 MSIOF1_SYNC_B_MARK, 2559 }; 2560 static const unsigned int msiof1_ss1_b_pins[] = { 2561 /* SS1 */ 2562 RCAR_GP_PIN(5, 4), 2563 }; 2564 static const unsigned int msiof1_ss1_b_mux[] = { 2565 MSIOF1_SS1_B_MARK, 2566 }; 2567 static const unsigned int msiof1_ss2_b_pins[] = { 2568 /* SS2 */ 2569 RCAR_GP_PIN(5, 0), 2570 }; 2571 static const unsigned int msiof1_ss2_b_mux[] = { 2572 MSIOF1_SS2_B_MARK, 2573 }; 2574 static const unsigned int msiof1_txd_b_pins[] = { 2575 /* TXD */ 2576 RCAR_GP_PIN(5, 8), 2577 }; 2578 static const unsigned int msiof1_txd_b_mux[] = { 2579 MSIOF1_TXD_B_MARK, 2580 }; 2581 static const unsigned int msiof1_rxd_b_pins[] = { 2582 /* RXD */ 2583 RCAR_GP_PIN(5, 7), 2584 }; 2585 static const unsigned int msiof1_rxd_b_mux[] = { 2586 MSIOF1_RXD_B_MARK, 2587 }; 2588 static const unsigned int msiof1_clk_c_pins[] = { 2589 /* SCK */ 2590 RCAR_GP_PIN(6, 17), 2591 }; 2592 static const unsigned int msiof1_clk_c_mux[] = { 2593 MSIOF1_SCK_C_MARK, 2594 }; 2595 static const unsigned int msiof1_sync_c_pins[] = { 2596 /* SYNC */ 2597 RCAR_GP_PIN(6, 18), 2598 }; 2599 static const unsigned int msiof1_sync_c_mux[] = { 2600 MSIOF1_SYNC_C_MARK, 2601 }; 2602 static const unsigned int msiof1_ss1_c_pins[] = { 2603 /* SS1 */ 2604 RCAR_GP_PIN(6, 21), 2605 }; 2606 static const unsigned int msiof1_ss1_c_mux[] = { 2607 MSIOF1_SS1_C_MARK, 2608 }; 2609 static const unsigned int msiof1_ss2_c_pins[] = { 2610 /* SS2 */ 2611 RCAR_GP_PIN(6, 27), 2612 }; 2613 static const unsigned int msiof1_ss2_c_mux[] = { 2614 MSIOF1_SS2_C_MARK, 2615 }; 2616 static const unsigned int msiof1_txd_c_pins[] = { 2617 /* TXD */ 2618 RCAR_GP_PIN(6, 20), 2619 }; 2620 static const unsigned int msiof1_txd_c_mux[] = { 2621 MSIOF1_TXD_C_MARK, 2622 }; 2623 static const unsigned int msiof1_rxd_c_pins[] = { 2624 /* RXD */ 2625 RCAR_GP_PIN(6, 19), 2626 }; 2627 static const unsigned int msiof1_rxd_c_mux[] = { 2628 MSIOF1_RXD_C_MARK, 2629 }; 2630 static const unsigned int msiof1_clk_d_pins[] = { 2631 /* SCK */ 2632 RCAR_GP_PIN(5, 12), 2633 }; 2634 static const unsigned int msiof1_clk_d_mux[] = { 2635 MSIOF1_SCK_D_MARK, 2636 }; 2637 static const unsigned int msiof1_sync_d_pins[] = { 2638 /* SYNC */ 2639 RCAR_GP_PIN(5, 15), 2640 }; 2641 static const unsigned int msiof1_sync_d_mux[] = { 2642 MSIOF1_SYNC_D_MARK, 2643 }; 2644 static const unsigned int msiof1_ss1_d_pins[] = { 2645 /* SS1 */ 2646 RCAR_GP_PIN(5, 16), 2647 }; 2648 static const unsigned int msiof1_ss1_d_mux[] = { 2649 MSIOF1_SS1_D_MARK, 2650 }; 2651 static const unsigned int msiof1_ss2_d_pins[] = { 2652 /* SS2 */ 2653 RCAR_GP_PIN(5, 21), 2654 }; 2655 static const unsigned int msiof1_ss2_d_mux[] = { 2656 MSIOF1_SS2_D_MARK, 2657 }; 2658 static const unsigned int msiof1_txd_d_pins[] = { 2659 /* TXD */ 2660 RCAR_GP_PIN(5, 14), 2661 }; 2662 static const unsigned int msiof1_txd_d_mux[] = { 2663 MSIOF1_TXD_D_MARK, 2664 }; 2665 static const unsigned int msiof1_rxd_d_pins[] = { 2666 /* RXD */ 2667 RCAR_GP_PIN(5, 13), 2668 }; 2669 static const unsigned int msiof1_rxd_d_mux[] = { 2670 MSIOF1_RXD_D_MARK, 2671 }; 2672 static const unsigned int msiof1_clk_e_pins[] = { 2673 /* SCK */ 2674 RCAR_GP_PIN(3, 0), 2675 }; 2676 static const unsigned int msiof1_clk_e_mux[] = { 2677 MSIOF1_SCK_E_MARK, 2678 }; 2679 static const unsigned int msiof1_sync_e_pins[] = { 2680 /* SYNC */ 2681 RCAR_GP_PIN(3, 1), 2682 }; 2683 static const unsigned int msiof1_sync_e_mux[] = { 2684 MSIOF1_SYNC_E_MARK, 2685 }; 2686 static const unsigned int msiof1_ss1_e_pins[] = { 2687 /* SS1 */ 2688 RCAR_GP_PIN(3, 4), 2689 }; 2690 static const unsigned int msiof1_ss1_e_mux[] = { 2691 MSIOF1_SS1_E_MARK, 2692 }; 2693 static const unsigned int msiof1_ss2_e_pins[] = { 2694 /* SS2 */ 2695 RCAR_GP_PIN(3, 5), 2696 }; 2697 static const unsigned int msiof1_ss2_e_mux[] = { 2698 MSIOF1_SS2_E_MARK, 2699 }; 2700 static const unsigned int msiof1_txd_e_pins[] = { 2701 /* TXD */ 2702 RCAR_GP_PIN(3, 3), 2703 }; 2704 static const unsigned int msiof1_txd_e_mux[] = { 2705 MSIOF1_TXD_E_MARK, 2706 }; 2707 static const unsigned int msiof1_rxd_e_pins[] = { 2708 /* RXD */ 2709 RCAR_GP_PIN(3, 2), 2710 }; 2711 static const unsigned int msiof1_rxd_e_mux[] = { 2712 MSIOF1_RXD_E_MARK, 2713 }; 2714 static const unsigned int msiof1_clk_f_pins[] = { 2715 /* SCK */ 2716 RCAR_GP_PIN(5, 23), 2717 }; 2718 static const unsigned int msiof1_clk_f_mux[] = { 2719 MSIOF1_SCK_F_MARK, 2720 }; 2721 static const unsigned int msiof1_sync_f_pins[] = { 2722 /* SYNC */ 2723 RCAR_GP_PIN(5, 24), 2724 }; 2725 static const unsigned int msiof1_sync_f_mux[] = { 2726 MSIOF1_SYNC_F_MARK, 2727 }; 2728 static const unsigned int msiof1_ss1_f_pins[] = { 2729 /* SS1 */ 2730 RCAR_GP_PIN(6, 1), 2731 }; 2732 static const unsigned int msiof1_ss1_f_mux[] = { 2733 MSIOF1_SS1_F_MARK, 2734 }; 2735 static const unsigned int msiof1_ss2_f_pins[] = { 2736 /* SS2 */ 2737 RCAR_GP_PIN(6, 2), 2738 }; 2739 static const unsigned int msiof1_ss2_f_mux[] = { 2740 MSIOF1_SS2_F_MARK, 2741 }; 2742 static const unsigned int msiof1_txd_f_pins[] = { 2743 /* TXD */ 2744 RCAR_GP_PIN(6, 0), 2745 }; 2746 static const unsigned int msiof1_txd_f_mux[] = { 2747 MSIOF1_TXD_F_MARK, 2748 }; 2749 static const unsigned int msiof1_rxd_f_pins[] = { 2750 /* RXD */ 2751 RCAR_GP_PIN(5, 25), 2752 }; 2753 static const unsigned int msiof1_rxd_f_mux[] = { 2754 MSIOF1_RXD_F_MARK, 2755 }; 2756 static const unsigned int msiof1_clk_g_pins[] = { 2757 /* SCK */ 2758 RCAR_GP_PIN(3, 6), 2759 }; 2760 static const unsigned int msiof1_clk_g_mux[] = { 2761 MSIOF1_SCK_G_MARK, 2762 }; 2763 static const unsigned int msiof1_sync_g_pins[] = { 2764 /* SYNC */ 2765 RCAR_GP_PIN(3, 7), 2766 }; 2767 static const unsigned int msiof1_sync_g_mux[] = { 2768 MSIOF1_SYNC_G_MARK, 2769 }; 2770 static const unsigned int msiof1_ss1_g_pins[] = { 2771 /* SS1 */ 2772 RCAR_GP_PIN(3, 10), 2773 }; 2774 static const unsigned int msiof1_ss1_g_mux[] = { 2775 MSIOF1_SS1_G_MARK, 2776 }; 2777 static const unsigned int msiof1_ss2_g_pins[] = { 2778 /* SS2 */ 2779 RCAR_GP_PIN(3, 11), 2780 }; 2781 static const unsigned int msiof1_ss2_g_mux[] = { 2782 MSIOF1_SS2_G_MARK, 2783 }; 2784 static const unsigned int msiof1_txd_g_pins[] = { 2785 /* TXD */ 2786 RCAR_GP_PIN(3, 9), 2787 }; 2788 static const unsigned int msiof1_txd_g_mux[] = { 2789 MSIOF1_TXD_G_MARK, 2790 }; 2791 static const unsigned int msiof1_rxd_g_pins[] = { 2792 /* RXD */ 2793 RCAR_GP_PIN(3, 8), 2794 }; 2795 static const unsigned int msiof1_rxd_g_mux[] = { 2796 MSIOF1_RXD_G_MARK, 2797 }; 2798 /* - MSIOF2 ----------------------------------------------------------------- */ 2799 static const unsigned int msiof2_clk_a_pins[] = { 2800 /* SCK */ 2801 RCAR_GP_PIN(1, 9), 2802 }; 2803 static const unsigned int msiof2_clk_a_mux[] = { 2804 MSIOF2_SCK_A_MARK, 2805 }; 2806 static const unsigned int msiof2_sync_a_pins[] = { 2807 /* SYNC */ 2808 RCAR_GP_PIN(1, 8), 2809 }; 2810 static const unsigned int msiof2_sync_a_mux[] = { 2811 MSIOF2_SYNC_A_MARK, 2812 }; 2813 static const unsigned int msiof2_ss1_a_pins[] = { 2814 /* SS1 */ 2815 RCAR_GP_PIN(1, 6), 2816 }; 2817 static const unsigned int msiof2_ss1_a_mux[] = { 2818 MSIOF2_SS1_A_MARK, 2819 }; 2820 static const unsigned int msiof2_ss2_a_pins[] = { 2821 /* SS2 */ 2822 RCAR_GP_PIN(1, 7), 2823 }; 2824 static const unsigned int msiof2_ss2_a_mux[] = { 2825 MSIOF2_SS2_A_MARK, 2826 }; 2827 static const unsigned int msiof2_txd_a_pins[] = { 2828 /* TXD */ 2829 RCAR_GP_PIN(1, 11), 2830 }; 2831 static const unsigned int msiof2_txd_a_mux[] = { 2832 MSIOF2_TXD_A_MARK, 2833 }; 2834 static const unsigned int msiof2_rxd_a_pins[] = { 2835 /* RXD */ 2836 RCAR_GP_PIN(1, 10), 2837 }; 2838 static const unsigned int msiof2_rxd_a_mux[] = { 2839 MSIOF2_RXD_A_MARK, 2840 }; 2841 static const unsigned int msiof2_clk_b_pins[] = { 2842 /* SCK */ 2843 RCAR_GP_PIN(0, 4), 2844 }; 2845 static const unsigned int msiof2_clk_b_mux[] = { 2846 MSIOF2_SCK_B_MARK, 2847 }; 2848 static const unsigned int msiof2_sync_b_pins[] = { 2849 /* SYNC */ 2850 RCAR_GP_PIN(0, 5), 2851 }; 2852 static const unsigned int msiof2_sync_b_mux[] = { 2853 MSIOF2_SYNC_B_MARK, 2854 }; 2855 static const unsigned int msiof2_ss1_b_pins[] = { 2856 /* SS1 */ 2857 RCAR_GP_PIN(0, 0), 2858 }; 2859 static const unsigned int msiof2_ss1_b_mux[] = { 2860 MSIOF2_SS1_B_MARK, 2861 }; 2862 static const unsigned int msiof2_ss2_b_pins[] = { 2863 /* SS2 */ 2864 RCAR_GP_PIN(0, 1), 2865 }; 2866 static const unsigned int msiof2_ss2_b_mux[] = { 2867 MSIOF2_SS2_B_MARK, 2868 }; 2869 static const unsigned int msiof2_txd_b_pins[] = { 2870 /* TXD */ 2871 RCAR_GP_PIN(0, 7), 2872 }; 2873 static const unsigned int msiof2_txd_b_mux[] = { 2874 MSIOF2_TXD_B_MARK, 2875 }; 2876 static const unsigned int msiof2_rxd_b_pins[] = { 2877 /* RXD */ 2878 RCAR_GP_PIN(0, 6), 2879 }; 2880 static const unsigned int msiof2_rxd_b_mux[] = { 2881 MSIOF2_RXD_B_MARK, 2882 }; 2883 static const unsigned int msiof2_clk_c_pins[] = { 2884 /* SCK */ 2885 RCAR_GP_PIN(2, 12), 2886 }; 2887 static const unsigned int msiof2_clk_c_mux[] = { 2888 MSIOF2_SCK_C_MARK, 2889 }; 2890 static const unsigned int msiof2_sync_c_pins[] = { 2891 /* SYNC */ 2892 RCAR_GP_PIN(2, 11), 2893 }; 2894 static const unsigned int msiof2_sync_c_mux[] = { 2895 MSIOF2_SYNC_C_MARK, 2896 }; 2897 static const unsigned int msiof2_ss1_c_pins[] = { 2898 /* SS1 */ 2899 RCAR_GP_PIN(2, 10), 2900 }; 2901 static const unsigned int msiof2_ss1_c_mux[] = { 2902 MSIOF2_SS1_C_MARK, 2903 }; 2904 static const unsigned int msiof2_ss2_c_pins[] = { 2905 /* SS2 */ 2906 RCAR_GP_PIN(2, 9), 2907 }; 2908 static const unsigned int msiof2_ss2_c_mux[] = { 2909 MSIOF2_SS2_C_MARK, 2910 }; 2911 static const unsigned int msiof2_txd_c_pins[] = { 2912 /* TXD */ 2913 RCAR_GP_PIN(2, 14), 2914 }; 2915 static const unsigned int msiof2_txd_c_mux[] = { 2916 MSIOF2_TXD_C_MARK, 2917 }; 2918 static const unsigned int msiof2_rxd_c_pins[] = { 2919 /* RXD */ 2920 RCAR_GP_PIN(2, 13), 2921 }; 2922 static const unsigned int msiof2_rxd_c_mux[] = { 2923 MSIOF2_RXD_C_MARK, 2924 }; 2925 static const unsigned int msiof2_clk_d_pins[] = { 2926 /* SCK */ 2927 RCAR_GP_PIN(0, 8), 2928 }; 2929 static const unsigned int msiof2_clk_d_mux[] = { 2930 MSIOF2_SCK_D_MARK, 2931 }; 2932 static const unsigned int msiof2_sync_d_pins[] = { 2933 /* SYNC */ 2934 RCAR_GP_PIN(0, 9), 2935 }; 2936 static const unsigned int msiof2_sync_d_mux[] = { 2937 MSIOF2_SYNC_D_MARK, 2938 }; 2939 static const unsigned int msiof2_ss1_d_pins[] = { 2940 /* SS1 */ 2941 RCAR_GP_PIN(0, 12), 2942 }; 2943 static const unsigned int msiof2_ss1_d_mux[] = { 2944 MSIOF2_SS1_D_MARK, 2945 }; 2946 static const unsigned int msiof2_ss2_d_pins[] = { 2947 /* SS2 */ 2948 RCAR_GP_PIN(0, 13), 2949 }; 2950 static const unsigned int msiof2_ss2_d_mux[] = { 2951 MSIOF2_SS2_D_MARK, 2952 }; 2953 static const unsigned int msiof2_txd_d_pins[] = { 2954 /* TXD */ 2955 RCAR_GP_PIN(0, 11), 2956 }; 2957 static const unsigned int msiof2_txd_d_mux[] = { 2958 MSIOF2_TXD_D_MARK, 2959 }; 2960 static const unsigned int msiof2_rxd_d_pins[] = { 2961 /* RXD */ 2962 RCAR_GP_PIN(0, 10), 2963 }; 2964 static const unsigned int msiof2_rxd_d_mux[] = { 2965 MSIOF2_RXD_D_MARK, 2966 }; 2967 /* - MSIOF3 ----------------------------------------------------------------- */ 2968 static const unsigned int msiof3_clk_a_pins[] = { 2969 /* SCK */ 2970 RCAR_GP_PIN(0, 0), 2971 }; 2972 static const unsigned int msiof3_clk_a_mux[] = { 2973 MSIOF3_SCK_A_MARK, 2974 }; 2975 static const unsigned int msiof3_sync_a_pins[] = { 2976 /* SYNC */ 2977 RCAR_GP_PIN(0, 1), 2978 }; 2979 static const unsigned int msiof3_sync_a_mux[] = { 2980 MSIOF3_SYNC_A_MARK, 2981 }; 2982 static const unsigned int msiof3_ss1_a_pins[] = { 2983 /* SS1 */ 2984 RCAR_GP_PIN(0, 14), 2985 }; 2986 static const unsigned int msiof3_ss1_a_mux[] = { 2987 MSIOF3_SS1_A_MARK, 2988 }; 2989 static const unsigned int msiof3_ss2_a_pins[] = { 2990 /* SS2 */ 2991 RCAR_GP_PIN(0, 15), 2992 }; 2993 static const unsigned int msiof3_ss2_a_mux[] = { 2994 MSIOF3_SS2_A_MARK, 2995 }; 2996 static const unsigned int msiof3_txd_a_pins[] = { 2997 /* TXD */ 2998 RCAR_GP_PIN(0, 3), 2999 }; 3000 static const unsigned int msiof3_txd_a_mux[] = { 3001 MSIOF3_TXD_A_MARK, 3002 }; 3003 static const unsigned int msiof3_rxd_a_pins[] = { 3004 /* RXD */ 3005 RCAR_GP_PIN(0, 2), 3006 }; 3007 static const unsigned int msiof3_rxd_a_mux[] = { 3008 MSIOF3_RXD_A_MARK, 3009 }; 3010 static const unsigned int msiof3_clk_b_pins[] = { 3011 /* SCK */ 3012 RCAR_GP_PIN(1, 2), 3013 }; 3014 static const unsigned int msiof3_clk_b_mux[] = { 3015 MSIOF3_SCK_B_MARK, 3016 }; 3017 static const unsigned int msiof3_sync_b_pins[] = { 3018 /* SYNC */ 3019 RCAR_GP_PIN(1, 0), 3020 }; 3021 static const unsigned int msiof3_sync_b_mux[] = { 3022 MSIOF3_SYNC_B_MARK, 3023 }; 3024 static const unsigned int msiof3_ss1_b_pins[] = { 3025 /* SS1 */ 3026 RCAR_GP_PIN(1, 4), 3027 }; 3028 static const unsigned int msiof3_ss1_b_mux[] = { 3029 MSIOF3_SS1_B_MARK, 3030 }; 3031 static const unsigned int msiof3_ss2_b_pins[] = { 3032 /* SS2 */ 3033 RCAR_GP_PIN(1, 5), 3034 }; 3035 static const unsigned int msiof3_ss2_b_mux[] = { 3036 MSIOF3_SS2_B_MARK, 3037 }; 3038 static const unsigned int msiof3_txd_b_pins[] = { 3039 /* TXD */ 3040 RCAR_GP_PIN(1, 1), 3041 }; 3042 static const unsigned int msiof3_txd_b_mux[] = { 3043 MSIOF3_TXD_B_MARK, 3044 }; 3045 static const unsigned int msiof3_rxd_b_pins[] = { 3046 /* RXD */ 3047 RCAR_GP_PIN(1, 3), 3048 }; 3049 static const unsigned int msiof3_rxd_b_mux[] = { 3050 MSIOF3_RXD_B_MARK, 3051 }; 3052 static const unsigned int msiof3_clk_c_pins[] = { 3053 /* SCK */ 3054 RCAR_GP_PIN(1, 12), 3055 }; 3056 static const unsigned int msiof3_clk_c_mux[] = { 3057 MSIOF3_SCK_C_MARK, 3058 }; 3059 static const unsigned int msiof3_sync_c_pins[] = { 3060 /* SYNC */ 3061 RCAR_GP_PIN(1, 13), 3062 }; 3063 static const unsigned int msiof3_sync_c_mux[] = { 3064 MSIOF3_SYNC_C_MARK, 3065 }; 3066 static const unsigned int msiof3_txd_c_pins[] = { 3067 /* TXD */ 3068 RCAR_GP_PIN(1, 15), 3069 }; 3070 static const unsigned int msiof3_txd_c_mux[] = { 3071 MSIOF3_TXD_C_MARK, 3072 }; 3073 static const unsigned int msiof3_rxd_c_pins[] = { 3074 /* RXD */ 3075 RCAR_GP_PIN(1, 14), 3076 }; 3077 static const unsigned int msiof3_rxd_c_mux[] = { 3078 MSIOF3_RXD_C_MARK, 3079 }; 3080 static const unsigned int msiof3_clk_d_pins[] = { 3081 /* SCK */ 3082 RCAR_GP_PIN(1, 22), 3083 }; 3084 static const unsigned int msiof3_clk_d_mux[] = { 3085 MSIOF3_SCK_D_MARK, 3086 }; 3087 static const unsigned int msiof3_sync_d_pins[] = { 3088 /* SYNC */ 3089 RCAR_GP_PIN(1, 23), 3090 }; 3091 static const unsigned int msiof3_sync_d_mux[] = { 3092 MSIOF3_SYNC_D_MARK, 3093 }; 3094 static const unsigned int msiof3_ss1_d_pins[] = { 3095 /* SS1 */ 3096 RCAR_GP_PIN(1, 26), 3097 }; 3098 static const unsigned int msiof3_ss1_d_mux[] = { 3099 MSIOF3_SS1_D_MARK, 3100 }; 3101 static const unsigned int msiof3_txd_d_pins[] = { 3102 /* TXD */ 3103 RCAR_GP_PIN(1, 25), 3104 }; 3105 static const unsigned int msiof3_txd_d_mux[] = { 3106 MSIOF3_TXD_D_MARK, 3107 }; 3108 static const unsigned int msiof3_rxd_d_pins[] = { 3109 /* RXD */ 3110 RCAR_GP_PIN(1, 24), 3111 }; 3112 static const unsigned int msiof3_rxd_d_mux[] = { 3113 MSIOF3_RXD_D_MARK, 3114 }; 3115 3116 static const unsigned int msiof3_clk_e_pins[] = { 3117 /* SCK */ 3118 RCAR_GP_PIN(2, 3), 3119 }; 3120 static const unsigned int msiof3_clk_e_mux[] = { 3121 MSIOF3_SCK_E_MARK, 3122 }; 3123 static const unsigned int msiof3_sync_e_pins[] = { 3124 /* SYNC */ 3125 RCAR_GP_PIN(2, 2), 3126 }; 3127 static const unsigned int msiof3_sync_e_mux[] = { 3128 MSIOF3_SYNC_E_MARK, 3129 }; 3130 static const unsigned int msiof3_ss1_e_pins[] = { 3131 /* SS1 */ 3132 RCAR_GP_PIN(2, 1), 3133 }; 3134 static const unsigned int msiof3_ss1_e_mux[] = { 3135 MSIOF3_SS1_E_MARK, 3136 }; 3137 static const unsigned int msiof3_ss2_e_pins[] = { 3138 /* SS2 */ 3139 RCAR_GP_PIN(2, 0), 3140 }; 3141 static const unsigned int msiof3_ss2_e_mux[] = { 3142 MSIOF3_SS2_E_MARK, 3143 }; 3144 static const unsigned int msiof3_txd_e_pins[] = { 3145 /* TXD */ 3146 RCAR_GP_PIN(2, 5), 3147 }; 3148 static const unsigned int msiof3_txd_e_mux[] = { 3149 MSIOF3_TXD_E_MARK, 3150 }; 3151 static const unsigned int msiof3_rxd_e_pins[] = { 3152 /* RXD */ 3153 RCAR_GP_PIN(2, 4), 3154 }; 3155 static const unsigned int msiof3_rxd_e_mux[] = { 3156 MSIOF3_RXD_E_MARK, 3157 }; 3158 3159 /* - PWM0 --------------------------------------------------------------------*/ 3160 static const unsigned int pwm0_pins[] = { 3161 /* PWM */ 3162 RCAR_GP_PIN(2, 6), 3163 }; 3164 static const unsigned int pwm0_mux[] = { 3165 PWM0_MARK, 3166 }; 3167 /* - PWM1 --------------------------------------------------------------------*/ 3168 static const unsigned int pwm1_a_pins[] = { 3169 /* PWM */ 3170 RCAR_GP_PIN(2, 7), 3171 }; 3172 static const unsigned int pwm1_a_mux[] = { 3173 PWM1_A_MARK, 3174 }; 3175 static const unsigned int pwm1_b_pins[] = { 3176 /* PWM */ 3177 RCAR_GP_PIN(1, 8), 3178 }; 3179 static const unsigned int pwm1_b_mux[] = { 3180 PWM1_B_MARK, 3181 }; 3182 /* - PWM2 --------------------------------------------------------------------*/ 3183 static const unsigned int pwm2_a_pins[] = { 3184 /* PWM */ 3185 RCAR_GP_PIN(2, 8), 3186 }; 3187 static const unsigned int pwm2_a_mux[] = { 3188 PWM2_A_MARK, 3189 }; 3190 static const unsigned int pwm2_b_pins[] = { 3191 /* PWM */ 3192 RCAR_GP_PIN(1, 11), 3193 }; 3194 static const unsigned int pwm2_b_mux[] = { 3195 PWM2_B_MARK, 3196 }; 3197 /* - PWM3 --------------------------------------------------------------------*/ 3198 static const unsigned int pwm3_a_pins[] = { 3199 /* PWM */ 3200 RCAR_GP_PIN(1, 0), 3201 }; 3202 static const unsigned int pwm3_a_mux[] = { 3203 PWM3_A_MARK, 3204 }; 3205 static const unsigned int pwm3_b_pins[] = { 3206 /* PWM */ 3207 RCAR_GP_PIN(2, 2), 3208 }; 3209 static const unsigned int pwm3_b_mux[] = { 3210 PWM3_B_MARK, 3211 }; 3212 /* - PWM4 --------------------------------------------------------------------*/ 3213 static const unsigned int pwm4_a_pins[] = { 3214 /* PWM */ 3215 RCAR_GP_PIN(1, 1), 3216 }; 3217 static const unsigned int pwm4_a_mux[] = { 3218 PWM4_A_MARK, 3219 }; 3220 static const unsigned int pwm4_b_pins[] = { 3221 /* PWM */ 3222 RCAR_GP_PIN(2, 3), 3223 }; 3224 static const unsigned int pwm4_b_mux[] = { 3225 PWM4_B_MARK, 3226 }; 3227 /* - PWM5 --------------------------------------------------------------------*/ 3228 static const unsigned int pwm5_a_pins[] = { 3229 /* PWM */ 3230 RCAR_GP_PIN(1, 2), 3231 }; 3232 static const unsigned int pwm5_a_mux[] = { 3233 PWM5_A_MARK, 3234 }; 3235 static const unsigned int pwm5_b_pins[] = { 3236 /* PWM */ 3237 RCAR_GP_PIN(2, 4), 3238 }; 3239 static const unsigned int pwm5_b_mux[] = { 3240 PWM5_B_MARK, 3241 }; 3242 /* - PWM6 --------------------------------------------------------------------*/ 3243 static const unsigned int pwm6_a_pins[] = { 3244 /* PWM */ 3245 RCAR_GP_PIN(1, 3), 3246 }; 3247 static const unsigned int pwm6_a_mux[] = { 3248 PWM6_A_MARK, 3249 }; 3250 static const unsigned int pwm6_b_pins[] = { 3251 /* PWM */ 3252 RCAR_GP_PIN(2, 5), 3253 }; 3254 static const unsigned int pwm6_b_mux[] = { 3255 PWM6_B_MARK, 3256 }; 3257 3258 /* - QSPI0 ------------------------------------------------------------------ */ 3259 static const unsigned int qspi0_ctrl_pins[] = { 3260 /* QSPI0_SPCLK, QSPI0_SSL */ 3261 PIN_QSPI0_SPCLK, PIN_QSPI0_SSL, 3262 }; 3263 static const unsigned int qspi0_ctrl_mux[] = { 3264 QSPI0_SPCLK_MARK, QSPI0_SSL_MARK, 3265 }; 3266 static const unsigned int qspi0_data2_pins[] = { 3267 /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */ 3268 PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1, 3269 }; 3270 static const unsigned int qspi0_data2_mux[] = { 3271 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, 3272 }; 3273 static const unsigned int qspi0_data4_pins[] = { 3274 /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */ 3275 PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1, 3276 /* QSPI0_IO2, QSPI0_IO3 */ 3277 PIN_QSPI0_IO2, PIN_QSPI0_IO3, 3278 }; 3279 static const unsigned int qspi0_data4_mux[] = { 3280 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, 3281 QSPI0_IO2_MARK, QSPI0_IO3_MARK, 3282 }; 3283 /* - QSPI1 ------------------------------------------------------------------ */ 3284 static const unsigned int qspi1_ctrl_pins[] = { 3285 /* QSPI1_SPCLK, QSPI1_SSL */ 3286 PIN_QSPI1_SPCLK, PIN_QSPI1_SSL, 3287 }; 3288 static const unsigned int qspi1_ctrl_mux[] = { 3289 QSPI1_SPCLK_MARK, QSPI1_SSL_MARK, 3290 }; 3291 static const unsigned int qspi1_data2_pins[] = { 3292 /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */ 3293 PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1, 3294 }; 3295 static const unsigned int qspi1_data2_mux[] = { 3296 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, 3297 }; 3298 static const unsigned int qspi1_data4_pins[] = { 3299 /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */ 3300 PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1, 3301 /* QSPI1_IO2, QSPI1_IO3 */ 3302 PIN_QSPI1_IO2, PIN_QSPI1_IO3, 3303 }; 3304 static const unsigned int qspi1_data4_mux[] = { 3305 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, 3306 QSPI1_IO2_MARK, QSPI1_IO3_MARK, 3307 }; 3308 3309 /* - SCIF0 ------------------------------------------------------------------ */ 3310 static const unsigned int scif0_data_pins[] = { 3311 /* RX, TX */ 3312 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), 3313 }; 3314 static const unsigned int scif0_data_mux[] = { 3315 RX0_MARK, TX0_MARK, 3316 }; 3317 static const unsigned int scif0_clk_pins[] = { 3318 /* SCK */ 3319 RCAR_GP_PIN(5, 0), 3320 }; 3321 static const unsigned int scif0_clk_mux[] = { 3322 SCK0_MARK, 3323 }; 3324 static const unsigned int scif0_ctrl_pins[] = { 3325 /* RTS, CTS */ 3326 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3), 3327 }; 3328 static const unsigned int scif0_ctrl_mux[] = { 3329 RTS0_N_MARK, CTS0_N_MARK, 3330 }; 3331 /* - SCIF1 ------------------------------------------------------------------ */ 3332 static const unsigned int scif1_data_a_pins[] = { 3333 /* RX, TX */ 3334 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6), 3335 }; 3336 static const unsigned int scif1_data_a_mux[] = { 3337 RX1_A_MARK, TX1_A_MARK, 3338 }; 3339 static const unsigned int scif1_clk_pins[] = { 3340 /* SCK */ 3341 RCAR_GP_PIN(6, 21), 3342 }; 3343 static const unsigned int scif1_clk_mux[] = { 3344 SCK1_MARK, 3345 }; 3346 static const unsigned int scif1_ctrl_pins[] = { 3347 /* RTS, CTS */ 3348 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7), 3349 }; 3350 static const unsigned int scif1_ctrl_mux[] = { 3351 RTS1_N_MARK, CTS1_N_MARK, 3352 }; 3353 3354 static const unsigned int scif1_data_b_pins[] = { 3355 /* RX, TX */ 3356 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25), 3357 }; 3358 static const unsigned int scif1_data_b_mux[] = { 3359 RX1_B_MARK, TX1_B_MARK, 3360 }; 3361 /* - SCIF2 ------------------------------------------------------------------ */ 3362 static const unsigned int scif2_data_a_pins[] = { 3363 /* RX, TX */ 3364 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10), 3365 }; 3366 static const unsigned int scif2_data_a_mux[] = { 3367 RX2_A_MARK, TX2_A_MARK, 3368 }; 3369 static const unsigned int scif2_clk_pins[] = { 3370 /* SCK */ 3371 RCAR_GP_PIN(5, 9), 3372 }; 3373 static const unsigned int scif2_clk_mux[] = { 3374 SCK2_MARK, 3375 }; 3376 static const unsigned int scif2_data_b_pins[] = { 3377 /* RX, TX */ 3378 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16), 3379 }; 3380 static const unsigned int scif2_data_b_mux[] = { 3381 RX2_B_MARK, TX2_B_MARK, 3382 }; 3383 /* - SCIF3 ------------------------------------------------------------------ */ 3384 static const unsigned int scif3_data_a_pins[] = { 3385 /* RX, TX */ 3386 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24), 3387 }; 3388 static const unsigned int scif3_data_a_mux[] = { 3389 RX3_A_MARK, TX3_A_MARK, 3390 }; 3391 static const unsigned int scif3_clk_pins[] = { 3392 /* SCK */ 3393 RCAR_GP_PIN(1, 22), 3394 }; 3395 static const unsigned int scif3_clk_mux[] = { 3396 SCK3_MARK, 3397 }; 3398 static const unsigned int scif3_ctrl_pins[] = { 3399 /* RTS, CTS */ 3400 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25), 3401 }; 3402 static const unsigned int scif3_ctrl_mux[] = { 3403 RTS3_N_MARK, CTS3_N_MARK, 3404 }; 3405 static const unsigned int scif3_data_b_pins[] = { 3406 /* RX, TX */ 3407 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), 3408 }; 3409 static const unsigned int scif3_data_b_mux[] = { 3410 RX3_B_MARK, TX3_B_MARK, 3411 }; 3412 /* - SCIF4 ------------------------------------------------------------------ */ 3413 static const unsigned int scif4_data_a_pins[] = { 3414 /* RX, TX */ 3415 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12), 3416 }; 3417 static const unsigned int scif4_data_a_mux[] = { 3418 RX4_A_MARK, TX4_A_MARK, 3419 }; 3420 static const unsigned int scif4_clk_a_pins[] = { 3421 /* SCK */ 3422 RCAR_GP_PIN(2, 10), 3423 }; 3424 static const unsigned int scif4_clk_a_mux[] = { 3425 SCK4_A_MARK, 3426 }; 3427 static const unsigned int scif4_ctrl_a_pins[] = { 3428 /* RTS, CTS */ 3429 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13), 3430 }; 3431 static const unsigned int scif4_ctrl_a_mux[] = { 3432 RTS4_N_A_MARK, CTS4_N_A_MARK, 3433 }; 3434 static const unsigned int scif4_data_b_pins[] = { 3435 /* RX, TX */ 3436 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 3437 }; 3438 static const unsigned int scif4_data_b_mux[] = { 3439 RX4_B_MARK, TX4_B_MARK, 3440 }; 3441 static const unsigned int scif4_clk_b_pins[] = { 3442 /* SCK */ 3443 RCAR_GP_PIN(1, 5), 3444 }; 3445 static const unsigned int scif4_clk_b_mux[] = { 3446 SCK4_B_MARK, 3447 }; 3448 static const unsigned int scif4_ctrl_b_pins[] = { 3449 /* RTS, CTS */ 3450 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9), 3451 }; 3452 static const unsigned int scif4_ctrl_b_mux[] = { 3453 RTS4_N_B_MARK, CTS4_N_B_MARK, 3454 }; 3455 static const unsigned int scif4_data_c_pins[] = { 3456 /* RX, TX */ 3457 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), 3458 }; 3459 static const unsigned int scif4_data_c_mux[] = { 3460 RX4_C_MARK, TX4_C_MARK, 3461 }; 3462 static const unsigned int scif4_clk_c_pins[] = { 3463 /* SCK */ 3464 RCAR_GP_PIN(0, 8), 3465 }; 3466 static const unsigned int scif4_clk_c_mux[] = { 3467 SCK4_C_MARK, 3468 }; 3469 static const unsigned int scif4_ctrl_c_pins[] = { 3470 /* RTS, CTS */ 3471 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), 3472 }; 3473 static const unsigned int scif4_ctrl_c_mux[] = { 3474 RTS4_N_C_MARK, CTS4_N_C_MARK, 3475 }; 3476 /* - SCIF5 ------------------------------------------------------------------ */ 3477 static const unsigned int scif5_data_a_pins[] = { 3478 /* RX, TX */ 3479 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21), 3480 }; 3481 static const unsigned int scif5_data_a_mux[] = { 3482 RX5_A_MARK, TX5_A_MARK, 3483 }; 3484 static const unsigned int scif5_clk_a_pins[] = { 3485 /* SCK */ 3486 RCAR_GP_PIN(6, 21), 3487 }; 3488 static const unsigned int scif5_clk_a_mux[] = { 3489 SCK5_A_MARK, 3490 }; 3491 3492 static const unsigned int scif5_data_b_pins[] = { 3493 /* RX, TX */ 3494 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18), 3495 }; 3496 static const unsigned int scif5_data_b_mux[] = { 3497 RX5_B_MARK, TX5_B_MARK, 3498 }; 3499 static const unsigned int scif5_clk_b_pins[] = { 3500 /* SCK */ 3501 RCAR_GP_PIN(5, 0), 3502 }; 3503 static const unsigned int scif5_clk_b_mux[] = { 3504 SCK5_B_MARK, 3505 }; 3506 3507 /* - SCIF Clock ------------------------------------------------------------- */ 3508 static const unsigned int scif_clk_a_pins[] = { 3509 /* SCIF_CLK */ 3510 RCAR_GP_PIN(6, 23), 3511 }; 3512 static const unsigned int scif_clk_a_mux[] = { 3513 SCIF_CLK_A_MARK, 3514 }; 3515 static const unsigned int scif_clk_b_pins[] = { 3516 /* SCIF_CLK */ 3517 RCAR_GP_PIN(5, 9), 3518 }; 3519 static const unsigned int scif_clk_b_mux[] = { 3520 SCIF_CLK_B_MARK, 3521 }; 3522 3523 /* - SDHI0 ------------------------------------------------------------------ */ 3524 static const unsigned int sdhi0_data1_pins[] = { 3525 /* D0 */ 3526 RCAR_GP_PIN(3, 2), 3527 }; 3528 static const unsigned int sdhi0_data1_mux[] = { 3529 SD0_DAT0_MARK, 3530 }; 3531 static const unsigned int sdhi0_data4_pins[] = { 3532 /* D[0:3] */ 3533 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), 3534 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), 3535 }; 3536 static const unsigned int sdhi0_data4_mux[] = { 3537 SD0_DAT0_MARK, SD0_DAT1_MARK, 3538 SD0_DAT2_MARK, SD0_DAT3_MARK, 3539 }; 3540 static const unsigned int sdhi0_ctrl_pins[] = { 3541 /* CLK, CMD */ 3542 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1), 3543 }; 3544 static const unsigned int sdhi0_ctrl_mux[] = { 3545 SD0_CLK_MARK, SD0_CMD_MARK, 3546 }; 3547 static const unsigned int sdhi0_cd_pins[] = { 3548 /* CD */ 3549 RCAR_GP_PIN(3, 12), 3550 }; 3551 static const unsigned int sdhi0_cd_mux[] = { 3552 SD0_CD_MARK, 3553 }; 3554 static const unsigned int sdhi0_wp_pins[] = { 3555 /* WP */ 3556 RCAR_GP_PIN(3, 13), 3557 }; 3558 static const unsigned int sdhi0_wp_mux[] = { 3559 SD0_WP_MARK, 3560 }; 3561 /* - SDHI1 ------------------------------------------------------------------ */ 3562 static const unsigned int sdhi1_data1_pins[] = { 3563 /* D0 */ 3564 RCAR_GP_PIN(3, 8), 3565 }; 3566 static const unsigned int sdhi1_data1_mux[] = { 3567 SD1_DAT0_MARK, 3568 }; 3569 static const unsigned int sdhi1_data4_pins[] = { 3570 /* D[0:3] */ 3571 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), 3572 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), 3573 }; 3574 static const unsigned int sdhi1_data4_mux[] = { 3575 SD1_DAT0_MARK, SD1_DAT1_MARK, 3576 SD1_DAT2_MARK, SD1_DAT3_MARK, 3577 }; 3578 static const unsigned int sdhi1_ctrl_pins[] = { 3579 /* CLK, CMD */ 3580 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), 3581 }; 3582 static const unsigned int sdhi1_ctrl_mux[] = { 3583 SD1_CLK_MARK, SD1_CMD_MARK, 3584 }; 3585 static const unsigned int sdhi1_cd_pins[] = { 3586 /* CD */ 3587 RCAR_GP_PIN(3, 14), 3588 }; 3589 static const unsigned int sdhi1_cd_mux[] = { 3590 SD1_CD_MARK, 3591 }; 3592 static const unsigned int sdhi1_wp_pins[] = { 3593 /* WP */ 3594 RCAR_GP_PIN(3, 15), 3595 }; 3596 static const unsigned int sdhi1_wp_mux[] = { 3597 SD1_WP_MARK, 3598 }; 3599 /* - SDHI2 ------------------------------------------------------------------ */ 3600 static const unsigned int sdhi2_data1_pins[] = { 3601 /* D0 */ 3602 RCAR_GP_PIN(4, 2), 3603 }; 3604 static const unsigned int sdhi2_data1_mux[] = { 3605 SD2_DAT0_MARK, 3606 }; 3607 static const unsigned int sdhi2_data4_pins[] = { 3608 /* D[0:3] */ 3609 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), 3610 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), 3611 }; 3612 static const unsigned int sdhi2_data4_mux[] = { 3613 SD2_DAT0_MARK, SD2_DAT1_MARK, 3614 SD2_DAT2_MARK, SD2_DAT3_MARK, 3615 }; 3616 static const unsigned int sdhi2_data8_pins[] = { 3617 /* D[0:7] */ 3618 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), 3619 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), 3620 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), 3621 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), 3622 }; 3623 static const unsigned int sdhi2_data8_mux[] = { 3624 SD2_DAT0_MARK, SD2_DAT1_MARK, 3625 SD2_DAT2_MARK, SD2_DAT3_MARK, 3626 SD2_DAT4_MARK, SD2_DAT5_MARK, 3627 SD2_DAT6_MARK, SD2_DAT7_MARK, 3628 }; 3629 static const unsigned int sdhi2_ctrl_pins[] = { 3630 /* CLK, CMD */ 3631 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1), 3632 }; 3633 static const unsigned int sdhi2_ctrl_mux[] = { 3634 SD2_CLK_MARK, SD2_CMD_MARK, 3635 }; 3636 static const unsigned int sdhi2_cd_a_pins[] = { 3637 /* CD */ 3638 RCAR_GP_PIN(4, 13), 3639 }; 3640 static const unsigned int sdhi2_cd_a_mux[] = { 3641 SD2_CD_A_MARK, 3642 }; 3643 static const unsigned int sdhi2_cd_b_pins[] = { 3644 /* CD */ 3645 RCAR_GP_PIN(5, 10), 3646 }; 3647 static const unsigned int sdhi2_cd_b_mux[] = { 3648 SD2_CD_B_MARK, 3649 }; 3650 static const unsigned int sdhi2_wp_a_pins[] = { 3651 /* WP */ 3652 RCAR_GP_PIN(4, 14), 3653 }; 3654 static const unsigned int sdhi2_wp_a_mux[] = { 3655 SD2_WP_A_MARK, 3656 }; 3657 static const unsigned int sdhi2_wp_b_pins[] = { 3658 /* WP */ 3659 RCAR_GP_PIN(5, 11), 3660 }; 3661 static const unsigned int sdhi2_wp_b_mux[] = { 3662 SD2_WP_B_MARK, 3663 }; 3664 static const unsigned int sdhi2_ds_pins[] = { 3665 /* DS */ 3666 RCAR_GP_PIN(4, 6), 3667 }; 3668 static const unsigned int sdhi2_ds_mux[] = { 3669 SD2_DS_MARK, 3670 }; 3671 /* - SDHI3 ------------------------------------------------------------------ */ 3672 static const unsigned int sdhi3_data1_pins[] = { 3673 /* D0 */ 3674 RCAR_GP_PIN(4, 9), 3675 }; 3676 static const unsigned int sdhi3_data1_mux[] = { 3677 SD3_DAT0_MARK, 3678 }; 3679 static const unsigned int sdhi3_data4_pins[] = { 3680 /* D[0:3] */ 3681 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10), 3682 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12), 3683 }; 3684 static const unsigned int sdhi3_data4_mux[] = { 3685 SD3_DAT0_MARK, SD3_DAT1_MARK, 3686 SD3_DAT2_MARK, SD3_DAT3_MARK, 3687 }; 3688 static const unsigned int sdhi3_data8_pins[] = { 3689 /* D[0:7] */ 3690 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10), 3691 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12), 3692 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14), 3693 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16), 3694 }; 3695 static const unsigned int sdhi3_data8_mux[] = { 3696 SD3_DAT0_MARK, SD3_DAT1_MARK, 3697 SD3_DAT2_MARK, SD3_DAT3_MARK, 3698 SD3_DAT4_MARK, SD3_DAT5_MARK, 3699 SD3_DAT6_MARK, SD3_DAT7_MARK, 3700 }; 3701 static const unsigned int sdhi3_ctrl_pins[] = { 3702 /* CLK, CMD */ 3703 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8), 3704 }; 3705 static const unsigned int sdhi3_ctrl_mux[] = { 3706 SD3_CLK_MARK, SD3_CMD_MARK, 3707 }; 3708 static const unsigned int sdhi3_cd_pins[] = { 3709 /* CD */ 3710 RCAR_GP_PIN(4, 15), 3711 }; 3712 static const unsigned int sdhi3_cd_mux[] = { 3713 SD3_CD_MARK, 3714 }; 3715 static const unsigned int sdhi3_wp_pins[] = { 3716 /* WP */ 3717 RCAR_GP_PIN(4, 16), 3718 }; 3719 static const unsigned int sdhi3_wp_mux[] = { 3720 SD3_WP_MARK, 3721 }; 3722 static const unsigned int sdhi3_ds_pins[] = { 3723 /* DS */ 3724 RCAR_GP_PIN(4, 17), 3725 }; 3726 static const unsigned int sdhi3_ds_mux[] = { 3727 SD3_DS_MARK, 3728 }; 3729 3730 /* - SSI -------------------------------------------------------------------- */ 3731 static const unsigned int ssi0_data_pins[] = { 3732 /* SDATA */ 3733 RCAR_GP_PIN(6, 2), 3734 }; 3735 static const unsigned int ssi0_data_mux[] = { 3736 SSI_SDATA0_MARK, 3737 }; 3738 static const unsigned int ssi01239_ctrl_pins[] = { 3739 /* SCK, WS */ 3740 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1), 3741 }; 3742 static const unsigned int ssi01239_ctrl_mux[] = { 3743 SSI_SCK01239_MARK, SSI_WS01239_MARK, 3744 }; 3745 static const unsigned int ssi1_data_a_pins[] = { 3746 /* SDATA */ 3747 RCAR_GP_PIN(6, 3), 3748 }; 3749 static const unsigned int ssi1_data_a_mux[] = { 3750 SSI_SDATA1_A_MARK, 3751 }; 3752 static const unsigned int ssi1_data_b_pins[] = { 3753 /* SDATA */ 3754 RCAR_GP_PIN(5, 12), 3755 }; 3756 static const unsigned int ssi1_data_b_mux[] = { 3757 SSI_SDATA1_B_MARK, 3758 }; 3759 static const unsigned int ssi1_ctrl_a_pins[] = { 3760 /* SCK, WS */ 3761 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27), 3762 }; 3763 static const unsigned int ssi1_ctrl_a_mux[] = { 3764 SSI_SCK1_A_MARK, SSI_WS1_A_MARK, 3765 }; 3766 static const unsigned int ssi1_ctrl_b_pins[] = { 3767 /* SCK, WS */ 3768 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21), 3769 }; 3770 static const unsigned int ssi1_ctrl_b_mux[] = { 3771 SSI_SCK1_B_MARK, SSI_WS1_B_MARK, 3772 }; 3773 static const unsigned int ssi2_data_a_pins[] = { 3774 /* SDATA */ 3775 RCAR_GP_PIN(6, 4), 3776 }; 3777 static const unsigned int ssi2_data_a_mux[] = { 3778 SSI_SDATA2_A_MARK, 3779 }; 3780 static const unsigned int ssi2_data_b_pins[] = { 3781 /* SDATA */ 3782 RCAR_GP_PIN(5, 13), 3783 }; 3784 static const unsigned int ssi2_data_b_mux[] = { 3785 SSI_SDATA2_B_MARK, 3786 }; 3787 static const unsigned int ssi2_ctrl_a_pins[] = { 3788 /* SCK, WS */ 3789 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21), 3790 }; 3791 static const unsigned int ssi2_ctrl_a_mux[] = { 3792 SSI_SCK2_A_MARK, SSI_WS2_A_MARK, 3793 }; 3794 static const unsigned int ssi2_ctrl_b_pins[] = { 3795 /* SCK, WS */ 3796 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29), 3797 }; 3798 static const unsigned int ssi2_ctrl_b_mux[] = { 3799 SSI_SCK2_B_MARK, SSI_WS2_B_MARK, 3800 }; 3801 static const unsigned int ssi3_data_pins[] = { 3802 /* SDATA */ 3803 RCAR_GP_PIN(6, 7), 3804 }; 3805 static const unsigned int ssi3_data_mux[] = { 3806 SSI_SDATA3_MARK, 3807 }; 3808 static const unsigned int ssi349_ctrl_pins[] = { 3809 /* SCK, WS */ 3810 RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6), 3811 }; 3812 static const unsigned int ssi349_ctrl_mux[] = { 3813 SSI_SCK349_MARK, SSI_WS349_MARK, 3814 }; 3815 static const unsigned int ssi4_data_pins[] = { 3816 /* SDATA */ 3817 RCAR_GP_PIN(6, 10), 3818 }; 3819 static const unsigned int ssi4_data_mux[] = { 3820 SSI_SDATA4_MARK, 3821 }; 3822 static const unsigned int ssi4_ctrl_pins[] = { 3823 /* SCK, WS */ 3824 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), 3825 }; 3826 static const unsigned int ssi4_ctrl_mux[] = { 3827 SSI_SCK4_MARK, SSI_WS4_MARK, 3828 }; 3829 static const unsigned int ssi5_data_pins[] = { 3830 /* SDATA */ 3831 RCAR_GP_PIN(6, 13), 3832 }; 3833 static const unsigned int ssi5_data_mux[] = { 3834 SSI_SDATA5_MARK, 3835 }; 3836 static const unsigned int ssi5_ctrl_pins[] = { 3837 /* SCK, WS */ 3838 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12), 3839 }; 3840 static const unsigned int ssi5_ctrl_mux[] = { 3841 SSI_SCK5_MARK, SSI_WS5_MARK, 3842 }; 3843 static const unsigned int ssi6_data_pins[] = { 3844 /* SDATA */ 3845 RCAR_GP_PIN(6, 16), 3846 }; 3847 static const unsigned int ssi6_data_mux[] = { 3848 SSI_SDATA6_MARK, 3849 }; 3850 static const unsigned int ssi6_ctrl_pins[] = { 3851 /* SCK, WS */ 3852 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15), 3853 }; 3854 static const unsigned int ssi6_ctrl_mux[] = { 3855 SSI_SCK6_MARK, SSI_WS6_MARK, 3856 }; 3857 static const unsigned int ssi7_data_pins[] = { 3858 /* SDATA */ 3859 RCAR_GP_PIN(6, 19), 3860 }; 3861 static const unsigned int ssi7_data_mux[] = { 3862 SSI_SDATA7_MARK, 3863 }; 3864 static const unsigned int ssi78_ctrl_pins[] = { 3865 /* SCK, WS */ 3866 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18), 3867 }; 3868 static const unsigned int ssi78_ctrl_mux[] = { 3869 SSI_SCK78_MARK, SSI_WS78_MARK, 3870 }; 3871 static const unsigned int ssi8_data_pins[] = { 3872 /* SDATA */ 3873 RCAR_GP_PIN(6, 20), 3874 }; 3875 static const unsigned int ssi8_data_mux[] = { 3876 SSI_SDATA8_MARK, 3877 }; 3878 static const unsigned int ssi9_data_a_pins[] = { 3879 /* SDATA */ 3880 RCAR_GP_PIN(6, 21), 3881 }; 3882 static const unsigned int ssi9_data_a_mux[] = { 3883 SSI_SDATA9_A_MARK, 3884 }; 3885 static const unsigned int ssi9_data_b_pins[] = { 3886 /* SDATA */ 3887 RCAR_GP_PIN(5, 14), 3888 }; 3889 static const unsigned int ssi9_data_b_mux[] = { 3890 SSI_SDATA9_B_MARK, 3891 }; 3892 static const unsigned int ssi9_ctrl_a_pins[] = { 3893 /* SCK, WS */ 3894 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16), 3895 }; 3896 static const unsigned int ssi9_ctrl_a_mux[] = { 3897 SSI_SCK9_A_MARK, SSI_WS9_A_MARK, 3898 }; 3899 static const unsigned int ssi9_ctrl_b_pins[] = { 3900 /* SCK, WS */ 3901 RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31), 3902 }; 3903 static const unsigned int ssi9_ctrl_b_mux[] = { 3904 SSI_SCK9_B_MARK, SSI_WS9_B_MARK, 3905 }; 3906 3907 /* - TMU -------------------------------------------------------------------- */ 3908 static const unsigned int tmu_tclk1_a_pins[] = { 3909 /* TCLK */ 3910 RCAR_GP_PIN(6, 23), 3911 }; 3912 static const unsigned int tmu_tclk1_a_mux[] = { 3913 TCLK1_A_MARK, 3914 }; 3915 static const unsigned int tmu_tclk1_b_pins[] = { 3916 /* TCLK */ 3917 RCAR_GP_PIN(5, 19), 3918 }; 3919 static const unsigned int tmu_tclk1_b_mux[] = { 3920 TCLK1_B_MARK, 3921 }; 3922 static const unsigned int tmu_tclk2_a_pins[] = { 3923 /* TCLK */ 3924 RCAR_GP_PIN(6, 19), 3925 }; 3926 static const unsigned int tmu_tclk2_a_mux[] = { 3927 TCLK2_A_MARK, 3928 }; 3929 static const unsigned int tmu_tclk2_b_pins[] = { 3930 /* TCLK */ 3931 RCAR_GP_PIN(6, 28), 3932 }; 3933 static const unsigned int tmu_tclk2_b_mux[] = { 3934 TCLK2_B_MARK, 3935 }; 3936 3937 /* - TPU ------------------------------------------------------------------- */ 3938 static const unsigned int tpu_to0_pins[] = { 3939 /* TPU0TO0 */ 3940 RCAR_GP_PIN(6, 28), 3941 }; 3942 static const unsigned int tpu_to0_mux[] = { 3943 TPU0TO0_MARK, 3944 }; 3945 static const unsigned int tpu_to1_pins[] = { 3946 /* TPU0TO1 */ 3947 RCAR_GP_PIN(6, 29), 3948 }; 3949 static const unsigned int tpu_to1_mux[] = { 3950 TPU0TO1_MARK, 3951 }; 3952 static const unsigned int tpu_to2_pins[] = { 3953 /* TPU0TO2 */ 3954 RCAR_GP_PIN(6, 30), 3955 }; 3956 static const unsigned int tpu_to2_mux[] = { 3957 TPU0TO2_MARK, 3958 }; 3959 static const unsigned int tpu_to3_pins[] = { 3960 /* TPU0TO3 */ 3961 RCAR_GP_PIN(6, 31), 3962 }; 3963 static const unsigned int tpu_to3_mux[] = { 3964 TPU0TO3_MARK, 3965 }; 3966 3967 /* - USB0 ------------------------------------------------------------------- */ 3968 static const unsigned int usb0_pins[] = { 3969 /* PWEN, OVC */ 3970 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25), 3971 }; 3972 static const unsigned int usb0_mux[] = { 3973 USB0_PWEN_MARK, USB0_OVC_MARK, 3974 }; 3975 /* - USB1 ------------------------------------------------------------------- */ 3976 static const unsigned int usb1_pins[] = { 3977 /* PWEN, OVC */ 3978 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27), 3979 }; 3980 static const unsigned int usb1_mux[] = { 3981 USB1_PWEN_MARK, USB1_OVC_MARK, 3982 }; 3983 3984 /* - USB30 ------------------------------------------------------------------ */ 3985 static const unsigned int usb30_pins[] = { 3986 /* PWEN, OVC */ 3987 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29), 3988 }; 3989 static const unsigned int usb30_mux[] = { 3990 USB30_PWEN_MARK, USB30_OVC_MARK, 3991 }; 3992 3993 /* - VIN4 ------------------------------------------------------------------- */ 3994 static const unsigned int vin4_data18_a_pins[] = { 3995 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), 3996 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), 3997 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), 3998 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), 3999 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), 4000 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 4001 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), 4002 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), 4003 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), 4004 }; 4005 static const unsigned int vin4_data18_a_mux[] = { 4006 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK, 4007 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK, 4008 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK, 4009 VI4_DATA10_MARK, VI4_DATA11_MARK, 4010 VI4_DATA12_MARK, VI4_DATA13_MARK, 4011 VI4_DATA14_MARK, VI4_DATA15_MARK, 4012 VI4_DATA18_MARK, VI4_DATA19_MARK, 4013 VI4_DATA20_MARK, VI4_DATA21_MARK, 4014 VI4_DATA22_MARK, VI4_DATA23_MARK, 4015 }; 4016 static const unsigned int vin4_data18_b_pins[] = { 4017 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), 4018 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), 4019 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), 4020 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), 4021 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), 4022 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 4023 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), 4024 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), 4025 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), 4026 }; 4027 static const unsigned int vin4_data18_b_mux[] = { 4028 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK, 4029 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK, 4030 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK, 4031 VI4_DATA10_MARK, VI4_DATA11_MARK, 4032 VI4_DATA12_MARK, VI4_DATA13_MARK, 4033 VI4_DATA14_MARK, VI4_DATA15_MARK, 4034 VI4_DATA18_MARK, VI4_DATA19_MARK, 4035 VI4_DATA20_MARK, VI4_DATA21_MARK, 4036 VI4_DATA22_MARK, VI4_DATA23_MARK, 4037 }; 4038 static const union vin_data vin4_data_a_pins = { 4039 .data24 = { 4040 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), 4041 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), 4042 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), 4043 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), 4044 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), 4045 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), 4046 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), 4047 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 4048 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), 4049 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), 4050 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), 4051 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), 4052 }, 4053 }; 4054 static const union vin_data vin4_data_a_mux = { 4055 .data24 = { 4056 VI4_DATA0_A_MARK, VI4_DATA1_A_MARK, 4057 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK, 4058 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK, 4059 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK, 4060 VI4_DATA8_MARK, VI4_DATA9_MARK, 4061 VI4_DATA10_MARK, VI4_DATA11_MARK, 4062 VI4_DATA12_MARK, VI4_DATA13_MARK, 4063 VI4_DATA14_MARK, VI4_DATA15_MARK, 4064 VI4_DATA16_MARK, VI4_DATA17_MARK, 4065 VI4_DATA18_MARK, VI4_DATA19_MARK, 4066 VI4_DATA20_MARK, VI4_DATA21_MARK, 4067 VI4_DATA22_MARK, VI4_DATA23_MARK, 4068 }, 4069 }; 4070 static const union vin_data vin4_data_b_pins = { 4071 .data24 = { 4072 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), 4073 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), 4074 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), 4075 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), 4076 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), 4077 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), 4078 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), 4079 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 4080 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), 4081 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), 4082 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), 4083 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), 4084 }, 4085 }; 4086 static const union vin_data vin4_data_b_mux = { 4087 .data24 = { 4088 VI4_DATA0_B_MARK, VI4_DATA1_B_MARK, 4089 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK, 4090 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK, 4091 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK, 4092 VI4_DATA8_MARK, VI4_DATA9_MARK, 4093 VI4_DATA10_MARK, VI4_DATA11_MARK, 4094 VI4_DATA12_MARK, VI4_DATA13_MARK, 4095 VI4_DATA14_MARK, VI4_DATA15_MARK, 4096 VI4_DATA16_MARK, VI4_DATA17_MARK, 4097 VI4_DATA18_MARK, VI4_DATA19_MARK, 4098 VI4_DATA20_MARK, VI4_DATA21_MARK, 4099 VI4_DATA22_MARK, VI4_DATA23_MARK, 4100 }, 4101 }; 4102 static const unsigned int vin4_g8_pins[] = { 4103 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), 4104 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), 4105 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), 4106 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 4107 }; 4108 static const unsigned int vin4_g8_mux[] = { 4109 VI4_DATA8_MARK, VI4_DATA9_MARK, 4110 VI4_DATA10_MARK, VI4_DATA11_MARK, 4111 VI4_DATA12_MARK, VI4_DATA13_MARK, 4112 VI4_DATA14_MARK, VI4_DATA15_MARK, 4113 }; 4114 static const unsigned int vin4_sync_pins[] = { 4115 /* HSYNC#, VSYNC# */ 4116 RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 17), 4117 }; 4118 static const unsigned int vin4_sync_mux[] = { 4119 VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK, 4120 }; 4121 static const unsigned int vin4_field_pins[] = { 4122 /* FIELD */ 4123 RCAR_GP_PIN(1, 16), 4124 }; 4125 static const unsigned int vin4_field_mux[] = { 4126 VI4_FIELD_MARK, 4127 }; 4128 static const unsigned int vin4_clkenb_pins[] = { 4129 /* CLKENB */ 4130 RCAR_GP_PIN(1, 19), 4131 }; 4132 static const unsigned int vin4_clkenb_mux[] = { 4133 VI4_CLKENB_MARK, 4134 }; 4135 static const unsigned int vin4_clk_pins[] = { 4136 /* CLK */ 4137 RCAR_GP_PIN(1, 27), 4138 }; 4139 static const unsigned int vin4_clk_mux[] = { 4140 VI4_CLK_MARK, 4141 }; 4142 4143 /* - VIN5 ------------------------------------------------------------------- */ 4144 static const union vin_data16 vin5_data_pins = { 4145 .data16 = { 4146 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), 4147 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), 4148 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), 4149 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), 4150 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), 4151 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), 4152 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), 4153 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 4154 }, 4155 }; 4156 static const union vin_data16 vin5_data_mux = { 4157 .data16 = { 4158 VI5_DATA0_MARK, VI5_DATA1_MARK, 4159 VI5_DATA2_MARK, VI5_DATA3_MARK, 4160 VI5_DATA4_MARK, VI5_DATA5_MARK, 4161 VI5_DATA6_MARK, VI5_DATA7_MARK, 4162 VI5_DATA8_MARK, VI5_DATA9_MARK, 4163 VI5_DATA10_MARK, VI5_DATA11_MARK, 4164 VI5_DATA12_MARK, VI5_DATA13_MARK, 4165 VI5_DATA14_MARK, VI5_DATA15_MARK, 4166 }, 4167 }; 4168 static const unsigned int vin5_high8_pins[] = { 4169 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), 4170 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), 4171 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), 4172 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 4173 }; 4174 static const unsigned int vin5_high8_mux[] = { 4175 VI5_DATA8_MARK, VI5_DATA9_MARK, 4176 VI5_DATA10_MARK, VI5_DATA11_MARK, 4177 VI5_DATA12_MARK, VI5_DATA13_MARK, 4178 VI5_DATA14_MARK, VI5_DATA15_MARK, 4179 }; 4180 static const unsigned int vin5_sync_pins[] = { 4181 /* HSYNC#, VSYNC# */ 4182 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9), 4183 }; 4184 static const unsigned int vin5_sync_mux[] = { 4185 VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK, 4186 }; 4187 static const unsigned int vin5_field_pins[] = { 4188 RCAR_GP_PIN(1, 11), 4189 }; 4190 static const unsigned int vin5_field_mux[] = { 4191 /* FIELD */ 4192 VI5_FIELD_MARK, 4193 }; 4194 static const unsigned int vin5_clkenb_pins[] = { 4195 RCAR_GP_PIN(1, 20), 4196 }; 4197 static const unsigned int vin5_clkenb_mux[] = { 4198 /* CLKENB */ 4199 VI5_CLKENB_MARK, 4200 }; 4201 static const unsigned int vin5_clk_pins[] = { 4202 RCAR_GP_PIN(1, 21), 4203 }; 4204 static const unsigned int vin5_clk_mux[] = { 4205 /* CLK */ 4206 VI5_CLK_MARK, 4207 }; 4208 4209 static const struct { 4210 struct sh_pfc_pin_group common[324]; 4211 #if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961) 4212 struct sh_pfc_pin_group automotive[30]; 4213 #endif 4214 } pinmux_groups = { 4215 .common = { 4216 SH_PFC_PIN_GROUP(audio_clk_a_a), 4217 SH_PFC_PIN_GROUP(audio_clk_a_b), 4218 SH_PFC_PIN_GROUP(audio_clk_a_c), 4219 SH_PFC_PIN_GROUP(audio_clk_b_a), 4220 SH_PFC_PIN_GROUP(audio_clk_b_b), 4221 SH_PFC_PIN_GROUP(audio_clk_c_a), 4222 SH_PFC_PIN_GROUP(audio_clk_c_b), 4223 SH_PFC_PIN_GROUP(audio_clkout_a), 4224 SH_PFC_PIN_GROUP(audio_clkout_b), 4225 SH_PFC_PIN_GROUP(audio_clkout_c), 4226 SH_PFC_PIN_GROUP(audio_clkout_d), 4227 SH_PFC_PIN_GROUP(audio_clkout1_a), 4228 SH_PFC_PIN_GROUP(audio_clkout1_b), 4229 SH_PFC_PIN_GROUP(audio_clkout2_a), 4230 SH_PFC_PIN_GROUP(audio_clkout2_b), 4231 SH_PFC_PIN_GROUP(audio_clkout3_a), 4232 SH_PFC_PIN_GROUP(audio_clkout3_b), 4233 SH_PFC_PIN_GROUP(avb_link), 4234 SH_PFC_PIN_GROUP(avb_magic), 4235 SH_PFC_PIN_GROUP(avb_phy_int), 4236 SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio), /* Deprecated */ 4237 SH_PFC_PIN_GROUP(avb_mdio), 4238 SH_PFC_PIN_GROUP(avb_mii), 4239 SH_PFC_PIN_GROUP(avb_avtp_pps), 4240 SH_PFC_PIN_GROUP(avb_avtp_match_a), 4241 SH_PFC_PIN_GROUP(avb_avtp_capture_a), 4242 SH_PFC_PIN_GROUP(avb_avtp_match_b), 4243 SH_PFC_PIN_GROUP(avb_avtp_capture_b), 4244 SH_PFC_PIN_GROUP(can0_data_a), 4245 SH_PFC_PIN_GROUP(can0_data_b), 4246 SH_PFC_PIN_GROUP(can1_data), 4247 SH_PFC_PIN_GROUP(can_clk), 4248 SH_PFC_PIN_GROUP(canfd0_data_a), 4249 SH_PFC_PIN_GROUP(canfd0_data_b), 4250 SH_PFC_PIN_GROUP(canfd1_data), 4251 SH_PFC_PIN_GROUP(du_rgb666), 4252 SH_PFC_PIN_GROUP(du_rgb888), 4253 SH_PFC_PIN_GROUP(du_clk_out_0), 4254 SH_PFC_PIN_GROUP(du_clk_out_1), 4255 SH_PFC_PIN_GROUP(du_sync), 4256 SH_PFC_PIN_GROUP(du_oddf), 4257 SH_PFC_PIN_GROUP(du_cde), 4258 SH_PFC_PIN_GROUP(du_disp), 4259 SH_PFC_PIN_GROUP(hscif0_data), 4260 SH_PFC_PIN_GROUP(hscif0_clk), 4261 SH_PFC_PIN_GROUP(hscif0_ctrl), 4262 SH_PFC_PIN_GROUP(hscif1_data_a), 4263 SH_PFC_PIN_GROUP(hscif1_clk_a), 4264 SH_PFC_PIN_GROUP(hscif1_ctrl_a), 4265 SH_PFC_PIN_GROUP(hscif1_data_b), 4266 SH_PFC_PIN_GROUP(hscif1_clk_b), 4267 SH_PFC_PIN_GROUP(hscif1_ctrl_b), 4268 SH_PFC_PIN_GROUP(hscif2_data_a), 4269 SH_PFC_PIN_GROUP(hscif2_clk_a), 4270 SH_PFC_PIN_GROUP(hscif2_ctrl_a), 4271 SH_PFC_PIN_GROUP(hscif2_data_b), 4272 SH_PFC_PIN_GROUP(hscif2_clk_b), 4273 SH_PFC_PIN_GROUP(hscif2_ctrl_b), 4274 SH_PFC_PIN_GROUP(hscif2_data_c), 4275 SH_PFC_PIN_GROUP(hscif2_clk_c), 4276 SH_PFC_PIN_GROUP(hscif2_ctrl_c), 4277 SH_PFC_PIN_GROUP(hscif3_data_a), 4278 SH_PFC_PIN_GROUP(hscif3_clk), 4279 SH_PFC_PIN_GROUP(hscif3_ctrl), 4280 SH_PFC_PIN_GROUP(hscif3_data_b), 4281 SH_PFC_PIN_GROUP(hscif3_data_c), 4282 SH_PFC_PIN_GROUP(hscif3_data_d), 4283 SH_PFC_PIN_GROUP(hscif4_data_a), 4284 SH_PFC_PIN_GROUP(hscif4_clk), 4285 SH_PFC_PIN_GROUP(hscif4_ctrl), 4286 SH_PFC_PIN_GROUP(hscif4_data_b), 4287 SH_PFC_PIN_GROUP(i2c0), 4288 SH_PFC_PIN_GROUP(i2c1_a), 4289 SH_PFC_PIN_GROUP(i2c1_b), 4290 SH_PFC_PIN_GROUP(i2c2_a), 4291 SH_PFC_PIN_GROUP(i2c2_b), 4292 SH_PFC_PIN_GROUP(i2c3), 4293 SH_PFC_PIN_GROUP(i2c5), 4294 SH_PFC_PIN_GROUP(i2c6_a), 4295 SH_PFC_PIN_GROUP(i2c6_b), 4296 SH_PFC_PIN_GROUP(i2c6_c), 4297 SH_PFC_PIN_GROUP(intc_ex_irq0), 4298 SH_PFC_PIN_GROUP(intc_ex_irq1), 4299 SH_PFC_PIN_GROUP(intc_ex_irq2), 4300 SH_PFC_PIN_GROUP(intc_ex_irq3), 4301 SH_PFC_PIN_GROUP(intc_ex_irq4), 4302 SH_PFC_PIN_GROUP(intc_ex_irq5), 4303 SH_PFC_PIN_GROUP(msiof0_clk), 4304 SH_PFC_PIN_GROUP(msiof0_sync), 4305 SH_PFC_PIN_GROUP(msiof0_ss1), 4306 SH_PFC_PIN_GROUP(msiof0_ss2), 4307 SH_PFC_PIN_GROUP(msiof0_txd), 4308 SH_PFC_PIN_GROUP(msiof0_rxd), 4309 SH_PFC_PIN_GROUP(msiof1_clk_a), 4310 SH_PFC_PIN_GROUP(msiof1_sync_a), 4311 SH_PFC_PIN_GROUP(msiof1_ss1_a), 4312 SH_PFC_PIN_GROUP(msiof1_ss2_a), 4313 SH_PFC_PIN_GROUP(msiof1_txd_a), 4314 SH_PFC_PIN_GROUP(msiof1_rxd_a), 4315 SH_PFC_PIN_GROUP(msiof1_clk_b), 4316 SH_PFC_PIN_GROUP(msiof1_sync_b), 4317 SH_PFC_PIN_GROUP(msiof1_ss1_b), 4318 SH_PFC_PIN_GROUP(msiof1_ss2_b), 4319 SH_PFC_PIN_GROUP(msiof1_txd_b), 4320 SH_PFC_PIN_GROUP(msiof1_rxd_b), 4321 SH_PFC_PIN_GROUP(msiof1_clk_c), 4322 SH_PFC_PIN_GROUP(msiof1_sync_c), 4323 SH_PFC_PIN_GROUP(msiof1_ss1_c), 4324 SH_PFC_PIN_GROUP(msiof1_ss2_c), 4325 SH_PFC_PIN_GROUP(msiof1_txd_c), 4326 SH_PFC_PIN_GROUP(msiof1_rxd_c), 4327 SH_PFC_PIN_GROUP(msiof1_clk_d), 4328 SH_PFC_PIN_GROUP(msiof1_sync_d), 4329 SH_PFC_PIN_GROUP(msiof1_ss1_d), 4330 SH_PFC_PIN_GROUP(msiof1_ss2_d), 4331 SH_PFC_PIN_GROUP(msiof1_txd_d), 4332 SH_PFC_PIN_GROUP(msiof1_rxd_d), 4333 SH_PFC_PIN_GROUP(msiof1_clk_e), 4334 SH_PFC_PIN_GROUP(msiof1_sync_e), 4335 SH_PFC_PIN_GROUP(msiof1_ss1_e), 4336 SH_PFC_PIN_GROUP(msiof1_ss2_e), 4337 SH_PFC_PIN_GROUP(msiof1_txd_e), 4338 SH_PFC_PIN_GROUP(msiof1_rxd_e), 4339 SH_PFC_PIN_GROUP(msiof1_clk_f), 4340 SH_PFC_PIN_GROUP(msiof1_sync_f), 4341 SH_PFC_PIN_GROUP(msiof1_ss1_f), 4342 SH_PFC_PIN_GROUP(msiof1_ss2_f), 4343 SH_PFC_PIN_GROUP(msiof1_txd_f), 4344 SH_PFC_PIN_GROUP(msiof1_rxd_f), 4345 SH_PFC_PIN_GROUP(msiof1_clk_g), 4346 SH_PFC_PIN_GROUP(msiof1_sync_g), 4347 SH_PFC_PIN_GROUP(msiof1_ss1_g), 4348 SH_PFC_PIN_GROUP(msiof1_ss2_g), 4349 SH_PFC_PIN_GROUP(msiof1_txd_g), 4350 SH_PFC_PIN_GROUP(msiof1_rxd_g), 4351 SH_PFC_PIN_GROUP(msiof2_clk_a), 4352 SH_PFC_PIN_GROUP(msiof2_sync_a), 4353 SH_PFC_PIN_GROUP(msiof2_ss1_a), 4354 SH_PFC_PIN_GROUP(msiof2_ss2_a), 4355 SH_PFC_PIN_GROUP(msiof2_txd_a), 4356 SH_PFC_PIN_GROUP(msiof2_rxd_a), 4357 SH_PFC_PIN_GROUP(msiof2_clk_b), 4358 SH_PFC_PIN_GROUP(msiof2_sync_b), 4359 SH_PFC_PIN_GROUP(msiof2_ss1_b), 4360 SH_PFC_PIN_GROUP(msiof2_ss2_b), 4361 SH_PFC_PIN_GROUP(msiof2_txd_b), 4362 SH_PFC_PIN_GROUP(msiof2_rxd_b), 4363 SH_PFC_PIN_GROUP(msiof2_clk_c), 4364 SH_PFC_PIN_GROUP(msiof2_sync_c), 4365 SH_PFC_PIN_GROUP(msiof2_ss1_c), 4366 SH_PFC_PIN_GROUP(msiof2_ss2_c), 4367 SH_PFC_PIN_GROUP(msiof2_txd_c), 4368 SH_PFC_PIN_GROUP(msiof2_rxd_c), 4369 SH_PFC_PIN_GROUP(msiof2_clk_d), 4370 SH_PFC_PIN_GROUP(msiof2_sync_d), 4371 SH_PFC_PIN_GROUP(msiof2_ss1_d), 4372 SH_PFC_PIN_GROUP(msiof2_ss2_d), 4373 SH_PFC_PIN_GROUP(msiof2_txd_d), 4374 SH_PFC_PIN_GROUP(msiof2_rxd_d), 4375 SH_PFC_PIN_GROUP(msiof3_clk_a), 4376 SH_PFC_PIN_GROUP(msiof3_sync_a), 4377 SH_PFC_PIN_GROUP(msiof3_ss1_a), 4378 SH_PFC_PIN_GROUP(msiof3_ss2_a), 4379 SH_PFC_PIN_GROUP(msiof3_txd_a), 4380 SH_PFC_PIN_GROUP(msiof3_rxd_a), 4381 SH_PFC_PIN_GROUP(msiof3_clk_b), 4382 SH_PFC_PIN_GROUP(msiof3_sync_b), 4383 SH_PFC_PIN_GROUP(msiof3_ss1_b), 4384 SH_PFC_PIN_GROUP(msiof3_ss2_b), 4385 SH_PFC_PIN_GROUP(msiof3_txd_b), 4386 SH_PFC_PIN_GROUP(msiof3_rxd_b), 4387 SH_PFC_PIN_GROUP(msiof3_clk_c), 4388 SH_PFC_PIN_GROUP(msiof3_sync_c), 4389 SH_PFC_PIN_GROUP(msiof3_txd_c), 4390 SH_PFC_PIN_GROUP(msiof3_rxd_c), 4391 SH_PFC_PIN_GROUP(msiof3_clk_d), 4392 SH_PFC_PIN_GROUP(msiof3_sync_d), 4393 SH_PFC_PIN_GROUP(msiof3_ss1_d), 4394 SH_PFC_PIN_GROUP(msiof3_txd_d), 4395 SH_PFC_PIN_GROUP(msiof3_rxd_d), 4396 SH_PFC_PIN_GROUP(msiof3_clk_e), 4397 SH_PFC_PIN_GROUP(msiof3_sync_e), 4398 SH_PFC_PIN_GROUP(msiof3_ss1_e), 4399 SH_PFC_PIN_GROUP(msiof3_ss2_e), 4400 SH_PFC_PIN_GROUP(msiof3_txd_e), 4401 SH_PFC_PIN_GROUP(msiof3_rxd_e), 4402 SH_PFC_PIN_GROUP(pwm0), 4403 SH_PFC_PIN_GROUP(pwm1_a), 4404 SH_PFC_PIN_GROUP(pwm1_b), 4405 SH_PFC_PIN_GROUP(pwm2_a), 4406 SH_PFC_PIN_GROUP(pwm2_b), 4407 SH_PFC_PIN_GROUP(pwm3_a), 4408 SH_PFC_PIN_GROUP(pwm3_b), 4409 SH_PFC_PIN_GROUP(pwm4_a), 4410 SH_PFC_PIN_GROUP(pwm4_b), 4411 SH_PFC_PIN_GROUP(pwm5_a), 4412 SH_PFC_PIN_GROUP(pwm5_b), 4413 SH_PFC_PIN_GROUP(pwm6_a), 4414 SH_PFC_PIN_GROUP(pwm6_b), 4415 SH_PFC_PIN_GROUP(qspi0_ctrl), 4416 SH_PFC_PIN_GROUP(qspi0_data2), 4417 SH_PFC_PIN_GROUP(qspi0_data4), 4418 SH_PFC_PIN_GROUP(qspi1_ctrl), 4419 SH_PFC_PIN_GROUP(qspi1_data2), 4420 SH_PFC_PIN_GROUP(qspi1_data4), 4421 SH_PFC_PIN_GROUP(scif0_data), 4422 SH_PFC_PIN_GROUP(scif0_clk), 4423 SH_PFC_PIN_GROUP(scif0_ctrl), 4424 SH_PFC_PIN_GROUP(scif1_data_a), 4425 SH_PFC_PIN_GROUP(scif1_clk), 4426 SH_PFC_PIN_GROUP(scif1_ctrl), 4427 SH_PFC_PIN_GROUP(scif1_data_b), 4428 SH_PFC_PIN_GROUP(scif2_data_a), 4429 SH_PFC_PIN_GROUP(scif2_clk), 4430 SH_PFC_PIN_GROUP(scif2_data_b), 4431 SH_PFC_PIN_GROUP(scif3_data_a), 4432 SH_PFC_PIN_GROUP(scif3_clk), 4433 SH_PFC_PIN_GROUP(scif3_ctrl), 4434 SH_PFC_PIN_GROUP(scif3_data_b), 4435 SH_PFC_PIN_GROUP(scif4_data_a), 4436 SH_PFC_PIN_GROUP(scif4_clk_a), 4437 SH_PFC_PIN_GROUP(scif4_ctrl_a), 4438 SH_PFC_PIN_GROUP(scif4_data_b), 4439 SH_PFC_PIN_GROUP(scif4_clk_b), 4440 SH_PFC_PIN_GROUP(scif4_ctrl_b), 4441 SH_PFC_PIN_GROUP(scif4_data_c), 4442 SH_PFC_PIN_GROUP(scif4_clk_c), 4443 SH_PFC_PIN_GROUP(scif4_ctrl_c), 4444 SH_PFC_PIN_GROUP(scif5_data_a), 4445 SH_PFC_PIN_GROUP(scif5_clk_a), 4446 SH_PFC_PIN_GROUP(scif5_data_b), 4447 SH_PFC_PIN_GROUP(scif5_clk_b), 4448 SH_PFC_PIN_GROUP(scif_clk_a), 4449 SH_PFC_PIN_GROUP(scif_clk_b), 4450 SH_PFC_PIN_GROUP(sdhi0_data1), 4451 SH_PFC_PIN_GROUP(sdhi0_data4), 4452 SH_PFC_PIN_GROUP(sdhi0_ctrl), 4453 SH_PFC_PIN_GROUP(sdhi0_cd), 4454 SH_PFC_PIN_GROUP(sdhi0_wp), 4455 SH_PFC_PIN_GROUP(sdhi1_data1), 4456 SH_PFC_PIN_GROUP(sdhi1_data4), 4457 SH_PFC_PIN_GROUP(sdhi1_ctrl), 4458 SH_PFC_PIN_GROUP(sdhi1_cd), 4459 SH_PFC_PIN_GROUP(sdhi1_wp), 4460 SH_PFC_PIN_GROUP(sdhi2_data1), 4461 SH_PFC_PIN_GROUP(sdhi2_data4), 4462 SH_PFC_PIN_GROUP(sdhi2_data8), 4463 SH_PFC_PIN_GROUP(sdhi2_ctrl), 4464 SH_PFC_PIN_GROUP(sdhi2_cd_a), 4465 SH_PFC_PIN_GROUP(sdhi2_wp_a), 4466 SH_PFC_PIN_GROUP(sdhi2_cd_b), 4467 SH_PFC_PIN_GROUP(sdhi2_wp_b), 4468 SH_PFC_PIN_GROUP(sdhi2_ds), 4469 SH_PFC_PIN_GROUP(sdhi3_data1), 4470 SH_PFC_PIN_GROUP(sdhi3_data4), 4471 SH_PFC_PIN_GROUP(sdhi3_data8), 4472 SH_PFC_PIN_GROUP(sdhi3_ctrl), 4473 SH_PFC_PIN_GROUP(sdhi3_cd), 4474 SH_PFC_PIN_GROUP(sdhi3_wp), 4475 SH_PFC_PIN_GROUP(sdhi3_ds), 4476 SH_PFC_PIN_GROUP(ssi0_data), 4477 SH_PFC_PIN_GROUP(ssi01239_ctrl), 4478 SH_PFC_PIN_GROUP(ssi1_data_a), 4479 SH_PFC_PIN_GROUP(ssi1_data_b), 4480 SH_PFC_PIN_GROUP(ssi1_ctrl_a), 4481 SH_PFC_PIN_GROUP(ssi1_ctrl_b), 4482 SH_PFC_PIN_GROUP(ssi2_data_a), 4483 SH_PFC_PIN_GROUP(ssi2_data_b), 4484 SH_PFC_PIN_GROUP(ssi2_ctrl_a), 4485 SH_PFC_PIN_GROUP(ssi2_ctrl_b), 4486 SH_PFC_PIN_GROUP(ssi3_data), 4487 SH_PFC_PIN_GROUP(ssi349_ctrl), 4488 SH_PFC_PIN_GROUP(ssi4_data), 4489 SH_PFC_PIN_GROUP(ssi4_ctrl), 4490 SH_PFC_PIN_GROUP(ssi5_data), 4491 SH_PFC_PIN_GROUP(ssi5_ctrl), 4492 SH_PFC_PIN_GROUP(ssi6_data), 4493 SH_PFC_PIN_GROUP(ssi6_ctrl), 4494 SH_PFC_PIN_GROUP(ssi7_data), 4495 SH_PFC_PIN_GROUP(ssi78_ctrl), 4496 SH_PFC_PIN_GROUP(ssi8_data), 4497 SH_PFC_PIN_GROUP(ssi9_data_a), 4498 SH_PFC_PIN_GROUP(ssi9_data_b), 4499 SH_PFC_PIN_GROUP(ssi9_ctrl_a), 4500 SH_PFC_PIN_GROUP(ssi9_ctrl_b), 4501 SH_PFC_PIN_GROUP(tmu_tclk1_a), 4502 SH_PFC_PIN_GROUP(tmu_tclk1_b), 4503 SH_PFC_PIN_GROUP(tmu_tclk2_a), 4504 SH_PFC_PIN_GROUP(tmu_tclk2_b), 4505 SH_PFC_PIN_GROUP(tpu_to0), 4506 SH_PFC_PIN_GROUP(tpu_to1), 4507 SH_PFC_PIN_GROUP(tpu_to2), 4508 SH_PFC_PIN_GROUP(tpu_to3), 4509 SH_PFC_PIN_GROUP(usb0), 4510 SH_PFC_PIN_GROUP(usb1), 4511 SH_PFC_PIN_GROUP(usb30), 4512 VIN_DATA_PIN_GROUP(vin4_data, 8, _a), 4513 VIN_DATA_PIN_GROUP(vin4_data, 10, _a), 4514 VIN_DATA_PIN_GROUP(vin4_data, 12, _a), 4515 VIN_DATA_PIN_GROUP(vin4_data, 16, _a), 4516 SH_PFC_PIN_GROUP(vin4_data18_a), 4517 VIN_DATA_PIN_GROUP(vin4_data, 20, _a), 4518 VIN_DATA_PIN_GROUP(vin4_data, 24, _a), 4519 VIN_DATA_PIN_GROUP(vin4_data, 8, _b), 4520 VIN_DATA_PIN_GROUP(vin4_data, 10, _b), 4521 VIN_DATA_PIN_GROUP(vin4_data, 12, _b), 4522 VIN_DATA_PIN_GROUP(vin4_data, 16, _b), 4523 SH_PFC_PIN_GROUP(vin4_data18_b), 4524 VIN_DATA_PIN_GROUP(vin4_data, 20, _b), 4525 VIN_DATA_PIN_GROUP(vin4_data, 24, _b), 4526 SH_PFC_PIN_GROUP(vin4_g8), 4527 SH_PFC_PIN_GROUP(vin4_sync), 4528 SH_PFC_PIN_GROUP(vin4_field), 4529 SH_PFC_PIN_GROUP(vin4_clkenb), 4530 SH_PFC_PIN_GROUP(vin4_clk), 4531 VIN_DATA_PIN_GROUP(vin5_data, 8), 4532 VIN_DATA_PIN_GROUP(vin5_data, 10), 4533 VIN_DATA_PIN_GROUP(vin5_data, 12), 4534 VIN_DATA_PIN_GROUP(vin5_data, 16), 4535 SH_PFC_PIN_GROUP(vin5_high8), 4536 SH_PFC_PIN_GROUP(vin5_sync), 4537 SH_PFC_PIN_GROUP(vin5_field), 4538 SH_PFC_PIN_GROUP(vin5_clkenb), 4539 SH_PFC_PIN_GROUP(vin5_clk), 4540 }, 4541 #if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961) 4542 .automotive = { 4543 SH_PFC_PIN_GROUP(drif0_ctrl_a), 4544 SH_PFC_PIN_GROUP(drif0_data0_a), 4545 SH_PFC_PIN_GROUP(drif0_data1_a), 4546 SH_PFC_PIN_GROUP(drif0_ctrl_b), 4547 SH_PFC_PIN_GROUP(drif0_data0_b), 4548 SH_PFC_PIN_GROUP(drif0_data1_b), 4549 SH_PFC_PIN_GROUP(drif0_ctrl_c), 4550 SH_PFC_PIN_GROUP(drif0_data0_c), 4551 SH_PFC_PIN_GROUP(drif0_data1_c), 4552 SH_PFC_PIN_GROUP(drif1_ctrl_a), 4553 SH_PFC_PIN_GROUP(drif1_data0_a), 4554 SH_PFC_PIN_GROUP(drif1_data1_a), 4555 SH_PFC_PIN_GROUP(drif1_ctrl_b), 4556 SH_PFC_PIN_GROUP(drif1_data0_b), 4557 SH_PFC_PIN_GROUP(drif1_data1_b), 4558 SH_PFC_PIN_GROUP(drif1_ctrl_c), 4559 SH_PFC_PIN_GROUP(drif1_data0_c), 4560 SH_PFC_PIN_GROUP(drif1_data1_c), 4561 SH_PFC_PIN_GROUP(drif2_ctrl_a), 4562 SH_PFC_PIN_GROUP(drif2_data0_a), 4563 SH_PFC_PIN_GROUP(drif2_data1_a), 4564 SH_PFC_PIN_GROUP(drif2_ctrl_b), 4565 SH_PFC_PIN_GROUP(drif2_data0_b), 4566 SH_PFC_PIN_GROUP(drif2_data1_b), 4567 SH_PFC_PIN_GROUP(drif3_ctrl_a), 4568 SH_PFC_PIN_GROUP(drif3_data0_a), 4569 SH_PFC_PIN_GROUP(drif3_data1_a), 4570 SH_PFC_PIN_GROUP(drif3_ctrl_b), 4571 SH_PFC_PIN_GROUP(drif3_data0_b), 4572 SH_PFC_PIN_GROUP(drif3_data1_b), 4573 } 4574 #endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */ 4575 }; 4576 4577 static const char * const audio_clk_groups[] = { 4578 "audio_clk_a_a", 4579 "audio_clk_a_b", 4580 "audio_clk_a_c", 4581 "audio_clk_b_a", 4582 "audio_clk_b_b", 4583 "audio_clk_c_a", 4584 "audio_clk_c_b", 4585 "audio_clkout_a", 4586 "audio_clkout_b", 4587 "audio_clkout_c", 4588 "audio_clkout_d", 4589 "audio_clkout1_a", 4590 "audio_clkout1_b", 4591 "audio_clkout2_a", 4592 "audio_clkout2_b", 4593 "audio_clkout3_a", 4594 "audio_clkout3_b", 4595 }; 4596 4597 static const char * const avb_groups[] = { 4598 "avb_link", 4599 "avb_magic", 4600 "avb_phy_int", 4601 "avb_mdc", /* Deprecated, please use "avb_mdio" instead */ 4602 "avb_mdio", 4603 "avb_mii", 4604 "avb_avtp_pps", 4605 "avb_avtp_match_a", 4606 "avb_avtp_capture_a", 4607 "avb_avtp_match_b", 4608 "avb_avtp_capture_b", 4609 }; 4610 4611 static const char * const can0_groups[] = { 4612 "can0_data_a", 4613 "can0_data_b", 4614 }; 4615 4616 static const char * const can1_groups[] = { 4617 "can1_data", 4618 }; 4619 4620 static const char * const can_clk_groups[] = { 4621 "can_clk", 4622 }; 4623 4624 static const char * const canfd0_groups[] = { 4625 "canfd0_data_a", 4626 "canfd0_data_b", 4627 }; 4628 4629 static const char * const canfd1_groups[] = { 4630 "canfd1_data", 4631 }; 4632 4633 #if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961) 4634 static const char * const drif0_groups[] = { 4635 "drif0_ctrl_a", 4636 "drif0_data0_a", 4637 "drif0_data1_a", 4638 "drif0_ctrl_b", 4639 "drif0_data0_b", 4640 "drif0_data1_b", 4641 "drif0_ctrl_c", 4642 "drif0_data0_c", 4643 "drif0_data1_c", 4644 }; 4645 4646 static const char * const drif1_groups[] = { 4647 "drif1_ctrl_a", 4648 "drif1_data0_a", 4649 "drif1_data1_a", 4650 "drif1_ctrl_b", 4651 "drif1_data0_b", 4652 "drif1_data1_b", 4653 "drif1_ctrl_c", 4654 "drif1_data0_c", 4655 "drif1_data1_c", 4656 }; 4657 4658 static const char * const drif2_groups[] = { 4659 "drif2_ctrl_a", 4660 "drif2_data0_a", 4661 "drif2_data1_a", 4662 "drif2_ctrl_b", 4663 "drif2_data0_b", 4664 "drif2_data1_b", 4665 }; 4666 4667 static const char * const drif3_groups[] = { 4668 "drif3_ctrl_a", 4669 "drif3_data0_a", 4670 "drif3_data1_a", 4671 "drif3_ctrl_b", 4672 "drif3_data0_b", 4673 "drif3_data1_b", 4674 }; 4675 #endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */ 4676 4677 static const char * const du_groups[] = { 4678 "du_rgb666", 4679 "du_rgb888", 4680 "du_clk_out_0", 4681 "du_clk_out_1", 4682 "du_sync", 4683 "du_oddf", 4684 "du_cde", 4685 "du_disp", 4686 }; 4687 4688 static const char * const hscif0_groups[] = { 4689 "hscif0_data", 4690 "hscif0_clk", 4691 "hscif0_ctrl", 4692 }; 4693 4694 static const char * const hscif1_groups[] = { 4695 "hscif1_data_a", 4696 "hscif1_clk_a", 4697 "hscif1_ctrl_a", 4698 "hscif1_data_b", 4699 "hscif1_clk_b", 4700 "hscif1_ctrl_b", 4701 }; 4702 4703 static const char * const hscif2_groups[] = { 4704 "hscif2_data_a", 4705 "hscif2_clk_a", 4706 "hscif2_ctrl_a", 4707 "hscif2_data_b", 4708 "hscif2_clk_b", 4709 "hscif2_ctrl_b", 4710 "hscif2_data_c", 4711 "hscif2_clk_c", 4712 "hscif2_ctrl_c", 4713 }; 4714 4715 static const char * const hscif3_groups[] = { 4716 "hscif3_data_a", 4717 "hscif3_clk", 4718 "hscif3_ctrl", 4719 "hscif3_data_b", 4720 "hscif3_data_c", 4721 "hscif3_data_d", 4722 }; 4723 4724 static const char * const hscif4_groups[] = { 4725 "hscif4_data_a", 4726 "hscif4_clk", 4727 "hscif4_ctrl", 4728 "hscif4_data_b", 4729 }; 4730 4731 static const char * const i2c0_groups[] = { 4732 "i2c0", 4733 }; 4734 4735 static const char * const i2c1_groups[] = { 4736 "i2c1_a", 4737 "i2c1_b", 4738 }; 4739 4740 static const char * const i2c2_groups[] = { 4741 "i2c2_a", 4742 "i2c2_b", 4743 }; 4744 4745 static const char * const i2c3_groups[] = { 4746 "i2c3", 4747 }; 4748 4749 static const char * const i2c5_groups[] = { 4750 "i2c5", 4751 }; 4752 4753 static const char * const i2c6_groups[] = { 4754 "i2c6_a", 4755 "i2c6_b", 4756 "i2c6_c", 4757 }; 4758 4759 static const char * const intc_ex_groups[] = { 4760 "intc_ex_irq0", 4761 "intc_ex_irq1", 4762 "intc_ex_irq2", 4763 "intc_ex_irq3", 4764 "intc_ex_irq4", 4765 "intc_ex_irq5", 4766 }; 4767 4768 static const char * const msiof0_groups[] = { 4769 "msiof0_clk", 4770 "msiof0_sync", 4771 "msiof0_ss1", 4772 "msiof0_ss2", 4773 "msiof0_txd", 4774 "msiof0_rxd", 4775 }; 4776 4777 static const char * const msiof1_groups[] = { 4778 "msiof1_clk_a", 4779 "msiof1_sync_a", 4780 "msiof1_ss1_a", 4781 "msiof1_ss2_a", 4782 "msiof1_txd_a", 4783 "msiof1_rxd_a", 4784 "msiof1_clk_b", 4785 "msiof1_sync_b", 4786 "msiof1_ss1_b", 4787 "msiof1_ss2_b", 4788 "msiof1_txd_b", 4789 "msiof1_rxd_b", 4790 "msiof1_clk_c", 4791 "msiof1_sync_c", 4792 "msiof1_ss1_c", 4793 "msiof1_ss2_c", 4794 "msiof1_txd_c", 4795 "msiof1_rxd_c", 4796 "msiof1_clk_d", 4797 "msiof1_sync_d", 4798 "msiof1_ss1_d", 4799 "msiof1_ss2_d", 4800 "msiof1_txd_d", 4801 "msiof1_rxd_d", 4802 "msiof1_clk_e", 4803 "msiof1_sync_e", 4804 "msiof1_ss1_e", 4805 "msiof1_ss2_e", 4806 "msiof1_txd_e", 4807 "msiof1_rxd_e", 4808 "msiof1_clk_f", 4809 "msiof1_sync_f", 4810 "msiof1_ss1_f", 4811 "msiof1_ss2_f", 4812 "msiof1_txd_f", 4813 "msiof1_rxd_f", 4814 "msiof1_clk_g", 4815 "msiof1_sync_g", 4816 "msiof1_ss1_g", 4817 "msiof1_ss2_g", 4818 "msiof1_txd_g", 4819 "msiof1_rxd_g", 4820 }; 4821 4822 static const char * const msiof2_groups[] = { 4823 "msiof2_clk_a", 4824 "msiof2_sync_a", 4825 "msiof2_ss1_a", 4826 "msiof2_ss2_a", 4827 "msiof2_txd_a", 4828 "msiof2_rxd_a", 4829 "msiof2_clk_b", 4830 "msiof2_sync_b", 4831 "msiof2_ss1_b", 4832 "msiof2_ss2_b", 4833 "msiof2_txd_b", 4834 "msiof2_rxd_b", 4835 "msiof2_clk_c", 4836 "msiof2_sync_c", 4837 "msiof2_ss1_c", 4838 "msiof2_ss2_c", 4839 "msiof2_txd_c", 4840 "msiof2_rxd_c", 4841 "msiof2_clk_d", 4842 "msiof2_sync_d", 4843 "msiof2_ss1_d", 4844 "msiof2_ss2_d", 4845 "msiof2_txd_d", 4846 "msiof2_rxd_d", 4847 }; 4848 4849 static const char * const msiof3_groups[] = { 4850 "msiof3_clk_a", 4851 "msiof3_sync_a", 4852 "msiof3_ss1_a", 4853 "msiof3_ss2_a", 4854 "msiof3_txd_a", 4855 "msiof3_rxd_a", 4856 "msiof3_clk_b", 4857 "msiof3_sync_b", 4858 "msiof3_ss1_b", 4859 "msiof3_ss2_b", 4860 "msiof3_txd_b", 4861 "msiof3_rxd_b", 4862 "msiof3_clk_c", 4863 "msiof3_sync_c", 4864 "msiof3_txd_c", 4865 "msiof3_rxd_c", 4866 "msiof3_clk_d", 4867 "msiof3_sync_d", 4868 "msiof3_ss1_d", 4869 "msiof3_txd_d", 4870 "msiof3_rxd_d", 4871 "msiof3_clk_e", 4872 "msiof3_sync_e", 4873 "msiof3_ss1_e", 4874 "msiof3_ss2_e", 4875 "msiof3_txd_e", 4876 "msiof3_rxd_e", 4877 }; 4878 4879 static const char * const pwm0_groups[] = { 4880 "pwm0", 4881 }; 4882 4883 static const char * const pwm1_groups[] = { 4884 "pwm1_a", 4885 "pwm1_b", 4886 }; 4887 4888 static const char * const pwm2_groups[] = { 4889 "pwm2_a", 4890 "pwm2_b", 4891 }; 4892 4893 static const char * const pwm3_groups[] = { 4894 "pwm3_a", 4895 "pwm3_b", 4896 }; 4897 4898 static const char * const pwm4_groups[] = { 4899 "pwm4_a", 4900 "pwm4_b", 4901 }; 4902 4903 static const char * const pwm5_groups[] = { 4904 "pwm5_a", 4905 "pwm5_b", 4906 }; 4907 4908 static const char * const pwm6_groups[] = { 4909 "pwm6_a", 4910 "pwm6_b", 4911 }; 4912 4913 static const char * const qspi0_groups[] = { 4914 "qspi0_ctrl", 4915 "qspi0_data2", 4916 "qspi0_data4", 4917 }; 4918 4919 static const char * const qspi1_groups[] = { 4920 "qspi1_ctrl", 4921 "qspi1_data2", 4922 "qspi1_data4", 4923 }; 4924 4925 static const char * const scif0_groups[] = { 4926 "scif0_data", 4927 "scif0_clk", 4928 "scif0_ctrl", 4929 }; 4930 4931 static const char * const scif1_groups[] = { 4932 "scif1_data_a", 4933 "scif1_clk", 4934 "scif1_ctrl", 4935 "scif1_data_b", 4936 }; 4937 4938 static const char * const scif2_groups[] = { 4939 "scif2_data_a", 4940 "scif2_clk", 4941 "scif2_data_b", 4942 }; 4943 4944 static const char * const scif3_groups[] = { 4945 "scif3_data_a", 4946 "scif3_clk", 4947 "scif3_ctrl", 4948 "scif3_data_b", 4949 }; 4950 4951 static const char * const scif4_groups[] = { 4952 "scif4_data_a", 4953 "scif4_clk_a", 4954 "scif4_ctrl_a", 4955 "scif4_data_b", 4956 "scif4_clk_b", 4957 "scif4_ctrl_b", 4958 "scif4_data_c", 4959 "scif4_clk_c", 4960 "scif4_ctrl_c", 4961 }; 4962 4963 static const char * const scif5_groups[] = { 4964 "scif5_data_a", 4965 "scif5_clk_a", 4966 "scif5_data_b", 4967 "scif5_clk_b", 4968 }; 4969 4970 static const char * const scif_clk_groups[] = { 4971 "scif_clk_a", 4972 "scif_clk_b", 4973 }; 4974 4975 static const char * const sdhi0_groups[] = { 4976 "sdhi0_data1", 4977 "sdhi0_data4", 4978 "sdhi0_ctrl", 4979 "sdhi0_cd", 4980 "sdhi0_wp", 4981 }; 4982 4983 static const char * const sdhi1_groups[] = { 4984 "sdhi1_data1", 4985 "sdhi1_data4", 4986 "sdhi1_ctrl", 4987 "sdhi1_cd", 4988 "sdhi1_wp", 4989 }; 4990 4991 static const char * const sdhi2_groups[] = { 4992 "sdhi2_data1", 4993 "sdhi2_data4", 4994 "sdhi2_data8", 4995 "sdhi2_ctrl", 4996 "sdhi2_cd_a", 4997 "sdhi2_wp_a", 4998 "sdhi2_cd_b", 4999 "sdhi2_wp_b", 5000 "sdhi2_ds", 5001 }; 5002 5003 static const char * const sdhi3_groups[] = { 5004 "sdhi3_data1", 5005 "sdhi3_data4", 5006 "sdhi3_data8", 5007 "sdhi3_ctrl", 5008 "sdhi3_cd", 5009 "sdhi3_wp", 5010 "sdhi3_ds", 5011 }; 5012 5013 static const char * const ssi_groups[] = { 5014 "ssi0_data", 5015 "ssi01239_ctrl", 5016 "ssi1_data_a", 5017 "ssi1_data_b", 5018 "ssi1_ctrl_a", 5019 "ssi1_ctrl_b", 5020 "ssi2_data_a", 5021 "ssi2_data_b", 5022 "ssi2_ctrl_a", 5023 "ssi2_ctrl_b", 5024 "ssi3_data", 5025 "ssi349_ctrl", 5026 "ssi4_data", 5027 "ssi4_ctrl", 5028 "ssi5_data", 5029 "ssi5_ctrl", 5030 "ssi6_data", 5031 "ssi6_ctrl", 5032 "ssi7_data", 5033 "ssi78_ctrl", 5034 "ssi8_data", 5035 "ssi9_data_a", 5036 "ssi9_data_b", 5037 "ssi9_ctrl_a", 5038 "ssi9_ctrl_b", 5039 }; 5040 5041 static const char * const tmu_groups[] = { 5042 "tmu_tclk1_a", 5043 "tmu_tclk1_b", 5044 "tmu_tclk2_a", 5045 "tmu_tclk2_b", 5046 }; 5047 5048 static const char * const tpu_groups[] = { 5049 "tpu_to0", 5050 "tpu_to1", 5051 "tpu_to2", 5052 "tpu_to3", 5053 }; 5054 5055 static const char * const usb0_groups[] = { 5056 "usb0", 5057 }; 5058 5059 static const char * const usb1_groups[] = { 5060 "usb1", 5061 }; 5062 5063 static const char * const usb30_groups[] = { 5064 "usb30", 5065 }; 5066 5067 static const char * const vin4_groups[] = { 5068 "vin4_data8_a", 5069 "vin4_data10_a", 5070 "vin4_data12_a", 5071 "vin4_data16_a", 5072 "vin4_data18_a", 5073 "vin4_data20_a", 5074 "vin4_data24_a", 5075 "vin4_data8_b", 5076 "vin4_data10_b", 5077 "vin4_data12_b", 5078 "vin4_data16_b", 5079 "vin4_data18_b", 5080 "vin4_data20_b", 5081 "vin4_data24_b", 5082 "vin4_g8", 5083 "vin4_sync", 5084 "vin4_field", 5085 "vin4_clkenb", 5086 "vin4_clk", 5087 }; 5088 5089 static const char * const vin5_groups[] = { 5090 "vin5_data8", 5091 "vin5_data10", 5092 "vin5_data12", 5093 "vin5_data16", 5094 "vin5_high8", 5095 "vin5_sync", 5096 "vin5_field", 5097 "vin5_clkenb", 5098 "vin5_clk", 5099 }; 5100 5101 static const struct { 5102 struct sh_pfc_function common[52]; 5103 #if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961) 5104 struct sh_pfc_function automotive[4]; 5105 #endif 5106 } pinmux_functions = { 5107 .common = { 5108 SH_PFC_FUNCTION(audio_clk), 5109 SH_PFC_FUNCTION(avb), 5110 SH_PFC_FUNCTION(can0), 5111 SH_PFC_FUNCTION(can1), 5112 SH_PFC_FUNCTION(can_clk), 5113 SH_PFC_FUNCTION(canfd0), 5114 SH_PFC_FUNCTION(canfd1), 5115 SH_PFC_FUNCTION(du), 5116 SH_PFC_FUNCTION(hscif0), 5117 SH_PFC_FUNCTION(hscif1), 5118 SH_PFC_FUNCTION(hscif2), 5119 SH_PFC_FUNCTION(hscif3), 5120 SH_PFC_FUNCTION(hscif4), 5121 SH_PFC_FUNCTION(i2c0), 5122 SH_PFC_FUNCTION(i2c1), 5123 SH_PFC_FUNCTION(i2c2), 5124 SH_PFC_FUNCTION(i2c3), 5125 SH_PFC_FUNCTION(i2c5), 5126 SH_PFC_FUNCTION(i2c6), 5127 SH_PFC_FUNCTION(intc_ex), 5128 SH_PFC_FUNCTION(msiof0), 5129 SH_PFC_FUNCTION(msiof1), 5130 SH_PFC_FUNCTION(msiof2), 5131 SH_PFC_FUNCTION(msiof3), 5132 SH_PFC_FUNCTION(pwm0), 5133 SH_PFC_FUNCTION(pwm1), 5134 SH_PFC_FUNCTION(pwm2), 5135 SH_PFC_FUNCTION(pwm3), 5136 SH_PFC_FUNCTION(pwm4), 5137 SH_PFC_FUNCTION(pwm5), 5138 SH_PFC_FUNCTION(pwm6), 5139 SH_PFC_FUNCTION(qspi0), 5140 SH_PFC_FUNCTION(qspi1), 5141 SH_PFC_FUNCTION(scif0), 5142 SH_PFC_FUNCTION(scif1), 5143 SH_PFC_FUNCTION(scif2), 5144 SH_PFC_FUNCTION(scif3), 5145 SH_PFC_FUNCTION(scif4), 5146 SH_PFC_FUNCTION(scif5), 5147 SH_PFC_FUNCTION(scif_clk), 5148 SH_PFC_FUNCTION(sdhi0), 5149 SH_PFC_FUNCTION(sdhi1), 5150 SH_PFC_FUNCTION(sdhi2), 5151 SH_PFC_FUNCTION(sdhi3), 5152 SH_PFC_FUNCTION(ssi), 5153 SH_PFC_FUNCTION(tmu), 5154 SH_PFC_FUNCTION(tpu), 5155 SH_PFC_FUNCTION(usb0), 5156 SH_PFC_FUNCTION(usb1), 5157 SH_PFC_FUNCTION(usb30), 5158 SH_PFC_FUNCTION(vin4), 5159 SH_PFC_FUNCTION(vin5), 5160 }, 5161 #if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961) 5162 .automotive = { 5163 SH_PFC_FUNCTION(drif0), 5164 SH_PFC_FUNCTION(drif1), 5165 SH_PFC_FUNCTION(drif2), 5166 SH_PFC_FUNCTION(drif3), 5167 } 5168 #endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */ 5169 }; 5170 5171 static const struct pinmux_cfg_reg pinmux_config_regs[] = { 5172 #define F_(x, y) FN_##y 5173 #define FM(x) FN_##x 5174 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP( 5175 0, 0, 5176 0, 0, 5177 0, 0, 5178 0, 0, 5179 0, 0, 5180 0, 0, 5181 0, 0, 5182 0, 0, 5183 0, 0, 5184 0, 0, 5185 0, 0, 5186 0, 0, 5187 0, 0, 5188 0, 0, 5189 0, 0, 5190 0, 0, 5191 GP_0_15_FN, GPSR0_15, 5192 GP_0_14_FN, GPSR0_14, 5193 GP_0_13_FN, GPSR0_13, 5194 GP_0_12_FN, GPSR0_12, 5195 GP_0_11_FN, GPSR0_11, 5196 GP_0_10_FN, GPSR0_10, 5197 GP_0_9_FN, GPSR0_9, 5198 GP_0_8_FN, GPSR0_8, 5199 GP_0_7_FN, GPSR0_7, 5200 GP_0_6_FN, GPSR0_6, 5201 GP_0_5_FN, GPSR0_5, 5202 GP_0_4_FN, GPSR0_4, 5203 GP_0_3_FN, GPSR0_3, 5204 GP_0_2_FN, GPSR0_2, 5205 GP_0_1_FN, GPSR0_1, 5206 GP_0_0_FN, GPSR0_0, )) 5207 }, 5208 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP( 5209 0, 0, 5210 0, 0, 5211 0, 0, 5212 GP_1_28_FN, GPSR1_28, 5213 GP_1_27_FN, GPSR1_27, 5214 GP_1_26_FN, GPSR1_26, 5215 GP_1_25_FN, GPSR1_25, 5216 GP_1_24_FN, GPSR1_24, 5217 GP_1_23_FN, GPSR1_23, 5218 GP_1_22_FN, GPSR1_22, 5219 GP_1_21_FN, GPSR1_21, 5220 GP_1_20_FN, GPSR1_20, 5221 GP_1_19_FN, GPSR1_19, 5222 GP_1_18_FN, GPSR1_18, 5223 GP_1_17_FN, GPSR1_17, 5224 GP_1_16_FN, GPSR1_16, 5225 GP_1_15_FN, GPSR1_15, 5226 GP_1_14_FN, GPSR1_14, 5227 GP_1_13_FN, GPSR1_13, 5228 GP_1_12_FN, GPSR1_12, 5229 GP_1_11_FN, GPSR1_11, 5230 GP_1_10_FN, GPSR1_10, 5231 GP_1_9_FN, GPSR1_9, 5232 GP_1_8_FN, GPSR1_8, 5233 GP_1_7_FN, GPSR1_7, 5234 GP_1_6_FN, GPSR1_6, 5235 GP_1_5_FN, GPSR1_5, 5236 GP_1_4_FN, GPSR1_4, 5237 GP_1_3_FN, GPSR1_3, 5238 GP_1_2_FN, GPSR1_2, 5239 GP_1_1_FN, GPSR1_1, 5240 GP_1_0_FN, GPSR1_0, )) 5241 }, 5242 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP( 5243 0, 0, 5244 0, 0, 5245 0, 0, 5246 0, 0, 5247 0, 0, 5248 0, 0, 5249 0, 0, 5250 0, 0, 5251 0, 0, 5252 0, 0, 5253 0, 0, 5254 0, 0, 5255 0, 0, 5256 0, 0, 5257 0, 0, 5258 0, 0, 5259 0, 0, 5260 GP_2_14_FN, GPSR2_14, 5261 GP_2_13_FN, GPSR2_13, 5262 GP_2_12_FN, GPSR2_12, 5263 GP_2_11_FN, GPSR2_11, 5264 GP_2_10_FN, GPSR2_10, 5265 GP_2_9_FN, GPSR2_9, 5266 GP_2_8_FN, GPSR2_8, 5267 GP_2_7_FN, GPSR2_7, 5268 GP_2_6_FN, GPSR2_6, 5269 GP_2_5_FN, GPSR2_5, 5270 GP_2_4_FN, GPSR2_4, 5271 GP_2_3_FN, GPSR2_3, 5272 GP_2_2_FN, GPSR2_2, 5273 GP_2_1_FN, GPSR2_1, 5274 GP_2_0_FN, GPSR2_0, )) 5275 }, 5276 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP( 5277 0, 0, 5278 0, 0, 5279 0, 0, 5280 0, 0, 5281 0, 0, 5282 0, 0, 5283 0, 0, 5284 0, 0, 5285 0, 0, 5286 0, 0, 5287 0, 0, 5288 0, 0, 5289 0, 0, 5290 0, 0, 5291 0, 0, 5292 0, 0, 5293 GP_3_15_FN, GPSR3_15, 5294 GP_3_14_FN, GPSR3_14, 5295 GP_3_13_FN, GPSR3_13, 5296 GP_3_12_FN, GPSR3_12, 5297 GP_3_11_FN, GPSR3_11, 5298 GP_3_10_FN, GPSR3_10, 5299 GP_3_9_FN, GPSR3_9, 5300 GP_3_8_FN, GPSR3_8, 5301 GP_3_7_FN, GPSR3_7, 5302 GP_3_6_FN, GPSR3_6, 5303 GP_3_5_FN, GPSR3_5, 5304 GP_3_4_FN, GPSR3_4, 5305 GP_3_3_FN, GPSR3_3, 5306 GP_3_2_FN, GPSR3_2, 5307 GP_3_1_FN, GPSR3_1, 5308 GP_3_0_FN, GPSR3_0, )) 5309 }, 5310 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP( 5311 0, 0, 5312 0, 0, 5313 0, 0, 5314 0, 0, 5315 0, 0, 5316 0, 0, 5317 0, 0, 5318 0, 0, 5319 0, 0, 5320 0, 0, 5321 0, 0, 5322 0, 0, 5323 0, 0, 5324 0, 0, 5325 GP_4_17_FN, GPSR4_17, 5326 GP_4_16_FN, GPSR4_16, 5327 GP_4_15_FN, GPSR4_15, 5328 GP_4_14_FN, GPSR4_14, 5329 GP_4_13_FN, GPSR4_13, 5330 GP_4_12_FN, GPSR4_12, 5331 GP_4_11_FN, GPSR4_11, 5332 GP_4_10_FN, GPSR4_10, 5333 GP_4_9_FN, GPSR4_9, 5334 GP_4_8_FN, GPSR4_8, 5335 GP_4_7_FN, GPSR4_7, 5336 GP_4_6_FN, GPSR4_6, 5337 GP_4_5_FN, GPSR4_5, 5338 GP_4_4_FN, GPSR4_4, 5339 GP_4_3_FN, GPSR4_3, 5340 GP_4_2_FN, GPSR4_2, 5341 GP_4_1_FN, GPSR4_1, 5342 GP_4_0_FN, GPSR4_0, )) 5343 }, 5344 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP( 5345 0, 0, 5346 0, 0, 5347 0, 0, 5348 0, 0, 5349 0, 0, 5350 0, 0, 5351 GP_5_25_FN, GPSR5_25, 5352 GP_5_24_FN, GPSR5_24, 5353 GP_5_23_FN, GPSR5_23, 5354 GP_5_22_FN, GPSR5_22, 5355 GP_5_21_FN, GPSR5_21, 5356 GP_5_20_FN, GPSR5_20, 5357 GP_5_19_FN, GPSR5_19, 5358 GP_5_18_FN, GPSR5_18, 5359 GP_5_17_FN, GPSR5_17, 5360 GP_5_16_FN, GPSR5_16, 5361 GP_5_15_FN, GPSR5_15, 5362 GP_5_14_FN, GPSR5_14, 5363 GP_5_13_FN, GPSR5_13, 5364 GP_5_12_FN, GPSR5_12, 5365 GP_5_11_FN, GPSR5_11, 5366 GP_5_10_FN, GPSR5_10, 5367 GP_5_9_FN, GPSR5_9, 5368 GP_5_8_FN, GPSR5_8, 5369 GP_5_7_FN, GPSR5_7, 5370 GP_5_6_FN, GPSR5_6, 5371 GP_5_5_FN, GPSR5_5, 5372 GP_5_4_FN, GPSR5_4, 5373 GP_5_3_FN, GPSR5_3, 5374 GP_5_2_FN, GPSR5_2, 5375 GP_5_1_FN, GPSR5_1, 5376 GP_5_0_FN, GPSR5_0, )) 5377 }, 5378 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP( 5379 GP_6_31_FN, GPSR6_31, 5380 GP_6_30_FN, GPSR6_30, 5381 GP_6_29_FN, GPSR6_29, 5382 GP_6_28_FN, GPSR6_28, 5383 GP_6_27_FN, GPSR6_27, 5384 GP_6_26_FN, GPSR6_26, 5385 GP_6_25_FN, GPSR6_25, 5386 GP_6_24_FN, GPSR6_24, 5387 GP_6_23_FN, GPSR6_23, 5388 GP_6_22_FN, GPSR6_22, 5389 GP_6_21_FN, GPSR6_21, 5390 GP_6_20_FN, GPSR6_20, 5391 GP_6_19_FN, GPSR6_19, 5392 GP_6_18_FN, GPSR6_18, 5393 GP_6_17_FN, GPSR6_17, 5394 GP_6_16_FN, GPSR6_16, 5395 GP_6_15_FN, GPSR6_15, 5396 GP_6_14_FN, GPSR6_14, 5397 GP_6_13_FN, GPSR6_13, 5398 GP_6_12_FN, GPSR6_12, 5399 GP_6_11_FN, GPSR6_11, 5400 GP_6_10_FN, GPSR6_10, 5401 GP_6_9_FN, GPSR6_9, 5402 GP_6_8_FN, GPSR6_8, 5403 GP_6_7_FN, GPSR6_7, 5404 GP_6_6_FN, GPSR6_6, 5405 GP_6_5_FN, GPSR6_5, 5406 GP_6_4_FN, GPSR6_4, 5407 GP_6_3_FN, GPSR6_3, 5408 GP_6_2_FN, GPSR6_2, 5409 GP_6_1_FN, GPSR6_1, 5410 GP_6_0_FN, GPSR6_0, )) 5411 }, 5412 { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1, GROUP( 5413 0, 0, 5414 0, 0, 5415 0, 0, 5416 0, 0, 5417 0, 0, 5418 0, 0, 5419 0, 0, 5420 0, 0, 5421 0, 0, 5422 0, 0, 5423 0, 0, 5424 0, 0, 5425 0, 0, 5426 0, 0, 5427 0, 0, 5428 0, 0, 5429 0, 0, 5430 0, 0, 5431 0, 0, 5432 0, 0, 5433 0, 0, 5434 0, 0, 5435 0, 0, 5436 0, 0, 5437 0, 0, 5438 0, 0, 5439 0, 0, 5440 0, 0, 5441 GP_7_3_FN, GPSR7_3, 5442 GP_7_2_FN, GPSR7_2, 5443 GP_7_1_FN, GPSR7_1, 5444 GP_7_0_FN, GPSR7_0, )) 5445 }, 5446 #undef F_ 5447 #undef FM 5448 5449 #define F_(x, y) x, 5450 #define FM(x) FN_##x, 5451 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP( 5452 IP0_31_28 5453 IP0_27_24 5454 IP0_23_20 5455 IP0_19_16 5456 IP0_15_12 5457 IP0_11_8 5458 IP0_7_4 5459 IP0_3_0 )) 5460 }, 5461 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP( 5462 IP1_31_28 5463 IP1_27_24 5464 IP1_23_20 5465 IP1_19_16 5466 IP1_15_12 5467 IP1_11_8 5468 IP1_7_4 5469 IP1_3_0 )) 5470 }, 5471 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP( 5472 IP2_31_28 5473 IP2_27_24 5474 IP2_23_20 5475 IP2_19_16 5476 IP2_15_12 5477 IP2_11_8 5478 IP2_7_4 5479 IP2_3_0 )) 5480 }, 5481 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP( 5482 IP3_31_28 5483 IP3_27_24 5484 IP3_23_20 5485 IP3_19_16 5486 IP3_15_12 5487 IP3_11_8 5488 IP3_7_4 5489 IP3_3_0 )) 5490 }, 5491 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP( 5492 IP4_31_28 5493 IP4_27_24 5494 IP4_23_20 5495 IP4_19_16 5496 IP4_15_12 5497 IP4_11_8 5498 IP4_7_4 5499 IP4_3_0 )) 5500 }, 5501 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP( 5502 IP5_31_28 5503 IP5_27_24 5504 IP5_23_20 5505 IP5_19_16 5506 IP5_15_12 5507 IP5_11_8 5508 IP5_7_4 5509 IP5_3_0 )) 5510 }, 5511 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP( 5512 IP6_31_28 5513 IP6_27_24 5514 IP6_23_20 5515 IP6_19_16 5516 IP6_15_12 5517 IP6_11_8 5518 IP6_7_4 5519 IP6_3_0 )) 5520 }, 5521 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP( 5522 IP7_31_28 5523 IP7_27_24 5524 IP7_23_20 5525 IP7_19_16 5526 /* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5527 IP7_11_8 5528 IP7_7_4 5529 IP7_3_0 )) 5530 }, 5531 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP( 5532 IP8_31_28 5533 IP8_27_24 5534 IP8_23_20 5535 IP8_19_16 5536 IP8_15_12 5537 IP8_11_8 5538 IP8_7_4 5539 IP8_3_0 )) 5540 }, 5541 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP( 5542 IP9_31_28 5543 IP9_27_24 5544 IP9_23_20 5545 IP9_19_16 5546 IP9_15_12 5547 IP9_11_8 5548 IP9_7_4 5549 IP9_3_0 )) 5550 }, 5551 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP( 5552 IP10_31_28 5553 IP10_27_24 5554 IP10_23_20 5555 IP10_19_16 5556 IP10_15_12 5557 IP10_11_8 5558 IP10_7_4 5559 IP10_3_0 )) 5560 }, 5561 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP( 5562 IP11_31_28 5563 IP11_27_24 5564 IP11_23_20 5565 IP11_19_16 5566 IP11_15_12 5567 IP11_11_8 5568 IP11_7_4 5569 IP11_3_0 )) 5570 }, 5571 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP( 5572 IP12_31_28 5573 IP12_27_24 5574 IP12_23_20 5575 IP12_19_16 5576 IP12_15_12 5577 IP12_11_8 5578 IP12_7_4 5579 IP12_3_0 )) 5580 }, 5581 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP( 5582 IP13_31_28 5583 IP13_27_24 5584 IP13_23_20 5585 IP13_19_16 5586 IP13_15_12 5587 IP13_11_8 5588 IP13_7_4 5589 IP13_3_0 )) 5590 }, 5591 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP( 5592 IP14_31_28 5593 IP14_27_24 5594 IP14_23_20 5595 IP14_19_16 5596 IP14_15_12 5597 IP14_11_8 5598 IP14_7_4 5599 IP14_3_0 )) 5600 }, 5601 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP( 5602 IP15_31_28 5603 IP15_27_24 5604 IP15_23_20 5605 IP15_19_16 5606 IP15_15_12 5607 IP15_11_8 5608 IP15_7_4 5609 IP15_3_0 )) 5610 }, 5611 { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4, GROUP( 5612 IP16_31_28 5613 IP16_27_24 5614 IP16_23_20 5615 IP16_19_16 5616 IP16_15_12 5617 IP16_11_8 5618 IP16_7_4 5619 IP16_3_0 )) 5620 }, 5621 { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4, GROUP( 5622 IP17_31_28 5623 IP17_27_24 5624 IP17_23_20 5625 IP17_19_16 5626 IP17_15_12 5627 IP17_11_8 5628 IP17_7_4 5629 IP17_3_0 )) 5630 }, 5631 { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4, GROUP( 5632 /* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5633 /* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5634 /* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5635 /* IP18_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5636 /* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5637 /* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5638 IP18_7_4 5639 IP18_3_0 )) 5640 }, 5641 #undef F_ 5642 #undef FM 5643 5644 #define F_(x, y) x, 5645 #define FM(x) FN_##x, 5646 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32, 5647 GROUP(3, 2, 3, 1, 1, 1, 1, 1, 2, 1, 1, 2, 5648 1, 1, 1, 2, 2, 1, 2, 3), 5649 GROUP( 5650 MOD_SEL0_31_30_29 5651 MOD_SEL0_28_27 5652 MOD_SEL0_26_25_24 5653 MOD_SEL0_23 5654 MOD_SEL0_22 5655 MOD_SEL0_21 5656 MOD_SEL0_20 5657 MOD_SEL0_19 5658 MOD_SEL0_18_17 5659 MOD_SEL0_16 5660 0, 0, /* RESERVED 15 */ 5661 MOD_SEL0_14_13 5662 MOD_SEL0_12 5663 MOD_SEL0_11 5664 MOD_SEL0_10 5665 MOD_SEL0_9_8 5666 MOD_SEL0_7_6 5667 MOD_SEL0_5 5668 MOD_SEL0_4_3 5669 /* RESERVED 2, 1, 0 */ 5670 0, 0, 0, 0, 0, 0, 0, 0 )) 5671 }, 5672 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32, 5673 GROUP(2, 3, 1, 2, 3, 1, 1, 2, 1, 2, 1, 1, 5674 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1), 5675 GROUP( 5676 MOD_SEL1_31_30 5677 MOD_SEL1_29_28_27 5678 MOD_SEL1_26 5679 MOD_SEL1_25_24 5680 MOD_SEL1_23_22_21 5681 MOD_SEL1_20 5682 MOD_SEL1_19 5683 MOD_SEL1_18_17 5684 MOD_SEL1_16 5685 MOD_SEL1_15_14 5686 MOD_SEL1_13 5687 MOD_SEL1_12 5688 MOD_SEL1_11 5689 MOD_SEL1_10 5690 MOD_SEL1_9 5691 0, 0, 0, 0, /* RESERVED 8, 7 */ 5692 MOD_SEL1_6 5693 MOD_SEL1_5 5694 MOD_SEL1_4 5695 MOD_SEL1_3 5696 MOD_SEL1_2 5697 MOD_SEL1_1 5698 MOD_SEL1_0 )) 5699 }, 5700 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32, 5701 GROUP(1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, 5702 1, 4, 4, 4, 3, 1), 5703 GROUP( 5704 MOD_SEL2_31 5705 MOD_SEL2_30 5706 MOD_SEL2_29 5707 MOD_SEL2_28_27 5708 MOD_SEL2_26 5709 MOD_SEL2_25_24_23 5710 MOD_SEL2_22 5711 MOD_SEL2_21 5712 MOD_SEL2_20 5713 MOD_SEL2_19 5714 MOD_SEL2_18 5715 MOD_SEL2_17 5716 /* RESERVED 16 */ 5717 0, 0, 5718 /* RESERVED 15, 14, 13, 12 */ 5719 0, 0, 0, 0, 0, 0, 0, 0, 5720 0, 0, 0, 0, 0, 0, 0, 0, 5721 /* RESERVED 11, 10, 9, 8 */ 5722 0, 0, 0, 0, 0, 0, 0, 0, 5723 0, 0, 0, 0, 0, 0, 0, 0, 5724 /* RESERVED 7, 6, 5, 4 */ 5725 0, 0, 0, 0, 0, 0, 0, 0, 5726 0, 0, 0, 0, 0, 0, 0, 0, 5727 /* RESERVED 3, 2, 1 */ 5728 0, 0, 0, 0, 0, 0, 0, 0, 5729 MOD_SEL2_0 )) 5730 }, 5731 { }, 5732 }; 5733 5734 static const struct pinmux_drive_reg pinmux_drive_regs[] = { 5735 { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) { 5736 { PIN_QSPI0_SPCLK, 28, 2 }, /* QSPI0_SPCLK */ 5737 { PIN_QSPI0_MOSI_IO0, 24, 2 }, /* QSPI0_MOSI_IO0 */ 5738 { PIN_QSPI0_MISO_IO1, 20, 2 }, /* QSPI0_MISO_IO1 */ 5739 { PIN_QSPI0_IO2, 16, 2 }, /* QSPI0_IO2 */ 5740 { PIN_QSPI0_IO3, 12, 2 }, /* QSPI0_IO3 */ 5741 { PIN_QSPI0_SSL, 8, 2 }, /* QSPI0_SSL */ 5742 { PIN_QSPI1_SPCLK, 4, 2 }, /* QSPI1_SPCLK */ 5743 { PIN_QSPI1_MOSI_IO0, 0, 2 }, /* QSPI1_MOSI_IO0 */ 5744 } }, 5745 { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) { 5746 { PIN_QSPI1_MISO_IO1, 28, 2 }, /* QSPI1_MISO_IO1 */ 5747 { PIN_QSPI1_IO2, 24, 2 }, /* QSPI1_IO2 */ 5748 { PIN_QSPI1_IO3, 20, 2 }, /* QSPI1_IO3 */ 5749 { PIN_QSPI1_SSL, 16, 2 }, /* QSPI1_SSL */ 5750 { PIN_RPC_INT_N, 12, 2 }, /* RPC_INT# */ 5751 { PIN_RPC_WP_N, 8, 2 }, /* RPC_WP# */ 5752 { PIN_RPC_RESET_N, 4, 2 }, /* RPC_RESET# */ 5753 { PIN_AVB_RX_CTL, 0, 3 }, /* AVB_RX_CTL */ 5754 } }, 5755 { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) { 5756 { PIN_AVB_RXC, 28, 3 }, /* AVB_RXC */ 5757 { PIN_AVB_RD0, 24, 3 }, /* AVB_RD0 */ 5758 { PIN_AVB_RD1, 20, 3 }, /* AVB_RD1 */ 5759 { PIN_AVB_RD2, 16, 3 }, /* AVB_RD2 */ 5760 { PIN_AVB_RD3, 12, 3 }, /* AVB_RD3 */ 5761 { PIN_AVB_TX_CTL, 8, 3 }, /* AVB_TX_CTL */ 5762 { PIN_AVB_TXC, 4, 3 }, /* AVB_TXC */ 5763 { PIN_AVB_TD0, 0, 3 }, /* AVB_TD0 */ 5764 } }, 5765 { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) { 5766 { PIN_AVB_TD1, 28, 3 }, /* AVB_TD1 */ 5767 { PIN_AVB_TD2, 24, 3 }, /* AVB_TD2 */ 5768 { PIN_AVB_TD3, 20, 3 }, /* AVB_TD3 */ 5769 { PIN_AVB_TXCREFCLK, 16, 3 }, /* AVB_TXCREFCLK */ 5770 { PIN_AVB_MDIO, 12, 3 }, /* AVB_MDIO */ 5771 { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */ 5772 { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */ 5773 { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */ 5774 } }, 5775 { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) { 5776 { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */ 5777 { RCAR_GP_PIN(2, 13), 24, 3 }, /* AVB_AVTP_MATCH */ 5778 { RCAR_GP_PIN(2, 14), 20, 3 }, /* AVB_AVTP_CAPTURE */ 5779 { RCAR_GP_PIN(2, 0), 16, 3 }, /* IRQ0 */ 5780 { RCAR_GP_PIN(2, 1), 12, 3 }, /* IRQ1 */ 5781 { RCAR_GP_PIN(2, 2), 8, 3 }, /* IRQ2 */ 5782 { RCAR_GP_PIN(2, 3), 4, 3 }, /* IRQ3 */ 5783 { RCAR_GP_PIN(2, 4), 0, 3 }, /* IRQ4 */ 5784 } }, 5785 { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) { 5786 { RCAR_GP_PIN(2, 5), 28, 3 }, /* IRQ5 */ 5787 { RCAR_GP_PIN(2, 6), 24, 3 }, /* PWM0 */ 5788 { RCAR_GP_PIN(2, 7), 20, 3 }, /* PWM1 */ 5789 { RCAR_GP_PIN(2, 8), 16, 3 }, /* PWM2 */ 5790 { RCAR_GP_PIN(1, 0), 12, 3 }, /* A0 */ 5791 { RCAR_GP_PIN(1, 1), 8, 3 }, /* A1 */ 5792 { RCAR_GP_PIN(1, 2), 4, 3 }, /* A2 */ 5793 { RCAR_GP_PIN(1, 3), 0, 3 }, /* A3 */ 5794 } }, 5795 { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) { 5796 { RCAR_GP_PIN(1, 4), 28, 3 }, /* A4 */ 5797 { RCAR_GP_PIN(1, 5), 24, 3 }, /* A5 */ 5798 { RCAR_GP_PIN(1, 6), 20, 3 }, /* A6 */ 5799 { RCAR_GP_PIN(1, 7), 16, 3 }, /* A7 */ 5800 { RCAR_GP_PIN(1, 8), 12, 3 }, /* A8 */ 5801 { RCAR_GP_PIN(1, 9), 8, 3 }, /* A9 */ 5802 { RCAR_GP_PIN(1, 10), 4, 3 }, /* A10 */ 5803 { RCAR_GP_PIN(1, 11), 0, 3 }, /* A11 */ 5804 } }, 5805 { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) { 5806 { RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */ 5807 { RCAR_GP_PIN(1, 13), 24, 3 }, /* A13 */ 5808 { RCAR_GP_PIN(1, 14), 20, 3 }, /* A14 */ 5809 { RCAR_GP_PIN(1, 15), 16, 3 }, /* A15 */ 5810 { RCAR_GP_PIN(1, 16), 12, 3 }, /* A16 */ 5811 { RCAR_GP_PIN(1, 17), 8, 3 }, /* A17 */ 5812 { RCAR_GP_PIN(1, 18), 4, 3 }, /* A18 */ 5813 { RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */ 5814 } }, 5815 { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) { 5816 { RCAR_GP_PIN(1, 28), 28, 3 }, /* CLKOUT */ 5817 { RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */ 5818 { RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */ 5819 { RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */ 5820 { RCAR_GP_PIN(1, 23), 12, 3 }, /* RD */ 5821 { RCAR_GP_PIN(1, 24), 8, 3 }, /* RD_WR */ 5822 { RCAR_GP_PIN(1, 25), 4, 3 }, /* WE0 */ 5823 { RCAR_GP_PIN(1, 26), 0, 3 }, /* WE1 */ 5824 } }, 5825 { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) { 5826 { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */ 5827 { PIN_PRESETOUT_N, 24, 3 }, /* PRESETOUT# */ 5828 { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */ 5829 { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */ 5830 { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */ 5831 { RCAR_GP_PIN(0, 3), 8, 3 }, /* D3 */ 5832 { RCAR_GP_PIN(0, 4), 4, 3 }, /* D4 */ 5833 { RCAR_GP_PIN(0, 5), 0, 3 }, /* D5 */ 5834 } }, 5835 { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) { 5836 { RCAR_GP_PIN(0, 6), 28, 3 }, /* D6 */ 5837 { RCAR_GP_PIN(0, 7), 24, 3 }, /* D7 */ 5838 { RCAR_GP_PIN(0, 8), 20, 3 }, /* D8 */ 5839 { RCAR_GP_PIN(0, 9), 16, 3 }, /* D9 */ 5840 { RCAR_GP_PIN(0, 10), 12, 3 }, /* D10 */ 5841 { RCAR_GP_PIN(0, 11), 8, 3 }, /* D11 */ 5842 { RCAR_GP_PIN(0, 12), 4, 3 }, /* D12 */ 5843 { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */ 5844 } }, 5845 { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) { 5846 { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */ 5847 { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */ 5848 { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */ 5849 { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */ 5850 { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */ 5851 { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */ 5852 { PIN_DU_DOTCLKIN0, 4, 2 }, /* DU_DOTCLKIN0 */ 5853 { PIN_DU_DOTCLKIN1, 0, 2 }, /* DU_DOTCLKIN1 */ 5854 } }, 5855 { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) { 5856 { PIN_DU_DOTCLKIN2, 28, 2 }, /* DU_DOTCLKIN2 */ 5857 { PIN_FSCLKST, 20, 2 }, /* FSCLKST */ 5858 { PIN_TMS, 4, 2 }, /* TMS */ 5859 } }, 5860 { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) { 5861 { PIN_TDO, 28, 2 }, /* TDO */ 5862 { PIN_ASEBRK, 24, 2 }, /* ASEBRK */ 5863 { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */ 5864 { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */ 5865 { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */ 5866 { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */ 5867 { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */ 5868 { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */ 5869 } }, 5870 { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) { 5871 { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */ 5872 { RCAR_GP_PIN(3, 7), 24, 3 }, /* SD1_CMD */ 5873 { RCAR_GP_PIN(3, 8), 20, 3 }, /* SD1_DAT0 */ 5874 { RCAR_GP_PIN(3, 9), 16, 3 }, /* SD1_DAT1 */ 5875 { RCAR_GP_PIN(3, 10), 12, 3 }, /* SD1_DAT2 */ 5876 { RCAR_GP_PIN(3, 11), 8, 3 }, /* SD1_DAT3 */ 5877 { RCAR_GP_PIN(4, 0), 4, 3 }, /* SD2_CLK */ 5878 { RCAR_GP_PIN(4, 1), 0, 3 }, /* SD2_CMD */ 5879 } }, 5880 { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) { 5881 { RCAR_GP_PIN(4, 2), 28, 3 }, /* SD2_DAT0 */ 5882 { RCAR_GP_PIN(4, 3), 24, 3 }, /* SD2_DAT1 */ 5883 { RCAR_GP_PIN(4, 4), 20, 3 }, /* SD2_DAT2 */ 5884 { RCAR_GP_PIN(4, 5), 16, 3 }, /* SD2_DAT3 */ 5885 { RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */ 5886 { RCAR_GP_PIN(4, 7), 8, 3 }, /* SD3_CLK */ 5887 { RCAR_GP_PIN(4, 8), 4, 3 }, /* SD3_CMD */ 5888 { RCAR_GP_PIN(4, 9), 0, 3 }, /* SD3_DAT0 */ 5889 } }, 5890 { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) { 5891 { RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */ 5892 { RCAR_GP_PIN(4, 11), 24, 3 }, /* SD3_DAT2 */ 5893 { RCAR_GP_PIN(4, 12), 20, 3 }, /* SD3_DAT3 */ 5894 { RCAR_GP_PIN(4, 13), 16, 3 }, /* SD3_DAT4 */ 5895 { RCAR_GP_PIN(4, 14), 12, 3 }, /* SD3_DAT5 */ 5896 { RCAR_GP_PIN(4, 15), 8, 3 }, /* SD3_DAT6 */ 5897 { RCAR_GP_PIN(4, 16), 4, 3 }, /* SD3_DAT7 */ 5898 { RCAR_GP_PIN(4, 17), 0, 3 }, /* SD3_DS */ 5899 } }, 5900 { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) { 5901 { RCAR_GP_PIN(3, 12), 28, 3 }, /* SD0_CD */ 5902 { RCAR_GP_PIN(3, 13), 24, 3 }, /* SD0_WP */ 5903 { RCAR_GP_PIN(3, 14), 20, 3 }, /* SD1_CD */ 5904 { RCAR_GP_PIN(3, 15), 16, 3 }, /* SD1_WP */ 5905 { RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */ 5906 { RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */ 5907 { RCAR_GP_PIN(5, 2), 4, 3 }, /* TX0 */ 5908 { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */ 5909 } }, 5910 { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) { 5911 { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0 */ 5912 { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */ 5913 { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */ 5914 { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */ 5915 { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1 */ 5916 { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */ 5917 { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */ 5918 { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */ 5919 } }, 5920 { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) { 5921 { RCAR_GP_PIN(5, 12), 28, 3 }, /* HSCK0 */ 5922 { RCAR_GP_PIN(5, 13), 24, 3 }, /* HRX0 */ 5923 { RCAR_GP_PIN(5, 14), 20, 3 }, /* HTX0 */ 5924 { RCAR_GP_PIN(5, 15), 16, 3 }, /* HCTS0 */ 5925 { RCAR_GP_PIN(5, 16), 12, 3 }, /* HRTS0 */ 5926 { RCAR_GP_PIN(5, 17), 8, 3 }, /* MSIOF0_SCK */ 5927 { RCAR_GP_PIN(5, 18), 4, 3 }, /* MSIOF0_SYNC */ 5928 { RCAR_GP_PIN(5, 19), 0, 3 }, /* MSIOF0_SS1 */ 5929 } }, 5930 { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) { 5931 { RCAR_GP_PIN(5, 20), 28, 3 }, /* MSIOF0_TXD */ 5932 { RCAR_GP_PIN(5, 21), 24, 3 }, /* MSIOF0_SS2 */ 5933 { RCAR_GP_PIN(5, 22), 20, 3 }, /* MSIOF0_RXD */ 5934 { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */ 5935 { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */ 5936 { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */ 5937 { PIN_MLB_REF, 4, 3 }, /* MLB_REF */ 5938 { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */ 5939 } }, 5940 { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) { 5941 { RCAR_GP_PIN(6, 1), 28, 3 }, /* SSI_WS01239 */ 5942 { RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */ 5943 { RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */ 5944 { RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */ 5945 { RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK349 */ 5946 { RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS349 */ 5947 { RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */ 5948 { RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */ 5949 } }, 5950 { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) { 5951 { RCAR_GP_PIN(6, 9), 28, 3 }, /* SSI_WS4 */ 5952 { RCAR_GP_PIN(6, 10), 24, 3 }, /* SSI_SDATA4 */ 5953 { RCAR_GP_PIN(6, 11), 20, 3 }, /* SSI_SCK5 */ 5954 { RCAR_GP_PIN(6, 12), 16, 3 }, /* SSI_WS5 */ 5955 { RCAR_GP_PIN(6, 13), 12, 3 }, /* SSI_SDATA5 */ 5956 { RCAR_GP_PIN(6, 14), 8, 3 }, /* SSI_SCK6 */ 5957 { RCAR_GP_PIN(6, 15), 4, 3 }, /* SSI_WS6 */ 5958 { RCAR_GP_PIN(6, 16), 0, 3 }, /* SSI_SDATA6 */ 5959 } }, 5960 { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) { 5961 { RCAR_GP_PIN(6, 17), 28, 3 }, /* SSI_SCK78 */ 5962 { RCAR_GP_PIN(6, 18), 24, 3 }, /* SSI_WS78 */ 5963 { RCAR_GP_PIN(6, 19), 20, 3 }, /* SSI_SDATA7 */ 5964 { RCAR_GP_PIN(6, 20), 16, 3 }, /* SSI_SDATA8 */ 5965 { RCAR_GP_PIN(6, 21), 12, 3 }, /* SSI_SDATA9 */ 5966 { RCAR_GP_PIN(6, 22), 8, 3 }, /* AUDIO_CLKA */ 5967 { RCAR_GP_PIN(6, 23), 4, 3 }, /* AUDIO_CLKB */ 5968 { RCAR_GP_PIN(6, 24), 0, 3 }, /* USB0_PWEN */ 5969 } }, 5970 { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) { 5971 { RCAR_GP_PIN(6, 25), 28, 3 }, /* USB0_OVC */ 5972 { RCAR_GP_PIN(6, 26), 24, 3 }, /* USB1_PWEN */ 5973 { RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */ 5974 { RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */ 5975 { RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */ 5976 { RCAR_GP_PIN(6, 30), 8, 3 }, /* GP6_30 */ 5977 { RCAR_GP_PIN(6, 31), 4, 3 }, /* GP6_31 */ 5978 } }, 5979 { }, 5980 }; 5981 5982 enum ioctrl_regs { 5983 POCCTRL, 5984 TDSELCTRL, 5985 }; 5986 5987 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { 5988 [POCCTRL] = { 0xe6060380, }, 5989 [TDSELCTRL] = { 0xe60603c0, }, 5990 { /* sentinel */ }, 5991 }; 5992 5993 static int r8a7796_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl) 5994 { 5995 int bit = -EINVAL; 5996 5997 *pocctrl = pinmux_ioctrl_regs[POCCTRL].reg; 5998 5999 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11)) 6000 bit = pin & 0x1f; 6001 6002 if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17)) 6003 bit = (pin & 0x1f) + 12; 6004 6005 return bit; 6006 } 6007 6008 static const struct pinmux_bias_reg pinmux_bias_regs[] = { 6009 { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) { 6010 [ 0] = PIN_QSPI0_SPCLK, /* QSPI0_SPCLK */ 6011 [ 1] = PIN_QSPI0_MOSI_IO0, /* QSPI0_MOSI_IO0 */ 6012 [ 2] = PIN_QSPI0_MISO_IO1, /* QSPI0_MISO_IO1 */ 6013 [ 3] = PIN_QSPI0_IO2, /* QSPI0_IO2 */ 6014 [ 4] = PIN_QSPI0_IO3, /* QSPI0_IO3 */ 6015 [ 5] = PIN_QSPI0_SSL, /* QSPI0_SSL */ 6016 [ 6] = PIN_QSPI1_SPCLK, /* QSPI1_SPCLK */ 6017 [ 7] = PIN_QSPI1_MOSI_IO0, /* QSPI1_MOSI_IO0 */ 6018 [ 8] = PIN_QSPI1_MISO_IO1, /* QSPI1_MISO_IO1 */ 6019 [ 9] = PIN_QSPI1_IO2, /* QSPI1_IO2 */ 6020 [10] = PIN_QSPI1_IO3, /* QSPI1_IO3 */ 6021 [11] = PIN_QSPI1_SSL, /* QSPI1_SSL */ 6022 [12] = PIN_RPC_INT_N, /* RPC_INT# */ 6023 [13] = PIN_RPC_WP_N, /* RPC_WP# */ 6024 [14] = PIN_RPC_RESET_N, /* RPC_RESET# */ 6025 [15] = PIN_AVB_RX_CTL, /* AVB_RX_CTL */ 6026 [16] = PIN_AVB_RXC, /* AVB_RXC */ 6027 [17] = PIN_AVB_RD0, /* AVB_RD0 */ 6028 [18] = PIN_AVB_RD1, /* AVB_RD1 */ 6029 [19] = PIN_AVB_RD2, /* AVB_RD2 */ 6030 [20] = PIN_AVB_RD3, /* AVB_RD3 */ 6031 [21] = PIN_AVB_TX_CTL, /* AVB_TX_CTL */ 6032 [22] = PIN_AVB_TXC, /* AVB_TXC */ 6033 [23] = PIN_AVB_TD0, /* AVB_TD0 */ 6034 [24] = PIN_AVB_TD1, /* AVB_TD1 */ 6035 [25] = PIN_AVB_TD2, /* AVB_TD2 */ 6036 [26] = PIN_AVB_TD3, /* AVB_TD3 */ 6037 [27] = PIN_AVB_TXCREFCLK, /* AVB_TXCREFCLK */ 6038 [28] = PIN_AVB_MDIO, /* AVB_MDIO */ 6039 [29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */ 6040 [30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */ 6041 [31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */ 6042 } }, 6043 { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) { 6044 [ 0] = RCAR_GP_PIN(2, 12), /* AVB_LINK */ 6045 [ 1] = RCAR_GP_PIN(2, 13), /* AVB_AVTP_MATCH_A */ 6046 [ 2] = RCAR_GP_PIN(2, 14), /* AVB_AVTP_CAPTURE_A */ 6047 [ 3] = RCAR_GP_PIN(2, 0), /* IRQ0 */ 6048 [ 4] = RCAR_GP_PIN(2, 1), /* IRQ1 */ 6049 [ 5] = RCAR_GP_PIN(2, 2), /* IRQ2 */ 6050 [ 6] = RCAR_GP_PIN(2, 3), /* IRQ3 */ 6051 [ 7] = RCAR_GP_PIN(2, 4), /* IRQ4 */ 6052 [ 8] = RCAR_GP_PIN(2, 5), /* IRQ5 */ 6053 [ 9] = RCAR_GP_PIN(2, 6), /* PWM0 */ 6054 [10] = RCAR_GP_PIN(2, 7), /* PWM1_A */ 6055 [11] = RCAR_GP_PIN(2, 8), /* PWM2_A */ 6056 [12] = RCAR_GP_PIN(1, 0), /* A0 */ 6057 [13] = RCAR_GP_PIN(1, 1), /* A1 */ 6058 [14] = RCAR_GP_PIN(1, 2), /* A2 */ 6059 [15] = RCAR_GP_PIN(1, 3), /* A3 */ 6060 [16] = RCAR_GP_PIN(1, 4), /* A4 */ 6061 [17] = RCAR_GP_PIN(1, 5), /* A5 */ 6062 [18] = RCAR_GP_PIN(1, 6), /* A6 */ 6063 [19] = RCAR_GP_PIN(1, 7), /* A7 */ 6064 [20] = RCAR_GP_PIN(1, 8), /* A8 */ 6065 [21] = RCAR_GP_PIN(1, 9), /* A9 */ 6066 [22] = RCAR_GP_PIN(1, 10), /* A10 */ 6067 [23] = RCAR_GP_PIN(1, 11), /* A11 */ 6068 [24] = RCAR_GP_PIN(1, 12), /* A12 */ 6069 [25] = RCAR_GP_PIN(1, 13), /* A13 */ 6070 [26] = RCAR_GP_PIN(1, 14), /* A14 */ 6071 [27] = RCAR_GP_PIN(1, 15), /* A15 */ 6072 [28] = RCAR_GP_PIN(1, 16), /* A16 */ 6073 [29] = RCAR_GP_PIN(1, 17), /* A17 */ 6074 [30] = RCAR_GP_PIN(1, 18), /* A18 */ 6075 [31] = RCAR_GP_PIN(1, 19), /* A19 */ 6076 } }, 6077 { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) { 6078 [ 0] = RCAR_GP_PIN(1, 28), /* CLKOUT */ 6079 [ 1] = RCAR_GP_PIN(1, 20), /* CS0_N */ 6080 [ 2] = RCAR_GP_PIN(1, 21), /* CS1_N */ 6081 [ 3] = RCAR_GP_PIN(1, 22), /* BS_N */ 6082 [ 4] = RCAR_GP_PIN(1, 23), /* RD_N */ 6083 [ 5] = RCAR_GP_PIN(1, 24), /* RD_WR_N */ 6084 [ 6] = RCAR_GP_PIN(1, 25), /* WE0_N */ 6085 [ 7] = RCAR_GP_PIN(1, 26), /* WE1_N */ 6086 [ 8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */ 6087 [ 9] = PIN_PRESETOUT_N, /* PRESETOUT# */ 6088 [10] = RCAR_GP_PIN(0, 0), /* D0 */ 6089 [11] = RCAR_GP_PIN(0, 1), /* D1 */ 6090 [12] = RCAR_GP_PIN(0, 2), /* D2 */ 6091 [13] = RCAR_GP_PIN(0, 3), /* D3 */ 6092 [14] = RCAR_GP_PIN(0, 4), /* D4 */ 6093 [15] = RCAR_GP_PIN(0, 5), /* D5 */ 6094 [16] = RCAR_GP_PIN(0, 6), /* D6 */ 6095 [17] = RCAR_GP_PIN(0, 7), /* D7 */ 6096 [18] = RCAR_GP_PIN(0, 8), /* D8 */ 6097 [19] = RCAR_GP_PIN(0, 9), /* D9 */ 6098 [20] = RCAR_GP_PIN(0, 10), /* D10 */ 6099 [21] = RCAR_GP_PIN(0, 11), /* D11 */ 6100 [22] = RCAR_GP_PIN(0, 12), /* D12 */ 6101 [23] = RCAR_GP_PIN(0, 13), /* D13 */ 6102 [24] = RCAR_GP_PIN(0, 14), /* D14 */ 6103 [25] = RCAR_GP_PIN(0, 15), /* D15 */ 6104 [26] = RCAR_GP_PIN(7, 0), /* AVS1 */ 6105 [27] = RCAR_GP_PIN(7, 1), /* AVS2 */ 6106 [28] = RCAR_GP_PIN(7, 2), /* GP7_02 */ 6107 [29] = RCAR_GP_PIN(7, 3), /* GP7_03 */ 6108 [30] = PIN_DU_DOTCLKIN0, /* DU_DOTCLKIN0 */ 6109 [31] = PIN_DU_DOTCLKIN1, /* DU_DOTCLKIN1 */ 6110 } }, 6111 { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) { 6112 [ 0] = PIN_DU_DOTCLKIN2, /* DU_DOTCLKIN2 */ 6113 [ 1] = SH_PFC_PIN_NONE, 6114 [ 2] = PIN_FSCLKST, /* FSCLKST */ 6115 [ 3] = PIN_EXTALR, /* EXTALR*/ 6116 [ 4] = PIN_TRST_N, /* TRST# */ 6117 [ 5] = PIN_TCK, /* TCK */ 6118 [ 6] = PIN_TMS, /* TMS */ 6119 [ 7] = PIN_TDI, /* TDI */ 6120 [ 8] = SH_PFC_PIN_NONE, 6121 [ 9] = PIN_ASEBRK, /* ASEBRK */ 6122 [10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */ 6123 [11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */ 6124 [12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */ 6125 [13] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */ 6126 [14] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */ 6127 [15] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */ 6128 [16] = RCAR_GP_PIN(3, 6), /* SD1_CLK */ 6129 [17] = RCAR_GP_PIN(3, 7), /* SD1_CMD */ 6130 [18] = RCAR_GP_PIN(3, 8), /* SD1_DAT0 */ 6131 [19] = RCAR_GP_PIN(3, 9), /* SD1_DAT1 */ 6132 [20] = RCAR_GP_PIN(3, 10), /* SD1_DAT2 */ 6133 [21] = RCAR_GP_PIN(3, 11), /* SD1_DAT3 */ 6134 [22] = RCAR_GP_PIN(4, 0), /* SD2_CLK */ 6135 [23] = RCAR_GP_PIN(4, 1), /* SD2_CMD */ 6136 [24] = RCAR_GP_PIN(4, 2), /* SD2_DAT0 */ 6137 [25] = RCAR_GP_PIN(4, 3), /* SD2_DAT1 */ 6138 [26] = RCAR_GP_PIN(4, 4), /* SD2_DAT2 */ 6139 [27] = RCAR_GP_PIN(4, 5), /* SD2_DAT3 */ 6140 [28] = RCAR_GP_PIN(4, 6), /* SD2_DS */ 6141 [29] = RCAR_GP_PIN(4, 7), /* SD3_CLK */ 6142 [30] = RCAR_GP_PIN(4, 8), /* SD3_CMD */ 6143 [31] = RCAR_GP_PIN(4, 9), /* SD3_DAT0 */ 6144 } }, 6145 { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) { 6146 [ 0] = RCAR_GP_PIN(4, 10), /* SD3_DAT1 */ 6147 [ 1] = RCAR_GP_PIN(4, 11), /* SD3_DAT2 */ 6148 [ 2] = RCAR_GP_PIN(4, 12), /* SD3_DAT3 */ 6149 [ 3] = RCAR_GP_PIN(4, 13), /* SD3_DAT4 */ 6150 [ 4] = RCAR_GP_PIN(4, 14), /* SD3_DAT5 */ 6151 [ 5] = RCAR_GP_PIN(4, 15), /* SD3_DAT6 */ 6152 [ 6] = RCAR_GP_PIN(4, 16), /* SD3_DAT7 */ 6153 [ 7] = RCAR_GP_PIN(4, 17), /* SD3_DS */ 6154 [ 8] = RCAR_GP_PIN(3, 12), /* SD0_CD */ 6155 [ 9] = RCAR_GP_PIN(3, 13), /* SD0_WP */ 6156 [10] = RCAR_GP_PIN(3, 14), /* SD1_CD */ 6157 [11] = RCAR_GP_PIN(3, 15), /* SD1_WP */ 6158 [12] = RCAR_GP_PIN(5, 0), /* SCK0 */ 6159 [13] = RCAR_GP_PIN(5, 1), /* RX0 */ 6160 [14] = RCAR_GP_PIN(5, 2), /* TX0 */ 6161 [15] = RCAR_GP_PIN(5, 3), /* CTS0_N */ 6162 [16] = RCAR_GP_PIN(5, 4), /* RTS0_N */ 6163 [17] = RCAR_GP_PIN(5, 5), /* RX1_A */ 6164 [18] = RCAR_GP_PIN(5, 6), /* TX1_A */ 6165 [19] = RCAR_GP_PIN(5, 7), /* CTS1_N */ 6166 [20] = RCAR_GP_PIN(5, 8), /* RTS1_N */ 6167 [21] = RCAR_GP_PIN(5, 9), /* SCK2 */ 6168 [22] = RCAR_GP_PIN(5, 10), /* TX2_A */ 6169 [23] = RCAR_GP_PIN(5, 11), /* RX2_A */ 6170 [24] = RCAR_GP_PIN(5, 12), /* HSCK0 */ 6171 [25] = RCAR_GP_PIN(5, 13), /* HRX0 */ 6172 [26] = RCAR_GP_PIN(5, 14), /* HTX0 */ 6173 [27] = RCAR_GP_PIN(5, 15), /* HCTS0_N */ 6174 [28] = RCAR_GP_PIN(5, 16), /* HRTS0_N */ 6175 [29] = RCAR_GP_PIN(5, 17), /* MSIOF0_SCK */ 6176 [30] = RCAR_GP_PIN(5, 18), /* MSIOF0_SYNC */ 6177 [31] = RCAR_GP_PIN(5, 19), /* MSIOF0_SS1 */ 6178 } }, 6179 { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) { 6180 [ 0] = RCAR_GP_PIN(5, 20), /* MSIOF0_TXD */ 6181 [ 1] = RCAR_GP_PIN(5, 21), /* MSIOF0_SS2 */ 6182 [ 2] = RCAR_GP_PIN(5, 22), /* MSIOF0_RXD */ 6183 [ 3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */ 6184 [ 4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */ 6185 [ 5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */ 6186 [ 6] = PIN_MLB_REF, /* MLB_REF */ 6187 [ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */ 6188 [ 8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */ 6189 [ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */ 6190 [10] = RCAR_GP_PIN(6, 3), /* SSI_SDATA1_A */ 6191 [11] = RCAR_GP_PIN(6, 4), /* SSI_SDATA2_A */ 6192 [12] = RCAR_GP_PIN(6, 5), /* SSI_SCK349 */ 6193 [13] = RCAR_GP_PIN(6, 6), /* SSI_WS349 */ 6194 [14] = RCAR_GP_PIN(6, 7), /* SSI_SDATA3 */ 6195 [15] = RCAR_GP_PIN(6, 8), /* SSI_SCK4 */ 6196 [16] = RCAR_GP_PIN(6, 9), /* SSI_WS4 */ 6197 [17] = RCAR_GP_PIN(6, 10), /* SSI_SDATA4 */ 6198 [18] = RCAR_GP_PIN(6, 11), /* SSI_SCK5 */ 6199 [19] = RCAR_GP_PIN(6, 12), /* SSI_WS5 */ 6200 [20] = RCAR_GP_PIN(6, 13), /* SSI_SDATA5 */ 6201 [21] = RCAR_GP_PIN(6, 14), /* SSI_SCK6 */ 6202 [22] = RCAR_GP_PIN(6, 15), /* SSI_WS6 */ 6203 [23] = RCAR_GP_PIN(6, 16), /* SSI_SDATA6 */ 6204 [24] = RCAR_GP_PIN(6, 17), /* SSI_SCK78 */ 6205 [25] = RCAR_GP_PIN(6, 18), /* SSI_WS78 */ 6206 [26] = RCAR_GP_PIN(6, 19), /* SSI_SDATA7 */ 6207 [27] = RCAR_GP_PIN(6, 20), /* SSI_SDATA8 */ 6208 [28] = RCAR_GP_PIN(6, 21), /* SSI_SDATA9_A */ 6209 [29] = RCAR_GP_PIN(6, 22), /* AUDIO_CLKA_A */ 6210 [30] = RCAR_GP_PIN(6, 23), /* AUDIO_CLKB_B */ 6211 [31] = RCAR_GP_PIN(6, 24), /* USB0_PWEN */ 6212 } }, 6213 { PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) { 6214 [ 0] = RCAR_GP_PIN(6, 25), /* USB0_OVC */ 6215 [ 1] = RCAR_GP_PIN(6, 26), /* USB1_PWEN */ 6216 [ 2] = RCAR_GP_PIN(6, 27), /* USB1_OVC */ 6217 [ 3] = RCAR_GP_PIN(6, 28), /* USB30_PWEN */ 6218 [ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */ 6219 [ 5] = RCAR_GP_PIN(6, 30), /* GP6_30 */ 6220 [ 6] = RCAR_GP_PIN(6, 31), /* GP6_31 */ 6221 [ 7] = SH_PFC_PIN_NONE, 6222 [ 8] = SH_PFC_PIN_NONE, 6223 [ 9] = SH_PFC_PIN_NONE, 6224 [10] = SH_PFC_PIN_NONE, 6225 [11] = SH_PFC_PIN_NONE, 6226 [12] = SH_PFC_PIN_NONE, 6227 [13] = SH_PFC_PIN_NONE, 6228 [14] = SH_PFC_PIN_NONE, 6229 [15] = SH_PFC_PIN_NONE, 6230 [16] = SH_PFC_PIN_NONE, 6231 [17] = SH_PFC_PIN_NONE, 6232 [18] = SH_PFC_PIN_NONE, 6233 [19] = SH_PFC_PIN_NONE, 6234 [20] = SH_PFC_PIN_NONE, 6235 [21] = SH_PFC_PIN_NONE, 6236 [22] = SH_PFC_PIN_NONE, 6237 [23] = SH_PFC_PIN_NONE, 6238 [24] = SH_PFC_PIN_NONE, 6239 [25] = SH_PFC_PIN_NONE, 6240 [26] = SH_PFC_PIN_NONE, 6241 [27] = SH_PFC_PIN_NONE, 6242 [28] = SH_PFC_PIN_NONE, 6243 [29] = SH_PFC_PIN_NONE, 6244 [30] = SH_PFC_PIN_NONE, 6245 [31] = SH_PFC_PIN_NONE, 6246 } }, 6247 { /* sentinel */ }, 6248 }; 6249 6250 static const struct sh_pfc_soc_operations r8a7796_pinmux_ops = { 6251 .pin_to_pocctrl = r8a7796_pin_to_pocctrl, 6252 .get_bias = rcar_pinmux_get_bias, 6253 .set_bias = rcar_pinmux_set_bias, 6254 }; 6255 6256 #ifdef CONFIG_PINCTRL_PFC_R8A774A1 6257 const struct sh_pfc_soc_info r8a774a1_pinmux_info = { 6258 .name = "r8a774a1_pfc", 6259 .ops = &r8a7796_pinmux_ops, 6260 .unlock_reg = 0xe6060000, /* PMMR */ 6261 6262 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 6263 6264 .pins = pinmux_pins, 6265 .nr_pins = ARRAY_SIZE(pinmux_pins), 6266 .groups = pinmux_groups.common, 6267 .nr_groups = ARRAY_SIZE(pinmux_groups.common), 6268 .functions = pinmux_functions.common, 6269 .nr_functions = ARRAY_SIZE(pinmux_functions.common), 6270 6271 .cfg_regs = pinmux_config_regs, 6272 .drive_regs = pinmux_drive_regs, 6273 .bias_regs = pinmux_bias_regs, 6274 .ioctrl_regs = pinmux_ioctrl_regs, 6275 6276 .pinmux_data = pinmux_data, 6277 .pinmux_data_size = ARRAY_SIZE(pinmux_data), 6278 }; 6279 #endif 6280 6281 #ifdef CONFIG_PINCTRL_PFC_R8A77960 6282 const struct sh_pfc_soc_info r8a77960_pinmux_info = { 6283 .name = "r8a77960_pfc", 6284 .ops = &r8a7796_pinmux_ops, 6285 .unlock_reg = 0xe6060000, /* PMMR */ 6286 6287 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 6288 6289 .pins = pinmux_pins, 6290 .nr_pins = ARRAY_SIZE(pinmux_pins), 6291 .groups = pinmux_groups.common, 6292 .nr_groups = ARRAY_SIZE(pinmux_groups.common) + 6293 ARRAY_SIZE(pinmux_groups.automotive), 6294 .functions = pinmux_functions.common, 6295 .nr_functions = ARRAY_SIZE(pinmux_functions.common) + 6296 ARRAY_SIZE(pinmux_functions.automotive), 6297 6298 .cfg_regs = pinmux_config_regs, 6299 .drive_regs = pinmux_drive_regs, 6300 .bias_regs = pinmux_bias_regs, 6301 .ioctrl_regs = pinmux_ioctrl_regs, 6302 6303 .pinmux_data = pinmux_data, 6304 .pinmux_data_size = ARRAY_SIZE(pinmux_data), 6305 }; 6306 #endif 6307 6308 #ifdef CONFIG_PINCTRL_PFC_R8A77961 6309 const struct sh_pfc_soc_info r8a77961_pinmux_info = { 6310 .name = "r8a77961_pfc", 6311 .ops = &r8a7796_pinmux_ops, 6312 .unlock_reg = 0xe6060000, /* PMMR */ 6313 6314 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 6315 6316 .pins = pinmux_pins, 6317 .nr_pins = ARRAY_SIZE(pinmux_pins), 6318 .groups = pinmux_groups.common, 6319 .nr_groups = ARRAY_SIZE(pinmux_groups.common) + 6320 ARRAY_SIZE(pinmux_groups.automotive), 6321 .functions = pinmux_functions.common, 6322 .nr_functions = ARRAY_SIZE(pinmux_functions.common) + 6323 ARRAY_SIZE(pinmux_functions.automotive), 6324 6325 .cfg_regs = pinmux_config_regs, 6326 .drive_regs = pinmux_drive_regs, 6327 .bias_regs = pinmux_bias_regs, 6328 .ioctrl_regs = pinmux_ioctrl_regs, 6329 6330 .pinmux_data = pinmux_data, 6331 .pinmux_data_size = ARRAY_SIZE(pinmux_data), 6332 }; 6333 #endif 6334