1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * R8A77951 processor support - PFC hardware block. 4 * 5 * Copyright (C) 2015-2019 Renesas Electronics Corporation 6 */ 7 8 #include <linux/errno.h> 9 #include <linux/kernel.h> 10 #include <linux/sys_soc.h> 11 12 #include "core.h" 13 #include "sh_pfc.h" 14 15 #define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN) 16 17 #define CPU_ALL_GP(fn, sfx) \ 18 PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \ 19 PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \ 20 PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \ 21 PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \ 22 PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \ 23 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \ 24 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \ 25 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \ 26 PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \ 27 PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \ 28 PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \ 29 PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS) 30 31 #define CPU_ALL_NOGP(fn) \ 32 PIN_NOGP_CFG(ASEBRK, "ASEBRK", fn, CFG_FLAGS), \ 33 PIN_NOGP_CFG(AVB_MDIO, "AVB_MDIO", fn, CFG_FLAGS), \ 34 PIN_NOGP_CFG(AVB_RD0, "AVB_RD0", fn, CFG_FLAGS), \ 35 PIN_NOGP_CFG(AVB_RD1, "AVB_RD1", fn, CFG_FLAGS), \ 36 PIN_NOGP_CFG(AVB_RD2, "AVB_RD2", fn, CFG_FLAGS), \ 37 PIN_NOGP_CFG(AVB_RD3, "AVB_RD3", fn, CFG_FLAGS), \ 38 PIN_NOGP_CFG(AVB_RXC, "AVB_RXC", fn, CFG_FLAGS), \ 39 PIN_NOGP_CFG(AVB_RX_CTL, "AVB_RX_CTL", fn, CFG_FLAGS), \ 40 PIN_NOGP_CFG(AVB_TD0, "AVB_TD0", fn, CFG_FLAGS), \ 41 PIN_NOGP_CFG(AVB_TD1, "AVB_TD1", fn, CFG_FLAGS), \ 42 PIN_NOGP_CFG(AVB_TD2, "AVB_TD2", fn, CFG_FLAGS), \ 43 PIN_NOGP_CFG(AVB_TD3, "AVB_TD3", fn, CFG_FLAGS), \ 44 PIN_NOGP_CFG(AVB_TXC, "AVB_TXC", fn, CFG_FLAGS), \ 45 PIN_NOGP_CFG(AVB_TXCREFCLK, "AVB_TXCREFCLK", fn, CFG_FLAGS), \ 46 PIN_NOGP_CFG(AVB_TX_CTL, "AVB_TX_CTL", fn, CFG_FLAGS), \ 47 PIN_NOGP_CFG(DU_DOTCLKIN0, "DU_DOTCLKIN0", fn, CFG_FLAGS), \ 48 PIN_NOGP_CFG(DU_DOTCLKIN1, "DU_DOTCLKIN1", fn, CFG_FLAGS), \ 49 PIN_NOGP_CFG(DU_DOTCLKIN2, "DU_DOTCLKIN2", fn, CFG_FLAGS), \ 50 PIN_NOGP_CFG(DU_DOTCLKIN3, "DU_DOTCLKIN3", fn, CFG_FLAGS), \ 51 PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),\ 52 PIN_NOGP_CFG(FSCLKST_N, "FSCLKST#", fn, CFG_FLAGS), \ 53 PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS), \ 54 PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, CFG_FLAGS), \ 55 PIN_NOGP_CFG(QSPI0_IO2, "QSPI0_IO2", fn, CFG_FLAGS), \ 56 PIN_NOGP_CFG(QSPI0_IO3, "QSPI0_IO3", fn, CFG_FLAGS), \ 57 PIN_NOGP_CFG(QSPI0_MISO_IO1, "QSPI0_MISO_IO1", fn, CFG_FLAGS), \ 58 PIN_NOGP_CFG(QSPI0_MOSI_IO0, "QSPI0_MOSI_IO0", fn, CFG_FLAGS), \ 59 PIN_NOGP_CFG(QSPI0_SPCLK, "QSPI0_SPCLK", fn, CFG_FLAGS), \ 60 PIN_NOGP_CFG(QSPI0_SSL, "QSPI0_SSL", fn, CFG_FLAGS), \ 61 PIN_NOGP_CFG(QSPI1_IO2, "QSPI1_IO2", fn, CFG_FLAGS), \ 62 PIN_NOGP_CFG(QSPI1_IO3, "QSPI1_IO3", fn, CFG_FLAGS), \ 63 PIN_NOGP_CFG(QSPI1_MISO_IO1, "QSPI1_MISO_IO1", fn, CFG_FLAGS), \ 64 PIN_NOGP_CFG(QSPI1_MOSI_IO0, "QSPI1_MOSI_IO0", fn, CFG_FLAGS), \ 65 PIN_NOGP_CFG(QSPI1_SPCLK, "QSPI1_SPCLK", fn, CFG_FLAGS), \ 66 PIN_NOGP_CFG(QSPI1_SSL, "QSPI1_SSL", fn, CFG_FLAGS), \ 67 PIN_NOGP_CFG(RPC_INT_N, "RPC_INT#", fn, CFG_FLAGS), \ 68 PIN_NOGP_CFG(RPC_RESET_N, "RPC_RESET#", fn, CFG_FLAGS), \ 69 PIN_NOGP_CFG(RPC_WP_N, "RPC_WP#", fn, CFG_FLAGS), \ 70 PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ 71 PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ 72 PIN_NOGP_CFG(TDO, "TDO", fn, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \ 73 PIN_NOGP_CFG(TMS, "TMS", fn, CFG_FLAGS), \ 74 PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN) 75 76 /* 77 * F_() : just information 78 * FM() : macro for FN_xxx / xxx_MARK 79 */ 80 81 /* GPSR0 */ 82 #define GPSR0_15 F_(D15, IP7_11_8) 83 #define GPSR0_14 F_(D14, IP7_7_4) 84 #define GPSR0_13 F_(D13, IP7_3_0) 85 #define GPSR0_12 F_(D12, IP6_31_28) 86 #define GPSR0_11 F_(D11, IP6_27_24) 87 #define GPSR0_10 F_(D10, IP6_23_20) 88 #define GPSR0_9 F_(D9, IP6_19_16) 89 #define GPSR0_8 F_(D8, IP6_15_12) 90 #define GPSR0_7 F_(D7, IP6_11_8) 91 #define GPSR0_6 F_(D6, IP6_7_4) 92 #define GPSR0_5 F_(D5, IP6_3_0) 93 #define GPSR0_4 F_(D4, IP5_31_28) 94 #define GPSR0_3 F_(D3, IP5_27_24) 95 #define GPSR0_2 F_(D2, IP5_23_20) 96 #define GPSR0_1 F_(D1, IP5_19_16) 97 #define GPSR0_0 F_(D0, IP5_15_12) 98 99 /* GPSR1 */ 100 #define GPSR1_28 FM(CLKOUT) 101 #define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8) 102 #define GPSR1_26 F_(WE1_N, IP5_7_4) 103 #define GPSR1_25 F_(WE0_N, IP5_3_0) 104 #define GPSR1_24 F_(RD_WR_N, IP4_31_28) 105 #define GPSR1_23 F_(RD_N, IP4_27_24) 106 #define GPSR1_22 F_(BS_N, IP4_23_20) 107 #define GPSR1_21 F_(CS1_N, IP4_19_16) 108 #define GPSR1_20 F_(CS0_N, IP4_15_12) 109 #define GPSR1_19 F_(A19, IP4_11_8) 110 #define GPSR1_18 F_(A18, IP4_7_4) 111 #define GPSR1_17 F_(A17, IP4_3_0) 112 #define GPSR1_16 F_(A16, IP3_31_28) 113 #define GPSR1_15 F_(A15, IP3_27_24) 114 #define GPSR1_14 F_(A14, IP3_23_20) 115 #define GPSR1_13 F_(A13, IP3_19_16) 116 #define GPSR1_12 F_(A12, IP3_15_12) 117 #define GPSR1_11 F_(A11, IP3_11_8) 118 #define GPSR1_10 F_(A10, IP3_7_4) 119 #define GPSR1_9 F_(A9, IP3_3_0) 120 #define GPSR1_8 F_(A8, IP2_31_28) 121 #define GPSR1_7 F_(A7, IP2_27_24) 122 #define GPSR1_6 F_(A6, IP2_23_20) 123 #define GPSR1_5 F_(A5, IP2_19_16) 124 #define GPSR1_4 F_(A4, IP2_15_12) 125 #define GPSR1_3 F_(A3, IP2_11_8) 126 #define GPSR1_2 F_(A2, IP2_7_4) 127 #define GPSR1_1 F_(A1, IP2_3_0) 128 #define GPSR1_0 F_(A0, IP1_31_28) 129 130 /* GPSR2 */ 131 #define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20) 132 #define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16) 133 #define GPSR2_12 F_(AVB_LINK, IP0_15_12) 134 #define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8) 135 #define GPSR2_10 F_(AVB_MAGIC, IP0_7_4) 136 #define GPSR2_9 F_(AVB_MDC, IP0_3_0) 137 #define GPSR2_8 F_(PWM2_A, IP1_27_24) 138 #define GPSR2_7 F_(PWM1_A, IP1_23_20) 139 #define GPSR2_6 F_(PWM0, IP1_19_16) 140 #define GPSR2_5 F_(IRQ5, IP1_15_12) 141 #define GPSR2_4 F_(IRQ4, IP1_11_8) 142 #define GPSR2_3 F_(IRQ3, IP1_7_4) 143 #define GPSR2_2 F_(IRQ2, IP1_3_0) 144 #define GPSR2_1 F_(IRQ1, IP0_31_28) 145 #define GPSR2_0 F_(IRQ0, IP0_27_24) 146 147 /* GPSR3 */ 148 #define GPSR3_15 F_(SD1_WP, IP11_23_20) 149 #define GPSR3_14 F_(SD1_CD, IP11_19_16) 150 #define GPSR3_13 F_(SD0_WP, IP11_15_12) 151 #define GPSR3_12 F_(SD0_CD, IP11_11_8) 152 #define GPSR3_11 F_(SD1_DAT3, IP8_31_28) 153 #define GPSR3_10 F_(SD1_DAT2, IP8_27_24) 154 #define GPSR3_9 F_(SD1_DAT1, IP8_23_20) 155 #define GPSR3_8 F_(SD1_DAT0, IP8_19_16) 156 #define GPSR3_7 F_(SD1_CMD, IP8_15_12) 157 #define GPSR3_6 F_(SD1_CLK, IP8_11_8) 158 #define GPSR3_5 F_(SD0_DAT3, IP8_7_4) 159 #define GPSR3_4 F_(SD0_DAT2, IP8_3_0) 160 #define GPSR3_3 F_(SD0_DAT1, IP7_31_28) 161 #define GPSR3_2 F_(SD0_DAT0, IP7_27_24) 162 #define GPSR3_1 F_(SD0_CMD, IP7_23_20) 163 #define GPSR3_0 F_(SD0_CLK, IP7_19_16) 164 165 /* GPSR4 */ 166 #define GPSR4_17 F_(SD3_DS, IP11_7_4) 167 #define GPSR4_16 F_(SD3_DAT7, IP11_3_0) 168 #define GPSR4_15 F_(SD3_DAT6, IP10_31_28) 169 #define GPSR4_14 F_(SD3_DAT5, IP10_27_24) 170 #define GPSR4_13 F_(SD3_DAT4, IP10_23_20) 171 #define GPSR4_12 F_(SD3_DAT3, IP10_19_16) 172 #define GPSR4_11 F_(SD3_DAT2, IP10_15_12) 173 #define GPSR4_10 F_(SD3_DAT1, IP10_11_8) 174 #define GPSR4_9 F_(SD3_DAT0, IP10_7_4) 175 #define GPSR4_8 F_(SD3_CMD, IP10_3_0) 176 #define GPSR4_7 F_(SD3_CLK, IP9_31_28) 177 #define GPSR4_6 F_(SD2_DS, IP9_27_24) 178 #define GPSR4_5 F_(SD2_DAT3, IP9_23_20) 179 #define GPSR4_4 F_(SD2_DAT2, IP9_19_16) 180 #define GPSR4_3 F_(SD2_DAT1, IP9_15_12) 181 #define GPSR4_2 F_(SD2_DAT0, IP9_11_8) 182 #define GPSR4_1 F_(SD2_CMD, IP9_7_4) 183 #define GPSR4_0 F_(SD2_CLK, IP9_3_0) 184 185 /* GPSR5 */ 186 #define GPSR5_25 F_(MLB_DAT, IP14_19_16) 187 #define GPSR5_24 F_(MLB_SIG, IP14_15_12) 188 #define GPSR5_23 F_(MLB_CLK, IP14_11_8) 189 #define GPSR5_22 FM(MSIOF0_RXD) 190 #define GPSR5_21 F_(MSIOF0_SS2, IP14_7_4) 191 #define GPSR5_20 FM(MSIOF0_TXD) 192 #define GPSR5_19 F_(MSIOF0_SS1, IP14_3_0) 193 #define GPSR5_18 F_(MSIOF0_SYNC, IP13_31_28) 194 #define GPSR5_17 FM(MSIOF0_SCK) 195 #define GPSR5_16 F_(HRTS0_N, IP13_27_24) 196 #define GPSR5_15 F_(HCTS0_N, IP13_23_20) 197 #define GPSR5_14 F_(HTX0, IP13_19_16) 198 #define GPSR5_13 F_(HRX0, IP13_15_12) 199 #define GPSR5_12 F_(HSCK0, IP13_11_8) 200 #define GPSR5_11 F_(RX2_A, IP13_7_4) 201 #define GPSR5_10 F_(TX2_A, IP13_3_0) 202 #define GPSR5_9 F_(SCK2, IP12_31_28) 203 #define GPSR5_8 F_(RTS1_N, IP12_27_24) 204 #define GPSR5_7 F_(CTS1_N, IP12_23_20) 205 #define GPSR5_6 F_(TX1_A, IP12_19_16) 206 #define GPSR5_5 F_(RX1_A, IP12_15_12) 207 #define GPSR5_4 F_(RTS0_N, IP12_11_8) 208 #define GPSR5_3 F_(CTS0_N, IP12_7_4) 209 #define GPSR5_2 F_(TX0, IP12_3_0) 210 #define GPSR5_1 F_(RX0, IP11_31_28) 211 #define GPSR5_0 F_(SCK0, IP11_27_24) 212 213 /* GPSR6 */ 214 #define GPSR6_31 F_(USB2_CH3_OVC, IP18_7_4) 215 #define GPSR6_30 F_(USB2_CH3_PWEN, IP18_3_0) 216 #define GPSR6_29 F_(USB30_OVC, IP17_31_28) 217 #define GPSR6_28 F_(USB30_PWEN, IP17_27_24) 218 #define GPSR6_27 F_(USB1_OVC, IP17_23_20) 219 #define GPSR6_26 F_(USB1_PWEN, IP17_19_16) 220 #define GPSR6_25 F_(USB0_OVC, IP17_15_12) 221 #define GPSR6_24 F_(USB0_PWEN, IP17_11_8) 222 #define GPSR6_23 F_(AUDIO_CLKB_B, IP17_7_4) 223 #define GPSR6_22 F_(AUDIO_CLKA_A, IP17_3_0) 224 #define GPSR6_21 F_(SSI_SDATA9_A, IP16_31_28) 225 #define GPSR6_20 F_(SSI_SDATA8, IP16_27_24) 226 #define GPSR6_19 F_(SSI_SDATA7, IP16_23_20) 227 #define GPSR6_18 F_(SSI_WS78, IP16_19_16) 228 #define GPSR6_17 F_(SSI_SCK78, IP16_15_12) 229 #define GPSR6_16 F_(SSI_SDATA6, IP16_11_8) 230 #define GPSR6_15 F_(SSI_WS6, IP16_7_4) 231 #define GPSR6_14 F_(SSI_SCK6, IP16_3_0) 232 #define GPSR6_13 FM(SSI_SDATA5) 233 #define GPSR6_12 FM(SSI_WS5) 234 #define GPSR6_11 FM(SSI_SCK5) 235 #define GPSR6_10 F_(SSI_SDATA4, IP15_31_28) 236 #define GPSR6_9 F_(SSI_WS4, IP15_27_24) 237 #define GPSR6_8 F_(SSI_SCK4, IP15_23_20) 238 #define GPSR6_7 F_(SSI_SDATA3, IP15_19_16) 239 #define GPSR6_6 F_(SSI_WS349, IP15_15_12) 240 #define GPSR6_5 F_(SSI_SCK349, IP15_11_8) 241 #define GPSR6_4 F_(SSI_SDATA2_A, IP15_7_4) 242 #define GPSR6_3 F_(SSI_SDATA1_A, IP15_3_0) 243 #define GPSR6_2 F_(SSI_SDATA0, IP14_31_28) 244 #define GPSR6_1 F_(SSI_WS01239, IP14_27_24) 245 #define GPSR6_0 F_(SSI_SCK01239, IP14_23_20) 246 247 /* GPSR7 */ 248 #define GPSR7_3 FM(GP7_03) 249 #define GPSR7_2 FM(GP7_02) 250 #define GPSR7_1 FM(AVS2) 251 #define GPSR7_0 FM(AVS1) 252 253 254 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ 255 #define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 256 #define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 257 #define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 258 #define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 259 #define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) FM(FSCLKST2_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 260 #define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 261 #define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 262 #define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 263 #define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 264 #define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) F_(0, 0) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 265 #define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) F_(0, 0) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 266 #define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) F_(0, 0) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) FM(FSCLKST2_N_B) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 267 #define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)F_(0, 0) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 268 #define IP1_23_20 FM(PWM1_A) F_(0, 0) F_(0, 0) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 269 #define IP1_27_24 FM(PWM2_A) F_(0, 0) F_(0, 0) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 270 #define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 271 #define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 272 #define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 273 #define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 274 275 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ 276 #define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 277 #define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 278 #define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 279 #define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 280 #define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 281 #define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 282 #define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 283 #define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 284 #define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 285 #define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 286 #define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 287 #define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 288 #define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 289 #define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 290 #define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 291 #define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 292 #define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 293 #define IP4_19_16 FM(CS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 294 #define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 295 #define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 296 #define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 297 #define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 298 #define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 299 #define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 300 #define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 301 #define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 302 #define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 303 #define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 304 #define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 305 #define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 306 #define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 307 #define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 308 #define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 309 #define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 310 #define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 311 #define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_C) FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 312 #define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 313 #define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 314 #define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 315 #define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 316 #define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 317 318 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ 319 #define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 320 #define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 321 #define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 322 #define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 323 #define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 324 #define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 325 #define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) FM(NFCE_N_B) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 326 #define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) FM(NFWP_N_B) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 327 #define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) FM(NFDATA14_B) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 328 #define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) FM(NFDATA15_B) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 329 #define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) FM(NFRB_N_B) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 330 #define IP9_3_0 FM(SD2_CLK) F_(0, 0) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 331 #define IP9_7_4 FM(SD2_CMD) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 332 #define IP9_11_8 FM(SD2_DAT0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 333 #define IP9_15_12 FM(SD2_DAT1) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 334 #define IP9_19_16 FM(SD2_DAT2) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 335 #define IP9_23_20 FM(SD2_DAT3) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 336 #define IP9_27_24 FM(SD2_DS) F_(0, 0) FM(NFALE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 337 #define IP9_31_28 FM(SD3_CLK) F_(0, 0) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 338 #define IP10_3_0 FM(SD3_CMD) F_(0, 0) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 339 #define IP10_7_4 FM(SD3_DAT0) F_(0, 0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 340 #define IP10_11_8 FM(SD3_DAT1) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 341 #define IP10_15_12 FM(SD3_DAT2) F_(0, 0) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 342 #define IP10_19_16 FM(SD3_DAT3) F_(0, 0) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 343 #define IP10_23_20 FM(SD3_DAT4) FM(SD2_CD_A) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 344 #define IP10_27_24 FM(SD3_DAT5) FM(SD2_WP_A) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 345 #define IP10_31_28 FM(SD3_DAT6) FM(SD3_CD) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 346 #define IP11_3_0 FM(SD3_DAT7) FM(SD3_WP) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 347 #define IP11_7_4 FM(SD3_DS) F_(0, 0) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 348 #define IP11_11_8 FM(SD0_CD) F_(0, 0) FM(NFDATA14_A) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 349 350 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ 351 #define IP11_15_12 FM(SD0_WP) F_(0, 0) FM(NFDATA15_A) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 352 #define IP11_19_16 FM(SD1_CD) F_(0, 0) FM(NFRB_N_A) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 353 #define IP11_23_20 FM(SD1_WP) F_(0, 0) FM(NFCE_N_A) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 354 #define IP11_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 355 #define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 356 #define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 357 #define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 358 #define IP12_11_8 FM(RTS0_N) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 359 #define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 360 #define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 361 #define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 362 #define IP12_27_24 FM(RTS1_N) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 363 #define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 364 #define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 365 #define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 366 #define IP13_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 367 #define IP13_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 368 #define IP13_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 369 #define IP13_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 370 #define IP13_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 371 #define IP13_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) FM(TX5_B) F_(0, 0) F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0) 372 #define IP14_3_0 FM(MSIOF0_SS1) FM(RX5_A) FM(NFWP_N_A) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 373 #define IP14_7_4 FM(MSIOF0_SS2) FM(TX5_A) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 374 #define IP14_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 375 #define IP14_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 376 #define IP14_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 377 #define IP14_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 378 #define IP14_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 379 380 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ 381 #define IP14_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 382 #define IP15_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 383 #define IP15_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 384 #define IP15_11_8 FM(SSI_SCK349) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 385 #define IP15_15_12 FM(SSI_WS349) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 386 #define IP15_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 387 #define IP15_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 388 #define IP15_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 389 #define IP15_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 390 #define IP16_3_0 FM(SSI_SCK6) FM(USB2_PWEN) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 391 #define IP16_7_4 FM(SSI_WS6) FM(USB2_OVC) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 392 #define IP16_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 393 #define IP16_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 394 #define IP16_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 395 #define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 396 #define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 397 #define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 398 #define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 399 #define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 400 #define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0) 401 #define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0) 402 #define IP17_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0) 403 #define IP17_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0) 404 #define IP17_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0) 405 #define IP17_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_N) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 406 #define IP18_3_0 FM(USB2_CH3_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0) 407 #define IP18_7_4 FM(USB2_CH3_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0) 408 409 #define PINMUX_GPSR \ 410 \ 411 GPSR6_31 \ 412 GPSR6_30 \ 413 GPSR6_29 \ 414 GPSR1_28 GPSR6_28 \ 415 GPSR1_27 GPSR6_27 \ 416 GPSR1_26 GPSR6_26 \ 417 GPSR1_25 GPSR5_25 GPSR6_25 \ 418 GPSR1_24 GPSR5_24 GPSR6_24 \ 419 GPSR1_23 GPSR5_23 GPSR6_23 \ 420 GPSR1_22 GPSR5_22 GPSR6_22 \ 421 GPSR1_21 GPSR5_21 GPSR6_21 \ 422 GPSR1_20 GPSR5_20 GPSR6_20 \ 423 GPSR1_19 GPSR5_19 GPSR6_19 \ 424 GPSR1_18 GPSR5_18 GPSR6_18 \ 425 GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \ 426 GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \ 427 GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \ 428 GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \ 429 GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \ 430 GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \ 431 GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \ 432 GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \ 433 GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \ 434 GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \ 435 GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \ 436 GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \ 437 GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \ 438 GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \ 439 GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \ 440 GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \ 441 GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \ 442 GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0 443 444 #define PINMUX_IPSR \ 445 \ 446 FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \ 447 FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \ 448 FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \ 449 FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \ 450 FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \ 451 FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \ 452 FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \ 453 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \ 454 \ 455 FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \ 456 FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \ 457 FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \ 458 FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 \ 459 FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \ 460 FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \ 461 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \ 462 FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \ 463 \ 464 FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \ 465 FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \ 466 FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \ 467 FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \ 468 FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \ 469 FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \ 470 FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \ 471 FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \ 472 \ 473 FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \ 474 FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \ 475 FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \ 476 FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \ 477 FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \ 478 FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \ 479 FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \ 480 FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \ 481 \ 482 FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 FM(IP18_3_0) IP18_3_0 \ 483 FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 FM(IP18_7_4) IP18_7_4 \ 484 FM(IP16_11_8) IP16_11_8 FM(IP17_11_8) IP17_11_8 \ 485 FM(IP16_15_12) IP16_15_12 FM(IP17_15_12) IP17_15_12 \ 486 FM(IP16_19_16) IP16_19_16 FM(IP17_19_16) IP17_19_16 \ 487 FM(IP16_23_20) IP16_23_20 FM(IP17_23_20) IP17_23_20 \ 488 FM(IP16_27_24) IP16_27_24 FM(IP17_27_24) IP17_27_24 \ 489 FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28 490 491 /* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ 492 #define MOD_SEL0_31_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3) FM(SEL_MSIOF3_4) F_(0, 0) F_(0, 0) F_(0, 0) 493 #define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3) 494 #define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0) 495 #define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1) 496 #define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1) 497 #define MOD_SEL0_21 FM(SEL_I2C2_0) FM(SEL_I2C2_1) 498 #define MOD_SEL0_20 FM(SEL_I2C1_0) FM(SEL_I2C1_1) 499 #define MOD_SEL0_19 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1) 500 #define MOD_SEL0_18_17 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3) 501 #define MOD_SEL0_16 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1) 502 #define MOD_SEL0_14_13 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) FM(SEL_HSCIF2_2) F_(0, 0) 503 #define MOD_SEL0_12 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1) 504 #define MOD_SEL0_11 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1) 505 #define MOD_SEL0_10 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1) 506 #define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0) 507 #define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0) 508 #define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1) 509 #define MOD_SEL0_4_3 FM(SEL_ADGA_0) FM(SEL_ADGA_1) FM(SEL_ADGA_2) FM(SEL_ADGA_3) 510 511 /* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ 512 #define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3) 513 #define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0) 514 #define MOD_SEL1_26 FM(SEL_TIMER_TMU1_0) FM(SEL_TIMER_TMU1_1) 515 #define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3) 516 #define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0) 517 #define MOD_SEL1_20 FM(SEL_SSI1_0) FM(SEL_SSI1_1) 518 #define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1) 519 #define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3) 520 #define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1) 521 #define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0) 522 #define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1) 523 #define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1) 524 #define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1) 525 #define MOD_SEL1_10 FM(SEL_SCIF_0) FM(SEL_SCIF_1) 526 #define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1) 527 #define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1) 528 #define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1) 529 #define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1) 530 #define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1) 531 #define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1) 532 #define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1) 533 #define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1) 534 535 /* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ 536 #define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1) 537 #define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1) 538 #define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1) 539 #define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3) 540 #define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1) 541 #define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 542 #define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1) 543 #define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1) 544 #define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1) 545 #define MOD_SEL2_18 FM(SEL_ADGB_0) FM(SEL_ADGB_1) 546 #define MOD_SEL2_17 FM(SEL_ADGC_0) FM(SEL_ADGC_1) 547 #define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1) 548 549 #define PINMUX_MOD_SELS \ 550 \ 551 MOD_SEL0_31_30_29 MOD_SEL1_31_30 MOD_SEL2_31 \ 552 MOD_SEL2_30 \ 553 MOD_SEL1_29_28_27 MOD_SEL2_29 \ 554 MOD_SEL0_28_27 MOD_SEL2_28_27 \ 555 MOD_SEL0_26_25_24 MOD_SEL1_26 MOD_SEL2_26 \ 556 MOD_SEL1_25_24 MOD_SEL2_25_24_23 \ 557 MOD_SEL0_23 MOD_SEL1_23_22_21 \ 558 MOD_SEL0_22 \ 559 MOD_SEL0_21 MOD_SEL2_21 \ 560 MOD_SEL0_20 MOD_SEL1_20 MOD_SEL2_20 \ 561 MOD_SEL0_19 MOD_SEL1_19 MOD_SEL2_19 \ 562 MOD_SEL0_18_17 MOD_SEL1_18_17 MOD_SEL2_18 \ 563 MOD_SEL2_17 \ 564 MOD_SEL0_16 MOD_SEL1_16 \ 565 MOD_SEL1_15_14 \ 566 MOD_SEL0_14_13 \ 567 MOD_SEL1_13 \ 568 MOD_SEL0_12 MOD_SEL1_12 \ 569 MOD_SEL0_11 MOD_SEL1_11 \ 570 MOD_SEL0_10 MOD_SEL1_10 \ 571 MOD_SEL0_9_8 MOD_SEL1_9 \ 572 MOD_SEL0_7_6 \ 573 MOD_SEL1_6 \ 574 MOD_SEL0_5 MOD_SEL1_5 \ 575 MOD_SEL0_4_3 MOD_SEL1_4 \ 576 MOD_SEL1_3 \ 577 MOD_SEL1_2 \ 578 MOD_SEL1_1 \ 579 MOD_SEL1_0 MOD_SEL2_0 580 581 /* 582 * These pins are not able to be muxed but have other properties 583 * that can be set, such as drive-strength or pull-up/pull-down enable. 584 */ 585 #define PINMUX_STATIC \ 586 FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \ 587 FM(QSPI0_IO2) FM(QSPI0_IO3) \ 588 FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \ 589 FM(QSPI1_IO2) FM(QSPI1_IO3) \ 590 FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \ 591 FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \ 592 FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \ 593 FM(AVB_TXCREFCLK) FM(AVB_MDIO) \ 594 FM(PRESETOUT) \ 595 FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) FM(DU_DOTCLKIN3) \ 596 FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR) 597 598 #define PINMUX_PHYS \ 599 FM(SCL0) FM(SDA0) FM(SCL3) FM(SDA3) FM(SCL5) FM(SDA5) 600 601 enum { 602 PINMUX_RESERVED = 0, 603 604 PINMUX_DATA_BEGIN, 605 GP_ALL(DATA), 606 PINMUX_DATA_END, 607 608 #define F_(x, y) 609 #define FM(x) FN_##x, 610 PINMUX_FUNCTION_BEGIN, 611 GP_ALL(FN), 612 PINMUX_GPSR 613 PINMUX_IPSR 614 PINMUX_MOD_SELS 615 PINMUX_FUNCTION_END, 616 #undef F_ 617 #undef FM 618 619 #define F_(x, y) 620 #define FM(x) x##_MARK, 621 PINMUX_MARK_BEGIN, 622 PINMUX_GPSR 623 PINMUX_IPSR 624 PINMUX_MOD_SELS 625 PINMUX_STATIC 626 PINMUX_PHYS 627 PINMUX_MARK_END, 628 #undef F_ 629 #undef FM 630 }; 631 632 static const u16 pinmux_data[] = { 633 PINMUX_DATA_GP_ALL(), 634 635 PINMUX_SINGLE(AVS1), 636 PINMUX_SINGLE(AVS2), 637 PINMUX_SINGLE(CLKOUT), 638 PINMUX_SINGLE(GP7_02), 639 PINMUX_SINGLE(GP7_03), 640 PINMUX_SINGLE(MSIOF0_RXD), 641 PINMUX_SINGLE(MSIOF0_SCK), 642 PINMUX_SINGLE(MSIOF0_TXD), 643 PINMUX_SINGLE(SSI_SCK5), 644 PINMUX_SINGLE(SSI_SDATA5), 645 PINMUX_SINGLE(SSI_WS5), 646 647 /* IPSR0 */ 648 PINMUX_IPSR_GPSR(IP0_3_0, AVB_MDC), 649 PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2), 650 651 PINMUX_IPSR_GPSR(IP0_7_4, AVB_MAGIC), 652 PINMUX_IPSR_MSEL(IP0_7_4, MSIOF2_SS1_C, SEL_MSIOF2_2), 653 PINMUX_IPSR_MSEL(IP0_7_4, SCK4_A, SEL_SCIF4_0), 654 655 PINMUX_IPSR_GPSR(IP0_11_8, AVB_PHY_INT), 656 PINMUX_IPSR_MSEL(IP0_11_8, MSIOF2_SYNC_C, SEL_MSIOF2_2), 657 PINMUX_IPSR_MSEL(IP0_11_8, RX4_A, SEL_SCIF4_0), 658 659 PINMUX_IPSR_GPSR(IP0_15_12, AVB_LINK), 660 PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2), 661 PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0), 662 663 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, I2C_SEL_5_0, SEL_ETHERAVB_0), 664 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, MSIOF2_RXD_C, I2C_SEL_5_0, SEL_MSIOF2_2), 665 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, CTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0), 666 PINMUX_IPSR_MSEL(IP0_19_16, FSCLKST2_N_A, I2C_SEL_5_0), 667 PINMUX_IPSR_PHYS(IP0_19_16, SCL5, I2C_SEL_5_1), 668 669 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, I2C_SEL_5_0, SEL_ETHERAVB_0), 670 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C, I2C_SEL_5_0, SEL_MSIOF2_2), 671 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0), 672 PINMUX_IPSR_PHYS(IP0_23_20, SDA5, I2C_SEL_5_1), 673 674 PINMUX_IPSR_GPSR(IP0_27_24, IRQ0), 675 PINMUX_IPSR_GPSR(IP0_27_24, QPOLB), 676 PINMUX_IPSR_GPSR(IP0_27_24, DU_CDE), 677 PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1), 678 PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1), 679 PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_B, SEL_CANFD0_1), 680 PINMUX_IPSR_MSEL(IP0_27_24, MSIOF3_SS2_E, SEL_MSIOF3_4), 681 682 PINMUX_IPSR_GPSR(IP0_31_28, IRQ1), 683 PINMUX_IPSR_GPSR(IP0_31_28, QPOLA), 684 PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP), 685 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1), 686 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1), 687 PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1), 688 PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_SS1_E, SEL_MSIOF3_4), 689 690 /* IPSR1 */ 691 PINMUX_IPSR_GPSR(IP1_3_0, IRQ2), 692 PINMUX_IPSR_GPSR(IP1_3_0, QCPV_QDE), 693 PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE), 694 PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1), 695 PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1), 696 PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_SYNC_E, SEL_MSIOF3_4), 697 698 PINMUX_IPSR_GPSR(IP1_7_4, IRQ3), 699 PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE), 700 PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1), 701 PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1), 702 PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1), 703 PINMUX_IPSR_MSEL(IP1_7_4, MSIOF3_SCK_E, SEL_MSIOF3_4), 704 705 PINMUX_IPSR_GPSR(IP1_11_8, IRQ4), 706 PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS), 707 PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC), 708 PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1), 709 PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1), 710 PINMUX_IPSR_MSEL(IP1_11_8, MSIOF3_RXD_E, SEL_MSIOF3_4), 711 712 PINMUX_IPSR_GPSR(IP1_15_12, IRQ5), 713 PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE), 714 PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC), 715 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1), 716 PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1), 717 PINMUX_IPSR_GPSR(IP1_15_12, FSCLKST2_N_B), 718 PINMUX_IPSR_MSEL(IP1_15_12, MSIOF3_TXD_E, SEL_MSIOF3_4), 719 720 PINMUX_IPSR_GPSR(IP1_19_16, PWM0), 721 PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS), 722 PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1), 723 PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1), 724 725 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, PWM1_A, I2C_SEL_3_0, SEL_PWM1_0), 726 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3), 727 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1), 728 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1), 729 PINMUX_IPSR_PHYS(IP1_23_20, SCL3, I2C_SEL_3_1), 730 731 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0), 732 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D, I2C_SEL_3_0, SEL_HSCIF3_3), 733 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, IETX_B, I2C_SEL_3_0, SEL_IEBUS_1), 734 PINMUX_IPSR_PHYS(IP1_27_24, SDA3, I2C_SEL_3_1), 735 736 PINMUX_IPSR_GPSR(IP1_31_28, A0), 737 PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16), 738 PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SYNC_B, SEL_MSIOF3_1), 739 PINMUX_IPSR_GPSR(IP1_31_28, VI4_DATA8), 740 PINMUX_IPSR_GPSR(IP1_31_28, DU_DB0), 741 PINMUX_IPSR_MSEL(IP1_31_28, PWM3_A, SEL_PWM3_0), 742 743 /* IPSR2 */ 744 PINMUX_IPSR_GPSR(IP2_3_0, A1), 745 PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT17), 746 PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_TXD_B, SEL_MSIOF3_1), 747 PINMUX_IPSR_GPSR(IP2_3_0, VI4_DATA9), 748 PINMUX_IPSR_GPSR(IP2_3_0, DU_DB1), 749 PINMUX_IPSR_MSEL(IP2_3_0, PWM4_A, SEL_PWM4_0), 750 751 PINMUX_IPSR_GPSR(IP2_7_4, A2), 752 PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT18), 753 PINMUX_IPSR_MSEL(IP2_7_4, MSIOF3_SCK_B, SEL_MSIOF3_1), 754 PINMUX_IPSR_GPSR(IP2_7_4, VI4_DATA10), 755 PINMUX_IPSR_GPSR(IP2_7_4, DU_DB2), 756 PINMUX_IPSR_MSEL(IP2_7_4, PWM5_A, SEL_PWM5_0), 757 758 PINMUX_IPSR_GPSR(IP2_11_8, A3), 759 PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT19), 760 PINMUX_IPSR_MSEL(IP2_11_8, MSIOF3_RXD_B, SEL_MSIOF3_1), 761 PINMUX_IPSR_GPSR(IP2_11_8, VI4_DATA11), 762 PINMUX_IPSR_GPSR(IP2_11_8, DU_DB3), 763 PINMUX_IPSR_MSEL(IP2_11_8, PWM6_A, SEL_PWM6_0), 764 765 PINMUX_IPSR_GPSR(IP2_15_12, A4), 766 PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT20), 767 PINMUX_IPSR_MSEL(IP2_15_12, MSIOF3_SS1_B, SEL_MSIOF3_1), 768 PINMUX_IPSR_GPSR(IP2_15_12, VI4_DATA12), 769 PINMUX_IPSR_GPSR(IP2_15_12, VI5_DATA12), 770 PINMUX_IPSR_GPSR(IP2_15_12, DU_DB4), 771 772 PINMUX_IPSR_GPSR(IP2_19_16, A5), 773 PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT21), 774 PINMUX_IPSR_MSEL(IP2_19_16, MSIOF3_SS2_B, SEL_MSIOF3_1), 775 PINMUX_IPSR_MSEL(IP2_19_16, SCK4_B, SEL_SCIF4_1), 776 PINMUX_IPSR_GPSR(IP2_19_16, VI4_DATA13), 777 PINMUX_IPSR_GPSR(IP2_19_16, VI5_DATA13), 778 PINMUX_IPSR_GPSR(IP2_19_16, DU_DB5), 779 780 PINMUX_IPSR_GPSR(IP2_23_20, A6), 781 PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT22), 782 PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_SS1_A, SEL_MSIOF2_0), 783 PINMUX_IPSR_MSEL(IP2_23_20, RX4_B, SEL_SCIF4_1), 784 PINMUX_IPSR_GPSR(IP2_23_20, VI4_DATA14), 785 PINMUX_IPSR_GPSR(IP2_23_20, VI5_DATA14), 786 PINMUX_IPSR_GPSR(IP2_23_20, DU_DB6), 787 788 PINMUX_IPSR_GPSR(IP2_27_24, A7), 789 PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT23), 790 PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SS2_A, SEL_MSIOF2_0), 791 PINMUX_IPSR_MSEL(IP2_27_24, TX4_B, SEL_SCIF4_1), 792 PINMUX_IPSR_GPSR(IP2_27_24, VI4_DATA15), 793 PINMUX_IPSR_GPSR(IP2_27_24, VI5_DATA15), 794 PINMUX_IPSR_GPSR(IP2_27_24, DU_DB7), 795 796 PINMUX_IPSR_GPSR(IP2_31_28, A8), 797 PINMUX_IPSR_MSEL(IP2_31_28, RX3_B, SEL_SCIF3_1), 798 PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0), 799 PINMUX_IPSR_MSEL(IP2_31_28, HRX4_B, SEL_HSCIF4_1), 800 PINMUX_IPSR_MSEL(IP2_31_28, SDA6_A, SEL_I2C6_0), 801 PINMUX_IPSR_MSEL(IP2_31_28, AVB_AVTP_MATCH_B, SEL_ETHERAVB_1), 802 PINMUX_IPSR_MSEL(IP2_31_28, PWM1_B, SEL_PWM1_1), 803 804 /* IPSR3 */ 805 PINMUX_IPSR_GPSR(IP3_3_0, A9), 806 PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0), 807 PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1), 808 PINMUX_IPSR_GPSR(IP3_3_0, VI5_VSYNC_N), 809 810 PINMUX_IPSR_GPSR(IP3_7_4, A10), 811 PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0), 812 PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_B, SEL_SCIF4_1), 813 PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N), 814 815 PINMUX_IPSR_GPSR(IP3_11_8, A11), 816 PINMUX_IPSR_MSEL(IP3_11_8, TX3_B, SEL_SCIF3_1), 817 PINMUX_IPSR_MSEL(IP3_11_8, MSIOF2_TXD_A, SEL_MSIOF2_0), 818 PINMUX_IPSR_MSEL(IP3_11_8, HTX4_B, SEL_HSCIF4_1), 819 PINMUX_IPSR_GPSR(IP3_11_8, HSCK4), 820 PINMUX_IPSR_GPSR(IP3_11_8, VI5_FIELD), 821 PINMUX_IPSR_MSEL(IP3_11_8, SCL6_A, SEL_I2C6_0), 822 PINMUX_IPSR_MSEL(IP3_11_8, AVB_AVTP_CAPTURE_B, SEL_ETHERAVB_1), 823 PINMUX_IPSR_MSEL(IP3_11_8, PWM2_B, SEL_PWM2_1), 824 825 PINMUX_IPSR_GPSR(IP3_15_12, A12), 826 PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT12), 827 PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SCK_C, SEL_MSIOF3_2), 828 PINMUX_IPSR_MSEL(IP3_15_12, HRX4_A, SEL_HSCIF4_0), 829 PINMUX_IPSR_GPSR(IP3_15_12, VI5_DATA8), 830 PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4), 831 832 PINMUX_IPSR_GPSR(IP3_19_16, A13), 833 PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT13), 834 PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SYNC_C, SEL_MSIOF3_2), 835 PINMUX_IPSR_MSEL(IP3_19_16, HTX4_A, SEL_HSCIF4_0), 836 PINMUX_IPSR_GPSR(IP3_19_16, VI5_DATA9), 837 PINMUX_IPSR_GPSR(IP3_19_16, DU_DG5), 838 839 PINMUX_IPSR_GPSR(IP3_23_20, A14), 840 PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT14), 841 PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_C, SEL_MSIOF3_2), 842 PINMUX_IPSR_GPSR(IP3_23_20, HCTS4_N), 843 PINMUX_IPSR_GPSR(IP3_23_20, VI5_DATA10), 844 PINMUX_IPSR_GPSR(IP3_23_20, DU_DG6), 845 846 PINMUX_IPSR_GPSR(IP3_27_24, A15), 847 PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT15), 848 PINMUX_IPSR_MSEL(IP3_27_24, MSIOF3_TXD_C, SEL_MSIOF3_2), 849 PINMUX_IPSR_GPSR(IP3_27_24, HRTS4_N), 850 PINMUX_IPSR_GPSR(IP3_27_24, VI5_DATA11), 851 PINMUX_IPSR_GPSR(IP3_27_24, DU_DG7), 852 853 PINMUX_IPSR_GPSR(IP3_31_28, A16), 854 PINMUX_IPSR_GPSR(IP3_31_28, LCDOUT8), 855 PINMUX_IPSR_GPSR(IP3_31_28, VI4_FIELD), 856 PINMUX_IPSR_GPSR(IP3_31_28, DU_DG0), 857 858 /* IPSR4 */ 859 PINMUX_IPSR_GPSR(IP4_3_0, A17), 860 PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT9), 861 PINMUX_IPSR_GPSR(IP4_3_0, VI4_VSYNC_N), 862 PINMUX_IPSR_GPSR(IP4_3_0, DU_DG1), 863 864 PINMUX_IPSR_GPSR(IP4_7_4, A18), 865 PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT10), 866 PINMUX_IPSR_GPSR(IP4_7_4, VI4_HSYNC_N), 867 PINMUX_IPSR_GPSR(IP4_7_4, DU_DG2), 868 869 PINMUX_IPSR_GPSR(IP4_11_8, A19), 870 PINMUX_IPSR_GPSR(IP4_11_8, LCDOUT11), 871 PINMUX_IPSR_GPSR(IP4_11_8, VI4_CLKENB), 872 PINMUX_IPSR_GPSR(IP4_11_8, DU_DG3), 873 874 PINMUX_IPSR_GPSR(IP4_15_12, CS0_N), 875 PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB), 876 877 PINMUX_IPSR_GPSR(IP4_19_16, CS1_N), 878 PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK), 879 PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1), 880 881 PINMUX_IPSR_GPSR(IP4_23_20, BS_N), 882 PINMUX_IPSR_GPSR(IP4_23_20, QSTVA_QVS), 883 PINMUX_IPSR_MSEL(IP4_23_20, MSIOF3_SCK_D, SEL_MSIOF3_3), 884 PINMUX_IPSR_GPSR(IP4_23_20, SCK3), 885 PINMUX_IPSR_GPSR(IP4_23_20, HSCK3), 886 PINMUX_IPSR_GPSR(IP4_23_20, CAN1_TX), 887 PINMUX_IPSR_GPSR(IP4_23_20, CANFD1_TX), 888 PINMUX_IPSR_MSEL(IP4_23_20, IETX_A, SEL_IEBUS_0), 889 890 PINMUX_IPSR_GPSR(IP4_27_24, RD_N), 891 PINMUX_IPSR_MSEL(IP4_27_24, MSIOF3_SYNC_D, SEL_MSIOF3_3), 892 PINMUX_IPSR_MSEL(IP4_27_24, RX3_A, SEL_SCIF3_0), 893 PINMUX_IPSR_MSEL(IP4_27_24, HRX3_A, SEL_HSCIF3_0), 894 PINMUX_IPSR_MSEL(IP4_27_24, CAN0_TX_A, SEL_RCAN0_0), 895 PINMUX_IPSR_MSEL(IP4_27_24, CANFD0_TX_A, SEL_CANFD0_0), 896 897 PINMUX_IPSR_GPSR(IP4_31_28, RD_WR_N), 898 PINMUX_IPSR_MSEL(IP4_31_28, MSIOF3_RXD_D, SEL_MSIOF3_3), 899 PINMUX_IPSR_MSEL(IP4_31_28, TX3_A, SEL_SCIF3_0), 900 PINMUX_IPSR_MSEL(IP4_31_28, HTX3_A, SEL_HSCIF3_0), 901 PINMUX_IPSR_MSEL(IP4_31_28, CAN0_RX_A, SEL_RCAN0_0), 902 PINMUX_IPSR_MSEL(IP4_31_28, CANFD0_RX_A, SEL_CANFD0_0), 903 904 /* IPSR5 */ 905 PINMUX_IPSR_GPSR(IP5_3_0, WE0_N), 906 PINMUX_IPSR_MSEL(IP5_3_0, MSIOF3_TXD_D, SEL_MSIOF3_3), 907 PINMUX_IPSR_GPSR(IP5_3_0, CTS3_N), 908 PINMUX_IPSR_GPSR(IP5_3_0, HCTS3_N), 909 PINMUX_IPSR_MSEL(IP5_3_0, SCL6_B, SEL_I2C6_1), 910 PINMUX_IPSR_GPSR(IP5_3_0, CAN_CLK), 911 PINMUX_IPSR_MSEL(IP5_3_0, IECLK_A, SEL_IEBUS_0), 912 913 PINMUX_IPSR_GPSR(IP5_7_4, WE1_N), 914 PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3), 915 PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N), 916 PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N), 917 PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1), 918 PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX), 919 PINMUX_IPSR_GPSR(IP5_7_4, CANFD1_RX), 920 PINMUX_IPSR_MSEL(IP5_7_4, IERX_A, SEL_IEBUS_0), 921 922 PINMUX_IPSR_MSEL(IP5_11_8, EX_WAIT0_A, SEL_LBSC_0), 923 PINMUX_IPSR_GPSR(IP5_11_8, QCLK), 924 PINMUX_IPSR_GPSR(IP5_11_8, VI4_CLK), 925 PINMUX_IPSR_GPSR(IP5_11_8, DU_DOTCLKOUT0), 926 927 PINMUX_IPSR_GPSR(IP5_15_12, D0), 928 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF2_SS1_B, SEL_MSIOF2_1), 929 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF3_SCK_A, SEL_MSIOF3_0), 930 PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA16), 931 PINMUX_IPSR_GPSR(IP5_15_12, VI5_DATA0), 932 933 PINMUX_IPSR_GPSR(IP5_19_16, D1), 934 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF2_SS2_B, SEL_MSIOF2_1), 935 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF3_SYNC_A, SEL_MSIOF3_0), 936 PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA17), 937 PINMUX_IPSR_GPSR(IP5_19_16, VI5_DATA1), 938 939 PINMUX_IPSR_GPSR(IP5_23_20, D2), 940 PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_RXD_A, SEL_MSIOF3_0), 941 PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA18), 942 PINMUX_IPSR_GPSR(IP5_23_20, VI5_DATA2), 943 944 PINMUX_IPSR_GPSR(IP5_27_24, D3), 945 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0), 946 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19), 947 PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3), 948 949 PINMUX_IPSR_GPSR(IP5_31_28, D4), 950 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF2_SCK_B, SEL_MSIOF2_1), 951 PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA20), 952 PINMUX_IPSR_GPSR(IP5_31_28, VI5_DATA4), 953 954 /* IPSR6 */ 955 PINMUX_IPSR_GPSR(IP6_3_0, D5), 956 PINMUX_IPSR_MSEL(IP6_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1), 957 PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA21), 958 PINMUX_IPSR_GPSR(IP6_3_0, VI5_DATA5), 959 960 PINMUX_IPSR_GPSR(IP6_7_4, D6), 961 PINMUX_IPSR_MSEL(IP6_7_4, MSIOF2_RXD_B, SEL_MSIOF2_1), 962 PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA22), 963 PINMUX_IPSR_GPSR(IP6_7_4, VI5_DATA6), 964 965 PINMUX_IPSR_GPSR(IP6_11_8, D7), 966 PINMUX_IPSR_MSEL(IP6_11_8, MSIOF2_TXD_B, SEL_MSIOF2_1), 967 PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA23), 968 PINMUX_IPSR_GPSR(IP6_11_8, VI5_DATA7), 969 970 PINMUX_IPSR_GPSR(IP6_15_12, D8), 971 PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT0), 972 PINMUX_IPSR_MSEL(IP6_15_12, MSIOF2_SCK_D, SEL_MSIOF2_3), 973 PINMUX_IPSR_MSEL(IP6_15_12, SCK4_C, SEL_SCIF4_2), 974 PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA0_A, SEL_VIN4_0), 975 PINMUX_IPSR_GPSR(IP6_15_12, DU_DR0), 976 977 PINMUX_IPSR_GPSR(IP6_19_16, D9), 978 PINMUX_IPSR_GPSR(IP6_19_16, LCDOUT1), 979 PINMUX_IPSR_MSEL(IP6_19_16, MSIOF2_SYNC_D, SEL_MSIOF2_3), 980 PINMUX_IPSR_MSEL(IP6_19_16, VI4_DATA1_A, SEL_VIN4_0), 981 PINMUX_IPSR_GPSR(IP6_19_16, DU_DR1), 982 983 PINMUX_IPSR_GPSR(IP6_23_20, D10), 984 PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT2), 985 PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_RXD_D, SEL_MSIOF2_3), 986 PINMUX_IPSR_MSEL(IP6_23_20, HRX3_B, SEL_HSCIF3_1), 987 PINMUX_IPSR_MSEL(IP6_23_20, VI4_DATA2_A, SEL_VIN4_0), 988 PINMUX_IPSR_MSEL(IP6_23_20, CTS4_N_C, SEL_SCIF4_2), 989 PINMUX_IPSR_GPSR(IP6_23_20, DU_DR2), 990 991 PINMUX_IPSR_GPSR(IP6_27_24, D11), 992 PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT3), 993 PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3), 994 PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1), 995 PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0), 996 PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_C, SEL_SCIF4_2), 997 PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3), 998 999 PINMUX_IPSR_GPSR(IP6_31_28, D12), 1000 PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT4), 1001 PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3), 1002 PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2), 1003 PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0), 1004 PINMUX_IPSR_GPSR(IP6_31_28, DU_DR4), 1005 1006 /* IPSR7 */ 1007 PINMUX_IPSR_GPSR(IP7_3_0, D13), 1008 PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT5), 1009 PINMUX_IPSR_MSEL(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3), 1010 PINMUX_IPSR_MSEL(IP7_3_0, TX4_C, SEL_SCIF4_2), 1011 PINMUX_IPSR_MSEL(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0), 1012 PINMUX_IPSR_GPSR(IP7_3_0, DU_DR5), 1013 1014 PINMUX_IPSR_GPSR(IP7_7_4, D14), 1015 PINMUX_IPSR_GPSR(IP7_7_4, LCDOUT6), 1016 PINMUX_IPSR_MSEL(IP7_7_4, MSIOF3_SS1_A, SEL_MSIOF3_0), 1017 PINMUX_IPSR_MSEL(IP7_7_4, HRX3_C, SEL_HSCIF3_2), 1018 PINMUX_IPSR_MSEL(IP7_7_4, VI4_DATA6_A, SEL_VIN4_0), 1019 PINMUX_IPSR_GPSR(IP7_7_4, DU_DR6), 1020 PINMUX_IPSR_MSEL(IP7_7_4, SCL6_C, SEL_I2C6_2), 1021 1022 PINMUX_IPSR_GPSR(IP7_11_8, D15), 1023 PINMUX_IPSR_GPSR(IP7_11_8, LCDOUT7), 1024 PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SS2_A, SEL_MSIOF3_0), 1025 PINMUX_IPSR_MSEL(IP7_11_8, HTX3_C, SEL_HSCIF3_2), 1026 PINMUX_IPSR_MSEL(IP7_11_8, VI4_DATA7_A, SEL_VIN4_0), 1027 PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7), 1028 PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2), 1029 1030 PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK), 1031 PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4), 1032 PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1), 1033 1034 PINMUX_IPSR_GPSR(IP7_23_20, SD0_CMD), 1035 PINMUX_IPSR_MSEL(IP7_23_20, MSIOF1_SYNC_E, SEL_MSIOF1_4), 1036 PINMUX_IPSR_MSEL(IP7_23_20, STP_IVCXO27_0_B, SEL_SSP1_0_1), 1037 1038 PINMUX_IPSR_GPSR(IP7_27_24, SD0_DAT0), 1039 PINMUX_IPSR_MSEL(IP7_27_24, MSIOF1_RXD_E, SEL_MSIOF1_4), 1040 PINMUX_IPSR_MSEL(IP7_27_24, TS_SCK0_B, SEL_TSIF0_1), 1041 PINMUX_IPSR_MSEL(IP7_27_24, STP_ISCLK_0_B, SEL_SSP1_0_1), 1042 1043 PINMUX_IPSR_GPSR(IP7_31_28, SD0_DAT1), 1044 PINMUX_IPSR_MSEL(IP7_31_28, MSIOF1_TXD_E, SEL_MSIOF1_4), 1045 PINMUX_IPSR_MSEL(IP7_31_28, TS_SPSYNC0_B, SEL_TSIF0_1), 1046 PINMUX_IPSR_MSEL(IP7_31_28, STP_ISSYNC_0_B, SEL_SSP1_0_1), 1047 1048 /* IPSR8 */ 1049 PINMUX_IPSR_GPSR(IP8_3_0, SD0_DAT2), 1050 PINMUX_IPSR_MSEL(IP8_3_0, MSIOF1_SS1_E, SEL_MSIOF1_4), 1051 PINMUX_IPSR_MSEL(IP8_3_0, TS_SDAT0_B, SEL_TSIF0_1), 1052 PINMUX_IPSR_MSEL(IP8_3_0, STP_ISD_0_B, SEL_SSP1_0_1), 1053 1054 PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT3), 1055 PINMUX_IPSR_MSEL(IP8_7_4, MSIOF1_SS2_E, SEL_MSIOF1_4), 1056 PINMUX_IPSR_MSEL(IP8_7_4, TS_SDEN0_B, SEL_TSIF0_1), 1057 PINMUX_IPSR_MSEL(IP8_7_4, STP_ISEN_0_B, SEL_SSP1_0_1), 1058 1059 PINMUX_IPSR_GPSR(IP8_11_8, SD1_CLK), 1060 PINMUX_IPSR_MSEL(IP8_11_8, MSIOF1_SCK_G, SEL_MSIOF1_6), 1061 PINMUX_IPSR_MSEL(IP8_11_8, SIM0_CLK_A, SEL_SIMCARD_0), 1062 1063 PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD), 1064 PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6), 1065 PINMUX_IPSR_GPSR(IP8_15_12, NFCE_N_B), 1066 PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0), 1067 PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1), 1068 1069 PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0), 1070 PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4), 1071 PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6), 1072 PINMUX_IPSR_GPSR(IP8_19_16, NFWP_N_B), 1073 PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1), 1074 PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1), 1075 1076 PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1), 1077 PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5), 1078 PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6), 1079 PINMUX_IPSR_GPSR(IP8_23_20, NFDATA14_B), 1080 PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1), 1081 PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1), 1082 1083 PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2), 1084 PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6), 1085 PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6), 1086 PINMUX_IPSR_GPSR(IP8_27_24, NFDATA15_B), 1087 PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1), 1088 PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1), 1089 1090 PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3), 1091 PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7), 1092 PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6), 1093 PINMUX_IPSR_GPSR(IP8_31_28, NFRB_N_B), 1094 PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1), 1095 PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1), 1096 1097 /* IPSR9 */ 1098 PINMUX_IPSR_GPSR(IP9_3_0, SD2_CLK), 1099 PINMUX_IPSR_GPSR(IP9_3_0, NFDATA8), 1100 1101 PINMUX_IPSR_GPSR(IP9_7_4, SD2_CMD), 1102 PINMUX_IPSR_GPSR(IP9_7_4, NFDATA9), 1103 1104 PINMUX_IPSR_GPSR(IP9_11_8, SD2_DAT0), 1105 PINMUX_IPSR_GPSR(IP9_11_8, NFDATA10), 1106 1107 PINMUX_IPSR_GPSR(IP9_15_12, SD2_DAT1), 1108 PINMUX_IPSR_GPSR(IP9_15_12, NFDATA11), 1109 1110 PINMUX_IPSR_GPSR(IP9_19_16, SD2_DAT2), 1111 PINMUX_IPSR_GPSR(IP9_19_16, NFDATA12), 1112 1113 PINMUX_IPSR_GPSR(IP9_23_20, SD2_DAT3), 1114 PINMUX_IPSR_GPSR(IP9_23_20, NFDATA13), 1115 1116 PINMUX_IPSR_GPSR(IP9_27_24, SD2_DS), 1117 PINMUX_IPSR_GPSR(IP9_27_24, NFALE), 1118 PINMUX_IPSR_GPSR(IP9_27_24, SATA_DEVSLP_B), 1119 1120 PINMUX_IPSR_GPSR(IP9_31_28, SD3_CLK), 1121 PINMUX_IPSR_GPSR(IP9_31_28, NFWE_N), 1122 1123 /* IPSR10 */ 1124 PINMUX_IPSR_GPSR(IP10_3_0, SD3_CMD), 1125 PINMUX_IPSR_GPSR(IP10_3_0, NFRE_N), 1126 1127 PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT0), 1128 PINMUX_IPSR_GPSR(IP10_7_4, NFDATA0), 1129 1130 PINMUX_IPSR_GPSR(IP10_11_8, SD3_DAT1), 1131 PINMUX_IPSR_GPSR(IP10_11_8, NFDATA1), 1132 1133 PINMUX_IPSR_GPSR(IP10_15_12, SD3_DAT2), 1134 PINMUX_IPSR_GPSR(IP10_15_12, NFDATA2), 1135 1136 PINMUX_IPSR_GPSR(IP10_19_16, SD3_DAT3), 1137 PINMUX_IPSR_GPSR(IP10_19_16, NFDATA3), 1138 1139 PINMUX_IPSR_GPSR(IP10_23_20, SD3_DAT4), 1140 PINMUX_IPSR_MSEL(IP10_23_20, SD2_CD_A, SEL_SDHI2_0), 1141 PINMUX_IPSR_GPSR(IP10_23_20, NFDATA4), 1142 1143 PINMUX_IPSR_GPSR(IP10_27_24, SD3_DAT5), 1144 PINMUX_IPSR_MSEL(IP10_27_24, SD2_WP_A, SEL_SDHI2_0), 1145 PINMUX_IPSR_GPSR(IP10_27_24, NFDATA5), 1146 1147 PINMUX_IPSR_GPSR(IP10_31_28, SD3_DAT6), 1148 PINMUX_IPSR_GPSR(IP10_31_28, SD3_CD), 1149 PINMUX_IPSR_GPSR(IP10_31_28, NFDATA6), 1150 1151 /* IPSR11 */ 1152 PINMUX_IPSR_GPSR(IP11_3_0, SD3_DAT7), 1153 PINMUX_IPSR_GPSR(IP11_3_0, SD3_WP), 1154 PINMUX_IPSR_GPSR(IP11_3_0, NFDATA7), 1155 1156 PINMUX_IPSR_GPSR(IP11_7_4, SD3_DS), 1157 PINMUX_IPSR_GPSR(IP11_7_4, NFCLE), 1158 1159 PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD), 1160 PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1), 1161 PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0), 1162 1163 PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP), 1164 PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1), 1165 1166 PINMUX_IPSR_MSEL(IP11_19_16, SD1_CD, I2C_SEL_0_0), 1167 PINMUX_IPSR_PHYS_MSEL(IP11_19_16, SIM0_CLK_B, I2C_SEL_0_0, SEL_SIMCARD_1), 1168 PINMUX_IPSR_PHYS(IP11_19_16, SCL0, I2C_SEL_0_1), 1169 1170 PINMUX_IPSR_MSEL(IP11_23_20, SD1_WP, I2C_SEL_0_0), 1171 PINMUX_IPSR_PHYS_MSEL(IP11_23_20, SIM0_D_B, I2C_SEL_0_0, SEL_SIMCARD_1), 1172 PINMUX_IPSR_PHYS(IP11_23_20, SDA0, I2C_SEL_0_1), 1173 1174 PINMUX_IPSR_GPSR(IP11_27_24, SCK0), 1175 PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1), 1176 PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1), 1177 PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADGC_1), 1178 PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0), 1179 PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1), 1180 PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2), 1181 PINMUX_IPSR_MSEL(IP11_27_24, RIF0_CLK_B, SEL_DRIF0_1), 1182 PINMUX_IPSR_GPSR(IP11_27_24, ADICHS2), 1183 PINMUX_IPSR_MSEL(IP11_27_24, SCK5_B, SEL_SCIF5_1), 1184 1185 PINMUX_IPSR_GPSR(IP11_31_28, RX0), 1186 PINMUX_IPSR_MSEL(IP11_31_28, HRX1_B, SEL_HSCIF1_1), 1187 PINMUX_IPSR_MSEL(IP11_31_28, TS_SCK0_C, SEL_TSIF0_2), 1188 PINMUX_IPSR_MSEL(IP11_31_28, STP_ISCLK_0_C, SEL_SSP1_0_2), 1189 PINMUX_IPSR_MSEL(IP11_31_28, RIF0_D0_B, SEL_DRIF0_1), 1190 1191 /* IPSR12 */ 1192 PINMUX_IPSR_GPSR(IP12_3_0, TX0), 1193 PINMUX_IPSR_MSEL(IP12_3_0, HTX1_B, SEL_HSCIF1_1), 1194 PINMUX_IPSR_MSEL(IP12_3_0, TS_SPSYNC0_C, SEL_TSIF0_2), 1195 PINMUX_IPSR_MSEL(IP12_3_0, STP_ISSYNC_0_C, SEL_SSP1_0_2), 1196 PINMUX_IPSR_MSEL(IP12_3_0, RIF0_D1_B, SEL_DRIF0_1), 1197 1198 PINMUX_IPSR_GPSR(IP12_7_4, CTS0_N), 1199 PINMUX_IPSR_MSEL(IP12_7_4, HCTS1_N_B, SEL_HSCIF1_1), 1200 PINMUX_IPSR_MSEL(IP12_7_4, MSIOF1_SYNC_B, SEL_MSIOF1_1), 1201 PINMUX_IPSR_MSEL(IP12_7_4, TS_SPSYNC1_C, SEL_TSIF1_2), 1202 PINMUX_IPSR_MSEL(IP12_7_4, STP_ISSYNC_1_C, SEL_SSP1_1_2), 1203 PINMUX_IPSR_MSEL(IP12_7_4, RIF1_SYNC_B, SEL_DRIF1_1), 1204 PINMUX_IPSR_GPSR(IP12_7_4, AUDIO_CLKOUT_C), 1205 PINMUX_IPSR_GPSR(IP12_7_4, ADICS_SAMP), 1206 1207 PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N), 1208 PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1), 1209 PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1), 1210 PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADGA_1), 1211 PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0), 1212 PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2), 1213 PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1), 1214 PINMUX_IPSR_GPSR(IP12_11_8, ADICHS1), 1215 1216 PINMUX_IPSR_MSEL(IP12_15_12, RX1_A, SEL_SCIF1_0), 1217 PINMUX_IPSR_MSEL(IP12_15_12, HRX1_A, SEL_HSCIF1_0), 1218 PINMUX_IPSR_MSEL(IP12_15_12, TS_SDAT0_C, SEL_TSIF0_2), 1219 PINMUX_IPSR_MSEL(IP12_15_12, STP_ISD_0_C, SEL_SSP1_0_2), 1220 PINMUX_IPSR_MSEL(IP12_15_12, RIF1_CLK_C, SEL_DRIF1_2), 1221 1222 PINMUX_IPSR_MSEL(IP12_19_16, TX1_A, SEL_SCIF1_0), 1223 PINMUX_IPSR_MSEL(IP12_19_16, HTX1_A, SEL_HSCIF1_0), 1224 PINMUX_IPSR_MSEL(IP12_19_16, TS_SDEN0_C, SEL_TSIF0_2), 1225 PINMUX_IPSR_MSEL(IP12_19_16, STP_ISEN_0_C, SEL_SSP1_0_2), 1226 PINMUX_IPSR_MSEL(IP12_19_16, RIF1_D0_C, SEL_DRIF1_2), 1227 1228 PINMUX_IPSR_GPSR(IP12_23_20, CTS1_N), 1229 PINMUX_IPSR_MSEL(IP12_23_20, HCTS1_N_A, SEL_HSCIF1_0), 1230 PINMUX_IPSR_MSEL(IP12_23_20, MSIOF1_RXD_B, SEL_MSIOF1_1), 1231 PINMUX_IPSR_MSEL(IP12_23_20, TS_SDEN1_C, SEL_TSIF1_2), 1232 PINMUX_IPSR_MSEL(IP12_23_20, STP_ISEN_1_C, SEL_SSP1_1_2), 1233 PINMUX_IPSR_MSEL(IP12_23_20, RIF1_D0_B, SEL_DRIF1_1), 1234 PINMUX_IPSR_GPSR(IP12_23_20, ADIDATA), 1235 1236 PINMUX_IPSR_GPSR(IP12_27_24, RTS1_N), 1237 PINMUX_IPSR_MSEL(IP12_27_24, HRTS1_N_A, SEL_HSCIF1_0), 1238 PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1), 1239 PINMUX_IPSR_MSEL(IP12_27_24, TS_SDAT1_C, SEL_TSIF1_2), 1240 PINMUX_IPSR_MSEL(IP12_27_24, STP_ISD_1_C, SEL_SSP1_1_2), 1241 PINMUX_IPSR_MSEL(IP12_27_24, RIF1_D1_B, SEL_DRIF1_1), 1242 PINMUX_IPSR_GPSR(IP12_27_24, ADICHS0), 1243 1244 PINMUX_IPSR_GPSR(IP12_31_28, SCK2), 1245 PINMUX_IPSR_MSEL(IP12_31_28, SCIF_CLK_B, SEL_SCIF_1), 1246 PINMUX_IPSR_MSEL(IP12_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1), 1247 PINMUX_IPSR_MSEL(IP12_31_28, TS_SCK1_C, SEL_TSIF1_2), 1248 PINMUX_IPSR_MSEL(IP12_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2), 1249 PINMUX_IPSR_MSEL(IP12_31_28, RIF1_CLK_B, SEL_DRIF1_1), 1250 PINMUX_IPSR_GPSR(IP12_31_28, ADICLK), 1251 1252 /* IPSR13 */ 1253 PINMUX_IPSR_MSEL(IP13_3_0, TX2_A, SEL_SCIF2_0), 1254 PINMUX_IPSR_MSEL(IP13_3_0, SD2_CD_B, SEL_SDHI2_1), 1255 PINMUX_IPSR_MSEL(IP13_3_0, SCL1_A, SEL_I2C1_0), 1256 PINMUX_IPSR_MSEL(IP13_3_0, FMCLK_A, SEL_FM_0), 1257 PINMUX_IPSR_MSEL(IP13_3_0, RIF1_D1_C, SEL_DRIF1_2), 1258 PINMUX_IPSR_GPSR(IP13_3_0, FSO_CFE_0_N), 1259 1260 PINMUX_IPSR_MSEL(IP13_7_4, RX2_A, SEL_SCIF2_0), 1261 PINMUX_IPSR_MSEL(IP13_7_4, SD2_WP_B, SEL_SDHI2_1), 1262 PINMUX_IPSR_MSEL(IP13_7_4, SDA1_A, SEL_I2C1_0), 1263 PINMUX_IPSR_MSEL(IP13_7_4, FMIN_A, SEL_FM_0), 1264 PINMUX_IPSR_MSEL(IP13_7_4, RIF1_SYNC_C, SEL_DRIF1_2), 1265 PINMUX_IPSR_GPSR(IP13_7_4, FSO_CFE_1_N), 1266 1267 PINMUX_IPSR_GPSR(IP13_11_8, HSCK0), 1268 PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3), 1269 PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADGB_0), 1270 PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI1_1), 1271 PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3), 1272 PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3), 1273 PINMUX_IPSR_MSEL(IP13_11_8, RIF0_CLK_C, SEL_DRIF0_2), 1274 PINMUX_IPSR_MSEL(IP13_11_8, RX5_B, SEL_SCIF5_1), 1275 1276 PINMUX_IPSR_GPSR(IP13_15_12, HRX0), 1277 PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3), 1278 PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA2_B, SEL_SSI2_1), 1279 PINMUX_IPSR_MSEL(IP13_15_12, TS_SDEN0_D, SEL_TSIF0_3), 1280 PINMUX_IPSR_MSEL(IP13_15_12, STP_ISEN_0_D, SEL_SSP1_0_3), 1281 PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_C, SEL_DRIF0_2), 1282 1283 PINMUX_IPSR_GPSR(IP13_19_16, HTX0), 1284 PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3), 1285 PINMUX_IPSR_MSEL(IP13_19_16, SSI_SDATA9_B, SEL_SSI9_1), 1286 PINMUX_IPSR_MSEL(IP13_19_16, TS_SDAT0_D, SEL_TSIF0_3), 1287 PINMUX_IPSR_MSEL(IP13_19_16, STP_ISD_0_D, SEL_SSP1_0_3), 1288 PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_C, SEL_DRIF0_2), 1289 1290 PINMUX_IPSR_GPSR(IP13_23_20, HCTS0_N), 1291 PINMUX_IPSR_MSEL(IP13_23_20, RX2_B, SEL_SCIF2_1), 1292 PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3), 1293 PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK9_A, SEL_SSI9_0), 1294 PINMUX_IPSR_MSEL(IP13_23_20, TS_SPSYNC0_D, SEL_TSIF0_3), 1295 PINMUX_IPSR_MSEL(IP13_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3), 1296 PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_C, SEL_DRIF0_2), 1297 PINMUX_IPSR_GPSR(IP13_23_20, AUDIO_CLKOUT1_A), 1298 1299 PINMUX_IPSR_GPSR(IP13_27_24, HRTS0_N), 1300 PINMUX_IPSR_MSEL(IP13_27_24, TX2_B, SEL_SCIF2_1), 1301 PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3), 1302 PINMUX_IPSR_MSEL(IP13_27_24, SSI_WS9_A, SEL_SSI9_0), 1303 PINMUX_IPSR_MSEL(IP13_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3), 1304 PINMUX_IPSR_MSEL(IP13_27_24, BPFCLK_A, SEL_FM_0), 1305 PINMUX_IPSR_GPSR(IP13_27_24, AUDIO_CLKOUT2_A), 1306 1307 PINMUX_IPSR_GPSR(IP13_31_28, MSIOF0_SYNC), 1308 PINMUX_IPSR_GPSR(IP13_31_28, AUDIO_CLKOUT_A), 1309 PINMUX_IPSR_MSEL(IP13_31_28, TX5_B, SEL_SCIF5_1), 1310 PINMUX_IPSR_MSEL(IP13_31_28, BPFCLK_D, SEL_FM_3), 1311 1312 /* IPSR14 */ 1313 PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1), 1314 PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0), 1315 PINMUX_IPSR_GPSR(IP14_3_0, NFWP_N_A), 1316 PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADGA_2), 1317 PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0), 1318 PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2), 1319 PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A), 1320 PINMUX_IPSR_MSEL(IP14_3_0, TCLK1_B, SEL_TIMER_TMU1_1), 1321 1322 PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2), 1323 PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0), 1324 PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3), 1325 PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADGC_0), 1326 PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI2_0), 1327 PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3), 1328 PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D), 1329 PINMUX_IPSR_MSEL(IP14_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1), 1330 1331 PINMUX_IPSR_GPSR(IP14_11_8, MLB_CLK), 1332 PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SCK_F, SEL_MSIOF1_5), 1333 PINMUX_IPSR_MSEL(IP14_11_8, SCL1_B, SEL_I2C1_1), 1334 1335 PINMUX_IPSR_GPSR(IP14_15_12, MLB_SIG), 1336 PINMUX_IPSR_MSEL(IP14_15_12, RX1_B, SEL_SCIF1_1), 1337 PINMUX_IPSR_MSEL(IP14_15_12, MSIOF1_SYNC_F, SEL_MSIOF1_5), 1338 PINMUX_IPSR_MSEL(IP14_15_12, SDA1_B, SEL_I2C1_1), 1339 1340 PINMUX_IPSR_GPSR(IP14_19_16, MLB_DAT), 1341 PINMUX_IPSR_MSEL(IP14_19_16, TX1_B, SEL_SCIF1_1), 1342 PINMUX_IPSR_MSEL(IP14_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5), 1343 1344 PINMUX_IPSR_GPSR(IP14_23_20, SSI_SCK01239), 1345 PINMUX_IPSR_MSEL(IP14_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5), 1346 1347 PINMUX_IPSR_GPSR(IP14_27_24, SSI_WS01239), 1348 PINMUX_IPSR_MSEL(IP14_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5), 1349 1350 PINMUX_IPSR_GPSR(IP14_31_28, SSI_SDATA0), 1351 PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5), 1352 1353 /* IPSR15 */ 1354 PINMUX_IPSR_MSEL(IP15_3_0, SSI_SDATA1_A, SEL_SSI1_0), 1355 1356 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SDATA2_A, SEL_SSI2_0), 1357 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SCK1_B, SEL_SSI1_1), 1358 1359 PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK349), 1360 PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0), 1361 PINMUX_IPSR_MSEL(IP15_11_8, STP_OPWM_0_A, SEL_SSP1_0_0), 1362 1363 PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS349), 1364 PINMUX_IPSR_MSEL(IP15_15_12, HCTS2_N_A, SEL_HSCIF2_0), 1365 PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0), 1366 PINMUX_IPSR_MSEL(IP15_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0), 1367 1368 PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA3), 1369 PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0), 1370 PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_TXD_A, SEL_MSIOF1_0), 1371 PINMUX_IPSR_MSEL(IP15_19_16, TS_SCK0_A, SEL_TSIF0_0), 1372 PINMUX_IPSR_MSEL(IP15_19_16, STP_ISCLK_0_A, SEL_SSP1_0_0), 1373 PINMUX_IPSR_MSEL(IP15_19_16, RIF0_D1_A, SEL_DRIF0_0), 1374 PINMUX_IPSR_MSEL(IP15_19_16, RIF2_D0_A, SEL_DRIF2_0), 1375 1376 PINMUX_IPSR_GPSR(IP15_23_20, SSI_SCK4), 1377 PINMUX_IPSR_MSEL(IP15_23_20, HRX2_A, SEL_HSCIF2_0), 1378 PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_SCK_A, SEL_MSIOF1_0), 1379 PINMUX_IPSR_MSEL(IP15_23_20, TS_SDAT0_A, SEL_TSIF0_0), 1380 PINMUX_IPSR_MSEL(IP15_23_20, STP_ISD_0_A, SEL_SSP1_0_0), 1381 PINMUX_IPSR_MSEL(IP15_23_20, RIF0_CLK_A, SEL_DRIF0_0), 1382 PINMUX_IPSR_MSEL(IP15_23_20, RIF2_CLK_A, SEL_DRIF2_0), 1383 1384 PINMUX_IPSR_GPSR(IP15_27_24, SSI_WS4), 1385 PINMUX_IPSR_MSEL(IP15_27_24, HTX2_A, SEL_HSCIF2_0), 1386 PINMUX_IPSR_MSEL(IP15_27_24, MSIOF1_SYNC_A, SEL_MSIOF1_0), 1387 PINMUX_IPSR_MSEL(IP15_27_24, TS_SDEN0_A, SEL_TSIF0_0), 1388 PINMUX_IPSR_MSEL(IP15_27_24, STP_ISEN_0_A, SEL_SSP1_0_0), 1389 PINMUX_IPSR_MSEL(IP15_27_24, RIF0_SYNC_A, SEL_DRIF0_0), 1390 PINMUX_IPSR_MSEL(IP15_27_24, RIF2_SYNC_A, SEL_DRIF2_0), 1391 1392 PINMUX_IPSR_GPSR(IP15_31_28, SSI_SDATA4), 1393 PINMUX_IPSR_MSEL(IP15_31_28, HSCK2_A, SEL_HSCIF2_0), 1394 PINMUX_IPSR_MSEL(IP15_31_28, MSIOF1_RXD_A, SEL_MSIOF1_0), 1395 PINMUX_IPSR_MSEL(IP15_31_28, TS_SPSYNC0_A, SEL_TSIF0_0), 1396 PINMUX_IPSR_MSEL(IP15_31_28, STP_ISSYNC_0_A, SEL_SSP1_0_0), 1397 PINMUX_IPSR_MSEL(IP15_31_28, RIF0_D0_A, SEL_DRIF0_0), 1398 PINMUX_IPSR_MSEL(IP15_31_28, RIF2_D1_A, SEL_DRIF2_0), 1399 1400 /* IPSR16 */ 1401 PINMUX_IPSR_GPSR(IP16_3_0, SSI_SCK6), 1402 PINMUX_IPSR_GPSR(IP16_3_0, USB2_PWEN), 1403 PINMUX_IPSR_MSEL(IP16_3_0, SIM0_RST_D, SEL_SIMCARD_3), 1404 1405 PINMUX_IPSR_GPSR(IP16_7_4, SSI_WS6), 1406 PINMUX_IPSR_GPSR(IP16_7_4, USB2_OVC), 1407 PINMUX_IPSR_MSEL(IP16_7_4, SIM0_D_D, SEL_SIMCARD_3), 1408 1409 PINMUX_IPSR_GPSR(IP16_11_8, SSI_SDATA6), 1410 PINMUX_IPSR_MSEL(IP16_11_8, SIM0_CLK_D, SEL_SIMCARD_3), 1411 PINMUX_IPSR_GPSR(IP16_11_8, SATA_DEVSLP_A), 1412 1413 PINMUX_IPSR_GPSR(IP16_15_12, SSI_SCK78), 1414 PINMUX_IPSR_MSEL(IP16_15_12, HRX2_B, SEL_HSCIF2_1), 1415 PINMUX_IPSR_MSEL(IP16_15_12, MSIOF1_SCK_C, SEL_MSIOF1_2), 1416 PINMUX_IPSR_MSEL(IP16_15_12, TS_SCK1_A, SEL_TSIF1_0), 1417 PINMUX_IPSR_MSEL(IP16_15_12, STP_ISCLK_1_A, SEL_SSP1_1_0), 1418 PINMUX_IPSR_MSEL(IP16_15_12, RIF1_CLK_A, SEL_DRIF1_0), 1419 PINMUX_IPSR_MSEL(IP16_15_12, RIF3_CLK_A, SEL_DRIF3_0), 1420 1421 PINMUX_IPSR_GPSR(IP16_19_16, SSI_WS78), 1422 PINMUX_IPSR_MSEL(IP16_19_16, HTX2_B, SEL_HSCIF2_1), 1423 PINMUX_IPSR_MSEL(IP16_19_16, MSIOF1_SYNC_C, SEL_MSIOF1_2), 1424 PINMUX_IPSR_MSEL(IP16_19_16, TS_SDAT1_A, SEL_TSIF1_0), 1425 PINMUX_IPSR_MSEL(IP16_19_16, STP_ISD_1_A, SEL_SSP1_1_0), 1426 PINMUX_IPSR_MSEL(IP16_19_16, RIF1_SYNC_A, SEL_DRIF1_0), 1427 PINMUX_IPSR_MSEL(IP16_19_16, RIF3_SYNC_A, SEL_DRIF3_0), 1428 1429 PINMUX_IPSR_GPSR(IP16_23_20, SSI_SDATA7), 1430 PINMUX_IPSR_MSEL(IP16_23_20, HCTS2_N_B, SEL_HSCIF2_1), 1431 PINMUX_IPSR_MSEL(IP16_23_20, MSIOF1_RXD_C, SEL_MSIOF1_2), 1432 PINMUX_IPSR_MSEL(IP16_23_20, TS_SDEN1_A, SEL_TSIF1_0), 1433 PINMUX_IPSR_MSEL(IP16_23_20, STP_ISEN_1_A, SEL_SSP1_1_0), 1434 PINMUX_IPSR_MSEL(IP16_23_20, RIF1_D0_A, SEL_DRIF1_0), 1435 PINMUX_IPSR_MSEL(IP16_23_20, RIF3_D0_A, SEL_DRIF3_0), 1436 PINMUX_IPSR_MSEL(IP16_23_20, TCLK2_A, SEL_TIMER_TMU2_0), 1437 1438 PINMUX_IPSR_GPSR(IP16_27_24, SSI_SDATA8), 1439 PINMUX_IPSR_MSEL(IP16_27_24, HRTS2_N_B, SEL_HSCIF2_1), 1440 PINMUX_IPSR_MSEL(IP16_27_24, MSIOF1_TXD_C, SEL_MSIOF1_2), 1441 PINMUX_IPSR_MSEL(IP16_27_24, TS_SPSYNC1_A, SEL_TSIF1_0), 1442 PINMUX_IPSR_MSEL(IP16_27_24, STP_ISSYNC_1_A, SEL_SSP1_1_0), 1443 PINMUX_IPSR_MSEL(IP16_27_24, RIF1_D1_A, SEL_DRIF1_0), 1444 PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D1_A, SEL_DRIF3_0), 1445 1446 PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA9_A, SEL_SSI9_0), 1447 PINMUX_IPSR_MSEL(IP16_31_28, HSCK2_B, SEL_HSCIF2_1), 1448 PINMUX_IPSR_MSEL(IP16_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2), 1449 PINMUX_IPSR_MSEL(IP16_31_28, HSCK1_A, SEL_HSCIF1_0), 1450 PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI1_1), 1451 PINMUX_IPSR_GPSR(IP16_31_28, SCK1), 1452 PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0), 1453 PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0), 1454 1455 /* IPSR17 */ 1456 PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADGA_0), 1457 1458 PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADGB_1), 1459 PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0), 1460 PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3), 1461 PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0), 1462 PINMUX_IPSR_MSEL(IP17_7_4, TCLK1_A, SEL_TIMER_TMU1_0), 1463 1464 PINMUX_IPSR_GPSR(IP17_11_8, USB0_PWEN), 1465 PINMUX_IPSR_MSEL(IP17_11_8, SIM0_RST_C, SEL_SIMCARD_2), 1466 PINMUX_IPSR_MSEL(IP17_11_8, TS_SCK1_D, SEL_TSIF1_3), 1467 PINMUX_IPSR_MSEL(IP17_11_8, STP_ISCLK_1_D, SEL_SSP1_1_3), 1468 PINMUX_IPSR_MSEL(IP17_11_8, BPFCLK_B, SEL_FM_1), 1469 PINMUX_IPSR_MSEL(IP17_11_8, RIF3_CLK_B, SEL_DRIF3_1), 1470 PINMUX_IPSR_MSEL(IP17_11_8, HSCK2_C, SEL_HSCIF2_2), 1471 1472 PINMUX_IPSR_GPSR(IP17_15_12, USB0_OVC), 1473 PINMUX_IPSR_MSEL(IP17_15_12, SIM0_D_C, SEL_SIMCARD_2), 1474 PINMUX_IPSR_MSEL(IP17_15_12, TS_SDAT1_D, SEL_TSIF1_3), 1475 PINMUX_IPSR_MSEL(IP17_15_12, STP_ISD_1_D, SEL_SSP1_1_3), 1476 PINMUX_IPSR_MSEL(IP17_15_12, RIF3_SYNC_B, SEL_DRIF3_1), 1477 PINMUX_IPSR_MSEL(IP17_15_12, HRX2_C, SEL_HSCIF2_2), 1478 1479 PINMUX_IPSR_GPSR(IP17_19_16, USB1_PWEN), 1480 PINMUX_IPSR_MSEL(IP17_19_16, SIM0_CLK_C, SEL_SIMCARD_2), 1481 PINMUX_IPSR_MSEL(IP17_19_16, SSI_SCK1_A, SEL_SSI1_0), 1482 PINMUX_IPSR_MSEL(IP17_19_16, TS_SCK0_E, SEL_TSIF0_4), 1483 PINMUX_IPSR_MSEL(IP17_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4), 1484 PINMUX_IPSR_MSEL(IP17_19_16, FMCLK_B, SEL_FM_1), 1485 PINMUX_IPSR_MSEL(IP17_19_16, RIF2_CLK_B, SEL_DRIF2_1), 1486 PINMUX_IPSR_MSEL(IP17_19_16, SPEEDIN_A, SEL_SPEED_PULSE_0), 1487 PINMUX_IPSR_MSEL(IP17_19_16, HTX2_C, SEL_HSCIF2_2), 1488 1489 PINMUX_IPSR_GPSR(IP17_23_20, USB1_OVC), 1490 PINMUX_IPSR_MSEL(IP17_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2), 1491 PINMUX_IPSR_MSEL(IP17_23_20, SSI_WS1_A, SEL_SSI1_0), 1492 PINMUX_IPSR_MSEL(IP17_23_20, TS_SDAT0_E, SEL_TSIF0_4), 1493 PINMUX_IPSR_MSEL(IP17_23_20, STP_ISD_0_E, SEL_SSP1_0_4), 1494 PINMUX_IPSR_MSEL(IP17_23_20, FMIN_B, SEL_FM_1), 1495 PINMUX_IPSR_MSEL(IP17_23_20, RIF2_SYNC_B, SEL_DRIF2_1), 1496 PINMUX_IPSR_MSEL(IP17_23_20, REMOCON_B, SEL_REMOCON_1), 1497 PINMUX_IPSR_MSEL(IP17_23_20, HCTS2_N_C, SEL_HSCIF2_2), 1498 1499 PINMUX_IPSR_GPSR(IP17_27_24, USB30_PWEN), 1500 PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_B), 1501 PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI2_1), 1502 PINMUX_IPSR_MSEL(IP17_27_24, TS_SDEN1_D, SEL_TSIF1_3), 1503 PINMUX_IPSR_MSEL(IP17_27_24, STP_ISEN_1_D, SEL_SSP1_1_3), 1504 PINMUX_IPSR_MSEL(IP17_27_24, STP_OPWM_0_E, SEL_SSP1_0_4), 1505 PINMUX_IPSR_MSEL(IP17_27_24, RIF3_D0_B, SEL_DRIF3_1), 1506 PINMUX_IPSR_MSEL(IP17_27_24, TCLK2_B, SEL_TIMER_TMU2_1), 1507 PINMUX_IPSR_GPSR(IP17_27_24, TPU0TO0), 1508 PINMUX_IPSR_MSEL(IP17_27_24, BPFCLK_C, SEL_FM_2), 1509 PINMUX_IPSR_MSEL(IP17_27_24, HRTS2_N_C, SEL_HSCIF2_2), 1510 1511 PINMUX_IPSR_GPSR(IP17_31_28, USB30_OVC), 1512 PINMUX_IPSR_GPSR(IP17_31_28, AUDIO_CLKOUT1_B), 1513 PINMUX_IPSR_MSEL(IP17_31_28, SSI_WS2_B, SEL_SSI2_1), 1514 PINMUX_IPSR_MSEL(IP17_31_28, TS_SPSYNC1_D, SEL_TSIF1_3), 1515 PINMUX_IPSR_MSEL(IP17_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3), 1516 PINMUX_IPSR_MSEL(IP17_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4), 1517 PINMUX_IPSR_MSEL(IP17_31_28, RIF3_D1_B, SEL_DRIF3_1), 1518 PINMUX_IPSR_GPSR(IP17_31_28, FSO_TOE_N), 1519 PINMUX_IPSR_GPSR(IP17_31_28, TPU0TO1), 1520 1521 /* IPSR18 */ 1522 PINMUX_IPSR_GPSR(IP18_3_0, USB2_CH3_PWEN), 1523 PINMUX_IPSR_GPSR(IP18_3_0, AUDIO_CLKOUT2_B), 1524 PINMUX_IPSR_MSEL(IP18_3_0, SSI_SCK9_B, SEL_SSI9_1), 1525 PINMUX_IPSR_MSEL(IP18_3_0, TS_SDEN0_E, SEL_TSIF0_4), 1526 PINMUX_IPSR_MSEL(IP18_3_0, STP_ISEN_0_E, SEL_SSP1_0_4), 1527 PINMUX_IPSR_MSEL(IP18_3_0, RIF2_D0_B, SEL_DRIF2_1), 1528 PINMUX_IPSR_GPSR(IP18_3_0, TPU0TO2), 1529 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_C, SEL_FM_2), 1530 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_D, SEL_FM_3), 1531 1532 PINMUX_IPSR_GPSR(IP18_7_4, USB2_CH3_OVC), 1533 PINMUX_IPSR_GPSR(IP18_7_4, AUDIO_CLKOUT3_B), 1534 PINMUX_IPSR_MSEL(IP18_7_4, SSI_WS9_B, SEL_SSI9_1), 1535 PINMUX_IPSR_MSEL(IP18_7_4, TS_SPSYNC0_E, SEL_TSIF0_4), 1536 PINMUX_IPSR_MSEL(IP18_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4), 1537 PINMUX_IPSR_MSEL(IP18_7_4, RIF2_D1_B, SEL_DRIF2_1), 1538 PINMUX_IPSR_GPSR(IP18_7_4, TPU0TO3), 1539 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_C, SEL_FM_2), 1540 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_D, SEL_FM_3), 1541 1542 /* 1543 * Static pins can not be muxed between different functions but 1544 * still need mark entries in the pinmux list. Add each static 1545 * pin to the list without an associated function. The sh-pfc 1546 * core will do the right thing and skip trying to mux the pin 1547 * while still applying configuration to it. 1548 */ 1549 #define FM(x) PINMUX_DATA(x##_MARK, 0), 1550 PINMUX_STATIC 1551 #undef FM 1552 }; 1553 1554 /* 1555 * Pins not associated with a GPIO port. 1556 */ 1557 enum { 1558 GP_ASSIGN_LAST(), 1559 NOGP_ALL(), 1560 }; 1561 1562 static const struct sh_pfc_pin pinmux_pins[] = { 1563 PINMUX_GPIO_GP_ALL(), 1564 PINMUX_NOGP_ALL(), 1565 }; 1566 1567 /* - AUDIO CLOCK ------------------------------------------------------------ */ 1568 static const unsigned int audio_clk_a_a_pins[] = { 1569 /* CLK A */ 1570 RCAR_GP_PIN(6, 22), 1571 }; 1572 static const unsigned int audio_clk_a_a_mux[] = { 1573 AUDIO_CLKA_A_MARK, 1574 }; 1575 static const unsigned int audio_clk_a_b_pins[] = { 1576 /* CLK A */ 1577 RCAR_GP_PIN(5, 4), 1578 }; 1579 static const unsigned int audio_clk_a_b_mux[] = { 1580 AUDIO_CLKA_B_MARK, 1581 }; 1582 static const unsigned int audio_clk_a_c_pins[] = { 1583 /* CLK A */ 1584 RCAR_GP_PIN(5, 19), 1585 }; 1586 static const unsigned int audio_clk_a_c_mux[] = { 1587 AUDIO_CLKA_C_MARK, 1588 }; 1589 static const unsigned int audio_clk_b_a_pins[] = { 1590 /* CLK B */ 1591 RCAR_GP_PIN(5, 12), 1592 }; 1593 static const unsigned int audio_clk_b_a_mux[] = { 1594 AUDIO_CLKB_A_MARK, 1595 }; 1596 static const unsigned int audio_clk_b_b_pins[] = { 1597 /* CLK B */ 1598 RCAR_GP_PIN(6, 23), 1599 }; 1600 static const unsigned int audio_clk_b_b_mux[] = { 1601 AUDIO_CLKB_B_MARK, 1602 }; 1603 static const unsigned int audio_clk_c_a_pins[] = { 1604 /* CLK C */ 1605 RCAR_GP_PIN(5, 21), 1606 }; 1607 static const unsigned int audio_clk_c_a_mux[] = { 1608 AUDIO_CLKC_A_MARK, 1609 }; 1610 static const unsigned int audio_clk_c_b_pins[] = { 1611 /* CLK C */ 1612 RCAR_GP_PIN(5, 0), 1613 }; 1614 static const unsigned int audio_clk_c_b_mux[] = { 1615 AUDIO_CLKC_B_MARK, 1616 }; 1617 static const unsigned int audio_clkout_a_pins[] = { 1618 /* CLKOUT */ 1619 RCAR_GP_PIN(5, 18), 1620 }; 1621 static const unsigned int audio_clkout_a_mux[] = { 1622 AUDIO_CLKOUT_A_MARK, 1623 }; 1624 static const unsigned int audio_clkout_b_pins[] = { 1625 /* CLKOUT */ 1626 RCAR_GP_PIN(6, 28), 1627 }; 1628 static const unsigned int audio_clkout_b_mux[] = { 1629 AUDIO_CLKOUT_B_MARK, 1630 }; 1631 static const unsigned int audio_clkout_c_pins[] = { 1632 /* CLKOUT */ 1633 RCAR_GP_PIN(5, 3), 1634 }; 1635 static const unsigned int audio_clkout_c_mux[] = { 1636 AUDIO_CLKOUT_C_MARK, 1637 }; 1638 static const unsigned int audio_clkout_d_pins[] = { 1639 /* CLKOUT */ 1640 RCAR_GP_PIN(5, 21), 1641 }; 1642 static const unsigned int audio_clkout_d_mux[] = { 1643 AUDIO_CLKOUT_D_MARK, 1644 }; 1645 static const unsigned int audio_clkout1_a_pins[] = { 1646 /* CLKOUT1 */ 1647 RCAR_GP_PIN(5, 15), 1648 }; 1649 static const unsigned int audio_clkout1_a_mux[] = { 1650 AUDIO_CLKOUT1_A_MARK, 1651 }; 1652 static const unsigned int audio_clkout1_b_pins[] = { 1653 /* CLKOUT1 */ 1654 RCAR_GP_PIN(6, 29), 1655 }; 1656 static const unsigned int audio_clkout1_b_mux[] = { 1657 AUDIO_CLKOUT1_B_MARK, 1658 }; 1659 static const unsigned int audio_clkout2_a_pins[] = { 1660 /* CLKOUT2 */ 1661 RCAR_GP_PIN(5, 16), 1662 }; 1663 static const unsigned int audio_clkout2_a_mux[] = { 1664 AUDIO_CLKOUT2_A_MARK, 1665 }; 1666 static const unsigned int audio_clkout2_b_pins[] = { 1667 /* CLKOUT2 */ 1668 RCAR_GP_PIN(6, 30), 1669 }; 1670 static const unsigned int audio_clkout2_b_mux[] = { 1671 AUDIO_CLKOUT2_B_MARK, 1672 }; 1673 static const unsigned int audio_clkout3_a_pins[] = { 1674 /* CLKOUT3 */ 1675 RCAR_GP_PIN(5, 19), 1676 }; 1677 static const unsigned int audio_clkout3_a_mux[] = { 1678 AUDIO_CLKOUT3_A_MARK, 1679 }; 1680 static const unsigned int audio_clkout3_b_pins[] = { 1681 /* CLKOUT3 */ 1682 RCAR_GP_PIN(6, 31), 1683 }; 1684 static const unsigned int audio_clkout3_b_mux[] = { 1685 AUDIO_CLKOUT3_B_MARK, 1686 }; 1687 1688 /* - EtherAVB --------------------------------------------------------------- */ 1689 static const unsigned int avb_link_pins[] = { 1690 /* AVB_LINK */ 1691 RCAR_GP_PIN(2, 12), 1692 }; 1693 static const unsigned int avb_link_mux[] = { 1694 AVB_LINK_MARK, 1695 }; 1696 static const unsigned int avb_magic_pins[] = { 1697 /* AVB_MAGIC_ */ 1698 RCAR_GP_PIN(2, 10), 1699 }; 1700 static const unsigned int avb_magic_mux[] = { 1701 AVB_MAGIC_MARK, 1702 }; 1703 static const unsigned int avb_phy_int_pins[] = { 1704 /* AVB_PHY_INT */ 1705 RCAR_GP_PIN(2, 11), 1706 }; 1707 static const unsigned int avb_phy_int_mux[] = { 1708 AVB_PHY_INT_MARK, 1709 }; 1710 static const unsigned int avb_mdio_pins[] = { 1711 /* AVB_MDC, AVB_MDIO */ 1712 RCAR_GP_PIN(2, 9), PIN_AVB_MDIO, 1713 }; 1714 static const unsigned int avb_mdio_mux[] = { 1715 AVB_MDC_MARK, AVB_MDIO_MARK, 1716 }; 1717 static const unsigned int avb_mii_pins[] = { 1718 /* 1719 * AVB_TX_CTL, AVB_TXC, AVB_TD0, 1720 * AVB_TD1, AVB_TD2, AVB_TD3, 1721 * AVB_RX_CTL, AVB_RXC, AVB_RD0, 1722 * AVB_RD1, AVB_RD2, AVB_RD3, 1723 * AVB_TXCREFCLK 1724 */ 1725 PIN_AVB_TX_CTL, PIN_AVB_TXC, PIN_AVB_TD0, 1726 PIN_AVB_TD1, PIN_AVB_TD2, PIN_AVB_TD3, 1727 PIN_AVB_RX_CTL, PIN_AVB_RXC, PIN_AVB_RD0, 1728 PIN_AVB_RD1, PIN_AVB_RD2, PIN_AVB_RD3, 1729 PIN_AVB_TXCREFCLK, 1730 1731 }; 1732 static const unsigned int avb_mii_mux[] = { 1733 AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK, 1734 AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK, 1735 AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK, 1736 AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK, 1737 AVB_TXCREFCLK_MARK, 1738 }; 1739 static const unsigned int avb_avtp_pps_pins[] = { 1740 /* AVB_AVTP_PPS */ 1741 RCAR_GP_PIN(2, 6), 1742 }; 1743 static const unsigned int avb_avtp_pps_mux[] = { 1744 AVB_AVTP_PPS_MARK, 1745 }; 1746 static const unsigned int avb_avtp_match_a_pins[] = { 1747 /* AVB_AVTP_MATCH_A */ 1748 RCAR_GP_PIN(2, 13), 1749 }; 1750 static const unsigned int avb_avtp_match_a_mux[] = { 1751 AVB_AVTP_MATCH_A_MARK, 1752 }; 1753 static const unsigned int avb_avtp_capture_a_pins[] = { 1754 /* AVB_AVTP_CAPTURE_A */ 1755 RCAR_GP_PIN(2, 14), 1756 }; 1757 static const unsigned int avb_avtp_capture_a_mux[] = { 1758 AVB_AVTP_CAPTURE_A_MARK, 1759 }; 1760 static const unsigned int avb_avtp_match_b_pins[] = { 1761 /* AVB_AVTP_MATCH_B */ 1762 RCAR_GP_PIN(1, 8), 1763 }; 1764 static const unsigned int avb_avtp_match_b_mux[] = { 1765 AVB_AVTP_MATCH_B_MARK, 1766 }; 1767 static const unsigned int avb_avtp_capture_b_pins[] = { 1768 /* AVB_AVTP_CAPTURE_B */ 1769 RCAR_GP_PIN(1, 11), 1770 }; 1771 static const unsigned int avb_avtp_capture_b_mux[] = { 1772 AVB_AVTP_CAPTURE_B_MARK, 1773 }; 1774 1775 /* - CAN ------------------------------------------------------------------ */ 1776 static const unsigned int can0_data_a_pins[] = { 1777 /* TX, RX */ 1778 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24), 1779 }; 1780 static const unsigned int can0_data_a_mux[] = { 1781 CAN0_TX_A_MARK, CAN0_RX_A_MARK, 1782 }; 1783 static const unsigned int can0_data_b_pins[] = { 1784 /* TX, RX */ 1785 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), 1786 }; 1787 static const unsigned int can0_data_b_mux[] = { 1788 CAN0_TX_B_MARK, CAN0_RX_B_MARK, 1789 }; 1790 static const unsigned int can1_data_pins[] = { 1791 /* TX, RX */ 1792 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26), 1793 }; 1794 static const unsigned int can1_data_mux[] = { 1795 CAN1_TX_MARK, CAN1_RX_MARK, 1796 }; 1797 1798 /* - CAN Clock -------------------------------------------------------------- */ 1799 static const unsigned int can_clk_pins[] = { 1800 /* CLK */ 1801 RCAR_GP_PIN(1, 25), 1802 }; 1803 static const unsigned int can_clk_mux[] = { 1804 CAN_CLK_MARK, 1805 }; 1806 1807 /* - CAN FD --------------------------------------------------------------- */ 1808 static const unsigned int canfd0_data_a_pins[] = { 1809 /* TX, RX */ 1810 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24), 1811 }; 1812 static const unsigned int canfd0_data_a_mux[] = { 1813 CANFD0_TX_A_MARK, CANFD0_RX_A_MARK, 1814 }; 1815 static const unsigned int canfd0_data_b_pins[] = { 1816 /* TX, RX */ 1817 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), 1818 }; 1819 static const unsigned int canfd0_data_b_mux[] = { 1820 CANFD0_TX_B_MARK, CANFD0_RX_B_MARK, 1821 }; 1822 static const unsigned int canfd1_data_pins[] = { 1823 /* TX, RX */ 1824 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26), 1825 }; 1826 static const unsigned int canfd1_data_mux[] = { 1827 CANFD1_TX_MARK, CANFD1_RX_MARK, 1828 }; 1829 1830 /* - DRIF0 --------------------------------------------------------------- */ 1831 static const unsigned int drif0_ctrl_a_pins[] = { 1832 /* CLK, SYNC */ 1833 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), 1834 }; 1835 static const unsigned int drif0_ctrl_a_mux[] = { 1836 RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK, 1837 }; 1838 static const unsigned int drif0_data0_a_pins[] = { 1839 /* D0 */ 1840 RCAR_GP_PIN(6, 10), 1841 }; 1842 static const unsigned int drif0_data0_a_mux[] = { 1843 RIF0_D0_A_MARK, 1844 }; 1845 static const unsigned int drif0_data1_a_pins[] = { 1846 /* D1 */ 1847 RCAR_GP_PIN(6, 7), 1848 }; 1849 static const unsigned int drif0_data1_a_mux[] = { 1850 RIF0_D1_A_MARK, 1851 }; 1852 static const unsigned int drif0_ctrl_b_pins[] = { 1853 /* CLK, SYNC */ 1854 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4), 1855 }; 1856 static const unsigned int drif0_ctrl_b_mux[] = { 1857 RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK, 1858 }; 1859 static const unsigned int drif0_data0_b_pins[] = { 1860 /* D0 */ 1861 RCAR_GP_PIN(5, 1), 1862 }; 1863 static const unsigned int drif0_data0_b_mux[] = { 1864 RIF0_D0_B_MARK, 1865 }; 1866 static const unsigned int drif0_data1_b_pins[] = { 1867 /* D1 */ 1868 RCAR_GP_PIN(5, 2), 1869 }; 1870 static const unsigned int drif0_data1_b_mux[] = { 1871 RIF0_D1_B_MARK, 1872 }; 1873 static const unsigned int drif0_ctrl_c_pins[] = { 1874 /* CLK, SYNC */ 1875 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15), 1876 }; 1877 static const unsigned int drif0_ctrl_c_mux[] = { 1878 RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK, 1879 }; 1880 static const unsigned int drif0_data0_c_pins[] = { 1881 /* D0 */ 1882 RCAR_GP_PIN(5, 13), 1883 }; 1884 static const unsigned int drif0_data0_c_mux[] = { 1885 RIF0_D0_C_MARK, 1886 }; 1887 static const unsigned int drif0_data1_c_pins[] = { 1888 /* D1 */ 1889 RCAR_GP_PIN(5, 14), 1890 }; 1891 static const unsigned int drif0_data1_c_mux[] = { 1892 RIF0_D1_C_MARK, 1893 }; 1894 /* - DRIF1 --------------------------------------------------------------- */ 1895 static const unsigned int drif1_ctrl_a_pins[] = { 1896 /* CLK, SYNC */ 1897 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18), 1898 }; 1899 static const unsigned int drif1_ctrl_a_mux[] = { 1900 RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK, 1901 }; 1902 static const unsigned int drif1_data0_a_pins[] = { 1903 /* D0 */ 1904 RCAR_GP_PIN(6, 19), 1905 }; 1906 static const unsigned int drif1_data0_a_mux[] = { 1907 RIF1_D0_A_MARK, 1908 }; 1909 static const unsigned int drif1_data1_a_pins[] = { 1910 /* D1 */ 1911 RCAR_GP_PIN(6, 20), 1912 }; 1913 static const unsigned int drif1_data1_a_mux[] = { 1914 RIF1_D1_A_MARK, 1915 }; 1916 static const unsigned int drif1_ctrl_b_pins[] = { 1917 /* CLK, SYNC */ 1918 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3), 1919 }; 1920 static const unsigned int drif1_ctrl_b_mux[] = { 1921 RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK, 1922 }; 1923 static const unsigned int drif1_data0_b_pins[] = { 1924 /* D0 */ 1925 RCAR_GP_PIN(5, 7), 1926 }; 1927 static const unsigned int drif1_data0_b_mux[] = { 1928 RIF1_D0_B_MARK, 1929 }; 1930 static const unsigned int drif1_data1_b_pins[] = { 1931 /* D1 */ 1932 RCAR_GP_PIN(5, 8), 1933 }; 1934 static const unsigned int drif1_data1_b_mux[] = { 1935 RIF1_D1_B_MARK, 1936 }; 1937 static const unsigned int drif1_ctrl_c_pins[] = { 1938 /* CLK, SYNC */ 1939 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11), 1940 }; 1941 static const unsigned int drif1_ctrl_c_mux[] = { 1942 RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK, 1943 }; 1944 static const unsigned int drif1_data0_c_pins[] = { 1945 /* D0 */ 1946 RCAR_GP_PIN(5, 6), 1947 }; 1948 static const unsigned int drif1_data0_c_mux[] = { 1949 RIF1_D0_C_MARK, 1950 }; 1951 static const unsigned int drif1_data1_c_pins[] = { 1952 /* D1 */ 1953 RCAR_GP_PIN(5, 10), 1954 }; 1955 static const unsigned int drif1_data1_c_mux[] = { 1956 RIF1_D1_C_MARK, 1957 }; 1958 /* - DRIF2 --------------------------------------------------------------- */ 1959 static const unsigned int drif2_ctrl_a_pins[] = { 1960 /* CLK, SYNC */ 1961 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), 1962 }; 1963 static const unsigned int drif2_ctrl_a_mux[] = { 1964 RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK, 1965 }; 1966 static const unsigned int drif2_data0_a_pins[] = { 1967 /* D0 */ 1968 RCAR_GP_PIN(6, 7), 1969 }; 1970 static const unsigned int drif2_data0_a_mux[] = { 1971 RIF2_D0_A_MARK, 1972 }; 1973 static const unsigned int drif2_data1_a_pins[] = { 1974 /* D1 */ 1975 RCAR_GP_PIN(6, 10), 1976 }; 1977 static const unsigned int drif2_data1_a_mux[] = { 1978 RIF2_D1_A_MARK, 1979 }; 1980 static const unsigned int drif2_ctrl_b_pins[] = { 1981 /* CLK, SYNC */ 1982 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27), 1983 }; 1984 static const unsigned int drif2_ctrl_b_mux[] = { 1985 RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK, 1986 }; 1987 static const unsigned int drif2_data0_b_pins[] = { 1988 /* D0 */ 1989 RCAR_GP_PIN(6, 30), 1990 }; 1991 static const unsigned int drif2_data0_b_mux[] = { 1992 RIF2_D0_B_MARK, 1993 }; 1994 static const unsigned int drif2_data1_b_pins[] = { 1995 /* D1 */ 1996 RCAR_GP_PIN(6, 31), 1997 }; 1998 static const unsigned int drif2_data1_b_mux[] = { 1999 RIF2_D1_B_MARK, 2000 }; 2001 /* - DRIF3 --------------------------------------------------------------- */ 2002 static const unsigned int drif3_ctrl_a_pins[] = { 2003 /* CLK, SYNC */ 2004 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18), 2005 }; 2006 static const unsigned int drif3_ctrl_a_mux[] = { 2007 RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK, 2008 }; 2009 static const unsigned int drif3_data0_a_pins[] = { 2010 /* D0 */ 2011 RCAR_GP_PIN(6, 19), 2012 }; 2013 static const unsigned int drif3_data0_a_mux[] = { 2014 RIF3_D0_A_MARK, 2015 }; 2016 static const unsigned int drif3_data1_a_pins[] = { 2017 /* D1 */ 2018 RCAR_GP_PIN(6, 20), 2019 }; 2020 static const unsigned int drif3_data1_a_mux[] = { 2021 RIF3_D1_A_MARK, 2022 }; 2023 static const unsigned int drif3_ctrl_b_pins[] = { 2024 /* CLK, SYNC */ 2025 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25), 2026 }; 2027 static const unsigned int drif3_ctrl_b_mux[] = { 2028 RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK, 2029 }; 2030 static const unsigned int drif3_data0_b_pins[] = { 2031 /* D0 */ 2032 RCAR_GP_PIN(6, 28), 2033 }; 2034 static const unsigned int drif3_data0_b_mux[] = { 2035 RIF3_D0_B_MARK, 2036 }; 2037 static const unsigned int drif3_data1_b_pins[] = { 2038 /* D1 */ 2039 RCAR_GP_PIN(6, 29), 2040 }; 2041 static const unsigned int drif3_data1_b_mux[] = { 2042 RIF3_D1_B_MARK, 2043 }; 2044 2045 /* - DU --------------------------------------------------------------------- */ 2046 static const unsigned int du_rgb666_pins[] = { 2047 /* R[7:2], G[7:2], B[7:2] */ 2048 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), 2049 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), 2050 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), 2051 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18), 2052 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5), 2053 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2), 2054 }; 2055 static const unsigned int du_rgb666_mux[] = { 2056 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK, 2057 DU_DR3_MARK, DU_DR2_MARK, 2058 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK, 2059 DU_DG3_MARK, DU_DG2_MARK, 2060 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK, 2061 DU_DB3_MARK, DU_DB2_MARK, 2062 }; 2063 static const unsigned int du_rgb888_pins[] = { 2064 /* R[7:0], G[7:0], B[7:0] */ 2065 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), 2066 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), 2067 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8), 2068 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), 2069 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18), 2070 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16), 2071 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5), 2072 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2), 2073 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0), 2074 }; 2075 static const unsigned int du_rgb888_mux[] = { 2076 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK, 2077 DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK, 2078 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK, 2079 DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK, 2080 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK, 2081 DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK, 2082 }; 2083 static const unsigned int du_clk_out_0_pins[] = { 2084 /* CLKOUT */ 2085 RCAR_GP_PIN(1, 27), 2086 }; 2087 static const unsigned int du_clk_out_0_mux[] = { 2088 DU_DOTCLKOUT0_MARK 2089 }; 2090 static const unsigned int du_clk_out_1_pins[] = { 2091 /* CLKOUT */ 2092 RCAR_GP_PIN(2, 3), 2093 }; 2094 static const unsigned int du_clk_out_1_mux[] = { 2095 DU_DOTCLKOUT1_MARK 2096 }; 2097 static const unsigned int du_sync_pins[] = { 2098 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */ 2099 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4), 2100 }; 2101 static const unsigned int du_sync_mux[] = { 2102 DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK 2103 }; 2104 static const unsigned int du_oddf_pins[] = { 2105 /* EXDISP/EXODDF/EXCDE */ 2106 RCAR_GP_PIN(2, 2), 2107 }; 2108 static const unsigned int du_oddf_mux[] = { 2109 DU_EXODDF_DU_ODDF_DISP_CDE_MARK, 2110 }; 2111 static const unsigned int du_cde_pins[] = { 2112 /* CDE */ 2113 RCAR_GP_PIN(2, 0), 2114 }; 2115 static const unsigned int du_cde_mux[] = { 2116 DU_CDE_MARK, 2117 }; 2118 static const unsigned int du_disp_pins[] = { 2119 /* DISP */ 2120 RCAR_GP_PIN(2, 1), 2121 }; 2122 static const unsigned int du_disp_mux[] = { 2123 DU_DISP_MARK, 2124 }; 2125 2126 /* - HSCIF0 ----------------------------------------------------------------- */ 2127 static const unsigned int hscif0_data_pins[] = { 2128 /* RX, TX */ 2129 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14), 2130 }; 2131 static const unsigned int hscif0_data_mux[] = { 2132 HRX0_MARK, HTX0_MARK, 2133 }; 2134 static const unsigned int hscif0_clk_pins[] = { 2135 /* SCK */ 2136 RCAR_GP_PIN(5, 12), 2137 }; 2138 static const unsigned int hscif0_clk_mux[] = { 2139 HSCK0_MARK, 2140 }; 2141 static const unsigned int hscif0_ctrl_pins[] = { 2142 /* RTS, CTS */ 2143 RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15), 2144 }; 2145 static const unsigned int hscif0_ctrl_mux[] = { 2146 HRTS0_N_MARK, HCTS0_N_MARK, 2147 }; 2148 /* - HSCIF1 ----------------------------------------------------------------- */ 2149 static const unsigned int hscif1_data_a_pins[] = { 2150 /* RX, TX */ 2151 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6), 2152 }; 2153 static const unsigned int hscif1_data_a_mux[] = { 2154 HRX1_A_MARK, HTX1_A_MARK, 2155 }; 2156 static const unsigned int hscif1_clk_a_pins[] = { 2157 /* SCK */ 2158 RCAR_GP_PIN(6, 21), 2159 }; 2160 static const unsigned int hscif1_clk_a_mux[] = { 2161 HSCK1_A_MARK, 2162 }; 2163 static const unsigned int hscif1_ctrl_a_pins[] = { 2164 /* RTS, CTS */ 2165 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7), 2166 }; 2167 static const unsigned int hscif1_ctrl_a_mux[] = { 2168 HRTS1_N_A_MARK, HCTS1_N_A_MARK, 2169 }; 2170 2171 static const unsigned int hscif1_data_b_pins[] = { 2172 /* RX, TX */ 2173 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), 2174 }; 2175 static const unsigned int hscif1_data_b_mux[] = { 2176 HRX1_B_MARK, HTX1_B_MARK, 2177 }; 2178 static const unsigned int hscif1_clk_b_pins[] = { 2179 /* SCK */ 2180 RCAR_GP_PIN(5, 0), 2181 }; 2182 static const unsigned int hscif1_clk_b_mux[] = { 2183 HSCK1_B_MARK, 2184 }; 2185 static const unsigned int hscif1_ctrl_b_pins[] = { 2186 /* RTS, CTS */ 2187 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3), 2188 }; 2189 static const unsigned int hscif1_ctrl_b_mux[] = { 2190 HRTS1_N_B_MARK, HCTS1_N_B_MARK, 2191 }; 2192 /* - HSCIF2 ----------------------------------------------------------------- */ 2193 static const unsigned int hscif2_data_a_pins[] = { 2194 /* RX, TX */ 2195 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), 2196 }; 2197 static const unsigned int hscif2_data_a_mux[] = { 2198 HRX2_A_MARK, HTX2_A_MARK, 2199 }; 2200 static const unsigned int hscif2_clk_a_pins[] = { 2201 /* SCK */ 2202 RCAR_GP_PIN(6, 10), 2203 }; 2204 static const unsigned int hscif2_clk_a_mux[] = { 2205 HSCK2_A_MARK, 2206 }; 2207 static const unsigned int hscif2_ctrl_a_pins[] = { 2208 /* RTS, CTS */ 2209 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6), 2210 }; 2211 static const unsigned int hscif2_ctrl_a_mux[] = { 2212 HRTS2_N_A_MARK, HCTS2_N_A_MARK, 2213 }; 2214 2215 static const unsigned int hscif2_data_b_pins[] = { 2216 /* RX, TX */ 2217 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18), 2218 }; 2219 static const unsigned int hscif2_data_b_mux[] = { 2220 HRX2_B_MARK, HTX2_B_MARK, 2221 }; 2222 static const unsigned int hscif2_clk_b_pins[] = { 2223 /* SCK */ 2224 RCAR_GP_PIN(6, 21), 2225 }; 2226 static const unsigned int hscif2_clk_b_mux[] = { 2227 HSCK2_B_MARK, 2228 }; 2229 static const unsigned int hscif2_ctrl_b_pins[] = { 2230 /* RTS, CTS */ 2231 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19), 2232 }; 2233 static const unsigned int hscif2_ctrl_b_mux[] = { 2234 HRTS2_N_B_MARK, HCTS2_N_B_MARK, 2235 }; 2236 2237 static const unsigned int hscif2_data_c_pins[] = { 2238 /* RX, TX */ 2239 RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26), 2240 }; 2241 static const unsigned int hscif2_data_c_mux[] = { 2242 HRX2_C_MARK, HTX2_C_MARK, 2243 }; 2244 static const unsigned int hscif2_clk_c_pins[] = { 2245 /* SCK */ 2246 RCAR_GP_PIN(6, 24), 2247 }; 2248 static const unsigned int hscif2_clk_c_mux[] = { 2249 HSCK2_C_MARK, 2250 }; 2251 static const unsigned int hscif2_ctrl_c_pins[] = { 2252 /* RTS, CTS */ 2253 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 27), 2254 }; 2255 static const unsigned int hscif2_ctrl_c_mux[] = { 2256 HRTS2_N_C_MARK, HCTS2_N_C_MARK, 2257 }; 2258 /* - HSCIF3 ----------------------------------------------------------------- */ 2259 static const unsigned int hscif3_data_a_pins[] = { 2260 /* RX, TX */ 2261 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24), 2262 }; 2263 static const unsigned int hscif3_data_a_mux[] = { 2264 HRX3_A_MARK, HTX3_A_MARK, 2265 }; 2266 static const unsigned int hscif3_clk_pins[] = { 2267 /* SCK */ 2268 RCAR_GP_PIN(1, 22), 2269 }; 2270 static const unsigned int hscif3_clk_mux[] = { 2271 HSCK3_MARK, 2272 }; 2273 static const unsigned int hscif3_ctrl_pins[] = { 2274 /* RTS, CTS */ 2275 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25), 2276 }; 2277 static const unsigned int hscif3_ctrl_mux[] = { 2278 HRTS3_N_MARK, HCTS3_N_MARK, 2279 }; 2280 2281 static const unsigned int hscif3_data_b_pins[] = { 2282 /* RX, TX */ 2283 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), 2284 }; 2285 static const unsigned int hscif3_data_b_mux[] = { 2286 HRX3_B_MARK, HTX3_B_MARK, 2287 }; 2288 static const unsigned int hscif3_data_c_pins[] = { 2289 /* RX, TX */ 2290 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), 2291 }; 2292 static const unsigned int hscif3_data_c_mux[] = { 2293 HRX3_C_MARK, HTX3_C_MARK, 2294 }; 2295 static const unsigned int hscif3_data_d_pins[] = { 2296 /* RX, TX */ 2297 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), 2298 }; 2299 static const unsigned int hscif3_data_d_mux[] = { 2300 HRX3_D_MARK, HTX3_D_MARK, 2301 }; 2302 /* - HSCIF4 ----------------------------------------------------------------- */ 2303 static const unsigned int hscif4_data_a_pins[] = { 2304 /* RX, TX */ 2305 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), 2306 }; 2307 static const unsigned int hscif4_data_a_mux[] = { 2308 HRX4_A_MARK, HTX4_A_MARK, 2309 }; 2310 static const unsigned int hscif4_clk_pins[] = { 2311 /* SCK */ 2312 RCAR_GP_PIN(1, 11), 2313 }; 2314 static const unsigned int hscif4_clk_mux[] = { 2315 HSCK4_MARK, 2316 }; 2317 static const unsigned int hscif4_ctrl_pins[] = { 2318 /* RTS, CTS */ 2319 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), 2320 }; 2321 static const unsigned int hscif4_ctrl_mux[] = { 2322 HRTS4_N_MARK, HCTS4_N_MARK, 2323 }; 2324 2325 static const unsigned int hscif4_data_b_pins[] = { 2326 /* RX, TX */ 2327 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), 2328 }; 2329 static const unsigned int hscif4_data_b_mux[] = { 2330 HRX4_B_MARK, HTX4_B_MARK, 2331 }; 2332 2333 /* - I2C -------------------------------------------------------------------- */ 2334 static const unsigned int i2c0_pins[] = { 2335 /* SCL, SDA */ 2336 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), 2337 }; 2338 2339 static const unsigned int i2c0_mux[] = { 2340 SCL0_MARK, SDA0_MARK, 2341 }; 2342 2343 static const unsigned int i2c1_a_pins[] = { 2344 /* SDA, SCL */ 2345 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10), 2346 }; 2347 static const unsigned int i2c1_a_mux[] = { 2348 SDA1_A_MARK, SCL1_A_MARK, 2349 }; 2350 static const unsigned int i2c1_b_pins[] = { 2351 /* SDA, SCL */ 2352 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23), 2353 }; 2354 static const unsigned int i2c1_b_mux[] = { 2355 SDA1_B_MARK, SCL1_B_MARK, 2356 }; 2357 static const unsigned int i2c2_a_pins[] = { 2358 /* SDA, SCL */ 2359 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4), 2360 }; 2361 static const unsigned int i2c2_a_mux[] = { 2362 SDA2_A_MARK, SCL2_A_MARK, 2363 }; 2364 static const unsigned int i2c2_b_pins[] = { 2365 /* SDA, SCL */ 2366 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12), 2367 }; 2368 static const unsigned int i2c2_b_mux[] = { 2369 SDA2_B_MARK, SCL2_B_MARK, 2370 }; 2371 2372 static const unsigned int i2c3_pins[] = { 2373 /* SCL, SDA */ 2374 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), 2375 }; 2376 2377 static const unsigned int i2c3_mux[] = { 2378 SCL3_MARK, SDA3_MARK, 2379 }; 2380 2381 static const unsigned int i2c5_pins[] = { 2382 /* SCL, SDA */ 2383 RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14), 2384 }; 2385 2386 static const unsigned int i2c5_mux[] = { 2387 SCL5_MARK, SDA5_MARK, 2388 }; 2389 2390 static const unsigned int i2c6_a_pins[] = { 2391 /* SDA, SCL */ 2392 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), 2393 }; 2394 static const unsigned int i2c6_a_mux[] = { 2395 SDA6_A_MARK, SCL6_A_MARK, 2396 }; 2397 static const unsigned int i2c6_b_pins[] = { 2398 /* SDA, SCL */ 2399 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25), 2400 }; 2401 static const unsigned int i2c6_b_mux[] = { 2402 SDA6_B_MARK, SCL6_B_MARK, 2403 }; 2404 static const unsigned int i2c6_c_pins[] = { 2405 /* SDA, SCL */ 2406 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), 2407 }; 2408 static const unsigned int i2c6_c_mux[] = { 2409 SDA6_C_MARK, SCL6_C_MARK, 2410 }; 2411 2412 /* - INTC-EX ---------------------------------------------------------------- */ 2413 static const unsigned int intc_ex_irq0_pins[] = { 2414 /* IRQ0 */ 2415 RCAR_GP_PIN(2, 0), 2416 }; 2417 static const unsigned int intc_ex_irq0_mux[] = { 2418 IRQ0_MARK, 2419 }; 2420 static const unsigned int intc_ex_irq1_pins[] = { 2421 /* IRQ1 */ 2422 RCAR_GP_PIN(2, 1), 2423 }; 2424 static const unsigned int intc_ex_irq1_mux[] = { 2425 IRQ1_MARK, 2426 }; 2427 static const unsigned int intc_ex_irq2_pins[] = { 2428 /* IRQ2 */ 2429 RCAR_GP_PIN(2, 2), 2430 }; 2431 static const unsigned int intc_ex_irq2_mux[] = { 2432 IRQ2_MARK, 2433 }; 2434 static const unsigned int intc_ex_irq3_pins[] = { 2435 /* IRQ3 */ 2436 RCAR_GP_PIN(2, 3), 2437 }; 2438 static const unsigned int intc_ex_irq3_mux[] = { 2439 IRQ3_MARK, 2440 }; 2441 static const unsigned int intc_ex_irq4_pins[] = { 2442 /* IRQ4 */ 2443 RCAR_GP_PIN(2, 4), 2444 }; 2445 static const unsigned int intc_ex_irq4_mux[] = { 2446 IRQ4_MARK, 2447 }; 2448 static const unsigned int intc_ex_irq5_pins[] = { 2449 /* IRQ5 */ 2450 RCAR_GP_PIN(2, 5), 2451 }; 2452 static const unsigned int intc_ex_irq5_mux[] = { 2453 IRQ5_MARK, 2454 }; 2455 2456 /* - MSIOF0 ----------------------------------------------------------------- */ 2457 static const unsigned int msiof0_clk_pins[] = { 2458 /* SCK */ 2459 RCAR_GP_PIN(5, 17), 2460 }; 2461 static const unsigned int msiof0_clk_mux[] = { 2462 MSIOF0_SCK_MARK, 2463 }; 2464 static const unsigned int msiof0_sync_pins[] = { 2465 /* SYNC */ 2466 RCAR_GP_PIN(5, 18), 2467 }; 2468 static const unsigned int msiof0_sync_mux[] = { 2469 MSIOF0_SYNC_MARK, 2470 }; 2471 static const unsigned int msiof0_ss1_pins[] = { 2472 /* SS1 */ 2473 RCAR_GP_PIN(5, 19), 2474 }; 2475 static const unsigned int msiof0_ss1_mux[] = { 2476 MSIOF0_SS1_MARK, 2477 }; 2478 static const unsigned int msiof0_ss2_pins[] = { 2479 /* SS2 */ 2480 RCAR_GP_PIN(5, 21), 2481 }; 2482 static const unsigned int msiof0_ss2_mux[] = { 2483 MSIOF0_SS2_MARK, 2484 }; 2485 static const unsigned int msiof0_txd_pins[] = { 2486 /* TXD */ 2487 RCAR_GP_PIN(5, 20), 2488 }; 2489 static const unsigned int msiof0_txd_mux[] = { 2490 MSIOF0_TXD_MARK, 2491 }; 2492 static const unsigned int msiof0_rxd_pins[] = { 2493 /* RXD */ 2494 RCAR_GP_PIN(5, 22), 2495 }; 2496 static const unsigned int msiof0_rxd_mux[] = { 2497 MSIOF0_RXD_MARK, 2498 }; 2499 /* - MSIOF1 ----------------------------------------------------------------- */ 2500 static const unsigned int msiof1_clk_a_pins[] = { 2501 /* SCK */ 2502 RCAR_GP_PIN(6, 8), 2503 }; 2504 static const unsigned int msiof1_clk_a_mux[] = { 2505 MSIOF1_SCK_A_MARK, 2506 }; 2507 static const unsigned int msiof1_sync_a_pins[] = { 2508 /* SYNC */ 2509 RCAR_GP_PIN(6, 9), 2510 }; 2511 static const unsigned int msiof1_sync_a_mux[] = { 2512 MSIOF1_SYNC_A_MARK, 2513 }; 2514 static const unsigned int msiof1_ss1_a_pins[] = { 2515 /* SS1 */ 2516 RCAR_GP_PIN(6, 5), 2517 }; 2518 static const unsigned int msiof1_ss1_a_mux[] = { 2519 MSIOF1_SS1_A_MARK, 2520 }; 2521 static const unsigned int msiof1_ss2_a_pins[] = { 2522 /* SS2 */ 2523 RCAR_GP_PIN(6, 6), 2524 }; 2525 static const unsigned int msiof1_ss2_a_mux[] = { 2526 MSIOF1_SS2_A_MARK, 2527 }; 2528 static const unsigned int msiof1_txd_a_pins[] = { 2529 /* TXD */ 2530 RCAR_GP_PIN(6, 7), 2531 }; 2532 static const unsigned int msiof1_txd_a_mux[] = { 2533 MSIOF1_TXD_A_MARK, 2534 }; 2535 static const unsigned int msiof1_rxd_a_pins[] = { 2536 /* RXD */ 2537 RCAR_GP_PIN(6, 10), 2538 }; 2539 static const unsigned int msiof1_rxd_a_mux[] = { 2540 MSIOF1_RXD_A_MARK, 2541 }; 2542 static const unsigned int msiof1_clk_b_pins[] = { 2543 /* SCK */ 2544 RCAR_GP_PIN(5, 9), 2545 }; 2546 static const unsigned int msiof1_clk_b_mux[] = { 2547 MSIOF1_SCK_B_MARK, 2548 }; 2549 static const unsigned int msiof1_sync_b_pins[] = { 2550 /* SYNC */ 2551 RCAR_GP_PIN(5, 3), 2552 }; 2553 static const unsigned int msiof1_sync_b_mux[] = { 2554 MSIOF1_SYNC_B_MARK, 2555 }; 2556 static const unsigned int msiof1_ss1_b_pins[] = { 2557 /* SS1 */ 2558 RCAR_GP_PIN(5, 4), 2559 }; 2560 static const unsigned int msiof1_ss1_b_mux[] = { 2561 MSIOF1_SS1_B_MARK, 2562 }; 2563 static const unsigned int msiof1_ss2_b_pins[] = { 2564 /* SS2 */ 2565 RCAR_GP_PIN(5, 0), 2566 }; 2567 static const unsigned int msiof1_ss2_b_mux[] = { 2568 MSIOF1_SS2_B_MARK, 2569 }; 2570 static const unsigned int msiof1_txd_b_pins[] = { 2571 /* TXD */ 2572 RCAR_GP_PIN(5, 8), 2573 }; 2574 static const unsigned int msiof1_txd_b_mux[] = { 2575 MSIOF1_TXD_B_MARK, 2576 }; 2577 static const unsigned int msiof1_rxd_b_pins[] = { 2578 /* RXD */ 2579 RCAR_GP_PIN(5, 7), 2580 }; 2581 static const unsigned int msiof1_rxd_b_mux[] = { 2582 MSIOF1_RXD_B_MARK, 2583 }; 2584 static const unsigned int msiof1_clk_c_pins[] = { 2585 /* SCK */ 2586 RCAR_GP_PIN(6, 17), 2587 }; 2588 static const unsigned int msiof1_clk_c_mux[] = { 2589 MSIOF1_SCK_C_MARK, 2590 }; 2591 static const unsigned int msiof1_sync_c_pins[] = { 2592 /* SYNC */ 2593 RCAR_GP_PIN(6, 18), 2594 }; 2595 static const unsigned int msiof1_sync_c_mux[] = { 2596 MSIOF1_SYNC_C_MARK, 2597 }; 2598 static const unsigned int msiof1_ss1_c_pins[] = { 2599 /* SS1 */ 2600 RCAR_GP_PIN(6, 21), 2601 }; 2602 static const unsigned int msiof1_ss1_c_mux[] = { 2603 MSIOF1_SS1_C_MARK, 2604 }; 2605 static const unsigned int msiof1_ss2_c_pins[] = { 2606 /* SS2 */ 2607 RCAR_GP_PIN(6, 27), 2608 }; 2609 static const unsigned int msiof1_ss2_c_mux[] = { 2610 MSIOF1_SS2_C_MARK, 2611 }; 2612 static const unsigned int msiof1_txd_c_pins[] = { 2613 /* TXD */ 2614 RCAR_GP_PIN(6, 20), 2615 }; 2616 static const unsigned int msiof1_txd_c_mux[] = { 2617 MSIOF1_TXD_C_MARK, 2618 }; 2619 static const unsigned int msiof1_rxd_c_pins[] = { 2620 /* RXD */ 2621 RCAR_GP_PIN(6, 19), 2622 }; 2623 static const unsigned int msiof1_rxd_c_mux[] = { 2624 MSIOF1_RXD_C_MARK, 2625 }; 2626 static const unsigned int msiof1_clk_d_pins[] = { 2627 /* SCK */ 2628 RCAR_GP_PIN(5, 12), 2629 }; 2630 static const unsigned int msiof1_clk_d_mux[] = { 2631 MSIOF1_SCK_D_MARK, 2632 }; 2633 static const unsigned int msiof1_sync_d_pins[] = { 2634 /* SYNC */ 2635 RCAR_GP_PIN(5, 15), 2636 }; 2637 static const unsigned int msiof1_sync_d_mux[] = { 2638 MSIOF1_SYNC_D_MARK, 2639 }; 2640 static const unsigned int msiof1_ss1_d_pins[] = { 2641 /* SS1 */ 2642 RCAR_GP_PIN(5, 16), 2643 }; 2644 static const unsigned int msiof1_ss1_d_mux[] = { 2645 MSIOF1_SS1_D_MARK, 2646 }; 2647 static const unsigned int msiof1_ss2_d_pins[] = { 2648 /* SS2 */ 2649 RCAR_GP_PIN(5, 21), 2650 }; 2651 static const unsigned int msiof1_ss2_d_mux[] = { 2652 MSIOF1_SS2_D_MARK, 2653 }; 2654 static const unsigned int msiof1_txd_d_pins[] = { 2655 /* TXD */ 2656 RCAR_GP_PIN(5, 14), 2657 }; 2658 static const unsigned int msiof1_txd_d_mux[] = { 2659 MSIOF1_TXD_D_MARK, 2660 }; 2661 static const unsigned int msiof1_rxd_d_pins[] = { 2662 /* RXD */ 2663 RCAR_GP_PIN(5, 13), 2664 }; 2665 static const unsigned int msiof1_rxd_d_mux[] = { 2666 MSIOF1_RXD_D_MARK, 2667 }; 2668 static const unsigned int msiof1_clk_e_pins[] = { 2669 /* SCK */ 2670 RCAR_GP_PIN(3, 0), 2671 }; 2672 static const unsigned int msiof1_clk_e_mux[] = { 2673 MSIOF1_SCK_E_MARK, 2674 }; 2675 static const unsigned int msiof1_sync_e_pins[] = { 2676 /* SYNC */ 2677 RCAR_GP_PIN(3, 1), 2678 }; 2679 static const unsigned int msiof1_sync_e_mux[] = { 2680 MSIOF1_SYNC_E_MARK, 2681 }; 2682 static const unsigned int msiof1_ss1_e_pins[] = { 2683 /* SS1 */ 2684 RCAR_GP_PIN(3, 4), 2685 }; 2686 static const unsigned int msiof1_ss1_e_mux[] = { 2687 MSIOF1_SS1_E_MARK, 2688 }; 2689 static const unsigned int msiof1_ss2_e_pins[] = { 2690 /* SS2 */ 2691 RCAR_GP_PIN(3, 5), 2692 }; 2693 static const unsigned int msiof1_ss2_e_mux[] = { 2694 MSIOF1_SS2_E_MARK, 2695 }; 2696 static const unsigned int msiof1_txd_e_pins[] = { 2697 /* TXD */ 2698 RCAR_GP_PIN(3, 3), 2699 }; 2700 static const unsigned int msiof1_txd_e_mux[] = { 2701 MSIOF1_TXD_E_MARK, 2702 }; 2703 static const unsigned int msiof1_rxd_e_pins[] = { 2704 /* RXD */ 2705 RCAR_GP_PIN(3, 2), 2706 }; 2707 static const unsigned int msiof1_rxd_e_mux[] = { 2708 MSIOF1_RXD_E_MARK, 2709 }; 2710 static const unsigned int msiof1_clk_f_pins[] = { 2711 /* SCK */ 2712 RCAR_GP_PIN(5, 23), 2713 }; 2714 static const unsigned int msiof1_clk_f_mux[] = { 2715 MSIOF1_SCK_F_MARK, 2716 }; 2717 static const unsigned int msiof1_sync_f_pins[] = { 2718 /* SYNC */ 2719 RCAR_GP_PIN(5, 24), 2720 }; 2721 static const unsigned int msiof1_sync_f_mux[] = { 2722 MSIOF1_SYNC_F_MARK, 2723 }; 2724 static const unsigned int msiof1_ss1_f_pins[] = { 2725 /* SS1 */ 2726 RCAR_GP_PIN(6, 1), 2727 }; 2728 static const unsigned int msiof1_ss1_f_mux[] = { 2729 MSIOF1_SS1_F_MARK, 2730 }; 2731 static const unsigned int msiof1_ss2_f_pins[] = { 2732 /* SS2 */ 2733 RCAR_GP_PIN(6, 2), 2734 }; 2735 static const unsigned int msiof1_ss2_f_mux[] = { 2736 MSIOF1_SS2_F_MARK, 2737 }; 2738 static const unsigned int msiof1_txd_f_pins[] = { 2739 /* TXD */ 2740 RCAR_GP_PIN(6, 0), 2741 }; 2742 static const unsigned int msiof1_txd_f_mux[] = { 2743 MSIOF1_TXD_F_MARK, 2744 }; 2745 static const unsigned int msiof1_rxd_f_pins[] = { 2746 /* RXD */ 2747 RCAR_GP_PIN(5, 25), 2748 }; 2749 static const unsigned int msiof1_rxd_f_mux[] = { 2750 MSIOF1_RXD_F_MARK, 2751 }; 2752 static const unsigned int msiof1_clk_g_pins[] = { 2753 /* SCK */ 2754 RCAR_GP_PIN(3, 6), 2755 }; 2756 static const unsigned int msiof1_clk_g_mux[] = { 2757 MSIOF1_SCK_G_MARK, 2758 }; 2759 static const unsigned int msiof1_sync_g_pins[] = { 2760 /* SYNC */ 2761 RCAR_GP_PIN(3, 7), 2762 }; 2763 static const unsigned int msiof1_sync_g_mux[] = { 2764 MSIOF1_SYNC_G_MARK, 2765 }; 2766 static const unsigned int msiof1_ss1_g_pins[] = { 2767 /* SS1 */ 2768 RCAR_GP_PIN(3, 10), 2769 }; 2770 static const unsigned int msiof1_ss1_g_mux[] = { 2771 MSIOF1_SS1_G_MARK, 2772 }; 2773 static const unsigned int msiof1_ss2_g_pins[] = { 2774 /* SS2 */ 2775 RCAR_GP_PIN(3, 11), 2776 }; 2777 static const unsigned int msiof1_ss2_g_mux[] = { 2778 MSIOF1_SS2_G_MARK, 2779 }; 2780 static const unsigned int msiof1_txd_g_pins[] = { 2781 /* TXD */ 2782 RCAR_GP_PIN(3, 9), 2783 }; 2784 static const unsigned int msiof1_txd_g_mux[] = { 2785 MSIOF1_TXD_G_MARK, 2786 }; 2787 static const unsigned int msiof1_rxd_g_pins[] = { 2788 /* RXD */ 2789 RCAR_GP_PIN(3, 8), 2790 }; 2791 static const unsigned int msiof1_rxd_g_mux[] = { 2792 MSIOF1_RXD_G_MARK, 2793 }; 2794 /* - MSIOF2 ----------------------------------------------------------------- */ 2795 static const unsigned int msiof2_clk_a_pins[] = { 2796 /* SCK */ 2797 RCAR_GP_PIN(1, 9), 2798 }; 2799 static const unsigned int msiof2_clk_a_mux[] = { 2800 MSIOF2_SCK_A_MARK, 2801 }; 2802 static const unsigned int msiof2_sync_a_pins[] = { 2803 /* SYNC */ 2804 RCAR_GP_PIN(1, 8), 2805 }; 2806 static const unsigned int msiof2_sync_a_mux[] = { 2807 MSIOF2_SYNC_A_MARK, 2808 }; 2809 static const unsigned int msiof2_ss1_a_pins[] = { 2810 /* SS1 */ 2811 RCAR_GP_PIN(1, 6), 2812 }; 2813 static const unsigned int msiof2_ss1_a_mux[] = { 2814 MSIOF2_SS1_A_MARK, 2815 }; 2816 static const unsigned int msiof2_ss2_a_pins[] = { 2817 /* SS2 */ 2818 RCAR_GP_PIN(1, 7), 2819 }; 2820 static const unsigned int msiof2_ss2_a_mux[] = { 2821 MSIOF2_SS2_A_MARK, 2822 }; 2823 static const unsigned int msiof2_txd_a_pins[] = { 2824 /* TXD */ 2825 RCAR_GP_PIN(1, 11), 2826 }; 2827 static const unsigned int msiof2_txd_a_mux[] = { 2828 MSIOF2_TXD_A_MARK, 2829 }; 2830 static const unsigned int msiof2_rxd_a_pins[] = { 2831 /* RXD */ 2832 RCAR_GP_PIN(1, 10), 2833 }; 2834 static const unsigned int msiof2_rxd_a_mux[] = { 2835 MSIOF2_RXD_A_MARK, 2836 }; 2837 static const unsigned int msiof2_clk_b_pins[] = { 2838 /* SCK */ 2839 RCAR_GP_PIN(0, 4), 2840 }; 2841 static const unsigned int msiof2_clk_b_mux[] = { 2842 MSIOF2_SCK_B_MARK, 2843 }; 2844 static const unsigned int msiof2_sync_b_pins[] = { 2845 /* SYNC */ 2846 RCAR_GP_PIN(0, 5), 2847 }; 2848 static const unsigned int msiof2_sync_b_mux[] = { 2849 MSIOF2_SYNC_B_MARK, 2850 }; 2851 static const unsigned int msiof2_ss1_b_pins[] = { 2852 /* SS1 */ 2853 RCAR_GP_PIN(0, 0), 2854 }; 2855 static const unsigned int msiof2_ss1_b_mux[] = { 2856 MSIOF2_SS1_B_MARK, 2857 }; 2858 static const unsigned int msiof2_ss2_b_pins[] = { 2859 /* SS2 */ 2860 RCAR_GP_PIN(0, 1), 2861 }; 2862 static const unsigned int msiof2_ss2_b_mux[] = { 2863 MSIOF2_SS2_B_MARK, 2864 }; 2865 static const unsigned int msiof2_txd_b_pins[] = { 2866 /* TXD */ 2867 RCAR_GP_PIN(0, 7), 2868 }; 2869 static const unsigned int msiof2_txd_b_mux[] = { 2870 MSIOF2_TXD_B_MARK, 2871 }; 2872 static const unsigned int msiof2_rxd_b_pins[] = { 2873 /* RXD */ 2874 RCAR_GP_PIN(0, 6), 2875 }; 2876 static const unsigned int msiof2_rxd_b_mux[] = { 2877 MSIOF2_RXD_B_MARK, 2878 }; 2879 static const unsigned int msiof2_clk_c_pins[] = { 2880 /* SCK */ 2881 RCAR_GP_PIN(2, 12), 2882 }; 2883 static const unsigned int msiof2_clk_c_mux[] = { 2884 MSIOF2_SCK_C_MARK, 2885 }; 2886 static const unsigned int msiof2_sync_c_pins[] = { 2887 /* SYNC */ 2888 RCAR_GP_PIN(2, 11), 2889 }; 2890 static const unsigned int msiof2_sync_c_mux[] = { 2891 MSIOF2_SYNC_C_MARK, 2892 }; 2893 static const unsigned int msiof2_ss1_c_pins[] = { 2894 /* SS1 */ 2895 RCAR_GP_PIN(2, 10), 2896 }; 2897 static const unsigned int msiof2_ss1_c_mux[] = { 2898 MSIOF2_SS1_C_MARK, 2899 }; 2900 static const unsigned int msiof2_ss2_c_pins[] = { 2901 /* SS2 */ 2902 RCAR_GP_PIN(2, 9), 2903 }; 2904 static const unsigned int msiof2_ss2_c_mux[] = { 2905 MSIOF2_SS2_C_MARK, 2906 }; 2907 static const unsigned int msiof2_txd_c_pins[] = { 2908 /* TXD */ 2909 RCAR_GP_PIN(2, 14), 2910 }; 2911 static const unsigned int msiof2_txd_c_mux[] = { 2912 MSIOF2_TXD_C_MARK, 2913 }; 2914 static const unsigned int msiof2_rxd_c_pins[] = { 2915 /* RXD */ 2916 RCAR_GP_PIN(2, 13), 2917 }; 2918 static const unsigned int msiof2_rxd_c_mux[] = { 2919 MSIOF2_RXD_C_MARK, 2920 }; 2921 static const unsigned int msiof2_clk_d_pins[] = { 2922 /* SCK */ 2923 RCAR_GP_PIN(0, 8), 2924 }; 2925 static const unsigned int msiof2_clk_d_mux[] = { 2926 MSIOF2_SCK_D_MARK, 2927 }; 2928 static const unsigned int msiof2_sync_d_pins[] = { 2929 /* SYNC */ 2930 RCAR_GP_PIN(0, 9), 2931 }; 2932 static const unsigned int msiof2_sync_d_mux[] = { 2933 MSIOF2_SYNC_D_MARK, 2934 }; 2935 static const unsigned int msiof2_ss1_d_pins[] = { 2936 /* SS1 */ 2937 RCAR_GP_PIN(0, 12), 2938 }; 2939 static const unsigned int msiof2_ss1_d_mux[] = { 2940 MSIOF2_SS1_D_MARK, 2941 }; 2942 static const unsigned int msiof2_ss2_d_pins[] = { 2943 /* SS2 */ 2944 RCAR_GP_PIN(0, 13), 2945 }; 2946 static const unsigned int msiof2_ss2_d_mux[] = { 2947 MSIOF2_SS2_D_MARK, 2948 }; 2949 static const unsigned int msiof2_txd_d_pins[] = { 2950 /* TXD */ 2951 RCAR_GP_PIN(0, 11), 2952 }; 2953 static const unsigned int msiof2_txd_d_mux[] = { 2954 MSIOF2_TXD_D_MARK, 2955 }; 2956 static const unsigned int msiof2_rxd_d_pins[] = { 2957 /* RXD */ 2958 RCAR_GP_PIN(0, 10), 2959 }; 2960 static const unsigned int msiof2_rxd_d_mux[] = { 2961 MSIOF2_RXD_D_MARK, 2962 }; 2963 /* - MSIOF3 ----------------------------------------------------------------- */ 2964 static const unsigned int msiof3_clk_a_pins[] = { 2965 /* SCK */ 2966 RCAR_GP_PIN(0, 0), 2967 }; 2968 static const unsigned int msiof3_clk_a_mux[] = { 2969 MSIOF3_SCK_A_MARK, 2970 }; 2971 static const unsigned int msiof3_sync_a_pins[] = { 2972 /* SYNC */ 2973 RCAR_GP_PIN(0, 1), 2974 }; 2975 static const unsigned int msiof3_sync_a_mux[] = { 2976 MSIOF3_SYNC_A_MARK, 2977 }; 2978 static const unsigned int msiof3_ss1_a_pins[] = { 2979 /* SS1 */ 2980 RCAR_GP_PIN(0, 14), 2981 }; 2982 static const unsigned int msiof3_ss1_a_mux[] = { 2983 MSIOF3_SS1_A_MARK, 2984 }; 2985 static const unsigned int msiof3_ss2_a_pins[] = { 2986 /* SS2 */ 2987 RCAR_GP_PIN(0, 15), 2988 }; 2989 static const unsigned int msiof3_ss2_a_mux[] = { 2990 MSIOF3_SS2_A_MARK, 2991 }; 2992 static const unsigned int msiof3_txd_a_pins[] = { 2993 /* TXD */ 2994 RCAR_GP_PIN(0, 3), 2995 }; 2996 static const unsigned int msiof3_txd_a_mux[] = { 2997 MSIOF3_TXD_A_MARK, 2998 }; 2999 static const unsigned int msiof3_rxd_a_pins[] = { 3000 /* RXD */ 3001 RCAR_GP_PIN(0, 2), 3002 }; 3003 static const unsigned int msiof3_rxd_a_mux[] = { 3004 MSIOF3_RXD_A_MARK, 3005 }; 3006 static const unsigned int msiof3_clk_b_pins[] = { 3007 /* SCK */ 3008 RCAR_GP_PIN(1, 2), 3009 }; 3010 static const unsigned int msiof3_clk_b_mux[] = { 3011 MSIOF3_SCK_B_MARK, 3012 }; 3013 static const unsigned int msiof3_sync_b_pins[] = { 3014 /* SYNC */ 3015 RCAR_GP_PIN(1, 0), 3016 }; 3017 static const unsigned int msiof3_sync_b_mux[] = { 3018 MSIOF3_SYNC_B_MARK, 3019 }; 3020 static const unsigned int msiof3_ss1_b_pins[] = { 3021 /* SS1 */ 3022 RCAR_GP_PIN(1, 4), 3023 }; 3024 static const unsigned int msiof3_ss1_b_mux[] = { 3025 MSIOF3_SS1_B_MARK, 3026 }; 3027 static const unsigned int msiof3_ss2_b_pins[] = { 3028 /* SS2 */ 3029 RCAR_GP_PIN(1, 5), 3030 }; 3031 static const unsigned int msiof3_ss2_b_mux[] = { 3032 MSIOF3_SS2_B_MARK, 3033 }; 3034 static const unsigned int msiof3_txd_b_pins[] = { 3035 /* TXD */ 3036 RCAR_GP_PIN(1, 1), 3037 }; 3038 static const unsigned int msiof3_txd_b_mux[] = { 3039 MSIOF3_TXD_B_MARK, 3040 }; 3041 static const unsigned int msiof3_rxd_b_pins[] = { 3042 /* RXD */ 3043 RCAR_GP_PIN(1, 3), 3044 }; 3045 static const unsigned int msiof3_rxd_b_mux[] = { 3046 MSIOF3_RXD_B_MARK, 3047 }; 3048 static const unsigned int msiof3_clk_c_pins[] = { 3049 /* SCK */ 3050 RCAR_GP_PIN(1, 12), 3051 }; 3052 static const unsigned int msiof3_clk_c_mux[] = { 3053 MSIOF3_SCK_C_MARK, 3054 }; 3055 static const unsigned int msiof3_sync_c_pins[] = { 3056 /* SYNC */ 3057 RCAR_GP_PIN(1, 13), 3058 }; 3059 static const unsigned int msiof3_sync_c_mux[] = { 3060 MSIOF3_SYNC_C_MARK, 3061 }; 3062 static const unsigned int msiof3_txd_c_pins[] = { 3063 /* TXD */ 3064 RCAR_GP_PIN(1, 15), 3065 }; 3066 static const unsigned int msiof3_txd_c_mux[] = { 3067 MSIOF3_TXD_C_MARK, 3068 }; 3069 static const unsigned int msiof3_rxd_c_pins[] = { 3070 /* RXD */ 3071 RCAR_GP_PIN(1, 14), 3072 }; 3073 static const unsigned int msiof3_rxd_c_mux[] = { 3074 MSIOF3_RXD_C_MARK, 3075 }; 3076 static const unsigned int msiof3_clk_d_pins[] = { 3077 /* SCK */ 3078 RCAR_GP_PIN(1, 22), 3079 }; 3080 static const unsigned int msiof3_clk_d_mux[] = { 3081 MSIOF3_SCK_D_MARK, 3082 }; 3083 static const unsigned int msiof3_sync_d_pins[] = { 3084 /* SYNC */ 3085 RCAR_GP_PIN(1, 23), 3086 }; 3087 static const unsigned int msiof3_sync_d_mux[] = { 3088 MSIOF3_SYNC_D_MARK, 3089 }; 3090 static const unsigned int msiof3_ss1_d_pins[] = { 3091 /* SS1 */ 3092 RCAR_GP_PIN(1, 26), 3093 }; 3094 static const unsigned int msiof3_ss1_d_mux[] = { 3095 MSIOF3_SS1_D_MARK, 3096 }; 3097 static const unsigned int msiof3_txd_d_pins[] = { 3098 /* TXD */ 3099 RCAR_GP_PIN(1, 25), 3100 }; 3101 static const unsigned int msiof3_txd_d_mux[] = { 3102 MSIOF3_TXD_D_MARK, 3103 }; 3104 static const unsigned int msiof3_rxd_d_pins[] = { 3105 /* RXD */ 3106 RCAR_GP_PIN(1, 24), 3107 }; 3108 static const unsigned int msiof3_rxd_d_mux[] = { 3109 MSIOF3_RXD_D_MARK, 3110 }; 3111 static const unsigned int msiof3_clk_e_pins[] = { 3112 /* SCK */ 3113 RCAR_GP_PIN(2, 3), 3114 }; 3115 static const unsigned int msiof3_clk_e_mux[] = { 3116 MSIOF3_SCK_E_MARK, 3117 }; 3118 static const unsigned int msiof3_sync_e_pins[] = { 3119 /* SYNC */ 3120 RCAR_GP_PIN(2, 2), 3121 }; 3122 static const unsigned int msiof3_sync_e_mux[] = { 3123 MSIOF3_SYNC_E_MARK, 3124 }; 3125 static const unsigned int msiof3_ss1_e_pins[] = { 3126 /* SS1 */ 3127 RCAR_GP_PIN(2, 1), 3128 }; 3129 static const unsigned int msiof3_ss1_e_mux[] = { 3130 MSIOF3_SS1_E_MARK, 3131 }; 3132 static const unsigned int msiof3_ss2_e_pins[] = { 3133 /* SS2 */ 3134 RCAR_GP_PIN(2, 0), 3135 }; 3136 static const unsigned int msiof3_ss2_e_mux[] = { 3137 MSIOF3_SS2_E_MARK, 3138 }; 3139 static const unsigned int msiof3_txd_e_pins[] = { 3140 /* TXD */ 3141 RCAR_GP_PIN(2, 5), 3142 }; 3143 static const unsigned int msiof3_txd_e_mux[] = { 3144 MSIOF3_TXD_E_MARK, 3145 }; 3146 static const unsigned int msiof3_rxd_e_pins[] = { 3147 /* RXD */ 3148 RCAR_GP_PIN(2, 4), 3149 }; 3150 static const unsigned int msiof3_rxd_e_mux[] = { 3151 MSIOF3_RXD_E_MARK, 3152 }; 3153 3154 /* - PWM0 --------------------------------------------------------------------*/ 3155 static const unsigned int pwm0_pins[] = { 3156 /* PWM */ 3157 RCAR_GP_PIN(2, 6), 3158 }; 3159 static const unsigned int pwm0_mux[] = { 3160 PWM0_MARK, 3161 }; 3162 /* - PWM1 --------------------------------------------------------------------*/ 3163 static const unsigned int pwm1_a_pins[] = { 3164 /* PWM */ 3165 RCAR_GP_PIN(2, 7), 3166 }; 3167 static const unsigned int pwm1_a_mux[] = { 3168 PWM1_A_MARK, 3169 }; 3170 static const unsigned int pwm1_b_pins[] = { 3171 /* PWM */ 3172 RCAR_GP_PIN(1, 8), 3173 }; 3174 static const unsigned int pwm1_b_mux[] = { 3175 PWM1_B_MARK, 3176 }; 3177 /* - PWM2 --------------------------------------------------------------------*/ 3178 static const unsigned int pwm2_a_pins[] = { 3179 /* PWM */ 3180 RCAR_GP_PIN(2, 8), 3181 }; 3182 static const unsigned int pwm2_a_mux[] = { 3183 PWM2_A_MARK, 3184 }; 3185 static const unsigned int pwm2_b_pins[] = { 3186 /* PWM */ 3187 RCAR_GP_PIN(1, 11), 3188 }; 3189 static const unsigned int pwm2_b_mux[] = { 3190 PWM2_B_MARK, 3191 }; 3192 /* - PWM3 --------------------------------------------------------------------*/ 3193 static const unsigned int pwm3_a_pins[] = { 3194 /* PWM */ 3195 RCAR_GP_PIN(1, 0), 3196 }; 3197 static const unsigned int pwm3_a_mux[] = { 3198 PWM3_A_MARK, 3199 }; 3200 static const unsigned int pwm3_b_pins[] = { 3201 /* PWM */ 3202 RCAR_GP_PIN(2, 2), 3203 }; 3204 static const unsigned int pwm3_b_mux[] = { 3205 PWM3_B_MARK, 3206 }; 3207 /* - PWM4 --------------------------------------------------------------------*/ 3208 static const unsigned int pwm4_a_pins[] = { 3209 /* PWM */ 3210 RCAR_GP_PIN(1, 1), 3211 }; 3212 static const unsigned int pwm4_a_mux[] = { 3213 PWM4_A_MARK, 3214 }; 3215 static const unsigned int pwm4_b_pins[] = { 3216 /* PWM */ 3217 RCAR_GP_PIN(2, 3), 3218 }; 3219 static const unsigned int pwm4_b_mux[] = { 3220 PWM4_B_MARK, 3221 }; 3222 /* - PWM5 --------------------------------------------------------------------*/ 3223 static const unsigned int pwm5_a_pins[] = { 3224 /* PWM */ 3225 RCAR_GP_PIN(1, 2), 3226 }; 3227 static const unsigned int pwm5_a_mux[] = { 3228 PWM5_A_MARK, 3229 }; 3230 static const unsigned int pwm5_b_pins[] = { 3231 /* PWM */ 3232 RCAR_GP_PIN(2, 4), 3233 }; 3234 static const unsigned int pwm5_b_mux[] = { 3235 PWM5_B_MARK, 3236 }; 3237 /* - PWM6 --------------------------------------------------------------------*/ 3238 static const unsigned int pwm6_a_pins[] = { 3239 /* PWM */ 3240 RCAR_GP_PIN(1, 3), 3241 }; 3242 static const unsigned int pwm6_a_mux[] = { 3243 PWM6_A_MARK, 3244 }; 3245 static const unsigned int pwm6_b_pins[] = { 3246 /* PWM */ 3247 RCAR_GP_PIN(2, 5), 3248 }; 3249 static const unsigned int pwm6_b_mux[] = { 3250 PWM6_B_MARK, 3251 }; 3252 3253 /* - SATA --------------------------------------------------------------------*/ 3254 static const unsigned int sata0_devslp_a_pins[] = { 3255 /* DEVSLP */ 3256 RCAR_GP_PIN(6, 16), 3257 }; 3258 static const unsigned int sata0_devslp_a_mux[] = { 3259 SATA_DEVSLP_A_MARK, 3260 }; 3261 static const unsigned int sata0_devslp_b_pins[] = { 3262 /* DEVSLP */ 3263 RCAR_GP_PIN(4, 6), 3264 }; 3265 static const unsigned int sata0_devslp_b_mux[] = { 3266 SATA_DEVSLP_B_MARK, 3267 }; 3268 3269 /* - SCIF0 ------------------------------------------------------------------ */ 3270 static const unsigned int scif0_data_pins[] = { 3271 /* RX, TX */ 3272 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), 3273 }; 3274 static const unsigned int scif0_data_mux[] = { 3275 RX0_MARK, TX0_MARK, 3276 }; 3277 static const unsigned int scif0_clk_pins[] = { 3278 /* SCK */ 3279 RCAR_GP_PIN(5, 0), 3280 }; 3281 static const unsigned int scif0_clk_mux[] = { 3282 SCK0_MARK, 3283 }; 3284 static const unsigned int scif0_ctrl_pins[] = { 3285 /* RTS, CTS */ 3286 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3), 3287 }; 3288 static const unsigned int scif0_ctrl_mux[] = { 3289 RTS0_N_MARK, CTS0_N_MARK, 3290 }; 3291 /* - SCIF1 ------------------------------------------------------------------ */ 3292 static const unsigned int scif1_data_a_pins[] = { 3293 /* RX, TX */ 3294 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6), 3295 }; 3296 static const unsigned int scif1_data_a_mux[] = { 3297 RX1_A_MARK, TX1_A_MARK, 3298 }; 3299 static const unsigned int scif1_clk_pins[] = { 3300 /* SCK */ 3301 RCAR_GP_PIN(6, 21), 3302 }; 3303 static const unsigned int scif1_clk_mux[] = { 3304 SCK1_MARK, 3305 }; 3306 static const unsigned int scif1_ctrl_pins[] = { 3307 /* RTS, CTS */ 3308 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7), 3309 }; 3310 static const unsigned int scif1_ctrl_mux[] = { 3311 RTS1_N_MARK, CTS1_N_MARK, 3312 }; 3313 3314 static const unsigned int scif1_data_b_pins[] = { 3315 /* RX, TX */ 3316 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25), 3317 }; 3318 static const unsigned int scif1_data_b_mux[] = { 3319 RX1_B_MARK, TX1_B_MARK, 3320 }; 3321 /* - SCIF2 ------------------------------------------------------------------ */ 3322 static const unsigned int scif2_data_a_pins[] = { 3323 /* RX, TX */ 3324 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10), 3325 }; 3326 static const unsigned int scif2_data_a_mux[] = { 3327 RX2_A_MARK, TX2_A_MARK, 3328 }; 3329 static const unsigned int scif2_clk_pins[] = { 3330 /* SCK */ 3331 RCAR_GP_PIN(5, 9), 3332 }; 3333 static const unsigned int scif2_clk_mux[] = { 3334 SCK2_MARK, 3335 }; 3336 static const unsigned int scif2_data_b_pins[] = { 3337 /* RX, TX */ 3338 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16), 3339 }; 3340 static const unsigned int scif2_data_b_mux[] = { 3341 RX2_B_MARK, TX2_B_MARK, 3342 }; 3343 /* - SCIF3 ------------------------------------------------------------------ */ 3344 static const unsigned int scif3_data_a_pins[] = { 3345 /* RX, TX */ 3346 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24), 3347 }; 3348 static const unsigned int scif3_data_a_mux[] = { 3349 RX3_A_MARK, TX3_A_MARK, 3350 }; 3351 static const unsigned int scif3_clk_pins[] = { 3352 /* SCK */ 3353 RCAR_GP_PIN(1, 22), 3354 }; 3355 static const unsigned int scif3_clk_mux[] = { 3356 SCK3_MARK, 3357 }; 3358 static const unsigned int scif3_ctrl_pins[] = { 3359 /* RTS, CTS */ 3360 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25), 3361 }; 3362 static const unsigned int scif3_ctrl_mux[] = { 3363 RTS3_N_MARK, CTS3_N_MARK, 3364 }; 3365 static const unsigned int scif3_data_b_pins[] = { 3366 /* RX, TX */ 3367 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), 3368 }; 3369 static const unsigned int scif3_data_b_mux[] = { 3370 RX3_B_MARK, TX3_B_MARK, 3371 }; 3372 /* - SCIF4 ------------------------------------------------------------------ */ 3373 static const unsigned int scif4_data_a_pins[] = { 3374 /* RX, TX */ 3375 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12), 3376 }; 3377 static const unsigned int scif4_data_a_mux[] = { 3378 RX4_A_MARK, TX4_A_MARK, 3379 }; 3380 static const unsigned int scif4_clk_a_pins[] = { 3381 /* SCK */ 3382 RCAR_GP_PIN(2, 10), 3383 }; 3384 static const unsigned int scif4_clk_a_mux[] = { 3385 SCK4_A_MARK, 3386 }; 3387 static const unsigned int scif4_ctrl_a_pins[] = { 3388 /* RTS, CTS */ 3389 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13), 3390 }; 3391 static const unsigned int scif4_ctrl_a_mux[] = { 3392 RTS4_N_A_MARK, CTS4_N_A_MARK, 3393 }; 3394 static const unsigned int scif4_data_b_pins[] = { 3395 /* RX, TX */ 3396 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 3397 }; 3398 static const unsigned int scif4_data_b_mux[] = { 3399 RX4_B_MARK, TX4_B_MARK, 3400 }; 3401 static const unsigned int scif4_clk_b_pins[] = { 3402 /* SCK */ 3403 RCAR_GP_PIN(1, 5), 3404 }; 3405 static const unsigned int scif4_clk_b_mux[] = { 3406 SCK4_B_MARK, 3407 }; 3408 static const unsigned int scif4_ctrl_b_pins[] = { 3409 /* RTS, CTS */ 3410 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9), 3411 }; 3412 static const unsigned int scif4_ctrl_b_mux[] = { 3413 RTS4_N_B_MARK, CTS4_N_B_MARK, 3414 }; 3415 static const unsigned int scif4_data_c_pins[] = { 3416 /* RX, TX */ 3417 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), 3418 }; 3419 static const unsigned int scif4_data_c_mux[] = { 3420 RX4_C_MARK, TX4_C_MARK, 3421 }; 3422 static const unsigned int scif4_clk_c_pins[] = { 3423 /* SCK */ 3424 RCAR_GP_PIN(0, 8), 3425 }; 3426 static const unsigned int scif4_clk_c_mux[] = { 3427 SCK4_C_MARK, 3428 }; 3429 static const unsigned int scif4_ctrl_c_pins[] = { 3430 /* RTS, CTS */ 3431 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), 3432 }; 3433 static const unsigned int scif4_ctrl_c_mux[] = { 3434 RTS4_N_C_MARK, CTS4_N_C_MARK, 3435 }; 3436 /* - SCIF5 ------------------------------------------------------------------ */ 3437 static const unsigned int scif5_data_a_pins[] = { 3438 /* RX, TX */ 3439 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21), 3440 }; 3441 static const unsigned int scif5_data_a_mux[] = { 3442 RX5_A_MARK, TX5_A_MARK, 3443 }; 3444 static const unsigned int scif5_clk_a_pins[] = { 3445 /* SCK */ 3446 RCAR_GP_PIN(6, 21), 3447 }; 3448 static const unsigned int scif5_clk_a_mux[] = { 3449 SCK5_A_MARK, 3450 }; 3451 static const unsigned int scif5_data_b_pins[] = { 3452 /* RX, TX */ 3453 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18), 3454 }; 3455 static const unsigned int scif5_data_b_mux[] = { 3456 RX5_B_MARK, TX5_B_MARK, 3457 }; 3458 static const unsigned int scif5_clk_b_pins[] = { 3459 /* SCK */ 3460 RCAR_GP_PIN(5, 0), 3461 }; 3462 static const unsigned int scif5_clk_b_mux[] = { 3463 SCK5_B_MARK, 3464 }; 3465 3466 /* - SCIF Clock ------------------------------------------------------------- */ 3467 static const unsigned int scif_clk_a_pins[] = { 3468 /* SCIF_CLK */ 3469 RCAR_GP_PIN(6, 23), 3470 }; 3471 static const unsigned int scif_clk_a_mux[] = { 3472 SCIF_CLK_A_MARK, 3473 }; 3474 static const unsigned int scif_clk_b_pins[] = { 3475 /* SCIF_CLK */ 3476 RCAR_GP_PIN(5, 9), 3477 }; 3478 static const unsigned int scif_clk_b_mux[] = { 3479 SCIF_CLK_B_MARK, 3480 }; 3481 3482 /* - SDHI0 ------------------------------------------------------------------ */ 3483 static const unsigned int sdhi0_data1_pins[] = { 3484 /* D0 */ 3485 RCAR_GP_PIN(3, 2), 3486 }; 3487 static const unsigned int sdhi0_data1_mux[] = { 3488 SD0_DAT0_MARK, 3489 }; 3490 static const unsigned int sdhi0_data4_pins[] = { 3491 /* D[0:3] */ 3492 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), 3493 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), 3494 }; 3495 static const unsigned int sdhi0_data4_mux[] = { 3496 SD0_DAT0_MARK, SD0_DAT1_MARK, 3497 SD0_DAT2_MARK, SD0_DAT3_MARK, 3498 }; 3499 static const unsigned int sdhi0_ctrl_pins[] = { 3500 /* CLK, CMD */ 3501 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1), 3502 }; 3503 static const unsigned int sdhi0_ctrl_mux[] = { 3504 SD0_CLK_MARK, SD0_CMD_MARK, 3505 }; 3506 static const unsigned int sdhi0_cd_pins[] = { 3507 /* CD */ 3508 RCAR_GP_PIN(3, 12), 3509 }; 3510 static const unsigned int sdhi0_cd_mux[] = { 3511 SD0_CD_MARK, 3512 }; 3513 static const unsigned int sdhi0_wp_pins[] = { 3514 /* WP */ 3515 RCAR_GP_PIN(3, 13), 3516 }; 3517 static const unsigned int sdhi0_wp_mux[] = { 3518 SD0_WP_MARK, 3519 }; 3520 /* - SDHI1 ------------------------------------------------------------------ */ 3521 static const unsigned int sdhi1_data1_pins[] = { 3522 /* D0 */ 3523 RCAR_GP_PIN(3, 8), 3524 }; 3525 static const unsigned int sdhi1_data1_mux[] = { 3526 SD1_DAT0_MARK, 3527 }; 3528 static const unsigned int sdhi1_data4_pins[] = { 3529 /* D[0:3] */ 3530 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), 3531 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), 3532 }; 3533 static const unsigned int sdhi1_data4_mux[] = { 3534 SD1_DAT0_MARK, SD1_DAT1_MARK, 3535 SD1_DAT2_MARK, SD1_DAT3_MARK, 3536 }; 3537 static const unsigned int sdhi1_ctrl_pins[] = { 3538 /* CLK, CMD */ 3539 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), 3540 }; 3541 static const unsigned int sdhi1_ctrl_mux[] = { 3542 SD1_CLK_MARK, SD1_CMD_MARK, 3543 }; 3544 static const unsigned int sdhi1_cd_pins[] = { 3545 /* CD */ 3546 RCAR_GP_PIN(3, 14), 3547 }; 3548 static const unsigned int sdhi1_cd_mux[] = { 3549 SD1_CD_MARK, 3550 }; 3551 static const unsigned int sdhi1_wp_pins[] = { 3552 /* WP */ 3553 RCAR_GP_PIN(3, 15), 3554 }; 3555 static const unsigned int sdhi1_wp_mux[] = { 3556 SD1_WP_MARK, 3557 }; 3558 /* - SDHI2 ------------------------------------------------------------------ */ 3559 static const unsigned int sdhi2_data1_pins[] = { 3560 /* D0 */ 3561 RCAR_GP_PIN(4, 2), 3562 }; 3563 static const unsigned int sdhi2_data1_mux[] = { 3564 SD2_DAT0_MARK, 3565 }; 3566 static const unsigned int sdhi2_data4_pins[] = { 3567 /* D[0:3] */ 3568 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), 3569 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), 3570 }; 3571 static const unsigned int sdhi2_data4_mux[] = { 3572 SD2_DAT0_MARK, SD2_DAT1_MARK, 3573 SD2_DAT2_MARK, SD2_DAT3_MARK, 3574 }; 3575 static const unsigned int sdhi2_data8_pins[] = { 3576 /* D[0:7] */ 3577 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), 3578 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), 3579 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), 3580 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), 3581 }; 3582 static const unsigned int sdhi2_data8_mux[] = { 3583 SD2_DAT0_MARK, SD2_DAT1_MARK, 3584 SD2_DAT2_MARK, SD2_DAT3_MARK, 3585 SD2_DAT4_MARK, SD2_DAT5_MARK, 3586 SD2_DAT6_MARK, SD2_DAT7_MARK, 3587 }; 3588 static const unsigned int sdhi2_ctrl_pins[] = { 3589 /* CLK, CMD */ 3590 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1), 3591 }; 3592 static const unsigned int sdhi2_ctrl_mux[] = { 3593 SD2_CLK_MARK, SD2_CMD_MARK, 3594 }; 3595 static const unsigned int sdhi2_cd_a_pins[] = { 3596 /* CD */ 3597 RCAR_GP_PIN(4, 13), 3598 }; 3599 static const unsigned int sdhi2_cd_a_mux[] = { 3600 SD2_CD_A_MARK, 3601 }; 3602 static const unsigned int sdhi2_cd_b_pins[] = { 3603 /* CD */ 3604 RCAR_GP_PIN(5, 10), 3605 }; 3606 static const unsigned int sdhi2_cd_b_mux[] = { 3607 SD2_CD_B_MARK, 3608 }; 3609 static const unsigned int sdhi2_wp_a_pins[] = { 3610 /* WP */ 3611 RCAR_GP_PIN(4, 14), 3612 }; 3613 static const unsigned int sdhi2_wp_a_mux[] = { 3614 SD2_WP_A_MARK, 3615 }; 3616 static const unsigned int sdhi2_wp_b_pins[] = { 3617 /* WP */ 3618 RCAR_GP_PIN(5, 11), 3619 }; 3620 static const unsigned int sdhi2_wp_b_mux[] = { 3621 SD2_WP_B_MARK, 3622 }; 3623 static const unsigned int sdhi2_ds_pins[] = { 3624 /* DS */ 3625 RCAR_GP_PIN(4, 6), 3626 }; 3627 static const unsigned int sdhi2_ds_mux[] = { 3628 SD2_DS_MARK, 3629 }; 3630 /* - SDHI3 ------------------------------------------------------------------ */ 3631 static const unsigned int sdhi3_data1_pins[] = { 3632 /* D0 */ 3633 RCAR_GP_PIN(4, 9), 3634 }; 3635 static const unsigned int sdhi3_data1_mux[] = { 3636 SD3_DAT0_MARK, 3637 }; 3638 static const unsigned int sdhi3_data4_pins[] = { 3639 /* D[0:3] */ 3640 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10), 3641 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12), 3642 }; 3643 static const unsigned int sdhi3_data4_mux[] = { 3644 SD3_DAT0_MARK, SD3_DAT1_MARK, 3645 SD3_DAT2_MARK, SD3_DAT3_MARK, 3646 }; 3647 static const unsigned int sdhi3_data8_pins[] = { 3648 /* D[0:7] */ 3649 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10), 3650 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12), 3651 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14), 3652 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16), 3653 }; 3654 static const unsigned int sdhi3_data8_mux[] = { 3655 SD3_DAT0_MARK, SD3_DAT1_MARK, 3656 SD3_DAT2_MARK, SD3_DAT3_MARK, 3657 SD3_DAT4_MARK, SD3_DAT5_MARK, 3658 SD3_DAT6_MARK, SD3_DAT7_MARK, 3659 }; 3660 static const unsigned int sdhi3_ctrl_pins[] = { 3661 /* CLK, CMD */ 3662 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8), 3663 }; 3664 static const unsigned int sdhi3_ctrl_mux[] = { 3665 SD3_CLK_MARK, SD3_CMD_MARK, 3666 }; 3667 static const unsigned int sdhi3_cd_pins[] = { 3668 /* CD */ 3669 RCAR_GP_PIN(4, 15), 3670 }; 3671 static const unsigned int sdhi3_cd_mux[] = { 3672 SD3_CD_MARK, 3673 }; 3674 static const unsigned int sdhi3_wp_pins[] = { 3675 /* WP */ 3676 RCAR_GP_PIN(4, 16), 3677 }; 3678 static const unsigned int sdhi3_wp_mux[] = { 3679 SD3_WP_MARK, 3680 }; 3681 static const unsigned int sdhi3_ds_pins[] = { 3682 /* DS */ 3683 RCAR_GP_PIN(4, 17), 3684 }; 3685 static const unsigned int sdhi3_ds_mux[] = { 3686 SD3_DS_MARK, 3687 }; 3688 3689 /* - SSI -------------------------------------------------------------------- */ 3690 static const unsigned int ssi0_data_pins[] = { 3691 /* SDATA */ 3692 RCAR_GP_PIN(6, 2), 3693 }; 3694 static const unsigned int ssi0_data_mux[] = { 3695 SSI_SDATA0_MARK, 3696 }; 3697 static const unsigned int ssi01239_ctrl_pins[] = { 3698 /* SCK, WS */ 3699 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1), 3700 }; 3701 static const unsigned int ssi01239_ctrl_mux[] = { 3702 SSI_SCK01239_MARK, SSI_WS01239_MARK, 3703 }; 3704 static const unsigned int ssi1_data_a_pins[] = { 3705 /* SDATA */ 3706 RCAR_GP_PIN(6, 3), 3707 }; 3708 static const unsigned int ssi1_data_a_mux[] = { 3709 SSI_SDATA1_A_MARK, 3710 }; 3711 static const unsigned int ssi1_data_b_pins[] = { 3712 /* SDATA */ 3713 RCAR_GP_PIN(5, 12), 3714 }; 3715 static const unsigned int ssi1_data_b_mux[] = { 3716 SSI_SDATA1_B_MARK, 3717 }; 3718 static const unsigned int ssi1_ctrl_a_pins[] = { 3719 /* SCK, WS */ 3720 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27), 3721 }; 3722 static const unsigned int ssi1_ctrl_a_mux[] = { 3723 SSI_SCK1_A_MARK, SSI_WS1_A_MARK, 3724 }; 3725 static const unsigned int ssi1_ctrl_b_pins[] = { 3726 /* SCK, WS */ 3727 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21), 3728 }; 3729 static const unsigned int ssi1_ctrl_b_mux[] = { 3730 SSI_SCK1_B_MARK, SSI_WS1_B_MARK, 3731 }; 3732 static const unsigned int ssi2_data_a_pins[] = { 3733 /* SDATA */ 3734 RCAR_GP_PIN(6, 4), 3735 }; 3736 static const unsigned int ssi2_data_a_mux[] = { 3737 SSI_SDATA2_A_MARK, 3738 }; 3739 static const unsigned int ssi2_data_b_pins[] = { 3740 /* SDATA */ 3741 RCAR_GP_PIN(5, 13), 3742 }; 3743 static const unsigned int ssi2_data_b_mux[] = { 3744 SSI_SDATA2_B_MARK, 3745 }; 3746 static const unsigned int ssi2_ctrl_a_pins[] = { 3747 /* SCK, WS */ 3748 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21), 3749 }; 3750 static const unsigned int ssi2_ctrl_a_mux[] = { 3751 SSI_SCK2_A_MARK, SSI_WS2_A_MARK, 3752 }; 3753 static const unsigned int ssi2_ctrl_b_pins[] = { 3754 /* SCK, WS */ 3755 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29), 3756 }; 3757 static const unsigned int ssi2_ctrl_b_mux[] = { 3758 SSI_SCK2_B_MARK, SSI_WS2_B_MARK, 3759 }; 3760 static const unsigned int ssi3_data_pins[] = { 3761 /* SDATA */ 3762 RCAR_GP_PIN(6, 7), 3763 }; 3764 static const unsigned int ssi3_data_mux[] = { 3765 SSI_SDATA3_MARK, 3766 }; 3767 static const unsigned int ssi349_ctrl_pins[] = { 3768 /* SCK, WS */ 3769 RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6), 3770 }; 3771 static const unsigned int ssi349_ctrl_mux[] = { 3772 SSI_SCK349_MARK, SSI_WS349_MARK, 3773 }; 3774 static const unsigned int ssi4_data_pins[] = { 3775 /* SDATA */ 3776 RCAR_GP_PIN(6, 10), 3777 }; 3778 static const unsigned int ssi4_data_mux[] = { 3779 SSI_SDATA4_MARK, 3780 }; 3781 static const unsigned int ssi4_ctrl_pins[] = { 3782 /* SCK, WS */ 3783 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), 3784 }; 3785 static const unsigned int ssi4_ctrl_mux[] = { 3786 SSI_SCK4_MARK, SSI_WS4_MARK, 3787 }; 3788 static const unsigned int ssi5_data_pins[] = { 3789 /* SDATA */ 3790 RCAR_GP_PIN(6, 13), 3791 }; 3792 static const unsigned int ssi5_data_mux[] = { 3793 SSI_SDATA5_MARK, 3794 }; 3795 static const unsigned int ssi5_ctrl_pins[] = { 3796 /* SCK, WS */ 3797 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12), 3798 }; 3799 static const unsigned int ssi5_ctrl_mux[] = { 3800 SSI_SCK5_MARK, SSI_WS5_MARK, 3801 }; 3802 static const unsigned int ssi6_data_pins[] = { 3803 /* SDATA */ 3804 RCAR_GP_PIN(6, 16), 3805 }; 3806 static const unsigned int ssi6_data_mux[] = { 3807 SSI_SDATA6_MARK, 3808 }; 3809 static const unsigned int ssi6_ctrl_pins[] = { 3810 /* SCK, WS */ 3811 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15), 3812 }; 3813 static const unsigned int ssi6_ctrl_mux[] = { 3814 SSI_SCK6_MARK, SSI_WS6_MARK, 3815 }; 3816 static const unsigned int ssi7_data_pins[] = { 3817 /* SDATA */ 3818 RCAR_GP_PIN(6, 19), 3819 }; 3820 static const unsigned int ssi7_data_mux[] = { 3821 SSI_SDATA7_MARK, 3822 }; 3823 static const unsigned int ssi78_ctrl_pins[] = { 3824 /* SCK, WS */ 3825 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18), 3826 }; 3827 static const unsigned int ssi78_ctrl_mux[] = { 3828 SSI_SCK78_MARK, SSI_WS78_MARK, 3829 }; 3830 static const unsigned int ssi8_data_pins[] = { 3831 /* SDATA */ 3832 RCAR_GP_PIN(6, 20), 3833 }; 3834 static const unsigned int ssi8_data_mux[] = { 3835 SSI_SDATA8_MARK, 3836 }; 3837 static const unsigned int ssi9_data_a_pins[] = { 3838 /* SDATA */ 3839 RCAR_GP_PIN(6, 21), 3840 }; 3841 static const unsigned int ssi9_data_a_mux[] = { 3842 SSI_SDATA9_A_MARK, 3843 }; 3844 static const unsigned int ssi9_data_b_pins[] = { 3845 /* SDATA */ 3846 RCAR_GP_PIN(5, 14), 3847 }; 3848 static const unsigned int ssi9_data_b_mux[] = { 3849 SSI_SDATA9_B_MARK, 3850 }; 3851 static const unsigned int ssi9_ctrl_a_pins[] = { 3852 /* SCK, WS */ 3853 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16), 3854 }; 3855 static const unsigned int ssi9_ctrl_a_mux[] = { 3856 SSI_SCK9_A_MARK, SSI_WS9_A_MARK, 3857 }; 3858 static const unsigned int ssi9_ctrl_b_pins[] = { 3859 /* SCK, WS */ 3860 RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31), 3861 }; 3862 static const unsigned int ssi9_ctrl_b_mux[] = { 3863 SSI_SCK9_B_MARK, SSI_WS9_B_MARK, 3864 }; 3865 3866 /* - TMU -------------------------------------------------------------------- */ 3867 static const unsigned int tmu_tclk1_a_pins[] = { 3868 /* TCLK */ 3869 RCAR_GP_PIN(6, 23), 3870 }; 3871 static const unsigned int tmu_tclk1_a_mux[] = { 3872 TCLK1_A_MARK, 3873 }; 3874 static const unsigned int tmu_tclk1_b_pins[] = { 3875 /* TCLK */ 3876 RCAR_GP_PIN(5, 19), 3877 }; 3878 static const unsigned int tmu_tclk1_b_mux[] = { 3879 TCLK1_B_MARK, 3880 }; 3881 static const unsigned int tmu_tclk2_a_pins[] = { 3882 /* TCLK */ 3883 RCAR_GP_PIN(6, 19), 3884 }; 3885 static const unsigned int tmu_tclk2_a_mux[] = { 3886 TCLK2_A_MARK, 3887 }; 3888 static const unsigned int tmu_tclk2_b_pins[] = { 3889 /* TCLK */ 3890 RCAR_GP_PIN(6, 28), 3891 }; 3892 static const unsigned int tmu_tclk2_b_mux[] = { 3893 TCLK2_B_MARK, 3894 }; 3895 3896 /* - TPU ------------------------------------------------------------------- */ 3897 static const unsigned int tpu_to0_pins[] = { 3898 /* TPU0TO0 */ 3899 RCAR_GP_PIN(6, 28), 3900 }; 3901 static const unsigned int tpu_to0_mux[] = { 3902 TPU0TO0_MARK, 3903 }; 3904 static const unsigned int tpu_to1_pins[] = { 3905 /* TPU0TO1 */ 3906 RCAR_GP_PIN(6, 29), 3907 }; 3908 static const unsigned int tpu_to1_mux[] = { 3909 TPU0TO1_MARK, 3910 }; 3911 static const unsigned int tpu_to2_pins[] = { 3912 /* TPU0TO2 */ 3913 RCAR_GP_PIN(6, 30), 3914 }; 3915 static const unsigned int tpu_to2_mux[] = { 3916 TPU0TO2_MARK, 3917 }; 3918 static const unsigned int tpu_to3_pins[] = { 3919 /* TPU0TO3 */ 3920 RCAR_GP_PIN(6, 31), 3921 }; 3922 static const unsigned int tpu_to3_mux[] = { 3923 TPU0TO3_MARK, 3924 }; 3925 3926 /* - USB0 ------------------------------------------------------------------- */ 3927 static const unsigned int usb0_pins[] = { 3928 /* PWEN, OVC */ 3929 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25), 3930 }; 3931 static const unsigned int usb0_mux[] = { 3932 USB0_PWEN_MARK, USB0_OVC_MARK, 3933 }; 3934 /* - USB1 ------------------------------------------------------------------- */ 3935 static const unsigned int usb1_pins[] = { 3936 /* PWEN, OVC */ 3937 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27), 3938 }; 3939 static const unsigned int usb1_mux[] = { 3940 USB1_PWEN_MARK, USB1_OVC_MARK, 3941 }; 3942 /* - USB2 ------------------------------------------------------------------- */ 3943 static const unsigned int usb2_pins[] = { 3944 /* PWEN, OVC */ 3945 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15), 3946 }; 3947 static const unsigned int usb2_mux[] = { 3948 USB2_PWEN_MARK, USB2_OVC_MARK, 3949 }; 3950 /* - USB2_CH3 --------------------------------------------------------------- */ 3951 static const unsigned int usb2_ch3_pins[] = { 3952 /* PWEN, OVC */ 3953 RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31), 3954 }; 3955 static const unsigned int usb2_ch3_mux[] = { 3956 USB2_CH3_PWEN_MARK, USB2_CH3_OVC_MARK, 3957 }; 3958 3959 /* - USB30 ------------------------------------------------------------------ */ 3960 static const unsigned int usb30_pins[] = { 3961 /* PWEN, OVC */ 3962 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29), 3963 }; 3964 static const unsigned int usb30_mux[] = { 3965 USB30_PWEN_MARK, USB30_OVC_MARK, 3966 }; 3967 3968 /* - VIN4 ------------------------------------------------------------------- */ 3969 static const unsigned int vin4_data18_a_pins[] = { 3970 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), 3971 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), 3972 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), 3973 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), 3974 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), 3975 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 3976 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), 3977 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), 3978 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), 3979 }; 3980 static const unsigned int vin4_data18_a_mux[] = { 3981 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK, 3982 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK, 3983 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK, 3984 VI4_DATA10_MARK, VI4_DATA11_MARK, 3985 VI4_DATA12_MARK, VI4_DATA13_MARK, 3986 VI4_DATA14_MARK, VI4_DATA15_MARK, 3987 VI4_DATA18_MARK, VI4_DATA19_MARK, 3988 VI4_DATA20_MARK, VI4_DATA21_MARK, 3989 VI4_DATA22_MARK, VI4_DATA23_MARK, 3990 }; 3991 static const unsigned int vin4_data18_b_pins[] = { 3992 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), 3993 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), 3994 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), 3995 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), 3996 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), 3997 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 3998 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), 3999 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), 4000 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), 4001 }; 4002 static const unsigned int vin4_data18_b_mux[] = { 4003 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK, 4004 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK, 4005 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK, 4006 VI4_DATA10_MARK, VI4_DATA11_MARK, 4007 VI4_DATA12_MARK, VI4_DATA13_MARK, 4008 VI4_DATA14_MARK, VI4_DATA15_MARK, 4009 VI4_DATA18_MARK, VI4_DATA19_MARK, 4010 VI4_DATA20_MARK, VI4_DATA21_MARK, 4011 VI4_DATA22_MARK, VI4_DATA23_MARK, 4012 }; 4013 static const union vin_data vin4_data_a_pins = { 4014 .data24 = { 4015 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), 4016 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), 4017 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), 4018 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), 4019 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), 4020 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), 4021 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), 4022 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 4023 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), 4024 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), 4025 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), 4026 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), 4027 }, 4028 }; 4029 static const union vin_data vin4_data_a_mux = { 4030 .data24 = { 4031 VI4_DATA0_A_MARK, VI4_DATA1_A_MARK, 4032 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK, 4033 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK, 4034 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK, 4035 VI4_DATA8_MARK, VI4_DATA9_MARK, 4036 VI4_DATA10_MARK, VI4_DATA11_MARK, 4037 VI4_DATA12_MARK, VI4_DATA13_MARK, 4038 VI4_DATA14_MARK, VI4_DATA15_MARK, 4039 VI4_DATA16_MARK, VI4_DATA17_MARK, 4040 VI4_DATA18_MARK, VI4_DATA19_MARK, 4041 VI4_DATA20_MARK, VI4_DATA21_MARK, 4042 VI4_DATA22_MARK, VI4_DATA23_MARK, 4043 }, 4044 }; 4045 static const union vin_data vin4_data_b_pins = { 4046 .data24 = { 4047 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), 4048 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), 4049 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), 4050 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), 4051 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), 4052 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), 4053 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), 4054 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 4055 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), 4056 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), 4057 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), 4058 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), 4059 }, 4060 }; 4061 static const union vin_data vin4_data_b_mux = { 4062 .data24 = { 4063 VI4_DATA0_B_MARK, VI4_DATA1_B_MARK, 4064 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK, 4065 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK, 4066 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK, 4067 VI4_DATA8_MARK, VI4_DATA9_MARK, 4068 VI4_DATA10_MARK, VI4_DATA11_MARK, 4069 VI4_DATA12_MARK, VI4_DATA13_MARK, 4070 VI4_DATA14_MARK, VI4_DATA15_MARK, 4071 VI4_DATA16_MARK, VI4_DATA17_MARK, 4072 VI4_DATA18_MARK, VI4_DATA19_MARK, 4073 VI4_DATA20_MARK, VI4_DATA21_MARK, 4074 VI4_DATA22_MARK, VI4_DATA23_MARK, 4075 }, 4076 }; 4077 static const unsigned int vin4_sync_pins[] = { 4078 /* HSYNC#, VSYNC# */ 4079 RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 17), 4080 }; 4081 static const unsigned int vin4_sync_mux[] = { 4082 VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK, 4083 }; 4084 static const unsigned int vin4_field_pins[] = { 4085 /* FIELD */ 4086 RCAR_GP_PIN(1, 16), 4087 }; 4088 static const unsigned int vin4_field_mux[] = { 4089 VI4_FIELD_MARK, 4090 }; 4091 static const unsigned int vin4_clkenb_pins[] = { 4092 /* CLKENB */ 4093 RCAR_GP_PIN(1, 19), 4094 }; 4095 static const unsigned int vin4_clkenb_mux[] = { 4096 VI4_CLKENB_MARK, 4097 }; 4098 static const unsigned int vin4_clk_pins[] = { 4099 /* CLK */ 4100 RCAR_GP_PIN(1, 27), 4101 }; 4102 static const unsigned int vin4_clk_mux[] = { 4103 VI4_CLK_MARK, 4104 }; 4105 4106 /* - VIN5 ------------------------------------------------------------------- */ 4107 static const union vin_data16 vin5_data_pins = { 4108 .data16 = { 4109 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), 4110 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), 4111 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), 4112 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), 4113 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), 4114 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), 4115 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), 4116 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 4117 }, 4118 }; 4119 static const union vin_data16 vin5_data_mux = { 4120 .data16 = { 4121 VI5_DATA0_MARK, VI5_DATA1_MARK, 4122 VI5_DATA2_MARK, VI5_DATA3_MARK, 4123 VI5_DATA4_MARK, VI5_DATA5_MARK, 4124 VI5_DATA6_MARK, VI5_DATA7_MARK, 4125 VI5_DATA8_MARK, VI5_DATA9_MARK, 4126 VI5_DATA10_MARK, VI5_DATA11_MARK, 4127 VI5_DATA12_MARK, VI5_DATA13_MARK, 4128 VI5_DATA14_MARK, VI5_DATA15_MARK, 4129 }, 4130 }; 4131 static const unsigned int vin5_sync_pins[] = { 4132 /* HSYNC#, VSYNC# */ 4133 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9), 4134 }; 4135 static const unsigned int vin5_sync_mux[] = { 4136 VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK, 4137 }; 4138 static const unsigned int vin5_field_pins[] = { 4139 RCAR_GP_PIN(1, 11), 4140 }; 4141 static const unsigned int vin5_field_mux[] = { 4142 /* FIELD */ 4143 VI5_FIELD_MARK, 4144 }; 4145 static const unsigned int vin5_clkenb_pins[] = { 4146 RCAR_GP_PIN(1, 20), 4147 }; 4148 static const unsigned int vin5_clkenb_mux[] = { 4149 /* CLKENB */ 4150 VI5_CLKENB_MARK, 4151 }; 4152 static const unsigned int vin5_clk_pins[] = { 4153 RCAR_GP_PIN(1, 21), 4154 }; 4155 static const unsigned int vin5_clk_mux[] = { 4156 /* CLK */ 4157 VI5_CLK_MARK, 4158 }; 4159 4160 static const struct { 4161 struct sh_pfc_pin_group common[320]; 4162 struct sh_pfc_pin_group automotive[30]; 4163 } pinmux_groups = { 4164 .common = { 4165 SH_PFC_PIN_GROUP(audio_clk_a_a), 4166 SH_PFC_PIN_GROUP(audio_clk_a_b), 4167 SH_PFC_PIN_GROUP(audio_clk_a_c), 4168 SH_PFC_PIN_GROUP(audio_clk_b_a), 4169 SH_PFC_PIN_GROUP(audio_clk_b_b), 4170 SH_PFC_PIN_GROUP(audio_clk_c_a), 4171 SH_PFC_PIN_GROUP(audio_clk_c_b), 4172 SH_PFC_PIN_GROUP(audio_clkout_a), 4173 SH_PFC_PIN_GROUP(audio_clkout_b), 4174 SH_PFC_PIN_GROUP(audio_clkout_c), 4175 SH_PFC_PIN_GROUP(audio_clkout_d), 4176 SH_PFC_PIN_GROUP(audio_clkout1_a), 4177 SH_PFC_PIN_GROUP(audio_clkout1_b), 4178 SH_PFC_PIN_GROUP(audio_clkout2_a), 4179 SH_PFC_PIN_GROUP(audio_clkout2_b), 4180 SH_PFC_PIN_GROUP(audio_clkout3_a), 4181 SH_PFC_PIN_GROUP(audio_clkout3_b), 4182 SH_PFC_PIN_GROUP(avb_link), 4183 SH_PFC_PIN_GROUP(avb_magic), 4184 SH_PFC_PIN_GROUP(avb_phy_int), 4185 SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio), /* Deprecated */ 4186 SH_PFC_PIN_GROUP(avb_mdio), 4187 SH_PFC_PIN_GROUP(avb_mii), 4188 SH_PFC_PIN_GROUP(avb_avtp_pps), 4189 SH_PFC_PIN_GROUP(avb_avtp_match_a), 4190 SH_PFC_PIN_GROUP(avb_avtp_capture_a), 4191 SH_PFC_PIN_GROUP(avb_avtp_match_b), 4192 SH_PFC_PIN_GROUP(avb_avtp_capture_b), 4193 SH_PFC_PIN_GROUP(can0_data_a), 4194 SH_PFC_PIN_GROUP(can0_data_b), 4195 SH_PFC_PIN_GROUP(can1_data), 4196 SH_PFC_PIN_GROUP(can_clk), 4197 SH_PFC_PIN_GROUP(canfd0_data_a), 4198 SH_PFC_PIN_GROUP(canfd0_data_b), 4199 SH_PFC_PIN_GROUP(canfd1_data), 4200 SH_PFC_PIN_GROUP(du_rgb666), 4201 SH_PFC_PIN_GROUP(du_rgb888), 4202 SH_PFC_PIN_GROUP(du_clk_out_0), 4203 SH_PFC_PIN_GROUP(du_clk_out_1), 4204 SH_PFC_PIN_GROUP(du_sync), 4205 SH_PFC_PIN_GROUP(du_oddf), 4206 SH_PFC_PIN_GROUP(du_cde), 4207 SH_PFC_PIN_GROUP(du_disp), 4208 SH_PFC_PIN_GROUP(hscif0_data), 4209 SH_PFC_PIN_GROUP(hscif0_clk), 4210 SH_PFC_PIN_GROUP(hscif0_ctrl), 4211 SH_PFC_PIN_GROUP(hscif1_data_a), 4212 SH_PFC_PIN_GROUP(hscif1_clk_a), 4213 SH_PFC_PIN_GROUP(hscif1_ctrl_a), 4214 SH_PFC_PIN_GROUP(hscif1_data_b), 4215 SH_PFC_PIN_GROUP(hscif1_clk_b), 4216 SH_PFC_PIN_GROUP(hscif1_ctrl_b), 4217 SH_PFC_PIN_GROUP(hscif2_data_a), 4218 SH_PFC_PIN_GROUP(hscif2_clk_a), 4219 SH_PFC_PIN_GROUP(hscif2_ctrl_a), 4220 SH_PFC_PIN_GROUP(hscif2_data_b), 4221 SH_PFC_PIN_GROUP(hscif2_clk_b), 4222 SH_PFC_PIN_GROUP(hscif2_ctrl_b), 4223 SH_PFC_PIN_GROUP(hscif2_data_c), 4224 SH_PFC_PIN_GROUP(hscif2_clk_c), 4225 SH_PFC_PIN_GROUP(hscif2_ctrl_c), 4226 SH_PFC_PIN_GROUP(hscif3_data_a), 4227 SH_PFC_PIN_GROUP(hscif3_clk), 4228 SH_PFC_PIN_GROUP(hscif3_ctrl), 4229 SH_PFC_PIN_GROUP(hscif3_data_b), 4230 SH_PFC_PIN_GROUP(hscif3_data_c), 4231 SH_PFC_PIN_GROUP(hscif3_data_d), 4232 SH_PFC_PIN_GROUP(hscif4_data_a), 4233 SH_PFC_PIN_GROUP(hscif4_clk), 4234 SH_PFC_PIN_GROUP(hscif4_ctrl), 4235 SH_PFC_PIN_GROUP(hscif4_data_b), 4236 SH_PFC_PIN_GROUP(i2c0), 4237 SH_PFC_PIN_GROUP(i2c1_a), 4238 SH_PFC_PIN_GROUP(i2c1_b), 4239 SH_PFC_PIN_GROUP(i2c2_a), 4240 SH_PFC_PIN_GROUP(i2c2_b), 4241 SH_PFC_PIN_GROUP(i2c3), 4242 SH_PFC_PIN_GROUP(i2c5), 4243 SH_PFC_PIN_GROUP(i2c6_a), 4244 SH_PFC_PIN_GROUP(i2c6_b), 4245 SH_PFC_PIN_GROUP(i2c6_c), 4246 SH_PFC_PIN_GROUP(intc_ex_irq0), 4247 SH_PFC_PIN_GROUP(intc_ex_irq1), 4248 SH_PFC_PIN_GROUP(intc_ex_irq2), 4249 SH_PFC_PIN_GROUP(intc_ex_irq3), 4250 SH_PFC_PIN_GROUP(intc_ex_irq4), 4251 SH_PFC_PIN_GROUP(intc_ex_irq5), 4252 SH_PFC_PIN_GROUP(msiof0_clk), 4253 SH_PFC_PIN_GROUP(msiof0_sync), 4254 SH_PFC_PIN_GROUP(msiof0_ss1), 4255 SH_PFC_PIN_GROUP(msiof0_ss2), 4256 SH_PFC_PIN_GROUP(msiof0_txd), 4257 SH_PFC_PIN_GROUP(msiof0_rxd), 4258 SH_PFC_PIN_GROUP(msiof1_clk_a), 4259 SH_PFC_PIN_GROUP(msiof1_sync_a), 4260 SH_PFC_PIN_GROUP(msiof1_ss1_a), 4261 SH_PFC_PIN_GROUP(msiof1_ss2_a), 4262 SH_PFC_PIN_GROUP(msiof1_txd_a), 4263 SH_PFC_PIN_GROUP(msiof1_rxd_a), 4264 SH_PFC_PIN_GROUP(msiof1_clk_b), 4265 SH_PFC_PIN_GROUP(msiof1_sync_b), 4266 SH_PFC_PIN_GROUP(msiof1_ss1_b), 4267 SH_PFC_PIN_GROUP(msiof1_ss2_b), 4268 SH_PFC_PIN_GROUP(msiof1_txd_b), 4269 SH_PFC_PIN_GROUP(msiof1_rxd_b), 4270 SH_PFC_PIN_GROUP(msiof1_clk_c), 4271 SH_PFC_PIN_GROUP(msiof1_sync_c), 4272 SH_PFC_PIN_GROUP(msiof1_ss1_c), 4273 SH_PFC_PIN_GROUP(msiof1_ss2_c), 4274 SH_PFC_PIN_GROUP(msiof1_txd_c), 4275 SH_PFC_PIN_GROUP(msiof1_rxd_c), 4276 SH_PFC_PIN_GROUP(msiof1_clk_d), 4277 SH_PFC_PIN_GROUP(msiof1_sync_d), 4278 SH_PFC_PIN_GROUP(msiof1_ss1_d), 4279 SH_PFC_PIN_GROUP(msiof1_ss2_d), 4280 SH_PFC_PIN_GROUP(msiof1_txd_d), 4281 SH_PFC_PIN_GROUP(msiof1_rxd_d), 4282 SH_PFC_PIN_GROUP(msiof1_clk_e), 4283 SH_PFC_PIN_GROUP(msiof1_sync_e), 4284 SH_PFC_PIN_GROUP(msiof1_ss1_e), 4285 SH_PFC_PIN_GROUP(msiof1_ss2_e), 4286 SH_PFC_PIN_GROUP(msiof1_txd_e), 4287 SH_PFC_PIN_GROUP(msiof1_rxd_e), 4288 SH_PFC_PIN_GROUP(msiof1_clk_f), 4289 SH_PFC_PIN_GROUP(msiof1_sync_f), 4290 SH_PFC_PIN_GROUP(msiof1_ss1_f), 4291 SH_PFC_PIN_GROUP(msiof1_ss2_f), 4292 SH_PFC_PIN_GROUP(msiof1_txd_f), 4293 SH_PFC_PIN_GROUP(msiof1_rxd_f), 4294 SH_PFC_PIN_GROUP(msiof1_clk_g), 4295 SH_PFC_PIN_GROUP(msiof1_sync_g), 4296 SH_PFC_PIN_GROUP(msiof1_ss1_g), 4297 SH_PFC_PIN_GROUP(msiof1_ss2_g), 4298 SH_PFC_PIN_GROUP(msiof1_txd_g), 4299 SH_PFC_PIN_GROUP(msiof1_rxd_g), 4300 SH_PFC_PIN_GROUP(msiof2_clk_a), 4301 SH_PFC_PIN_GROUP(msiof2_sync_a), 4302 SH_PFC_PIN_GROUP(msiof2_ss1_a), 4303 SH_PFC_PIN_GROUP(msiof2_ss2_a), 4304 SH_PFC_PIN_GROUP(msiof2_txd_a), 4305 SH_PFC_PIN_GROUP(msiof2_rxd_a), 4306 SH_PFC_PIN_GROUP(msiof2_clk_b), 4307 SH_PFC_PIN_GROUP(msiof2_sync_b), 4308 SH_PFC_PIN_GROUP(msiof2_ss1_b), 4309 SH_PFC_PIN_GROUP(msiof2_ss2_b), 4310 SH_PFC_PIN_GROUP(msiof2_txd_b), 4311 SH_PFC_PIN_GROUP(msiof2_rxd_b), 4312 SH_PFC_PIN_GROUP(msiof2_clk_c), 4313 SH_PFC_PIN_GROUP(msiof2_sync_c), 4314 SH_PFC_PIN_GROUP(msiof2_ss1_c), 4315 SH_PFC_PIN_GROUP(msiof2_ss2_c), 4316 SH_PFC_PIN_GROUP(msiof2_txd_c), 4317 SH_PFC_PIN_GROUP(msiof2_rxd_c), 4318 SH_PFC_PIN_GROUP(msiof2_clk_d), 4319 SH_PFC_PIN_GROUP(msiof2_sync_d), 4320 SH_PFC_PIN_GROUP(msiof2_ss1_d), 4321 SH_PFC_PIN_GROUP(msiof2_ss2_d), 4322 SH_PFC_PIN_GROUP(msiof2_txd_d), 4323 SH_PFC_PIN_GROUP(msiof2_rxd_d), 4324 SH_PFC_PIN_GROUP(msiof3_clk_a), 4325 SH_PFC_PIN_GROUP(msiof3_sync_a), 4326 SH_PFC_PIN_GROUP(msiof3_ss1_a), 4327 SH_PFC_PIN_GROUP(msiof3_ss2_a), 4328 SH_PFC_PIN_GROUP(msiof3_txd_a), 4329 SH_PFC_PIN_GROUP(msiof3_rxd_a), 4330 SH_PFC_PIN_GROUP(msiof3_clk_b), 4331 SH_PFC_PIN_GROUP(msiof3_sync_b), 4332 SH_PFC_PIN_GROUP(msiof3_ss1_b), 4333 SH_PFC_PIN_GROUP(msiof3_ss2_b), 4334 SH_PFC_PIN_GROUP(msiof3_txd_b), 4335 SH_PFC_PIN_GROUP(msiof3_rxd_b), 4336 SH_PFC_PIN_GROUP(msiof3_clk_c), 4337 SH_PFC_PIN_GROUP(msiof3_sync_c), 4338 SH_PFC_PIN_GROUP(msiof3_txd_c), 4339 SH_PFC_PIN_GROUP(msiof3_rxd_c), 4340 SH_PFC_PIN_GROUP(msiof3_clk_d), 4341 SH_PFC_PIN_GROUP(msiof3_sync_d), 4342 SH_PFC_PIN_GROUP(msiof3_ss1_d), 4343 SH_PFC_PIN_GROUP(msiof3_txd_d), 4344 SH_PFC_PIN_GROUP(msiof3_rxd_d), 4345 SH_PFC_PIN_GROUP(msiof3_clk_e), 4346 SH_PFC_PIN_GROUP(msiof3_sync_e), 4347 SH_PFC_PIN_GROUP(msiof3_ss1_e), 4348 SH_PFC_PIN_GROUP(msiof3_ss2_e), 4349 SH_PFC_PIN_GROUP(msiof3_txd_e), 4350 SH_PFC_PIN_GROUP(msiof3_rxd_e), 4351 SH_PFC_PIN_GROUP(pwm0), 4352 SH_PFC_PIN_GROUP(pwm1_a), 4353 SH_PFC_PIN_GROUP(pwm1_b), 4354 SH_PFC_PIN_GROUP(pwm2_a), 4355 SH_PFC_PIN_GROUP(pwm2_b), 4356 SH_PFC_PIN_GROUP(pwm3_a), 4357 SH_PFC_PIN_GROUP(pwm3_b), 4358 SH_PFC_PIN_GROUP(pwm4_a), 4359 SH_PFC_PIN_GROUP(pwm4_b), 4360 SH_PFC_PIN_GROUP(pwm5_a), 4361 SH_PFC_PIN_GROUP(pwm5_b), 4362 SH_PFC_PIN_GROUP(pwm6_a), 4363 SH_PFC_PIN_GROUP(pwm6_b), 4364 SH_PFC_PIN_GROUP(sata0_devslp_a), 4365 SH_PFC_PIN_GROUP(sata0_devslp_b), 4366 SH_PFC_PIN_GROUP(scif0_data), 4367 SH_PFC_PIN_GROUP(scif0_clk), 4368 SH_PFC_PIN_GROUP(scif0_ctrl), 4369 SH_PFC_PIN_GROUP(scif1_data_a), 4370 SH_PFC_PIN_GROUP(scif1_clk), 4371 SH_PFC_PIN_GROUP(scif1_ctrl), 4372 SH_PFC_PIN_GROUP(scif1_data_b), 4373 SH_PFC_PIN_GROUP(scif2_data_a), 4374 SH_PFC_PIN_GROUP(scif2_clk), 4375 SH_PFC_PIN_GROUP(scif2_data_b), 4376 SH_PFC_PIN_GROUP(scif3_data_a), 4377 SH_PFC_PIN_GROUP(scif3_clk), 4378 SH_PFC_PIN_GROUP(scif3_ctrl), 4379 SH_PFC_PIN_GROUP(scif3_data_b), 4380 SH_PFC_PIN_GROUP(scif4_data_a), 4381 SH_PFC_PIN_GROUP(scif4_clk_a), 4382 SH_PFC_PIN_GROUP(scif4_ctrl_a), 4383 SH_PFC_PIN_GROUP(scif4_data_b), 4384 SH_PFC_PIN_GROUP(scif4_clk_b), 4385 SH_PFC_PIN_GROUP(scif4_ctrl_b), 4386 SH_PFC_PIN_GROUP(scif4_data_c), 4387 SH_PFC_PIN_GROUP(scif4_clk_c), 4388 SH_PFC_PIN_GROUP(scif4_ctrl_c), 4389 SH_PFC_PIN_GROUP(scif5_data_a), 4390 SH_PFC_PIN_GROUP(scif5_clk_a), 4391 SH_PFC_PIN_GROUP(scif5_data_b), 4392 SH_PFC_PIN_GROUP(scif5_clk_b), 4393 SH_PFC_PIN_GROUP(scif_clk_a), 4394 SH_PFC_PIN_GROUP(scif_clk_b), 4395 SH_PFC_PIN_GROUP(sdhi0_data1), 4396 SH_PFC_PIN_GROUP(sdhi0_data4), 4397 SH_PFC_PIN_GROUP(sdhi0_ctrl), 4398 SH_PFC_PIN_GROUP(sdhi0_cd), 4399 SH_PFC_PIN_GROUP(sdhi0_wp), 4400 SH_PFC_PIN_GROUP(sdhi1_data1), 4401 SH_PFC_PIN_GROUP(sdhi1_data4), 4402 SH_PFC_PIN_GROUP(sdhi1_ctrl), 4403 SH_PFC_PIN_GROUP(sdhi1_cd), 4404 SH_PFC_PIN_GROUP(sdhi1_wp), 4405 SH_PFC_PIN_GROUP(sdhi2_data1), 4406 SH_PFC_PIN_GROUP(sdhi2_data4), 4407 SH_PFC_PIN_GROUP(sdhi2_data8), 4408 SH_PFC_PIN_GROUP(sdhi2_ctrl), 4409 SH_PFC_PIN_GROUP(sdhi2_cd_a), 4410 SH_PFC_PIN_GROUP(sdhi2_wp_a), 4411 SH_PFC_PIN_GROUP(sdhi2_cd_b), 4412 SH_PFC_PIN_GROUP(sdhi2_wp_b), 4413 SH_PFC_PIN_GROUP(sdhi2_ds), 4414 SH_PFC_PIN_GROUP(sdhi3_data1), 4415 SH_PFC_PIN_GROUP(sdhi3_data4), 4416 SH_PFC_PIN_GROUP(sdhi3_data8), 4417 SH_PFC_PIN_GROUP(sdhi3_ctrl), 4418 SH_PFC_PIN_GROUP(sdhi3_cd), 4419 SH_PFC_PIN_GROUP(sdhi3_wp), 4420 SH_PFC_PIN_GROUP(sdhi3_ds), 4421 SH_PFC_PIN_GROUP(ssi0_data), 4422 SH_PFC_PIN_GROUP(ssi01239_ctrl), 4423 SH_PFC_PIN_GROUP(ssi1_data_a), 4424 SH_PFC_PIN_GROUP(ssi1_data_b), 4425 SH_PFC_PIN_GROUP(ssi1_ctrl_a), 4426 SH_PFC_PIN_GROUP(ssi1_ctrl_b), 4427 SH_PFC_PIN_GROUP(ssi2_data_a), 4428 SH_PFC_PIN_GROUP(ssi2_data_b), 4429 SH_PFC_PIN_GROUP(ssi2_ctrl_a), 4430 SH_PFC_PIN_GROUP(ssi2_ctrl_b), 4431 SH_PFC_PIN_GROUP(ssi3_data), 4432 SH_PFC_PIN_GROUP(ssi349_ctrl), 4433 SH_PFC_PIN_GROUP(ssi4_data), 4434 SH_PFC_PIN_GROUP(ssi4_ctrl), 4435 SH_PFC_PIN_GROUP(ssi5_data), 4436 SH_PFC_PIN_GROUP(ssi5_ctrl), 4437 SH_PFC_PIN_GROUP(ssi6_data), 4438 SH_PFC_PIN_GROUP(ssi6_ctrl), 4439 SH_PFC_PIN_GROUP(ssi7_data), 4440 SH_PFC_PIN_GROUP(ssi78_ctrl), 4441 SH_PFC_PIN_GROUP(ssi8_data), 4442 SH_PFC_PIN_GROUP(ssi9_data_a), 4443 SH_PFC_PIN_GROUP(ssi9_data_b), 4444 SH_PFC_PIN_GROUP(ssi9_ctrl_a), 4445 SH_PFC_PIN_GROUP(ssi9_ctrl_b), 4446 SH_PFC_PIN_GROUP(tmu_tclk1_a), 4447 SH_PFC_PIN_GROUP(tmu_tclk1_b), 4448 SH_PFC_PIN_GROUP(tmu_tclk2_a), 4449 SH_PFC_PIN_GROUP(tmu_tclk2_b), 4450 SH_PFC_PIN_GROUP(tpu_to0), 4451 SH_PFC_PIN_GROUP(tpu_to1), 4452 SH_PFC_PIN_GROUP(tpu_to2), 4453 SH_PFC_PIN_GROUP(tpu_to3), 4454 SH_PFC_PIN_GROUP(usb0), 4455 SH_PFC_PIN_GROUP(usb1), 4456 SH_PFC_PIN_GROUP(usb2), 4457 SH_PFC_PIN_GROUP(usb2_ch3), 4458 SH_PFC_PIN_GROUP(usb30), 4459 VIN_DATA_PIN_GROUP(vin4_data, 8, _a), 4460 VIN_DATA_PIN_GROUP(vin4_data, 10, _a), 4461 VIN_DATA_PIN_GROUP(vin4_data, 12, _a), 4462 VIN_DATA_PIN_GROUP(vin4_data, 16, _a), 4463 SH_PFC_PIN_GROUP(vin4_data18_a), 4464 VIN_DATA_PIN_GROUP(vin4_data, 20, _a), 4465 VIN_DATA_PIN_GROUP(vin4_data, 24, _a), 4466 VIN_DATA_PIN_GROUP(vin4_data, 8, _b), 4467 VIN_DATA_PIN_GROUP(vin4_data, 10, _b), 4468 VIN_DATA_PIN_GROUP(vin4_data, 12, _b), 4469 VIN_DATA_PIN_GROUP(vin4_data, 16, _b), 4470 SH_PFC_PIN_GROUP(vin4_data18_b), 4471 VIN_DATA_PIN_GROUP(vin4_data, 20, _b), 4472 VIN_DATA_PIN_GROUP(vin4_data, 24, _b), 4473 SH_PFC_PIN_GROUP(vin4_sync), 4474 SH_PFC_PIN_GROUP(vin4_field), 4475 SH_PFC_PIN_GROUP(vin4_clkenb), 4476 SH_PFC_PIN_GROUP(vin4_clk), 4477 VIN_DATA_PIN_GROUP(vin5_data, 8), 4478 VIN_DATA_PIN_GROUP(vin5_data, 10), 4479 VIN_DATA_PIN_GROUP(vin5_data, 12), 4480 VIN_DATA_PIN_GROUP(vin5_data, 16), 4481 SH_PFC_PIN_GROUP(vin5_sync), 4482 SH_PFC_PIN_GROUP(vin5_field), 4483 SH_PFC_PIN_GROUP(vin5_clkenb), 4484 SH_PFC_PIN_GROUP(vin5_clk), 4485 }, 4486 .automotive = { 4487 SH_PFC_PIN_GROUP(drif0_ctrl_a), 4488 SH_PFC_PIN_GROUP(drif0_data0_a), 4489 SH_PFC_PIN_GROUP(drif0_data1_a), 4490 SH_PFC_PIN_GROUP(drif0_ctrl_b), 4491 SH_PFC_PIN_GROUP(drif0_data0_b), 4492 SH_PFC_PIN_GROUP(drif0_data1_b), 4493 SH_PFC_PIN_GROUP(drif0_ctrl_c), 4494 SH_PFC_PIN_GROUP(drif0_data0_c), 4495 SH_PFC_PIN_GROUP(drif0_data1_c), 4496 SH_PFC_PIN_GROUP(drif1_ctrl_a), 4497 SH_PFC_PIN_GROUP(drif1_data0_a), 4498 SH_PFC_PIN_GROUP(drif1_data1_a), 4499 SH_PFC_PIN_GROUP(drif1_ctrl_b), 4500 SH_PFC_PIN_GROUP(drif1_data0_b), 4501 SH_PFC_PIN_GROUP(drif1_data1_b), 4502 SH_PFC_PIN_GROUP(drif1_ctrl_c), 4503 SH_PFC_PIN_GROUP(drif1_data0_c), 4504 SH_PFC_PIN_GROUP(drif1_data1_c), 4505 SH_PFC_PIN_GROUP(drif2_ctrl_a), 4506 SH_PFC_PIN_GROUP(drif2_data0_a), 4507 SH_PFC_PIN_GROUP(drif2_data1_a), 4508 SH_PFC_PIN_GROUP(drif2_ctrl_b), 4509 SH_PFC_PIN_GROUP(drif2_data0_b), 4510 SH_PFC_PIN_GROUP(drif2_data1_b), 4511 SH_PFC_PIN_GROUP(drif3_ctrl_a), 4512 SH_PFC_PIN_GROUP(drif3_data0_a), 4513 SH_PFC_PIN_GROUP(drif3_data1_a), 4514 SH_PFC_PIN_GROUP(drif3_ctrl_b), 4515 SH_PFC_PIN_GROUP(drif3_data0_b), 4516 SH_PFC_PIN_GROUP(drif3_data1_b), 4517 } 4518 4519 }; 4520 4521 static const char * const audio_clk_groups[] = { 4522 "audio_clk_a_a", 4523 "audio_clk_a_b", 4524 "audio_clk_a_c", 4525 "audio_clk_b_a", 4526 "audio_clk_b_b", 4527 "audio_clk_c_a", 4528 "audio_clk_c_b", 4529 "audio_clkout_a", 4530 "audio_clkout_b", 4531 "audio_clkout_c", 4532 "audio_clkout_d", 4533 "audio_clkout1_a", 4534 "audio_clkout1_b", 4535 "audio_clkout2_a", 4536 "audio_clkout2_b", 4537 "audio_clkout3_a", 4538 "audio_clkout3_b", 4539 }; 4540 4541 static const char * const avb_groups[] = { 4542 "avb_link", 4543 "avb_magic", 4544 "avb_phy_int", 4545 "avb_mdc", /* Deprecated, please use "avb_mdio" instead */ 4546 "avb_mdio", 4547 "avb_mii", 4548 "avb_avtp_pps", 4549 "avb_avtp_match_a", 4550 "avb_avtp_capture_a", 4551 "avb_avtp_match_b", 4552 "avb_avtp_capture_b", 4553 }; 4554 4555 static const char * const can0_groups[] = { 4556 "can0_data_a", 4557 "can0_data_b", 4558 }; 4559 4560 static const char * const can1_groups[] = { 4561 "can1_data", 4562 }; 4563 4564 static const char * const can_clk_groups[] = { 4565 "can_clk", 4566 }; 4567 4568 static const char * const canfd0_groups[] = { 4569 "canfd0_data_a", 4570 "canfd0_data_b", 4571 }; 4572 4573 static const char * const canfd1_groups[] = { 4574 "canfd1_data", 4575 }; 4576 4577 static const char * const drif0_groups[] = { 4578 "drif0_ctrl_a", 4579 "drif0_data0_a", 4580 "drif0_data1_a", 4581 "drif0_ctrl_b", 4582 "drif0_data0_b", 4583 "drif0_data1_b", 4584 "drif0_ctrl_c", 4585 "drif0_data0_c", 4586 "drif0_data1_c", 4587 }; 4588 4589 static const char * const drif1_groups[] = { 4590 "drif1_ctrl_a", 4591 "drif1_data0_a", 4592 "drif1_data1_a", 4593 "drif1_ctrl_b", 4594 "drif1_data0_b", 4595 "drif1_data1_b", 4596 "drif1_ctrl_c", 4597 "drif1_data0_c", 4598 "drif1_data1_c", 4599 }; 4600 4601 static const char * const drif2_groups[] = { 4602 "drif2_ctrl_a", 4603 "drif2_data0_a", 4604 "drif2_data1_a", 4605 "drif2_ctrl_b", 4606 "drif2_data0_b", 4607 "drif2_data1_b", 4608 }; 4609 4610 static const char * const drif3_groups[] = { 4611 "drif3_ctrl_a", 4612 "drif3_data0_a", 4613 "drif3_data1_a", 4614 "drif3_ctrl_b", 4615 "drif3_data0_b", 4616 "drif3_data1_b", 4617 }; 4618 4619 static const char * const du_groups[] = { 4620 "du_rgb666", 4621 "du_rgb888", 4622 "du_clk_out_0", 4623 "du_clk_out_1", 4624 "du_sync", 4625 "du_oddf", 4626 "du_cde", 4627 "du_disp", 4628 }; 4629 4630 static const char * const hscif0_groups[] = { 4631 "hscif0_data", 4632 "hscif0_clk", 4633 "hscif0_ctrl", 4634 }; 4635 4636 static const char * const hscif1_groups[] = { 4637 "hscif1_data_a", 4638 "hscif1_clk_a", 4639 "hscif1_ctrl_a", 4640 "hscif1_data_b", 4641 "hscif1_clk_b", 4642 "hscif1_ctrl_b", 4643 }; 4644 4645 static const char * const hscif2_groups[] = { 4646 "hscif2_data_a", 4647 "hscif2_clk_a", 4648 "hscif2_ctrl_a", 4649 "hscif2_data_b", 4650 "hscif2_clk_b", 4651 "hscif2_ctrl_b", 4652 "hscif2_data_c", 4653 "hscif2_clk_c", 4654 "hscif2_ctrl_c", 4655 }; 4656 4657 static const char * const hscif3_groups[] = { 4658 "hscif3_data_a", 4659 "hscif3_clk", 4660 "hscif3_ctrl", 4661 "hscif3_data_b", 4662 "hscif3_data_c", 4663 "hscif3_data_d", 4664 }; 4665 4666 static const char * const hscif4_groups[] = { 4667 "hscif4_data_a", 4668 "hscif4_clk", 4669 "hscif4_ctrl", 4670 "hscif4_data_b", 4671 }; 4672 4673 static const char * const i2c0_groups[] = { 4674 "i2c0", 4675 }; 4676 4677 static const char * const i2c1_groups[] = { 4678 "i2c1_a", 4679 "i2c1_b", 4680 }; 4681 4682 static const char * const i2c2_groups[] = { 4683 "i2c2_a", 4684 "i2c2_b", 4685 }; 4686 4687 static const char * const i2c3_groups[] = { 4688 "i2c3", 4689 }; 4690 4691 static const char * const i2c5_groups[] = { 4692 "i2c5", 4693 }; 4694 4695 static const char * const i2c6_groups[] = { 4696 "i2c6_a", 4697 "i2c6_b", 4698 "i2c6_c", 4699 }; 4700 4701 static const char * const intc_ex_groups[] = { 4702 "intc_ex_irq0", 4703 "intc_ex_irq1", 4704 "intc_ex_irq2", 4705 "intc_ex_irq3", 4706 "intc_ex_irq4", 4707 "intc_ex_irq5", 4708 }; 4709 4710 static const char * const msiof0_groups[] = { 4711 "msiof0_clk", 4712 "msiof0_sync", 4713 "msiof0_ss1", 4714 "msiof0_ss2", 4715 "msiof0_txd", 4716 "msiof0_rxd", 4717 }; 4718 4719 static const char * const msiof1_groups[] = { 4720 "msiof1_clk_a", 4721 "msiof1_sync_a", 4722 "msiof1_ss1_a", 4723 "msiof1_ss2_a", 4724 "msiof1_txd_a", 4725 "msiof1_rxd_a", 4726 "msiof1_clk_b", 4727 "msiof1_sync_b", 4728 "msiof1_ss1_b", 4729 "msiof1_ss2_b", 4730 "msiof1_txd_b", 4731 "msiof1_rxd_b", 4732 "msiof1_clk_c", 4733 "msiof1_sync_c", 4734 "msiof1_ss1_c", 4735 "msiof1_ss2_c", 4736 "msiof1_txd_c", 4737 "msiof1_rxd_c", 4738 "msiof1_clk_d", 4739 "msiof1_sync_d", 4740 "msiof1_ss1_d", 4741 "msiof1_ss2_d", 4742 "msiof1_txd_d", 4743 "msiof1_rxd_d", 4744 "msiof1_clk_e", 4745 "msiof1_sync_e", 4746 "msiof1_ss1_e", 4747 "msiof1_ss2_e", 4748 "msiof1_txd_e", 4749 "msiof1_rxd_e", 4750 "msiof1_clk_f", 4751 "msiof1_sync_f", 4752 "msiof1_ss1_f", 4753 "msiof1_ss2_f", 4754 "msiof1_txd_f", 4755 "msiof1_rxd_f", 4756 "msiof1_clk_g", 4757 "msiof1_sync_g", 4758 "msiof1_ss1_g", 4759 "msiof1_ss2_g", 4760 "msiof1_txd_g", 4761 "msiof1_rxd_g", 4762 }; 4763 4764 static const char * const msiof2_groups[] = { 4765 "msiof2_clk_a", 4766 "msiof2_sync_a", 4767 "msiof2_ss1_a", 4768 "msiof2_ss2_a", 4769 "msiof2_txd_a", 4770 "msiof2_rxd_a", 4771 "msiof2_clk_b", 4772 "msiof2_sync_b", 4773 "msiof2_ss1_b", 4774 "msiof2_ss2_b", 4775 "msiof2_txd_b", 4776 "msiof2_rxd_b", 4777 "msiof2_clk_c", 4778 "msiof2_sync_c", 4779 "msiof2_ss1_c", 4780 "msiof2_ss2_c", 4781 "msiof2_txd_c", 4782 "msiof2_rxd_c", 4783 "msiof2_clk_d", 4784 "msiof2_sync_d", 4785 "msiof2_ss1_d", 4786 "msiof2_ss2_d", 4787 "msiof2_txd_d", 4788 "msiof2_rxd_d", 4789 }; 4790 4791 static const char * const msiof3_groups[] = { 4792 "msiof3_clk_a", 4793 "msiof3_sync_a", 4794 "msiof3_ss1_a", 4795 "msiof3_ss2_a", 4796 "msiof3_txd_a", 4797 "msiof3_rxd_a", 4798 "msiof3_clk_b", 4799 "msiof3_sync_b", 4800 "msiof3_ss1_b", 4801 "msiof3_ss2_b", 4802 "msiof3_txd_b", 4803 "msiof3_rxd_b", 4804 "msiof3_clk_c", 4805 "msiof3_sync_c", 4806 "msiof3_txd_c", 4807 "msiof3_rxd_c", 4808 "msiof3_clk_d", 4809 "msiof3_sync_d", 4810 "msiof3_ss1_d", 4811 "msiof3_txd_d", 4812 "msiof3_rxd_d", 4813 "msiof3_clk_e", 4814 "msiof3_sync_e", 4815 "msiof3_ss1_e", 4816 "msiof3_ss2_e", 4817 "msiof3_txd_e", 4818 "msiof3_rxd_e", 4819 }; 4820 4821 static const char * const pwm0_groups[] = { 4822 "pwm0", 4823 }; 4824 4825 static const char * const pwm1_groups[] = { 4826 "pwm1_a", 4827 "pwm1_b", 4828 }; 4829 4830 static const char * const pwm2_groups[] = { 4831 "pwm2_a", 4832 "pwm2_b", 4833 }; 4834 4835 static const char * const pwm3_groups[] = { 4836 "pwm3_a", 4837 "pwm3_b", 4838 }; 4839 4840 static const char * const pwm4_groups[] = { 4841 "pwm4_a", 4842 "pwm4_b", 4843 }; 4844 4845 static const char * const pwm5_groups[] = { 4846 "pwm5_a", 4847 "pwm5_b", 4848 }; 4849 4850 static const char * const pwm6_groups[] = { 4851 "pwm6_a", 4852 "pwm6_b", 4853 }; 4854 4855 static const char * const sata0_groups[] = { 4856 "sata0_devslp_a", 4857 "sata0_devslp_b", 4858 }; 4859 4860 static const char * const scif0_groups[] = { 4861 "scif0_data", 4862 "scif0_clk", 4863 "scif0_ctrl", 4864 }; 4865 4866 static const char * const scif1_groups[] = { 4867 "scif1_data_a", 4868 "scif1_clk", 4869 "scif1_ctrl", 4870 "scif1_data_b", 4871 }; 4872 4873 static const char * const scif2_groups[] = { 4874 "scif2_data_a", 4875 "scif2_clk", 4876 "scif2_data_b", 4877 }; 4878 4879 static const char * const scif3_groups[] = { 4880 "scif3_data_a", 4881 "scif3_clk", 4882 "scif3_ctrl", 4883 "scif3_data_b", 4884 }; 4885 4886 static const char * const scif4_groups[] = { 4887 "scif4_data_a", 4888 "scif4_clk_a", 4889 "scif4_ctrl_a", 4890 "scif4_data_b", 4891 "scif4_clk_b", 4892 "scif4_ctrl_b", 4893 "scif4_data_c", 4894 "scif4_clk_c", 4895 "scif4_ctrl_c", 4896 }; 4897 4898 static const char * const scif5_groups[] = { 4899 "scif5_data_a", 4900 "scif5_clk_a", 4901 "scif5_data_b", 4902 "scif5_clk_b", 4903 }; 4904 4905 static const char * const scif_clk_groups[] = { 4906 "scif_clk_a", 4907 "scif_clk_b", 4908 }; 4909 4910 static const char * const sdhi0_groups[] = { 4911 "sdhi0_data1", 4912 "sdhi0_data4", 4913 "sdhi0_ctrl", 4914 "sdhi0_cd", 4915 "sdhi0_wp", 4916 }; 4917 4918 static const char * const sdhi1_groups[] = { 4919 "sdhi1_data1", 4920 "sdhi1_data4", 4921 "sdhi1_ctrl", 4922 "sdhi1_cd", 4923 "sdhi1_wp", 4924 }; 4925 4926 static const char * const sdhi2_groups[] = { 4927 "sdhi2_data1", 4928 "sdhi2_data4", 4929 "sdhi2_data8", 4930 "sdhi2_ctrl", 4931 "sdhi2_cd_a", 4932 "sdhi2_wp_a", 4933 "sdhi2_cd_b", 4934 "sdhi2_wp_b", 4935 "sdhi2_ds", 4936 }; 4937 4938 static const char * const sdhi3_groups[] = { 4939 "sdhi3_data1", 4940 "sdhi3_data4", 4941 "sdhi3_data8", 4942 "sdhi3_ctrl", 4943 "sdhi3_cd", 4944 "sdhi3_wp", 4945 "sdhi3_ds", 4946 }; 4947 4948 static const char * const ssi_groups[] = { 4949 "ssi0_data", 4950 "ssi01239_ctrl", 4951 "ssi1_data_a", 4952 "ssi1_data_b", 4953 "ssi1_ctrl_a", 4954 "ssi1_ctrl_b", 4955 "ssi2_data_a", 4956 "ssi2_data_b", 4957 "ssi2_ctrl_a", 4958 "ssi2_ctrl_b", 4959 "ssi3_data", 4960 "ssi349_ctrl", 4961 "ssi4_data", 4962 "ssi4_ctrl", 4963 "ssi5_data", 4964 "ssi5_ctrl", 4965 "ssi6_data", 4966 "ssi6_ctrl", 4967 "ssi7_data", 4968 "ssi78_ctrl", 4969 "ssi8_data", 4970 "ssi9_data_a", 4971 "ssi9_data_b", 4972 "ssi9_ctrl_a", 4973 "ssi9_ctrl_b", 4974 }; 4975 4976 static const char * const tmu_groups[] = { 4977 "tmu_tclk1_a", 4978 "tmu_tclk1_b", 4979 "tmu_tclk2_a", 4980 "tmu_tclk2_b", 4981 }; 4982 4983 static const char * const tpu_groups[] = { 4984 "tpu_to0", 4985 "tpu_to1", 4986 "tpu_to2", 4987 "tpu_to3", 4988 }; 4989 4990 static const char * const usb0_groups[] = { 4991 "usb0", 4992 }; 4993 4994 static const char * const usb1_groups[] = { 4995 "usb1", 4996 }; 4997 4998 static const char * const usb2_groups[] = { 4999 "usb2", 5000 }; 5001 5002 static const char * const usb2_ch3_groups[] = { 5003 "usb2_ch3", 5004 }; 5005 5006 static const char * const usb30_groups[] = { 5007 "usb30", 5008 }; 5009 5010 static const char * const vin4_groups[] = { 5011 "vin4_data8_a", 5012 "vin4_data10_a", 5013 "vin4_data12_a", 5014 "vin4_data16_a", 5015 "vin4_data18_a", 5016 "vin4_data20_a", 5017 "vin4_data24_a", 5018 "vin4_data8_b", 5019 "vin4_data10_b", 5020 "vin4_data12_b", 5021 "vin4_data16_b", 5022 "vin4_data18_b", 5023 "vin4_data20_b", 5024 "vin4_data24_b", 5025 "vin4_sync", 5026 "vin4_field", 5027 "vin4_clkenb", 5028 "vin4_clk", 5029 }; 5030 5031 static const char * const vin5_groups[] = { 5032 "vin5_data8", 5033 "vin5_data10", 5034 "vin5_data12", 5035 "vin5_data16", 5036 "vin5_sync", 5037 "vin5_field", 5038 "vin5_clkenb", 5039 "vin5_clk", 5040 }; 5041 5042 static const struct { 5043 struct sh_pfc_function common[53]; 5044 struct sh_pfc_function automotive[4]; 5045 } pinmux_functions = { 5046 .common = { 5047 SH_PFC_FUNCTION(audio_clk), 5048 SH_PFC_FUNCTION(avb), 5049 SH_PFC_FUNCTION(can0), 5050 SH_PFC_FUNCTION(can1), 5051 SH_PFC_FUNCTION(can_clk), 5052 SH_PFC_FUNCTION(canfd0), 5053 SH_PFC_FUNCTION(canfd1), 5054 SH_PFC_FUNCTION(du), 5055 SH_PFC_FUNCTION(hscif0), 5056 SH_PFC_FUNCTION(hscif1), 5057 SH_PFC_FUNCTION(hscif2), 5058 SH_PFC_FUNCTION(hscif3), 5059 SH_PFC_FUNCTION(hscif4), 5060 SH_PFC_FUNCTION(i2c0), 5061 SH_PFC_FUNCTION(i2c1), 5062 SH_PFC_FUNCTION(i2c2), 5063 SH_PFC_FUNCTION(i2c3), 5064 SH_PFC_FUNCTION(i2c5), 5065 SH_PFC_FUNCTION(i2c6), 5066 SH_PFC_FUNCTION(intc_ex), 5067 SH_PFC_FUNCTION(msiof0), 5068 SH_PFC_FUNCTION(msiof1), 5069 SH_PFC_FUNCTION(msiof2), 5070 SH_PFC_FUNCTION(msiof3), 5071 SH_PFC_FUNCTION(pwm0), 5072 SH_PFC_FUNCTION(pwm1), 5073 SH_PFC_FUNCTION(pwm2), 5074 SH_PFC_FUNCTION(pwm3), 5075 SH_PFC_FUNCTION(pwm4), 5076 SH_PFC_FUNCTION(pwm5), 5077 SH_PFC_FUNCTION(pwm6), 5078 SH_PFC_FUNCTION(sata0), 5079 SH_PFC_FUNCTION(scif0), 5080 SH_PFC_FUNCTION(scif1), 5081 SH_PFC_FUNCTION(scif2), 5082 SH_PFC_FUNCTION(scif3), 5083 SH_PFC_FUNCTION(scif4), 5084 SH_PFC_FUNCTION(scif5), 5085 SH_PFC_FUNCTION(scif_clk), 5086 SH_PFC_FUNCTION(sdhi0), 5087 SH_PFC_FUNCTION(sdhi1), 5088 SH_PFC_FUNCTION(sdhi2), 5089 SH_PFC_FUNCTION(sdhi3), 5090 SH_PFC_FUNCTION(ssi), 5091 SH_PFC_FUNCTION(tmu), 5092 SH_PFC_FUNCTION(tpu), 5093 SH_PFC_FUNCTION(usb0), 5094 SH_PFC_FUNCTION(usb1), 5095 SH_PFC_FUNCTION(usb2), 5096 SH_PFC_FUNCTION(usb2_ch3), 5097 SH_PFC_FUNCTION(usb30), 5098 SH_PFC_FUNCTION(vin4), 5099 SH_PFC_FUNCTION(vin5), 5100 }, 5101 .automotive = { 5102 SH_PFC_FUNCTION(drif0), 5103 SH_PFC_FUNCTION(drif1), 5104 SH_PFC_FUNCTION(drif2), 5105 SH_PFC_FUNCTION(drif3), 5106 } 5107 5108 }; 5109 5110 static const struct pinmux_cfg_reg pinmux_config_regs[] = { 5111 #define F_(x, y) FN_##y 5112 #define FM(x) FN_##x 5113 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP( 5114 0, 0, 5115 0, 0, 5116 0, 0, 5117 0, 0, 5118 0, 0, 5119 0, 0, 5120 0, 0, 5121 0, 0, 5122 0, 0, 5123 0, 0, 5124 0, 0, 5125 0, 0, 5126 0, 0, 5127 0, 0, 5128 0, 0, 5129 0, 0, 5130 GP_0_15_FN, GPSR0_15, 5131 GP_0_14_FN, GPSR0_14, 5132 GP_0_13_FN, GPSR0_13, 5133 GP_0_12_FN, GPSR0_12, 5134 GP_0_11_FN, GPSR0_11, 5135 GP_0_10_FN, GPSR0_10, 5136 GP_0_9_FN, GPSR0_9, 5137 GP_0_8_FN, GPSR0_8, 5138 GP_0_7_FN, GPSR0_7, 5139 GP_0_6_FN, GPSR0_6, 5140 GP_0_5_FN, GPSR0_5, 5141 GP_0_4_FN, GPSR0_4, 5142 GP_0_3_FN, GPSR0_3, 5143 GP_0_2_FN, GPSR0_2, 5144 GP_0_1_FN, GPSR0_1, 5145 GP_0_0_FN, GPSR0_0, )) 5146 }, 5147 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP( 5148 0, 0, 5149 0, 0, 5150 0, 0, 5151 GP_1_28_FN, GPSR1_28, 5152 GP_1_27_FN, GPSR1_27, 5153 GP_1_26_FN, GPSR1_26, 5154 GP_1_25_FN, GPSR1_25, 5155 GP_1_24_FN, GPSR1_24, 5156 GP_1_23_FN, GPSR1_23, 5157 GP_1_22_FN, GPSR1_22, 5158 GP_1_21_FN, GPSR1_21, 5159 GP_1_20_FN, GPSR1_20, 5160 GP_1_19_FN, GPSR1_19, 5161 GP_1_18_FN, GPSR1_18, 5162 GP_1_17_FN, GPSR1_17, 5163 GP_1_16_FN, GPSR1_16, 5164 GP_1_15_FN, GPSR1_15, 5165 GP_1_14_FN, GPSR1_14, 5166 GP_1_13_FN, GPSR1_13, 5167 GP_1_12_FN, GPSR1_12, 5168 GP_1_11_FN, GPSR1_11, 5169 GP_1_10_FN, GPSR1_10, 5170 GP_1_9_FN, GPSR1_9, 5171 GP_1_8_FN, GPSR1_8, 5172 GP_1_7_FN, GPSR1_7, 5173 GP_1_6_FN, GPSR1_6, 5174 GP_1_5_FN, GPSR1_5, 5175 GP_1_4_FN, GPSR1_4, 5176 GP_1_3_FN, GPSR1_3, 5177 GP_1_2_FN, GPSR1_2, 5178 GP_1_1_FN, GPSR1_1, 5179 GP_1_0_FN, GPSR1_0, )) 5180 }, 5181 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP( 5182 0, 0, 5183 0, 0, 5184 0, 0, 5185 0, 0, 5186 0, 0, 5187 0, 0, 5188 0, 0, 5189 0, 0, 5190 0, 0, 5191 0, 0, 5192 0, 0, 5193 0, 0, 5194 0, 0, 5195 0, 0, 5196 0, 0, 5197 0, 0, 5198 0, 0, 5199 GP_2_14_FN, GPSR2_14, 5200 GP_2_13_FN, GPSR2_13, 5201 GP_2_12_FN, GPSR2_12, 5202 GP_2_11_FN, GPSR2_11, 5203 GP_2_10_FN, GPSR2_10, 5204 GP_2_9_FN, GPSR2_9, 5205 GP_2_8_FN, GPSR2_8, 5206 GP_2_7_FN, GPSR2_7, 5207 GP_2_6_FN, GPSR2_6, 5208 GP_2_5_FN, GPSR2_5, 5209 GP_2_4_FN, GPSR2_4, 5210 GP_2_3_FN, GPSR2_3, 5211 GP_2_2_FN, GPSR2_2, 5212 GP_2_1_FN, GPSR2_1, 5213 GP_2_0_FN, GPSR2_0, )) 5214 }, 5215 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP( 5216 0, 0, 5217 0, 0, 5218 0, 0, 5219 0, 0, 5220 0, 0, 5221 0, 0, 5222 0, 0, 5223 0, 0, 5224 0, 0, 5225 0, 0, 5226 0, 0, 5227 0, 0, 5228 0, 0, 5229 0, 0, 5230 0, 0, 5231 0, 0, 5232 GP_3_15_FN, GPSR3_15, 5233 GP_3_14_FN, GPSR3_14, 5234 GP_3_13_FN, GPSR3_13, 5235 GP_3_12_FN, GPSR3_12, 5236 GP_3_11_FN, GPSR3_11, 5237 GP_3_10_FN, GPSR3_10, 5238 GP_3_9_FN, GPSR3_9, 5239 GP_3_8_FN, GPSR3_8, 5240 GP_3_7_FN, GPSR3_7, 5241 GP_3_6_FN, GPSR3_6, 5242 GP_3_5_FN, GPSR3_5, 5243 GP_3_4_FN, GPSR3_4, 5244 GP_3_3_FN, GPSR3_3, 5245 GP_3_2_FN, GPSR3_2, 5246 GP_3_1_FN, GPSR3_1, 5247 GP_3_0_FN, GPSR3_0, )) 5248 }, 5249 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP( 5250 0, 0, 5251 0, 0, 5252 0, 0, 5253 0, 0, 5254 0, 0, 5255 0, 0, 5256 0, 0, 5257 0, 0, 5258 0, 0, 5259 0, 0, 5260 0, 0, 5261 0, 0, 5262 0, 0, 5263 0, 0, 5264 GP_4_17_FN, GPSR4_17, 5265 GP_4_16_FN, GPSR4_16, 5266 GP_4_15_FN, GPSR4_15, 5267 GP_4_14_FN, GPSR4_14, 5268 GP_4_13_FN, GPSR4_13, 5269 GP_4_12_FN, GPSR4_12, 5270 GP_4_11_FN, GPSR4_11, 5271 GP_4_10_FN, GPSR4_10, 5272 GP_4_9_FN, GPSR4_9, 5273 GP_4_8_FN, GPSR4_8, 5274 GP_4_7_FN, GPSR4_7, 5275 GP_4_6_FN, GPSR4_6, 5276 GP_4_5_FN, GPSR4_5, 5277 GP_4_4_FN, GPSR4_4, 5278 GP_4_3_FN, GPSR4_3, 5279 GP_4_2_FN, GPSR4_2, 5280 GP_4_1_FN, GPSR4_1, 5281 GP_4_0_FN, GPSR4_0, )) 5282 }, 5283 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP( 5284 0, 0, 5285 0, 0, 5286 0, 0, 5287 0, 0, 5288 0, 0, 5289 0, 0, 5290 GP_5_25_FN, GPSR5_25, 5291 GP_5_24_FN, GPSR5_24, 5292 GP_5_23_FN, GPSR5_23, 5293 GP_5_22_FN, GPSR5_22, 5294 GP_5_21_FN, GPSR5_21, 5295 GP_5_20_FN, GPSR5_20, 5296 GP_5_19_FN, GPSR5_19, 5297 GP_5_18_FN, GPSR5_18, 5298 GP_5_17_FN, GPSR5_17, 5299 GP_5_16_FN, GPSR5_16, 5300 GP_5_15_FN, GPSR5_15, 5301 GP_5_14_FN, GPSR5_14, 5302 GP_5_13_FN, GPSR5_13, 5303 GP_5_12_FN, GPSR5_12, 5304 GP_5_11_FN, GPSR5_11, 5305 GP_5_10_FN, GPSR5_10, 5306 GP_5_9_FN, GPSR5_9, 5307 GP_5_8_FN, GPSR5_8, 5308 GP_5_7_FN, GPSR5_7, 5309 GP_5_6_FN, GPSR5_6, 5310 GP_5_5_FN, GPSR5_5, 5311 GP_5_4_FN, GPSR5_4, 5312 GP_5_3_FN, GPSR5_3, 5313 GP_5_2_FN, GPSR5_2, 5314 GP_5_1_FN, GPSR5_1, 5315 GP_5_0_FN, GPSR5_0, )) 5316 }, 5317 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP( 5318 GP_6_31_FN, GPSR6_31, 5319 GP_6_30_FN, GPSR6_30, 5320 GP_6_29_FN, GPSR6_29, 5321 GP_6_28_FN, GPSR6_28, 5322 GP_6_27_FN, GPSR6_27, 5323 GP_6_26_FN, GPSR6_26, 5324 GP_6_25_FN, GPSR6_25, 5325 GP_6_24_FN, GPSR6_24, 5326 GP_6_23_FN, GPSR6_23, 5327 GP_6_22_FN, GPSR6_22, 5328 GP_6_21_FN, GPSR6_21, 5329 GP_6_20_FN, GPSR6_20, 5330 GP_6_19_FN, GPSR6_19, 5331 GP_6_18_FN, GPSR6_18, 5332 GP_6_17_FN, GPSR6_17, 5333 GP_6_16_FN, GPSR6_16, 5334 GP_6_15_FN, GPSR6_15, 5335 GP_6_14_FN, GPSR6_14, 5336 GP_6_13_FN, GPSR6_13, 5337 GP_6_12_FN, GPSR6_12, 5338 GP_6_11_FN, GPSR6_11, 5339 GP_6_10_FN, GPSR6_10, 5340 GP_6_9_FN, GPSR6_9, 5341 GP_6_8_FN, GPSR6_8, 5342 GP_6_7_FN, GPSR6_7, 5343 GP_6_6_FN, GPSR6_6, 5344 GP_6_5_FN, GPSR6_5, 5345 GP_6_4_FN, GPSR6_4, 5346 GP_6_3_FN, GPSR6_3, 5347 GP_6_2_FN, GPSR6_2, 5348 GP_6_1_FN, GPSR6_1, 5349 GP_6_0_FN, GPSR6_0, )) 5350 }, 5351 { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1, GROUP( 5352 0, 0, 5353 0, 0, 5354 0, 0, 5355 0, 0, 5356 0, 0, 5357 0, 0, 5358 0, 0, 5359 0, 0, 5360 0, 0, 5361 0, 0, 5362 0, 0, 5363 0, 0, 5364 0, 0, 5365 0, 0, 5366 0, 0, 5367 0, 0, 5368 0, 0, 5369 0, 0, 5370 0, 0, 5371 0, 0, 5372 0, 0, 5373 0, 0, 5374 0, 0, 5375 0, 0, 5376 0, 0, 5377 0, 0, 5378 0, 0, 5379 0, 0, 5380 GP_7_3_FN, GPSR7_3, 5381 GP_7_2_FN, GPSR7_2, 5382 GP_7_1_FN, GPSR7_1, 5383 GP_7_0_FN, GPSR7_0, )) 5384 }, 5385 #undef F_ 5386 #undef FM 5387 5388 #define F_(x, y) x, 5389 #define FM(x) FN_##x, 5390 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP( 5391 IP0_31_28 5392 IP0_27_24 5393 IP0_23_20 5394 IP0_19_16 5395 IP0_15_12 5396 IP0_11_8 5397 IP0_7_4 5398 IP0_3_0 )) 5399 }, 5400 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP( 5401 IP1_31_28 5402 IP1_27_24 5403 IP1_23_20 5404 IP1_19_16 5405 IP1_15_12 5406 IP1_11_8 5407 IP1_7_4 5408 IP1_3_0 )) 5409 }, 5410 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP( 5411 IP2_31_28 5412 IP2_27_24 5413 IP2_23_20 5414 IP2_19_16 5415 IP2_15_12 5416 IP2_11_8 5417 IP2_7_4 5418 IP2_3_0 )) 5419 }, 5420 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP( 5421 IP3_31_28 5422 IP3_27_24 5423 IP3_23_20 5424 IP3_19_16 5425 IP3_15_12 5426 IP3_11_8 5427 IP3_7_4 5428 IP3_3_0 )) 5429 }, 5430 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP( 5431 IP4_31_28 5432 IP4_27_24 5433 IP4_23_20 5434 IP4_19_16 5435 IP4_15_12 5436 IP4_11_8 5437 IP4_7_4 5438 IP4_3_0 )) 5439 }, 5440 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP( 5441 IP5_31_28 5442 IP5_27_24 5443 IP5_23_20 5444 IP5_19_16 5445 IP5_15_12 5446 IP5_11_8 5447 IP5_7_4 5448 IP5_3_0 )) 5449 }, 5450 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP( 5451 IP6_31_28 5452 IP6_27_24 5453 IP6_23_20 5454 IP6_19_16 5455 IP6_15_12 5456 IP6_11_8 5457 IP6_7_4 5458 IP6_3_0 )) 5459 }, 5460 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP( 5461 IP7_31_28 5462 IP7_27_24 5463 IP7_23_20 5464 IP7_19_16 5465 /* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5466 IP7_11_8 5467 IP7_7_4 5468 IP7_3_0 )) 5469 }, 5470 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP( 5471 IP8_31_28 5472 IP8_27_24 5473 IP8_23_20 5474 IP8_19_16 5475 IP8_15_12 5476 IP8_11_8 5477 IP8_7_4 5478 IP8_3_0 )) 5479 }, 5480 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP( 5481 IP9_31_28 5482 IP9_27_24 5483 IP9_23_20 5484 IP9_19_16 5485 IP9_15_12 5486 IP9_11_8 5487 IP9_7_4 5488 IP9_3_0 )) 5489 }, 5490 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP( 5491 IP10_31_28 5492 IP10_27_24 5493 IP10_23_20 5494 IP10_19_16 5495 IP10_15_12 5496 IP10_11_8 5497 IP10_7_4 5498 IP10_3_0 )) 5499 }, 5500 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP( 5501 IP11_31_28 5502 IP11_27_24 5503 IP11_23_20 5504 IP11_19_16 5505 IP11_15_12 5506 IP11_11_8 5507 IP11_7_4 5508 IP11_3_0 )) 5509 }, 5510 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP( 5511 IP12_31_28 5512 IP12_27_24 5513 IP12_23_20 5514 IP12_19_16 5515 IP12_15_12 5516 IP12_11_8 5517 IP12_7_4 5518 IP12_3_0 )) 5519 }, 5520 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP( 5521 IP13_31_28 5522 IP13_27_24 5523 IP13_23_20 5524 IP13_19_16 5525 IP13_15_12 5526 IP13_11_8 5527 IP13_7_4 5528 IP13_3_0 )) 5529 }, 5530 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP( 5531 IP14_31_28 5532 IP14_27_24 5533 IP14_23_20 5534 IP14_19_16 5535 IP14_15_12 5536 IP14_11_8 5537 IP14_7_4 5538 IP14_3_0 )) 5539 }, 5540 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP( 5541 IP15_31_28 5542 IP15_27_24 5543 IP15_23_20 5544 IP15_19_16 5545 IP15_15_12 5546 IP15_11_8 5547 IP15_7_4 5548 IP15_3_0 )) 5549 }, 5550 { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4, GROUP( 5551 IP16_31_28 5552 IP16_27_24 5553 IP16_23_20 5554 IP16_19_16 5555 IP16_15_12 5556 IP16_11_8 5557 IP16_7_4 5558 IP16_3_0 )) 5559 }, 5560 { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4, GROUP( 5561 IP17_31_28 5562 IP17_27_24 5563 IP17_23_20 5564 IP17_19_16 5565 IP17_15_12 5566 IP17_11_8 5567 IP17_7_4 5568 IP17_3_0 )) 5569 }, 5570 { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4, GROUP( 5571 /* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5572 /* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5573 /* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5574 /* IP18_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5575 /* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5576 /* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5577 IP18_7_4 5578 IP18_3_0 )) 5579 }, 5580 #undef F_ 5581 #undef FM 5582 5583 #define F_(x, y) x, 5584 #define FM(x) FN_##x, 5585 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32, 5586 GROUP(3, 2, 3, 1, 1, 1, 1, 1, 2, 1, 1, 2, 5587 1, 1, 1, 2, 2, 1, 2, 3), 5588 GROUP( 5589 MOD_SEL0_31_30_29 5590 MOD_SEL0_28_27 5591 MOD_SEL0_26_25_24 5592 MOD_SEL0_23 5593 MOD_SEL0_22 5594 MOD_SEL0_21 5595 MOD_SEL0_20 5596 MOD_SEL0_19 5597 MOD_SEL0_18_17 5598 MOD_SEL0_16 5599 0, 0, /* RESERVED 15 */ 5600 MOD_SEL0_14_13 5601 MOD_SEL0_12 5602 MOD_SEL0_11 5603 MOD_SEL0_10 5604 MOD_SEL0_9_8 5605 MOD_SEL0_7_6 5606 MOD_SEL0_5 5607 MOD_SEL0_4_3 5608 /* RESERVED 2, 1, 0 */ 5609 0, 0, 0, 0, 0, 0, 0, 0 )) 5610 }, 5611 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32, 5612 GROUP(2, 3, 1, 2, 3, 1, 1, 2, 1, 2, 1, 1, 5613 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1), 5614 GROUP( 5615 MOD_SEL1_31_30 5616 MOD_SEL1_29_28_27 5617 MOD_SEL1_26 5618 MOD_SEL1_25_24 5619 MOD_SEL1_23_22_21 5620 MOD_SEL1_20 5621 MOD_SEL1_19 5622 MOD_SEL1_18_17 5623 MOD_SEL1_16 5624 MOD_SEL1_15_14 5625 MOD_SEL1_13 5626 MOD_SEL1_12 5627 MOD_SEL1_11 5628 MOD_SEL1_10 5629 MOD_SEL1_9 5630 0, 0, 0, 0, /* RESERVED 8, 7 */ 5631 MOD_SEL1_6 5632 MOD_SEL1_5 5633 MOD_SEL1_4 5634 MOD_SEL1_3 5635 MOD_SEL1_2 5636 MOD_SEL1_1 5637 MOD_SEL1_0 )) 5638 }, 5639 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32, 5640 GROUP(1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, 5641 1, 4, 4, 4, 3, 1), 5642 GROUP( 5643 MOD_SEL2_31 5644 MOD_SEL2_30 5645 MOD_SEL2_29 5646 MOD_SEL2_28_27 5647 MOD_SEL2_26 5648 MOD_SEL2_25_24_23 5649 /* RESERVED 22 */ 5650 0, 0, 5651 MOD_SEL2_21 5652 MOD_SEL2_20 5653 MOD_SEL2_19 5654 MOD_SEL2_18 5655 MOD_SEL2_17 5656 /* RESERVED 16 */ 5657 0, 0, 5658 /* RESERVED 15, 14, 13, 12 */ 5659 0, 0, 0, 0, 0, 0, 0, 0, 5660 0, 0, 0, 0, 0, 0, 0, 0, 5661 /* RESERVED 11, 10, 9, 8 */ 5662 0, 0, 0, 0, 0, 0, 0, 0, 5663 0, 0, 0, 0, 0, 0, 0, 0, 5664 /* RESERVED 7, 6, 5, 4 */ 5665 0, 0, 0, 0, 0, 0, 0, 0, 5666 0, 0, 0, 0, 0, 0, 0, 0, 5667 /* RESERVED 3, 2, 1 */ 5668 0, 0, 0, 0, 0, 0, 0, 0, 5669 MOD_SEL2_0 )) 5670 }, 5671 { }, 5672 }; 5673 5674 static const struct pinmux_drive_reg pinmux_drive_regs[] = { 5675 { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) { 5676 { PIN_QSPI0_SPCLK, 28, 2 }, /* QSPI0_SPCLK */ 5677 { PIN_QSPI0_MOSI_IO0, 24, 2 }, /* QSPI0_MOSI_IO0 */ 5678 { PIN_QSPI0_MISO_IO1, 20, 2 }, /* QSPI0_MISO_IO1 */ 5679 { PIN_QSPI0_IO2, 16, 2 }, /* QSPI0_IO2 */ 5680 { PIN_QSPI0_IO3, 12, 2 }, /* QSPI0_IO3 */ 5681 { PIN_QSPI0_SSL, 8, 2 }, /* QSPI0_SSL */ 5682 { PIN_QSPI1_SPCLK, 4, 2 }, /* QSPI1_SPCLK */ 5683 { PIN_QSPI1_MOSI_IO0, 0, 2 }, /* QSPI1_MOSI_IO0 */ 5684 } }, 5685 { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) { 5686 { PIN_QSPI1_MISO_IO1, 28, 2 }, /* QSPI1_MISO_IO1 */ 5687 { PIN_QSPI1_IO2, 24, 2 }, /* QSPI1_IO2 */ 5688 { PIN_QSPI1_IO3, 20, 2 }, /* QSPI1_IO3 */ 5689 { PIN_QSPI1_SSL, 16, 2 }, /* QSPI1_SSL */ 5690 { PIN_RPC_INT_N, 12, 2 }, /* RPC_INT# */ 5691 { PIN_RPC_WP_N, 8, 2 }, /* RPC_WP# */ 5692 { PIN_RPC_RESET_N, 4, 2 }, /* RPC_RESET# */ 5693 { PIN_AVB_RX_CTL, 0, 3 }, /* AVB_RX_CTL */ 5694 } }, 5695 { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) { 5696 { PIN_AVB_RXC, 28, 3 }, /* AVB_RXC */ 5697 { PIN_AVB_RD0, 24, 3 }, /* AVB_RD0 */ 5698 { PIN_AVB_RD1, 20, 3 }, /* AVB_RD1 */ 5699 { PIN_AVB_RD2, 16, 3 }, /* AVB_RD2 */ 5700 { PIN_AVB_RD3, 12, 3 }, /* AVB_RD3 */ 5701 { PIN_AVB_TX_CTL, 8, 3 }, /* AVB_TX_CTL */ 5702 { PIN_AVB_TXC, 4, 3 }, /* AVB_TXC */ 5703 { PIN_AVB_TD0, 0, 3 }, /* AVB_TD0 */ 5704 } }, 5705 { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) { 5706 { PIN_AVB_TD1, 28, 3 }, /* AVB_TD1 */ 5707 { PIN_AVB_TD2, 24, 3 }, /* AVB_TD2 */ 5708 { PIN_AVB_TD3, 20, 3 }, /* AVB_TD3 */ 5709 { PIN_AVB_TXCREFCLK, 16, 3 }, /* AVB_TXCREFCLK */ 5710 { PIN_AVB_MDIO, 12, 3 }, /* AVB_MDIO */ 5711 { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */ 5712 { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */ 5713 { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */ 5714 } }, 5715 { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) { 5716 { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */ 5717 { RCAR_GP_PIN(2, 13), 24, 3 }, /* AVB_AVTP_MATCH */ 5718 { RCAR_GP_PIN(2, 14), 20, 3 }, /* AVB_AVTP_CAPTURE */ 5719 { RCAR_GP_PIN(2, 0), 16, 3 }, /* IRQ0 */ 5720 { RCAR_GP_PIN(2, 1), 12, 3 }, /* IRQ1 */ 5721 { RCAR_GP_PIN(2, 2), 8, 3 }, /* IRQ2 */ 5722 { RCAR_GP_PIN(2, 3), 4, 3 }, /* IRQ3 */ 5723 { RCAR_GP_PIN(2, 4), 0, 3 }, /* IRQ4 */ 5724 } }, 5725 { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) { 5726 { RCAR_GP_PIN(2, 5), 28, 3 }, /* IRQ5 */ 5727 { RCAR_GP_PIN(2, 6), 24, 3 }, /* PWM0 */ 5728 { RCAR_GP_PIN(2, 7), 20, 3 }, /* PWM1 */ 5729 { RCAR_GP_PIN(2, 8), 16, 3 }, /* PWM2 */ 5730 { RCAR_GP_PIN(1, 0), 12, 3 }, /* A0 */ 5731 { RCAR_GP_PIN(1, 1), 8, 3 }, /* A1 */ 5732 { RCAR_GP_PIN(1, 2), 4, 3 }, /* A2 */ 5733 { RCAR_GP_PIN(1, 3), 0, 3 }, /* A3 */ 5734 } }, 5735 { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) { 5736 { RCAR_GP_PIN(1, 4), 28, 3 }, /* A4 */ 5737 { RCAR_GP_PIN(1, 5), 24, 3 }, /* A5 */ 5738 { RCAR_GP_PIN(1, 6), 20, 3 }, /* A6 */ 5739 { RCAR_GP_PIN(1, 7), 16, 3 }, /* A7 */ 5740 { RCAR_GP_PIN(1, 8), 12, 3 }, /* A8 */ 5741 { RCAR_GP_PIN(1, 9), 8, 3 }, /* A9 */ 5742 { RCAR_GP_PIN(1, 10), 4, 3 }, /* A10 */ 5743 { RCAR_GP_PIN(1, 11), 0, 3 }, /* A11 */ 5744 } }, 5745 { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) { 5746 { RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */ 5747 { RCAR_GP_PIN(1, 13), 24, 3 }, /* A13 */ 5748 { RCAR_GP_PIN(1, 14), 20, 3 }, /* A14 */ 5749 { RCAR_GP_PIN(1, 15), 16, 3 }, /* A15 */ 5750 { RCAR_GP_PIN(1, 16), 12, 3 }, /* A16 */ 5751 { RCAR_GP_PIN(1, 17), 8, 3 }, /* A17 */ 5752 { RCAR_GP_PIN(1, 18), 4, 3 }, /* A18 */ 5753 { RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */ 5754 } }, 5755 { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) { 5756 { RCAR_GP_PIN(1, 28), 28, 3 }, /* CLKOUT */ 5757 { RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */ 5758 { RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */ 5759 { RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */ 5760 { RCAR_GP_PIN(1, 23), 12, 3 }, /* RD */ 5761 { RCAR_GP_PIN(1, 24), 8, 3 }, /* RD_WR */ 5762 { RCAR_GP_PIN(1, 25), 4, 3 }, /* WE0 */ 5763 { RCAR_GP_PIN(1, 26), 0, 3 }, /* WE1 */ 5764 } }, 5765 { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) { 5766 { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */ 5767 { PIN_PRESETOUT_N, 24, 3 }, /* PRESETOUT# */ 5768 { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */ 5769 { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */ 5770 { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */ 5771 { RCAR_GP_PIN(0, 3), 8, 3 }, /* D3 */ 5772 { RCAR_GP_PIN(0, 4), 4, 3 }, /* D4 */ 5773 { RCAR_GP_PIN(0, 5), 0, 3 }, /* D5 */ 5774 } }, 5775 { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) { 5776 { RCAR_GP_PIN(0, 6), 28, 3 }, /* D6 */ 5777 { RCAR_GP_PIN(0, 7), 24, 3 }, /* D7 */ 5778 { RCAR_GP_PIN(0, 8), 20, 3 }, /* D8 */ 5779 { RCAR_GP_PIN(0, 9), 16, 3 }, /* D9 */ 5780 { RCAR_GP_PIN(0, 10), 12, 3 }, /* D10 */ 5781 { RCAR_GP_PIN(0, 11), 8, 3 }, /* D11 */ 5782 { RCAR_GP_PIN(0, 12), 4, 3 }, /* D12 */ 5783 { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */ 5784 } }, 5785 { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) { 5786 { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */ 5787 { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */ 5788 { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */ 5789 { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */ 5790 { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */ 5791 { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */ 5792 { PIN_DU_DOTCLKIN0, 4, 2 }, /* DU_DOTCLKIN0 */ 5793 { PIN_DU_DOTCLKIN1, 0, 2 }, /* DU_DOTCLKIN1 */ 5794 } }, 5795 { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) { 5796 #ifdef CONFIG_PINCTRL_PFC_R8A77951 5797 { PIN_DU_DOTCLKIN2, 28, 2 }, /* DU_DOTCLKIN2 */ 5798 #endif 5799 { PIN_DU_DOTCLKIN3, 24, 2 }, /* DU_DOTCLKIN3 */ 5800 { PIN_FSCLKST_N, 20, 2 }, /* FSCLKST# */ 5801 { PIN_TMS, 4, 2 }, /* TMS */ 5802 } }, 5803 { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) { 5804 { PIN_TDO, 28, 2 }, /* TDO */ 5805 { PIN_ASEBRK, 24, 2 }, /* ASEBRK */ 5806 { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */ 5807 { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */ 5808 { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */ 5809 { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */ 5810 { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */ 5811 { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */ 5812 } }, 5813 { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) { 5814 { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */ 5815 { RCAR_GP_PIN(3, 7), 24, 3 }, /* SD1_CMD */ 5816 { RCAR_GP_PIN(3, 8), 20, 3 }, /* SD1_DAT0 */ 5817 { RCAR_GP_PIN(3, 9), 16, 3 }, /* SD1_DAT1 */ 5818 { RCAR_GP_PIN(3, 10), 12, 3 }, /* SD1_DAT2 */ 5819 { RCAR_GP_PIN(3, 11), 8, 3 }, /* SD1_DAT3 */ 5820 { RCAR_GP_PIN(4, 0), 4, 3 }, /* SD2_CLK */ 5821 { RCAR_GP_PIN(4, 1), 0, 3 }, /* SD2_CMD */ 5822 } }, 5823 { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) { 5824 { RCAR_GP_PIN(4, 2), 28, 3 }, /* SD2_DAT0 */ 5825 { RCAR_GP_PIN(4, 3), 24, 3 }, /* SD2_DAT1 */ 5826 { RCAR_GP_PIN(4, 4), 20, 3 }, /* SD2_DAT2 */ 5827 { RCAR_GP_PIN(4, 5), 16, 3 }, /* SD2_DAT3 */ 5828 { RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */ 5829 { RCAR_GP_PIN(4, 7), 8, 3 }, /* SD3_CLK */ 5830 { RCAR_GP_PIN(4, 8), 4, 3 }, /* SD3_CMD */ 5831 { RCAR_GP_PIN(4, 9), 0, 3 }, /* SD3_DAT0 */ 5832 } }, 5833 { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) { 5834 { RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */ 5835 { RCAR_GP_PIN(4, 11), 24, 3 }, /* SD3_DAT2 */ 5836 { RCAR_GP_PIN(4, 12), 20, 3 }, /* SD3_DAT3 */ 5837 { RCAR_GP_PIN(4, 13), 16, 3 }, /* SD3_DAT4 */ 5838 { RCAR_GP_PIN(4, 14), 12, 3 }, /* SD3_DAT5 */ 5839 { RCAR_GP_PIN(4, 15), 8, 3 }, /* SD3_DAT6 */ 5840 { RCAR_GP_PIN(4, 16), 4, 3 }, /* SD3_DAT7 */ 5841 { RCAR_GP_PIN(4, 17), 0, 3 }, /* SD3_DS */ 5842 } }, 5843 { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) { 5844 { RCAR_GP_PIN(3, 12), 28, 3 }, /* SD0_CD */ 5845 { RCAR_GP_PIN(3, 13), 24, 3 }, /* SD0_WP */ 5846 { RCAR_GP_PIN(3, 14), 20, 3 }, /* SD1_CD */ 5847 { RCAR_GP_PIN(3, 15), 16, 3 }, /* SD1_WP */ 5848 { RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */ 5849 { RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */ 5850 { RCAR_GP_PIN(5, 2), 4, 3 }, /* TX0 */ 5851 { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */ 5852 } }, 5853 { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) { 5854 { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0 */ 5855 { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */ 5856 { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */ 5857 { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */ 5858 { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1 */ 5859 { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */ 5860 { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */ 5861 { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */ 5862 } }, 5863 { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) { 5864 { RCAR_GP_PIN(5, 12), 28, 3 }, /* HSCK0 */ 5865 { RCAR_GP_PIN(5, 13), 24, 3 }, /* HRX0 */ 5866 { RCAR_GP_PIN(5, 14), 20, 3 }, /* HTX0 */ 5867 { RCAR_GP_PIN(5, 15), 16, 3 }, /* HCTS0 */ 5868 { RCAR_GP_PIN(5, 16), 12, 3 }, /* HRTS0 */ 5869 { RCAR_GP_PIN(5, 17), 8, 3 }, /* MSIOF0_SCK */ 5870 { RCAR_GP_PIN(5, 18), 4, 3 }, /* MSIOF0_SYNC */ 5871 { RCAR_GP_PIN(5, 19), 0, 3 }, /* MSIOF0_SS1 */ 5872 } }, 5873 { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) { 5874 { RCAR_GP_PIN(5, 20), 28, 3 }, /* MSIOF0_TXD */ 5875 { RCAR_GP_PIN(5, 21), 24, 3 }, /* MSIOF0_SS2 */ 5876 { RCAR_GP_PIN(5, 22), 20, 3 }, /* MSIOF0_RXD */ 5877 { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */ 5878 { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */ 5879 { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */ 5880 { PIN_MLB_REF, 4, 3 }, /* MLB_REF */ 5881 { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */ 5882 } }, 5883 { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) { 5884 { RCAR_GP_PIN(6, 1), 28, 3 }, /* SSI_WS01239 */ 5885 { RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */ 5886 { RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */ 5887 { RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */ 5888 { RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK349 */ 5889 { RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS349 */ 5890 { RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */ 5891 { RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */ 5892 } }, 5893 { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) { 5894 { RCAR_GP_PIN(6, 9), 28, 3 }, /* SSI_WS4 */ 5895 { RCAR_GP_PIN(6, 10), 24, 3 }, /* SSI_SDATA4 */ 5896 { RCAR_GP_PIN(6, 11), 20, 3 }, /* SSI_SCK5 */ 5897 { RCAR_GP_PIN(6, 12), 16, 3 }, /* SSI_WS5 */ 5898 { RCAR_GP_PIN(6, 13), 12, 3 }, /* SSI_SDATA5 */ 5899 { RCAR_GP_PIN(6, 14), 8, 3 }, /* SSI_SCK6 */ 5900 { RCAR_GP_PIN(6, 15), 4, 3 }, /* SSI_WS6 */ 5901 { RCAR_GP_PIN(6, 16), 0, 3 }, /* SSI_SDATA6 */ 5902 } }, 5903 { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) { 5904 { RCAR_GP_PIN(6, 17), 28, 3 }, /* SSI_SCK78 */ 5905 { RCAR_GP_PIN(6, 18), 24, 3 }, /* SSI_WS78 */ 5906 { RCAR_GP_PIN(6, 19), 20, 3 }, /* SSI_SDATA7 */ 5907 { RCAR_GP_PIN(6, 20), 16, 3 }, /* SSI_SDATA8 */ 5908 { RCAR_GP_PIN(6, 21), 12, 3 }, /* SSI_SDATA9 */ 5909 { RCAR_GP_PIN(6, 22), 8, 3 }, /* AUDIO_CLKA */ 5910 { RCAR_GP_PIN(6, 23), 4, 3 }, /* AUDIO_CLKB */ 5911 { RCAR_GP_PIN(6, 24), 0, 3 }, /* USB0_PWEN */ 5912 } }, 5913 { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) { 5914 { RCAR_GP_PIN(6, 25), 28, 3 }, /* USB0_OVC */ 5915 { RCAR_GP_PIN(6, 26), 24, 3 }, /* USB1_PWEN */ 5916 { RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */ 5917 { RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */ 5918 { RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */ 5919 { RCAR_GP_PIN(6, 30), 8, 3 }, /* GP6_30/USB2_CH3_PWEN */ 5920 { RCAR_GP_PIN(6, 31), 4, 3 }, /* GP6_31/USB2_CH3_OVC */ 5921 } }, 5922 { }, 5923 }; 5924 5925 enum ioctrl_regs { 5926 POCCTRL, 5927 TDSELCTRL, 5928 }; 5929 5930 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { 5931 [POCCTRL] = { 0xe6060380, }, 5932 [TDSELCTRL] = { 0xe60603c0, }, 5933 { /* sentinel */ }, 5934 }; 5935 5936 static int r8a77951_pin_to_pocctrl(struct sh_pfc *pfc, 5937 unsigned int pin, u32 *pocctrl) 5938 { 5939 int bit = -EINVAL; 5940 5941 *pocctrl = pinmux_ioctrl_regs[POCCTRL].reg; 5942 5943 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11)) 5944 bit = pin & 0x1f; 5945 5946 if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17)) 5947 bit = (pin & 0x1f) + 12; 5948 5949 return bit; 5950 } 5951 5952 static const struct pinmux_bias_reg pinmux_bias_regs[] = { 5953 { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) { 5954 [ 0] = PIN_QSPI0_SPCLK, /* QSPI0_SPCLK */ 5955 [ 1] = PIN_QSPI0_MOSI_IO0, /* QSPI0_MOSI_IO0 */ 5956 [ 2] = PIN_QSPI0_MISO_IO1, /* QSPI0_MISO_IO1 */ 5957 [ 3] = PIN_QSPI0_IO2, /* QSPI0_IO2 */ 5958 [ 4] = PIN_QSPI0_IO3, /* QSPI0_IO3 */ 5959 [ 5] = PIN_QSPI0_SSL, /* QSPI0_SSL */ 5960 [ 6] = PIN_QSPI1_SPCLK, /* QSPI1_SPCLK */ 5961 [ 7] = PIN_QSPI1_MOSI_IO0, /* QSPI1_MOSI_IO0 */ 5962 [ 8] = PIN_QSPI1_MISO_IO1, /* QSPI1_MISO_IO1 */ 5963 [ 9] = PIN_QSPI1_IO2, /* QSPI1_IO2 */ 5964 [10] = PIN_QSPI1_IO3, /* QSPI1_IO3 */ 5965 [11] = PIN_QSPI1_SSL, /* QSPI1_SSL */ 5966 [12] = PIN_RPC_INT_N, /* RPC_INT# */ 5967 [13] = PIN_RPC_WP_N, /* RPC_WP# */ 5968 [14] = PIN_RPC_RESET_N, /* RPC_RESET# */ 5969 [15] = PIN_AVB_RX_CTL, /* AVB_RX_CTL */ 5970 [16] = PIN_AVB_RXC, /* AVB_RXC */ 5971 [17] = PIN_AVB_RD0, /* AVB_RD0 */ 5972 [18] = PIN_AVB_RD1, /* AVB_RD1 */ 5973 [19] = PIN_AVB_RD2, /* AVB_RD2 */ 5974 [20] = PIN_AVB_RD3, /* AVB_RD3 */ 5975 [21] = PIN_AVB_TX_CTL, /* AVB_TX_CTL */ 5976 [22] = PIN_AVB_TXC, /* AVB_TXC */ 5977 [23] = PIN_AVB_TD0, /* AVB_TD0 */ 5978 [24] = PIN_AVB_TD1, /* AVB_TD1 */ 5979 [25] = PIN_AVB_TD2, /* AVB_TD2 */ 5980 [26] = PIN_AVB_TD3, /* AVB_TD3 */ 5981 [27] = PIN_AVB_TXCREFCLK, /* AVB_TXCREFCLK */ 5982 [28] = PIN_AVB_MDIO, /* AVB_MDIO */ 5983 [29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */ 5984 [30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */ 5985 [31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */ 5986 } }, 5987 { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) { 5988 [ 0] = RCAR_GP_PIN(2, 12), /* AVB_LINK */ 5989 [ 1] = RCAR_GP_PIN(2, 13), /* AVB_AVTP_MATCH_A */ 5990 [ 2] = RCAR_GP_PIN(2, 14), /* AVB_AVTP_CAPTURE_A */ 5991 [ 3] = RCAR_GP_PIN(2, 0), /* IRQ0 */ 5992 [ 4] = RCAR_GP_PIN(2, 1), /* IRQ1 */ 5993 [ 5] = RCAR_GP_PIN(2, 2), /* IRQ2 */ 5994 [ 6] = RCAR_GP_PIN(2, 3), /* IRQ3 */ 5995 [ 7] = RCAR_GP_PIN(2, 4), /* IRQ4 */ 5996 [ 8] = RCAR_GP_PIN(2, 5), /* IRQ5 */ 5997 [ 9] = RCAR_GP_PIN(2, 6), /* PWM0 */ 5998 [10] = RCAR_GP_PIN(2, 7), /* PWM1_A */ 5999 [11] = RCAR_GP_PIN(2, 8), /* PWM2_A */ 6000 [12] = RCAR_GP_PIN(1, 0), /* A0 */ 6001 [13] = RCAR_GP_PIN(1, 1), /* A1 */ 6002 [14] = RCAR_GP_PIN(1, 2), /* A2 */ 6003 [15] = RCAR_GP_PIN(1, 3), /* A3 */ 6004 [16] = RCAR_GP_PIN(1, 4), /* A4 */ 6005 [17] = RCAR_GP_PIN(1, 5), /* A5 */ 6006 [18] = RCAR_GP_PIN(1, 6), /* A6 */ 6007 [19] = RCAR_GP_PIN(1, 7), /* A7 */ 6008 [20] = RCAR_GP_PIN(1, 8), /* A8 */ 6009 [21] = RCAR_GP_PIN(1, 9), /* A9 */ 6010 [22] = RCAR_GP_PIN(1, 10), /* A10 */ 6011 [23] = RCAR_GP_PIN(1, 11), /* A11 */ 6012 [24] = RCAR_GP_PIN(1, 12), /* A12 */ 6013 [25] = RCAR_GP_PIN(1, 13), /* A13 */ 6014 [26] = RCAR_GP_PIN(1, 14), /* A14 */ 6015 [27] = RCAR_GP_PIN(1, 15), /* A15 */ 6016 [28] = RCAR_GP_PIN(1, 16), /* A16 */ 6017 [29] = RCAR_GP_PIN(1, 17), /* A17 */ 6018 [30] = RCAR_GP_PIN(1, 18), /* A18 */ 6019 [31] = RCAR_GP_PIN(1, 19), /* A19 */ 6020 } }, 6021 { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) { 6022 [ 0] = RCAR_GP_PIN(1, 28), /* CLKOUT */ 6023 [ 1] = RCAR_GP_PIN(1, 20), /* CS0_N */ 6024 [ 2] = RCAR_GP_PIN(1, 21), /* CS1_N */ 6025 [ 3] = RCAR_GP_PIN(1, 22), /* BS_N */ 6026 [ 4] = RCAR_GP_PIN(1, 23), /* RD_N */ 6027 [ 5] = RCAR_GP_PIN(1, 24), /* RD_WR_N */ 6028 [ 6] = RCAR_GP_PIN(1, 25), /* WE0_N */ 6029 [ 7] = RCAR_GP_PIN(1, 26), /* WE1_N */ 6030 [ 8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */ 6031 [ 9] = PIN_PRESETOUT_N, /* PRESETOUT# */ 6032 [10] = RCAR_GP_PIN(0, 0), /* D0 */ 6033 [11] = RCAR_GP_PIN(0, 1), /* D1 */ 6034 [12] = RCAR_GP_PIN(0, 2), /* D2 */ 6035 [13] = RCAR_GP_PIN(0, 3), /* D3 */ 6036 [14] = RCAR_GP_PIN(0, 4), /* D4 */ 6037 [15] = RCAR_GP_PIN(0, 5), /* D5 */ 6038 [16] = RCAR_GP_PIN(0, 6), /* D6 */ 6039 [17] = RCAR_GP_PIN(0, 7), /* D7 */ 6040 [18] = RCAR_GP_PIN(0, 8), /* D8 */ 6041 [19] = RCAR_GP_PIN(0, 9), /* D9 */ 6042 [20] = RCAR_GP_PIN(0, 10), /* D10 */ 6043 [21] = RCAR_GP_PIN(0, 11), /* D11 */ 6044 [22] = RCAR_GP_PIN(0, 12), /* D12 */ 6045 [23] = RCAR_GP_PIN(0, 13), /* D13 */ 6046 [24] = RCAR_GP_PIN(0, 14), /* D14 */ 6047 [25] = RCAR_GP_PIN(0, 15), /* D15 */ 6048 [26] = RCAR_GP_PIN(7, 0), /* AVS1 */ 6049 [27] = RCAR_GP_PIN(7, 1), /* AVS2 */ 6050 [28] = RCAR_GP_PIN(7, 2), /* GP7_02 */ 6051 [29] = RCAR_GP_PIN(7, 3), /* GP7_03 */ 6052 [30] = PIN_DU_DOTCLKIN0, /* DU_DOTCLKIN0 */ 6053 [31] = PIN_DU_DOTCLKIN1, /* DU_DOTCLKIN1 */ 6054 } }, 6055 { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) { 6056 [ 0] = PIN_DU_DOTCLKIN2, /* DU_DOTCLKIN2 */ 6057 [ 1] = PIN_DU_DOTCLKIN3, /* DU_DOTCLKIN3 */ 6058 [ 2] = PIN_FSCLKST_N, /* FSCLKST# */ 6059 [ 3] = PIN_EXTALR, /* EXTALR*/ 6060 [ 4] = PIN_TRST_N, /* TRST# */ 6061 [ 5] = PIN_TCK, /* TCK */ 6062 [ 6] = PIN_TMS, /* TMS */ 6063 [ 7] = PIN_TDI, /* TDI */ 6064 [ 8] = SH_PFC_PIN_NONE, 6065 [ 9] = PIN_ASEBRK, /* ASEBRK */ 6066 [10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */ 6067 [11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */ 6068 [12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */ 6069 [13] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */ 6070 [14] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */ 6071 [15] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */ 6072 [16] = RCAR_GP_PIN(3, 6), /* SD1_CLK */ 6073 [17] = RCAR_GP_PIN(3, 7), /* SD1_CMD */ 6074 [18] = RCAR_GP_PIN(3, 8), /* SD1_DAT0 */ 6075 [19] = RCAR_GP_PIN(3, 9), /* SD1_DAT1 */ 6076 [20] = RCAR_GP_PIN(3, 10), /* SD1_DAT2 */ 6077 [21] = RCAR_GP_PIN(3, 11), /* SD1_DAT3 */ 6078 [22] = RCAR_GP_PIN(4, 0), /* SD2_CLK */ 6079 [23] = RCAR_GP_PIN(4, 1), /* SD2_CMD */ 6080 [24] = RCAR_GP_PIN(4, 2), /* SD2_DAT0 */ 6081 [25] = RCAR_GP_PIN(4, 3), /* SD2_DAT1 */ 6082 [26] = RCAR_GP_PIN(4, 4), /* SD2_DAT2 */ 6083 [27] = RCAR_GP_PIN(4, 5), /* SD2_DAT3 */ 6084 [28] = RCAR_GP_PIN(4, 6), /* SD2_DS */ 6085 [29] = RCAR_GP_PIN(4, 7), /* SD3_CLK */ 6086 [30] = RCAR_GP_PIN(4, 8), /* SD3_CMD */ 6087 [31] = RCAR_GP_PIN(4, 9), /* SD3_DAT0 */ 6088 } }, 6089 { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) { 6090 [ 0] = RCAR_GP_PIN(4, 10), /* SD3_DAT1 */ 6091 [ 1] = RCAR_GP_PIN(4, 11), /* SD3_DAT2 */ 6092 [ 2] = RCAR_GP_PIN(4, 12), /* SD3_DAT3 */ 6093 [ 3] = RCAR_GP_PIN(4, 13), /* SD3_DAT4 */ 6094 [ 4] = RCAR_GP_PIN(4, 14), /* SD3_DAT5 */ 6095 [ 5] = RCAR_GP_PIN(4, 15), /* SD3_DAT6 */ 6096 [ 6] = RCAR_GP_PIN(4, 16), /* SD3_DAT7 */ 6097 [ 7] = RCAR_GP_PIN(4, 17), /* SD3_DS */ 6098 [ 8] = RCAR_GP_PIN(3, 12), /* SD0_CD */ 6099 [ 9] = RCAR_GP_PIN(3, 13), /* SD0_WP */ 6100 [10] = RCAR_GP_PIN(3, 14), /* SD1_CD */ 6101 [11] = RCAR_GP_PIN(3, 15), /* SD1_WP */ 6102 [12] = RCAR_GP_PIN(5, 0), /* SCK0 */ 6103 [13] = RCAR_GP_PIN(5, 1), /* RX0 */ 6104 [14] = RCAR_GP_PIN(5, 2), /* TX0 */ 6105 [15] = RCAR_GP_PIN(5, 3), /* CTS0_N */ 6106 [16] = RCAR_GP_PIN(5, 4), /* RTS0_N */ 6107 [17] = RCAR_GP_PIN(5, 5), /* RX1_A */ 6108 [18] = RCAR_GP_PIN(5, 6), /* TX1_A */ 6109 [19] = RCAR_GP_PIN(5, 7), /* CTS1_N */ 6110 [20] = RCAR_GP_PIN(5, 8), /* RTS1_N */ 6111 [21] = RCAR_GP_PIN(5, 9), /* SCK2 */ 6112 [22] = RCAR_GP_PIN(5, 10), /* TX2_A */ 6113 [23] = RCAR_GP_PIN(5, 11), /* RX2_A */ 6114 [24] = RCAR_GP_PIN(5, 12), /* HSCK0 */ 6115 [25] = RCAR_GP_PIN(5, 13), /* HRX0 */ 6116 [26] = RCAR_GP_PIN(5, 14), /* HTX0 */ 6117 [27] = RCAR_GP_PIN(5, 15), /* HCTS0_N */ 6118 [28] = RCAR_GP_PIN(5, 16), /* HRTS0_N */ 6119 [29] = RCAR_GP_PIN(5, 17), /* MSIOF0_SCK */ 6120 [30] = RCAR_GP_PIN(5, 18), /* MSIOF0_SYNC */ 6121 [31] = RCAR_GP_PIN(5, 19), /* MSIOF0_SS1 */ 6122 } }, 6123 { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) { 6124 [ 0] = RCAR_GP_PIN(5, 20), /* MSIOF0_TXD */ 6125 [ 1] = RCAR_GP_PIN(5, 21), /* MSIOF0_SS2 */ 6126 [ 2] = RCAR_GP_PIN(5, 22), /* MSIOF0_RXD */ 6127 [ 3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */ 6128 [ 4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */ 6129 [ 5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */ 6130 [ 6] = PIN_MLB_REF, /* MLB_REF */ 6131 [ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */ 6132 [ 8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */ 6133 [ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */ 6134 [10] = RCAR_GP_PIN(6, 3), /* SSI_SDATA1_A */ 6135 [11] = RCAR_GP_PIN(6, 4), /* SSI_SDATA2_A */ 6136 [12] = RCAR_GP_PIN(6, 5), /* SSI_SCK349 */ 6137 [13] = RCAR_GP_PIN(6, 6), /* SSI_WS349 */ 6138 [14] = RCAR_GP_PIN(6, 7), /* SSI_SDATA3 */ 6139 [15] = RCAR_GP_PIN(6, 8), /* SSI_SCK4 */ 6140 [16] = RCAR_GP_PIN(6, 9), /* SSI_WS4 */ 6141 [17] = RCAR_GP_PIN(6, 10), /* SSI_SDATA4 */ 6142 [18] = RCAR_GP_PIN(6, 11), /* SSI_SCK5 */ 6143 [19] = RCAR_GP_PIN(6, 12), /* SSI_WS5 */ 6144 [20] = RCAR_GP_PIN(6, 13), /* SSI_SDATA5 */ 6145 [21] = RCAR_GP_PIN(6, 14), /* SSI_SCK6 */ 6146 [22] = RCAR_GP_PIN(6, 15), /* SSI_WS6 */ 6147 [23] = RCAR_GP_PIN(6, 16), /* SSI_SDATA6 */ 6148 [24] = RCAR_GP_PIN(6, 17), /* SSI_SCK78 */ 6149 [25] = RCAR_GP_PIN(6, 18), /* SSI_WS78 */ 6150 [26] = RCAR_GP_PIN(6, 19), /* SSI_SDATA7 */ 6151 [27] = RCAR_GP_PIN(6, 20), /* SSI_SDATA8 */ 6152 [28] = RCAR_GP_PIN(6, 21), /* SSI_SDATA9_A */ 6153 [29] = RCAR_GP_PIN(6, 22), /* AUDIO_CLKA_A */ 6154 [30] = RCAR_GP_PIN(6, 23), /* AUDIO_CLKB_B */ 6155 [31] = RCAR_GP_PIN(6, 24), /* USB0_PWEN */ 6156 } }, 6157 { PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) { 6158 [ 0] = RCAR_GP_PIN(6, 25), /* USB0_OVC */ 6159 [ 1] = RCAR_GP_PIN(6, 26), /* USB1_PWEN */ 6160 [ 2] = RCAR_GP_PIN(6, 27), /* USB1_OVC */ 6161 [ 3] = RCAR_GP_PIN(6, 28), /* USB30_PWEN */ 6162 [ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */ 6163 [ 5] = RCAR_GP_PIN(6, 30), /* USB2_CH3_PWEN */ 6164 [ 6] = RCAR_GP_PIN(6, 31), /* USB2_CH3_OVC */ 6165 [ 7] = SH_PFC_PIN_NONE, 6166 [ 8] = SH_PFC_PIN_NONE, 6167 [ 9] = SH_PFC_PIN_NONE, 6168 [10] = SH_PFC_PIN_NONE, 6169 [11] = SH_PFC_PIN_NONE, 6170 [12] = SH_PFC_PIN_NONE, 6171 [13] = SH_PFC_PIN_NONE, 6172 [14] = SH_PFC_PIN_NONE, 6173 [15] = SH_PFC_PIN_NONE, 6174 [16] = SH_PFC_PIN_NONE, 6175 [17] = SH_PFC_PIN_NONE, 6176 [18] = SH_PFC_PIN_NONE, 6177 [19] = SH_PFC_PIN_NONE, 6178 [20] = SH_PFC_PIN_NONE, 6179 [21] = SH_PFC_PIN_NONE, 6180 [22] = SH_PFC_PIN_NONE, 6181 [23] = SH_PFC_PIN_NONE, 6182 [24] = SH_PFC_PIN_NONE, 6183 [25] = SH_PFC_PIN_NONE, 6184 [26] = SH_PFC_PIN_NONE, 6185 [27] = SH_PFC_PIN_NONE, 6186 [28] = SH_PFC_PIN_NONE, 6187 [29] = SH_PFC_PIN_NONE, 6188 [30] = SH_PFC_PIN_NONE, 6189 [31] = SH_PFC_PIN_NONE, 6190 } }, 6191 { /* sentinel */ }, 6192 }; 6193 6194 static unsigned int r8a77951_pinmux_get_bias(struct sh_pfc *pfc, 6195 unsigned int pin) 6196 { 6197 const struct pinmux_bias_reg *reg; 6198 unsigned int bit; 6199 6200 reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit); 6201 if (!reg) 6202 return PIN_CONFIG_BIAS_DISABLE; 6203 6204 if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit))) 6205 return PIN_CONFIG_BIAS_DISABLE; 6206 else if (sh_pfc_read(pfc, reg->pud) & BIT(bit)) 6207 return PIN_CONFIG_BIAS_PULL_UP; 6208 else 6209 return PIN_CONFIG_BIAS_PULL_DOWN; 6210 } 6211 6212 static void r8a77951_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, 6213 unsigned int bias) 6214 { 6215 const struct pinmux_bias_reg *reg; 6216 u32 enable, updown; 6217 unsigned int bit; 6218 6219 reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit); 6220 if (!reg) 6221 return; 6222 6223 enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit); 6224 if (bias != PIN_CONFIG_BIAS_DISABLE) 6225 enable |= BIT(bit); 6226 6227 updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit); 6228 if (bias == PIN_CONFIG_BIAS_PULL_UP) 6229 updown |= BIT(bit); 6230 6231 sh_pfc_write(pfc, reg->pud, updown); 6232 sh_pfc_write(pfc, reg->puen, enable); 6233 } 6234 6235 static const struct sh_pfc_soc_operations r8a77951_pinmux_ops = { 6236 .pin_to_pocctrl = r8a77951_pin_to_pocctrl, 6237 .get_bias = r8a77951_pinmux_get_bias, 6238 .set_bias = r8a77951_pinmux_set_bias, 6239 }; 6240 6241 #ifdef CONFIG_PINCTRL_PFC_R8A774E1 6242 const struct sh_pfc_soc_info r8a774e1_pinmux_info = { 6243 .name = "r8a774e1_pfc", 6244 .ops = &r8a77951_pinmux_ops, 6245 .unlock_reg = 0xe6060000, /* PMMR */ 6246 6247 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 6248 6249 .pins = pinmux_pins, 6250 .nr_pins = ARRAY_SIZE(pinmux_pins), 6251 .groups = pinmux_groups.common, 6252 .nr_groups = ARRAY_SIZE(pinmux_groups.common), 6253 .functions = pinmux_functions.common, 6254 .nr_functions = ARRAY_SIZE(pinmux_functions.common), 6255 6256 .cfg_regs = pinmux_config_regs, 6257 .drive_regs = pinmux_drive_regs, 6258 .bias_regs = pinmux_bias_regs, 6259 .ioctrl_regs = pinmux_ioctrl_regs, 6260 6261 .pinmux_data = pinmux_data, 6262 .pinmux_data_size = ARRAY_SIZE(pinmux_data), 6263 }; 6264 #endif 6265 6266 #ifdef CONFIG_PINCTRL_PFC_R8A77951 6267 const struct sh_pfc_soc_info r8a77951_pinmux_info = { 6268 .name = "r8a77951_pfc", 6269 .ops = &r8a77951_pinmux_ops, 6270 .unlock_reg = 0xe6060000, /* PMMR */ 6271 6272 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 6273 6274 .pins = pinmux_pins, 6275 .nr_pins = ARRAY_SIZE(pinmux_pins), 6276 .groups = pinmux_groups.common, 6277 .nr_groups = ARRAY_SIZE(pinmux_groups.common) + 6278 ARRAY_SIZE(pinmux_groups.automotive), 6279 .functions = pinmux_functions.common, 6280 .nr_functions = ARRAY_SIZE(pinmux_functions.common) + 6281 ARRAY_SIZE(pinmux_functions.automotive), 6282 6283 .cfg_regs = pinmux_config_regs, 6284 .drive_regs = pinmux_drive_regs, 6285 .bias_regs = pinmux_bias_regs, 6286 .ioctrl_regs = pinmux_ioctrl_regs, 6287 6288 .pinmux_data = pinmux_data, 6289 .pinmux_data_size = ARRAY_SIZE(pinmux_data), 6290 }; 6291 #endif 6292