1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * R8A77951 processor support - PFC hardware block. 4 * 5 * Copyright (C) 2015-2019 Renesas Electronics Corporation 6 */ 7 8 #include <linux/errno.h> 9 #include <linux/kernel.h> 10 #include <linux/sys_soc.h> 11 12 #include "core.h" 13 #include "sh_pfc.h" 14 15 #define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN) 16 17 #define CPU_ALL_GP(fn, sfx) \ 18 PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \ 19 PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \ 20 PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \ 21 PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \ 22 PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \ 23 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \ 24 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \ 25 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \ 26 PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \ 27 PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \ 28 PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \ 29 PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS) 30 31 #define CPU_ALL_NOGP(fn) \ 32 PIN_NOGP_CFG(ASEBRK, "ASEBRK", fn, CFG_FLAGS), \ 33 PIN_NOGP_CFG(AVB_MDIO, "AVB_MDIO", fn, CFG_FLAGS), \ 34 PIN_NOGP_CFG(AVB_RD0, "AVB_RD0", fn, CFG_FLAGS), \ 35 PIN_NOGP_CFG(AVB_RD1, "AVB_RD1", fn, CFG_FLAGS), \ 36 PIN_NOGP_CFG(AVB_RD2, "AVB_RD2", fn, CFG_FLAGS), \ 37 PIN_NOGP_CFG(AVB_RD3, "AVB_RD3", fn, CFG_FLAGS), \ 38 PIN_NOGP_CFG(AVB_RXC, "AVB_RXC", fn, CFG_FLAGS), \ 39 PIN_NOGP_CFG(AVB_RX_CTL, "AVB_RX_CTL", fn, CFG_FLAGS), \ 40 PIN_NOGP_CFG(AVB_TD0, "AVB_TD0", fn, CFG_FLAGS), \ 41 PIN_NOGP_CFG(AVB_TD1, "AVB_TD1", fn, CFG_FLAGS), \ 42 PIN_NOGP_CFG(AVB_TD2, "AVB_TD2", fn, CFG_FLAGS), \ 43 PIN_NOGP_CFG(AVB_TD3, "AVB_TD3", fn, CFG_FLAGS), \ 44 PIN_NOGP_CFG(AVB_TXC, "AVB_TXC", fn, CFG_FLAGS), \ 45 PIN_NOGP_CFG(AVB_TXCREFCLK, "AVB_TXCREFCLK", fn, CFG_FLAGS), \ 46 PIN_NOGP_CFG(AVB_TX_CTL, "AVB_TX_CTL", fn, CFG_FLAGS), \ 47 PIN_NOGP_CFG(DU_DOTCLKIN0, "DU_DOTCLKIN0", fn, CFG_FLAGS), \ 48 PIN_NOGP_CFG(DU_DOTCLKIN1, "DU_DOTCLKIN1", fn, CFG_FLAGS), \ 49 PIN_NOGP_CFG(DU_DOTCLKIN2, "DU_DOTCLKIN2", fn, CFG_FLAGS), \ 50 PIN_NOGP_CFG(DU_DOTCLKIN3, "DU_DOTCLKIN3", fn, CFG_FLAGS), \ 51 PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),\ 52 PIN_NOGP_CFG(FSCLKST_N, "FSCLKST#", fn, CFG_FLAGS), \ 53 PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS), \ 54 PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, CFG_FLAGS), \ 55 PIN_NOGP_CFG(QSPI0_IO2, "QSPI0_IO2", fn, CFG_FLAGS), \ 56 PIN_NOGP_CFG(QSPI0_IO3, "QSPI0_IO3", fn, CFG_FLAGS), \ 57 PIN_NOGP_CFG(QSPI0_MISO_IO1, "QSPI0_MISO_IO1", fn, CFG_FLAGS), \ 58 PIN_NOGP_CFG(QSPI0_MOSI_IO0, "QSPI0_MOSI_IO0", fn, CFG_FLAGS), \ 59 PIN_NOGP_CFG(QSPI0_SPCLK, "QSPI0_SPCLK", fn, CFG_FLAGS), \ 60 PIN_NOGP_CFG(QSPI0_SSL, "QSPI0_SSL", fn, CFG_FLAGS), \ 61 PIN_NOGP_CFG(QSPI1_IO2, "QSPI1_IO2", fn, CFG_FLAGS), \ 62 PIN_NOGP_CFG(QSPI1_IO3, "QSPI1_IO3", fn, CFG_FLAGS), \ 63 PIN_NOGP_CFG(QSPI1_MISO_IO1, "QSPI1_MISO_IO1", fn, CFG_FLAGS), \ 64 PIN_NOGP_CFG(QSPI1_MOSI_IO0, "QSPI1_MOSI_IO0", fn, CFG_FLAGS), \ 65 PIN_NOGP_CFG(QSPI1_SPCLK, "QSPI1_SPCLK", fn, CFG_FLAGS), \ 66 PIN_NOGP_CFG(QSPI1_SSL, "QSPI1_SSL", fn, CFG_FLAGS), \ 67 PIN_NOGP_CFG(RPC_INT_N, "RPC_INT#", fn, CFG_FLAGS), \ 68 PIN_NOGP_CFG(RPC_RESET_N, "RPC_RESET#", fn, CFG_FLAGS), \ 69 PIN_NOGP_CFG(RPC_WP_N, "RPC_WP#", fn, CFG_FLAGS), \ 70 PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ 71 PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ 72 PIN_NOGP_CFG(TDO, "TDO", fn, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \ 73 PIN_NOGP_CFG(TMS, "TMS", fn, CFG_FLAGS), \ 74 PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN) 75 76 /* 77 * F_() : just information 78 * FM() : macro for FN_xxx / xxx_MARK 79 */ 80 81 /* GPSR0 */ 82 #define GPSR0_15 F_(D15, IP7_11_8) 83 #define GPSR0_14 F_(D14, IP7_7_4) 84 #define GPSR0_13 F_(D13, IP7_3_0) 85 #define GPSR0_12 F_(D12, IP6_31_28) 86 #define GPSR0_11 F_(D11, IP6_27_24) 87 #define GPSR0_10 F_(D10, IP6_23_20) 88 #define GPSR0_9 F_(D9, IP6_19_16) 89 #define GPSR0_8 F_(D8, IP6_15_12) 90 #define GPSR0_7 F_(D7, IP6_11_8) 91 #define GPSR0_6 F_(D6, IP6_7_4) 92 #define GPSR0_5 F_(D5, IP6_3_0) 93 #define GPSR0_4 F_(D4, IP5_31_28) 94 #define GPSR0_3 F_(D3, IP5_27_24) 95 #define GPSR0_2 F_(D2, IP5_23_20) 96 #define GPSR0_1 F_(D1, IP5_19_16) 97 #define GPSR0_0 F_(D0, IP5_15_12) 98 99 /* GPSR1 */ 100 #define GPSR1_28 FM(CLKOUT) 101 #define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8) 102 #define GPSR1_26 F_(WE1_N, IP5_7_4) 103 #define GPSR1_25 F_(WE0_N, IP5_3_0) 104 #define GPSR1_24 F_(RD_WR_N, IP4_31_28) 105 #define GPSR1_23 F_(RD_N, IP4_27_24) 106 #define GPSR1_22 F_(BS_N, IP4_23_20) 107 #define GPSR1_21 F_(CS1_N, IP4_19_16) 108 #define GPSR1_20 F_(CS0_N, IP4_15_12) 109 #define GPSR1_19 F_(A19, IP4_11_8) 110 #define GPSR1_18 F_(A18, IP4_7_4) 111 #define GPSR1_17 F_(A17, IP4_3_0) 112 #define GPSR1_16 F_(A16, IP3_31_28) 113 #define GPSR1_15 F_(A15, IP3_27_24) 114 #define GPSR1_14 F_(A14, IP3_23_20) 115 #define GPSR1_13 F_(A13, IP3_19_16) 116 #define GPSR1_12 F_(A12, IP3_15_12) 117 #define GPSR1_11 F_(A11, IP3_11_8) 118 #define GPSR1_10 F_(A10, IP3_7_4) 119 #define GPSR1_9 F_(A9, IP3_3_0) 120 #define GPSR1_8 F_(A8, IP2_31_28) 121 #define GPSR1_7 F_(A7, IP2_27_24) 122 #define GPSR1_6 F_(A6, IP2_23_20) 123 #define GPSR1_5 F_(A5, IP2_19_16) 124 #define GPSR1_4 F_(A4, IP2_15_12) 125 #define GPSR1_3 F_(A3, IP2_11_8) 126 #define GPSR1_2 F_(A2, IP2_7_4) 127 #define GPSR1_1 F_(A1, IP2_3_0) 128 #define GPSR1_0 F_(A0, IP1_31_28) 129 130 /* GPSR2 */ 131 #define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20) 132 #define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16) 133 #define GPSR2_12 F_(AVB_LINK, IP0_15_12) 134 #define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8) 135 #define GPSR2_10 F_(AVB_MAGIC, IP0_7_4) 136 #define GPSR2_9 F_(AVB_MDC, IP0_3_0) 137 #define GPSR2_8 F_(PWM2_A, IP1_27_24) 138 #define GPSR2_7 F_(PWM1_A, IP1_23_20) 139 #define GPSR2_6 F_(PWM0, IP1_19_16) 140 #define GPSR2_5 F_(IRQ5, IP1_15_12) 141 #define GPSR2_4 F_(IRQ4, IP1_11_8) 142 #define GPSR2_3 F_(IRQ3, IP1_7_4) 143 #define GPSR2_2 F_(IRQ2, IP1_3_0) 144 #define GPSR2_1 F_(IRQ1, IP0_31_28) 145 #define GPSR2_0 F_(IRQ0, IP0_27_24) 146 147 /* GPSR3 */ 148 #define GPSR3_15 F_(SD1_WP, IP11_23_20) 149 #define GPSR3_14 F_(SD1_CD, IP11_19_16) 150 #define GPSR3_13 F_(SD0_WP, IP11_15_12) 151 #define GPSR3_12 F_(SD0_CD, IP11_11_8) 152 #define GPSR3_11 F_(SD1_DAT3, IP8_31_28) 153 #define GPSR3_10 F_(SD1_DAT2, IP8_27_24) 154 #define GPSR3_9 F_(SD1_DAT1, IP8_23_20) 155 #define GPSR3_8 F_(SD1_DAT0, IP8_19_16) 156 #define GPSR3_7 F_(SD1_CMD, IP8_15_12) 157 #define GPSR3_6 F_(SD1_CLK, IP8_11_8) 158 #define GPSR3_5 F_(SD0_DAT3, IP8_7_4) 159 #define GPSR3_4 F_(SD0_DAT2, IP8_3_0) 160 #define GPSR3_3 F_(SD0_DAT1, IP7_31_28) 161 #define GPSR3_2 F_(SD0_DAT0, IP7_27_24) 162 #define GPSR3_1 F_(SD0_CMD, IP7_23_20) 163 #define GPSR3_0 F_(SD0_CLK, IP7_19_16) 164 165 /* GPSR4 */ 166 #define GPSR4_17 F_(SD3_DS, IP11_7_4) 167 #define GPSR4_16 F_(SD3_DAT7, IP11_3_0) 168 #define GPSR4_15 F_(SD3_DAT6, IP10_31_28) 169 #define GPSR4_14 F_(SD3_DAT5, IP10_27_24) 170 #define GPSR4_13 F_(SD3_DAT4, IP10_23_20) 171 #define GPSR4_12 F_(SD3_DAT3, IP10_19_16) 172 #define GPSR4_11 F_(SD3_DAT2, IP10_15_12) 173 #define GPSR4_10 F_(SD3_DAT1, IP10_11_8) 174 #define GPSR4_9 F_(SD3_DAT0, IP10_7_4) 175 #define GPSR4_8 F_(SD3_CMD, IP10_3_0) 176 #define GPSR4_7 F_(SD3_CLK, IP9_31_28) 177 #define GPSR4_6 F_(SD2_DS, IP9_27_24) 178 #define GPSR4_5 F_(SD2_DAT3, IP9_23_20) 179 #define GPSR4_4 F_(SD2_DAT2, IP9_19_16) 180 #define GPSR4_3 F_(SD2_DAT1, IP9_15_12) 181 #define GPSR4_2 F_(SD2_DAT0, IP9_11_8) 182 #define GPSR4_1 F_(SD2_CMD, IP9_7_4) 183 #define GPSR4_0 F_(SD2_CLK, IP9_3_0) 184 185 /* GPSR5 */ 186 #define GPSR5_25 F_(MLB_DAT, IP14_19_16) 187 #define GPSR5_24 F_(MLB_SIG, IP14_15_12) 188 #define GPSR5_23 F_(MLB_CLK, IP14_11_8) 189 #define GPSR5_22 FM(MSIOF0_RXD) 190 #define GPSR5_21 F_(MSIOF0_SS2, IP14_7_4) 191 #define GPSR5_20 FM(MSIOF0_TXD) 192 #define GPSR5_19 F_(MSIOF0_SS1, IP14_3_0) 193 #define GPSR5_18 F_(MSIOF0_SYNC, IP13_31_28) 194 #define GPSR5_17 FM(MSIOF0_SCK) 195 #define GPSR5_16 F_(HRTS0_N, IP13_27_24) 196 #define GPSR5_15 F_(HCTS0_N, IP13_23_20) 197 #define GPSR5_14 F_(HTX0, IP13_19_16) 198 #define GPSR5_13 F_(HRX0, IP13_15_12) 199 #define GPSR5_12 F_(HSCK0, IP13_11_8) 200 #define GPSR5_11 F_(RX2_A, IP13_7_4) 201 #define GPSR5_10 F_(TX2_A, IP13_3_0) 202 #define GPSR5_9 F_(SCK2, IP12_31_28) 203 #define GPSR5_8 F_(RTS1_N, IP12_27_24) 204 #define GPSR5_7 F_(CTS1_N, IP12_23_20) 205 #define GPSR5_6 F_(TX1_A, IP12_19_16) 206 #define GPSR5_5 F_(RX1_A, IP12_15_12) 207 #define GPSR5_4 F_(RTS0_N, IP12_11_8) 208 #define GPSR5_3 F_(CTS0_N, IP12_7_4) 209 #define GPSR5_2 F_(TX0, IP12_3_0) 210 #define GPSR5_1 F_(RX0, IP11_31_28) 211 #define GPSR5_0 F_(SCK0, IP11_27_24) 212 213 /* GPSR6 */ 214 #define GPSR6_31 F_(USB2_CH3_OVC, IP18_7_4) 215 #define GPSR6_30 F_(USB2_CH3_PWEN, IP18_3_0) 216 #define GPSR6_29 F_(USB30_OVC, IP17_31_28) 217 #define GPSR6_28 F_(USB30_PWEN, IP17_27_24) 218 #define GPSR6_27 F_(USB1_OVC, IP17_23_20) 219 #define GPSR6_26 F_(USB1_PWEN, IP17_19_16) 220 #define GPSR6_25 F_(USB0_OVC, IP17_15_12) 221 #define GPSR6_24 F_(USB0_PWEN, IP17_11_8) 222 #define GPSR6_23 F_(AUDIO_CLKB_B, IP17_7_4) 223 #define GPSR6_22 F_(AUDIO_CLKA_A, IP17_3_0) 224 #define GPSR6_21 F_(SSI_SDATA9_A, IP16_31_28) 225 #define GPSR6_20 F_(SSI_SDATA8, IP16_27_24) 226 #define GPSR6_19 F_(SSI_SDATA7, IP16_23_20) 227 #define GPSR6_18 F_(SSI_WS78, IP16_19_16) 228 #define GPSR6_17 F_(SSI_SCK78, IP16_15_12) 229 #define GPSR6_16 F_(SSI_SDATA6, IP16_11_8) 230 #define GPSR6_15 F_(SSI_WS6, IP16_7_4) 231 #define GPSR6_14 F_(SSI_SCK6, IP16_3_0) 232 #define GPSR6_13 FM(SSI_SDATA5) 233 #define GPSR6_12 FM(SSI_WS5) 234 #define GPSR6_11 FM(SSI_SCK5) 235 #define GPSR6_10 F_(SSI_SDATA4, IP15_31_28) 236 #define GPSR6_9 F_(SSI_WS4, IP15_27_24) 237 #define GPSR6_8 F_(SSI_SCK4, IP15_23_20) 238 #define GPSR6_7 F_(SSI_SDATA3, IP15_19_16) 239 #define GPSR6_6 F_(SSI_WS349, IP15_15_12) 240 #define GPSR6_5 F_(SSI_SCK349, IP15_11_8) 241 #define GPSR6_4 F_(SSI_SDATA2_A, IP15_7_4) 242 #define GPSR6_3 F_(SSI_SDATA1_A, IP15_3_0) 243 #define GPSR6_2 F_(SSI_SDATA0, IP14_31_28) 244 #define GPSR6_1 F_(SSI_WS01239, IP14_27_24) 245 #define GPSR6_0 F_(SSI_SCK01239, IP14_23_20) 246 247 /* GPSR7 */ 248 #define GPSR7_3 FM(GP7_03) 249 #define GPSR7_2 FM(GP7_02) 250 #define GPSR7_1 FM(AVS2) 251 #define GPSR7_0 FM(AVS1) 252 253 254 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ 255 #define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 256 #define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 257 #define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 258 #define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 259 #define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) FM(FSCLKST2_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 260 #define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 261 #define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 262 #define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 263 #define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 264 #define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) F_(0, 0) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 265 #define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) F_(0, 0) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 266 #define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) F_(0, 0) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) FM(FSCLKST2_N_B) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 267 #define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)F_(0, 0) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 268 #define IP1_23_20 FM(PWM1_A) F_(0, 0) F_(0, 0) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 269 #define IP1_27_24 FM(PWM2_A) F_(0, 0) F_(0, 0) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 270 #define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 271 #define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 272 #define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 273 #define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 274 275 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ 276 #define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 277 #define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 278 #define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 279 #define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 280 #define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 281 #define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 282 #define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 283 #define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 284 #define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 285 #define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 286 #define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 287 #define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 288 #define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 289 #define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 290 #define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 291 #define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 292 #define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 293 #define IP4_19_16 FM(CS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 294 #define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 295 #define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 296 #define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 297 #define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 298 #define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 299 #define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 300 #define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 301 #define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 302 #define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 303 #define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 304 #define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 305 #define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 306 #define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 307 #define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 308 #define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 309 #define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 310 #define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 311 #define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_C) FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 312 #define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 313 #define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 314 #define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 315 #define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 316 #define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 317 318 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ 319 #define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 320 #define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 321 #define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 322 #define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 323 #define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 324 #define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 325 #define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) FM(NFCE_N_B) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 326 #define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) FM(NFWP_N_B) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 327 #define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) FM(NFDATA14_B) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 328 #define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) FM(NFDATA15_B) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 329 #define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) FM(NFRB_N_B) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 330 #define IP9_3_0 FM(SD2_CLK) F_(0, 0) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 331 #define IP9_7_4 FM(SD2_CMD) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 332 #define IP9_11_8 FM(SD2_DAT0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 333 #define IP9_15_12 FM(SD2_DAT1) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 334 #define IP9_19_16 FM(SD2_DAT2) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 335 #define IP9_23_20 FM(SD2_DAT3) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 336 #define IP9_27_24 FM(SD2_DS) F_(0, 0) FM(NFALE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 337 #define IP9_31_28 FM(SD3_CLK) F_(0, 0) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 338 #define IP10_3_0 FM(SD3_CMD) F_(0, 0) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 339 #define IP10_7_4 FM(SD3_DAT0) F_(0, 0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 340 #define IP10_11_8 FM(SD3_DAT1) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 341 #define IP10_15_12 FM(SD3_DAT2) F_(0, 0) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 342 #define IP10_19_16 FM(SD3_DAT3) F_(0, 0) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 343 #define IP10_23_20 FM(SD3_DAT4) FM(SD2_CD_A) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 344 #define IP10_27_24 FM(SD3_DAT5) FM(SD2_WP_A) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 345 #define IP10_31_28 FM(SD3_DAT6) FM(SD3_CD) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 346 #define IP11_3_0 FM(SD3_DAT7) FM(SD3_WP) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 347 #define IP11_7_4 FM(SD3_DS) F_(0, 0) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 348 #define IP11_11_8 FM(SD0_CD) F_(0, 0) FM(NFDATA14_A) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 349 350 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ 351 #define IP11_15_12 FM(SD0_WP) F_(0, 0) FM(NFDATA15_A) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 352 #define IP11_19_16 FM(SD1_CD) F_(0, 0) FM(NFRB_N_A) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 353 #define IP11_23_20 FM(SD1_WP) F_(0, 0) FM(NFCE_N_A) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 354 #define IP11_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 355 #define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 356 #define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 357 #define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 358 #define IP12_11_8 FM(RTS0_N) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 359 #define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 360 #define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 361 #define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 362 #define IP12_27_24 FM(RTS1_N) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 363 #define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 364 #define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 365 #define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 366 #define IP13_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 367 #define IP13_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 368 #define IP13_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 369 #define IP13_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 370 #define IP13_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 371 #define IP13_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) FM(TX5_B) F_(0, 0) F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0) 372 #define IP14_3_0 FM(MSIOF0_SS1) FM(RX5_A) FM(NFWP_N_A) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 373 #define IP14_7_4 FM(MSIOF0_SS2) FM(TX5_A) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 374 #define IP14_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 375 #define IP14_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 376 #define IP14_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 377 #define IP14_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 378 #define IP14_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 379 380 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ 381 #define IP14_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 382 #define IP15_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 383 #define IP15_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 384 #define IP15_11_8 FM(SSI_SCK349) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 385 #define IP15_15_12 FM(SSI_WS349) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 386 #define IP15_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 387 #define IP15_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 388 #define IP15_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 389 #define IP15_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 390 #define IP16_3_0 FM(SSI_SCK6) FM(USB2_PWEN) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 391 #define IP16_7_4 FM(SSI_WS6) FM(USB2_OVC) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 392 #define IP16_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 393 #define IP16_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 394 #define IP16_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 395 #define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 396 #define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 397 #define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 398 #define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 399 #define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 400 #define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0) 401 #define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0) 402 #define IP17_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0) 403 #define IP17_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0) 404 #define IP17_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0) 405 #define IP17_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_N) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 406 #define IP18_3_0 FM(USB2_CH3_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0) 407 #define IP18_7_4 FM(USB2_CH3_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0) 408 409 #define PINMUX_GPSR \ 410 \ 411 GPSR6_31 \ 412 GPSR6_30 \ 413 GPSR6_29 \ 414 GPSR1_28 GPSR6_28 \ 415 GPSR1_27 GPSR6_27 \ 416 GPSR1_26 GPSR6_26 \ 417 GPSR1_25 GPSR5_25 GPSR6_25 \ 418 GPSR1_24 GPSR5_24 GPSR6_24 \ 419 GPSR1_23 GPSR5_23 GPSR6_23 \ 420 GPSR1_22 GPSR5_22 GPSR6_22 \ 421 GPSR1_21 GPSR5_21 GPSR6_21 \ 422 GPSR1_20 GPSR5_20 GPSR6_20 \ 423 GPSR1_19 GPSR5_19 GPSR6_19 \ 424 GPSR1_18 GPSR5_18 GPSR6_18 \ 425 GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \ 426 GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \ 427 GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \ 428 GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \ 429 GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \ 430 GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \ 431 GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \ 432 GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \ 433 GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \ 434 GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \ 435 GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \ 436 GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \ 437 GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \ 438 GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \ 439 GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \ 440 GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \ 441 GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \ 442 GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0 443 444 #define PINMUX_IPSR \ 445 \ 446 FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \ 447 FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \ 448 FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \ 449 FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \ 450 FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \ 451 FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \ 452 FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \ 453 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \ 454 \ 455 FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \ 456 FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \ 457 FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \ 458 FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 \ 459 FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \ 460 FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \ 461 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \ 462 FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \ 463 \ 464 FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \ 465 FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \ 466 FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \ 467 FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \ 468 FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \ 469 FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \ 470 FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \ 471 FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \ 472 \ 473 FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \ 474 FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \ 475 FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \ 476 FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \ 477 FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \ 478 FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \ 479 FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \ 480 FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \ 481 \ 482 FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 FM(IP18_3_0) IP18_3_0 \ 483 FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 FM(IP18_7_4) IP18_7_4 \ 484 FM(IP16_11_8) IP16_11_8 FM(IP17_11_8) IP17_11_8 \ 485 FM(IP16_15_12) IP16_15_12 FM(IP17_15_12) IP17_15_12 \ 486 FM(IP16_19_16) IP16_19_16 FM(IP17_19_16) IP17_19_16 \ 487 FM(IP16_23_20) IP16_23_20 FM(IP17_23_20) IP17_23_20 \ 488 FM(IP16_27_24) IP16_27_24 FM(IP17_27_24) IP17_27_24 \ 489 FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28 490 491 /* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ 492 #define MOD_SEL0_31_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3) FM(SEL_MSIOF3_4) F_(0, 0) F_(0, 0) F_(0, 0) 493 #define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3) 494 #define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0) 495 #define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1) 496 #define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1) 497 #define MOD_SEL0_21 FM(SEL_I2C2_0) FM(SEL_I2C2_1) 498 #define MOD_SEL0_20 FM(SEL_I2C1_0) FM(SEL_I2C1_1) 499 #define MOD_SEL0_19 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1) 500 #define MOD_SEL0_18_17 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3) 501 #define MOD_SEL0_16 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1) 502 #define MOD_SEL0_14_13 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) FM(SEL_HSCIF2_2) F_(0, 0) 503 #define MOD_SEL0_12 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1) 504 #define MOD_SEL0_11 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1) 505 #define MOD_SEL0_10 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1) 506 #define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0) 507 #define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0) 508 #define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1) 509 #define MOD_SEL0_4_3 FM(SEL_ADGA_0) FM(SEL_ADGA_1) FM(SEL_ADGA_2) FM(SEL_ADGA_3) 510 511 /* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ 512 #define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3) 513 #define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0) 514 #define MOD_SEL1_26 FM(SEL_TIMER_TMU1_0) FM(SEL_TIMER_TMU1_1) 515 #define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3) 516 #define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0) 517 #define MOD_SEL1_20 FM(SEL_SSI1_0) FM(SEL_SSI1_1) 518 #define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1) 519 #define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3) 520 #define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1) 521 #define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0) 522 #define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1) 523 #define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1) 524 #define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1) 525 #define MOD_SEL1_10 FM(SEL_SCIF_0) FM(SEL_SCIF_1) 526 #define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1) 527 #define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1) 528 #define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1) 529 #define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1) 530 #define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1) 531 #define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1) 532 #define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1) 533 #define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1) 534 535 /* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ 536 #define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1) 537 #define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1) 538 #define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1) 539 #define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3) 540 #define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1) 541 #define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 542 #define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1) 543 #define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1) 544 #define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1) 545 #define MOD_SEL2_18 FM(SEL_ADGB_0) FM(SEL_ADGB_1) 546 #define MOD_SEL2_17 FM(SEL_ADGC_0) FM(SEL_ADGC_1) 547 #define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1) 548 549 #define PINMUX_MOD_SELS \ 550 \ 551 MOD_SEL0_31_30_29 MOD_SEL1_31_30 MOD_SEL2_31 \ 552 MOD_SEL2_30 \ 553 MOD_SEL1_29_28_27 MOD_SEL2_29 \ 554 MOD_SEL0_28_27 MOD_SEL2_28_27 \ 555 MOD_SEL0_26_25_24 MOD_SEL1_26 MOD_SEL2_26 \ 556 MOD_SEL1_25_24 MOD_SEL2_25_24_23 \ 557 MOD_SEL0_23 MOD_SEL1_23_22_21 \ 558 MOD_SEL0_22 \ 559 MOD_SEL0_21 MOD_SEL2_21 \ 560 MOD_SEL0_20 MOD_SEL1_20 MOD_SEL2_20 \ 561 MOD_SEL0_19 MOD_SEL1_19 MOD_SEL2_19 \ 562 MOD_SEL0_18_17 MOD_SEL1_18_17 MOD_SEL2_18 \ 563 MOD_SEL2_17 \ 564 MOD_SEL0_16 MOD_SEL1_16 \ 565 MOD_SEL1_15_14 \ 566 MOD_SEL0_14_13 \ 567 MOD_SEL1_13 \ 568 MOD_SEL0_12 MOD_SEL1_12 \ 569 MOD_SEL0_11 MOD_SEL1_11 \ 570 MOD_SEL0_10 MOD_SEL1_10 \ 571 MOD_SEL0_9_8 MOD_SEL1_9 \ 572 MOD_SEL0_7_6 \ 573 MOD_SEL1_6 \ 574 MOD_SEL0_5 MOD_SEL1_5 \ 575 MOD_SEL0_4_3 MOD_SEL1_4 \ 576 MOD_SEL1_3 \ 577 MOD_SEL1_2 \ 578 MOD_SEL1_1 \ 579 MOD_SEL1_0 MOD_SEL2_0 580 581 /* 582 * These pins are not able to be muxed but have other properties 583 * that can be set, such as drive-strength or pull-up/pull-down enable. 584 */ 585 #define PINMUX_STATIC \ 586 FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \ 587 FM(QSPI0_IO2) FM(QSPI0_IO3) \ 588 FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \ 589 FM(QSPI1_IO2) FM(QSPI1_IO3) \ 590 FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \ 591 FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \ 592 FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \ 593 FM(AVB_TXCREFCLK) FM(AVB_MDIO) \ 594 FM(PRESETOUT) \ 595 FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) FM(DU_DOTCLKIN3) \ 596 FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR) 597 598 #define PINMUX_PHYS \ 599 FM(SCL0) FM(SDA0) FM(SCL3) FM(SDA3) FM(SCL5) FM(SDA5) 600 601 enum { 602 PINMUX_RESERVED = 0, 603 604 PINMUX_DATA_BEGIN, 605 GP_ALL(DATA), 606 PINMUX_DATA_END, 607 608 #define F_(x, y) 609 #define FM(x) FN_##x, 610 PINMUX_FUNCTION_BEGIN, 611 GP_ALL(FN), 612 PINMUX_GPSR 613 PINMUX_IPSR 614 PINMUX_MOD_SELS 615 PINMUX_FUNCTION_END, 616 #undef F_ 617 #undef FM 618 619 #define F_(x, y) 620 #define FM(x) x##_MARK, 621 PINMUX_MARK_BEGIN, 622 PINMUX_GPSR 623 PINMUX_IPSR 624 PINMUX_MOD_SELS 625 PINMUX_STATIC 626 PINMUX_PHYS 627 PINMUX_MARK_END, 628 #undef F_ 629 #undef FM 630 }; 631 632 static const u16 pinmux_data[] = { 633 PINMUX_DATA_GP_ALL(), 634 635 PINMUX_SINGLE(AVS1), 636 PINMUX_SINGLE(AVS2), 637 PINMUX_SINGLE(CLKOUT), 638 PINMUX_SINGLE(GP7_02), 639 PINMUX_SINGLE(GP7_03), 640 PINMUX_SINGLE(MSIOF0_RXD), 641 PINMUX_SINGLE(MSIOF0_SCK), 642 PINMUX_SINGLE(MSIOF0_TXD), 643 PINMUX_SINGLE(SSI_SCK5), 644 PINMUX_SINGLE(SSI_SDATA5), 645 PINMUX_SINGLE(SSI_WS5), 646 647 /* IPSR0 */ 648 PINMUX_IPSR_GPSR(IP0_3_0, AVB_MDC), 649 PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2), 650 651 PINMUX_IPSR_GPSR(IP0_7_4, AVB_MAGIC), 652 PINMUX_IPSR_MSEL(IP0_7_4, MSIOF2_SS1_C, SEL_MSIOF2_2), 653 PINMUX_IPSR_MSEL(IP0_7_4, SCK4_A, SEL_SCIF4_0), 654 655 PINMUX_IPSR_GPSR(IP0_11_8, AVB_PHY_INT), 656 PINMUX_IPSR_MSEL(IP0_11_8, MSIOF2_SYNC_C, SEL_MSIOF2_2), 657 PINMUX_IPSR_MSEL(IP0_11_8, RX4_A, SEL_SCIF4_0), 658 659 PINMUX_IPSR_GPSR(IP0_15_12, AVB_LINK), 660 PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2), 661 PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0), 662 663 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, I2C_SEL_5_0, SEL_ETHERAVB_0), 664 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, MSIOF2_RXD_C, I2C_SEL_5_0, SEL_MSIOF2_2), 665 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, CTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0), 666 PINMUX_IPSR_MSEL(IP0_19_16, FSCLKST2_N_A, I2C_SEL_5_0), 667 PINMUX_IPSR_PHYS(IP0_19_16, SCL5, I2C_SEL_5_1), 668 669 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, I2C_SEL_5_0, SEL_ETHERAVB_0), 670 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C, I2C_SEL_5_0, SEL_MSIOF2_2), 671 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0), 672 PINMUX_IPSR_PHYS(IP0_23_20, SDA5, I2C_SEL_5_1), 673 674 PINMUX_IPSR_GPSR(IP0_27_24, IRQ0), 675 PINMUX_IPSR_GPSR(IP0_27_24, QPOLB), 676 PINMUX_IPSR_GPSR(IP0_27_24, DU_CDE), 677 PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1), 678 PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1), 679 PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_B, SEL_CANFD0_1), 680 PINMUX_IPSR_MSEL(IP0_27_24, MSIOF3_SS2_E, SEL_MSIOF3_4), 681 682 PINMUX_IPSR_GPSR(IP0_31_28, IRQ1), 683 PINMUX_IPSR_GPSR(IP0_31_28, QPOLA), 684 PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP), 685 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1), 686 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1), 687 PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1), 688 PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_SS1_E, SEL_MSIOF3_4), 689 690 /* IPSR1 */ 691 PINMUX_IPSR_GPSR(IP1_3_0, IRQ2), 692 PINMUX_IPSR_GPSR(IP1_3_0, QCPV_QDE), 693 PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE), 694 PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1), 695 PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1), 696 PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_SYNC_E, SEL_MSIOF3_4), 697 698 PINMUX_IPSR_GPSR(IP1_7_4, IRQ3), 699 PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE), 700 PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1), 701 PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1), 702 PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1), 703 PINMUX_IPSR_MSEL(IP1_7_4, MSIOF3_SCK_E, SEL_MSIOF3_4), 704 705 PINMUX_IPSR_GPSR(IP1_11_8, IRQ4), 706 PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS), 707 PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC), 708 PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1), 709 PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1), 710 PINMUX_IPSR_MSEL(IP1_11_8, MSIOF3_RXD_E, SEL_MSIOF3_4), 711 712 PINMUX_IPSR_GPSR(IP1_15_12, IRQ5), 713 PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE), 714 PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC), 715 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1), 716 PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1), 717 PINMUX_IPSR_GPSR(IP1_15_12, FSCLKST2_N_B), 718 PINMUX_IPSR_MSEL(IP1_15_12, MSIOF3_TXD_E, SEL_MSIOF3_4), 719 720 PINMUX_IPSR_GPSR(IP1_19_16, PWM0), 721 PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS), 722 PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1), 723 PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1), 724 725 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, PWM1_A, I2C_SEL_3_0, SEL_PWM1_0), 726 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3), 727 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1), 728 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1), 729 PINMUX_IPSR_PHYS(IP1_23_20, SCL3, I2C_SEL_3_1), 730 731 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0), 732 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D, I2C_SEL_3_0, SEL_HSCIF3_3), 733 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, IETX_B, I2C_SEL_3_0, SEL_IEBUS_1), 734 PINMUX_IPSR_PHYS(IP1_27_24, SDA3, I2C_SEL_3_1), 735 736 PINMUX_IPSR_GPSR(IP1_31_28, A0), 737 PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16), 738 PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SYNC_B, SEL_MSIOF3_1), 739 PINMUX_IPSR_GPSR(IP1_31_28, VI4_DATA8), 740 PINMUX_IPSR_GPSR(IP1_31_28, DU_DB0), 741 PINMUX_IPSR_MSEL(IP1_31_28, PWM3_A, SEL_PWM3_0), 742 743 /* IPSR2 */ 744 PINMUX_IPSR_GPSR(IP2_3_0, A1), 745 PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT17), 746 PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_TXD_B, SEL_MSIOF3_1), 747 PINMUX_IPSR_GPSR(IP2_3_0, VI4_DATA9), 748 PINMUX_IPSR_GPSR(IP2_3_0, DU_DB1), 749 PINMUX_IPSR_MSEL(IP2_3_0, PWM4_A, SEL_PWM4_0), 750 751 PINMUX_IPSR_GPSR(IP2_7_4, A2), 752 PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT18), 753 PINMUX_IPSR_MSEL(IP2_7_4, MSIOF3_SCK_B, SEL_MSIOF3_1), 754 PINMUX_IPSR_GPSR(IP2_7_4, VI4_DATA10), 755 PINMUX_IPSR_GPSR(IP2_7_4, DU_DB2), 756 PINMUX_IPSR_MSEL(IP2_7_4, PWM5_A, SEL_PWM5_0), 757 758 PINMUX_IPSR_GPSR(IP2_11_8, A3), 759 PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT19), 760 PINMUX_IPSR_MSEL(IP2_11_8, MSIOF3_RXD_B, SEL_MSIOF3_1), 761 PINMUX_IPSR_GPSR(IP2_11_8, VI4_DATA11), 762 PINMUX_IPSR_GPSR(IP2_11_8, DU_DB3), 763 PINMUX_IPSR_MSEL(IP2_11_8, PWM6_A, SEL_PWM6_0), 764 765 PINMUX_IPSR_GPSR(IP2_15_12, A4), 766 PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT20), 767 PINMUX_IPSR_MSEL(IP2_15_12, MSIOF3_SS1_B, SEL_MSIOF3_1), 768 PINMUX_IPSR_GPSR(IP2_15_12, VI4_DATA12), 769 PINMUX_IPSR_GPSR(IP2_15_12, VI5_DATA12), 770 PINMUX_IPSR_GPSR(IP2_15_12, DU_DB4), 771 772 PINMUX_IPSR_GPSR(IP2_19_16, A5), 773 PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT21), 774 PINMUX_IPSR_MSEL(IP2_19_16, MSIOF3_SS2_B, SEL_MSIOF3_1), 775 PINMUX_IPSR_MSEL(IP2_19_16, SCK4_B, SEL_SCIF4_1), 776 PINMUX_IPSR_GPSR(IP2_19_16, VI4_DATA13), 777 PINMUX_IPSR_GPSR(IP2_19_16, VI5_DATA13), 778 PINMUX_IPSR_GPSR(IP2_19_16, DU_DB5), 779 780 PINMUX_IPSR_GPSR(IP2_23_20, A6), 781 PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT22), 782 PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_SS1_A, SEL_MSIOF2_0), 783 PINMUX_IPSR_MSEL(IP2_23_20, RX4_B, SEL_SCIF4_1), 784 PINMUX_IPSR_GPSR(IP2_23_20, VI4_DATA14), 785 PINMUX_IPSR_GPSR(IP2_23_20, VI5_DATA14), 786 PINMUX_IPSR_GPSR(IP2_23_20, DU_DB6), 787 788 PINMUX_IPSR_GPSR(IP2_27_24, A7), 789 PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT23), 790 PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SS2_A, SEL_MSIOF2_0), 791 PINMUX_IPSR_MSEL(IP2_27_24, TX4_B, SEL_SCIF4_1), 792 PINMUX_IPSR_GPSR(IP2_27_24, VI4_DATA15), 793 PINMUX_IPSR_GPSR(IP2_27_24, VI5_DATA15), 794 PINMUX_IPSR_GPSR(IP2_27_24, DU_DB7), 795 796 PINMUX_IPSR_GPSR(IP2_31_28, A8), 797 PINMUX_IPSR_MSEL(IP2_31_28, RX3_B, SEL_SCIF3_1), 798 PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0), 799 PINMUX_IPSR_MSEL(IP2_31_28, HRX4_B, SEL_HSCIF4_1), 800 PINMUX_IPSR_MSEL(IP2_31_28, SDA6_A, SEL_I2C6_0), 801 PINMUX_IPSR_MSEL(IP2_31_28, AVB_AVTP_MATCH_B, SEL_ETHERAVB_1), 802 PINMUX_IPSR_MSEL(IP2_31_28, PWM1_B, SEL_PWM1_1), 803 804 /* IPSR3 */ 805 PINMUX_IPSR_GPSR(IP3_3_0, A9), 806 PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0), 807 PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1), 808 PINMUX_IPSR_GPSR(IP3_3_0, VI5_VSYNC_N), 809 810 PINMUX_IPSR_GPSR(IP3_7_4, A10), 811 PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0), 812 PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_B, SEL_SCIF4_1), 813 PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N), 814 815 PINMUX_IPSR_GPSR(IP3_11_8, A11), 816 PINMUX_IPSR_MSEL(IP3_11_8, TX3_B, SEL_SCIF3_1), 817 PINMUX_IPSR_MSEL(IP3_11_8, MSIOF2_TXD_A, SEL_MSIOF2_0), 818 PINMUX_IPSR_MSEL(IP3_11_8, HTX4_B, SEL_HSCIF4_1), 819 PINMUX_IPSR_GPSR(IP3_11_8, HSCK4), 820 PINMUX_IPSR_GPSR(IP3_11_8, VI5_FIELD), 821 PINMUX_IPSR_MSEL(IP3_11_8, SCL6_A, SEL_I2C6_0), 822 PINMUX_IPSR_MSEL(IP3_11_8, AVB_AVTP_CAPTURE_B, SEL_ETHERAVB_1), 823 PINMUX_IPSR_MSEL(IP3_11_8, PWM2_B, SEL_PWM2_1), 824 825 PINMUX_IPSR_GPSR(IP3_15_12, A12), 826 PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT12), 827 PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SCK_C, SEL_MSIOF3_2), 828 PINMUX_IPSR_MSEL(IP3_15_12, HRX4_A, SEL_HSCIF4_0), 829 PINMUX_IPSR_GPSR(IP3_15_12, VI5_DATA8), 830 PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4), 831 832 PINMUX_IPSR_GPSR(IP3_19_16, A13), 833 PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT13), 834 PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SYNC_C, SEL_MSIOF3_2), 835 PINMUX_IPSR_MSEL(IP3_19_16, HTX4_A, SEL_HSCIF4_0), 836 PINMUX_IPSR_GPSR(IP3_19_16, VI5_DATA9), 837 PINMUX_IPSR_GPSR(IP3_19_16, DU_DG5), 838 839 PINMUX_IPSR_GPSR(IP3_23_20, A14), 840 PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT14), 841 PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_C, SEL_MSIOF3_2), 842 PINMUX_IPSR_GPSR(IP3_23_20, HCTS4_N), 843 PINMUX_IPSR_GPSR(IP3_23_20, VI5_DATA10), 844 PINMUX_IPSR_GPSR(IP3_23_20, DU_DG6), 845 846 PINMUX_IPSR_GPSR(IP3_27_24, A15), 847 PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT15), 848 PINMUX_IPSR_MSEL(IP3_27_24, MSIOF3_TXD_C, SEL_MSIOF3_2), 849 PINMUX_IPSR_GPSR(IP3_27_24, HRTS4_N), 850 PINMUX_IPSR_GPSR(IP3_27_24, VI5_DATA11), 851 PINMUX_IPSR_GPSR(IP3_27_24, DU_DG7), 852 853 PINMUX_IPSR_GPSR(IP3_31_28, A16), 854 PINMUX_IPSR_GPSR(IP3_31_28, LCDOUT8), 855 PINMUX_IPSR_GPSR(IP3_31_28, VI4_FIELD), 856 PINMUX_IPSR_GPSR(IP3_31_28, DU_DG0), 857 858 /* IPSR4 */ 859 PINMUX_IPSR_GPSR(IP4_3_0, A17), 860 PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT9), 861 PINMUX_IPSR_GPSR(IP4_3_0, VI4_VSYNC_N), 862 PINMUX_IPSR_GPSR(IP4_3_0, DU_DG1), 863 864 PINMUX_IPSR_GPSR(IP4_7_4, A18), 865 PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT10), 866 PINMUX_IPSR_GPSR(IP4_7_4, VI4_HSYNC_N), 867 PINMUX_IPSR_GPSR(IP4_7_4, DU_DG2), 868 869 PINMUX_IPSR_GPSR(IP4_11_8, A19), 870 PINMUX_IPSR_GPSR(IP4_11_8, LCDOUT11), 871 PINMUX_IPSR_GPSR(IP4_11_8, VI4_CLKENB), 872 PINMUX_IPSR_GPSR(IP4_11_8, DU_DG3), 873 874 PINMUX_IPSR_GPSR(IP4_15_12, CS0_N), 875 PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB), 876 877 PINMUX_IPSR_GPSR(IP4_19_16, CS1_N), 878 PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK), 879 PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1), 880 881 PINMUX_IPSR_GPSR(IP4_23_20, BS_N), 882 PINMUX_IPSR_GPSR(IP4_23_20, QSTVA_QVS), 883 PINMUX_IPSR_MSEL(IP4_23_20, MSIOF3_SCK_D, SEL_MSIOF3_3), 884 PINMUX_IPSR_GPSR(IP4_23_20, SCK3), 885 PINMUX_IPSR_GPSR(IP4_23_20, HSCK3), 886 PINMUX_IPSR_GPSR(IP4_23_20, CAN1_TX), 887 PINMUX_IPSR_GPSR(IP4_23_20, CANFD1_TX), 888 PINMUX_IPSR_MSEL(IP4_23_20, IETX_A, SEL_IEBUS_0), 889 890 PINMUX_IPSR_GPSR(IP4_27_24, RD_N), 891 PINMUX_IPSR_MSEL(IP4_27_24, MSIOF3_SYNC_D, SEL_MSIOF3_3), 892 PINMUX_IPSR_MSEL(IP4_27_24, RX3_A, SEL_SCIF3_0), 893 PINMUX_IPSR_MSEL(IP4_27_24, HRX3_A, SEL_HSCIF3_0), 894 PINMUX_IPSR_MSEL(IP4_27_24, CAN0_TX_A, SEL_RCAN0_0), 895 PINMUX_IPSR_MSEL(IP4_27_24, CANFD0_TX_A, SEL_CANFD0_0), 896 897 PINMUX_IPSR_GPSR(IP4_31_28, RD_WR_N), 898 PINMUX_IPSR_MSEL(IP4_31_28, MSIOF3_RXD_D, SEL_MSIOF3_3), 899 PINMUX_IPSR_MSEL(IP4_31_28, TX3_A, SEL_SCIF3_0), 900 PINMUX_IPSR_MSEL(IP4_31_28, HTX3_A, SEL_HSCIF3_0), 901 PINMUX_IPSR_MSEL(IP4_31_28, CAN0_RX_A, SEL_RCAN0_0), 902 PINMUX_IPSR_MSEL(IP4_31_28, CANFD0_RX_A, SEL_CANFD0_0), 903 904 /* IPSR5 */ 905 PINMUX_IPSR_GPSR(IP5_3_0, WE0_N), 906 PINMUX_IPSR_MSEL(IP5_3_0, MSIOF3_TXD_D, SEL_MSIOF3_3), 907 PINMUX_IPSR_GPSR(IP5_3_0, CTS3_N), 908 PINMUX_IPSR_GPSR(IP5_3_0, HCTS3_N), 909 PINMUX_IPSR_MSEL(IP5_3_0, SCL6_B, SEL_I2C6_1), 910 PINMUX_IPSR_GPSR(IP5_3_0, CAN_CLK), 911 PINMUX_IPSR_MSEL(IP5_3_0, IECLK_A, SEL_IEBUS_0), 912 913 PINMUX_IPSR_GPSR(IP5_7_4, WE1_N), 914 PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3), 915 PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N), 916 PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N), 917 PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1), 918 PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX), 919 PINMUX_IPSR_GPSR(IP5_7_4, CANFD1_RX), 920 PINMUX_IPSR_MSEL(IP5_7_4, IERX_A, SEL_IEBUS_0), 921 922 PINMUX_IPSR_MSEL(IP5_11_8, EX_WAIT0_A, SEL_LBSC_0), 923 PINMUX_IPSR_GPSR(IP5_11_8, QCLK), 924 PINMUX_IPSR_GPSR(IP5_11_8, VI4_CLK), 925 PINMUX_IPSR_GPSR(IP5_11_8, DU_DOTCLKOUT0), 926 927 PINMUX_IPSR_GPSR(IP5_15_12, D0), 928 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF2_SS1_B, SEL_MSIOF2_1), 929 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF3_SCK_A, SEL_MSIOF3_0), 930 PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA16), 931 PINMUX_IPSR_GPSR(IP5_15_12, VI5_DATA0), 932 933 PINMUX_IPSR_GPSR(IP5_19_16, D1), 934 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF2_SS2_B, SEL_MSIOF2_1), 935 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF3_SYNC_A, SEL_MSIOF3_0), 936 PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA17), 937 PINMUX_IPSR_GPSR(IP5_19_16, VI5_DATA1), 938 939 PINMUX_IPSR_GPSR(IP5_23_20, D2), 940 PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_RXD_A, SEL_MSIOF3_0), 941 PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA18), 942 PINMUX_IPSR_GPSR(IP5_23_20, VI5_DATA2), 943 944 PINMUX_IPSR_GPSR(IP5_27_24, D3), 945 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0), 946 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19), 947 PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3), 948 949 PINMUX_IPSR_GPSR(IP5_31_28, D4), 950 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF2_SCK_B, SEL_MSIOF2_1), 951 PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA20), 952 PINMUX_IPSR_GPSR(IP5_31_28, VI5_DATA4), 953 954 /* IPSR6 */ 955 PINMUX_IPSR_GPSR(IP6_3_0, D5), 956 PINMUX_IPSR_MSEL(IP6_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1), 957 PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA21), 958 PINMUX_IPSR_GPSR(IP6_3_0, VI5_DATA5), 959 960 PINMUX_IPSR_GPSR(IP6_7_4, D6), 961 PINMUX_IPSR_MSEL(IP6_7_4, MSIOF2_RXD_B, SEL_MSIOF2_1), 962 PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA22), 963 PINMUX_IPSR_GPSR(IP6_7_4, VI5_DATA6), 964 965 PINMUX_IPSR_GPSR(IP6_11_8, D7), 966 PINMUX_IPSR_MSEL(IP6_11_8, MSIOF2_TXD_B, SEL_MSIOF2_1), 967 PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA23), 968 PINMUX_IPSR_GPSR(IP6_11_8, VI5_DATA7), 969 970 PINMUX_IPSR_GPSR(IP6_15_12, D8), 971 PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT0), 972 PINMUX_IPSR_MSEL(IP6_15_12, MSIOF2_SCK_D, SEL_MSIOF2_3), 973 PINMUX_IPSR_MSEL(IP6_15_12, SCK4_C, SEL_SCIF4_2), 974 PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA0_A, SEL_VIN4_0), 975 PINMUX_IPSR_GPSR(IP6_15_12, DU_DR0), 976 977 PINMUX_IPSR_GPSR(IP6_19_16, D9), 978 PINMUX_IPSR_GPSR(IP6_19_16, LCDOUT1), 979 PINMUX_IPSR_MSEL(IP6_19_16, MSIOF2_SYNC_D, SEL_MSIOF2_3), 980 PINMUX_IPSR_MSEL(IP6_19_16, VI4_DATA1_A, SEL_VIN4_0), 981 PINMUX_IPSR_GPSR(IP6_19_16, DU_DR1), 982 983 PINMUX_IPSR_GPSR(IP6_23_20, D10), 984 PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT2), 985 PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_RXD_D, SEL_MSIOF2_3), 986 PINMUX_IPSR_MSEL(IP6_23_20, HRX3_B, SEL_HSCIF3_1), 987 PINMUX_IPSR_MSEL(IP6_23_20, VI4_DATA2_A, SEL_VIN4_0), 988 PINMUX_IPSR_MSEL(IP6_23_20, CTS4_N_C, SEL_SCIF4_2), 989 PINMUX_IPSR_GPSR(IP6_23_20, DU_DR2), 990 991 PINMUX_IPSR_GPSR(IP6_27_24, D11), 992 PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT3), 993 PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3), 994 PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1), 995 PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0), 996 PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_C, SEL_SCIF4_2), 997 PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3), 998 999 PINMUX_IPSR_GPSR(IP6_31_28, D12), 1000 PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT4), 1001 PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3), 1002 PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2), 1003 PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0), 1004 PINMUX_IPSR_GPSR(IP6_31_28, DU_DR4), 1005 1006 /* IPSR7 */ 1007 PINMUX_IPSR_GPSR(IP7_3_0, D13), 1008 PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT5), 1009 PINMUX_IPSR_MSEL(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3), 1010 PINMUX_IPSR_MSEL(IP7_3_0, TX4_C, SEL_SCIF4_2), 1011 PINMUX_IPSR_MSEL(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0), 1012 PINMUX_IPSR_GPSR(IP7_3_0, DU_DR5), 1013 1014 PINMUX_IPSR_GPSR(IP7_7_4, D14), 1015 PINMUX_IPSR_GPSR(IP7_7_4, LCDOUT6), 1016 PINMUX_IPSR_MSEL(IP7_7_4, MSIOF3_SS1_A, SEL_MSIOF3_0), 1017 PINMUX_IPSR_MSEL(IP7_7_4, HRX3_C, SEL_HSCIF3_2), 1018 PINMUX_IPSR_MSEL(IP7_7_4, VI4_DATA6_A, SEL_VIN4_0), 1019 PINMUX_IPSR_GPSR(IP7_7_4, DU_DR6), 1020 PINMUX_IPSR_MSEL(IP7_7_4, SCL6_C, SEL_I2C6_2), 1021 1022 PINMUX_IPSR_GPSR(IP7_11_8, D15), 1023 PINMUX_IPSR_GPSR(IP7_11_8, LCDOUT7), 1024 PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SS2_A, SEL_MSIOF3_0), 1025 PINMUX_IPSR_MSEL(IP7_11_8, HTX3_C, SEL_HSCIF3_2), 1026 PINMUX_IPSR_MSEL(IP7_11_8, VI4_DATA7_A, SEL_VIN4_0), 1027 PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7), 1028 PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2), 1029 1030 PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK), 1031 PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4), 1032 PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1), 1033 1034 PINMUX_IPSR_GPSR(IP7_23_20, SD0_CMD), 1035 PINMUX_IPSR_MSEL(IP7_23_20, MSIOF1_SYNC_E, SEL_MSIOF1_4), 1036 PINMUX_IPSR_MSEL(IP7_23_20, STP_IVCXO27_0_B, SEL_SSP1_0_1), 1037 1038 PINMUX_IPSR_GPSR(IP7_27_24, SD0_DAT0), 1039 PINMUX_IPSR_MSEL(IP7_27_24, MSIOF1_RXD_E, SEL_MSIOF1_4), 1040 PINMUX_IPSR_MSEL(IP7_27_24, TS_SCK0_B, SEL_TSIF0_1), 1041 PINMUX_IPSR_MSEL(IP7_27_24, STP_ISCLK_0_B, SEL_SSP1_0_1), 1042 1043 PINMUX_IPSR_GPSR(IP7_31_28, SD0_DAT1), 1044 PINMUX_IPSR_MSEL(IP7_31_28, MSIOF1_TXD_E, SEL_MSIOF1_4), 1045 PINMUX_IPSR_MSEL(IP7_31_28, TS_SPSYNC0_B, SEL_TSIF0_1), 1046 PINMUX_IPSR_MSEL(IP7_31_28, STP_ISSYNC_0_B, SEL_SSP1_0_1), 1047 1048 /* IPSR8 */ 1049 PINMUX_IPSR_GPSR(IP8_3_0, SD0_DAT2), 1050 PINMUX_IPSR_MSEL(IP8_3_0, MSIOF1_SS1_E, SEL_MSIOF1_4), 1051 PINMUX_IPSR_MSEL(IP8_3_0, TS_SDAT0_B, SEL_TSIF0_1), 1052 PINMUX_IPSR_MSEL(IP8_3_0, STP_ISD_0_B, SEL_SSP1_0_1), 1053 1054 PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT3), 1055 PINMUX_IPSR_MSEL(IP8_7_4, MSIOF1_SS2_E, SEL_MSIOF1_4), 1056 PINMUX_IPSR_MSEL(IP8_7_4, TS_SDEN0_B, SEL_TSIF0_1), 1057 PINMUX_IPSR_MSEL(IP8_7_4, STP_ISEN_0_B, SEL_SSP1_0_1), 1058 1059 PINMUX_IPSR_GPSR(IP8_11_8, SD1_CLK), 1060 PINMUX_IPSR_MSEL(IP8_11_8, MSIOF1_SCK_G, SEL_MSIOF1_6), 1061 PINMUX_IPSR_MSEL(IP8_11_8, SIM0_CLK_A, SEL_SIMCARD_0), 1062 1063 PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD), 1064 PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6), 1065 PINMUX_IPSR_GPSR(IP8_15_12, NFCE_N_B), 1066 PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0), 1067 PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1), 1068 1069 PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0), 1070 PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4), 1071 PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6), 1072 PINMUX_IPSR_GPSR(IP8_19_16, NFWP_N_B), 1073 PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1), 1074 PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1), 1075 1076 PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1), 1077 PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5), 1078 PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6), 1079 PINMUX_IPSR_GPSR(IP8_23_20, NFDATA14_B), 1080 PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1), 1081 PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1), 1082 1083 PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2), 1084 PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6), 1085 PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6), 1086 PINMUX_IPSR_GPSR(IP8_27_24, NFDATA15_B), 1087 PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1), 1088 PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1), 1089 1090 PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3), 1091 PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7), 1092 PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6), 1093 PINMUX_IPSR_GPSR(IP8_31_28, NFRB_N_B), 1094 PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1), 1095 PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1), 1096 1097 /* IPSR9 */ 1098 PINMUX_IPSR_GPSR(IP9_3_0, SD2_CLK), 1099 PINMUX_IPSR_GPSR(IP9_3_0, NFDATA8), 1100 1101 PINMUX_IPSR_GPSR(IP9_7_4, SD2_CMD), 1102 PINMUX_IPSR_GPSR(IP9_7_4, NFDATA9), 1103 1104 PINMUX_IPSR_GPSR(IP9_11_8, SD2_DAT0), 1105 PINMUX_IPSR_GPSR(IP9_11_8, NFDATA10), 1106 1107 PINMUX_IPSR_GPSR(IP9_15_12, SD2_DAT1), 1108 PINMUX_IPSR_GPSR(IP9_15_12, NFDATA11), 1109 1110 PINMUX_IPSR_GPSR(IP9_19_16, SD2_DAT2), 1111 PINMUX_IPSR_GPSR(IP9_19_16, NFDATA12), 1112 1113 PINMUX_IPSR_GPSR(IP9_23_20, SD2_DAT3), 1114 PINMUX_IPSR_GPSR(IP9_23_20, NFDATA13), 1115 1116 PINMUX_IPSR_GPSR(IP9_27_24, SD2_DS), 1117 PINMUX_IPSR_GPSR(IP9_27_24, NFALE), 1118 PINMUX_IPSR_GPSR(IP9_27_24, SATA_DEVSLP_B), 1119 1120 PINMUX_IPSR_GPSR(IP9_31_28, SD3_CLK), 1121 PINMUX_IPSR_GPSR(IP9_31_28, NFWE_N), 1122 1123 /* IPSR10 */ 1124 PINMUX_IPSR_GPSR(IP10_3_0, SD3_CMD), 1125 PINMUX_IPSR_GPSR(IP10_3_0, NFRE_N), 1126 1127 PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT0), 1128 PINMUX_IPSR_GPSR(IP10_7_4, NFDATA0), 1129 1130 PINMUX_IPSR_GPSR(IP10_11_8, SD3_DAT1), 1131 PINMUX_IPSR_GPSR(IP10_11_8, NFDATA1), 1132 1133 PINMUX_IPSR_GPSR(IP10_15_12, SD3_DAT2), 1134 PINMUX_IPSR_GPSR(IP10_15_12, NFDATA2), 1135 1136 PINMUX_IPSR_GPSR(IP10_19_16, SD3_DAT3), 1137 PINMUX_IPSR_GPSR(IP10_19_16, NFDATA3), 1138 1139 PINMUX_IPSR_GPSR(IP10_23_20, SD3_DAT4), 1140 PINMUX_IPSR_MSEL(IP10_23_20, SD2_CD_A, SEL_SDHI2_0), 1141 PINMUX_IPSR_GPSR(IP10_23_20, NFDATA4), 1142 1143 PINMUX_IPSR_GPSR(IP10_27_24, SD3_DAT5), 1144 PINMUX_IPSR_MSEL(IP10_27_24, SD2_WP_A, SEL_SDHI2_0), 1145 PINMUX_IPSR_GPSR(IP10_27_24, NFDATA5), 1146 1147 PINMUX_IPSR_GPSR(IP10_31_28, SD3_DAT6), 1148 PINMUX_IPSR_GPSR(IP10_31_28, SD3_CD), 1149 PINMUX_IPSR_GPSR(IP10_31_28, NFDATA6), 1150 1151 /* IPSR11 */ 1152 PINMUX_IPSR_GPSR(IP11_3_0, SD3_DAT7), 1153 PINMUX_IPSR_GPSR(IP11_3_0, SD3_WP), 1154 PINMUX_IPSR_GPSR(IP11_3_0, NFDATA7), 1155 1156 PINMUX_IPSR_GPSR(IP11_7_4, SD3_DS), 1157 PINMUX_IPSR_GPSR(IP11_7_4, NFCLE), 1158 1159 PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD), 1160 PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1), 1161 PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0), 1162 1163 PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP), 1164 PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1), 1165 1166 PINMUX_IPSR_MSEL(IP11_19_16, SD1_CD, I2C_SEL_0_0), 1167 PINMUX_IPSR_PHYS_MSEL(IP11_19_16, SIM0_CLK_B, I2C_SEL_0_0, SEL_SIMCARD_1), 1168 PINMUX_IPSR_PHYS(IP11_19_16, SCL0, I2C_SEL_0_1), 1169 1170 PINMUX_IPSR_MSEL(IP11_23_20, SD1_WP, I2C_SEL_0_0), 1171 PINMUX_IPSR_PHYS_MSEL(IP11_23_20, SIM0_D_B, I2C_SEL_0_0, SEL_SIMCARD_1), 1172 PINMUX_IPSR_PHYS(IP11_23_20, SDA0, I2C_SEL_0_1), 1173 1174 PINMUX_IPSR_GPSR(IP11_27_24, SCK0), 1175 PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1), 1176 PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1), 1177 PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADGC_1), 1178 PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0), 1179 PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1), 1180 PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2), 1181 PINMUX_IPSR_MSEL(IP11_27_24, RIF0_CLK_B, SEL_DRIF0_1), 1182 PINMUX_IPSR_GPSR(IP11_27_24, ADICHS2), 1183 PINMUX_IPSR_MSEL(IP11_27_24, SCK5_B, SEL_SCIF5_1), 1184 1185 PINMUX_IPSR_GPSR(IP11_31_28, RX0), 1186 PINMUX_IPSR_MSEL(IP11_31_28, HRX1_B, SEL_HSCIF1_1), 1187 PINMUX_IPSR_MSEL(IP11_31_28, TS_SCK0_C, SEL_TSIF0_2), 1188 PINMUX_IPSR_MSEL(IP11_31_28, STP_ISCLK_0_C, SEL_SSP1_0_2), 1189 PINMUX_IPSR_MSEL(IP11_31_28, RIF0_D0_B, SEL_DRIF0_1), 1190 1191 /* IPSR12 */ 1192 PINMUX_IPSR_GPSR(IP12_3_0, TX0), 1193 PINMUX_IPSR_MSEL(IP12_3_0, HTX1_B, SEL_HSCIF1_1), 1194 PINMUX_IPSR_MSEL(IP12_3_0, TS_SPSYNC0_C, SEL_TSIF0_2), 1195 PINMUX_IPSR_MSEL(IP12_3_0, STP_ISSYNC_0_C, SEL_SSP1_0_2), 1196 PINMUX_IPSR_MSEL(IP12_3_0, RIF0_D1_B, SEL_DRIF0_1), 1197 1198 PINMUX_IPSR_GPSR(IP12_7_4, CTS0_N), 1199 PINMUX_IPSR_MSEL(IP12_7_4, HCTS1_N_B, SEL_HSCIF1_1), 1200 PINMUX_IPSR_MSEL(IP12_7_4, MSIOF1_SYNC_B, SEL_MSIOF1_1), 1201 PINMUX_IPSR_MSEL(IP12_7_4, TS_SPSYNC1_C, SEL_TSIF1_2), 1202 PINMUX_IPSR_MSEL(IP12_7_4, STP_ISSYNC_1_C, SEL_SSP1_1_2), 1203 PINMUX_IPSR_MSEL(IP12_7_4, RIF1_SYNC_B, SEL_DRIF1_1), 1204 PINMUX_IPSR_GPSR(IP12_7_4, AUDIO_CLKOUT_C), 1205 PINMUX_IPSR_GPSR(IP12_7_4, ADICS_SAMP), 1206 1207 PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N), 1208 PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1), 1209 PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1), 1210 PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADGA_1), 1211 PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0), 1212 PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2), 1213 PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1), 1214 PINMUX_IPSR_GPSR(IP12_11_8, ADICHS1), 1215 1216 PINMUX_IPSR_MSEL(IP12_15_12, RX1_A, SEL_SCIF1_0), 1217 PINMUX_IPSR_MSEL(IP12_15_12, HRX1_A, SEL_HSCIF1_0), 1218 PINMUX_IPSR_MSEL(IP12_15_12, TS_SDAT0_C, SEL_TSIF0_2), 1219 PINMUX_IPSR_MSEL(IP12_15_12, STP_ISD_0_C, SEL_SSP1_0_2), 1220 PINMUX_IPSR_MSEL(IP12_15_12, RIF1_CLK_C, SEL_DRIF1_2), 1221 1222 PINMUX_IPSR_MSEL(IP12_19_16, TX1_A, SEL_SCIF1_0), 1223 PINMUX_IPSR_MSEL(IP12_19_16, HTX1_A, SEL_HSCIF1_0), 1224 PINMUX_IPSR_MSEL(IP12_19_16, TS_SDEN0_C, SEL_TSIF0_2), 1225 PINMUX_IPSR_MSEL(IP12_19_16, STP_ISEN_0_C, SEL_SSP1_0_2), 1226 PINMUX_IPSR_MSEL(IP12_19_16, RIF1_D0_C, SEL_DRIF1_2), 1227 1228 PINMUX_IPSR_GPSR(IP12_23_20, CTS1_N), 1229 PINMUX_IPSR_MSEL(IP12_23_20, HCTS1_N_A, SEL_HSCIF1_0), 1230 PINMUX_IPSR_MSEL(IP12_23_20, MSIOF1_RXD_B, SEL_MSIOF1_1), 1231 PINMUX_IPSR_MSEL(IP12_23_20, TS_SDEN1_C, SEL_TSIF1_2), 1232 PINMUX_IPSR_MSEL(IP12_23_20, STP_ISEN_1_C, SEL_SSP1_1_2), 1233 PINMUX_IPSR_MSEL(IP12_23_20, RIF1_D0_B, SEL_DRIF1_1), 1234 PINMUX_IPSR_GPSR(IP12_23_20, ADIDATA), 1235 1236 PINMUX_IPSR_GPSR(IP12_27_24, RTS1_N), 1237 PINMUX_IPSR_MSEL(IP12_27_24, HRTS1_N_A, SEL_HSCIF1_0), 1238 PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1), 1239 PINMUX_IPSR_MSEL(IP12_27_24, TS_SDAT1_C, SEL_TSIF1_2), 1240 PINMUX_IPSR_MSEL(IP12_27_24, STP_ISD_1_C, SEL_SSP1_1_2), 1241 PINMUX_IPSR_MSEL(IP12_27_24, RIF1_D1_B, SEL_DRIF1_1), 1242 PINMUX_IPSR_GPSR(IP12_27_24, ADICHS0), 1243 1244 PINMUX_IPSR_GPSR(IP12_31_28, SCK2), 1245 PINMUX_IPSR_MSEL(IP12_31_28, SCIF_CLK_B, SEL_SCIF_1), 1246 PINMUX_IPSR_MSEL(IP12_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1), 1247 PINMUX_IPSR_MSEL(IP12_31_28, TS_SCK1_C, SEL_TSIF1_2), 1248 PINMUX_IPSR_MSEL(IP12_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2), 1249 PINMUX_IPSR_MSEL(IP12_31_28, RIF1_CLK_B, SEL_DRIF1_1), 1250 PINMUX_IPSR_GPSR(IP12_31_28, ADICLK), 1251 1252 /* IPSR13 */ 1253 PINMUX_IPSR_MSEL(IP13_3_0, TX2_A, SEL_SCIF2_0), 1254 PINMUX_IPSR_MSEL(IP13_3_0, SD2_CD_B, SEL_SDHI2_1), 1255 PINMUX_IPSR_MSEL(IP13_3_0, SCL1_A, SEL_I2C1_0), 1256 PINMUX_IPSR_MSEL(IP13_3_0, FMCLK_A, SEL_FM_0), 1257 PINMUX_IPSR_MSEL(IP13_3_0, RIF1_D1_C, SEL_DRIF1_2), 1258 PINMUX_IPSR_GPSR(IP13_3_0, FSO_CFE_0_N), 1259 1260 PINMUX_IPSR_MSEL(IP13_7_4, RX2_A, SEL_SCIF2_0), 1261 PINMUX_IPSR_MSEL(IP13_7_4, SD2_WP_B, SEL_SDHI2_1), 1262 PINMUX_IPSR_MSEL(IP13_7_4, SDA1_A, SEL_I2C1_0), 1263 PINMUX_IPSR_MSEL(IP13_7_4, FMIN_A, SEL_FM_0), 1264 PINMUX_IPSR_MSEL(IP13_7_4, RIF1_SYNC_C, SEL_DRIF1_2), 1265 PINMUX_IPSR_GPSR(IP13_7_4, FSO_CFE_1_N), 1266 1267 PINMUX_IPSR_GPSR(IP13_11_8, HSCK0), 1268 PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3), 1269 PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADGB_0), 1270 PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI1_1), 1271 PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3), 1272 PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3), 1273 PINMUX_IPSR_MSEL(IP13_11_8, RIF0_CLK_C, SEL_DRIF0_2), 1274 PINMUX_IPSR_MSEL(IP13_11_8, RX5_B, SEL_SCIF5_1), 1275 1276 PINMUX_IPSR_GPSR(IP13_15_12, HRX0), 1277 PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3), 1278 PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA2_B, SEL_SSI2_1), 1279 PINMUX_IPSR_MSEL(IP13_15_12, TS_SDEN0_D, SEL_TSIF0_3), 1280 PINMUX_IPSR_MSEL(IP13_15_12, STP_ISEN_0_D, SEL_SSP1_0_3), 1281 PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_C, SEL_DRIF0_2), 1282 1283 PINMUX_IPSR_GPSR(IP13_19_16, HTX0), 1284 PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3), 1285 PINMUX_IPSR_MSEL(IP13_19_16, SSI_SDATA9_B, SEL_SSI9_1), 1286 PINMUX_IPSR_MSEL(IP13_19_16, TS_SDAT0_D, SEL_TSIF0_3), 1287 PINMUX_IPSR_MSEL(IP13_19_16, STP_ISD_0_D, SEL_SSP1_0_3), 1288 PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_C, SEL_DRIF0_2), 1289 1290 PINMUX_IPSR_GPSR(IP13_23_20, HCTS0_N), 1291 PINMUX_IPSR_MSEL(IP13_23_20, RX2_B, SEL_SCIF2_1), 1292 PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3), 1293 PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK9_A, SEL_SSI9_0), 1294 PINMUX_IPSR_MSEL(IP13_23_20, TS_SPSYNC0_D, SEL_TSIF0_3), 1295 PINMUX_IPSR_MSEL(IP13_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3), 1296 PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_C, SEL_DRIF0_2), 1297 PINMUX_IPSR_GPSR(IP13_23_20, AUDIO_CLKOUT1_A), 1298 1299 PINMUX_IPSR_GPSR(IP13_27_24, HRTS0_N), 1300 PINMUX_IPSR_MSEL(IP13_27_24, TX2_B, SEL_SCIF2_1), 1301 PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3), 1302 PINMUX_IPSR_MSEL(IP13_27_24, SSI_WS9_A, SEL_SSI9_0), 1303 PINMUX_IPSR_MSEL(IP13_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3), 1304 PINMUX_IPSR_MSEL(IP13_27_24, BPFCLK_A, SEL_FM_0), 1305 PINMUX_IPSR_GPSR(IP13_27_24, AUDIO_CLKOUT2_A), 1306 1307 PINMUX_IPSR_GPSR(IP13_31_28, MSIOF0_SYNC), 1308 PINMUX_IPSR_GPSR(IP13_31_28, AUDIO_CLKOUT_A), 1309 PINMUX_IPSR_MSEL(IP13_31_28, TX5_B, SEL_SCIF5_1), 1310 PINMUX_IPSR_MSEL(IP13_31_28, BPFCLK_D, SEL_FM_3), 1311 1312 /* IPSR14 */ 1313 PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1), 1314 PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0), 1315 PINMUX_IPSR_GPSR(IP14_3_0, NFWP_N_A), 1316 PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADGA_2), 1317 PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0), 1318 PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2), 1319 PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A), 1320 PINMUX_IPSR_MSEL(IP14_3_0, TCLK1_B, SEL_TIMER_TMU1_1), 1321 1322 PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2), 1323 PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0), 1324 PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3), 1325 PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADGC_0), 1326 PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI2_0), 1327 PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3), 1328 PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D), 1329 PINMUX_IPSR_MSEL(IP14_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1), 1330 1331 PINMUX_IPSR_GPSR(IP14_11_8, MLB_CLK), 1332 PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SCK_F, SEL_MSIOF1_5), 1333 PINMUX_IPSR_MSEL(IP14_11_8, SCL1_B, SEL_I2C1_1), 1334 1335 PINMUX_IPSR_GPSR(IP14_15_12, MLB_SIG), 1336 PINMUX_IPSR_MSEL(IP14_15_12, RX1_B, SEL_SCIF1_1), 1337 PINMUX_IPSR_MSEL(IP14_15_12, MSIOF1_SYNC_F, SEL_MSIOF1_5), 1338 PINMUX_IPSR_MSEL(IP14_15_12, SDA1_B, SEL_I2C1_1), 1339 1340 PINMUX_IPSR_GPSR(IP14_19_16, MLB_DAT), 1341 PINMUX_IPSR_MSEL(IP14_19_16, TX1_B, SEL_SCIF1_1), 1342 PINMUX_IPSR_MSEL(IP14_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5), 1343 1344 PINMUX_IPSR_GPSR(IP14_23_20, SSI_SCK01239), 1345 PINMUX_IPSR_MSEL(IP14_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5), 1346 1347 PINMUX_IPSR_GPSR(IP14_27_24, SSI_WS01239), 1348 PINMUX_IPSR_MSEL(IP14_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5), 1349 1350 PINMUX_IPSR_GPSR(IP14_31_28, SSI_SDATA0), 1351 PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5), 1352 1353 /* IPSR15 */ 1354 PINMUX_IPSR_MSEL(IP15_3_0, SSI_SDATA1_A, SEL_SSI1_0), 1355 1356 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SDATA2_A, SEL_SSI2_0), 1357 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SCK1_B, SEL_SSI1_1), 1358 1359 PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK349), 1360 PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0), 1361 PINMUX_IPSR_MSEL(IP15_11_8, STP_OPWM_0_A, SEL_SSP1_0_0), 1362 1363 PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS349), 1364 PINMUX_IPSR_MSEL(IP15_15_12, HCTS2_N_A, SEL_HSCIF2_0), 1365 PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0), 1366 PINMUX_IPSR_MSEL(IP15_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0), 1367 1368 PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA3), 1369 PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0), 1370 PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_TXD_A, SEL_MSIOF1_0), 1371 PINMUX_IPSR_MSEL(IP15_19_16, TS_SCK0_A, SEL_TSIF0_0), 1372 PINMUX_IPSR_MSEL(IP15_19_16, STP_ISCLK_0_A, SEL_SSP1_0_0), 1373 PINMUX_IPSR_MSEL(IP15_19_16, RIF0_D1_A, SEL_DRIF0_0), 1374 PINMUX_IPSR_MSEL(IP15_19_16, RIF2_D0_A, SEL_DRIF2_0), 1375 1376 PINMUX_IPSR_GPSR(IP15_23_20, SSI_SCK4), 1377 PINMUX_IPSR_MSEL(IP15_23_20, HRX2_A, SEL_HSCIF2_0), 1378 PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_SCK_A, SEL_MSIOF1_0), 1379 PINMUX_IPSR_MSEL(IP15_23_20, TS_SDAT0_A, SEL_TSIF0_0), 1380 PINMUX_IPSR_MSEL(IP15_23_20, STP_ISD_0_A, SEL_SSP1_0_0), 1381 PINMUX_IPSR_MSEL(IP15_23_20, RIF0_CLK_A, SEL_DRIF0_0), 1382 PINMUX_IPSR_MSEL(IP15_23_20, RIF2_CLK_A, SEL_DRIF2_0), 1383 1384 PINMUX_IPSR_GPSR(IP15_27_24, SSI_WS4), 1385 PINMUX_IPSR_MSEL(IP15_27_24, HTX2_A, SEL_HSCIF2_0), 1386 PINMUX_IPSR_MSEL(IP15_27_24, MSIOF1_SYNC_A, SEL_MSIOF1_0), 1387 PINMUX_IPSR_MSEL(IP15_27_24, TS_SDEN0_A, SEL_TSIF0_0), 1388 PINMUX_IPSR_MSEL(IP15_27_24, STP_ISEN_0_A, SEL_SSP1_0_0), 1389 PINMUX_IPSR_MSEL(IP15_27_24, RIF0_SYNC_A, SEL_DRIF0_0), 1390 PINMUX_IPSR_MSEL(IP15_27_24, RIF2_SYNC_A, SEL_DRIF2_0), 1391 1392 PINMUX_IPSR_GPSR(IP15_31_28, SSI_SDATA4), 1393 PINMUX_IPSR_MSEL(IP15_31_28, HSCK2_A, SEL_HSCIF2_0), 1394 PINMUX_IPSR_MSEL(IP15_31_28, MSIOF1_RXD_A, SEL_MSIOF1_0), 1395 PINMUX_IPSR_MSEL(IP15_31_28, TS_SPSYNC0_A, SEL_TSIF0_0), 1396 PINMUX_IPSR_MSEL(IP15_31_28, STP_ISSYNC_0_A, SEL_SSP1_0_0), 1397 PINMUX_IPSR_MSEL(IP15_31_28, RIF0_D0_A, SEL_DRIF0_0), 1398 PINMUX_IPSR_MSEL(IP15_31_28, RIF2_D1_A, SEL_DRIF2_0), 1399 1400 /* IPSR16 */ 1401 PINMUX_IPSR_GPSR(IP16_3_0, SSI_SCK6), 1402 PINMUX_IPSR_GPSR(IP16_3_0, USB2_PWEN), 1403 PINMUX_IPSR_MSEL(IP16_3_0, SIM0_RST_D, SEL_SIMCARD_3), 1404 1405 PINMUX_IPSR_GPSR(IP16_7_4, SSI_WS6), 1406 PINMUX_IPSR_GPSR(IP16_7_4, USB2_OVC), 1407 PINMUX_IPSR_MSEL(IP16_7_4, SIM0_D_D, SEL_SIMCARD_3), 1408 1409 PINMUX_IPSR_GPSR(IP16_11_8, SSI_SDATA6), 1410 PINMUX_IPSR_MSEL(IP16_11_8, SIM0_CLK_D, SEL_SIMCARD_3), 1411 PINMUX_IPSR_GPSR(IP16_11_8, SATA_DEVSLP_A), 1412 1413 PINMUX_IPSR_GPSR(IP16_15_12, SSI_SCK78), 1414 PINMUX_IPSR_MSEL(IP16_15_12, HRX2_B, SEL_HSCIF2_1), 1415 PINMUX_IPSR_MSEL(IP16_15_12, MSIOF1_SCK_C, SEL_MSIOF1_2), 1416 PINMUX_IPSR_MSEL(IP16_15_12, TS_SCK1_A, SEL_TSIF1_0), 1417 PINMUX_IPSR_MSEL(IP16_15_12, STP_ISCLK_1_A, SEL_SSP1_1_0), 1418 PINMUX_IPSR_MSEL(IP16_15_12, RIF1_CLK_A, SEL_DRIF1_0), 1419 PINMUX_IPSR_MSEL(IP16_15_12, RIF3_CLK_A, SEL_DRIF3_0), 1420 1421 PINMUX_IPSR_GPSR(IP16_19_16, SSI_WS78), 1422 PINMUX_IPSR_MSEL(IP16_19_16, HTX2_B, SEL_HSCIF2_1), 1423 PINMUX_IPSR_MSEL(IP16_19_16, MSIOF1_SYNC_C, SEL_MSIOF1_2), 1424 PINMUX_IPSR_MSEL(IP16_19_16, TS_SDAT1_A, SEL_TSIF1_0), 1425 PINMUX_IPSR_MSEL(IP16_19_16, STP_ISD_1_A, SEL_SSP1_1_0), 1426 PINMUX_IPSR_MSEL(IP16_19_16, RIF1_SYNC_A, SEL_DRIF1_0), 1427 PINMUX_IPSR_MSEL(IP16_19_16, RIF3_SYNC_A, SEL_DRIF3_0), 1428 1429 PINMUX_IPSR_GPSR(IP16_23_20, SSI_SDATA7), 1430 PINMUX_IPSR_MSEL(IP16_23_20, HCTS2_N_B, SEL_HSCIF2_1), 1431 PINMUX_IPSR_MSEL(IP16_23_20, MSIOF1_RXD_C, SEL_MSIOF1_2), 1432 PINMUX_IPSR_MSEL(IP16_23_20, TS_SDEN1_A, SEL_TSIF1_0), 1433 PINMUX_IPSR_MSEL(IP16_23_20, STP_ISEN_1_A, SEL_SSP1_1_0), 1434 PINMUX_IPSR_MSEL(IP16_23_20, RIF1_D0_A, SEL_DRIF1_0), 1435 PINMUX_IPSR_MSEL(IP16_23_20, RIF3_D0_A, SEL_DRIF3_0), 1436 PINMUX_IPSR_MSEL(IP16_23_20, TCLK2_A, SEL_TIMER_TMU2_0), 1437 1438 PINMUX_IPSR_GPSR(IP16_27_24, SSI_SDATA8), 1439 PINMUX_IPSR_MSEL(IP16_27_24, HRTS2_N_B, SEL_HSCIF2_1), 1440 PINMUX_IPSR_MSEL(IP16_27_24, MSIOF1_TXD_C, SEL_MSIOF1_2), 1441 PINMUX_IPSR_MSEL(IP16_27_24, TS_SPSYNC1_A, SEL_TSIF1_0), 1442 PINMUX_IPSR_MSEL(IP16_27_24, STP_ISSYNC_1_A, SEL_SSP1_1_0), 1443 PINMUX_IPSR_MSEL(IP16_27_24, RIF1_D1_A, SEL_DRIF1_0), 1444 PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D1_A, SEL_DRIF3_0), 1445 1446 PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA9_A, SEL_SSI9_0), 1447 PINMUX_IPSR_MSEL(IP16_31_28, HSCK2_B, SEL_HSCIF2_1), 1448 PINMUX_IPSR_MSEL(IP16_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2), 1449 PINMUX_IPSR_MSEL(IP16_31_28, HSCK1_A, SEL_HSCIF1_0), 1450 PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI1_1), 1451 PINMUX_IPSR_GPSR(IP16_31_28, SCK1), 1452 PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0), 1453 PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0), 1454 1455 /* IPSR17 */ 1456 PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADGA_0), 1457 1458 PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADGB_1), 1459 PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0), 1460 PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3), 1461 PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0), 1462 PINMUX_IPSR_MSEL(IP17_7_4, TCLK1_A, SEL_TIMER_TMU1_0), 1463 1464 PINMUX_IPSR_GPSR(IP17_11_8, USB0_PWEN), 1465 PINMUX_IPSR_MSEL(IP17_11_8, SIM0_RST_C, SEL_SIMCARD_2), 1466 PINMUX_IPSR_MSEL(IP17_11_8, TS_SCK1_D, SEL_TSIF1_3), 1467 PINMUX_IPSR_MSEL(IP17_11_8, STP_ISCLK_1_D, SEL_SSP1_1_3), 1468 PINMUX_IPSR_MSEL(IP17_11_8, BPFCLK_B, SEL_FM_1), 1469 PINMUX_IPSR_MSEL(IP17_11_8, RIF3_CLK_B, SEL_DRIF3_1), 1470 PINMUX_IPSR_MSEL(IP17_11_8, HSCK2_C, SEL_HSCIF2_2), 1471 1472 PINMUX_IPSR_GPSR(IP17_15_12, USB0_OVC), 1473 PINMUX_IPSR_MSEL(IP17_15_12, SIM0_D_C, SEL_SIMCARD_2), 1474 PINMUX_IPSR_MSEL(IP17_15_12, TS_SDAT1_D, SEL_TSIF1_3), 1475 PINMUX_IPSR_MSEL(IP17_15_12, STP_ISD_1_D, SEL_SSP1_1_3), 1476 PINMUX_IPSR_MSEL(IP17_15_12, RIF3_SYNC_B, SEL_DRIF3_1), 1477 PINMUX_IPSR_MSEL(IP17_15_12, HRX2_C, SEL_HSCIF2_2), 1478 1479 PINMUX_IPSR_GPSR(IP17_19_16, USB1_PWEN), 1480 PINMUX_IPSR_MSEL(IP17_19_16, SIM0_CLK_C, SEL_SIMCARD_2), 1481 PINMUX_IPSR_MSEL(IP17_19_16, SSI_SCK1_A, SEL_SSI1_0), 1482 PINMUX_IPSR_MSEL(IP17_19_16, TS_SCK0_E, SEL_TSIF0_4), 1483 PINMUX_IPSR_MSEL(IP17_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4), 1484 PINMUX_IPSR_MSEL(IP17_19_16, FMCLK_B, SEL_FM_1), 1485 PINMUX_IPSR_MSEL(IP17_19_16, RIF2_CLK_B, SEL_DRIF2_1), 1486 PINMUX_IPSR_MSEL(IP17_19_16, SPEEDIN_A, SEL_SPEED_PULSE_0), 1487 PINMUX_IPSR_MSEL(IP17_19_16, HTX2_C, SEL_HSCIF2_2), 1488 1489 PINMUX_IPSR_GPSR(IP17_23_20, USB1_OVC), 1490 PINMUX_IPSR_MSEL(IP17_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2), 1491 PINMUX_IPSR_MSEL(IP17_23_20, SSI_WS1_A, SEL_SSI1_0), 1492 PINMUX_IPSR_MSEL(IP17_23_20, TS_SDAT0_E, SEL_TSIF0_4), 1493 PINMUX_IPSR_MSEL(IP17_23_20, STP_ISD_0_E, SEL_SSP1_0_4), 1494 PINMUX_IPSR_MSEL(IP17_23_20, FMIN_B, SEL_FM_1), 1495 PINMUX_IPSR_MSEL(IP17_23_20, RIF2_SYNC_B, SEL_DRIF2_1), 1496 PINMUX_IPSR_MSEL(IP17_23_20, REMOCON_B, SEL_REMOCON_1), 1497 PINMUX_IPSR_MSEL(IP17_23_20, HCTS2_N_C, SEL_HSCIF2_2), 1498 1499 PINMUX_IPSR_GPSR(IP17_27_24, USB30_PWEN), 1500 PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_B), 1501 PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI2_1), 1502 PINMUX_IPSR_MSEL(IP17_27_24, TS_SDEN1_D, SEL_TSIF1_3), 1503 PINMUX_IPSR_MSEL(IP17_27_24, STP_ISEN_1_D, SEL_SSP1_1_3), 1504 PINMUX_IPSR_MSEL(IP17_27_24, STP_OPWM_0_E, SEL_SSP1_0_4), 1505 PINMUX_IPSR_MSEL(IP17_27_24, RIF3_D0_B, SEL_DRIF3_1), 1506 PINMUX_IPSR_MSEL(IP17_27_24, TCLK2_B, SEL_TIMER_TMU2_1), 1507 PINMUX_IPSR_GPSR(IP17_27_24, TPU0TO0), 1508 PINMUX_IPSR_MSEL(IP17_27_24, BPFCLK_C, SEL_FM_2), 1509 PINMUX_IPSR_MSEL(IP17_27_24, HRTS2_N_C, SEL_HSCIF2_2), 1510 1511 PINMUX_IPSR_GPSR(IP17_31_28, USB30_OVC), 1512 PINMUX_IPSR_GPSR(IP17_31_28, AUDIO_CLKOUT1_B), 1513 PINMUX_IPSR_MSEL(IP17_31_28, SSI_WS2_B, SEL_SSI2_1), 1514 PINMUX_IPSR_MSEL(IP17_31_28, TS_SPSYNC1_D, SEL_TSIF1_3), 1515 PINMUX_IPSR_MSEL(IP17_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3), 1516 PINMUX_IPSR_MSEL(IP17_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4), 1517 PINMUX_IPSR_MSEL(IP17_31_28, RIF3_D1_B, SEL_DRIF3_1), 1518 PINMUX_IPSR_GPSR(IP17_31_28, FSO_TOE_N), 1519 PINMUX_IPSR_GPSR(IP17_31_28, TPU0TO1), 1520 1521 /* IPSR18 */ 1522 PINMUX_IPSR_GPSR(IP18_3_0, USB2_CH3_PWEN), 1523 PINMUX_IPSR_GPSR(IP18_3_0, AUDIO_CLKOUT2_B), 1524 PINMUX_IPSR_MSEL(IP18_3_0, SSI_SCK9_B, SEL_SSI9_1), 1525 PINMUX_IPSR_MSEL(IP18_3_0, TS_SDEN0_E, SEL_TSIF0_4), 1526 PINMUX_IPSR_MSEL(IP18_3_0, STP_ISEN_0_E, SEL_SSP1_0_4), 1527 PINMUX_IPSR_MSEL(IP18_3_0, RIF2_D0_B, SEL_DRIF2_1), 1528 PINMUX_IPSR_GPSR(IP18_3_0, TPU0TO2), 1529 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_C, SEL_FM_2), 1530 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_D, SEL_FM_3), 1531 1532 PINMUX_IPSR_GPSR(IP18_7_4, USB2_CH3_OVC), 1533 PINMUX_IPSR_GPSR(IP18_7_4, AUDIO_CLKOUT3_B), 1534 PINMUX_IPSR_MSEL(IP18_7_4, SSI_WS9_B, SEL_SSI9_1), 1535 PINMUX_IPSR_MSEL(IP18_7_4, TS_SPSYNC0_E, SEL_TSIF0_4), 1536 PINMUX_IPSR_MSEL(IP18_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4), 1537 PINMUX_IPSR_MSEL(IP18_7_4, RIF2_D1_B, SEL_DRIF2_1), 1538 PINMUX_IPSR_GPSR(IP18_7_4, TPU0TO3), 1539 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_C, SEL_FM_2), 1540 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_D, SEL_FM_3), 1541 1542 /* 1543 * Static pins can not be muxed between different functions but 1544 * still need mark entries in the pinmux list. Add each static 1545 * pin to the list without an associated function. The sh-pfc 1546 * core will do the right thing and skip trying to mux the pin 1547 * while still applying configuration to it. 1548 */ 1549 #define FM(x) PINMUX_DATA(x##_MARK, 0), 1550 PINMUX_STATIC 1551 #undef FM 1552 }; 1553 1554 /* 1555 * Pins not associated with a GPIO port. 1556 */ 1557 enum { 1558 GP_ASSIGN_LAST(), 1559 NOGP_ALL(), 1560 }; 1561 1562 static const struct sh_pfc_pin pinmux_pins[] = { 1563 PINMUX_GPIO_GP_ALL(), 1564 PINMUX_NOGP_ALL(), 1565 }; 1566 1567 /* - AUDIO CLOCK ------------------------------------------------------------ */ 1568 static const unsigned int audio_clk_a_a_pins[] = { 1569 /* CLK A */ 1570 RCAR_GP_PIN(6, 22), 1571 }; 1572 static const unsigned int audio_clk_a_a_mux[] = { 1573 AUDIO_CLKA_A_MARK, 1574 }; 1575 static const unsigned int audio_clk_a_b_pins[] = { 1576 /* CLK A */ 1577 RCAR_GP_PIN(5, 4), 1578 }; 1579 static const unsigned int audio_clk_a_b_mux[] = { 1580 AUDIO_CLKA_B_MARK, 1581 }; 1582 static const unsigned int audio_clk_a_c_pins[] = { 1583 /* CLK A */ 1584 RCAR_GP_PIN(5, 19), 1585 }; 1586 static const unsigned int audio_clk_a_c_mux[] = { 1587 AUDIO_CLKA_C_MARK, 1588 }; 1589 static const unsigned int audio_clk_b_a_pins[] = { 1590 /* CLK B */ 1591 RCAR_GP_PIN(5, 12), 1592 }; 1593 static const unsigned int audio_clk_b_a_mux[] = { 1594 AUDIO_CLKB_A_MARK, 1595 }; 1596 static const unsigned int audio_clk_b_b_pins[] = { 1597 /* CLK B */ 1598 RCAR_GP_PIN(6, 23), 1599 }; 1600 static const unsigned int audio_clk_b_b_mux[] = { 1601 AUDIO_CLKB_B_MARK, 1602 }; 1603 static const unsigned int audio_clk_c_a_pins[] = { 1604 /* CLK C */ 1605 RCAR_GP_PIN(5, 21), 1606 }; 1607 static const unsigned int audio_clk_c_a_mux[] = { 1608 AUDIO_CLKC_A_MARK, 1609 }; 1610 static const unsigned int audio_clk_c_b_pins[] = { 1611 /* CLK C */ 1612 RCAR_GP_PIN(5, 0), 1613 }; 1614 static const unsigned int audio_clk_c_b_mux[] = { 1615 AUDIO_CLKC_B_MARK, 1616 }; 1617 static const unsigned int audio_clkout_a_pins[] = { 1618 /* CLKOUT */ 1619 RCAR_GP_PIN(5, 18), 1620 }; 1621 static const unsigned int audio_clkout_a_mux[] = { 1622 AUDIO_CLKOUT_A_MARK, 1623 }; 1624 static const unsigned int audio_clkout_b_pins[] = { 1625 /* CLKOUT */ 1626 RCAR_GP_PIN(6, 28), 1627 }; 1628 static const unsigned int audio_clkout_b_mux[] = { 1629 AUDIO_CLKOUT_B_MARK, 1630 }; 1631 static const unsigned int audio_clkout_c_pins[] = { 1632 /* CLKOUT */ 1633 RCAR_GP_PIN(5, 3), 1634 }; 1635 static const unsigned int audio_clkout_c_mux[] = { 1636 AUDIO_CLKOUT_C_MARK, 1637 }; 1638 static const unsigned int audio_clkout_d_pins[] = { 1639 /* CLKOUT */ 1640 RCAR_GP_PIN(5, 21), 1641 }; 1642 static const unsigned int audio_clkout_d_mux[] = { 1643 AUDIO_CLKOUT_D_MARK, 1644 }; 1645 static const unsigned int audio_clkout1_a_pins[] = { 1646 /* CLKOUT1 */ 1647 RCAR_GP_PIN(5, 15), 1648 }; 1649 static const unsigned int audio_clkout1_a_mux[] = { 1650 AUDIO_CLKOUT1_A_MARK, 1651 }; 1652 static const unsigned int audio_clkout1_b_pins[] = { 1653 /* CLKOUT1 */ 1654 RCAR_GP_PIN(6, 29), 1655 }; 1656 static const unsigned int audio_clkout1_b_mux[] = { 1657 AUDIO_CLKOUT1_B_MARK, 1658 }; 1659 static const unsigned int audio_clkout2_a_pins[] = { 1660 /* CLKOUT2 */ 1661 RCAR_GP_PIN(5, 16), 1662 }; 1663 static const unsigned int audio_clkout2_a_mux[] = { 1664 AUDIO_CLKOUT2_A_MARK, 1665 }; 1666 static const unsigned int audio_clkout2_b_pins[] = { 1667 /* CLKOUT2 */ 1668 RCAR_GP_PIN(6, 30), 1669 }; 1670 static const unsigned int audio_clkout2_b_mux[] = { 1671 AUDIO_CLKOUT2_B_MARK, 1672 }; 1673 static const unsigned int audio_clkout3_a_pins[] = { 1674 /* CLKOUT3 */ 1675 RCAR_GP_PIN(5, 19), 1676 }; 1677 static const unsigned int audio_clkout3_a_mux[] = { 1678 AUDIO_CLKOUT3_A_MARK, 1679 }; 1680 static const unsigned int audio_clkout3_b_pins[] = { 1681 /* CLKOUT3 */ 1682 RCAR_GP_PIN(6, 31), 1683 }; 1684 static const unsigned int audio_clkout3_b_mux[] = { 1685 AUDIO_CLKOUT3_B_MARK, 1686 }; 1687 1688 /* - EtherAVB --------------------------------------------------------------- */ 1689 static const unsigned int avb_link_pins[] = { 1690 /* AVB_LINK */ 1691 RCAR_GP_PIN(2, 12), 1692 }; 1693 static const unsigned int avb_link_mux[] = { 1694 AVB_LINK_MARK, 1695 }; 1696 static const unsigned int avb_magic_pins[] = { 1697 /* AVB_MAGIC_ */ 1698 RCAR_GP_PIN(2, 10), 1699 }; 1700 static const unsigned int avb_magic_mux[] = { 1701 AVB_MAGIC_MARK, 1702 }; 1703 static const unsigned int avb_phy_int_pins[] = { 1704 /* AVB_PHY_INT */ 1705 RCAR_GP_PIN(2, 11), 1706 }; 1707 static const unsigned int avb_phy_int_mux[] = { 1708 AVB_PHY_INT_MARK, 1709 }; 1710 static const unsigned int avb_mdio_pins[] = { 1711 /* AVB_MDC, AVB_MDIO */ 1712 RCAR_GP_PIN(2, 9), PIN_AVB_MDIO, 1713 }; 1714 static const unsigned int avb_mdio_mux[] = { 1715 AVB_MDC_MARK, AVB_MDIO_MARK, 1716 }; 1717 static const unsigned int avb_mii_pins[] = { 1718 /* 1719 * AVB_TX_CTL, AVB_TXC, AVB_TD0, 1720 * AVB_TD1, AVB_TD2, AVB_TD3, 1721 * AVB_RX_CTL, AVB_RXC, AVB_RD0, 1722 * AVB_RD1, AVB_RD2, AVB_RD3, 1723 * AVB_TXCREFCLK 1724 */ 1725 PIN_AVB_TX_CTL, PIN_AVB_TXC, PIN_AVB_TD0, 1726 PIN_AVB_TD1, PIN_AVB_TD2, PIN_AVB_TD3, 1727 PIN_AVB_RX_CTL, PIN_AVB_RXC, PIN_AVB_RD0, 1728 PIN_AVB_RD1, PIN_AVB_RD2, PIN_AVB_RD3, 1729 PIN_AVB_TXCREFCLK, 1730 }; 1731 static const unsigned int avb_mii_mux[] = { 1732 AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK, 1733 AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK, 1734 AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK, 1735 AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK, 1736 AVB_TXCREFCLK_MARK, 1737 }; 1738 static const unsigned int avb_avtp_pps_pins[] = { 1739 /* AVB_AVTP_PPS */ 1740 RCAR_GP_PIN(2, 6), 1741 }; 1742 static const unsigned int avb_avtp_pps_mux[] = { 1743 AVB_AVTP_PPS_MARK, 1744 }; 1745 static const unsigned int avb_avtp_match_a_pins[] = { 1746 /* AVB_AVTP_MATCH_A */ 1747 RCAR_GP_PIN(2, 13), 1748 }; 1749 static const unsigned int avb_avtp_match_a_mux[] = { 1750 AVB_AVTP_MATCH_A_MARK, 1751 }; 1752 static const unsigned int avb_avtp_capture_a_pins[] = { 1753 /* AVB_AVTP_CAPTURE_A */ 1754 RCAR_GP_PIN(2, 14), 1755 }; 1756 static const unsigned int avb_avtp_capture_a_mux[] = { 1757 AVB_AVTP_CAPTURE_A_MARK, 1758 }; 1759 static const unsigned int avb_avtp_match_b_pins[] = { 1760 /* AVB_AVTP_MATCH_B */ 1761 RCAR_GP_PIN(1, 8), 1762 }; 1763 static const unsigned int avb_avtp_match_b_mux[] = { 1764 AVB_AVTP_MATCH_B_MARK, 1765 }; 1766 static const unsigned int avb_avtp_capture_b_pins[] = { 1767 /* AVB_AVTP_CAPTURE_B */ 1768 RCAR_GP_PIN(1, 11), 1769 }; 1770 static const unsigned int avb_avtp_capture_b_mux[] = { 1771 AVB_AVTP_CAPTURE_B_MARK, 1772 }; 1773 1774 /* - CAN ------------------------------------------------------------------ */ 1775 static const unsigned int can0_data_a_pins[] = { 1776 /* TX, RX */ 1777 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24), 1778 }; 1779 static const unsigned int can0_data_a_mux[] = { 1780 CAN0_TX_A_MARK, CAN0_RX_A_MARK, 1781 }; 1782 static const unsigned int can0_data_b_pins[] = { 1783 /* TX, RX */ 1784 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), 1785 }; 1786 static const unsigned int can0_data_b_mux[] = { 1787 CAN0_TX_B_MARK, CAN0_RX_B_MARK, 1788 }; 1789 static const unsigned int can1_data_pins[] = { 1790 /* TX, RX */ 1791 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26), 1792 }; 1793 static const unsigned int can1_data_mux[] = { 1794 CAN1_TX_MARK, CAN1_RX_MARK, 1795 }; 1796 1797 /* - CAN Clock -------------------------------------------------------------- */ 1798 static const unsigned int can_clk_pins[] = { 1799 /* CLK */ 1800 RCAR_GP_PIN(1, 25), 1801 }; 1802 static const unsigned int can_clk_mux[] = { 1803 CAN_CLK_MARK, 1804 }; 1805 1806 /* - CAN FD --------------------------------------------------------------- */ 1807 static const unsigned int canfd0_data_a_pins[] = { 1808 /* TX, RX */ 1809 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24), 1810 }; 1811 static const unsigned int canfd0_data_a_mux[] = { 1812 CANFD0_TX_A_MARK, CANFD0_RX_A_MARK, 1813 }; 1814 static const unsigned int canfd0_data_b_pins[] = { 1815 /* TX, RX */ 1816 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), 1817 }; 1818 static const unsigned int canfd0_data_b_mux[] = { 1819 CANFD0_TX_B_MARK, CANFD0_RX_B_MARK, 1820 }; 1821 static const unsigned int canfd1_data_pins[] = { 1822 /* TX, RX */ 1823 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26), 1824 }; 1825 static const unsigned int canfd1_data_mux[] = { 1826 CANFD1_TX_MARK, CANFD1_RX_MARK, 1827 }; 1828 1829 /* - DRIF0 --------------------------------------------------------------- */ 1830 static const unsigned int drif0_ctrl_a_pins[] = { 1831 /* CLK, SYNC */ 1832 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), 1833 }; 1834 static const unsigned int drif0_ctrl_a_mux[] = { 1835 RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK, 1836 }; 1837 static const unsigned int drif0_data0_a_pins[] = { 1838 /* D0 */ 1839 RCAR_GP_PIN(6, 10), 1840 }; 1841 static const unsigned int drif0_data0_a_mux[] = { 1842 RIF0_D0_A_MARK, 1843 }; 1844 static const unsigned int drif0_data1_a_pins[] = { 1845 /* D1 */ 1846 RCAR_GP_PIN(6, 7), 1847 }; 1848 static const unsigned int drif0_data1_a_mux[] = { 1849 RIF0_D1_A_MARK, 1850 }; 1851 static const unsigned int drif0_ctrl_b_pins[] = { 1852 /* CLK, SYNC */ 1853 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4), 1854 }; 1855 static const unsigned int drif0_ctrl_b_mux[] = { 1856 RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK, 1857 }; 1858 static const unsigned int drif0_data0_b_pins[] = { 1859 /* D0 */ 1860 RCAR_GP_PIN(5, 1), 1861 }; 1862 static const unsigned int drif0_data0_b_mux[] = { 1863 RIF0_D0_B_MARK, 1864 }; 1865 static const unsigned int drif0_data1_b_pins[] = { 1866 /* D1 */ 1867 RCAR_GP_PIN(5, 2), 1868 }; 1869 static const unsigned int drif0_data1_b_mux[] = { 1870 RIF0_D1_B_MARK, 1871 }; 1872 static const unsigned int drif0_ctrl_c_pins[] = { 1873 /* CLK, SYNC */ 1874 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15), 1875 }; 1876 static const unsigned int drif0_ctrl_c_mux[] = { 1877 RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK, 1878 }; 1879 static const unsigned int drif0_data0_c_pins[] = { 1880 /* D0 */ 1881 RCAR_GP_PIN(5, 13), 1882 }; 1883 static const unsigned int drif0_data0_c_mux[] = { 1884 RIF0_D0_C_MARK, 1885 }; 1886 static const unsigned int drif0_data1_c_pins[] = { 1887 /* D1 */ 1888 RCAR_GP_PIN(5, 14), 1889 }; 1890 static const unsigned int drif0_data1_c_mux[] = { 1891 RIF0_D1_C_MARK, 1892 }; 1893 /* - DRIF1 --------------------------------------------------------------- */ 1894 static const unsigned int drif1_ctrl_a_pins[] = { 1895 /* CLK, SYNC */ 1896 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18), 1897 }; 1898 static const unsigned int drif1_ctrl_a_mux[] = { 1899 RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK, 1900 }; 1901 static const unsigned int drif1_data0_a_pins[] = { 1902 /* D0 */ 1903 RCAR_GP_PIN(6, 19), 1904 }; 1905 static const unsigned int drif1_data0_a_mux[] = { 1906 RIF1_D0_A_MARK, 1907 }; 1908 static const unsigned int drif1_data1_a_pins[] = { 1909 /* D1 */ 1910 RCAR_GP_PIN(6, 20), 1911 }; 1912 static const unsigned int drif1_data1_a_mux[] = { 1913 RIF1_D1_A_MARK, 1914 }; 1915 static const unsigned int drif1_ctrl_b_pins[] = { 1916 /* CLK, SYNC */ 1917 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3), 1918 }; 1919 static const unsigned int drif1_ctrl_b_mux[] = { 1920 RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK, 1921 }; 1922 static const unsigned int drif1_data0_b_pins[] = { 1923 /* D0 */ 1924 RCAR_GP_PIN(5, 7), 1925 }; 1926 static const unsigned int drif1_data0_b_mux[] = { 1927 RIF1_D0_B_MARK, 1928 }; 1929 static const unsigned int drif1_data1_b_pins[] = { 1930 /* D1 */ 1931 RCAR_GP_PIN(5, 8), 1932 }; 1933 static const unsigned int drif1_data1_b_mux[] = { 1934 RIF1_D1_B_MARK, 1935 }; 1936 static const unsigned int drif1_ctrl_c_pins[] = { 1937 /* CLK, SYNC */ 1938 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11), 1939 }; 1940 static const unsigned int drif1_ctrl_c_mux[] = { 1941 RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK, 1942 }; 1943 static const unsigned int drif1_data0_c_pins[] = { 1944 /* D0 */ 1945 RCAR_GP_PIN(5, 6), 1946 }; 1947 static const unsigned int drif1_data0_c_mux[] = { 1948 RIF1_D0_C_MARK, 1949 }; 1950 static const unsigned int drif1_data1_c_pins[] = { 1951 /* D1 */ 1952 RCAR_GP_PIN(5, 10), 1953 }; 1954 static const unsigned int drif1_data1_c_mux[] = { 1955 RIF1_D1_C_MARK, 1956 }; 1957 /* - DRIF2 --------------------------------------------------------------- */ 1958 static const unsigned int drif2_ctrl_a_pins[] = { 1959 /* CLK, SYNC */ 1960 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), 1961 }; 1962 static const unsigned int drif2_ctrl_a_mux[] = { 1963 RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK, 1964 }; 1965 static const unsigned int drif2_data0_a_pins[] = { 1966 /* D0 */ 1967 RCAR_GP_PIN(6, 7), 1968 }; 1969 static const unsigned int drif2_data0_a_mux[] = { 1970 RIF2_D0_A_MARK, 1971 }; 1972 static const unsigned int drif2_data1_a_pins[] = { 1973 /* D1 */ 1974 RCAR_GP_PIN(6, 10), 1975 }; 1976 static const unsigned int drif2_data1_a_mux[] = { 1977 RIF2_D1_A_MARK, 1978 }; 1979 static const unsigned int drif2_ctrl_b_pins[] = { 1980 /* CLK, SYNC */ 1981 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27), 1982 }; 1983 static const unsigned int drif2_ctrl_b_mux[] = { 1984 RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK, 1985 }; 1986 static const unsigned int drif2_data0_b_pins[] = { 1987 /* D0 */ 1988 RCAR_GP_PIN(6, 30), 1989 }; 1990 static const unsigned int drif2_data0_b_mux[] = { 1991 RIF2_D0_B_MARK, 1992 }; 1993 static const unsigned int drif2_data1_b_pins[] = { 1994 /* D1 */ 1995 RCAR_GP_PIN(6, 31), 1996 }; 1997 static const unsigned int drif2_data1_b_mux[] = { 1998 RIF2_D1_B_MARK, 1999 }; 2000 /* - DRIF3 --------------------------------------------------------------- */ 2001 static const unsigned int drif3_ctrl_a_pins[] = { 2002 /* CLK, SYNC */ 2003 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18), 2004 }; 2005 static const unsigned int drif3_ctrl_a_mux[] = { 2006 RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK, 2007 }; 2008 static const unsigned int drif3_data0_a_pins[] = { 2009 /* D0 */ 2010 RCAR_GP_PIN(6, 19), 2011 }; 2012 static const unsigned int drif3_data0_a_mux[] = { 2013 RIF3_D0_A_MARK, 2014 }; 2015 static const unsigned int drif3_data1_a_pins[] = { 2016 /* D1 */ 2017 RCAR_GP_PIN(6, 20), 2018 }; 2019 static const unsigned int drif3_data1_a_mux[] = { 2020 RIF3_D1_A_MARK, 2021 }; 2022 static const unsigned int drif3_ctrl_b_pins[] = { 2023 /* CLK, SYNC */ 2024 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25), 2025 }; 2026 static const unsigned int drif3_ctrl_b_mux[] = { 2027 RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK, 2028 }; 2029 static const unsigned int drif3_data0_b_pins[] = { 2030 /* D0 */ 2031 RCAR_GP_PIN(6, 28), 2032 }; 2033 static const unsigned int drif3_data0_b_mux[] = { 2034 RIF3_D0_B_MARK, 2035 }; 2036 static const unsigned int drif3_data1_b_pins[] = { 2037 /* D1 */ 2038 RCAR_GP_PIN(6, 29), 2039 }; 2040 static const unsigned int drif3_data1_b_mux[] = { 2041 RIF3_D1_B_MARK, 2042 }; 2043 2044 /* - DU --------------------------------------------------------------------- */ 2045 static const unsigned int du_rgb666_pins[] = { 2046 /* R[7:2], G[7:2], B[7:2] */ 2047 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), 2048 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), 2049 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), 2050 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18), 2051 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5), 2052 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2), 2053 }; 2054 static const unsigned int du_rgb666_mux[] = { 2055 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK, 2056 DU_DR3_MARK, DU_DR2_MARK, 2057 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK, 2058 DU_DG3_MARK, DU_DG2_MARK, 2059 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK, 2060 DU_DB3_MARK, DU_DB2_MARK, 2061 }; 2062 static const unsigned int du_rgb888_pins[] = { 2063 /* R[7:0], G[7:0], B[7:0] */ 2064 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), 2065 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), 2066 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8), 2067 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), 2068 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18), 2069 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16), 2070 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5), 2071 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2), 2072 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0), 2073 }; 2074 static const unsigned int du_rgb888_mux[] = { 2075 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK, 2076 DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK, 2077 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK, 2078 DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK, 2079 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK, 2080 DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK, 2081 }; 2082 static const unsigned int du_clk_out_0_pins[] = { 2083 /* CLKOUT */ 2084 RCAR_GP_PIN(1, 27), 2085 }; 2086 static const unsigned int du_clk_out_0_mux[] = { 2087 DU_DOTCLKOUT0_MARK 2088 }; 2089 static const unsigned int du_clk_out_1_pins[] = { 2090 /* CLKOUT */ 2091 RCAR_GP_PIN(2, 3), 2092 }; 2093 static const unsigned int du_clk_out_1_mux[] = { 2094 DU_DOTCLKOUT1_MARK 2095 }; 2096 static const unsigned int du_sync_pins[] = { 2097 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */ 2098 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4), 2099 }; 2100 static const unsigned int du_sync_mux[] = { 2101 DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK 2102 }; 2103 static const unsigned int du_oddf_pins[] = { 2104 /* EXDISP/EXODDF/EXCDE */ 2105 RCAR_GP_PIN(2, 2), 2106 }; 2107 static const unsigned int du_oddf_mux[] = { 2108 DU_EXODDF_DU_ODDF_DISP_CDE_MARK, 2109 }; 2110 static const unsigned int du_cde_pins[] = { 2111 /* CDE */ 2112 RCAR_GP_PIN(2, 0), 2113 }; 2114 static const unsigned int du_cde_mux[] = { 2115 DU_CDE_MARK, 2116 }; 2117 static const unsigned int du_disp_pins[] = { 2118 /* DISP */ 2119 RCAR_GP_PIN(2, 1), 2120 }; 2121 static const unsigned int du_disp_mux[] = { 2122 DU_DISP_MARK, 2123 }; 2124 2125 /* - HSCIF0 ----------------------------------------------------------------- */ 2126 static const unsigned int hscif0_data_pins[] = { 2127 /* RX, TX */ 2128 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14), 2129 }; 2130 static const unsigned int hscif0_data_mux[] = { 2131 HRX0_MARK, HTX0_MARK, 2132 }; 2133 static const unsigned int hscif0_clk_pins[] = { 2134 /* SCK */ 2135 RCAR_GP_PIN(5, 12), 2136 }; 2137 static const unsigned int hscif0_clk_mux[] = { 2138 HSCK0_MARK, 2139 }; 2140 static const unsigned int hscif0_ctrl_pins[] = { 2141 /* RTS, CTS */ 2142 RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15), 2143 }; 2144 static const unsigned int hscif0_ctrl_mux[] = { 2145 HRTS0_N_MARK, HCTS0_N_MARK, 2146 }; 2147 /* - HSCIF1 ----------------------------------------------------------------- */ 2148 static const unsigned int hscif1_data_a_pins[] = { 2149 /* RX, TX */ 2150 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6), 2151 }; 2152 static const unsigned int hscif1_data_a_mux[] = { 2153 HRX1_A_MARK, HTX1_A_MARK, 2154 }; 2155 static const unsigned int hscif1_clk_a_pins[] = { 2156 /* SCK */ 2157 RCAR_GP_PIN(6, 21), 2158 }; 2159 static const unsigned int hscif1_clk_a_mux[] = { 2160 HSCK1_A_MARK, 2161 }; 2162 static const unsigned int hscif1_ctrl_a_pins[] = { 2163 /* RTS, CTS */ 2164 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7), 2165 }; 2166 static const unsigned int hscif1_ctrl_a_mux[] = { 2167 HRTS1_N_A_MARK, HCTS1_N_A_MARK, 2168 }; 2169 2170 static const unsigned int hscif1_data_b_pins[] = { 2171 /* RX, TX */ 2172 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), 2173 }; 2174 static const unsigned int hscif1_data_b_mux[] = { 2175 HRX1_B_MARK, HTX1_B_MARK, 2176 }; 2177 static const unsigned int hscif1_clk_b_pins[] = { 2178 /* SCK */ 2179 RCAR_GP_PIN(5, 0), 2180 }; 2181 static const unsigned int hscif1_clk_b_mux[] = { 2182 HSCK1_B_MARK, 2183 }; 2184 static const unsigned int hscif1_ctrl_b_pins[] = { 2185 /* RTS, CTS */ 2186 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3), 2187 }; 2188 static const unsigned int hscif1_ctrl_b_mux[] = { 2189 HRTS1_N_B_MARK, HCTS1_N_B_MARK, 2190 }; 2191 /* - HSCIF2 ----------------------------------------------------------------- */ 2192 static const unsigned int hscif2_data_a_pins[] = { 2193 /* RX, TX */ 2194 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), 2195 }; 2196 static const unsigned int hscif2_data_a_mux[] = { 2197 HRX2_A_MARK, HTX2_A_MARK, 2198 }; 2199 static const unsigned int hscif2_clk_a_pins[] = { 2200 /* SCK */ 2201 RCAR_GP_PIN(6, 10), 2202 }; 2203 static const unsigned int hscif2_clk_a_mux[] = { 2204 HSCK2_A_MARK, 2205 }; 2206 static const unsigned int hscif2_ctrl_a_pins[] = { 2207 /* RTS, CTS */ 2208 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6), 2209 }; 2210 static const unsigned int hscif2_ctrl_a_mux[] = { 2211 HRTS2_N_A_MARK, HCTS2_N_A_MARK, 2212 }; 2213 2214 static const unsigned int hscif2_data_b_pins[] = { 2215 /* RX, TX */ 2216 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18), 2217 }; 2218 static const unsigned int hscif2_data_b_mux[] = { 2219 HRX2_B_MARK, HTX2_B_MARK, 2220 }; 2221 static const unsigned int hscif2_clk_b_pins[] = { 2222 /* SCK */ 2223 RCAR_GP_PIN(6, 21), 2224 }; 2225 static const unsigned int hscif2_clk_b_mux[] = { 2226 HSCK2_B_MARK, 2227 }; 2228 static const unsigned int hscif2_ctrl_b_pins[] = { 2229 /* RTS, CTS */ 2230 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19), 2231 }; 2232 static const unsigned int hscif2_ctrl_b_mux[] = { 2233 HRTS2_N_B_MARK, HCTS2_N_B_MARK, 2234 }; 2235 2236 static const unsigned int hscif2_data_c_pins[] = { 2237 /* RX, TX */ 2238 RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26), 2239 }; 2240 static const unsigned int hscif2_data_c_mux[] = { 2241 HRX2_C_MARK, HTX2_C_MARK, 2242 }; 2243 static const unsigned int hscif2_clk_c_pins[] = { 2244 /* SCK */ 2245 RCAR_GP_PIN(6, 24), 2246 }; 2247 static const unsigned int hscif2_clk_c_mux[] = { 2248 HSCK2_C_MARK, 2249 }; 2250 static const unsigned int hscif2_ctrl_c_pins[] = { 2251 /* RTS, CTS */ 2252 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 27), 2253 }; 2254 static const unsigned int hscif2_ctrl_c_mux[] = { 2255 HRTS2_N_C_MARK, HCTS2_N_C_MARK, 2256 }; 2257 /* - HSCIF3 ----------------------------------------------------------------- */ 2258 static const unsigned int hscif3_data_a_pins[] = { 2259 /* RX, TX */ 2260 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24), 2261 }; 2262 static const unsigned int hscif3_data_a_mux[] = { 2263 HRX3_A_MARK, HTX3_A_MARK, 2264 }; 2265 static const unsigned int hscif3_clk_pins[] = { 2266 /* SCK */ 2267 RCAR_GP_PIN(1, 22), 2268 }; 2269 static const unsigned int hscif3_clk_mux[] = { 2270 HSCK3_MARK, 2271 }; 2272 static const unsigned int hscif3_ctrl_pins[] = { 2273 /* RTS, CTS */ 2274 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25), 2275 }; 2276 static const unsigned int hscif3_ctrl_mux[] = { 2277 HRTS3_N_MARK, HCTS3_N_MARK, 2278 }; 2279 2280 static const unsigned int hscif3_data_b_pins[] = { 2281 /* RX, TX */ 2282 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), 2283 }; 2284 static const unsigned int hscif3_data_b_mux[] = { 2285 HRX3_B_MARK, HTX3_B_MARK, 2286 }; 2287 static const unsigned int hscif3_data_c_pins[] = { 2288 /* RX, TX */ 2289 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), 2290 }; 2291 static const unsigned int hscif3_data_c_mux[] = { 2292 HRX3_C_MARK, HTX3_C_MARK, 2293 }; 2294 static const unsigned int hscif3_data_d_pins[] = { 2295 /* RX, TX */ 2296 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), 2297 }; 2298 static const unsigned int hscif3_data_d_mux[] = { 2299 HRX3_D_MARK, HTX3_D_MARK, 2300 }; 2301 /* - HSCIF4 ----------------------------------------------------------------- */ 2302 static const unsigned int hscif4_data_a_pins[] = { 2303 /* RX, TX */ 2304 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), 2305 }; 2306 static const unsigned int hscif4_data_a_mux[] = { 2307 HRX4_A_MARK, HTX4_A_MARK, 2308 }; 2309 static const unsigned int hscif4_clk_pins[] = { 2310 /* SCK */ 2311 RCAR_GP_PIN(1, 11), 2312 }; 2313 static const unsigned int hscif4_clk_mux[] = { 2314 HSCK4_MARK, 2315 }; 2316 static const unsigned int hscif4_ctrl_pins[] = { 2317 /* RTS, CTS */ 2318 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), 2319 }; 2320 static const unsigned int hscif4_ctrl_mux[] = { 2321 HRTS4_N_MARK, HCTS4_N_MARK, 2322 }; 2323 2324 static const unsigned int hscif4_data_b_pins[] = { 2325 /* RX, TX */ 2326 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), 2327 }; 2328 static const unsigned int hscif4_data_b_mux[] = { 2329 HRX4_B_MARK, HTX4_B_MARK, 2330 }; 2331 2332 /* - I2C -------------------------------------------------------------------- */ 2333 static const unsigned int i2c0_pins[] = { 2334 /* SCL, SDA */ 2335 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), 2336 }; 2337 2338 static const unsigned int i2c0_mux[] = { 2339 SCL0_MARK, SDA0_MARK, 2340 }; 2341 2342 static const unsigned int i2c1_a_pins[] = { 2343 /* SDA, SCL */ 2344 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10), 2345 }; 2346 static const unsigned int i2c1_a_mux[] = { 2347 SDA1_A_MARK, SCL1_A_MARK, 2348 }; 2349 static const unsigned int i2c1_b_pins[] = { 2350 /* SDA, SCL */ 2351 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23), 2352 }; 2353 static const unsigned int i2c1_b_mux[] = { 2354 SDA1_B_MARK, SCL1_B_MARK, 2355 }; 2356 static const unsigned int i2c2_a_pins[] = { 2357 /* SDA, SCL */ 2358 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4), 2359 }; 2360 static const unsigned int i2c2_a_mux[] = { 2361 SDA2_A_MARK, SCL2_A_MARK, 2362 }; 2363 static const unsigned int i2c2_b_pins[] = { 2364 /* SDA, SCL */ 2365 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12), 2366 }; 2367 static const unsigned int i2c2_b_mux[] = { 2368 SDA2_B_MARK, SCL2_B_MARK, 2369 }; 2370 2371 static const unsigned int i2c3_pins[] = { 2372 /* SCL, SDA */ 2373 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), 2374 }; 2375 2376 static const unsigned int i2c3_mux[] = { 2377 SCL3_MARK, SDA3_MARK, 2378 }; 2379 2380 static const unsigned int i2c5_pins[] = { 2381 /* SCL, SDA */ 2382 RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14), 2383 }; 2384 2385 static const unsigned int i2c5_mux[] = { 2386 SCL5_MARK, SDA5_MARK, 2387 }; 2388 2389 static const unsigned int i2c6_a_pins[] = { 2390 /* SDA, SCL */ 2391 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), 2392 }; 2393 static const unsigned int i2c6_a_mux[] = { 2394 SDA6_A_MARK, SCL6_A_MARK, 2395 }; 2396 static const unsigned int i2c6_b_pins[] = { 2397 /* SDA, SCL */ 2398 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25), 2399 }; 2400 static const unsigned int i2c6_b_mux[] = { 2401 SDA6_B_MARK, SCL6_B_MARK, 2402 }; 2403 static const unsigned int i2c6_c_pins[] = { 2404 /* SDA, SCL */ 2405 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), 2406 }; 2407 static const unsigned int i2c6_c_mux[] = { 2408 SDA6_C_MARK, SCL6_C_MARK, 2409 }; 2410 2411 /* - INTC-EX ---------------------------------------------------------------- */ 2412 static const unsigned int intc_ex_irq0_pins[] = { 2413 /* IRQ0 */ 2414 RCAR_GP_PIN(2, 0), 2415 }; 2416 static const unsigned int intc_ex_irq0_mux[] = { 2417 IRQ0_MARK, 2418 }; 2419 static const unsigned int intc_ex_irq1_pins[] = { 2420 /* IRQ1 */ 2421 RCAR_GP_PIN(2, 1), 2422 }; 2423 static const unsigned int intc_ex_irq1_mux[] = { 2424 IRQ1_MARK, 2425 }; 2426 static const unsigned int intc_ex_irq2_pins[] = { 2427 /* IRQ2 */ 2428 RCAR_GP_PIN(2, 2), 2429 }; 2430 static const unsigned int intc_ex_irq2_mux[] = { 2431 IRQ2_MARK, 2432 }; 2433 static const unsigned int intc_ex_irq3_pins[] = { 2434 /* IRQ3 */ 2435 RCAR_GP_PIN(2, 3), 2436 }; 2437 static const unsigned int intc_ex_irq3_mux[] = { 2438 IRQ3_MARK, 2439 }; 2440 static const unsigned int intc_ex_irq4_pins[] = { 2441 /* IRQ4 */ 2442 RCAR_GP_PIN(2, 4), 2443 }; 2444 static const unsigned int intc_ex_irq4_mux[] = { 2445 IRQ4_MARK, 2446 }; 2447 static const unsigned int intc_ex_irq5_pins[] = { 2448 /* IRQ5 */ 2449 RCAR_GP_PIN(2, 5), 2450 }; 2451 static const unsigned int intc_ex_irq5_mux[] = { 2452 IRQ5_MARK, 2453 }; 2454 2455 /* - MSIOF0 ----------------------------------------------------------------- */ 2456 static const unsigned int msiof0_clk_pins[] = { 2457 /* SCK */ 2458 RCAR_GP_PIN(5, 17), 2459 }; 2460 static const unsigned int msiof0_clk_mux[] = { 2461 MSIOF0_SCK_MARK, 2462 }; 2463 static const unsigned int msiof0_sync_pins[] = { 2464 /* SYNC */ 2465 RCAR_GP_PIN(5, 18), 2466 }; 2467 static const unsigned int msiof0_sync_mux[] = { 2468 MSIOF0_SYNC_MARK, 2469 }; 2470 static const unsigned int msiof0_ss1_pins[] = { 2471 /* SS1 */ 2472 RCAR_GP_PIN(5, 19), 2473 }; 2474 static const unsigned int msiof0_ss1_mux[] = { 2475 MSIOF0_SS1_MARK, 2476 }; 2477 static const unsigned int msiof0_ss2_pins[] = { 2478 /* SS2 */ 2479 RCAR_GP_PIN(5, 21), 2480 }; 2481 static const unsigned int msiof0_ss2_mux[] = { 2482 MSIOF0_SS2_MARK, 2483 }; 2484 static const unsigned int msiof0_txd_pins[] = { 2485 /* TXD */ 2486 RCAR_GP_PIN(5, 20), 2487 }; 2488 static const unsigned int msiof0_txd_mux[] = { 2489 MSIOF0_TXD_MARK, 2490 }; 2491 static const unsigned int msiof0_rxd_pins[] = { 2492 /* RXD */ 2493 RCAR_GP_PIN(5, 22), 2494 }; 2495 static const unsigned int msiof0_rxd_mux[] = { 2496 MSIOF0_RXD_MARK, 2497 }; 2498 /* - MSIOF1 ----------------------------------------------------------------- */ 2499 static const unsigned int msiof1_clk_a_pins[] = { 2500 /* SCK */ 2501 RCAR_GP_PIN(6, 8), 2502 }; 2503 static const unsigned int msiof1_clk_a_mux[] = { 2504 MSIOF1_SCK_A_MARK, 2505 }; 2506 static const unsigned int msiof1_sync_a_pins[] = { 2507 /* SYNC */ 2508 RCAR_GP_PIN(6, 9), 2509 }; 2510 static const unsigned int msiof1_sync_a_mux[] = { 2511 MSIOF1_SYNC_A_MARK, 2512 }; 2513 static const unsigned int msiof1_ss1_a_pins[] = { 2514 /* SS1 */ 2515 RCAR_GP_PIN(6, 5), 2516 }; 2517 static const unsigned int msiof1_ss1_a_mux[] = { 2518 MSIOF1_SS1_A_MARK, 2519 }; 2520 static const unsigned int msiof1_ss2_a_pins[] = { 2521 /* SS2 */ 2522 RCAR_GP_PIN(6, 6), 2523 }; 2524 static const unsigned int msiof1_ss2_a_mux[] = { 2525 MSIOF1_SS2_A_MARK, 2526 }; 2527 static const unsigned int msiof1_txd_a_pins[] = { 2528 /* TXD */ 2529 RCAR_GP_PIN(6, 7), 2530 }; 2531 static const unsigned int msiof1_txd_a_mux[] = { 2532 MSIOF1_TXD_A_MARK, 2533 }; 2534 static const unsigned int msiof1_rxd_a_pins[] = { 2535 /* RXD */ 2536 RCAR_GP_PIN(6, 10), 2537 }; 2538 static const unsigned int msiof1_rxd_a_mux[] = { 2539 MSIOF1_RXD_A_MARK, 2540 }; 2541 static const unsigned int msiof1_clk_b_pins[] = { 2542 /* SCK */ 2543 RCAR_GP_PIN(5, 9), 2544 }; 2545 static const unsigned int msiof1_clk_b_mux[] = { 2546 MSIOF1_SCK_B_MARK, 2547 }; 2548 static const unsigned int msiof1_sync_b_pins[] = { 2549 /* SYNC */ 2550 RCAR_GP_PIN(5, 3), 2551 }; 2552 static const unsigned int msiof1_sync_b_mux[] = { 2553 MSIOF1_SYNC_B_MARK, 2554 }; 2555 static const unsigned int msiof1_ss1_b_pins[] = { 2556 /* SS1 */ 2557 RCAR_GP_PIN(5, 4), 2558 }; 2559 static const unsigned int msiof1_ss1_b_mux[] = { 2560 MSIOF1_SS1_B_MARK, 2561 }; 2562 static const unsigned int msiof1_ss2_b_pins[] = { 2563 /* SS2 */ 2564 RCAR_GP_PIN(5, 0), 2565 }; 2566 static const unsigned int msiof1_ss2_b_mux[] = { 2567 MSIOF1_SS2_B_MARK, 2568 }; 2569 static const unsigned int msiof1_txd_b_pins[] = { 2570 /* TXD */ 2571 RCAR_GP_PIN(5, 8), 2572 }; 2573 static const unsigned int msiof1_txd_b_mux[] = { 2574 MSIOF1_TXD_B_MARK, 2575 }; 2576 static const unsigned int msiof1_rxd_b_pins[] = { 2577 /* RXD */ 2578 RCAR_GP_PIN(5, 7), 2579 }; 2580 static const unsigned int msiof1_rxd_b_mux[] = { 2581 MSIOF1_RXD_B_MARK, 2582 }; 2583 static const unsigned int msiof1_clk_c_pins[] = { 2584 /* SCK */ 2585 RCAR_GP_PIN(6, 17), 2586 }; 2587 static const unsigned int msiof1_clk_c_mux[] = { 2588 MSIOF1_SCK_C_MARK, 2589 }; 2590 static const unsigned int msiof1_sync_c_pins[] = { 2591 /* SYNC */ 2592 RCAR_GP_PIN(6, 18), 2593 }; 2594 static const unsigned int msiof1_sync_c_mux[] = { 2595 MSIOF1_SYNC_C_MARK, 2596 }; 2597 static const unsigned int msiof1_ss1_c_pins[] = { 2598 /* SS1 */ 2599 RCAR_GP_PIN(6, 21), 2600 }; 2601 static const unsigned int msiof1_ss1_c_mux[] = { 2602 MSIOF1_SS1_C_MARK, 2603 }; 2604 static const unsigned int msiof1_ss2_c_pins[] = { 2605 /* SS2 */ 2606 RCAR_GP_PIN(6, 27), 2607 }; 2608 static const unsigned int msiof1_ss2_c_mux[] = { 2609 MSIOF1_SS2_C_MARK, 2610 }; 2611 static const unsigned int msiof1_txd_c_pins[] = { 2612 /* TXD */ 2613 RCAR_GP_PIN(6, 20), 2614 }; 2615 static const unsigned int msiof1_txd_c_mux[] = { 2616 MSIOF1_TXD_C_MARK, 2617 }; 2618 static const unsigned int msiof1_rxd_c_pins[] = { 2619 /* RXD */ 2620 RCAR_GP_PIN(6, 19), 2621 }; 2622 static const unsigned int msiof1_rxd_c_mux[] = { 2623 MSIOF1_RXD_C_MARK, 2624 }; 2625 static const unsigned int msiof1_clk_d_pins[] = { 2626 /* SCK */ 2627 RCAR_GP_PIN(5, 12), 2628 }; 2629 static const unsigned int msiof1_clk_d_mux[] = { 2630 MSIOF1_SCK_D_MARK, 2631 }; 2632 static const unsigned int msiof1_sync_d_pins[] = { 2633 /* SYNC */ 2634 RCAR_GP_PIN(5, 15), 2635 }; 2636 static const unsigned int msiof1_sync_d_mux[] = { 2637 MSIOF1_SYNC_D_MARK, 2638 }; 2639 static const unsigned int msiof1_ss1_d_pins[] = { 2640 /* SS1 */ 2641 RCAR_GP_PIN(5, 16), 2642 }; 2643 static const unsigned int msiof1_ss1_d_mux[] = { 2644 MSIOF1_SS1_D_MARK, 2645 }; 2646 static const unsigned int msiof1_ss2_d_pins[] = { 2647 /* SS2 */ 2648 RCAR_GP_PIN(5, 21), 2649 }; 2650 static const unsigned int msiof1_ss2_d_mux[] = { 2651 MSIOF1_SS2_D_MARK, 2652 }; 2653 static const unsigned int msiof1_txd_d_pins[] = { 2654 /* TXD */ 2655 RCAR_GP_PIN(5, 14), 2656 }; 2657 static const unsigned int msiof1_txd_d_mux[] = { 2658 MSIOF1_TXD_D_MARK, 2659 }; 2660 static const unsigned int msiof1_rxd_d_pins[] = { 2661 /* RXD */ 2662 RCAR_GP_PIN(5, 13), 2663 }; 2664 static const unsigned int msiof1_rxd_d_mux[] = { 2665 MSIOF1_RXD_D_MARK, 2666 }; 2667 static const unsigned int msiof1_clk_e_pins[] = { 2668 /* SCK */ 2669 RCAR_GP_PIN(3, 0), 2670 }; 2671 static const unsigned int msiof1_clk_e_mux[] = { 2672 MSIOF1_SCK_E_MARK, 2673 }; 2674 static const unsigned int msiof1_sync_e_pins[] = { 2675 /* SYNC */ 2676 RCAR_GP_PIN(3, 1), 2677 }; 2678 static const unsigned int msiof1_sync_e_mux[] = { 2679 MSIOF1_SYNC_E_MARK, 2680 }; 2681 static const unsigned int msiof1_ss1_e_pins[] = { 2682 /* SS1 */ 2683 RCAR_GP_PIN(3, 4), 2684 }; 2685 static const unsigned int msiof1_ss1_e_mux[] = { 2686 MSIOF1_SS1_E_MARK, 2687 }; 2688 static const unsigned int msiof1_ss2_e_pins[] = { 2689 /* SS2 */ 2690 RCAR_GP_PIN(3, 5), 2691 }; 2692 static const unsigned int msiof1_ss2_e_mux[] = { 2693 MSIOF1_SS2_E_MARK, 2694 }; 2695 static const unsigned int msiof1_txd_e_pins[] = { 2696 /* TXD */ 2697 RCAR_GP_PIN(3, 3), 2698 }; 2699 static const unsigned int msiof1_txd_e_mux[] = { 2700 MSIOF1_TXD_E_MARK, 2701 }; 2702 static const unsigned int msiof1_rxd_e_pins[] = { 2703 /* RXD */ 2704 RCAR_GP_PIN(3, 2), 2705 }; 2706 static const unsigned int msiof1_rxd_e_mux[] = { 2707 MSIOF1_RXD_E_MARK, 2708 }; 2709 static const unsigned int msiof1_clk_f_pins[] = { 2710 /* SCK */ 2711 RCAR_GP_PIN(5, 23), 2712 }; 2713 static const unsigned int msiof1_clk_f_mux[] = { 2714 MSIOF1_SCK_F_MARK, 2715 }; 2716 static const unsigned int msiof1_sync_f_pins[] = { 2717 /* SYNC */ 2718 RCAR_GP_PIN(5, 24), 2719 }; 2720 static const unsigned int msiof1_sync_f_mux[] = { 2721 MSIOF1_SYNC_F_MARK, 2722 }; 2723 static const unsigned int msiof1_ss1_f_pins[] = { 2724 /* SS1 */ 2725 RCAR_GP_PIN(6, 1), 2726 }; 2727 static const unsigned int msiof1_ss1_f_mux[] = { 2728 MSIOF1_SS1_F_MARK, 2729 }; 2730 static const unsigned int msiof1_ss2_f_pins[] = { 2731 /* SS2 */ 2732 RCAR_GP_PIN(6, 2), 2733 }; 2734 static const unsigned int msiof1_ss2_f_mux[] = { 2735 MSIOF1_SS2_F_MARK, 2736 }; 2737 static const unsigned int msiof1_txd_f_pins[] = { 2738 /* TXD */ 2739 RCAR_GP_PIN(6, 0), 2740 }; 2741 static const unsigned int msiof1_txd_f_mux[] = { 2742 MSIOF1_TXD_F_MARK, 2743 }; 2744 static const unsigned int msiof1_rxd_f_pins[] = { 2745 /* RXD */ 2746 RCAR_GP_PIN(5, 25), 2747 }; 2748 static const unsigned int msiof1_rxd_f_mux[] = { 2749 MSIOF1_RXD_F_MARK, 2750 }; 2751 static const unsigned int msiof1_clk_g_pins[] = { 2752 /* SCK */ 2753 RCAR_GP_PIN(3, 6), 2754 }; 2755 static const unsigned int msiof1_clk_g_mux[] = { 2756 MSIOF1_SCK_G_MARK, 2757 }; 2758 static const unsigned int msiof1_sync_g_pins[] = { 2759 /* SYNC */ 2760 RCAR_GP_PIN(3, 7), 2761 }; 2762 static const unsigned int msiof1_sync_g_mux[] = { 2763 MSIOF1_SYNC_G_MARK, 2764 }; 2765 static const unsigned int msiof1_ss1_g_pins[] = { 2766 /* SS1 */ 2767 RCAR_GP_PIN(3, 10), 2768 }; 2769 static const unsigned int msiof1_ss1_g_mux[] = { 2770 MSIOF1_SS1_G_MARK, 2771 }; 2772 static const unsigned int msiof1_ss2_g_pins[] = { 2773 /* SS2 */ 2774 RCAR_GP_PIN(3, 11), 2775 }; 2776 static const unsigned int msiof1_ss2_g_mux[] = { 2777 MSIOF1_SS2_G_MARK, 2778 }; 2779 static const unsigned int msiof1_txd_g_pins[] = { 2780 /* TXD */ 2781 RCAR_GP_PIN(3, 9), 2782 }; 2783 static const unsigned int msiof1_txd_g_mux[] = { 2784 MSIOF1_TXD_G_MARK, 2785 }; 2786 static const unsigned int msiof1_rxd_g_pins[] = { 2787 /* RXD */ 2788 RCAR_GP_PIN(3, 8), 2789 }; 2790 static const unsigned int msiof1_rxd_g_mux[] = { 2791 MSIOF1_RXD_G_MARK, 2792 }; 2793 /* - MSIOF2 ----------------------------------------------------------------- */ 2794 static const unsigned int msiof2_clk_a_pins[] = { 2795 /* SCK */ 2796 RCAR_GP_PIN(1, 9), 2797 }; 2798 static const unsigned int msiof2_clk_a_mux[] = { 2799 MSIOF2_SCK_A_MARK, 2800 }; 2801 static const unsigned int msiof2_sync_a_pins[] = { 2802 /* SYNC */ 2803 RCAR_GP_PIN(1, 8), 2804 }; 2805 static const unsigned int msiof2_sync_a_mux[] = { 2806 MSIOF2_SYNC_A_MARK, 2807 }; 2808 static const unsigned int msiof2_ss1_a_pins[] = { 2809 /* SS1 */ 2810 RCAR_GP_PIN(1, 6), 2811 }; 2812 static const unsigned int msiof2_ss1_a_mux[] = { 2813 MSIOF2_SS1_A_MARK, 2814 }; 2815 static const unsigned int msiof2_ss2_a_pins[] = { 2816 /* SS2 */ 2817 RCAR_GP_PIN(1, 7), 2818 }; 2819 static const unsigned int msiof2_ss2_a_mux[] = { 2820 MSIOF2_SS2_A_MARK, 2821 }; 2822 static const unsigned int msiof2_txd_a_pins[] = { 2823 /* TXD */ 2824 RCAR_GP_PIN(1, 11), 2825 }; 2826 static const unsigned int msiof2_txd_a_mux[] = { 2827 MSIOF2_TXD_A_MARK, 2828 }; 2829 static const unsigned int msiof2_rxd_a_pins[] = { 2830 /* RXD */ 2831 RCAR_GP_PIN(1, 10), 2832 }; 2833 static const unsigned int msiof2_rxd_a_mux[] = { 2834 MSIOF2_RXD_A_MARK, 2835 }; 2836 static const unsigned int msiof2_clk_b_pins[] = { 2837 /* SCK */ 2838 RCAR_GP_PIN(0, 4), 2839 }; 2840 static const unsigned int msiof2_clk_b_mux[] = { 2841 MSIOF2_SCK_B_MARK, 2842 }; 2843 static const unsigned int msiof2_sync_b_pins[] = { 2844 /* SYNC */ 2845 RCAR_GP_PIN(0, 5), 2846 }; 2847 static const unsigned int msiof2_sync_b_mux[] = { 2848 MSIOF2_SYNC_B_MARK, 2849 }; 2850 static const unsigned int msiof2_ss1_b_pins[] = { 2851 /* SS1 */ 2852 RCAR_GP_PIN(0, 0), 2853 }; 2854 static const unsigned int msiof2_ss1_b_mux[] = { 2855 MSIOF2_SS1_B_MARK, 2856 }; 2857 static const unsigned int msiof2_ss2_b_pins[] = { 2858 /* SS2 */ 2859 RCAR_GP_PIN(0, 1), 2860 }; 2861 static const unsigned int msiof2_ss2_b_mux[] = { 2862 MSIOF2_SS2_B_MARK, 2863 }; 2864 static const unsigned int msiof2_txd_b_pins[] = { 2865 /* TXD */ 2866 RCAR_GP_PIN(0, 7), 2867 }; 2868 static const unsigned int msiof2_txd_b_mux[] = { 2869 MSIOF2_TXD_B_MARK, 2870 }; 2871 static const unsigned int msiof2_rxd_b_pins[] = { 2872 /* RXD */ 2873 RCAR_GP_PIN(0, 6), 2874 }; 2875 static const unsigned int msiof2_rxd_b_mux[] = { 2876 MSIOF2_RXD_B_MARK, 2877 }; 2878 static const unsigned int msiof2_clk_c_pins[] = { 2879 /* SCK */ 2880 RCAR_GP_PIN(2, 12), 2881 }; 2882 static const unsigned int msiof2_clk_c_mux[] = { 2883 MSIOF2_SCK_C_MARK, 2884 }; 2885 static const unsigned int msiof2_sync_c_pins[] = { 2886 /* SYNC */ 2887 RCAR_GP_PIN(2, 11), 2888 }; 2889 static const unsigned int msiof2_sync_c_mux[] = { 2890 MSIOF2_SYNC_C_MARK, 2891 }; 2892 static const unsigned int msiof2_ss1_c_pins[] = { 2893 /* SS1 */ 2894 RCAR_GP_PIN(2, 10), 2895 }; 2896 static const unsigned int msiof2_ss1_c_mux[] = { 2897 MSIOF2_SS1_C_MARK, 2898 }; 2899 static const unsigned int msiof2_ss2_c_pins[] = { 2900 /* SS2 */ 2901 RCAR_GP_PIN(2, 9), 2902 }; 2903 static const unsigned int msiof2_ss2_c_mux[] = { 2904 MSIOF2_SS2_C_MARK, 2905 }; 2906 static const unsigned int msiof2_txd_c_pins[] = { 2907 /* TXD */ 2908 RCAR_GP_PIN(2, 14), 2909 }; 2910 static const unsigned int msiof2_txd_c_mux[] = { 2911 MSIOF2_TXD_C_MARK, 2912 }; 2913 static const unsigned int msiof2_rxd_c_pins[] = { 2914 /* RXD */ 2915 RCAR_GP_PIN(2, 13), 2916 }; 2917 static const unsigned int msiof2_rxd_c_mux[] = { 2918 MSIOF2_RXD_C_MARK, 2919 }; 2920 static const unsigned int msiof2_clk_d_pins[] = { 2921 /* SCK */ 2922 RCAR_GP_PIN(0, 8), 2923 }; 2924 static const unsigned int msiof2_clk_d_mux[] = { 2925 MSIOF2_SCK_D_MARK, 2926 }; 2927 static const unsigned int msiof2_sync_d_pins[] = { 2928 /* SYNC */ 2929 RCAR_GP_PIN(0, 9), 2930 }; 2931 static const unsigned int msiof2_sync_d_mux[] = { 2932 MSIOF2_SYNC_D_MARK, 2933 }; 2934 static const unsigned int msiof2_ss1_d_pins[] = { 2935 /* SS1 */ 2936 RCAR_GP_PIN(0, 12), 2937 }; 2938 static const unsigned int msiof2_ss1_d_mux[] = { 2939 MSIOF2_SS1_D_MARK, 2940 }; 2941 static const unsigned int msiof2_ss2_d_pins[] = { 2942 /* SS2 */ 2943 RCAR_GP_PIN(0, 13), 2944 }; 2945 static const unsigned int msiof2_ss2_d_mux[] = { 2946 MSIOF2_SS2_D_MARK, 2947 }; 2948 static const unsigned int msiof2_txd_d_pins[] = { 2949 /* TXD */ 2950 RCAR_GP_PIN(0, 11), 2951 }; 2952 static const unsigned int msiof2_txd_d_mux[] = { 2953 MSIOF2_TXD_D_MARK, 2954 }; 2955 static const unsigned int msiof2_rxd_d_pins[] = { 2956 /* RXD */ 2957 RCAR_GP_PIN(0, 10), 2958 }; 2959 static const unsigned int msiof2_rxd_d_mux[] = { 2960 MSIOF2_RXD_D_MARK, 2961 }; 2962 /* - MSIOF3 ----------------------------------------------------------------- */ 2963 static const unsigned int msiof3_clk_a_pins[] = { 2964 /* SCK */ 2965 RCAR_GP_PIN(0, 0), 2966 }; 2967 static const unsigned int msiof3_clk_a_mux[] = { 2968 MSIOF3_SCK_A_MARK, 2969 }; 2970 static const unsigned int msiof3_sync_a_pins[] = { 2971 /* SYNC */ 2972 RCAR_GP_PIN(0, 1), 2973 }; 2974 static const unsigned int msiof3_sync_a_mux[] = { 2975 MSIOF3_SYNC_A_MARK, 2976 }; 2977 static const unsigned int msiof3_ss1_a_pins[] = { 2978 /* SS1 */ 2979 RCAR_GP_PIN(0, 14), 2980 }; 2981 static const unsigned int msiof3_ss1_a_mux[] = { 2982 MSIOF3_SS1_A_MARK, 2983 }; 2984 static const unsigned int msiof3_ss2_a_pins[] = { 2985 /* SS2 */ 2986 RCAR_GP_PIN(0, 15), 2987 }; 2988 static const unsigned int msiof3_ss2_a_mux[] = { 2989 MSIOF3_SS2_A_MARK, 2990 }; 2991 static const unsigned int msiof3_txd_a_pins[] = { 2992 /* TXD */ 2993 RCAR_GP_PIN(0, 3), 2994 }; 2995 static const unsigned int msiof3_txd_a_mux[] = { 2996 MSIOF3_TXD_A_MARK, 2997 }; 2998 static const unsigned int msiof3_rxd_a_pins[] = { 2999 /* RXD */ 3000 RCAR_GP_PIN(0, 2), 3001 }; 3002 static const unsigned int msiof3_rxd_a_mux[] = { 3003 MSIOF3_RXD_A_MARK, 3004 }; 3005 static const unsigned int msiof3_clk_b_pins[] = { 3006 /* SCK */ 3007 RCAR_GP_PIN(1, 2), 3008 }; 3009 static const unsigned int msiof3_clk_b_mux[] = { 3010 MSIOF3_SCK_B_MARK, 3011 }; 3012 static const unsigned int msiof3_sync_b_pins[] = { 3013 /* SYNC */ 3014 RCAR_GP_PIN(1, 0), 3015 }; 3016 static const unsigned int msiof3_sync_b_mux[] = { 3017 MSIOF3_SYNC_B_MARK, 3018 }; 3019 static const unsigned int msiof3_ss1_b_pins[] = { 3020 /* SS1 */ 3021 RCAR_GP_PIN(1, 4), 3022 }; 3023 static const unsigned int msiof3_ss1_b_mux[] = { 3024 MSIOF3_SS1_B_MARK, 3025 }; 3026 static const unsigned int msiof3_ss2_b_pins[] = { 3027 /* SS2 */ 3028 RCAR_GP_PIN(1, 5), 3029 }; 3030 static const unsigned int msiof3_ss2_b_mux[] = { 3031 MSIOF3_SS2_B_MARK, 3032 }; 3033 static const unsigned int msiof3_txd_b_pins[] = { 3034 /* TXD */ 3035 RCAR_GP_PIN(1, 1), 3036 }; 3037 static const unsigned int msiof3_txd_b_mux[] = { 3038 MSIOF3_TXD_B_MARK, 3039 }; 3040 static const unsigned int msiof3_rxd_b_pins[] = { 3041 /* RXD */ 3042 RCAR_GP_PIN(1, 3), 3043 }; 3044 static const unsigned int msiof3_rxd_b_mux[] = { 3045 MSIOF3_RXD_B_MARK, 3046 }; 3047 static const unsigned int msiof3_clk_c_pins[] = { 3048 /* SCK */ 3049 RCAR_GP_PIN(1, 12), 3050 }; 3051 static const unsigned int msiof3_clk_c_mux[] = { 3052 MSIOF3_SCK_C_MARK, 3053 }; 3054 static const unsigned int msiof3_sync_c_pins[] = { 3055 /* SYNC */ 3056 RCAR_GP_PIN(1, 13), 3057 }; 3058 static const unsigned int msiof3_sync_c_mux[] = { 3059 MSIOF3_SYNC_C_MARK, 3060 }; 3061 static const unsigned int msiof3_txd_c_pins[] = { 3062 /* TXD */ 3063 RCAR_GP_PIN(1, 15), 3064 }; 3065 static const unsigned int msiof3_txd_c_mux[] = { 3066 MSIOF3_TXD_C_MARK, 3067 }; 3068 static const unsigned int msiof3_rxd_c_pins[] = { 3069 /* RXD */ 3070 RCAR_GP_PIN(1, 14), 3071 }; 3072 static const unsigned int msiof3_rxd_c_mux[] = { 3073 MSIOF3_RXD_C_MARK, 3074 }; 3075 static const unsigned int msiof3_clk_d_pins[] = { 3076 /* SCK */ 3077 RCAR_GP_PIN(1, 22), 3078 }; 3079 static const unsigned int msiof3_clk_d_mux[] = { 3080 MSIOF3_SCK_D_MARK, 3081 }; 3082 static const unsigned int msiof3_sync_d_pins[] = { 3083 /* SYNC */ 3084 RCAR_GP_PIN(1, 23), 3085 }; 3086 static const unsigned int msiof3_sync_d_mux[] = { 3087 MSIOF3_SYNC_D_MARK, 3088 }; 3089 static const unsigned int msiof3_ss1_d_pins[] = { 3090 /* SS1 */ 3091 RCAR_GP_PIN(1, 26), 3092 }; 3093 static const unsigned int msiof3_ss1_d_mux[] = { 3094 MSIOF3_SS1_D_MARK, 3095 }; 3096 static const unsigned int msiof3_txd_d_pins[] = { 3097 /* TXD */ 3098 RCAR_GP_PIN(1, 25), 3099 }; 3100 static const unsigned int msiof3_txd_d_mux[] = { 3101 MSIOF3_TXD_D_MARK, 3102 }; 3103 static const unsigned int msiof3_rxd_d_pins[] = { 3104 /* RXD */ 3105 RCAR_GP_PIN(1, 24), 3106 }; 3107 static const unsigned int msiof3_rxd_d_mux[] = { 3108 MSIOF3_RXD_D_MARK, 3109 }; 3110 static const unsigned int msiof3_clk_e_pins[] = { 3111 /* SCK */ 3112 RCAR_GP_PIN(2, 3), 3113 }; 3114 static const unsigned int msiof3_clk_e_mux[] = { 3115 MSIOF3_SCK_E_MARK, 3116 }; 3117 static const unsigned int msiof3_sync_e_pins[] = { 3118 /* SYNC */ 3119 RCAR_GP_PIN(2, 2), 3120 }; 3121 static const unsigned int msiof3_sync_e_mux[] = { 3122 MSIOF3_SYNC_E_MARK, 3123 }; 3124 static const unsigned int msiof3_ss1_e_pins[] = { 3125 /* SS1 */ 3126 RCAR_GP_PIN(2, 1), 3127 }; 3128 static const unsigned int msiof3_ss1_e_mux[] = { 3129 MSIOF3_SS1_E_MARK, 3130 }; 3131 static const unsigned int msiof3_ss2_e_pins[] = { 3132 /* SS2 */ 3133 RCAR_GP_PIN(2, 0), 3134 }; 3135 static const unsigned int msiof3_ss2_e_mux[] = { 3136 MSIOF3_SS2_E_MARK, 3137 }; 3138 static const unsigned int msiof3_txd_e_pins[] = { 3139 /* TXD */ 3140 RCAR_GP_PIN(2, 5), 3141 }; 3142 static const unsigned int msiof3_txd_e_mux[] = { 3143 MSIOF3_TXD_E_MARK, 3144 }; 3145 static const unsigned int msiof3_rxd_e_pins[] = { 3146 /* RXD */ 3147 RCAR_GP_PIN(2, 4), 3148 }; 3149 static const unsigned int msiof3_rxd_e_mux[] = { 3150 MSIOF3_RXD_E_MARK, 3151 }; 3152 3153 /* - PWM0 --------------------------------------------------------------------*/ 3154 static const unsigned int pwm0_pins[] = { 3155 /* PWM */ 3156 RCAR_GP_PIN(2, 6), 3157 }; 3158 static const unsigned int pwm0_mux[] = { 3159 PWM0_MARK, 3160 }; 3161 /* - PWM1 --------------------------------------------------------------------*/ 3162 static const unsigned int pwm1_a_pins[] = { 3163 /* PWM */ 3164 RCAR_GP_PIN(2, 7), 3165 }; 3166 static const unsigned int pwm1_a_mux[] = { 3167 PWM1_A_MARK, 3168 }; 3169 static const unsigned int pwm1_b_pins[] = { 3170 /* PWM */ 3171 RCAR_GP_PIN(1, 8), 3172 }; 3173 static const unsigned int pwm1_b_mux[] = { 3174 PWM1_B_MARK, 3175 }; 3176 /* - PWM2 --------------------------------------------------------------------*/ 3177 static const unsigned int pwm2_a_pins[] = { 3178 /* PWM */ 3179 RCAR_GP_PIN(2, 8), 3180 }; 3181 static const unsigned int pwm2_a_mux[] = { 3182 PWM2_A_MARK, 3183 }; 3184 static const unsigned int pwm2_b_pins[] = { 3185 /* PWM */ 3186 RCAR_GP_PIN(1, 11), 3187 }; 3188 static const unsigned int pwm2_b_mux[] = { 3189 PWM2_B_MARK, 3190 }; 3191 /* - PWM3 --------------------------------------------------------------------*/ 3192 static const unsigned int pwm3_a_pins[] = { 3193 /* PWM */ 3194 RCAR_GP_PIN(1, 0), 3195 }; 3196 static const unsigned int pwm3_a_mux[] = { 3197 PWM3_A_MARK, 3198 }; 3199 static const unsigned int pwm3_b_pins[] = { 3200 /* PWM */ 3201 RCAR_GP_PIN(2, 2), 3202 }; 3203 static const unsigned int pwm3_b_mux[] = { 3204 PWM3_B_MARK, 3205 }; 3206 /* - PWM4 --------------------------------------------------------------------*/ 3207 static const unsigned int pwm4_a_pins[] = { 3208 /* PWM */ 3209 RCAR_GP_PIN(1, 1), 3210 }; 3211 static const unsigned int pwm4_a_mux[] = { 3212 PWM4_A_MARK, 3213 }; 3214 static const unsigned int pwm4_b_pins[] = { 3215 /* PWM */ 3216 RCAR_GP_PIN(2, 3), 3217 }; 3218 static const unsigned int pwm4_b_mux[] = { 3219 PWM4_B_MARK, 3220 }; 3221 /* - PWM5 --------------------------------------------------------------------*/ 3222 static const unsigned int pwm5_a_pins[] = { 3223 /* PWM */ 3224 RCAR_GP_PIN(1, 2), 3225 }; 3226 static const unsigned int pwm5_a_mux[] = { 3227 PWM5_A_MARK, 3228 }; 3229 static const unsigned int pwm5_b_pins[] = { 3230 /* PWM */ 3231 RCAR_GP_PIN(2, 4), 3232 }; 3233 static const unsigned int pwm5_b_mux[] = { 3234 PWM5_B_MARK, 3235 }; 3236 /* - PWM6 --------------------------------------------------------------------*/ 3237 static const unsigned int pwm6_a_pins[] = { 3238 /* PWM */ 3239 RCAR_GP_PIN(1, 3), 3240 }; 3241 static const unsigned int pwm6_a_mux[] = { 3242 PWM6_A_MARK, 3243 }; 3244 static const unsigned int pwm6_b_pins[] = { 3245 /* PWM */ 3246 RCAR_GP_PIN(2, 5), 3247 }; 3248 static const unsigned int pwm6_b_mux[] = { 3249 PWM6_B_MARK, 3250 }; 3251 3252 /* - SATA --------------------------------------------------------------------*/ 3253 static const unsigned int sata0_devslp_a_pins[] = { 3254 /* DEVSLP */ 3255 RCAR_GP_PIN(6, 16), 3256 }; 3257 static const unsigned int sata0_devslp_a_mux[] = { 3258 SATA_DEVSLP_A_MARK, 3259 }; 3260 static const unsigned int sata0_devslp_b_pins[] = { 3261 /* DEVSLP */ 3262 RCAR_GP_PIN(4, 6), 3263 }; 3264 static const unsigned int sata0_devslp_b_mux[] = { 3265 SATA_DEVSLP_B_MARK, 3266 }; 3267 3268 /* - SCIF0 ------------------------------------------------------------------ */ 3269 static const unsigned int scif0_data_pins[] = { 3270 /* RX, TX */ 3271 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), 3272 }; 3273 static const unsigned int scif0_data_mux[] = { 3274 RX0_MARK, TX0_MARK, 3275 }; 3276 static const unsigned int scif0_clk_pins[] = { 3277 /* SCK */ 3278 RCAR_GP_PIN(5, 0), 3279 }; 3280 static const unsigned int scif0_clk_mux[] = { 3281 SCK0_MARK, 3282 }; 3283 static const unsigned int scif0_ctrl_pins[] = { 3284 /* RTS, CTS */ 3285 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3), 3286 }; 3287 static const unsigned int scif0_ctrl_mux[] = { 3288 RTS0_N_MARK, CTS0_N_MARK, 3289 }; 3290 /* - SCIF1 ------------------------------------------------------------------ */ 3291 static const unsigned int scif1_data_a_pins[] = { 3292 /* RX, TX */ 3293 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6), 3294 }; 3295 static const unsigned int scif1_data_a_mux[] = { 3296 RX1_A_MARK, TX1_A_MARK, 3297 }; 3298 static const unsigned int scif1_clk_pins[] = { 3299 /* SCK */ 3300 RCAR_GP_PIN(6, 21), 3301 }; 3302 static const unsigned int scif1_clk_mux[] = { 3303 SCK1_MARK, 3304 }; 3305 static const unsigned int scif1_ctrl_pins[] = { 3306 /* RTS, CTS */ 3307 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7), 3308 }; 3309 static const unsigned int scif1_ctrl_mux[] = { 3310 RTS1_N_MARK, CTS1_N_MARK, 3311 }; 3312 3313 static const unsigned int scif1_data_b_pins[] = { 3314 /* RX, TX */ 3315 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25), 3316 }; 3317 static const unsigned int scif1_data_b_mux[] = { 3318 RX1_B_MARK, TX1_B_MARK, 3319 }; 3320 /* - SCIF2 ------------------------------------------------------------------ */ 3321 static const unsigned int scif2_data_a_pins[] = { 3322 /* RX, TX */ 3323 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10), 3324 }; 3325 static const unsigned int scif2_data_a_mux[] = { 3326 RX2_A_MARK, TX2_A_MARK, 3327 }; 3328 static const unsigned int scif2_clk_pins[] = { 3329 /* SCK */ 3330 RCAR_GP_PIN(5, 9), 3331 }; 3332 static const unsigned int scif2_clk_mux[] = { 3333 SCK2_MARK, 3334 }; 3335 static const unsigned int scif2_data_b_pins[] = { 3336 /* RX, TX */ 3337 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16), 3338 }; 3339 static const unsigned int scif2_data_b_mux[] = { 3340 RX2_B_MARK, TX2_B_MARK, 3341 }; 3342 /* - SCIF3 ------------------------------------------------------------------ */ 3343 static const unsigned int scif3_data_a_pins[] = { 3344 /* RX, TX */ 3345 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24), 3346 }; 3347 static const unsigned int scif3_data_a_mux[] = { 3348 RX3_A_MARK, TX3_A_MARK, 3349 }; 3350 static const unsigned int scif3_clk_pins[] = { 3351 /* SCK */ 3352 RCAR_GP_PIN(1, 22), 3353 }; 3354 static const unsigned int scif3_clk_mux[] = { 3355 SCK3_MARK, 3356 }; 3357 static const unsigned int scif3_ctrl_pins[] = { 3358 /* RTS, CTS */ 3359 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25), 3360 }; 3361 static const unsigned int scif3_ctrl_mux[] = { 3362 RTS3_N_MARK, CTS3_N_MARK, 3363 }; 3364 static const unsigned int scif3_data_b_pins[] = { 3365 /* RX, TX */ 3366 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), 3367 }; 3368 static const unsigned int scif3_data_b_mux[] = { 3369 RX3_B_MARK, TX3_B_MARK, 3370 }; 3371 /* - SCIF4 ------------------------------------------------------------------ */ 3372 static const unsigned int scif4_data_a_pins[] = { 3373 /* RX, TX */ 3374 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12), 3375 }; 3376 static const unsigned int scif4_data_a_mux[] = { 3377 RX4_A_MARK, TX4_A_MARK, 3378 }; 3379 static const unsigned int scif4_clk_a_pins[] = { 3380 /* SCK */ 3381 RCAR_GP_PIN(2, 10), 3382 }; 3383 static const unsigned int scif4_clk_a_mux[] = { 3384 SCK4_A_MARK, 3385 }; 3386 static const unsigned int scif4_ctrl_a_pins[] = { 3387 /* RTS, CTS */ 3388 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13), 3389 }; 3390 static const unsigned int scif4_ctrl_a_mux[] = { 3391 RTS4_N_A_MARK, CTS4_N_A_MARK, 3392 }; 3393 static const unsigned int scif4_data_b_pins[] = { 3394 /* RX, TX */ 3395 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 3396 }; 3397 static const unsigned int scif4_data_b_mux[] = { 3398 RX4_B_MARK, TX4_B_MARK, 3399 }; 3400 static const unsigned int scif4_clk_b_pins[] = { 3401 /* SCK */ 3402 RCAR_GP_PIN(1, 5), 3403 }; 3404 static const unsigned int scif4_clk_b_mux[] = { 3405 SCK4_B_MARK, 3406 }; 3407 static const unsigned int scif4_ctrl_b_pins[] = { 3408 /* RTS, CTS */ 3409 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9), 3410 }; 3411 static const unsigned int scif4_ctrl_b_mux[] = { 3412 RTS4_N_B_MARK, CTS4_N_B_MARK, 3413 }; 3414 static const unsigned int scif4_data_c_pins[] = { 3415 /* RX, TX */ 3416 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), 3417 }; 3418 static const unsigned int scif4_data_c_mux[] = { 3419 RX4_C_MARK, TX4_C_MARK, 3420 }; 3421 static const unsigned int scif4_clk_c_pins[] = { 3422 /* SCK */ 3423 RCAR_GP_PIN(0, 8), 3424 }; 3425 static const unsigned int scif4_clk_c_mux[] = { 3426 SCK4_C_MARK, 3427 }; 3428 static const unsigned int scif4_ctrl_c_pins[] = { 3429 /* RTS, CTS */ 3430 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), 3431 }; 3432 static const unsigned int scif4_ctrl_c_mux[] = { 3433 RTS4_N_C_MARK, CTS4_N_C_MARK, 3434 }; 3435 /* - SCIF5 ------------------------------------------------------------------ */ 3436 static const unsigned int scif5_data_a_pins[] = { 3437 /* RX, TX */ 3438 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21), 3439 }; 3440 static const unsigned int scif5_data_a_mux[] = { 3441 RX5_A_MARK, TX5_A_MARK, 3442 }; 3443 static const unsigned int scif5_clk_a_pins[] = { 3444 /* SCK */ 3445 RCAR_GP_PIN(6, 21), 3446 }; 3447 static const unsigned int scif5_clk_a_mux[] = { 3448 SCK5_A_MARK, 3449 }; 3450 static const unsigned int scif5_data_b_pins[] = { 3451 /* RX, TX */ 3452 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18), 3453 }; 3454 static const unsigned int scif5_data_b_mux[] = { 3455 RX5_B_MARK, TX5_B_MARK, 3456 }; 3457 static const unsigned int scif5_clk_b_pins[] = { 3458 /* SCK */ 3459 RCAR_GP_PIN(5, 0), 3460 }; 3461 static const unsigned int scif5_clk_b_mux[] = { 3462 SCK5_B_MARK, 3463 }; 3464 3465 /* - SCIF Clock ------------------------------------------------------------- */ 3466 static const unsigned int scif_clk_a_pins[] = { 3467 /* SCIF_CLK */ 3468 RCAR_GP_PIN(6, 23), 3469 }; 3470 static const unsigned int scif_clk_a_mux[] = { 3471 SCIF_CLK_A_MARK, 3472 }; 3473 static const unsigned int scif_clk_b_pins[] = { 3474 /* SCIF_CLK */ 3475 RCAR_GP_PIN(5, 9), 3476 }; 3477 static const unsigned int scif_clk_b_mux[] = { 3478 SCIF_CLK_B_MARK, 3479 }; 3480 3481 /* - SDHI0 ------------------------------------------------------------------ */ 3482 static const unsigned int sdhi0_data1_pins[] = { 3483 /* D0 */ 3484 RCAR_GP_PIN(3, 2), 3485 }; 3486 static const unsigned int sdhi0_data1_mux[] = { 3487 SD0_DAT0_MARK, 3488 }; 3489 static const unsigned int sdhi0_data4_pins[] = { 3490 /* D[0:3] */ 3491 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), 3492 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), 3493 }; 3494 static const unsigned int sdhi0_data4_mux[] = { 3495 SD0_DAT0_MARK, SD0_DAT1_MARK, 3496 SD0_DAT2_MARK, SD0_DAT3_MARK, 3497 }; 3498 static const unsigned int sdhi0_ctrl_pins[] = { 3499 /* CLK, CMD */ 3500 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1), 3501 }; 3502 static const unsigned int sdhi0_ctrl_mux[] = { 3503 SD0_CLK_MARK, SD0_CMD_MARK, 3504 }; 3505 static const unsigned int sdhi0_cd_pins[] = { 3506 /* CD */ 3507 RCAR_GP_PIN(3, 12), 3508 }; 3509 static const unsigned int sdhi0_cd_mux[] = { 3510 SD0_CD_MARK, 3511 }; 3512 static const unsigned int sdhi0_wp_pins[] = { 3513 /* WP */ 3514 RCAR_GP_PIN(3, 13), 3515 }; 3516 static const unsigned int sdhi0_wp_mux[] = { 3517 SD0_WP_MARK, 3518 }; 3519 /* - SDHI1 ------------------------------------------------------------------ */ 3520 static const unsigned int sdhi1_data1_pins[] = { 3521 /* D0 */ 3522 RCAR_GP_PIN(3, 8), 3523 }; 3524 static const unsigned int sdhi1_data1_mux[] = { 3525 SD1_DAT0_MARK, 3526 }; 3527 static const unsigned int sdhi1_data4_pins[] = { 3528 /* D[0:3] */ 3529 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), 3530 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), 3531 }; 3532 static const unsigned int sdhi1_data4_mux[] = { 3533 SD1_DAT0_MARK, SD1_DAT1_MARK, 3534 SD1_DAT2_MARK, SD1_DAT3_MARK, 3535 }; 3536 static const unsigned int sdhi1_ctrl_pins[] = { 3537 /* CLK, CMD */ 3538 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), 3539 }; 3540 static const unsigned int sdhi1_ctrl_mux[] = { 3541 SD1_CLK_MARK, SD1_CMD_MARK, 3542 }; 3543 static const unsigned int sdhi1_cd_pins[] = { 3544 /* CD */ 3545 RCAR_GP_PIN(3, 14), 3546 }; 3547 static const unsigned int sdhi1_cd_mux[] = { 3548 SD1_CD_MARK, 3549 }; 3550 static const unsigned int sdhi1_wp_pins[] = { 3551 /* WP */ 3552 RCAR_GP_PIN(3, 15), 3553 }; 3554 static const unsigned int sdhi1_wp_mux[] = { 3555 SD1_WP_MARK, 3556 }; 3557 /* - SDHI2 ------------------------------------------------------------------ */ 3558 static const unsigned int sdhi2_data1_pins[] = { 3559 /* D0 */ 3560 RCAR_GP_PIN(4, 2), 3561 }; 3562 static const unsigned int sdhi2_data1_mux[] = { 3563 SD2_DAT0_MARK, 3564 }; 3565 static const unsigned int sdhi2_data4_pins[] = { 3566 /* D[0:3] */ 3567 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), 3568 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), 3569 }; 3570 static const unsigned int sdhi2_data4_mux[] = { 3571 SD2_DAT0_MARK, SD2_DAT1_MARK, 3572 SD2_DAT2_MARK, SD2_DAT3_MARK, 3573 }; 3574 static const unsigned int sdhi2_data8_pins[] = { 3575 /* D[0:7] */ 3576 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), 3577 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), 3578 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), 3579 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), 3580 }; 3581 static const unsigned int sdhi2_data8_mux[] = { 3582 SD2_DAT0_MARK, SD2_DAT1_MARK, 3583 SD2_DAT2_MARK, SD2_DAT3_MARK, 3584 SD2_DAT4_MARK, SD2_DAT5_MARK, 3585 SD2_DAT6_MARK, SD2_DAT7_MARK, 3586 }; 3587 static const unsigned int sdhi2_ctrl_pins[] = { 3588 /* CLK, CMD */ 3589 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1), 3590 }; 3591 static const unsigned int sdhi2_ctrl_mux[] = { 3592 SD2_CLK_MARK, SD2_CMD_MARK, 3593 }; 3594 static const unsigned int sdhi2_cd_a_pins[] = { 3595 /* CD */ 3596 RCAR_GP_PIN(4, 13), 3597 }; 3598 static const unsigned int sdhi2_cd_a_mux[] = { 3599 SD2_CD_A_MARK, 3600 }; 3601 static const unsigned int sdhi2_cd_b_pins[] = { 3602 /* CD */ 3603 RCAR_GP_PIN(5, 10), 3604 }; 3605 static const unsigned int sdhi2_cd_b_mux[] = { 3606 SD2_CD_B_MARK, 3607 }; 3608 static const unsigned int sdhi2_wp_a_pins[] = { 3609 /* WP */ 3610 RCAR_GP_PIN(4, 14), 3611 }; 3612 static const unsigned int sdhi2_wp_a_mux[] = { 3613 SD2_WP_A_MARK, 3614 }; 3615 static const unsigned int sdhi2_wp_b_pins[] = { 3616 /* WP */ 3617 RCAR_GP_PIN(5, 11), 3618 }; 3619 static const unsigned int sdhi2_wp_b_mux[] = { 3620 SD2_WP_B_MARK, 3621 }; 3622 static const unsigned int sdhi2_ds_pins[] = { 3623 /* DS */ 3624 RCAR_GP_PIN(4, 6), 3625 }; 3626 static const unsigned int sdhi2_ds_mux[] = { 3627 SD2_DS_MARK, 3628 }; 3629 /* - SDHI3 ------------------------------------------------------------------ */ 3630 static const unsigned int sdhi3_data1_pins[] = { 3631 /* D0 */ 3632 RCAR_GP_PIN(4, 9), 3633 }; 3634 static const unsigned int sdhi3_data1_mux[] = { 3635 SD3_DAT0_MARK, 3636 }; 3637 static const unsigned int sdhi3_data4_pins[] = { 3638 /* D[0:3] */ 3639 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10), 3640 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12), 3641 }; 3642 static const unsigned int sdhi3_data4_mux[] = { 3643 SD3_DAT0_MARK, SD3_DAT1_MARK, 3644 SD3_DAT2_MARK, SD3_DAT3_MARK, 3645 }; 3646 static const unsigned int sdhi3_data8_pins[] = { 3647 /* D[0:7] */ 3648 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10), 3649 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12), 3650 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14), 3651 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16), 3652 }; 3653 static const unsigned int sdhi3_data8_mux[] = { 3654 SD3_DAT0_MARK, SD3_DAT1_MARK, 3655 SD3_DAT2_MARK, SD3_DAT3_MARK, 3656 SD3_DAT4_MARK, SD3_DAT5_MARK, 3657 SD3_DAT6_MARK, SD3_DAT7_MARK, 3658 }; 3659 static const unsigned int sdhi3_ctrl_pins[] = { 3660 /* CLK, CMD */ 3661 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8), 3662 }; 3663 static const unsigned int sdhi3_ctrl_mux[] = { 3664 SD3_CLK_MARK, SD3_CMD_MARK, 3665 }; 3666 static const unsigned int sdhi3_cd_pins[] = { 3667 /* CD */ 3668 RCAR_GP_PIN(4, 15), 3669 }; 3670 static const unsigned int sdhi3_cd_mux[] = { 3671 SD3_CD_MARK, 3672 }; 3673 static const unsigned int sdhi3_wp_pins[] = { 3674 /* WP */ 3675 RCAR_GP_PIN(4, 16), 3676 }; 3677 static const unsigned int sdhi3_wp_mux[] = { 3678 SD3_WP_MARK, 3679 }; 3680 static const unsigned int sdhi3_ds_pins[] = { 3681 /* DS */ 3682 RCAR_GP_PIN(4, 17), 3683 }; 3684 static const unsigned int sdhi3_ds_mux[] = { 3685 SD3_DS_MARK, 3686 }; 3687 3688 /* - SSI -------------------------------------------------------------------- */ 3689 static const unsigned int ssi0_data_pins[] = { 3690 /* SDATA */ 3691 RCAR_GP_PIN(6, 2), 3692 }; 3693 static const unsigned int ssi0_data_mux[] = { 3694 SSI_SDATA0_MARK, 3695 }; 3696 static const unsigned int ssi01239_ctrl_pins[] = { 3697 /* SCK, WS */ 3698 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1), 3699 }; 3700 static const unsigned int ssi01239_ctrl_mux[] = { 3701 SSI_SCK01239_MARK, SSI_WS01239_MARK, 3702 }; 3703 static const unsigned int ssi1_data_a_pins[] = { 3704 /* SDATA */ 3705 RCAR_GP_PIN(6, 3), 3706 }; 3707 static const unsigned int ssi1_data_a_mux[] = { 3708 SSI_SDATA1_A_MARK, 3709 }; 3710 static const unsigned int ssi1_data_b_pins[] = { 3711 /* SDATA */ 3712 RCAR_GP_PIN(5, 12), 3713 }; 3714 static const unsigned int ssi1_data_b_mux[] = { 3715 SSI_SDATA1_B_MARK, 3716 }; 3717 static const unsigned int ssi1_ctrl_a_pins[] = { 3718 /* SCK, WS */ 3719 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27), 3720 }; 3721 static const unsigned int ssi1_ctrl_a_mux[] = { 3722 SSI_SCK1_A_MARK, SSI_WS1_A_MARK, 3723 }; 3724 static const unsigned int ssi1_ctrl_b_pins[] = { 3725 /* SCK, WS */ 3726 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21), 3727 }; 3728 static const unsigned int ssi1_ctrl_b_mux[] = { 3729 SSI_SCK1_B_MARK, SSI_WS1_B_MARK, 3730 }; 3731 static const unsigned int ssi2_data_a_pins[] = { 3732 /* SDATA */ 3733 RCAR_GP_PIN(6, 4), 3734 }; 3735 static const unsigned int ssi2_data_a_mux[] = { 3736 SSI_SDATA2_A_MARK, 3737 }; 3738 static const unsigned int ssi2_data_b_pins[] = { 3739 /* SDATA */ 3740 RCAR_GP_PIN(5, 13), 3741 }; 3742 static const unsigned int ssi2_data_b_mux[] = { 3743 SSI_SDATA2_B_MARK, 3744 }; 3745 static const unsigned int ssi2_ctrl_a_pins[] = { 3746 /* SCK, WS */ 3747 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21), 3748 }; 3749 static const unsigned int ssi2_ctrl_a_mux[] = { 3750 SSI_SCK2_A_MARK, SSI_WS2_A_MARK, 3751 }; 3752 static const unsigned int ssi2_ctrl_b_pins[] = { 3753 /* SCK, WS */ 3754 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29), 3755 }; 3756 static const unsigned int ssi2_ctrl_b_mux[] = { 3757 SSI_SCK2_B_MARK, SSI_WS2_B_MARK, 3758 }; 3759 static const unsigned int ssi3_data_pins[] = { 3760 /* SDATA */ 3761 RCAR_GP_PIN(6, 7), 3762 }; 3763 static const unsigned int ssi3_data_mux[] = { 3764 SSI_SDATA3_MARK, 3765 }; 3766 static const unsigned int ssi349_ctrl_pins[] = { 3767 /* SCK, WS */ 3768 RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6), 3769 }; 3770 static const unsigned int ssi349_ctrl_mux[] = { 3771 SSI_SCK349_MARK, SSI_WS349_MARK, 3772 }; 3773 static const unsigned int ssi4_data_pins[] = { 3774 /* SDATA */ 3775 RCAR_GP_PIN(6, 10), 3776 }; 3777 static const unsigned int ssi4_data_mux[] = { 3778 SSI_SDATA4_MARK, 3779 }; 3780 static const unsigned int ssi4_ctrl_pins[] = { 3781 /* SCK, WS */ 3782 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), 3783 }; 3784 static const unsigned int ssi4_ctrl_mux[] = { 3785 SSI_SCK4_MARK, SSI_WS4_MARK, 3786 }; 3787 static const unsigned int ssi5_data_pins[] = { 3788 /* SDATA */ 3789 RCAR_GP_PIN(6, 13), 3790 }; 3791 static const unsigned int ssi5_data_mux[] = { 3792 SSI_SDATA5_MARK, 3793 }; 3794 static const unsigned int ssi5_ctrl_pins[] = { 3795 /* SCK, WS */ 3796 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12), 3797 }; 3798 static const unsigned int ssi5_ctrl_mux[] = { 3799 SSI_SCK5_MARK, SSI_WS5_MARK, 3800 }; 3801 static const unsigned int ssi6_data_pins[] = { 3802 /* SDATA */ 3803 RCAR_GP_PIN(6, 16), 3804 }; 3805 static const unsigned int ssi6_data_mux[] = { 3806 SSI_SDATA6_MARK, 3807 }; 3808 static const unsigned int ssi6_ctrl_pins[] = { 3809 /* SCK, WS */ 3810 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15), 3811 }; 3812 static const unsigned int ssi6_ctrl_mux[] = { 3813 SSI_SCK6_MARK, SSI_WS6_MARK, 3814 }; 3815 static const unsigned int ssi7_data_pins[] = { 3816 /* SDATA */ 3817 RCAR_GP_PIN(6, 19), 3818 }; 3819 static const unsigned int ssi7_data_mux[] = { 3820 SSI_SDATA7_MARK, 3821 }; 3822 static const unsigned int ssi78_ctrl_pins[] = { 3823 /* SCK, WS */ 3824 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18), 3825 }; 3826 static const unsigned int ssi78_ctrl_mux[] = { 3827 SSI_SCK78_MARK, SSI_WS78_MARK, 3828 }; 3829 static const unsigned int ssi8_data_pins[] = { 3830 /* SDATA */ 3831 RCAR_GP_PIN(6, 20), 3832 }; 3833 static const unsigned int ssi8_data_mux[] = { 3834 SSI_SDATA8_MARK, 3835 }; 3836 static const unsigned int ssi9_data_a_pins[] = { 3837 /* SDATA */ 3838 RCAR_GP_PIN(6, 21), 3839 }; 3840 static const unsigned int ssi9_data_a_mux[] = { 3841 SSI_SDATA9_A_MARK, 3842 }; 3843 static const unsigned int ssi9_data_b_pins[] = { 3844 /* SDATA */ 3845 RCAR_GP_PIN(5, 14), 3846 }; 3847 static const unsigned int ssi9_data_b_mux[] = { 3848 SSI_SDATA9_B_MARK, 3849 }; 3850 static const unsigned int ssi9_ctrl_a_pins[] = { 3851 /* SCK, WS */ 3852 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16), 3853 }; 3854 static const unsigned int ssi9_ctrl_a_mux[] = { 3855 SSI_SCK9_A_MARK, SSI_WS9_A_MARK, 3856 }; 3857 static const unsigned int ssi9_ctrl_b_pins[] = { 3858 /* SCK, WS */ 3859 RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31), 3860 }; 3861 static const unsigned int ssi9_ctrl_b_mux[] = { 3862 SSI_SCK9_B_MARK, SSI_WS9_B_MARK, 3863 }; 3864 3865 /* - TMU -------------------------------------------------------------------- */ 3866 static const unsigned int tmu_tclk1_a_pins[] = { 3867 /* TCLK */ 3868 RCAR_GP_PIN(6, 23), 3869 }; 3870 static const unsigned int tmu_tclk1_a_mux[] = { 3871 TCLK1_A_MARK, 3872 }; 3873 static const unsigned int tmu_tclk1_b_pins[] = { 3874 /* TCLK */ 3875 RCAR_GP_PIN(5, 19), 3876 }; 3877 static const unsigned int tmu_tclk1_b_mux[] = { 3878 TCLK1_B_MARK, 3879 }; 3880 static const unsigned int tmu_tclk2_a_pins[] = { 3881 /* TCLK */ 3882 RCAR_GP_PIN(6, 19), 3883 }; 3884 static const unsigned int tmu_tclk2_a_mux[] = { 3885 TCLK2_A_MARK, 3886 }; 3887 static const unsigned int tmu_tclk2_b_pins[] = { 3888 /* TCLK */ 3889 RCAR_GP_PIN(6, 28), 3890 }; 3891 static const unsigned int tmu_tclk2_b_mux[] = { 3892 TCLK2_B_MARK, 3893 }; 3894 3895 /* - TPU ------------------------------------------------------------------- */ 3896 static const unsigned int tpu_to0_pins[] = { 3897 /* TPU0TO0 */ 3898 RCAR_GP_PIN(6, 28), 3899 }; 3900 static const unsigned int tpu_to0_mux[] = { 3901 TPU0TO0_MARK, 3902 }; 3903 static const unsigned int tpu_to1_pins[] = { 3904 /* TPU0TO1 */ 3905 RCAR_GP_PIN(6, 29), 3906 }; 3907 static const unsigned int tpu_to1_mux[] = { 3908 TPU0TO1_MARK, 3909 }; 3910 static const unsigned int tpu_to2_pins[] = { 3911 /* TPU0TO2 */ 3912 RCAR_GP_PIN(6, 30), 3913 }; 3914 static const unsigned int tpu_to2_mux[] = { 3915 TPU0TO2_MARK, 3916 }; 3917 static const unsigned int tpu_to3_pins[] = { 3918 /* TPU0TO3 */ 3919 RCAR_GP_PIN(6, 31), 3920 }; 3921 static const unsigned int tpu_to3_mux[] = { 3922 TPU0TO3_MARK, 3923 }; 3924 3925 /* - USB0 ------------------------------------------------------------------- */ 3926 static const unsigned int usb0_pins[] = { 3927 /* PWEN, OVC */ 3928 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25), 3929 }; 3930 static const unsigned int usb0_mux[] = { 3931 USB0_PWEN_MARK, USB0_OVC_MARK, 3932 }; 3933 /* - USB1 ------------------------------------------------------------------- */ 3934 static const unsigned int usb1_pins[] = { 3935 /* PWEN, OVC */ 3936 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27), 3937 }; 3938 static const unsigned int usb1_mux[] = { 3939 USB1_PWEN_MARK, USB1_OVC_MARK, 3940 }; 3941 /* - USB2 ------------------------------------------------------------------- */ 3942 static const unsigned int usb2_pins[] = { 3943 /* PWEN, OVC */ 3944 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15), 3945 }; 3946 static const unsigned int usb2_mux[] = { 3947 USB2_PWEN_MARK, USB2_OVC_MARK, 3948 }; 3949 /* - USB2_CH3 --------------------------------------------------------------- */ 3950 static const unsigned int usb2_ch3_pins[] = { 3951 /* PWEN, OVC */ 3952 RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31), 3953 }; 3954 static const unsigned int usb2_ch3_mux[] = { 3955 USB2_CH3_PWEN_MARK, USB2_CH3_OVC_MARK, 3956 }; 3957 3958 /* - USB30 ------------------------------------------------------------------ */ 3959 static const unsigned int usb30_pins[] = { 3960 /* PWEN, OVC */ 3961 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29), 3962 }; 3963 static const unsigned int usb30_mux[] = { 3964 USB30_PWEN_MARK, USB30_OVC_MARK, 3965 }; 3966 3967 /* - VIN4 ------------------------------------------------------------------- */ 3968 static const unsigned int vin4_data18_a_pins[] = { 3969 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), 3970 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), 3971 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), 3972 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), 3973 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), 3974 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 3975 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), 3976 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), 3977 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), 3978 }; 3979 static const unsigned int vin4_data18_a_mux[] = { 3980 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK, 3981 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK, 3982 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK, 3983 VI4_DATA10_MARK, VI4_DATA11_MARK, 3984 VI4_DATA12_MARK, VI4_DATA13_MARK, 3985 VI4_DATA14_MARK, VI4_DATA15_MARK, 3986 VI4_DATA18_MARK, VI4_DATA19_MARK, 3987 VI4_DATA20_MARK, VI4_DATA21_MARK, 3988 VI4_DATA22_MARK, VI4_DATA23_MARK, 3989 }; 3990 static const unsigned int vin4_data18_b_pins[] = { 3991 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), 3992 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), 3993 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), 3994 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), 3995 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), 3996 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 3997 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), 3998 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), 3999 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), 4000 }; 4001 static const unsigned int vin4_data18_b_mux[] = { 4002 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK, 4003 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK, 4004 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK, 4005 VI4_DATA10_MARK, VI4_DATA11_MARK, 4006 VI4_DATA12_MARK, VI4_DATA13_MARK, 4007 VI4_DATA14_MARK, VI4_DATA15_MARK, 4008 VI4_DATA18_MARK, VI4_DATA19_MARK, 4009 VI4_DATA20_MARK, VI4_DATA21_MARK, 4010 VI4_DATA22_MARK, VI4_DATA23_MARK, 4011 }; 4012 static const union vin_data vin4_data_a_pins = { 4013 .data24 = { 4014 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), 4015 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), 4016 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), 4017 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), 4018 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), 4019 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), 4020 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), 4021 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 4022 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), 4023 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), 4024 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), 4025 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), 4026 }, 4027 }; 4028 static const union vin_data vin4_data_a_mux = { 4029 .data24 = { 4030 VI4_DATA0_A_MARK, VI4_DATA1_A_MARK, 4031 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK, 4032 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK, 4033 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK, 4034 VI4_DATA8_MARK, VI4_DATA9_MARK, 4035 VI4_DATA10_MARK, VI4_DATA11_MARK, 4036 VI4_DATA12_MARK, VI4_DATA13_MARK, 4037 VI4_DATA14_MARK, VI4_DATA15_MARK, 4038 VI4_DATA16_MARK, VI4_DATA17_MARK, 4039 VI4_DATA18_MARK, VI4_DATA19_MARK, 4040 VI4_DATA20_MARK, VI4_DATA21_MARK, 4041 VI4_DATA22_MARK, VI4_DATA23_MARK, 4042 }, 4043 }; 4044 static const union vin_data vin4_data_b_pins = { 4045 .data24 = { 4046 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), 4047 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), 4048 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), 4049 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), 4050 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), 4051 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), 4052 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), 4053 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 4054 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), 4055 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), 4056 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), 4057 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), 4058 }, 4059 }; 4060 static const union vin_data vin4_data_b_mux = { 4061 .data24 = { 4062 VI4_DATA0_B_MARK, VI4_DATA1_B_MARK, 4063 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK, 4064 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK, 4065 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK, 4066 VI4_DATA8_MARK, VI4_DATA9_MARK, 4067 VI4_DATA10_MARK, VI4_DATA11_MARK, 4068 VI4_DATA12_MARK, VI4_DATA13_MARK, 4069 VI4_DATA14_MARK, VI4_DATA15_MARK, 4070 VI4_DATA16_MARK, VI4_DATA17_MARK, 4071 VI4_DATA18_MARK, VI4_DATA19_MARK, 4072 VI4_DATA20_MARK, VI4_DATA21_MARK, 4073 VI4_DATA22_MARK, VI4_DATA23_MARK, 4074 }, 4075 }; 4076 static const unsigned int vin4_sync_pins[] = { 4077 /* HSYNC#, VSYNC# */ 4078 RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 17), 4079 }; 4080 static const unsigned int vin4_sync_mux[] = { 4081 VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK, 4082 }; 4083 static const unsigned int vin4_field_pins[] = { 4084 /* FIELD */ 4085 RCAR_GP_PIN(1, 16), 4086 }; 4087 static const unsigned int vin4_field_mux[] = { 4088 VI4_FIELD_MARK, 4089 }; 4090 static const unsigned int vin4_clkenb_pins[] = { 4091 /* CLKENB */ 4092 RCAR_GP_PIN(1, 19), 4093 }; 4094 static const unsigned int vin4_clkenb_mux[] = { 4095 VI4_CLKENB_MARK, 4096 }; 4097 static const unsigned int vin4_clk_pins[] = { 4098 /* CLK */ 4099 RCAR_GP_PIN(1, 27), 4100 }; 4101 static const unsigned int vin4_clk_mux[] = { 4102 VI4_CLK_MARK, 4103 }; 4104 4105 /* - VIN5 ------------------------------------------------------------------- */ 4106 static const union vin_data16 vin5_data_pins = { 4107 .data16 = { 4108 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), 4109 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), 4110 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), 4111 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), 4112 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), 4113 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), 4114 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), 4115 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 4116 }, 4117 }; 4118 static const union vin_data16 vin5_data_mux = { 4119 .data16 = { 4120 VI5_DATA0_MARK, VI5_DATA1_MARK, 4121 VI5_DATA2_MARK, VI5_DATA3_MARK, 4122 VI5_DATA4_MARK, VI5_DATA5_MARK, 4123 VI5_DATA6_MARK, VI5_DATA7_MARK, 4124 VI5_DATA8_MARK, VI5_DATA9_MARK, 4125 VI5_DATA10_MARK, VI5_DATA11_MARK, 4126 VI5_DATA12_MARK, VI5_DATA13_MARK, 4127 VI5_DATA14_MARK, VI5_DATA15_MARK, 4128 }, 4129 }; 4130 static const unsigned int vin5_sync_pins[] = { 4131 /* HSYNC#, VSYNC# */ 4132 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9), 4133 }; 4134 static const unsigned int vin5_sync_mux[] = { 4135 VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK, 4136 }; 4137 static const unsigned int vin5_field_pins[] = { 4138 RCAR_GP_PIN(1, 11), 4139 }; 4140 static const unsigned int vin5_field_mux[] = { 4141 /* FIELD */ 4142 VI5_FIELD_MARK, 4143 }; 4144 static const unsigned int vin5_clkenb_pins[] = { 4145 RCAR_GP_PIN(1, 20), 4146 }; 4147 static const unsigned int vin5_clkenb_mux[] = { 4148 /* CLKENB */ 4149 VI5_CLKENB_MARK, 4150 }; 4151 static const unsigned int vin5_clk_pins[] = { 4152 RCAR_GP_PIN(1, 21), 4153 }; 4154 static const unsigned int vin5_clk_mux[] = { 4155 /* CLK */ 4156 VI5_CLK_MARK, 4157 }; 4158 4159 static const struct { 4160 struct sh_pfc_pin_group common[320]; 4161 struct sh_pfc_pin_group automotive[30]; 4162 } pinmux_groups = { 4163 .common = { 4164 SH_PFC_PIN_GROUP(audio_clk_a_a), 4165 SH_PFC_PIN_GROUP(audio_clk_a_b), 4166 SH_PFC_PIN_GROUP(audio_clk_a_c), 4167 SH_PFC_PIN_GROUP(audio_clk_b_a), 4168 SH_PFC_PIN_GROUP(audio_clk_b_b), 4169 SH_PFC_PIN_GROUP(audio_clk_c_a), 4170 SH_PFC_PIN_GROUP(audio_clk_c_b), 4171 SH_PFC_PIN_GROUP(audio_clkout_a), 4172 SH_PFC_PIN_GROUP(audio_clkout_b), 4173 SH_PFC_PIN_GROUP(audio_clkout_c), 4174 SH_PFC_PIN_GROUP(audio_clkout_d), 4175 SH_PFC_PIN_GROUP(audio_clkout1_a), 4176 SH_PFC_PIN_GROUP(audio_clkout1_b), 4177 SH_PFC_PIN_GROUP(audio_clkout2_a), 4178 SH_PFC_PIN_GROUP(audio_clkout2_b), 4179 SH_PFC_PIN_GROUP(audio_clkout3_a), 4180 SH_PFC_PIN_GROUP(audio_clkout3_b), 4181 SH_PFC_PIN_GROUP(avb_link), 4182 SH_PFC_PIN_GROUP(avb_magic), 4183 SH_PFC_PIN_GROUP(avb_phy_int), 4184 SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio), /* Deprecated */ 4185 SH_PFC_PIN_GROUP(avb_mdio), 4186 SH_PFC_PIN_GROUP(avb_mii), 4187 SH_PFC_PIN_GROUP(avb_avtp_pps), 4188 SH_PFC_PIN_GROUP(avb_avtp_match_a), 4189 SH_PFC_PIN_GROUP(avb_avtp_capture_a), 4190 SH_PFC_PIN_GROUP(avb_avtp_match_b), 4191 SH_PFC_PIN_GROUP(avb_avtp_capture_b), 4192 SH_PFC_PIN_GROUP(can0_data_a), 4193 SH_PFC_PIN_GROUP(can0_data_b), 4194 SH_PFC_PIN_GROUP(can1_data), 4195 SH_PFC_PIN_GROUP(can_clk), 4196 SH_PFC_PIN_GROUP(canfd0_data_a), 4197 SH_PFC_PIN_GROUP(canfd0_data_b), 4198 SH_PFC_PIN_GROUP(canfd1_data), 4199 SH_PFC_PIN_GROUP(du_rgb666), 4200 SH_PFC_PIN_GROUP(du_rgb888), 4201 SH_PFC_PIN_GROUP(du_clk_out_0), 4202 SH_PFC_PIN_GROUP(du_clk_out_1), 4203 SH_PFC_PIN_GROUP(du_sync), 4204 SH_PFC_PIN_GROUP(du_oddf), 4205 SH_PFC_PIN_GROUP(du_cde), 4206 SH_PFC_PIN_GROUP(du_disp), 4207 SH_PFC_PIN_GROUP(hscif0_data), 4208 SH_PFC_PIN_GROUP(hscif0_clk), 4209 SH_PFC_PIN_GROUP(hscif0_ctrl), 4210 SH_PFC_PIN_GROUP(hscif1_data_a), 4211 SH_PFC_PIN_GROUP(hscif1_clk_a), 4212 SH_PFC_PIN_GROUP(hscif1_ctrl_a), 4213 SH_PFC_PIN_GROUP(hscif1_data_b), 4214 SH_PFC_PIN_GROUP(hscif1_clk_b), 4215 SH_PFC_PIN_GROUP(hscif1_ctrl_b), 4216 SH_PFC_PIN_GROUP(hscif2_data_a), 4217 SH_PFC_PIN_GROUP(hscif2_clk_a), 4218 SH_PFC_PIN_GROUP(hscif2_ctrl_a), 4219 SH_PFC_PIN_GROUP(hscif2_data_b), 4220 SH_PFC_PIN_GROUP(hscif2_clk_b), 4221 SH_PFC_PIN_GROUP(hscif2_ctrl_b), 4222 SH_PFC_PIN_GROUP(hscif2_data_c), 4223 SH_PFC_PIN_GROUP(hscif2_clk_c), 4224 SH_PFC_PIN_GROUP(hscif2_ctrl_c), 4225 SH_PFC_PIN_GROUP(hscif3_data_a), 4226 SH_PFC_PIN_GROUP(hscif3_clk), 4227 SH_PFC_PIN_GROUP(hscif3_ctrl), 4228 SH_PFC_PIN_GROUP(hscif3_data_b), 4229 SH_PFC_PIN_GROUP(hscif3_data_c), 4230 SH_PFC_PIN_GROUP(hscif3_data_d), 4231 SH_PFC_PIN_GROUP(hscif4_data_a), 4232 SH_PFC_PIN_GROUP(hscif4_clk), 4233 SH_PFC_PIN_GROUP(hscif4_ctrl), 4234 SH_PFC_PIN_GROUP(hscif4_data_b), 4235 SH_PFC_PIN_GROUP(i2c0), 4236 SH_PFC_PIN_GROUP(i2c1_a), 4237 SH_PFC_PIN_GROUP(i2c1_b), 4238 SH_PFC_PIN_GROUP(i2c2_a), 4239 SH_PFC_PIN_GROUP(i2c2_b), 4240 SH_PFC_PIN_GROUP(i2c3), 4241 SH_PFC_PIN_GROUP(i2c5), 4242 SH_PFC_PIN_GROUP(i2c6_a), 4243 SH_PFC_PIN_GROUP(i2c6_b), 4244 SH_PFC_PIN_GROUP(i2c6_c), 4245 SH_PFC_PIN_GROUP(intc_ex_irq0), 4246 SH_PFC_PIN_GROUP(intc_ex_irq1), 4247 SH_PFC_PIN_GROUP(intc_ex_irq2), 4248 SH_PFC_PIN_GROUP(intc_ex_irq3), 4249 SH_PFC_PIN_GROUP(intc_ex_irq4), 4250 SH_PFC_PIN_GROUP(intc_ex_irq5), 4251 SH_PFC_PIN_GROUP(msiof0_clk), 4252 SH_PFC_PIN_GROUP(msiof0_sync), 4253 SH_PFC_PIN_GROUP(msiof0_ss1), 4254 SH_PFC_PIN_GROUP(msiof0_ss2), 4255 SH_PFC_PIN_GROUP(msiof0_txd), 4256 SH_PFC_PIN_GROUP(msiof0_rxd), 4257 SH_PFC_PIN_GROUP(msiof1_clk_a), 4258 SH_PFC_PIN_GROUP(msiof1_sync_a), 4259 SH_PFC_PIN_GROUP(msiof1_ss1_a), 4260 SH_PFC_PIN_GROUP(msiof1_ss2_a), 4261 SH_PFC_PIN_GROUP(msiof1_txd_a), 4262 SH_PFC_PIN_GROUP(msiof1_rxd_a), 4263 SH_PFC_PIN_GROUP(msiof1_clk_b), 4264 SH_PFC_PIN_GROUP(msiof1_sync_b), 4265 SH_PFC_PIN_GROUP(msiof1_ss1_b), 4266 SH_PFC_PIN_GROUP(msiof1_ss2_b), 4267 SH_PFC_PIN_GROUP(msiof1_txd_b), 4268 SH_PFC_PIN_GROUP(msiof1_rxd_b), 4269 SH_PFC_PIN_GROUP(msiof1_clk_c), 4270 SH_PFC_PIN_GROUP(msiof1_sync_c), 4271 SH_PFC_PIN_GROUP(msiof1_ss1_c), 4272 SH_PFC_PIN_GROUP(msiof1_ss2_c), 4273 SH_PFC_PIN_GROUP(msiof1_txd_c), 4274 SH_PFC_PIN_GROUP(msiof1_rxd_c), 4275 SH_PFC_PIN_GROUP(msiof1_clk_d), 4276 SH_PFC_PIN_GROUP(msiof1_sync_d), 4277 SH_PFC_PIN_GROUP(msiof1_ss1_d), 4278 SH_PFC_PIN_GROUP(msiof1_ss2_d), 4279 SH_PFC_PIN_GROUP(msiof1_txd_d), 4280 SH_PFC_PIN_GROUP(msiof1_rxd_d), 4281 SH_PFC_PIN_GROUP(msiof1_clk_e), 4282 SH_PFC_PIN_GROUP(msiof1_sync_e), 4283 SH_PFC_PIN_GROUP(msiof1_ss1_e), 4284 SH_PFC_PIN_GROUP(msiof1_ss2_e), 4285 SH_PFC_PIN_GROUP(msiof1_txd_e), 4286 SH_PFC_PIN_GROUP(msiof1_rxd_e), 4287 SH_PFC_PIN_GROUP(msiof1_clk_f), 4288 SH_PFC_PIN_GROUP(msiof1_sync_f), 4289 SH_PFC_PIN_GROUP(msiof1_ss1_f), 4290 SH_PFC_PIN_GROUP(msiof1_ss2_f), 4291 SH_PFC_PIN_GROUP(msiof1_txd_f), 4292 SH_PFC_PIN_GROUP(msiof1_rxd_f), 4293 SH_PFC_PIN_GROUP(msiof1_clk_g), 4294 SH_PFC_PIN_GROUP(msiof1_sync_g), 4295 SH_PFC_PIN_GROUP(msiof1_ss1_g), 4296 SH_PFC_PIN_GROUP(msiof1_ss2_g), 4297 SH_PFC_PIN_GROUP(msiof1_txd_g), 4298 SH_PFC_PIN_GROUP(msiof1_rxd_g), 4299 SH_PFC_PIN_GROUP(msiof2_clk_a), 4300 SH_PFC_PIN_GROUP(msiof2_sync_a), 4301 SH_PFC_PIN_GROUP(msiof2_ss1_a), 4302 SH_PFC_PIN_GROUP(msiof2_ss2_a), 4303 SH_PFC_PIN_GROUP(msiof2_txd_a), 4304 SH_PFC_PIN_GROUP(msiof2_rxd_a), 4305 SH_PFC_PIN_GROUP(msiof2_clk_b), 4306 SH_PFC_PIN_GROUP(msiof2_sync_b), 4307 SH_PFC_PIN_GROUP(msiof2_ss1_b), 4308 SH_PFC_PIN_GROUP(msiof2_ss2_b), 4309 SH_PFC_PIN_GROUP(msiof2_txd_b), 4310 SH_PFC_PIN_GROUP(msiof2_rxd_b), 4311 SH_PFC_PIN_GROUP(msiof2_clk_c), 4312 SH_PFC_PIN_GROUP(msiof2_sync_c), 4313 SH_PFC_PIN_GROUP(msiof2_ss1_c), 4314 SH_PFC_PIN_GROUP(msiof2_ss2_c), 4315 SH_PFC_PIN_GROUP(msiof2_txd_c), 4316 SH_PFC_PIN_GROUP(msiof2_rxd_c), 4317 SH_PFC_PIN_GROUP(msiof2_clk_d), 4318 SH_PFC_PIN_GROUP(msiof2_sync_d), 4319 SH_PFC_PIN_GROUP(msiof2_ss1_d), 4320 SH_PFC_PIN_GROUP(msiof2_ss2_d), 4321 SH_PFC_PIN_GROUP(msiof2_txd_d), 4322 SH_PFC_PIN_GROUP(msiof2_rxd_d), 4323 SH_PFC_PIN_GROUP(msiof3_clk_a), 4324 SH_PFC_PIN_GROUP(msiof3_sync_a), 4325 SH_PFC_PIN_GROUP(msiof3_ss1_a), 4326 SH_PFC_PIN_GROUP(msiof3_ss2_a), 4327 SH_PFC_PIN_GROUP(msiof3_txd_a), 4328 SH_PFC_PIN_GROUP(msiof3_rxd_a), 4329 SH_PFC_PIN_GROUP(msiof3_clk_b), 4330 SH_PFC_PIN_GROUP(msiof3_sync_b), 4331 SH_PFC_PIN_GROUP(msiof3_ss1_b), 4332 SH_PFC_PIN_GROUP(msiof3_ss2_b), 4333 SH_PFC_PIN_GROUP(msiof3_txd_b), 4334 SH_PFC_PIN_GROUP(msiof3_rxd_b), 4335 SH_PFC_PIN_GROUP(msiof3_clk_c), 4336 SH_PFC_PIN_GROUP(msiof3_sync_c), 4337 SH_PFC_PIN_GROUP(msiof3_txd_c), 4338 SH_PFC_PIN_GROUP(msiof3_rxd_c), 4339 SH_PFC_PIN_GROUP(msiof3_clk_d), 4340 SH_PFC_PIN_GROUP(msiof3_sync_d), 4341 SH_PFC_PIN_GROUP(msiof3_ss1_d), 4342 SH_PFC_PIN_GROUP(msiof3_txd_d), 4343 SH_PFC_PIN_GROUP(msiof3_rxd_d), 4344 SH_PFC_PIN_GROUP(msiof3_clk_e), 4345 SH_PFC_PIN_GROUP(msiof3_sync_e), 4346 SH_PFC_PIN_GROUP(msiof3_ss1_e), 4347 SH_PFC_PIN_GROUP(msiof3_ss2_e), 4348 SH_PFC_PIN_GROUP(msiof3_txd_e), 4349 SH_PFC_PIN_GROUP(msiof3_rxd_e), 4350 SH_PFC_PIN_GROUP(pwm0), 4351 SH_PFC_PIN_GROUP(pwm1_a), 4352 SH_PFC_PIN_GROUP(pwm1_b), 4353 SH_PFC_PIN_GROUP(pwm2_a), 4354 SH_PFC_PIN_GROUP(pwm2_b), 4355 SH_PFC_PIN_GROUP(pwm3_a), 4356 SH_PFC_PIN_GROUP(pwm3_b), 4357 SH_PFC_PIN_GROUP(pwm4_a), 4358 SH_PFC_PIN_GROUP(pwm4_b), 4359 SH_PFC_PIN_GROUP(pwm5_a), 4360 SH_PFC_PIN_GROUP(pwm5_b), 4361 SH_PFC_PIN_GROUP(pwm6_a), 4362 SH_PFC_PIN_GROUP(pwm6_b), 4363 SH_PFC_PIN_GROUP(sata0_devslp_a), 4364 SH_PFC_PIN_GROUP(sata0_devslp_b), 4365 SH_PFC_PIN_GROUP(scif0_data), 4366 SH_PFC_PIN_GROUP(scif0_clk), 4367 SH_PFC_PIN_GROUP(scif0_ctrl), 4368 SH_PFC_PIN_GROUP(scif1_data_a), 4369 SH_PFC_PIN_GROUP(scif1_clk), 4370 SH_PFC_PIN_GROUP(scif1_ctrl), 4371 SH_PFC_PIN_GROUP(scif1_data_b), 4372 SH_PFC_PIN_GROUP(scif2_data_a), 4373 SH_PFC_PIN_GROUP(scif2_clk), 4374 SH_PFC_PIN_GROUP(scif2_data_b), 4375 SH_PFC_PIN_GROUP(scif3_data_a), 4376 SH_PFC_PIN_GROUP(scif3_clk), 4377 SH_PFC_PIN_GROUP(scif3_ctrl), 4378 SH_PFC_PIN_GROUP(scif3_data_b), 4379 SH_PFC_PIN_GROUP(scif4_data_a), 4380 SH_PFC_PIN_GROUP(scif4_clk_a), 4381 SH_PFC_PIN_GROUP(scif4_ctrl_a), 4382 SH_PFC_PIN_GROUP(scif4_data_b), 4383 SH_PFC_PIN_GROUP(scif4_clk_b), 4384 SH_PFC_PIN_GROUP(scif4_ctrl_b), 4385 SH_PFC_PIN_GROUP(scif4_data_c), 4386 SH_PFC_PIN_GROUP(scif4_clk_c), 4387 SH_PFC_PIN_GROUP(scif4_ctrl_c), 4388 SH_PFC_PIN_GROUP(scif5_data_a), 4389 SH_PFC_PIN_GROUP(scif5_clk_a), 4390 SH_PFC_PIN_GROUP(scif5_data_b), 4391 SH_PFC_PIN_GROUP(scif5_clk_b), 4392 SH_PFC_PIN_GROUP(scif_clk_a), 4393 SH_PFC_PIN_GROUP(scif_clk_b), 4394 SH_PFC_PIN_GROUP(sdhi0_data1), 4395 SH_PFC_PIN_GROUP(sdhi0_data4), 4396 SH_PFC_PIN_GROUP(sdhi0_ctrl), 4397 SH_PFC_PIN_GROUP(sdhi0_cd), 4398 SH_PFC_PIN_GROUP(sdhi0_wp), 4399 SH_PFC_PIN_GROUP(sdhi1_data1), 4400 SH_PFC_PIN_GROUP(sdhi1_data4), 4401 SH_PFC_PIN_GROUP(sdhi1_ctrl), 4402 SH_PFC_PIN_GROUP(sdhi1_cd), 4403 SH_PFC_PIN_GROUP(sdhi1_wp), 4404 SH_PFC_PIN_GROUP(sdhi2_data1), 4405 SH_PFC_PIN_GROUP(sdhi2_data4), 4406 SH_PFC_PIN_GROUP(sdhi2_data8), 4407 SH_PFC_PIN_GROUP(sdhi2_ctrl), 4408 SH_PFC_PIN_GROUP(sdhi2_cd_a), 4409 SH_PFC_PIN_GROUP(sdhi2_wp_a), 4410 SH_PFC_PIN_GROUP(sdhi2_cd_b), 4411 SH_PFC_PIN_GROUP(sdhi2_wp_b), 4412 SH_PFC_PIN_GROUP(sdhi2_ds), 4413 SH_PFC_PIN_GROUP(sdhi3_data1), 4414 SH_PFC_PIN_GROUP(sdhi3_data4), 4415 SH_PFC_PIN_GROUP(sdhi3_data8), 4416 SH_PFC_PIN_GROUP(sdhi3_ctrl), 4417 SH_PFC_PIN_GROUP(sdhi3_cd), 4418 SH_PFC_PIN_GROUP(sdhi3_wp), 4419 SH_PFC_PIN_GROUP(sdhi3_ds), 4420 SH_PFC_PIN_GROUP(ssi0_data), 4421 SH_PFC_PIN_GROUP(ssi01239_ctrl), 4422 SH_PFC_PIN_GROUP(ssi1_data_a), 4423 SH_PFC_PIN_GROUP(ssi1_data_b), 4424 SH_PFC_PIN_GROUP(ssi1_ctrl_a), 4425 SH_PFC_PIN_GROUP(ssi1_ctrl_b), 4426 SH_PFC_PIN_GROUP(ssi2_data_a), 4427 SH_PFC_PIN_GROUP(ssi2_data_b), 4428 SH_PFC_PIN_GROUP(ssi2_ctrl_a), 4429 SH_PFC_PIN_GROUP(ssi2_ctrl_b), 4430 SH_PFC_PIN_GROUP(ssi3_data), 4431 SH_PFC_PIN_GROUP(ssi349_ctrl), 4432 SH_PFC_PIN_GROUP(ssi4_data), 4433 SH_PFC_PIN_GROUP(ssi4_ctrl), 4434 SH_PFC_PIN_GROUP(ssi5_data), 4435 SH_PFC_PIN_GROUP(ssi5_ctrl), 4436 SH_PFC_PIN_GROUP(ssi6_data), 4437 SH_PFC_PIN_GROUP(ssi6_ctrl), 4438 SH_PFC_PIN_GROUP(ssi7_data), 4439 SH_PFC_PIN_GROUP(ssi78_ctrl), 4440 SH_PFC_PIN_GROUP(ssi8_data), 4441 SH_PFC_PIN_GROUP(ssi9_data_a), 4442 SH_PFC_PIN_GROUP(ssi9_data_b), 4443 SH_PFC_PIN_GROUP(ssi9_ctrl_a), 4444 SH_PFC_PIN_GROUP(ssi9_ctrl_b), 4445 SH_PFC_PIN_GROUP(tmu_tclk1_a), 4446 SH_PFC_PIN_GROUP(tmu_tclk1_b), 4447 SH_PFC_PIN_GROUP(tmu_tclk2_a), 4448 SH_PFC_PIN_GROUP(tmu_tclk2_b), 4449 SH_PFC_PIN_GROUP(tpu_to0), 4450 SH_PFC_PIN_GROUP(tpu_to1), 4451 SH_PFC_PIN_GROUP(tpu_to2), 4452 SH_PFC_PIN_GROUP(tpu_to3), 4453 SH_PFC_PIN_GROUP(usb0), 4454 SH_PFC_PIN_GROUP(usb1), 4455 SH_PFC_PIN_GROUP(usb2), 4456 SH_PFC_PIN_GROUP(usb2_ch3), 4457 SH_PFC_PIN_GROUP(usb30), 4458 VIN_DATA_PIN_GROUP(vin4_data, 8, _a), 4459 VIN_DATA_PIN_GROUP(vin4_data, 10, _a), 4460 VIN_DATA_PIN_GROUP(vin4_data, 12, _a), 4461 VIN_DATA_PIN_GROUP(vin4_data, 16, _a), 4462 SH_PFC_PIN_GROUP(vin4_data18_a), 4463 VIN_DATA_PIN_GROUP(vin4_data, 20, _a), 4464 VIN_DATA_PIN_GROUP(vin4_data, 24, _a), 4465 VIN_DATA_PIN_GROUP(vin4_data, 8, _b), 4466 VIN_DATA_PIN_GROUP(vin4_data, 10, _b), 4467 VIN_DATA_PIN_GROUP(vin4_data, 12, _b), 4468 VIN_DATA_PIN_GROUP(vin4_data, 16, _b), 4469 SH_PFC_PIN_GROUP(vin4_data18_b), 4470 VIN_DATA_PIN_GROUP(vin4_data, 20, _b), 4471 VIN_DATA_PIN_GROUP(vin4_data, 24, _b), 4472 SH_PFC_PIN_GROUP(vin4_sync), 4473 SH_PFC_PIN_GROUP(vin4_field), 4474 SH_PFC_PIN_GROUP(vin4_clkenb), 4475 SH_PFC_PIN_GROUP(vin4_clk), 4476 VIN_DATA_PIN_GROUP(vin5_data, 8), 4477 VIN_DATA_PIN_GROUP(vin5_data, 10), 4478 VIN_DATA_PIN_GROUP(vin5_data, 12), 4479 VIN_DATA_PIN_GROUP(vin5_data, 16), 4480 SH_PFC_PIN_GROUP(vin5_sync), 4481 SH_PFC_PIN_GROUP(vin5_field), 4482 SH_PFC_PIN_GROUP(vin5_clkenb), 4483 SH_PFC_PIN_GROUP(vin5_clk), 4484 }, 4485 .automotive = { 4486 SH_PFC_PIN_GROUP(drif0_ctrl_a), 4487 SH_PFC_PIN_GROUP(drif0_data0_a), 4488 SH_PFC_PIN_GROUP(drif0_data1_a), 4489 SH_PFC_PIN_GROUP(drif0_ctrl_b), 4490 SH_PFC_PIN_GROUP(drif0_data0_b), 4491 SH_PFC_PIN_GROUP(drif0_data1_b), 4492 SH_PFC_PIN_GROUP(drif0_ctrl_c), 4493 SH_PFC_PIN_GROUP(drif0_data0_c), 4494 SH_PFC_PIN_GROUP(drif0_data1_c), 4495 SH_PFC_PIN_GROUP(drif1_ctrl_a), 4496 SH_PFC_PIN_GROUP(drif1_data0_a), 4497 SH_PFC_PIN_GROUP(drif1_data1_a), 4498 SH_PFC_PIN_GROUP(drif1_ctrl_b), 4499 SH_PFC_PIN_GROUP(drif1_data0_b), 4500 SH_PFC_PIN_GROUP(drif1_data1_b), 4501 SH_PFC_PIN_GROUP(drif1_ctrl_c), 4502 SH_PFC_PIN_GROUP(drif1_data0_c), 4503 SH_PFC_PIN_GROUP(drif1_data1_c), 4504 SH_PFC_PIN_GROUP(drif2_ctrl_a), 4505 SH_PFC_PIN_GROUP(drif2_data0_a), 4506 SH_PFC_PIN_GROUP(drif2_data1_a), 4507 SH_PFC_PIN_GROUP(drif2_ctrl_b), 4508 SH_PFC_PIN_GROUP(drif2_data0_b), 4509 SH_PFC_PIN_GROUP(drif2_data1_b), 4510 SH_PFC_PIN_GROUP(drif3_ctrl_a), 4511 SH_PFC_PIN_GROUP(drif3_data0_a), 4512 SH_PFC_PIN_GROUP(drif3_data1_a), 4513 SH_PFC_PIN_GROUP(drif3_ctrl_b), 4514 SH_PFC_PIN_GROUP(drif3_data0_b), 4515 SH_PFC_PIN_GROUP(drif3_data1_b), 4516 } 4517 4518 }; 4519 4520 static const char * const audio_clk_groups[] = { 4521 "audio_clk_a_a", 4522 "audio_clk_a_b", 4523 "audio_clk_a_c", 4524 "audio_clk_b_a", 4525 "audio_clk_b_b", 4526 "audio_clk_c_a", 4527 "audio_clk_c_b", 4528 "audio_clkout_a", 4529 "audio_clkout_b", 4530 "audio_clkout_c", 4531 "audio_clkout_d", 4532 "audio_clkout1_a", 4533 "audio_clkout1_b", 4534 "audio_clkout2_a", 4535 "audio_clkout2_b", 4536 "audio_clkout3_a", 4537 "audio_clkout3_b", 4538 }; 4539 4540 static const char * const avb_groups[] = { 4541 "avb_link", 4542 "avb_magic", 4543 "avb_phy_int", 4544 "avb_mdc", /* Deprecated, please use "avb_mdio" instead */ 4545 "avb_mdio", 4546 "avb_mii", 4547 "avb_avtp_pps", 4548 "avb_avtp_match_a", 4549 "avb_avtp_capture_a", 4550 "avb_avtp_match_b", 4551 "avb_avtp_capture_b", 4552 }; 4553 4554 static const char * const can0_groups[] = { 4555 "can0_data_a", 4556 "can0_data_b", 4557 }; 4558 4559 static const char * const can1_groups[] = { 4560 "can1_data", 4561 }; 4562 4563 static const char * const can_clk_groups[] = { 4564 "can_clk", 4565 }; 4566 4567 static const char * const canfd0_groups[] = { 4568 "canfd0_data_a", 4569 "canfd0_data_b", 4570 }; 4571 4572 static const char * const canfd1_groups[] = { 4573 "canfd1_data", 4574 }; 4575 4576 static const char * const drif0_groups[] = { 4577 "drif0_ctrl_a", 4578 "drif0_data0_a", 4579 "drif0_data1_a", 4580 "drif0_ctrl_b", 4581 "drif0_data0_b", 4582 "drif0_data1_b", 4583 "drif0_ctrl_c", 4584 "drif0_data0_c", 4585 "drif0_data1_c", 4586 }; 4587 4588 static const char * const drif1_groups[] = { 4589 "drif1_ctrl_a", 4590 "drif1_data0_a", 4591 "drif1_data1_a", 4592 "drif1_ctrl_b", 4593 "drif1_data0_b", 4594 "drif1_data1_b", 4595 "drif1_ctrl_c", 4596 "drif1_data0_c", 4597 "drif1_data1_c", 4598 }; 4599 4600 static const char * const drif2_groups[] = { 4601 "drif2_ctrl_a", 4602 "drif2_data0_a", 4603 "drif2_data1_a", 4604 "drif2_ctrl_b", 4605 "drif2_data0_b", 4606 "drif2_data1_b", 4607 }; 4608 4609 static const char * const drif3_groups[] = { 4610 "drif3_ctrl_a", 4611 "drif3_data0_a", 4612 "drif3_data1_a", 4613 "drif3_ctrl_b", 4614 "drif3_data0_b", 4615 "drif3_data1_b", 4616 }; 4617 4618 static const char * const du_groups[] = { 4619 "du_rgb666", 4620 "du_rgb888", 4621 "du_clk_out_0", 4622 "du_clk_out_1", 4623 "du_sync", 4624 "du_oddf", 4625 "du_cde", 4626 "du_disp", 4627 }; 4628 4629 static const char * const hscif0_groups[] = { 4630 "hscif0_data", 4631 "hscif0_clk", 4632 "hscif0_ctrl", 4633 }; 4634 4635 static const char * const hscif1_groups[] = { 4636 "hscif1_data_a", 4637 "hscif1_clk_a", 4638 "hscif1_ctrl_a", 4639 "hscif1_data_b", 4640 "hscif1_clk_b", 4641 "hscif1_ctrl_b", 4642 }; 4643 4644 static const char * const hscif2_groups[] = { 4645 "hscif2_data_a", 4646 "hscif2_clk_a", 4647 "hscif2_ctrl_a", 4648 "hscif2_data_b", 4649 "hscif2_clk_b", 4650 "hscif2_ctrl_b", 4651 "hscif2_data_c", 4652 "hscif2_clk_c", 4653 "hscif2_ctrl_c", 4654 }; 4655 4656 static const char * const hscif3_groups[] = { 4657 "hscif3_data_a", 4658 "hscif3_clk", 4659 "hscif3_ctrl", 4660 "hscif3_data_b", 4661 "hscif3_data_c", 4662 "hscif3_data_d", 4663 }; 4664 4665 static const char * const hscif4_groups[] = { 4666 "hscif4_data_a", 4667 "hscif4_clk", 4668 "hscif4_ctrl", 4669 "hscif4_data_b", 4670 }; 4671 4672 static const char * const i2c0_groups[] = { 4673 "i2c0", 4674 }; 4675 4676 static const char * const i2c1_groups[] = { 4677 "i2c1_a", 4678 "i2c1_b", 4679 }; 4680 4681 static const char * const i2c2_groups[] = { 4682 "i2c2_a", 4683 "i2c2_b", 4684 }; 4685 4686 static const char * const i2c3_groups[] = { 4687 "i2c3", 4688 }; 4689 4690 static const char * const i2c5_groups[] = { 4691 "i2c5", 4692 }; 4693 4694 static const char * const i2c6_groups[] = { 4695 "i2c6_a", 4696 "i2c6_b", 4697 "i2c6_c", 4698 }; 4699 4700 static const char * const intc_ex_groups[] = { 4701 "intc_ex_irq0", 4702 "intc_ex_irq1", 4703 "intc_ex_irq2", 4704 "intc_ex_irq3", 4705 "intc_ex_irq4", 4706 "intc_ex_irq5", 4707 }; 4708 4709 static const char * const msiof0_groups[] = { 4710 "msiof0_clk", 4711 "msiof0_sync", 4712 "msiof0_ss1", 4713 "msiof0_ss2", 4714 "msiof0_txd", 4715 "msiof0_rxd", 4716 }; 4717 4718 static const char * const msiof1_groups[] = { 4719 "msiof1_clk_a", 4720 "msiof1_sync_a", 4721 "msiof1_ss1_a", 4722 "msiof1_ss2_a", 4723 "msiof1_txd_a", 4724 "msiof1_rxd_a", 4725 "msiof1_clk_b", 4726 "msiof1_sync_b", 4727 "msiof1_ss1_b", 4728 "msiof1_ss2_b", 4729 "msiof1_txd_b", 4730 "msiof1_rxd_b", 4731 "msiof1_clk_c", 4732 "msiof1_sync_c", 4733 "msiof1_ss1_c", 4734 "msiof1_ss2_c", 4735 "msiof1_txd_c", 4736 "msiof1_rxd_c", 4737 "msiof1_clk_d", 4738 "msiof1_sync_d", 4739 "msiof1_ss1_d", 4740 "msiof1_ss2_d", 4741 "msiof1_txd_d", 4742 "msiof1_rxd_d", 4743 "msiof1_clk_e", 4744 "msiof1_sync_e", 4745 "msiof1_ss1_e", 4746 "msiof1_ss2_e", 4747 "msiof1_txd_e", 4748 "msiof1_rxd_e", 4749 "msiof1_clk_f", 4750 "msiof1_sync_f", 4751 "msiof1_ss1_f", 4752 "msiof1_ss2_f", 4753 "msiof1_txd_f", 4754 "msiof1_rxd_f", 4755 "msiof1_clk_g", 4756 "msiof1_sync_g", 4757 "msiof1_ss1_g", 4758 "msiof1_ss2_g", 4759 "msiof1_txd_g", 4760 "msiof1_rxd_g", 4761 }; 4762 4763 static const char * const msiof2_groups[] = { 4764 "msiof2_clk_a", 4765 "msiof2_sync_a", 4766 "msiof2_ss1_a", 4767 "msiof2_ss2_a", 4768 "msiof2_txd_a", 4769 "msiof2_rxd_a", 4770 "msiof2_clk_b", 4771 "msiof2_sync_b", 4772 "msiof2_ss1_b", 4773 "msiof2_ss2_b", 4774 "msiof2_txd_b", 4775 "msiof2_rxd_b", 4776 "msiof2_clk_c", 4777 "msiof2_sync_c", 4778 "msiof2_ss1_c", 4779 "msiof2_ss2_c", 4780 "msiof2_txd_c", 4781 "msiof2_rxd_c", 4782 "msiof2_clk_d", 4783 "msiof2_sync_d", 4784 "msiof2_ss1_d", 4785 "msiof2_ss2_d", 4786 "msiof2_txd_d", 4787 "msiof2_rxd_d", 4788 }; 4789 4790 static const char * const msiof3_groups[] = { 4791 "msiof3_clk_a", 4792 "msiof3_sync_a", 4793 "msiof3_ss1_a", 4794 "msiof3_ss2_a", 4795 "msiof3_txd_a", 4796 "msiof3_rxd_a", 4797 "msiof3_clk_b", 4798 "msiof3_sync_b", 4799 "msiof3_ss1_b", 4800 "msiof3_ss2_b", 4801 "msiof3_txd_b", 4802 "msiof3_rxd_b", 4803 "msiof3_clk_c", 4804 "msiof3_sync_c", 4805 "msiof3_txd_c", 4806 "msiof3_rxd_c", 4807 "msiof3_clk_d", 4808 "msiof3_sync_d", 4809 "msiof3_ss1_d", 4810 "msiof3_txd_d", 4811 "msiof3_rxd_d", 4812 "msiof3_clk_e", 4813 "msiof3_sync_e", 4814 "msiof3_ss1_e", 4815 "msiof3_ss2_e", 4816 "msiof3_txd_e", 4817 "msiof3_rxd_e", 4818 }; 4819 4820 static const char * const pwm0_groups[] = { 4821 "pwm0", 4822 }; 4823 4824 static const char * const pwm1_groups[] = { 4825 "pwm1_a", 4826 "pwm1_b", 4827 }; 4828 4829 static const char * const pwm2_groups[] = { 4830 "pwm2_a", 4831 "pwm2_b", 4832 }; 4833 4834 static const char * const pwm3_groups[] = { 4835 "pwm3_a", 4836 "pwm3_b", 4837 }; 4838 4839 static const char * const pwm4_groups[] = { 4840 "pwm4_a", 4841 "pwm4_b", 4842 }; 4843 4844 static const char * const pwm5_groups[] = { 4845 "pwm5_a", 4846 "pwm5_b", 4847 }; 4848 4849 static const char * const pwm6_groups[] = { 4850 "pwm6_a", 4851 "pwm6_b", 4852 }; 4853 4854 static const char * const sata0_groups[] = { 4855 "sata0_devslp_a", 4856 "sata0_devslp_b", 4857 }; 4858 4859 static const char * const scif0_groups[] = { 4860 "scif0_data", 4861 "scif0_clk", 4862 "scif0_ctrl", 4863 }; 4864 4865 static const char * const scif1_groups[] = { 4866 "scif1_data_a", 4867 "scif1_clk", 4868 "scif1_ctrl", 4869 "scif1_data_b", 4870 }; 4871 4872 static const char * const scif2_groups[] = { 4873 "scif2_data_a", 4874 "scif2_clk", 4875 "scif2_data_b", 4876 }; 4877 4878 static const char * const scif3_groups[] = { 4879 "scif3_data_a", 4880 "scif3_clk", 4881 "scif3_ctrl", 4882 "scif3_data_b", 4883 }; 4884 4885 static const char * const scif4_groups[] = { 4886 "scif4_data_a", 4887 "scif4_clk_a", 4888 "scif4_ctrl_a", 4889 "scif4_data_b", 4890 "scif4_clk_b", 4891 "scif4_ctrl_b", 4892 "scif4_data_c", 4893 "scif4_clk_c", 4894 "scif4_ctrl_c", 4895 }; 4896 4897 static const char * const scif5_groups[] = { 4898 "scif5_data_a", 4899 "scif5_clk_a", 4900 "scif5_data_b", 4901 "scif5_clk_b", 4902 }; 4903 4904 static const char * const scif_clk_groups[] = { 4905 "scif_clk_a", 4906 "scif_clk_b", 4907 }; 4908 4909 static const char * const sdhi0_groups[] = { 4910 "sdhi0_data1", 4911 "sdhi0_data4", 4912 "sdhi0_ctrl", 4913 "sdhi0_cd", 4914 "sdhi0_wp", 4915 }; 4916 4917 static const char * const sdhi1_groups[] = { 4918 "sdhi1_data1", 4919 "sdhi1_data4", 4920 "sdhi1_ctrl", 4921 "sdhi1_cd", 4922 "sdhi1_wp", 4923 }; 4924 4925 static const char * const sdhi2_groups[] = { 4926 "sdhi2_data1", 4927 "sdhi2_data4", 4928 "sdhi2_data8", 4929 "sdhi2_ctrl", 4930 "sdhi2_cd_a", 4931 "sdhi2_wp_a", 4932 "sdhi2_cd_b", 4933 "sdhi2_wp_b", 4934 "sdhi2_ds", 4935 }; 4936 4937 static const char * const sdhi3_groups[] = { 4938 "sdhi3_data1", 4939 "sdhi3_data4", 4940 "sdhi3_data8", 4941 "sdhi3_ctrl", 4942 "sdhi3_cd", 4943 "sdhi3_wp", 4944 "sdhi3_ds", 4945 }; 4946 4947 static const char * const ssi_groups[] = { 4948 "ssi0_data", 4949 "ssi01239_ctrl", 4950 "ssi1_data_a", 4951 "ssi1_data_b", 4952 "ssi1_ctrl_a", 4953 "ssi1_ctrl_b", 4954 "ssi2_data_a", 4955 "ssi2_data_b", 4956 "ssi2_ctrl_a", 4957 "ssi2_ctrl_b", 4958 "ssi3_data", 4959 "ssi349_ctrl", 4960 "ssi4_data", 4961 "ssi4_ctrl", 4962 "ssi5_data", 4963 "ssi5_ctrl", 4964 "ssi6_data", 4965 "ssi6_ctrl", 4966 "ssi7_data", 4967 "ssi78_ctrl", 4968 "ssi8_data", 4969 "ssi9_data_a", 4970 "ssi9_data_b", 4971 "ssi9_ctrl_a", 4972 "ssi9_ctrl_b", 4973 }; 4974 4975 static const char * const tmu_groups[] = { 4976 "tmu_tclk1_a", 4977 "tmu_tclk1_b", 4978 "tmu_tclk2_a", 4979 "tmu_tclk2_b", 4980 }; 4981 4982 static const char * const tpu_groups[] = { 4983 "tpu_to0", 4984 "tpu_to1", 4985 "tpu_to2", 4986 "tpu_to3", 4987 }; 4988 4989 static const char * const usb0_groups[] = { 4990 "usb0", 4991 }; 4992 4993 static const char * const usb1_groups[] = { 4994 "usb1", 4995 }; 4996 4997 static const char * const usb2_groups[] = { 4998 "usb2", 4999 }; 5000 5001 static const char * const usb2_ch3_groups[] = { 5002 "usb2_ch3", 5003 }; 5004 5005 static const char * const usb30_groups[] = { 5006 "usb30", 5007 }; 5008 5009 static const char * const vin4_groups[] = { 5010 "vin4_data8_a", 5011 "vin4_data10_a", 5012 "vin4_data12_a", 5013 "vin4_data16_a", 5014 "vin4_data18_a", 5015 "vin4_data20_a", 5016 "vin4_data24_a", 5017 "vin4_data8_b", 5018 "vin4_data10_b", 5019 "vin4_data12_b", 5020 "vin4_data16_b", 5021 "vin4_data18_b", 5022 "vin4_data20_b", 5023 "vin4_data24_b", 5024 "vin4_sync", 5025 "vin4_field", 5026 "vin4_clkenb", 5027 "vin4_clk", 5028 }; 5029 5030 static const char * const vin5_groups[] = { 5031 "vin5_data8", 5032 "vin5_data10", 5033 "vin5_data12", 5034 "vin5_data16", 5035 "vin5_sync", 5036 "vin5_field", 5037 "vin5_clkenb", 5038 "vin5_clk", 5039 }; 5040 5041 static const struct { 5042 struct sh_pfc_function common[53]; 5043 struct sh_pfc_function automotive[4]; 5044 } pinmux_functions = { 5045 .common = { 5046 SH_PFC_FUNCTION(audio_clk), 5047 SH_PFC_FUNCTION(avb), 5048 SH_PFC_FUNCTION(can0), 5049 SH_PFC_FUNCTION(can1), 5050 SH_PFC_FUNCTION(can_clk), 5051 SH_PFC_FUNCTION(canfd0), 5052 SH_PFC_FUNCTION(canfd1), 5053 SH_PFC_FUNCTION(du), 5054 SH_PFC_FUNCTION(hscif0), 5055 SH_PFC_FUNCTION(hscif1), 5056 SH_PFC_FUNCTION(hscif2), 5057 SH_PFC_FUNCTION(hscif3), 5058 SH_PFC_FUNCTION(hscif4), 5059 SH_PFC_FUNCTION(i2c0), 5060 SH_PFC_FUNCTION(i2c1), 5061 SH_PFC_FUNCTION(i2c2), 5062 SH_PFC_FUNCTION(i2c3), 5063 SH_PFC_FUNCTION(i2c5), 5064 SH_PFC_FUNCTION(i2c6), 5065 SH_PFC_FUNCTION(intc_ex), 5066 SH_PFC_FUNCTION(msiof0), 5067 SH_PFC_FUNCTION(msiof1), 5068 SH_PFC_FUNCTION(msiof2), 5069 SH_PFC_FUNCTION(msiof3), 5070 SH_PFC_FUNCTION(pwm0), 5071 SH_PFC_FUNCTION(pwm1), 5072 SH_PFC_FUNCTION(pwm2), 5073 SH_PFC_FUNCTION(pwm3), 5074 SH_PFC_FUNCTION(pwm4), 5075 SH_PFC_FUNCTION(pwm5), 5076 SH_PFC_FUNCTION(pwm6), 5077 SH_PFC_FUNCTION(sata0), 5078 SH_PFC_FUNCTION(scif0), 5079 SH_PFC_FUNCTION(scif1), 5080 SH_PFC_FUNCTION(scif2), 5081 SH_PFC_FUNCTION(scif3), 5082 SH_PFC_FUNCTION(scif4), 5083 SH_PFC_FUNCTION(scif5), 5084 SH_PFC_FUNCTION(scif_clk), 5085 SH_PFC_FUNCTION(sdhi0), 5086 SH_PFC_FUNCTION(sdhi1), 5087 SH_PFC_FUNCTION(sdhi2), 5088 SH_PFC_FUNCTION(sdhi3), 5089 SH_PFC_FUNCTION(ssi), 5090 SH_PFC_FUNCTION(tmu), 5091 SH_PFC_FUNCTION(tpu), 5092 SH_PFC_FUNCTION(usb0), 5093 SH_PFC_FUNCTION(usb1), 5094 SH_PFC_FUNCTION(usb2), 5095 SH_PFC_FUNCTION(usb2_ch3), 5096 SH_PFC_FUNCTION(usb30), 5097 SH_PFC_FUNCTION(vin4), 5098 SH_PFC_FUNCTION(vin5), 5099 }, 5100 .automotive = { 5101 SH_PFC_FUNCTION(drif0), 5102 SH_PFC_FUNCTION(drif1), 5103 SH_PFC_FUNCTION(drif2), 5104 SH_PFC_FUNCTION(drif3), 5105 } 5106 5107 }; 5108 5109 static const struct pinmux_cfg_reg pinmux_config_regs[] = { 5110 #define F_(x, y) FN_##y 5111 #define FM(x) FN_##x 5112 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP( 5113 0, 0, 5114 0, 0, 5115 0, 0, 5116 0, 0, 5117 0, 0, 5118 0, 0, 5119 0, 0, 5120 0, 0, 5121 0, 0, 5122 0, 0, 5123 0, 0, 5124 0, 0, 5125 0, 0, 5126 0, 0, 5127 0, 0, 5128 0, 0, 5129 GP_0_15_FN, GPSR0_15, 5130 GP_0_14_FN, GPSR0_14, 5131 GP_0_13_FN, GPSR0_13, 5132 GP_0_12_FN, GPSR0_12, 5133 GP_0_11_FN, GPSR0_11, 5134 GP_0_10_FN, GPSR0_10, 5135 GP_0_9_FN, GPSR0_9, 5136 GP_0_8_FN, GPSR0_8, 5137 GP_0_7_FN, GPSR0_7, 5138 GP_0_6_FN, GPSR0_6, 5139 GP_0_5_FN, GPSR0_5, 5140 GP_0_4_FN, GPSR0_4, 5141 GP_0_3_FN, GPSR0_3, 5142 GP_0_2_FN, GPSR0_2, 5143 GP_0_1_FN, GPSR0_1, 5144 GP_0_0_FN, GPSR0_0, )) 5145 }, 5146 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP( 5147 0, 0, 5148 0, 0, 5149 0, 0, 5150 GP_1_28_FN, GPSR1_28, 5151 GP_1_27_FN, GPSR1_27, 5152 GP_1_26_FN, GPSR1_26, 5153 GP_1_25_FN, GPSR1_25, 5154 GP_1_24_FN, GPSR1_24, 5155 GP_1_23_FN, GPSR1_23, 5156 GP_1_22_FN, GPSR1_22, 5157 GP_1_21_FN, GPSR1_21, 5158 GP_1_20_FN, GPSR1_20, 5159 GP_1_19_FN, GPSR1_19, 5160 GP_1_18_FN, GPSR1_18, 5161 GP_1_17_FN, GPSR1_17, 5162 GP_1_16_FN, GPSR1_16, 5163 GP_1_15_FN, GPSR1_15, 5164 GP_1_14_FN, GPSR1_14, 5165 GP_1_13_FN, GPSR1_13, 5166 GP_1_12_FN, GPSR1_12, 5167 GP_1_11_FN, GPSR1_11, 5168 GP_1_10_FN, GPSR1_10, 5169 GP_1_9_FN, GPSR1_9, 5170 GP_1_8_FN, GPSR1_8, 5171 GP_1_7_FN, GPSR1_7, 5172 GP_1_6_FN, GPSR1_6, 5173 GP_1_5_FN, GPSR1_5, 5174 GP_1_4_FN, GPSR1_4, 5175 GP_1_3_FN, GPSR1_3, 5176 GP_1_2_FN, GPSR1_2, 5177 GP_1_1_FN, GPSR1_1, 5178 GP_1_0_FN, GPSR1_0, )) 5179 }, 5180 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP( 5181 0, 0, 5182 0, 0, 5183 0, 0, 5184 0, 0, 5185 0, 0, 5186 0, 0, 5187 0, 0, 5188 0, 0, 5189 0, 0, 5190 0, 0, 5191 0, 0, 5192 0, 0, 5193 0, 0, 5194 0, 0, 5195 0, 0, 5196 0, 0, 5197 0, 0, 5198 GP_2_14_FN, GPSR2_14, 5199 GP_2_13_FN, GPSR2_13, 5200 GP_2_12_FN, GPSR2_12, 5201 GP_2_11_FN, GPSR2_11, 5202 GP_2_10_FN, GPSR2_10, 5203 GP_2_9_FN, GPSR2_9, 5204 GP_2_8_FN, GPSR2_8, 5205 GP_2_7_FN, GPSR2_7, 5206 GP_2_6_FN, GPSR2_6, 5207 GP_2_5_FN, GPSR2_5, 5208 GP_2_4_FN, GPSR2_4, 5209 GP_2_3_FN, GPSR2_3, 5210 GP_2_2_FN, GPSR2_2, 5211 GP_2_1_FN, GPSR2_1, 5212 GP_2_0_FN, GPSR2_0, )) 5213 }, 5214 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP( 5215 0, 0, 5216 0, 0, 5217 0, 0, 5218 0, 0, 5219 0, 0, 5220 0, 0, 5221 0, 0, 5222 0, 0, 5223 0, 0, 5224 0, 0, 5225 0, 0, 5226 0, 0, 5227 0, 0, 5228 0, 0, 5229 0, 0, 5230 0, 0, 5231 GP_3_15_FN, GPSR3_15, 5232 GP_3_14_FN, GPSR3_14, 5233 GP_3_13_FN, GPSR3_13, 5234 GP_3_12_FN, GPSR3_12, 5235 GP_3_11_FN, GPSR3_11, 5236 GP_3_10_FN, GPSR3_10, 5237 GP_3_9_FN, GPSR3_9, 5238 GP_3_8_FN, GPSR3_8, 5239 GP_3_7_FN, GPSR3_7, 5240 GP_3_6_FN, GPSR3_6, 5241 GP_3_5_FN, GPSR3_5, 5242 GP_3_4_FN, GPSR3_4, 5243 GP_3_3_FN, GPSR3_3, 5244 GP_3_2_FN, GPSR3_2, 5245 GP_3_1_FN, GPSR3_1, 5246 GP_3_0_FN, GPSR3_0, )) 5247 }, 5248 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP( 5249 0, 0, 5250 0, 0, 5251 0, 0, 5252 0, 0, 5253 0, 0, 5254 0, 0, 5255 0, 0, 5256 0, 0, 5257 0, 0, 5258 0, 0, 5259 0, 0, 5260 0, 0, 5261 0, 0, 5262 0, 0, 5263 GP_4_17_FN, GPSR4_17, 5264 GP_4_16_FN, GPSR4_16, 5265 GP_4_15_FN, GPSR4_15, 5266 GP_4_14_FN, GPSR4_14, 5267 GP_4_13_FN, GPSR4_13, 5268 GP_4_12_FN, GPSR4_12, 5269 GP_4_11_FN, GPSR4_11, 5270 GP_4_10_FN, GPSR4_10, 5271 GP_4_9_FN, GPSR4_9, 5272 GP_4_8_FN, GPSR4_8, 5273 GP_4_7_FN, GPSR4_7, 5274 GP_4_6_FN, GPSR4_6, 5275 GP_4_5_FN, GPSR4_5, 5276 GP_4_4_FN, GPSR4_4, 5277 GP_4_3_FN, GPSR4_3, 5278 GP_4_2_FN, GPSR4_2, 5279 GP_4_1_FN, GPSR4_1, 5280 GP_4_0_FN, GPSR4_0, )) 5281 }, 5282 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP( 5283 0, 0, 5284 0, 0, 5285 0, 0, 5286 0, 0, 5287 0, 0, 5288 0, 0, 5289 GP_5_25_FN, GPSR5_25, 5290 GP_5_24_FN, GPSR5_24, 5291 GP_5_23_FN, GPSR5_23, 5292 GP_5_22_FN, GPSR5_22, 5293 GP_5_21_FN, GPSR5_21, 5294 GP_5_20_FN, GPSR5_20, 5295 GP_5_19_FN, GPSR5_19, 5296 GP_5_18_FN, GPSR5_18, 5297 GP_5_17_FN, GPSR5_17, 5298 GP_5_16_FN, GPSR5_16, 5299 GP_5_15_FN, GPSR5_15, 5300 GP_5_14_FN, GPSR5_14, 5301 GP_5_13_FN, GPSR5_13, 5302 GP_5_12_FN, GPSR5_12, 5303 GP_5_11_FN, GPSR5_11, 5304 GP_5_10_FN, GPSR5_10, 5305 GP_5_9_FN, GPSR5_9, 5306 GP_5_8_FN, GPSR5_8, 5307 GP_5_7_FN, GPSR5_7, 5308 GP_5_6_FN, GPSR5_6, 5309 GP_5_5_FN, GPSR5_5, 5310 GP_5_4_FN, GPSR5_4, 5311 GP_5_3_FN, GPSR5_3, 5312 GP_5_2_FN, GPSR5_2, 5313 GP_5_1_FN, GPSR5_1, 5314 GP_5_0_FN, GPSR5_0, )) 5315 }, 5316 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP( 5317 GP_6_31_FN, GPSR6_31, 5318 GP_6_30_FN, GPSR6_30, 5319 GP_6_29_FN, GPSR6_29, 5320 GP_6_28_FN, GPSR6_28, 5321 GP_6_27_FN, GPSR6_27, 5322 GP_6_26_FN, GPSR6_26, 5323 GP_6_25_FN, GPSR6_25, 5324 GP_6_24_FN, GPSR6_24, 5325 GP_6_23_FN, GPSR6_23, 5326 GP_6_22_FN, GPSR6_22, 5327 GP_6_21_FN, GPSR6_21, 5328 GP_6_20_FN, GPSR6_20, 5329 GP_6_19_FN, GPSR6_19, 5330 GP_6_18_FN, GPSR6_18, 5331 GP_6_17_FN, GPSR6_17, 5332 GP_6_16_FN, GPSR6_16, 5333 GP_6_15_FN, GPSR6_15, 5334 GP_6_14_FN, GPSR6_14, 5335 GP_6_13_FN, GPSR6_13, 5336 GP_6_12_FN, GPSR6_12, 5337 GP_6_11_FN, GPSR6_11, 5338 GP_6_10_FN, GPSR6_10, 5339 GP_6_9_FN, GPSR6_9, 5340 GP_6_8_FN, GPSR6_8, 5341 GP_6_7_FN, GPSR6_7, 5342 GP_6_6_FN, GPSR6_6, 5343 GP_6_5_FN, GPSR6_5, 5344 GP_6_4_FN, GPSR6_4, 5345 GP_6_3_FN, GPSR6_3, 5346 GP_6_2_FN, GPSR6_2, 5347 GP_6_1_FN, GPSR6_1, 5348 GP_6_0_FN, GPSR6_0, )) 5349 }, 5350 { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1, GROUP( 5351 0, 0, 5352 0, 0, 5353 0, 0, 5354 0, 0, 5355 0, 0, 5356 0, 0, 5357 0, 0, 5358 0, 0, 5359 0, 0, 5360 0, 0, 5361 0, 0, 5362 0, 0, 5363 0, 0, 5364 0, 0, 5365 0, 0, 5366 0, 0, 5367 0, 0, 5368 0, 0, 5369 0, 0, 5370 0, 0, 5371 0, 0, 5372 0, 0, 5373 0, 0, 5374 0, 0, 5375 0, 0, 5376 0, 0, 5377 0, 0, 5378 0, 0, 5379 GP_7_3_FN, GPSR7_3, 5380 GP_7_2_FN, GPSR7_2, 5381 GP_7_1_FN, GPSR7_1, 5382 GP_7_0_FN, GPSR7_0, )) 5383 }, 5384 #undef F_ 5385 #undef FM 5386 5387 #define F_(x, y) x, 5388 #define FM(x) FN_##x, 5389 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP( 5390 IP0_31_28 5391 IP0_27_24 5392 IP0_23_20 5393 IP0_19_16 5394 IP0_15_12 5395 IP0_11_8 5396 IP0_7_4 5397 IP0_3_0 )) 5398 }, 5399 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP( 5400 IP1_31_28 5401 IP1_27_24 5402 IP1_23_20 5403 IP1_19_16 5404 IP1_15_12 5405 IP1_11_8 5406 IP1_7_4 5407 IP1_3_0 )) 5408 }, 5409 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP( 5410 IP2_31_28 5411 IP2_27_24 5412 IP2_23_20 5413 IP2_19_16 5414 IP2_15_12 5415 IP2_11_8 5416 IP2_7_4 5417 IP2_3_0 )) 5418 }, 5419 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP( 5420 IP3_31_28 5421 IP3_27_24 5422 IP3_23_20 5423 IP3_19_16 5424 IP3_15_12 5425 IP3_11_8 5426 IP3_7_4 5427 IP3_3_0 )) 5428 }, 5429 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP( 5430 IP4_31_28 5431 IP4_27_24 5432 IP4_23_20 5433 IP4_19_16 5434 IP4_15_12 5435 IP4_11_8 5436 IP4_7_4 5437 IP4_3_0 )) 5438 }, 5439 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP( 5440 IP5_31_28 5441 IP5_27_24 5442 IP5_23_20 5443 IP5_19_16 5444 IP5_15_12 5445 IP5_11_8 5446 IP5_7_4 5447 IP5_3_0 )) 5448 }, 5449 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP( 5450 IP6_31_28 5451 IP6_27_24 5452 IP6_23_20 5453 IP6_19_16 5454 IP6_15_12 5455 IP6_11_8 5456 IP6_7_4 5457 IP6_3_0 )) 5458 }, 5459 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP( 5460 IP7_31_28 5461 IP7_27_24 5462 IP7_23_20 5463 IP7_19_16 5464 /* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5465 IP7_11_8 5466 IP7_7_4 5467 IP7_3_0 )) 5468 }, 5469 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP( 5470 IP8_31_28 5471 IP8_27_24 5472 IP8_23_20 5473 IP8_19_16 5474 IP8_15_12 5475 IP8_11_8 5476 IP8_7_4 5477 IP8_3_0 )) 5478 }, 5479 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP( 5480 IP9_31_28 5481 IP9_27_24 5482 IP9_23_20 5483 IP9_19_16 5484 IP9_15_12 5485 IP9_11_8 5486 IP9_7_4 5487 IP9_3_0 )) 5488 }, 5489 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP( 5490 IP10_31_28 5491 IP10_27_24 5492 IP10_23_20 5493 IP10_19_16 5494 IP10_15_12 5495 IP10_11_8 5496 IP10_7_4 5497 IP10_3_0 )) 5498 }, 5499 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP( 5500 IP11_31_28 5501 IP11_27_24 5502 IP11_23_20 5503 IP11_19_16 5504 IP11_15_12 5505 IP11_11_8 5506 IP11_7_4 5507 IP11_3_0 )) 5508 }, 5509 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP( 5510 IP12_31_28 5511 IP12_27_24 5512 IP12_23_20 5513 IP12_19_16 5514 IP12_15_12 5515 IP12_11_8 5516 IP12_7_4 5517 IP12_3_0 )) 5518 }, 5519 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP( 5520 IP13_31_28 5521 IP13_27_24 5522 IP13_23_20 5523 IP13_19_16 5524 IP13_15_12 5525 IP13_11_8 5526 IP13_7_4 5527 IP13_3_0 )) 5528 }, 5529 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP( 5530 IP14_31_28 5531 IP14_27_24 5532 IP14_23_20 5533 IP14_19_16 5534 IP14_15_12 5535 IP14_11_8 5536 IP14_7_4 5537 IP14_3_0 )) 5538 }, 5539 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP( 5540 IP15_31_28 5541 IP15_27_24 5542 IP15_23_20 5543 IP15_19_16 5544 IP15_15_12 5545 IP15_11_8 5546 IP15_7_4 5547 IP15_3_0 )) 5548 }, 5549 { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4, GROUP( 5550 IP16_31_28 5551 IP16_27_24 5552 IP16_23_20 5553 IP16_19_16 5554 IP16_15_12 5555 IP16_11_8 5556 IP16_7_4 5557 IP16_3_0 )) 5558 }, 5559 { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4, GROUP( 5560 IP17_31_28 5561 IP17_27_24 5562 IP17_23_20 5563 IP17_19_16 5564 IP17_15_12 5565 IP17_11_8 5566 IP17_7_4 5567 IP17_3_0 )) 5568 }, 5569 { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4, GROUP( 5570 /* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5571 /* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5572 /* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5573 /* IP18_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5574 /* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5575 /* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5576 IP18_7_4 5577 IP18_3_0 )) 5578 }, 5579 #undef F_ 5580 #undef FM 5581 5582 #define F_(x, y) x, 5583 #define FM(x) FN_##x, 5584 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32, 5585 GROUP(3, 2, 3, 1, 1, 1, 1, 1, 2, 1, 1, 2, 5586 1, 1, 1, 2, 2, 1, 2, 3), 5587 GROUP( 5588 MOD_SEL0_31_30_29 5589 MOD_SEL0_28_27 5590 MOD_SEL0_26_25_24 5591 MOD_SEL0_23 5592 MOD_SEL0_22 5593 MOD_SEL0_21 5594 MOD_SEL0_20 5595 MOD_SEL0_19 5596 MOD_SEL0_18_17 5597 MOD_SEL0_16 5598 0, 0, /* RESERVED 15 */ 5599 MOD_SEL0_14_13 5600 MOD_SEL0_12 5601 MOD_SEL0_11 5602 MOD_SEL0_10 5603 MOD_SEL0_9_8 5604 MOD_SEL0_7_6 5605 MOD_SEL0_5 5606 MOD_SEL0_4_3 5607 /* RESERVED 2, 1, 0 */ 5608 0, 0, 0, 0, 0, 0, 0, 0 )) 5609 }, 5610 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32, 5611 GROUP(2, 3, 1, 2, 3, 1, 1, 2, 1, 2, 1, 1, 5612 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1), 5613 GROUP( 5614 MOD_SEL1_31_30 5615 MOD_SEL1_29_28_27 5616 MOD_SEL1_26 5617 MOD_SEL1_25_24 5618 MOD_SEL1_23_22_21 5619 MOD_SEL1_20 5620 MOD_SEL1_19 5621 MOD_SEL1_18_17 5622 MOD_SEL1_16 5623 MOD_SEL1_15_14 5624 MOD_SEL1_13 5625 MOD_SEL1_12 5626 MOD_SEL1_11 5627 MOD_SEL1_10 5628 MOD_SEL1_9 5629 0, 0, 0, 0, /* RESERVED 8, 7 */ 5630 MOD_SEL1_6 5631 MOD_SEL1_5 5632 MOD_SEL1_4 5633 MOD_SEL1_3 5634 MOD_SEL1_2 5635 MOD_SEL1_1 5636 MOD_SEL1_0 )) 5637 }, 5638 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32, 5639 GROUP(1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, 5640 1, 4, 4, 4, 3, 1), 5641 GROUP( 5642 MOD_SEL2_31 5643 MOD_SEL2_30 5644 MOD_SEL2_29 5645 MOD_SEL2_28_27 5646 MOD_SEL2_26 5647 MOD_SEL2_25_24_23 5648 /* RESERVED 22 */ 5649 0, 0, 5650 MOD_SEL2_21 5651 MOD_SEL2_20 5652 MOD_SEL2_19 5653 MOD_SEL2_18 5654 MOD_SEL2_17 5655 /* RESERVED 16 */ 5656 0, 0, 5657 /* RESERVED 15, 14, 13, 12 */ 5658 0, 0, 0, 0, 0, 0, 0, 0, 5659 0, 0, 0, 0, 0, 0, 0, 0, 5660 /* RESERVED 11, 10, 9, 8 */ 5661 0, 0, 0, 0, 0, 0, 0, 0, 5662 0, 0, 0, 0, 0, 0, 0, 0, 5663 /* RESERVED 7, 6, 5, 4 */ 5664 0, 0, 0, 0, 0, 0, 0, 0, 5665 0, 0, 0, 0, 0, 0, 0, 0, 5666 /* RESERVED 3, 2, 1 */ 5667 0, 0, 0, 0, 0, 0, 0, 0, 5668 MOD_SEL2_0 )) 5669 }, 5670 { }, 5671 }; 5672 5673 static const struct pinmux_drive_reg pinmux_drive_regs[] = { 5674 { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) { 5675 { PIN_QSPI0_SPCLK, 28, 2 }, /* QSPI0_SPCLK */ 5676 { PIN_QSPI0_MOSI_IO0, 24, 2 }, /* QSPI0_MOSI_IO0 */ 5677 { PIN_QSPI0_MISO_IO1, 20, 2 }, /* QSPI0_MISO_IO1 */ 5678 { PIN_QSPI0_IO2, 16, 2 }, /* QSPI0_IO2 */ 5679 { PIN_QSPI0_IO3, 12, 2 }, /* QSPI0_IO3 */ 5680 { PIN_QSPI0_SSL, 8, 2 }, /* QSPI0_SSL */ 5681 { PIN_QSPI1_SPCLK, 4, 2 }, /* QSPI1_SPCLK */ 5682 { PIN_QSPI1_MOSI_IO0, 0, 2 }, /* QSPI1_MOSI_IO0 */ 5683 } }, 5684 { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) { 5685 { PIN_QSPI1_MISO_IO1, 28, 2 }, /* QSPI1_MISO_IO1 */ 5686 { PIN_QSPI1_IO2, 24, 2 }, /* QSPI1_IO2 */ 5687 { PIN_QSPI1_IO3, 20, 2 }, /* QSPI1_IO3 */ 5688 { PIN_QSPI1_SSL, 16, 2 }, /* QSPI1_SSL */ 5689 { PIN_RPC_INT_N, 12, 2 }, /* RPC_INT# */ 5690 { PIN_RPC_WP_N, 8, 2 }, /* RPC_WP# */ 5691 { PIN_RPC_RESET_N, 4, 2 }, /* RPC_RESET# */ 5692 { PIN_AVB_RX_CTL, 0, 3 }, /* AVB_RX_CTL */ 5693 } }, 5694 { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) { 5695 { PIN_AVB_RXC, 28, 3 }, /* AVB_RXC */ 5696 { PIN_AVB_RD0, 24, 3 }, /* AVB_RD0 */ 5697 { PIN_AVB_RD1, 20, 3 }, /* AVB_RD1 */ 5698 { PIN_AVB_RD2, 16, 3 }, /* AVB_RD2 */ 5699 { PIN_AVB_RD3, 12, 3 }, /* AVB_RD3 */ 5700 { PIN_AVB_TX_CTL, 8, 3 }, /* AVB_TX_CTL */ 5701 { PIN_AVB_TXC, 4, 3 }, /* AVB_TXC */ 5702 { PIN_AVB_TD0, 0, 3 }, /* AVB_TD0 */ 5703 } }, 5704 { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) { 5705 { PIN_AVB_TD1, 28, 3 }, /* AVB_TD1 */ 5706 { PIN_AVB_TD2, 24, 3 }, /* AVB_TD2 */ 5707 { PIN_AVB_TD3, 20, 3 }, /* AVB_TD3 */ 5708 { PIN_AVB_TXCREFCLK, 16, 3 }, /* AVB_TXCREFCLK */ 5709 { PIN_AVB_MDIO, 12, 3 }, /* AVB_MDIO */ 5710 { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */ 5711 { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */ 5712 { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */ 5713 } }, 5714 { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) { 5715 { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */ 5716 { RCAR_GP_PIN(2, 13), 24, 3 }, /* AVB_AVTP_MATCH */ 5717 { RCAR_GP_PIN(2, 14), 20, 3 }, /* AVB_AVTP_CAPTURE */ 5718 { RCAR_GP_PIN(2, 0), 16, 3 }, /* IRQ0 */ 5719 { RCAR_GP_PIN(2, 1), 12, 3 }, /* IRQ1 */ 5720 { RCAR_GP_PIN(2, 2), 8, 3 }, /* IRQ2 */ 5721 { RCAR_GP_PIN(2, 3), 4, 3 }, /* IRQ3 */ 5722 { RCAR_GP_PIN(2, 4), 0, 3 }, /* IRQ4 */ 5723 } }, 5724 { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) { 5725 { RCAR_GP_PIN(2, 5), 28, 3 }, /* IRQ5 */ 5726 { RCAR_GP_PIN(2, 6), 24, 3 }, /* PWM0 */ 5727 { RCAR_GP_PIN(2, 7), 20, 3 }, /* PWM1 */ 5728 { RCAR_GP_PIN(2, 8), 16, 3 }, /* PWM2 */ 5729 { RCAR_GP_PIN(1, 0), 12, 3 }, /* A0 */ 5730 { RCAR_GP_PIN(1, 1), 8, 3 }, /* A1 */ 5731 { RCAR_GP_PIN(1, 2), 4, 3 }, /* A2 */ 5732 { RCAR_GP_PIN(1, 3), 0, 3 }, /* A3 */ 5733 } }, 5734 { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) { 5735 { RCAR_GP_PIN(1, 4), 28, 3 }, /* A4 */ 5736 { RCAR_GP_PIN(1, 5), 24, 3 }, /* A5 */ 5737 { RCAR_GP_PIN(1, 6), 20, 3 }, /* A6 */ 5738 { RCAR_GP_PIN(1, 7), 16, 3 }, /* A7 */ 5739 { RCAR_GP_PIN(1, 8), 12, 3 }, /* A8 */ 5740 { RCAR_GP_PIN(1, 9), 8, 3 }, /* A9 */ 5741 { RCAR_GP_PIN(1, 10), 4, 3 }, /* A10 */ 5742 { RCAR_GP_PIN(1, 11), 0, 3 }, /* A11 */ 5743 } }, 5744 { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) { 5745 { RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */ 5746 { RCAR_GP_PIN(1, 13), 24, 3 }, /* A13 */ 5747 { RCAR_GP_PIN(1, 14), 20, 3 }, /* A14 */ 5748 { RCAR_GP_PIN(1, 15), 16, 3 }, /* A15 */ 5749 { RCAR_GP_PIN(1, 16), 12, 3 }, /* A16 */ 5750 { RCAR_GP_PIN(1, 17), 8, 3 }, /* A17 */ 5751 { RCAR_GP_PIN(1, 18), 4, 3 }, /* A18 */ 5752 { RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */ 5753 } }, 5754 { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) { 5755 { RCAR_GP_PIN(1, 28), 28, 3 }, /* CLKOUT */ 5756 { RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */ 5757 { RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */ 5758 { RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */ 5759 { RCAR_GP_PIN(1, 23), 12, 3 }, /* RD */ 5760 { RCAR_GP_PIN(1, 24), 8, 3 }, /* RD_WR */ 5761 { RCAR_GP_PIN(1, 25), 4, 3 }, /* WE0 */ 5762 { RCAR_GP_PIN(1, 26), 0, 3 }, /* WE1 */ 5763 } }, 5764 { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) { 5765 { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */ 5766 { PIN_PRESETOUT_N, 24, 3 }, /* PRESETOUT# */ 5767 { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */ 5768 { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */ 5769 { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */ 5770 { RCAR_GP_PIN(0, 3), 8, 3 }, /* D3 */ 5771 { RCAR_GP_PIN(0, 4), 4, 3 }, /* D4 */ 5772 { RCAR_GP_PIN(0, 5), 0, 3 }, /* D5 */ 5773 } }, 5774 { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) { 5775 { RCAR_GP_PIN(0, 6), 28, 3 }, /* D6 */ 5776 { RCAR_GP_PIN(0, 7), 24, 3 }, /* D7 */ 5777 { RCAR_GP_PIN(0, 8), 20, 3 }, /* D8 */ 5778 { RCAR_GP_PIN(0, 9), 16, 3 }, /* D9 */ 5779 { RCAR_GP_PIN(0, 10), 12, 3 }, /* D10 */ 5780 { RCAR_GP_PIN(0, 11), 8, 3 }, /* D11 */ 5781 { RCAR_GP_PIN(0, 12), 4, 3 }, /* D12 */ 5782 { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */ 5783 } }, 5784 { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) { 5785 { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */ 5786 { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */ 5787 { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */ 5788 { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */ 5789 { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */ 5790 { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */ 5791 { PIN_DU_DOTCLKIN0, 4, 2 }, /* DU_DOTCLKIN0 */ 5792 { PIN_DU_DOTCLKIN1, 0, 2 }, /* DU_DOTCLKIN1 */ 5793 } }, 5794 { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) { 5795 #ifdef CONFIG_PINCTRL_PFC_R8A77951 5796 { PIN_DU_DOTCLKIN2, 28, 2 }, /* DU_DOTCLKIN2 */ 5797 #endif 5798 { PIN_DU_DOTCLKIN3, 24, 2 }, /* DU_DOTCLKIN3 */ 5799 { PIN_FSCLKST_N, 20, 2 }, /* FSCLKST# */ 5800 { PIN_TMS, 4, 2 }, /* TMS */ 5801 } }, 5802 { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) { 5803 { PIN_TDO, 28, 2 }, /* TDO */ 5804 { PIN_ASEBRK, 24, 2 }, /* ASEBRK */ 5805 { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */ 5806 { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */ 5807 { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */ 5808 { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */ 5809 { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */ 5810 { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */ 5811 } }, 5812 { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) { 5813 { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */ 5814 { RCAR_GP_PIN(3, 7), 24, 3 }, /* SD1_CMD */ 5815 { RCAR_GP_PIN(3, 8), 20, 3 }, /* SD1_DAT0 */ 5816 { RCAR_GP_PIN(3, 9), 16, 3 }, /* SD1_DAT1 */ 5817 { RCAR_GP_PIN(3, 10), 12, 3 }, /* SD1_DAT2 */ 5818 { RCAR_GP_PIN(3, 11), 8, 3 }, /* SD1_DAT3 */ 5819 { RCAR_GP_PIN(4, 0), 4, 3 }, /* SD2_CLK */ 5820 { RCAR_GP_PIN(4, 1), 0, 3 }, /* SD2_CMD */ 5821 } }, 5822 { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) { 5823 { RCAR_GP_PIN(4, 2), 28, 3 }, /* SD2_DAT0 */ 5824 { RCAR_GP_PIN(4, 3), 24, 3 }, /* SD2_DAT1 */ 5825 { RCAR_GP_PIN(4, 4), 20, 3 }, /* SD2_DAT2 */ 5826 { RCAR_GP_PIN(4, 5), 16, 3 }, /* SD2_DAT3 */ 5827 { RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */ 5828 { RCAR_GP_PIN(4, 7), 8, 3 }, /* SD3_CLK */ 5829 { RCAR_GP_PIN(4, 8), 4, 3 }, /* SD3_CMD */ 5830 { RCAR_GP_PIN(4, 9), 0, 3 }, /* SD3_DAT0 */ 5831 } }, 5832 { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) { 5833 { RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */ 5834 { RCAR_GP_PIN(4, 11), 24, 3 }, /* SD3_DAT2 */ 5835 { RCAR_GP_PIN(4, 12), 20, 3 }, /* SD3_DAT3 */ 5836 { RCAR_GP_PIN(4, 13), 16, 3 }, /* SD3_DAT4 */ 5837 { RCAR_GP_PIN(4, 14), 12, 3 }, /* SD3_DAT5 */ 5838 { RCAR_GP_PIN(4, 15), 8, 3 }, /* SD3_DAT6 */ 5839 { RCAR_GP_PIN(4, 16), 4, 3 }, /* SD3_DAT7 */ 5840 { RCAR_GP_PIN(4, 17), 0, 3 }, /* SD3_DS */ 5841 } }, 5842 { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) { 5843 { RCAR_GP_PIN(3, 12), 28, 3 }, /* SD0_CD */ 5844 { RCAR_GP_PIN(3, 13), 24, 3 }, /* SD0_WP */ 5845 { RCAR_GP_PIN(3, 14), 20, 3 }, /* SD1_CD */ 5846 { RCAR_GP_PIN(3, 15), 16, 3 }, /* SD1_WP */ 5847 { RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */ 5848 { RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */ 5849 { RCAR_GP_PIN(5, 2), 4, 3 }, /* TX0 */ 5850 { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */ 5851 } }, 5852 { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) { 5853 { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0 */ 5854 { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */ 5855 { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */ 5856 { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */ 5857 { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1 */ 5858 { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */ 5859 { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */ 5860 { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */ 5861 } }, 5862 { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) { 5863 { RCAR_GP_PIN(5, 12), 28, 3 }, /* HSCK0 */ 5864 { RCAR_GP_PIN(5, 13), 24, 3 }, /* HRX0 */ 5865 { RCAR_GP_PIN(5, 14), 20, 3 }, /* HTX0 */ 5866 { RCAR_GP_PIN(5, 15), 16, 3 }, /* HCTS0 */ 5867 { RCAR_GP_PIN(5, 16), 12, 3 }, /* HRTS0 */ 5868 { RCAR_GP_PIN(5, 17), 8, 3 }, /* MSIOF0_SCK */ 5869 { RCAR_GP_PIN(5, 18), 4, 3 }, /* MSIOF0_SYNC */ 5870 { RCAR_GP_PIN(5, 19), 0, 3 }, /* MSIOF0_SS1 */ 5871 } }, 5872 { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) { 5873 { RCAR_GP_PIN(5, 20), 28, 3 }, /* MSIOF0_TXD */ 5874 { RCAR_GP_PIN(5, 21), 24, 3 }, /* MSIOF0_SS2 */ 5875 { RCAR_GP_PIN(5, 22), 20, 3 }, /* MSIOF0_RXD */ 5876 { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */ 5877 { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */ 5878 { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */ 5879 { PIN_MLB_REF, 4, 3 }, /* MLB_REF */ 5880 { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */ 5881 } }, 5882 { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) { 5883 { RCAR_GP_PIN(6, 1), 28, 3 }, /* SSI_WS01239 */ 5884 { RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */ 5885 { RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */ 5886 { RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */ 5887 { RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK349 */ 5888 { RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS349 */ 5889 { RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */ 5890 { RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */ 5891 } }, 5892 { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) { 5893 { RCAR_GP_PIN(6, 9), 28, 3 }, /* SSI_WS4 */ 5894 { RCAR_GP_PIN(6, 10), 24, 3 }, /* SSI_SDATA4 */ 5895 { RCAR_GP_PIN(6, 11), 20, 3 }, /* SSI_SCK5 */ 5896 { RCAR_GP_PIN(6, 12), 16, 3 }, /* SSI_WS5 */ 5897 { RCAR_GP_PIN(6, 13), 12, 3 }, /* SSI_SDATA5 */ 5898 { RCAR_GP_PIN(6, 14), 8, 3 }, /* SSI_SCK6 */ 5899 { RCAR_GP_PIN(6, 15), 4, 3 }, /* SSI_WS6 */ 5900 { RCAR_GP_PIN(6, 16), 0, 3 }, /* SSI_SDATA6 */ 5901 } }, 5902 { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) { 5903 { RCAR_GP_PIN(6, 17), 28, 3 }, /* SSI_SCK78 */ 5904 { RCAR_GP_PIN(6, 18), 24, 3 }, /* SSI_WS78 */ 5905 { RCAR_GP_PIN(6, 19), 20, 3 }, /* SSI_SDATA7 */ 5906 { RCAR_GP_PIN(6, 20), 16, 3 }, /* SSI_SDATA8 */ 5907 { RCAR_GP_PIN(6, 21), 12, 3 }, /* SSI_SDATA9 */ 5908 { RCAR_GP_PIN(6, 22), 8, 3 }, /* AUDIO_CLKA */ 5909 { RCAR_GP_PIN(6, 23), 4, 3 }, /* AUDIO_CLKB */ 5910 { RCAR_GP_PIN(6, 24), 0, 3 }, /* USB0_PWEN */ 5911 } }, 5912 { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) { 5913 { RCAR_GP_PIN(6, 25), 28, 3 }, /* USB0_OVC */ 5914 { RCAR_GP_PIN(6, 26), 24, 3 }, /* USB1_PWEN */ 5915 { RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */ 5916 { RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */ 5917 { RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */ 5918 { RCAR_GP_PIN(6, 30), 8, 3 }, /* GP6_30/USB2_CH3_PWEN */ 5919 { RCAR_GP_PIN(6, 31), 4, 3 }, /* GP6_31/USB2_CH3_OVC */ 5920 } }, 5921 { }, 5922 }; 5923 5924 enum ioctrl_regs { 5925 POCCTRL, 5926 TDSELCTRL, 5927 }; 5928 5929 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { 5930 [POCCTRL] = { 0xe6060380, }, 5931 [TDSELCTRL] = { 0xe60603c0, }, 5932 { /* sentinel */ }, 5933 }; 5934 5935 static int r8a77951_pin_to_pocctrl(struct sh_pfc *pfc, 5936 unsigned int pin, u32 *pocctrl) 5937 { 5938 int bit = -EINVAL; 5939 5940 *pocctrl = pinmux_ioctrl_regs[POCCTRL].reg; 5941 5942 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11)) 5943 bit = pin & 0x1f; 5944 5945 if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17)) 5946 bit = (pin & 0x1f) + 12; 5947 5948 return bit; 5949 } 5950 5951 static const struct pinmux_bias_reg pinmux_bias_regs[] = { 5952 { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) { 5953 [ 0] = PIN_QSPI0_SPCLK, /* QSPI0_SPCLK */ 5954 [ 1] = PIN_QSPI0_MOSI_IO0, /* QSPI0_MOSI_IO0 */ 5955 [ 2] = PIN_QSPI0_MISO_IO1, /* QSPI0_MISO_IO1 */ 5956 [ 3] = PIN_QSPI0_IO2, /* QSPI0_IO2 */ 5957 [ 4] = PIN_QSPI0_IO3, /* QSPI0_IO3 */ 5958 [ 5] = PIN_QSPI0_SSL, /* QSPI0_SSL */ 5959 [ 6] = PIN_QSPI1_SPCLK, /* QSPI1_SPCLK */ 5960 [ 7] = PIN_QSPI1_MOSI_IO0, /* QSPI1_MOSI_IO0 */ 5961 [ 8] = PIN_QSPI1_MISO_IO1, /* QSPI1_MISO_IO1 */ 5962 [ 9] = PIN_QSPI1_IO2, /* QSPI1_IO2 */ 5963 [10] = PIN_QSPI1_IO3, /* QSPI1_IO3 */ 5964 [11] = PIN_QSPI1_SSL, /* QSPI1_SSL */ 5965 [12] = PIN_RPC_INT_N, /* RPC_INT# */ 5966 [13] = PIN_RPC_WP_N, /* RPC_WP# */ 5967 [14] = PIN_RPC_RESET_N, /* RPC_RESET# */ 5968 [15] = PIN_AVB_RX_CTL, /* AVB_RX_CTL */ 5969 [16] = PIN_AVB_RXC, /* AVB_RXC */ 5970 [17] = PIN_AVB_RD0, /* AVB_RD0 */ 5971 [18] = PIN_AVB_RD1, /* AVB_RD1 */ 5972 [19] = PIN_AVB_RD2, /* AVB_RD2 */ 5973 [20] = PIN_AVB_RD3, /* AVB_RD3 */ 5974 [21] = PIN_AVB_TX_CTL, /* AVB_TX_CTL */ 5975 [22] = PIN_AVB_TXC, /* AVB_TXC */ 5976 [23] = PIN_AVB_TD0, /* AVB_TD0 */ 5977 [24] = PIN_AVB_TD1, /* AVB_TD1 */ 5978 [25] = PIN_AVB_TD2, /* AVB_TD2 */ 5979 [26] = PIN_AVB_TD3, /* AVB_TD3 */ 5980 [27] = PIN_AVB_TXCREFCLK, /* AVB_TXCREFCLK */ 5981 [28] = PIN_AVB_MDIO, /* AVB_MDIO */ 5982 [29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */ 5983 [30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */ 5984 [31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */ 5985 } }, 5986 { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) { 5987 [ 0] = RCAR_GP_PIN(2, 12), /* AVB_LINK */ 5988 [ 1] = RCAR_GP_PIN(2, 13), /* AVB_AVTP_MATCH_A */ 5989 [ 2] = RCAR_GP_PIN(2, 14), /* AVB_AVTP_CAPTURE_A */ 5990 [ 3] = RCAR_GP_PIN(2, 0), /* IRQ0 */ 5991 [ 4] = RCAR_GP_PIN(2, 1), /* IRQ1 */ 5992 [ 5] = RCAR_GP_PIN(2, 2), /* IRQ2 */ 5993 [ 6] = RCAR_GP_PIN(2, 3), /* IRQ3 */ 5994 [ 7] = RCAR_GP_PIN(2, 4), /* IRQ4 */ 5995 [ 8] = RCAR_GP_PIN(2, 5), /* IRQ5 */ 5996 [ 9] = RCAR_GP_PIN(2, 6), /* PWM0 */ 5997 [10] = RCAR_GP_PIN(2, 7), /* PWM1_A */ 5998 [11] = RCAR_GP_PIN(2, 8), /* PWM2_A */ 5999 [12] = RCAR_GP_PIN(1, 0), /* A0 */ 6000 [13] = RCAR_GP_PIN(1, 1), /* A1 */ 6001 [14] = RCAR_GP_PIN(1, 2), /* A2 */ 6002 [15] = RCAR_GP_PIN(1, 3), /* A3 */ 6003 [16] = RCAR_GP_PIN(1, 4), /* A4 */ 6004 [17] = RCAR_GP_PIN(1, 5), /* A5 */ 6005 [18] = RCAR_GP_PIN(1, 6), /* A6 */ 6006 [19] = RCAR_GP_PIN(1, 7), /* A7 */ 6007 [20] = RCAR_GP_PIN(1, 8), /* A8 */ 6008 [21] = RCAR_GP_PIN(1, 9), /* A9 */ 6009 [22] = RCAR_GP_PIN(1, 10), /* A10 */ 6010 [23] = RCAR_GP_PIN(1, 11), /* A11 */ 6011 [24] = RCAR_GP_PIN(1, 12), /* A12 */ 6012 [25] = RCAR_GP_PIN(1, 13), /* A13 */ 6013 [26] = RCAR_GP_PIN(1, 14), /* A14 */ 6014 [27] = RCAR_GP_PIN(1, 15), /* A15 */ 6015 [28] = RCAR_GP_PIN(1, 16), /* A16 */ 6016 [29] = RCAR_GP_PIN(1, 17), /* A17 */ 6017 [30] = RCAR_GP_PIN(1, 18), /* A18 */ 6018 [31] = RCAR_GP_PIN(1, 19), /* A19 */ 6019 } }, 6020 { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) { 6021 [ 0] = RCAR_GP_PIN(1, 28), /* CLKOUT */ 6022 [ 1] = RCAR_GP_PIN(1, 20), /* CS0_N */ 6023 [ 2] = RCAR_GP_PIN(1, 21), /* CS1_N */ 6024 [ 3] = RCAR_GP_PIN(1, 22), /* BS_N */ 6025 [ 4] = RCAR_GP_PIN(1, 23), /* RD_N */ 6026 [ 5] = RCAR_GP_PIN(1, 24), /* RD_WR_N */ 6027 [ 6] = RCAR_GP_PIN(1, 25), /* WE0_N */ 6028 [ 7] = RCAR_GP_PIN(1, 26), /* WE1_N */ 6029 [ 8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */ 6030 [ 9] = PIN_PRESETOUT_N, /* PRESETOUT# */ 6031 [10] = RCAR_GP_PIN(0, 0), /* D0 */ 6032 [11] = RCAR_GP_PIN(0, 1), /* D1 */ 6033 [12] = RCAR_GP_PIN(0, 2), /* D2 */ 6034 [13] = RCAR_GP_PIN(0, 3), /* D3 */ 6035 [14] = RCAR_GP_PIN(0, 4), /* D4 */ 6036 [15] = RCAR_GP_PIN(0, 5), /* D5 */ 6037 [16] = RCAR_GP_PIN(0, 6), /* D6 */ 6038 [17] = RCAR_GP_PIN(0, 7), /* D7 */ 6039 [18] = RCAR_GP_PIN(0, 8), /* D8 */ 6040 [19] = RCAR_GP_PIN(0, 9), /* D9 */ 6041 [20] = RCAR_GP_PIN(0, 10), /* D10 */ 6042 [21] = RCAR_GP_PIN(0, 11), /* D11 */ 6043 [22] = RCAR_GP_PIN(0, 12), /* D12 */ 6044 [23] = RCAR_GP_PIN(0, 13), /* D13 */ 6045 [24] = RCAR_GP_PIN(0, 14), /* D14 */ 6046 [25] = RCAR_GP_PIN(0, 15), /* D15 */ 6047 [26] = RCAR_GP_PIN(7, 0), /* AVS1 */ 6048 [27] = RCAR_GP_PIN(7, 1), /* AVS2 */ 6049 [28] = RCAR_GP_PIN(7, 2), /* GP7_02 */ 6050 [29] = RCAR_GP_PIN(7, 3), /* GP7_03 */ 6051 [30] = PIN_DU_DOTCLKIN0, /* DU_DOTCLKIN0 */ 6052 [31] = PIN_DU_DOTCLKIN1, /* DU_DOTCLKIN1 */ 6053 } }, 6054 { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) { 6055 [ 0] = PIN_DU_DOTCLKIN2, /* DU_DOTCLKIN2 */ 6056 [ 1] = PIN_DU_DOTCLKIN3, /* DU_DOTCLKIN3 */ 6057 [ 2] = PIN_FSCLKST_N, /* FSCLKST# */ 6058 [ 3] = PIN_EXTALR, /* EXTALR*/ 6059 [ 4] = PIN_TRST_N, /* TRST# */ 6060 [ 5] = PIN_TCK, /* TCK */ 6061 [ 6] = PIN_TMS, /* TMS */ 6062 [ 7] = PIN_TDI, /* TDI */ 6063 [ 8] = SH_PFC_PIN_NONE, 6064 [ 9] = PIN_ASEBRK, /* ASEBRK */ 6065 [10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */ 6066 [11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */ 6067 [12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */ 6068 [13] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */ 6069 [14] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */ 6070 [15] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */ 6071 [16] = RCAR_GP_PIN(3, 6), /* SD1_CLK */ 6072 [17] = RCAR_GP_PIN(3, 7), /* SD1_CMD */ 6073 [18] = RCAR_GP_PIN(3, 8), /* SD1_DAT0 */ 6074 [19] = RCAR_GP_PIN(3, 9), /* SD1_DAT1 */ 6075 [20] = RCAR_GP_PIN(3, 10), /* SD1_DAT2 */ 6076 [21] = RCAR_GP_PIN(3, 11), /* SD1_DAT3 */ 6077 [22] = RCAR_GP_PIN(4, 0), /* SD2_CLK */ 6078 [23] = RCAR_GP_PIN(4, 1), /* SD2_CMD */ 6079 [24] = RCAR_GP_PIN(4, 2), /* SD2_DAT0 */ 6080 [25] = RCAR_GP_PIN(4, 3), /* SD2_DAT1 */ 6081 [26] = RCAR_GP_PIN(4, 4), /* SD2_DAT2 */ 6082 [27] = RCAR_GP_PIN(4, 5), /* SD2_DAT3 */ 6083 [28] = RCAR_GP_PIN(4, 6), /* SD2_DS */ 6084 [29] = RCAR_GP_PIN(4, 7), /* SD3_CLK */ 6085 [30] = RCAR_GP_PIN(4, 8), /* SD3_CMD */ 6086 [31] = RCAR_GP_PIN(4, 9), /* SD3_DAT0 */ 6087 } }, 6088 { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) { 6089 [ 0] = RCAR_GP_PIN(4, 10), /* SD3_DAT1 */ 6090 [ 1] = RCAR_GP_PIN(4, 11), /* SD3_DAT2 */ 6091 [ 2] = RCAR_GP_PIN(4, 12), /* SD3_DAT3 */ 6092 [ 3] = RCAR_GP_PIN(4, 13), /* SD3_DAT4 */ 6093 [ 4] = RCAR_GP_PIN(4, 14), /* SD3_DAT5 */ 6094 [ 5] = RCAR_GP_PIN(4, 15), /* SD3_DAT6 */ 6095 [ 6] = RCAR_GP_PIN(4, 16), /* SD3_DAT7 */ 6096 [ 7] = RCAR_GP_PIN(4, 17), /* SD3_DS */ 6097 [ 8] = RCAR_GP_PIN(3, 12), /* SD0_CD */ 6098 [ 9] = RCAR_GP_PIN(3, 13), /* SD0_WP */ 6099 [10] = RCAR_GP_PIN(3, 14), /* SD1_CD */ 6100 [11] = RCAR_GP_PIN(3, 15), /* SD1_WP */ 6101 [12] = RCAR_GP_PIN(5, 0), /* SCK0 */ 6102 [13] = RCAR_GP_PIN(5, 1), /* RX0 */ 6103 [14] = RCAR_GP_PIN(5, 2), /* TX0 */ 6104 [15] = RCAR_GP_PIN(5, 3), /* CTS0_N */ 6105 [16] = RCAR_GP_PIN(5, 4), /* RTS0_N */ 6106 [17] = RCAR_GP_PIN(5, 5), /* RX1_A */ 6107 [18] = RCAR_GP_PIN(5, 6), /* TX1_A */ 6108 [19] = RCAR_GP_PIN(5, 7), /* CTS1_N */ 6109 [20] = RCAR_GP_PIN(5, 8), /* RTS1_N */ 6110 [21] = RCAR_GP_PIN(5, 9), /* SCK2 */ 6111 [22] = RCAR_GP_PIN(5, 10), /* TX2_A */ 6112 [23] = RCAR_GP_PIN(5, 11), /* RX2_A */ 6113 [24] = RCAR_GP_PIN(5, 12), /* HSCK0 */ 6114 [25] = RCAR_GP_PIN(5, 13), /* HRX0 */ 6115 [26] = RCAR_GP_PIN(5, 14), /* HTX0 */ 6116 [27] = RCAR_GP_PIN(5, 15), /* HCTS0_N */ 6117 [28] = RCAR_GP_PIN(5, 16), /* HRTS0_N */ 6118 [29] = RCAR_GP_PIN(5, 17), /* MSIOF0_SCK */ 6119 [30] = RCAR_GP_PIN(5, 18), /* MSIOF0_SYNC */ 6120 [31] = RCAR_GP_PIN(5, 19), /* MSIOF0_SS1 */ 6121 } }, 6122 { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) { 6123 [ 0] = RCAR_GP_PIN(5, 20), /* MSIOF0_TXD */ 6124 [ 1] = RCAR_GP_PIN(5, 21), /* MSIOF0_SS2 */ 6125 [ 2] = RCAR_GP_PIN(5, 22), /* MSIOF0_RXD */ 6126 [ 3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */ 6127 [ 4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */ 6128 [ 5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */ 6129 [ 6] = PIN_MLB_REF, /* MLB_REF */ 6130 [ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */ 6131 [ 8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */ 6132 [ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */ 6133 [10] = RCAR_GP_PIN(6, 3), /* SSI_SDATA1_A */ 6134 [11] = RCAR_GP_PIN(6, 4), /* SSI_SDATA2_A */ 6135 [12] = RCAR_GP_PIN(6, 5), /* SSI_SCK349 */ 6136 [13] = RCAR_GP_PIN(6, 6), /* SSI_WS349 */ 6137 [14] = RCAR_GP_PIN(6, 7), /* SSI_SDATA3 */ 6138 [15] = RCAR_GP_PIN(6, 8), /* SSI_SCK4 */ 6139 [16] = RCAR_GP_PIN(6, 9), /* SSI_WS4 */ 6140 [17] = RCAR_GP_PIN(6, 10), /* SSI_SDATA4 */ 6141 [18] = RCAR_GP_PIN(6, 11), /* SSI_SCK5 */ 6142 [19] = RCAR_GP_PIN(6, 12), /* SSI_WS5 */ 6143 [20] = RCAR_GP_PIN(6, 13), /* SSI_SDATA5 */ 6144 [21] = RCAR_GP_PIN(6, 14), /* SSI_SCK6 */ 6145 [22] = RCAR_GP_PIN(6, 15), /* SSI_WS6 */ 6146 [23] = RCAR_GP_PIN(6, 16), /* SSI_SDATA6 */ 6147 [24] = RCAR_GP_PIN(6, 17), /* SSI_SCK78 */ 6148 [25] = RCAR_GP_PIN(6, 18), /* SSI_WS78 */ 6149 [26] = RCAR_GP_PIN(6, 19), /* SSI_SDATA7 */ 6150 [27] = RCAR_GP_PIN(6, 20), /* SSI_SDATA8 */ 6151 [28] = RCAR_GP_PIN(6, 21), /* SSI_SDATA9_A */ 6152 [29] = RCAR_GP_PIN(6, 22), /* AUDIO_CLKA_A */ 6153 [30] = RCAR_GP_PIN(6, 23), /* AUDIO_CLKB_B */ 6154 [31] = RCAR_GP_PIN(6, 24), /* USB0_PWEN */ 6155 } }, 6156 { PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) { 6157 [ 0] = RCAR_GP_PIN(6, 25), /* USB0_OVC */ 6158 [ 1] = RCAR_GP_PIN(6, 26), /* USB1_PWEN */ 6159 [ 2] = RCAR_GP_PIN(6, 27), /* USB1_OVC */ 6160 [ 3] = RCAR_GP_PIN(6, 28), /* USB30_PWEN */ 6161 [ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */ 6162 [ 5] = RCAR_GP_PIN(6, 30), /* USB2_CH3_PWEN */ 6163 [ 6] = RCAR_GP_PIN(6, 31), /* USB2_CH3_OVC */ 6164 [ 7] = SH_PFC_PIN_NONE, 6165 [ 8] = SH_PFC_PIN_NONE, 6166 [ 9] = SH_PFC_PIN_NONE, 6167 [10] = SH_PFC_PIN_NONE, 6168 [11] = SH_PFC_PIN_NONE, 6169 [12] = SH_PFC_PIN_NONE, 6170 [13] = SH_PFC_PIN_NONE, 6171 [14] = SH_PFC_PIN_NONE, 6172 [15] = SH_PFC_PIN_NONE, 6173 [16] = SH_PFC_PIN_NONE, 6174 [17] = SH_PFC_PIN_NONE, 6175 [18] = SH_PFC_PIN_NONE, 6176 [19] = SH_PFC_PIN_NONE, 6177 [20] = SH_PFC_PIN_NONE, 6178 [21] = SH_PFC_PIN_NONE, 6179 [22] = SH_PFC_PIN_NONE, 6180 [23] = SH_PFC_PIN_NONE, 6181 [24] = SH_PFC_PIN_NONE, 6182 [25] = SH_PFC_PIN_NONE, 6183 [26] = SH_PFC_PIN_NONE, 6184 [27] = SH_PFC_PIN_NONE, 6185 [28] = SH_PFC_PIN_NONE, 6186 [29] = SH_PFC_PIN_NONE, 6187 [30] = SH_PFC_PIN_NONE, 6188 [31] = SH_PFC_PIN_NONE, 6189 } }, 6190 { /* sentinel */ }, 6191 }; 6192 6193 static unsigned int r8a77951_pinmux_get_bias(struct sh_pfc *pfc, 6194 unsigned int pin) 6195 { 6196 const struct pinmux_bias_reg *reg; 6197 unsigned int bit; 6198 6199 reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit); 6200 if (!reg) 6201 return PIN_CONFIG_BIAS_DISABLE; 6202 6203 if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit))) 6204 return PIN_CONFIG_BIAS_DISABLE; 6205 else if (sh_pfc_read(pfc, reg->pud) & BIT(bit)) 6206 return PIN_CONFIG_BIAS_PULL_UP; 6207 else 6208 return PIN_CONFIG_BIAS_PULL_DOWN; 6209 } 6210 6211 static void r8a77951_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, 6212 unsigned int bias) 6213 { 6214 const struct pinmux_bias_reg *reg; 6215 u32 enable, updown; 6216 unsigned int bit; 6217 6218 reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit); 6219 if (!reg) 6220 return; 6221 6222 enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit); 6223 if (bias != PIN_CONFIG_BIAS_DISABLE) 6224 enable |= BIT(bit); 6225 6226 updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit); 6227 if (bias == PIN_CONFIG_BIAS_PULL_UP) 6228 updown |= BIT(bit); 6229 6230 sh_pfc_write(pfc, reg->pud, updown); 6231 sh_pfc_write(pfc, reg->puen, enable); 6232 } 6233 6234 static const struct sh_pfc_soc_operations r8a77951_pinmux_ops = { 6235 .pin_to_pocctrl = r8a77951_pin_to_pocctrl, 6236 .get_bias = r8a77951_pinmux_get_bias, 6237 .set_bias = r8a77951_pinmux_set_bias, 6238 }; 6239 6240 #ifdef CONFIG_PINCTRL_PFC_R8A774E1 6241 const struct sh_pfc_soc_info r8a774e1_pinmux_info = { 6242 .name = "r8a774e1_pfc", 6243 .ops = &r8a77951_pinmux_ops, 6244 .unlock_reg = 0xe6060000, /* PMMR */ 6245 6246 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 6247 6248 .pins = pinmux_pins, 6249 .nr_pins = ARRAY_SIZE(pinmux_pins), 6250 .groups = pinmux_groups.common, 6251 .nr_groups = ARRAY_SIZE(pinmux_groups.common), 6252 .functions = pinmux_functions.common, 6253 .nr_functions = ARRAY_SIZE(pinmux_functions.common), 6254 6255 .cfg_regs = pinmux_config_regs, 6256 .drive_regs = pinmux_drive_regs, 6257 .bias_regs = pinmux_bias_regs, 6258 .ioctrl_regs = pinmux_ioctrl_regs, 6259 6260 .pinmux_data = pinmux_data, 6261 .pinmux_data_size = ARRAY_SIZE(pinmux_data), 6262 }; 6263 #endif 6264 6265 #ifdef CONFIG_PINCTRL_PFC_R8A77951 6266 const struct sh_pfc_soc_info r8a77951_pinmux_info = { 6267 .name = "r8a77951_pfc", 6268 .ops = &r8a77951_pinmux_ops, 6269 .unlock_reg = 0xe6060000, /* PMMR */ 6270 6271 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 6272 6273 .pins = pinmux_pins, 6274 .nr_pins = ARRAY_SIZE(pinmux_pins), 6275 .groups = pinmux_groups.common, 6276 .nr_groups = ARRAY_SIZE(pinmux_groups.common) + 6277 ARRAY_SIZE(pinmux_groups.automotive), 6278 .functions = pinmux_functions.common, 6279 .nr_functions = ARRAY_SIZE(pinmux_functions.common) + 6280 ARRAY_SIZE(pinmux_functions.automotive), 6281 6282 .cfg_regs = pinmux_config_regs, 6283 .drive_regs = pinmux_drive_regs, 6284 .bias_regs = pinmux_bias_regs, 6285 .ioctrl_regs = pinmux_ioctrl_regs, 6286 6287 .pinmux_data = pinmux_data, 6288 .pinmux_data_size = ARRAY_SIZE(pinmux_data), 6289 }; 6290 #endif 6291