1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * R8A77951 processor support - PFC hardware block. 4 * 5 * Copyright (C) 2015-2019 Renesas Electronics Corporation 6 */ 7 8 #include <linux/errno.h> 9 #include <linux/kernel.h> 10 #include <linux/sys_soc.h> 11 12 #include "core.h" 13 #include "sh_pfc.h" 14 15 #define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN) 16 17 #define CPU_ALL_GP(fn, sfx) \ 18 PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \ 19 PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \ 20 PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \ 21 PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \ 22 PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \ 23 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \ 24 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \ 25 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \ 26 PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \ 27 PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \ 28 PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \ 29 PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS) 30 31 #define CPU_ALL_NOGP(fn) \ 32 PIN_NOGP_CFG(ASEBRK, "ASEBRK", fn, CFG_FLAGS), \ 33 PIN_NOGP_CFG(AVB_MDIO, "AVB_MDIO", fn, CFG_FLAGS), \ 34 PIN_NOGP_CFG(AVB_RD0, "AVB_RD0", fn, CFG_FLAGS), \ 35 PIN_NOGP_CFG(AVB_RD1, "AVB_RD1", fn, CFG_FLAGS), \ 36 PIN_NOGP_CFG(AVB_RD2, "AVB_RD2", fn, CFG_FLAGS), \ 37 PIN_NOGP_CFG(AVB_RD3, "AVB_RD3", fn, CFG_FLAGS), \ 38 PIN_NOGP_CFG(AVB_RXC, "AVB_RXC", fn, CFG_FLAGS), \ 39 PIN_NOGP_CFG(AVB_RX_CTL, "AVB_RX_CTL", fn, CFG_FLAGS), \ 40 PIN_NOGP_CFG(AVB_TD0, "AVB_TD0", fn, CFG_FLAGS), \ 41 PIN_NOGP_CFG(AVB_TD1, "AVB_TD1", fn, CFG_FLAGS), \ 42 PIN_NOGP_CFG(AVB_TD2, "AVB_TD2", fn, CFG_FLAGS), \ 43 PIN_NOGP_CFG(AVB_TD3, "AVB_TD3", fn, CFG_FLAGS), \ 44 PIN_NOGP_CFG(AVB_TXC, "AVB_TXC", fn, CFG_FLAGS), \ 45 PIN_NOGP_CFG(AVB_TXCREFCLK, "AVB_TXCREFCLK", fn, CFG_FLAGS), \ 46 PIN_NOGP_CFG(AVB_TX_CTL, "AVB_TX_CTL", fn, CFG_FLAGS), \ 47 PIN_NOGP_CFG(DU_DOTCLKIN0, "DU_DOTCLKIN0", fn, CFG_FLAGS), \ 48 PIN_NOGP_CFG(DU_DOTCLKIN1, "DU_DOTCLKIN1", fn, CFG_FLAGS), \ 49 PIN_NOGP_CFG(DU_DOTCLKIN2, "DU_DOTCLKIN2", fn, CFG_FLAGS), \ 50 PIN_NOGP_CFG(DU_DOTCLKIN3, "DU_DOTCLKIN3", fn, CFG_FLAGS), \ 51 PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),\ 52 PIN_NOGP_CFG(FSCLKST_N, "FSCLKST#", fn, CFG_FLAGS), \ 53 PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS), \ 54 PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, CFG_FLAGS), \ 55 PIN_NOGP_CFG(QSPI0_IO2, "QSPI0_IO2", fn, CFG_FLAGS), \ 56 PIN_NOGP_CFG(QSPI0_IO3, "QSPI0_IO3", fn, CFG_FLAGS), \ 57 PIN_NOGP_CFG(QSPI0_MISO_IO1, "QSPI0_MISO_IO1", fn, CFG_FLAGS), \ 58 PIN_NOGP_CFG(QSPI0_MOSI_IO0, "QSPI0_MOSI_IO0", fn, CFG_FLAGS), \ 59 PIN_NOGP_CFG(QSPI0_SPCLK, "QSPI0_SPCLK", fn, CFG_FLAGS), \ 60 PIN_NOGP_CFG(QSPI0_SSL, "QSPI0_SSL", fn, CFG_FLAGS), \ 61 PIN_NOGP_CFG(QSPI1_IO2, "QSPI1_IO2", fn, CFG_FLAGS), \ 62 PIN_NOGP_CFG(QSPI1_IO3, "QSPI1_IO3", fn, CFG_FLAGS), \ 63 PIN_NOGP_CFG(QSPI1_MISO_IO1, "QSPI1_MISO_IO1", fn, CFG_FLAGS), \ 64 PIN_NOGP_CFG(QSPI1_MOSI_IO0, "QSPI1_MOSI_IO0", fn, CFG_FLAGS), \ 65 PIN_NOGP_CFG(QSPI1_SPCLK, "QSPI1_SPCLK", fn, CFG_FLAGS), \ 66 PIN_NOGP_CFG(QSPI1_SSL, "QSPI1_SSL", fn, CFG_FLAGS), \ 67 PIN_NOGP_CFG(RPC_INT_N, "RPC_INT#", fn, CFG_FLAGS), \ 68 PIN_NOGP_CFG(RPC_RESET_N, "RPC_RESET#", fn, CFG_FLAGS), \ 69 PIN_NOGP_CFG(RPC_WP_N, "RPC_WP#", fn, CFG_FLAGS), \ 70 PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ 71 PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ 72 PIN_NOGP_CFG(TDO, "TDO", fn, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \ 73 PIN_NOGP_CFG(TMS, "TMS", fn, CFG_FLAGS), \ 74 PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN) 75 76 /* 77 * F_() : just information 78 * FM() : macro for FN_xxx / xxx_MARK 79 */ 80 81 /* GPSR0 */ 82 #define GPSR0_15 F_(D15, IP7_11_8) 83 #define GPSR0_14 F_(D14, IP7_7_4) 84 #define GPSR0_13 F_(D13, IP7_3_0) 85 #define GPSR0_12 F_(D12, IP6_31_28) 86 #define GPSR0_11 F_(D11, IP6_27_24) 87 #define GPSR0_10 F_(D10, IP6_23_20) 88 #define GPSR0_9 F_(D9, IP6_19_16) 89 #define GPSR0_8 F_(D8, IP6_15_12) 90 #define GPSR0_7 F_(D7, IP6_11_8) 91 #define GPSR0_6 F_(D6, IP6_7_4) 92 #define GPSR0_5 F_(D5, IP6_3_0) 93 #define GPSR0_4 F_(D4, IP5_31_28) 94 #define GPSR0_3 F_(D3, IP5_27_24) 95 #define GPSR0_2 F_(D2, IP5_23_20) 96 #define GPSR0_1 F_(D1, IP5_19_16) 97 #define GPSR0_0 F_(D0, IP5_15_12) 98 99 /* GPSR1 */ 100 #define GPSR1_28 FM(CLKOUT) 101 #define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8) 102 #define GPSR1_26 F_(WE1_N, IP5_7_4) 103 #define GPSR1_25 F_(WE0_N, IP5_3_0) 104 #define GPSR1_24 F_(RD_WR_N, IP4_31_28) 105 #define GPSR1_23 F_(RD_N, IP4_27_24) 106 #define GPSR1_22 F_(BS_N, IP4_23_20) 107 #define GPSR1_21 F_(CS1_N, IP4_19_16) 108 #define GPSR1_20 F_(CS0_N, IP4_15_12) 109 #define GPSR1_19 F_(A19, IP4_11_8) 110 #define GPSR1_18 F_(A18, IP4_7_4) 111 #define GPSR1_17 F_(A17, IP4_3_0) 112 #define GPSR1_16 F_(A16, IP3_31_28) 113 #define GPSR1_15 F_(A15, IP3_27_24) 114 #define GPSR1_14 F_(A14, IP3_23_20) 115 #define GPSR1_13 F_(A13, IP3_19_16) 116 #define GPSR1_12 F_(A12, IP3_15_12) 117 #define GPSR1_11 F_(A11, IP3_11_8) 118 #define GPSR1_10 F_(A10, IP3_7_4) 119 #define GPSR1_9 F_(A9, IP3_3_0) 120 #define GPSR1_8 F_(A8, IP2_31_28) 121 #define GPSR1_7 F_(A7, IP2_27_24) 122 #define GPSR1_6 F_(A6, IP2_23_20) 123 #define GPSR1_5 F_(A5, IP2_19_16) 124 #define GPSR1_4 F_(A4, IP2_15_12) 125 #define GPSR1_3 F_(A3, IP2_11_8) 126 #define GPSR1_2 F_(A2, IP2_7_4) 127 #define GPSR1_1 F_(A1, IP2_3_0) 128 #define GPSR1_0 F_(A0, IP1_31_28) 129 130 /* GPSR2 */ 131 #define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20) 132 #define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16) 133 #define GPSR2_12 F_(AVB_LINK, IP0_15_12) 134 #define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8) 135 #define GPSR2_10 F_(AVB_MAGIC, IP0_7_4) 136 #define GPSR2_9 F_(AVB_MDC, IP0_3_0) 137 #define GPSR2_8 F_(PWM2_A, IP1_27_24) 138 #define GPSR2_7 F_(PWM1_A, IP1_23_20) 139 #define GPSR2_6 F_(PWM0, IP1_19_16) 140 #define GPSR2_5 F_(IRQ5, IP1_15_12) 141 #define GPSR2_4 F_(IRQ4, IP1_11_8) 142 #define GPSR2_3 F_(IRQ3, IP1_7_4) 143 #define GPSR2_2 F_(IRQ2, IP1_3_0) 144 #define GPSR2_1 F_(IRQ1, IP0_31_28) 145 #define GPSR2_0 F_(IRQ0, IP0_27_24) 146 147 /* GPSR3 */ 148 #define GPSR3_15 F_(SD1_WP, IP11_23_20) 149 #define GPSR3_14 F_(SD1_CD, IP11_19_16) 150 #define GPSR3_13 F_(SD0_WP, IP11_15_12) 151 #define GPSR3_12 F_(SD0_CD, IP11_11_8) 152 #define GPSR3_11 F_(SD1_DAT3, IP8_31_28) 153 #define GPSR3_10 F_(SD1_DAT2, IP8_27_24) 154 #define GPSR3_9 F_(SD1_DAT1, IP8_23_20) 155 #define GPSR3_8 F_(SD1_DAT0, IP8_19_16) 156 #define GPSR3_7 F_(SD1_CMD, IP8_15_12) 157 #define GPSR3_6 F_(SD1_CLK, IP8_11_8) 158 #define GPSR3_5 F_(SD0_DAT3, IP8_7_4) 159 #define GPSR3_4 F_(SD0_DAT2, IP8_3_0) 160 #define GPSR3_3 F_(SD0_DAT1, IP7_31_28) 161 #define GPSR3_2 F_(SD0_DAT0, IP7_27_24) 162 #define GPSR3_1 F_(SD0_CMD, IP7_23_20) 163 #define GPSR3_0 F_(SD0_CLK, IP7_19_16) 164 165 /* GPSR4 */ 166 #define GPSR4_17 F_(SD3_DS, IP11_7_4) 167 #define GPSR4_16 F_(SD3_DAT7, IP11_3_0) 168 #define GPSR4_15 F_(SD3_DAT6, IP10_31_28) 169 #define GPSR4_14 F_(SD3_DAT5, IP10_27_24) 170 #define GPSR4_13 F_(SD3_DAT4, IP10_23_20) 171 #define GPSR4_12 F_(SD3_DAT3, IP10_19_16) 172 #define GPSR4_11 F_(SD3_DAT2, IP10_15_12) 173 #define GPSR4_10 F_(SD3_DAT1, IP10_11_8) 174 #define GPSR4_9 F_(SD3_DAT0, IP10_7_4) 175 #define GPSR4_8 F_(SD3_CMD, IP10_3_0) 176 #define GPSR4_7 F_(SD3_CLK, IP9_31_28) 177 #define GPSR4_6 F_(SD2_DS, IP9_27_24) 178 #define GPSR4_5 F_(SD2_DAT3, IP9_23_20) 179 #define GPSR4_4 F_(SD2_DAT2, IP9_19_16) 180 #define GPSR4_3 F_(SD2_DAT1, IP9_15_12) 181 #define GPSR4_2 F_(SD2_DAT0, IP9_11_8) 182 #define GPSR4_1 F_(SD2_CMD, IP9_7_4) 183 #define GPSR4_0 F_(SD2_CLK, IP9_3_0) 184 185 /* GPSR5 */ 186 #define GPSR5_25 F_(MLB_DAT, IP14_19_16) 187 #define GPSR5_24 F_(MLB_SIG, IP14_15_12) 188 #define GPSR5_23 F_(MLB_CLK, IP14_11_8) 189 #define GPSR5_22 FM(MSIOF0_RXD) 190 #define GPSR5_21 F_(MSIOF0_SS2, IP14_7_4) 191 #define GPSR5_20 FM(MSIOF0_TXD) 192 #define GPSR5_19 F_(MSIOF0_SS1, IP14_3_0) 193 #define GPSR5_18 F_(MSIOF0_SYNC, IP13_31_28) 194 #define GPSR5_17 FM(MSIOF0_SCK) 195 #define GPSR5_16 F_(HRTS0_N, IP13_27_24) 196 #define GPSR5_15 F_(HCTS0_N, IP13_23_20) 197 #define GPSR5_14 F_(HTX0, IP13_19_16) 198 #define GPSR5_13 F_(HRX0, IP13_15_12) 199 #define GPSR5_12 F_(HSCK0, IP13_11_8) 200 #define GPSR5_11 F_(RX2_A, IP13_7_4) 201 #define GPSR5_10 F_(TX2_A, IP13_3_0) 202 #define GPSR5_9 F_(SCK2, IP12_31_28) 203 #define GPSR5_8 F_(RTS1_N, IP12_27_24) 204 #define GPSR5_7 F_(CTS1_N, IP12_23_20) 205 #define GPSR5_6 F_(TX1_A, IP12_19_16) 206 #define GPSR5_5 F_(RX1_A, IP12_15_12) 207 #define GPSR5_4 F_(RTS0_N, IP12_11_8) 208 #define GPSR5_3 F_(CTS0_N, IP12_7_4) 209 #define GPSR5_2 F_(TX0, IP12_3_0) 210 #define GPSR5_1 F_(RX0, IP11_31_28) 211 #define GPSR5_0 F_(SCK0, IP11_27_24) 212 213 /* GPSR6 */ 214 #define GPSR6_31 F_(USB2_CH3_OVC, IP18_7_4) 215 #define GPSR6_30 F_(USB2_CH3_PWEN, IP18_3_0) 216 #define GPSR6_29 F_(USB30_OVC, IP17_31_28) 217 #define GPSR6_28 F_(USB30_PWEN, IP17_27_24) 218 #define GPSR6_27 F_(USB1_OVC, IP17_23_20) 219 #define GPSR6_26 F_(USB1_PWEN, IP17_19_16) 220 #define GPSR6_25 F_(USB0_OVC, IP17_15_12) 221 #define GPSR6_24 F_(USB0_PWEN, IP17_11_8) 222 #define GPSR6_23 F_(AUDIO_CLKB_B, IP17_7_4) 223 #define GPSR6_22 F_(AUDIO_CLKA_A, IP17_3_0) 224 #define GPSR6_21 F_(SSI_SDATA9_A, IP16_31_28) 225 #define GPSR6_20 F_(SSI_SDATA8, IP16_27_24) 226 #define GPSR6_19 F_(SSI_SDATA7, IP16_23_20) 227 #define GPSR6_18 F_(SSI_WS78, IP16_19_16) 228 #define GPSR6_17 F_(SSI_SCK78, IP16_15_12) 229 #define GPSR6_16 F_(SSI_SDATA6, IP16_11_8) 230 #define GPSR6_15 F_(SSI_WS6, IP16_7_4) 231 #define GPSR6_14 F_(SSI_SCK6, IP16_3_0) 232 #define GPSR6_13 FM(SSI_SDATA5) 233 #define GPSR6_12 FM(SSI_WS5) 234 #define GPSR6_11 FM(SSI_SCK5) 235 #define GPSR6_10 F_(SSI_SDATA4, IP15_31_28) 236 #define GPSR6_9 F_(SSI_WS4, IP15_27_24) 237 #define GPSR6_8 F_(SSI_SCK4, IP15_23_20) 238 #define GPSR6_7 F_(SSI_SDATA3, IP15_19_16) 239 #define GPSR6_6 F_(SSI_WS349, IP15_15_12) 240 #define GPSR6_5 F_(SSI_SCK349, IP15_11_8) 241 #define GPSR6_4 F_(SSI_SDATA2_A, IP15_7_4) 242 #define GPSR6_3 F_(SSI_SDATA1_A, IP15_3_0) 243 #define GPSR6_2 F_(SSI_SDATA0, IP14_31_28) 244 #define GPSR6_1 F_(SSI_WS01239, IP14_27_24) 245 #define GPSR6_0 F_(SSI_SCK01239, IP14_23_20) 246 247 /* GPSR7 */ 248 #define GPSR7_3 FM(GP7_03) 249 #define GPSR7_2 FM(GP7_02) 250 #define GPSR7_1 FM(AVS2) 251 #define GPSR7_0 FM(AVS1) 252 253 254 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ 255 #define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 256 #define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 257 #define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 258 #define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 259 #define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) FM(FSCLKST2_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 260 #define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 261 #define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 262 #define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 263 #define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 264 #define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) F_(0, 0) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 265 #define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) F_(0, 0) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 266 #define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) F_(0, 0) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) FM(FSCLKST2_N_B) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 267 #define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)F_(0, 0) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 268 #define IP1_23_20 FM(PWM1_A) F_(0, 0) F_(0, 0) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 269 #define IP1_27_24 FM(PWM2_A) F_(0, 0) F_(0, 0) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 270 #define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 271 #define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 272 #define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 273 #define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 274 275 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ 276 #define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 277 #define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 278 #define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 279 #define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 280 #define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 281 #define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 282 #define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 283 #define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 284 #define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 285 #define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 286 #define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 287 #define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 288 #define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 289 #define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 290 #define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 291 #define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 292 #define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 293 #define IP4_19_16 FM(CS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 294 #define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 295 #define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 296 #define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 297 #define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 298 #define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 299 #define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 300 #define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 301 #define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 302 #define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 303 #define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 304 #define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 305 #define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 306 #define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 307 #define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 308 #define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 309 #define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 310 #define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 311 #define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_C) FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 312 #define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 313 #define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 314 #define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 315 #define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 316 #define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 317 318 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ 319 #define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 320 #define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 321 #define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 322 #define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 323 #define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 324 #define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 325 #define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) FM(NFCE_N_B) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 326 #define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) FM(NFWP_N_B) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 327 #define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) FM(NFDATA14_B) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 328 #define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) FM(NFDATA15_B) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 329 #define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) FM(NFRB_N_B) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 330 #define IP9_3_0 FM(SD2_CLK) F_(0, 0) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 331 #define IP9_7_4 FM(SD2_CMD) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 332 #define IP9_11_8 FM(SD2_DAT0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 333 #define IP9_15_12 FM(SD2_DAT1) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 334 #define IP9_19_16 FM(SD2_DAT2) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 335 #define IP9_23_20 FM(SD2_DAT3) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 336 #define IP9_27_24 FM(SD2_DS) F_(0, 0) FM(NFALE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 337 #define IP9_31_28 FM(SD3_CLK) F_(0, 0) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 338 #define IP10_3_0 FM(SD3_CMD) F_(0, 0) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 339 #define IP10_7_4 FM(SD3_DAT0) F_(0, 0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 340 #define IP10_11_8 FM(SD3_DAT1) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 341 #define IP10_15_12 FM(SD3_DAT2) F_(0, 0) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 342 #define IP10_19_16 FM(SD3_DAT3) F_(0, 0) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 343 #define IP10_23_20 FM(SD3_DAT4) FM(SD2_CD_A) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 344 #define IP10_27_24 FM(SD3_DAT5) FM(SD2_WP_A) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 345 #define IP10_31_28 FM(SD3_DAT6) FM(SD3_CD) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 346 #define IP11_3_0 FM(SD3_DAT7) FM(SD3_WP) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 347 #define IP11_7_4 FM(SD3_DS) F_(0, 0) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 348 #define IP11_11_8 FM(SD0_CD) F_(0, 0) FM(NFDATA14_A) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 349 350 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ 351 #define IP11_15_12 FM(SD0_WP) F_(0, 0) FM(NFDATA15_A) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 352 #define IP11_19_16 FM(SD1_CD) F_(0, 0) FM(NFRB_N_A) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 353 #define IP11_23_20 FM(SD1_WP) F_(0, 0) FM(NFCE_N_A) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 354 #define IP11_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 355 #define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 356 #define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 357 #define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 358 #define IP12_11_8 FM(RTS0_N) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 359 #define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 360 #define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 361 #define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 362 #define IP12_27_24 FM(RTS1_N) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 363 #define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 364 #define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 365 #define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 366 #define IP13_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 367 #define IP13_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 368 #define IP13_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 369 #define IP13_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 370 #define IP13_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 371 #define IP13_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) FM(TX5_B) F_(0, 0) F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0) 372 #define IP14_3_0 FM(MSIOF0_SS1) FM(RX5_A) FM(NFWP_N_A) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 373 #define IP14_7_4 FM(MSIOF0_SS2) FM(TX5_A) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 374 #define IP14_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 375 #define IP14_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 376 #define IP14_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 377 #define IP14_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 378 #define IP14_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 379 380 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ 381 #define IP14_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 382 #define IP15_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 383 #define IP15_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 384 #define IP15_11_8 FM(SSI_SCK349) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 385 #define IP15_15_12 FM(SSI_WS349) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 386 #define IP15_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 387 #define IP15_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 388 #define IP15_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 389 #define IP15_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 390 #define IP16_3_0 FM(SSI_SCK6) FM(USB2_PWEN) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 391 #define IP16_7_4 FM(SSI_WS6) FM(USB2_OVC) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 392 #define IP16_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 393 #define IP16_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 394 #define IP16_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 395 #define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 396 #define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 397 #define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 398 #define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 399 #define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 400 #define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0) 401 #define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0) 402 #define IP17_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0) 403 #define IP17_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0) 404 #define IP17_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0) 405 #define IP17_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_N) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 406 #define IP18_3_0 FM(USB2_CH3_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0) 407 #define IP18_7_4 FM(USB2_CH3_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0) 408 409 #define PINMUX_GPSR \ 410 \ 411 GPSR6_31 \ 412 GPSR6_30 \ 413 GPSR6_29 \ 414 GPSR1_28 GPSR6_28 \ 415 GPSR1_27 GPSR6_27 \ 416 GPSR1_26 GPSR6_26 \ 417 GPSR1_25 GPSR5_25 GPSR6_25 \ 418 GPSR1_24 GPSR5_24 GPSR6_24 \ 419 GPSR1_23 GPSR5_23 GPSR6_23 \ 420 GPSR1_22 GPSR5_22 GPSR6_22 \ 421 GPSR1_21 GPSR5_21 GPSR6_21 \ 422 GPSR1_20 GPSR5_20 GPSR6_20 \ 423 GPSR1_19 GPSR5_19 GPSR6_19 \ 424 GPSR1_18 GPSR5_18 GPSR6_18 \ 425 GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \ 426 GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \ 427 GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \ 428 GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \ 429 GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \ 430 GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \ 431 GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \ 432 GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \ 433 GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \ 434 GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \ 435 GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \ 436 GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \ 437 GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \ 438 GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \ 439 GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \ 440 GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \ 441 GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \ 442 GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0 443 444 #define PINMUX_IPSR \ 445 \ 446 FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \ 447 FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \ 448 FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \ 449 FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \ 450 FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \ 451 FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \ 452 FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \ 453 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \ 454 \ 455 FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \ 456 FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \ 457 FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \ 458 FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 \ 459 FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \ 460 FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \ 461 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \ 462 FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \ 463 \ 464 FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \ 465 FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \ 466 FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \ 467 FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \ 468 FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \ 469 FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \ 470 FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \ 471 FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \ 472 \ 473 FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \ 474 FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \ 475 FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \ 476 FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \ 477 FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \ 478 FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \ 479 FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \ 480 FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \ 481 \ 482 FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 FM(IP18_3_0) IP18_3_0 \ 483 FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 FM(IP18_7_4) IP18_7_4 \ 484 FM(IP16_11_8) IP16_11_8 FM(IP17_11_8) IP17_11_8 \ 485 FM(IP16_15_12) IP16_15_12 FM(IP17_15_12) IP17_15_12 \ 486 FM(IP16_19_16) IP16_19_16 FM(IP17_19_16) IP17_19_16 \ 487 FM(IP16_23_20) IP16_23_20 FM(IP17_23_20) IP17_23_20 \ 488 FM(IP16_27_24) IP16_27_24 FM(IP17_27_24) IP17_27_24 \ 489 FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28 490 491 /* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ 492 #define MOD_SEL0_31_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3) FM(SEL_MSIOF3_4) F_(0, 0) F_(0, 0) F_(0, 0) 493 #define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3) 494 #define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0) 495 #define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1) 496 #define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1) 497 #define MOD_SEL0_21 FM(SEL_I2C2_0) FM(SEL_I2C2_1) 498 #define MOD_SEL0_20 FM(SEL_I2C1_0) FM(SEL_I2C1_1) 499 #define MOD_SEL0_19 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1) 500 #define MOD_SEL0_18_17 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3) 501 #define MOD_SEL0_16 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1) 502 #define MOD_SEL0_14_13 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) FM(SEL_HSCIF2_2) F_(0, 0) 503 #define MOD_SEL0_12 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1) 504 #define MOD_SEL0_11 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1) 505 #define MOD_SEL0_10 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1) 506 #define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0) 507 #define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0) 508 #define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1) 509 #define MOD_SEL0_4_3 FM(SEL_ADGA_0) FM(SEL_ADGA_1) FM(SEL_ADGA_2) FM(SEL_ADGA_3) 510 511 /* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ 512 #define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3) 513 #define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0) 514 #define MOD_SEL1_26 FM(SEL_TIMER_TMU1_0) FM(SEL_TIMER_TMU1_1) 515 #define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3) 516 #define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0) 517 #define MOD_SEL1_20 FM(SEL_SSI1_0) FM(SEL_SSI1_1) 518 #define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1) 519 #define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3) 520 #define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1) 521 #define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0) 522 #define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1) 523 #define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1) 524 #define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1) 525 #define MOD_SEL1_10 FM(SEL_SCIF_0) FM(SEL_SCIF_1) 526 #define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1) 527 #define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1) 528 #define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1) 529 #define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1) 530 #define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1) 531 #define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1) 532 #define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1) 533 #define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1) 534 535 /* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ 536 #define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1) 537 #define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1) 538 #define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1) 539 #define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3) 540 #define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1) 541 #define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 542 #define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1) 543 #define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1) 544 #define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1) 545 #define MOD_SEL2_18 FM(SEL_ADGB_0) FM(SEL_ADGB_1) 546 #define MOD_SEL2_17 FM(SEL_ADGC_0) FM(SEL_ADGC_1) 547 #define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1) 548 549 #define PINMUX_MOD_SELS \ 550 \ 551 MOD_SEL0_31_30_29 MOD_SEL1_31_30 MOD_SEL2_31 \ 552 MOD_SEL2_30 \ 553 MOD_SEL1_29_28_27 MOD_SEL2_29 \ 554 MOD_SEL0_28_27 MOD_SEL2_28_27 \ 555 MOD_SEL0_26_25_24 MOD_SEL1_26 MOD_SEL2_26 \ 556 MOD_SEL1_25_24 MOD_SEL2_25_24_23 \ 557 MOD_SEL0_23 MOD_SEL1_23_22_21 \ 558 MOD_SEL0_22 \ 559 MOD_SEL0_21 MOD_SEL2_21 \ 560 MOD_SEL0_20 MOD_SEL1_20 MOD_SEL2_20 \ 561 MOD_SEL0_19 MOD_SEL1_19 MOD_SEL2_19 \ 562 MOD_SEL0_18_17 MOD_SEL1_18_17 MOD_SEL2_18 \ 563 MOD_SEL2_17 \ 564 MOD_SEL0_16 MOD_SEL1_16 \ 565 MOD_SEL1_15_14 \ 566 MOD_SEL0_14_13 \ 567 MOD_SEL1_13 \ 568 MOD_SEL0_12 MOD_SEL1_12 \ 569 MOD_SEL0_11 MOD_SEL1_11 \ 570 MOD_SEL0_10 MOD_SEL1_10 \ 571 MOD_SEL0_9_8 MOD_SEL1_9 \ 572 MOD_SEL0_7_6 \ 573 MOD_SEL1_6 \ 574 MOD_SEL0_5 MOD_SEL1_5 \ 575 MOD_SEL0_4_3 MOD_SEL1_4 \ 576 MOD_SEL1_3 \ 577 MOD_SEL1_2 \ 578 MOD_SEL1_1 \ 579 MOD_SEL1_0 MOD_SEL2_0 580 581 /* 582 * These pins are not able to be muxed but have other properties 583 * that can be set, such as drive-strength or pull-up/pull-down enable. 584 */ 585 #define PINMUX_STATIC \ 586 FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \ 587 FM(QSPI0_IO2) FM(QSPI0_IO3) \ 588 FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \ 589 FM(QSPI1_IO2) FM(QSPI1_IO3) \ 590 FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \ 591 FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \ 592 FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \ 593 FM(AVB_TXCREFCLK) FM(AVB_MDIO) \ 594 FM(PRESETOUT) \ 595 FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) FM(DU_DOTCLKIN3) \ 596 FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR) 597 598 #define PINMUX_PHYS \ 599 FM(SCL0) FM(SDA0) FM(SCL3) FM(SDA3) FM(SCL5) FM(SDA5) 600 601 enum { 602 PINMUX_RESERVED = 0, 603 604 PINMUX_DATA_BEGIN, 605 GP_ALL(DATA), 606 PINMUX_DATA_END, 607 608 #define F_(x, y) 609 #define FM(x) FN_##x, 610 PINMUX_FUNCTION_BEGIN, 611 GP_ALL(FN), 612 PINMUX_GPSR 613 PINMUX_IPSR 614 PINMUX_MOD_SELS 615 PINMUX_FUNCTION_END, 616 #undef F_ 617 #undef FM 618 619 #define F_(x, y) 620 #define FM(x) x##_MARK, 621 PINMUX_MARK_BEGIN, 622 PINMUX_GPSR 623 PINMUX_IPSR 624 PINMUX_MOD_SELS 625 PINMUX_STATIC 626 PINMUX_PHYS 627 PINMUX_MARK_END, 628 #undef F_ 629 #undef FM 630 }; 631 632 static const u16 pinmux_data[] = { 633 PINMUX_DATA_GP_ALL(), 634 635 PINMUX_SINGLE(AVS1), 636 PINMUX_SINGLE(AVS2), 637 PINMUX_SINGLE(CLKOUT), 638 PINMUX_SINGLE(GP7_02), 639 PINMUX_SINGLE(GP7_03), 640 PINMUX_SINGLE(MSIOF0_RXD), 641 PINMUX_SINGLE(MSIOF0_SCK), 642 PINMUX_SINGLE(MSIOF0_TXD), 643 PINMUX_SINGLE(SSI_SCK5), 644 PINMUX_SINGLE(SSI_SDATA5), 645 PINMUX_SINGLE(SSI_WS5), 646 647 /* IPSR0 */ 648 PINMUX_IPSR_GPSR(IP0_3_0, AVB_MDC), 649 PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2), 650 651 PINMUX_IPSR_GPSR(IP0_7_4, AVB_MAGIC), 652 PINMUX_IPSR_MSEL(IP0_7_4, MSIOF2_SS1_C, SEL_MSIOF2_2), 653 PINMUX_IPSR_MSEL(IP0_7_4, SCK4_A, SEL_SCIF4_0), 654 655 PINMUX_IPSR_GPSR(IP0_11_8, AVB_PHY_INT), 656 PINMUX_IPSR_MSEL(IP0_11_8, MSIOF2_SYNC_C, SEL_MSIOF2_2), 657 PINMUX_IPSR_MSEL(IP0_11_8, RX4_A, SEL_SCIF4_0), 658 659 PINMUX_IPSR_GPSR(IP0_15_12, AVB_LINK), 660 PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2), 661 PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0), 662 663 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, I2C_SEL_5_0, SEL_ETHERAVB_0), 664 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, MSIOF2_RXD_C, I2C_SEL_5_0, SEL_MSIOF2_2), 665 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, CTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0), 666 PINMUX_IPSR_MSEL(IP0_19_16, FSCLKST2_N_A, I2C_SEL_5_0), 667 PINMUX_IPSR_PHYS(IP0_19_16, SCL5, I2C_SEL_5_1), 668 669 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, I2C_SEL_5_0, SEL_ETHERAVB_0), 670 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C, I2C_SEL_5_0, SEL_MSIOF2_2), 671 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0), 672 PINMUX_IPSR_PHYS(IP0_23_20, SDA5, I2C_SEL_5_1), 673 674 PINMUX_IPSR_GPSR(IP0_27_24, IRQ0), 675 PINMUX_IPSR_GPSR(IP0_27_24, QPOLB), 676 PINMUX_IPSR_GPSR(IP0_27_24, DU_CDE), 677 PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1), 678 PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1), 679 PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_B, SEL_CANFD0_1), 680 PINMUX_IPSR_MSEL(IP0_27_24, MSIOF3_SS2_E, SEL_MSIOF3_4), 681 682 PINMUX_IPSR_GPSR(IP0_31_28, IRQ1), 683 PINMUX_IPSR_GPSR(IP0_31_28, QPOLA), 684 PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP), 685 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1), 686 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1), 687 PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1), 688 PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_SS1_E, SEL_MSIOF3_4), 689 690 /* IPSR1 */ 691 PINMUX_IPSR_GPSR(IP1_3_0, IRQ2), 692 PINMUX_IPSR_GPSR(IP1_3_0, QCPV_QDE), 693 PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE), 694 PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1), 695 PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1), 696 PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_SYNC_E, SEL_MSIOF3_4), 697 698 PINMUX_IPSR_GPSR(IP1_7_4, IRQ3), 699 PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE), 700 PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1), 701 PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1), 702 PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1), 703 PINMUX_IPSR_MSEL(IP1_7_4, MSIOF3_SCK_E, SEL_MSIOF3_4), 704 705 PINMUX_IPSR_GPSR(IP1_11_8, IRQ4), 706 PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS), 707 PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC), 708 PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1), 709 PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1), 710 PINMUX_IPSR_MSEL(IP1_11_8, MSIOF3_RXD_E, SEL_MSIOF3_4), 711 712 PINMUX_IPSR_GPSR(IP1_15_12, IRQ5), 713 PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE), 714 PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC), 715 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1), 716 PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1), 717 PINMUX_IPSR_GPSR(IP1_15_12, FSCLKST2_N_B), 718 PINMUX_IPSR_MSEL(IP1_15_12, MSIOF3_TXD_E, SEL_MSIOF3_4), 719 720 PINMUX_IPSR_GPSR(IP1_19_16, PWM0), 721 PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS), 722 PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1), 723 PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1), 724 725 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, PWM1_A, I2C_SEL_3_0, SEL_PWM1_0), 726 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3), 727 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1), 728 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1), 729 PINMUX_IPSR_PHYS(IP1_23_20, SCL3, I2C_SEL_3_1), 730 731 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0), 732 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D, I2C_SEL_3_0, SEL_HSCIF3_3), 733 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, IETX_B, I2C_SEL_3_0, SEL_IEBUS_1), 734 PINMUX_IPSR_PHYS(IP1_27_24, SDA3, I2C_SEL_3_1), 735 736 PINMUX_IPSR_GPSR(IP1_31_28, A0), 737 PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16), 738 PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SYNC_B, SEL_MSIOF3_1), 739 PINMUX_IPSR_GPSR(IP1_31_28, VI4_DATA8), 740 PINMUX_IPSR_GPSR(IP1_31_28, DU_DB0), 741 PINMUX_IPSR_MSEL(IP1_31_28, PWM3_A, SEL_PWM3_0), 742 743 /* IPSR2 */ 744 PINMUX_IPSR_GPSR(IP2_3_0, A1), 745 PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT17), 746 PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_TXD_B, SEL_MSIOF3_1), 747 PINMUX_IPSR_GPSR(IP2_3_0, VI4_DATA9), 748 PINMUX_IPSR_GPSR(IP2_3_0, DU_DB1), 749 PINMUX_IPSR_MSEL(IP2_3_0, PWM4_A, SEL_PWM4_0), 750 751 PINMUX_IPSR_GPSR(IP2_7_4, A2), 752 PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT18), 753 PINMUX_IPSR_MSEL(IP2_7_4, MSIOF3_SCK_B, SEL_MSIOF3_1), 754 PINMUX_IPSR_GPSR(IP2_7_4, VI4_DATA10), 755 PINMUX_IPSR_GPSR(IP2_7_4, DU_DB2), 756 PINMUX_IPSR_MSEL(IP2_7_4, PWM5_A, SEL_PWM5_0), 757 758 PINMUX_IPSR_GPSR(IP2_11_8, A3), 759 PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT19), 760 PINMUX_IPSR_MSEL(IP2_11_8, MSIOF3_RXD_B, SEL_MSIOF3_1), 761 PINMUX_IPSR_GPSR(IP2_11_8, VI4_DATA11), 762 PINMUX_IPSR_GPSR(IP2_11_8, DU_DB3), 763 PINMUX_IPSR_MSEL(IP2_11_8, PWM6_A, SEL_PWM6_0), 764 765 PINMUX_IPSR_GPSR(IP2_15_12, A4), 766 PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT20), 767 PINMUX_IPSR_MSEL(IP2_15_12, MSIOF3_SS1_B, SEL_MSIOF3_1), 768 PINMUX_IPSR_GPSR(IP2_15_12, VI4_DATA12), 769 PINMUX_IPSR_GPSR(IP2_15_12, VI5_DATA12), 770 PINMUX_IPSR_GPSR(IP2_15_12, DU_DB4), 771 772 PINMUX_IPSR_GPSR(IP2_19_16, A5), 773 PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT21), 774 PINMUX_IPSR_MSEL(IP2_19_16, MSIOF3_SS2_B, SEL_MSIOF3_1), 775 PINMUX_IPSR_MSEL(IP2_19_16, SCK4_B, SEL_SCIF4_1), 776 PINMUX_IPSR_GPSR(IP2_19_16, VI4_DATA13), 777 PINMUX_IPSR_GPSR(IP2_19_16, VI5_DATA13), 778 PINMUX_IPSR_GPSR(IP2_19_16, DU_DB5), 779 780 PINMUX_IPSR_GPSR(IP2_23_20, A6), 781 PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT22), 782 PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_SS1_A, SEL_MSIOF2_0), 783 PINMUX_IPSR_MSEL(IP2_23_20, RX4_B, SEL_SCIF4_1), 784 PINMUX_IPSR_GPSR(IP2_23_20, VI4_DATA14), 785 PINMUX_IPSR_GPSR(IP2_23_20, VI5_DATA14), 786 PINMUX_IPSR_GPSR(IP2_23_20, DU_DB6), 787 788 PINMUX_IPSR_GPSR(IP2_27_24, A7), 789 PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT23), 790 PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SS2_A, SEL_MSIOF2_0), 791 PINMUX_IPSR_MSEL(IP2_27_24, TX4_B, SEL_SCIF4_1), 792 PINMUX_IPSR_GPSR(IP2_27_24, VI4_DATA15), 793 PINMUX_IPSR_GPSR(IP2_27_24, VI5_DATA15), 794 PINMUX_IPSR_GPSR(IP2_27_24, DU_DB7), 795 796 PINMUX_IPSR_GPSR(IP2_31_28, A8), 797 PINMUX_IPSR_MSEL(IP2_31_28, RX3_B, SEL_SCIF3_1), 798 PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0), 799 PINMUX_IPSR_MSEL(IP2_31_28, HRX4_B, SEL_HSCIF4_1), 800 PINMUX_IPSR_MSEL(IP2_31_28, SDA6_A, SEL_I2C6_0), 801 PINMUX_IPSR_MSEL(IP2_31_28, AVB_AVTP_MATCH_B, SEL_ETHERAVB_1), 802 PINMUX_IPSR_MSEL(IP2_31_28, PWM1_B, SEL_PWM1_1), 803 804 /* IPSR3 */ 805 PINMUX_IPSR_GPSR(IP3_3_0, A9), 806 PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0), 807 PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1), 808 PINMUX_IPSR_GPSR(IP3_3_0, VI5_VSYNC_N), 809 810 PINMUX_IPSR_GPSR(IP3_7_4, A10), 811 PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0), 812 PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_B, SEL_SCIF4_1), 813 PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N), 814 815 PINMUX_IPSR_GPSR(IP3_11_8, A11), 816 PINMUX_IPSR_MSEL(IP3_11_8, TX3_B, SEL_SCIF3_1), 817 PINMUX_IPSR_MSEL(IP3_11_8, MSIOF2_TXD_A, SEL_MSIOF2_0), 818 PINMUX_IPSR_MSEL(IP3_11_8, HTX4_B, SEL_HSCIF4_1), 819 PINMUX_IPSR_GPSR(IP3_11_8, HSCK4), 820 PINMUX_IPSR_GPSR(IP3_11_8, VI5_FIELD), 821 PINMUX_IPSR_MSEL(IP3_11_8, SCL6_A, SEL_I2C6_0), 822 PINMUX_IPSR_MSEL(IP3_11_8, AVB_AVTP_CAPTURE_B, SEL_ETHERAVB_1), 823 PINMUX_IPSR_MSEL(IP3_11_8, PWM2_B, SEL_PWM2_1), 824 825 PINMUX_IPSR_GPSR(IP3_15_12, A12), 826 PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT12), 827 PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SCK_C, SEL_MSIOF3_2), 828 PINMUX_IPSR_MSEL(IP3_15_12, HRX4_A, SEL_HSCIF4_0), 829 PINMUX_IPSR_GPSR(IP3_15_12, VI5_DATA8), 830 PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4), 831 832 PINMUX_IPSR_GPSR(IP3_19_16, A13), 833 PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT13), 834 PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SYNC_C, SEL_MSIOF3_2), 835 PINMUX_IPSR_MSEL(IP3_19_16, HTX4_A, SEL_HSCIF4_0), 836 PINMUX_IPSR_GPSR(IP3_19_16, VI5_DATA9), 837 PINMUX_IPSR_GPSR(IP3_19_16, DU_DG5), 838 839 PINMUX_IPSR_GPSR(IP3_23_20, A14), 840 PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT14), 841 PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_C, SEL_MSIOF3_2), 842 PINMUX_IPSR_GPSR(IP3_23_20, HCTS4_N), 843 PINMUX_IPSR_GPSR(IP3_23_20, VI5_DATA10), 844 PINMUX_IPSR_GPSR(IP3_23_20, DU_DG6), 845 846 PINMUX_IPSR_GPSR(IP3_27_24, A15), 847 PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT15), 848 PINMUX_IPSR_MSEL(IP3_27_24, MSIOF3_TXD_C, SEL_MSIOF3_2), 849 PINMUX_IPSR_GPSR(IP3_27_24, HRTS4_N), 850 PINMUX_IPSR_GPSR(IP3_27_24, VI5_DATA11), 851 PINMUX_IPSR_GPSR(IP3_27_24, DU_DG7), 852 853 PINMUX_IPSR_GPSR(IP3_31_28, A16), 854 PINMUX_IPSR_GPSR(IP3_31_28, LCDOUT8), 855 PINMUX_IPSR_GPSR(IP3_31_28, VI4_FIELD), 856 PINMUX_IPSR_GPSR(IP3_31_28, DU_DG0), 857 858 /* IPSR4 */ 859 PINMUX_IPSR_GPSR(IP4_3_0, A17), 860 PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT9), 861 PINMUX_IPSR_GPSR(IP4_3_0, VI4_VSYNC_N), 862 PINMUX_IPSR_GPSR(IP4_3_0, DU_DG1), 863 864 PINMUX_IPSR_GPSR(IP4_7_4, A18), 865 PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT10), 866 PINMUX_IPSR_GPSR(IP4_7_4, VI4_HSYNC_N), 867 PINMUX_IPSR_GPSR(IP4_7_4, DU_DG2), 868 869 PINMUX_IPSR_GPSR(IP4_11_8, A19), 870 PINMUX_IPSR_GPSR(IP4_11_8, LCDOUT11), 871 PINMUX_IPSR_GPSR(IP4_11_8, VI4_CLKENB), 872 PINMUX_IPSR_GPSR(IP4_11_8, DU_DG3), 873 874 PINMUX_IPSR_GPSR(IP4_15_12, CS0_N), 875 PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB), 876 877 PINMUX_IPSR_GPSR(IP4_19_16, CS1_N), 878 PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK), 879 PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1), 880 881 PINMUX_IPSR_GPSR(IP4_23_20, BS_N), 882 PINMUX_IPSR_GPSR(IP4_23_20, QSTVA_QVS), 883 PINMUX_IPSR_MSEL(IP4_23_20, MSIOF3_SCK_D, SEL_MSIOF3_3), 884 PINMUX_IPSR_GPSR(IP4_23_20, SCK3), 885 PINMUX_IPSR_GPSR(IP4_23_20, HSCK3), 886 PINMUX_IPSR_GPSR(IP4_23_20, CAN1_TX), 887 PINMUX_IPSR_GPSR(IP4_23_20, CANFD1_TX), 888 PINMUX_IPSR_MSEL(IP4_23_20, IETX_A, SEL_IEBUS_0), 889 890 PINMUX_IPSR_GPSR(IP4_27_24, RD_N), 891 PINMUX_IPSR_MSEL(IP4_27_24, MSIOF3_SYNC_D, SEL_MSIOF3_3), 892 PINMUX_IPSR_MSEL(IP4_27_24, RX3_A, SEL_SCIF3_0), 893 PINMUX_IPSR_MSEL(IP4_27_24, HRX3_A, SEL_HSCIF3_0), 894 PINMUX_IPSR_MSEL(IP4_27_24, CAN0_TX_A, SEL_RCAN0_0), 895 PINMUX_IPSR_MSEL(IP4_27_24, CANFD0_TX_A, SEL_CANFD0_0), 896 897 PINMUX_IPSR_GPSR(IP4_31_28, RD_WR_N), 898 PINMUX_IPSR_MSEL(IP4_31_28, MSIOF3_RXD_D, SEL_MSIOF3_3), 899 PINMUX_IPSR_MSEL(IP4_31_28, TX3_A, SEL_SCIF3_0), 900 PINMUX_IPSR_MSEL(IP4_31_28, HTX3_A, SEL_HSCIF3_0), 901 PINMUX_IPSR_MSEL(IP4_31_28, CAN0_RX_A, SEL_RCAN0_0), 902 PINMUX_IPSR_MSEL(IP4_31_28, CANFD0_RX_A, SEL_CANFD0_0), 903 904 /* IPSR5 */ 905 PINMUX_IPSR_GPSR(IP5_3_0, WE0_N), 906 PINMUX_IPSR_MSEL(IP5_3_0, MSIOF3_TXD_D, SEL_MSIOF3_3), 907 PINMUX_IPSR_GPSR(IP5_3_0, CTS3_N), 908 PINMUX_IPSR_GPSR(IP5_3_0, HCTS3_N), 909 PINMUX_IPSR_MSEL(IP5_3_0, SCL6_B, SEL_I2C6_1), 910 PINMUX_IPSR_GPSR(IP5_3_0, CAN_CLK), 911 PINMUX_IPSR_MSEL(IP5_3_0, IECLK_A, SEL_IEBUS_0), 912 913 PINMUX_IPSR_GPSR(IP5_7_4, WE1_N), 914 PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3), 915 PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N), 916 PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N), 917 PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1), 918 PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX), 919 PINMUX_IPSR_GPSR(IP5_7_4, CANFD1_RX), 920 PINMUX_IPSR_MSEL(IP5_7_4, IERX_A, SEL_IEBUS_0), 921 922 PINMUX_IPSR_MSEL(IP5_11_8, EX_WAIT0_A, SEL_LBSC_0), 923 PINMUX_IPSR_GPSR(IP5_11_8, QCLK), 924 PINMUX_IPSR_GPSR(IP5_11_8, VI4_CLK), 925 PINMUX_IPSR_GPSR(IP5_11_8, DU_DOTCLKOUT0), 926 927 PINMUX_IPSR_GPSR(IP5_15_12, D0), 928 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF2_SS1_B, SEL_MSIOF2_1), 929 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF3_SCK_A, SEL_MSIOF3_0), 930 PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA16), 931 PINMUX_IPSR_GPSR(IP5_15_12, VI5_DATA0), 932 933 PINMUX_IPSR_GPSR(IP5_19_16, D1), 934 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF2_SS2_B, SEL_MSIOF2_1), 935 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF3_SYNC_A, SEL_MSIOF3_0), 936 PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA17), 937 PINMUX_IPSR_GPSR(IP5_19_16, VI5_DATA1), 938 939 PINMUX_IPSR_GPSR(IP5_23_20, D2), 940 PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_RXD_A, SEL_MSIOF3_0), 941 PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA18), 942 PINMUX_IPSR_GPSR(IP5_23_20, VI5_DATA2), 943 944 PINMUX_IPSR_GPSR(IP5_27_24, D3), 945 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0), 946 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19), 947 PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3), 948 949 PINMUX_IPSR_GPSR(IP5_31_28, D4), 950 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF2_SCK_B, SEL_MSIOF2_1), 951 PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA20), 952 PINMUX_IPSR_GPSR(IP5_31_28, VI5_DATA4), 953 954 /* IPSR6 */ 955 PINMUX_IPSR_GPSR(IP6_3_0, D5), 956 PINMUX_IPSR_MSEL(IP6_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1), 957 PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA21), 958 PINMUX_IPSR_GPSR(IP6_3_0, VI5_DATA5), 959 960 PINMUX_IPSR_GPSR(IP6_7_4, D6), 961 PINMUX_IPSR_MSEL(IP6_7_4, MSIOF2_RXD_B, SEL_MSIOF2_1), 962 PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA22), 963 PINMUX_IPSR_GPSR(IP6_7_4, VI5_DATA6), 964 965 PINMUX_IPSR_GPSR(IP6_11_8, D7), 966 PINMUX_IPSR_MSEL(IP6_11_8, MSIOF2_TXD_B, SEL_MSIOF2_1), 967 PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA23), 968 PINMUX_IPSR_GPSR(IP6_11_8, VI5_DATA7), 969 970 PINMUX_IPSR_GPSR(IP6_15_12, D8), 971 PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT0), 972 PINMUX_IPSR_MSEL(IP6_15_12, MSIOF2_SCK_D, SEL_MSIOF2_3), 973 PINMUX_IPSR_MSEL(IP6_15_12, SCK4_C, SEL_SCIF4_2), 974 PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA0_A, SEL_VIN4_0), 975 PINMUX_IPSR_GPSR(IP6_15_12, DU_DR0), 976 977 PINMUX_IPSR_GPSR(IP6_19_16, D9), 978 PINMUX_IPSR_GPSR(IP6_19_16, LCDOUT1), 979 PINMUX_IPSR_MSEL(IP6_19_16, MSIOF2_SYNC_D, SEL_MSIOF2_3), 980 PINMUX_IPSR_MSEL(IP6_19_16, VI4_DATA1_A, SEL_VIN4_0), 981 PINMUX_IPSR_GPSR(IP6_19_16, DU_DR1), 982 983 PINMUX_IPSR_GPSR(IP6_23_20, D10), 984 PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT2), 985 PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_RXD_D, SEL_MSIOF2_3), 986 PINMUX_IPSR_MSEL(IP6_23_20, HRX3_B, SEL_HSCIF3_1), 987 PINMUX_IPSR_MSEL(IP6_23_20, VI4_DATA2_A, SEL_VIN4_0), 988 PINMUX_IPSR_MSEL(IP6_23_20, CTS4_N_C, SEL_SCIF4_2), 989 PINMUX_IPSR_GPSR(IP6_23_20, DU_DR2), 990 991 PINMUX_IPSR_GPSR(IP6_27_24, D11), 992 PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT3), 993 PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3), 994 PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1), 995 PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0), 996 PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_C, SEL_SCIF4_2), 997 PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3), 998 999 PINMUX_IPSR_GPSR(IP6_31_28, D12), 1000 PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT4), 1001 PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3), 1002 PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2), 1003 PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0), 1004 PINMUX_IPSR_GPSR(IP6_31_28, DU_DR4), 1005 1006 /* IPSR7 */ 1007 PINMUX_IPSR_GPSR(IP7_3_0, D13), 1008 PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT5), 1009 PINMUX_IPSR_MSEL(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3), 1010 PINMUX_IPSR_MSEL(IP7_3_0, TX4_C, SEL_SCIF4_2), 1011 PINMUX_IPSR_MSEL(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0), 1012 PINMUX_IPSR_GPSR(IP7_3_0, DU_DR5), 1013 1014 PINMUX_IPSR_GPSR(IP7_7_4, D14), 1015 PINMUX_IPSR_GPSR(IP7_7_4, LCDOUT6), 1016 PINMUX_IPSR_MSEL(IP7_7_4, MSIOF3_SS1_A, SEL_MSIOF3_0), 1017 PINMUX_IPSR_MSEL(IP7_7_4, HRX3_C, SEL_HSCIF3_2), 1018 PINMUX_IPSR_MSEL(IP7_7_4, VI4_DATA6_A, SEL_VIN4_0), 1019 PINMUX_IPSR_GPSR(IP7_7_4, DU_DR6), 1020 PINMUX_IPSR_MSEL(IP7_7_4, SCL6_C, SEL_I2C6_2), 1021 1022 PINMUX_IPSR_GPSR(IP7_11_8, D15), 1023 PINMUX_IPSR_GPSR(IP7_11_8, LCDOUT7), 1024 PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SS2_A, SEL_MSIOF3_0), 1025 PINMUX_IPSR_MSEL(IP7_11_8, HTX3_C, SEL_HSCIF3_2), 1026 PINMUX_IPSR_MSEL(IP7_11_8, VI4_DATA7_A, SEL_VIN4_0), 1027 PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7), 1028 PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2), 1029 1030 PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK), 1031 PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4), 1032 PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1), 1033 1034 PINMUX_IPSR_GPSR(IP7_23_20, SD0_CMD), 1035 PINMUX_IPSR_MSEL(IP7_23_20, MSIOF1_SYNC_E, SEL_MSIOF1_4), 1036 PINMUX_IPSR_MSEL(IP7_23_20, STP_IVCXO27_0_B, SEL_SSP1_0_1), 1037 1038 PINMUX_IPSR_GPSR(IP7_27_24, SD0_DAT0), 1039 PINMUX_IPSR_MSEL(IP7_27_24, MSIOF1_RXD_E, SEL_MSIOF1_4), 1040 PINMUX_IPSR_MSEL(IP7_27_24, TS_SCK0_B, SEL_TSIF0_1), 1041 PINMUX_IPSR_MSEL(IP7_27_24, STP_ISCLK_0_B, SEL_SSP1_0_1), 1042 1043 PINMUX_IPSR_GPSR(IP7_31_28, SD0_DAT1), 1044 PINMUX_IPSR_MSEL(IP7_31_28, MSIOF1_TXD_E, SEL_MSIOF1_4), 1045 PINMUX_IPSR_MSEL(IP7_31_28, TS_SPSYNC0_B, SEL_TSIF0_1), 1046 PINMUX_IPSR_MSEL(IP7_31_28, STP_ISSYNC_0_B, SEL_SSP1_0_1), 1047 1048 /* IPSR8 */ 1049 PINMUX_IPSR_GPSR(IP8_3_0, SD0_DAT2), 1050 PINMUX_IPSR_MSEL(IP8_3_0, MSIOF1_SS1_E, SEL_MSIOF1_4), 1051 PINMUX_IPSR_MSEL(IP8_3_0, TS_SDAT0_B, SEL_TSIF0_1), 1052 PINMUX_IPSR_MSEL(IP8_3_0, STP_ISD_0_B, SEL_SSP1_0_1), 1053 1054 PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT3), 1055 PINMUX_IPSR_MSEL(IP8_7_4, MSIOF1_SS2_E, SEL_MSIOF1_4), 1056 PINMUX_IPSR_MSEL(IP8_7_4, TS_SDEN0_B, SEL_TSIF0_1), 1057 PINMUX_IPSR_MSEL(IP8_7_4, STP_ISEN_0_B, SEL_SSP1_0_1), 1058 1059 PINMUX_IPSR_GPSR(IP8_11_8, SD1_CLK), 1060 PINMUX_IPSR_MSEL(IP8_11_8, MSIOF1_SCK_G, SEL_MSIOF1_6), 1061 PINMUX_IPSR_MSEL(IP8_11_8, SIM0_CLK_A, SEL_SIMCARD_0), 1062 1063 PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD), 1064 PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6), 1065 PINMUX_IPSR_GPSR(IP8_15_12, NFCE_N_B), 1066 PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0), 1067 PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1), 1068 1069 PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0), 1070 PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4), 1071 PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6), 1072 PINMUX_IPSR_GPSR(IP8_19_16, NFWP_N_B), 1073 PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1), 1074 PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1), 1075 1076 PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1), 1077 PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5), 1078 PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6), 1079 PINMUX_IPSR_GPSR(IP8_23_20, NFDATA14_B), 1080 PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1), 1081 PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1), 1082 1083 PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2), 1084 PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6), 1085 PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6), 1086 PINMUX_IPSR_GPSR(IP8_27_24, NFDATA15_B), 1087 PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1), 1088 PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1), 1089 1090 PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3), 1091 PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7), 1092 PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6), 1093 PINMUX_IPSR_GPSR(IP8_31_28, NFRB_N_B), 1094 PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1), 1095 PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1), 1096 1097 /* IPSR9 */ 1098 PINMUX_IPSR_GPSR(IP9_3_0, SD2_CLK), 1099 PINMUX_IPSR_GPSR(IP9_3_0, NFDATA8), 1100 1101 PINMUX_IPSR_GPSR(IP9_7_4, SD2_CMD), 1102 PINMUX_IPSR_GPSR(IP9_7_4, NFDATA9), 1103 1104 PINMUX_IPSR_GPSR(IP9_11_8, SD2_DAT0), 1105 PINMUX_IPSR_GPSR(IP9_11_8, NFDATA10), 1106 1107 PINMUX_IPSR_GPSR(IP9_15_12, SD2_DAT1), 1108 PINMUX_IPSR_GPSR(IP9_15_12, NFDATA11), 1109 1110 PINMUX_IPSR_GPSR(IP9_19_16, SD2_DAT2), 1111 PINMUX_IPSR_GPSR(IP9_19_16, NFDATA12), 1112 1113 PINMUX_IPSR_GPSR(IP9_23_20, SD2_DAT3), 1114 PINMUX_IPSR_GPSR(IP9_23_20, NFDATA13), 1115 1116 PINMUX_IPSR_GPSR(IP9_27_24, SD2_DS), 1117 PINMUX_IPSR_GPSR(IP9_27_24, NFALE), 1118 PINMUX_IPSR_GPSR(IP9_27_24, SATA_DEVSLP_B), 1119 1120 PINMUX_IPSR_GPSR(IP9_31_28, SD3_CLK), 1121 PINMUX_IPSR_GPSR(IP9_31_28, NFWE_N), 1122 1123 /* IPSR10 */ 1124 PINMUX_IPSR_GPSR(IP10_3_0, SD3_CMD), 1125 PINMUX_IPSR_GPSR(IP10_3_0, NFRE_N), 1126 1127 PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT0), 1128 PINMUX_IPSR_GPSR(IP10_7_4, NFDATA0), 1129 1130 PINMUX_IPSR_GPSR(IP10_11_8, SD3_DAT1), 1131 PINMUX_IPSR_GPSR(IP10_11_8, NFDATA1), 1132 1133 PINMUX_IPSR_GPSR(IP10_15_12, SD3_DAT2), 1134 PINMUX_IPSR_GPSR(IP10_15_12, NFDATA2), 1135 1136 PINMUX_IPSR_GPSR(IP10_19_16, SD3_DAT3), 1137 PINMUX_IPSR_GPSR(IP10_19_16, NFDATA3), 1138 1139 PINMUX_IPSR_GPSR(IP10_23_20, SD3_DAT4), 1140 PINMUX_IPSR_MSEL(IP10_23_20, SD2_CD_A, SEL_SDHI2_0), 1141 PINMUX_IPSR_GPSR(IP10_23_20, NFDATA4), 1142 1143 PINMUX_IPSR_GPSR(IP10_27_24, SD3_DAT5), 1144 PINMUX_IPSR_MSEL(IP10_27_24, SD2_WP_A, SEL_SDHI2_0), 1145 PINMUX_IPSR_GPSR(IP10_27_24, NFDATA5), 1146 1147 PINMUX_IPSR_GPSR(IP10_31_28, SD3_DAT6), 1148 PINMUX_IPSR_GPSR(IP10_31_28, SD3_CD), 1149 PINMUX_IPSR_GPSR(IP10_31_28, NFDATA6), 1150 1151 /* IPSR11 */ 1152 PINMUX_IPSR_GPSR(IP11_3_0, SD3_DAT7), 1153 PINMUX_IPSR_GPSR(IP11_3_0, SD3_WP), 1154 PINMUX_IPSR_GPSR(IP11_3_0, NFDATA7), 1155 1156 PINMUX_IPSR_GPSR(IP11_7_4, SD3_DS), 1157 PINMUX_IPSR_GPSR(IP11_7_4, NFCLE), 1158 1159 PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD), 1160 PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1), 1161 PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0), 1162 1163 PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP), 1164 PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1), 1165 1166 PINMUX_IPSR_MSEL(IP11_19_16, SD1_CD, I2C_SEL_0_0), 1167 PINMUX_IPSR_PHYS_MSEL(IP11_19_16, SIM0_CLK_B, I2C_SEL_0_0, SEL_SIMCARD_1), 1168 PINMUX_IPSR_PHYS(IP11_19_16, SCL0, I2C_SEL_0_1), 1169 1170 PINMUX_IPSR_MSEL(IP11_23_20, SD1_WP, I2C_SEL_0_0), 1171 PINMUX_IPSR_PHYS_MSEL(IP11_23_20, SIM0_D_B, I2C_SEL_0_0, SEL_SIMCARD_1), 1172 PINMUX_IPSR_PHYS(IP11_23_20, SDA0, I2C_SEL_0_1), 1173 1174 PINMUX_IPSR_GPSR(IP11_27_24, SCK0), 1175 PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1), 1176 PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1), 1177 PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADGC_1), 1178 PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0), 1179 PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1), 1180 PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2), 1181 PINMUX_IPSR_MSEL(IP11_27_24, RIF0_CLK_B, SEL_DRIF0_1), 1182 PINMUX_IPSR_GPSR(IP11_27_24, ADICHS2), 1183 PINMUX_IPSR_MSEL(IP11_27_24, SCK5_B, SEL_SCIF5_1), 1184 1185 PINMUX_IPSR_GPSR(IP11_31_28, RX0), 1186 PINMUX_IPSR_MSEL(IP11_31_28, HRX1_B, SEL_HSCIF1_1), 1187 PINMUX_IPSR_MSEL(IP11_31_28, TS_SCK0_C, SEL_TSIF0_2), 1188 PINMUX_IPSR_MSEL(IP11_31_28, STP_ISCLK_0_C, SEL_SSP1_0_2), 1189 PINMUX_IPSR_MSEL(IP11_31_28, RIF0_D0_B, SEL_DRIF0_1), 1190 1191 /* IPSR12 */ 1192 PINMUX_IPSR_GPSR(IP12_3_0, TX0), 1193 PINMUX_IPSR_MSEL(IP12_3_0, HTX1_B, SEL_HSCIF1_1), 1194 PINMUX_IPSR_MSEL(IP12_3_0, TS_SPSYNC0_C, SEL_TSIF0_2), 1195 PINMUX_IPSR_MSEL(IP12_3_0, STP_ISSYNC_0_C, SEL_SSP1_0_2), 1196 PINMUX_IPSR_MSEL(IP12_3_0, RIF0_D1_B, SEL_DRIF0_1), 1197 1198 PINMUX_IPSR_GPSR(IP12_7_4, CTS0_N), 1199 PINMUX_IPSR_MSEL(IP12_7_4, HCTS1_N_B, SEL_HSCIF1_1), 1200 PINMUX_IPSR_MSEL(IP12_7_4, MSIOF1_SYNC_B, SEL_MSIOF1_1), 1201 PINMUX_IPSR_MSEL(IP12_7_4, TS_SPSYNC1_C, SEL_TSIF1_2), 1202 PINMUX_IPSR_MSEL(IP12_7_4, STP_ISSYNC_1_C, SEL_SSP1_1_2), 1203 PINMUX_IPSR_MSEL(IP12_7_4, RIF1_SYNC_B, SEL_DRIF1_1), 1204 PINMUX_IPSR_GPSR(IP12_7_4, AUDIO_CLKOUT_C), 1205 PINMUX_IPSR_GPSR(IP12_7_4, ADICS_SAMP), 1206 1207 PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N), 1208 PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1), 1209 PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1), 1210 PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADGA_1), 1211 PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0), 1212 PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2), 1213 PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1), 1214 PINMUX_IPSR_GPSR(IP12_11_8, ADICHS1), 1215 1216 PINMUX_IPSR_MSEL(IP12_15_12, RX1_A, SEL_SCIF1_0), 1217 PINMUX_IPSR_MSEL(IP12_15_12, HRX1_A, SEL_HSCIF1_0), 1218 PINMUX_IPSR_MSEL(IP12_15_12, TS_SDAT0_C, SEL_TSIF0_2), 1219 PINMUX_IPSR_MSEL(IP12_15_12, STP_ISD_0_C, SEL_SSP1_0_2), 1220 PINMUX_IPSR_MSEL(IP12_15_12, RIF1_CLK_C, SEL_DRIF1_2), 1221 1222 PINMUX_IPSR_MSEL(IP12_19_16, TX1_A, SEL_SCIF1_0), 1223 PINMUX_IPSR_MSEL(IP12_19_16, HTX1_A, SEL_HSCIF1_0), 1224 PINMUX_IPSR_MSEL(IP12_19_16, TS_SDEN0_C, SEL_TSIF0_2), 1225 PINMUX_IPSR_MSEL(IP12_19_16, STP_ISEN_0_C, SEL_SSP1_0_2), 1226 PINMUX_IPSR_MSEL(IP12_19_16, RIF1_D0_C, SEL_DRIF1_2), 1227 1228 PINMUX_IPSR_GPSR(IP12_23_20, CTS1_N), 1229 PINMUX_IPSR_MSEL(IP12_23_20, HCTS1_N_A, SEL_HSCIF1_0), 1230 PINMUX_IPSR_MSEL(IP12_23_20, MSIOF1_RXD_B, SEL_MSIOF1_1), 1231 PINMUX_IPSR_MSEL(IP12_23_20, TS_SDEN1_C, SEL_TSIF1_2), 1232 PINMUX_IPSR_MSEL(IP12_23_20, STP_ISEN_1_C, SEL_SSP1_1_2), 1233 PINMUX_IPSR_MSEL(IP12_23_20, RIF1_D0_B, SEL_DRIF1_1), 1234 PINMUX_IPSR_GPSR(IP12_23_20, ADIDATA), 1235 1236 PINMUX_IPSR_GPSR(IP12_27_24, RTS1_N), 1237 PINMUX_IPSR_MSEL(IP12_27_24, HRTS1_N_A, SEL_HSCIF1_0), 1238 PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1), 1239 PINMUX_IPSR_MSEL(IP12_27_24, TS_SDAT1_C, SEL_TSIF1_2), 1240 PINMUX_IPSR_MSEL(IP12_27_24, STP_ISD_1_C, SEL_SSP1_1_2), 1241 PINMUX_IPSR_MSEL(IP12_27_24, RIF1_D1_B, SEL_DRIF1_1), 1242 PINMUX_IPSR_GPSR(IP12_27_24, ADICHS0), 1243 1244 PINMUX_IPSR_GPSR(IP12_31_28, SCK2), 1245 PINMUX_IPSR_MSEL(IP12_31_28, SCIF_CLK_B, SEL_SCIF_1), 1246 PINMUX_IPSR_MSEL(IP12_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1), 1247 PINMUX_IPSR_MSEL(IP12_31_28, TS_SCK1_C, SEL_TSIF1_2), 1248 PINMUX_IPSR_MSEL(IP12_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2), 1249 PINMUX_IPSR_MSEL(IP12_31_28, RIF1_CLK_B, SEL_DRIF1_1), 1250 PINMUX_IPSR_GPSR(IP12_31_28, ADICLK), 1251 1252 /* IPSR13 */ 1253 PINMUX_IPSR_MSEL(IP13_3_0, TX2_A, SEL_SCIF2_0), 1254 PINMUX_IPSR_MSEL(IP13_3_0, SD2_CD_B, SEL_SDHI2_1), 1255 PINMUX_IPSR_MSEL(IP13_3_0, SCL1_A, SEL_I2C1_0), 1256 PINMUX_IPSR_MSEL(IP13_3_0, FMCLK_A, SEL_FM_0), 1257 PINMUX_IPSR_MSEL(IP13_3_0, RIF1_D1_C, SEL_DRIF1_2), 1258 PINMUX_IPSR_GPSR(IP13_3_0, FSO_CFE_0_N), 1259 1260 PINMUX_IPSR_MSEL(IP13_7_4, RX2_A, SEL_SCIF2_0), 1261 PINMUX_IPSR_MSEL(IP13_7_4, SD2_WP_B, SEL_SDHI2_1), 1262 PINMUX_IPSR_MSEL(IP13_7_4, SDA1_A, SEL_I2C1_0), 1263 PINMUX_IPSR_MSEL(IP13_7_4, FMIN_A, SEL_FM_0), 1264 PINMUX_IPSR_MSEL(IP13_7_4, RIF1_SYNC_C, SEL_DRIF1_2), 1265 PINMUX_IPSR_GPSR(IP13_7_4, FSO_CFE_1_N), 1266 1267 PINMUX_IPSR_GPSR(IP13_11_8, HSCK0), 1268 PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3), 1269 PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADGB_0), 1270 PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI1_1), 1271 PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3), 1272 PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3), 1273 PINMUX_IPSR_MSEL(IP13_11_8, RIF0_CLK_C, SEL_DRIF0_2), 1274 PINMUX_IPSR_MSEL(IP13_11_8, RX5_B, SEL_SCIF5_1), 1275 1276 PINMUX_IPSR_GPSR(IP13_15_12, HRX0), 1277 PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3), 1278 PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA2_B, SEL_SSI2_1), 1279 PINMUX_IPSR_MSEL(IP13_15_12, TS_SDEN0_D, SEL_TSIF0_3), 1280 PINMUX_IPSR_MSEL(IP13_15_12, STP_ISEN_0_D, SEL_SSP1_0_3), 1281 PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_C, SEL_DRIF0_2), 1282 1283 PINMUX_IPSR_GPSR(IP13_19_16, HTX0), 1284 PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3), 1285 PINMUX_IPSR_MSEL(IP13_19_16, SSI_SDATA9_B, SEL_SSI9_1), 1286 PINMUX_IPSR_MSEL(IP13_19_16, TS_SDAT0_D, SEL_TSIF0_3), 1287 PINMUX_IPSR_MSEL(IP13_19_16, STP_ISD_0_D, SEL_SSP1_0_3), 1288 PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_C, SEL_DRIF0_2), 1289 1290 PINMUX_IPSR_GPSR(IP13_23_20, HCTS0_N), 1291 PINMUX_IPSR_MSEL(IP13_23_20, RX2_B, SEL_SCIF2_1), 1292 PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3), 1293 PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK9_A, SEL_SSI9_0), 1294 PINMUX_IPSR_MSEL(IP13_23_20, TS_SPSYNC0_D, SEL_TSIF0_3), 1295 PINMUX_IPSR_MSEL(IP13_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3), 1296 PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_C, SEL_DRIF0_2), 1297 PINMUX_IPSR_GPSR(IP13_23_20, AUDIO_CLKOUT1_A), 1298 1299 PINMUX_IPSR_GPSR(IP13_27_24, HRTS0_N), 1300 PINMUX_IPSR_MSEL(IP13_27_24, TX2_B, SEL_SCIF2_1), 1301 PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3), 1302 PINMUX_IPSR_MSEL(IP13_27_24, SSI_WS9_A, SEL_SSI9_0), 1303 PINMUX_IPSR_MSEL(IP13_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3), 1304 PINMUX_IPSR_MSEL(IP13_27_24, BPFCLK_A, SEL_FM_0), 1305 PINMUX_IPSR_GPSR(IP13_27_24, AUDIO_CLKOUT2_A), 1306 1307 PINMUX_IPSR_GPSR(IP13_31_28, MSIOF0_SYNC), 1308 PINMUX_IPSR_GPSR(IP13_31_28, AUDIO_CLKOUT_A), 1309 PINMUX_IPSR_MSEL(IP13_31_28, TX5_B, SEL_SCIF5_1), 1310 PINMUX_IPSR_MSEL(IP13_31_28, BPFCLK_D, SEL_FM_3), 1311 1312 /* IPSR14 */ 1313 PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1), 1314 PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0), 1315 PINMUX_IPSR_GPSR(IP14_3_0, NFWP_N_A), 1316 PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADGA_2), 1317 PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0), 1318 PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2), 1319 PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A), 1320 PINMUX_IPSR_MSEL(IP14_3_0, TCLK1_B, SEL_TIMER_TMU1_1), 1321 1322 PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2), 1323 PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0), 1324 PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3), 1325 PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADGC_0), 1326 PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI2_0), 1327 PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3), 1328 PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D), 1329 PINMUX_IPSR_MSEL(IP14_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1), 1330 1331 PINMUX_IPSR_GPSR(IP14_11_8, MLB_CLK), 1332 PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SCK_F, SEL_MSIOF1_5), 1333 PINMUX_IPSR_MSEL(IP14_11_8, SCL1_B, SEL_I2C1_1), 1334 1335 PINMUX_IPSR_GPSR(IP14_15_12, MLB_SIG), 1336 PINMUX_IPSR_MSEL(IP14_15_12, RX1_B, SEL_SCIF1_1), 1337 PINMUX_IPSR_MSEL(IP14_15_12, MSIOF1_SYNC_F, SEL_MSIOF1_5), 1338 PINMUX_IPSR_MSEL(IP14_15_12, SDA1_B, SEL_I2C1_1), 1339 1340 PINMUX_IPSR_GPSR(IP14_19_16, MLB_DAT), 1341 PINMUX_IPSR_MSEL(IP14_19_16, TX1_B, SEL_SCIF1_1), 1342 PINMUX_IPSR_MSEL(IP14_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5), 1343 1344 PINMUX_IPSR_GPSR(IP14_23_20, SSI_SCK01239), 1345 PINMUX_IPSR_MSEL(IP14_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5), 1346 1347 PINMUX_IPSR_GPSR(IP14_27_24, SSI_WS01239), 1348 PINMUX_IPSR_MSEL(IP14_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5), 1349 1350 PINMUX_IPSR_GPSR(IP14_31_28, SSI_SDATA0), 1351 PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5), 1352 1353 /* IPSR15 */ 1354 PINMUX_IPSR_MSEL(IP15_3_0, SSI_SDATA1_A, SEL_SSI1_0), 1355 1356 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SDATA2_A, SEL_SSI2_0), 1357 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SCK1_B, SEL_SSI1_1), 1358 1359 PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK349), 1360 PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0), 1361 PINMUX_IPSR_MSEL(IP15_11_8, STP_OPWM_0_A, SEL_SSP1_0_0), 1362 1363 PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS349), 1364 PINMUX_IPSR_MSEL(IP15_15_12, HCTS2_N_A, SEL_HSCIF2_0), 1365 PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0), 1366 PINMUX_IPSR_MSEL(IP15_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0), 1367 1368 PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA3), 1369 PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0), 1370 PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_TXD_A, SEL_MSIOF1_0), 1371 PINMUX_IPSR_MSEL(IP15_19_16, TS_SCK0_A, SEL_TSIF0_0), 1372 PINMUX_IPSR_MSEL(IP15_19_16, STP_ISCLK_0_A, SEL_SSP1_0_0), 1373 PINMUX_IPSR_MSEL(IP15_19_16, RIF0_D1_A, SEL_DRIF0_0), 1374 PINMUX_IPSR_MSEL(IP15_19_16, RIF2_D0_A, SEL_DRIF2_0), 1375 1376 PINMUX_IPSR_GPSR(IP15_23_20, SSI_SCK4), 1377 PINMUX_IPSR_MSEL(IP15_23_20, HRX2_A, SEL_HSCIF2_0), 1378 PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_SCK_A, SEL_MSIOF1_0), 1379 PINMUX_IPSR_MSEL(IP15_23_20, TS_SDAT0_A, SEL_TSIF0_0), 1380 PINMUX_IPSR_MSEL(IP15_23_20, STP_ISD_0_A, SEL_SSP1_0_0), 1381 PINMUX_IPSR_MSEL(IP15_23_20, RIF0_CLK_A, SEL_DRIF0_0), 1382 PINMUX_IPSR_MSEL(IP15_23_20, RIF2_CLK_A, SEL_DRIF2_0), 1383 1384 PINMUX_IPSR_GPSR(IP15_27_24, SSI_WS4), 1385 PINMUX_IPSR_MSEL(IP15_27_24, HTX2_A, SEL_HSCIF2_0), 1386 PINMUX_IPSR_MSEL(IP15_27_24, MSIOF1_SYNC_A, SEL_MSIOF1_0), 1387 PINMUX_IPSR_MSEL(IP15_27_24, TS_SDEN0_A, SEL_TSIF0_0), 1388 PINMUX_IPSR_MSEL(IP15_27_24, STP_ISEN_0_A, SEL_SSP1_0_0), 1389 PINMUX_IPSR_MSEL(IP15_27_24, RIF0_SYNC_A, SEL_DRIF0_0), 1390 PINMUX_IPSR_MSEL(IP15_27_24, RIF2_SYNC_A, SEL_DRIF2_0), 1391 1392 PINMUX_IPSR_GPSR(IP15_31_28, SSI_SDATA4), 1393 PINMUX_IPSR_MSEL(IP15_31_28, HSCK2_A, SEL_HSCIF2_0), 1394 PINMUX_IPSR_MSEL(IP15_31_28, MSIOF1_RXD_A, SEL_MSIOF1_0), 1395 PINMUX_IPSR_MSEL(IP15_31_28, TS_SPSYNC0_A, SEL_TSIF0_0), 1396 PINMUX_IPSR_MSEL(IP15_31_28, STP_ISSYNC_0_A, SEL_SSP1_0_0), 1397 PINMUX_IPSR_MSEL(IP15_31_28, RIF0_D0_A, SEL_DRIF0_0), 1398 PINMUX_IPSR_MSEL(IP15_31_28, RIF2_D1_A, SEL_DRIF2_0), 1399 1400 /* IPSR16 */ 1401 PINMUX_IPSR_GPSR(IP16_3_0, SSI_SCK6), 1402 PINMUX_IPSR_GPSR(IP16_3_0, USB2_PWEN), 1403 PINMUX_IPSR_MSEL(IP16_3_0, SIM0_RST_D, SEL_SIMCARD_3), 1404 1405 PINMUX_IPSR_GPSR(IP16_7_4, SSI_WS6), 1406 PINMUX_IPSR_GPSR(IP16_7_4, USB2_OVC), 1407 PINMUX_IPSR_MSEL(IP16_7_4, SIM0_D_D, SEL_SIMCARD_3), 1408 1409 PINMUX_IPSR_GPSR(IP16_11_8, SSI_SDATA6), 1410 PINMUX_IPSR_MSEL(IP16_11_8, SIM0_CLK_D, SEL_SIMCARD_3), 1411 PINMUX_IPSR_GPSR(IP16_11_8, SATA_DEVSLP_A), 1412 1413 PINMUX_IPSR_GPSR(IP16_15_12, SSI_SCK78), 1414 PINMUX_IPSR_MSEL(IP16_15_12, HRX2_B, SEL_HSCIF2_1), 1415 PINMUX_IPSR_MSEL(IP16_15_12, MSIOF1_SCK_C, SEL_MSIOF1_2), 1416 PINMUX_IPSR_MSEL(IP16_15_12, TS_SCK1_A, SEL_TSIF1_0), 1417 PINMUX_IPSR_MSEL(IP16_15_12, STP_ISCLK_1_A, SEL_SSP1_1_0), 1418 PINMUX_IPSR_MSEL(IP16_15_12, RIF1_CLK_A, SEL_DRIF1_0), 1419 PINMUX_IPSR_MSEL(IP16_15_12, RIF3_CLK_A, SEL_DRIF3_0), 1420 1421 PINMUX_IPSR_GPSR(IP16_19_16, SSI_WS78), 1422 PINMUX_IPSR_MSEL(IP16_19_16, HTX2_B, SEL_HSCIF2_1), 1423 PINMUX_IPSR_MSEL(IP16_19_16, MSIOF1_SYNC_C, SEL_MSIOF1_2), 1424 PINMUX_IPSR_MSEL(IP16_19_16, TS_SDAT1_A, SEL_TSIF1_0), 1425 PINMUX_IPSR_MSEL(IP16_19_16, STP_ISD_1_A, SEL_SSP1_1_0), 1426 PINMUX_IPSR_MSEL(IP16_19_16, RIF1_SYNC_A, SEL_DRIF1_0), 1427 PINMUX_IPSR_MSEL(IP16_19_16, RIF3_SYNC_A, SEL_DRIF3_0), 1428 1429 PINMUX_IPSR_GPSR(IP16_23_20, SSI_SDATA7), 1430 PINMUX_IPSR_MSEL(IP16_23_20, HCTS2_N_B, SEL_HSCIF2_1), 1431 PINMUX_IPSR_MSEL(IP16_23_20, MSIOF1_RXD_C, SEL_MSIOF1_2), 1432 PINMUX_IPSR_MSEL(IP16_23_20, TS_SDEN1_A, SEL_TSIF1_0), 1433 PINMUX_IPSR_MSEL(IP16_23_20, STP_ISEN_1_A, SEL_SSP1_1_0), 1434 PINMUX_IPSR_MSEL(IP16_23_20, RIF1_D0_A, SEL_DRIF1_0), 1435 PINMUX_IPSR_MSEL(IP16_23_20, RIF3_D0_A, SEL_DRIF3_0), 1436 PINMUX_IPSR_MSEL(IP16_23_20, TCLK2_A, SEL_TIMER_TMU2_0), 1437 1438 PINMUX_IPSR_GPSR(IP16_27_24, SSI_SDATA8), 1439 PINMUX_IPSR_MSEL(IP16_27_24, HRTS2_N_B, SEL_HSCIF2_1), 1440 PINMUX_IPSR_MSEL(IP16_27_24, MSIOF1_TXD_C, SEL_MSIOF1_2), 1441 PINMUX_IPSR_MSEL(IP16_27_24, TS_SPSYNC1_A, SEL_TSIF1_0), 1442 PINMUX_IPSR_MSEL(IP16_27_24, STP_ISSYNC_1_A, SEL_SSP1_1_0), 1443 PINMUX_IPSR_MSEL(IP16_27_24, RIF1_D1_A, SEL_DRIF1_0), 1444 PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D1_A, SEL_DRIF3_0), 1445 1446 PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA9_A, SEL_SSI9_0), 1447 PINMUX_IPSR_MSEL(IP16_31_28, HSCK2_B, SEL_HSCIF2_1), 1448 PINMUX_IPSR_MSEL(IP16_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2), 1449 PINMUX_IPSR_MSEL(IP16_31_28, HSCK1_A, SEL_HSCIF1_0), 1450 PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI1_1), 1451 PINMUX_IPSR_GPSR(IP16_31_28, SCK1), 1452 PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0), 1453 PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0), 1454 1455 /* IPSR17 */ 1456 PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADGA_0), 1457 1458 PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADGB_1), 1459 PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0), 1460 PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3), 1461 PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0), 1462 PINMUX_IPSR_MSEL(IP17_7_4, TCLK1_A, SEL_TIMER_TMU1_0), 1463 1464 PINMUX_IPSR_GPSR(IP17_11_8, USB0_PWEN), 1465 PINMUX_IPSR_MSEL(IP17_11_8, SIM0_RST_C, SEL_SIMCARD_2), 1466 PINMUX_IPSR_MSEL(IP17_11_8, TS_SCK1_D, SEL_TSIF1_3), 1467 PINMUX_IPSR_MSEL(IP17_11_8, STP_ISCLK_1_D, SEL_SSP1_1_3), 1468 PINMUX_IPSR_MSEL(IP17_11_8, BPFCLK_B, SEL_FM_1), 1469 PINMUX_IPSR_MSEL(IP17_11_8, RIF3_CLK_B, SEL_DRIF3_1), 1470 PINMUX_IPSR_MSEL(IP17_11_8, HSCK2_C, SEL_HSCIF2_2), 1471 1472 PINMUX_IPSR_GPSR(IP17_15_12, USB0_OVC), 1473 PINMUX_IPSR_MSEL(IP17_15_12, SIM0_D_C, SEL_SIMCARD_2), 1474 PINMUX_IPSR_MSEL(IP17_15_12, TS_SDAT1_D, SEL_TSIF1_3), 1475 PINMUX_IPSR_MSEL(IP17_15_12, STP_ISD_1_D, SEL_SSP1_1_3), 1476 PINMUX_IPSR_MSEL(IP17_15_12, RIF3_SYNC_B, SEL_DRIF3_1), 1477 PINMUX_IPSR_MSEL(IP17_15_12, HRX2_C, SEL_HSCIF2_2), 1478 1479 PINMUX_IPSR_GPSR(IP17_19_16, USB1_PWEN), 1480 PINMUX_IPSR_MSEL(IP17_19_16, SIM0_CLK_C, SEL_SIMCARD_2), 1481 PINMUX_IPSR_MSEL(IP17_19_16, SSI_SCK1_A, SEL_SSI1_0), 1482 PINMUX_IPSR_MSEL(IP17_19_16, TS_SCK0_E, SEL_TSIF0_4), 1483 PINMUX_IPSR_MSEL(IP17_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4), 1484 PINMUX_IPSR_MSEL(IP17_19_16, FMCLK_B, SEL_FM_1), 1485 PINMUX_IPSR_MSEL(IP17_19_16, RIF2_CLK_B, SEL_DRIF2_1), 1486 PINMUX_IPSR_MSEL(IP17_19_16, SPEEDIN_A, SEL_SPEED_PULSE_0), 1487 PINMUX_IPSR_MSEL(IP17_19_16, HTX2_C, SEL_HSCIF2_2), 1488 1489 PINMUX_IPSR_GPSR(IP17_23_20, USB1_OVC), 1490 PINMUX_IPSR_MSEL(IP17_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2), 1491 PINMUX_IPSR_MSEL(IP17_23_20, SSI_WS1_A, SEL_SSI1_0), 1492 PINMUX_IPSR_MSEL(IP17_23_20, TS_SDAT0_E, SEL_TSIF0_4), 1493 PINMUX_IPSR_MSEL(IP17_23_20, STP_ISD_0_E, SEL_SSP1_0_4), 1494 PINMUX_IPSR_MSEL(IP17_23_20, FMIN_B, SEL_FM_1), 1495 PINMUX_IPSR_MSEL(IP17_23_20, RIF2_SYNC_B, SEL_DRIF2_1), 1496 PINMUX_IPSR_MSEL(IP17_23_20, REMOCON_B, SEL_REMOCON_1), 1497 PINMUX_IPSR_MSEL(IP17_23_20, HCTS2_N_C, SEL_HSCIF2_2), 1498 1499 PINMUX_IPSR_GPSR(IP17_27_24, USB30_PWEN), 1500 PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_B), 1501 PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI2_1), 1502 PINMUX_IPSR_MSEL(IP17_27_24, TS_SDEN1_D, SEL_TSIF1_3), 1503 PINMUX_IPSR_MSEL(IP17_27_24, STP_ISEN_1_D, SEL_SSP1_1_3), 1504 PINMUX_IPSR_MSEL(IP17_27_24, STP_OPWM_0_E, SEL_SSP1_0_4), 1505 PINMUX_IPSR_MSEL(IP17_27_24, RIF3_D0_B, SEL_DRIF3_1), 1506 PINMUX_IPSR_MSEL(IP17_27_24, TCLK2_B, SEL_TIMER_TMU2_1), 1507 PINMUX_IPSR_GPSR(IP17_27_24, TPU0TO0), 1508 PINMUX_IPSR_MSEL(IP17_27_24, BPFCLK_C, SEL_FM_2), 1509 PINMUX_IPSR_MSEL(IP17_27_24, HRTS2_N_C, SEL_HSCIF2_2), 1510 1511 PINMUX_IPSR_GPSR(IP17_31_28, USB30_OVC), 1512 PINMUX_IPSR_GPSR(IP17_31_28, AUDIO_CLKOUT1_B), 1513 PINMUX_IPSR_MSEL(IP17_31_28, SSI_WS2_B, SEL_SSI2_1), 1514 PINMUX_IPSR_MSEL(IP17_31_28, TS_SPSYNC1_D, SEL_TSIF1_3), 1515 PINMUX_IPSR_MSEL(IP17_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3), 1516 PINMUX_IPSR_MSEL(IP17_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4), 1517 PINMUX_IPSR_MSEL(IP17_31_28, RIF3_D1_B, SEL_DRIF3_1), 1518 PINMUX_IPSR_GPSR(IP17_31_28, FSO_TOE_N), 1519 PINMUX_IPSR_GPSR(IP17_31_28, TPU0TO1), 1520 1521 /* IPSR18 */ 1522 PINMUX_IPSR_GPSR(IP18_3_0, USB2_CH3_PWEN), 1523 PINMUX_IPSR_GPSR(IP18_3_0, AUDIO_CLKOUT2_B), 1524 PINMUX_IPSR_MSEL(IP18_3_0, SSI_SCK9_B, SEL_SSI9_1), 1525 PINMUX_IPSR_MSEL(IP18_3_0, TS_SDEN0_E, SEL_TSIF0_4), 1526 PINMUX_IPSR_MSEL(IP18_3_0, STP_ISEN_0_E, SEL_SSP1_0_4), 1527 PINMUX_IPSR_MSEL(IP18_3_0, RIF2_D0_B, SEL_DRIF2_1), 1528 PINMUX_IPSR_GPSR(IP18_3_0, TPU0TO2), 1529 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_C, SEL_FM_2), 1530 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_D, SEL_FM_3), 1531 1532 PINMUX_IPSR_GPSR(IP18_7_4, USB2_CH3_OVC), 1533 PINMUX_IPSR_GPSR(IP18_7_4, AUDIO_CLKOUT3_B), 1534 PINMUX_IPSR_MSEL(IP18_7_4, SSI_WS9_B, SEL_SSI9_1), 1535 PINMUX_IPSR_MSEL(IP18_7_4, TS_SPSYNC0_E, SEL_TSIF0_4), 1536 PINMUX_IPSR_MSEL(IP18_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4), 1537 PINMUX_IPSR_MSEL(IP18_7_4, RIF2_D1_B, SEL_DRIF2_1), 1538 PINMUX_IPSR_GPSR(IP18_7_4, TPU0TO3), 1539 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_C, SEL_FM_2), 1540 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_D, SEL_FM_3), 1541 1542 /* 1543 * Static pins can not be muxed between different functions but 1544 * still need mark entries in the pinmux list. Add each static 1545 * pin to the list without an associated function. The sh-pfc 1546 * core will do the right thing and skip trying to mux the pin 1547 * while still applying configuration to it. 1548 */ 1549 #define FM(x) PINMUX_DATA(x##_MARK, 0), 1550 PINMUX_STATIC 1551 #undef FM 1552 }; 1553 1554 /* 1555 * Pins not associated with a GPIO port. 1556 */ 1557 enum { 1558 GP_ASSIGN_LAST(), 1559 NOGP_ALL(), 1560 }; 1561 1562 static const struct sh_pfc_pin pinmux_pins[] = { 1563 PINMUX_GPIO_GP_ALL(), 1564 PINMUX_NOGP_ALL(), 1565 }; 1566 1567 /* - AUDIO CLOCK ------------------------------------------------------------ */ 1568 static const unsigned int audio_clk_a_a_pins[] = { 1569 /* CLK A */ 1570 RCAR_GP_PIN(6, 22), 1571 }; 1572 static const unsigned int audio_clk_a_a_mux[] = { 1573 AUDIO_CLKA_A_MARK, 1574 }; 1575 static const unsigned int audio_clk_a_b_pins[] = { 1576 /* CLK A */ 1577 RCAR_GP_PIN(5, 4), 1578 }; 1579 static const unsigned int audio_clk_a_b_mux[] = { 1580 AUDIO_CLKA_B_MARK, 1581 }; 1582 static const unsigned int audio_clk_a_c_pins[] = { 1583 /* CLK A */ 1584 RCAR_GP_PIN(5, 19), 1585 }; 1586 static const unsigned int audio_clk_a_c_mux[] = { 1587 AUDIO_CLKA_C_MARK, 1588 }; 1589 static const unsigned int audio_clk_b_a_pins[] = { 1590 /* CLK B */ 1591 RCAR_GP_PIN(5, 12), 1592 }; 1593 static const unsigned int audio_clk_b_a_mux[] = { 1594 AUDIO_CLKB_A_MARK, 1595 }; 1596 static const unsigned int audio_clk_b_b_pins[] = { 1597 /* CLK B */ 1598 RCAR_GP_PIN(6, 23), 1599 }; 1600 static const unsigned int audio_clk_b_b_mux[] = { 1601 AUDIO_CLKB_B_MARK, 1602 }; 1603 static const unsigned int audio_clk_c_a_pins[] = { 1604 /* CLK C */ 1605 RCAR_GP_PIN(5, 21), 1606 }; 1607 static const unsigned int audio_clk_c_a_mux[] = { 1608 AUDIO_CLKC_A_MARK, 1609 }; 1610 static const unsigned int audio_clk_c_b_pins[] = { 1611 /* CLK C */ 1612 RCAR_GP_PIN(5, 0), 1613 }; 1614 static const unsigned int audio_clk_c_b_mux[] = { 1615 AUDIO_CLKC_B_MARK, 1616 }; 1617 static const unsigned int audio_clkout_a_pins[] = { 1618 /* CLKOUT */ 1619 RCAR_GP_PIN(5, 18), 1620 }; 1621 static const unsigned int audio_clkout_a_mux[] = { 1622 AUDIO_CLKOUT_A_MARK, 1623 }; 1624 static const unsigned int audio_clkout_b_pins[] = { 1625 /* CLKOUT */ 1626 RCAR_GP_PIN(6, 28), 1627 }; 1628 static const unsigned int audio_clkout_b_mux[] = { 1629 AUDIO_CLKOUT_B_MARK, 1630 }; 1631 static const unsigned int audio_clkout_c_pins[] = { 1632 /* CLKOUT */ 1633 RCAR_GP_PIN(5, 3), 1634 }; 1635 static const unsigned int audio_clkout_c_mux[] = { 1636 AUDIO_CLKOUT_C_MARK, 1637 }; 1638 static const unsigned int audio_clkout_d_pins[] = { 1639 /* CLKOUT */ 1640 RCAR_GP_PIN(5, 21), 1641 }; 1642 static const unsigned int audio_clkout_d_mux[] = { 1643 AUDIO_CLKOUT_D_MARK, 1644 }; 1645 static const unsigned int audio_clkout1_a_pins[] = { 1646 /* CLKOUT1 */ 1647 RCAR_GP_PIN(5, 15), 1648 }; 1649 static const unsigned int audio_clkout1_a_mux[] = { 1650 AUDIO_CLKOUT1_A_MARK, 1651 }; 1652 static const unsigned int audio_clkout1_b_pins[] = { 1653 /* CLKOUT1 */ 1654 RCAR_GP_PIN(6, 29), 1655 }; 1656 static const unsigned int audio_clkout1_b_mux[] = { 1657 AUDIO_CLKOUT1_B_MARK, 1658 }; 1659 static const unsigned int audio_clkout2_a_pins[] = { 1660 /* CLKOUT2 */ 1661 RCAR_GP_PIN(5, 16), 1662 }; 1663 static const unsigned int audio_clkout2_a_mux[] = { 1664 AUDIO_CLKOUT2_A_MARK, 1665 }; 1666 static const unsigned int audio_clkout2_b_pins[] = { 1667 /* CLKOUT2 */ 1668 RCAR_GP_PIN(6, 30), 1669 }; 1670 static const unsigned int audio_clkout2_b_mux[] = { 1671 AUDIO_CLKOUT2_B_MARK, 1672 }; 1673 static const unsigned int audio_clkout3_a_pins[] = { 1674 /* CLKOUT3 */ 1675 RCAR_GP_PIN(5, 19), 1676 }; 1677 static const unsigned int audio_clkout3_a_mux[] = { 1678 AUDIO_CLKOUT3_A_MARK, 1679 }; 1680 static const unsigned int audio_clkout3_b_pins[] = { 1681 /* CLKOUT3 */ 1682 RCAR_GP_PIN(6, 31), 1683 }; 1684 static const unsigned int audio_clkout3_b_mux[] = { 1685 AUDIO_CLKOUT3_B_MARK, 1686 }; 1687 1688 /* - EtherAVB --------------------------------------------------------------- */ 1689 static const unsigned int avb_link_pins[] = { 1690 /* AVB_LINK */ 1691 RCAR_GP_PIN(2, 12), 1692 }; 1693 static const unsigned int avb_link_mux[] = { 1694 AVB_LINK_MARK, 1695 }; 1696 static const unsigned int avb_magic_pins[] = { 1697 /* AVB_MAGIC_ */ 1698 RCAR_GP_PIN(2, 10), 1699 }; 1700 static const unsigned int avb_magic_mux[] = { 1701 AVB_MAGIC_MARK, 1702 }; 1703 static const unsigned int avb_phy_int_pins[] = { 1704 /* AVB_PHY_INT */ 1705 RCAR_GP_PIN(2, 11), 1706 }; 1707 static const unsigned int avb_phy_int_mux[] = { 1708 AVB_PHY_INT_MARK, 1709 }; 1710 static const unsigned int avb_mdio_pins[] = { 1711 /* AVB_MDC, AVB_MDIO */ 1712 RCAR_GP_PIN(2, 9), PIN_AVB_MDIO, 1713 }; 1714 static const unsigned int avb_mdio_mux[] = { 1715 AVB_MDC_MARK, AVB_MDIO_MARK, 1716 }; 1717 static const unsigned int avb_mii_pins[] = { 1718 /* 1719 * AVB_TX_CTL, AVB_TXC, AVB_TD0, 1720 * AVB_TD1, AVB_TD2, AVB_TD3, 1721 * AVB_RX_CTL, AVB_RXC, AVB_RD0, 1722 * AVB_RD1, AVB_RD2, AVB_RD3, 1723 * AVB_TXCREFCLK 1724 */ 1725 PIN_AVB_TX_CTL, PIN_AVB_TXC, PIN_AVB_TD0, 1726 PIN_AVB_TD1, PIN_AVB_TD2, PIN_AVB_TD3, 1727 PIN_AVB_RX_CTL, PIN_AVB_RXC, PIN_AVB_RD0, 1728 PIN_AVB_RD1, PIN_AVB_RD2, PIN_AVB_RD3, 1729 PIN_AVB_TXCREFCLK, 1730 }; 1731 static const unsigned int avb_mii_mux[] = { 1732 AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK, 1733 AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK, 1734 AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK, 1735 AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK, 1736 AVB_TXCREFCLK_MARK, 1737 }; 1738 static const unsigned int avb_avtp_pps_pins[] = { 1739 /* AVB_AVTP_PPS */ 1740 RCAR_GP_PIN(2, 6), 1741 }; 1742 static const unsigned int avb_avtp_pps_mux[] = { 1743 AVB_AVTP_PPS_MARK, 1744 }; 1745 static const unsigned int avb_avtp_match_a_pins[] = { 1746 /* AVB_AVTP_MATCH_A */ 1747 RCAR_GP_PIN(2, 13), 1748 }; 1749 static const unsigned int avb_avtp_match_a_mux[] = { 1750 AVB_AVTP_MATCH_A_MARK, 1751 }; 1752 static const unsigned int avb_avtp_capture_a_pins[] = { 1753 /* AVB_AVTP_CAPTURE_A */ 1754 RCAR_GP_PIN(2, 14), 1755 }; 1756 static const unsigned int avb_avtp_capture_a_mux[] = { 1757 AVB_AVTP_CAPTURE_A_MARK, 1758 }; 1759 static const unsigned int avb_avtp_match_b_pins[] = { 1760 /* AVB_AVTP_MATCH_B */ 1761 RCAR_GP_PIN(1, 8), 1762 }; 1763 static const unsigned int avb_avtp_match_b_mux[] = { 1764 AVB_AVTP_MATCH_B_MARK, 1765 }; 1766 static const unsigned int avb_avtp_capture_b_pins[] = { 1767 /* AVB_AVTP_CAPTURE_B */ 1768 RCAR_GP_PIN(1, 11), 1769 }; 1770 static const unsigned int avb_avtp_capture_b_mux[] = { 1771 AVB_AVTP_CAPTURE_B_MARK, 1772 }; 1773 1774 /* - CAN ------------------------------------------------------------------ */ 1775 static const unsigned int can0_data_a_pins[] = { 1776 /* TX, RX */ 1777 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24), 1778 }; 1779 static const unsigned int can0_data_a_mux[] = { 1780 CAN0_TX_A_MARK, CAN0_RX_A_MARK, 1781 }; 1782 static const unsigned int can0_data_b_pins[] = { 1783 /* TX, RX */ 1784 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), 1785 }; 1786 static const unsigned int can0_data_b_mux[] = { 1787 CAN0_TX_B_MARK, CAN0_RX_B_MARK, 1788 }; 1789 static const unsigned int can1_data_pins[] = { 1790 /* TX, RX */ 1791 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26), 1792 }; 1793 static const unsigned int can1_data_mux[] = { 1794 CAN1_TX_MARK, CAN1_RX_MARK, 1795 }; 1796 1797 /* - CAN Clock -------------------------------------------------------------- */ 1798 static const unsigned int can_clk_pins[] = { 1799 /* CLK */ 1800 RCAR_GP_PIN(1, 25), 1801 }; 1802 static const unsigned int can_clk_mux[] = { 1803 CAN_CLK_MARK, 1804 }; 1805 1806 /* - CAN FD --------------------------------------------------------------- */ 1807 static const unsigned int canfd0_data_a_pins[] = { 1808 /* TX, RX */ 1809 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24), 1810 }; 1811 static const unsigned int canfd0_data_a_mux[] = { 1812 CANFD0_TX_A_MARK, CANFD0_RX_A_MARK, 1813 }; 1814 static const unsigned int canfd0_data_b_pins[] = { 1815 /* TX, RX */ 1816 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), 1817 }; 1818 static const unsigned int canfd0_data_b_mux[] = { 1819 CANFD0_TX_B_MARK, CANFD0_RX_B_MARK, 1820 }; 1821 static const unsigned int canfd1_data_pins[] = { 1822 /* TX, RX */ 1823 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26), 1824 }; 1825 static const unsigned int canfd1_data_mux[] = { 1826 CANFD1_TX_MARK, CANFD1_RX_MARK, 1827 }; 1828 1829 #ifdef CONFIG_PINCTRL_PFC_R8A77951 1830 /* - DRIF0 --------------------------------------------------------------- */ 1831 static const unsigned int drif0_ctrl_a_pins[] = { 1832 /* CLK, SYNC */ 1833 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), 1834 }; 1835 static const unsigned int drif0_ctrl_a_mux[] = { 1836 RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK, 1837 }; 1838 static const unsigned int drif0_data0_a_pins[] = { 1839 /* D0 */ 1840 RCAR_GP_PIN(6, 10), 1841 }; 1842 static const unsigned int drif0_data0_a_mux[] = { 1843 RIF0_D0_A_MARK, 1844 }; 1845 static const unsigned int drif0_data1_a_pins[] = { 1846 /* D1 */ 1847 RCAR_GP_PIN(6, 7), 1848 }; 1849 static const unsigned int drif0_data1_a_mux[] = { 1850 RIF0_D1_A_MARK, 1851 }; 1852 static const unsigned int drif0_ctrl_b_pins[] = { 1853 /* CLK, SYNC */ 1854 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4), 1855 }; 1856 static const unsigned int drif0_ctrl_b_mux[] = { 1857 RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK, 1858 }; 1859 static const unsigned int drif0_data0_b_pins[] = { 1860 /* D0 */ 1861 RCAR_GP_PIN(5, 1), 1862 }; 1863 static const unsigned int drif0_data0_b_mux[] = { 1864 RIF0_D0_B_MARK, 1865 }; 1866 static const unsigned int drif0_data1_b_pins[] = { 1867 /* D1 */ 1868 RCAR_GP_PIN(5, 2), 1869 }; 1870 static const unsigned int drif0_data1_b_mux[] = { 1871 RIF0_D1_B_MARK, 1872 }; 1873 static const unsigned int drif0_ctrl_c_pins[] = { 1874 /* CLK, SYNC */ 1875 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15), 1876 }; 1877 static const unsigned int drif0_ctrl_c_mux[] = { 1878 RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK, 1879 }; 1880 static const unsigned int drif0_data0_c_pins[] = { 1881 /* D0 */ 1882 RCAR_GP_PIN(5, 13), 1883 }; 1884 static const unsigned int drif0_data0_c_mux[] = { 1885 RIF0_D0_C_MARK, 1886 }; 1887 static const unsigned int drif0_data1_c_pins[] = { 1888 /* D1 */ 1889 RCAR_GP_PIN(5, 14), 1890 }; 1891 static const unsigned int drif0_data1_c_mux[] = { 1892 RIF0_D1_C_MARK, 1893 }; 1894 /* - DRIF1 --------------------------------------------------------------- */ 1895 static const unsigned int drif1_ctrl_a_pins[] = { 1896 /* CLK, SYNC */ 1897 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18), 1898 }; 1899 static const unsigned int drif1_ctrl_a_mux[] = { 1900 RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK, 1901 }; 1902 static const unsigned int drif1_data0_a_pins[] = { 1903 /* D0 */ 1904 RCAR_GP_PIN(6, 19), 1905 }; 1906 static const unsigned int drif1_data0_a_mux[] = { 1907 RIF1_D0_A_MARK, 1908 }; 1909 static const unsigned int drif1_data1_a_pins[] = { 1910 /* D1 */ 1911 RCAR_GP_PIN(6, 20), 1912 }; 1913 static const unsigned int drif1_data1_a_mux[] = { 1914 RIF1_D1_A_MARK, 1915 }; 1916 static const unsigned int drif1_ctrl_b_pins[] = { 1917 /* CLK, SYNC */ 1918 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3), 1919 }; 1920 static const unsigned int drif1_ctrl_b_mux[] = { 1921 RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK, 1922 }; 1923 static const unsigned int drif1_data0_b_pins[] = { 1924 /* D0 */ 1925 RCAR_GP_PIN(5, 7), 1926 }; 1927 static const unsigned int drif1_data0_b_mux[] = { 1928 RIF1_D0_B_MARK, 1929 }; 1930 static const unsigned int drif1_data1_b_pins[] = { 1931 /* D1 */ 1932 RCAR_GP_PIN(5, 8), 1933 }; 1934 static const unsigned int drif1_data1_b_mux[] = { 1935 RIF1_D1_B_MARK, 1936 }; 1937 static const unsigned int drif1_ctrl_c_pins[] = { 1938 /* CLK, SYNC */ 1939 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11), 1940 }; 1941 static const unsigned int drif1_ctrl_c_mux[] = { 1942 RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK, 1943 }; 1944 static const unsigned int drif1_data0_c_pins[] = { 1945 /* D0 */ 1946 RCAR_GP_PIN(5, 6), 1947 }; 1948 static const unsigned int drif1_data0_c_mux[] = { 1949 RIF1_D0_C_MARK, 1950 }; 1951 static const unsigned int drif1_data1_c_pins[] = { 1952 /* D1 */ 1953 RCAR_GP_PIN(5, 10), 1954 }; 1955 static const unsigned int drif1_data1_c_mux[] = { 1956 RIF1_D1_C_MARK, 1957 }; 1958 /* - DRIF2 --------------------------------------------------------------- */ 1959 static const unsigned int drif2_ctrl_a_pins[] = { 1960 /* CLK, SYNC */ 1961 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), 1962 }; 1963 static const unsigned int drif2_ctrl_a_mux[] = { 1964 RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK, 1965 }; 1966 static const unsigned int drif2_data0_a_pins[] = { 1967 /* D0 */ 1968 RCAR_GP_PIN(6, 7), 1969 }; 1970 static const unsigned int drif2_data0_a_mux[] = { 1971 RIF2_D0_A_MARK, 1972 }; 1973 static const unsigned int drif2_data1_a_pins[] = { 1974 /* D1 */ 1975 RCAR_GP_PIN(6, 10), 1976 }; 1977 static const unsigned int drif2_data1_a_mux[] = { 1978 RIF2_D1_A_MARK, 1979 }; 1980 static const unsigned int drif2_ctrl_b_pins[] = { 1981 /* CLK, SYNC */ 1982 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27), 1983 }; 1984 static const unsigned int drif2_ctrl_b_mux[] = { 1985 RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK, 1986 }; 1987 static const unsigned int drif2_data0_b_pins[] = { 1988 /* D0 */ 1989 RCAR_GP_PIN(6, 30), 1990 }; 1991 static const unsigned int drif2_data0_b_mux[] = { 1992 RIF2_D0_B_MARK, 1993 }; 1994 static const unsigned int drif2_data1_b_pins[] = { 1995 /* D1 */ 1996 RCAR_GP_PIN(6, 31), 1997 }; 1998 static const unsigned int drif2_data1_b_mux[] = { 1999 RIF2_D1_B_MARK, 2000 }; 2001 /* - DRIF3 --------------------------------------------------------------- */ 2002 static const unsigned int drif3_ctrl_a_pins[] = { 2003 /* CLK, SYNC */ 2004 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18), 2005 }; 2006 static const unsigned int drif3_ctrl_a_mux[] = { 2007 RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK, 2008 }; 2009 static const unsigned int drif3_data0_a_pins[] = { 2010 /* D0 */ 2011 RCAR_GP_PIN(6, 19), 2012 }; 2013 static const unsigned int drif3_data0_a_mux[] = { 2014 RIF3_D0_A_MARK, 2015 }; 2016 static const unsigned int drif3_data1_a_pins[] = { 2017 /* D1 */ 2018 RCAR_GP_PIN(6, 20), 2019 }; 2020 static const unsigned int drif3_data1_a_mux[] = { 2021 RIF3_D1_A_MARK, 2022 }; 2023 static const unsigned int drif3_ctrl_b_pins[] = { 2024 /* CLK, SYNC */ 2025 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25), 2026 }; 2027 static const unsigned int drif3_ctrl_b_mux[] = { 2028 RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK, 2029 }; 2030 static const unsigned int drif3_data0_b_pins[] = { 2031 /* D0 */ 2032 RCAR_GP_PIN(6, 28), 2033 }; 2034 static const unsigned int drif3_data0_b_mux[] = { 2035 RIF3_D0_B_MARK, 2036 }; 2037 static const unsigned int drif3_data1_b_pins[] = { 2038 /* D1 */ 2039 RCAR_GP_PIN(6, 29), 2040 }; 2041 static const unsigned int drif3_data1_b_mux[] = { 2042 RIF3_D1_B_MARK, 2043 }; 2044 #endif /* CONFIG_PINCTRL_PFC_R8A77951 */ 2045 2046 /* - DU --------------------------------------------------------------------- */ 2047 static const unsigned int du_rgb666_pins[] = { 2048 /* R[7:2], G[7:2], B[7:2] */ 2049 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), 2050 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), 2051 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), 2052 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18), 2053 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5), 2054 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2), 2055 }; 2056 static const unsigned int du_rgb666_mux[] = { 2057 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK, 2058 DU_DR3_MARK, DU_DR2_MARK, 2059 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK, 2060 DU_DG3_MARK, DU_DG2_MARK, 2061 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK, 2062 DU_DB3_MARK, DU_DB2_MARK, 2063 }; 2064 static const unsigned int du_rgb888_pins[] = { 2065 /* R[7:0], G[7:0], B[7:0] */ 2066 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), 2067 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), 2068 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8), 2069 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), 2070 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18), 2071 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16), 2072 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5), 2073 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2), 2074 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0), 2075 }; 2076 static const unsigned int du_rgb888_mux[] = { 2077 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK, 2078 DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK, 2079 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK, 2080 DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK, 2081 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK, 2082 DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK, 2083 }; 2084 static const unsigned int du_clk_out_0_pins[] = { 2085 /* CLKOUT */ 2086 RCAR_GP_PIN(1, 27), 2087 }; 2088 static const unsigned int du_clk_out_0_mux[] = { 2089 DU_DOTCLKOUT0_MARK 2090 }; 2091 static const unsigned int du_clk_out_1_pins[] = { 2092 /* CLKOUT */ 2093 RCAR_GP_PIN(2, 3), 2094 }; 2095 static const unsigned int du_clk_out_1_mux[] = { 2096 DU_DOTCLKOUT1_MARK 2097 }; 2098 static const unsigned int du_sync_pins[] = { 2099 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */ 2100 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4), 2101 }; 2102 static const unsigned int du_sync_mux[] = { 2103 DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK 2104 }; 2105 static const unsigned int du_oddf_pins[] = { 2106 /* EXDISP/EXODDF/EXCDE */ 2107 RCAR_GP_PIN(2, 2), 2108 }; 2109 static const unsigned int du_oddf_mux[] = { 2110 DU_EXODDF_DU_ODDF_DISP_CDE_MARK, 2111 }; 2112 static const unsigned int du_cde_pins[] = { 2113 /* CDE */ 2114 RCAR_GP_PIN(2, 0), 2115 }; 2116 static const unsigned int du_cde_mux[] = { 2117 DU_CDE_MARK, 2118 }; 2119 static const unsigned int du_disp_pins[] = { 2120 /* DISP */ 2121 RCAR_GP_PIN(2, 1), 2122 }; 2123 static const unsigned int du_disp_mux[] = { 2124 DU_DISP_MARK, 2125 }; 2126 2127 /* - HSCIF0 ----------------------------------------------------------------- */ 2128 static const unsigned int hscif0_data_pins[] = { 2129 /* RX, TX */ 2130 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14), 2131 }; 2132 static const unsigned int hscif0_data_mux[] = { 2133 HRX0_MARK, HTX0_MARK, 2134 }; 2135 static const unsigned int hscif0_clk_pins[] = { 2136 /* SCK */ 2137 RCAR_GP_PIN(5, 12), 2138 }; 2139 static const unsigned int hscif0_clk_mux[] = { 2140 HSCK0_MARK, 2141 }; 2142 static const unsigned int hscif0_ctrl_pins[] = { 2143 /* RTS, CTS */ 2144 RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15), 2145 }; 2146 static const unsigned int hscif0_ctrl_mux[] = { 2147 HRTS0_N_MARK, HCTS0_N_MARK, 2148 }; 2149 /* - HSCIF1 ----------------------------------------------------------------- */ 2150 static const unsigned int hscif1_data_a_pins[] = { 2151 /* RX, TX */ 2152 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6), 2153 }; 2154 static const unsigned int hscif1_data_a_mux[] = { 2155 HRX1_A_MARK, HTX1_A_MARK, 2156 }; 2157 static const unsigned int hscif1_clk_a_pins[] = { 2158 /* SCK */ 2159 RCAR_GP_PIN(6, 21), 2160 }; 2161 static const unsigned int hscif1_clk_a_mux[] = { 2162 HSCK1_A_MARK, 2163 }; 2164 static const unsigned int hscif1_ctrl_a_pins[] = { 2165 /* RTS, CTS */ 2166 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7), 2167 }; 2168 static const unsigned int hscif1_ctrl_a_mux[] = { 2169 HRTS1_N_A_MARK, HCTS1_N_A_MARK, 2170 }; 2171 2172 static const unsigned int hscif1_data_b_pins[] = { 2173 /* RX, TX */ 2174 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), 2175 }; 2176 static const unsigned int hscif1_data_b_mux[] = { 2177 HRX1_B_MARK, HTX1_B_MARK, 2178 }; 2179 static const unsigned int hscif1_clk_b_pins[] = { 2180 /* SCK */ 2181 RCAR_GP_PIN(5, 0), 2182 }; 2183 static const unsigned int hscif1_clk_b_mux[] = { 2184 HSCK1_B_MARK, 2185 }; 2186 static const unsigned int hscif1_ctrl_b_pins[] = { 2187 /* RTS, CTS */ 2188 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3), 2189 }; 2190 static const unsigned int hscif1_ctrl_b_mux[] = { 2191 HRTS1_N_B_MARK, HCTS1_N_B_MARK, 2192 }; 2193 /* - HSCIF2 ----------------------------------------------------------------- */ 2194 static const unsigned int hscif2_data_a_pins[] = { 2195 /* RX, TX */ 2196 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), 2197 }; 2198 static const unsigned int hscif2_data_a_mux[] = { 2199 HRX2_A_MARK, HTX2_A_MARK, 2200 }; 2201 static const unsigned int hscif2_clk_a_pins[] = { 2202 /* SCK */ 2203 RCAR_GP_PIN(6, 10), 2204 }; 2205 static const unsigned int hscif2_clk_a_mux[] = { 2206 HSCK2_A_MARK, 2207 }; 2208 static const unsigned int hscif2_ctrl_a_pins[] = { 2209 /* RTS, CTS */ 2210 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6), 2211 }; 2212 static const unsigned int hscif2_ctrl_a_mux[] = { 2213 HRTS2_N_A_MARK, HCTS2_N_A_MARK, 2214 }; 2215 2216 static const unsigned int hscif2_data_b_pins[] = { 2217 /* RX, TX */ 2218 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18), 2219 }; 2220 static const unsigned int hscif2_data_b_mux[] = { 2221 HRX2_B_MARK, HTX2_B_MARK, 2222 }; 2223 static const unsigned int hscif2_clk_b_pins[] = { 2224 /* SCK */ 2225 RCAR_GP_PIN(6, 21), 2226 }; 2227 static const unsigned int hscif2_clk_b_mux[] = { 2228 HSCK2_B_MARK, 2229 }; 2230 static const unsigned int hscif2_ctrl_b_pins[] = { 2231 /* RTS, CTS */ 2232 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19), 2233 }; 2234 static const unsigned int hscif2_ctrl_b_mux[] = { 2235 HRTS2_N_B_MARK, HCTS2_N_B_MARK, 2236 }; 2237 2238 static const unsigned int hscif2_data_c_pins[] = { 2239 /* RX, TX */ 2240 RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26), 2241 }; 2242 static const unsigned int hscif2_data_c_mux[] = { 2243 HRX2_C_MARK, HTX2_C_MARK, 2244 }; 2245 static const unsigned int hscif2_clk_c_pins[] = { 2246 /* SCK */ 2247 RCAR_GP_PIN(6, 24), 2248 }; 2249 static const unsigned int hscif2_clk_c_mux[] = { 2250 HSCK2_C_MARK, 2251 }; 2252 static const unsigned int hscif2_ctrl_c_pins[] = { 2253 /* RTS, CTS */ 2254 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 27), 2255 }; 2256 static const unsigned int hscif2_ctrl_c_mux[] = { 2257 HRTS2_N_C_MARK, HCTS2_N_C_MARK, 2258 }; 2259 /* - HSCIF3 ----------------------------------------------------------------- */ 2260 static const unsigned int hscif3_data_a_pins[] = { 2261 /* RX, TX */ 2262 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24), 2263 }; 2264 static const unsigned int hscif3_data_a_mux[] = { 2265 HRX3_A_MARK, HTX3_A_MARK, 2266 }; 2267 static const unsigned int hscif3_clk_pins[] = { 2268 /* SCK */ 2269 RCAR_GP_PIN(1, 22), 2270 }; 2271 static const unsigned int hscif3_clk_mux[] = { 2272 HSCK3_MARK, 2273 }; 2274 static const unsigned int hscif3_ctrl_pins[] = { 2275 /* RTS, CTS */ 2276 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25), 2277 }; 2278 static const unsigned int hscif3_ctrl_mux[] = { 2279 HRTS3_N_MARK, HCTS3_N_MARK, 2280 }; 2281 2282 static const unsigned int hscif3_data_b_pins[] = { 2283 /* RX, TX */ 2284 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), 2285 }; 2286 static const unsigned int hscif3_data_b_mux[] = { 2287 HRX3_B_MARK, HTX3_B_MARK, 2288 }; 2289 static const unsigned int hscif3_data_c_pins[] = { 2290 /* RX, TX */ 2291 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), 2292 }; 2293 static const unsigned int hscif3_data_c_mux[] = { 2294 HRX3_C_MARK, HTX3_C_MARK, 2295 }; 2296 static const unsigned int hscif3_data_d_pins[] = { 2297 /* RX, TX */ 2298 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), 2299 }; 2300 static const unsigned int hscif3_data_d_mux[] = { 2301 HRX3_D_MARK, HTX3_D_MARK, 2302 }; 2303 /* - HSCIF4 ----------------------------------------------------------------- */ 2304 static const unsigned int hscif4_data_a_pins[] = { 2305 /* RX, TX */ 2306 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), 2307 }; 2308 static const unsigned int hscif4_data_a_mux[] = { 2309 HRX4_A_MARK, HTX4_A_MARK, 2310 }; 2311 static const unsigned int hscif4_clk_pins[] = { 2312 /* SCK */ 2313 RCAR_GP_PIN(1, 11), 2314 }; 2315 static const unsigned int hscif4_clk_mux[] = { 2316 HSCK4_MARK, 2317 }; 2318 static const unsigned int hscif4_ctrl_pins[] = { 2319 /* RTS, CTS */ 2320 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), 2321 }; 2322 static const unsigned int hscif4_ctrl_mux[] = { 2323 HRTS4_N_MARK, HCTS4_N_MARK, 2324 }; 2325 2326 static const unsigned int hscif4_data_b_pins[] = { 2327 /* RX, TX */ 2328 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), 2329 }; 2330 static const unsigned int hscif4_data_b_mux[] = { 2331 HRX4_B_MARK, HTX4_B_MARK, 2332 }; 2333 2334 /* - I2C -------------------------------------------------------------------- */ 2335 static const unsigned int i2c0_pins[] = { 2336 /* SCL, SDA */ 2337 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), 2338 }; 2339 2340 static const unsigned int i2c0_mux[] = { 2341 SCL0_MARK, SDA0_MARK, 2342 }; 2343 2344 static const unsigned int i2c1_a_pins[] = { 2345 /* SDA, SCL */ 2346 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10), 2347 }; 2348 static const unsigned int i2c1_a_mux[] = { 2349 SDA1_A_MARK, SCL1_A_MARK, 2350 }; 2351 static const unsigned int i2c1_b_pins[] = { 2352 /* SDA, SCL */ 2353 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23), 2354 }; 2355 static const unsigned int i2c1_b_mux[] = { 2356 SDA1_B_MARK, SCL1_B_MARK, 2357 }; 2358 static const unsigned int i2c2_a_pins[] = { 2359 /* SDA, SCL */ 2360 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4), 2361 }; 2362 static const unsigned int i2c2_a_mux[] = { 2363 SDA2_A_MARK, SCL2_A_MARK, 2364 }; 2365 static const unsigned int i2c2_b_pins[] = { 2366 /* SDA, SCL */ 2367 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12), 2368 }; 2369 static const unsigned int i2c2_b_mux[] = { 2370 SDA2_B_MARK, SCL2_B_MARK, 2371 }; 2372 2373 static const unsigned int i2c3_pins[] = { 2374 /* SCL, SDA */ 2375 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), 2376 }; 2377 2378 static const unsigned int i2c3_mux[] = { 2379 SCL3_MARK, SDA3_MARK, 2380 }; 2381 2382 static const unsigned int i2c5_pins[] = { 2383 /* SCL, SDA */ 2384 RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14), 2385 }; 2386 2387 static const unsigned int i2c5_mux[] = { 2388 SCL5_MARK, SDA5_MARK, 2389 }; 2390 2391 static const unsigned int i2c6_a_pins[] = { 2392 /* SDA, SCL */ 2393 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), 2394 }; 2395 static const unsigned int i2c6_a_mux[] = { 2396 SDA6_A_MARK, SCL6_A_MARK, 2397 }; 2398 static const unsigned int i2c6_b_pins[] = { 2399 /* SDA, SCL */ 2400 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25), 2401 }; 2402 static const unsigned int i2c6_b_mux[] = { 2403 SDA6_B_MARK, SCL6_B_MARK, 2404 }; 2405 static const unsigned int i2c6_c_pins[] = { 2406 /* SDA, SCL */ 2407 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), 2408 }; 2409 static const unsigned int i2c6_c_mux[] = { 2410 SDA6_C_MARK, SCL6_C_MARK, 2411 }; 2412 2413 /* - INTC-EX ---------------------------------------------------------------- */ 2414 static const unsigned int intc_ex_irq0_pins[] = { 2415 /* IRQ0 */ 2416 RCAR_GP_PIN(2, 0), 2417 }; 2418 static const unsigned int intc_ex_irq0_mux[] = { 2419 IRQ0_MARK, 2420 }; 2421 static const unsigned int intc_ex_irq1_pins[] = { 2422 /* IRQ1 */ 2423 RCAR_GP_PIN(2, 1), 2424 }; 2425 static const unsigned int intc_ex_irq1_mux[] = { 2426 IRQ1_MARK, 2427 }; 2428 static const unsigned int intc_ex_irq2_pins[] = { 2429 /* IRQ2 */ 2430 RCAR_GP_PIN(2, 2), 2431 }; 2432 static const unsigned int intc_ex_irq2_mux[] = { 2433 IRQ2_MARK, 2434 }; 2435 static const unsigned int intc_ex_irq3_pins[] = { 2436 /* IRQ3 */ 2437 RCAR_GP_PIN(2, 3), 2438 }; 2439 static const unsigned int intc_ex_irq3_mux[] = { 2440 IRQ3_MARK, 2441 }; 2442 static const unsigned int intc_ex_irq4_pins[] = { 2443 /* IRQ4 */ 2444 RCAR_GP_PIN(2, 4), 2445 }; 2446 static const unsigned int intc_ex_irq4_mux[] = { 2447 IRQ4_MARK, 2448 }; 2449 static const unsigned int intc_ex_irq5_pins[] = { 2450 /* IRQ5 */ 2451 RCAR_GP_PIN(2, 5), 2452 }; 2453 static const unsigned int intc_ex_irq5_mux[] = { 2454 IRQ5_MARK, 2455 }; 2456 2457 /* - MSIOF0 ----------------------------------------------------------------- */ 2458 static const unsigned int msiof0_clk_pins[] = { 2459 /* SCK */ 2460 RCAR_GP_PIN(5, 17), 2461 }; 2462 static const unsigned int msiof0_clk_mux[] = { 2463 MSIOF0_SCK_MARK, 2464 }; 2465 static const unsigned int msiof0_sync_pins[] = { 2466 /* SYNC */ 2467 RCAR_GP_PIN(5, 18), 2468 }; 2469 static const unsigned int msiof0_sync_mux[] = { 2470 MSIOF0_SYNC_MARK, 2471 }; 2472 static const unsigned int msiof0_ss1_pins[] = { 2473 /* SS1 */ 2474 RCAR_GP_PIN(5, 19), 2475 }; 2476 static const unsigned int msiof0_ss1_mux[] = { 2477 MSIOF0_SS1_MARK, 2478 }; 2479 static const unsigned int msiof0_ss2_pins[] = { 2480 /* SS2 */ 2481 RCAR_GP_PIN(5, 21), 2482 }; 2483 static const unsigned int msiof0_ss2_mux[] = { 2484 MSIOF0_SS2_MARK, 2485 }; 2486 static const unsigned int msiof0_txd_pins[] = { 2487 /* TXD */ 2488 RCAR_GP_PIN(5, 20), 2489 }; 2490 static const unsigned int msiof0_txd_mux[] = { 2491 MSIOF0_TXD_MARK, 2492 }; 2493 static const unsigned int msiof0_rxd_pins[] = { 2494 /* RXD */ 2495 RCAR_GP_PIN(5, 22), 2496 }; 2497 static const unsigned int msiof0_rxd_mux[] = { 2498 MSIOF0_RXD_MARK, 2499 }; 2500 /* - MSIOF1 ----------------------------------------------------------------- */ 2501 static const unsigned int msiof1_clk_a_pins[] = { 2502 /* SCK */ 2503 RCAR_GP_PIN(6, 8), 2504 }; 2505 static const unsigned int msiof1_clk_a_mux[] = { 2506 MSIOF1_SCK_A_MARK, 2507 }; 2508 static const unsigned int msiof1_sync_a_pins[] = { 2509 /* SYNC */ 2510 RCAR_GP_PIN(6, 9), 2511 }; 2512 static const unsigned int msiof1_sync_a_mux[] = { 2513 MSIOF1_SYNC_A_MARK, 2514 }; 2515 static const unsigned int msiof1_ss1_a_pins[] = { 2516 /* SS1 */ 2517 RCAR_GP_PIN(6, 5), 2518 }; 2519 static const unsigned int msiof1_ss1_a_mux[] = { 2520 MSIOF1_SS1_A_MARK, 2521 }; 2522 static const unsigned int msiof1_ss2_a_pins[] = { 2523 /* SS2 */ 2524 RCAR_GP_PIN(6, 6), 2525 }; 2526 static const unsigned int msiof1_ss2_a_mux[] = { 2527 MSIOF1_SS2_A_MARK, 2528 }; 2529 static const unsigned int msiof1_txd_a_pins[] = { 2530 /* TXD */ 2531 RCAR_GP_PIN(6, 7), 2532 }; 2533 static const unsigned int msiof1_txd_a_mux[] = { 2534 MSIOF1_TXD_A_MARK, 2535 }; 2536 static const unsigned int msiof1_rxd_a_pins[] = { 2537 /* RXD */ 2538 RCAR_GP_PIN(6, 10), 2539 }; 2540 static const unsigned int msiof1_rxd_a_mux[] = { 2541 MSIOF1_RXD_A_MARK, 2542 }; 2543 static const unsigned int msiof1_clk_b_pins[] = { 2544 /* SCK */ 2545 RCAR_GP_PIN(5, 9), 2546 }; 2547 static const unsigned int msiof1_clk_b_mux[] = { 2548 MSIOF1_SCK_B_MARK, 2549 }; 2550 static const unsigned int msiof1_sync_b_pins[] = { 2551 /* SYNC */ 2552 RCAR_GP_PIN(5, 3), 2553 }; 2554 static const unsigned int msiof1_sync_b_mux[] = { 2555 MSIOF1_SYNC_B_MARK, 2556 }; 2557 static const unsigned int msiof1_ss1_b_pins[] = { 2558 /* SS1 */ 2559 RCAR_GP_PIN(5, 4), 2560 }; 2561 static const unsigned int msiof1_ss1_b_mux[] = { 2562 MSIOF1_SS1_B_MARK, 2563 }; 2564 static const unsigned int msiof1_ss2_b_pins[] = { 2565 /* SS2 */ 2566 RCAR_GP_PIN(5, 0), 2567 }; 2568 static const unsigned int msiof1_ss2_b_mux[] = { 2569 MSIOF1_SS2_B_MARK, 2570 }; 2571 static const unsigned int msiof1_txd_b_pins[] = { 2572 /* TXD */ 2573 RCAR_GP_PIN(5, 8), 2574 }; 2575 static const unsigned int msiof1_txd_b_mux[] = { 2576 MSIOF1_TXD_B_MARK, 2577 }; 2578 static const unsigned int msiof1_rxd_b_pins[] = { 2579 /* RXD */ 2580 RCAR_GP_PIN(5, 7), 2581 }; 2582 static const unsigned int msiof1_rxd_b_mux[] = { 2583 MSIOF1_RXD_B_MARK, 2584 }; 2585 static const unsigned int msiof1_clk_c_pins[] = { 2586 /* SCK */ 2587 RCAR_GP_PIN(6, 17), 2588 }; 2589 static const unsigned int msiof1_clk_c_mux[] = { 2590 MSIOF1_SCK_C_MARK, 2591 }; 2592 static const unsigned int msiof1_sync_c_pins[] = { 2593 /* SYNC */ 2594 RCAR_GP_PIN(6, 18), 2595 }; 2596 static const unsigned int msiof1_sync_c_mux[] = { 2597 MSIOF1_SYNC_C_MARK, 2598 }; 2599 static const unsigned int msiof1_ss1_c_pins[] = { 2600 /* SS1 */ 2601 RCAR_GP_PIN(6, 21), 2602 }; 2603 static const unsigned int msiof1_ss1_c_mux[] = { 2604 MSIOF1_SS1_C_MARK, 2605 }; 2606 static const unsigned int msiof1_ss2_c_pins[] = { 2607 /* SS2 */ 2608 RCAR_GP_PIN(6, 27), 2609 }; 2610 static const unsigned int msiof1_ss2_c_mux[] = { 2611 MSIOF1_SS2_C_MARK, 2612 }; 2613 static const unsigned int msiof1_txd_c_pins[] = { 2614 /* TXD */ 2615 RCAR_GP_PIN(6, 20), 2616 }; 2617 static const unsigned int msiof1_txd_c_mux[] = { 2618 MSIOF1_TXD_C_MARK, 2619 }; 2620 static const unsigned int msiof1_rxd_c_pins[] = { 2621 /* RXD */ 2622 RCAR_GP_PIN(6, 19), 2623 }; 2624 static const unsigned int msiof1_rxd_c_mux[] = { 2625 MSIOF1_RXD_C_MARK, 2626 }; 2627 static const unsigned int msiof1_clk_d_pins[] = { 2628 /* SCK */ 2629 RCAR_GP_PIN(5, 12), 2630 }; 2631 static const unsigned int msiof1_clk_d_mux[] = { 2632 MSIOF1_SCK_D_MARK, 2633 }; 2634 static const unsigned int msiof1_sync_d_pins[] = { 2635 /* SYNC */ 2636 RCAR_GP_PIN(5, 15), 2637 }; 2638 static const unsigned int msiof1_sync_d_mux[] = { 2639 MSIOF1_SYNC_D_MARK, 2640 }; 2641 static const unsigned int msiof1_ss1_d_pins[] = { 2642 /* SS1 */ 2643 RCAR_GP_PIN(5, 16), 2644 }; 2645 static const unsigned int msiof1_ss1_d_mux[] = { 2646 MSIOF1_SS1_D_MARK, 2647 }; 2648 static const unsigned int msiof1_ss2_d_pins[] = { 2649 /* SS2 */ 2650 RCAR_GP_PIN(5, 21), 2651 }; 2652 static const unsigned int msiof1_ss2_d_mux[] = { 2653 MSIOF1_SS2_D_MARK, 2654 }; 2655 static const unsigned int msiof1_txd_d_pins[] = { 2656 /* TXD */ 2657 RCAR_GP_PIN(5, 14), 2658 }; 2659 static const unsigned int msiof1_txd_d_mux[] = { 2660 MSIOF1_TXD_D_MARK, 2661 }; 2662 static const unsigned int msiof1_rxd_d_pins[] = { 2663 /* RXD */ 2664 RCAR_GP_PIN(5, 13), 2665 }; 2666 static const unsigned int msiof1_rxd_d_mux[] = { 2667 MSIOF1_RXD_D_MARK, 2668 }; 2669 static const unsigned int msiof1_clk_e_pins[] = { 2670 /* SCK */ 2671 RCAR_GP_PIN(3, 0), 2672 }; 2673 static const unsigned int msiof1_clk_e_mux[] = { 2674 MSIOF1_SCK_E_MARK, 2675 }; 2676 static const unsigned int msiof1_sync_e_pins[] = { 2677 /* SYNC */ 2678 RCAR_GP_PIN(3, 1), 2679 }; 2680 static const unsigned int msiof1_sync_e_mux[] = { 2681 MSIOF1_SYNC_E_MARK, 2682 }; 2683 static const unsigned int msiof1_ss1_e_pins[] = { 2684 /* SS1 */ 2685 RCAR_GP_PIN(3, 4), 2686 }; 2687 static const unsigned int msiof1_ss1_e_mux[] = { 2688 MSIOF1_SS1_E_MARK, 2689 }; 2690 static const unsigned int msiof1_ss2_e_pins[] = { 2691 /* SS2 */ 2692 RCAR_GP_PIN(3, 5), 2693 }; 2694 static const unsigned int msiof1_ss2_e_mux[] = { 2695 MSIOF1_SS2_E_MARK, 2696 }; 2697 static const unsigned int msiof1_txd_e_pins[] = { 2698 /* TXD */ 2699 RCAR_GP_PIN(3, 3), 2700 }; 2701 static const unsigned int msiof1_txd_e_mux[] = { 2702 MSIOF1_TXD_E_MARK, 2703 }; 2704 static const unsigned int msiof1_rxd_e_pins[] = { 2705 /* RXD */ 2706 RCAR_GP_PIN(3, 2), 2707 }; 2708 static const unsigned int msiof1_rxd_e_mux[] = { 2709 MSIOF1_RXD_E_MARK, 2710 }; 2711 static const unsigned int msiof1_clk_f_pins[] = { 2712 /* SCK */ 2713 RCAR_GP_PIN(5, 23), 2714 }; 2715 static const unsigned int msiof1_clk_f_mux[] = { 2716 MSIOF1_SCK_F_MARK, 2717 }; 2718 static const unsigned int msiof1_sync_f_pins[] = { 2719 /* SYNC */ 2720 RCAR_GP_PIN(5, 24), 2721 }; 2722 static const unsigned int msiof1_sync_f_mux[] = { 2723 MSIOF1_SYNC_F_MARK, 2724 }; 2725 static const unsigned int msiof1_ss1_f_pins[] = { 2726 /* SS1 */ 2727 RCAR_GP_PIN(6, 1), 2728 }; 2729 static const unsigned int msiof1_ss1_f_mux[] = { 2730 MSIOF1_SS1_F_MARK, 2731 }; 2732 static const unsigned int msiof1_ss2_f_pins[] = { 2733 /* SS2 */ 2734 RCAR_GP_PIN(6, 2), 2735 }; 2736 static const unsigned int msiof1_ss2_f_mux[] = { 2737 MSIOF1_SS2_F_MARK, 2738 }; 2739 static const unsigned int msiof1_txd_f_pins[] = { 2740 /* TXD */ 2741 RCAR_GP_PIN(6, 0), 2742 }; 2743 static const unsigned int msiof1_txd_f_mux[] = { 2744 MSIOF1_TXD_F_MARK, 2745 }; 2746 static const unsigned int msiof1_rxd_f_pins[] = { 2747 /* RXD */ 2748 RCAR_GP_PIN(5, 25), 2749 }; 2750 static const unsigned int msiof1_rxd_f_mux[] = { 2751 MSIOF1_RXD_F_MARK, 2752 }; 2753 static const unsigned int msiof1_clk_g_pins[] = { 2754 /* SCK */ 2755 RCAR_GP_PIN(3, 6), 2756 }; 2757 static const unsigned int msiof1_clk_g_mux[] = { 2758 MSIOF1_SCK_G_MARK, 2759 }; 2760 static const unsigned int msiof1_sync_g_pins[] = { 2761 /* SYNC */ 2762 RCAR_GP_PIN(3, 7), 2763 }; 2764 static const unsigned int msiof1_sync_g_mux[] = { 2765 MSIOF1_SYNC_G_MARK, 2766 }; 2767 static const unsigned int msiof1_ss1_g_pins[] = { 2768 /* SS1 */ 2769 RCAR_GP_PIN(3, 10), 2770 }; 2771 static const unsigned int msiof1_ss1_g_mux[] = { 2772 MSIOF1_SS1_G_MARK, 2773 }; 2774 static const unsigned int msiof1_ss2_g_pins[] = { 2775 /* SS2 */ 2776 RCAR_GP_PIN(3, 11), 2777 }; 2778 static const unsigned int msiof1_ss2_g_mux[] = { 2779 MSIOF1_SS2_G_MARK, 2780 }; 2781 static const unsigned int msiof1_txd_g_pins[] = { 2782 /* TXD */ 2783 RCAR_GP_PIN(3, 9), 2784 }; 2785 static const unsigned int msiof1_txd_g_mux[] = { 2786 MSIOF1_TXD_G_MARK, 2787 }; 2788 static const unsigned int msiof1_rxd_g_pins[] = { 2789 /* RXD */ 2790 RCAR_GP_PIN(3, 8), 2791 }; 2792 static const unsigned int msiof1_rxd_g_mux[] = { 2793 MSIOF1_RXD_G_MARK, 2794 }; 2795 /* - MSIOF2 ----------------------------------------------------------------- */ 2796 static const unsigned int msiof2_clk_a_pins[] = { 2797 /* SCK */ 2798 RCAR_GP_PIN(1, 9), 2799 }; 2800 static const unsigned int msiof2_clk_a_mux[] = { 2801 MSIOF2_SCK_A_MARK, 2802 }; 2803 static const unsigned int msiof2_sync_a_pins[] = { 2804 /* SYNC */ 2805 RCAR_GP_PIN(1, 8), 2806 }; 2807 static const unsigned int msiof2_sync_a_mux[] = { 2808 MSIOF2_SYNC_A_MARK, 2809 }; 2810 static const unsigned int msiof2_ss1_a_pins[] = { 2811 /* SS1 */ 2812 RCAR_GP_PIN(1, 6), 2813 }; 2814 static const unsigned int msiof2_ss1_a_mux[] = { 2815 MSIOF2_SS1_A_MARK, 2816 }; 2817 static const unsigned int msiof2_ss2_a_pins[] = { 2818 /* SS2 */ 2819 RCAR_GP_PIN(1, 7), 2820 }; 2821 static const unsigned int msiof2_ss2_a_mux[] = { 2822 MSIOF2_SS2_A_MARK, 2823 }; 2824 static const unsigned int msiof2_txd_a_pins[] = { 2825 /* TXD */ 2826 RCAR_GP_PIN(1, 11), 2827 }; 2828 static const unsigned int msiof2_txd_a_mux[] = { 2829 MSIOF2_TXD_A_MARK, 2830 }; 2831 static const unsigned int msiof2_rxd_a_pins[] = { 2832 /* RXD */ 2833 RCAR_GP_PIN(1, 10), 2834 }; 2835 static const unsigned int msiof2_rxd_a_mux[] = { 2836 MSIOF2_RXD_A_MARK, 2837 }; 2838 static const unsigned int msiof2_clk_b_pins[] = { 2839 /* SCK */ 2840 RCAR_GP_PIN(0, 4), 2841 }; 2842 static const unsigned int msiof2_clk_b_mux[] = { 2843 MSIOF2_SCK_B_MARK, 2844 }; 2845 static const unsigned int msiof2_sync_b_pins[] = { 2846 /* SYNC */ 2847 RCAR_GP_PIN(0, 5), 2848 }; 2849 static const unsigned int msiof2_sync_b_mux[] = { 2850 MSIOF2_SYNC_B_MARK, 2851 }; 2852 static const unsigned int msiof2_ss1_b_pins[] = { 2853 /* SS1 */ 2854 RCAR_GP_PIN(0, 0), 2855 }; 2856 static const unsigned int msiof2_ss1_b_mux[] = { 2857 MSIOF2_SS1_B_MARK, 2858 }; 2859 static const unsigned int msiof2_ss2_b_pins[] = { 2860 /* SS2 */ 2861 RCAR_GP_PIN(0, 1), 2862 }; 2863 static const unsigned int msiof2_ss2_b_mux[] = { 2864 MSIOF2_SS2_B_MARK, 2865 }; 2866 static const unsigned int msiof2_txd_b_pins[] = { 2867 /* TXD */ 2868 RCAR_GP_PIN(0, 7), 2869 }; 2870 static const unsigned int msiof2_txd_b_mux[] = { 2871 MSIOF2_TXD_B_MARK, 2872 }; 2873 static const unsigned int msiof2_rxd_b_pins[] = { 2874 /* RXD */ 2875 RCAR_GP_PIN(0, 6), 2876 }; 2877 static const unsigned int msiof2_rxd_b_mux[] = { 2878 MSIOF2_RXD_B_MARK, 2879 }; 2880 static const unsigned int msiof2_clk_c_pins[] = { 2881 /* SCK */ 2882 RCAR_GP_PIN(2, 12), 2883 }; 2884 static const unsigned int msiof2_clk_c_mux[] = { 2885 MSIOF2_SCK_C_MARK, 2886 }; 2887 static const unsigned int msiof2_sync_c_pins[] = { 2888 /* SYNC */ 2889 RCAR_GP_PIN(2, 11), 2890 }; 2891 static const unsigned int msiof2_sync_c_mux[] = { 2892 MSIOF2_SYNC_C_MARK, 2893 }; 2894 static const unsigned int msiof2_ss1_c_pins[] = { 2895 /* SS1 */ 2896 RCAR_GP_PIN(2, 10), 2897 }; 2898 static const unsigned int msiof2_ss1_c_mux[] = { 2899 MSIOF2_SS1_C_MARK, 2900 }; 2901 static const unsigned int msiof2_ss2_c_pins[] = { 2902 /* SS2 */ 2903 RCAR_GP_PIN(2, 9), 2904 }; 2905 static const unsigned int msiof2_ss2_c_mux[] = { 2906 MSIOF2_SS2_C_MARK, 2907 }; 2908 static const unsigned int msiof2_txd_c_pins[] = { 2909 /* TXD */ 2910 RCAR_GP_PIN(2, 14), 2911 }; 2912 static const unsigned int msiof2_txd_c_mux[] = { 2913 MSIOF2_TXD_C_MARK, 2914 }; 2915 static const unsigned int msiof2_rxd_c_pins[] = { 2916 /* RXD */ 2917 RCAR_GP_PIN(2, 13), 2918 }; 2919 static const unsigned int msiof2_rxd_c_mux[] = { 2920 MSIOF2_RXD_C_MARK, 2921 }; 2922 static const unsigned int msiof2_clk_d_pins[] = { 2923 /* SCK */ 2924 RCAR_GP_PIN(0, 8), 2925 }; 2926 static const unsigned int msiof2_clk_d_mux[] = { 2927 MSIOF2_SCK_D_MARK, 2928 }; 2929 static const unsigned int msiof2_sync_d_pins[] = { 2930 /* SYNC */ 2931 RCAR_GP_PIN(0, 9), 2932 }; 2933 static const unsigned int msiof2_sync_d_mux[] = { 2934 MSIOF2_SYNC_D_MARK, 2935 }; 2936 static const unsigned int msiof2_ss1_d_pins[] = { 2937 /* SS1 */ 2938 RCAR_GP_PIN(0, 12), 2939 }; 2940 static const unsigned int msiof2_ss1_d_mux[] = { 2941 MSIOF2_SS1_D_MARK, 2942 }; 2943 static const unsigned int msiof2_ss2_d_pins[] = { 2944 /* SS2 */ 2945 RCAR_GP_PIN(0, 13), 2946 }; 2947 static const unsigned int msiof2_ss2_d_mux[] = { 2948 MSIOF2_SS2_D_MARK, 2949 }; 2950 static const unsigned int msiof2_txd_d_pins[] = { 2951 /* TXD */ 2952 RCAR_GP_PIN(0, 11), 2953 }; 2954 static const unsigned int msiof2_txd_d_mux[] = { 2955 MSIOF2_TXD_D_MARK, 2956 }; 2957 static const unsigned int msiof2_rxd_d_pins[] = { 2958 /* RXD */ 2959 RCAR_GP_PIN(0, 10), 2960 }; 2961 static const unsigned int msiof2_rxd_d_mux[] = { 2962 MSIOF2_RXD_D_MARK, 2963 }; 2964 /* - MSIOF3 ----------------------------------------------------------------- */ 2965 static const unsigned int msiof3_clk_a_pins[] = { 2966 /* SCK */ 2967 RCAR_GP_PIN(0, 0), 2968 }; 2969 static const unsigned int msiof3_clk_a_mux[] = { 2970 MSIOF3_SCK_A_MARK, 2971 }; 2972 static const unsigned int msiof3_sync_a_pins[] = { 2973 /* SYNC */ 2974 RCAR_GP_PIN(0, 1), 2975 }; 2976 static const unsigned int msiof3_sync_a_mux[] = { 2977 MSIOF3_SYNC_A_MARK, 2978 }; 2979 static const unsigned int msiof3_ss1_a_pins[] = { 2980 /* SS1 */ 2981 RCAR_GP_PIN(0, 14), 2982 }; 2983 static const unsigned int msiof3_ss1_a_mux[] = { 2984 MSIOF3_SS1_A_MARK, 2985 }; 2986 static const unsigned int msiof3_ss2_a_pins[] = { 2987 /* SS2 */ 2988 RCAR_GP_PIN(0, 15), 2989 }; 2990 static const unsigned int msiof3_ss2_a_mux[] = { 2991 MSIOF3_SS2_A_MARK, 2992 }; 2993 static const unsigned int msiof3_txd_a_pins[] = { 2994 /* TXD */ 2995 RCAR_GP_PIN(0, 3), 2996 }; 2997 static const unsigned int msiof3_txd_a_mux[] = { 2998 MSIOF3_TXD_A_MARK, 2999 }; 3000 static const unsigned int msiof3_rxd_a_pins[] = { 3001 /* RXD */ 3002 RCAR_GP_PIN(0, 2), 3003 }; 3004 static const unsigned int msiof3_rxd_a_mux[] = { 3005 MSIOF3_RXD_A_MARK, 3006 }; 3007 static const unsigned int msiof3_clk_b_pins[] = { 3008 /* SCK */ 3009 RCAR_GP_PIN(1, 2), 3010 }; 3011 static const unsigned int msiof3_clk_b_mux[] = { 3012 MSIOF3_SCK_B_MARK, 3013 }; 3014 static const unsigned int msiof3_sync_b_pins[] = { 3015 /* SYNC */ 3016 RCAR_GP_PIN(1, 0), 3017 }; 3018 static const unsigned int msiof3_sync_b_mux[] = { 3019 MSIOF3_SYNC_B_MARK, 3020 }; 3021 static const unsigned int msiof3_ss1_b_pins[] = { 3022 /* SS1 */ 3023 RCAR_GP_PIN(1, 4), 3024 }; 3025 static const unsigned int msiof3_ss1_b_mux[] = { 3026 MSIOF3_SS1_B_MARK, 3027 }; 3028 static const unsigned int msiof3_ss2_b_pins[] = { 3029 /* SS2 */ 3030 RCAR_GP_PIN(1, 5), 3031 }; 3032 static const unsigned int msiof3_ss2_b_mux[] = { 3033 MSIOF3_SS2_B_MARK, 3034 }; 3035 static const unsigned int msiof3_txd_b_pins[] = { 3036 /* TXD */ 3037 RCAR_GP_PIN(1, 1), 3038 }; 3039 static const unsigned int msiof3_txd_b_mux[] = { 3040 MSIOF3_TXD_B_MARK, 3041 }; 3042 static const unsigned int msiof3_rxd_b_pins[] = { 3043 /* RXD */ 3044 RCAR_GP_PIN(1, 3), 3045 }; 3046 static const unsigned int msiof3_rxd_b_mux[] = { 3047 MSIOF3_RXD_B_MARK, 3048 }; 3049 static const unsigned int msiof3_clk_c_pins[] = { 3050 /* SCK */ 3051 RCAR_GP_PIN(1, 12), 3052 }; 3053 static const unsigned int msiof3_clk_c_mux[] = { 3054 MSIOF3_SCK_C_MARK, 3055 }; 3056 static const unsigned int msiof3_sync_c_pins[] = { 3057 /* SYNC */ 3058 RCAR_GP_PIN(1, 13), 3059 }; 3060 static const unsigned int msiof3_sync_c_mux[] = { 3061 MSIOF3_SYNC_C_MARK, 3062 }; 3063 static const unsigned int msiof3_txd_c_pins[] = { 3064 /* TXD */ 3065 RCAR_GP_PIN(1, 15), 3066 }; 3067 static const unsigned int msiof3_txd_c_mux[] = { 3068 MSIOF3_TXD_C_MARK, 3069 }; 3070 static const unsigned int msiof3_rxd_c_pins[] = { 3071 /* RXD */ 3072 RCAR_GP_PIN(1, 14), 3073 }; 3074 static const unsigned int msiof3_rxd_c_mux[] = { 3075 MSIOF3_RXD_C_MARK, 3076 }; 3077 static const unsigned int msiof3_clk_d_pins[] = { 3078 /* SCK */ 3079 RCAR_GP_PIN(1, 22), 3080 }; 3081 static const unsigned int msiof3_clk_d_mux[] = { 3082 MSIOF3_SCK_D_MARK, 3083 }; 3084 static const unsigned int msiof3_sync_d_pins[] = { 3085 /* SYNC */ 3086 RCAR_GP_PIN(1, 23), 3087 }; 3088 static const unsigned int msiof3_sync_d_mux[] = { 3089 MSIOF3_SYNC_D_MARK, 3090 }; 3091 static const unsigned int msiof3_ss1_d_pins[] = { 3092 /* SS1 */ 3093 RCAR_GP_PIN(1, 26), 3094 }; 3095 static const unsigned int msiof3_ss1_d_mux[] = { 3096 MSIOF3_SS1_D_MARK, 3097 }; 3098 static const unsigned int msiof3_txd_d_pins[] = { 3099 /* TXD */ 3100 RCAR_GP_PIN(1, 25), 3101 }; 3102 static const unsigned int msiof3_txd_d_mux[] = { 3103 MSIOF3_TXD_D_MARK, 3104 }; 3105 static const unsigned int msiof3_rxd_d_pins[] = { 3106 /* RXD */ 3107 RCAR_GP_PIN(1, 24), 3108 }; 3109 static const unsigned int msiof3_rxd_d_mux[] = { 3110 MSIOF3_RXD_D_MARK, 3111 }; 3112 static const unsigned int msiof3_clk_e_pins[] = { 3113 /* SCK */ 3114 RCAR_GP_PIN(2, 3), 3115 }; 3116 static const unsigned int msiof3_clk_e_mux[] = { 3117 MSIOF3_SCK_E_MARK, 3118 }; 3119 static const unsigned int msiof3_sync_e_pins[] = { 3120 /* SYNC */ 3121 RCAR_GP_PIN(2, 2), 3122 }; 3123 static const unsigned int msiof3_sync_e_mux[] = { 3124 MSIOF3_SYNC_E_MARK, 3125 }; 3126 static const unsigned int msiof3_ss1_e_pins[] = { 3127 /* SS1 */ 3128 RCAR_GP_PIN(2, 1), 3129 }; 3130 static const unsigned int msiof3_ss1_e_mux[] = { 3131 MSIOF3_SS1_E_MARK, 3132 }; 3133 static const unsigned int msiof3_ss2_e_pins[] = { 3134 /* SS2 */ 3135 RCAR_GP_PIN(2, 0), 3136 }; 3137 static const unsigned int msiof3_ss2_e_mux[] = { 3138 MSIOF3_SS2_E_MARK, 3139 }; 3140 static const unsigned int msiof3_txd_e_pins[] = { 3141 /* TXD */ 3142 RCAR_GP_PIN(2, 5), 3143 }; 3144 static const unsigned int msiof3_txd_e_mux[] = { 3145 MSIOF3_TXD_E_MARK, 3146 }; 3147 static const unsigned int msiof3_rxd_e_pins[] = { 3148 /* RXD */ 3149 RCAR_GP_PIN(2, 4), 3150 }; 3151 static const unsigned int msiof3_rxd_e_mux[] = { 3152 MSIOF3_RXD_E_MARK, 3153 }; 3154 3155 /* - PWM0 --------------------------------------------------------------------*/ 3156 static const unsigned int pwm0_pins[] = { 3157 /* PWM */ 3158 RCAR_GP_PIN(2, 6), 3159 }; 3160 static const unsigned int pwm0_mux[] = { 3161 PWM0_MARK, 3162 }; 3163 /* - PWM1 --------------------------------------------------------------------*/ 3164 static const unsigned int pwm1_a_pins[] = { 3165 /* PWM */ 3166 RCAR_GP_PIN(2, 7), 3167 }; 3168 static const unsigned int pwm1_a_mux[] = { 3169 PWM1_A_MARK, 3170 }; 3171 static const unsigned int pwm1_b_pins[] = { 3172 /* PWM */ 3173 RCAR_GP_PIN(1, 8), 3174 }; 3175 static const unsigned int pwm1_b_mux[] = { 3176 PWM1_B_MARK, 3177 }; 3178 /* - PWM2 --------------------------------------------------------------------*/ 3179 static const unsigned int pwm2_a_pins[] = { 3180 /* PWM */ 3181 RCAR_GP_PIN(2, 8), 3182 }; 3183 static const unsigned int pwm2_a_mux[] = { 3184 PWM2_A_MARK, 3185 }; 3186 static const unsigned int pwm2_b_pins[] = { 3187 /* PWM */ 3188 RCAR_GP_PIN(1, 11), 3189 }; 3190 static const unsigned int pwm2_b_mux[] = { 3191 PWM2_B_MARK, 3192 }; 3193 /* - PWM3 --------------------------------------------------------------------*/ 3194 static const unsigned int pwm3_a_pins[] = { 3195 /* PWM */ 3196 RCAR_GP_PIN(1, 0), 3197 }; 3198 static const unsigned int pwm3_a_mux[] = { 3199 PWM3_A_MARK, 3200 }; 3201 static const unsigned int pwm3_b_pins[] = { 3202 /* PWM */ 3203 RCAR_GP_PIN(2, 2), 3204 }; 3205 static const unsigned int pwm3_b_mux[] = { 3206 PWM3_B_MARK, 3207 }; 3208 /* - PWM4 --------------------------------------------------------------------*/ 3209 static const unsigned int pwm4_a_pins[] = { 3210 /* PWM */ 3211 RCAR_GP_PIN(1, 1), 3212 }; 3213 static const unsigned int pwm4_a_mux[] = { 3214 PWM4_A_MARK, 3215 }; 3216 static const unsigned int pwm4_b_pins[] = { 3217 /* PWM */ 3218 RCAR_GP_PIN(2, 3), 3219 }; 3220 static const unsigned int pwm4_b_mux[] = { 3221 PWM4_B_MARK, 3222 }; 3223 /* - PWM5 --------------------------------------------------------------------*/ 3224 static const unsigned int pwm5_a_pins[] = { 3225 /* PWM */ 3226 RCAR_GP_PIN(1, 2), 3227 }; 3228 static const unsigned int pwm5_a_mux[] = { 3229 PWM5_A_MARK, 3230 }; 3231 static const unsigned int pwm5_b_pins[] = { 3232 /* PWM */ 3233 RCAR_GP_PIN(2, 4), 3234 }; 3235 static const unsigned int pwm5_b_mux[] = { 3236 PWM5_B_MARK, 3237 }; 3238 /* - PWM6 --------------------------------------------------------------------*/ 3239 static const unsigned int pwm6_a_pins[] = { 3240 /* PWM */ 3241 RCAR_GP_PIN(1, 3), 3242 }; 3243 static const unsigned int pwm6_a_mux[] = { 3244 PWM6_A_MARK, 3245 }; 3246 static const unsigned int pwm6_b_pins[] = { 3247 /* PWM */ 3248 RCAR_GP_PIN(2, 5), 3249 }; 3250 static const unsigned int pwm6_b_mux[] = { 3251 PWM6_B_MARK, 3252 }; 3253 3254 /* - QSPI0 ------------------------------------------------------------------ */ 3255 static const unsigned int qspi0_ctrl_pins[] = { 3256 /* QSPI0_SPCLK, QSPI0_SSL */ 3257 PIN_QSPI0_SPCLK, PIN_QSPI0_SSL, 3258 }; 3259 static const unsigned int qspi0_ctrl_mux[] = { 3260 QSPI0_SPCLK_MARK, QSPI0_SSL_MARK, 3261 }; 3262 static const unsigned int qspi0_data2_pins[] = { 3263 /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */ 3264 PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1, 3265 }; 3266 static const unsigned int qspi0_data2_mux[] = { 3267 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, 3268 }; 3269 static const unsigned int qspi0_data4_pins[] = { 3270 /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */ 3271 PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1, 3272 /* QSPI0_IO2, QSPI0_IO3 */ 3273 PIN_QSPI0_IO2, PIN_QSPI0_IO3, 3274 }; 3275 static const unsigned int qspi0_data4_mux[] = { 3276 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, 3277 QSPI0_IO2_MARK, QSPI0_IO3_MARK, 3278 }; 3279 /* - QSPI1 ------------------------------------------------------------------ */ 3280 static const unsigned int qspi1_ctrl_pins[] = { 3281 /* QSPI1_SPCLK, QSPI1_SSL */ 3282 PIN_QSPI1_SPCLK, PIN_QSPI1_SSL, 3283 }; 3284 static const unsigned int qspi1_ctrl_mux[] = { 3285 QSPI1_SPCLK_MARK, QSPI1_SSL_MARK, 3286 }; 3287 static const unsigned int qspi1_data2_pins[] = { 3288 /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */ 3289 PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1, 3290 }; 3291 static const unsigned int qspi1_data2_mux[] = { 3292 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, 3293 }; 3294 static const unsigned int qspi1_data4_pins[] = { 3295 /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */ 3296 PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1, 3297 /* QSPI1_IO2, QSPI1_IO3 */ 3298 PIN_QSPI1_IO2, PIN_QSPI1_IO3, 3299 }; 3300 static const unsigned int qspi1_data4_mux[] = { 3301 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, 3302 QSPI1_IO2_MARK, QSPI1_IO3_MARK, 3303 }; 3304 3305 /* - SATA --------------------------------------------------------------------*/ 3306 static const unsigned int sata0_devslp_a_pins[] = { 3307 /* DEVSLP */ 3308 RCAR_GP_PIN(6, 16), 3309 }; 3310 static const unsigned int sata0_devslp_a_mux[] = { 3311 SATA_DEVSLP_A_MARK, 3312 }; 3313 static const unsigned int sata0_devslp_b_pins[] = { 3314 /* DEVSLP */ 3315 RCAR_GP_PIN(4, 6), 3316 }; 3317 static const unsigned int sata0_devslp_b_mux[] = { 3318 SATA_DEVSLP_B_MARK, 3319 }; 3320 3321 /* - SCIF0 ------------------------------------------------------------------ */ 3322 static const unsigned int scif0_data_pins[] = { 3323 /* RX, TX */ 3324 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), 3325 }; 3326 static const unsigned int scif0_data_mux[] = { 3327 RX0_MARK, TX0_MARK, 3328 }; 3329 static const unsigned int scif0_clk_pins[] = { 3330 /* SCK */ 3331 RCAR_GP_PIN(5, 0), 3332 }; 3333 static const unsigned int scif0_clk_mux[] = { 3334 SCK0_MARK, 3335 }; 3336 static const unsigned int scif0_ctrl_pins[] = { 3337 /* RTS, CTS */ 3338 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3), 3339 }; 3340 static const unsigned int scif0_ctrl_mux[] = { 3341 RTS0_N_MARK, CTS0_N_MARK, 3342 }; 3343 /* - SCIF1 ------------------------------------------------------------------ */ 3344 static const unsigned int scif1_data_a_pins[] = { 3345 /* RX, TX */ 3346 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6), 3347 }; 3348 static const unsigned int scif1_data_a_mux[] = { 3349 RX1_A_MARK, TX1_A_MARK, 3350 }; 3351 static const unsigned int scif1_clk_pins[] = { 3352 /* SCK */ 3353 RCAR_GP_PIN(6, 21), 3354 }; 3355 static const unsigned int scif1_clk_mux[] = { 3356 SCK1_MARK, 3357 }; 3358 static const unsigned int scif1_ctrl_pins[] = { 3359 /* RTS, CTS */ 3360 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7), 3361 }; 3362 static const unsigned int scif1_ctrl_mux[] = { 3363 RTS1_N_MARK, CTS1_N_MARK, 3364 }; 3365 3366 static const unsigned int scif1_data_b_pins[] = { 3367 /* RX, TX */ 3368 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25), 3369 }; 3370 static const unsigned int scif1_data_b_mux[] = { 3371 RX1_B_MARK, TX1_B_MARK, 3372 }; 3373 /* - SCIF2 ------------------------------------------------------------------ */ 3374 static const unsigned int scif2_data_a_pins[] = { 3375 /* RX, TX */ 3376 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10), 3377 }; 3378 static const unsigned int scif2_data_a_mux[] = { 3379 RX2_A_MARK, TX2_A_MARK, 3380 }; 3381 static const unsigned int scif2_clk_pins[] = { 3382 /* SCK */ 3383 RCAR_GP_PIN(5, 9), 3384 }; 3385 static const unsigned int scif2_clk_mux[] = { 3386 SCK2_MARK, 3387 }; 3388 static const unsigned int scif2_data_b_pins[] = { 3389 /* RX, TX */ 3390 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16), 3391 }; 3392 static const unsigned int scif2_data_b_mux[] = { 3393 RX2_B_MARK, TX2_B_MARK, 3394 }; 3395 /* - SCIF3 ------------------------------------------------------------------ */ 3396 static const unsigned int scif3_data_a_pins[] = { 3397 /* RX, TX */ 3398 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24), 3399 }; 3400 static const unsigned int scif3_data_a_mux[] = { 3401 RX3_A_MARK, TX3_A_MARK, 3402 }; 3403 static const unsigned int scif3_clk_pins[] = { 3404 /* SCK */ 3405 RCAR_GP_PIN(1, 22), 3406 }; 3407 static const unsigned int scif3_clk_mux[] = { 3408 SCK3_MARK, 3409 }; 3410 static const unsigned int scif3_ctrl_pins[] = { 3411 /* RTS, CTS */ 3412 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25), 3413 }; 3414 static const unsigned int scif3_ctrl_mux[] = { 3415 RTS3_N_MARK, CTS3_N_MARK, 3416 }; 3417 static const unsigned int scif3_data_b_pins[] = { 3418 /* RX, TX */ 3419 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), 3420 }; 3421 static const unsigned int scif3_data_b_mux[] = { 3422 RX3_B_MARK, TX3_B_MARK, 3423 }; 3424 /* - SCIF4 ------------------------------------------------------------------ */ 3425 static const unsigned int scif4_data_a_pins[] = { 3426 /* RX, TX */ 3427 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12), 3428 }; 3429 static const unsigned int scif4_data_a_mux[] = { 3430 RX4_A_MARK, TX4_A_MARK, 3431 }; 3432 static const unsigned int scif4_clk_a_pins[] = { 3433 /* SCK */ 3434 RCAR_GP_PIN(2, 10), 3435 }; 3436 static const unsigned int scif4_clk_a_mux[] = { 3437 SCK4_A_MARK, 3438 }; 3439 static const unsigned int scif4_ctrl_a_pins[] = { 3440 /* RTS, CTS */ 3441 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13), 3442 }; 3443 static const unsigned int scif4_ctrl_a_mux[] = { 3444 RTS4_N_A_MARK, CTS4_N_A_MARK, 3445 }; 3446 static const unsigned int scif4_data_b_pins[] = { 3447 /* RX, TX */ 3448 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 3449 }; 3450 static const unsigned int scif4_data_b_mux[] = { 3451 RX4_B_MARK, TX4_B_MARK, 3452 }; 3453 static const unsigned int scif4_clk_b_pins[] = { 3454 /* SCK */ 3455 RCAR_GP_PIN(1, 5), 3456 }; 3457 static const unsigned int scif4_clk_b_mux[] = { 3458 SCK4_B_MARK, 3459 }; 3460 static const unsigned int scif4_ctrl_b_pins[] = { 3461 /* RTS, CTS */ 3462 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9), 3463 }; 3464 static const unsigned int scif4_ctrl_b_mux[] = { 3465 RTS4_N_B_MARK, CTS4_N_B_MARK, 3466 }; 3467 static const unsigned int scif4_data_c_pins[] = { 3468 /* RX, TX */ 3469 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), 3470 }; 3471 static const unsigned int scif4_data_c_mux[] = { 3472 RX4_C_MARK, TX4_C_MARK, 3473 }; 3474 static const unsigned int scif4_clk_c_pins[] = { 3475 /* SCK */ 3476 RCAR_GP_PIN(0, 8), 3477 }; 3478 static const unsigned int scif4_clk_c_mux[] = { 3479 SCK4_C_MARK, 3480 }; 3481 static const unsigned int scif4_ctrl_c_pins[] = { 3482 /* RTS, CTS */ 3483 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), 3484 }; 3485 static const unsigned int scif4_ctrl_c_mux[] = { 3486 RTS4_N_C_MARK, CTS4_N_C_MARK, 3487 }; 3488 /* - SCIF5 ------------------------------------------------------------------ */ 3489 static const unsigned int scif5_data_a_pins[] = { 3490 /* RX, TX */ 3491 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21), 3492 }; 3493 static const unsigned int scif5_data_a_mux[] = { 3494 RX5_A_MARK, TX5_A_MARK, 3495 }; 3496 static const unsigned int scif5_clk_a_pins[] = { 3497 /* SCK */ 3498 RCAR_GP_PIN(6, 21), 3499 }; 3500 static const unsigned int scif5_clk_a_mux[] = { 3501 SCK5_A_MARK, 3502 }; 3503 static const unsigned int scif5_data_b_pins[] = { 3504 /* RX, TX */ 3505 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18), 3506 }; 3507 static const unsigned int scif5_data_b_mux[] = { 3508 RX5_B_MARK, TX5_B_MARK, 3509 }; 3510 static const unsigned int scif5_clk_b_pins[] = { 3511 /* SCK */ 3512 RCAR_GP_PIN(5, 0), 3513 }; 3514 static const unsigned int scif5_clk_b_mux[] = { 3515 SCK5_B_MARK, 3516 }; 3517 3518 /* - SCIF Clock ------------------------------------------------------------- */ 3519 static const unsigned int scif_clk_a_pins[] = { 3520 /* SCIF_CLK */ 3521 RCAR_GP_PIN(6, 23), 3522 }; 3523 static const unsigned int scif_clk_a_mux[] = { 3524 SCIF_CLK_A_MARK, 3525 }; 3526 static const unsigned int scif_clk_b_pins[] = { 3527 /* SCIF_CLK */ 3528 RCAR_GP_PIN(5, 9), 3529 }; 3530 static const unsigned int scif_clk_b_mux[] = { 3531 SCIF_CLK_B_MARK, 3532 }; 3533 3534 /* - SDHI0 ------------------------------------------------------------------ */ 3535 static const unsigned int sdhi0_data1_pins[] = { 3536 /* D0 */ 3537 RCAR_GP_PIN(3, 2), 3538 }; 3539 static const unsigned int sdhi0_data1_mux[] = { 3540 SD0_DAT0_MARK, 3541 }; 3542 static const unsigned int sdhi0_data4_pins[] = { 3543 /* D[0:3] */ 3544 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), 3545 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), 3546 }; 3547 static const unsigned int sdhi0_data4_mux[] = { 3548 SD0_DAT0_MARK, SD0_DAT1_MARK, 3549 SD0_DAT2_MARK, SD0_DAT3_MARK, 3550 }; 3551 static const unsigned int sdhi0_ctrl_pins[] = { 3552 /* CLK, CMD */ 3553 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1), 3554 }; 3555 static const unsigned int sdhi0_ctrl_mux[] = { 3556 SD0_CLK_MARK, SD0_CMD_MARK, 3557 }; 3558 static const unsigned int sdhi0_cd_pins[] = { 3559 /* CD */ 3560 RCAR_GP_PIN(3, 12), 3561 }; 3562 static const unsigned int sdhi0_cd_mux[] = { 3563 SD0_CD_MARK, 3564 }; 3565 static const unsigned int sdhi0_wp_pins[] = { 3566 /* WP */ 3567 RCAR_GP_PIN(3, 13), 3568 }; 3569 static const unsigned int sdhi0_wp_mux[] = { 3570 SD0_WP_MARK, 3571 }; 3572 /* - SDHI1 ------------------------------------------------------------------ */ 3573 static const unsigned int sdhi1_data1_pins[] = { 3574 /* D0 */ 3575 RCAR_GP_PIN(3, 8), 3576 }; 3577 static const unsigned int sdhi1_data1_mux[] = { 3578 SD1_DAT0_MARK, 3579 }; 3580 static const unsigned int sdhi1_data4_pins[] = { 3581 /* D[0:3] */ 3582 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), 3583 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), 3584 }; 3585 static const unsigned int sdhi1_data4_mux[] = { 3586 SD1_DAT0_MARK, SD1_DAT1_MARK, 3587 SD1_DAT2_MARK, SD1_DAT3_MARK, 3588 }; 3589 static const unsigned int sdhi1_ctrl_pins[] = { 3590 /* CLK, CMD */ 3591 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), 3592 }; 3593 static const unsigned int sdhi1_ctrl_mux[] = { 3594 SD1_CLK_MARK, SD1_CMD_MARK, 3595 }; 3596 static const unsigned int sdhi1_cd_pins[] = { 3597 /* CD */ 3598 RCAR_GP_PIN(3, 14), 3599 }; 3600 static const unsigned int sdhi1_cd_mux[] = { 3601 SD1_CD_MARK, 3602 }; 3603 static const unsigned int sdhi1_wp_pins[] = { 3604 /* WP */ 3605 RCAR_GP_PIN(3, 15), 3606 }; 3607 static const unsigned int sdhi1_wp_mux[] = { 3608 SD1_WP_MARK, 3609 }; 3610 /* - SDHI2 ------------------------------------------------------------------ */ 3611 static const unsigned int sdhi2_data1_pins[] = { 3612 /* D0 */ 3613 RCAR_GP_PIN(4, 2), 3614 }; 3615 static const unsigned int sdhi2_data1_mux[] = { 3616 SD2_DAT0_MARK, 3617 }; 3618 static const unsigned int sdhi2_data4_pins[] = { 3619 /* D[0:3] */ 3620 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), 3621 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), 3622 }; 3623 static const unsigned int sdhi2_data4_mux[] = { 3624 SD2_DAT0_MARK, SD2_DAT1_MARK, 3625 SD2_DAT2_MARK, SD2_DAT3_MARK, 3626 }; 3627 static const unsigned int sdhi2_data8_pins[] = { 3628 /* D[0:7] */ 3629 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), 3630 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), 3631 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), 3632 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), 3633 }; 3634 static const unsigned int sdhi2_data8_mux[] = { 3635 SD2_DAT0_MARK, SD2_DAT1_MARK, 3636 SD2_DAT2_MARK, SD2_DAT3_MARK, 3637 SD2_DAT4_MARK, SD2_DAT5_MARK, 3638 SD2_DAT6_MARK, SD2_DAT7_MARK, 3639 }; 3640 static const unsigned int sdhi2_ctrl_pins[] = { 3641 /* CLK, CMD */ 3642 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1), 3643 }; 3644 static const unsigned int sdhi2_ctrl_mux[] = { 3645 SD2_CLK_MARK, SD2_CMD_MARK, 3646 }; 3647 static const unsigned int sdhi2_cd_a_pins[] = { 3648 /* CD */ 3649 RCAR_GP_PIN(4, 13), 3650 }; 3651 static const unsigned int sdhi2_cd_a_mux[] = { 3652 SD2_CD_A_MARK, 3653 }; 3654 static const unsigned int sdhi2_cd_b_pins[] = { 3655 /* CD */ 3656 RCAR_GP_PIN(5, 10), 3657 }; 3658 static const unsigned int sdhi2_cd_b_mux[] = { 3659 SD2_CD_B_MARK, 3660 }; 3661 static const unsigned int sdhi2_wp_a_pins[] = { 3662 /* WP */ 3663 RCAR_GP_PIN(4, 14), 3664 }; 3665 static const unsigned int sdhi2_wp_a_mux[] = { 3666 SD2_WP_A_MARK, 3667 }; 3668 static const unsigned int sdhi2_wp_b_pins[] = { 3669 /* WP */ 3670 RCAR_GP_PIN(5, 11), 3671 }; 3672 static const unsigned int sdhi2_wp_b_mux[] = { 3673 SD2_WP_B_MARK, 3674 }; 3675 static const unsigned int sdhi2_ds_pins[] = { 3676 /* DS */ 3677 RCAR_GP_PIN(4, 6), 3678 }; 3679 static const unsigned int sdhi2_ds_mux[] = { 3680 SD2_DS_MARK, 3681 }; 3682 /* - SDHI3 ------------------------------------------------------------------ */ 3683 static const unsigned int sdhi3_data1_pins[] = { 3684 /* D0 */ 3685 RCAR_GP_PIN(4, 9), 3686 }; 3687 static const unsigned int sdhi3_data1_mux[] = { 3688 SD3_DAT0_MARK, 3689 }; 3690 static const unsigned int sdhi3_data4_pins[] = { 3691 /* D[0:3] */ 3692 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10), 3693 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12), 3694 }; 3695 static const unsigned int sdhi3_data4_mux[] = { 3696 SD3_DAT0_MARK, SD3_DAT1_MARK, 3697 SD3_DAT2_MARK, SD3_DAT3_MARK, 3698 }; 3699 static const unsigned int sdhi3_data8_pins[] = { 3700 /* D[0:7] */ 3701 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10), 3702 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12), 3703 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14), 3704 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16), 3705 }; 3706 static const unsigned int sdhi3_data8_mux[] = { 3707 SD3_DAT0_MARK, SD3_DAT1_MARK, 3708 SD3_DAT2_MARK, SD3_DAT3_MARK, 3709 SD3_DAT4_MARK, SD3_DAT5_MARK, 3710 SD3_DAT6_MARK, SD3_DAT7_MARK, 3711 }; 3712 static const unsigned int sdhi3_ctrl_pins[] = { 3713 /* CLK, CMD */ 3714 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8), 3715 }; 3716 static const unsigned int sdhi3_ctrl_mux[] = { 3717 SD3_CLK_MARK, SD3_CMD_MARK, 3718 }; 3719 static const unsigned int sdhi3_cd_pins[] = { 3720 /* CD */ 3721 RCAR_GP_PIN(4, 15), 3722 }; 3723 static const unsigned int sdhi3_cd_mux[] = { 3724 SD3_CD_MARK, 3725 }; 3726 static const unsigned int sdhi3_wp_pins[] = { 3727 /* WP */ 3728 RCAR_GP_PIN(4, 16), 3729 }; 3730 static const unsigned int sdhi3_wp_mux[] = { 3731 SD3_WP_MARK, 3732 }; 3733 static const unsigned int sdhi3_ds_pins[] = { 3734 /* DS */ 3735 RCAR_GP_PIN(4, 17), 3736 }; 3737 static const unsigned int sdhi3_ds_mux[] = { 3738 SD3_DS_MARK, 3739 }; 3740 3741 /* - SSI -------------------------------------------------------------------- */ 3742 static const unsigned int ssi0_data_pins[] = { 3743 /* SDATA */ 3744 RCAR_GP_PIN(6, 2), 3745 }; 3746 static const unsigned int ssi0_data_mux[] = { 3747 SSI_SDATA0_MARK, 3748 }; 3749 static const unsigned int ssi01239_ctrl_pins[] = { 3750 /* SCK, WS */ 3751 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1), 3752 }; 3753 static const unsigned int ssi01239_ctrl_mux[] = { 3754 SSI_SCK01239_MARK, SSI_WS01239_MARK, 3755 }; 3756 static const unsigned int ssi1_data_a_pins[] = { 3757 /* SDATA */ 3758 RCAR_GP_PIN(6, 3), 3759 }; 3760 static const unsigned int ssi1_data_a_mux[] = { 3761 SSI_SDATA1_A_MARK, 3762 }; 3763 static const unsigned int ssi1_data_b_pins[] = { 3764 /* SDATA */ 3765 RCAR_GP_PIN(5, 12), 3766 }; 3767 static const unsigned int ssi1_data_b_mux[] = { 3768 SSI_SDATA1_B_MARK, 3769 }; 3770 static const unsigned int ssi1_ctrl_a_pins[] = { 3771 /* SCK, WS */ 3772 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27), 3773 }; 3774 static const unsigned int ssi1_ctrl_a_mux[] = { 3775 SSI_SCK1_A_MARK, SSI_WS1_A_MARK, 3776 }; 3777 static const unsigned int ssi1_ctrl_b_pins[] = { 3778 /* SCK, WS */ 3779 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21), 3780 }; 3781 static const unsigned int ssi1_ctrl_b_mux[] = { 3782 SSI_SCK1_B_MARK, SSI_WS1_B_MARK, 3783 }; 3784 static const unsigned int ssi2_data_a_pins[] = { 3785 /* SDATA */ 3786 RCAR_GP_PIN(6, 4), 3787 }; 3788 static const unsigned int ssi2_data_a_mux[] = { 3789 SSI_SDATA2_A_MARK, 3790 }; 3791 static const unsigned int ssi2_data_b_pins[] = { 3792 /* SDATA */ 3793 RCAR_GP_PIN(5, 13), 3794 }; 3795 static const unsigned int ssi2_data_b_mux[] = { 3796 SSI_SDATA2_B_MARK, 3797 }; 3798 static const unsigned int ssi2_ctrl_a_pins[] = { 3799 /* SCK, WS */ 3800 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21), 3801 }; 3802 static const unsigned int ssi2_ctrl_a_mux[] = { 3803 SSI_SCK2_A_MARK, SSI_WS2_A_MARK, 3804 }; 3805 static const unsigned int ssi2_ctrl_b_pins[] = { 3806 /* SCK, WS */ 3807 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29), 3808 }; 3809 static const unsigned int ssi2_ctrl_b_mux[] = { 3810 SSI_SCK2_B_MARK, SSI_WS2_B_MARK, 3811 }; 3812 static const unsigned int ssi3_data_pins[] = { 3813 /* SDATA */ 3814 RCAR_GP_PIN(6, 7), 3815 }; 3816 static const unsigned int ssi3_data_mux[] = { 3817 SSI_SDATA3_MARK, 3818 }; 3819 static const unsigned int ssi349_ctrl_pins[] = { 3820 /* SCK, WS */ 3821 RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6), 3822 }; 3823 static const unsigned int ssi349_ctrl_mux[] = { 3824 SSI_SCK349_MARK, SSI_WS349_MARK, 3825 }; 3826 static const unsigned int ssi4_data_pins[] = { 3827 /* SDATA */ 3828 RCAR_GP_PIN(6, 10), 3829 }; 3830 static const unsigned int ssi4_data_mux[] = { 3831 SSI_SDATA4_MARK, 3832 }; 3833 static const unsigned int ssi4_ctrl_pins[] = { 3834 /* SCK, WS */ 3835 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), 3836 }; 3837 static const unsigned int ssi4_ctrl_mux[] = { 3838 SSI_SCK4_MARK, SSI_WS4_MARK, 3839 }; 3840 static const unsigned int ssi5_data_pins[] = { 3841 /* SDATA */ 3842 RCAR_GP_PIN(6, 13), 3843 }; 3844 static const unsigned int ssi5_data_mux[] = { 3845 SSI_SDATA5_MARK, 3846 }; 3847 static const unsigned int ssi5_ctrl_pins[] = { 3848 /* SCK, WS */ 3849 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12), 3850 }; 3851 static const unsigned int ssi5_ctrl_mux[] = { 3852 SSI_SCK5_MARK, SSI_WS5_MARK, 3853 }; 3854 static const unsigned int ssi6_data_pins[] = { 3855 /* SDATA */ 3856 RCAR_GP_PIN(6, 16), 3857 }; 3858 static const unsigned int ssi6_data_mux[] = { 3859 SSI_SDATA6_MARK, 3860 }; 3861 static const unsigned int ssi6_ctrl_pins[] = { 3862 /* SCK, WS */ 3863 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15), 3864 }; 3865 static const unsigned int ssi6_ctrl_mux[] = { 3866 SSI_SCK6_MARK, SSI_WS6_MARK, 3867 }; 3868 static const unsigned int ssi7_data_pins[] = { 3869 /* SDATA */ 3870 RCAR_GP_PIN(6, 19), 3871 }; 3872 static const unsigned int ssi7_data_mux[] = { 3873 SSI_SDATA7_MARK, 3874 }; 3875 static const unsigned int ssi78_ctrl_pins[] = { 3876 /* SCK, WS */ 3877 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18), 3878 }; 3879 static const unsigned int ssi78_ctrl_mux[] = { 3880 SSI_SCK78_MARK, SSI_WS78_MARK, 3881 }; 3882 static const unsigned int ssi8_data_pins[] = { 3883 /* SDATA */ 3884 RCAR_GP_PIN(6, 20), 3885 }; 3886 static const unsigned int ssi8_data_mux[] = { 3887 SSI_SDATA8_MARK, 3888 }; 3889 static const unsigned int ssi9_data_a_pins[] = { 3890 /* SDATA */ 3891 RCAR_GP_PIN(6, 21), 3892 }; 3893 static const unsigned int ssi9_data_a_mux[] = { 3894 SSI_SDATA9_A_MARK, 3895 }; 3896 static const unsigned int ssi9_data_b_pins[] = { 3897 /* SDATA */ 3898 RCAR_GP_PIN(5, 14), 3899 }; 3900 static const unsigned int ssi9_data_b_mux[] = { 3901 SSI_SDATA9_B_MARK, 3902 }; 3903 static const unsigned int ssi9_ctrl_a_pins[] = { 3904 /* SCK, WS */ 3905 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16), 3906 }; 3907 static const unsigned int ssi9_ctrl_a_mux[] = { 3908 SSI_SCK9_A_MARK, SSI_WS9_A_MARK, 3909 }; 3910 static const unsigned int ssi9_ctrl_b_pins[] = { 3911 /* SCK, WS */ 3912 RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31), 3913 }; 3914 static const unsigned int ssi9_ctrl_b_mux[] = { 3915 SSI_SCK9_B_MARK, SSI_WS9_B_MARK, 3916 }; 3917 3918 /* - TMU -------------------------------------------------------------------- */ 3919 static const unsigned int tmu_tclk1_a_pins[] = { 3920 /* TCLK */ 3921 RCAR_GP_PIN(6, 23), 3922 }; 3923 static const unsigned int tmu_tclk1_a_mux[] = { 3924 TCLK1_A_MARK, 3925 }; 3926 static const unsigned int tmu_tclk1_b_pins[] = { 3927 /* TCLK */ 3928 RCAR_GP_PIN(5, 19), 3929 }; 3930 static const unsigned int tmu_tclk1_b_mux[] = { 3931 TCLK1_B_MARK, 3932 }; 3933 static const unsigned int tmu_tclk2_a_pins[] = { 3934 /* TCLK */ 3935 RCAR_GP_PIN(6, 19), 3936 }; 3937 static const unsigned int tmu_tclk2_a_mux[] = { 3938 TCLK2_A_MARK, 3939 }; 3940 static const unsigned int tmu_tclk2_b_pins[] = { 3941 /* TCLK */ 3942 RCAR_GP_PIN(6, 28), 3943 }; 3944 static const unsigned int tmu_tclk2_b_mux[] = { 3945 TCLK2_B_MARK, 3946 }; 3947 3948 /* - TPU ------------------------------------------------------------------- */ 3949 static const unsigned int tpu_to0_pins[] = { 3950 /* TPU0TO0 */ 3951 RCAR_GP_PIN(6, 28), 3952 }; 3953 static const unsigned int tpu_to0_mux[] = { 3954 TPU0TO0_MARK, 3955 }; 3956 static const unsigned int tpu_to1_pins[] = { 3957 /* TPU0TO1 */ 3958 RCAR_GP_PIN(6, 29), 3959 }; 3960 static const unsigned int tpu_to1_mux[] = { 3961 TPU0TO1_MARK, 3962 }; 3963 static const unsigned int tpu_to2_pins[] = { 3964 /* TPU0TO2 */ 3965 RCAR_GP_PIN(6, 30), 3966 }; 3967 static const unsigned int tpu_to2_mux[] = { 3968 TPU0TO2_MARK, 3969 }; 3970 static const unsigned int tpu_to3_pins[] = { 3971 /* TPU0TO3 */ 3972 RCAR_GP_PIN(6, 31), 3973 }; 3974 static const unsigned int tpu_to3_mux[] = { 3975 TPU0TO3_MARK, 3976 }; 3977 3978 /* - USB0 ------------------------------------------------------------------- */ 3979 static const unsigned int usb0_pins[] = { 3980 /* PWEN, OVC */ 3981 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25), 3982 }; 3983 static const unsigned int usb0_mux[] = { 3984 USB0_PWEN_MARK, USB0_OVC_MARK, 3985 }; 3986 /* - USB1 ------------------------------------------------------------------- */ 3987 static const unsigned int usb1_pins[] = { 3988 /* PWEN, OVC */ 3989 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27), 3990 }; 3991 static const unsigned int usb1_mux[] = { 3992 USB1_PWEN_MARK, USB1_OVC_MARK, 3993 }; 3994 /* - USB2 ------------------------------------------------------------------- */ 3995 static const unsigned int usb2_pins[] = { 3996 /* PWEN, OVC */ 3997 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15), 3998 }; 3999 static const unsigned int usb2_mux[] = { 4000 USB2_PWEN_MARK, USB2_OVC_MARK, 4001 }; 4002 /* - USB2_CH3 --------------------------------------------------------------- */ 4003 static const unsigned int usb2_ch3_pins[] = { 4004 /* PWEN, OVC */ 4005 RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31), 4006 }; 4007 static const unsigned int usb2_ch3_mux[] = { 4008 USB2_CH3_PWEN_MARK, USB2_CH3_OVC_MARK, 4009 }; 4010 4011 /* - USB30 ------------------------------------------------------------------ */ 4012 static const unsigned int usb30_pins[] = { 4013 /* PWEN, OVC */ 4014 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29), 4015 }; 4016 static const unsigned int usb30_mux[] = { 4017 USB30_PWEN_MARK, USB30_OVC_MARK, 4018 }; 4019 4020 /* - VIN4 ------------------------------------------------------------------- */ 4021 static const unsigned int vin4_data18_a_pins[] = { 4022 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), 4023 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), 4024 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), 4025 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), 4026 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), 4027 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 4028 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), 4029 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), 4030 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), 4031 }; 4032 static const unsigned int vin4_data18_a_mux[] = { 4033 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK, 4034 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK, 4035 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK, 4036 VI4_DATA10_MARK, VI4_DATA11_MARK, 4037 VI4_DATA12_MARK, VI4_DATA13_MARK, 4038 VI4_DATA14_MARK, VI4_DATA15_MARK, 4039 VI4_DATA18_MARK, VI4_DATA19_MARK, 4040 VI4_DATA20_MARK, VI4_DATA21_MARK, 4041 VI4_DATA22_MARK, VI4_DATA23_MARK, 4042 }; 4043 static const unsigned int vin4_data18_b_pins[] = { 4044 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), 4045 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), 4046 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), 4047 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), 4048 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), 4049 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 4050 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), 4051 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), 4052 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), 4053 }; 4054 static const unsigned int vin4_data18_b_mux[] = { 4055 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK, 4056 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK, 4057 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK, 4058 VI4_DATA10_MARK, VI4_DATA11_MARK, 4059 VI4_DATA12_MARK, VI4_DATA13_MARK, 4060 VI4_DATA14_MARK, VI4_DATA15_MARK, 4061 VI4_DATA18_MARK, VI4_DATA19_MARK, 4062 VI4_DATA20_MARK, VI4_DATA21_MARK, 4063 VI4_DATA22_MARK, VI4_DATA23_MARK, 4064 }; 4065 static const union vin_data vin4_data_a_pins = { 4066 .data24 = { 4067 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), 4068 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), 4069 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), 4070 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), 4071 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), 4072 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), 4073 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), 4074 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 4075 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), 4076 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), 4077 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), 4078 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), 4079 }, 4080 }; 4081 static const union vin_data vin4_data_a_mux = { 4082 .data24 = { 4083 VI4_DATA0_A_MARK, VI4_DATA1_A_MARK, 4084 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK, 4085 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK, 4086 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK, 4087 VI4_DATA8_MARK, VI4_DATA9_MARK, 4088 VI4_DATA10_MARK, VI4_DATA11_MARK, 4089 VI4_DATA12_MARK, VI4_DATA13_MARK, 4090 VI4_DATA14_MARK, VI4_DATA15_MARK, 4091 VI4_DATA16_MARK, VI4_DATA17_MARK, 4092 VI4_DATA18_MARK, VI4_DATA19_MARK, 4093 VI4_DATA20_MARK, VI4_DATA21_MARK, 4094 VI4_DATA22_MARK, VI4_DATA23_MARK, 4095 }, 4096 }; 4097 static const union vin_data vin4_data_b_pins = { 4098 .data24 = { 4099 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), 4100 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), 4101 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), 4102 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), 4103 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), 4104 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), 4105 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), 4106 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 4107 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), 4108 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), 4109 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), 4110 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), 4111 }, 4112 }; 4113 static const union vin_data vin4_data_b_mux = { 4114 .data24 = { 4115 VI4_DATA0_B_MARK, VI4_DATA1_B_MARK, 4116 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK, 4117 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK, 4118 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK, 4119 VI4_DATA8_MARK, VI4_DATA9_MARK, 4120 VI4_DATA10_MARK, VI4_DATA11_MARK, 4121 VI4_DATA12_MARK, VI4_DATA13_MARK, 4122 VI4_DATA14_MARK, VI4_DATA15_MARK, 4123 VI4_DATA16_MARK, VI4_DATA17_MARK, 4124 VI4_DATA18_MARK, VI4_DATA19_MARK, 4125 VI4_DATA20_MARK, VI4_DATA21_MARK, 4126 VI4_DATA22_MARK, VI4_DATA23_MARK, 4127 }, 4128 }; 4129 static const unsigned int vin4_sync_pins[] = { 4130 /* HSYNC#, VSYNC# */ 4131 RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 17), 4132 }; 4133 static const unsigned int vin4_sync_mux[] = { 4134 VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK, 4135 }; 4136 static const unsigned int vin4_field_pins[] = { 4137 /* FIELD */ 4138 RCAR_GP_PIN(1, 16), 4139 }; 4140 static const unsigned int vin4_field_mux[] = { 4141 VI4_FIELD_MARK, 4142 }; 4143 static const unsigned int vin4_clkenb_pins[] = { 4144 /* CLKENB */ 4145 RCAR_GP_PIN(1, 19), 4146 }; 4147 static const unsigned int vin4_clkenb_mux[] = { 4148 VI4_CLKENB_MARK, 4149 }; 4150 static const unsigned int vin4_clk_pins[] = { 4151 /* CLK */ 4152 RCAR_GP_PIN(1, 27), 4153 }; 4154 static const unsigned int vin4_clk_mux[] = { 4155 VI4_CLK_MARK, 4156 }; 4157 4158 /* - VIN5 ------------------------------------------------------------------- */ 4159 static const union vin_data16 vin5_data_pins = { 4160 .data16 = { 4161 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), 4162 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), 4163 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), 4164 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), 4165 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), 4166 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), 4167 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), 4168 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 4169 }, 4170 }; 4171 static const union vin_data16 vin5_data_mux = { 4172 .data16 = { 4173 VI5_DATA0_MARK, VI5_DATA1_MARK, 4174 VI5_DATA2_MARK, VI5_DATA3_MARK, 4175 VI5_DATA4_MARK, VI5_DATA5_MARK, 4176 VI5_DATA6_MARK, VI5_DATA7_MARK, 4177 VI5_DATA8_MARK, VI5_DATA9_MARK, 4178 VI5_DATA10_MARK, VI5_DATA11_MARK, 4179 VI5_DATA12_MARK, VI5_DATA13_MARK, 4180 VI5_DATA14_MARK, VI5_DATA15_MARK, 4181 }, 4182 }; 4183 static const unsigned int vin5_sync_pins[] = { 4184 /* HSYNC#, VSYNC# */ 4185 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9), 4186 }; 4187 static const unsigned int vin5_sync_mux[] = { 4188 VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK, 4189 }; 4190 static const unsigned int vin5_field_pins[] = { 4191 RCAR_GP_PIN(1, 11), 4192 }; 4193 static const unsigned int vin5_field_mux[] = { 4194 /* FIELD */ 4195 VI5_FIELD_MARK, 4196 }; 4197 static const unsigned int vin5_clkenb_pins[] = { 4198 RCAR_GP_PIN(1, 20), 4199 }; 4200 static const unsigned int vin5_clkenb_mux[] = { 4201 /* CLKENB */ 4202 VI5_CLKENB_MARK, 4203 }; 4204 static const unsigned int vin5_clk_pins[] = { 4205 RCAR_GP_PIN(1, 21), 4206 }; 4207 static const unsigned int vin5_clk_mux[] = { 4208 /* CLK */ 4209 VI5_CLK_MARK, 4210 }; 4211 4212 static const struct { 4213 struct sh_pfc_pin_group common[326]; 4214 #ifdef CONFIG_PINCTRL_PFC_R8A77951 4215 struct sh_pfc_pin_group automotive[30]; 4216 #endif 4217 } pinmux_groups = { 4218 .common = { 4219 SH_PFC_PIN_GROUP(audio_clk_a_a), 4220 SH_PFC_PIN_GROUP(audio_clk_a_b), 4221 SH_PFC_PIN_GROUP(audio_clk_a_c), 4222 SH_PFC_PIN_GROUP(audio_clk_b_a), 4223 SH_PFC_PIN_GROUP(audio_clk_b_b), 4224 SH_PFC_PIN_GROUP(audio_clk_c_a), 4225 SH_PFC_PIN_GROUP(audio_clk_c_b), 4226 SH_PFC_PIN_GROUP(audio_clkout_a), 4227 SH_PFC_PIN_GROUP(audio_clkout_b), 4228 SH_PFC_PIN_GROUP(audio_clkout_c), 4229 SH_PFC_PIN_GROUP(audio_clkout_d), 4230 SH_PFC_PIN_GROUP(audio_clkout1_a), 4231 SH_PFC_PIN_GROUP(audio_clkout1_b), 4232 SH_PFC_PIN_GROUP(audio_clkout2_a), 4233 SH_PFC_PIN_GROUP(audio_clkout2_b), 4234 SH_PFC_PIN_GROUP(audio_clkout3_a), 4235 SH_PFC_PIN_GROUP(audio_clkout3_b), 4236 SH_PFC_PIN_GROUP(avb_link), 4237 SH_PFC_PIN_GROUP(avb_magic), 4238 SH_PFC_PIN_GROUP(avb_phy_int), 4239 SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio), /* Deprecated */ 4240 SH_PFC_PIN_GROUP(avb_mdio), 4241 SH_PFC_PIN_GROUP(avb_mii), 4242 SH_PFC_PIN_GROUP(avb_avtp_pps), 4243 SH_PFC_PIN_GROUP(avb_avtp_match_a), 4244 SH_PFC_PIN_GROUP(avb_avtp_capture_a), 4245 SH_PFC_PIN_GROUP(avb_avtp_match_b), 4246 SH_PFC_PIN_GROUP(avb_avtp_capture_b), 4247 SH_PFC_PIN_GROUP(can0_data_a), 4248 SH_PFC_PIN_GROUP(can0_data_b), 4249 SH_PFC_PIN_GROUP(can1_data), 4250 SH_PFC_PIN_GROUP(can_clk), 4251 SH_PFC_PIN_GROUP(canfd0_data_a), 4252 SH_PFC_PIN_GROUP(canfd0_data_b), 4253 SH_PFC_PIN_GROUP(canfd1_data), 4254 SH_PFC_PIN_GROUP(du_rgb666), 4255 SH_PFC_PIN_GROUP(du_rgb888), 4256 SH_PFC_PIN_GROUP(du_clk_out_0), 4257 SH_PFC_PIN_GROUP(du_clk_out_1), 4258 SH_PFC_PIN_GROUP(du_sync), 4259 SH_PFC_PIN_GROUP(du_oddf), 4260 SH_PFC_PIN_GROUP(du_cde), 4261 SH_PFC_PIN_GROUP(du_disp), 4262 SH_PFC_PIN_GROUP(hscif0_data), 4263 SH_PFC_PIN_GROUP(hscif0_clk), 4264 SH_PFC_PIN_GROUP(hscif0_ctrl), 4265 SH_PFC_PIN_GROUP(hscif1_data_a), 4266 SH_PFC_PIN_GROUP(hscif1_clk_a), 4267 SH_PFC_PIN_GROUP(hscif1_ctrl_a), 4268 SH_PFC_PIN_GROUP(hscif1_data_b), 4269 SH_PFC_PIN_GROUP(hscif1_clk_b), 4270 SH_PFC_PIN_GROUP(hscif1_ctrl_b), 4271 SH_PFC_PIN_GROUP(hscif2_data_a), 4272 SH_PFC_PIN_GROUP(hscif2_clk_a), 4273 SH_PFC_PIN_GROUP(hscif2_ctrl_a), 4274 SH_PFC_PIN_GROUP(hscif2_data_b), 4275 SH_PFC_PIN_GROUP(hscif2_clk_b), 4276 SH_PFC_PIN_GROUP(hscif2_ctrl_b), 4277 SH_PFC_PIN_GROUP(hscif2_data_c), 4278 SH_PFC_PIN_GROUP(hscif2_clk_c), 4279 SH_PFC_PIN_GROUP(hscif2_ctrl_c), 4280 SH_PFC_PIN_GROUP(hscif3_data_a), 4281 SH_PFC_PIN_GROUP(hscif3_clk), 4282 SH_PFC_PIN_GROUP(hscif3_ctrl), 4283 SH_PFC_PIN_GROUP(hscif3_data_b), 4284 SH_PFC_PIN_GROUP(hscif3_data_c), 4285 SH_PFC_PIN_GROUP(hscif3_data_d), 4286 SH_PFC_PIN_GROUP(hscif4_data_a), 4287 SH_PFC_PIN_GROUP(hscif4_clk), 4288 SH_PFC_PIN_GROUP(hscif4_ctrl), 4289 SH_PFC_PIN_GROUP(hscif4_data_b), 4290 SH_PFC_PIN_GROUP(i2c0), 4291 SH_PFC_PIN_GROUP(i2c1_a), 4292 SH_PFC_PIN_GROUP(i2c1_b), 4293 SH_PFC_PIN_GROUP(i2c2_a), 4294 SH_PFC_PIN_GROUP(i2c2_b), 4295 SH_PFC_PIN_GROUP(i2c3), 4296 SH_PFC_PIN_GROUP(i2c5), 4297 SH_PFC_PIN_GROUP(i2c6_a), 4298 SH_PFC_PIN_GROUP(i2c6_b), 4299 SH_PFC_PIN_GROUP(i2c6_c), 4300 SH_PFC_PIN_GROUP(intc_ex_irq0), 4301 SH_PFC_PIN_GROUP(intc_ex_irq1), 4302 SH_PFC_PIN_GROUP(intc_ex_irq2), 4303 SH_PFC_PIN_GROUP(intc_ex_irq3), 4304 SH_PFC_PIN_GROUP(intc_ex_irq4), 4305 SH_PFC_PIN_GROUP(intc_ex_irq5), 4306 SH_PFC_PIN_GROUP(msiof0_clk), 4307 SH_PFC_PIN_GROUP(msiof0_sync), 4308 SH_PFC_PIN_GROUP(msiof0_ss1), 4309 SH_PFC_PIN_GROUP(msiof0_ss2), 4310 SH_PFC_PIN_GROUP(msiof0_txd), 4311 SH_PFC_PIN_GROUP(msiof0_rxd), 4312 SH_PFC_PIN_GROUP(msiof1_clk_a), 4313 SH_PFC_PIN_GROUP(msiof1_sync_a), 4314 SH_PFC_PIN_GROUP(msiof1_ss1_a), 4315 SH_PFC_PIN_GROUP(msiof1_ss2_a), 4316 SH_PFC_PIN_GROUP(msiof1_txd_a), 4317 SH_PFC_PIN_GROUP(msiof1_rxd_a), 4318 SH_PFC_PIN_GROUP(msiof1_clk_b), 4319 SH_PFC_PIN_GROUP(msiof1_sync_b), 4320 SH_PFC_PIN_GROUP(msiof1_ss1_b), 4321 SH_PFC_PIN_GROUP(msiof1_ss2_b), 4322 SH_PFC_PIN_GROUP(msiof1_txd_b), 4323 SH_PFC_PIN_GROUP(msiof1_rxd_b), 4324 SH_PFC_PIN_GROUP(msiof1_clk_c), 4325 SH_PFC_PIN_GROUP(msiof1_sync_c), 4326 SH_PFC_PIN_GROUP(msiof1_ss1_c), 4327 SH_PFC_PIN_GROUP(msiof1_ss2_c), 4328 SH_PFC_PIN_GROUP(msiof1_txd_c), 4329 SH_PFC_PIN_GROUP(msiof1_rxd_c), 4330 SH_PFC_PIN_GROUP(msiof1_clk_d), 4331 SH_PFC_PIN_GROUP(msiof1_sync_d), 4332 SH_PFC_PIN_GROUP(msiof1_ss1_d), 4333 SH_PFC_PIN_GROUP(msiof1_ss2_d), 4334 SH_PFC_PIN_GROUP(msiof1_txd_d), 4335 SH_PFC_PIN_GROUP(msiof1_rxd_d), 4336 SH_PFC_PIN_GROUP(msiof1_clk_e), 4337 SH_PFC_PIN_GROUP(msiof1_sync_e), 4338 SH_PFC_PIN_GROUP(msiof1_ss1_e), 4339 SH_PFC_PIN_GROUP(msiof1_ss2_e), 4340 SH_PFC_PIN_GROUP(msiof1_txd_e), 4341 SH_PFC_PIN_GROUP(msiof1_rxd_e), 4342 SH_PFC_PIN_GROUP(msiof1_clk_f), 4343 SH_PFC_PIN_GROUP(msiof1_sync_f), 4344 SH_PFC_PIN_GROUP(msiof1_ss1_f), 4345 SH_PFC_PIN_GROUP(msiof1_ss2_f), 4346 SH_PFC_PIN_GROUP(msiof1_txd_f), 4347 SH_PFC_PIN_GROUP(msiof1_rxd_f), 4348 SH_PFC_PIN_GROUP(msiof1_clk_g), 4349 SH_PFC_PIN_GROUP(msiof1_sync_g), 4350 SH_PFC_PIN_GROUP(msiof1_ss1_g), 4351 SH_PFC_PIN_GROUP(msiof1_ss2_g), 4352 SH_PFC_PIN_GROUP(msiof1_txd_g), 4353 SH_PFC_PIN_GROUP(msiof1_rxd_g), 4354 SH_PFC_PIN_GROUP(msiof2_clk_a), 4355 SH_PFC_PIN_GROUP(msiof2_sync_a), 4356 SH_PFC_PIN_GROUP(msiof2_ss1_a), 4357 SH_PFC_PIN_GROUP(msiof2_ss2_a), 4358 SH_PFC_PIN_GROUP(msiof2_txd_a), 4359 SH_PFC_PIN_GROUP(msiof2_rxd_a), 4360 SH_PFC_PIN_GROUP(msiof2_clk_b), 4361 SH_PFC_PIN_GROUP(msiof2_sync_b), 4362 SH_PFC_PIN_GROUP(msiof2_ss1_b), 4363 SH_PFC_PIN_GROUP(msiof2_ss2_b), 4364 SH_PFC_PIN_GROUP(msiof2_txd_b), 4365 SH_PFC_PIN_GROUP(msiof2_rxd_b), 4366 SH_PFC_PIN_GROUP(msiof2_clk_c), 4367 SH_PFC_PIN_GROUP(msiof2_sync_c), 4368 SH_PFC_PIN_GROUP(msiof2_ss1_c), 4369 SH_PFC_PIN_GROUP(msiof2_ss2_c), 4370 SH_PFC_PIN_GROUP(msiof2_txd_c), 4371 SH_PFC_PIN_GROUP(msiof2_rxd_c), 4372 SH_PFC_PIN_GROUP(msiof2_clk_d), 4373 SH_PFC_PIN_GROUP(msiof2_sync_d), 4374 SH_PFC_PIN_GROUP(msiof2_ss1_d), 4375 SH_PFC_PIN_GROUP(msiof2_ss2_d), 4376 SH_PFC_PIN_GROUP(msiof2_txd_d), 4377 SH_PFC_PIN_GROUP(msiof2_rxd_d), 4378 SH_PFC_PIN_GROUP(msiof3_clk_a), 4379 SH_PFC_PIN_GROUP(msiof3_sync_a), 4380 SH_PFC_PIN_GROUP(msiof3_ss1_a), 4381 SH_PFC_PIN_GROUP(msiof3_ss2_a), 4382 SH_PFC_PIN_GROUP(msiof3_txd_a), 4383 SH_PFC_PIN_GROUP(msiof3_rxd_a), 4384 SH_PFC_PIN_GROUP(msiof3_clk_b), 4385 SH_PFC_PIN_GROUP(msiof3_sync_b), 4386 SH_PFC_PIN_GROUP(msiof3_ss1_b), 4387 SH_PFC_PIN_GROUP(msiof3_ss2_b), 4388 SH_PFC_PIN_GROUP(msiof3_txd_b), 4389 SH_PFC_PIN_GROUP(msiof3_rxd_b), 4390 SH_PFC_PIN_GROUP(msiof3_clk_c), 4391 SH_PFC_PIN_GROUP(msiof3_sync_c), 4392 SH_PFC_PIN_GROUP(msiof3_txd_c), 4393 SH_PFC_PIN_GROUP(msiof3_rxd_c), 4394 SH_PFC_PIN_GROUP(msiof3_clk_d), 4395 SH_PFC_PIN_GROUP(msiof3_sync_d), 4396 SH_PFC_PIN_GROUP(msiof3_ss1_d), 4397 SH_PFC_PIN_GROUP(msiof3_txd_d), 4398 SH_PFC_PIN_GROUP(msiof3_rxd_d), 4399 SH_PFC_PIN_GROUP(msiof3_clk_e), 4400 SH_PFC_PIN_GROUP(msiof3_sync_e), 4401 SH_PFC_PIN_GROUP(msiof3_ss1_e), 4402 SH_PFC_PIN_GROUP(msiof3_ss2_e), 4403 SH_PFC_PIN_GROUP(msiof3_txd_e), 4404 SH_PFC_PIN_GROUP(msiof3_rxd_e), 4405 SH_PFC_PIN_GROUP(pwm0), 4406 SH_PFC_PIN_GROUP(pwm1_a), 4407 SH_PFC_PIN_GROUP(pwm1_b), 4408 SH_PFC_PIN_GROUP(pwm2_a), 4409 SH_PFC_PIN_GROUP(pwm2_b), 4410 SH_PFC_PIN_GROUP(pwm3_a), 4411 SH_PFC_PIN_GROUP(pwm3_b), 4412 SH_PFC_PIN_GROUP(pwm4_a), 4413 SH_PFC_PIN_GROUP(pwm4_b), 4414 SH_PFC_PIN_GROUP(pwm5_a), 4415 SH_PFC_PIN_GROUP(pwm5_b), 4416 SH_PFC_PIN_GROUP(pwm6_a), 4417 SH_PFC_PIN_GROUP(pwm6_b), 4418 SH_PFC_PIN_GROUP(qspi0_ctrl), 4419 SH_PFC_PIN_GROUP(qspi0_data2), 4420 SH_PFC_PIN_GROUP(qspi0_data4), 4421 SH_PFC_PIN_GROUP(qspi1_ctrl), 4422 SH_PFC_PIN_GROUP(qspi1_data2), 4423 SH_PFC_PIN_GROUP(qspi1_data4), 4424 SH_PFC_PIN_GROUP(sata0_devslp_a), 4425 SH_PFC_PIN_GROUP(sata0_devslp_b), 4426 SH_PFC_PIN_GROUP(scif0_data), 4427 SH_PFC_PIN_GROUP(scif0_clk), 4428 SH_PFC_PIN_GROUP(scif0_ctrl), 4429 SH_PFC_PIN_GROUP(scif1_data_a), 4430 SH_PFC_PIN_GROUP(scif1_clk), 4431 SH_PFC_PIN_GROUP(scif1_ctrl), 4432 SH_PFC_PIN_GROUP(scif1_data_b), 4433 SH_PFC_PIN_GROUP(scif2_data_a), 4434 SH_PFC_PIN_GROUP(scif2_clk), 4435 SH_PFC_PIN_GROUP(scif2_data_b), 4436 SH_PFC_PIN_GROUP(scif3_data_a), 4437 SH_PFC_PIN_GROUP(scif3_clk), 4438 SH_PFC_PIN_GROUP(scif3_ctrl), 4439 SH_PFC_PIN_GROUP(scif3_data_b), 4440 SH_PFC_PIN_GROUP(scif4_data_a), 4441 SH_PFC_PIN_GROUP(scif4_clk_a), 4442 SH_PFC_PIN_GROUP(scif4_ctrl_a), 4443 SH_PFC_PIN_GROUP(scif4_data_b), 4444 SH_PFC_PIN_GROUP(scif4_clk_b), 4445 SH_PFC_PIN_GROUP(scif4_ctrl_b), 4446 SH_PFC_PIN_GROUP(scif4_data_c), 4447 SH_PFC_PIN_GROUP(scif4_clk_c), 4448 SH_PFC_PIN_GROUP(scif4_ctrl_c), 4449 SH_PFC_PIN_GROUP(scif5_data_a), 4450 SH_PFC_PIN_GROUP(scif5_clk_a), 4451 SH_PFC_PIN_GROUP(scif5_data_b), 4452 SH_PFC_PIN_GROUP(scif5_clk_b), 4453 SH_PFC_PIN_GROUP(scif_clk_a), 4454 SH_PFC_PIN_GROUP(scif_clk_b), 4455 SH_PFC_PIN_GROUP(sdhi0_data1), 4456 SH_PFC_PIN_GROUP(sdhi0_data4), 4457 SH_PFC_PIN_GROUP(sdhi0_ctrl), 4458 SH_PFC_PIN_GROUP(sdhi0_cd), 4459 SH_PFC_PIN_GROUP(sdhi0_wp), 4460 SH_PFC_PIN_GROUP(sdhi1_data1), 4461 SH_PFC_PIN_GROUP(sdhi1_data4), 4462 SH_PFC_PIN_GROUP(sdhi1_ctrl), 4463 SH_PFC_PIN_GROUP(sdhi1_cd), 4464 SH_PFC_PIN_GROUP(sdhi1_wp), 4465 SH_PFC_PIN_GROUP(sdhi2_data1), 4466 SH_PFC_PIN_GROUP(sdhi2_data4), 4467 SH_PFC_PIN_GROUP(sdhi2_data8), 4468 SH_PFC_PIN_GROUP(sdhi2_ctrl), 4469 SH_PFC_PIN_GROUP(sdhi2_cd_a), 4470 SH_PFC_PIN_GROUP(sdhi2_wp_a), 4471 SH_PFC_PIN_GROUP(sdhi2_cd_b), 4472 SH_PFC_PIN_GROUP(sdhi2_wp_b), 4473 SH_PFC_PIN_GROUP(sdhi2_ds), 4474 SH_PFC_PIN_GROUP(sdhi3_data1), 4475 SH_PFC_PIN_GROUP(sdhi3_data4), 4476 SH_PFC_PIN_GROUP(sdhi3_data8), 4477 SH_PFC_PIN_GROUP(sdhi3_ctrl), 4478 SH_PFC_PIN_GROUP(sdhi3_cd), 4479 SH_PFC_PIN_GROUP(sdhi3_wp), 4480 SH_PFC_PIN_GROUP(sdhi3_ds), 4481 SH_PFC_PIN_GROUP(ssi0_data), 4482 SH_PFC_PIN_GROUP(ssi01239_ctrl), 4483 SH_PFC_PIN_GROUP(ssi1_data_a), 4484 SH_PFC_PIN_GROUP(ssi1_data_b), 4485 SH_PFC_PIN_GROUP(ssi1_ctrl_a), 4486 SH_PFC_PIN_GROUP(ssi1_ctrl_b), 4487 SH_PFC_PIN_GROUP(ssi2_data_a), 4488 SH_PFC_PIN_GROUP(ssi2_data_b), 4489 SH_PFC_PIN_GROUP(ssi2_ctrl_a), 4490 SH_PFC_PIN_GROUP(ssi2_ctrl_b), 4491 SH_PFC_PIN_GROUP(ssi3_data), 4492 SH_PFC_PIN_GROUP(ssi349_ctrl), 4493 SH_PFC_PIN_GROUP(ssi4_data), 4494 SH_PFC_PIN_GROUP(ssi4_ctrl), 4495 SH_PFC_PIN_GROUP(ssi5_data), 4496 SH_PFC_PIN_GROUP(ssi5_ctrl), 4497 SH_PFC_PIN_GROUP(ssi6_data), 4498 SH_PFC_PIN_GROUP(ssi6_ctrl), 4499 SH_PFC_PIN_GROUP(ssi7_data), 4500 SH_PFC_PIN_GROUP(ssi78_ctrl), 4501 SH_PFC_PIN_GROUP(ssi8_data), 4502 SH_PFC_PIN_GROUP(ssi9_data_a), 4503 SH_PFC_PIN_GROUP(ssi9_data_b), 4504 SH_PFC_PIN_GROUP(ssi9_ctrl_a), 4505 SH_PFC_PIN_GROUP(ssi9_ctrl_b), 4506 SH_PFC_PIN_GROUP(tmu_tclk1_a), 4507 SH_PFC_PIN_GROUP(tmu_tclk1_b), 4508 SH_PFC_PIN_GROUP(tmu_tclk2_a), 4509 SH_PFC_PIN_GROUP(tmu_tclk2_b), 4510 SH_PFC_PIN_GROUP(tpu_to0), 4511 SH_PFC_PIN_GROUP(tpu_to1), 4512 SH_PFC_PIN_GROUP(tpu_to2), 4513 SH_PFC_PIN_GROUP(tpu_to3), 4514 SH_PFC_PIN_GROUP(usb0), 4515 SH_PFC_PIN_GROUP(usb1), 4516 SH_PFC_PIN_GROUP(usb2), 4517 SH_PFC_PIN_GROUP(usb2_ch3), 4518 SH_PFC_PIN_GROUP(usb30), 4519 VIN_DATA_PIN_GROUP(vin4_data, 8, _a), 4520 VIN_DATA_PIN_GROUP(vin4_data, 10, _a), 4521 VIN_DATA_PIN_GROUP(vin4_data, 12, _a), 4522 VIN_DATA_PIN_GROUP(vin4_data, 16, _a), 4523 SH_PFC_PIN_GROUP(vin4_data18_a), 4524 VIN_DATA_PIN_GROUP(vin4_data, 20, _a), 4525 VIN_DATA_PIN_GROUP(vin4_data, 24, _a), 4526 VIN_DATA_PIN_GROUP(vin4_data, 8, _b), 4527 VIN_DATA_PIN_GROUP(vin4_data, 10, _b), 4528 VIN_DATA_PIN_GROUP(vin4_data, 12, _b), 4529 VIN_DATA_PIN_GROUP(vin4_data, 16, _b), 4530 SH_PFC_PIN_GROUP(vin4_data18_b), 4531 VIN_DATA_PIN_GROUP(vin4_data, 20, _b), 4532 VIN_DATA_PIN_GROUP(vin4_data, 24, _b), 4533 SH_PFC_PIN_GROUP(vin4_sync), 4534 SH_PFC_PIN_GROUP(vin4_field), 4535 SH_PFC_PIN_GROUP(vin4_clkenb), 4536 SH_PFC_PIN_GROUP(vin4_clk), 4537 VIN_DATA_PIN_GROUP(vin5_data, 8), 4538 VIN_DATA_PIN_GROUP(vin5_data, 10), 4539 VIN_DATA_PIN_GROUP(vin5_data, 12), 4540 VIN_DATA_PIN_GROUP(vin5_data, 16), 4541 SH_PFC_PIN_GROUP(vin5_sync), 4542 SH_PFC_PIN_GROUP(vin5_field), 4543 SH_PFC_PIN_GROUP(vin5_clkenb), 4544 SH_PFC_PIN_GROUP(vin5_clk), 4545 }, 4546 #ifdef CONFIG_PINCTRL_PFC_R8A77951 4547 .automotive = { 4548 SH_PFC_PIN_GROUP(drif0_ctrl_a), 4549 SH_PFC_PIN_GROUP(drif0_data0_a), 4550 SH_PFC_PIN_GROUP(drif0_data1_a), 4551 SH_PFC_PIN_GROUP(drif0_ctrl_b), 4552 SH_PFC_PIN_GROUP(drif0_data0_b), 4553 SH_PFC_PIN_GROUP(drif0_data1_b), 4554 SH_PFC_PIN_GROUP(drif0_ctrl_c), 4555 SH_PFC_PIN_GROUP(drif0_data0_c), 4556 SH_PFC_PIN_GROUP(drif0_data1_c), 4557 SH_PFC_PIN_GROUP(drif1_ctrl_a), 4558 SH_PFC_PIN_GROUP(drif1_data0_a), 4559 SH_PFC_PIN_GROUP(drif1_data1_a), 4560 SH_PFC_PIN_GROUP(drif1_ctrl_b), 4561 SH_PFC_PIN_GROUP(drif1_data0_b), 4562 SH_PFC_PIN_GROUP(drif1_data1_b), 4563 SH_PFC_PIN_GROUP(drif1_ctrl_c), 4564 SH_PFC_PIN_GROUP(drif1_data0_c), 4565 SH_PFC_PIN_GROUP(drif1_data1_c), 4566 SH_PFC_PIN_GROUP(drif2_ctrl_a), 4567 SH_PFC_PIN_GROUP(drif2_data0_a), 4568 SH_PFC_PIN_GROUP(drif2_data1_a), 4569 SH_PFC_PIN_GROUP(drif2_ctrl_b), 4570 SH_PFC_PIN_GROUP(drif2_data0_b), 4571 SH_PFC_PIN_GROUP(drif2_data1_b), 4572 SH_PFC_PIN_GROUP(drif3_ctrl_a), 4573 SH_PFC_PIN_GROUP(drif3_data0_a), 4574 SH_PFC_PIN_GROUP(drif3_data1_a), 4575 SH_PFC_PIN_GROUP(drif3_ctrl_b), 4576 SH_PFC_PIN_GROUP(drif3_data0_b), 4577 SH_PFC_PIN_GROUP(drif3_data1_b), 4578 } 4579 #endif /* CONFIG_PINCTRL_PFC_R8A77951 */ 4580 }; 4581 4582 static const char * const audio_clk_groups[] = { 4583 "audio_clk_a_a", 4584 "audio_clk_a_b", 4585 "audio_clk_a_c", 4586 "audio_clk_b_a", 4587 "audio_clk_b_b", 4588 "audio_clk_c_a", 4589 "audio_clk_c_b", 4590 "audio_clkout_a", 4591 "audio_clkout_b", 4592 "audio_clkout_c", 4593 "audio_clkout_d", 4594 "audio_clkout1_a", 4595 "audio_clkout1_b", 4596 "audio_clkout2_a", 4597 "audio_clkout2_b", 4598 "audio_clkout3_a", 4599 "audio_clkout3_b", 4600 }; 4601 4602 static const char * const avb_groups[] = { 4603 "avb_link", 4604 "avb_magic", 4605 "avb_phy_int", 4606 "avb_mdc", /* Deprecated, please use "avb_mdio" instead */ 4607 "avb_mdio", 4608 "avb_mii", 4609 "avb_avtp_pps", 4610 "avb_avtp_match_a", 4611 "avb_avtp_capture_a", 4612 "avb_avtp_match_b", 4613 "avb_avtp_capture_b", 4614 }; 4615 4616 static const char * const can0_groups[] = { 4617 "can0_data_a", 4618 "can0_data_b", 4619 }; 4620 4621 static const char * const can1_groups[] = { 4622 "can1_data", 4623 }; 4624 4625 static const char * const can_clk_groups[] = { 4626 "can_clk", 4627 }; 4628 4629 static const char * const canfd0_groups[] = { 4630 "canfd0_data_a", 4631 "canfd0_data_b", 4632 }; 4633 4634 static const char * const canfd1_groups[] = { 4635 "canfd1_data", 4636 }; 4637 4638 #ifdef CONFIG_PINCTRL_PFC_R8A77951 4639 static const char * const drif0_groups[] = { 4640 "drif0_ctrl_a", 4641 "drif0_data0_a", 4642 "drif0_data1_a", 4643 "drif0_ctrl_b", 4644 "drif0_data0_b", 4645 "drif0_data1_b", 4646 "drif0_ctrl_c", 4647 "drif0_data0_c", 4648 "drif0_data1_c", 4649 }; 4650 4651 static const char * const drif1_groups[] = { 4652 "drif1_ctrl_a", 4653 "drif1_data0_a", 4654 "drif1_data1_a", 4655 "drif1_ctrl_b", 4656 "drif1_data0_b", 4657 "drif1_data1_b", 4658 "drif1_ctrl_c", 4659 "drif1_data0_c", 4660 "drif1_data1_c", 4661 }; 4662 4663 static const char * const drif2_groups[] = { 4664 "drif2_ctrl_a", 4665 "drif2_data0_a", 4666 "drif2_data1_a", 4667 "drif2_ctrl_b", 4668 "drif2_data0_b", 4669 "drif2_data1_b", 4670 }; 4671 4672 static const char * const drif3_groups[] = { 4673 "drif3_ctrl_a", 4674 "drif3_data0_a", 4675 "drif3_data1_a", 4676 "drif3_ctrl_b", 4677 "drif3_data0_b", 4678 "drif3_data1_b", 4679 }; 4680 #endif /* CONFIG_PINCTRL_PFC_R8A77951 */ 4681 4682 static const char * const du_groups[] = { 4683 "du_rgb666", 4684 "du_rgb888", 4685 "du_clk_out_0", 4686 "du_clk_out_1", 4687 "du_sync", 4688 "du_oddf", 4689 "du_cde", 4690 "du_disp", 4691 }; 4692 4693 static const char * const hscif0_groups[] = { 4694 "hscif0_data", 4695 "hscif0_clk", 4696 "hscif0_ctrl", 4697 }; 4698 4699 static const char * const hscif1_groups[] = { 4700 "hscif1_data_a", 4701 "hscif1_clk_a", 4702 "hscif1_ctrl_a", 4703 "hscif1_data_b", 4704 "hscif1_clk_b", 4705 "hscif1_ctrl_b", 4706 }; 4707 4708 static const char * const hscif2_groups[] = { 4709 "hscif2_data_a", 4710 "hscif2_clk_a", 4711 "hscif2_ctrl_a", 4712 "hscif2_data_b", 4713 "hscif2_clk_b", 4714 "hscif2_ctrl_b", 4715 "hscif2_data_c", 4716 "hscif2_clk_c", 4717 "hscif2_ctrl_c", 4718 }; 4719 4720 static const char * const hscif3_groups[] = { 4721 "hscif3_data_a", 4722 "hscif3_clk", 4723 "hscif3_ctrl", 4724 "hscif3_data_b", 4725 "hscif3_data_c", 4726 "hscif3_data_d", 4727 }; 4728 4729 static const char * const hscif4_groups[] = { 4730 "hscif4_data_a", 4731 "hscif4_clk", 4732 "hscif4_ctrl", 4733 "hscif4_data_b", 4734 }; 4735 4736 static const char * const i2c0_groups[] = { 4737 "i2c0", 4738 }; 4739 4740 static const char * const i2c1_groups[] = { 4741 "i2c1_a", 4742 "i2c1_b", 4743 }; 4744 4745 static const char * const i2c2_groups[] = { 4746 "i2c2_a", 4747 "i2c2_b", 4748 }; 4749 4750 static const char * const i2c3_groups[] = { 4751 "i2c3", 4752 }; 4753 4754 static const char * const i2c5_groups[] = { 4755 "i2c5", 4756 }; 4757 4758 static const char * const i2c6_groups[] = { 4759 "i2c6_a", 4760 "i2c6_b", 4761 "i2c6_c", 4762 }; 4763 4764 static const char * const intc_ex_groups[] = { 4765 "intc_ex_irq0", 4766 "intc_ex_irq1", 4767 "intc_ex_irq2", 4768 "intc_ex_irq3", 4769 "intc_ex_irq4", 4770 "intc_ex_irq5", 4771 }; 4772 4773 static const char * const msiof0_groups[] = { 4774 "msiof0_clk", 4775 "msiof0_sync", 4776 "msiof0_ss1", 4777 "msiof0_ss2", 4778 "msiof0_txd", 4779 "msiof0_rxd", 4780 }; 4781 4782 static const char * const msiof1_groups[] = { 4783 "msiof1_clk_a", 4784 "msiof1_sync_a", 4785 "msiof1_ss1_a", 4786 "msiof1_ss2_a", 4787 "msiof1_txd_a", 4788 "msiof1_rxd_a", 4789 "msiof1_clk_b", 4790 "msiof1_sync_b", 4791 "msiof1_ss1_b", 4792 "msiof1_ss2_b", 4793 "msiof1_txd_b", 4794 "msiof1_rxd_b", 4795 "msiof1_clk_c", 4796 "msiof1_sync_c", 4797 "msiof1_ss1_c", 4798 "msiof1_ss2_c", 4799 "msiof1_txd_c", 4800 "msiof1_rxd_c", 4801 "msiof1_clk_d", 4802 "msiof1_sync_d", 4803 "msiof1_ss1_d", 4804 "msiof1_ss2_d", 4805 "msiof1_txd_d", 4806 "msiof1_rxd_d", 4807 "msiof1_clk_e", 4808 "msiof1_sync_e", 4809 "msiof1_ss1_e", 4810 "msiof1_ss2_e", 4811 "msiof1_txd_e", 4812 "msiof1_rxd_e", 4813 "msiof1_clk_f", 4814 "msiof1_sync_f", 4815 "msiof1_ss1_f", 4816 "msiof1_ss2_f", 4817 "msiof1_txd_f", 4818 "msiof1_rxd_f", 4819 "msiof1_clk_g", 4820 "msiof1_sync_g", 4821 "msiof1_ss1_g", 4822 "msiof1_ss2_g", 4823 "msiof1_txd_g", 4824 "msiof1_rxd_g", 4825 }; 4826 4827 static const char * const msiof2_groups[] = { 4828 "msiof2_clk_a", 4829 "msiof2_sync_a", 4830 "msiof2_ss1_a", 4831 "msiof2_ss2_a", 4832 "msiof2_txd_a", 4833 "msiof2_rxd_a", 4834 "msiof2_clk_b", 4835 "msiof2_sync_b", 4836 "msiof2_ss1_b", 4837 "msiof2_ss2_b", 4838 "msiof2_txd_b", 4839 "msiof2_rxd_b", 4840 "msiof2_clk_c", 4841 "msiof2_sync_c", 4842 "msiof2_ss1_c", 4843 "msiof2_ss2_c", 4844 "msiof2_txd_c", 4845 "msiof2_rxd_c", 4846 "msiof2_clk_d", 4847 "msiof2_sync_d", 4848 "msiof2_ss1_d", 4849 "msiof2_ss2_d", 4850 "msiof2_txd_d", 4851 "msiof2_rxd_d", 4852 }; 4853 4854 static const char * const msiof3_groups[] = { 4855 "msiof3_clk_a", 4856 "msiof3_sync_a", 4857 "msiof3_ss1_a", 4858 "msiof3_ss2_a", 4859 "msiof3_txd_a", 4860 "msiof3_rxd_a", 4861 "msiof3_clk_b", 4862 "msiof3_sync_b", 4863 "msiof3_ss1_b", 4864 "msiof3_ss2_b", 4865 "msiof3_txd_b", 4866 "msiof3_rxd_b", 4867 "msiof3_clk_c", 4868 "msiof3_sync_c", 4869 "msiof3_txd_c", 4870 "msiof3_rxd_c", 4871 "msiof3_clk_d", 4872 "msiof3_sync_d", 4873 "msiof3_ss1_d", 4874 "msiof3_txd_d", 4875 "msiof3_rxd_d", 4876 "msiof3_clk_e", 4877 "msiof3_sync_e", 4878 "msiof3_ss1_e", 4879 "msiof3_ss2_e", 4880 "msiof3_txd_e", 4881 "msiof3_rxd_e", 4882 }; 4883 4884 static const char * const pwm0_groups[] = { 4885 "pwm0", 4886 }; 4887 4888 static const char * const pwm1_groups[] = { 4889 "pwm1_a", 4890 "pwm1_b", 4891 }; 4892 4893 static const char * const pwm2_groups[] = { 4894 "pwm2_a", 4895 "pwm2_b", 4896 }; 4897 4898 static const char * const pwm3_groups[] = { 4899 "pwm3_a", 4900 "pwm3_b", 4901 }; 4902 4903 static const char * const pwm4_groups[] = { 4904 "pwm4_a", 4905 "pwm4_b", 4906 }; 4907 4908 static const char * const pwm5_groups[] = { 4909 "pwm5_a", 4910 "pwm5_b", 4911 }; 4912 4913 static const char * const pwm6_groups[] = { 4914 "pwm6_a", 4915 "pwm6_b", 4916 }; 4917 4918 static const char * const qspi0_groups[] = { 4919 "qspi0_ctrl", 4920 "qspi0_data2", 4921 "qspi0_data4", 4922 }; 4923 4924 static const char * const qspi1_groups[] = { 4925 "qspi1_ctrl", 4926 "qspi1_data2", 4927 "qspi1_data4", 4928 }; 4929 4930 static const char * const sata0_groups[] = { 4931 "sata0_devslp_a", 4932 "sata0_devslp_b", 4933 }; 4934 4935 static const char * const scif0_groups[] = { 4936 "scif0_data", 4937 "scif0_clk", 4938 "scif0_ctrl", 4939 }; 4940 4941 static const char * const scif1_groups[] = { 4942 "scif1_data_a", 4943 "scif1_clk", 4944 "scif1_ctrl", 4945 "scif1_data_b", 4946 }; 4947 4948 static const char * const scif2_groups[] = { 4949 "scif2_data_a", 4950 "scif2_clk", 4951 "scif2_data_b", 4952 }; 4953 4954 static const char * const scif3_groups[] = { 4955 "scif3_data_a", 4956 "scif3_clk", 4957 "scif3_ctrl", 4958 "scif3_data_b", 4959 }; 4960 4961 static const char * const scif4_groups[] = { 4962 "scif4_data_a", 4963 "scif4_clk_a", 4964 "scif4_ctrl_a", 4965 "scif4_data_b", 4966 "scif4_clk_b", 4967 "scif4_ctrl_b", 4968 "scif4_data_c", 4969 "scif4_clk_c", 4970 "scif4_ctrl_c", 4971 }; 4972 4973 static const char * const scif5_groups[] = { 4974 "scif5_data_a", 4975 "scif5_clk_a", 4976 "scif5_data_b", 4977 "scif5_clk_b", 4978 }; 4979 4980 static const char * const scif_clk_groups[] = { 4981 "scif_clk_a", 4982 "scif_clk_b", 4983 }; 4984 4985 static const char * const sdhi0_groups[] = { 4986 "sdhi0_data1", 4987 "sdhi0_data4", 4988 "sdhi0_ctrl", 4989 "sdhi0_cd", 4990 "sdhi0_wp", 4991 }; 4992 4993 static const char * const sdhi1_groups[] = { 4994 "sdhi1_data1", 4995 "sdhi1_data4", 4996 "sdhi1_ctrl", 4997 "sdhi1_cd", 4998 "sdhi1_wp", 4999 }; 5000 5001 static const char * const sdhi2_groups[] = { 5002 "sdhi2_data1", 5003 "sdhi2_data4", 5004 "sdhi2_data8", 5005 "sdhi2_ctrl", 5006 "sdhi2_cd_a", 5007 "sdhi2_wp_a", 5008 "sdhi2_cd_b", 5009 "sdhi2_wp_b", 5010 "sdhi2_ds", 5011 }; 5012 5013 static const char * const sdhi3_groups[] = { 5014 "sdhi3_data1", 5015 "sdhi3_data4", 5016 "sdhi3_data8", 5017 "sdhi3_ctrl", 5018 "sdhi3_cd", 5019 "sdhi3_wp", 5020 "sdhi3_ds", 5021 }; 5022 5023 static const char * const ssi_groups[] = { 5024 "ssi0_data", 5025 "ssi01239_ctrl", 5026 "ssi1_data_a", 5027 "ssi1_data_b", 5028 "ssi1_ctrl_a", 5029 "ssi1_ctrl_b", 5030 "ssi2_data_a", 5031 "ssi2_data_b", 5032 "ssi2_ctrl_a", 5033 "ssi2_ctrl_b", 5034 "ssi3_data", 5035 "ssi349_ctrl", 5036 "ssi4_data", 5037 "ssi4_ctrl", 5038 "ssi5_data", 5039 "ssi5_ctrl", 5040 "ssi6_data", 5041 "ssi6_ctrl", 5042 "ssi7_data", 5043 "ssi78_ctrl", 5044 "ssi8_data", 5045 "ssi9_data_a", 5046 "ssi9_data_b", 5047 "ssi9_ctrl_a", 5048 "ssi9_ctrl_b", 5049 }; 5050 5051 static const char * const tmu_groups[] = { 5052 "tmu_tclk1_a", 5053 "tmu_tclk1_b", 5054 "tmu_tclk2_a", 5055 "tmu_tclk2_b", 5056 }; 5057 5058 static const char * const tpu_groups[] = { 5059 "tpu_to0", 5060 "tpu_to1", 5061 "tpu_to2", 5062 "tpu_to3", 5063 }; 5064 5065 static const char * const usb0_groups[] = { 5066 "usb0", 5067 }; 5068 5069 static const char * const usb1_groups[] = { 5070 "usb1", 5071 }; 5072 5073 static const char * const usb2_groups[] = { 5074 "usb2", 5075 }; 5076 5077 static const char * const usb2_ch3_groups[] = { 5078 "usb2_ch3", 5079 }; 5080 5081 static const char * const usb30_groups[] = { 5082 "usb30", 5083 }; 5084 5085 static const char * const vin4_groups[] = { 5086 "vin4_data8_a", 5087 "vin4_data10_a", 5088 "vin4_data12_a", 5089 "vin4_data16_a", 5090 "vin4_data18_a", 5091 "vin4_data20_a", 5092 "vin4_data24_a", 5093 "vin4_data8_b", 5094 "vin4_data10_b", 5095 "vin4_data12_b", 5096 "vin4_data16_b", 5097 "vin4_data18_b", 5098 "vin4_data20_b", 5099 "vin4_data24_b", 5100 "vin4_sync", 5101 "vin4_field", 5102 "vin4_clkenb", 5103 "vin4_clk", 5104 }; 5105 5106 static const char * const vin5_groups[] = { 5107 "vin5_data8", 5108 "vin5_data10", 5109 "vin5_data12", 5110 "vin5_data16", 5111 "vin5_sync", 5112 "vin5_field", 5113 "vin5_clkenb", 5114 "vin5_clk", 5115 }; 5116 5117 static const struct { 5118 struct sh_pfc_function common[55]; 5119 #ifdef CONFIG_PINCTRL_PFC_R8A77951 5120 struct sh_pfc_function automotive[4]; 5121 #endif 5122 } pinmux_functions = { 5123 .common = { 5124 SH_PFC_FUNCTION(audio_clk), 5125 SH_PFC_FUNCTION(avb), 5126 SH_PFC_FUNCTION(can0), 5127 SH_PFC_FUNCTION(can1), 5128 SH_PFC_FUNCTION(can_clk), 5129 SH_PFC_FUNCTION(canfd0), 5130 SH_PFC_FUNCTION(canfd1), 5131 SH_PFC_FUNCTION(du), 5132 SH_PFC_FUNCTION(hscif0), 5133 SH_PFC_FUNCTION(hscif1), 5134 SH_PFC_FUNCTION(hscif2), 5135 SH_PFC_FUNCTION(hscif3), 5136 SH_PFC_FUNCTION(hscif4), 5137 SH_PFC_FUNCTION(i2c0), 5138 SH_PFC_FUNCTION(i2c1), 5139 SH_PFC_FUNCTION(i2c2), 5140 SH_PFC_FUNCTION(i2c3), 5141 SH_PFC_FUNCTION(i2c5), 5142 SH_PFC_FUNCTION(i2c6), 5143 SH_PFC_FUNCTION(intc_ex), 5144 SH_PFC_FUNCTION(msiof0), 5145 SH_PFC_FUNCTION(msiof1), 5146 SH_PFC_FUNCTION(msiof2), 5147 SH_PFC_FUNCTION(msiof3), 5148 SH_PFC_FUNCTION(pwm0), 5149 SH_PFC_FUNCTION(pwm1), 5150 SH_PFC_FUNCTION(pwm2), 5151 SH_PFC_FUNCTION(pwm3), 5152 SH_PFC_FUNCTION(pwm4), 5153 SH_PFC_FUNCTION(pwm5), 5154 SH_PFC_FUNCTION(pwm6), 5155 SH_PFC_FUNCTION(qspi0), 5156 SH_PFC_FUNCTION(qspi1), 5157 SH_PFC_FUNCTION(sata0), 5158 SH_PFC_FUNCTION(scif0), 5159 SH_PFC_FUNCTION(scif1), 5160 SH_PFC_FUNCTION(scif2), 5161 SH_PFC_FUNCTION(scif3), 5162 SH_PFC_FUNCTION(scif4), 5163 SH_PFC_FUNCTION(scif5), 5164 SH_PFC_FUNCTION(scif_clk), 5165 SH_PFC_FUNCTION(sdhi0), 5166 SH_PFC_FUNCTION(sdhi1), 5167 SH_PFC_FUNCTION(sdhi2), 5168 SH_PFC_FUNCTION(sdhi3), 5169 SH_PFC_FUNCTION(ssi), 5170 SH_PFC_FUNCTION(tmu), 5171 SH_PFC_FUNCTION(tpu), 5172 SH_PFC_FUNCTION(usb0), 5173 SH_PFC_FUNCTION(usb1), 5174 SH_PFC_FUNCTION(usb2), 5175 SH_PFC_FUNCTION(usb2_ch3), 5176 SH_PFC_FUNCTION(usb30), 5177 SH_PFC_FUNCTION(vin4), 5178 SH_PFC_FUNCTION(vin5), 5179 }, 5180 #ifdef CONFIG_PINCTRL_PFC_R8A77951 5181 .automotive = { 5182 SH_PFC_FUNCTION(drif0), 5183 SH_PFC_FUNCTION(drif1), 5184 SH_PFC_FUNCTION(drif2), 5185 SH_PFC_FUNCTION(drif3), 5186 } 5187 #endif /* CONFIG_PINCTRL_PFC_R8A77951 */ 5188 }; 5189 5190 static const struct pinmux_cfg_reg pinmux_config_regs[] = { 5191 #define F_(x, y) FN_##y 5192 #define FM(x) FN_##x 5193 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP( 5194 0, 0, 5195 0, 0, 5196 0, 0, 5197 0, 0, 5198 0, 0, 5199 0, 0, 5200 0, 0, 5201 0, 0, 5202 0, 0, 5203 0, 0, 5204 0, 0, 5205 0, 0, 5206 0, 0, 5207 0, 0, 5208 0, 0, 5209 0, 0, 5210 GP_0_15_FN, GPSR0_15, 5211 GP_0_14_FN, GPSR0_14, 5212 GP_0_13_FN, GPSR0_13, 5213 GP_0_12_FN, GPSR0_12, 5214 GP_0_11_FN, GPSR0_11, 5215 GP_0_10_FN, GPSR0_10, 5216 GP_0_9_FN, GPSR0_9, 5217 GP_0_8_FN, GPSR0_8, 5218 GP_0_7_FN, GPSR0_7, 5219 GP_0_6_FN, GPSR0_6, 5220 GP_0_5_FN, GPSR0_5, 5221 GP_0_4_FN, GPSR0_4, 5222 GP_0_3_FN, GPSR0_3, 5223 GP_0_2_FN, GPSR0_2, 5224 GP_0_1_FN, GPSR0_1, 5225 GP_0_0_FN, GPSR0_0, )) 5226 }, 5227 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP( 5228 0, 0, 5229 0, 0, 5230 0, 0, 5231 GP_1_28_FN, GPSR1_28, 5232 GP_1_27_FN, GPSR1_27, 5233 GP_1_26_FN, GPSR1_26, 5234 GP_1_25_FN, GPSR1_25, 5235 GP_1_24_FN, GPSR1_24, 5236 GP_1_23_FN, GPSR1_23, 5237 GP_1_22_FN, GPSR1_22, 5238 GP_1_21_FN, GPSR1_21, 5239 GP_1_20_FN, GPSR1_20, 5240 GP_1_19_FN, GPSR1_19, 5241 GP_1_18_FN, GPSR1_18, 5242 GP_1_17_FN, GPSR1_17, 5243 GP_1_16_FN, GPSR1_16, 5244 GP_1_15_FN, GPSR1_15, 5245 GP_1_14_FN, GPSR1_14, 5246 GP_1_13_FN, GPSR1_13, 5247 GP_1_12_FN, GPSR1_12, 5248 GP_1_11_FN, GPSR1_11, 5249 GP_1_10_FN, GPSR1_10, 5250 GP_1_9_FN, GPSR1_9, 5251 GP_1_8_FN, GPSR1_8, 5252 GP_1_7_FN, GPSR1_7, 5253 GP_1_6_FN, GPSR1_6, 5254 GP_1_5_FN, GPSR1_5, 5255 GP_1_4_FN, GPSR1_4, 5256 GP_1_3_FN, GPSR1_3, 5257 GP_1_2_FN, GPSR1_2, 5258 GP_1_1_FN, GPSR1_1, 5259 GP_1_0_FN, GPSR1_0, )) 5260 }, 5261 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP( 5262 0, 0, 5263 0, 0, 5264 0, 0, 5265 0, 0, 5266 0, 0, 5267 0, 0, 5268 0, 0, 5269 0, 0, 5270 0, 0, 5271 0, 0, 5272 0, 0, 5273 0, 0, 5274 0, 0, 5275 0, 0, 5276 0, 0, 5277 0, 0, 5278 0, 0, 5279 GP_2_14_FN, GPSR2_14, 5280 GP_2_13_FN, GPSR2_13, 5281 GP_2_12_FN, GPSR2_12, 5282 GP_2_11_FN, GPSR2_11, 5283 GP_2_10_FN, GPSR2_10, 5284 GP_2_9_FN, GPSR2_9, 5285 GP_2_8_FN, GPSR2_8, 5286 GP_2_7_FN, GPSR2_7, 5287 GP_2_6_FN, GPSR2_6, 5288 GP_2_5_FN, GPSR2_5, 5289 GP_2_4_FN, GPSR2_4, 5290 GP_2_3_FN, GPSR2_3, 5291 GP_2_2_FN, GPSR2_2, 5292 GP_2_1_FN, GPSR2_1, 5293 GP_2_0_FN, GPSR2_0, )) 5294 }, 5295 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP( 5296 0, 0, 5297 0, 0, 5298 0, 0, 5299 0, 0, 5300 0, 0, 5301 0, 0, 5302 0, 0, 5303 0, 0, 5304 0, 0, 5305 0, 0, 5306 0, 0, 5307 0, 0, 5308 0, 0, 5309 0, 0, 5310 0, 0, 5311 0, 0, 5312 GP_3_15_FN, GPSR3_15, 5313 GP_3_14_FN, GPSR3_14, 5314 GP_3_13_FN, GPSR3_13, 5315 GP_3_12_FN, GPSR3_12, 5316 GP_3_11_FN, GPSR3_11, 5317 GP_3_10_FN, GPSR3_10, 5318 GP_3_9_FN, GPSR3_9, 5319 GP_3_8_FN, GPSR3_8, 5320 GP_3_7_FN, GPSR3_7, 5321 GP_3_6_FN, GPSR3_6, 5322 GP_3_5_FN, GPSR3_5, 5323 GP_3_4_FN, GPSR3_4, 5324 GP_3_3_FN, GPSR3_3, 5325 GP_3_2_FN, GPSR3_2, 5326 GP_3_1_FN, GPSR3_1, 5327 GP_3_0_FN, GPSR3_0, )) 5328 }, 5329 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP( 5330 0, 0, 5331 0, 0, 5332 0, 0, 5333 0, 0, 5334 0, 0, 5335 0, 0, 5336 0, 0, 5337 0, 0, 5338 0, 0, 5339 0, 0, 5340 0, 0, 5341 0, 0, 5342 0, 0, 5343 0, 0, 5344 GP_4_17_FN, GPSR4_17, 5345 GP_4_16_FN, GPSR4_16, 5346 GP_4_15_FN, GPSR4_15, 5347 GP_4_14_FN, GPSR4_14, 5348 GP_4_13_FN, GPSR4_13, 5349 GP_4_12_FN, GPSR4_12, 5350 GP_4_11_FN, GPSR4_11, 5351 GP_4_10_FN, GPSR4_10, 5352 GP_4_9_FN, GPSR4_9, 5353 GP_4_8_FN, GPSR4_8, 5354 GP_4_7_FN, GPSR4_7, 5355 GP_4_6_FN, GPSR4_6, 5356 GP_4_5_FN, GPSR4_5, 5357 GP_4_4_FN, GPSR4_4, 5358 GP_4_3_FN, GPSR4_3, 5359 GP_4_2_FN, GPSR4_2, 5360 GP_4_1_FN, GPSR4_1, 5361 GP_4_0_FN, GPSR4_0, )) 5362 }, 5363 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP( 5364 0, 0, 5365 0, 0, 5366 0, 0, 5367 0, 0, 5368 0, 0, 5369 0, 0, 5370 GP_5_25_FN, GPSR5_25, 5371 GP_5_24_FN, GPSR5_24, 5372 GP_5_23_FN, GPSR5_23, 5373 GP_5_22_FN, GPSR5_22, 5374 GP_5_21_FN, GPSR5_21, 5375 GP_5_20_FN, GPSR5_20, 5376 GP_5_19_FN, GPSR5_19, 5377 GP_5_18_FN, GPSR5_18, 5378 GP_5_17_FN, GPSR5_17, 5379 GP_5_16_FN, GPSR5_16, 5380 GP_5_15_FN, GPSR5_15, 5381 GP_5_14_FN, GPSR5_14, 5382 GP_5_13_FN, GPSR5_13, 5383 GP_5_12_FN, GPSR5_12, 5384 GP_5_11_FN, GPSR5_11, 5385 GP_5_10_FN, GPSR5_10, 5386 GP_5_9_FN, GPSR5_9, 5387 GP_5_8_FN, GPSR5_8, 5388 GP_5_7_FN, GPSR5_7, 5389 GP_5_6_FN, GPSR5_6, 5390 GP_5_5_FN, GPSR5_5, 5391 GP_5_4_FN, GPSR5_4, 5392 GP_5_3_FN, GPSR5_3, 5393 GP_5_2_FN, GPSR5_2, 5394 GP_5_1_FN, GPSR5_1, 5395 GP_5_0_FN, GPSR5_0, )) 5396 }, 5397 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP( 5398 GP_6_31_FN, GPSR6_31, 5399 GP_6_30_FN, GPSR6_30, 5400 GP_6_29_FN, GPSR6_29, 5401 GP_6_28_FN, GPSR6_28, 5402 GP_6_27_FN, GPSR6_27, 5403 GP_6_26_FN, GPSR6_26, 5404 GP_6_25_FN, GPSR6_25, 5405 GP_6_24_FN, GPSR6_24, 5406 GP_6_23_FN, GPSR6_23, 5407 GP_6_22_FN, GPSR6_22, 5408 GP_6_21_FN, GPSR6_21, 5409 GP_6_20_FN, GPSR6_20, 5410 GP_6_19_FN, GPSR6_19, 5411 GP_6_18_FN, GPSR6_18, 5412 GP_6_17_FN, GPSR6_17, 5413 GP_6_16_FN, GPSR6_16, 5414 GP_6_15_FN, GPSR6_15, 5415 GP_6_14_FN, GPSR6_14, 5416 GP_6_13_FN, GPSR6_13, 5417 GP_6_12_FN, GPSR6_12, 5418 GP_6_11_FN, GPSR6_11, 5419 GP_6_10_FN, GPSR6_10, 5420 GP_6_9_FN, GPSR6_9, 5421 GP_6_8_FN, GPSR6_8, 5422 GP_6_7_FN, GPSR6_7, 5423 GP_6_6_FN, GPSR6_6, 5424 GP_6_5_FN, GPSR6_5, 5425 GP_6_4_FN, GPSR6_4, 5426 GP_6_3_FN, GPSR6_3, 5427 GP_6_2_FN, GPSR6_2, 5428 GP_6_1_FN, GPSR6_1, 5429 GP_6_0_FN, GPSR6_0, )) 5430 }, 5431 { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1, GROUP( 5432 0, 0, 5433 0, 0, 5434 0, 0, 5435 0, 0, 5436 0, 0, 5437 0, 0, 5438 0, 0, 5439 0, 0, 5440 0, 0, 5441 0, 0, 5442 0, 0, 5443 0, 0, 5444 0, 0, 5445 0, 0, 5446 0, 0, 5447 0, 0, 5448 0, 0, 5449 0, 0, 5450 0, 0, 5451 0, 0, 5452 0, 0, 5453 0, 0, 5454 0, 0, 5455 0, 0, 5456 0, 0, 5457 0, 0, 5458 0, 0, 5459 0, 0, 5460 GP_7_3_FN, GPSR7_3, 5461 GP_7_2_FN, GPSR7_2, 5462 GP_7_1_FN, GPSR7_1, 5463 GP_7_0_FN, GPSR7_0, )) 5464 }, 5465 #undef F_ 5466 #undef FM 5467 5468 #define F_(x, y) x, 5469 #define FM(x) FN_##x, 5470 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP( 5471 IP0_31_28 5472 IP0_27_24 5473 IP0_23_20 5474 IP0_19_16 5475 IP0_15_12 5476 IP0_11_8 5477 IP0_7_4 5478 IP0_3_0 )) 5479 }, 5480 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP( 5481 IP1_31_28 5482 IP1_27_24 5483 IP1_23_20 5484 IP1_19_16 5485 IP1_15_12 5486 IP1_11_8 5487 IP1_7_4 5488 IP1_3_0 )) 5489 }, 5490 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP( 5491 IP2_31_28 5492 IP2_27_24 5493 IP2_23_20 5494 IP2_19_16 5495 IP2_15_12 5496 IP2_11_8 5497 IP2_7_4 5498 IP2_3_0 )) 5499 }, 5500 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP( 5501 IP3_31_28 5502 IP3_27_24 5503 IP3_23_20 5504 IP3_19_16 5505 IP3_15_12 5506 IP3_11_8 5507 IP3_7_4 5508 IP3_3_0 )) 5509 }, 5510 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP( 5511 IP4_31_28 5512 IP4_27_24 5513 IP4_23_20 5514 IP4_19_16 5515 IP4_15_12 5516 IP4_11_8 5517 IP4_7_4 5518 IP4_3_0 )) 5519 }, 5520 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP( 5521 IP5_31_28 5522 IP5_27_24 5523 IP5_23_20 5524 IP5_19_16 5525 IP5_15_12 5526 IP5_11_8 5527 IP5_7_4 5528 IP5_3_0 )) 5529 }, 5530 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP( 5531 IP6_31_28 5532 IP6_27_24 5533 IP6_23_20 5534 IP6_19_16 5535 IP6_15_12 5536 IP6_11_8 5537 IP6_7_4 5538 IP6_3_0 )) 5539 }, 5540 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP( 5541 IP7_31_28 5542 IP7_27_24 5543 IP7_23_20 5544 IP7_19_16 5545 /* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5546 IP7_11_8 5547 IP7_7_4 5548 IP7_3_0 )) 5549 }, 5550 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP( 5551 IP8_31_28 5552 IP8_27_24 5553 IP8_23_20 5554 IP8_19_16 5555 IP8_15_12 5556 IP8_11_8 5557 IP8_7_4 5558 IP8_3_0 )) 5559 }, 5560 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP( 5561 IP9_31_28 5562 IP9_27_24 5563 IP9_23_20 5564 IP9_19_16 5565 IP9_15_12 5566 IP9_11_8 5567 IP9_7_4 5568 IP9_3_0 )) 5569 }, 5570 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP( 5571 IP10_31_28 5572 IP10_27_24 5573 IP10_23_20 5574 IP10_19_16 5575 IP10_15_12 5576 IP10_11_8 5577 IP10_7_4 5578 IP10_3_0 )) 5579 }, 5580 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP( 5581 IP11_31_28 5582 IP11_27_24 5583 IP11_23_20 5584 IP11_19_16 5585 IP11_15_12 5586 IP11_11_8 5587 IP11_7_4 5588 IP11_3_0 )) 5589 }, 5590 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP( 5591 IP12_31_28 5592 IP12_27_24 5593 IP12_23_20 5594 IP12_19_16 5595 IP12_15_12 5596 IP12_11_8 5597 IP12_7_4 5598 IP12_3_0 )) 5599 }, 5600 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP( 5601 IP13_31_28 5602 IP13_27_24 5603 IP13_23_20 5604 IP13_19_16 5605 IP13_15_12 5606 IP13_11_8 5607 IP13_7_4 5608 IP13_3_0 )) 5609 }, 5610 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP( 5611 IP14_31_28 5612 IP14_27_24 5613 IP14_23_20 5614 IP14_19_16 5615 IP14_15_12 5616 IP14_11_8 5617 IP14_7_4 5618 IP14_3_0 )) 5619 }, 5620 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP( 5621 IP15_31_28 5622 IP15_27_24 5623 IP15_23_20 5624 IP15_19_16 5625 IP15_15_12 5626 IP15_11_8 5627 IP15_7_4 5628 IP15_3_0 )) 5629 }, 5630 { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4, GROUP( 5631 IP16_31_28 5632 IP16_27_24 5633 IP16_23_20 5634 IP16_19_16 5635 IP16_15_12 5636 IP16_11_8 5637 IP16_7_4 5638 IP16_3_0 )) 5639 }, 5640 { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4, GROUP( 5641 IP17_31_28 5642 IP17_27_24 5643 IP17_23_20 5644 IP17_19_16 5645 IP17_15_12 5646 IP17_11_8 5647 IP17_7_4 5648 IP17_3_0 )) 5649 }, 5650 { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4, GROUP( 5651 /* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5652 /* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5653 /* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5654 /* IP18_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5655 /* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5656 /* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5657 IP18_7_4 5658 IP18_3_0 )) 5659 }, 5660 #undef F_ 5661 #undef FM 5662 5663 #define F_(x, y) x, 5664 #define FM(x) FN_##x, 5665 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32, 5666 GROUP(3, 2, 3, 1, 1, 1, 1, 1, 2, 1, 1, 2, 5667 1, 1, 1, 2, 2, 1, 2, 3), 5668 GROUP( 5669 MOD_SEL0_31_30_29 5670 MOD_SEL0_28_27 5671 MOD_SEL0_26_25_24 5672 MOD_SEL0_23 5673 MOD_SEL0_22 5674 MOD_SEL0_21 5675 MOD_SEL0_20 5676 MOD_SEL0_19 5677 MOD_SEL0_18_17 5678 MOD_SEL0_16 5679 0, 0, /* RESERVED 15 */ 5680 MOD_SEL0_14_13 5681 MOD_SEL0_12 5682 MOD_SEL0_11 5683 MOD_SEL0_10 5684 MOD_SEL0_9_8 5685 MOD_SEL0_7_6 5686 MOD_SEL0_5 5687 MOD_SEL0_4_3 5688 /* RESERVED 2, 1, 0 */ 5689 0, 0, 0, 0, 0, 0, 0, 0 )) 5690 }, 5691 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32, 5692 GROUP(2, 3, 1, 2, 3, 1, 1, 2, 1, 2, 1, 1, 5693 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1), 5694 GROUP( 5695 MOD_SEL1_31_30 5696 MOD_SEL1_29_28_27 5697 MOD_SEL1_26 5698 MOD_SEL1_25_24 5699 MOD_SEL1_23_22_21 5700 MOD_SEL1_20 5701 MOD_SEL1_19 5702 MOD_SEL1_18_17 5703 MOD_SEL1_16 5704 MOD_SEL1_15_14 5705 MOD_SEL1_13 5706 MOD_SEL1_12 5707 MOD_SEL1_11 5708 MOD_SEL1_10 5709 MOD_SEL1_9 5710 0, 0, 0, 0, /* RESERVED 8, 7 */ 5711 MOD_SEL1_6 5712 MOD_SEL1_5 5713 MOD_SEL1_4 5714 MOD_SEL1_3 5715 MOD_SEL1_2 5716 MOD_SEL1_1 5717 MOD_SEL1_0 )) 5718 }, 5719 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32, 5720 GROUP(1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, 5721 1, 4, 4, 4, 3, 1), 5722 GROUP( 5723 MOD_SEL2_31 5724 MOD_SEL2_30 5725 MOD_SEL2_29 5726 MOD_SEL2_28_27 5727 MOD_SEL2_26 5728 MOD_SEL2_25_24_23 5729 /* RESERVED 22 */ 5730 0, 0, 5731 MOD_SEL2_21 5732 MOD_SEL2_20 5733 MOD_SEL2_19 5734 MOD_SEL2_18 5735 MOD_SEL2_17 5736 /* RESERVED 16 */ 5737 0, 0, 5738 /* RESERVED 15, 14, 13, 12 */ 5739 0, 0, 0, 0, 0, 0, 0, 0, 5740 0, 0, 0, 0, 0, 0, 0, 0, 5741 /* RESERVED 11, 10, 9, 8 */ 5742 0, 0, 0, 0, 0, 0, 0, 0, 5743 0, 0, 0, 0, 0, 0, 0, 0, 5744 /* RESERVED 7, 6, 5, 4 */ 5745 0, 0, 0, 0, 0, 0, 0, 0, 5746 0, 0, 0, 0, 0, 0, 0, 0, 5747 /* RESERVED 3, 2, 1 */ 5748 0, 0, 0, 0, 0, 0, 0, 0, 5749 MOD_SEL2_0 )) 5750 }, 5751 { }, 5752 }; 5753 5754 static const struct pinmux_drive_reg pinmux_drive_regs[] = { 5755 { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) { 5756 { PIN_QSPI0_SPCLK, 28, 2 }, /* QSPI0_SPCLK */ 5757 { PIN_QSPI0_MOSI_IO0, 24, 2 }, /* QSPI0_MOSI_IO0 */ 5758 { PIN_QSPI0_MISO_IO1, 20, 2 }, /* QSPI0_MISO_IO1 */ 5759 { PIN_QSPI0_IO2, 16, 2 }, /* QSPI0_IO2 */ 5760 { PIN_QSPI0_IO3, 12, 2 }, /* QSPI0_IO3 */ 5761 { PIN_QSPI0_SSL, 8, 2 }, /* QSPI0_SSL */ 5762 { PIN_QSPI1_SPCLK, 4, 2 }, /* QSPI1_SPCLK */ 5763 { PIN_QSPI1_MOSI_IO0, 0, 2 }, /* QSPI1_MOSI_IO0 */ 5764 } }, 5765 { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) { 5766 { PIN_QSPI1_MISO_IO1, 28, 2 }, /* QSPI1_MISO_IO1 */ 5767 { PIN_QSPI1_IO2, 24, 2 }, /* QSPI1_IO2 */ 5768 { PIN_QSPI1_IO3, 20, 2 }, /* QSPI1_IO3 */ 5769 { PIN_QSPI1_SSL, 16, 2 }, /* QSPI1_SSL */ 5770 { PIN_RPC_INT_N, 12, 2 }, /* RPC_INT# */ 5771 { PIN_RPC_WP_N, 8, 2 }, /* RPC_WP# */ 5772 { PIN_RPC_RESET_N, 4, 2 }, /* RPC_RESET# */ 5773 { PIN_AVB_RX_CTL, 0, 3 }, /* AVB_RX_CTL */ 5774 } }, 5775 { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) { 5776 { PIN_AVB_RXC, 28, 3 }, /* AVB_RXC */ 5777 { PIN_AVB_RD0, 24, 3 }, /* AVB_RD0 */ 5778 { PIN_AVB_RD1, 20, 3 }, /* AVB_RD1 */ 5779 { PIN_AVB_RD2, 16, 3 }, /* AVB_RD2 */ 5780 { PIN_AVB_RD3, 12, 3 }, /* AVB_RD3 */ 5781 { PIN_AVB_TX_CTL, 8, 3 }, /* AVB_TX_CTL */ 5782 { PIN_AVB_TXC, 4, 3 }, /* AVB_TXC */ 5783 { PIN_AVB_TD0, 0, 3 }, /* AVB_TD0 */ 5784 } }, 5785 { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) { 5786 { PIN_AVB_TD1, 28, 3 }, /* AVB_TD1 */ 5787 { PIN_AVB_TD2, 24, 3 }, /* AVB_TD2 */ 5788 { PIN_AVB_TD3, 20, 3 }, /* AVB_TD3 */ 5789 { PIN_AVB_TXCREFCLK, 16, 3 }, /* AVB_TXCREFCLK */ 5790 { PIN_AVB_MDIO, 12, 3 }, /* AVB_MDIO */ 5791 { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */ 5792 { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */ 5793 { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */ 5794 } }, 5795 { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) { 5796 { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */ 5797 { RCAR_GP_PIN(2, 13), 24, 3 }, /* AVB_AVTP_MATCH */ 5798 { RCAR_GP_PIN(2, 14), 20, 3 }, /* AVB_AVTP_CAPTURE */ 5799 { RCAR_GP_PIN(2, 0), 16, 3 }, /* IRQ0 */ 5800 { RCAR_GP_PIN(2, 1), 12, 3 }, /* IRQ1 */ 5801 { RCAR_GP_PIN(2, 2), 8, 3 }, /* IRQ2 */ 5802 { RCAR_GP_PIN(2, 3), 4, 3 }, /* IRQ3 */ 5803 { RCAR_GP_PIN(2, 4), 0, 3 }, /* IRQ4 */ 5804 } }, 5805 { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) { 5806 { RCAR_GP_PIN(2, 5), 28, 3 }, /* IRQ5 */ 5807 { RCAR_GP_PIN(2, 6), 24, 3 }, /* PWM0 */ 5808 { RCAR_GP_PIN(2, 7), 20, 3 }, /* PWM1 */ 5809 { RCAR_GP_PIN(2, 8), 16, 3 }, /* PWM2 */ 5810 { RCAR_GP_PIN(1, 0), 12, 3 }, /* A0 */ 5811 { RCAR_GP_PIN(1, 1), 8, 3 }, /* A1 */ 5812 { RCAR_GP_PIN(1, 2), 4, 3 }, /* A2 */ 5813 { RCAR_GP_PIN(1, 3), 0, 3 }, /* A3 */ 5814 } }, 5815 { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) { 5816 { RCAR_GP_PIN(1, 4), 28, 3 }, /* A4 */ 5817 { RCAR_GP_PIN(1, 5), 24, 3 }, /* A5 */ 5818 { RCAR_GP_PIN(1, 6), 20, 3 }, /* A6 */ 5819 { RCAR_GP_PIN(1, 7), 16, 3 }, /* A7 */ 5820 { RCAR_GP_PIN(1, 8), 12, 3 }, /* A8 */ 5821 { RCAR_GP_PIN(1, 9), 8, 3 }, /* A9 */ 5822 { RCAR_GP_PIN(1, 10), 4, 3 }, /* A10 */ 5823 { RCAR_GP_PIN(1, 11), 0, 3 }, /* A11 */ 5824 } }, 5825 { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) { 5826 { RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */ 5827 { RCAR_GP_PIN(1, 13), 24, 3 }, /* A13 */ 5828 { RCAR_GP_PIN(1, 14), 20, 3 }, /* A14 */ 5829 { RCAR_GP_PIN(1, 15), 16, 3 }, /* A15 */ 5830 { RCAR_GP_PIN(1, 16), 12, 3 }, /* A16 */ 5831 { RCAR_GP_PIN(1, 17), 8, 3 }, /* A17 */ 5832 { RCAR_GP_PIN(1, 18), 4, 3 }, /* A18 */ 5833 { RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */ 5834 } }, 5835 { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) { 5836 { RCAR_GP_PIN(1, 28), 28, 3 }, /* CLKOUT */ 5837 { RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */ 5838 { RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */ 5839 { RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */ 5840 { RCAR_GP_PIN(1, 23), 12, 3 }, /* RD */ 5841 { RCAR_GP_PIN(1, 24), 8, 3 }, /* RD_WR */ 5842 { RCAR_GP_PIN(1, 25), 4, 3 }, /* WE0 */ 5843 { RCAR_GP_PIN(1, 26), 0, 3 }, /* WE1 */ 5844 } }, 5845 { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) { 5846 { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */ 5847 { PIN_PRESETOUT_N, 24, 3 }, /* PRESETOUT# */ 5848 { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */ 5849 { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */ 5850 { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */ 5851 { RCAR_GP_PIN(0, 3), 8, 3 }, /* D3 */ 5852 { RCAR_GP_PIN(0, 4), 4, 3 }, /* D4 */ 5853 { RCAR_GP_PIN(0, 5), 0, 3 }, /* D5 */ 5854 } }, 5855 { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) { 5856 { RCAR_GP_PIN(0, 6), 28, 3 }, /* D6 */ 5857 { RCAR_GP_PIN(0, 7), 24, 3 }, /* D7 */ 5858 { RCAR_GP_PIN(0, 8), 20, 3 }, /* D8 */ 5859 { RCAR_GP_PIN(0, 9), 16, 3 }, /* D9 */ 5860 { RCAR_GP_PIN(0, 10), 12, 3 }, /* D10 */ 5861 { RCAR_GP_PIN(0, 11), 8, 3 }, /* D11 */ 5862 { RCAR_GP_PIN(0, 12), 4, 3 }, /* D12 */ 5863 { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */ 5864 } }, 5865 { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) { 5866 { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */ 5867 { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */ 5868 { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */ 5869 { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */ 5870 { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */ 5871 { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */ 5872 { PIN_DU_DOTCLKIN0, 4, 2 }, /* DU_DOTCLKIN0 */ 5873 { PIN_DU_DOTCLKIN1, 0, 2 }, /* DU_DOTCLKIN1 */ 5874 } }, 5875 { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) { 5876 #ifdef CONFIG_PINCTRL_PFC_R8A77951 5877 { PIN_DU_DOTCLKIN2, 28, 2 }, /* DU_DOTCLKIN2 */ 5878 #endif 5879 { PIN_DU_DOTCLKIN3, 24, 2 }, /* DU_DOTCLKIN3 */ 5880 { PIN_FSCLKST_N, 20, 2 }, /* FSCLKST# */ 5881 { PIN_TMS, 4, 2 }, /* TMS */ 5882 } }, 5883 { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) { 5884 { PIN_TDO, 28, 2 }, /* TDO */ 5885 { PIN_ASEBRK, 24, 2 }, /* ASEBRK */ 5886 { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */ 5887 { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */ 5888 { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */ 5889 { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */ 5890 { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */ 5891 { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */ 5892 } }, 5893 { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) { 5894 { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */ 5895 { RCAR_GP_PIN(3, 7), 24, 3 }, /* SD1_CMD */ 5896 { RCAR_GP_PIN(3, 8), 20, 3 }, /* SD1_DAT0 */ 5897 { RCAR_GP_PIN(3, 9), 16, 3 }, /* SD1_DAT1 */ 5898 { RCAR_GP_PIN(3, 10), 12, 3 }, /* SD1_DAT2 */ 5899 { RCAR_GP_PIN(3, 11), 8, 3 }, /* SD1_DAT3 */ 5900 { RCAR_GP_PIN(4, 0), 4, 3 }, /* SD2_CLK */ 5901 { RCAR_GP_PIN(4, 1), 0, 3 }, /* SD2_CMD */ 5902 } }, 5903 { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) { 5904 { RCAR_GP_PIN(4, 2), 28, 3 }, /* SD2_DAT0 */ 5905 { RCAR_GP_PIN(4, 3), 24, 3 }, /* SD2_DAT1 */ 5906 { RCAR_GP_PIN(4, 4), 20, 3 }, /* SD2_DAT2 */ 5907 { RCAR_GP_PIN(4, 5), 16, 3 }, /* SD2_DAT3 */ 5908 { RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */ 5909 { RCAR_GP_PIN(4, 7), 8, 3 }, /* SD3_CLK */ 5910 { RCAR_GP_PIN(4, 8), 4, 3 }, /* SD3_CMD */ 5911 { RCAR_GP_PIN(4, 9), 0, 3 }, /* SD3_DAT0 */ 5912 } }, 5913 { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) { 5914 { RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */ 5915 { RCAR_GP_PIN(4, 11), 24, 3 }, /* SD3_DAT2 */ 5916 { RCAR_GP_PIN(4, 12), 20, 3 }, /* SD3_DAT3 */ 5917 { RCAR_GP_PIN(4, 13), 16, 3 }, /* SD3_DAT4 */ 5918 { RCAR_GP_PIN(4, 14), 12, 3 }, /* SD3_DAT5 */ 5919 { RCAR_GP_PIN(4, 15), 8, 3 }, /* SD3_DAT6 */ 5920 { RCAR_GP_PIN(4, 16), 4, 3 }, /* SD3_DAT7 */ 5921 { RCAR_GP_PIN(4, 17), 0, 3 }, /* SD3_DS */ 5922 } }, 5923 { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) { 5924 { RCAR_GP_PIN(3, 12), 28, 3 }, /* SD0_CD */ 5925 { RCAR_GP_PIN(3, 13), 24, 3 }, /* SD0_WP */ 5926 { RCAR_GP_PIN(3, 14), 20, 3 }, /* SD1_CD */ 5927 { RCAR_GP_PIN(3, 15), 16, 3 }, /* SD1_WP */ 5928 { RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */ 5929 { RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */ 5930 { RCAR_GP_PIN(5, 2), 4, 3 }, /* TX0 */ 5931 { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */ 5932 } }, 5933 { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) { 5934 { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0 */ 5935 { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */ 5936 { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */ 5937 { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */ 5938 { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1 */ 5939 { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */ 5940 { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */ 5941 { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */ 5942 } }, 5943 { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) { 5944 { RCAR_GP_PIN(5, 12), 28, 3 }, /* HSCK0 */ 5945 { RCAR_GP_PIN(5, 13), 24, 3 }, /* HRX0 */ 5946 { RCAR_GP_PIN(5, 14), 20, 3 }, /* HTX0 */ 5947 { RCAR_GP_PIN(5, 15), 16, 3 }, /* HCTS0 */ 5948 { RCAR_GP_PIN(5, 16), 12, 3 }, /* HRTS0 */ 5949 { RCAR_GP_PIN(5, 17), 8, 3 }, /* MSIOF0_SCK */ 5950 { RCAR_GP_PIN(5, 18), 4, 3 }, /* MSIOF0_SYNC */ 5951 { RCAR_GP_PIN(5, 19), 0, 3 }, /* MSIOF0_SS1 */ 5952 } }, 5953 { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) { 5954 { RCAR_GP_PIN(5, 20), 28, 3 }, /* MSIOF0_TXD */ 5955 { RCAR_GP_PIN(5, 21), 24, 3 }, /* MSIOF0_SS2 */ 5956 { RCAR_GP_PIN(5, 22), 20, 3 }, /* MSIOF0_RXD */ 5957 { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */ 5958 { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */ 5959 { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */ 5960 { PIN_MLB_REF, 4, 3 }, /* MLB_REF */ 5961 { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */ 5962 } }, 5963 { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) { 5964 { RCAR_GP_PIN(6, 1), 28, 3 }, /* SSI_WS01239 */ 5965 { RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */ 5966 { RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */ 5967 { RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */ 5968 { RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK349 */ 5969 { RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS349 */ 5970 { RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */ 5971 { RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */ 5972 } }, 5973 { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) { 5974 { RCAR_GP_PIN(6, 9), 28, 3 }, /* SSI_WS4 */ 5975 { RCAR_GP_PIN(6, 10), 24, 3 }, /* SSI_SDATA4 */ 5976 { RCAR_GP_PIN(6, 11), 20, 3 }, /* SSI_SCK5 */ 5977 { RCAR_GP_PIN(6, 12), 16, 3 }, /* SSI_WS5 */ 5978 { RCAR_GP_PIN(6, 13), 12, 3 }, /* SSI_SDATA5 */ 5979 { RCAR_GP_PIN(6, 14), 8, 3 }, /* SSI_SCK6 */ 5980 { RCAR_GP_PIN(6, 15), 4, 3 }, /* SSI_WS6 */ 5981 { RCAR_GP_PIN(6, 16), 0, 3 }, /* SSI_SDATA6 */ 5982 } }, 5983 { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) { 5984 { RCAR_GP_PIN(6, 17), 28, 3 }, /* SSI_SCK78 */ 5985 { RCAR_GP_PIN(6, 18), 24, 3 }, /* SSI_WS78 */ 5986 { RCAR_GP_PIN(6, 19), 20, 3 }, /* SSI_SDATA7 */ 5987 { RCAR_GP_PIN(6, 20), 16, 3 }, /* SSI_SDATA8 */ 5988 { RCAR_GP_PIN(6, 21), 12, 3 }, /* SSI_SDATA9 */ 5989 { RCAR_GP_PIN(6, 22), 8, 3 }, /* AUDIO_CLKA */ 5990 { RCAR_GP_PIN(6, 23), 4, 3 }, /* AUDIO_CLKB */ 5991 { RCAR_GP_PIN(6, 24), 0, 3 }, /* USB0_PWEN */ 5992 } }, 5993 { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) { 5994 { RCAR_GP_PIN(6, 25), 28, 3 }, /* USB0_OVC */ 5995 { RCAR_GP_PIN(6, 26), 24, 3 }, /* USB1_PWEN */ 5996 { RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */ 5997 { RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */ 5998 { RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */ 5999 { RCAR_GP_PIN(6, 30), 8, 3 }, /* GP6_30/USB2_CH3_PWEN */ 6000 { RCAR_GP_PIN(6, 31), 4, 3 }, /* GP6_31/USB2_CH3_OVC */ 6001 } }, 6002 { }, 6003 }; 6004 6005 enum ioctrl_regs { 6006 POCCTRL, 6007 TDSELCTRL, 6008 }; 6009 6010 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { 6011 [POCCTRL] = { 0xe6060380, }, 6012 [TDSELCTRL] = { 0xe60603c0, }, 6013 { /* sentinel */ }, 6014 }; 6015 6016 static int r8a77951_pin_to_pocctrl(struct sh_pfc *pfc, 6017 unsigned int pin, u32 *pocctrl) 6018 { 6019 int bit = -EINVAL; 6020 6021 *pocctrl = pinmux_ioctrl_regs[POCCTRL].reg; 6022 6023 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11)) 6024 bit = pin & 0x1f; 6025 6026 if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17)) 6027 bit = (pin & 0x1f) + 12; 6028 6029 return bit; 6030 } 6031 6032 static const struct pinmux_bias_reg pinmux_bias_regs[] = { 6033 { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) { 6034 [ 0] = PIN_QSPI0_SPCLK, /* QSPI0_SPCLK */ 6035 [ 1] = PIN_QSPI0_MOSI_IO0, /* QSPI0_MOSI_IO0 */ 6036 [ 2] = PIN_QSPI0_MISO_IO1, /* QSPI0_MISO_IO1 */ 6037 [ 3] = PIN_QSPI0_IO2, /* QSPI0_IO2 */ 6038 [ 4] = PIN_QSPI0_IO3, /* QSPI0_IO3 */ 6039 [ 5] = PIN_QSPI0_SSL, /* QSPI0_SSL */ 6040 [ 6] = PIN_QSPI1_SPCLK, /* QSPI1_SPCLK */ 6041 [ 7] = PIN_QSPI1_MOSI_IO0, /* QSPI1_MOSI_IO0 */ 6042 [ 8] = PIN_QSPI1_MISO_IO1, /* QSPI1_MISO_IO1 */ 6043 [ 9] = PIN_QSPI1_IO2, /* QSPI1_IO2 */ 6044 [10] = PIN_QSPI1_IO3, /* QSPI1_IO3 */ 6045 [11] = PIN_QSPI1_SSL, /* QSPI1_SSL */ 6046 [12] = PIN_RPC_INT_N, /* RPC_INT# */ 6047 [13] = PIN_RPC_WP_N, /* RPC_WP# */ 6048 [14] = PIN_RPC_RESET_N, /* RPC_RESET# */ 6049 [15] = PIN_AVB_RX_CTL, /* AVB_RX_CTL */ 6050 [16] = PIN_AVB_RXC, /* AVB_RXC */ 6051 [17] = PIN_AVB_RD0, /* AVB_RD0 */ 6052 [18] = PIN_AVB_RD1, /* AVB_RD1 */ 6053 [19] = PIN_AVB_RD2, /* AVB_RD2 */ 6054 [20] = PIN_AVB_RD3, /* AVB_RD3 */ 6055 [21] = PIN_AVB_TX_CTL, /* AVB_TX_CTL */ 6056 [22] = PIN_AVB_TXC, /* AVB_TXC */ 6057 [23] = PIN_AVB_TD0, /* AVB_TD0 */ 6058 [24] = PIN_AVB_TD1, /* AVB_TD1 */ 6059 [25] = PIN_AVB_TD2, /* AVB_TD2 */ 6060 [26] = PIN_AVB_TD3, /* AVB_TD3 */ 6061 [27] = PIN_AVB_TXCREFCLK, /* AVB_TXCREFCLK */ 6062 [28] = PIN_AVB_MDIO, /* AVB_MDIO */ 6063 [29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */ 6064 [30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */ 6065 [31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */ 6066 } }, 6067 { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) { 6068 [ 0] = RCAR_GP_PIN(2, 12), /* AVB_LINK */ 6069 [ 1] = RCAR_GP_PIN(2, 13), /* AVB_AVTP_MATCH_A */ 6070 [ 2] = RCAR_GP_PIN(2, 14), /* AVB_AVTP_CAPTURE_A */ 6071 [ 3] = RCAR_GP_PIN(2, 0), /* IRQ0 */ 6072 [ 4] = RCAR_GP_PIN(2, 1), /* IRQ1 */ 6073 [ 5] = RCAR_GP_PIN(2, 2), /* IRQ2 */ 6074 [ 6] = RCAR_GP_PIN(2, 3), /* IRQ3 */ 6075 [ 7] = RCAR_GP_PIN(2, 4), /* IRQ4 */ 6076 [ 8] = RCAR_GP_PIN(2, 5), /* IRQ5 */ 6077 [ 9] = RCAR_GP_PIN(2, 6), /* PWM0 */ 6078 [10] = RCAR_GP_PIN(2, 7), /* PWM1_A */ 6079 [11] = RCAR_GP_PIN(2, 8), /* PWM2_A */ 6080 [12] = RCAR_GP_PIN(1, 0), /* A0 */ 6081 [13] = RCAR_GP_PIN(1, 1), /* A1 */ 6082 [14] = RCAR_GP_PIN(1, 2), /* A2 */ 6083 [15] = RCAR_GP_PIN(1, 3), /* A3 */ 6084 [16] = RCAR_GP_PIN(1, 4), /* A4 */ 6085 [17] = RCAR_GP_PIN(1, 5), /* A5 */ 6086 [18] = RCAR_GP_PIN(1, 6), /* A6 */ 6087 [19] = RCAR_GP_PIN(1, 7), /* A7 */ 6088 [20] = RCAR_GP_PIN(1, 8), /* A8 */ 6089 [21] = RCAR_GP_PIN(1, 9), /* A9 */ 6090 [22] = RCAR_GP_PIN(1, 10), /* A10 */ 6091 [23] = RCAR_GP_PIN(1, 11), /* A11 */ 6092 [24] = RCAR_GP_PIN(1, 12), /* A12 */ 6093 [25] = RCAR_GP_PIN(1, 13), /* A13 */ 6094 [26] = RCAR_GP_PIN(1, 14), /* A14 */ 6095 [27] = RCAR_GP_PIN(1, 15), /* A15 */ 6096 [28] = RCAR_GP_PIN(1, 16), /* A16 */ 6097 [29] = RCAR_GP_PIN(1, 17), /* A17 */ 6098 [30] = RCAR_GP_PIN(1, 18), /* A18 */ 6099 [31] = RCAR_GP_PIN(1, 19), /* A19 */ 6100 } }, 6101 { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) { 6102 [ 0] = RCAR_GP_PIN(1, 28), /* CLKOUT */ 6103 [ 1] = RCAR_GP_PIN(1, 20), /* CS0_N */ 6104 [ 2] = RCAR_GP_PIN(1, 21), /* CS1_N */ 6105 [ 3] = RCAR_GP_PIN(1, 22), /* BS_N */ 6106 [ 4] = RCAR_GP_PIN(1, 23), /* RD_N */ 6107 [ 5] = RCAR_GP_PIN(1, 24), /* RD_WR_N */ 6108 [ 6] = RCAR_GP_PIN(1, 25), /* WE0_N */ 6109 [ 7] = RCAR_GP_PIN(1, 26), /* WE1_N */ 6110 [ 8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */ 6111 [ 9] = PIN_PRESETOUT_N, /* PRESETOUT# */ 6112 [10] = RCAR_GP_PIN(0, 0), /* D0 */ 6113 [11] = RCAR_GP_PIN(0, 1), /* D1 */ 6114 [12] = RCAR_GP_PIN(0, 2), /* D2 */ 6115 [13] = RCAR_GP_PIN(0, 3), /* D3 */ 6116 [14] = RCAR_GP_PIN(0, 4), /* D4 */ 6117 [15] = RCAR_GP_PIN(0, 5), /* D5 */ 6118 [16] = RCAR_GP_PIN(0, 6), /* D6 */ 6119 [17] = RCAR_GP_PIN(0, 7), /* D7 */ 6120 [18] = RCAR_GP_PIN(0, 8), /* D8 */ 6121 [19] = RCAR_GP_PIN(0, 9), /* D9 */ 6122 [20] = RCAR_GP_PIN(0, 10), /* D10 */ 6123 [21] = RCAR_GP_PIN(0, 11), /* D11 */ 6124 [22] = RCAR_GP_PIN(0, 12), /* D12 */ 6125 [23] = RCAR_GP_PIN(0, 13), /* D13 */ 6126 [24] = RCAR_GP_PIN(0, 14), /* D14 */ 6127 [25] = RCAR_GP_PIN(0, 15), /* D15 */ 6128 [26] = RCAR_GP_PIN(7, 0), /* AVS1 */ 6129 [27] = RCAR_GP_PIN(7, 1), /* AVS2 */ 6130 [28] = RCAR_GP_PIN(7, 2), /* GP7_02 */ 6131 [29] = RCAR_GP_PIN(7, 3), /* GP7_03 */ 6132 [30] = PIN_DU_DOTCLKIN0, /* DU_DOTCLKIN0 */ 6133 [31] = PIN_DU_DOTCLKIN1, /* DU_DOTCLKIN1 */ 6134 } }, 6135 { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) { 6136 [ 0] = PIN_DU_DOTCLKIN2, /* DU_DOTCLKIN2 */ 6137 [ 1] = PIN_DU_DOTCLKIN3, /* DU_DOTCLKIN3 */ 6138 [ 2] = PIN_FSCLKST_N, /* FSCLKST# */ 6139 [ 3] = PIN_EXTALR, /* EXTALR*/ 6140 [ 4] = PIN_TRST_N, /* TRST# */ 6141 [ 5] = PIN_TCK, /* TCK */ 6142 [ 6] = PIN_TMS, /* TMS */ 6143 [ 7] = PIN_TDI, /* TDI */ 6144 [ 8] = SH_PFC_PIN_NONE, 6145 [ 9] = PIN_ASEBRK, /* ASEBRK */ 6146 [10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */ 6147 [11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */ 6148 [12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */ 6149 [13] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */ 6150 [14] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */ 6151 [15] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */ 6152 [16] = RCAR_GP_PIN(3, 6), /* SD1_CLK */ 6153 [17] = RCAR_GP_PIN(3, 7), /* SD1_CMD */ 6154 [18] = RCAR_GP_PIN(3, 8), /* SD1_DAT0 */ 6155 [19] = RCAR_GP_PIN(3, 9), /* SD1_DAT1 */ 6156 [20] = RCAR_GP_PIN(3, 10), /* SD1_DAT2 */ 6157 [21] = RCAR_GP_PIN(3, 11), /* SD1_DAT3 */ 6158 [22] = RCAR_GP_PIN(4, 0), /* SD2_CLK */ 6159 [23] = RCAR_GP_PIN(4, 1), /* SD2_CMD */ 6160 [24] = RCAR_GP_PIN(4, 2), /* SD2_DAT0 */ 6161 [25] = RCAR_GP_PIN(4, 3), /* SD2_DAT1 */ 6162 [26] = RCAR_GP_PIN(4, 4), /* SD2_DAT2 */ 6163 [27] = RCAR_GP_PIN(4, 5), /* SD2_DAT3 */ 6164 [28] = RCAR_GP_PIN(4, 6), /* SD2_DS */ 6165 [29] = RCAR_GP_PIN(4, 7), /* SD3_CLK */ 6166 [30] = RCAR_GP_PIN(4, 8), /* SD3_CMD */ 6167 [31] = RCAR_GP_PIN(4, 9), /* SD3_DAT0 */ 6168 } }, 6169 { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) { 6170 [ 0] = RCAR_GP_PIN(4, 10), /* SD3_DAT1 */ 6171 [ 1] = RCAR_GP_PIN(4, 11), /* SD3_DAT2 */ 6172 [ 2] = RCAR_GP_PIN(4, 12), /* SD3_DAT3 */ 6173 [ 3] = RCAR_GP_PIN(4, 13), /* SD3_DAT4 */ 6174 [ 4] = RCAR_GP_PIN(4, 14), /* SD3_DAT5 */ 6175 [ 5] = RCAR_GP_PIN(4, 15), /* SD3_DAT6 */ 6176 [ 6] = RCAR_GP_PIN(4, 16), /* SD3_DAT7 */ 6177 [ 7] = RCAR_GP_PIN(4, 17), /* SD3_DS */ 6178 [ 8] = RCAR_GP_PIN(3, 12), /* SD0_CD */ 6179 [ 9] = RCAR_GP_PIN(3, 13), /* SD0_WP */ 6180 [10] = RCAR_GP_PIN(3, 14), /* SD1_CD */ 6181 [11] = RCAR_GP_PIN(3, 15), /* SD1_WP */ 6182 [12] = RCAR_GP_PIN(5, 0), /* SCK0 */ 6183 [13] = RCAR_GP_PIN(5, 1), /* RX0 */ 6184 [14] = RCAR_GP_PIN(5, 2), /* TX0 */ 6185 [15] = RCAR_GP_PIN(5, 3), /* CTS0_N */ 6186 [16] = RCAR_GP_PIN(5, 4), /* RTS0_N */ 6187 [17] = RCAR_GP_PIN(5, 5), /* RX1_A */ 6188 [18] = RCAR_GP_PIN(5, 6), /* TX1_A */ 6189 [19] = RCAR_GP_PIN(5, 7), /* CTS1_N */ 6190 [20] = RCAR_GP_PIN(5, 8), /* RTS1_N */ 6191 [21] = RCAR_GP_PIN(5, 9), /* SCK2 */ 6192 [22] = RCAR_GP_PIN(5, 10), /* TX2_A */ 6193 [23] = RCAR_GP_PIN(5, 11), /* RX2_A */ 6194 [24] = RCAR_GP_PIN(5, 12), /* HSCK0 */ 6195 [25] = RCAR_GP_PIN(5, 13), /* HRX0 */ 6196 [26] = RCAR_GP_PIN(5, 14), /* HTX0 */ 6197 [27] = RCAR_GP_PIN(5, 15), /* HCTS0_N */ 6198 [28] = RCAR_GP_PIN(5, 16), /* HRTS0_N */ 6199 [29] = RCAR_GP_PIN(5, 17), /* MSIOF0_SCK */ 6200 [30] = RCAR_GP_PIN(5, 18), /* MSIOF0_SYNC */ 6201 [31] = RCAR_GP_PIN(5, 19), /* MSIOF0_SS1 */ 6202 } }, 6203 { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) { 6204 [ 0] = RCAR_GP_PIN(5, 20), /* MSIOF0_TXD */ 6205 [ 1] = RCAR_GP_PIN(5, 21), /* MSIOF0_SS2 */ 6206 [ 2] = RCAR_GP_PIN(5, 22), /* MSIOF0_RXD */ 6207 [ 3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */ 6208 [ 4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */ 6209 [ 5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */ 6210 [ 6] = PIN_MLB_REF, /* MLB_REF */ 6211 [ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */ 6212 [ 8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */ 6213 [ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */ 6214 [10] = RCAR_GP_PIN(6, 3), /* SSI_SDATA1_A */ 6215 [11] = RCAR_GP_PIN(6, 4), /* SSI_SDATA2_A */ 6216 [12] = RCAR_GP_PIN(6, 5), /* SSI_SCK349 */ 6217 [13] = RCAR_GP_PIN(6, 6), /* SSI_WS349 */ 6218 [14] = RCAR_GP_PIN(6, 7), /* SSI_SDATA3 */ 6219 [15] = RCAR_GP_PIN(6, 8), /* SSI_SCK4 */ 6220 [16] = RCAR_GP_PIN(6, 9), /* SSI_WS4 */ 6221 [17] = RCAR_GP_PIN(6, 10), /* SSI_SDATA4 */ 6222 [18] = RCAR_GP_PIN(6, 11), /* SSI_SCK5 */ 6223 [19] = RCAR_GP_PIN(6, 12), /* SSI_WS5 */ 6224 [20] = RCAR_GP_PIN(6, 13), /* SSI_SDATA5 */ 6225 [21] = RCAR_GP_PIN(6, 14), /* SSI_SCK6 */ 6226 [22] = RCAR_GP_PIN(6, 15), /* SSI_WS6 */ 6227 [23] = RCAR_GP_PIN(6, 16), /* SSI_SDATA6 */ 6228 [24] = RCAR_GP_PIN(6, 17), /* SSI_SCK78 */ 6229 [25] = RCAR_GP_PIN(6, 18), /* SSI_WS78 */ 6230 [26] = RCAR_GP_PIN(6, 19), /* SSI_SDATA7 */ 6231 [27] = RCAR_GP_PIN(6, 20), /* SSI_SDATA8 */ 6232 [28] = RCAR_GP_PIN(6, 21), /* SSI_SDATA9_A */ 6233 [29] = RCAR_GP_PIN(6, 22), /* AUDIO_CLKA_A */ 6234 [30] = RCAR_GP_PIN(6, 23), /* AUDIO_CLKB_B */ 6235 [31] = RCAR_GP_PIN(6, 24), /* USB0_PWEN */ 6236 } }, 6237 { PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) { 6238 [ 0] = RCAR_GP_PIN(6, 25), /* USB0_OVC */ 6239 [ 1] = RCAR_GP_PIN(6, 26), /* USB1_PWEN */ 6240 [ 2] = RCAR_GP_PIN(6, 27), /* USB1_OVC */ 6241 [ 3] = RCAR_GP_PIN(6, 28), /* USB30_PWEN */ 6242 [ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */ 6243 [ 5] = RCAR_GP_PIN(6, 30), /* USB2_CH3_PWEN */ 6244 [ 6] = RCAR_GP_PIN(6, 31), /* USB2_CH3_OVC */ 6245 [ 7] = SH_PFC_PIN_NONE, 6246 [ 8] = SH_PFC_PIN_NONE, 6247 [ 9] = SH_PFC_PIN_NONE, 6248 [10] = SH_PFC_PIN_NONE, 6249 [11] = SH_PFC_PIN_NONE, 6250 [12] = SH_PFC_PIN_NONE, 6251 [13] = SH_PFC_PIN_NONE, 6252 [14] = SH_PFC_PIN_NONE, 6253 [15] = SH_PFC_PIN_NONE, 6254 [16] = SH_PFC_PIN_NONE, 6255 [17] = SH_PFC_PIN_NONE, 6256 [18] = SH_PFC_PIN_NONE, 6257 [19] = SH_PFC_PIN_NONE, 6258 [20] = SH_PFC_PIN_NONE, 6259 [21] = SH_PFC_PIN_NONE, 6260 [22] = SH_PFC_PIN_NONE, 6261 [23] = SH_PFC_PIN_NONE, 6262 [24] = SH_PFC_PIN_NONE, 6263 [25] = SH_PFC_PIN_NONE, 6264 [26] = SH_PFC_PIN_NONE, 6265 [27] = SH_PFC_PIN_NONE, 6266 [28] = SH_PFC_PIN_NONE, 6267 [29] = SH_PFC_PIN_NONE, 6268 [30] = SH_PFC_PIN_NONE, 6269 [31] = SH_PFC_PIN_NONE, 6270 } }, 6271 { /* sentinel */ }, 6272 }; 6273 6274 static const struct sh_pfc_soc_operations r8a77951_pinmux_ops = { 6275 .pin_to_pocctrl = r8a77951_pin_to_pocctrl, 6276 .get_bias = rcar_pinmux_get_bias, 6277 .set_bias = rcar_pinmux_set_bias, 6278 }; 6279 6280 #ifdef CONFIG_PINCTRL_PFC_R8A774E1 6281 const struct sh_pfc_soc_info r8a774e1_pinmux_info = { 6282 .name = "r8a774e1_pfc", 6283 .ops = &r8a77951_pinmux_ops, 6284 .unlock_reg = 0xe6060000, /* PMMR */ 6285 6286 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 6287 6288 .pins = pinmux_pins, 6289 .nr_pins = ARRAY_SIZE(pinmux_pins), 6290 .groups = pinmux_groups.common, 6291 .nr_groups = ARRAY_SIZE(pinmux_groups.common), 6292 .functions = pinmux_functions.common, 6293 .nr_functions = ARRAY_SIZE(pinmux_functions.common), 6294 6295 .cfg_regs = pinmux_config_regs, 6296 .drive_regs = pinmux_drive_regs, 6297 .bias_regs = pinmux_bias_regs, 6298 .ioctrl_regs = pinmux_ioctrl_regs, 6299 6300 .pinmux_data = pinmux_data, 6301 .pinmux_data_size = ARRAY_SIZE(pinmux_data), 6302 }; 6303 #endif 6304 6305 #ifdef CONFIG_PINCTRL_PFC_R8A77951 6306 const struct sh_pfc_soc_info r8a77951_pinmux_info = { 6307 .name = "r8a77951_pfc", 6308 .ops = &r8a77951_pinmux_ops, 6309 .unlock_reg = 0xe6060000, /* PMMR */ 6310 6311 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 6312 6313 .pins = pinmux_pins, 6314 .nr_pins = ARRAY_SIZE(pinmux_pins), 6315 .groups = pinmux_groups.common, 6316 .nr_groups = ARRAY_SIZE(pinmux_groups.common) + 6317 ARRAY_SIZE(pinmux_groups.automotive), 6318 .functions = pinmux_functions.common, 6319 .nr_functions = ARRAY_SIZE(pinmux_functions.common) + 6320 ARRAY_SIZE(pinmux_functions.automotive), 6321 6322 .cfg_regs = pinmux_config_regs, 6323 .drive_regs = pinmux_drive_regs, 6324 .bias_regs = pinmux_bias_regs, 6325 .ioctrl_regs = pinmux_ioctrl_regs, 6326 6327 .pinmux_data = pinmux_data, 6328 .pinmux_data_size = ARRAY_SIZE(pinmux_data), 6329 }; 6330 #endif 6331