1077365a9SGeert Uytterhoeven // SPDX-License-Identifier: GPL-2.0 2077365a9SGeert Uytterhoeven /* 3077365a9SGeert Uytterhoeven * R8A77951 processor support - PFC hardware block. 4077365a9SGeert Uytterhoeven * 5077365a9SGeert Uytterhoeven * Copyright (C) 2015-2019 Renesas Electronics Corporation 6077365a9SGeert Uytterhoeven */ 7077365a9SGeert Uytterhoeven 8077365a9SGeert Uytterhoeven #include <linux/errno.h> 9077365a9SGeert Uytterhoeven #include <linux/kernel.h> 10077365a9SGeert Uytterhoeven #include <linux/sys_soc.h> 11077365a9SGeert Uytterhoeven 12077365a9SGeert Uytterhoeven #include "sh_pfc.h" 13077365a9SGeert Uytterhoeven 14077365a9SGeert Uytterhoeven #define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN) 15077365a9SGeert Uytterhoeven 16077365a9SGeert Uytterhoeven #define CPU_ALL_GP(fn, sfx) \ 17077365a9SGeert Uytterhoeven PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \ 18077365a9SGeert Uytterhoeven PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \ 19077365a9SGeert Uytterhoeven PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \ 20*a3ca1e18SGeert Uytterhoeven PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ 21077365a9SGeert Uytterhoeven PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \ 22077365a9SGeert Uytterhoeven PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \ 23077365a9SGeert Uytterhoeven PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \ 24077365a9SGeert Uytterhoeven PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \ 25*a3ca1e18SGeert Uytterhoeven PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ 26077365a9SGeert Uytterhoeven PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \ 27077365a9SGeert Uytterhoeven PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \ 28077365a9SGeert Uytterhoeven PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS) 29077365a9SGeert Uytterhoeven 30077365a9SGeert Uytterhoeven #define CPU_ALL_NOGP(fn) \ 31077365a9SGeert Uytterhoeven PIN_NOGP_CFG(ASEBRK, "ASEBRK", fn, CFG_FLAGS), \ 32077365a9SGeert Uytterhoeven PIN_NOGP_CFG(AVB_MDIO, "AVB_MDIO", fn, CFG_FLAGS), \ 33077365a9SGeert Uytterhoeven PIN_NOGP_CFG(AVB_RD0, "AVB_RD0", fn, CFG_FLAGS), \ 34077365a9SGeert Uytterhoeven PIN_NOGP_CFG(AVB_RD1, "AVB_RD1", fn, CFG_FLAGS), \ 35077365a9SGeert Uytterhoeven PIN_NOGP_CFG(AVB_RD2, "AVB_RD2", fn, CFG_FLAGS), \ 36077365a9SGeert Uytterhoeven PIN_NOGP_CFG(AVB_RD3, "AVB_RD3", fn, CFG_FLAGS), \ 37077365a9SGeert Uytterhoeven PIN_NOGP_CFG(AVB_RXC, "AVB_RXC", fn, CFG_FLAGS), \ 38077365a9SGeert Uytterhoeven PIN_NOGP_CFG(AVB_RX_CTL, "AVB_RX_CTL", fn, CFG_FLAGS), \ 39077365a9SGeert Uytterhoeven PIN_NOGP_CFG(AVB_TD0, "AVB_TD0", fn, CFG_FLAGS), \ 40077365a9SGeert Uytterhoeven PIN_NOGP_CFG(AVB_TD1, "AVB_TD1", fn, CFG_FLAGS), \ 41077365a9SGeert Uytterhoeven PIN_NOGP_CFG(AVB_TD2, "AVB_TD2", fn, CFG_FLAGS), \ 42077365a9SGeert Uytterhoeven PIN_NOGP_CFG(AVB_TD3, "AVB_TD3", fn, CFG_FLAGS), \ 43077365a9SGeert Uytterhoeven PIN_NOGP_CFG(AVB_TXC, "AVB_TXC", fn, CFG_FLAGS), \ 44077365a9SGeert Uytterhoeven PIN_NOGP_CFG(AVB_TXCREFCLK, "AVB_TXCREFCLK", fn, CFG_FLAGS), \ 45077365a9SGeert Uytterhoeven PIN_NOGP_CFG(AVB_TX_CTL, "AVB_TX_CTL", fn, CFG_FLAGS), \ 46077365a9SGeert Uytterhoeven PIN_NOGP_CFG(DU_DOTCLKIN0, "DU_DOTCLKIN0", fn, CFG_FLAGS), \ 47077365a9SGeert Uytterhoeven PIN_NOGP_CFG(DU_DOTCLKIN1, "DU_DOTCLKIN1", fn, CFG_FLAGS), \ 48077365a9SGeert Uytterhoeven PIN_NOGP_CFG(DU_DOTCLKIN2, "DU_DOTCLKIN2", fn, CFG_FLAGS), \ 49077365a9SGeert Uytterhoeven PIN_NOGP_CFG(DU_DOTCLKIN3, "DU_DOTCLKIN3", fn, CFG_FLAGS), \ 50077365a9SGeert Uytterhoeven PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),\ 51077365a9SGeert Uytterhoeven PIN_NOGP_CFG(FSCLKST_N, "FSCLKST#", fn, CFG_FLAGS), \ 52077365a9SGeert Uytterhoeven PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS), \ 53077365a9SGeert Uytterhoeven PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, CFG_FLAGS), \ 54077365a9SGeert Uytterhoeven PIN_NOGP_CFG(QSPI0_IO2, "QSPI0_IO2", fn, CFG_FLAGS), \ 55077365a9SGeert Uytterhoeven PIN_NOGP_CFG(QSPI0_IO3, "QSPI0_IO3", fn, CFG_FLAGS), \ 56077365a9SGeert Uytterhoeven PIN_NOGP_CFG(QSPI0_MISO_IO1, "QSPI0_MISO_IO1", fn, CFG_FLAGS), \ 57077365a9SGeert Uytterhoeven PIN_NOGP_CFG(QSPI0_MOSI_IO0, "QSPI0_MOSI_IO0", fn, CFG_FLAGS), \ 58077365a9SGeert Uytterhoeven PIN_NOGP_CFG(QSPI0_SPCLK, "QSPI0_SPCLK", fn, CFG_FLAGS), \ 59077365a9SGeert Uytterhoeven PIN_NOGP_CFG(QSPI0_SSL, "QSPI0_SSL", fn, CFG_FLAGS), \ 60077365a9SGeert Uytterhoeven PIN_NOGP_CFG(QSPI1_IO2, "QSPI1_IO2", fn, CFG_FLAGS), \ 61077365a9SGeert Uytterhoeven PIN_NOGP_CFG(QSPI1_IO3, "QSPI1_IO3", fn, CFG_FLAGS), \ 62077365a9SGeert Uytterhoeven PIN_NOGP_CFG(QSPI1_MISO_IO1, "QSPI1_MISO_IO1", fn, CFG_FLAGS), \ 63077365a9SGeert Uytterhoeven PIN_NOGP_CFG(QSPI1_MOSI_IO0, "QSPI1_MOSI_IO0", fn, CFG_FLAGS), \ 64077365a9SGeert Uytterhoeven PIN_NOGP_CFG(QSPI1_SPCLK, "QSPI1_SPCLK", fn, CFG_FLAGS), \ 65077365a9SGeert Uytterhoeven PIN_NOGP_CFG(QSPI1_SSL, "QSPI1_SSL", fn, CFG_FLAGS), \ 66077365a9SGeert Uytterhoeven PIN_NOGP_CFG(RPC_INT_N, "RPC_INT#", fn, CFG_FLAGS), \ 67077365a9SGeert Uytterhoeven PIN_NOGP_CFG(RPC_RESET_N, "RPC_RESET#", fn, CFG_FLAGS), \ 68077365a9SGeert Uytterhoeven PIN_NOGP_CFG(RPC_WP_N, "RPC_WP#", fn, CFG_FLAGS), \ 69077365a9SGeert Uytterhoeven PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ 70077365a9SGeert Uytterhoeven PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ 71077365a9SGeert Uytterhoeven PIN_NOGP_CFG(TDO, "TDO", fn, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \ 72077365a9SGeert Uytterhoeven PIN_NOGP_CFG(TMS, "TMS", fn, CFG_FLAGS), \ 73077365a9SGeert Uytterhoeven PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN) 74077365a9SGeert Uytterhoeven 75077365a9SGeert Uytterhoeven /* 76077365a9SGeert Uytterhoeven * F_() : just information 77077365a9SGeert Uytterhoeven * FM() : macro for FN_xxx / xxx_MARK 78077365a9SGeert Uytterhoeven */ 79077365a9SGeert Uytterhoeven 80077365a9SGeert Uytterhoeven /* GPSR0 */ 81077365a9SGeert Uytterhoeven #define GPSR0_15 F_(D15, IP7_11_8) 82077365a9SGeert Uytterhoeven #define GPSR0_14 F_(D14, IP7_7_4) 83077365a9SGeert Uytterhoeven #define GPSR0_13 F_(D13, IP7_3_0) 84077365a9SGeert Uytterhoeven #define GPSR0_12 F_(D12, IP6_31_28) 85077365a9SGeert Uytterhoeven #define GPSR0_11 F_(D11, IP6_27_24) 86077365a9SGeert Uytterhoeven #define GPSR0_10 F_(D10, IP6_23_20) 87077365a9SGeert Uytterhoeven #define GPSR0_9 F_(D9, IP6_19_16) 88077365a9SGeert Uytterhoeven #define GPSR0_8 F_(D8, IP6_15_12) 89077365a9SGeert Uytterhoeven #define GPSR0_7 F_(D7, IP6_11_8) 90077365a9SGeert Uytterhoeven #define GPSR0_6 F_(D6, IP6_7_4) 91077365a9SGeert Uytterhoeven #define GPSR0_5 F_(D5, IP6_3_0) 92077365a9SGeert Uytterhoeven #define GPSR0_4 F_(D4, IP5_31_28) 93077365a9SGeert Uytterhoeven #define GPSR0_3 F_(D3, IP5_27_24) 94077365a9SGeert Uytterhoeven #define GPSR0_2 F_(D2, IP5_23_20) 95077365a9SGeert Uytterhoeven #define GPSR0_1 F_(D1, IP5_19_16) 96077365a9SGeert Uytterhoeven #define GPSR0_0 F_(D0, IP5_15_12) 97077365a9SGeert Uytterhoeven 98077365a9SGeert Uytterhoeven /* GPSR1 */ 99077365a9SGeert Uytterhoeven #define GPSR1_28 FM(CLKOUT) 100077365a9SGeert Uytterhoeven #define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8) 101077365a9SGeert Uytterhoeven #define GPSR1_26 F_(WE1_N, IP5_7_4) 102077365a9SGeert Uytterhoeven #define GPSR1_25 F_(WE0_N, IP5_3_0) 103077365a9SGeert Uytterhoeven #define GPSR1_24 F_(RD_WR_N, IP4_31_28) 104077365a9SGeert Uytterhoeven #define GPSR1_23 F_(RD_N, IP4_27_24) 105077365a9SGeert Uytterhoeven #define GPSR1_22 F_(BS_N, IP4_23_20) 106077365a9SGeert Uytterhoeven #define GPSR1_21 F_(CS1_N, IP4_19_16) 107077365a9SGeert Uytterhoeven #define GPSR1_20 F_(CS0_N, IP4_15_12) 108077365a9SGeert Uytterhoeven #define GPSR1_19 F_(A19, IP4_11_8) 109077365a9SGeert Uytterhoeven #define GPSR1_18 F_(A18, IP4_7_4) 110077365a9SGeert Uytterhoeven #define GPSR1_17 F_(A17, IP4_3_0) 111077365a9SGeert Uytterhoeven #define GPSR1_16 F_(A16, IP3_31_28) 112077365a9SGeert Uytterhoeven #define GPSR1_15 F_(A15, IP3_27_24) 113077365a9SGeert Uytterhoeven #define GPSR1_14 F_(A14, IP3_23_20) 114077365a9SGeert Uytterhoeven #define GPSR1_13 F_(A13, IP3_19_16) 115077365a9SGeert Uytterhoeven #define GPSR1_12 F_(A12, IP3_15_12) 116077365a9SGeert Uytterhoeven #define GPSR1_11 F_(A11, IP3_11_8) 117077365a9SGeert Uytterhoeven #define GPSR1_10 F_(A10, IP3_7_4) 118077365a9SGeert Uytterhoeven #define GPSR1_9 F_(A9, IP3_3_0) 119077365a9SGeert Uytterhoeven #define GPSR1_8 F_(A8, IP2_31_28) 120077365a9SGeert Uytterhoeven #define GPSR1_7 F_(A7, IP2_27_24) 121077365a9SGeert Uytterhoeven #define GPSR1_6 F_(A6, IP2_23_20) 122077365a9SGeert Uytterhoeven #define GPSR1_5 F_(A5, IP2_19_16) 123077365a9SGeert Uytterhoeven #define GPSR1_4 F_(A4, IP2_15_12) 124077365a9SGeert Uytterhoeven #define GPSR1_3 F_(A3, IP2_11_8) 125077365a9SGeert Uytterhoeven #define GPSR1_2 F_(A2, IP2_7_4) 126077365a9SGeert Uytterhoeven #define GPSR1_1 F_(A1, IP2_3_0) 127077365a9SGeert Uytterhoeven #define GPSR1_0 F_(A0, IP1_31_28) 128077365a9SGeert Uytterhoeven 129077365a9SGeert Uytterhoeven /* GPSR2 */ 130077365a9SGeert Uytterhoeven #define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20) 131077365a9SGeert Uytterhoeven #define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16) 132077365a9SGeert Uytterhoeven #define GPSR2_12 F_(AVB_LINK, IP0_15_12) 133077365a9SGeert Uytterhoeven #define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8) 134077365a9SGeert Uytterhoeven #define GPSR2_10 F_(AVB_MAGIC, IP0_7_4) 135077365a9SGeert Uytterhoeven #define GPSR2_9 F_(AVB_MDC, IP0_3_0) 136077365a9SGeert Uytterhoeven #define GPSR2_8 F_(PWM2_A, IP1_27_24) 137077365a9SGeert Uytterhoeven #define GPSR2_7 F_(PWM1_A, IP1_23_20) 138077365a9SGeert Uytterhoeven #define GPSR2_6 F_(PWM0, IP1_19_16) 139077365a9SGeert Uytterhoeven #define GPSR2_5 F_(IRQ5, IP1_15_12) 140077365a9SGeert Uytterhoeven #define GPSR2_4 F_(IRQ4, IP1_11_8) 141077365a9SGeert Uytterhoeven #define GPSR2_3 F_(IRQ3, IP1_7_4) 142077365a9SGeert Uytterhoeven #define GPSR2_2 F_(IRQ2, IP1_3_0) 143077365a9SGeert Uytterhoeven #define GPSR2_1 F_(IRQ1, IP0_31_28) 144077365a9SGeert Uytterhoeven #define GPSR2_0 F_(IRQ0, IP0_27_24) 145077365a9SGeert Uytterhoeven 146077365a9SGeert Uytterhoeven /* GPSR3 */ 147077365a9SGeert Uytterhoeven #define GPSR3_15 F_(SD1_WP, IP11_23_20) 148077365a9SGeert Uytterhoeven #define GPSR3_14 F_(SD1_CD, IP11_19_16) 149077365a9SGeert Uytterhoeven #define GPSR3_13 F_(SD0_WP, IP11_15_12) 150077365a9SGeert Uytterhoeven #define GPSR3_12 F_(SD0_CD, IP11_11_8) 151077365a9SGeert Uytterhoeven #define GPSR3_11 F_(SD1_DAT3, IP8_31_28) 152077365a9SGeert Uytterhoeven #define GPSR3_10 F_(SD1_DAT2, IP8_27_24) 153077365a9SGeert Uytterhoeven #define GPSR3_9 F_(SD1_DAT1, IP8_23_20) 154077365a9SGeert Uytterhoeven #define GPSR3_8 F_(SD1_DAT0, IP8_19_16) 155077365a9SGeert Uytterhoeven #define GPSR3_7 F_(SD1_CMD, IP8_15_12) 156077365a9SGeert Uytterhoeven #define GPSR3_6 F_(SD1_CLK, IP8_11_8) 157077365a9SGeert Uytterhoeven #define GPSR3_5 F_(SD0_DAT3, IP8_7_4) 158077365a9SGeert Uytterhoeven #define GPSR3_4 F_(SD0_DAT2, IP8_3_0) 159077365a9SGeert Uytterhoeven #define GPSR3_3 F_(SD0_DAT1, IP7_31_28) 160077365a9SGeert Uytterhoeven #define GPSR3_2 F_(SD0_DAT0, IP7_27_24) 161077365a9SGeert Uytterhoeven #define GPSR3_1 F_(SD0_CMD, IP7_23_20) 162077365a9SGeert Uytterhoeven #define GPSR3_0 F_(SD0_CLK, IP7_19_16) 163077365a9SGeert Uytterhoeven 164077365a9SGeert Uytterhoeven /* GPSR4 */ 165077365a9SGeert Uytterhoeven #define GPSR4_17 F_(SD3_DS, IP11_7_4) 166077365a9SGeert Uytterhoeven #define GPSR4_16 F_(SD3_DAT7, IP11_3_0) 167077365a9SGeert Uytterhoeven #define GPSR4_15 F_(SD3_DAT6, IP10_31_28) 168077365a9SGeert Uytterhoeven #define GPSR4_14 F_(SD3_DAT5, IP10_27_24) 169077365a9SGeert Uytterhoeven #define GPSR4_13 F_(SD3_DAT4, IP10_23_20) 170077365a9SGeert Uytterhoeven #define GPSR4_12 F_(SD3_DAT3, IP10_19_16) 171077365a9SGeert Uytterhoeven #define GPSR4_11 F_(SD3_DAT2, IP10_15_12) 172077365a9SGeert Uytterhoeven #define GPSR4_10 F_(SD3_DAT1, IP10_11_8) 173077365a9SGeert Uytterhoeven #define GPSR4_9 F_(SD3_DAT0, IP10_7_4) 174077365a9SGeert Uytterhoeven #define GPSR4_8 F_(SD3_CMD, IP10_3_0) 175077365a9SGeert Uytterhoeven #define GPSR4_7 F_(SD3_CLK, IP9_31_28) 176077365a9SGeert Uytterhoeven #define GPSR4_6 F_(SD2_DS, IP9_27_24) 177077365a9SGeert Uytterhoeven #define GPSR4_5 F_(SD2_DAT3, IP9_23_20) 178077365a9SGeert Uytterhoeven #define GPSR4_4 F_(SD2_DAT2, IP9_19_16) 179077365a9SGeert Uytterhoeven #define GPSR4_3 F_(SD2_DAT1, IP9_15_12) 180077365a9SGeert Uytterhoeven #define GPSR4_2 F_(SD2_DAT0, IP9_11_8) 181077365a9SGeert Uytterhoeven #define GPSR4_1 F_(SD2_CMD, IP9_7_4) 182077365a9SGeert Uytterhoeven #define GPSR4_0 F_(SD2_CLK, IP9_3_0) 183077365a9SGeert Uytterhoeven 184077365a9SGeert Uytterhoeven /* GPSR5 */ 185077365a9SGeert Uytterhoeven #define GPSR5_25 F_(MLB_DAT, IP14_19_16) 186077365a9SGeert Uytterhoeven #define GPSR5_24 F_(MLB_SIG, IP14_15_12) 187077365a9SGeert Uytterhoeven #define GPSR5_23 F_(MLB_CLK, IP14_11_8) 188077365a9SGeert Uytterhoeven #define GPSR5_22 FM(MSIOF0_RXD) 189077365a9SGeert Uytterhoeven #define GPSR5_21 F_(MSIOF0_SS2, IP14_7_4) 190077365a9SGeert Uytterhoeven #define GPSR5_20 FM(MSIOF0_TXD) 191077365a9SGeert Uytterhoeven #define GPSR5_19 F_(MSIOF0_SS1, IP14_3_0) 192077365a9SGeert Uytterhoeven #define GPSR5_18 F_(MSIOF0_SYNC, IP13_31_28) 193077365a9SGeert Uytterhoeven #define GPSR5_17 FM(MSIOF0_SCK) 194077365a9SGeert Uytterhoeven #define GPSR5_16 F_(HRTS0_N, IP13_27_24) 195077365a9SGeert Uytterhoeven #define GPSR5_15 F_(HCTS0_N, IP13_23_20) 196077365a9SGeert Uytterhoeven #define GPSR5_14 F_(HTX0, IP13_19_16) 197077365a9SGeert Uytterhoeven #define GPSR5_13 F_(HRX0, IP13_15_12) 198077365a9SGeert Uytterhoeven #define GPSR5_12 F_(HSCK0, IP13_11_8) 199077365a9SGeert Uytterhoeven #define GPSR5_11 F_(RX2_A, IP13_7_4) 200077365a9SGeert Uytterhoeven #define GPSR5_10 F_(TX2_A, IP13_3_0) 201077365a9SGeert Uytterhoeven #define GPSR5_9 F_(SCK2, IP12_31_28) 202077365a9SGeert Uytterhoeven #define GPSR5_8 F_(RTS1_N, IP12_27_24) 203077365a9SGeert Uytterhoeven #define GPSR5_7 F_(CTS1_N, IP12_23_20) 204077365a9SGeert Uytterhoeven #define GPSR5_6 F_(TX1_A, IP12_19_16) 205077365a9SGeert Uytterhoeven #define GPSR5_5 F_(RX1_A, IP12_15_12) 206077365a9SGeert Uytterhoeven #define GPSR5_4 F_(RTS0_N, IP12_11_8) 207077365a9SGeert Uytterhoeven #define GPSR5_3 F_(CTS0_N, IP12_7_4) 208077365a9SGeert Uytterhoeven #define GPSR5_2 F_(TX0, IP12_3_0) 209077365a9SGeert Uytterhoeven #define GPSR5_1 F_(RX0, IP11_31_28) 210077365a9SGeert Uytterhoeven #define GPSR5_0 F_(SCK0, IP11_27_24) 211077365a9SGeert Uytterhoeven 212077365a9SGeert Uytterhoeven /* GPSR6 */ 213077365a9SGeert Uytterhoeven #define GPSR6_31 F_(USB2_CH3_OVC, IP18_7_4) 214077365a9SGeert Uytterhoeven #define GPSR6_30 F_(USB2_CH3_PWEN, IP18_3_0) 215077365a9SGeert Uytterhoeven #define GPSR6_29 F_(USB30_OVC, IP17_31_28) 216077365a9SGeert Uytterhoeven #define GPSR6_28 F_(USB30_PWEN, IP17_27_24) 217077365a9SGeert Uytterhoeven #define GPSR6_27 F_(USB1_OVC, IP17_23_20) 218077365a9SGeert Uytterhoeven #define GPSR6_26 F_(USB1_PWEN, IP17_19_16) 219077365a9SGeert Uytterhoeven #define GPSR6_25 F_(USB0_OVC, IP17_15_12) 220077365a9SGeert Uytterhoeven #define GPSR6_24 F_(USB0_PWEN, IP17_11_8) 221077365a9SGeert Uytterhoeven #define GPSR6_23 F_(AUDIO_CLKB_B, IP17_7_4) 222077365a9SGeert Uytterhoeven #define GPSR6_22 F_(AUDIO_CLKA_A, IP17_3_0) 223077365a9SGeert Uytterhoeven #define GPSR6_21 F_(SSI_SDATA9_A, IP16_31_28) 224077365a9SGeert Uytterhoeven #define GPSR6_20 F_(SSI_SDATA8, IP16_27_24) 225077365a9SGeert Uytterhoeven #define GPSR6_19 F_(SSI_SDATA7, IP16_23_20) 226077365a9SGeert Uytterhoeven #define GPSR6_18 F_(SSI_WS78, IP16_19_16) 227077365a9SGeert Uytterhoeven #define GPSR6_17 F_(SSI_SCK78, IP16_15_12) 228077365a9SGeert Uytterhoeven #define GPSR6_16 F_(SSI_SDATA6, IP16_11_8) 229077365a9SGeert Uytterhoeven #define GPSR6_15 F_(SSI_WS6, IP16_7_4) 230077365a9SGeert Uytterhoeven #define GPSR6_14 F_(SSI_SCK6, IP16_3_0) 231077365a9SGeert Uytterhoeven #define GPSR6_13 FM(SSI_SDATA5) 232077365a9SGeert Uytterhoeven #define GPSR6_12 FM(SSI_WS5) 233077365a9SGeert Uytterhoeven #define GPSR6_11 FM(SSI_SCK5) 234077365a9SGeert Uytterhoeven #define GPSR6_10 F_(SSI_SDATA4, IP15_31_28) 235077365a9SGeert Uytterhoeven #define GPSR6_9 F_(SSI_WS4, IP15_27_24) 236077365a9SGeert Uytterhoeven #define GPSR6_8 F_(SSI_SCK4, IP15_23_20) 237077365a9SGeert Uytterhoeven #define GPSR6_7 F_(SSI_SDATA3, IP15_19_16) 238077365a9SGeert Uytterhoeven #define GPSR6_6 F_(SSI_WS349, IP15_15_12) 239077365a9SGeert Uytterhoeven #define GPSR6_5 F_(SSI_SCK349, IP15_11_8) 240077365a9SGeert Uytterhoeven #define GPSR6_4 F_(SSI_SDATA2_A, IP15_7_4) 241077365a9SGeert Uytterhoeven #define GPSR6_3 F_(SSI_SDATA1_A, IP15_3_0) 242077365a9SGeert Uytterhoeven #define GPSR6_2 F_(SSI_SDATA0, IP14_31_28) 243077365a9SGeert Uytterhoeven #define GPSR6_1 F_(SSI_WS01239, IP14_27_24) 244077365a9SGeert Uytterhoeven #define GPSR6_0 F_(SSI_SCK01239, IP14_23_20) 245077365a9SGeert Uytterhoeven 246077365a9SGeert Uytterhoeven /* GPSR7 */ 247077365a9SGeert Uytterhoeven #define GPSR7_3 FM(GP7_03) 248077365a9SGeert Uytterhoeven #define GPSR7_2 FM(GP7_02) 249077365a9SGeert Uytterhoeven #define GPSR7_1 FM(AVS2) 250077365a9SGeert Uytterhoeven #define GPSR7_0 FM(AVS1) 251077365a9SGeert Uytterhoeven 252077365a9SGeert Uytterhoeven 253077365a9SGeert Uytterhoeven /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ 254077365a9SGeert Uytterhoeven #define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 255077365a9SGeert Uytterhoeven #define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 256077365a9SGeert Uytterhoeven #define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 257077365a9SGeert Uytterhoeven #define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 258077365a9SGeert Uytterhoeven #define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) FM(FSCLKST2_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 259077365a9SGeert Uytterhoeven #define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 260077365a9SGeert Uytterhoeven #define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 261077365a9SGeert Uytterhoeven #define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 262077365a9SGeert Uytterhoeven #define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 263077365a9SGeert Uytterhoeven #define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) F_(0, 0) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 264077365a9SGeert Uytterhoeven #define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) F_(0, 0) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 265077365a9SGeert Uytterhoeven #define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) F_(0, 0) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) FM(FSCLKST2_N_B) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 266077365a9SGeert Uytterhoeven #define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)F_(0, 0) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 267077365a9SGeert Uytterhoeven #define IP1_23_20 FM(PWM1_A) F_(0, 0) F_(0, 0) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 268077365a9SGeert Uytterhoeven #define IP1_27_24 FM(PWM2_A) F_(0, 0) F_(0, 0) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 269077365a9SGeert Uytterhoeven #define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 270077365a9SGeert Uytterhoeven #define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 271077365a9SGeert Uytterhoeven #define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 272077365a9SGeert Uytterhoeven #define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 273077365a9SGeert Uytterhoeven 274077365a9SGeert Uytterhoeven /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ 275077365a9SGeert Uytterhoeven #define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 276077365a9SGeert Uytterhoeven #define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 277077365a9SGeert Uytterhoeven #define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 278077365a9SGeert Uytterhoeven #define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 279077365a9SGeert Uytterhoeven #define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 280077365a9SGeert Uytterhoeven #define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 281077365a9SGeert Uytterhoeven #define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 282077365a9SGeert Uytterhoeven #define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 283077365a9SGeert Uytterhoeven #define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 284077365a9SGeert Uytterhoeven #define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 285077365a9SGeert Uytterhoeven #define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 286077365a9SGeert Uytterhoeven #define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 287077365a9SGeert Uytterhoeven #define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 288077365a9SGeert Uytterhoeven #define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 289077365a9SGeert Uytterhoeven #define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 290077365a9SGeert Uytterhoeven #define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 291077365a9SGeert Uytterhoeven #define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 292077365a9SGeert Uytterhoeven #define IP4_19_16 FM(CS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 293077365a9SGeert Uytterhoeven #define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 294077365a9SGeert Uytterhoeven #define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 295077365a9SGeert Uytterhoeven #define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 296077365a9SGeert Uytterhoeven #define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 297077365a9SGeert Uytterhoeven #define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 298077365a9SGeert Uytterhoeven #define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 299077365a9SGeert Uytterhoeven #define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 300077365a9SGeert Uytterhoeven #define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 301077365a9SGeert Uytterhoeven #define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 302077365a9SGeert Uytterhoeven #define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 303077365a9SGeert Uytterhoeven #define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 304077365a9SGeert Uytterhoeven #define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 305077365a9SGeert Uytterhoeven #define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 306077365a9SGeert Uytterhoeven #define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 307077365a9SGeert Uytterhoeven #define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 308077365a9SGeert Uytterhoeven #define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 309077365a9SGeert Uytterhoeven #define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 310077365a9SGeert Uytterhoeven #define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_C) FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 311077365a9SGeert Uytterhoeven #define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 312077365a9SGeert Uytterhoeven #define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 313077365a9SGeert Uytterhoeven #define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 314077365a9SGeert Uytterhoeven #define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 315077365a9SGeert Uytterhoeven #define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 316077365a9SGeert Uytterhoeven 317077365a9SGeert Uytterhoeven /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ 318077365a9SGeert Uytterhoeven #define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 319077365a9SGeert Uytterhoeven #define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 320077365a9SGeert Uytterhoeven #define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 321077365a9SGeert Uytterhoeven #define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 322077365a9SGeert Uytterhoeven #define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 323077365a9SGeert Uytterhoeven #define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 324077365a9SGeert Uytterhoeven #define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) FM(NFCE_N_B) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 325077365a9SGeert Uytterhoeven #define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) FM(NFWP_N_B) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 326077365a9SGeert Uytterhoeven #define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) FM(NFDATA14_B) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 327077365a9SGeert Uytterhoeven #define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) FM(NFDATA15_B) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 328077365a9SGeert Uytterhoeven #define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) FM(NFRB_N_B) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 329077365a9SGeert Uytterhoeven #define IP9_3_0 FM(SD2_CLK) F_(0, 0) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 330077365a9SGeert Uytterhoeven #define IP9_7_4 FM(SD2_CMD) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 331077365a9SGeert Uytterhoeven #define IP9_11_8 FM(SD2_DAT0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 332077365a9SGeert Uytterhoeven #define IP9_15_12 FM(SD2_DAT1) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 333077365a9SGeert Uytterhoeven #define IP9_19_16 FM(SD2_DAT2) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 334077365a9SGeert Uytterhoeven #define IP9_23_20 FM(SD2_DAT3) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 335077365a9SGeert Uytterhoeven #define IP9_27_24 FM(SD2_DS) F_(0, 0) FM(NFALE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 336077365a9SGeert Uytterhoeven #define IP9_31_28 FM(SD3_CLK) F_(0, 0) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 337077365a9SGeert Uytterhoeven #define IP10_3_0 FM(SD3_CMD) F_(0, 0) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 338077365a9SGeert Uytterhoeven #define IP10_7_4 FM(SD3_DAT0) F_(0, 0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 339077365a9SGeert Uytterhoeven #define IP10_11_8 FM(SD3_DAT1) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 340077365a9SGeert Uytterhoeven #define IP10_15_12 FM(SD3_DAT2) F_(0, 0) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 341077365a9SGeert Uytterhoeven #define IP10_19_16 FM(SD3_DAT3) F_(0, 0) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 342077365a9SGeert Uytterhoeven #define IP10_23_20 FM(SD3_DAT4) FM(SD2_CD_A) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 343077365a9SGeert Uytterhoeven #define IP10_27_24 FM(SD3_DAT5) FM(SD2_WP_A) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 344077365a9SGeert Uytterhoeven #define IP10_31_28 FM(SD3_DAT6) FM(SD3_CD) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 345077365a9SGeert Uytterhoeven #define IP11_3_0 FM(SD3_DAT7) FM(SD3_WP) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 346077365a9SGeert Uytterhoeven #define IP11_7_4 FM(SD3_DS) F_(0, 0) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 347077365a9SGeert Uytterhoeven #define IP11_11_8 FM(SD0_CD) F_(0, 0) FM(NFDATA14_A) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 348077365a9SGeert Uytterhoeven 349077365a9SGeert Uytterhoeven /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ 350077365a9SGeert Uytterhoeven #define IP11_15_12 FM(SD0_WP) F_(0, 0) FM(NFDATA15_A) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 351077365a9SGeert Uytterhoeven #define IP11_19_16 FM(SD1_CD) F_(0, 0) FM(NFRB_N_A) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 352077365a9SGeert Uytterhoeven #define IP11_23_20 FM(SD1_WP) F_(0, 0) FM(NFCE_N_A) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 353077365a9SGeert Uytterhoeven #define IP11_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 354077365a9SGeert Uytterhoeven #define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 355077365a9SGeert Uytterhoeven #define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 356077365a9SGeert Uytterhoeven #define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 357077365a9SGeert Uytterhoeven #define IP12_11_8 FM(RTS0_N) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 358077365a9SGeert Uytterhoeven #define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 359077365a9SGeert Uytterhoeven #define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 360077365a9SGeert Uytterhoeven #define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 361077365a9SGeert Uytterhoeven #define IP12_27_24 FM(RTS1_N) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 362077365a9SGeert Uytterhoeven #define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 363077365a9SGeert Uytterhoeven #define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 364077365a9SGeert Uytterhoeven #define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 365077365a9SGeert Uytterhoeven #define IP13_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 366077365a9SGeert Uytterhoeven #define IP13_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 367077365a9SGeert Uytterhoeven #define IP13_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 368077365a9SGeert Uytterhoeven #define IP13_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 369077365a9SGeert Uytterhoeven #define IP13_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 370077365a9SGeert Uytterhoeven #define IP13_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) FM(TX5_B) F_(0, 0) F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0) 371077365a9SGeert Uytterhoeven #define IP14_3_0 FM(MSIOF0_SS1) FM(RX5_A) FM(NFWP_N_A) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 372077365a9SGeert Uytterhoeven #define IP14_7_4 FM(MSIOF0_SS2) FM(TX5_A) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 373077365a9SGeert Uytterhoeven #define IP14_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 374077365a9SGeert Uytterhoeven #define IP14_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 375077365a9SGeert Uytterhoeven #define IP14_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 376077365a9SGeert Uytterhoeven #define IP14_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 377077365a9SGeert Uytterhoeven #define IP14_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 378077365a9SGeert Uytterhoeven 379077365a9SGeert Uytterhoeven /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ 380077365a9SGeert Uytterhoeven #define IP14_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 381077365a9SGeert Uytterhoeven #define IP15_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 382077365a9SGeert Uytterhoeven #define IP15_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 383077365a9SGeert Uytterhoeven #define IP15_11_8 FM(SSI_SCK349) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 384077365a9SGeert Uytterhoeven #define IP15_15_12 FM(SSI_WS349) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 385077365a9SGeert Uytterhoeven #define IP15_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 386077365a9SGeert Uytterhoeven #define IP15_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 387077365a9SGeert Uytterhoeven #define IP15_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 388077365a9SGeert Uytterhoeven #define IP15_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 389077365a9SGeert Uytterhoeven #define IP16_3_0 FM(SSI_SCK6) FM(USB2_PWEN) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 390077365a9SGeert Uytterhoeven #define IP16_7_4 FM(SSI_WS6) FM(USB2_OVC) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 391077365a9SGeert Uytterhoeven #define IP16_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 392077365a9SGeert Uytterhoeven #define IP16_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 393077365a9SGeert Uytterhoeven #define IP16_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 394077365a9SGeert Uytterhoeven #define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 395077365a9SGeert Uytterhoeven #define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 396077365a9SGeert Uytterhoeven #define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 397077365a9SGeert Uytterhoeven #define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 398077365a9SGeert Uytterhoeven #define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 399077365a9SGeert Uytterhoeven #define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0) 400077365a9SGeert Uytterhoeven #define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0) 401077365a9SGeert Uytterhoeven #define IP17_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0) 402077365a9SGeert Uytterhoeven #define IP17_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0) 403077365a9SGeert Uytterhoeven #define IP17_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0) 404077365a9SGeert Uytterhoeven #define IP17_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_N) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 405077365a9SGeert Uytterhoeven #define IP18_3_0 FM(USB2_CH3_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0) 406077365a9SGeert Uytterhoeven #define IP18_7_4 FM(USB2_CH3_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0) 407077365a9SGeert Uytterhoeven 408077365a9SGeert Uytterhoeven #define PINMUX_GPSR \ 409077365a9SGeert Uytterhoeven \ 410077365a9SGeert Uytterhoeven GPSR6_31 \ 411077365a9SGeert Uytterhoeven GPSR6_30 \ 412077365a9SGeert Uytterhoeven GPSR6_29 \ 413077365a9SGeert Uytterhoeven GPSR1_28 GPSR6_28 \ 414077365a9SGeert Uytterhoeven GPSR1_27 GPSR6_27 \ 415077365a9SGeert Uytterhoeven GPSR1_26 GPSR6_26 \ 416077365a9SGeert Uytterhoeven GPSR1_25 GPSR5_25 GPSR6_25 \ 417077365a9SGeert Uytterhoeven GPSR1_24 GPSR5_24 GPSR6_24 \ 418077365a9SGeert Uytterhoeven GPSR1_23 GPSR5_23 GPSR6_23 \ 419077365a9SGeert Uytterhoeven GPSR1_22 GPSR5_22 GPSR6_22 \ 420077365a9SGeert Uytterhoeven GPSR1_21 GPSR5_21 GPSR6_21 \ 421077365a9SGeert Uytterhoeven GPSR1_20 GPSR5_20 GPSR6_20 \ 422077365a9SGeert Uytterhoeven GPSR1_19 GPSR5_19 GPSR6_19 \ 423077365a9SGeert Uytterhoeven GPSR1_18 GPSR5_18 GPSR6_18 \ 424077365a9SGeert Uytterhoeven GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \ 425077365a9SGeert Uytterhoeven GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \ 426077365a9SGeert Uytterhoeven GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \ 427077365a9SGeert Uytterhoeven GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \ 428077365a9SGeert Uytterhoeven GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \ 429077365a9SGeert Uytterhoeven GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \ 430077365a9SGeert Uytterhoeven GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \ 431077365a9SGeert Uytterhoeven GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \ 432077365a9SGeert Uytterhoeven GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \ 433077365a9SGeert Uytterhoeven GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \ 434077365a9SGeert Uytterhoeven GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \ 435077365a9SGeert Uytterhoeven GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \ 436077365a9SGeert Uytterhoeven GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \ 437077365a9SGeert Uytterhoeven GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \ 438077365a9SGeert Uytterhoeven GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \ 439077365a9SGeert Uytterhoeven GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \ 440077365a9SGeert Uytterhoeven GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \ 441077365a9SGeert Uytterhoeven GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0 442077365a9SGeert Uytterhoeven 443077365a9SGeert Uytterhoeven #define PINMUX_IPSR \ 444077365a9SGeert Uytterhoeven \ 445077365a9SGeert Uytterhoeven FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \ 446077365a9SGeert Uytterhoeven FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \ 447077365a9SGeert Uytterhoeven FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \ 448077365a9SGeert Uytterhoeven FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \ 449077365a9SGeert Uytterhoeven FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \ 450077365a9SGeert Uytterhoeven FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \ 451077365a9SGeert Uytterhoeven FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \ 452077365a9SGeert Uytterhoeven FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \ 453077365a9SGeert Uytterhoeven \ 454077365a9SGeert Uytterhoeven FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \ 455077365a9SGeert Uytterhoeven FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \ 456077365a9SGeert Uytterhoeven FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \ 457077365a9SGeert Uytterhoeven FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 \ 458077365a9SGeert Uytterhoeven FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \ 459077365a9SGeert Uytterhoeven FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \ 460077365a9SGeert Uytterhoeven FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \ 461077365a9SGeert Uytterhoeven FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \ 462077365a9SGeert Uytterhoeven \ 463077365a9SGeert Uytterhoeven FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \ 464077365a9SGeert Uytterhoeven FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \ 465077365a9SGeert Uytterhoeven FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \ 466077365a9SGeert Uytterhoeven FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \ 467077365a9SGeert Uytterhoeven FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \ 468077365a9SGeert Uytterhoeven FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \ 469077365a9SGeert Uytterhoeven FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \ 470077365a9SGeert Uytterhoeven FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \ 471077365a9SGeert Uytterhoeven \ 472077365a9SGeert Uytterhoeven FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \ 473077365a9SGeert Uytterhoeven FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \ 474077365a9SGeert Uytterhoeven FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \ 475077365a9SGeert Uytterhoeven FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \ 476077365a9SGeert Uytterhoeven FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \ 477077365a9SGeert Uytterhoeven FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \ 478077365a9SGeert Uytterhoeven FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \ 479077365a9SGeert Uytterhoeven FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \ 480077365a9SGeert Uytterhoeven \ 481077365a9SGeert Uytterhoeven FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 FM(IP18_3_0) IP18_3_0 \ 482077365a9SGeert Uytterhoeven FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 FM(IP18_7_4) IP18_7_4 \ 483077365a9SGeert Uytterhoeven FM(IP16_11_8) IP16_11_8 FM(IP17_11_8) IP17_11_8 \ 484077365a9SGeert Uytterhoeven FM(IP16_15_12) IP16_15_12 FM(IP17_15_12) IP17_15_12 \ 485077365a9SGeert Uytterhoeven FM(IP16_19_16) IP16_19_16 FM(IP17_19_16) IP17_19_16 \ 486077365a9SGeert Uytterhoeven FM(IP16_23_20) IP16_23_20 FM(IP17_23_20) IP17_23_20 \ 487077365a9SGeert Uytterhoeven FM(IP16_27_24) IP16_27_24 FM(IP17_27_24) IP17_27_24 \ 488077365a9SGeert Uytterhoeven FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28 489077365a9SGeert Uytterhoeven 490077365a9SGeert Uytterhoeven /* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ 491077365a9SGeert Uytterhoeven #define MOD_SEL0_31_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3) FM(SEL_MSIOF3_4) F_(0, 0) F_(0, 0) F_(0, 0) 492077365a9SGeert Uytterhoeven #define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3) 493077365a9SGeert Uytterhoeven #define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0) 494077365a9SGeert Uytterhoeven #define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1) 495077365a9SGeert Uytterhoeven #define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1) 496077365a9SGeert Uytterhoeven #define MOD_SEL0_21 FM(SEL_I2C2_0) FM(SEL_I2C2_1) 497077365a9SGeert Uytterhoeven #define MOD_SEL0_20 FM(SEL_I2C1_0) FM(SEL_I2C1_1) 498077365a9SGeert Uytterhoeven #define MOD_SEL0_19 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1) 499077365a9SGeert Uytterhoeven #define MOD_SEL0_18_17 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3) 500077365a9SGeert Uytterhoeven #define MOD_SEL0_16 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1) 501077365a9SGeert Uytterhoeven #define MOD_SEL0_14_13 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) FM(SEL_HSCIF2_2) F_(0, 0) 502077365a9SGeert Uytterhoeven #define MOD_SEL0_12 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1) 503077365a9SGeert Uytterhoeven #define MOD_SEL0_11 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1) 504077365a9SGeert Uytterhoeven #define MOD_SEL0_10 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1) 505077365a9SGeert Uytterhoeven #define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0) 506077365a9SGeert Uytterhoeven #define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0) 507077365a9SGeert Uytterhoeven #define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1) 508077365a9SGeert Uytterhoeven #define MOD_SEL0_4_3 FM(SEL_ADGA_0) FM(SEL_ADGA_1) FM(SEL_ADGA_2) FM(SEL_ADGA_3) 509077365a9SGeert Uytterhoeven 510077365a9SGeert Uytterhoeven /* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ 511077365a9SGeert Uytterhoeven #define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3) 512077365a9SGeert Uytterhoeven #define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0) 513077365a9SGeert Uytterhoeven #define MOD_SEL1_26 FM(SEL_TIMER_TMU1_0) FM(SEL_TIMER_TMU1_1) 514077365a9SGeert Uytterhoeven #define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3) 515077365a9SGeert Uytterhoeven #define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0) 516077365a9SGeert Uytterhoeven #define MOD_SEL1_20 FM(SEL_SSI1_0) FM(SEL_SSI1_1) 517077365a9SGeert Uytterhoeven #define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1) 518077365a9SGeert Uytterhoeven #define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3) 519077365a9SGeert Uytterhoeven #define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1) 520077365a9SGeert Uytterhoeven #define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0) 521077365a9SGeert Uytterhoeven #define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1) 522077365a9SGeert Uytterhoeven #define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1) 523077365a9SGeert Uytterhoeven #define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1) 524077365a9SGeert Uytterhoeven #define MOD_SEL1_10 FM(SEL_SCIF_0) FM(SEL_SCIF_1) 525077365a9SGeert Uytterhoeven #define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1) 526077365a9SGeert Uytterhoeven #define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1) 527077365a9SGeert Uytterhoeven #define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1) 528077365a9SGeert Uytterhoeven #define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1) 529077365a9SGeert Uytterhoeven #define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1) 530077365a9SGeert Uytterhoeven #define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1) 531077365a9SGeert Uytterhoeven #define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1) 532077365a9SGeert Uytterhoeven #define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1) 533077365a9SGeert Uytterhoeven 534077365a9SGeert Uytterhoeven /* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ 535077365a9SGeert Uytterhoeven #define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1) 536077365a9SGeert Uytterhoeven #define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1) 537077365a9SGeert Uytterhoeven #define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1) 538077365a9SGeert Uytterhoeven #define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3) 539077365a9SGeert Uytterhoeven #define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1) 540077365a9SGeert Uytterhoeven #define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 541077365a9SGeert Uytterhoeven #define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1) 542077365a9SGeert Uytterhoeven #define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1) 543077365a9SGeert Uytterhoeven #define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1) 544077365a9SGeert Uytterhoeven #define MOD_SEL2_18 FM(SEL_ADGB_0) FM(SEL_ADGB_1) 545077365a9SGeert Uytterhoeven #define MOD_SEL2_17 FM(SEL_ADGC_0) FM(SEL_ADGC_1) 546077365a9SGeert Uytterhoeven #define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1) 547077365a9SGeert Uytterhoeven 548077365a9SGeert Uytterhoeven #define PINMUX_MOD_SELS \ 549077365a9SGeert Uytterhoeven \ 550077365a9SGeert Uytterhoeven MOD_SEL0_31_30_29 MOD_SEL1_31_30 MOD_SEL2_31 \ 551077365a9SGeert Uytterhoeven MOD_SEL2_30 \ 552077365a9SGeert Uytterhoeven MOD_SEL1_29_28_27 MOD_SEL2_29 \ 553077365a9SGeert Uytterhoeven MOD_SEL0_28_27 MOD_SEL2_28_27 \ 554077365a9SGeert Uytterhoeven MOD_SEL0_26_25_24 MOD_SEL1_26 MOD_SEL2_26 \ 555077365a9SGeert Uytterhoeven MOD_SEL1_25_24 MOD_SEL2_25_24_23 \ 556077365a9SGeert Uytterhoeven MOD_SEL0_23 MOD_SEL1_23_22_21 \ 557077365a9SGeert Uytterhoeven MOD_SEL0_22 \ 558077365a9SGeert Uytterhoeven MOD_SEL0_21 MOD_SEL2_21 \ 559077365a9SGeert Uytterhoeven MOD_SEL0_20 MOD_SEL1_20 MOD_SEL2_20 \ 560077365a9SGeert Uytterhoeven MOD_SEL0_19 MOD_SEL1_19 MOD_SEL2_19 \ 561077365a9SGeert Uytterhoeven MOD_SEL0_18_17 MOD_SEL1_18_17 MOD_SEL2_18 \ 562077365a9SGeert Uytterhoeven MOD_SEL2_17 \ 563077365a9SGeert Uytterhoeven MOD_SEL0_16 MOD_SEL1_16 \ 564077365a9SGeert Uytterhoeven MOD_SEL1_15_14 \ 565077365a9SGeert Uytterhoeven MOD_SEL0_14_13 \ 566077365a9SGeert Uytterhoeven MOD_SEL1_13 \ 567077365a9SGeert Uytterhoeven MOD_SEL0_12 MOD_SEL1_12 \ 568077365a9SGeert Uytterhoeven MOD_SEL0_11 MOD_SEL1_11 \ 569077365a9SGeert Uytterhoeven MOD_SEL0_10 MOD_SEL1_10 \ 570077365a9SGeert Uytterhoeven MOD_SEL0_9_8 MOD_SEL1_9 \ 571077365a9SGeert Uytterhoeven MOD_SEL0_7_6 \ 572077365a9SGeert Uytterhoeven MOD_SEL1_6 \ 573077365a9SGeert Uytterhoeven MOD_SEL0_5 MOD_SEL1_5 \ 574077365a9SGeert Uytterhoeven MOD_SEL0_4_3 MOD_SEL1_4 \ 575077365a9SGeert Uytterhoeven MOD_SEL1_3 \ 576077365a9SGeert Uytterhoeven MOD_SEL1_2 \ 577077365a9SGeert Uytterhoeven MOD_SEL1_1 \ 578077365a9SGeert Uytterhoeven MOD_SEL1_0 MOD_SEL2_0 579077365a9SGeert Uytterhoeven 580077365a9SGeert Uytterhoeven /* 581077365a9SGeert Uytterhoeven * These pins are not able to be muxed but have other properties 582077365a9SGeert Uytterhoeven * that can be set, such as drive-strength or pull-up/pull-down enable. 583077365a9SGeert Uytterhoeven */ 584077365a9SGeert Uytterhoeven #define PINMUX_STATIC \ 585077365a9SGeert Uytterhoeven FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \ 586077365a9SGeert Uytterhoeven FM(QSPI0_IO2) FM(QSPI0_IO3) \ 587077365a9SGeert Uytterhoeven FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \ 588077365a9SGeert Uytterhoeven FM(QSPI1_IO2) FM(QSPI1_IO3) \ 589077365a9SGeert Uytterhoeven FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \ 590077365a9SGeert Uytterhoeven FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \ 591077365a9SGeert Uytterhoeven FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \ 592077365a9SGeert Uytterhoeven FM(AVB_TXCREFCLK) FM(AVB_MDIO) \ 593077365a9SGeert Uytterhoeven FM(PRESETOUT) \ 594077365a9SGeert Uytterhoeven FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) FM(DU_DOTCLKIN3) \ 595077365a9SGeert Uytterhoeven FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR) 596077365a9SGeert Uytterhoeven 597077365a9SGeert Uytterhoeven #define PINMUX_PHYS \ 598077365a9SGeert Uytterhoeven FM(SCL0) FM(SDA0) FM(SCL3) FM(SDA3) FM(SCL5) FM(SDA5) 599077365a9SGeert Uytterhoeven 600077365a9SGeert Uytterhoeven enum { 601077365a9SGeert Uytterhoeven PINMUX_RESERVED = 0, 602077365a9SGeert Uytterhoeven 603077365a9SGeert Uytterhoeven PINMUX_DATA_BEGIN, 604077365a9SGeert Uytterhoeven GP_ALL(DATA), 605077365a9SGeert Uytterhoeven PINMUX_DATA_END, 606077365a9SGeert Uytterhoeven 607077365a9SGeert Uytterhoeven #define F_(x, y) 608077365a9SGeert Uytterhoeven #define FM(x) FN_##x, 609077365a9SGeert Uytterhoeven PINMUX_FUNCTION_BEGIN, 610077365a9SGeert Uytterhoeven GP_ALL(FN), 611077365a9SGeert Uytterhoeven PINMUX_GPSR 612077365a9SGeert Uytterhoeven PINMUX_IPSR 613077365a9SGeert Uytterhoeven PINMUX_MOD_SELS 614077365a9SGeert Uytterhoeven PINMUX_FUNCTION_END, 615077365a9SGeert Uytterhoeven #undef F_ 616077365a9SGeert Uytterhoeven #undef FM 617077365a9SGeert Uytterhoeven 618077365a9SGeert Uytterhoeven #define F_(x, y) 619077365a9SGeert Uytterhoeven #define FM(x) x##_MARK, 620077365a9SGeert Uytterhoeven PINMUX_MARK_BEGIN, 621077365a9SGeert Uytterhoeven PINMUX_GPSR 622077365a9SGeert Uytterhoeven PINMUX_IPSR 623077365a9SGeert Uytterhoeven PINMUX_MOD_SELS 624077365a9SGeert Uytterhoeven PINMUX_STATIC 625077365a9SGeert Uytterhoeven PINMUX_PHYS 626077365a9SGeert Uytterhoeven PINMUX_MARK_END, 627077365a9SGeert Uytterhoeven #undef F_ 628077365a9SGeert Uytterhoeven #undef FM 629077365a9SGeert Uytterhoeven }; 630077365a9SGeert Uytterhoeven 631077365a9SGeert Uytterhoeven static const u16 pinmux_data[] = { 632077365a9SGeert Uytterhoeven PINMUX_DATA_GP_ALL(), 633077365a9SGeert Uytterhoeven 634077365a9SGeert Uytterhoeven PINMUX_SINGLE(AVS1), 635077365a9SGeert Uytterhoeven PINMUX_SINGLE(AVS2), 636077365a9SGeert Uytterhoeven PINMUX_SINGLE(CLKOUT), 637077365a9SGeert Uytterhoeven PINMUX_SINGLE(GP7_02), 638077365a9SGeert Uytterhoeven PINMUX_SINGLE(GP7_03), 639077365a9SGeert Uytterhoeven PINMUX_SINGLE(MSIOF0_RXD), 640077365a9SGeert Uytterhoeven PINMUX_SINGLE(MSIOF0_SCK), 641077365a9SGeert Uytterhoeven PINMUX_SINGLE(MSIOF0_TXD), 642077365a9SGeert Uytterhoeven PINMUX_SINGLE(SSI_SCK5), 643077365a9SGeert Uytterhoeven PINMUX_SINGLE(SSI_SDATA5), 644077365a9SGeert Uytterhoeven PINMUX_SINGLE(SSI_WS5), 645077365a9SGeert Uytterhoeven 646077365a9SGeert Uytterhoeven /* IPSR0 */ 647077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP0_3_0, AVB_MDC), 648077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2), 649077365a9SGeert Uytterhoeven 650077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP0_7_4, AVB_MAGIC), 651077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP0_7_4, MSIOF2_SS1_C, SEL_MSIOF2_2), 652077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP0_7_4, SCK4_A, SEL_SCIF4_0), 653077365a9SGeert Uytterhoeven 654077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP0_11_8, AVB_PHY_INT), 655077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP0_11_8, MSIOF2_SYNC_C, SEL_MSIOF2_2), 656077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP0_11_8, RX4_A, SEL_SCIF4_0), 657077365a9SGeert Uytterhoeven 658077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP0_15_12, AVB_LINK), 659077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2), 660077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0), 661077365a9SGeert Uytterhoeven 662077365a9SGeert Uytterhoeven PINMUX_IPSR_PHYS_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, I2C_SEL_5_0, SEL_ETHERAVB_0), 663077365a9SGeert Uytterhoeven PINMUX_IPSR_PHYS_MSEL(IP0_19_16, MSIOF2_RXD_C, I2C_SEL_5_0, SEL_MSIOF2_2), 664077365a9SGeert Uytterhoeven PINMUX_IPSR_PHYS_MSEL(IP0_19_16, CTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0), 665077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP0_19_16, FSCLKST2_N_A, I2C_SEL_5_0), 666077365a9SGeert Uytterhoeven PINMUX_IPSR_PHYS(IP0_19_16, SCL5, I2C_SEL_5_1), 667077365a9SGeert Uytterhoeven 668077365a9SGeert Uytterhoeven PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, I2C_SEL_5_0, SEL_ETHERAVB_0), 669077365a9SGeert Uytterhoeven PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C, I2C_SEL_5_0, SEL_MSIOF2_2), 670077365a9SGeert Uytterhoeven PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0), 671077365a9SGeert Uytterhoeven PINMUX_IPSR_PHYS(IP0_23_20, SDA5, I2C_SEL_5_1), 672077365a9SGeert Uytterhoeven 673077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP0_27_24, IRQ0), 674077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP0_27_24, QPOLB), 675077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP0_27_24, DU_CDE), 676077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1), 677077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1), 678077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_B, SEL_CANFD0_1), 679077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP0_27_24, MSIOF3_SS2_E, SEL_MSIOF3_4), 680077365a9SGeert Uytterhoeven 681077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP0_31_28, IRQ1), 682077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP0_31_28, QPOLA), 683077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP), 684077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1), 685077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1), 686077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1), 687077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_SS1_E, SEL_MSIOF3_4), 688077365a9SGeert Uytterhoeven 689077365a9SGeert Uytterhoeven /* IPSR1 */ 690077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP1_3_0, IRQ2), 691077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP1_3_0, QCPV_QDE), 692077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE), 693077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1), 694077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1), 695077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_SYNC_E, SEL_MSIOF3_4), 696077365a9SGeert Uytterhoeven 697077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP1_7_4, IRQ3), 698077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE), 699077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1), 700077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1), 701077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1), 702077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP1_7_4, MSIOF3_SCK_E, SEL_MSIOF3_4), 703077365a9SGeert Uytterhoeven 704077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP1_11_8, IRQ4), 705077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS), 706077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC), 707077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1), 708077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1), 709077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP1_11_8, MSIOF3_RXD_E, SEL_MSIOF3_4), 710077365a9SGeert Uytterhoeven 711077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP1_15_12, IRQ5), 712077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE), 713077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC), 714077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1), 715077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1), 716077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP1_15_12, FSCLKST2_N_B), 717077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP1_15_12, MSIOF3_TXD_E, SEL_MSIOF3_4), 718077365a9SGeert Uytterhoeven 719077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP1_19_16, PWM0), 720077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS), 721077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1), 722077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1), 723077365a9SGeert Uytterhoeven 724077365a9SGeert Uytterhoeven PINMUX_IPSR_PHYS_MSEL(IP1_23_20, PWM1_A, I2C_SEL_3_0, SEL_PWM1_0), 725077365a9SGeert Uytterhoeven PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3), 726077365a9SGeert Uytterhoeven PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1), 727077365a9SGeert Uytterhoeven PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1), 728077365a9SGeert Uytterhoeven PINMUX_IPSR_PHYS(IP1_23_20, SCL3, I2C_SEL_3_1), 729077365a9SGeert Uytterhoeven 730077365a9SGeert Uytterhoeven PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0), 731077365a9SGeert Uytterhoeven PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D, I2C_SEL_3_0, SEL_HSCIF3_3), 732077365a9SGeert Uytterhoeven PINMUX_IPSR_PHYS_MSEL(IP1_27_24, IETX_B, I2C_SEL_3_0, SEL_IEBUS_1), 733077365a9SGeert Uytterhoeven PINMUX_IPSR_PHYS(IP1_27_24, SDA3, I2C_SEL_3_1), 734077365a9SGeert Uytterhoeven 735077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP1_31_28, A0), 736077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16), 737077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SYNC_B, SEL_MSIOF3_1), 738077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP1_31_28, VI4_DATA8), 739077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP1_31_28, DU_DB0), 740077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP1_31_28, PWM3_A, SEL_PWM3_0), 741077365a9SGeert Uytterhoeven 742077365a9SGeert Uytterhoeven /* IPSR2 */ 743077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP2_3_0, A1), 744077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT17), 745077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_TXD_B, SEL_MSIOF3_1), 746077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP2_3_0, VI4_DATA9), 747077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP2_3_0, DU_DB1), 748077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP2_3_0, PWM4_A, SEL_PWM4_0), 749077365a9SGeert Uytterhoeven 750077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP2_7_4, A2), 751077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT18), 752077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP2_7_4, MSIOF3_SCK_B, SEL_MSIOF3_1), 753077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP2_7_4, VI4_DATA10), 754077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP2_7_4, DU_DB2), 755077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP2_7_4, PWM5_A, SEL_PWM5_0), 756077365a9SGeert Uytterhoeven 757077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP2_11_8, A3), 758077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT19), 759077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP2_11_8, MSIOF3_RXD_B, SEL_MSIOF3_1), 760077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP2_11_8, VI4_DATA11), 761077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP2_11_8, DU_DB3), 762077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP2_11_8, PWM6_A, SEL_PWM6_0), 763077365a9SGeert Uytterhoeven 764077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP2_15_12, A4), 765077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT20), 766077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP2_15_12, MSIOF3_SS1_B, SEL_MSIOF3_1), 767077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP2_15_12, VI4_DATA12), 768077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP2_15_12, VI5_DATA12), 769077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP2_15_12, DU_DB4), 770077365a9SGeert Uytterhoeven 771077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP2_19_16, A5), 772077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT21), 773077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP2_19_16, MSIOF3_SS2_B, SEL_MSIOF3_1), 774077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP2_19_16, SCK4_B, SEL_SCIF4_1), 775077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP2_19_16, VI4_DATA13), 776077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP2_19_16, VI5_DATA13), 777077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP2_19_16, DU_DB5), 778077365a9SGeert Uytterhoeven 779077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP2_23_20, A6), 780077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT22), 781077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_SS1_A, SEL_MSIOF2_0), 782077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP2_23_20, RX4_B, SEL_SCIF4_1), 783077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP2_23_20, VI4_DATA14), 784077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP2_23_20, VI5_DATA14), 785077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP2_23_20, DU_DB6), 786077365a9SGeert Uytterhoeven 787077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP2_27_24, A7), 788077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT23), 789077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SS2_A, SEL_MSIOF2_0), 790077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP2_27_24, TX4_B, SEL_SCIF4_1), 791077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP2_27_24, VI4_DATA15), 792077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP2_27_24, VI5_DATA15), 793077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP2_27_24, DU_DB7), 794077365a9SGeert Uytterhoeven 795077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP2_31_28, A8), 796077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP2_31_28, RX3_B, SEL_SCIF3_1), 797077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0), 798077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP2_31_28, HRX4_B, SEL_HSCIF4_1), 799077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP2_31_28, SDA6_A, SEL_I2C6_0), 800077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP2_31_28, AVB_AVTP_MATCH_B, SEL_ETHERAVB_1), 801077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP2_31_28, PWM1_B, SEL_PWM1_1), 802077365a9SGeert Uytterhoeven 803077365a9SGeert Uytterhoeven /* IPSR3 */ 804077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP3_3_0, A9), 805077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0), 806077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1), 807077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP3_3_0, VI5_VSYNC_N), 808077365a9SGeert Uytterhoeven 809077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP3_7_4, A10), 810077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0), 811077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_B, SEL_SCIF4_1), 812077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N), 813077365a9SGeert Uytterhoeven 814077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP3_11_8, A11), 815077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP3_11_8, TX3_B, SEL_SCIF3_1), 816077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP3_11_8, MSIOF2_TXD_A, SEL_MSIOF2_0), 817077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP3_11_8, HTX4_B, SEL_HSCIF4_1), 818077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP3_11_8, HSCK4), 819077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP3_11_8, VI5_FIELD), 820077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP3_11_8, SCL6_A, SEL_I2C6_0), 821077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP3_11_8, AVB_AVTP_CAPTURE_B, SEL_ETHERAVB_1), 822077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP3_11_8, PWM2_B, SEL_PWM2_1), 823077365a9SGeert Uytterhoeven 824077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP3_15_12, A12), 825077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT12), 826077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SCK_C, SEL_MSIOF3_2), 827077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP3_15_12, HRX4_A, SEL_HSCIF4_0), 828077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP3_15_12, VI5_DATA8), 829077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4), 830077365a9SGeert Uytterhoeven 831077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP3_19_16, A13), 832077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT13), 833077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SYNC_C, SEL_MSIOF3_2), 834077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP3_19_16, HTX4_A, SEL_HSCIF4_0), 835077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP3_19_16, VI5_DATA9), 836077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP3_19_16, DU_DG5), 837077365a9SGeert Uytterhoeven 838077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP3_23_20, A14), 839077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT14), 840077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_C, SEL_MSIOF3_2), 841077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP3_23_20, HCTS4_N), 842077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP3_23_20, VI5_DATA10), 843077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP3_23_20, DU_DG6), 844077365a9SGeert Uytterhoeven 845077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP3_27_24, A15), 846077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT15), 847077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP3_27_24, MSIOF3_TXD_C, SEL_MSIOF3_2), 848077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP3_27_24, HRTS4_N), 849077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP3_27_24, VI5_DATA11), 850077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP3_27_24, DU_DG7), 851077365a9SGeert Uytterhoeven 852077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP3_31_28, A16), 853077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP3_31_28, LCDOUT8), 854077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP3_31_28, VI4_FIELD), 855077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP3_31_28, DU_DG0), 856077365a9SGeert Uytterhoeven 857077365a9SGeert Uytterhoeven /* IPSR4 */ 858077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP4_3_0, A17), 859077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT9), 860077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP4_3_0, VI4_VSYNC_N), 861077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP4_3_0, DU_DG1), 862077365a9SGeert Uytterhoeven 863077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP4_7_4, A18), 864077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT10), 865077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP4_7_4, VI4_HSYNC_N), 866077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP4_7_4, DU_DG2), 867077365a9SGeert Uytterhoeven 868077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP4_11_8, A19), 869077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP4_11_8, LCDOUT11), 870077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP4_11_8, VI4_CLKENB), 871077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP4_11_8, DU_DG3), 872077365a9SGeert Uytterhoeven 873077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP4_15_12, CS0_N), 874077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB), 875077365a9SGeert Uytterhoeven 876077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP4_19_16, CS1_N), 877077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK), 878077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1), 879077365a9SGeert Uytterhoeven 880077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP4_23_20, BS_N), 881077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP4_23_20, QSTVA_QVS), 882077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP4_23_20, MSIOF3_SCK_D, SEL_MSIOF3_3), 883077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP4_23_20, SCK3), 884077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP4_23_20, HSCK3), 885077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP4_23_20, CAN1_TX), 886077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP4_23_20, CANFD1_TX), 887077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP4_23_20, IETX_A, SEL_IEBUS_0), 888077365a9SGeert Uytterhoeven 889077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP4_27_24, RD_N), 890077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP4_27_24, MSIOF3_SYNC_D, SEL_MSIOF3_3), 891077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP4_27_24, RX3_A, SEL_SCIF3_0), 892077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP4_27_24, HRX3_A, SEL_HSCIF3_0), 893077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP4_27_24, CAN0_TX_A, SEL_RCAN0_0), 894077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP4_27_24, CANFD0_TX_A, SEL_CANFD0_0), 895077365a9SGeert Uytterhoeven 896077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP4_31_28, RD_WR_N), 897077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP4_31_28, MSIOF3_RXD_D, SEL_MSIOF3_3), 898077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP4_31_28, TX3_A, SEL_SCIF3_0), 899077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP4_31_28, HTX3_A, SEL_HSCIF3_0), 900077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP4_31_28, CAN0_RX_A, SEL_RCAN0_0), 901077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP4_31_28, CANFD0_RX_A, SEL_CANFD0_0), 902077365a9SGeert Uytterhoeven 903077365a9SGeert Uytterhoeven /* IPSR5 */ 904077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP5_3_0, WE0_N), 905077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP5_3_0, MSIOF3_TXD_D, SEL_MSIOF3_3), 906077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP5_3_0, CTS3_N), 907077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP5_3_0, HCTS3_N), 908077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP5_3_0, SCL6_B, SEL_I2C6_1), 909077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP5_3_0, CAN_CLK), 910077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP5_3_0, IECLK_A, SEL_IEBUS_0), 911077365a9SGeert Uytterhoeven 912077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP5_7_4, WE1_N), 913077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3), 914077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N), 915077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N), 916077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1), 917077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX), 918077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP5_7_4, CANFD1_RX), 919077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP5_7_4, IERX_A, SEL_IEBUS_0), 920077365a9SGeert Uytterhoeven 921077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP5_11_8, EX_WAIT0_A, SEL_LBSC_0), 922077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP5_11_8, QCLK), 923077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP5_11_8, VI4_CLK), 924077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP5_11_8, DU_DOTCLKOUT0), 925077365a9SGeert Uytterhoeven 926077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP5_15_12, D0), 927077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP5_15_12, MSIOF2_SS1_B, SEL_MSIOF2_1), 928077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP5_15_12, MSIOF3_SCK_A, SEL_MSIOF3_0), 929077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA16), 930077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP5_15_12, VI5_DATA0), 931077365a9SGeert Uytterhoeven 932077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP5_19_16, D1), 933077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP5_19_16, MSIOF2_SS2_B, SEL_MSIOF2_1), 934077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP5_19_16, MSIOF3_SYNC_A, SEL_MSIOF3_0), 935077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA17), 936077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP5_19_16, VI5_DATA1), 937077365a9SGeert Uytterhoeven 938077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP5_23_20, D2), 939077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_RXD_A, SEL_MSIOF3_0), 940077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA18), 941077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP5_23_20, VI5_DATA2), 942077365a9SGeert Uytterhoeven 943077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP5_27_24, D3), 944077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0), 945077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19), 946077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3), 947077365a9SGeert Uytterhoeven 948077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP5_31_28, D4), 949077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP5_31_28, MSIOF2_SCK_B, SEL_MSIOF2_1), 950077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA20), 951077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP5_31_28, VI5_DATA4), 952077365a9SGeert Uytterhoeven 953077365a9SGeert Uytterhoeven /* IPSR6 */ 954077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP6_3_0, D5), 955077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP6_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1), 956077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA21), 957077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP6_3_0, VI5_DATA5), 958077365a9SGeert Uytterhoeven 959077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP6_7_4, D6), 960077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP6_7_4, MSIOF2_RXD_B, SEL_MSIOF2_1), 961077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA22), 962077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP6_7_4, VI5_DATA6), 963077365a9SGeert Uytterhoeven 964077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP6_11_8, D7), 965077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP6_11_8, MSIOF2_TXD_B, SEL_MSIOF2_1), 966077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA23), 967077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP6_11_8, VI5_DATA7), 968077365a9SGeert Uytterhoeven 969077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP6_15_12, D8), 970077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT0), 971077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP6_15_12, MSIOF2_SCK_D, SEL_MSIOF2_3), 972077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP6_15_12, SCK4_C, SEL_SCIF4_2), 973077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA0_A, SEL_VIN4_0), 974077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP6_15_12, DU_DR0), 975077365a9SGeert Uytterhoeven 976077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP6_19_16, D9), 977077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP6_19_16, LCDOUT1), 978077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP6_19_16, MSIOF2_SYNC_D, SEL_MSIOF2_3), 979077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP6_19_16, VI4_DATA1_A, SEL_VIN4_0), 980077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP6_19_16, DU_DR1), 981077365a9SGeert Uytterhoeven 982077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP6_23_20, D10), 983077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT2), 984077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_RXD_D, SEL_MSIOF2_3), 985077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP6_23_20, HRX3_B, SEL_HSCIF3_1), 986077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP6_23_20, VI4_DATA2_A, SEL_VIN4_0), 987077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP6_23_20, CTS4_N_C, SEL_SCIF4_2), 988077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP6_23_20, DU_DR2), 989077365a9SGeert Uytterhoeven 990077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP6_27_24, D11), 991077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT3), 992077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3), 993077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1), 994077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0), 995077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_C, SEL_SCIF4_2), 996077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3), 997077365a9SGeert Uytterhoeven 998077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP6_31_28, D12), 999077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT4), 1000077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3), 1001077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2), 1002077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0), 1003077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP6_31_28, DU_DR4), 1004077365a9SGeert Uytterhoeven 1005077365a9SGeert Uytterhoeven /* IPSR7 */ 1006077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP7_3_0, D13), 1007077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT5), 1008077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3), 1009077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP7_3_0, TX4_C, SEL_SCIF4_2), 1010077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0), 1011077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP7_3_0, DU_DR5), 1012077365a9SGeert Uytterhoeven 1013077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP7_7_4, D14), 1014077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP7_7_4, LCDOUT6), 1015077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP7_7_4, MSIOF3_SS1_A, SEL_MSIOF3_0), 1016077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP7_7_4, HRX3_C, SEL_HSCIF3_2), 1017077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP7_7_4, VI4_DATA6_A, SEL_VIN4_0), 1018077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP7_7_4, DU_DR6), 1019077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP7_7_4, SCL6_C, SEL_I2C6_2), 1020077365a9SGeert Uytterhoeven 1021077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP7_11_8, D15), 1022077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP7_11_8, LCDOUT7), 1023077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SS2_A, SEL_MSIOF3_0), 1024077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP7_11_8, HTX3_C, SEL_HSCIF3_2), 1025077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP7_11_8, VI4_DATA7_A, SEL_VIN4_0), 1026077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7), 1027077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2), 1028077365a9SGeert Uytterhoeven 1029077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK), 1030077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4), 1031077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1), 1032077365a9SGeert Uytterhoeven 1033077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP7_23_20, SD0_CMD), 1034077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP7_23_20, MSIOF1_SYNC_E, SEL_MSIOF1_4), 1035077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP7_23_20, STP_IVCXO27_0_B, SEL_SSP1_0_1), 1036077365a9SGeert Uytterhoeven 1037077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP7_27_24, SD0_DAT0), 1038077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP7_27_24, MSIOF1_RXD_E, SEL_MSIOF1_4), 1039077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP7_27_24, TS_SCK0_B, SEL_TSIF0_1), 1040077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP7_27_24, STP_ISCLK_0_B, SEL_SSP1_0_1), 1041077365a9SGeert Uytterhoeven 1042077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP7_31_28, SD0_DAT1), 1043077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP7_31_28, MSIOF1_TXD_E, SEL_MSIOF1_4), 1044077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP7_31_28, TS_SPSYNC0_B, SEL_TSIF0_1), 1045077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP7_31_28, STP_ISSYNC_0_B, SEL_SSP1_0_1), 1046077365a9SGeert Uytterhoeven 1047077365a9SGeert Uytterhoeven /* IPSR8 */ 1048077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP8_3_0, SD0_DAT2), 1049077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP8_3_0, MSIOF1_SS1_E, SEL_MSIOF1_4), 1050077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP8_3_0, TS_SDAT0_B, SEL_TSIF0_1), 1051077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP8_3_0, STP_ISD_0_B, SEL_SSP1_0_1), 1052077365a9SGeert Uytterhoeven 1053077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT3), 1054077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP8_7_4, MSIOF1_SS2_E, SEL_MSIOF1_4), 1055077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP8_7_4, TS_SDEN0_B, SEL_TSIF0_1), 1056077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP8_7_4, STP_ISEN_0_B, SEL_SSP1_0_1), 1057077365a9SGeert Uytterhoeven 1058077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP8_11_8, SD1_CLK), 1059077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP8_11_8, MSIOF1_SCK_G, SEL_MSIOF1_6), 1060077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP8_11_8, SIM0_CLK_A, SEL_SIMCARD_0), 1061077365a9SGeert Uytterhoeven 1062077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD), 1063077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6), 1064077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP8_15_12, NFCE_N_B), 1065077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0), 1066077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1), 1067077365a9SGeert Uytterhoeven 1068077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0), 1069077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4), 1070077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6), 1071077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP8_19_16, NFWP_N_B), 1072077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1), 1073077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1), 1074077365a9SGeert Uytterhoeven 1075077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1), 1076077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5), 1077077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6), 1078077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP8_23_20, NFDATA14_B), 1079077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1), 1080077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1), 1081077365a9SGeert Uytterhoeven 1082077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2), 1083077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6), 1084077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6), 1085077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP8_27_24, NFDATA15_B), 1086077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1), 1087077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1), 1088077365a9SGeert Uytterhoeven 1089077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3), 1090077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7), 1091077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6), 1092077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP8_31_28, NFRB_N_B), 1093077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1), 1094077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1), 1095077365a9SGeert Uytterhoeven 1096077365a9SGeert Uytterhoeven /* IPSR9 */ 1097077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP9_3_0, SD2_CLK), 1098077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP9_3_0, NFDATA8), 1099077365a9SGeert Uytterhoeven 1100077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP9_7_4, SD2_CMD), 1101077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP9_7_4, NFDATA9), 1102077365a9SGeert Uytterhoeven 1103077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP9_11_8, SD2_DAT0), 1104077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP9_11_8, NFDATA10), 1105077365a9SGeert Uytterhoeven 1106077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP9_15_12, SD2_DAT1), 1107077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP9_15_12, NFDATA11), 1108077365a9SGeert Uytterhoeven 1109077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP9_19_16, SD2_DAT2), 1110077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP9_19_16, NFDATA12), 1111077365a9SGeert Uytterhoeven 1112077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP9_23_20, SD2_DAT3), 1113077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP9_23_20, NFDATA13), 1114077365a9SGeert Uytterhoeven 1115077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP9_27_24, SD2_DS), 1116077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP9_27_24, NFALE), 1117077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP9_27_24, SATA_DEVSLP_B), 1118077365a9SGeert Uytterhoeven 1119077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP9_31_28, SD3_CLK), 1120077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP9_31_28, NFWE_N), 1121077365a9SGeert Uytterhoeven 1122077365a9SGeert Uytterhoeven /* IPSR10 */ 1123077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP10_3_0, SD3_CMD), 1124077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP10_3_0, NFRE_N), 1125077365a9SGeert Uytterhoeven 1126077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT0), 1127077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP10_7_4, NFDATA0), 1128077365a9SGeert Uytterhoeven 1129077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP10_11_8, SD3_DAT1), 1130077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP10_11_8, NFDATA1), 1131077365a9SGeert Uytterhoeven 1132077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP10_15_12, SD3_DAT2), 1133077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP10_15_12, NFDATA2), 1134077365a9SGeert Uytterhoeven 1135077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP10_19_16, SD3_DAT3), 1136077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP10_19_16, NFDATA3), 1137077365a9SGeert Uytterhoeven 1138077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP10_23_20, SD3_DAT4), 1139077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP10_23_20, SD2_CD_A, SEL_SDHI2_0), 1140077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP10_23_20, NFDATA4), 1141077365a9SGeert Uytterhoeven 1142077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP10_27_24, SD3_DAT5), 1143077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP10_27_24, SD2_WP_A, SEL_SDHI2_0), 1144077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP10_27_24, NFDATA5), 1145077365a9SGeert Uytterhoeven 1146077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP10_31_28, SD3_DAT6), 1147077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP10_31_28, SD3_CD), 1148077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP10_31_28, NFDATA6), 1149077365a9SGeert Uytterhoeven 1150077365a9SGeert Uytterhoeven /* IPSR11 */ 1151077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP11_3_0, SD3_DAT7), 1152077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP11_3_0, SD3_WP), 1153077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP11_3_0, NFDATA7), 1154077365a9SGeert Uytterhoeven 1155077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP11_7_4, SD3_DS), 1156077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP11_7_4, NFCLE), 1157077365a9SGeert Uytterhoeven 1158077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD), 1159077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1), 1160077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0), 1161077365a9SGeert Uytterhoeven 1162077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP), 1163077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1), 1164077365a9SGeert Uytterhoeven 1165077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP11_19_16, SD1_CD, I2C_SEL_0_0), 1166077365a9SGeert Uytterhoeven PINMUX_IPSR_PHYS_MSEL(IP11_19_16, SIM0_CLK_B, I2C_SEL_0_0, SEL_SIMCARD_1), 1167077365a9SGeert Uytterhoeven PINMUX_IPSR_PHYS(IP11_19_16, SCL0, I2C_SEL_0_1), 1168077365a9SGeert Uytterhoeven 1169077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP11_23_20, SD1_WP, I2C_SEL_0_0), 1170077365a9SGeert Uytterhoeven PINMUX_IPSR_PHYS_MSEL(IP11_23_20, SIM0_D_B, I2C_SEL_0_0, SEL_SIMCARD_1), 1171077365a9SGeert Uytterhoeven PINMUX_IPSR_PHYS(IP11_23_20, SDA0, I2C_SEL_0_1), 1172077365a9SGeert Uytterhoeven 1173077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP11_27_24, SCK0), 1174077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1), 1175077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1), 1176077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADGC_1), 1177077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0), 1178077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1), 1179077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2), 1180077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP11_27_24, RIF0_CLK_B, SEL_DRIF0_1), 1181077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP11_27_24, ADICHS2), 1182077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP11_27_24, SCK5_B, SEL_SCIF5_1), 1183077365a9SGeert Uytterhoeven 1184077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP11_31_28, RX0), 1185077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP11_31_28, HRX1_B, SEL_HSCIF1_1), 1186077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP11_31_28, TS_SCK0_C, SEL_TSIF0_2), 1187077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP11_31_28, STP_ISCLK_0_C, SEL_SSP1_0_2), 1188077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP11_31_28, RIF0_D0_B, SEL_DRIF0_1), 1189077365a9SGeert Uytterhoeven 1190077365a9SGeert Uytterhoeven /* IPSR12 */ 1191077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP12_3_0, TX0), 1192077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP12_3_0, HTX1_B, SEL_HSCIF1_1), 1193077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP12_3_0, TS_SPSYNC0_C, SEL_TSIF0_2), 1194077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP12_3_0, STP_ISSYNC_0_C, SEL_SSP1_0_2), 1195077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP12_3_0, RIF0_D1_B, SEL_DRIF0_1), 1196077365a9SGeert Uytterhoeven 1197077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP12_7_4, CTS0_N), 1198077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP12_7_4, HCTS1_N_B, SEL_HSCIF1_1), 1199077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP12_7_4, MSIOF1_SYNC_B, SEL_MSIOF1_1), 1200077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP12_7_4, TS_SPSYNC1_C, SEL_TSIF1_2), 1201077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP12_7_4, STP_ISSYNC_1_C, SEL_SSP1_1_2), 1202077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP12_7_4, RIF1_SYNC_B, SEL_DRIF1_1), 1203077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP12_7_4, AUDIO_CLKOUT_C), 1204077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP12_7_4, ADICS_SAMP), 1205077365a9SGeert Uytterhoeven 1206077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N), 1207077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1), 1208077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1), 1209077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADGA_1), 1210077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0), 1211077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2), 1212077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1), 1213077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP12_11_8, ADICHS1), 1214077365a9SGeert Uytterhoeven 1215077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP12_15_12, RX1_A, SEL_SCIF1_0), 1216077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP12_15_12, HRX1_A, SEL_HSCIF1_0), 1217077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP12_15_12, TS_SDAT0_C, SEL_TSIF0_2), 1218077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP12_15_12, STP_ISD_0_C, SEL_SSP1_0_2), 1219077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP12_15_12, RIF1_CLK_C, SEL_DRIF1_2), 1220077365a9SGeert Uytterhoeven 1221077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP12_19_16, TX1_A, SEL_SCIF1_0), 1222077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP12_19_16, HTX1_A, SEL_HSCIF1_0), 1223077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP12_19_16, TS_SDEN0_C, SEL_TSIF0_2), 1224077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP12_19_16, STP_ISEN_0_C, SEL_SSP1_0_2), 1225077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP12_19_16, RIF1_D0_C, SEL_DRIF1_2), 1226077365a9SGeert Uytterhoeven 1227077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP12_23_20, CTS1_N), 1228077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP12_23_20, HCTS1_N_A, SEL_HSCIF1_0), 1229077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP12_23_20, MSIOF1_RXD_B, SEL_MSIOF1_1), 1230077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP12_23_20, TS_SDEN1_C, SEL_TSIF1_2), 1231077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP12_23_20, STP_ISEN_1_C, SEL_SSP1_1_2), 1232077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP12_23_20, RIF1_D0_B, SEL_DRIF1_1), 1233077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP12_23_20, ADIDATA), 1234077365a9SGeert Uytterhoeven 1235077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP12_27_24, RTS1_N), 1236077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP12_27_24, HRTS1_N_A, SEL_HSCIF1_0), 1237077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1), 1238077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP12_27_24, TS_SDAT1_C, SEL_TSIF1_2), 1239077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP12_27_24, STP_ISD_1_C, SEL_SSP1_1_2), 1240077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP12_27_24, RIF1_D1_B, SEL_DRIF1_1), 1241077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP12_27_24, ADICHS0), 1242077365a9SGeert Uytterhoeven 1243077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP12_31_28, SCK2), 1244077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP12_31_28, SCIF_CLK_B, SEL_SCIF_1), 1245077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP12_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1), 1246077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP12_31_28, TS_SCK1_C, SEL_TSIF1_2), 1247077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP12_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2), 1248077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP12_31_28, RIF1_CLK_B, SEL_DRIF1_1), 1249077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP12_31_28, ADICLK), 1250077365a9SGeert Uytterhoeven 1251077365a9SGeert Uytterhoeven /* IPSR13 */ 1252077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP13_3_0, TX2_A, SEL_SCIF2_0), 1253077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP13_3_0, SD2_CD_B, SEL_SDHI2_1), 1254077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP13_3_0, SCL1_A, SEL_I2C1_0), 1255077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP13_3_0, FMCLK_A, SEL_FM_0), 1256077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP13_3_0, RIF1_D1_C, SEL_DRIF1_2), 1257077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP13_3_0, FSO_CFE_0_N), 1258077365a9SGeert Uytterhoeven 1259077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP13_7_4, RX2_A, SEL_SCIF2_0), 1260077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP13_7_4, SD2_WP_B, SEL_SDHI2_1), 1261077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP13_7_4, SDA1_A, SEL_I2C1_0), 1262077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP13_7_4, FMIN_A, SEL_FM_0), 1263077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP13_7_4, RIF1_SYNC_C, SEL_DRIF1_2), 1264077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP13_7_4, FSO_CFE_1_N), 1265077365a9SGeert Uytterhoeven 1266077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP13_11_8, HSCK0), 1267077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3), 1268077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADGB_0), 1269077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI1_1), 1270077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3), 1271077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3), 1272077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP13_11_8, RIF0_CLK_C, SEL_DRIF0_2), 1273077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP13_11_8, RX5_B, SEL_SCIF5_1), 1274077365a9SGeert Uytterhoeven 1275077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP13_15_12, HRX0), 1276077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3), 1277077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA2_B, SEL_SSI2_1), 1278077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP13_15_12, TS_SDEN0_D, SEL_TSIF0_3), 1279077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP13_15_12, STP_ISEN_0_D, SEL_SSP1_0_3), 1280077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_C, SEL_DRIF0_2), 1281077365a9SGeert Uytterhoeven 1282077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP13_19_16, HTX0), 1283077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3), 1284077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP13_19_16, SSI_SDATA9_B, SEL_SSI9_1), 1285077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP13_19_16, TS_SDAT0_D, SEL_TSIF0_3), 1286077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP13_19_16, STP_ISD_0_D, SEL_SSP1_0_3), 1287077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_C, SEL_DRIF0_2), 1288077365a9SGeert Uytterhoeven 1289077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP13_23_20, HCTS0_N), 1290077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP13_23_20, RX2_B, SEL_SCIF2_1), 1291077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3), 1292077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK9_A, SEL_SSI9_0), 1293077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP13_23_20, TS_SPSYNC0_D, SEL_TSIF0_3), 1294077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP13_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3), 1295077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_C, SEL_DRIF0_2), 1296077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP13_23_20, AUDIO_CLKOUT1_A), 1297077365a9SGeert Uytterhoeven 1298077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP13_27_24, HRTS0_N), 1299077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP13_27_24, TX2_B, SEL_SCIF2_1), 1300077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3), 1301077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP13_27_24, SSI_WS9_A, SEL_SSI9_0), 1302077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP13_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3), 1303077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP13_27_24, BPFCLK_A, SEL_FM_0), 1304077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP13_27_24, AUDIO_CLKOUT2_A), 1305077365a9SGeert Uytterhoeven 1306077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP13_31_28, MSIOF0_SYNC), 1307077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP13_31_28, AUDIO_CLKOUT_A), 1308077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP13_31_28, TX5_B, SEL_SCIF5_1), 1309077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP13_31_28, BPFCLK_D, SEL_FM_3), 1310077365a9SGeert Uytterhoeven 1311077365a9SGeert Uytterhoeven /* IPSR14 */ 1312077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1), 1313077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0), 1314077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP14_3_0, NFWP_N_A), 1315077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADGA_2), 1316077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0), 1317077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2), 1318077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A), 1319077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP14_3_0, TCLK1_B, SEL_TIMER_TMU1_1), 1320077365a9SGeert Uytterhoeven 1321077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2), 1322077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0), 1323077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3), 1324077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADGC_0), 1325077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI2_0), 1326077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3), 1327077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D), 1328077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP14_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1), 1329077365a9SGeert Uytterhoeven 1330077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP14_11_8, MLB_CLK), 1331077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SCK_F, SEL_MSIOF1_5), 1332077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP14_11_8, SCL1_B, SEL_I2C1_1), 1333077365a9SGeert Uytterhoeven 1334077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP14_15_12, MLB_SIG), 1335077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP14_15_12, RX1_B, SEL_SCIF1_1), 1336077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP14_15_12, MSIOF1_SYNC_F, SEL_MSIOF1_5), 1337077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP14_15_12, SDA1_B, SEL_I2C1_1), 1338077365a9SGeert Uytterhoeven 1339077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP14_19_16, MLB_DAT), 1340077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP14_19_16, TX1_B, SEL_SCIF1_1), 1341077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP14_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5), 1342077365a9SGeert Uytterhoeven 1343077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP14_23_20, SSI_SCK01239), 1344077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP14_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5), 1345077365a9SGeert Uytterhoeven 1346077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP14_27_24, SSI_WS01239), 1347077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP14_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5), 1348077365a9SGeert Uytterhoeven 1349077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP14_31_28, SSI_SDATA0), 1350077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5), 1351077365a9SGeert Uytterhoeven 1352077365a9SGeert Uytterhoeven /* IPSR15 */ 1353077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP15_3_0, SSI_SDATA1_A, SEL_SSI1_0), 1354077365a9SGeert Uytterhoeven 1355077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP15_7_4, SSI_SDATA2_A, SEL_SSI2_0), 1356077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP15_7_4, SSI_SCK1_B, SEL_SSI1_1), 1357077365a9SGeert Uytterhoeven 1358077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK349), 1359077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0), 1360077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP15_11_8, STP_OPWM_0_A, SEL_SSP1_0_0), 1361077365a9SGeert Uytterhoeven 1362077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS349), 1363077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP15_15_12, HCTS2_N_A, SEL_HSCIF2_0), 1364077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0), 1365077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP15_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0), 1366077365a9SGeert Uytterhoeven 1367077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA3), 1368077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0), 1369077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_TXD_A, SEL_MSIOF1_0), 1370077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP15_19_16, TS_SCK0_A, SEL_TSIF0_0), 1371077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP15_19_16, STP_ISCLK_0_A, SEL_SSP1_0_0), 1372077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP15_19_16, RIF0_D1_A, SEL_DRIF0_0), 1373077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP15_19_16, RIF2_D0_A, SEL_DRIF2_0), 1374077365a9SGeert Uytterhoeven 1375077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP15_23_20, SSI_SCK4), 1376077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP15_23_20, HRX2_A, SEL_HSCIF2_0), 1377077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_SCK_A, SEL_MSIOF1_0), 1378077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP15_23_20, TS_SDAT0_A, SEL_TSIF0_0), 1379077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP15_23_20, STP_ISD_0_A, SEL_SSP1_0_0), 1380077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP15_23_20, RIF0_CLK_A, SEL_DRIF0_0), 1381077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP15_23_20, RIF2_CLK_A, SEL_DRIF2_0), 1382077365a9SGeert Uytterhoeven 1383077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP15_27_24, SSI_WS4), 1384077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP15_27_24, HTX2_A, SEL_HSCIF2_0), 1385077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP15_27_24, MSIOF1_SYNC_A, SEL_MSIOF1_0), 1386077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP15_27_24, TS_SDEN0_A, SEL_TSIF0_0), 1387077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP15_27_24, STP_ISEN_0_A, SEL_SSP1_0_0), 1388077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP15_27_24, RIF0_SYNC_A, SEL_DRIF0_0), 1389077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP15_27_24, RIF2_SYNC_A, SEL_DRIF2_0), 1390077365a9SGeert Uytterhoeven 1391077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP15_31_28, SSI_SDATA4), 1392077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP15_31_28, HSCK2_A, SEL_HSCIF2_0), 1393077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP15_31_28, MSIOF1_RXD_A, SEL_MSIOF1_0), 1394077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP15_31_28, TS_SPSYNC0_A, SEL_TSIF0_0), 1395077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP15_31_28, STP_ISSYNC_0_A, SEL_SSP1_0_0), 1396077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP15_31_28, RIF0_D0_A, SEL_DRIF0_0), 1397077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP15_31_28, RIF2_D1_A, SEL_DRIF2_0), 1398077365a9SGeert Uytterhoeven 1399077365a9SGeert Uytterhoeven /* IPSR16 */ 1400077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP16_3_0, SSI_SCK6), 1401077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP16_3_0, USB2_PWEN), 1402077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP16_3_0, SIM0_RST_D, SEL_SIMCARD_3), 1403077365a9SGeert Uytterhoeven 1404077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP16_7_4, SSI_WS6), 1405077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP16_7_4, USB2_OVC), 1406077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP16_7_4, SIM0_D_D, SEL_SIMCARD_3), 1407077365a9SGeert Uytterhoeven 1408077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP16_11_8, SSI_SDATA6), 1409077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP16_11_8, SIM0_CLK_D, SEL_SIMCARD_3), 1410077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP16_11_8, SATA_DEVSLP_A), 1411077365a9SGeert Uytterhoeven 1412077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP16_15_12, SSI_SCK78), 1413077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP16_15_12, HRX2_B, SEL_HSCIF2_1), 1414077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP16_15_12, MSIOF1_SCK_C, SEL_MSIOF1_2), 1415077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP16_15_12, TS_SCK1_A, SEL_TSIF1_0), 1416077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP16_15_12, STP_ISCLK_1_A, SEL_SSP1_1_0), 1417077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP16_15_12, RIF1_CLK_A, SEL_DRIF1_0), 1418077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP16_15_12, RIF3_CLK_A, SEL_DRIF3_0), 1419077365a9SGeert Uytterhoeven 1420077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP16_19_16, SSI_WS78), 1421077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP16_19_16, HTX2_B, SEL_HSCIF2_1), 1422077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP16_19_16, MSIOF1_SYNC_C, SEL_MSIOF1_2), 1423077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP16_19_16, TS_SDAT1_A, SEL_TSIF1_0), 1424077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP16_19_16, STP_ISD_1_A, SEL_SSP1_1_0), 1425077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP16_19_16, RIF1_SYNC_A, SEL_DRIF1_0), 1426077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP16_19_16, RIF3_SYNC_A, SEL_DRIF3_0), 1427077365a9SGeert Uytterhoeven 1428077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP16_23_20, SSI_SDATA7), 1429077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP16_23_20, HCTS2_N_B, SEL_HSCIF2_1), 1430077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP16_23_20, MSIOF1_RXD_C, SEL_MSIOF1_2), 1431077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP16_23_20, TS_SDEN1_A, SEL_TSIF1_0), 1432077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP16_23_20, STP_ISEN_1_A, SEL_SSP1_1_0), 1433077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP16_23_20, RIF1_D0_A, SEL_DRIF1_0), 1434077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP16_23_20, RIF3_D0_A, SEL_DRIF3_0), 1435077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP16_23_20, TCLK2_A, SEL_TIMER_TMU2_0), 1436077365a9SGeert Uytterhoeven 1437077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP16_27_24, SSI_SDATA8), 1438077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP16_27_24, HRTS2_N_B, SEL_HSCIF2_1), 1439077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP16_27_24, MSIOF1_TXD_C, SEL_MSIOF1_2), 1440077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP16_27_24, TS_SPSYNC1_A, SEL_TSIF1_0), 1441077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP16_27_24, STP_ISSYNC_1_A, SEL_SSP1_1_0), 1442077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP16_27_24, RIF1_D1_A, SEL_DRIF1_0), 1443077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D1_A, SEL_DRIF3_0), 1444077365a9SGeert Uytterhoeven 1445077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA9_A, SEL_SSI9_0), 1446077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP16_31_28, HSCK2_B, SEL_HSCIF2_1), 1447077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP16_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2), 1448077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP16_31_28, HSCK1_A, SEL_HSCIF1_0), 1449077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI1_1), 1450077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP16_31_28, SCK1), 1451077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0), 1452077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0), 1453077365a9SGeert Uytterhoeven 1454077365a9SGeert Uytterhoeven /* IPSR17 */ 1455077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADGA_0), 1456077365a9SGeert Uytterhoeven 1457077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADGB_1), 1458077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0), 1459077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3), 1460077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0), 1461077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP17_7_4, TCLK1_A, SEL_TIMER_TMU1_0), 1462077365a9SGeert Uytterhoeven 1463077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP17_11_8, USB0_PWEN), 1464077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP17_11_8, SIM0_RST_C, SEL_SIMCARD_2), 1465077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP17_11_8, TS_SCK1_D, SEL_TSIF1_3), 1466077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP17_11_8, STP_ISCLK_1_D, SEL_SSP1_1_3), 1467077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP17_11_8, BPFCLK_B, SEL_FM_1), 1468077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP17_11_8, RIF3_CLK_B, SEL_DRIF3_1), 1469077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP17_11_8, HSCK2_C, SEL_HSCIF2_2), 1470077365a9SGeert Uytterhoeven 1471077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP17_15_12, USB0_OVC), 1472077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP17_15_12, SIM0_D_C, SEL_SIMCARD_2), 1473077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP17_15_12, TS_SDAT1_D, SEL_TSIF1_3), 1474077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP17_15_12, STP_ISD_1_D, SEL_SSP1_1_3), 1475077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP17_15_12, RIF3_SYNC_B, SEL_DRIF3_1), 1476077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP17_15_12, HRX2_C, SEL_HSCIF2_2), 1477077365a9SGeert Uytterhoeven 1478077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP17_19_16, USB1_PWEN), 1479077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP17_19_16, SIM0_CLK_C, SEL_SIMCARD_2), 1480077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP17_19_16, SSI_SCK1_A, SEL_SSI1_0), 1481077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP17_19_16, TS_SCK0_E, SEL_TSIF0_4), 1482077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP17_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4), 1483077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP17_19_16, FMCLK_B, SEL_FM_1), 1484077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP17_19_16, RIF2_CLK_B, SEL_DRIF2_1), 1485077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP17_19_16, SPEEDIN_A, SEL_SPEED_PULSE_0), 1486077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP17_19_16, HTX2_C, SEL_HSCIF2_2), 1487077365a9SGeert Uytterhoeven 1488077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP17_23_20, USB1_OVC), 1489077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP17_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2), 1490077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP17_23_20, SSI_WS1_A, SEL_SSI1_0), 1491077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP17_23_20, TS_SDAT0_E, SEL_TSIF0_4), 1492077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP17_23_20, STP_ISD_0_E, SEL_SSP1_0_4), 1493077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP17_23_20, FMIN_B, SEL_FM_1), 1494077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP17_23_20, RIF2_SYNC_B, SEL_DRIF2_1), 1495077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP17_23_20, REMOCON_B, SEL_REMOCON_1), 1496077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP17_23_20, HCTS2_N_C, SEL_HSCIF2_2), 1497077365a9SGeert Uytterhoeven 1498077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP17_27_24, USB30_PWEN), 1499077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_B), 1500077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI2_1), 1501077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP17_27_24, TS_SDEN1_D, SEL_TSIF1_3), 1502077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP17_27_24, STP_ISEN_1_D, SEL_SSP1_1_3), 1503077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP17_27_24, STP_OPWM_0_E, SEL_SSP1_0_4), 1504077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP17_27_24, RIF3_D0_B, SEL_DRIF3_1), 1505077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP17_27_24, TCLK2_B, SEL_TIMER_TMU2_1), 1506077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP17_27_24, TPU0TO0), 1507077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP17_27_24, BPFCLK_C, SEL_FM_2), 1508077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP17_27_24, HRTS2_N_C, SEL_HSCIF2_2), 1509077365a9SGeert Uytterhoeven 1510077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP17_31_28, USB30_OVC), 1511077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP17_31_28, AUDIO_CLKOUT1_B), 1512077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP17_31_28, SSI_WS2_B, SEL_SSI2_1), 1513077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP17_31_28, TS_SPSYNC1_D, SEL_TSIF1_3), 1514077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP17_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3), 1515077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP17_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4), 1516077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP17_31_28, RIF3_D1_B, SEL_DRIF3_1), 1517077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP17_31_28, FSO_TOE_N), 1518077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP17_31_28, TPU0TO1), 1519077365a9SGeert Uytterhoeven 1520077365a9SGeert Uytterhoeven /* IPSR18 */ 1521077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP18_3_0, USB2_CH3_PWEN), 1522077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP18_3_0, AUDIO_CLKOUT2_B), 1523077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP18_3_0, SSI_SCK9_B, SEL_SSI9_1), 1524077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP18_3_0, TS_SDEN0_E, SEL_TSIF0_4), 1525077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP18_3_0, STP_ISEN_0_E, SEL_SSP1_0_4), 1526077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP18_3_0, RIF2_D0_B, SEL_DRIF2_1), 1527077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP18_3_0, TPU0TO2), 1528077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_C, SEL_FM_2), 1529077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_D, SEL_FM_3), 1530077365a9SGeert Uytterhoeven 1531077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP18_7_4, USB2_CH3_OVC), 1532077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP18_7_4, AUDIO_CLKOUT3_B), 1533077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP18_7_4, SSI_WS9_B, SEL_SSI9_1), 1534077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP18_7_4, TS_SPSYNC0_E, SEL_TSIF0_4), 1535077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP18_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4), 1536077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP18_7_4, RIF2_D1_B, SEL_DRIF2_1), 1537077365a9SGeert Uytterhoeven PINMUX_IPSR_GPSR(IP18_7_4, TPU0TO3), 1538077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP18_7_4, FMIN_C, SEL_FM_2), 1539077365a9SGeert Uytterhoeven PINMUX_IPSR_MSEL(IP18_7_4, FMIN_D, SEL_FM_3), 1540077365a9SGeert Uytterhoeven 1541077365a9SGeert Uytterhoeven /* 1542077365a9SGeert Uytterhoeven * Static pins can not be muxed between different functions but 1543077365a9SGeert Uytterhoeven * still need mark entries in the pinmux list. Add each static 1544077365a9SGeert Uytterhoeven * pin to the list without an associated function. The sh-pfc 1545077365a9SGeert Uytterhoeven * core will do the right thing and skip trying to mux the pin 1546077365a9SGeert Uytterhoeven * while still applying configuration to it. 1547077365a9SGeert Uytterhoeven */ 1548077365a9SGeert Uytterhoeven #define FM(x) PINMUX_DATA(x##_MARK, 0), 1549077365a9SGeert Uytterhoeven PINMUX_STATIC 1550077365a9SGeert Uytterhoeven #undef FM 1551077365a9SGeert Uytterhoeven }; 1552077365a9SGeert Uytterhoeven 1553077365a9SGeert Uytterhoeven /* 1554077365a9SGeert Uytterhoeven * Pins not associated with a GPIO port. 1555077365a9SGeert Uytterhoeven */ 1556077365a9SGeert Uytterhoeven enum { 1557077365a9SGeert Uytterhoeven GP_ASSIGN_LAST(), 1558077365a9SGeert Uytterhoeven NOGP_ALL(), 1559077365a9SGeert Uytterhoeven }; 1560077365a9SGeert Uytterhoeven 1561077365a9SGeert Uytterhoeven static const struct sh_pfc_pin pinmux_pins[] = { 1562077365a9SGeert Uytterhoeven PINMUX_GPIO_GP_ALL(), 1563077365a9SGeert Uytterhoeven PINMUX_NOGP_ALL(), 1564077365a9SGeert Uytterhoeven }; 1565077365a9SGeert Uytterhoeven 1566077365a9SGeert Uytterhoeven /* - AUDIO CLOCK ------------------------------------------------------------ */ 1567077365a9SGeert Uytterhoeven static const unsigned int audio_clk_a_a_pins[] = { 1568077365a9SGeert Uytterhoeven /* CLK A */ 1569077365a9SGeert Uytterhoeven RCAR_GP_PIN(6, 22), 1570077365a9SGeert Uytterhoeven }; 1571077365a9SGeert Uytterhoeven static const unsigned int audio_clk_a_a_mux[] = { 1572077365a9SGeert Uytterhoeven AUDIO_CLKA_A_MARK, 1573077365a9SGeert Uytterhoeven }; 1574077365a9SGeert Uytterhoeven static const unsigned int audio_clk_a_b_pins[] = { 1575077365a9SGeert Uytterhoeven /* CLK A */ 1576077365a9SGeert Uytterhoeven RCAR_GP_PIN(5, 4), 1577077365a9SGeert Uytterhoeven }; 1578077365a9SGeert Uytterhoeven static const unsigned int audio_clk_a_b_mux[] = { 1579077365a9SGeert Uytterhoeven AUDIO_CLKA_B_MARK, 1580077365a9SGeert Uytterhoeven }; 1581077365a9SGeert Uytterhoeven static const unsigned int audio_clk_a_c_pins[] = { 1582077365a9SGeert Uytterhoeven /* CLK A */ 1583077365a9SGeert Uytterhoeven RCAR_GP_PIN(5, 19), 1584077365a9SGeert Uytterhoeven }; 1585077365a9SGeert Uytterhoeven static const unsigned int audio_clk_a_c_mux[] = { 1586077365a9SGeert Uytterhoeven AUDIO_CLKA_C_MARK, 1587077365a9SGeert Uytterhoeven }; 1588077365a9SGeert Uytterhoeven static const unsigned int audio_clk_b_a_pins[] = { 1589077365a9SGeert Uytterhoeven /* CLK B */ 1590077365a9SGeert Uytterhoeven RCAR_GP_PIN(5, 12), 1591077365a9SGeert Uytterhoeven }; 1592077365a9SGeert Uytterhoeven static const unsigned int audio_clk_b_a_mux[] = { 1593077365a9SGeert Uytterhoeven AUDIO_CLKB_A_MARK, 1594077365a9SGeert Uytterhoeven }; 1595077365a9SGeert Uytterhoeven static const unsigned int audio_clk_b_b_pins[] = { 1596077365a9SGeert Uytterhoeven /* CLK B */ 1597077365a9SGeert Uytterhoeven RCAR_GP_PIN(6, 23), 1598077365a9SGeert Uytterhoeven }; 1599077365a9SGeert Uytterhoeven static const unsigned int audio_clk_b_b_mux[] = { 1600077365a9SGeert Uytterhoeven AUDIO_CLKB_B_MARK, 1601077365a9SGeert Uytterhoeven }; 1602077365a9SGeert Uytterhoeven static const unsigned int audio_clk_c_a_pins[] = { 1603077365a9SGeert Uytterhoeven /* CLK C */ 1604077365a9SGeert Uytterhoeven RCAR_GP_PIN(5, 21), 1605077365a9SGeert Uytterhoeven }; 1606077365a9SGeert Uytterhoeven static const unsigned int audio_clk_c_a_mux[] = { 1607077365a9SGeert Uytterhoeven AUDIO_CLKC_A_MARK, 1608077365a9SGeert Uytterhoeven }; 1609077365a9SGeert Uytterhoeven static const unsigned int audio_clk_c_b_pins[] = { 1610077365a9SGeert Uytterhoeven /* CLK C */ 1611077365a9SGeert Uytterhoeven RCAR_GP_PIN(5, 0), 1612077365a9SGeert Uytterhoeven }; 1613077365a9SGeert Uytterhoeven static const unsigned int audio_clk_c_b_mux[] = { 1614077365a9SGeert Uytterhoeven AUDIO_CLKC_B_MARK, 1615077365a9SGeert Uytterhoeven }; 1616077365a9SGeert Uytterhoeven static const unsigned int audio_clkout_a_pins[] = { 1617077365a9SGeert Uytterhoeven /* CLKOUT */ 1618077365a9SGeert Uytterhoeven RCAR_GP_PIN(5, 18), 1619077365a9SGeert Uytterhoeven }; 1620077365a9SGeert Uytterhoeven static const unsigned int audio_clkout_a_mux[] = { 1621077365a9SGeert Uytterhoeven AUDIO_CLKOUT_A_MARK, 1622077365a9SGeert Uytterhoeven }; 1623077365a9SGeert Uytterhoeven static const unsigned int audio_clkout_b_pins[] = { 1624077365a9SGeert Uytterhoeven /* CLKOUT */ 1625077365a9SGeert Uytterhoeven RCAR_GP_PIN(6, 28), 1626077365a9SGeert Uytterhoeven }; 1627077365a9SGeert Uytterhoeven static const unsigned int audio_clkout_b_mux[] = { 1628077365a9SGeert Uytterhoeven AUDIO_CLKOUT_B_MARK, 1629077365a9SGeert Uytterhoeven }; 1630077365a9SGeert Uytterhoeven static const unsigned int audio_clkout_c_pins[] = { 1631077365a9SGeert Uytterhoeven /* CLKOUT */ 1632077365a9SGeert Uytterhoeven RCAR_GP_PIN(5, 3), 1633077365a9SGeert Uytterhoeven }; 1634077365a9SGeert Uytterhoeven static const unsigned int audio_clkout_c_mux[] = { 1635077365a9SGeert Uytterhoeven AUDIO_CLKOUT_C_MARK, 1636077365a9SGeert Uytterhoeven }; 1637077365a9SGeert Uytterhoeven static const unsigned int audio_clkout_d_pins[] = { 1638077365a9SGeert Uytterhoeven /* CLKOUT */ 1639077365a9SGeert Uytterhoeven RCAR_GP_PIN(5, 21), 1640077365a9SGeert Uytterhoeven }; 1641077365a9SGeert Uytterhoeven static const unsigned int audio_clkout_d_mux[] = { 1642077365a9SGeert Uytterhoeven AUDIO_CLKOUT_D_MARK, 1643077365a9SGeert Uytterhoeven }; 1644077365a9SGeert Uytterhoeven static const unsigned int audio_clkout1_a_pins[] = { 1645077365a9SGeert Uytterhoeven /* CLKOUT1 */ 1646077365a9SGeert Uytterhoeven RCAR_GP_PIN(5, 15), 1647077365a9SGeert Uytterhoeven }; 1648077365a9SGeert Uytterhoeven static const unsigned int audio_clkout1_a_mux[] = { 1649077365a9SGeert Uytterhoeven AUDIO_CLKOUT1_A_MARK, 1650077365a9SGeert Uytterhoeven }; 1651077365a9SGeert Uytterhoeven static const unsigned int audio_clkout1_b_pins[] = { 1652077365a9SGeert Uytterhoeven /* CLKOUT1 */ 1653077365a9SGeert Uytterhoeven RCAR_GP_PIN(6, 29), 1654077365a9SGeert Uytterhoeven }; 1655077365a9SGeert Uytterhoeven static const unsigned int audio_clkout1_b_mux[] = { 1656077365a9SGeert Uytterhoeven AUDIO_CLKOUT1_B_MARK, 1657077365a9SGeert Uytterhoeven }; 1658077365a9SGeert Uytterhoeven static const unsigned int audio_clkout2_a_pins[] = { 1659077365a9SGeert Uytterhoeven /* CLKOUT2 */ 1660077365a9SGeert Uytterhoeven RCAR_GP_PIN(5, 16), 1661077365a9SGeert Uytterhoeven }; 1662077365a9SGeert Uytterhoeven static const unsigned int audio_clkout2_a_mux[] = { 1663077365a9SGeert Uytterhoeven AUDIO_CLKOUT2_A_MARK, 1664077365a9SGeert Uytterhoeven }; 1665077365a9SGeert Uytterhoeven static const unsigned int audio_clkout2_b_pins[] = { 1666077365a9SGeert Uytterhoeven /* CLKOUT2 */ 1667077365a9SGeert Uytterhoeven RCAR_GP_PIN(6, 30), 1668077365a9SGeert Uytterhoeven }; 1669077365a9SGeert Uytterhoeven static const unsigned int audio_clkout2_b_mux[] = { 1670077365a9SGeert Uytterhoeven AUDIO_CLKOUT2_B_MARK, 1671077365a9SGeert Uytterhoeven }; 1672077365a9SGeert Uytterhoeven static const unsigned int audio_clkout3_a_pins[] = { 1673077365a9SGeert Uytterhoeven /* CLKOUT3 */ 1674077365a9SGeert Uytterhoeven RCAR_GP_PIN(5, 19), 1675077365a9SGeert Uytterhoeven }; 1676077365a9SGeert Uytterhoeven static const unsigned int audio_clkout3_a_mux[] = { 1677077365a9SGeert Uytterhoeven AUDIO_CLKOUT3_A_MARK, 1678077365a9SGeert Uytterhoeven }; 1679077365a9SGeert Uytterhoeven static const unsigned int audio_clkout3_b_pins[] = { 1680077365a9SGeert Uytterhoeven /* CLKOUT3 */ 1681077365a9SGeert Uytterhoeven RCAR_GP_PIN(6, 31), 1682077365a9SGeert Uytterhoeven }; 1683077365a9SGeert Uytterhoeven static const unsigned int audio_clkout3_b_mux[] = { 1684077365a9SGeert Uytterhoeven AUDIO_CLKOUT3_B_MARK, 1685077365a9SGeert Uytterhoeven }; 1686077365a9SGeert Uytterhoeven 1687077365a9SGeert Uytterhoeven /* - EtherAVB --------------------------------------------------------------- */ 1688077365a9SGeert Uytterhoeven static const unsigned int avb_link_pins[] = { 1689077365a9SGeert Uytterhoeven /* AVB_LINK */ 1690077365a9SGeert Uytterhoeven RCAR_GP_PIN(2, 12), 1691077365a9SGeert Uytterhoeven }; 1692077365a9SGeert Uytterhoeven static const unsigned int avb_link_mux[] = { 1693077365a9SGeert Uytterhoeven AVB_LINK_MARK, 1694077365a9SGeert Uytterhoeven }; 1695077365a9SGeert Uytterhoeven static const unsigned int avb_magic_pins[] = { 1696077365a9SGeert Uytterhoeven /* AVB_MAGIC_ */ 1697077365a9SGeert Uytterhoeven RCAR_GP_PIN(2, 10), 1698077365a9SGeert Uytterhoeven }; 1699077365a9SGeert Uytterhoeven static const unsigned int avb_magic_mux[] = { 1700077365a9SGeert Uytterhoeven AVB_MAGIC_MARK, 1701077365a9SGeert Uytterhoeven }; 1702077365a9SGeert Uytterhoeven static const unsigned int avb_phy_int_pins[] = { 1703077365a9SGeert Uytterhoeven /* AVB_PHY_INT */ 1704077365a9SGeert Uytterhoeven RCAR_GP_PIN(2, 11), 1705077365a9SGeert Uytterhoeven }; 1706077365a9SGeert Uytterhoeven static const unsigned int avb_phy_int_mux[] = { 1707077365a9SGeert Uytterhoeven AVB_PHY_INT_MARK, 1708077365a9SGeert Uytterhoeven }; 1709077365a9SGeert Uytterhoeven static const unsigned int avb_mdio_pins[] = { 1710077365a9SGeert Uytterhoeven /* AVB_MDC, AVB_MDIO */ 1711077365a9SGeert Uytterhoeven RCAR_GP_PIN(2, 9), PIN_AVB_MDIO, 1712077365a9SGeert Uytterhoeven }; 1713077365a9SGeert Uytterhoeven static const unsigned int avb_mdio_mux[] = { 1714077365a9SGeert Uytterhoeven AVB_MDC_MARK, AVB_MDIO_MARK, 1715077365a9SGeert Uytterhoeven }; 1716077365a9SGeert Uytterhoeven static const unsigned int avb_mii_pins[] = { 1717077365a9SGeert Uytterhoeven /* 1718077365a9SGeert Uytterhoeven * AVB_TX_CTL, AVB_TXC, AVB_TD0, 1719077365a9SGeert Uytterhoeven * AVB_TD1, AVB_TD2, AVB_TD3, 1720077365a9SGeert Uytterhoeven * AVB_RX_CTL, AVB_RXC, AVB_RD0, 1721077365a9SGeert Uytterhoeven * AVB_RD1, AVB_RD2, AVB_RD3, 1722077365a9SGeert Uytterhoeven * AVB_TXCREFCLK 1723077365a9SGeert Uytterhoeven */ 1724077365a9SGeert Uytterhoeven PIN_AVB_TX_CTL, PIN_AVB_TXC, PIN_AVB_TD0, 1725077365a9SGeert Uytterhoeven PIN_AVB_TD1, PIN_AVB_TD2, PIN_AVB_TD3, 1726077365a9SGeert Uytterhoeven PIN_AVB_RX_CTL, PIN_AVB_RXC, PIN_AVB_RD0, 1727077365a9SGeert Uytterhoeven PIN_AVB_RD1, PIN_AVB_RD2, PIN_AVB_RD3, 1728077365a9SGeert Uytterhoeven PIN_AVB_TXCREFCLK, 1729077365a9SGeert Uytterhoeven }; 1730077365a9SGeert Uytterhoeven static const unsigned int avb_mii_mux[] = { 1731077365a9SGeert Uytterhoeven AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK, 1732077365a9SGeert Uytterhoeven AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK, 1733077365a9SGeert Uytterhoeven AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK, 1734077365a9SGeert Uytterhoeven AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK, 1735077365a9SGeert Uytterhoeven AVB_TXCREFCLK_MARK, 1736077365a9SGeert Uytterhoeven }; 1737077365a9SGeert Uytterhoeven static const unsigned int avb_avtp_pps_pins[] = { 1738077365a9SGeert Uytterhoeven /* AVB_AVTP_PPS */ 1739077365a9SGeert Uytterhoeven RCAR_GP_PIN(2, 6), 1740077365a9SGeert Uytterhoeven }; 1741077365a9SGeert Uytterhoeven static const unsigned int avb_avtp_pps_mux[] = { 1742077365a9SGeert Uytterhoeven AVB_AVTP_PPS_MARK, 1743077365a9SGeert Uytterhoeven }; 1744077365a9SGeert Uytterhoeven static const unsigned int avb_avtp_match_a_pins[] = { 1745077365a9SGeert Uytterhoeven /* AVB_AVTP_MATCH_A */ 1746077365a9SGeert Uytterhoeven RCAR_GP_PIN(2, 13), 1747077365a9SGeert Uytterhoeven }; 1748077365a9SGeert Uytterhoeven static const unsigned int avb_avtp_match_a_mux[] = { 1749077365a9SGeert Uytterhoeven AVB_AVTP_MATCH_A_MARK, 1750077365a9SGeert Uytterhoeven }; 1751077365a9SGeert Uytterhoeven static const unsigned int avb_avtp_capture_a_pins[] = { 1752077365a9SGeert Uytterhoeven /* AVB_AVTP_CAPTURE_A */ 1753077365a9SGeert Uytterhoeven RCAR_GP_PIN(2, 14), 1754077365a9SGeert Uytterhoeven }; 1755077365a9SGeert Uytterhoeven static const unsigned int avb_avtp_capture_a_mux[] = { 1756077365a9SGeert Uytterhoeven AVB_AVTP_CAPTURE_A_MARK, 1757077365a9SGeert Uytterhoeven }; 1758077365a9SGeert Uytterhoeven static const unsigned int avb_avtp_match_b_pins[] = { 1759077365a9SGeert Uytterhoeven /* AVB_AVTP_MATCH_B */ 1760077365a9SGeert Uytterhoeven RCAR_GP_PIN(1, 8), 1761077365a9SGeert Uytterhoeven }; 1762077365a9SGeert Uytterhoeven static const unsigned int avb_avtp_match_b_mux[] = { 1763077365a9SGeert Uytterhoeven AVB_AVTP_MATCH_B_MARK, 1764077365a9SGeert Uytterhoeven }; 1765077365a9SGeert Uytterhoeven static const unsigned int avb_avtp_capture_b_pins[] = { 1766077365a9SGeert Uytterhoeven /* AVB_AVTP_CAPTURE_B */ 1767077365a9SGeert Uytterhoeven RCAR_GP_PIN(1, 11), 1768077365a9SGeert Uytterhoeven }; 1769077365a9SGeert Uytterhoeven static const unsigned int avb_avtp_capture_b_mux[] = { 1770077365a9SGeert Uytterhoeven AVB_AVTP_CAPTURE_B_MARK, 1771077365a9SGeert Uytterhoeven }; 1772077365a9SGeert Uytterhoeven 1773077365a9SGeert Uytterhoeven /* - CAN ------------------------------------------------------------------ */ 1774077365a9SGeert Uytterhoeven static const unsigned int can0_data_a_pins[] = { 1775077365a9SGeert Uytterhoeven /* TX, RX */ 1776077365a9SGeert Uytterhoeven RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24), 1777077365a9SGeert Uytterhoeven }; 1778077365a9SGeert Uytterhoeven static const unsigned int can0_data_a_mux[] = { 1779077365a9SGeert Uytterhoeven CAN0_TX_A_MARK, CAN0_RX_A_MARK, 1780077365a9SGeert Uytterhoeven }; 1781077365a9SGeert Uytterhoeven static const unsigned int can0_data_b_pins[] = { 1782077365a9SGeert Uytterhoeven /* TX, RX */ 1783077365a9SGeert Uytterhoeven RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), 1784077365a9SGeert Uytterhoeven }; 1785077365a9SGeert Uytterhoeven static const unsigned int can0_data_b_mux[] = { 1786077365a9SGeert Uytterhoeven CAN0_TX_B_MARK, CAN0_RX_B_MARK, 1787077365a9SGeert Uytterhoeven }; 1788077365a9SGeert Uytterhoeven static const unsigned int can1_data_pins[] = { 1789077365a9SGeert Uytterhoeven /* TX, RX */ 1790077365a9SGeert Uytterhoeven RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26), 1791077365a9SGeert Uytterhoeven }; 1792077365a9SGeert Uytterhoeven static const unsigned int can1_data_mux[] = { 1793077365a9SGeert Uytterhoeven CAN1_TX_MARK, CAN1_RX_MARK, 1794077365a9SGeert Uytterhoeven }; 1795077365a9SGeert Uytterhoeven 1796077365a9SGeert Uytterhoeven /* - CAN Clock -------------------------------------------------------------- */ 1797077365a9SGeert Uytterhoeven static const unsigned int can_clk_pins[] = { 1798077365a9SGeert Uytterhoeven /* CLK */ 1799077365a9SGeert Uytterhoeven RCAR_GP_PIN(1, 25), 1800077365a9SGeert Uytterhoeven }; 1801077365a9SGeert Uytterhoeven static const unsigned int can_clk_mux[] = { 1802077365a9SGeert Uytterhoeven CAN_CLK_MARK, 1803077365a9SGeert Uytterhoeven }; 1804077365a9SGeert Uytterhoeven 1805077365a9SGeert Uytterhoeven /* - CAN FD --------------------------------------------------------------- */ 1806077365a9SGeert Uytterhoeven static const unsigned int canfd0_data_a_pins[] = { 1807077365a9SGeert Uytterhoeven /* TX, RX */ 1808077365a9SGeert Uytterhoeven RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24), 1809077365a9SGeert Uytterhoeven }; 1810077365a9SGeert Uytterhoeven static const unsigned int canfd0_data_a_mux[] = { 1811077365a9SGeert Uytterhoeven CANFD0_TX_A_MARK, CANFD0_RX_A_MARK, 1812077365a9SGeert Uytterhoeven }; 1813077365a9SGeert Uytterhoeven static const unsigned int canfd0_data_b_pins[] = { 1814077365a9SGeert Uytterhoeven /* TX, RX */ 1815077365a9SGeert Uytterhoeven RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), 1816077365a9SGeert Uytterhoeven }; 1817077365a9SGeert Uytterhoeven static const unsigned int canfd0_data_b_mux[] = { 1818077365a9SGeert Uytterhoeven CANFD0_TX_B_MARK, CANFD0_RX_B_MARK, 1819077365a9SGeert Uytterhoeven }; 1820077365a9SGeert Uytterhoeven static const unsigned int canfd1_data_pins[] = { 1821077365a9SGeert Uytterhoeven /* TX, RX */ 1822077365a9SGeert Uytterhoeven RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26), 1823077365a9SGeert Uytterhoeven }; 1824077365a9SGeert Uytterhoeven static const unsigned int canfd1_data_mux[] = { 1825077365a9SGeert Uytterhoeven CANFD1_TX_MARK, CANFD1_RX_MARK, 1826077365a9SGeert Uytterhoeven }; 1827077365a9SGeert Uytterhoeven 1828b8029394SBiju Das #ifdef CONFIG_PINCTRL_PFC_R8A77951 1829077365a9SGeert Uytterhoeven /* - DRIF0 --------------------------------------------------------------- */ 1830077365a9SGeert Uytterhoeven static const unsigned int drif0_ctrl_a_pins[] = { 1831077365a9SGeert Uytterhoeven /* CLK, SYNC */ 1832077365a9SGeert Uytterhoeven RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), 1833077365a9SGeert Uytterhoeven }; 1834077365a9SGeert Uytterhoeven static const unsigned int drif0_ctrl_a_mux[] = { 1835077365a9SGeert Uytterhoeven RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK, 1836077365a9SGeert Uytterhoeven }; 1837077365a9SGeert Uytterhoeven static const unsigned int drif0_data0_a_pins[] = { 1838077365a9SGeert Uytterhoeven /* D0 */ 1839077365a9SGeert Uytterhoeven RCAR_GP_PIN(6, 10), 1840077365a9SGeert Uytterhoeven }; 1841077365a9SGeert Uytterhoeven static const unsigned int drif0_data0_a_mux[] = { 1842077365a9SGeert Uytterhoeven RIF0_D0_A_MARK, 1843077365a9SGeert Uytterhoeven }; 1844077365a9SGeert Uytterhoeven static const unsigned int drif0_data1_a_pins[] = { 1845077365a9SGeert Uytterhoeven /* D1 */ 1846077365a9SGeert Uytterhoeven RCAR_GP_PIN(6, 7), 1847077365a9SGeert Uytterhoeven }; 1848077365a9SGeert Uytterhoeven static const unsigned int drif0_data1_a_mux[] = { 1849077365a9SGeert Uytterhoeven RIF0_D1_A_MARK, 1850077365a9SGeert Uytterhoeven }; 1851077365a9SGeert Uytterhoeven static const unsigned int drif0_ctrl_b_pins[] = { 1852077365a9SGeert Uytterhoeven /* CLK, SYNC */ 1853077365a9SGeert Uytterhoeven RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4), 1854077365a9SGeert Uytterhoeven }; 1855077365a9SGeert Uytterhoeven static const unsigned int drif0_ctrl_b_mux[] = { 1856077365a9SGeert Uytterhoeven RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK, 1857077365a9SGeert Uytterhoeven }; 1858077365a9SGeert Uytterhoeven static const unsigned int drif0_data0_b_pins[] = { 1859077365a9SGeert Uytterhoeven /* D0 */ 1860077365a9SGeert Uytterhoeven RCAR_GP_PIN(5, 1), 1861077365a9SGeert Uytterhoeven }; 1862077365a9SGeert Uytterhoeven static const unsigned int drif0_data0_b_mux[] = { 1863077365a9SGeert Uytterhoeven RIF0_D0_B_MARK, 1864077365a9SGeert Uytterhoeven }; 1865077365a9SGeert Uytterhoeven static const unsigned int drif0_data1_b_pins[] = { 1866077365a9SGeert Uytterhoeven /* D1 */ 1867077365a9SGeert Uytterhoeven RCAR_GP_PIN(5, 2), 1868077365a9SGeert Uytterhoeven }; 1869077365a9SGeert Uytterhoeven static const unsigned int drif0_data1_b_mux[] = { 1870077365a9SGeert Uytterhoeven RIF0_D1_B_MARK, 1871077365a9SGeert Uytterhoeven }; 1872077365a9SGeert Uytterhoeven static const unsigned int drif0_ctrl_c_pins[] = { 1873077365a9SGeert Uytterhoeven /* CLK, SYNC */ 1874077365a9SGeert Uytterhoeven RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15), 1875077365a9SGeert Uytterhoeven }; 1876077365a9SGeert Uytterhoeven static const unsigned int drif0_ctrl_c_mux[] = { 1877077365a9SGeert Uytterhoeven RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK, 1878077365a9SGeert Uytterhoeven }; 1879077365a9SGeert Uytterhoeven static const unsigned int drif0_data0_c_pins[] = { 1880077365a9SGeert Uytterhoeven /* D0 */ 1881077365a9SGeert Uytterhoeven RCAR_GP_PIN(5, 13), 1882077365a9SGeert Uytterhoeven }; 1883077365a9SGeert Uytterhoeven static const unsigned int drif0_data0_c_mux[] = { 1884077365a9SGeert Uytterhoeven RIF0_D0_C_MARK, 1885077365a9SGeert Uytterhoeven }; 1886077365a9SGeert Uytterhoeven static const unsigned int drif0_data1_c_pins[] = { 1887077365a9SGeert Uytterhoeven /* D1 */ 1888077365a9SGeert Uytterhoeven RCAR_GP_PIN(5, 14), 1889077365a9SGeert Uytterhoeven }; 1890077365a9SGeert Uytterhoeven static const unsigned int drif0_data1_c_mux[] = { 1891077365a9SGeert Uytterhoeven RIF0_D1_C_MARK, 1892077365a9SGeert Uytterhoeven }; 1893077365a9SGeert Uytterhoeven /* - DRIF1 --------------------------------------------------------------- */ 1894077365a9SGeert Uytterhoeven static const unsigned int drif1_ctrl_a_pins[] = { 1895077365a9SGeert Uytterhoeven /* CLK, SYNC */ 1896077365a9SGeert Uytterhoeven RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18), 1897077365a9SGeert Uytterhoeven }; 1898077365a9SGeert Uytterhoeven static const unsigned int drif1_ctrl_a_mux[] = { 1899077365a9SGeert Uytterhoeven RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK, 1900077365a9SGeert Uytterhoeven }; 1901077365a9SGeert Uytterhoeven static const unsigned int drif1_data0_a_pins[] = { 1902077365a9SGeert Uytterhoeven /* D0 */ 1903077365a9SGeert Uytterhoeven RCAR_GP_PIN(6, 19), 1904077365a9SGeert Uytterhoeven }; 1905077365a9SGeert Uytterhoeven static const unsigned int drif1_data0_a_mux[] = { 1906077365a9SGeert Uytterhoeven RIF1_D0_A_MARK, 1907077365a9SGeert Uytterhoeven }; 1908077365a9SGeert Uytterhoeven static const unsigned int drif1_data1_a_pins[] = { 1909077365a9SGeert Uytterhoeven /* D1 */ 1910077365a9SGeert Uytterhoeven RCAR_GP_PIN(6, 20), 1911077365a9SGeert Uytterhoeven }; 1912077365a9SGeert Uytterhoeven static const unsigned int drif1_data1_a_mux[] = { 1913077365a9SGeert Uytterhoeven RIF1_D1_A_MARK, 1914077365a9SGeert Uytterhoeven }; 1915077365a9SGeert Uytterhoeven static const unsigned int drif1_ctrl_b_pins[] = { 1916077365a9SGeert Uytterhoeven /* CLK, SYNC */ 1917077365a9SGeert Uytterhoeven RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3), 1918077365a9SGeert Uytterhoeven }; 1919077365a9SGeert Uytterhoeven static const unsigned int drif1_ctrl_b_mux[] = { 1920077365a9SGeert Uytterhoeven RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK, 1921077365a9SGeert Uytterhoeven }; 1922077365a9SGeert Uytterhoeven static const unsigned int drif1_data0_b_pins[] = { 1923077365a9SGeert Uytterhoeven /* D0 */ 1924077365a9SGeert Uytterhoeven RCAR_GP_PIN(5, 7), 1925077365a9SGeert Uytterhoeven }; 1926077365a9SGeert Uytterhoeven static const unsigned int drif1_data0_b_mux[] = { 1927077365a9SGeert Uytterhoeven RIF1_D0_B_MARK, 1928077365a9SGeert Uytterhoeven }; 1929077365a9SGeert Uytterhoeven static const unsigned int drif1_data1_b_pins[] = { 1930077365a9SGeert Uytterhoeven /* D1 */ 1931077365a9SGeert Uytterhoeven RCAR_GP_PIN(5, 8), 1932077365a9SGeert Uytterhoeven }; 1933077365a9SGeert Uytterhoeven static const unsigned int drif1_data1_b_mux[] = { 1934077365a9SGeert Uytterhoeven RIF1_D1_B_MARK, 1935077365a9SGeert Uytterhoeven }; 1936077365a9SGeert Uytterhoeven static const unsigned int drif1_ctrl_c_pins[] = { 1937077365a9SGeert Uytterhoeven /* CLK, SYNC */ 1938077365a9SGeert Uytterhoeven RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11), 1939077365a9SGeert Uytterhoeven }; 1940077365a9SGeert Uytterhoeven static const unsigned int drif1_ctrl_c_mux[] = { 1941077365a9SGeert Uytterhoeven RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK, 1942077365a9SGeert Uytterhoeven }; 1943077365a9SGeert Uytterhoeven static const unsigned int drif1_data0_c_pins[] = { 1944077365a9SGeert Uytterhoeven /* D0 */ 1945077365a9SGeert Uytterhoeven RCAR_GP_PIN(5, 6), 1946077365a9SGeert Uytterhoeven }; 1947077365a9SGeert Uytterhoeven static const unsigned int drif1_data0_c_mux[] = { 1948077365a9SGeert Uytterhoeven RIF1_D0_C_MARK, 1949077365a9SGeert Uytterhoeven }; 1950077365a9SGeert Uytterhoeven static const unsigned int drif1_data1_c_pins[] = { 1951077365a9SGeert Uytterhoeven /* D1 */ 1952077365a9SGeert Uytterhoeven RCAR_GP_PIN(5, 10), 1953077365a9SGeert Uytterhoeven }; 1954077365a9SGeert Uytterhoeven static const unsigned int drif1_data1_c_mux[] = { 1955077365a9SGeert Uytterhoeven RIF1_D1_C_MARK, 1956077365a9SGeert Uytterhoeven }; 1957077365a9SGeert Uytterhoeven /* - DRIF2 --------------------------------------------------------------- */ 1958077365a9SGeert Uytterhoeven static const unsigned int drif2_ctrl_a_pins[] = { 1959077365a9SGeert Uytterhoeven /* CLK, SYNC */ 1960077365a9SGeert Uytterhoeven RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), 1961077365a9SGeert Uytterhoeven }; 1962077365a9SGeert Uytterhoeven static const unsigned int drif2_ctrl_a_mux[] = { 1963077365a9SGeert Uytterhoeven RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK, 1964077365a9SGeert Uytterhoeven }; 1965077365a9SGeert Uytterhoeven static const unsigned int drif2_data0_a_pins[] = { 1966077365a9SGeert Uytterhoeven /* D0 */ 1967077365a9SGeert Uytterhoeven RCAR_GP_PIN(6, 7), 1968077365a9SGeert Uytterhoeven }; 1969077365a9SGeert Uytterhoeven static const unsigned int drif2_data0_a_mux[] = { 1970077365a9SGeert Uytterhoeven RIF2_D0_A_MARK, 1971077365a9SGeert Uytterhoeven }; 1972077365a9SGeert Uytterhoeven static const unsigned int drif2_data1_a_pins[] = { 1973077365a9SGeert Uytterhoeven /* D1 */ 1974077365a9SGeert Uytterhoeven RCAR_GP_PIN(6, 10), 1975077365a9SGeert Uytterhoeven }; 1976077365a9SGeert Uytterhoeven static const unsigned int drif2_data1_a_mux[] = { 1977077365a9SGeert Uytterhoeven RIF2_D1_A_MARK, 1978077365a9SGeert Uytterhoeven }; 1979077365a9SGeert Uytterhoeven static const unsigned int drif2_ctrl_b_pins[] = { 1980077365a9SGeert Uytterhoeven /* CLK, SYNC */ 1981077365a9SGeert Uytterhoeven RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27), 1982077365a9SGeert Uytterhoeven }; 1983077365a9SGeert Uytterhoeven static const unsigned int drif2_ctrl_b_mux[] = { 1984077365a9SGeert Uytterhoeven RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK, 1985077365a9SGeert Uytterhoeven }; 1986077365a9SGeert Uytterhoeven static const unsigned int drif2_data0_b_pins[] = { 1987077365a9SGeert Uytterhoeven /* D0 */ 1988077365a9SGeert Uytterhoeven RCAR_GP_PIN(6, 30), 1989077365a9SGeert Uytterhoeven }; 1990077365a9SGeert Uytterhoeven static const unsigned int drif2_data0_b_mux[] = { 1991077365a9SGeert Uytterhoeven RIF2_D0_B_MARK, 1992077365a9SGeert Uytterhoeven }; 1993077365a9SGeert Uytterhoeven static const unsigned int drif2_data1_b_pins[] = { 1994077365a9SGeert Uytterhoeven /* D1 */ 1995077365a9SGeert Uytterhoeven RCAR_GP_PIN(6, 31), 1996077365a9SGeert Uytterhoeven }; 1997077365a9SGeert Uytterhoeven static const unsigned int drif2_data1_b_mux[] = { 1998077365a9SGeert Uytterhoeven RIF2_D1_B_MARK, 1999077365a9SGeert Uytterhoeven }; 2000077365a9SGeert Uytterhoeven /* - DRIF3 --------------------------------------------------------------- */ 2001077365a9SGeert Uytterhoeven static const unsigned int drif3_ctrl_a_pins[] = { 2002077365a9SGeert Uytterhoeven /* CLK, SYNC */ 2003077365a9SGeert Uytterhoeven RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18), 2004077365a9SGeert Uytterhoeven }; 2005077365a9SGeert Uytterhoeven static const unsigned int drif3_ctrl_a_mux[] = { 2006077365a9SGeert Uytterhoeven RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK, 2007077365a9SGeert Uytterhoeven }; 2008077365a9SGeert Uytterhoeven static const unsigned int drif3_data0_a_pins[] = { 2009077365a9SGeert Uytterhoeven /* D0 */ 2010077365a9SGeert Uytterhoeven RCAR_GP_PIN(6, 19), 2011077365a9SGeert Uytterhoeven }; 2012077365a9SGeert Uytterhoeven static const unsigned int drif3_data0_a_mux[] = { 2013077365a9SGeert Uytterhoeven RIF3_D0_A_MARK, 2014077365a9SGeert Uytterhoeven }; 2015077365a9SGeert Uytterhoeven static const unsigned int drif3_data1_a_pins[] = { 2016077365a9SGeert Uytterhoeven /* D1 */ 2017077365a9SGeert Uytterhoeven RCAR_GP_PIN(6, 20), 2018077365a9SGeert Uytterhoeven }; 2019077365a9SGeert Uytterhoeven static const unsigned int drif3_data1_a_mux[] = { 2020077365a9SGeert Uytterhoeven RIF3_D1_A_MARK, 2021077365a9SGeert Uytterhoeven }; 2022077365a9SGeert Uytterhoeven static const unsigned int drif3_ctrl_b_pins[] = { 2023077365a9SGeert Uytterhoeven /* CLK, SYNC */ 2024077365a9SGeert Uytterhoeven RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25), 2025077365a9SGeert Uytterhoeven }; 2026077365a9SGeert Uytterhoeven static const unsigned int drif3_ctrl_b_mux[] = { 2027077365a9SGeert Uytterhoeven RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK, 2028077365a9SGeert Uytterhoeven }; 2029077365a9SGeert Uytterhoeven static const unsigned int drif3_data0_b_pins[] = { 2030077365a9SGeert Uytterhoeven /* D0 */ 2031077365a9SGeert Uytterhoeven RCAR_GP_PIN(6, 28), 2032077365a9SGeert Uytterhoeven }; 2033077365a9SGeert Uytterhoeven static const unsigned int drif3_data0_b_mux[] = { 2034077365a9SGeert Uytterhoeven RIF3_D0_B_MARK, 2035077365a9SGeert Uytterhoeven }; 2036077365a9SGeert Uytterhoeven static const unsigned int drif3_data1_b_pins[] = { 2037077365a9SGeert Uytterhoeven /* D1 */ 2038077365a9SGeert Uytterhoeven RCAR_GP_PIN(6, 29), 2039077365a9SGeert Uytterhoeven }; 2040077365a9SGeert Uytterhoeven static const unsigned int drif3_data1_b_mux[] = { 2041077365a9SGeert Uytterhoeven RIF3_D1_B_MARK, 2042077365a9SGeert Uytterhoeven }; 2043b8029394SBiju Das #endif /* CONFIG_PINCTRL_PFC_R8A77951 */ 2044077365a9SGeert Uytterhoeven 2045077365a9SGeert Uytterhoeven /* - DU --------------------------------------------------------------------- */ 2046077365a9SGeert Uytterhoeven static const unsigned int du_rgb666_pins[] = { 2047077365a9SGeert Uytterhoeven /* R[7:2], G[7:2], B[7:2] */ 2048077365a9SGeert Uytterhoeven RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), 2049077365a9SGeert Uytterhoeven RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), 2050077365a9SGeert Uytterhoeven RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), 2051077365a9SGeert Uytterhoeven RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18), 2052077365a9SGeert Uytterhoeven RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5), 2053077365a9SGeert Uytterhoeven RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2), 2054077365a9SGeert Uytterhoeven }; 2055077365a9SGeert Uytterhoeven static const unsigned int du_rgb666_mux[] = { 2056077365a9SGeert Uytterhoeven DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK, 2057077365a9SGeert Uytterhoeven DU_DR3_MARK, DU_DR2_MARK, 2058077365a9SGeert Uytterhoeven DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK, 2059077365a9SGeert Uytterhoeven DU_DG3_MARK, DU_DG2_MARK, 2060077365a9SGeert Uytterhoeven DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK, 2061077365a9SGeert Uytterhoeven DU_DB3_MARK, DU_DB2_MARK, 2062077365a9SGeert Uytterhoeven }; 2063077365a9SGeert Uytterhoeven static const unsigned int du_rgb888_pins[] = { 2064077365a9SGeert Uytterhoeven /* R[7:0], G[7:0], B[7:0] */ 2065077365a9SGeert Uytterhoeven RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), 2066077365a9SGeert Uytterhoeven RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), 2067077365a9SGeert Uytterhoeven RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8), 2068077365a9SGeert Uytterhoeven RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), 2069077365a9SGeert Uytterhoeven RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18), 2070077365a9SGeert Uytterhoeven RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16), 2071077365a9SGeert Uytterhoeven RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5), 2072077365a9SGeert Uytterhoeven RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2), 2073077365a9SGeert Uytterhoeven RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0), 2074077365a9SGeert Uytterhoeven }; 2075077365a9SGeert Uytterhoeven static const unsigned int du_rgb888_mux[] = { 2076077365a9SGeert Uytterhoeven DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK, 2077077365a9SGeert Uytterhoeven DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK, 2078077365a9SGeert Uytterhoeven DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK, 2079077365a9SGeert Uytterhoeven DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK, 2080077365a9SGeert Uytterhoeven DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK, 2081077365a9SGeert Uytterhoeven DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK, 2082077365a9SGeert Uytterhoeven }; 2083077365a9SGeert Uytterhoeven static const unsigned int du_clk_out_0_pins[] = { 2084077365a9SGeert Uytterhoeven /* CLKOUT */ 2085077365a9SGeert Uytterhoeven RCAR_GP_PIN(1, 27), 2086077365a9SGeert Uytterhoeven }; 2087077365a9SGeert Uytterhoeven static const unsigned int du_clk_out_0_mux[] = { 2088077365a9SGeert Uytterhoeven DU_DOTCLKOUT0_MARK 2089077365a9SGeert Uytterhoeven }; 2090077365a9SGeert Uytterhoeven static const unsigned int du_clk_out_1_pins[] = { 2091077365a9SGeert Uytterhoeven /* CLKOUT */ 2092077365a9SGeert Uytterhoeven RCAR_GP_PIN(2, 3), 2093077365a9SGeert Uytterhoeven }; 2094077365a9SGeert Uytterhoeven static const unsigned int du_clk_out_1_mux[] = { 2095077365a9SGeert Uytterhoeven DU_DOTCLKOUT1_MARK 2096077365a9SGeert Uytterhoeven }; 2097077365a9SGeert Uytterhoeven static const unsigned int du_sync_pins[] = { 2098077365a9SGeert Uytterhoeven /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */ 2099077365a9SGeert Uytterhoeven RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4), 2100077365a9SGeert Uytterhoeven }; 2101077365a9SGeert Uytterhoeven static const unsigned int du_sync_mux[] = { 2102077365a9SGeert Uytterhoeven DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK 2103077365a9SGeert Uytterhoeven }; 2104077365a9SGeert Uytterhoeven static const unsigned int du_oddf_pins[] = { 2105077365a9SGeert Uytterhoeven /* EXDISP/EXODDF/EXCDE */ 2106077365a9SGeert Uytterhoeven RCAR_GP_PIN(2, 2), 2107077365a9SGeert Uytterhoeven }; 2108077365a9SGeert Uytterhoeven static const unsigned int du_oddf_mux[] = { 2109077365a9SGeert Uytterhoeven DU_EXODDF_DU_ODDF_DISP_CDE_MARK, 2110077365a9SGeert Uytterhoeven }; 2111077365a9SGeert Uytterhoeven static const unsigned int du_cde_pins[] = { 2112077365a9SGeert Uytterhoeven /* CDE */ 2113077365a9SGeert Uytterhoeven RCAR_GP_PIN(2, 0), 2114077365a9SGeert Uytterhoeven }; 2115077365a9SGeert Uytterhoeven static const unsigned int du_cde_mux[] = { 2116077365a9SGeert Uytterhoeven DU_CDE_MARK, 2117077365a9SGeert Uytterhoeven }; 2118077365a9SGeert Uytterhoeven static const unsigned int du_disp_pins[] = { 2119077365a9SGeert Uytterhoeven /* DISP */ 2120077365a9SGeert Uytterhoeven RCAR_GP_PIN(2, 1), 2121077365a9SGeert Uytterhoeven }; 2122077365a9SGeert Uytterhoeven static const unsigned int du_disp_mux[] = { 2123077365a9SGeert Uytterhoeven DU_DISP_MARK, 2124077365a9SGeert Uytterhoeven }; 2125077365a9SGeert Uytterhoeven 2126077365a9SGeert Uytterhoeven /* - HSCIF0 ----------------------------------------------------------------- */ 2127077365a9SGeert Uytterhoeven static const unsigned int hscif0_data_pins[] = { 2128077365a9SGeert Uytterhoeven /* RX, TX */ 2129077365a9SGeert Uytterhoeven RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14), 2130077365a9SGeert Uytterhoeven }; 2131077365a9SGeert Uytterhoeven static const unsigned int hscif0_data_mux[] = { 2132077365a9SGeert Uytterhoeven HRX0_MARK, HTX0_MARK, 2133077365a9SGeert Uytterhoeven }; 2134077365a9SGeert Uytterhoeven static const unsigned int hscif0_clk_pins[] = { 2135077365a9SGeert Uytterhoeven /* SCK */ 2136077365a9SGeert Uytterhoeven RCAR_GP_PIN(5, 12), 2137077365a9SGeert Uytterhoeven }; 2138077365a9SGeert Uytterhoeven static const unsigned int hscif0_clk_mux[] = { 2139077365a9SGeert Uytterhoeven HSCK0_MARK, 2140077365a9SGeert Uytterhoeven }; 2141077365a9SGeert Uytterhoeven static const unsigned int hscif0_ctrl_pins[] = { 2142077365a9SGeert Uytterhoeven /* RTS, CTS */ 2143077365a9SGeert Uytterhoeven RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15), 2144077365a9SGeert Uytterhoeven }; 2145077365a9SGeert Uytterhoeven static const unsigned int hscif0_ctrl_mux[] = { 2146077365a9SGeert Uytterhoeven HRTS0_N_MARK, HCTS0_N_MARK, 2147077365a9SGeert Uytterhoeven }; 2148077365a9SGeert Uytterhoeven /* - HSCIF1 ----------------------------------------------------------------- */ 2149077365a9SGeert Uytterhoeven static const unsigned int hscif1_data_a_pins[] = { 2150077365a9SGeert Uytterhoeven /* RX, TX */ 2151077365a9SGeert Uytterhoeven RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6), 2152077365a9SGeert Uytterhoeven }; 2153077365a9SGeert Uytterhoeven static const unsigned int hscif1_data_a_mux[] = { 2154077365a9SGeert Uytterhoeven HRX1_A_MARK, HTX1_A_MARK, 2155077365a9SGeert Uytterhoeven }; 2156077365a9SGeert Uytterhoeven static const unsigned int hscif1_clk_a_pins[] = { 2157077365a9SGeert Uytterhoeven /* SCK */ 2158077365a9SGeert Uytterhoeven RCAR_GP_PIN(6, 21), 2159077365a9SGeert Uytterhoeven }; 2160077365a9SGeert Uytterhoeven static const unsigned int hscif1_clk_a_mux[] = { 2161077365a9SGeert Uytterhoeven HSCK1_A_MARK, 2162077365a9SGeert Uytterhoeven }; 2163077365a9SGeert Uytterhoeven static const unsigned int hscif1_ctrl_a_pins[] = { 2164077365a9SGeert Uytterhoeven /* RTS, CTS */ 2165077365a9SGeert Uytterhoeven RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7), 2166077365a9SGeert Uytterhoeven }; 2167077365a9SGeert Uytterhoeven static const unsigned int hscif1_ctrl_a_mux[] = { 2168077365a9SGeert Uytterhoeven HRTS1_N_A_MARK, HCTS1_N_A_MARK, 2169077365a9SGeert Uytterhoeven }; 2170077365a9SGeert Uytterhoeven 2171077365a9SGeert Uytterhoeven static const unsigned int hscif1_data_b_pins[] = { 2172077365a9SGeert Uytterhoeven /* RX, TX */ 2173077365a9SGeert Uytterhoeven RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), 2174077365a9SGeert Uytterhoeven }; 2175077365a9SGeert Uytterhoeven static const unsigned int hscif1_data_b_mux[] = { 2176077365a9SGeert Uytterhoeven HRX1_B_MARK, HTX1_B_MARK, 2177077365a9SGeert Uytterhoeven }; 2178077365a9SGeert Uytterhoeven static const unsigned int hscif1_clk_b_pins[] = { 2179077365a9SGeert Uytterhoeven /* SCK */ 2180077365a9SGeert Uytterhoeven RCAR_GP_PIN(5, 0), 2181077365a9SGeert Uytterhoeven }; 2182077365a9SGeert Uytterhoeven static const unsigned int hscif1_clk_b_mux[] = { 2183077365a9SGeert Uytterhoeven HSCK1_B_MARK, 2184077365a9SGeert Uytterhoeven }; 2185077365a9SGeert Uytterhoeven static const unsigned int hscif1_ctrl_b_pins[] = { 2186077365a9SGeert Uytterhoeven /* RTS, CTS */ 2187077365a9SGeert Uytterhoeven RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3), 2188077365a9SGeert Uytterhoeven }; 2189077365a9SGeert Uytterhoeven static const unsigned int hscif1_ctrl_b_mux[] = { 2190077365a9SGeert Uytterhoeven HRTS1_N_B_MARK, HCTS1_N_B_MARK, 2191077365a9SGeert Uytterhoeven }; 2192077365a9SGeert Uytterhoeven /* - HSCIF2 ----------------------------------------------------------------- */ 2193077365a9SGeert Uytterhoeven static const unsigned int hscif2_data_a_pins[] = { 2194077365a9SGeert Uytterhoeven /* RX, TX */ 2195077365a9SGeert Uytterhoeven RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), 2196077365a9SGeert Uytterhoeven }; 2197077365a9SGeert Uytterhoeven static const unsigned int hscif2_data_a_mux[] = { 2198077365a9SGeert Uytterhoeven HRX2_A_MARK, HTX2_A_MARK, 2199077365a9SGeert Uytterhoeven }; 2200077365a9SGeert Uytterhoeven static const unsigned int hscif2_clk_a_pins[] = { 2201077365a9SGeert Uytterhoeven /* SCK */ 2202077365a9SGeert Uytterhoeven RCAR_GP_PIN(6, 10), 2203077365a9SGeert Uytterhoeven }; 2204077365a9SGeert Uytterhoeven static const unsigned int hscif2_clk_a_mux[] = { 2205077365a9SGeert Uytterhoeven HSCK2_A_MARK, 2206077365a9SGeert Uytterhoeven }; 2207077365a9SGeert Uytterhoeven static const unsigned int hscif2_ctrl_a_pins[] = { 2208077365a9SGeert Uytterhoeven /* RTS, CTS */ 2209077365a9SGeert Uytterhoeven RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6), 2210077365a9SGeert Uytterhoeven }; 2211077365a9SGeert Uytterhoeven static const unsigned int hscif2_ctrl_a_mux[] = { 2212077365a9SGeert Uytterhoeven HRTS2_N_A_MARK, HCTS2_N_A_MARK, 2213077365a9SGeert Uytterhoeven }; 2214077365a9SGeert Uytterhoeven 2215077365a9SGeert Uytterhoeven static const unsigned int hscif2_data_b_pins[] = { 2216077365a9SGeert Uytterhoeven /* RX, TX */ 2217077365a9SGeert Uytterhoeven RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18), 2218077365a9SGeert Uytterhoeven }; 2219077365a9SGeert Uytterhoeven static const unsigned int hscif2_data_b_mux[] = { 2220077365a9SGeert Uytterhoeven HRX2_B_MARK, HTX2_B_MARK, 2221077365a9SGeert Uytterhoeven }; 2222077365a9SGeert Uytterhoeven static const unsigned int hscif2_clk_b_pins[] = { 2223077365a9SGeert Uytterhoeven /* SCK */ 2224077365a9SGeert Uytterhoeven RCAR_GP_PIN(6, 21), 2225077365a9SGeert Uytterhoeven }; 2226077365a9SGeert Uytterhoeven static const unsigned int hscif2_clk_b_mux[] = { 2227077365a9SGeert Uytterhoeven HSCK2_B_MARK, 2228077365a9SGeert Uytterhoeven }; 2229077365a9SGeert Uytterhoeven static const unsigned int hscif2_ctrl_b_pins[] = { 2230077365a9SGeert Uytterhoeven /* RTS, CTS */ 2231077365a9SGeert Uytterhoeven RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19), 2232077365a9SGeert Uytterhoeven }; 2233077365a9SGeert Uytterhoeven static const unsigned int hscif2_ctrl_b_mux[] = { 2234077365a9SGeert Uytterhoeven HRTS2_N_B_MARK, HCTS2_N_B_MARK, 2235077365a9SGeert Uytterhoeven }; 2236077365a9SGeert Uytterhoeven 2237077365a9SGeert Uytterhoeven static const unsigned int hscif2_data_c_pins[] = { 2238077365a9SGeert Uytterhoeven /* RX, TX */ 2239077365a9SGeert Uytterhoeven RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26), 2240077365a9SGeert Uytterhoeven }; 2241077365a9SGeert Uytterhoeven static const unsigned int hscif2_data_c_mux[] = { 2242077365a9SGeert Uytterhoeven HRX2_C_MARK, HTX2_C_MARK, 2243077365a9SGeert Uytterhoeven }; 2244077365a9SGeert Uytterhoeven static const unsigned int hscif2_clk_c_pins[] = { 2245077365a9SGeert Uytterhoeven /* SCK */ 2246077365a9SGeert Uytterhoeven RCAR_GP_PIN(6, 24), 2247077365a9SGeert Uytterhoeven }; 2248077365a9SGeert Uytterhoeven static const unsigned int hscif2_clk_c_mux[] = { 2249077365a9SGeert Uytterhoeven HSCK2_C_MARK, 2250077365a9SGeert Uytterhoeven }; 2251077365a9SGeert Uytterhoeven static const unsigned int hscif2_ctrl_c_pins[] = { 2252077365a9SGeert Uytterhoeven /* RTS, CTS */ 2253077365a9SGeert Uytterhoeven RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 27), 2254077365a9SGeert Uytterhoeven }; 2255077365a9SGeert Uytterhoeven static const unsigned int hscif2_ctrl_c_mux[] = { 2256077365a9SGeert Uytterhoeven HRTS2_N_C_MARK, HCTS2_N_C_MARK, 2257077365a9SGeert Uytterhoeven }; 2258077365a9SGeert Uytterhoeven /* - HSCIF3 ----------------------------------------------------------------- */ 2259077365a9SGeert Uytterhoeven static const unsigned int hscif3_data_a_pins[] = { 2260077365a9SGeert Uytterhoeven /* RX, TX */ 2261077365a9SGeert Uytterhoeven RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24), 2262077365a9SGeert Uytterhoeven }; 2263077365a9SGeert Uytterhoeven static const unsigned int hscif3_data_a_mux[] = { 2264077365a9SGeert Uytterhoeven HRX3_A_MARK, HTX3_A_MARK, 2265077365a9SGeert Uytterhoeven }; 2266077365a9SGeert Uytterhoeven static const unsigned int hscif3_clk_pins[] = { 2267077365a9SGeert Uytterhoeven /* SCK */ 2268077365a9SGeert Uytterhoeven RCAR_GP_PIN(1, 22), 2269077365a9SGeert Uytterhoeven }; 2270077365a9SGeert Uytterhoeven static const unsigned int hscif3_clk_mux[] = { 2271077365a9SGeert Uytterhoeven HSCK3_MARK, 2272077365a9SGeert Uytterhoeven }; 2273077365a9SGeert Uytterhoeven static const unsigned int hscif3_ctrl_pins[] = { 2274077365a9SGeert Uytterhoeven /* RTS, CTS */ 2275077365a9SGeert Uytterhoeven RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25), 2276077365a9SGeert Uytterhoeven }; 2277077365a9SGeert Uytterhoeven static const unsigned int hscif3_ctrl_mux[] = { 2278077365a9SGeert Uytterhoeven HRTS3_N_MARK, HCTS3_N_MARK, 2279077365a9SGeert Uytterhoeven }; 2280077365a9SGeert Uytterhoeven 2281077365a9SGeert Uytterhoeven static const unsigned int hscif3_data_b_pins[] = { 2282077365a9SGeert Uytterhoeven /* RX, TX */ 2283077365a9SGeert Uytterhoeven RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), 2284077365a9SGeert Uytterhoeven }; 2285077365a9SGeert Uytterhoeven static const unsigned int hscif3_data_b_mux[] = { 2286077365a9SGeert Uytterhoeven HRX3_B_MARK, HTX3_B_MARK, 2287077365a9SGeert Uytterhoeven }; 2288077365a9SGeert Uytterhoeven static const unsigned int hscif3_data_c_pins[] = { 2289077365a9SGeert Uytterhoeven /* RX, TX */ 2290077365a9SGeert Uytterhoeven RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), 2291077365a9SGeert Uytterhoeven }; 2292077365a9SGeert Uytterhoeven static const unsigned int hscif3_data_c_mux[] = { 2293077365a9SGeert Uytterhoeven HRX3_C_MARK, HTX3_C_MARK, 2294077365a9SGeert Uytterhoeven }; 2295077365a9SGeert Uytterhoeven static const unsigned int hscif3_data_d_pins[] = { 2296077365a9SGeert Uytterhoeven /* RX, TX */ 2297077365a9SGeert Uytterhoeven RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), 2298077365a9SGeert Uytterhoeven }; 2299077365a9SGeert Uytterhoeven static const unsigned int hscif3_data_d_mux[] = { 2300077365a9SGeert Uytterhoeven HRX3_D_MARK, HTX3_D_MARK, 2301077365a9SGeert Uytterhoeven }; 2302077365a9SGeert Uytterhoeven /* - HSCIF4 ----------------------------------------------------------------- */ 2303077365a9SGeert Uytterhoeven static const unsigned int hscif4_data_a_pins[] = { 2304077365a9SGeert Uytterhoeven /* RX, TX */ 2305077365a9SGeert Uytterhoeven RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), 2306077365a9SGeert Uytterhoeven }; 2307077365a9SGeert Uytterhoeven static const unsigned int hscif4_data_a_mux[] = { 2308077365a9SGeert Uytterhoeven HRX4_A_MARK, HTX4_A_MARK, 2309077365a9SGeert Uytterhoeven }; 2310077365a9SGeert Uytterhoeven static const unsigned int hscif4_clk_pins[] = { 2311077365a9SGeert Uytterhoeven /* SCK */ 2312077365a9SGeert Uytterhoeven RCAR_GP_PIN(1, 11), 2313077365a9SGeert Uytterhoeven }; 2314077365a9SGeert Uytterhoeven static const unsigned int hscif4_clk_mux[] = { 2315077365a9SGeert Uytterhoeven HSCK4_MARK, 2316077365a9SGeert Uytterhoeven }; 2317077365a9SGeert Uytterhoeven static const unsigned int hscif4_ctrl_pins[] = { 2318077365a9SGeert Uytterhoeven /* RTS, CTS */ 2319077365a9SGeert Uytterhoeven RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), 2320077365a9SGeert Uytterhoeven }; 2321077365a9SGeert Uytterhoeven static const unsigned int hscif4_ctrl_mux[] = { 2322077365a9SGeert Uytterhoeven HRTS4_N_MARK, HCTS4_N_MARK, 2323077365a9SGeert Uytterhoeven }; 2324077365a9SGeert Uytterhoeven 2325077365a9SGeert Uytterhoeven static const unsigned int hscif4_data_b_pins[] = { 2326077365a9SGeert Uytterhoeven /* RX, TX */ 2327077365a9SGeert Uytterhoeven RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), 2328077365a9SGeert Uytterhoeven }; 2329077365a9SGeert Uytterhoeven static const unsigned int hscif4_data_b_mux[] = { 2330077365a9SGeert Uytterhoeven HRX4_B_MARK, HTX4_B_MARK, 2331077365a9SGeert Uytterhoeven }; 2332077365a9SGeert Uytterhoeven 2333077365a9SGeert Uytterhoeven /* - I2C -------------------------------------------------------------------- */ 2334077365a9SGeert Uytterhoeven static const unsigned int i2c0_pins[] = { 2335077365a9SGeert Uytterhoeven /* SCL, SDA */ 2336077365a9SGeert Uytterhoeven RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), 2337077365a9SGeert Uytterhoeven }; 2338077365a9SGeert Uytterhoeven 2339077365a9SGeert Uytterhoeven static const unsigned int i2c0_mux[] = { 2340077365a9SGeert Uytterhoeven SCL0_MARK, SDA0_MARK, 2341077365a9SGeert Uytterhoeven }; 2342077365a9SGeert Uytterhoeven 2343077365a9SGeert Uytterhoeven static const unsigned int i2c1_a_pins[] = { 2344077365a9SGeert Uytterhoeven /* SDA, SCL */ 2345077365a9SGeert Uytterhoeven RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10), 2346077365a9SGeert Uytterhoeven }; 2347077365a9SGeert Uytterhoeven static const unsigned int i2c1_a_mux[] = { 2348077365a9SGeert Uytterhoeven SDA1_A_MARK, SCL1_A_MARK, 2349077365a9SGeert Uytterhoeven }; 2350077365a9SGeert Uytterhoeven static const unsigned int i2c1_b_pins[] = { 2351077365a9SGeert Uytterhoeven /* SDA, SCL */ 2352077365a9SGeert Uytterhoeven RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23), 2353077365a9SGeert Uytterhoeven }; 2354077365a9SGeert Uytterhoeven static const unsigned int i2c1_b_mux[] = { 2355077365a9SGeert Uytterhoeven SDA1_B_MARK, SCL1_B_MARK, 2356077365a9SGeert Uytterhoeven }; 2357077365a9SGeert Uytterhoeven static const unsigned int i2c2_a_pins[] = { 2358077365a9SGeert Uytterhoeven /* SDA, SCL */ 2359077365a9SGeert Uytterhoeven RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4), 2360077365a9SGeert Uytterhoeven }; 2361077365a9SGeert Uytterhoeven static const unsigned int i2c2_a_mux[] = { 2362077365a9SGeert Uytterhoeven SDA2_A_MARK, SCL2_A_MARK, 2363077365a9SGeert Uytterhoeven }; 2364077365a9SGeert Uytterhoeven static const unsigned int i2c2_b_pins[] = { 2365077365a9SGeert Uytterhoeven /* SDA, SCL */ 2366077365a9SGeert Uytterhoeven RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12), 2367077365a9SGeert Uytterhoeven }; 2368077365a9SGeert Uytterhoeven static const unsigned int i2c2_b_mux[] = { 2369077365a9SGeert Uytterhoeven SDA2_B_MARK, SCL2_B_MARK, 2370077365a9SGeert Uytterhoeven }; 2371077365a9SGeert Uytterhoeven 2372077365a9SGeert Uytterhoeven static const unsigned int i2c3_pins[] = { 2373077365a9SGeert Uytterhoeven /* SCL, SDA */ 2374077365a9SGeert Uytterhoeven RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), 2375077365a9SGeert Uytterhoeven }; 2376077365a9SGeert Uytterhoeven 2377077365a9SGeert Uytterhoeven static const unsigned int i2c3_mux[] = { 2378077365a9SGeert Uytterhoeven SCL3_MARK, SDA3_MARK, 2379077365a9SGeert Uytterhoeven }; 2380077365a9SGeert Uytterhoeven 2381077365a9SGeert Uytterhoeven static const unsigned int i2c5_pins[] = { 2382077365a9SGeert Uytterhoeven /* SCL, SDA */ 2383077365a9SGeert Uytterhoeven RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14), 2384077365a9SGeert Uytterhoeven }; 2385077365a9SGeert Uytterhoeven 2386077365a9SGeert Uytterhoeven static const unsigned int i2c5_mux[] = { 2387077365a9SGeert Uytterhoeven SCL5_MARK, SDA5_MARK, 2388077365a9SGeert Uytterhoeven }; 2389077365a9SGeert Uytterhoeven 2390077365a9SGeert Uytterhoeven static const unsigned int i2c6_a_pins[] = { 2391077365a9SGeert Uytterhoeven /* SDA, SCL */ 2392077365a9SGeert Uytterhoeven RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), 2393077365a9SGeert Uytterhoeven }; 2394077365a9SGeert Uytterhoeven static const unsigned int i2c6_a_mux[] = { 2395077365a9SGeert Uytterhoeven SDA6_A_MARK, SCL6_A_MARK, 2396077365a9SGeert Uytterhoeven }; 2397077365a9SGeert Uytterhoeven static const unsigned int i2c6_b_pins[] = { 2398077365a9SGeert Uytterhoeven /* SDA, SCL */ 2399077365a9SGeert Uytterhoeven RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25), 2400077365a9SGeert Uytterhoeven }; 2401077365a9SGeert Uytterhoeven static const unsigned int i2c6_b_mux[] = { 2402077365a9SGeert Uytterhoeven SDA6_B_MARK, SCL6_B_MARK, 2403077365a9SGeert Uytterhoeven }; 2404077365a9SGeert Uytterhoeven static const unsigned int i2c6_c_pins[] = { 2405077365a9SGeert Uytterhoeven /* SDA, SCL */ 2406077365a9SGeert Uytterhoeven RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), 2407077365a9SGeert Uytterhoeven }; 2408077365a9SGeert Uytterhoeven static const unsigned int i2c6_c_mux[] = { 2409077365a9SGeert Uytterhoeven SDA6_C_MARK, SCL6_C_MARK, 2410077365a9SGeert Uytterhoeven }; 2411077365a9SGeert Uytterhoeven 2412077365a9SGeert Uytterhoeven /* - INTC-EX ---------------------------------------------------------------- */ 2413077365a9SGeert Uytterhoeven static const unsigned int intc_ex_irq0_pins[] = { 2414077365a9SGeert Uytterhoeven /* IRQ0 */ 2415077365a9SGeert Uytterhoeven RCAR_GP_PIN(2, 0), 2416077365a9SGeert Uytterhoeven }; 2417077365a9SGeert Uytterhoeven static const unsigned int intc_ex_irq0_mux[] = { 2418077365a9SGeert Uytterhoeven IRQ0_MARK, 2419077365a9SGeert Uytterhoeven }; 2420077365a9SGeert Uytterhoeven static const unsigned int intc_ex_irq1_pins[] = { 2421077365a9SGeert Uytterhoeven /* IRQ1 */ 2422077365a9SGeert Uytterhoeven RCAR_GP_PIN(2, 1), 2423077365a9SGeert Uytterhoeven }; 2424077365a9SGeert Uytterhoeven static const unsigned int intc_ex_irq1_mux[] = { 2425077365a9SGeert Uytterhoeven IRQ1_MARK, 2426077365a9SGeert Uytterhoeven }; 2427077365a9SGeert Uytterhoeven static const unsigned int intc_ex_irq2_pins[] = { 2428077365a9SGeert Uytterhoeven /* IRQ2 */ 2429077365a9SGeert Uytterhoeven RCAR_GP_PIN(2, 2), 2430077365a9SGeert Uytterhoeven }; 2431077365a9SGeert Uytterhoeven static const unsigned int intc_ex_irq2_mux[] = { 2432077365a9SGeert Uytterhoeven IRQ2_MARK, 2433077365a9SGeert Uytterhoeven }; 2434077365a9SGeert Uytterhoeven static const unsigned int intc_ex_irq3_pins[] = { 2435077365a9SGeert Uytterhoeven /* IRQ3 */ 2436077365a9SGeert Uytterhoeven RCAR_GP_PIN(2, 3), 2437077365a9SGeert Uytterhoeven }; 2438077365a9SGeert Uytterhoeven static const unsigned int intc_ex_irq3_mux[] = { 2439077365a9SGeert Uytterhoeven IRQ3_MARK, 2440077365a9SGeert Uytterhoeven }; 2441077365a9SGeert Uytterhoeven static const unsigned int intc_ex_irq4_pins[] = { 2442077365a9SGeert Uytterhoeven /* IRQ4 */ 2443077365a9SGeert Uytterhoeven RCAR_GP_PIN(2, 4), 2444077365a9SGeert Uytterhoeven }; 2445077365a9SGeert Uytterhoeven static const unsigned int intc_ex_irq4_mux[] = { 2446077365a9SGeert Uytterhoeven IRQ4_MARK, 2447077365a9SGeert Uytterhoeven }; 2448077365a9SGeert Uytterhoeven static const unsigned int intc_ex_irq5_pins[] = { 2449077365a9SGeert Uytterhoeven /* IRQ5 */ 2450077365a9SGeert Uytterhoeven RCAR_GP_PIN(2, 5), 2451077365a9SGeert Uytterhoeven }; 2452077365a9SGeert Uytterhoeven static const unsigned int intc_ex_irq5_mux[] = { 2453077365a9SGeert Uytterhoeven IRQ5_MARK, 2454077365a9SGeert Uytterhoeven }; 2455077365a9SGeert Uytterhoeven 2456ce34fb3cSAndrey Gusakov #ifdef CONFIG_PINCTRL_PFC_R8A77951 2457ce34fb3cSAndrey Gusakov /* - MLB+ ------------------------------------------------------------------- */ 2458ce34fb3cSAndrey Gusakov static const unsigned int mlb_3pin_pins[] = { 2459ce34fb3cSAndrey Gusakov RCAR_GP_PIN(5, 23), RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25), 2460ce34fb3cSAndrey Gusakov }; 2461ce34fb3cSAndrey Gusakov static const unsigned int mlb_3pin_mux[] = { 2462ce34fb3cSAndrey Gusakov MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK, 2463ce34fb3cSAndrey Gusakov }; 2464ce34fb3cSAndrey Gusakov #endif /* CONFIG_PINCTRL_PFC_R8A77951 */ 2465ce34fb3cSAndrey Gusakov 2466077365a9SGeert Uytterhoeven /* - MSIOF0 ----------------------------------------------------------------- */ 2467077365a9SGeert Uytterhoeven static const unsigned int msiof0_clk_pins[] = { 2468077365a9SGeert Uytterhoeven /* SCK */ 2469077365a9SGeert Uytterhoeven RCAR_GP_PIN(5, 17), 2470077365a9SGeert Uytterhoeven }; 2471077365a9SGeert Uytterhoeven static const unsigned int msiof0_clk_mux[] = { 2472077365a9SGeert Uytterhoeven MSIOF0_SCK_MARK, 2473077365a9SGeert Uytterhoeven }; 2474077365a9SGeert Uytterhoeven static const unsigned int msiof0_sync_pins[] = { 2475077365a9SGeert Uytterhoeven /* SYNC */ 2476077365a9SGeert Uytterhoeven RCAR_GP_PIN(5, 18), 2477077365a9SGeert Uytterhoeven }; 2478077365a9SGeert Uytterhoeven static const unsigned int msiof0_sync_mux[] = { 2479077365a9SGeert Uytterhoeven MSIOF0_SYNC_MARK, 2480077365a9SGeert Uytterhoeven }; 2481077365a9SGeert Uytterhoeven static const unsigned int msiof0_ss1_pins[] = { 2482077365a9SGeert Uytterhoeven /* SS1 */ 2483077365a9SGeert Uytterhoeven RCAR_GP_PIN(5, 19), 2484077365a9SGeert Uytterhoeven }; 2485077365a9SGeert Uytterhoeven static const unsigned int msiof0_ss1_mux[] = { 2486077365a9SGeert Uytterhoeven MSIOF0_SS1_MARK, 2487077365a9SGeert Uytterhoeven }; 2488077365a9SGeert Uytterhoeven static const unsigned int msiof0_ss2_pins[] = { 2489077365a9SGeert Uytterhoeven /* SS2 */ 2490077365a9SGeert Uytterhoeven RCAR_GP_PIN(5, 21), 2491077365a9SGeert Uytterhoeven }; 2492077365a9SGeert Uytterhoeven static const unsigned int msiof0_ss2_mux[] = { 2493077365a9SGeert Uytterhoeven MSIOF0_SS2_MARK, 2494077365a9SGeert Uytterhoeven }; 2495077365a9SGeert Uytterhoeven static const unsigned int msiof0_txd_pins[] = { 2496077365a9SGeert Uytterhoeven /* TXD */ 2497077365a9SGeert Uytterhoeven RCAR_GP_PIN(5, 20), 2498077365a9SGeert Uytterhoeven }; 2499077365a9SGeert Uytterhoeven static const unsigned int msiof0_txd_mux[] = { 2500077365a9SGeert Uytterhoeven MSIOF0_TXD_MARK, 2501077365a9SGeert Uytterhoeven }; 2502077365a9SGeert Uytterhoeven static const unsigned int msiof0_rxd_pins[] = { 2503077365a9SGeert Uytterhoeven /* RXD */ 2504077365a9SGeert Uytterhoeven RCAR_GP_PIN(5, 22), 2505077365a9SGeert Uytterhoeven }; 2506077365a9SGeert Uytterhoeven static const unsigned int msiof0_rxd_mux[] = { 2507077365a9SGeert Uytterhoeven MSIOF0_RXD_MARK, 2508077365a9SGeert Uytterhoeven }; 2509077365a9SGeert Uytterhoeven /* - MSIOF1 ----------------------------------------------------------------- */ 2510077365a9SGeert Uytterhoeven static const unsigned int msiof1_clk_a_pins[] = { 2511077365a9SGeert Uytterhoeven /* SCK */ 2512077365a9SGeert Uytterhoeven RCAR_GP_PIN(6, 8), 2513077365a9SGeert Uytterhoeven }; 2514077365a9SGeert Uytterhoeven static const unsigned int msiof1_clk_a_mux[] = { 2515077365a9SGeert Uytterhoeven MSIOF1_SCK_A_MARK, 2516077365a9SGeert Uytterhoeven }; 2517077365a9SGeert Uytterhoeven static const unsigned int msiof1_sync_a_pins[] = { 2518077365a9SGeert Uytterhoeven /* SYNC */ 2519077365a9SGeert Uytterhoeven RCAR_GP_PIN(6, 9), 2520077365a9SGeert Uytterhoeven }; 2521077365a9SGeert Uytterhoeven static const unsigned int msiof1_sync_a_mux[] = { 2522077365a9SGeert Uytterhoeven MSIOF1_SYNC_A_MARK, 2523077365a9SGeert Uytterhoeven }; 2524077365a9SGeert Uytterhoeven static const unsigned int msiof1_ss1_a_pins[] = { 2525077365a9SGeert Uytterhoeven /* SS1 */ 2526077365a9SGeert Uytterhoeven RCAR_GP_PIN(6, 5), 2527077365a9SGeert Uytterhoeven }; 2528077365a9SGeert Uytterhoeven static const unsigned int msiof1_ss1_a_mux[] = { 2529077365a9SGeert Uytterhoeven MSIOF1_SS1_A_MARK, 2530077365a9SGeert Uytterhoeven }; 2531077365a9SGeert Uytterhoeven static const unsigned int msiof1_ss2_a_pins[] = { 2532077365a9SGeert Uytterhoeven /* SS2 */ 2533077365a9SGeert Uytterhoeven RCAR_GP_PIN(6, 6), 2534077365a9SGeert Uytterhoeven }; 2535077365a9SGeert Uytterhoeven static const unsigned int msiof1_ss2_a_mux[] = { 2536077365a9SGeert Uytterhoeven MSIOF1_SS2_A_MARK, 2537077365a9SGeert Uytterhoeven }; 2538077365a9SGeert Uytterhoeven static const unsigned int msiof1_txd_a_pins[] = { 2539077365a9SGeert Uytterhoeven /* TXD */ 2540077365a9SGeert Uytterhoeven RCAR_GP_PIN(6, 7), 2541077365a9SGeert Uytterhoeven }; 2542077365a9SGeert Uytterhoeven static const unsigned int msiof1_txd_a_mux[] = { 2543077365a9SGeert Uytterhoeven MSIOF1_TXD_A_MARK, 2544077365a9SGeert Uytterhoeven }; 2545077365a9SGeert Uytterhoeven static const unsigned int msiof1_rxd_a_pins[] = { 2546077365a9SGeert Uytterhoeven /* RXD */ 2547077365a9SGeert Uytterhoeven RCAR_GP_PIN(6, 10), 2548077365a9SGeert Uytterhoeven }; 2549077365a9SGeert Uytterhoeven static const unsigned int msiof1_rxd_a_mux[] = { 2550077365a9SGeert Uytterhoeven MSIOF1_RXD_A_MARK, 2551077365a9SGeert Uytterhoeven }; 2552077365a9SGeert Uytterhoeven static const unsigned int msiof1_clk_b_pins[] = { 2553077365a9SGeert Uytterhoeven /* SCK */ 2554077365a9SGeert Uytterhoeven RCAR_GP_PIN(5, 9), 2555077365a9SGeert Uytterhoeven }; 2556077365a9SGeert Uytterhoeven static const unsigned int msiof1_clk_b_mux[] = { 2557077365a9SGeert Uytterhoeven MSIOF1_SCK_B_MARK, 2558077365a9SGeert Uytterhoeven }; 2559077365a9SGeert Uytterhoeven static const unsigned int msiof1_sync_b_pins[] = { 2560077365a9SGeert Uytterhoeven /* SYNC */ 2561077365a9SGeert Uytterhoeven RCAR_GP_PIN(5, 3), 2562077365a9SGeert Uytterhoeven }; 2563077365a9SGeert Uytterhoeven static const unsigned int msiof1_sync_b_mux[] = { 2564077365a9SGeert Uytterhoeven MSIOF1_SYNC_B_MARK, 2565077365a9SGeert Uytterhoeven }; 2566077365a9SGeert Uytterhoeven static const unsigned int msiof1_ss1_b_pins[] = { 2567077365a9SGeert Uytterhoeven /* SS1 */ 2568077365a9SGeert Uytterhoeven RCAR_GP_PIN(5, 4), 2569077365a9SGeert Uytterhoeven }; 2570077365a9SGeert Uytterhoeven static const unsigned int msiof1_ss1_b_mux[] = { 2571077365a9SGeert Uytterhoeven MSIOF1_SS1_B_MARK, 2572077365a9SGeert Uytterhoeven }; 2573077365a9SGeert Uytterhoeven static const unsigned int msiof1_ss2_b_pins[] = { 2574077365a9SGeert Uytterhoeven /* SS2 */ 2575077365a9SGeert Uytterhoeven RCAR_GP_PIN(5, 0), 2576077365a9SGeert Uytterhoeven }; 2577077365a9SGeert Uytterhoeven static const unsigned int msiof1_ss2_b_mux[] = { 2578077365a9SGeert Uytterhoeven MSIOF1_SS2_B_MARK, 2579077365a9SGeert Uytterhoeven }; 2580077365a9SGeert Uytterhoeven static const unsigned int msiof1_txd_b_pins[] = { 2581077365a9SGeert Uytterhoeven /* TXD */ 2582077365a9SGeert Uytterhoeven RCAR_GP_PIN(5, 8), 2583077365a9SGeert Uytterhoeven }; 2584077365a9SGeert Uytterhoeven static const unsigned int msiof1_txd_b_mux[] = { 2585077365a9SGeert Uytterhoeven MSIOF1_TXD_B_MARK, 2586077365a9SGeert Uytterhoeven }; 2587077365a9SGeert Uytterhoeven static const unsigned int msiof1_rxd_b_pins[] = { 2588077365a9SGeert Uytterhoeven /* RXD */ 2589077365a9SGeert Uytterhoeven RCAR_GP_PIN(5, 7), 2590077365a9SGeert Uytterhoeven }; 2591077365a9SGeert Uytterhoeven static const unsigned int msiof1_rxd_b_mux[] = { 2592077365a9SGeert Uytterhoeven MSIOF1_RXD_B_MARK, 2593077365a9SGeert Uytterhoeven }; 2594077365a9SGeert Uytterhoeven static const unsigned int msiof1_clk_c_pins[] = { 2595077365a9SGeert Uytterhoeven /* SCK */ 2596077365a9SGeert Uytterhoeven RCAR_GP_PIN(6, 17), 2597077365a9SGeert Uytterhoeven }; 2598077365a9SGeert Uytterhoeven static const unsigned int msiof1_clk_c_mux[] = { 2599077365a9SGeert Uytterhoeven MSIOF1_SCK_C_MARK, 2600077365a9SGeert Uytterhoeven }; 2601077365a9SGeert Uytterhoeven static const unsigned int msiof1_sync_c_pins[] = { 2602077365a9SGeert Uytterhoeven /* SYNC */ 2603077365a9SGeert Uytterhoeven RCAR_GP_PIN(6, 18), 2604077365a9SGeert Uytterhoeven }; 2605077365a9SGeert Uytterhoeven static const unsigned int msiof1_sync_c_mux[] = { 2606077365a9SGeert Uytterhoeven MSIOF1_SYNC_C_MARK, 2607077365a9SGeert Uytterhoeven }; 2608077365a9SGeert Uytterhoeven static const unsigned int msiof1_ss1_c_pins[] = { 2609077365a9SGeert Uytterhoeven /* SS1 */ 2610077365a9SGeert Uytterhoeven RCAR_GP_PIN(6, 21), 2611077365a9SGeert Uytterhoeven }; 2612077365a9SGeert Uytterhoeven static const unsigned int msiof1_ss1_c_mux[] = { 2613077365a9SGeert Uytterhoeven MSIOF1_SS1_C_MARK, 2614077365a9SGeert Uytterhoeven }; 2615077365a9SGeert Uytterhoeven static const unsigned int msiof1_ss2_c_pins[] = { 2616077365a9SGeert Uytterhoeven /* SS2 */ 2617077365a9SGeert Uytterhoeven RCAR_GP_PIN(6, 27), 2618077365a9SGeert Uytterhoeven }; 2619077365a9SGeert Uytterhoeven static const unsigned int msiof1_ss2_c_mux[] = { 2620077365a9SGeert Uytterhoeven MSIOF1_SS2_C_MARK, 2621077365a9SGeert Uytterhoeven }; 2622077365a9SGeert Uytterhoeven static const unsigned int msiof1_txd_c_pins[] = { 2623077365a9SGeert Uytterhoeven /* TXD */ 2624077365a9SGeert Uytterhoeven RCAR_GP_PIN(6, 20), 2625077365a9SGeert Uytterhoeven }; 2626077365a9SGeert Uytterhoeven static const unsigned int msiof1_txd_c_mux[] = { 2627077365a9SGeert Uytterhoeven MSIOF1_TXD_C_MARK, 2628077365a9SGeert Uytterhoeven }; 2629077365a9SGeert Uytterhoeven static const unsigned int msiof1_rxd_c_pins[] = { 2630077365a9SGeert Uytterhoeven /* RXD */ 2631077365a9SGeert Uytterhoeven RCAR_GP_PIN(6, 19), 2632077365a9SGeert Uytterhoeven }; 2633077365a9SGeert Uytterhoeven static const unsigned int msiof1_rxd_c_mux[] = { 2634077365a9SGeert Uytterhoeven MSIOF1_RXD_C_MARK, 2635077365a9SGeert Uytterhoeven }; 2636077365a9SGeert Uytterhoeven static const unsigned int msiof1_clk_d_pins[] = { 2637077365a9SGeert Uytterhoeven /* SCK */ 2638077365a9SGeert Uytterhoeven RCAR_GP_PIN(5, 12), 2639077365a9SGeert Uytterhoeven }; 2640077365a9SGeert Uytterhoeven static const unsigned int msiof1_clk_d_mux[] = { 2641077365a9SGeert Uytterhoeven MSIOF1_SCK_D_MARK, 2642077365a9SGeert Uytterhoeven }; 2643077365a9SGeert Uytterhoeven static const unsigned int msiof1_sync_d_pins[] = { 2644077365a9SGeert Uytterhoeven /* SYNC */ 2645077365a9SGeert Uytterhoeven RCAR_GP_PIN(5, 15), 2646077365a9SGeert Uytterhoeven }; 2647077365a9SGeert Uytterhoeven static const unsigned int msiof1_sync_d_mux[] = { 2648077365a9SGeert Uytterhoeven MSIOF1_SYNC_D_MARK, 2649077365a9SGeert Uytterhoeven }; 2650077365a9SGeert Uytterhoeven static const unsigned int msiof1_ss1_d_pins[] = { 2651077365a9SGeert Uytterhoeven /* SS1 */ 2652077365a9SGeert Uytterhoeven RCAR_GP_PIN(5, 16), 2653077365a9SGeert Uytterhoeven }; 2654077365a9SGeert Uytterhoeven static const unsigned int msiof1_ss1_d_mux[] = { 2655077365a9SGeert Uytterhoeven MSIOF1_SS1_D_MARK, 2656077365a9SGeert Uytterhoeven }; 2657077365a9SGeert Uytterhoeven static const unsigned int msiof1_ss2_d_pins[] = { 2658077365a9SGeert Uytterhoeven /* SS2 */ 2659077365a9SGeert Uytterhoeven RCAR_GP_PIN(5, 21), 2660077365a9SGeert Uytterhoeven }; 2661077365a9SGeert Uytterhoeven static const unsigned int msiof1_ss2_d_mux[] = { 2662077365a9SGeert Uytterhoeven MSIOF1_SS2_D_MARK, 2663077365a9SGeert Uytterhoeven }; 2664077365a9SGeert Uytterhoeven static const unsigned int msiof1_txd_d_pins[] = { 2665077365a9SGeert Uytterhoeven /* TXD */ 2666077365a9SGeert Uytterhoeven RCAR_GP_PIN(5, 14), 2667077365a9SGeert Uytterhoeven }; 2668077365a9SGeert Uytterhoeven static const unsigned int msiof1_txd_d_mux[] = { 2669077365a9SGeert Uytterhoeven MSIOF1_TXD_D_MARK, 2670077365a9SGeert Uytterhoeven }; 2671077365a9SGeert Uytterhoeven static const unsigned int msiof1_rxd_d_pins[] = { 2672077365a9SGeert Uytterhoeven /* RXD */ 2673077365a9SGeert Uytterhoeven RCAR_GP_PIN(5, 13), 2674077365a9SGeert Uytterhoeven }; 2675077365a9SGeert Uytterhoeven static const unsigned int msiof1_rxd_d_mux[] = { 2676077365a9SGeert Uytterhoeven MSIOF1_RXD_D_MARK, 2677077365a9SGeert Uytterhoeven }; 2678077365a9SGeert Uytterhoeven static const unsigned int msiof1_clk_e_pins[] = { 2679077365a9SGeert Uytterhoeven /* SCK */ 2680077365a9SGeert Uytterhoeven RCAR_GP_PIN(3, 0), 2681077365a9SGeert Uytterhoeven }; 2682077365a9SGeert Uytterhoeven static const unsigned int msiof1_clk_e_mux[] = { 2683077365a9SGeert Uytterhoeven MSIOF1_SCK_E_MARK, 2684077365a9SGeert Uytterhoeven }; 2685077365a9SGeert Uytterhoeven static const unsigned int msiof1_sync_e_pins[] = { 2686077365a9SGeert Uytterhoeven /* SYNC */ 2687077365a9SGeert Uytterhoeven RCAR_GP_PIN(3, 1), 2688077365a9SGeert Uytterhoeven }; 2689077365a9SGeert Uytterhoeven static const unsigned int msiof1_sync_e_mux[] = { 2690077365a9SGeert Uytterhoeven MSIOF1_SYNC_E_MARK, 2691077365a9SGeert Uytterhoeven }; 2692077365a9SGeert Uytterhoeven static const unsigned int msiof1_ss1_e_pins[] = { 2693077365a9SGeert Uytterhoeven /* SS1 */ 2694077365a9SGeert Uytterhoeven RCAR_GP_PIN(3, 4), 2695077365a9SGeert Uytterhoeven }; 2696077365a9SGeert Uytterhoeven static const unsigned int msiof1_ss1_e_mux[] = { 2697077365a9SGeert Uytterhoeven MSIOF1_SS1_E_MARK, 2698077365a9SGeert Uytterhoeven }; 2699077365a9SGeert Uytterhoeven static const unsigned int msiof1_ss2_e_pins[] = { 2700077365a9SGeert Uytterhoeven /* SS2 */ 2701077365a9SGeert Uytterhoeven RCAR_GP_PIN(3, 5), 2702077365a9SGeert Uytterhoeven }; 2703077365a9SGeert Uytterhoeven static const unsigned int msiof1_ss2_e_mux[] = { 2704077365a9SGeert Uytterhoeven MSIOF1_SS2_E_MARK, 2705077365a9SGeert Uytterhoeven }; 2706077365a9SGeert Uytterhoeven static const unsigned int msiof1_txd_e_pins[] = { 2707077365a9SGeert Uytterhoeven /* TXD */ 2708077365a9SGeert Uytterhoeven RCAR_GP_PIN(3, 3), 2709077365a9SGeert Uytterhoeven }; 2710077365a9SGeert Uytterhoeven static const unsigned int msiof1_txd_e_mux[] = { 2711077365a9SGeert Uytterhoeven MSIOF1_TXD_E_MARK, 2712077365a9SGeert Uytterhoeven }; 2713077365a9SGeert Uytterhoeven static const unsigned int msiof1_rxd_e_pins[] = { 2714077365a9SGeert Uytterhoeven /* RXD */ 2715077365a9SGeert Uytterhoeven RCAR_GP_PIN(3, 2), 2716077365a9SGeert Uytterhoeven }; 2717077365a9SGeert Uytterhoeven static const unsigned int msiof1_rxd_e_mux[] = { 2718077365a9SGeert Uytterhoeven MSIOF1_RXD_E_MARK, 2719077365a9SGeert Uytterhoeven }; 2720077365a9SGeert Uytterhoeven static const unsigned int msiof1_clk_f_pins[] = { 2721077365a9SGeert Uytterhoeven /* SCK */ 2722077365a9SGeert Uytterhoeven RCAR_GP_PIN(5, 23), 2723077365a9SGeert Uytterhoeven }; 2724077365a9SGeert Uytterhoeven static const unsigned int msiof1_clk_f_mux[] = { 2725077365a9SGeert Uytterhoeven MSIOF1_SCK_F_MARK, 2726077365a9SGeert Uytterhoeven }; 2727077365a9SGeert Uytterhoeven static const unsigned int msiof1_sync_f_pins[] = { 2728077365a9SGeert Uytterhoeven /* SYNC */ 2729077365a9SGeert Uytterhoeven RCAR_GP_PIN(5, 24), 2730077365a9SGeert Uytterhoeven }; 2731077365a9SGeert Uytterhoeven static const unsigned int msiof1_sync_f_mux[] = { 2732077365a9SGeert Uytterhoeven MSIOF1_SYNC_F_MARK, 2733077365a9SGeert Uytterhoeven }; 2734077365a9SGeert Uytterhoeven static const unsigned int msiof1_ss1_f_pins[] = { 2735077365a9SGeert Uytterhoeven /* SS1 */ 2736077365a9SGeert Uytterhoeven RCAR_GP_PIN(6, 1), 2737077365a9SGeert Uytterhoeven }; 2738077365a9SGeert Uytterhoeven static const unsigned int msiof1_ss1_f_mux[] = { 2739077365a9SGeert Uytterhoeven MSIOF1_SS1_F_MARK, 2740077365a9SGeert Uytterhoeven }; 2741077365a9SGeert Uytterhoeven static const unsigned int msiof1_ss2_f_pins[] = { 2742077365a9SGeert Uytterhoeven /* SS2 */ 2743077365a9SGeert Uytterhoeven RCAR_GP_PIN(6, 2), 2744077365a9SGeert Uytterhoeven }; 2745077365a9SGeert Uytterhoeven static const unsigned int msiof1_ss2_f_mux[] = { 2746077365a9SGeert Uytterhoeven MSIOF1_SS2_F_MARK, 2747077365a9SGeert Uytterhoeven }; 2748077365a9SGeert Uytterhoeven static const unsigned int msiof1_txd_f_pins[] = { 2749077365a9SGeert Uytterhoeven /* TXD */ 2750077365a9SGeert Uytterhoeven RCAR_GP_PIN(6, 0), 2751077365a9SGeert Uytterhoeven }; 2752077365a9SGeert Uytterhoeven static const unsigned int msiof1_txd_f_mux[] = { 2753077365a9SGeert Uytterhoeven MSIOF1_TXD_F_MARK, 2754077365a9SGeert Uytterhoeven }; 2755077365a9SGeert Uytterhoeven static const unsigned int msiof1_rxd_f_pins[] = { 2756077365a9SGeert Uytterhoeven /* RXD */ 2757077365a9SGeert Uytterhoeven RCAR_GP_PIN(5, 25), 2758077365a9SGeert Uytterhoeven }; 2759077365a9SGeert Uytterhoeven static const unsigned int msiof1_rxd_f_mux[] = { 2760077365a9SGeert Uytterhoeven MSIOF1_RXD_F_MARK, 2761077365a9SGeert Uytterhoeven }; 2762077365a9SGeert Uytterhoeven static const unsigned int msiof1_clk_g_pins[] = { 2763077365a9SGeert Uytterhoeven /* SCK */ 2764077365a9SGeert Uytterhoeven RCAR_GP_PIN(3, 6), 2765077365a9SGeert Uytterhoeven }; 2766077365a9SGeert Uytterhoeven static const unsigned int msiof1_clk_g_mux[] = { 2767077365a9SGeert Uytterhoeven MSIOF1_SCK_G_MARK, 2768077365a9SGeert Uytterhoeven }; 2769077365a9SGeert Uytterhoeven static const unsigned int msiof1_sync_g_pins[] = { 2770077365a9SGeert Uytterhoeven /* SYNC */ 2771077365a9SGeert Uytterhoeven RCAR_GP_PIN(3, 7), 2772077365a9SGeert Uytterhoeven }; 2773077365a9SGeert Uytterhoeven static const unsigned int msiof1_sync_g_mux[] = { 2774077365a9SGeert Uytterhoeven MSIOF1_SYNC_G_MARK, 2775077365a9SGeert Uytterhoeven }; 2776077365a9SGeert Uytterhoeven static const unsigned int msiof1_ss1_g_pins[] = { 2777077365a9SGeert Uytterhoeven /* SS1 */ 2778077365a9SGeert Uytterhoeven RCAR_GP_PIN(3, 10), 2779077365a9SGeert Uytterhoeven }; 2780077365a9SGeert Uytterhoeven static const unsigned int msiof1_ss1_g_mux[] = { 2781077365a9SGeert Uytterhoeven MSIOF1_SS1_G_MARK, 2782077365a9SGeert Uytterhoeven }; 2783077365a9SGeert Uytterhoeven static const unsigned int msiof1_ss2_g_pins[] = { 2784077365a9SGeert Uytterhoeven /* SS2 */ 2785077365a9SGeert Uytterhoeven RCAR_GP_PIN(3, 11), 2786077365a9SGeert Uytterhoeven }; 2787077365a9SGeert Uytterhoeven static const unsigned int msiof1_ss2_g_mux[] = { 2788077365a9SGeert Uytterhoeven MSIOF1_SS2_G_MARK, 2789077365a9SGeert Uytterhoeven }; 2790077365a9SGeert Uytterhoeven static const unsigned int msiof1_txd_g_pins[] = { 2791077365a9SGeert Uytterhoeven /* TXD */ 2792077365a9SGeert Uytterhoeven RCAR_GP_PIN(3, 9), 2793077365a9SGeert Uytterhoeven }; 2794077365a9SGeert Uytterhoeven static const unsigned int msiof1_txd_g_mux[] = { 2795077365a9SGeert Uytterhoeven MSIOF1_TXD_G_MARK, 2796077365a9SGeert Uytterhoeven }; 2797077365a9SGeert Uytterhoeven static const unsigned int msiof1_rxd_g_pins[] = { 2798077365a9SGeert Uytterhoeven /* RXD */ 2799077365a9SGeert Uytterhoeven RCAR_GP_PIN(3, 8), 2800077365a9SGeert Uytterhoeven }; 2801077365a9SGeert Uytterhoeven static const unsigned int msiof1_rxd_g_mux[] = { 2802077365a9SGeert Uytterhoeven MSIOF1_RXD_G_MARK, 2803077365a9SGeert Uytterhoeven }; 2804077365a9SGeert Uytterhoeven /* - MSIOF2 ----------------------------------------------------------------- */ 2805077365a9SGeert Uytterhoeven static const unsigned int msiof2_clk_a_pins[] = { 2806077365a9SGeert Uytterhoeven /* SCK */ 2807077365a9SGeert Uytterhoeven RCAR_GP_PIN(1, 9), 2808077365a9SGeert Uytterhoeven }; 2809077365a9SGeert Uytterhoeven static const unsigned int msiof2_clk_a_mux[] = { 2810077365a9SGeert Uytterhoeven MSIOF2_SCK_A_MARK, 2811077365a9SGeert Uytterhoeven }; 2812077365a9SGeert Uytterhoeven static const unsigned int msiof2_sync_a_pins[] = { 2813077365a9SGeert Uytterhoeven /* SYNC */ 2814077365a9SGeert Uytterhoeven RCAR_GP_PIN(1, 8), 2815077365a9SGeert Uytterhoeven }; 2816077365a9SGeert Uytterhoeven static const unsigned int msiof2_sync_a_mux[] = { 2817077365a9SGeert Uytterhoeven MSIOF2_SYNC_A_MARK, 2818077365a9SGeert Uytterhoeven }; 2819077365a9SGeert Uytterhoeven static const unsigned int msiof2_ss1_a_pins[] = { 2820077365a9SGeert Uytterhoeven /* SS1 */ 2821077365a9SGeert Uytterhoeven RCAR_GP_PIN(1, 6), 2822077365a9SGeert Uytterhoeven }; 2823077365a9SGeert Uytterhoeven static const unsigned int msiof2_ss1_a_mux[] = { 2824077365a9SGeert Uytterhoeven MSIOF2_SS1_A_MARK, 2825077365a9SGeert Uytterhoeven }; 2826077365a9SGeert Uytterhoeven static const unsigned int msiof2_ss2_a_pins[] = { 2827077365a9SGeert Uytterhoeven /* SS2 */ 2828077365a9SGeert Uytterhoeven RCAR_GP_PIN(1, 7), 2829077365a9SGeert Uytterhoeven }; 2830077365a9SGeert Uytterhoeven static const unsigned int msiof2_ss2_a_mux[] = { 2831077365a9SGeert Uytterhoeven MSIOF2_SS2_A_MARK, 2832077365a9SGeert Uytterhoeven }; 2833077365a9SGeert Uytterhoeven static const unsigned int msiof2_txd_a_pins[] = { 2834077365a9SGeert Uytterhoeven /* TXD */ 2835077365a9SGeert Uytterhoeven RCAR_GP_PIN(1, 11), 2836077365a9SGeert Uytterhoeven }; 2837077365a9SGeert Uytterhoeven static const unsigned int msiof2_txd_a_mux[] = { 2838077365a9SGeert Uytterhoeven MSIOF2_TXD_A_MARK, 2839077365a9SGeert Uytterhoeven }; 2840077365a9SGeert Uytterhoeven static const unsigned int msiof2_rxd_a_pins[] = { 2841077365a9SGeert Uytterhoeven /* RXD */ 2842077365a9SGeert Uytterhoeven RCAR_GP_PIN(1, 10), 2843077365a9SGeert Uytterhoeven }; 2844077365a9SGeert Uytterhoeven static const unsigned int msiof2_rxd_a_mux[] = { 2845077365a9SGeert Uytterhoeven MSIOF2_RXD_A_MARK, 2846077365a9SGeert Uytterhoeven }; 2847077365a9SGeert Uytterhoeven static const unsigned int msiof2_clk_b_pins[] = { 2848077365a9SGeert Uytterhoeven /* SCK */ 2849077365a9SGeert Uytterhoeven RCAR_GP_PIN(0, 4), 2850077365a9SGeert Uytterhoeven }; 2851077365a9SGeert Uytterhoeven static const unsigned int msiof2_clk_b_mux[] = { 2852077365a9SGeert Uytterhoeven MSIOF2_SCK_B_MARK, 2853077365a9SGeert Uytterhoeven }; 2854077365a9SGeert Uytterhoeven static const unsigned int msiof2_sync_b_pins[] = { 2855077365a9SGeert Uytterhoeven /* SYNC */ 2856077365a9SGeert Uytterhoeven RCAR_GP_PIN(0, 5), 2857077365a9SGeert Uytterhoeven }; 2858077365a9SGeert Uytterhoeven static const unsigned int msiof2_sync_b_mux[] = { 2859077365a9SGeert Uytterhoeven MSIOF2_SYNC_B_MARK, 2860077365a9SGeert Uytterhoeven }; 2861077365a9SGeert Uytterhoeven static const unsigned int msiof2_ss1_b_pins[] = { 2862077365a9SGeert Uytterhoeven /* SS1 */ 2863077365a9SGeert Uytterhoeven RCAR_GP_PIN(0, 0), 2864077365a9SGeert Uytterhoeven }; 2865077365a9SGeert Uytterhoeven static const unsigned int msiof2_ss1_b_mux[] = { 2866077365a9SGeert Uytterhoeven MSIOF2_SS1_B_MARK, 2867077365a9SGeert Uytterhoeven }; 2868077365a9SGeert Uytterhoeven static const unsigned int msiof2_ss2_b_pins[] = { 2869077365a9SGeert Uytterhoeven /* SS2 */ 2870077365a9SGeert Uytterhoeven RCAR_GP_PIN(0, 1), 2871077365a9SGeert Uytterhoeven }; 2872077365a9SGeert Uytterhoeven static const unsigned int msiof2_ss2_b_mux[] = { 2873077365a9SGeert Uytterhoeven MSIOF2_SS2_B_MARK, 2874077365a9SGeert Uytterhoeven }; 2875077365a9SGeert Uytterhoeven static const unsigned int msiof2_txd_b_pins[] = { 2876077365a9SGeert Uytterhoeven /* TXD */ 2877077365a9SGeert Uytterhoeven RCAR_GP_PIN(0, 7), 2878077365a9SGeert Uytterhoeven }; 2879077365a9SGeert Uytterhoeven static const unsigned int msiof2_txd_b_mux[] = { 2880077365a9SGeert Uytterhoeven MSIOF2_TXD_B_MARK, 2881077365a9SGeert Uytterhoeven }; 2882077365a9SGeert Uytterhoeven static const unsigned int msiof2_rxd_b_pins[] = { 2883077365a9SGeert Uytterhoeven /* RXD */ 2884077365a9SGeert Uytterhoeven RCAR_GP_PIN(0, 6), 2885077365a9SGeert Uytterhoeven }; 2886077365a9SGeert Uytterhoeven static const unsigned int msiof2_rxd_b_mux[] = { 2887077365a9SGeert Uytterhoeven MSIOF2_RXD_B_MARK, 2888077365a9SGeert Uytterhoeven }; 2889077365a9SGeert Uytterhoeven static const unsigned int msiof2_clk_c_pins[] = { 2890077365a9SGeert Uytterhoeven /* SCK */ 2891077365a9SGeert Uytterhoeven RCAR_GP_PIN(2, 12), 2892077365a9SGeert Uytterhoeven }; 2893077365a9SGeert Uytterhoeven static const unsigned int msiof2_clk_c_mux[] = { 2894077365a9SGeert Uytterhoeven MSIOF2_SCK_C_MARK, 2895077365a9SGeert Uytterhoeven }; 2896077365a9SGeert Uytterhoeven static const unsigned int msiof2_sync_c_pins[] = { 2897077365a9SGeert Uytterhoeven /* SYNC */ 2898077365a9SGeert Uytterhoeven RCAR_GP_PIN(2, 11), 2899077365a9SGeert Uytterhoeven }; 2900077365a9SGeert Uytterhoeven static const unsigned int msiof2_sync_c_mux[] = { 2901077365a9SGeert Uytterhoeven MSIOF2_SYNC_C_MARK, 2902077365a9SGeert Uytterhoeven }; 2903077365a9SGeert Uytterhoeven static const unsigned int msiof2_ss1_c_pins[] = { 2904077365a9SGeert Uytterhoeven /* SS1 */ 2905077365a9SGeert Uytterhoeven RCAR_GP_PIN(2, 10), 2906077365a9SGeert Uytterhoeven }; 2907077365a9SGeert Uytterhoeven static const unsigned int msiof2_ss1_c_mux[] = { 2908077365a9SGeert Uytterhoeven MSIOF2_SS1_C_MARK, 2909077365a9SGeert Uytterhoeven }; 2910077365a9SGeert Uytterhoeven static const unsigned int msiof2_ss2_c_pins[] = { 2911077365a9SGeert Uytterhoeven /* SS2 */ 2912077365a9SGeert Uytterhoeven RCAR_GP_PIN(2, 9), 2913077365a9SGeert Uytterhoeven }; 2914077365a9SGeert Uytterhoeven static const unsigned int msiof2_ss2_c_mux[] = { 2915077365a9SGeert Uytterhoeven MSIOF2_SS2_C_MARK, 2916077365a9SGeert Uytterhoeven }; 2917077365a9SGeert Uytterhoeven static const unsigned int msiof2_txd_c_pins[] = { 2918077365a9SGeert Uytterhoeven /* TXD */ 2919077365a9SGeert Uytterhoeven RCAR_GP_PIN(2, 14), 2920077365a9SGeert Uytterhoeven }; 2921077365a9SGeert Uytterhoeven static const unsigned int msiof2_txd_c_mux[] = { 2922077365a9SGeert Uytterhoeven MSIOF2_TXD_C_MARK, 2923077365a9SGeert Uytterhoeven }; 2924077365a9SGeert Uytterhoeven static const unsigned int msiof2_rxd_c_pins[] = { 2925077365a9SGeert Uytterhoeven /* RXD */ 2926077365a9SGeert Uytterhoeven RCAR_GP_PIN(2, 13), 2927077365a9SGeert Uytterhoeven }; 2928077365a9SGeert Uytterhoeven static const unsigned int msiof2_rxd_c_mux[] = { 2929077365a9SGeert Uytterhoeven MSIOF2_RXD_C_MARK, 2930077365a9SGeert Uytterhoeven }; 2931077365a9SGeert Uytterhoeven static const unsigned int msiof2_clk_d_pins[] = { 2932077365a9SGeert Uytterhoeven /* SCK */ 2933077365a9SGeert Uytterhoeven RCAR_GP_PIN(0, 8), 2934077365a9SGeert Uytterhoeven }; 2935077365a9SGeert Uytterhoeven static const unsigned int msiof2_clk_d_mux[] = { 2936077365a9SGeert Uytterhoeven MSIOF2_SCK_D_MARK, 2937077365a9SGeert Uytterhoeven }; 2938077365a9SGeert Uytterhoeven static const unsigned int msiof2_sync_d_pins[] = { 2939077365a9SGeert Uytterhoeven /* SYNC */ 2940077365a9SGeert Uytterhoeven RCAR_GP_PIN(0, 9), 2941077365a9SGeert Uytterhoeven }; 2942077365a9SGeert Uytterhoeven static const unsigned int msiof2_sync_d_mux[] = { 2943077365a9SGeert Uytterhoeven MSIOF2_SYNC_D_MARK, 2944077365a9SGeert Uytterhoeven }; 2945077365a9SGeert Uytterhoeven static const unsigned int msiof2_ss1_d_pins[] = { 2946077365a9SGeert Uytterhoeven /* SS1 */ 2947077365a9SGeert Uytterhoeven RCAR_GP_PIN(0, 12), 2948077365a9SGeert Uytterhoeven }; 2949077365a9SGeert Uytterhoeven static const unsigned int msiof2_ss1_d_mux[] = { 2950077365a9SGeert Uytterhoeven MSIOF2_SS1_D_MARK, 2951077365a9SGeert Uytterhoeven }; 2952077365a9SGeert Uytterhoeven static const unsigned int msiof2_ss2_d_pins[] = { 2953077365a9SGeert Uytterhoeven /* SS2 */ 2954077365a9SGeert Uytterhoeven RCAR_GP_PIN(0, 13), 2955077365a9SGeert Uytterhoeven }; 2956077365a9SGeert Uytterhoeven static const unsigned int msiof2_ss2_d_mux[] = { 2957077365a9SGeert Uytterhoeven MSIOF2_SS2_D_MARK, 2958077365a9SGeert Uytterhoeven }; 2959077365a9SGeert Uytterhoeven static const unsigned int msiof2_txd_d_pins[] = { 2960077365a9SGeert Uytterhoeven /* TXD */ 2961077365a9SGeert Uytterhoeven RCAR_GP_PIN(0, 11), 2962077365a9SGeert Uytterhoeven }; 2963077365a9SGeert Uytterhoeven static const unsigned int msiof2_txd_d_mux[] = { 2964077365a9SGeert Uytterhoeven MSIOF2_TXD_D_MARK, 2965077365a9SGeert Uytterhoeven }; 2966077365a9SGeert Uytterhoeven static const unsigned int msiof2_rxd_d_pins[] = { 2967077365a9SGeert Uytterhoeven /* RXD */ 2968077365a9SGeert Uytterhoeven RCAR_GP_PIN(0, 10), 2969077365a9SGeert Uytterhoeven }; 2970077365a9SGeert Uytterhoeven static const unsigned int msiof2_rxd_d_mux[] = { 2971077365a9SGeert Uytterhoeven MSIOF2_RXD_D_MARK, 2972077365a9SGeert Uytterhoeven }; 2973077365a9SGeert Uytterhoeven /* - MSIOF3 ----------------------------------------------------------------- */ 2974077365a9SGeert Uytterhoeven static const unsigned int msiof3_clk_a_pins[] = { 2975077365a9SGeert Uytterhoeven /* SCK */ 2976077365a9SGeert Uytterhoeven RCAR_GP_PIN(0, 0), 2977077365a9SGeert Uytterhoeven }; 2978077365a9SGeert Uytterhoeven static const unsigned int msiof3_clk_a_mux[] = { 2979077365a9SGeert Uytterhoeven MSIOF3_SCK_A_MARK, 2980077365a9SGeert Uytterhoeven }; 2981077365a9SGeert Uytterhoeven static const unsigned int msiof3_sync_a_pins[] = { 2982077365a9SGeert Uytterhoeven /* SYNC */ 2983077365a9SGeert Uytterhoeven RCAR_GP_PIN(0, 1), 2984077365a9SGeert Uytterhoeven }; 2985077365a9SGeert Uytterhoeven static const unsigned int msiof3_sync_a_mux[] = { 2986077365a9SGeert Uytterhoeven MSIOF3_SYNC_A_MARK, 2987077365a9SGeert Uytterhoeven }; 2988077365a9SGeert Uytterhoeven static const unsigned int msiof3_ss1_a_pins[] = { 2989077365a9SGeert Uytterhoeven /* SS1 */ 2990077365a9SGeert Uytterhoeven RCAR_GP_PIN(0, 14), 2991077365a9SGeert Uytterhoeven }; 2992077365a9SGeert Uytterhoeven static const unsigned int msiof3_ss1_a_mux[] = { 2993077365a9SGeert Uytterhoeven MSIOF3_SS1_A_MARK, 2994077365a9SGeert Uytterhoeven }; 2995077365a9SGeert Uytterhoeven static const unsigned int msiof3_ss2_a_pins[] = { 2996077365a9SGeert Uytterhoeven /* SS2 */ 2997077365a9SGeert Uytterhoeven RCAR_GP_PIN(0, 15), 2998077365a9SGeert Uytterhoeven }; 2999077365a9SGeert Uytterhoeven static const unsigned int msiof3_ss2_a_mux[] = { 3000077365a9SGeert Uytterhoeven MSIOF3_SS2_A_MARK, 3001077365a9SGeert Uytterhoeven }; 3002077365a9SGeert Uytterhoeven static const unsigned int msiof3_txd_a_pins[] = { 3003077365a9SGeert Uytterhoeven /* TXD */ 3004077365a9SGeert Uytterhoeven RCAR_GP_PIN(0, 3), 3005077365a9SGeert Uytterhoeven }; 3006077365a9SGeert Uytterhoeven static const unsigned int msiof3_txd_a_mux[] = { 3007077365a9SGeert Uytterhoeven MSIOF3_TXD_A_MARK, 3008077365a9SGeert Uytterhoeven }; 3009077365a9SGeert Uytterhoeven static const unsigned int msiof3_rxd_a_pins[] = { 3010077365a9SGeert Uytterhoeven /* RXD */ 3011077365a9SGeert Uytterhoeven RCAR_GP_PIN(0, 2), 3012077365a9SGeert Uytterhoeven }; 3013077365a9SGeert Uytterhoeven static const unsigned int msiof3_rxd_a_mux[] = { 3014077365a9SGeert Uytterhoeven MSIOF3_RXD_A_MARK, 3015077365a9SGeert Uytterhoeven }; 3016077365a9SGeert Uytterhoeven static const unsigned int msiof3_clk_b_pins[] = { 3017077365a9SGeert Uytterhoeven /* SCK */ 3018077365a9SGeert Uytterhoeven RCAR_GP_PIN(1, 2), 3019077365a9SGeert Uytterhoeven }; 3020077365a9SGeert Uytterhoeven static const unsigned int msiof3_clk_b_mux[] = { 3021077365a9SGeert Uytterhoeven MSIOF3_SCK_B_MARK, 3022077365a9SGeert Uytterhoeven }; 3023077365a9SGeert Uytterhoeven static const unsigned int msiof3_sync_b_pins[] = { 3024077365a9SGeert Uytterhoeven /* SYNC */ 3025077365a9SGeert Uytterhoeven RCAR_GP_PIN(1, 0), 3026077365a9SGeert Uytterhoeven }; 3027077365a9SGeert Uytterhoeven static const unsigned int msiof3_sync_b_mux[] = { 3028077365a9SGeert Uytterhoeven MSIOF3_SYNC_B_MARK, 3029077365a9SGeert Uytterhoeven }; 3030077365a9SGeert Uytterhoeven static const unsigned int msiof3_ss1_b_pins[] = { 3031077365a9SGeert Uytterhoeven /* SS1 */ 3032077365a9SGeert Uytterhoeven RCAR_GP_PIN(1, 4), 3033077365a9SGeert Uytterhoeven }; 3034077365a9SGeert Uytterhoeven static const unsigned int msiof3_ss1_b_mux[] = { 3035077365a9SGeert Uytterhoeven MSIOF3_SS1_B_MARK, 3036077365a9SGeert Uytterhoeven }; 3037077365a9SGeert Uytterhoeven static const unsigned int msiof3_ss2_b_pins[] = { 3038077365a9SGeert Uytterhoeven /* SS2 */ 3039077365a9SGeert Uytterhoeven RCAR_GP_PIN(1, 5), 3040077365a9SGeert Uytterhoeven }; 3041077365a9SGeert Uytterhoeven static const unsigned int msiof3_ss2_b_mux[] = { 3042077365a9SGeert Uytterhoeven MSIOF3_SS2_B_MARK, 3043077365a9SGeert Uytterhoeven }; 3044077365a9SGeert Uytterhoeven static const unsigned int msiof3_txd_b_pins[] = { 3045077365a9SGeert Uytterhoeven /* TXD */ 3046077365a9SGeert Uytterhoeven RCAR_GP_PIN(1, 1), 3047077365a9SGeert Uytterhoeven }; 3048077365a9SGeert Uytterhoeven static const unsigned int msiof3_txd_b_mux[] = { 3049077365a9SGeert Uytterhoeven MSIOF3_TXD_B_MARK, 3050077365a9SGeert Uytterhoeven }; 3051077365a9SGeert Uytterhoeven static const unsigned int msiof3_rxd_b_pins[] = { 3052077365a9SGeert Uytterhoeven /* RXD */ 3053077365a9SGeert Uytterhoeven RCAR_GP_PIN(1, 3), 3054077365a9SGeert Uytterhoeven }; 3055077365a9SGeert Uytterhoeven static const unsigned int msiof3_rxd_b_mux[] = { 3056077365a9SGeert Uytterhoeven MSIOF3_RXD_B_MARK, 3057077365a9SGeert Uytterhoeven }; 3058077365a9SGeert Uytterhoeven static const unsigned int msiof3_clk_c_pins[] = { 3059077365a9SGeert Uytterhoeven /* SCK */ 3060077365a9SGeert Uytterhoeven RCAR_GP_PIN(1, 12), 3061077365a9SGeert Uytterhoeven }; 3062077365a9SGeert Uytterhoeven static const unsigned int msiof3_clk_c_mux[] = { 3063077365a9SGeert Uytterhoeven MSIOF3_SCK_C_MARK, 3064077365a9SGeert Uytterhoeven }; 3065077365a9SGeert Uytterhoeven static const unsigned int msiof3_sync_c_pins[] = { 3066077365a9SGeert Uytterhoeven /* SYNC */ 3067077365a9SGeert Uytterhoeven RCAR_GP_PIN(1, 13), 3068077365a9SGeert Uytterhoeven }; 3069077365a9SGeert Uytterhoeven static const unsigned int msiof3_sync_c_mux[] = { 3070077365a9SGeert Uytterhoeven MSIOF3_SYNC_C_MARK, 3071077365a9SGeert Uytterhoeven }; 3072077365a9SGeert Uytterhoeven static const unsigned int msiof3_txd_c_pins[] = { 3073077365a9SGeert Uytterhoeven /* TXD */ 3074077365a9SGeert Uytterhoeven RCAR_GP_PIN(1, 15), 3075077365a9SGeert Uytterhoeven }; 3076077365a9SGeert Uytterhoeven static const unsigned int msiof3_txd_c_mux[] = { 3077077365a9SGeert Uytterhoeven MSIOF3_TXD_C_MARK, 3078077365a9SGeert Uytterhoeven }; 3079077365a9SGeert Uytterhoeven static const unsigned int msiof3_rxd_c_pins[] = { 3080077365a9SGeert Uytterhoeven /* RXD */ 3081077365a9SGeert Uytterhoeven RCAR_GP_PIN(1, 14), 3082077365a9SGeert Uytterhoeven }; 3083077365a9SGeert Uytterhoeven static const unsigned int msiof3_rxd_c_mux[] = { 3084077365a9SGeert Uytterhoeven MSIOF3_RXD_C_MARK, 3085077365a9SGeert Uytterhoeven }; 3086077365a9SGeert Uytterhoeven static const unsigned int msiof3_clk_d_pins[] = { 3087077365a9SGeert Uytterhoeven /* SCK */ 3088077365a9SGeert Uytterhoeven RCAR_GP_PIN(1, 22), 3089077365a9SGeert Uytterhoeven }; 3090077365a9SGeert Uytterhoeven static const unsigned int msiof3_clk_d_mux[] = { 3091077365a9SGeert Uytterhoeven MSIOF3_SCK_D_MARK, 3092077365a9SGeert Uytterhoeven }; 3093077365a9SGeert Uytterhoeven static const unsigned int msiof3_sync_d_pins[] = { 3094077365a9SGeert Uytterhoeven /* SYNC */ 3095077365a9SGeert Uytterhoeven RCAR_GP_PIN(1, 23), 3096077365a9SGeert Uytterhoeven }; 3097077365a9SGeert Uytterhoeven static const unsigned int msiof3_sync_d_mux[] = { 3098077365a9SGeert Uytterhoeven MSIOF3_SYNC_D_MARK, 3099077365a9SGeert Uytterhoeven }; 3100077365a9SGeert Uytterhoeven static const unsigned int msiof3_ss1_d_pins[] = { 3101077365a9SGeert Uytterhoeven /* SS1 */ 3102077365a9SGeert Uytterhoeven RCAR_GP_PIN(1, 26), 3103077365a9SGeert Uytterhoeven }; 3104077365a9SGeert Uytterhoeven static const unsigned int msiof3_ss1_d_mux[] = { 3105077365a9SGeert Uytterhoeven MSIOF3_SS1_D_MARK, 3106077365a9SGeert Uytterhoeven }; 3107077365a9SGeert Uytterhoeven static const unsigned int msiof3_txd_d_pins[] = { 3108077365a9SGeert Uytterhoeven /* TXD */ 3109077365a9SGeert Uytterhoeven RCAR_GP_PIN(1, 25), 3110077365a9SGeert Uytterhoeven }; 3111077365a9SGeert Uytterhoeven static const unsigned int msiof3_txd_d_mux[] = { 3112077365a9SGeert Uytterhoeven MSIOF3_TXD_D_MARK, 3113077365a9SGeert Uytterhoeven }; 3114077365a9SGeert Uytterhoeven static const unsigned int msiof3_rxd_d_pins[] = { 3115077365a9SGeert Uytterhoeven /* RXD */ 3116077365a9SGeert Uytterhoeven RCAR_GP_PIN(1, 24), 3117077365a9SGeert Uytterhoeven }; 3118077365a9SGeert Uytterhoeven static const unsigned int msiof3_rxd_d_mux[] = { 3119077365a9SGeert Uytterhoeven MSIOF3_RXD_D_MARK, 3120077365a9SGeert Uytterhoeven }; 3121077365a9SGeert Uytterhoeven static const unsigned int msiof3_clk_e_pins[] = { 3122077365a9SGeert Uytterhoeven /* SCK */ 3123077365a9SGeert Uytterhoeven RCAR_GP_PIN(2, 3), 3124077365a9SGeert Uytterhoeven }; 3125077365a9SGeert Uytterhoeven static const unsigned int msiof3_clk_e_mux[] = { 3126077365a9SGeert Uytterhoeven MSIOF3_SCK_E_MARK, 3127077365a9SGeert Uytterhoeven }; 3128077365a9SGeert Uytterhoeven static const unsigned int msiof3_sync_e_pins[] = { 3129077365a9SGeert Uytterhoeven /* SYNC */ 3130077365a9SGeert Uytterhoeven RCAR_GP_PIN(2, 2), 3131077365a9SGeert Uytterhoeven }; 3132077365a9SGeert Uytterhoeven static const unsigned int msiof3_sync_e_mux[] = { 3133077365a9SGeert Uytterhoeven MSIOF3_SYNC_E_MARK, 3134077365a9SGeert Uytterhoeven }; 3135077365a9SGeert Uytterhoeven static const unsigned int msiof3_ss1_e_pins[] = { 3136077365a9SGeert Uytterhoeven /* SS1 */ 3137077365a9SGeert Uytterhoeven RCAR_GP_PIN(2, 1), 3138077365a9SGeert Uytterhoeven }; 3139077365a9SGeert Uytterhoeven static const unsigned int msiof3_ss1_e_mux[] = { 3140077365a9SGeert Uytterhoeven MSIOF3_SS1_E_MARK, 3141077365a9SGeert Uytterhoeven }; 3142077365a9SGeert Uytterhoeven static const unsigned int msiof3_ss2_e_pins[] = { 3143077365a9SGeert Uytterhoeven /* SS2 */ 3144077365a9SGeert Uytterhoeven RCAR_GP_PIN(2, 0), 3145077365a9SGeert Uytterhoeven }; 3146077365a9SGeert Uytterhoeven static const unsigned int msiof3_ss2_e_mux[] = { 3147077365a9SGeert Uytterhoeven MSIOF3_SS2_E_MARK, 3148077365a9SGeert Uytterhoeven }; 3149077365a9SGeert Uytterhoeven static const unsigned int msiof3_txd_e_pins[] = { 3150077365a9SGeert Uytterhoeven /* TXD */ 3151077365a9SGeert Uytterhoeven RCAR_GP_PIN(2, 5), 3152077365a9SGeert Uytterhoeven }; 3153077365a9SGeert Uytterhoeven static const unsigned int msiof3_txd_e_mux[] = { 3154077365a9SGeert Uytterhoeven MSIOF3_TXD_E_MARK, 3155077365a9SGeert Uytterhoeven }; 3156077365a9SGeert Uytterhoeven static const unsigned int msiof3_rxd_e_pins[] = { 3157077365a9SGeert Uytterhoeven /* RXD */ 3158077365a9SGeert Uytterhoeven RCAR_GP_PIN(2, 4), 3159077365a9SGeert Uytterhoeven }; 3160077365a9SGeert Uytterhoeven static const unsigned int msiof3_rxd_e_mux[] = { 3161077365a9SGeert Uytterhoeven MSIOF3_RXD_E_MARK, 3162077365a9SGeert Uytterhoeven }; 3163077365a9SGeert Uytterhoeven 3164077365a9SGeert Uytterhoeven /* - PWM0 --------------------------------------------------------------------*/ 3165077365a9SGeert Uytterhoeven static const unsigned int pwm0_pins[] = { 3166077365a9SGeert Uytterhoeven /* PWM */ 3167077365a9SGeert Uytterhoeven RCAR_GP_PIN(2, 6), 3168077365a9SGeert Uytterhoeven }; 3169077365a9SGeert Uytterhoeven static const unsigned int pwm0_mux[] = { 3170077365a9SGeert Uytterhoeven PWM0_MARK, 3171077365a9SGeert Uytterhoeven }; 3172077365a9SGeert Uytterhoeven /* - PWM1 --------------------------------------------------------------------*/ 3173077365a9SGeert Uytterhoeven static const unsigned int pwm1_a_pins[] = { 3174077365a9SGeert Uytterhoeven /* PWM */ 3175077365a9SGeert Uytterhoeven RCAR_GP_PIN(2, 7), 3176077365a9SGeert Uytterhoeven }; 3177077365a9SGeert Uytterhoeven static const unsigned int pwm1_a_mux[] = { 3178077365a9SGeert Uytterhoeven PWM1_A_MARK, 3179077365a9SGeert Uytterhoeven }; 3180077365a9SGeert Uytterhoeven static const unsigned int pwm1_b_pins[] = { 3181077365a9SGeert Uytterhoeven /* PWM */ 3182077365a9SGeert Uytterhoeven RCAR_GP_PIN(1, 8), 3183077365a9SGeert Uytterhoeven }; 3184077365a9SGeert Uytterhoeven static const unsigned int pwm1_b_mux[] = { 3185077365a9SGeert Uytterhoeven PWM1_B_MARK, 3186077365a9SGeert Uytterhoeven }; 3187077365a9SGeert Uytterhoeven /* - PWM2 --------------------------------------------------------------------*/ 3188077365a9SGeert Uytterhoeven static const unsigned int pwm2_a_pins[] = { 3189077365a9SGeert Uytterhoeven /* PWM */ 3190077365a9SGeert Uytterhoeven RCAR_GP_PIN(2, 8), 3191077365a9SGeert Uytterhoeven }; 3192077365a9SGeert Uytterhoeven static const unsigned int pwm2_a_mux[] = { 3193077365a9SGeert Uytterhoeven PWM2_A_MARK, 3194077365a9SGeert Uytterhoeven }; 3195077365a9SGeert Uytterhoeven static const unsigned int pwm2_b_pins[] = { 3196077365a9SGeert Uytterhoeven /* PWM */ 3197077365a9SGeert Uytterhoeven RCAR_GP_PIN(1, 11), 3198077365a9SGeert Uytterhoeven }; 3199077365a9SGeert Uytterhoeven static const unsigned int pwm2_b_mux[] = { 3200077365a9SGeert Uytterhoeven PWM2_B_MARK, 3201077365a9SGeert Uytterhoeven }; 3202077365a9SGeert Uytterhoeven /* - PWM3 --------------------------------------------------------------------*/ 3203077365a9SGeert Uytterhoeven static const unsigned int pwm3_a_pins[] = { 3204077365a9SGeert Uytterhoeven /* PWM */ 3205077365a9SGeert Uytterhoeven RCAR_GP_PIN(1, 0), 3206077365a9SGeert Uytterhoeven }; 3207077365a9SGeert Uytterhoeven static const unsigned int pwm3_a_mux[] = { 3208077365a9SGeert Uytterhoeven PWM3_A_MARK, 3209077365a9SGeert Uytterhoeven }; 3210077365a9SGeert Uytterhoeven static const unsigned int pwm3_b_pins[] = { 3211077365a9SGeert Uytterhoeven /* PWM */ 3212077365a9SGeert Uytterhoeven RCAR_GP_PIN(2, 2), 3213077365a9SGeert Uytterhoeven }; 3214077365a9SGeert Uytterhoeven static const unsigned int pwm3_b_mux[] = { 3215077365a9SGeert Uytterhoeven PWM3_B_MARK, 3216077365a9SGeert Uytterhoeven }; 3217077365a9SGeert Uytterhoeven /* - PWM4 --------------------------------------------------------------------*/ 3218077365a9SGeert Uytterhoeven static const unsigned int pwm4_a_pins[] = { 3219077365a9SGeert Uytterhoeven /* PWM */ 3220077365a9SGeert Uytterhoeven RCAR_GP_PIN(1, 1), 3221077365a9SGeert Uytterhoeven }; 3222077365a9SGeert Uytterhoeven static const unsigned int pwm4_a_mux[] = { 3223077365a9SGeert Uytterhoeven PWM4_A_MARK, 3224077365a9SGeert Uytterhoeven }; 3225077365a9SGeert Uytterhoeven static const unsigned int pwm4_b_pins[] = { 3226077365a9SGeert Uytterhoeven /* PWM */ 3227077365a9SGeert Uytterhoeven RCAR_GP_PIN(2, 3), 3228077365a9SGeert Uytterhoeven }; 3229077365a9SGeert Uytterhoeven static const unsigned int pwm4_b_mux[] = { 3230077365a9SGeert Uytterhoeven PWM4_B_MARK, 3231077365a9SGeert Uytterhoeven }; 3232077365a9SGeert Uytterhoeven /* - PWM5 --------------------------------------------------------------------*/ 3233077365a9SGeert Uytterhoeven static const unsigned int pwm5_a_pins[] = { 3234077365a9SGeert Uytterhoeven /* PWM */ 3235077365a9SGeert Uytterhoeven RCAR_GP_PIN(1, 2), 3236077365a9SGeert Uytterhoeven }; 3237077365a9SGeert Uytterhoeven static const unsigned int pwm5_a_mux[] = { 3238077365a9SGeert Uytterhoeven PWM5_A_MARK, 3239077365a9SGeert Uytterhoeven }; 3240077365a9SGeert Uytterhoeven static const unsigned int pwm5_b_pins[] = { 3241077365a9SGeert Uytterhoeven /* PWM */ 3242077365a9SGeert Uytterhoeven RCAR_GP_PIN(2, 4), 3243077365a9SGeert Uytterhoeven }; 3244077365a9SGeert Uytterhoeven static const unsigned int pwm5_b_mux[] = { 3245077365a9SGeert Uytterhoeven PWM5_B_MARK, 3246077365a9SGeert Uytterhoeven }; 3247077365a9SGeert Uytterhoeven /* - PWM6 --------------------------------------------------------------------*/ 3248077365a9SGeert Uytterhoeven static const unsigned int pwm6_a_pins[] = { 3249077365a9SGeert Uytterhoeven /* PWM */ 3250077365a9SGeert Uytterhoeven RCAR_GP_PIN(1, 3), 3251077365a9SGeert Uytterhoeven }; 3252077365a9SGeert Uytterhoeven static const unsigned int pwm6_a_mux[] = { 3253077365a9SGeert Uytterhoeven PWM6_A_MARK, 3254077365a9SGeert Uytterhoeven }; 3255077365a9SGeert Uytterhoeven static const unsigned int pwm6_b_pins[] = { 3256077365a9SGeert Uytterhoeven /* PWM */ 3257077365a9SGeert Uytterhoeven RCAR_GP_PIN(2, 5), 3258077365a9SGeert Uytterhoeven }; 3259077365a9SGeert Uytterhoeven static const unsigned int pwm6_b_mux[] = { 3260077365a9SGeert Uytterhoeven PWM6_B_MARK, 3261077365a9SGeert Uytterhoeven }; 3262077365a9SGeert Uytterhoeven 3263590567bfSLad Prabhakar /* - QSPI0 ------------------------------------------------------------------ */ 3264590567bfSLad Prabhakar static const unsigned int qspi0_ctrl_pins[] = { 3265590567bfSLad Prabhakar /* QSPI0_SPCLK, QSPI0_SSL */ 3266590567bfSLad Prabhakar PIN_QSPI0_SPCLK, PIN_QSPI0_SSL, 3267590567bfSLad Prabhakar }; 3268590567bfSLad Prabhakar static const unsigned int qspi0_ctrl_mux[] = { 3269590567bfSLad Prabhakar QSPI0_SPCLK_MARK, QSPI0_SSL_MARK, 3270590567bfSLad Prabhakar }; 3271aaf186d8SGeert Uytterhoeven static const unsigned int qspi0_data_pins[] = { 3272590567bfSLad Prabhakar /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */ 3273590567bfSLad Prabhakar PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1, 3274590567bfSLad Prabhakar /* QSPI0_IO2, QSPI0_IO3 */ 3275590567bfSLad Prabhakar PIN_QSPI0_IO2, PIN_QSPI0_IO3, 3276590567bfSLad Prabhakar }; 3277aaf186d8SGeert Uytterhoeven static const unsigned int qspi0_data_mux[] = { 3278590567bfSLad Prabhakar QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, 3279590567bfSLad Prabhakar QSPI0_IO2_MARK, QSPI0_IO3_MARK, 3280590567bfSLad Prabhakar }; 3281590567bfSLad Prabhakar /* - QSPI1 ------------------------------------------------------------------ */ 3282590567bfSLad Prabhakar static const unsigned int qspi1_ctrl_pins[] = { 3283590567bfSLad Prabhakar /* QSPI1_SPCLK, QSPI1_SSL */ 3284590567bfSLad Prabhakar PIN_QSPI1_SPCLK, PIN_QSPI1_SSL, 3285590567bfSLad Prabhakar }; 3286590567bfSLad Prabhakar static const unsigned int qspi1_ctrl_mux[] = { 3287590567bfSLad Prabhakar QSPI1_SPCLK_MARK, QSPI1_SSL_MARK, 3288590567bfSLad Prabhakar }; 3289aaf186d8SGeert Uytterhoeven static const unsigned int qspi1_data_pins[] = { 3290590567bfSLad Prabhakar /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */ 3291590567bfSLad Prabhakar PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1, 3292590567bfSLad Prabhakar /* QSPI1_IO2, QSPI1_IO3 */ 3293590567bfSLad Prabhakar PIN_QSPI1_IO2, PIN_QSPI1_IO3, 3294590567bfSLad Prabhakar }; 3295aaf186d8SGeert Uytterhoeven static const unsigned int qspi1_data_mux[] = { 3296590567bfSLad Prabhakar QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, 3297590567bfSLad Prabhakar QSPI1_IO2_MARK, QSPI1_IO3_MARK, 3298590567bfSLad Prabhakar }; 3299590567bfSLad Prabhakar 3300077365a9SGeert Uytterhoeven /* - SATA --------------------------------------------------------------------*/ 3301077365a9SGeert Uytterhoeven static const unsigned int sata0_devslp_a_pins[] = { 3302077365a9SGeert Uytterhoeven /* DEVSLP */ 3303077365a9SGeert Uytterhoeven RCAR_GP_PIN(6, 16), 3304077365a9SGeert Uytterhoeven }; 3305077365a9SGeert Uytterhoeven static const unsigned int sata0_devslp_a_mux[] = { 3306077365a9SGeert Uytterhoeven SATA_DEVSLP_A_MARK, 3307077365a9SGeert Uytterhoeven }; 3308077365a9SGeert Uytterhoeven static const unsigned int sata0_devslp_b_pins[] = { 3309077365a9SGeert Uytterhoeven /* DEVSLP */ 3310077365a9SGeert Uytterhoeven RCAR_GP_PIN(4, 6), 3311077365a9SGeert Uytterhoeven }; 3312077365a9SGeert Uytterhoeven static const unsigned int sata0_devslp_b_mux[] = { 3313077365a9SGeert Uytterhoeven SATA_DEVSLP_B_MARK, 3314077365a9SGeert Uytterhoeven }; 3315077365a9SGeert Uytterhoeven 3316077365a9SGeert Uytterhoeven /* - SCIF0 ------------------------------------------------------------------ */ 3317077365a9SGeert Uytterhoeven static const unsigned int scif0_data_pins[] = { 3318077365a9SGeert Uytterhoeven /* RX, TX */ 3319077365a9SGeert Uytterhoeven RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), 3320077365a9SGeert Uytterhoeven }; 3321077365a9SGeert Uytterhoeven static const unsigned int scif0_data_mux[] = { 3322077365a9SGeert Uytterhoeven RX0_MARK, TX0_MARK, 3323077365a9SGeert Uytterhoeven }; 3324077365a9SGeert Uytterhoeven static const unsigned int scif0_clk_pins[] = { 3325077365a9SGeert Uytterhoeven /* SCK */ 3326077365a9SGeert Uytterhoeven RCAR_GP_PIN(5, 0), 3327077365a9SGeert Uytterhoeven }; 3328077365a9SGeert Uytterhoeven static const unsigned int scif0_clk_mux[] = { 3329077365a9SGeert Uytterhoeven SCK0_MARK, 3330077365a9SGeert Uytterhoeven }; 3331077365a9SGeert Uytterhoeven static const unsigned int scif0_ctrl_pins[] = { 3332077365a9SGeert Uytterhoeven /* RTS, CTS */ 3333077365a9SGeert Uytterhoeven RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3), 3334077365a9SGeert Uytterhoeven }; 3335077365a9SGeert Uytterhoeven static const unsigned int scif0_ctrl_mux[] = { 3336077365a9SGeert Uytterhoeven RTS0_N_MARK, CTS0_N_MARK, 3337077365a9SGeert Uytterhoeven }; 3338077365a9SGeert Uytterhoeven /* - SCIF1 ------------------------------------------------------------------ */ 3339077365a9SGeert Uytterhoeven static const unsigned int scif1_data_a_pins[] = { 3340077365a9SGeert Uytterhoeven /* RX, TX */ 3341077365a9SGeert Uytterhoeven RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6), 3342077365a9SGeert Uytterhoeven }; 3343077365a9SGeert Uytterhoeven static const unsigned int scif1_data_a_mux[] = { 3344077365a9SGeert Uytterhoeven RX1_A_MARK, TX1_A_MARK, 3345077365a9SGeert Uytterhoeven }; 3346077365a9SGeert Uytterhoeven static const unsigned int scif1_clk_pins[] = { 3347077365a9SGeert Uytterhoeven /* SCK */ 3348077365a9SGeert Uytterhoeven RCAR_GP_PIN(6, 21), 3349077365a9SGeert Uytterhoeven }; 3350077365a9SGeert Uytterhoeven static const unsigned int scif1_clk_mux[] = { 3351077365a9SGeert Uytterhoeven SCK1_MARK, 3352077365a9SGeert Uytterhoeven }; 3353077365a9SGeert Uytterhoeven static const unsigned int scif1_ctrl_pins[] = { 3354077365a9SGeert Uytterhoeven /* RTS, CTS */ 3355077365a9SGeert Uytterhoeven RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7), 3356077365a9SGeert Uytterhoeven }; 3357077365a9SGeert Uytterhoeven static const unsigned int scif1_ctrl_mux[] = { 3358077365a9SGeert Uytterhoeven RTS1_N_MARK, CTS1_N_MARK, 3359077365a9SGeert Uytterhoeven }; 3360077365a9SGeert Uytterhoeven 3361077365a9SGeert Uytterhoeven static const unsigned int scif1_data_b_pins[] = { 3362077365a9SGeert Uytterhoeven /* RX, TX */ 3363077365a9SGeert Uytterhoeven RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25), 3364077365a9SGeert Uytterhoeven }; 3365077365a9SGeert Uytterhoeven static const unsigned int scif1_data_b_mux[] = { 3366077365a9SGeert Uytterhoeven RX1_B_MARK, TX1_B_MARK, 3367077365a9SGeert Uytterhoeven }; 3368077365a9SGeert Uytterhoeven /* - SCIF2 ------------------------------------------------------------------ */ 3369077365a9SGeert Uytterhoeven static const unsigned int scif2_data_a_pins[] = { 3370077365a9SGeert Uytterhoeven /* RX, TX */ 3371077365a9SGeert Uytterhoeven RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10), 3372077365a9SGeert Uytterhoeven }; 3373077365a9SGeert Uytterhoeven static const unsigned int scif2_data_a_mux[] = { 3374077365a9SGeert Uytterhoeven RX2_A_MARK, TX2_A_MARK, 3375077365a9SGeert Uytterhoeven }; 3376077365a9SGeert Uytterhoeven static const unsigned int scif2_clk_pins[] = { 3377077365a9SGeert Uytterhoeven /* SCK */ 3378077365a9SGeert Uytterhoeven RCAR_GP_PIN(5, 9), 3379077365a9SGeert Uytterhoeven }; 3380077365a9SGeert Uytterhoeven static const unsigned int scif2_clk_mux[] = { 3381077365a9SGeert Uytterhoeven SCK2_MARK, 3382077365a9SGeert Uytterhoeven }; 3383077365a9SGeert Uytterhoeven static const unsigned int scif2_data_b_pins[] = { 3384077365a9SGeert Uytterhoeven /* RX, TX */ 3385077365a9SGeert Uytterhoeven RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16), 3386077365a9SGeert Uytterhoeven }; 3387077365a9SGeert Uytterhoeven static const unsigned int scif2_data_b_mux[] = { 3388077365a9SGeert Uytterhoeven RX2_B_MARK, TX2_B_MARK, 3389077365a9SGeert Uytterhoeven }; 3390077365a9SGeert Uytterhoeven /* - SCIF3 ------------------------------------------------------------------ */ 3391077365a9SGeert Uytterhoeven static const unsigned int scif3_data_a_pins[] = { 3392077365a9SGeert Uytterhoeven /* RX, TX */ 3393077365a9SGeert Uytterhoeven RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24), 3394077365a9SGeert Uytterhoeven }; 3395077365a9SGeert Uytterhoeven static const unsigned int scif3_data_a_mux[] = { 3396077365a9SGeert Uytterhoeven RX3_A_MARK, TX3_A_MARK, 3397077365a9SGeert Uytterhoeven }; 3398077365a9SGeert Uytterhoeven static const unsigned int scif3_clk_pins[] = { 3399077365a9SGeert Uytterhoeven /* SCK */ 3400077365a9SGeert Uytterhoeven RCAR_GP_PIN(1, 22), 3401077365a9SGeert Uytterhoeven }; 3402077365a9SGeert Uytterhoeven static const unsigned int scif3_clk_mux[] = { 3403077365a9SGeert Uytterhoeven SCK3_MARK, 3404077365a9SGeert Uytterhoeven }; 3405077365a9SGeert Uytterhoeven static const unsigned int scif3_ctrl_pins[] = { 3406077365a9SGeert Uytterhoeven /* RTS, CTS */ 3407077365a9SGeert Uytterhoeven RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25), 3408077365a9SGeert Uytterhoeven }; 3409077365a9SGeert Uytterhoeven static const unsigned int scif3_ctrl_mux[] = { 3410077365a9SGeert Uytterhoeven RTS3_N_MARK, CTS3_N_MARK, 3411077365a9SGeert Uytterhoeven }; 3412077365a9SGeert Uytterhoeven static const unsigned int scif3_data_b_pins[] = { 3413077365a9SGeert Uytterhoeven /* RX, TX */ 3414077365a9SGeert Uytterhoeven RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), 3415077365a9SGeert Uytterhoeven }; 3416077365a9SGeert Uytterhoeven static const unsigned int scif3_data_b_mux[] = { 3417077365a9SGeert Uytterhoeven RX3_B_MARK, TX3_B_MARK, 3418077365a9SGeert Uytterhoeven }; 3419077365a9SGeert Uytterhoeven /* - SCIF4 ------------------------------------------------------------------ */ 3420077365a9SGeert Uytterhoeven static const unsigned int scif4_data_a_pins[] = { 3421077365a9SGeert Uytterhoeven /* RX, TX */ 3422077365a9SGeert Uytterhoeven RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12), 3423077365a9SGeert Uytterhoeven }; 3424077365a9SGeert Uytterhoeven static const unsigned int scif4_data_a_mux[] = { 3425077365a9SGeert Uytterhoeven RX4_A_MARK, TX4_A_MARK, 3426077365a9SGeert Uytterhoeven }; 3427077365a9SGeert Uytterhoeven static const unsigned int scif4_clk_a_pins[] = { 3428077365a9SGeert Uytterhoeven /* SCK */ 3429077365a9SGeert Uytterhoeven RCAR_GP_PIN(2, 10), 3430077365a9SGeert Uytterhoeven }; 3431077365a9SGeert Uytterhoeven static const unsigned int scif4_clk_a_mux[] = { 3432077365a9SGeert Uytterhoeven SCK4_A_MARK, 3433077365a9SGeert Uytterhoeven }; 3434077365a9SGeert Uytterhoeven static const unsigned int scif4_ctrl_a_pins[] = { 3435077365a9SGeert Uytterhoeven /* RTS, CTS */ 3436077365a9SGeert Uytterhoeven RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13), 3437077365a9SGeert Uytterhoeven }; 3438077365a9SGeert Uytterhoeven static const unsigned int scif4_ctrl_a_mux[] = { 3439077365a9SGeert Uytterhoeven RTS4_N_A_MARK, CTS4_N_A_MARK, 3440077365a9SGeert Uytterhoeven }; 3441077365a9SGeert Uytterhoeven static const unsigned int scif4_data_b_pins[] = { 3442077365a9SGeert Uytterhoeven /* RX, TX */ 3443077365a9SGeert Uytterhoeven RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 3444077365a9SGeert Uytterhoeven }; 3445077365a9SGeert Uytterhoeven static const unsigned int scif4_data_b_mux[] = { 3446077365a9SGeert Uytterhoeven RX4_B_MARK, TX4_B_MARK, 3447077365a9SGeert Uytterhoeven }; 3448077365a9SGeert Uytterhoeven static const unsigned int scif4_clk_b_pins[] = { 3449077365a9SGeert Uytterhoeven /* SCK */ 3450077365a9SGeert Uytterhoeven RCAR_GP_PIN(1, 5), 3451077365a9SGeert Uytterhoeven }; 3452077365a9SGeert Uytterhoeven static const unsigned int scif4_clk_b_mux[] = { 3453077365a9SGeert Uytterhoeven SCK4_B_MARK, 3454077365a9SGeert Uytterhoeven }; 3455077365a9SGeert Uytterhoeven static const unsigned int scif4_ctrl_b_pins[] = { 3456077365a9SGeert Uytterhoeven /* RTS, CTS */ 3457077365a9SGeert Uytterhoeven RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9), 3458077365a9SGeert Uytterhoeven }; 3459077365a9SGeert Uytterhoeven static const unsigned int scif4_ctrl_b_mux[] = { 3460077365a9SGeert Uytterhoeven RTS4_N_B_MARK, CTS4_N_B_MARK, 3461077365a9SGeert Uytterhoeven }; 3462077365a9SGeert Uytterhoeven static const unsigned int scif4_data_c_pins[] = { 3463077365a9SGeert Uytterhoeven /* RX, TX */ 3464077365a9SGeert Uytterhoeven RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), 3465077365a9SGeert Uytterhoeven }; 3466077365a9SGeert Uytterhoeven static const unsigned int scif4_data_c_mux[] = { 3467077365a9SGeert Uytterhoeven RX4_C_MARK, TX4_C_MARK, 3468077365a9SGeert Uytterhoeven }; 3469077365a9SGeert Uytterhoeven static const unsigned int scif4_clk_c_pins[] = { 3470077365a9SGeert Uytterhoeven /* SCK */ 3471077365a9SGeert Uytterhoeven RCAR_GP_PIN(0, 8), 3472077365a9SGeert Uytterhoeven }; 3473077365a9SGeert Uytterhoeven static const unsigned int scif4_clk_c_mux[] = { 3474077365a9SGeert Uytterhoeven SCK4_C_MARK, 3475077365a9SGeert Uytterhoeven }; 3476077365a9SGeert Uytterhoeven static const unsigned int scif4_ctrl_c_pins[] = { 3477077365a9SGeert Uytterhoeven /* RTS, CTS */ 3478077365a9SGeert Uytterhoeven RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), 3479077365a9SGeert Uytterhoeven }; 3480077365a9SGeert Uytterhoeven static const unsigned int scif4_ctrl_c_mux[] = { 3481077365a9SGeert Uytterhoeven RTS4_N_C_MARK, CTS4_N_C_MARK, 3482077365a9SGeert Uytterhoeven }; 3483077365a9SGeert Uytterhoeven /* - SCIF5 ------------------------------------------------------------------ */ 3484077365a9SGeert Uytterhoeven static const unsigned int scif5_data_a_pins[] = { 3485077365a9SGeert Uytterhoeven /* RX, TX */ 3486077365a9SGeert Uytterhoeven RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21), 3487077365a9SGeert Uytterhoeven }; 3488077365a9SGeert Uytterhoeven static const unsigned int scif5_data_a_mux[] = { 3489077365a9SGeert Uytterhoeven RX5_A_MARK, TX5_A_MARK, 3490077365a9SGeert Uytterhoeven }; 3491077365a9SGeert Uytterhoeven static const unsigned int scif5_clk_a_pins[] = { 3492077365a9SGeert Uytterhoeven /* SCK */ 3493077365a9SGeert Uytterhoeven RCAR_GP_PIN(6, 21), 3494077365a9SGeert Uytterhoeven }; 3495077365a9SGeert Uytterhoeven static const unsigned int scif5_clk_a_mux[] = { 3496077365a9SGeert Uytterhoeven SCK5_A_MARK, 3497077365a9SGeert Uytterhoeven }; 3498077365a9SGeert Uytterhoeven static const unsigned int scif5_data_b_pins[] = { 3499077365a9SGeert Uytterhoeven /* RX, TX */ 3500077365a9SGeert Uytterhoeven RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18), 3501077365a9SGeert Uytterhoeven }; 3502077365a9SGeert Uytterhoeven static const unsigned int scif5_data_b_mux[] = { 3503077365a9SGeert Uytterhoeven RX5_B_MARK, TX5_B_MARK, 3504077365a9SGeert Uytterhoeven }; 3505077365a9SGeert Uytterhoeven static const unsigned int scif5_clk_b_pins[] = { 3506077365a9SGeert Uytterhoeven /* SCK */ 3507077365a9SGeert Uytterhoeven RCAR_GP_PIN(5, 0), 3508077365a9SGeert Uytterhoeven }; 3509077365a9SGeert Uytterhoeven static const unsigned int scif5_clk_b_mux[] = { 3510077365a9SGeert Uytterhoeven SCK5_B_MARK, 3511077365a9SGeert Uytterhoeven }; 3512077365a9SGeert Uytterhoeven 3513077365a9SGeert Uytterhoeven /* - SCIF Clock ------------------------------------------------------------- */ 3514077365a9SGeert Uytterhoeven static const unsigned int scif_clk_a_pins[] = { 3515077365a9SGeert Uytterhoeven /* SCIF_CLK */ 3516077365a9SGeert Uytterhoeven RCAR_GP_PIN(6, 23), 3517077365a9SGeert Uytterhoeven }; 3518077365a9SGeert Uytterhoeven static const unsigned int scif_clk_a_mux[] = { 3519077365a9SGeert Uytterhoeven SCIF_CLK_A_MARK, 3520077365a9SGeert Uytterhoeven }; 3521077365a9SGeert Uytterhoeven static const unsigned int scif_clk_b_pins[] = { 3522077365a9SGeert Uytterhoeven /* SCIF_CLK */ 3523077365a9SGeert Uytterhoeven RCAR_GP_PIN(5, 9), 3524077365a9SGeert Uytterhoeven }; 3525077365a9SGeert Uytterhoeven static const unsigned int scif_clk_b_mux[] = { 3526077365a9SGeert Uytterhoeven SCIF_CLK_B_MARK, 3527077365a9SGeert Uytterhoeven }; 3528077365a9SGeert Uytterhoeven 3529077365a9SGeert Uytterhoeven /* - SDHI0 ------------------------------------------------------------------ */ 3530c8c05e81SGeert Uytterhoeven static const unsigned int sdhi0_data_pins[] = { 3531077365a9SGeert Uytterhoeven /* D[0:3] */ 3532077365a9SGeert Uytterhoeven RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), 3533077365a9SGeert Uytterhoeven RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), 3534077365a9SGeert Uytterhoeven }; 3535c8c05e81SGeert Uytterhoeven static const unsigned int sdhi0_data_mux[] = { 3536077365a9SGeert Uytterhoeven SD0_DAT0_MARK, SD0_DAT1_MARK, 3537077365a9SGeert Uytterhoeven SD0_DAT2_MARK, SD0_DAT3_MARK, 3538077365a9SGeert Uytterhoeven }; 3539077365a9SGeert Uytterhoeven static const unsigned int sdhi0_ctrl_pins[] = { 3540077365a9SGeert Uytterhoeven /* CLK, CMD */ 3541077365a9SGeert Uytterhoeven RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1), 3542077365a9SGeert Uytterhoeven }; 3543077365a9SGeert Uytterhoeven static const unsigned int sdhi0_ctrl_mux[] = { 3544077365a9SGeert Uytterhoeven SD0_CLK_MARK, SD0_CMD_MARK, 3545077365a9SGeert Uytterhoeven }; 3546077365a9SGeert Uytterhoeven static const unsigned int sdhi0_cd_pins[] = { 3547077365a9SGeert Uytterhoeven /* CD */ 3548077365a9SGeert Uytterhoeven RCAR_GP_PIN(3, 12), 3549077365a9SGeert Uytterhoeven }; 3550077365a9SGeert Uytterhoeven static const unsigned int sdhi0_cd_mux[] = { 3551077365a9SGeert Uytterhoeven SD0_CD_MARK, 3552077365a9SGeert Uytterhoeven }; 3553077365a9SGeert Uytterhoeven static const unsigned int sdhi0_wp_pins[] = { 3554077365a9SGeert Uytterhoeven /* WP */ 3555077365a9SGeert Uytterhoeven RCAR_GP_PIN(3, 13), 3556077365a9SGeert Uytterhoeven }; 3557077365a9SGeert Uytterhoeven static const unsigned int sdhi0_wp_mux[] = { 3558077365a9SGeert Uytterhoeven SD0_WP_MARK, 3559077365a9SGeert Uytterhoeven }; 3560077365a9SGeert Uytterhoeven /* - SDHI1 ------------------------------------------------------------------ */ 3561c8c05e81SGeert Uytterhoeven static const unsigned int sdhi1_data_pins[] = { 3562077365a9SGeert Uytterhoeven /* D[0:3] */ 3563077365a9SGeert Uytterhoeven RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), 3564077365a9SGeert Uytterhoeven RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), 3565077365a9SGeert Uytterhoeven }; 3566c8c05e81SGeert Uytterhoeven static const unsigned int sdhi1_data_mux[] = { 3567077365a9SGeert Uytterhoeven SD1_DAT0_MARK, SD1_DAT1_MARK, 3568077365a9SGeert Uytterhoeven SD1_DAT2_MARK, SD1_DAT3_MARK, 3569077365a9SGeert Uytterhoeven }; 3570077365a9SGeert Uytterhoeven static const unsigned int sdhi1_ctrl_pins[] = { 3571077365a9SGeert Uytterhoeven /* CLK, CMD */ 3572077365a9SGeert Uytterhoeven RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), 3573077365a9SGeert Uytterhoeven }; 3574077365a9SGeert Uytterhoeven static const unsigned int sdhi1_ctrl_mux[] = { 3575077365a9SGeert Uytterhoeven SD1_CLK_MARK, SD1_CMD_MARK, 3576077365a9SGeert Uytterhoeven }; 3577077365a9SGeert Uytterhoeven static const unsigned int sdhi1_cd_pins[] = { 3578077365a9SGeert Uytterhoeven /* CD */ 3579077365a9SGeert Uytterhoeven RCAR_GP_PIN(3, 14), 3580077365a9SGeert Uytterhoeven }; 3581077365a9SGeert Uytterhoeven static const unsigned int sdhi1_cd_mux[] = { 3582077365a9SGeert Uytterhoeven SD1_CD_MARK, 3583077365a9SGeert Uytterhoeven }; 3584077365a9SGeert Uytterhoeven static const unsigned int sdhi1_wp_pins[] = { 3585077365a9SGeert Uytterhoeven /* WP */ 3586077365a9SGeert Uytterhoeven RCAR_GP_PIN(3, 15), 3587077365a9SGeert Uytterhoeven }; 3588077365a9SGeert Uytterhoeven static const unsigned int sdhi1_wp_mux[] = { 3589077365a9SGeert Uytterhoeven SD1_WP_MARK, 3590077365a9SGeert Uytterhoeven }; 3591077365a9SGeert Uytterhoeven /* - SDHI2 ------------------------------------------------------------------ */ 3592c8c05e81SGeert Uytterhoeven static const unsigned int sdhi2_data_pins[] = { 3593077365a9SGeert Uytterhoeven /* D[0:7] */ 3594077365a9SGeert Uytterhoeven RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), 3595077365a9SGeert Uytterhoeven RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), 3596077365a9SGeert Uytterhoeven RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), 3597077365a9SGeert Uytterhoeven RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), 3598077365a9SGeert Uytterhoeven }; 3599c8c05e81SGeert Uytterhoeven static const unsigned int sdhi2_data_mux[] = { 3600077365a9SGeert Uytterhoeven SD2_DAT0_MARK, SD2_DAT1_MARK, 3601077365a9SGeert Uytterhoeven SD2_DAT2_MARK, SD2_DAT3_MARK, 3602077365a9SGeert Uytterhoeven SD2_DAT4_MARK, SD2_DAT5_MARK, 3603077365a9SGeert Uytterhoeven SD2_DAT6_MARK, SD2_DAT7_MARK, 3604077365a9SGeert Uytterhoeven }; 3605077365a9SGeert Uytterhoeven static const unsigned int sdhi2_ctrl_pins[] = { 3606077365a9SGeert Uytterhoeven /* CLK, CMD */ 3607077365a9SGeert Uytterhoeven RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1), 3608077365a9SGeert Uytterhoeven }; 3609077365a9SGeert Uytterhoeven static const unsigned int sdhi2_ctrl_mux[] = { 3610077365a9SGeert Uytterhoeven SD2_CLK_MARK, SD2_CMD_MARK, 3611077365a9SGeert Uytterhoeven }; 3612077365a9SGeert Uytterhoeven static const unsigned int sdhi2_cd_a_pins[] = { 3613077365a9SGeert Uytterhoeven /* CD */ 3614077365a9SGeert Uytterhoeven RCAR_GP_PIN(4, 13), 3615077365a9SGeert Uytterhoeven }; 3616077365a9SGeert Uytterhoeven static const unsigned int sdhi2_cd_a_mux[] = { 3617077365a9SGeert Uytterhoeven SD2_CD_A_MARK, 3618077365a9SGeert Uytterhoeven }; 3619077365a9SGeert Uytterhoeven static const unsigned int sdhi2_cd_b_pins[] = { 3620077365a9SGeert Uytterhoeven /* CD */ 3621077365a9SGeert Uytterhoeven RCAR_GP_PIN(5, 10), 3622077365a9SGeert Uytterhoeven }; 3623077365a9SGeert Uytterhoeven static const unsigned int sdhi2_cd_b_mux[] = { 3624077365a9SGeert Uytterhoeven SD2_CD_B_MARK, 3625077365a9SGeert Uytterhoeven }; 3626077365a9SGeert Uytterhoeven static const unsigned int sdhi2_wp_a_pins[] = { 3627077365a9SGeert Uytterhoeven /* WP */ 3628077365a9SGeert Uytterhoeven RCAR_GP_PIN(4, 14), 3629077365a9SGeert Uytterhoeven }; 3630077365a9SGeert Uytterhoeven static const unsigned int sdhi2_wp_a_mux[] = { 3631077365a9SGeert Uytterhoeven SD2_WP_A_MARK, 3632077365a9SGeert Uytterhoeven }; 3633077365a9SGeert Uytterhoeven static const unsigned int sdhi2_wp_b_pins[] = { 3634077365a9SGeert Uytterhoeven /* WP */ 3635077365a9SGeert Uytterhoeven RCAR_GP_PIN(5, 11), 3636077365a9SGeert Uytterhoeven }; 3637077365a9SGeert Uytterhoeven static const unsigned int sdhi2_wp_b_mux[] = { 3638077365a9SGeert Uytterhoeven SD2_WP_B_MARK, 3639077365a9SGeert Uytterhoeven }; 3640077365a9SGeert Uytterhoeven static const unsigned int sdhi2_ds_pins[] = { 3641077365a9SGeert Uytterhoeven /* DS */ 3642077365a9SGeert Uytterhoeven RCAR_GP_PIN(4, 6), 3643077365a9SGeert Uytterhoeven }; 3644077365a9SGeert Uytterhoeven static const unsigned int sdhi2_ds_mux[] = { 3645077365a9SGeert Uytterhoeven SD2_DS_MARK, 3646077365a9SGeert Uytterhoeven }; 3647077365a9SGeert Uytterhoeven /* - SDHI3 ------------------------------------------------------------------ */ 3648c8c05e81SGeert Uytterhoeven static const unsigned int sdhi3_data_pins[] = { 3649077365a9SGeert Uytterhoeven /* D[0:7] */ 3650077365a9SGeert Uytterhoeven RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10), 3651077365a9SGeert Uytterhoeven RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12), 3652077365a9SGeert Uytterhoeven RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14), 3653077365a9SGeert Uytterhoeven RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16), 3654077365a9SGeert Uytterhoeven }; 3655c8c05e81SGeert Uytterhoeven static const unsigned int sdhi3_data_mux[] = { 3656077365a9SGeert Uytterhoeven SD3_DAT0_MARK, SD3_DAT1_MARK, 3657077365a9SGeert Uytterhoeven SD3_DAT2_MARK, SD3_DAT3_MARK, 3658077365a9SGeert Uytterhoeven SD3_DAT4_MARK, SD3_DAT5_MARK, 3659077365a9SGeert Uytterhoeven SD3_DAT6_MARK, SD3_DAT7_MARK, 3660077365a9SGeert Uytterhoeven }; 3661077365a9SGeert Uytterhoeven static const unsigned int sdhi3_ctrl_pins[] = { 3662077365a9SGeert Uytterhoeven /* CLK, CMD */ 3663077365a9SGeert Uytterhoeven RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8), 3664077365a9SGeert Uytterhoeven }; 3665077365a9SGeert Uytterhoeven static const unsigned int sdhi3_ctrl_mux[] = { 3666077365a9SGeert Uytterhoeven SD3_CLK_MARK, SD3_CMD_MARK, 3667077365a9SGeert Uytterhoeven }; 3668077365a9SGeert Uytterhoeven static const unsigned int sdhi3_cd_pins[] = { 3669077365a9SGeert Uytterhoeven /* CD */ 3670077365a9SGeert Uytterhoeven RCAR_GP_PIN(4, 15), 3671077365a9SGeert Uytterhoeven }; 3672077365a9SGeert Uytterhoeven static const unsigned int sdhi3_cd_mux[] = { 3673077365a9SGeert Uytterhoeven SD3_CD_MARK, 3674077365a9SGeert Uytterhoeven }; 3675077365a9SGeert Uytterhoeven static const unsigned int sdhi3_wp_pins[] = { 3676077365a9SGeert Uytterhoeven /* WP */ 3677077365a9SGeert Uytterhoeven RCAR_GP_PIN(4, 16), 3678077365a9SGeert Uytterhoeven }; 3679077365a9SGeert Uytterhoeven static const unsigned int sdhi3_wp_mux[] = { 3680077365a9SGeert Uytterhoeven SD3_WP_MARK, 3681077365a9SGeert Uytterhoeven }; 3682077365a9SGeert Uytterhoeven static const unsigned int sdhi3_ds_pins[] = { 3683077365a9SGeert Uytterhoeven /* DS */ 3684077365a9SGeert Uytterhoeven RCAR_GP_PIN(4, 17), 3685077365a9SGeert Uytterhoeven }; 3686077365a9SGeert Uytterhoeven static const unsigned int sdhi3_ds_mux[] = { 3687077365a9SGeert Uytterhoeven SD3_DS_MARK, 3688077365a9SGeert Uytterhoeven }; 3689077365a9SGeert Uytterhoeven 3690077365a9SGeert Uytterhoeven /* - SSI -------------------------------------------------------------------- */ 3691077365a9SGeert Uytterhoeven static const unsigned int ssi0_data_pins[] = { 3692077365a9SGeert Uytterhoeven /* SDATA */ 3693077365a9SGeert Uytterhoeven RCAR_GP_PIN(6, 2), 3694077365a9SGeert Uytterhoeven }; 3695077365a9SGeert Uytterhoeven static const unsigned int ssi0_data_mux[] = { 3696077365a9SGeert Uytterhoeven SSI_SDATA0_MARK, 3697077365a9SGeert Uytterhoeven }; 3698077365a9SGeert Uytterhoeven static const unsigned int ssi01239_ctrl_pins[] = { 3699077365a9SGeert Uytterhoeven /* SCK, WS */ 3700077365a9SGeert Uytterhoeven RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1), 3701077365a9SGeert Uytterhoeven }; 3702077365a9SGeert Uytterhoeven static const unsigned int ssi01239_ctrl_mux[] = { 3703077365a9SGeert Uytterhoeven SSI_SCK01239_MARK, SSI_WS01239_MARK, 3704077365a9SGeert Uytterhoeven }; 3705077365a9SGeert Uytterhoeven static const unsigned int ssi1_data_a_pins[] = { 3706077365a9SGeert Uytterhoeven /* SDATA */ 3707077365a9SGeert Uytterhoeven RCAR_GP_PIN(6, 3), 3708077365a9SGeert Uytterhoeven }; 3709077365a9SGeert Uytterhoeven static const unsigned int ssi1_data_a_mux[] = { 3710077365a9SGeert Uytterhoeven SSI_SDATA1_A_MARK, 3711077365a9SGeert Uytterhoeven }; 3712077365a9SGeert Uytterhoeven static const unsigned int ssi1_data_b_pins[] = { 3713077365a9SGeert Uytterhoeven /* SDATA */ 3714077365a9SGeert Uytterhoeven RCAR_GP_PIN(5, 12), 3715077365a9SGeert Uytterhoeven }; 3716077365a9SGeert Uytterhoeven static const unsigned int ssi1_data_b_mux[] = { 3717077365a9SGeert Uytterhoeven SSI_SDATA1_B_MARK, 3718077365a9SGeert Uytterhoeven }; 3719077365a9SGeert Uytterhoeven static const unsigned int ssi1_ctrl_a_pins[] = { 3720077365a9SGeert Uytterhoeven /* SCK, WS */ 3721077365a9SGeert Uytterhoeven RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27), 3722077365a9SGeert Uytterhoeven }; 3723077365a9SGeert Uytterhoeven static const unsigned int ssi1_ctrl_a_mux[] = { 3724077365a9SGeert Uytterhoeven SSI_SCK1_A_MARK, SSI_WS1_A_MARK, 3725077365a9SGeert Uytterhoeven }; 3726077365a9SGeert Uytterhoeven static const unsigned int ssi1_ctrl_b_pins[] = { 3727077365a9SGeert Uytterhoeven /* SCK, WS */ 3728077365a9SGeert Uytterhoeven RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21), 3729077365a9SGeert Uytterhoeven }; 3730077365a9SGeert Uytterhoeven static const unsigned int ssi1_ctrl_b_mux[] = { 3731077365a9SGeert Uytterhoeven SSI_SCK1_B_MARK, SSI_WS1_B_MARK, 3732077365a9SGeert Uytterhoeven }; 3733077365a9SGeert Uytterhoeven static const unsigned int ssi2_data_a_pins[] = { 3734077365a9SGeert Uytterhoeven /* SDATA */ 3735077365a9SGeert Uytterhoeven RCAR_GP_PIN(6, 4), 3736077365a9SGeert Uytterhoeven }; 3737077365a9SGeert Uytterhoeven static const unsigned int ssi2_data_a_mux[] = { 3738077365a9SGeert Uytterhoeven SSI_SDATA2_A_MARK, 3739077365a9SGeert Uytterhoeven }; 3740077365a9SGeert Uytterhoeven static const unsigned int ssi2_data_b_pins[] = { 3741077365a9SGeert Uytterhoeven /* SDATA */ 3742077365a9SGeert Uytterhoeven RCAR_GP_PIN(5, 13), 3743077365a9SGeert Uytterhoeven }; 3744077365a9SGeert Uytterhoeven static const unsigned int ssi2_data_b_mux[] = { 3745077365a9SGeert Uytterhoeven SSI_SDATA2_B_MARK, 3746077365a9SGeert Uytterhoeven }; 3747077365a9SGeert Uytterhoeven static const unsigned int ssi2_ctrl_a_pins[] = { 3748077365a9SGeert Uytterhoeven /* SCK, WS */ 3749077365a9SGeert Uytterhoeven RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21), 3750077365a9SGeert Uytterhoeven }; 3751077365a9SGeert Uytterhoeven static const unsigned int ssi2_ctrl_a_mux[] = { 3752077365a9SGeert Uytterhoeven SSI_SCK2_A_MARK, SSI_WS2_A_MARK, 3753077365a9SGeert Uytterhoeven }; 3754077365a9SGeert Uytterhoeven static const unsigned int ssi2_ctrl_b_pins[] = { 3755077365a9SGeert Uytterhoeven /* SCK, WS */ 3756077365a9SGeert Uytterhoeven RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29), 3757077365a9SGeert Uytterhoeven }; 3758077365a9SGeert Uytterhoeven static const unsigned int ssi2_ctrl_b_mux[] = { 3759077365a9SGeert Uytterhoeven SSI_SCK2_B_MARK, SSI_WS2_B_MARK, 3760077365a9SGeert Uytterhoeven }; 3761077365a9SGeert Uytterhoeven static const unsigned int ssi3_data_pins[] = { 3762077365a9SGeert Uytterhoeven /* SDATA */ 3763077365a9SGeert Uytterhoeven RCAR_GP_PIN(6, 7), 3764077365a9SGeert Uytterhoeven }; 3765077365a9SGeert Uytterhoeven static const unsigned int ssi3_data_mux[] = { 3766077365a9SGeert Uytterhoeven SSI_SDATA3_MARK, 3767077365a9SGeert Uytterhoeven }; 3768077365a9SGeert Uytterhoeven static const unsigned int ssi349_ctrl_pins[] = { 3769077365a9SGeert Uytterhoeven /* SCK, WS */ 3770077365a9SGeert Uytterhoeven RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6), 3771077365a9SGeert Uytterhoeven }; 3772077365a9SGeert Uytterhoeven static const unsigned int ssi349_ctrl_mux[] = { 3773077365a9SGeert Uytterhoeven SSI_SCK349_MARK, SSI_WS349_MARK, 3774077365a9SGeert Uytterhoeven }; 3775077365a9SGeert Uytterhoeven static const unsigned int ssi4_data_pins[] = { 3776077365a9SGeert Uytterhoeven /* SDATA */ 3777077365a9SGeert Uytterhoeven RCAR_GP_PIN(6, 10), 3778077365a9SGeert Uytterhoeven }; 3779077365a9SGeert Uytterhoeven static const unsigned int ssi4_data_mux[] = { 3780077365a9SGeert Uytterhoeven SSI_SDATA4_MARK, 3781077365a9SGeert Uytterhoeven }; 3782077365a9SGeert Uytterhoeven static const unsigned int ssi4_ctrl_pins[] = { 3783077365a9SGeert Uytterhoeven /* SCK, WS */ 3784077365a9SGeert Uytterhoeven RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), 3785077365a9SGeert Uytterhoeven }; 3786077365a9SGeert Uytterhoeven static const unsigned int ssi4_ctrl_mux[] = { 3787077365a9SGeert Uytterhoeven SSI_SCK4_MARK, SSI_WS4_MARK, 3788077365a9SGeert Uytterhoeven }; 3789077365a9SGeert Uytterhoeven static const unsigned int ssi5_data_pins[] = { 3790077365a9SGeert Uytterhoeven /* SDATA */ 3791077365a9SGeert Uytterhoeven RCAR_GP_PIN(6, 13), 3792077365a9SGeert Uytterhoeven }; 3793077365a9SGeert Uytterhoeven static const unsigned int ssi5_data_mux[] = { 3794077365a9SGeert Uytterhoeven SSI_SDATA5_MARK, 3795077365a9SGeert Uytterhoeven }; 3796077365a9SGeert Uytterhoeven static const unsigned int ssi5_ctrl_pins[] = { 3797077365a9SGeert Uytterhoeven /* SCK, WS */ 3798077365a9SGeert Uytterhoeven RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12), 3799077365a9SGeert Uytterhoeven }; 3800077365a9SGeert Uytterhoeven static const unsigned int ssi5_ctrl_mux[] = { 3801077365a9SGeert Uytterhoeven SSI_SCK5_MARK, SSI_WS5_MARK, 3802077365a9SGeert Uytterhoeven }; 3803077365a9SGeert Uytterhoeven static const unsigned int ssi6_data_pins[] = { 3804077365a9SGeert Uytterhoeven /* SDATA */ 3805077365a9SGeert Uytterhoeven RCAR_GP_PIN(6, 16), 3806077365a9SGeert Uytterhoeven }; 3807077365a9SGeert Uytterhoeven static const unsigned int ssi6_data_mux[] = { 3808077365a9SGeert Uytterhoeven SSI_SDATA6_MARK, 3809077365a9SGeert Uytterhoeven }; 3810077365a9SGeert Uytterhoeven static const unsigned int ssi6_ctrl_pins[] = { 3811077365a9SGeert Uytterhoeven /* SCK, WS */ 3812077365a9SGeert Uytterhoeven RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15), 3813077365a9SGeert Uytterhoeven }; 3814077365a9SGeert Uytterhoeven static const unsigned int ssi6_ctrl_mux[] = { 3815077365a9SGeert Uytterhoeven SSI_SCK6_MARK, SSI_WS6_MARK, 3816077365a9SGeert Uytterhoeven }; 3817077365a9SGeert Uytterhoeven static const unsigned int ssi7_data_pins[] = { 3818077365a9SGeert Uytterhoeven /* SDATA */ 3819077365a9SGeert Uytterhoeven RCAR_GP_PIN(6, 19), 3820077365a9SGeert Uytterhoeven }; 3821077365a9SGeert Uytterhoeven static const unsigned int ssi7_data_mux[] = { 3822077365a9SGeert Uytterhoeven SSI_SDATA7_MARK, 3823077365a9SGeert Uytterhoeven }; 3824077365a9SGeert Uytterhoeven static const unsigned int ssi78_ctrl_pins[] = { 3825077365a9SGeert Uytterhoeven /* SCK, WS */ 3826077365a9SGeert Uytterhoeven RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18), 3827077365a9SGeert Uytterhoeven }; 3828077365a9SGeert Uytterhoeven static const unsigned int ssi78_ctrl_mux[] = { 3829077365a9SGeert Uytterhoeven SSI_SCK78_MARK, SSI_WS78_MARK, 3830077365a9SGeert Uytterhoeven }; 3831077365a9SGeert Uytterhoeven static const unsigned int ssi8_data_pins[] = { 3832077365a9SGeert Uytterhoeven /* SDATA */ 3833077365a9SGeert Uytterhoeven RCAR_GP_PIN(6, 20), 3834077365a9SGeert Uytterhoeven }; 3835077365a9SGeert Uytterhoeven static const unsigned int ssi8_data_mux[] = { 3836077365a9SGeert Uytterhoeven SSI_SDATA8_MARK, 3837077365a9SGeert Uytterhoeven }; 3838077365a9SGeert Uytterhoeven static const unsigned int ssi9_data_a_pins[] = { 3839077365a9SGeert Uytterhoeven /* SDATA */ 3840077365a9SGeert Uytterhoeven RCAR_GP_PIN(6, 21), 3841077365a9SGeert Uytterhoeven }; 3842077365a9SGeert Uytterhoeven static const unsigned int ssi9_data_a_mux[] = { 3843077365a9SGeert Uytterhoeven SSI_SDATA9_A_MARK, 3844077365a9SGeert Uytterhoeven }; 3845077365a9SGeert Uytterhoeven static const unsigned int ssi9_data_b_pins[] = { 3846077365a9SGeert Uytterhoeven /* SDATA */ 3847077365a9SGeert Uytterhoeven RCAR_GP_PIN(5, 14), 3848077365a9SGeert Uytterhoeven }; 3849077365a9SGeert Uytterhoeven static const unsigned int ssi9_data_b_mux[] = { 3850077365a9SGeert Uytterhoeven SSI_SDATA9_B_MARK, 3851077365a9SGeert Uytterhoeven }; 3852077365a9SGeert Uytterhoeven static const unsigned int ssi9_ctrl_a_pins[] = { 3853077365a9SGeert Uytterhoeven /* SCK, WS */ 3854077365a9SGeert Uytterhoeven RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16), 3855077365a9SGeert Uytterhoeven }; 3856077365a9SGeert Uytterhoeven static const unsigned int ssi9_ctrl_a_mux[] = { 3857077365a9SGeert Uytterhoeven SSI_SCK9_A_MARK, SSI_WS9_A_MARK, 3858077365a9SGeert Uytterhoeven }; 3859077365a9SGeert Uytterhoeven static const unsigned int ssi9_ctrl_b_pins[] = { 3860077365a9SGeert Uytterhoeven /* SCK, WS */ 3861077365a9SGeert Uytterhoeven RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31), 3862077365a9SGeert Uytterhoeven }; 3863077365a9SGeert Uytterhoeven static const unsigned int ssi9_ctrl_b_mux[] = { 3864077365a9SGeert Uytterhoeven SSI_SCK9_B_MARK, SSI_WS9_B_MARK, 3865077365a9SGeert Uytterhoeven }; 3866077365a9SGeert Uytterhoeven 3867077365a9SGeert Uytterhoeven /* - TMU -------------------------------------------------------------------- */ 3868077365a9SGeert Uytterhoeven static const unsigned int tmu_tclk1_a_pins[] = { 3869077365a9SGeert Uytterhoeven /* TCLK */ 3870077365a9SGeert Uytterhoeven RCAR_GP_PIN(6, 23), 3871077365a9SGeert Uytterhoeven }; 3872077365a9SGeert Uytterhoeven static const unsigned int tmu_tclk1_a_mux[] = { 3873077365a9SGeert Uytterhoeven TCLK1_A_MARK, 3874077365a9SGeert Uytterhoeven }; 3875077365a9SGeert Uytterhoeven static const unsigned int tmu_tclk1_b_pins[] = { 3876077365a9SGeert Uytterhoeven /* TCLK */ 3877077365a9SGeert Uytterhoeven RCAR_GP_PIN(5, 19), 3878077365a9SGeert Uytterhoeven }; 3879077365a9SGeert Uytterhoeven static const unsigned int tmu_tclk1_b_mux[] = { 3880077365a9SGeert Uytterhoeven TCLK1_B_MARK, 3881077365a9SGeert Uytterhoeven }; 3882077365a9SGeert Uytterhoeven static const unsigned int tmu_tclk2_a_pins[] = { 3883077365a9SGeert Uytterhoeven /* TCLK */ 3884077365a9SGeert Uytterhoeven RCAR_GP_PIN(6, 19), 3885077365a9SGeert Uytterhoeven }; 3886077365a9SGeert Uytterhoeven static const unsigned int tmu_tclk2_a_mux[] = { 3887077365a9SGeert Uytterhoeven TCLK2_A_MARK, 3888077365a9SGeert Uytterhoeven }; 3889077365a9SGeert Uytterhoeven static const unsigned int tmu_tclk2_b_pins[] = { 3890077365a9SGeert Uytterhoeven /* TCLK */ 3891077365a9SGeert Uytterhoeven RCAR_GP_PIN(6, 28), 3892077365a9SGeert Uytterhoeven }; 3893077365a9SGeert Uytterhoeven static const unsigned int tmu_tclk2_b_mux[] = { 3894077365a9SGeert Uytterhoeven TCLK2_B_MARK, 3895077365a9SGeert Uytterhoeven }; 3896077365a9SGeert Uytterhoeven 3897077365a9SGeert Uytterhoeven /* - TPU ------------------------------------------------------------------- */ 3898077365a9SGeert Uytterhoeven static const unsigned int tpu_to0_pins[] = { 3899077365a9SGeert Uytterhoeven /* TPU0TO0 */ 3900077365a9SGeert Uytterhoeven RCAR_GP_PIN(6, 28), 3901077365a9SGeert Uytterhoeven }; 3902077365a9SGeert Uytterhoeven static const unsigned int tpu_to0_mux[] = { 3903077365a9SGeert Uytterhoeven TPU0TO0_MARK, 3904077365a9SGeert Uytterhoeven }; 3905077365a9SGeert Uytterhoeven static const unsigned int tpu_to1_pins[] = { 3906077365a9SGeert Uytterhoeven /* TPU0TO1 */ 3907077365a9SGeert Uytterhoeven RCAR_GP_PIN(6, 29), 3908077365a9SGeert Uytterhoeven }; 3909077365a9SGeert Uytterhoeven static const unsigned int tpu_to1_mux[] = { 3910077365a9SGeert Uytterhoeven TPU0TO1_MARK, 3911077365a9SGeert Uytterhoeven }; 3912077365a9SGeert Uytterhoeven static const unsigned int tpu_to2_pins[] = { 3913077365a9SGeert Uytterhoeven /* TPU0TO2 */ 3914077365a9SGeert Uytterhoeven RCAR_GP_PIN(6, 30), 3915077365a9SGeert Uytterhoeven }; 3916077365a9SGeert Uytterhoeven static const unsigned int tpu_to2_mux[] = { 3917077365a9SGeert Uytterhoeven TPU0TO2_MARK, 3918077365a9SGeert Uytterhoeven }; 3919077365a9SGeert Uytterhoeven static const unsigned int tpu_to3_pins[] = { 3920077365a9SGeert Uytterhoeven /* TPU0TO3 */ 3921077365a9SGeert Uytterhoeven RCAR_GP_PIN(6, 31), 3922077365a9SGeert Uytterhoeven }; 3923077365a9SGeert Uytterhoeven static const unsigned int tpu_to3_mux[] = { 3924077365a9SGeert Uytterhoeven TPU0TO3_MARK, 3925077365a9SGeert Uytterhoeven }; 3926077365a9SGeert Uytterhoeven 3927077365a9SGeert Uytterhoeven /* - USB0 ------------------------------------------------------------------- */ 3928077365a9SGeert Uytterhoeven static const unsigned int usb0_pins[] = { 3929077365a9SGeert Uytterhoeven /* PWEN, OVC */ 3930077365a9SGeert Uytterhoeven RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25), 3931077365a9SGeert Uytterhoeven }; 3932077365a9SGeert Uytterhoeven static const unsigned int usb0_mux[] = { 3933077365a9SGeert Uytterhoeven USB0_PWEN_MARK, USB0_OVC_MARK, 3934077365a9SGeert Uytterhoeven }; 3935077365a9SGeert Uytterhoeven /* - USB1 ------------------------------------------------------------------- */ 3936077365a9SGeert Uytterhoeven static const unsigned int usb1_pins[] = { 3937077365a9SGeert Uytterhoeven /* PWEN, OVC */ 3938077365a9SGeert Uytterhoeven RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27), 3939077365a9SGeert Uytterhoeven }; 3940077365a9SGeert Uytterhoeven static const unsigned int usb1_mux[] = { 3941077365a9SGeert Uytterhoeven USB1_PWEN_MARK, USB1_OVC_MARK, 3942077365a9SGeert Uytterhoeven }; 3943077365a9SGeert Uytterhoeven /* - USB2 ------------------------------------------------------------------- */ 3944077365a9SGeert Uytterhoeven static const unsigned int usb2_pins[] = { 3945077365a9SGeert Uytterhoeven /* PWEN, OVC */ 3946077365a9SGeert Uytterhoeven RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15), 3947077365a9SGeert Uytterhoeven }; 3948077365a9SGeert Uytterhoeven static const unsigned int usb2_mux[] = { 3949077365a9SGeert Uytterhoeven USB2_PWEN_MARK, USB2_OVC_MARK, 3950077365a9SGeert Uytterhoeven }; 3951077365a9SGeert Uytterhoeven /* - USB2_CH3 --------------------------------------------------------------- */ 3952077365a9SGeert Uytterhoeven static const unsigned int usb2_ch3_pins[] = { 3953077365a9SGeert Uytterhoeven /* PWEN, OVC */ 3954077365a9SGeert Uytterhoeven RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31), 3955077365a9SGeert Uytterhoeven }; 3956077365a9SGeert Uytterhoeven static const unsigned int usb2_ch3_mux[] = { 3957077365a9SGeert Uytterhoeven USB2_CH3_PWEN_MARK, USB2_CH3_OVC_MARK, 3958077365a9SGeert Uytterhoeven }; 3959077365a9SGeert Uytterhoeven 3960077365a9SGeert Uytterhoeven /* - USB30 ------------------------------------------------------------------ */ 3961077365a9SGeert Uytterhoeven static const unsigned int usb30_pins[] = { 3962077365a9SGeert Uytterhoeven /* PWEN, OVC */ 3963077365a9SGeert Uytterhoeven RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29), 3964077365a9SGeert Uytterhoeven }; 3965077365a9SGeert Uytterhoeven static const unsigned int usb30_mux[] = { 3966077365a9SGeert Uytterhoeven USB30_PWEN_MARK, USB30_OVC_MARK, 3967077365a9SGeert Uytterhoeven }; 3968077365a9SGeert Uytterhoeven 3969077365a9SGeert Uytterhoeven /* - VIN4 ------------------------------------------------------------------- */ 3970077365a9SGeert Uytterhoeven static const unsigned int vin4_data18_a_pins[] = { 3971077365a9SGeert Uytterhoeven RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), 3972077365a9SGeert Uytterhoeven RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), 3973077365a9SGeert Uytterhoeven RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), 3974077365a9SGeert Uytterhoeven RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), 3975077365a9SGeert Uytterhoeven RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), 3976077365a9SGeert Uytterhoeven RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 3977077365a9SGeert Uytterhoeven RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), 3978077365a9SGeert Uytterhoeven RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), 3979077365a9SGeert Uytterhoeven RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), 3980077365a9SGeert Uytterhoeven }; 3981077365a9SGeert Uytterhoeven static const unsigned int vin4_data18_a_mux[] = { 3982077365a9SGeert Uytterhoeven VI4_DATA2_A_MARK, VI4_DATA3_A_MARK, 3983077365a9SGeert Uytterhoeven VI4_DATA4_A_MARK, VI4_DATA5_A_MARK, 3984077365a9SGeert Uytterhoeven VI4_DATA6_A_MARK, VI4_DATA7_A_MARK, 3985077365a9SGeert Uytterhoeven VI4_DATA10_MARK, VI4_DATA11_MARK, 3986077365a9SGeert Uytterhoeven VI4_DATA12_MARK, VI4_DATA13_MARK, 3987077365a9SGeert Uytterhoeven VI4_DATA14_MARK, VI4_DATA15_MARK, 3988077365a9SGeert Uytterhoeven VI4_DATA18_MARK, VI4_DATA19_MARK, 3989077365a9SGeert Uytterhoeven VI4_DATA20_MARK, VI4_DATA21_MARK, 3990077365a9SGeert Uytterhoeven VI4_DATA22_MARK, VI4_DATA23_MARK, 3991077365a9SGeert Uytterhoeven }; 3992077365a9SGeert Uytterhoeven static const unsigned int vin4_data18_b_pins[] = { 3993077365a9SGeert Uytterhoeven RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), 3994077365a9SGeert Uytterhoeven RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), 3995077365a9SGeert Uytterhoeven RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), 3996077365a9SGeert Uytterhoeven RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), 3997077365a9SGeert Uytterhoeven RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), 3998077365a9SGeert Uytterhoeven RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 3999077365a9SGeert Uytterhoeven RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), 4000077365a9SGeert Uytterhoeven RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), 4001077365a9SGeert Uytterhoeven RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), 4002077365a9SGeert Uytterhoeven }; 4003077365a9SGeert Uytterhoeven static const unsigned int vin4_data18_b_mux[] = { 4004077365a9SGeert Uytterhoeven VI4_DATA2_B_MARK, VI4_DATA3_B_MARK, 4005077365a9SGeert Uytterhoeven VI4_DATA4_B_MARK, VI4_DATA5_B_MARK, 4006077365a9SGeert Uytterhoeven VI4_DATA6_B_MARK, VI4_DATA7_B_MARK, 4007077365a9SGeert Uytterhoeven VI4_DATA10_MARK, VI4_DATA11_MARK, 4008077365a9SGeert Uytterhoeven VI4_DATA12_MARK, VI4_DATA13_MARK, 4009077365a9SGeert Uytterhoeven VI4_DATA14_MARK, VI4_DATA15_MARK, 4010077365a9SGeert Uytterhoeven VI4_DATA18_MARK, VI4_DATA19_MARK, 4011077365a9SGeert Uytterhoeven VI4_DATA20_MARK, VI4_DATA21_MARK, 4012077365a9SGeert Uytterhoeven VI4_DATA22_MARK, VI4_DATA23_MARK, 4013077365a9SGeert Uytterhoeven }; 4014496da100SGeert Uytterhoeven static const unsigned int vin4_data_a_pins[] = { 4015077365a9SGeert Uytterhoeven RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), 4016077365a9SGeert Uytterhoeven RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), 4017077365a9SGeert Uytterhoeven RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), 4018077365a9SGeert Uytterhoeven RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), 4019077365a9SGeert Uytterhoeven RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), 4020077365a9SGeert Uytterhoeven RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), 4021077365a9SGeert Uytterhoeven RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), 4022077365a9SGeert Uytterhoeven RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 4023077365a9SGeert Uytterhoeven RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), 4024077365a9SGeert Uytterhoeven RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), 4025077365a9SGeert Uytterhoeven RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), 4026077365a9SGeert Uytterhoeven RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), 4027077365a9SGeert Uytterhoeven }; 4028496da100SGeert Uytterhoeven static const unsigned int vin4_data_a_mux[] = { 4029077365a9SGeert Uytterhoeven VI4_DATA0_A_MARK, VI4_DATA1_A_MARK, 4030077365a9SGeert Uytterhoeven VI4_DATA2_A_MARK, VI4_DATA3_A_MARK, 4031077365a9SGeert Uytterhoeven VI4_DATA4_A_MARK, VI4_DATA5_A_MARK, 4032077365a9SGeert Uytterhoeven VI4_DATA6_A_MARK, VI4_DATA7_A_MARK, 4033077365a9SGeert Uytterhoeven VI4_DATA8_MARK, VI4_DATA9_MARK, 4034077365a9SGeert Uytterhoeven VI4_DATA10_MARK, VI4_DATA11_MARK, 4035077365a9SGeert Uytterhoeven VI4_DATA12_MARK, VI4_DATA13_MARK, 4036077365a9SGeert Uytterhoeven VI4_DATA14_MARK, VI4_DATA15_MARK, 4037077365a9SGeert Uytterhoeven VI4_DATA16_MARK, VI4_DATA17_MARK, 4038077365a9SGeert Uytterhoeven VI4_DATA18_MARK, VI4_DATA19_MARK, 4039077365a9SGeert Uytterhoeven VI4_DATA20_MARK, VI4_DATA21_MARK, 4040077365a9SGeert Uytterhoeven VI4_DATA22_MARK, VI4_DATA23_MARK, 4041077365a9SGeert Uytterhoeven }; 4042496da100SGeert Uytterhoeven static const unsigned int vin4_data_b_pins[] = { 4043077365a9SGeert Uytterhoeven RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), 4044077365a9SGeert Uytterhoeven RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), 4045077365a9SGeert Uytterhoeven RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), 4046077365a9SGeert Uytterhoeven RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), 4047077365a9SGeert Uytterhoeven RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), 4048077365a9SGeert Uytterhoeven RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), 4049077365a9SGeert Uytterhoeven RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), 4050077365a9SGeert Uytterhoeven RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 4051077365a9SGeert Uytterhoeven RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), 4052077365a9SGeert Uytterhoeven RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), 4053077365a9SGeert Uytterhoeven RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), 4054077365a9SGeert Uytterhoeven RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), 4055077365a9SGeert Uytterhoeven }; 4056496da100SGeert Uytterhoeven static const unsigned int vin4_data_b_mux[] = { 4057077365a9SGeert Uytterhoeven VI4_DATA0_B_MARK, VI4_DATA1_B_MARK, 4058077365a9SGeert Uytterhoeven VI4_DATA2_B_MARK, VI4_DATA3_B_MARK, 4059077365a9SGeert Uytterhoeven VI4_DATA4_B_MARK, VI4_DATA5_B_MARK, 4060077365a9SGeert Uytterhoeven VI4_DATA6_B_MARK, VI4_DATA7_B_MARK, 4061077365a9SGeert Uytterhoeven VI4_DATA8_MARK, VI4_DATA9_MARK, 4062077365a9SGeert Uytterhoeven VI4_DATA10_MARK, VI4_DATA11_MARK, 4063077365a9SGeert Uytterhoeven VI4_DATA12_MARK, VI4_DATA13_MARK, 4064077365a9SGeert Uytterhoeven VI4_DATA14_MARK, VI4_DATA15_MARK, 4065077365a9SGeert Uytterhoeven VI4_DATA16_MARK, VI4_DATA17_MARK, 4066077365a9SGeert Uytterhoeven VI4_DATA18_MARK, VI4_DATA19_MARK, 4067077365a9SGeert Uytterhoeven VI4_DATA20_MARK, VI4_DATA21_MARK, 4068077365a9SGeert Uytterhoeven VI4_DATA22_MARK, VI4_DATA23_MARK, 4069077365a9SGeert Uytterhoeven }; 4070077365a9SGeert Uytterhoeven static const unsigned int vin4_sync_pins[] = { 4071077365a9SGeert Uytterhoeven /* HSYNC#, VSYNC# */ 4072077365a9SGeert Uytterhoeven RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 17), 4073077365a9SGeert Uytterhoeven }; 4074077365a9SGeert Uytterhoeven static const unsigned int vin4_sync_mux[] = { 4075077365a9SGeert Uytterhoeven VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK, 4076077365a9SGeert Uytterhoeven }; 4077077365a9SGeert Uytterhoeven static const unsigned int vin4_field_pins[] = { 4078077365a9SGeert Uytterhoeven /* FIELD */ 4079077365a9SGeert Uytterhoeven RCAR_GP_PIN(1, 16), 4080077365a9SGeert Uytterhoeven }; 4081077365a9SGeert Uytterhoeven static const unsigned int vin4_field_mux[] = { 4082077365a9SGeert Uytterhoeven VI4_FIELD_MARK, 4083077365a9SGeert Uytterhoeven }; 4084077365a9SGeert Uytterhoeven static const unsigned int vin4_clkenb_pins[] = { 4085077365a9SGeert Uytterhoeven /* CLKENB */ 4086077365a9SGeert Uytterhoeven RCAR_GP_PIN(1, 19), 4087077365a9SGeert Uytterhoeven }; 4088077365a9SGeert Uytterhoeven static const unsigned int vin4_clkenb_mux[] = { 4089077365a9SGeert Uytterhoeven VI4_CLKENB_MARK, 4090077365a9SGeert Uytterhoeven }; 4091077365a9SGeert Uytterhoeven static const unsigned int vin4_clk_pins[] = { 4092077365a9SGeert Uytterhoeven /* CLK */ 4093077365a9SGeert Uytterhoeven RCAR_GP_PIN(1, 27), 4094077365a9SGeert Uytterhoeven }; 4095077365a9SGeert Uytterhoeven static const unsigned int vin4_clk_mux[] = { 4096077365a9SGeert Uytterhoeven VI4_CLK_MARK, 4097077365a9SGeert Uytterhoeven }; 4098077365a9SGeert Uytterhoeven 4099077365a9SGeert Uytterhoeven /* - VIN5 ------------------------------------------------------------------- */ 4100496da100SGeert Uytterhoeven static const unsigned int vin5_data_pins[] = { 4101077365a9SGeert Uytterhoeven RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), 4102077365a9SGeert Uytterhoeven RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), 4103077365a9SGeert Uytterhoeven RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), 4104077365a9SGeert Uytterhoeven RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), 4105077365a9SGeert Uytterhoeven RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), 4106077365a9SGeert Uytterhoeven RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), 4107077365a9SGeert Uytterhoeven RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), 4108077365a9SGeert Uytterhoeven RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 4109077365a9SGeert Uytterhoeven }; 4110496da100SGeert Uytterhoeven static const unsigned int vin5_data_mux[] = { 4111077365a9SGeert Uytterhoeven VI5_DATA0_MARK, VI5_DATA1_MARK, 4112077365a9SGeert Uytterhoeven VI5_DATA2_MARK, VI5_DATA3_MARK, 4113077365a9SGeert Uytterhoeven VI5_DATA4_MARK, VI5_DATA5_MARK, 4114077365a9SGeert Uytterhoeven VI5_DATA6_MARK, VI5_DATA7_MARK, 4115077365a9SGeert Uytterhoeven VI5_DATA8_MARK, VI5_DATA9_MARK, 4116077365a9SGeert Uytterhoeven VI5_DATA10_MARK, VI5_DATA11_MARK, 4117077365a9SGeert Uytterhoeven VI5_DATA12_MARK, VI5_DATA13_MARK, 4118077365a9SGeert Uytterhoeven VI5_DATA14_MARK, VI5_DATA15_MARK, 4119077365a9SGeert Uytterhoeven }; 4120077365a9SGeert Uytterhoeven static const unsigned int vin5_sync_pins[] = { 4121077365a9SGeert Uytterhoeven /* HSYNC#, VSYNC# */ 4122077365a9SGeert Uytterhoeven RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9), 4123077365a9SGeert Uytterhoeven }; 4124077365a9SGeert Uytterhoeven static const unsigned int vin5_sync_mux[] = { 4125077365a9SGeert Uytterhoeven VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK, 4126077365a9SGeert Uytterhoeven }; 4127077365a9SGeert Uytterhoeven static const unsigned int vin5_field_pins[] = { 4128077365a9SGeert Uytterhoeven RCAR_GP_PIN(1, 11), 4129077365a9SGeert Uytterhoeven }; 4130077365a9SGeert Uytterhoeven static const unsigned int vin5_field_mux[] = { 4131077365a9SGeert Uytterhoeven /* FIELD */ 4132077365a9SGeert Uytterhoeven VI5_FIELD_MARK, 4133077365a9SGeert Uytterhoeven }; 4134077365a9SGeert Uytterhoeven static const unsigned int vin5_clkenb_pins[] = { 4135077365a9SGeert Uytterhoeven RCAR_GP_PIN(1, 20), 4136077365a9SGeert Uytterhoeven }; 4137077365a9SGeert Uytterhoeven static const unsigned int vin5_clkenb_mux[] = { 4138077365a9SGeert Uytterhoeven /* CLKENB */ 4139077365a9SGeert Uytterhoeven VI5_CLKENB_MARK, 4140077365a9SGeert Uytterhoeven }; 4141077365a9SGeert Uytterhoeven static const unsigned int vin5_clk_pins[] = { 4142077365a9SGeert Uytterhoeven RCAR_GP_PIN(1, 21), 4143077365a9SGeert Uytterhoeven }; 4144077365a9SGeert Uytterhoeven static const unsigned int vin5_clk_mux[] = { 4145077365a9SGeert Uytterhoeven /* CLK */ 4146077365a9SGeert Uytterhoeven VI5_CLK_MARK, 4147077365a9SGeert Uytterhoeven }; 4148077365a9SGeert Uytterhoeven 4149077365a9SGeert Uytterhoeven static const struct { 41505f79bbb2SNiklas Söderlund struct sh_pfc_pin_group common[328]; 4151b8029394SBiju Das #ifdef CONFIG_PINCTRL_PFC_R8A77951 4152ce34fb3cSAndrey Gusakov struct sh_pfc_pin_group automotive[31]; 4153b8029394SBiju Das #endif 4154077365a9SGeert Uytterhoeven } pinmux_groups = { 4155077365a9SGeert Uytterhoeven .common = { 4156077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(audio_clk_a_a), 4157077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(audio_clk_a_b), 4158077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(audio_clk_a_c), 4159077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(audio_clk_b_a), 4160077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(audio_clk_b_b), 4161077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(audio_clk_c_a), 4162077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(audio_clk_c_b), 4163077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(audio_clkout_a), 4164077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(audio_clkout_b), 4165077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(audio_clkout_c), 4166077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(audio_clkout_d), 4167077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(audio_clkout1_a), 4168077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(audio_clkout1_b), 4169077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(audio_clkout2_a), 4170077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(audio_clkout2_b), 4171077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(audio_clkout3_a), 4172077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(audio_clkout3_b), 4173077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(avb_link), 4174077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(avb_magic), 4175077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(avb_phy_int), 4176077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio), /* Deprecated */ 4177077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(avb_mdio), 4178077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(avb_mii), 4179077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(avb_avtp_pps), 4180077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(avb_avtp_match_a), 4181077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(avb_avtp_capture_a), 4182077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(avb_avtp_match_b), 4183077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(avb_avtp_capture_b), 4184077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(can0_data_a), 4185077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(can0_data_b), 4186077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(can1_data), 4187077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(can_clk), 4188077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(canfd0_data_a), 4189077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(canfd0_data_b), 4190077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(canfd1_data), 4191077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(du_rgb666), 4192077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(du_rgb888), 4193077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(du_clk_out_0), 4194077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(du_clk_out_1), 4195077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(du_sync), 4196077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(du_oddf), 4197077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(du_cde), 4198077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(du_disp), 4199077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(hscif0_data), 4200077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(hscif0_clk), 4201077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(hscif0_ctrl), 4202077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(hscif1_data_a), 4203077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(hscif1_clk_a), 4204077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(hscif1_ctrl_a), 4205077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(hscif1_data_b), 4206077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(hscif1_clk_b), 4207077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(hscif1_ctrl_b), 4208077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(hscif2_data_a), 4209077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(hscif2_clk_a), 4210077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(hscif2_ctrl_a), 4211077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(hscif2_data_b), 4212077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(hscif2_clk_b), 4213077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(hscif2_ctrl_b), 4214077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(hscif2_data_c), 4215077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(hscif2_clk_c), 4216077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(hscif2_ctrl_c), 4217077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(hscif3_data_a), 4218077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(hscif3_clk), 4219077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(hscif3_ctrl), 4220077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(hscif3_data_b), 4221077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(hscif3_data_c), 4222077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(hscif3_data_d), 4223077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(hscif4_data_a), 4224077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(hscif4_clk), 4225077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(hscif4_ctrl), 4226077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(hscif4_data_b), 4227077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(i2c0), 4228077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(i2c1_a), 4229077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(i2c1_b), 4230077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(i2c2_a), 4231077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(i2c2_b), 4232077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(i2c3), 4233077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(i2c5), 4234077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(i2c6_a), 4235077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(i2c6_b), 4236077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(i2c6_c), 4237077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(intc_ex_irq0), 4238077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(intc_ex_irq1), 4239077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(intc_ex_irq2), 4240077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(intc_ex_irq3), 4241077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(intc_ex_irq4), 4242077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(intc_ex_irq5), 4243077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof0_clk), 4244077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof0_sync), 4245077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof0_ss1), 4246077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof0_ss2), 4247077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof0_txd), 4248077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof0_rxd), 4249077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof1_clk_a), 4250077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof1_sync_a), 4251077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof1_ss1_a), 4252077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof1_ss2_a), 4253077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof1_txd_a), 4254077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof1_rxd_a), 4255077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof1_clk_b), 4256077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof1_sync_b), 4257077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof1_ss1_b), 4258077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof1_ss2_b), 4259077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof1_txd_b), 4260077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof1_rxd_b), 4261077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof1_clk_c), 4262077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof1_sync_c), 4263077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof1_ss1_c), 4264077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof1_ss2_c), 4265077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof1_txd_c), 4266077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof1_rxd_c), 4267077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof1_clk_d), 4268077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof1_sync_d), 4269077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof1_ss1_d), 4270077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof1_ss2_d), 4271077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof1_txd_d), 4272077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof1_rxd_d), 4273077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof1_clk_e), 4274077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof1_sync_e), 4275077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof1_ss1_e), 4276077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof1_ss2_e), 4277077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof1_txd_e), 4278077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof1_rxd_e), 4279077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof1_clk_f), 4280077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof1_sync_f), 4281077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof1_ss1_f), 4282077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof1_ss2_f), 4283077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof1_txd_f), 4284077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof1_rxd_f), 4285077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof1_clk_g), 4286077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof1_sync_g), 4287077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof1_ss1_g), 4288077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof1_ss2_g), 4289077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof1_txd_g), 4290077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof1_rxd_g), 4291077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof2_clk_a), 4292077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof2_sync_a), 4293077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof2_ss1_a), 4294077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof2_ss2_a), 4295077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof2_txd_a), 4296077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof2_rxd_a), 4297077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof2_clk_b), 4298077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof2_sync_b), 4299077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof2_ss1_b), 4300077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof2_ss2_b), 4301077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof2_txd_b), 4302077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof2_rxd_b), 4303077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof2_clk_c), 4304077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof2_sync_c), 4305077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof2_ss1_c), 4306077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof2_ss2_c), 4307077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof2_txd_c), 4308077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof2_rxd_c), 4309077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof2_clk_d), 4310077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof2_sync_d), 4311077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof2_ss1_d), 4312077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof2_ss2_d), 4313077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof2_txd_d), 4314077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof2_rxd_d), 4315077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof3_clk_a), 4316077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof3_sync_a), 4317077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof3_ss1_a), 4318077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof3_ss2_a), 4319077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof3_txd_a), 4320077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof3_rxd_a), 4321077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof3_clk_b), 4322077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof3_sync_b), 4323077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof3_ss1_b), 4324077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof3_ss2_b), 4325077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof3_txd_b), 4326077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof3_rxd_b), 4327077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof3_clk_c), 4328077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof3_sync_c), 4329077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof3_txd_c), 4330077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof3_rxd_c), 4331077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof3_clk_d), 4332077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof3_sync_d), 4333077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof3_ss1_d), 4334077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof3_txd_d), 4335077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof3_rxd_d), 4336077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof3_clk_e), 4337077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof3_sync_e), 4338077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof3_ss1_e), 4339077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof3_ss2_e), 4340077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof3_txd_e), 4341077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(msiof3_rxd_e), 4342077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(pwm0), 4343077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(pwm1_a), 4344077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(pwm1_b), 4345077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(pwm2_a), 4346077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(pwm2_b), 4347077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(pwm3_a), 4348077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(pwm3_b), 4349077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(pwm4_a), 4350077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(pwm4_b), 4351077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(pwm5_a), 4352077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(pwm5_b), 4353077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(pwm6_a), 4354077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(pwm6_b), 4355590567bfSLad Prabhakar SH_PFC_PIN_GROUP(qspi0_ctrl), 4356aaf186d8SGeert Uytterhoeven BUS_DATA_PIN_GROUP(qspi0_data, 2), 4357aaf186d8SGeert Uytterhoeven BUS_DATA_PIN_GROUP(qspi0_data, 4), 4358590567bfSLad Prabhakar SH_PFC_PIN_GROUP(qspi1_ctrl), 4359aaf186d8SGeert Uytterhoeven BUS_DATA_PIN_GROUP(qspi1_data, 2), 4360aaf186d8SGeert Uytterhoeven BUS_DATA_PIN_GROUP(qspi1_data, 4), 4361077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(sata0_devslp_a), 4362077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(sata0_devslp_b), 4363077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(scif0_data), 4364077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(scif0_clk), 4365077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(scif0_ctrl), 4366077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(scif1_data_a), 4367077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(scif1_clk), 4368077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(scif1_ctrl), 4369077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(scif1_data_b), 4370077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(scif2_data_a), 4371077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(scif2_clk), 4372077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(scif2_data_b), 4373077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(scif3_data_a), 4374077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(scif3_clk), 4375077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(scif3_ctrl), 4376077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(scif3_data_b), 4377077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(scif4_data_a), 4378077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(scif4_clk_a), 4379077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(scif4_ctrl_a), 4380077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(scif4_data_b), 4381077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(scif4_clk_b), 4382077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(scif4_ctrl_b), 4383077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(scif4_data_c), 4384077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(scif4_clk_c), 4385077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(scif4_ctrl_c), 4386077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(scif5_data_a), 4387077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(scif5_clk_a), 4388077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(scif5_data_b), 4389077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(scif5_clk_b), 4390077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(scif_clk_a), 4391077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(scif_clk_b), 4392c8c05e81SGeert Uytterhoeven BUS_DATA_PIN_GROUP(sdhi0_data, 1), 4393c8c05e81SGeert Uytterhoeven BUS_DATA_PIN_GROUP(sdhi0_data, 4), 4394077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(sdhi0_ctrl), 4395077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(sdhi0_cd), 4396077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(sdhi0_wp), 4397c8c05e81SGeert Uytterhoeven BUS_DATA_PIN_GROUP(sdhi1_data, 1), 4398c8c05e81SGeert Uytterhoeven BUS_DATA_PIN_GROUP(sdhi1_data, 4), 4399077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(sdhi1_ctrl), 4400077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(sdhi1_cd), 4401077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(sdhi1_wp), 4402c8c05e81SGeert Uytterhoeven BUS_DATA_PIN_GROUP(sdhi2_data, 1), 4403c8c05e81SGeert Uytterhoeven BUS_DATA_PIN_GROUP(sdhi2_data, 4), 4404c8c05e81SGeert Uytterhoeven BUS_DATA_PIN_GROUP(sdhi2_data, 8), 4405077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(sdhi2_ctrl), 4406077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(sdhi2_cd_a), 4407077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(sdhi2_wp_a), 4408077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(sdhi2_cd_b), 4409077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(sdhi2_wp_b), 4410077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(sdhi2_ds), 4411c8c05e81SGeert Uytterhoeven BUS_DATA_PIN_GROUP(sdhi3_data, 1), 4412c8c05e81SGeert Uytterhoeven BUS_DATA_PIN_GROUP(sdhi3_data, 4), 4413c8c05e81SGeert Uytterhoeven BUS_DATA_PIN_GROUP(sdhi3_data, 8), 4414077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(sdhi3_ctrl), 4415077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(sdhi3_cd), 4416077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(sdhi3_wp), 4417077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(sdhi3_ds), 4418077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(ssi0_data), 4419077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(ssi01239_ctrl), 4420077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(ssi1_data_a), 4421077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(ssi1_data_b), 4422077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(ssi1_ctrl_a), 4423077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(ssi1_ctrl_b), 4424077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(ssi2_data_a), 4425077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(ssi2_data_b), 4426077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(ssi2_ctrl_a), 4427077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(ssi2_ctrl_b), 4428077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(ssi3_data), 4429077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(ssi349_ctrl), 4430077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(ssi4_data), 4431077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(ssi4_ctrl), 4432077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(ssi5_data), 4433077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(ssi5_ctrl), 4434077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(ssi6_data), 4435077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(ssi6_ctrl), 4436077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(ssi7_data), 4437077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(ssi78_ctrl), 4438077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(ssi8_data), 4439077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(ssi9_data_a), 4440077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(ssi9_data_b), 4441077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(ssi9_ctrl_a), 4442077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(ssi9_ctrl_b), 4443077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(tmu_tclk1_a), 4444077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(tmu_tclk1_b), 4445077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(tmu_tclk2_a), 4446077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(tmu_tclk2_b), 4447077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(tpu_to0), 4448077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(tpu_to1), 4449077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(tpu_to2), 4450077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(tpu_to3), 4451077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(usb0), 4452077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(usb1), 4453077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(usb2), 4454077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(usb2_ch3), 4455077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(usb30), 4456496da100SGeert Uytterhoeven BUS_DATA_PIN_GROUP(vin4_data, 8, _a), 4457496da100SGeert Uytterhoeven BUS_DATA_PIN_GROUP(vin4_data, 10, _a), 4458496da100SGeert Uytterhoeven BUS_DATA_PIN_GROUP(vin4_data, 12, _a), 4459496da100SGeert Uytterhoeven BUS_DATA_PIN_GROUP(vin4_data, 16, _a), 4460077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(vin4_data18_a), 4461496da100SGeert Uytterhoeven BUS_DATA_PIN_GROUP(vin4_data, 20, _a), 4462496da100SGeert Uytterhoeven BUS_DATA_PIN_GROUP(vin4_data, 24, _a), 4463496da100SGeert Uytterhoeven BUS_DATA_PIN_GROUP(vin4_data, 8, _b), 4464496da100SGeert Uytterhoeven BUS_DATA_PIN_GROUP(vin4_data, 10, _b), 4465496da100SGeert Uytterhoeven BUS_DATA_PIN_GROUP(vin4_data, 12, _b), 4466496da100SGeert Uytterhoeven BUS_DATA_PIN_GROUP(vin4_data, 16, _b), 4467077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(vin4_data18_b), 4468496da100SGeert Uytterhoeven BUS_DATA_PIN_GROUP(vin4_data, 20, _b), 4469496da100SGeert Uytterhoeven BUS_DATA_PIN_GROUP(vin4_data, 24, _b), 44700b4423f7SGeert Uytterhoeven SH_PFC_PIN_GROUP_SUBSET(vin4_g8, vin4_data_a, 8, 8), 4471077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(vin4_sync), 4472077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(vin4_field), 4473077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(vin4_clkenb), 4474077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(vin4_clk), 4475496da100SGeert Uytterhoeven BUS_DATA_PIN_GROUP(vin5_data, 8), 4476496da100SGeert Uytterhoeven BUS_DATA_PIN_GROUP(vin5_data, 10), 4477496da100SGeert Uytterhoeven BUS_DATA_PIN_GROUP(vin5_data, 12), 4478496da100SGeert Uytterhoeven BUS_DATA_PIN_GROUP(vin5_data, 16), 44790b4423f7SGeert Uytterhoeven SH_PFC_PIN_GROUP_SUBSET(vin5_high8, vin5_data, 8, 8), 4480077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(vin5_sync), 4481077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(vin5_field), 4482077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(vin5_clkenb), 4483077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(vin5_clk), 4484077365a9SGeert Uytterhoeven }, 4485b8029394SBiju Das #ifdef CONFIG_PINCTRL_PFC_R8A77951 4486077365a9SGeert Uytterhoeven .automotive = { 4487077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(drif0_ctrl_a), 4488077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(drif0_data0_a), 4489077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(drif0_data1_a), 4490077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(drif0_ctrl_b), 4491077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(drif0_data0_b), 4492077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(drif0_data1_b), 4493077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(drif0_ctrl_c), 4494077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(drif0_data0_c), 4495077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(drif0_data1_c), 4496077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(drif1_ctrl_a), 4497077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(drif1_data0_a), 4498077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(drif1_data1_a), 4499077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(drif1_ctrl_b), 4500077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(drif1_data0_b), 4501077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(drif1_data1_b), 4502077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(drif1_ctrl_c), 4503077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(drif1_data0_c), 4504077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(drif1_data1_c), 4505077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(drif2_ctrl_a), 4506077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(drif2_data0_a), 4507077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(drif2_data1_a), 4508077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(drif2_ctrl_b), 4509077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(drif2_data0_b), 4510077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(drif2_data1_b), 4511077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(drif3_ctrl_a), 4512077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(drif3_data0_a), 4513077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(drif3_data1_a), 4514077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(drif3_ctrl_b), 4515077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(drif3_data0_b), 4516077365a9SGeert Uytterhoeven SH_PFC_PIN_GROUP(drif3_data1_b), 4517ce34fb3cSAndrey Gusakov SH_PFC_PIN_GROUP(mlb_3pin), 4518077365a9SGeert Uytterhoeven } 4519b8029394SBiju Das #endif /* CONFIG_PINCTRL_PFC_R8A77951 */ 4520077365a9SGeert Uytterhoeven }; 4521077365a9SGeert Uytterhoeven 4522077365a9SGeert Uytterhoeven static const char * const audio_clk_groups[] = { 4523077365a9SGeert Uytterhoeven "audio_clk_a_a", 4524077365a9SGeert Uytterhoeven "audio_clk_a_b", 4525077365a9SGeert Uytterhoeven "audio_clk_a_c", 4526077365a9SGeert Uytterhoeven "audio_clk_b_a", 4527077365a9SGeert Uytterhoeven "audio_clk_b_b", 4528077365a9SGeert Uytterhoeven "audio_clk_c_a", 4529077365a9SGeert Uytterhoeven "audio_clk_c_b", 4530077365a9SGeert Uytterhoeven "audio_clkout_a", 4531077365a9SGeert Uytterhoeven "audio_clkout_b", 4532077365a9SGeert Uytterhoeven "audio_clkout_c", 4533077365a9SGeert Uytterhoeven "audio_clkout_d", 4534077365a9SGeert Uytterhoeven "audio_clkout1_a", 4535077365a9SGeert Uytterhoeven "audio_clkout1_b", 4536077365a9SGeert Uytterhoeven "audio_clkout2_a", 4537077365a9SGeert Uytterhoeven "audio_clkout2_b", 4538077365a9SGeert Uytterhoeven "audio_clkout3_a", 4539077365a9SGeert Uytterhoeven "audio_clkout3_b", 4540077365a9SGeert Uytterhoeven }; 4541077365a9SGeert Uytterhoeven 4542077365a9SGeert Uytterhoeven static const char * const avb_groups[] = { 4543077365a9SGeert Uytterhoeven "avb_link", 4544077365a9SGeert Uytterhoeven "avb_magic", 4545077365a9SGeert Uytterhoeven "avb_phy_int", 4546077365a9SGeert Uytterhoeven "avb_mdc", /* Deprecated, please use "avb_mdio" instead */ 4547077365a9SGeert Uytterhoeven "avb_mdio", 4548077365a9SGeert Uytterhoeven "avb_mii", 4549077365a9SGeert Uytterhoeven "avb_avtp_pps", 4550077365a9SGeert Uytterhoeven "avb_avtp_match_a", 4551077365a9SGeert Uytterhoeven "avb_avtp_capture_a", 4552077365a9SGeert Uytterhoeven "avb_avtp_match_b", 4553077365a9SGeert Uytterhoeven "avb_avtp_capture_b", 4554077365a9SGeert Uytterhoeven }; 4555077365a9SGeert Uytterhoeven 4556077365a9SGeert Uytterhoeven static const char * const can0_groups[] = { 4557077365a9SGeert Uytterhoeven "can0_data_a", 4558077365a9SGeert Uytterhoeven "can0_data_b", 4559077365a9SGeert Uytterhoeven }; 4560077365a9SGeert Uytterhoeven 4561077365a9SGeert Uytterhoeven static const char * const can1_groups[] = { 4562077365a9SGeert Uytterhoeven "can1_data", 4563077365a9SGeert Uytterhoeven }; 4564077365a9SGeert Uytterhoeven 4565077365a9SGeert Uytterhoeven static const char * const can_clk_groups[] = { 4566077365a9SGeert Uytterhoeven "can_clk", 4567077365a9SGeert Uytterhoeven }; 4568077365a9SGeert Uytterhoeven 4569077365a9SGeert Uytterhoeven static const char * const canfd0_groups[] = { 4570077365a9SGeert Uytterhoeven "canfd0_data_a", 4571077365a9SGeert Uytterhoeven "canfd0_data_b", 4572077365a9SGeert Uytterhoeven }; 4573077365a9SGeert Uytterhoeven 4574077365a9SGeert Uytterhoeven static const char * const canfd1_groups[] = { 4575077365a9SGeert Uytterhoeven "canfd1_data", 4576077365a9SGeert Uytterhoeven }; 4577077365a9SGeert Uytterhoeven 4578b8029394SBiju Das #ifdef CONFIG_PINCTRL_PFC_R8A77951 4579077365a9SGeert Uytterhoeven static const char * const drif0_groups[] = { 4580077365a9SGeert Uytterhoeven "drif0_ctrl_a", 4581077365a9SGeert Uytterhoeven "drif0_data0_a", 4582077365a9SGeert Uytterhoeven "drif0_data1_a", 4583077365a9SGeert Uytterhoeven "drif0_ctrl_b", 4584077365a9SGeert Uytterhoeven "drif0_data0_b", 4585077365a9SGeert Uytterhoeven "drif0_data1_b", 4586077365a9SGeert Uytterhoeven "drif0_ctrl_c", 4587077365a9SGeert Uytterhoeven "drif0_data0_c", 4588077365a9SGeert Uytterhoeven "drif0_data1_c", 4589077365a9SGeert Uytterhoeven }; 4590077365a9SGeert Uytterhoeven 4591077365a9SGeert Uytterhoeven static const char * const drif1_groups[] = { 4592077365a9SGeert Uytterhoeven "drif1_ctrl_a", 4593077365a9SGeert Uytterhoeven "drif1_data0_a", 4594077365a9SGeert Uytterhoeven "drif1_data1_a", 4595077365a9SGeert Uytterhoeven "drif1_ctrl_b", 4596077365a9SGeert Uytterhoeven "drif1_data0_b", 4597077365a9SGeert Uytterhoeven "drif1_data1_b", 4598077365a9SGeert Uytterhoeven "drif1_ctrl_c", 4599077365a9SGeert Uytterhoeven "drif1_data0_c", 4600077365a9SGeert Uytterhoeven "drif1_data1_c", 4601077365a9SGeert Uytterhoeven }; 4602077365a9SGeert Uytterhoeven 4603077365a9SGeert Uytterhoeven static const char * const drif2_groups[] = { 4604077365a9SGeert Uytterhoeven "drif2_ctrl_a", 4605077365a9SGeert Uytterhoeven "drif2_data0_a", 4606077365a9SGeert Uytterhoeven "drif2_data1_a", 4607077365a9SGeert Uytterhoeven "drif2_ctrl_b", 4608077365a9SGeert Uytterhoeven "drif2_data0_b", 4609077365a9SGeert Uytterhoeven "drif2_data1_b", 4610077365a9SGeert Uytterhoeven }; 4611077365a9SGeert Uytterhoeven 4612077365a9SGeert Uytterhoeven static const char * const drif3_groups[] = { 4613077365a9SGeert Uytterhoeven "drif3_ctrl_a", 4614077365a9SGeert Uytterhoeven "drif3_data0_a", 4615077365a9SGeert Uytterhoeven "drif3_data1_a", 4616077365a9SGeert Uytterhoeven "drif3_ctrl_b", 4617077365a9SGeert Uytterhoeven "drif3_data0_b", 4618077365a9SGeert Uytterhoeven "drif3_data1_b", 4619077365a9SGeert Uytterhoeven }; 4620b8029394SBiju Das #endif /* CONFIG_PINCTRL_PFC_R8A77951 */ 4621077365a9SGeert Uytterhoeven 4622077365a9SGeert Uytterhoeven static const char * const du_groups[] = { 4623077365a9SGeert Uytterhoeven "du_rgb666", 4624077365a9SGeert Uytterhoeven "du_rgb888", 4625077365a9SGeert Uytterhoeven "du_clk_out_0", 4626077365a9SGeert Uytterhoeven "du_clk_out_1", 4627077365a9SGeert Uytterhoeven "du_sync", 4628077365a9SGeert Uytterhoeven "du_oddf", 4629077365a9SGeert Uytterhoeven "du_cde", 4630077365a9SGeert Uytterhoeven "du_disp", 4631077365a9SGeert Uytterhoeven }; 4632077365a9SGeert Uytterhoeven 4633077365a9SGeert Uytterhoeven static const char * const hscif0_groups[] = { 4634077365a9SGeert Uytterhoeven "hscif0_data", 4635077365a9SGeert Uytterhoeven "hscif0_clk", 4636077365a9SGeert Uytterhoeven "hscif0_ctrl", 4637077365a9SGeert Uytterhoeven }; 4638077365a9SGeert Uytterhoeven 4639077365a9SGeert Uytterhoeven static const char * const hscif1_groups[] = { 4640077365a9SGeert Uytterhoeven "hscif1_data_a", 4641077365a9SGeert Uytterhoeven "hscif1_clk_a", 4642077365a9SGeert Uytterhoeven "hscif1_ctrl_a", 4643077365a9SGeert Uytterhoeven "hscif1_data_b", 4644077365a9SGeert Uytterhoeven "hscif1_clk_b", 4645077365a9SGeert Uytterhoeven "hscif1_ctrl_b", 4646077365a9SGeert Uytterhoeven }; 4647077365a9SGeert Uytterhoeven 4648077365a9SGeert Uytterhoeven static const char * const hscif2_groups[] = { 4649077365a9SGeert Uytterhoeven "hscif2_data_a", 4650077365a9SGeert Uytterhoeven "hscif2_clk_a", 4651077365a9SGeert Uytterhoeven "hscif2_ctrl_a", 4652077365a9SGeert Uytterhoeven "hscif2_data_b", 4653077365a9SGeert Uytterhoeven "hscif2_clk_b", 4654077365a9SGeert Uytterhoeven "hscif2_ctrl_b", 4655077365a9SGeert Uytterhoeven "hscif2_data_c", 4656077365a9SGeert Uytterhoeven "hscif2_clk_c", 4657077365a9SGeert Uytterhoeven "hscif2_ctrl_c", 4658077365a9SGeert Uytterhoeven }; 4659077365a9SGeert Uytterhoeven 4660077365a9SGeert Uytterhoeven static const char * const hscif3_groups[] = { 4661077365a9SGeert Uytterhoeven "hscif3_data_a", 4662077365a9SGeert Uytterhoeven "hscif3_clk", 4663077365a9SGeert Uytterhoeven "hscif3_ctrl", 4664077365a9SGeert Uytterhoeven "hscif3_data_b", 4665077365a9SGeert Uytterhoeven "hscif3_data_c", 4666077365a9SGeert Uytterhoeven "hscif3_data_d", 4667077365a9SGeert Uytterhoeven }; 4668077365a9SGeert Uytterhoeven 4669077365a9SGeert Uytterhoeven static const char * const hscif4_groups[] = { 4670077365a9SGeert Uytterhoeven "hscif4_data_a", 4671077365a9SGeert Uytterhoeven "hscif4_clk", 4672077365a9SGeert Uytterhoeven "hscif4_ctrl", 4673077365a9SGeert Uytterhoeven "hscif4_data_b", 4674077365a9SGeert Uytterhoeven }; 4675077365a9SGeert Uytterhoeven 4676077365a9SGeert Uytterhoeven static const char * const i2c0_groups[] = { 4677077365a9SGeert Uytterhoeven "i2c0", 4678077365a9SGeert Uytterhoeven }; 4679077365a9SGeert Uytterhoeven 4680077365a9SGeert Uytterhoeven static const char * const i2c1_groups[] = { 4681077365a9SGeert Uytterhoeven "i2c1_a", 4682077365a9SGeert Uytterhoeven "i2c1_b", 4683077365a9SGeert Uytterhoeven }; 4684077365a9SGeert Uytterhoeven 4685077365a9SGeert Uytterhoeven static const char * const i2c2_groups[] = { 4686077365a9SGeert Uytterhoeven "i2c2_a", 4687077365a9SGeert Uytterhoeven "i2c2_b", 4688077365a9SGeert Uytterhoeven }; 4689077365a9SGeert Uytterhoeven 4690077365a9SGeert Uytterhoeven static const char * const i2c3_groups[] = { 4691077365a9SGeert Uytterhoeven "i2c3", 4692077365a9SGeert Uytterhoeven }; 4693077365a9SGeert Uytterhoeven 4694077365a9SGeert Uytterhoeven static const char * const i2c5_groups[] = { 4695077365a9SGeert Uytterhoeven "i2c5", 4696077365a9SGeert Uytterhoeven }; 4697077365a9SGeert Uytterhoeven 4698077365a9SGeert Uytterhoeven static const char * const i2c6_groups[] = { 4699077365a9SGeert Uytterhoeven "i2c6_a", 4700077365a9SGeert Uytterhoeven "i2c6_b", 4701077365a9SGeert Uytterhoeven "i2c6_c", 4702077365a9SGeert Uytterhoeven }; 4703077365a9SGeert Uytterhoeven 4704077365a9SGeert Uytterhoeven static const char * const intc_ex_groups[] = { 4705077365a9SGeert Uytterhoeven "intc_ex_irq0", 4706077365a9SGeert Uytterhoeven "intc_ex_irq1", 4707077365a9SGeert Uytterhoeven "intc_ex_irq2", 4708077365a9SGeert Uytterhoeven "intc_ex_irq3", 4709077365a9SGeert Uytterhoeven "intc_ex_irq4", 4710077365a9SGeert Uytterhoeven "intc_ex_irq5", 4711077365a9SGeert Uytterhoeven }; 4712077365a9SGeert Uytterhoeven 4713ce34fb3cSAndrey Gusakov #ifdef CONFIG_PINCTRL_PFC_R8A77951 4714ce34fb3cSAndrey Gusakov static const char * const mlb_3pin_groups[] = { 4715ce34fb3cSAndrey Gusakov "mlb_3pin", 4716ce34fb3cSAndrey Gusakov }; 4717ce34fb3cSAndrey Gusakov #endif /* CONFIG_PINCTRL_PFC_R8A77951 */ 4718ce34fb3cSAndrey Gusakov 4719077365a9SGeert Uytterhoeven static const char * const msiof0_groups[] = { 4720077365a9SGeert Uytterhoeven "msiof0_clk", 4721077365a9SGeert Uytterhoeven "msiof0_sync", 4722077365a9SGeert Uytterhoeven "msiof0_ss1", 4723077365a9SGeert Uytterhoeven "msiof0_ss2", 4724077365a9SGeert Uytterhoeven "msiof0_txd", 4725077365a9SGeert Uytterhoeven "msiof0_rxd", 4726077365a9SGeert Uytterhoeven }; 4727077365a9SGeert Uytterhoeven 4728077365a9SGeert Uytterhoeven static const char * const msiof1_groups[] = { 4729077365a9SGeert Uytterhoeven "msiof1_clk_a", 4730077365a9SGeert Uytterhoeven "msiof1_sync_a", 4731077365a9SGeert Uytterhoeven "msiof1_ss1_a", 4732077365a9SGeert Uytterhoeven "msiof1_ss2_a", 4733077365a9SGeert Uytterhoeven "msiof1_txd_a", 4734077365a9SGeert Uytterhoeven "msiof1_rxd_a", 4735077365a9SGeert Uytterhoeven "msiof1_clk_b", 4736077365a9SGeert Uytterhoeven "msiof1_sync_b", 4737077365a9SGeert Uytterhoeven "msiof1_ss1_b", 4738077365a9SGeert Uytterhoeven "msiof1_ss2_b", 4739077365a9SGeert Uytterhoeven "msiof1_txd_b", 4740077365a9SGeert Uytterhoeven "msiof1_rxd_b", 4741077365a9SGeert Uytterhoeven "msiof1_clk_c", 4742077365a9SGeert Uytterhoeven "msiof1_sync_c", 4743077365a9SGeert Uytterhoeven "msiof1_ss1_c", 4744077365a9SGeert Uytterhoeven "msiof1_ss2_c", 4745077365a9SGeert Uytterhoeven "msiof1_txd_c", 4746077365a9SGeert Uytterhoeven "msiof1_rxd_c", 4747077365a9SGeert Uytterhoeven "msiof1_clk_d", 4748077365a9SGeert Uytterhoeven "msiof1_sync_d", 4749077365a9SGeert Uytterhoeven "msiof1_ss1_d", 4750077365a9SGeert Uytterhoeven "msiof1_ss2_d", 4751077365a9SGeert Uytterhoeven "msiof1_txd_d", 4752077365a9SGeert Uytterhoeven "msiof1_rxd_d", 4753077365a9SGeert Uytterhoeven "msiof1_clk_e", 4754077365a9SGeert Uytterhoeven "msiof1_sync_e", 4755077365a9SGeert Uytterhoeven "msiof1_ss1_e", 4756077365a9SGeert Uytterhoeven "msiof1_ss2_e", 4757077365a9SGeert Uytterhoeven "msiof1_txd_e", 4758077365a9SGeert Uytterhoeven "msiof1_rxd_e", 4759077365a9SGeert Uytterhoeven "msiof1_clk_f", 4760077365a9SGeert Uytterhoeven "msiof1_sync_f", 4761077365a9SGeert Uytterhoeven "msiof1_ss1_f", 4762077365a9SGeert Uytterhoeven "msiof1_ss2_f", 4763077365a9SGeert Uytterhoeven "msiof1_txd_f", 4764077365a9SGeert Uytterhoeven "msiof1_rxd_f", 4765077365a9SGeert Uytterhoeven "msiof1_clk_g", 4766077365a9SGeert Uytterhoeven "msiof1_sync_g", 4767077365a9SGeert Uytterhoeven "msiof1_ss1_g", 4768077365a9SGeert Uytterhoeven "msiof1_ss2_g", 4769077365a9SGeert Uytterhoeven "msiof1_txd_g", 4770077365a9SGeert Uytterhoeven "msiof1_rxd_g", 4771077365a9SGeert Uytterhoeven }; 4772077365a9SGeert Uytterhoeven 4773077365a9SGeert Uytterhoeven static const char * const msiof2_groups[] = { 4774077365a9SGeert Uytterhoeven "msiof2_clk_a", 4775077365a9SGeert Uytterhoeven "msiof2_sync_a", 4776077365a9SGeert Uytterhoeven "msiof2_ss1_a", 4777077365a9SGeert Uytterhoeven "msiof2_ss2_a", 4778077365a9SGeert Uytterhoeven "msiof2_txd_a", 4779077365a9SGeert Uytterhoeven "msiof2_rxd_a", 4780077365a9SGeert Uytterhoeven "msiof2_clk_b", 4781077365a9SGeert Uytterhoeven "msiof2_sync_b", 4782077365a9SGeert Uytterhoeven "msiof2_ss1_b", 4783077365a9SGeert Uytterhoeven "msiof2_ss2_b", 4784077365a9SGeert Uytterhoeven "msiof2_txd_b", 4785077365a9SGeert Uytterhoeven "msiof2_rxd_b", 4786077365a9SGeert Uytterhoeven "msiof2_clk_c", 4787077365a9SGeert Uytterhoeven "msiof2_sync_c", 4788077365a9SGeert Uytterhoeven "msiof2_ss1_c", 4789077365a9SGeert Uytterhoeven "msiof2_ss2_c", 4790077365a9SGeert Uytterhoeven "msiof2_txd_c", 4791077365a9SGeert Uytterhoeven "msiof2_rxd_c", 4792077365a9SGeert Uytterhoeven "msiof2_clk_d", 4793077365a9SGeert Uytterhoeven "msiof2_sync_d", 4794077365a9SGeert Uytterhoeven "msiof2_ss1_d", 4795077365a9SGeert Uytterhoeven "msiof2_ss2_d", 4796077365a9SGeert Uytterhoeven "msiof2_txd_d", 4797077365a9SGeert Uytterhoeven "msiof2_rxd_d", 4798077365a9SGeert Uytterhoeven }; 4799077365a9SGeert Uytterhoeven 4800077365a9SGeert Uytterhoeven static const char * const msiof3_groups[] = { 4801077365a9SGeert Uytterhoeven "msiof3_clk_a", 4802077365a9SGeert Uytterhoeven "msiof3_sync_a", 4803077365a9SGeert Uytterhoeven "msiof3_ss1_a", 4804077365a9SGeert Uytterhoeven "msiof3_ss2_a", 4805077365a9SGeert Uytterhoeven "msiof3_txd_a", 4806077365a9SGeert Uytterhoeven "msiof3_rxd_a", 4807077365a9SGeert Uytterhoeven "msiof3_clk_b", 4808077365a9SGeert Uytterhoeven "msiof3_sync_b", 4809077365a9SGeert Uytterhoeven "msiof3_ss1_b", 4810077365a9SGeert Uytterhoeven "msiof3_ss2_b", 4811077365a9SGeert Uytterhoeven "msiof3_txd_b", 4812077365a9SGeert Uytterhoeven "msiof3_rxd_b", 4813077365a9SGeert Uytterhoeven "msiof3_clk_c", 4814077365a9SGeert Uytterhoeven "msiof3_sync_c", 4815077365a9SGeert Uytterhoeven "msiof3_txd_c", 4816077365a9SGeert Uytterhoeven "msiof3_rxd_c", 4817077365a9SGeert Uytterhoeven "msiof3_clk_d", 4818077365a9SGeert Uytterhoeven "msiof3_sync_d", 4819077365a9SGeert Uytterhoeven "msiof3_ss1_d", 4820077365a9SGeert Uytterhoeven "msiof3_txd_d", 4821077365a9SGeert Uytterhoeven "msiof3_rxd_d", 4822077365a9SGeert Uytterhoeven "msiof3_clk_e", 4823077365a9SGeert Uytterhoeven "msiof3_sync_e", 4824077365a9SGeert Uytterhoeven "msiof3_ss1_e", 4825077365a9SGeert Uytterhoeven "msiof3_ss2_e", 4826077365a9SGeert Uytterhoeven "msiof3_txd_e", 4827077365a9SGeert Uytterhoeven "msiof3_rxd_e", 4828077365a9SGeert Uytterhoeven }; 4829077365a9SGeert Uytterhoeven 4830077365a9SGeert Uytterhoeven static const char * const pwm0_groups[] = { 4831077365a9SGeert Uytterhoeven "pwm0", 4832077365a9SGeert Uytterhoeven }; 4833077365a9SGeert Uytterhoeven 4834077365a9SGeert Uytterhoeven static const char * const pwm1_groups[] = { 4835077365a9SGeert Uytterhoeven "pwm1_a", 4836077365a9SGeert Uytterhoeven "pwm1_b", 4837077365a9SGeert Uytterhoeven }; 4838077365a9SGeert Uytterhoeven 4839077365a9SGeert Uytterhoeven static const char * const pwm2_groups[] = { 4840077365a9SGeert Uytterhoeven "pwm2_a", 4841077365a9SGeert Uytterhoeven "pwm2_b", 4842077365a9SGeert Uytterhoeven }; 4843077365a9SGeert Uytterhoeven 4844077365a9SGeert Uytterhoeven static const char * const pwm3_groups[] = { 4845077365a9SGeert Uytterhoeven "pwm3_a", 4846077365a9SGeert Uytterhoeven "pwm3_b", 4847077365a9SGeert Uytterhoeven }; 4848077365a9SGeert Uytterhoeven 4849077365a9SGeert Uytterhoeven static const char * const pwm4_groups[] = { 4850077365a9SGeert Uytterhoeven "pwm4_a", 4851077365a9SGeert Uytterhoeven "pwm4_b", 4852077365a9SGeert Uytterhoeven }; 4853077365a9SGeert Uytterhoeven 4854077365a9SGeert Uytterhoeven static const char * const pwm5_groups[] = { 4855077365a9SGeert Uytterhoeven "pwm5_a", 4856077365a9SGeert Uytterhoeven "pwm5_b", 4857077365a9SGeert Uytterhoeven }; 4858077365a9SGeert Uytterhoeven 4859077365a9SGeert Uytterhoeven static const char * const pwm6_groups[] = { 4860077365a9SGeert Uytterhoeven "pwm6_a", 4861077365a9SGeert Uytterhoeven "pwm6_b", 4862077365a9SGeert Uytterhoeven }; 4863077365a9SGeert Uytterhoeven 4864590567bfSLad Prabhakar static const char * const qspi0_groups[] = { 4865590567bfSLad Prabhakar "qspi0_ctrl", 4866590567bfSLad Prabhakar "qspi0_data2", 4867590567bfSLad Prabhakar "qspi0_data4", 4868590567bfSLad Prabhakar }; 4869590567bfSLad Prabhakar 4870590567bfSLad Prabhakar static const char * const qspi1_groups[] = { 4871590567bfSLad Prabhakar "qspi1_ctrl", 4872590567bfSLad Prabhakar "qspi1_data2", 4873590567bfSLad Prabhakar "qspi1_data4", 4874590567bfSLad Prabhakar }; 4875590567bfSLad Prabhakar 4876077365a9SGeert Uytterhoeven static const char * const sata0_groups[] = { 4877077365a9SGeert Uytterhoeven "sata0_devslp_a", 4878077365a9SGeert Uytterhoeven "sata0_devslp_b", 4879077365a9SGeert Uytterhoeven }; 4880077365a9SGeert Uytterhoeven 4881077365a9SGeert Uytterhoeven static const char * const scif0_groups[] = { 4882077365a9SGeert Uytterhoeven "scif0_data", 4883077365a9SGeert Uytterhoeven "scif0_clk", 4884077365a9SGeert Uytterhoeven "scif0_ctrl", 4885077365a9SGeert Uytterhoeven }; 4886077365a9SGeert Uytterhoeven 4887077365a9SGeert Uytterhoeven static const char * const scif1_groups[] = { 4888077365a9SGeert Uytterhoeven "scif1_data_a", 4889077365a9SGeert Uytterhoeven "scif1_clk", 4890077365a9SGeert Uytterhoeven "scif1_ctrl", 4891077365a9SGeert Uytterhoeven "scif1_data_b", 4892077365a9SGeert Uytterhoeven }; 4893077365a9SGeert Uytterhoeven 4894077365a9SGeert Uytterhoeven static const char * const scif2_groups[] = { 4895077365a9SGeert Uytterhoeven "scif2_data_a", 4896077365a9SGeert Uytterhoeven "scif2_clk", 4897077365a9SGeert Uytterhoeven "scif2_data_b", 4898077365a9SGeert Uytterhoeven }; 4899077365a9SGeert Uytterhoeven 4900077365a9SGeert Uytterhoeven static const char * const scif3_groups[] = { 4901077365a9SGeert Uytterhoeven "scif3_data_a", 4902077365a9SGeert Uytterhoeven "scif3_clk", 4903077365a9SGeert Uytterhoeven "scif3_ctrl", 4904077365a9SGeert Uytterhoeven "scif3_data_b", 4905077365a9SGeert Uytterhoeven }; 4906077365a9SGeert Uytterhoeven 4907077365a9SGeert Uytterhoeven static const char * const scif4_groups[] = { 4908077365a9SGeert Uytterhoeven "scif4_data_a", 4909077365a9SGeert Uytterhoeven "scif4_clk_a", 4910077365a9SGeert Uytterhoeven "scif4_ctrl_a", 4911077365a9SGeert Uytterhoeven "scif4_data_b", 4912077365a9SGeert Uytterhoeven "scif4_clk_b", 4913077365a9SGeert Uytterhoeven "scif4_ctrl_b", 4914077365a9SGeert Uytterhoeven "scif4_data_c", 4915077365a9SGeert Uytterhoeven "scif4_clk_c", 4916077365a9SGeert Uytterhoeven "scif4_ctrl_c", 4917077365a9SGeert Uytterhoeven }; 4918077365a9SGeert Uytterhoeven 4919077365a9SGeert Uytterhoeven static const char * const scif5_groups[] = { 4920077365a9SGeert Uytterhoeven "scif5_data_a", 4921077365a9SGeert Uytterhoeven "scif5_clk_a", 4922077365a9SGeert Uytterhoeven "scif5_data_b", 4923077365a9SGeert Uytterhoeven "scif5_clk_b", 4924077365a9SGeert Uytterhoeven }; 4925077365a9SGeert Uytterhoeven 4926077365a9SGeert Uytterhoeven static const char * const scif_clk_groups[] = { 4927077365a9SGeert Uytterhoeven "scif_clk_a", 4928077365a9SGeert Uytterhoeven "scif_clk_b", 4929077365a9SGeert Uytterhoeven }; 4930077365a9SGeert Uytterhoeven 4931077365a9SGeert Uytterhoeven static const char * const sdhi0_groups[] = { 4932077365a9SGeert Uytterhoeven "sdhi0_data1", 4933077365a9SGeert Uytterhoeven "sdhi0_data4", 4934077365a9SGeert Uytterhoeven "sdhi0_ctrl", 4935077365a9SGeert Uytterhoeven "sdhi0_cd", 4936077365a9SGeert Uytterhoeven "sdhi0_wp", 4937077365a9SGeert Uytterhoeven }; 4938077365a9SGeert Uytterhoeven 4939077365a9SGeert Uytterhoeven static const char * const sdhi1_groups[] = { 4940077365a9SGeert Uytterhoeven "sdhi1_data1", 4941077365a9SGeert Uytterhoeven "sdhi1_data4", 4942077365a9SGeert Uytterhoeven "sdhi1_ctrl", 4943077365a9SGeert Uytterhoeven "sdhi1_cd", 4944077365a9SGeert Uytterhoeven "sdhi1_wp", 4945077365a9SGeert Uytterhoeven }; 4946077365a9SGeert Uytterhoeven 4947077365a9SGeert Uytterhoeven static const char * const sdhi2_groups[] = { 4948077365a9SGeert Uytterhoeven "sdhi2_data1", 4949077365a9SGeert Uytterhoeven "sdhi2_data4", 4950077365a9SGeert Uytterhoeven "sdhi2_data8", 4951077365a9SGeert Uytterhoeven "sdhi2_ctrl", 4952077365a9SGeert Uytterhoeven "sdhi2_cd_a", 4953077365a9SGeert Uytterhoeven "sdhi2_wp_a", 4954077365a9SGeert Uytterhoeven "sdhi2_cd_b", 4955077365a9SGeert Uytterhoeven "sdhi2_wp_b", 4956077365a9SGeert Uytterhoeven "sdhi2_ds", 4957077365a9SGeert Uytterhoeven }; 4958077365a9SGeert Uytterhoeven 4959077365a9SGeert Uytterhoeven static const char * const sdhi3_groups[] = { 4960077365a9SGeert Uytterhoeven "sdhi3_data1", 4961077365a9SGeert Uytterhoeven "sdhi3_data4", 4962077365a9SGeert Uytterhoeven "sdhi3_data8", 4963077365a9SGeert Uytterhoeven "sdhi3_ctrl", 4964077365a9SGeert Uytterhoeven "sdhi3_cd", 4965077365a9SGeert Uytterhoeven "sdhi3_wp", 4966077365a9SGeert Uytterhoeven "sdhi3_ds", 4967077365a9SGeert Uytterhoeven }; 4968077365a9SGeert Uytterhoeven 4969077365a9SGeert Uytterhoeven static const char * const ssi_groups[] = { 4970077365a9SGeert Uytterhoeven "ssi0_data", 4971077365a9SGeert Uytterhoeven "ssi01239_ctrl", 4972077365a9SGeert Uytterhoeven "ssi1_data_a", 4973077365a9SGeert Uytterhoeven "ssi1_data_b", 4974077365a9SGeert Uytterhoeven "ssi1_ctrl_a", 4975077365a9SGeert Uytterhoeven "ssi1_ctrl_b", 4976077365a9SGeert Uytterhoeven "ssi2_data_a", 4977077365a9SGeert Uytterhoeven "ssi2_data_b", 4978077365a9SGeert Uytterhoeven "ssi2_ctrl_a", 4979077365a9SGeert Uytterhoeven "ssi2_ctrl_b", 4980077365a9SGeert Uytterhoeven "ssi3_data", 4981077365a9SGeert Uytterhoeven "ssi349_ctrl", 4982077365a9SGeert Uytterhoeven "ssi4_data", 4983077365a9SGeert Uytterhoeven "ssi4_ctrl", 4984077365a9SGeert Uytterhoeven "ssi5_data", 4985077365a9SGeert Uytterhoeven "ssi5_ctrl", 4986077365a9SGeert Uytterhoeven "ssi6_data", 4987077365a9SGeert Uytterhoeven "ssi6_ctrl", 4988077365a9SGeert Uytterhoeven "ssi7_data", 4989077365a9SGeert Uytterhoeven "ssi78_ctrl", 4990077365a9SGeert Uytterhoeven "ssi8_data", 4991077365a9SGeert Uytterhoeven "ssi9_data_a", 4992077365a9SGeert Uytterhoeven "ssi9_data_b", 4993077365a9SGeert Uytterhoeven "ssi9_ctrl_a", 4994077365a9SGeert Uytterhoeven "ssi9_ctrl_b", 4995077365a9SGeert Uytterhoeven }; 4996077365a9SGeert Uytterhoeven 4997077365a9SGeert Uytterhoeven static const char * const tmu_groups[] = { 4998077365a9SGeert Uytterhoeven "tmu_tclk1_a", 4999077365a9SGeert Uytterhoeven "tmu_tclk1_b", 5000077365a9SGeert Uytterhoeven "tmu_tclk2_a", 5001077365a9SGeert Uytterhoeven "tmu_tclk2_b", 5002077365a9SGeert Uytterhoeven }; 5003077365a9SGeert Uytterhoeven 5004077365a9SGeert Uytterhoeven static const char * const tpu_groups[] = { 5005077365a9SGeert Uytterhoeven "tpu_to0", 5006077365a9SGeert Uytterhoeven "tpu_to1", 5007077365a9SGeert Uytterhoeven "tpu_to2", 5008077365a9SGeert Uytterhoeven "tpu_to3", 5009077365a9SGeert Uytterhoeven }; 5010077365a9SGeert Uytterhoeven 5011077365a9SGeert Uytterhoeven static const char * const usb0_groups[] = { 5012077365a9SGeert Uytterhoeven "usb0", 5013077365a9SGeert Uytterhoeven }; 5014077365a9SGeert Uytterhoeven 5015077365a9SGeert Uytterhoeven static const char * const usb1_groups[] = { 5016077365a9SGeert Uytterhoeven "usb1", 5017077365a9SGeert Uytterhoeven }; 5018077365a9SGeert Uytterhoeven 5019077365a9SGeert Uytterhoeven static const char * const usb2_groups[] = { 5020077365a9SGeert Uytterhoeven "usb2", 5021077365a9SGeert Uytterhoeven }; 5022077365a9SGeert Uytterhoeven 5023077365a9SGeert Uytterhoeven static const char * const usb2_ch3_groups[] = { 5024077365a9SGeert Uytterhoeven "usb2_ch3", 5025077365a9SGeert Uytterhoeven }; 5026077365a9SGeert Uytterhoeven 5027077365a9SGeert Uytterhoeven static const char * const usb30_groups[] = { 5028077365a9SGeert Uytterhoeven "usb30", 5029077365a9SGeert Uytterhoeven }; 5030077365a9SGeert Uytterhoeven 5031077365a9SGeert Uytterhoeven static const char * const vin4_groups[] = { 5032077365a9SGeert Uytterhoeven "vin4_data8_a", 5033077365a9SGeert Uytterhoeven "vin4_data10_a", 5034077365a9SGeert Uytterhoeven "vin4_data12_a", 5035077365a9SGeert Uytterhoeven "vin4_data16_a", 5036077365a9SGeert Uytterhoeven "vin4_data18_a", 5037077365a9SGeert Uytterhoeven "vin4_data20_a", 5038077365a9SGeert Uytterhoeven "vin4_data24_a", 5039077365a9SGeert Uytterhoeven "vin4_data8_b", 5040077365a9SGeert Uytterhoeven "vin4_data10_b", 5041077365a9SGeert Uytterhoeven "vin4_data12_b", 5042077365a9SGeert Uytterhoeven "vin4_data16_b", 5043077365a9SGeert Uytterhoeven "vin4_data18_b", 5044077365a9SGeert Uytterhoeven "vin4_data20_b", 5045077365a9SGeert Uytterhoeven "vin4_data24_b", 50465f79bbb2SNiklas Söderlund "vin4_g8", 5047077365a9SGeert Uytterhoeven "vin4_sync", 5048077365a9SGeert Uytterhoeven "vin4_field", 5049077365a9SGeert Uytterhoeven "vin4_clkenb", 5050077365a9SGeert Uytterhoeven "vin4_clk", 5051077365a9SGeert Uytterhoeven }; 5052077365a9SGeert Uytterhoeven 5053077365a9SGeert Uytterhoeven static const char * const vin5_groups[] = { 5054077365a9SGeert Uytterhoeven "vin5_data8", 5055077365a9SGeert Uytterhoeven "vin5_data10", 5056077365a9SGeert Uytterhoeven "vin5_data12", 5057077365a9SGeert Uytterhoeven "vin5_data16", 50585f79bbb2SNiklas Söderlund "vin5_high8", 5059077365a9SGeert Uytterhoeven "vin5_sync", 5060077365a9SGeert Uytterhoeven "vin5_field", 5061077365a9SGeert Uytterhoeven "vin5_clkenb", 5062077365a9SGeert Uytterhoeven "vin5_clk", 5063077365a9SGeert Uytterhoeven }; 5064077365a9SGeert Uytterhoeven 5065077365a9SGeert Uytterhoeven static const struct { 5066590567bfSLad Prabhakar struct sh_pfc_function common[55]; 5067b8029394SBiju Das #ifdef CONFIG_PINCTRL_PFC_R8A77951 5068ce34fb3cSAndrey Gusakov struct sh_pfc_function automotive[5]; 5069b8029394SBiju Das #endif 5070077365a9SGeert Uytterhoeven } pinmux_functions = { 5071077365a9SGeert Uytterhoeven .common = { 5072077365a9SGeert Uytterhoeven SH_PFC_FUNCTION(audio_clk), 5073077365a9SGeert Uytterhoeven SH_PFC_FUNCTION(avb), 5074077365a9SGeert Uytterhoeven SH_PFC_FUNCTION(can0), 5075077365a9SGeert Uytterhoeven SH_PFC_FUNCTION(can1), 5076077365a9SGeert Uytterhoeven SH_PFC_FUNCTION(can_clk), 5077077365a9SGeert Uytterhoeven SH_PFC_FUNCTION(canfd0), 5078077365a9SGeert Uytterhoeven SH_PFC_FUNCTION(canfd1), 5079077365a9SGeert Uytterhoeven SH_PFC_FUNCTION(du), 5080077365a9SGeert Uytterhoeven SH_PFC_FUNCTION(hscif0), 5081077365a9SGeert Uytterhoeven SH_PFC_FUNCTION(hscif1), 5082077365a9SGeert Uytterhoeven SH_PFC_FUNCTION(hscif2), 5083077365a9SGeert Uytterhoeven SH_PFC_FUNCTION(hscif3), 5084077365a9SGeert Uytterhoeven SH_PFC_FUNCTION(hscif4), 5085077365a9SGeert Uytterhoeven SH_PFC_FUNCTION(i2c0), 5086077365a9SGeert Uytterhoeven SH_PFC_FUNCTION(i2c1), 5087077365a9SGeert Uytterhoeven SH_PFC_FUNCTION(i2c2), 5088077365a9SGeert Uytterhoeven SH_PFC_FUNCTION(i2c3), 5089077365a9SGeert Uytterhoeven SH_PFC_FUNCTION(i2c5), 5090077365a9SGeert Uytterhoeven SH_PFC_FUNCTION(i2c6), 5091077365a9SGeert Uytterhoeven SH_PFC_FUNCTION(intc_ex), 5092077365a9SGeert Uytterhoeven SH_PFC_FUNCTION(msiof0), 5093077365a9SGeert Uytterhoeven SH_PFC_FUNCTION(msiof1), 5094077365a9SGeert Uytterhoeven SH_PFC_FUNCTION(msiof2), 5095077365a9SGeert Uytterhoeven SH_PFC_FUNCTION(msiof3), 5096077365a9SGeert Uytterhoeven SH_PFC_FUNCTION(pwm0), 5097077365a9SGeert Uytterhoeven SH_PFC_FUNCTION(pwm1), 5098077365a9SGeert Uytterhoeven SH_PFC_FUNCTION(pwm2), 5099077365a9SGeert Uytterhoeven SH_PFC_FUNCTION(pwm3), 5100077365a9SGeert Uytterhoeven SH_PFC_FUNCTION(pwm4), 5101077365a9SGeert Uytterhoeven SH_PFC_FUNCTION(pwm5), 5102077365a9SGeert Uytterhoeven SH_PFC_FUNCTION(pwm6), 5103590567bfSLad Prabhakar SH_PFC_FUNCTION(qspi0), 5104590567bfSLad Prabhakar SH_PFC_FUNCTION(qspi1), 5105077365a9SGeert Uytterhoeven SH_PFC_FUNCTION(sata0), 5106077365a9SGeert Uytterhoeven SH_PFC_FUNCTION(scif0), 5107077365a9SGeert Uytterhoeven SH_PFC_FUNCTION(scif1), 5108077365a9SGeert Uytterhoeven SH_PFC_FUNCTION(scif2), 5109077365a9SGeert Uytterhoeven SH_PFC_FUNCTION(scif3), 5110077365a9SGeert Uytterhoeven SH_PFC_FUNCTION(scif4), 5111077365a9SGeert Uytterhoeven SH_PFC_FUNCTION(scif5), 5112077365a9SGeert Uytterhoeven SH_PFC_FUNCTION(scif_clk), 5113077365a9SGeert Uytterhoeven SH_PFC_FUNCTION(sdhi0), 5114077365a9SGeert Uytterhoeven SH_PFC_FUNCTION(sdhi1), 5115077365a9SGeert Uytterhoeven SH_PFC_FUNCTION(sdhi2), 5116077365a9SGeert Uytterhoeven SH_PFC_FUNCTION(sdhi3), 5117077365a9SGeert Uytterhoeven SH_PFC_FUNCTION(ssi), 5118077365a9SGeert Uytterhoeven SH_PFC_FUNCTION(tmu), 5119077365a9SGeert Uytterhoeven SH_PFC_FUNCTION(tpu), 5120077365a9SGeert Uytterhoeven SH_PFC_FUNCTION(usb0), 5121077365a9SGeert Uytterhoeven SH_PFC_FUNCTION(usb1), 5122077365a9SGeert Uytterhoeven SH_PFC_FUNCTION(usb2), 5123077365a9SGeert Uytterhoeven SH_PFC_FUNCTION(usb2_ch3), 5124077365a9SGeert Uytterhoeven SH_PFC_FUNCTION(usb30), 5125077365a9SGeert Uytterhoeven SH_PFC_FUNCTION(vin4), 5126077365a9SGeert Uytterhoeven SH_PFC_FUNCTION(vin5), 5127077365a9SGeert Uytterhoeven }, 5128b8029394SBiju Das #ifdef CONFIG_PINCTRL_PFC_R8A77951 5129077365a9SGeert Uytterhoeven .automotive = { 5130077365a9SGeert Uytterhoeven SH_PFC_FUNCTION(drif0), 5131077365a9SGeert Uytterhoeven SH_PFC_FUNCTION(drif1), 5132077365a9SGeert Uytterhoeven SH_PFC_FUNCTION(drif2), 5133077365a9SGeert Uytterhoeven SH_PFC_FUNCTION(drif3), 5134ce34fb3cSAndrey Gusakov SH_PFC_FUNCTION(mlb_3pin), 5135077365a9SGeert Uytterhoeven } 5136b8029394SBiju Das #endif /* CONFIG_PINCTRL_PFC_R8A77951 */ 5137077365a9SGeert Uytterhoeven }; 5138077365a9SGeert Uytterhoeven 5139077365a9SGeert Uytterhoeven static const struct pinmux_cfg_reg pinmux_config_regs[] = { 5140077365a9SGeert Uytterhoeven #define F_(x, y) FN_##y 5141077365a9SGeert Uytterhoeven #define FM(x) FN_##x 5142d5ea70eaSGeert Uytterhoeven { PINMUX_CFG_REG_VAR("GPSR0", 0xe6060100, 32, 5143d5ea70eaSGeert Uytterhoeven GROUP(-16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 5144d5ea70eaSGeert Uytterhoeven 1, 1, 1, 1, 1), 5145d5ea70eaSGeert Uytterhoeven GROUP( 5146d5ea70eaSGeert Uytterhoeven /* GP0_31_16 RESERVED */ 5147077365a9SGeert Uytterhoeven GP_0_15_FN, GPSR0_15, 5148077365a9SGeert Uytterhoeven GP_0_14_FN, GPSR0_14, 5149077365a9SGeert Uytterhoeven GP_0_13_FN, GPSR0_13, 5150077365a9SGeert Uytterhoeven GP_0_12_FN, GPSR0_12, 5151077365a9SGeert Uytterhoeven GP_0_11_FN, GPSR0_11, 5152077365a9SGeert Uytterhoeven GP_0_10_FN, GPSR0_10, 5153077365a9SGeert Uytterhoeven GP_0_9_FN, GPSR0_9, 5154077365a9SGeert Uytterhoeven GP_0_8_FN, GPSR0_8, 5155077365a9SGeert Uytterhoeven GP_0_7_FN, GPSR0_7, 5156077365a9SGeert Uytterhoeven GP_0_6_FN, GPSR0_6, 5157077365a9SGeert Uytterhoeven GP_0_5_FN, GPSR0_5, 5158077365a9SGeert Uytterhoeven GP_0_4_FN, GPSR0_4, 5159077365a9SGeert Uytterhoeven GP_0_3_FN, GPSR0_3, 5160077365a9SGeert Uytterhoeven GP_0_2_FN, GPSR0_2, 5161077365a9SGeert Uytterhoeven GP_0_1_FN, GPSR0_1, 5162077365a9SGeert Uytterhoeven GP_0_0_FN, GPSR0_0, )) 5163077365a9SGeert Uytterhoeven }, 5164077365a9SGeert Uytterhoeven { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP( 5165077365a9SGeert Uytterhoeven 0, 0, 5166077365a9SGeert Uytterhoeven 0, 0, 5167077365a9SGeert Uytterhoeven 0, 0, 5168077365a9SGeert Uytterhoeven GP_1_28_FN, GPSR1_28, 5169077365a9SGeert Uytterhoeven GP_1_27_FN, GPSR1_27, 5170077365a9SGeert Uytterhoeven GP_1_26_FN, GPSR1_26, 5171077365a9SGeert Uytterhoeven GP_1_25_FN, GPSR1_25, 5172077365a9SGeert Uytterhoeven GP_1_24_FN, GPSR1_24, 5173077365a9SGeert Uytterhoeven GP_1_23_FN, GPSR1_23, 5174077365a9SGeert Uytterhoeven GP_1_22_FN, GPSR1_22, 5175077365a9SGeert Uytterhoeven GP_1_21_FN, GPSR1_21, 5176077365a9SGeert Uytterhoeven GP_1_20_FN, GPSR1_20, 5177077365a9SGeert Uytterhoeven GP_1_19_FN, GPSR1_19, 5178077365a9SGeert Uytterhoeven GP_1_18_FN, GPSR1_18, 5179077365a9SGeert Uytterhoeven GP_1_17_FN, GPSR1_17, 5180077365a9SGeert Uytterhoeven GP_1_16_FN, GPSR1_16, 5181077365a9SGeert Uytterhoeven GP_1_15_FN, GPSR1_15, 5182077365a9SGeert Uytterhoeven GP_1_14_FN, GPSR1_14, 5183077365a9SGeert Uytterhoeven GP_1_13_FN, GPSR1_13, 5184077365a9SGeert Uytterhoeven GP_1_12_FN, GPSR1_12, 5185077365a9SGeert Uytterhoeven GP_1_11_FN, GPSR1_11, 5186077365a9SGeert Uytterhoeven GP_1_10_FN, GPSR1_10, 5187077365a9SGeert Uytterhoeven GP_1_9_FN, GPSR1_9, 5188077365a9SGeert Uytterhoeven GP_1_8_FN, GPSR1_8, 5189077365a9SGeert Uytterhoeven GP_1_7_FN, GPSR1_7, 5190077365a9SGeert Uytterhoeven GP_1_6_FN, GPSR1_6, 5191077365a9SGeert Uytterhoeven GP_1_5_FN, GPSR1_5, 5192077365a9SGeert Uytterhoeven GP_1_4_FN, GPSR1_4, 5193077365a9SGeert Uytterhoeven GP_1_3_FN, GPSR1_3, 5194077365a9SGeert Uytterhoeven GP_1_2_FN, GPSR1_2, 5195077365a9SGeert Uytterhoeven GP_1_1_FN, GPSR1_1, 5196077365a9SGeert Uytterhoeven GP_1_0_FN, GPSR1_0, )) 5197077365a9SGeert Uytterhoeven }, 5198d5ea70eaSGeert Uytterhoeven { PINMUX_CFG_REG_VAR("GPSR2", 0xe6060108, 32, 5199d5ea70eaSGeert Uytterhoeven GROUP(-17, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 5200d5ea70eaSGeert Uytterhoeven 1, 1, 1, 1), 5201d5ea70eaSGeert Uytterhoeven GROUP( 5202d5ea70eaSGeert Uytterhoeven /* GP2_31_15 RESERVED */ 5203077365a9SGeert Uytterhoeven GP_2_14_FN, GPSR2_14, 5204077365a9SGeert Uytterhoeven GP_2_13_FN, GPSR2_13, 5205077365a9SGeert Uytterhoeven GP_2_12_FN, GPSR2_12, 5206077365a9SGeert Uytterhoeven GP_2_11_FN, GPSR2_11, 5207077365a9SGeert Uytterhoeven GP_2_10_FN, GPSR2_10, 5208077365a9SGeert Uytterhoeven GP_2_9_FN, GPSR2_9, 5209077365a9SGeert Uytterhoeven GP_2_8_FN, GPSR2_8, 5210077365a9SGeert Uytterhoeven GP_2_7_FN, GPSR2_7, 5211077365a9SGeert Uytterhoeven GP_2_6_FN, GPSR2_6, 5212077365a9SGeert Uytterhoeven GP_2_5_FN, GPSR2_5, 5213077365a9SGeert Uytterhoeven GP_2_4_FN, GPSR2_4, 5214077365a9SGeert Uytterhoeven GP_2_3_FN, GPSR2_3, 5215077365a9SGeert Uytterhoeven GP_2_2_FN, GPSR2_2, 5216077365a9SGeert Uytterhoeven GP_2_1_FN, GPSR2_1, 5217077365a9SGeert Uytterhoeven GP_2_0_FN, GPSR2_0, )) 5218077365a9SGeert Uytterhoeven }, 5219d5ea70eaSGeert Uytterhoeven { PINMUX_CFG_REG_VAR("GPSR3", 0xe606010c, 32, 5220d5ea70eaSGeert Uytterhoeven GROUP(-16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 5221d5ea70eaSGeert Uytterhoeven 1, 1, 1, 1, 1), 5222d5ea70eaSGeert Uytterhoeven GROUP( 5223d5ea70eaSGeert Uytterhoeven /* GP3_31_16 RESERVED */ 5224077365a9SGeert Uytterhoeven GP_3_15_FN, GPSR3_15, 5225077365a9SGeert Uytterhoeven GP_3_14_FN, GPSR3_14, 5226077365a9SGeert Uytterhoeven GP_3_13_FN, GPSR3_13, 5227077365a9SGeert Uytterhoeven GP_3_12_FN, GPSR3_12, 5228077365a9SGeert Uytterhoeven GP_3_11_FN, GPSR3_11, 5229077365a9SGeert Uytterhoeven GP_3_10_FN, GPSR3_10, 5230077365a9SGeert Uytterhoeven GP_3_9_FN, GPSR3_9, 5231077365a9SGeert Uytterhoeven GP_3_8_FN, GPSR3_8, 5232077365a9SGeert Uytterhoeven GP_3_7_FN, GPSR3_7, 5233077365a9SGeert Uytterhoeven GP_3_6_FN, GPSR3_6, 5234077365a9SGeert Uytterhoeven GP_3_5_FN, GPSR3_5, 5235077365a9SGeert Uytterhoeven GP_3_4_FN, GPSR3_4, 5236077365a9SGeert Uytterhoeven GP_3_3_FN, GPSR3_3, 5237077365a9SGeert Uytterhoeven GP_3_2_FN, GPSR3_2, 5238077365a9SGeert Uytterhoeven GP_3_1_FN, GPSR3_1, 5239077365a9SGeert Uytterhoeven GP_3_0_FN, GPSR3_0, )) 5240077365a9SGeert Uytterhoeven }, 5241d5ea70eaSGeert Uytterhoeven { PINMUX_CFG_REG_VAR("GPSR4", 0xe6060110, 32, 5242d5ea70eaSGeert Uytterhoeven GROUP(-14, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 5243d5ea70eaSGeert Uytterhoeven 1, 1, 1, 1, 1, 1, 1), 5244d5ea70eaSGeert Uytterhoeven GROUP( 5245d5ea70eaSGeert Uytterhoeven /* GP4_31_18 RESERVED */ 5246077365a9SGeert Uytterhoeven GP_4_17_FN, GPSR4_17, 5247077365a9SGeert Uytterhoeven GP_4_16_FN, GPSR4_16, 5248077365a9SGeert Uytterhoeven GP_4_15_FN, GPSR4_15, 5249077365a9SGeert Uytterhoeven GP_4_14_FN, GPSR4_14, 5250077365a9SGeert Uytterhoeven GP_4_13_FN, GPSR4_13, 5251077365a9SGeert Uytterhoeven GP_4_12_FN, GPSR4_12, 5252077365a9SGeert Uytterhoeven GP_4_11_FN, GPSR4_11, 5253077365a9SGeert Uytterhoeven GP_4_10_FN, GPSR4_10, 5254077365a9SGeert Uytterhoeven GP_4_9_FN, GPSR4_9, 5255077365a9SGeert Uytterhoeven GP_4_8_FN, GPSR4_8, 5256077365a9SGeert Uytterhoeven GP_4_7_FN, GPSR4_7, 5257077365a9SGeert Uytterhoeven GP_4_6_FN, GPSR4_6, 5258077365a9SGeert Uytterhoeven GP_4_5_FN, GPSR4_5, 5259077365a9SGeert Uytterhoeven GP_4_4_FN, GPSR4_4, 5260077365a9SGeert Uytterhoeven GP_4_3_FN, GPSR4_3, 5261077365a9SGeert Uytterhoeven GP_4_2_FN, GPSR4_2, 5262077365a9SGeert Uytterhoeven GP_4_1_FN, GPSR4_1, 5263077365a9SGeert Uytterhoeven GP_4_0_FN, GPSR4_0, )) 5264077365a9SGeert Uytterhoeven }, 5265077365a9SGeert Uytterhoeven { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP( 5266077365a9SGeert Uytterhoeven 0, 0, 5267077365a9SGeert Uytterhoeven 0, 0, 5268077365a9SGeert Uytterhoeven 0, 0, 5269077365a9SGeert Uytterhoeven 0, 0, 5270077365a9SGeert Uytterhoeven 0, 0, 5271077365a9SGeert Uytterhoeven 0, 0, 5272077365a9SGeert Uytterhoeven GP_5_25_FN, GPSR5_25, 5273077365a9SGeert Uytterhoeven GP_5_24_FN, GPSR5_24, 5274077365a9SGeert Uytterhoeven GP_5_23_FN, GPSR5_23, 5275077365a9SGeert Uytterhoeven GP_5_22_FN, GPSR5_22, 5276077365a9SGeert Uytterhoeven GP_5_21_FN, GPSR5_21, 5277077365a9SGeert Uytterhoeven GP_5_20_FN, GPSR5_20, 5278077365a9SGeert Uytterhoeven GP_5_19_FN, GPSR5_19, 5279077365a9SGeert Uytterhoeven GP_5_18_FN, GPSR5_18, 5280077365a9SGeert Uytterhoeven GP_5_17_FN, GPSR5_17, 5281077365a9SGeert Uytterhoeven GP_5_16_FN, GPSR5_16, 5282077365a9SGeert Uytterhoeven GP_5_15_FN, GPSR5_15, 5283077365a9SGeert Uytterhoeven GP_5_14_FN, GPSR5_14, 5284077365a9SGeert Uytterhoeven GP_5_13_FN, GPSR5_13, 5285077365a9SGeert Uytterhoeven GP_5_12_FN, GPSR5_12, 5286077365a9SGeert Uytterhoeven GP_5_11_FN, GPSR5_11, 5287077365a9SGeert Uytterhoeven GP_5_10_FN, GPSR5_10, 5288077365a9SGeert Uytterhoeven GP_5_9_FN, GPSR5_9, 5289077365a9SGeert Uytterhoeven GP_5_8_FN, GPSR5_8, 5290077365a9SGeert Uytterhoeven GP_5_7_FN, GPSR5_7, 5291077365a9SGeert Uytterhoeven GP_5_6_FN, GPSR5_6, 5292077365a9SGeert Uytterhoeven GP_5_5_FN, GPSR5_5, 5293077365a9SGeert Uytterhoeven GP_5_4_FN, GPSR5_4, 5294077365a9SGeert Uytterhoeven GP_5_3_FN, GPSR5_3, 5295077365a9SGeert Uytterhoeven GP_5_2_FN, GPSR5_2, 5296077365a9SGeert Uytterhoeven GP_5_1_FN, GPSR5_1, 5297077365a9SGeert Uytterhoeven GP_5_0_FN, GPSR5_0, )) 5298077365a9SGeert Uytterhoeven }, 5299077365a9SGeert Uytterhoeven { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP( 5300077365a9SGeert Uytterhoeven GP_6_31_FN, GPSR6_31, 5301077365a9SGeert Uytterhoeven GP_6_30_FN, GPSR6_30, 5302077365a9SGeert Uytterhoeven GP_6_29_FN, GPSR6_29, 5303077365a9SGeert Uytterhoeven GP_6_28_FN, GPSR6_28, 5304077365a9SGeert Uytterhoeven GP_6_27_FN, GPSR6_27, 5305077365a9SGeert Uytterhoeven GP_6_26_FN, GPSR6_26, 5306077365a9SGeert Uytterhoeven GP_6_25_FN, GPSR6_25, 5307077365a9SGeert Uytterhoeven GP_6_24_FN, GPSR6_24, 5308077365a9SGeert Uytterhoeven GP_6_23_FN, GPSR6_23, 5309077365a9SGeert Uytterhoeven GP_6_22_FN, GPSR6_22, 5310077365a9SGeert Uytterhoeven GP_6_21_FN, GPSR6_21, 5311077365a9SGeert Uytterhoeven GP_6_20_FN, GPSR6_20, 5312077365a9SGeert Uytterhoeven GP_6_19_FN, GPSR6_19, 5313077365a9SGeert Uytterhoeven GP_6_18_FN, GPSR6_18, 5314077365a9SGeert Uytterhoeven GP_6_17_FN, GPSR6_17, 5315077365a9SGeert Uytterhoeven GP_6_16_FN, GPSR6_16, 5316077365a9SGeert Uytterhoeven GP_6_15_FN, GPSR6_15, 5317077365a9SGeert Uytterhoeven GP_6_14_FN, GPSR6_14, 5318077365a9SGeert Uytterhoeven GP_6_13_FN, GPSR6_13, 5319077365a9SGeert Uytterhoeven GP_6_12_FN, GPSR6_12, 5320077365a9SGeert Uytterhoeven GP_6_11_FN, GPSR6_11, 5321077365a9SGeert Uytterhoeven GP_6_10_FN, GPSR6_10, 5322077365a9SGeert Uytterhoeven GP_6_9_FN, GPSR6_9, 5323077365a9SGeert Uytterhoeven GP_6_8_FN, GPSR6_8, 5324077365a9SGeert Uytterhoeven GP_6_7_FN, GPSR6_7, 5325077365a9SGeert Uytterhoeven GP_6_6_FN, GPSR6_6, 5326077365a9SGeert Uytterhoeven GP_6_5_FN, GPSR6_5, 5327077365a9SGeert Uytterhoeven GP_6_4_FN, GPSR6_4, 5328077365a9SGeert Uytterhoeven GP_6_3_FN, GPSR6_3, 5329077365a9SGeert Uytterhoeven GP_6_2_FN, GPSR6_2, 5330077365a9SGeert Uytterhoeven GP_6_1_FN, GPSR6_1, 5331077365a9SGeert Uytterhoeven GP_6_0_FN, GPSR6_0, )) 5332077365a9SGeert Uytterhoeven }, 5333d5ea70eaSGeert Uytterhoeven { PINMUX_CFG_REG_VAR("GPSR7", 0xe606011c, 32, 5334d5ea70eaSGeert Uytterhoeven GROUP(-28, 1, 1, 1, 1), 5335d5ea70eaSGeert Uytterhoeven GROUP( 5336d5ea70eaSGeert Uytterhoeven /* GP7_31_4 RESERVED */ 5337077365a9SGeert Uytterhoeven GP_7_3_FN, GPSR7_3, 5338077365a9SGeert Uytterhoeven GP_7_2_FN, GPSR7_2, 5339077365a9SGeert Uytterhoeven GP_7_1_FN, GPSR7_1, 5340077365a9SGeert Uytterhoeven GP_7_0_FN, GPSR7_0, )) 5341077365a9SGeert Uytterhoeven }, 5342077365a9SGeert Uytterhoeven #undef F_ 5343077365a9SGeert Uytterhoeven #undef FM 5344077365a9SGeert Uytterhoeven 5345077365a9SGeert Uytterhoeven #define F_(x, y) x, 5346077365a9SGeert Uytterhoeven #define FM(x) FN_##x, 5347077365a9SGeert Uytterhoeven { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP( 5348077365a9SGeert Uytterhoeven IP0_31_28 5349077365a9SGeert Uytterhoeven IP0_27_24 5350077365a9SGeert Uytterhoeven IP0_23_20 5351077365a9SGeert Uytterhoeven IP0_19_16 5352077365a9SGeert Uytterhoeven IP0_15_12 5353077365a9SGeert Uytterhoeven IP0_11_8 5354077365a9SGeert Uytterhoeven IP0_7_4 5355077365a9SGeert Uytterhoeven IP0_3_0 )) 5356077365a9SGeert Uytterhoeven }, 5357077365a9SGeert Uytterhoeven { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP( 5358077365a9SGeert Uytterhoeven IP1_31_28 5359077365a9SGeert Uytterhoeven IP1_27_24 5360077365a9SGeert Uytterhoeven IP1_23_20 5361077365a9SGeert Uytterhoeven IP1_19_16 5362077365a9SGeert Uytterhoeven IP1_15_12 5363077365a9SGeert Uytterhoeven IP1_11_8 5364077365a9SGeert Uytterhoeven IP1_7_4 5365077365a9SGeert Uytterhoeven IP1_3_0 )) 5366077365a9SGeert Uytterhoeven }, 5367077365a9SGeert Uytterhoeven { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP( 5368077365a9SGeert Uytterhoeven IP2_31_28 5369077365a9SGeert Uytterhoeven IP2_27_24 5370077365a9SGeert Uytterhoeven IP2_23_20 5371077365a9SGeert Uytterhoeven IP2_19_16 5372077365a9SGeert Uytterhoeven IP2_15_12 5373077365a9SGeert Uytterhoeven IP2_11_8 5374077365a9SGeert Uytterhoeven IP2_7_4 5375077365a9SGeert Uytterhoeven IP2_3_0 )) 5376077365a9SGeert Uytterhoeven }, 5377077365a9SGeert Uytterhoeven { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP( 5378077365a9SGeert Uytterhoeven IP3_31_28 5379077365a9SGeert Uytterhoeven IP3_27_24 5380077365a9SGeert Uytterhoeven IP3_23_20 5381077365a9SGeert Uytterhoeven IP3_19_16 5382077365a9SGeert Uytterhoeven IP3_15_12 5383077365a9SGeert Uytterhoeven IP3_11_8 5384077365a9SGeert Uytterhoeven IP3_7_4 5385077365a9SGeert Uytterhoeven IP3_3_0 )) 5386077365a9SGeert Uytterhoeven }, 5387077365a9SGeert Uytterhoeven { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP( 5388077365a9SGeert Uytterhoeven IP4_31_28 5389077365a9SGeert Uytterhoeven IP4_27_24 5390077365a9SGeert Uytterhoeven IP4_23_20 5391077365a9SGeert Uytterhoeven IP4_19_16 5392077365a9SGeert Uytterhoeven IP4_15_12 5393077365a9SGeert Uytterhoeven IP4_11_8 5394077365a9SGeert Uytterhoeven IP4_7_4 5395077365a9SGeert Uytterhoeven IP4_3_0 )) 5396077365a9SGeert Uytterhoeven }, 5397077365a9SGeert Uytterhoeven { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP( 5398077365a9SGeert Uytterhoeven IP5_31_28 5399077365a9SGeert Uytterhoeven IP5_27_24 5400077365a9SGeert Uytterhoeven IP5_23_20 5401077365a9SGeert Uytterhoeven IP5_19_16 5402077365a9SGeert Uytterhoeven IP5_15_12 5403077365a9SGeert Uytterhoeven IP5_11_8 5404077365a9SGeert Uytterhoeven IP5_7_4 5405077365a9SGeert Uytterhoeven IP5_3_0 )) 5406077365a9SGeert Uytterhoeven }, 5407077365a9SGeert Uytterhoeven { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP( 5408077365a9SGeert Uytterhoeven IP6_31_28 5409077365a9SGeert Uytterhoeven IP6_27_24 5410077365a9SGeert Uytterhoeven IP6_23_20 5411077365a9SGeert Uytterhoeven IP6_19_16 5412077365a9SGeert Uytterhoeven IP6_15_12 5413077365a9SGeert Uytterhoeven IP6_11_8 5414077365a9SGeert Uytterhoeven IP6_7_4 5415077365a9SGeert Uytterhoeven IP6_3_0 )) 5416077365a9SGeert Uytterhoeven }, 5417d5ea70eaSGeert Uytterhoeven { PINMUX_CFG_REG_VAR("IPSR7", 0xe606021c, 32, 5418d5ea70eaSGeert Uytterhoeven GROUP(4, 4, 4, 4, -4, 4, 4, 4), 5419d5ea70eaSGeert Uytterhoeven GROUP( 5420077365a9SGeert Uytterhoeven IP7_31_28 5421077365a9SGeert Uytterhoeven IP7_27_24 5422077365a9SGeert Uytterhoeven IP7_23_20 5423077365a9SGeert Uytterhoeven IP7_19_16 5424d5ea70eaSGeert Uytterhoeven /* IP7_15_12 RESERVED */ 5425077365a9SGeert Uytterhoeven IP7_11_8 5426077365a9SGeert Uytterhoeven IP7_7_4 5427077365a9SGeert Uytterhoeven IP7_3_0 )) 5428077365a9SGeert Uytterhoeven }, 5429077365a9SGeert Uytterhoeven { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP( 5430077365a9SGeert Uytterhoeven IP8_31_28 5431077365a9SGeert Uytterhoeven IP8_27_24 5432077365a9SGeert Uytterhoeven IP8_23_20 5433077365a9SGeert Uytterhoeven IP8_19_16 5434077365a9SGeert Uytterhoeven IP8_15_12 5435077365a9SGeert Uytterhoeven IP8_11_8 5436077365a9SGeert Uytterhoeven IP8_7_4 5437077365a9SGeert Uytterhoeven IP8_3_0 )) 5438077365a9SGeert Uytterhoeven }, 5439077365a9SGeert Uytterhoeven { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP( 5440077365a9SGeert Uytterhoeven IP9_31_28 5441077365a9SGeert Uytterhoeven IP9_27_24 5442077365a9SGeert Uytterhoeven IP9_23_20 5443077365a9SGeert Uytterhoeven IP9_19_16 5444077365a9SGeert Uytterhoeven IP9_15_12 5445077365a9SGeert Uytterhoeven IP9_11_8 5446077365a9SGeert Uytterhoeven IP9_7_4 5447077365a9SGeert Uytterhoeven IP9_3_0 )) 5448077365a9SGeert Uytterhoeven }, 5449077365a9SGeert Uytterhoeven { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP( 5450077365a9SGeert Uytterhoeven IP10_31_28 5451077365a9SGeert Uytterhoeven IP10_27_24 5452077365a9SGeert Uytterhoeven IP10_23_20 5453077365a9SGeert Uytterhoeven IP10_19_16 5454077365a9SGeert Uytterhoeven IP10_15_12 5455077365a9SGeert Uytterhoeven IP10_11_8 5456077365a9SGeert Uytterhoeven IP10_7_4 5457077365a9SGeert Uytterhoeven IP10_3_0 )) 5458077365a9SGeert Uytterhoeven }, 5459077365a9SGeert Uytterhoeven { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP( 5460077365a9SGeert Uytterhoeven IP11_31_28 5461077365a9SGeert Uytterhoeven IP11_27_24 5462077365a9SGeert Uytterhoeven IP11_23_20 5463077365a9SGeert Uytterhoeven IP11_19_16 5464077365a9SGeert Uytterhoeven IP11_15_12 5465077365a9SGeert Uytterhoeven IP11_11_8 5466077365a9SGeert Uytterhoeven IP11_7_4 5467077365a9SGeert Uytterhoeven IP11_3_0 )) 5468077365a9SGeert Uytterhoeven }, 5469077365a9SGeert Uytterhoeven { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP( 5470077365a9SGeert Uytterhoeven IP12_31_28 5471077365a9SGeert Uytterhoeven IP12_27_24 5472077365a9SGeert Uytterhoeven IP12_23_20 5473077365a9SGeert Uytterhoeven IP12_19_16 5474077365a9SGeert Uytterhoeven IP12_15_12 5475077365a9SGeert Uytterhoeven IP12_11_8 5476077365a9SGeert Uytterhoeven IP12_7_4 5477077365a9SGeert Uytterhoeven IP12_3_0 )) 5478077365a9SGeert Uytterhoeven }, 5479077365a9SGeert Uytterhoeven { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP( 5480077365a9SGeert Uytterhoeven IP13_31_28 5481077365a9SGeert Uytterhoeven IP13_27_24 5482077365a9SGeert Uytterhoeven IP13_23_20 5483077365a9SGeert Uytterhoeven IP13_19_16 5484077365a9SGeert Uytterhoeven IP13_15_12 5485077365a9SGeert Uytterhoeven IP13_11_8 5486077365a9SGeert Uytterhoeven IP13_7_4 5487077365a9SGeert Uytterhoeven IP13_3_0 )) 5488077365a9SGeert Uytterhoeven }, 5489077365a9SGeert Uytterhoeven { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP( 5490077365a9SGeert Uytterhoeven IP14_31_28 5491077365a9SGeert Uytterhoeven IP14_27_24 5492077365a9SGeert Uytterhoeven IP14_23_20 5493077365a9SGeert Uytterhoeven IP14_19_16 5494077365a9SGeert Uytterhoeven IP14_15_12 5495077365a9SGeert Uytterhoeven IP14_11_8 5496077365a9SGeert Uytterhoeven IP14_7_4 5497077365a9SGeert Uytterhoeven IP14_3_0 )) 5498077365a9SGeert Uytterhoeven }, 5499077365a9SGeert Uytterhoeven { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP( 5500077365a9SGeert Uytterhoeven IP15_31_28 5501077365a9SGeert Uytterhoeven IP15_27_24 5502077365a9SGeert Uytterhoeven IP15_23_20 5503077365a9SGeert Uytterhoeven IP15_19_16 5504077365a9SGeert Uytterhoeven IP15_15_12 5505077365a9SGeert Uytterhoeven IP15_11_8 5506077365a9SGeert Uytterhoeven IP15_7_4 5507077365a9SGeert Uytterhoeven IP15_3_0 )) 5508077365a9SGeert Uytterhoeven }, 5509077365a9SGeert Uytterhoeven { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4, GROUP( 5510077365a9SGeert Uytterhoeven IP16_31_28 5511077365a9SGeert Uytterhoeven IP16_27_24 5512077365a9SGeert Uytterhoeven IP16_23_20 5513077365a9SGeert Uytterhoeven IP16_19_16 5514077365a9SGeert Uytterhoeven IP16_15_12 5515077365a9SGeert Uytterhoeven IP16_11_8 5516077365a9SGeert Uytterhoeven IP16_7_4 5517077365a9SGeert Uytterhoeven IP16_3_0 )) 5518077365a9SGeert Uytterhoeven }, 5519077365a9SGeert Uytterhoeven { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4, GROUP( 5520077365a9SGeert Uytterhoeven IP17_31_28 5521077365a9SGeert Uytterhoeven IP17_27_24 5522077365a9SGeert Uytterhoeven IP17_23_20 5523077365a9SGeert Uytterhoeven IP17_19_16 5524077365a9SGeert Uytterhoeven IP17_15_12 5525077365a9SGeert Uytterhoeven IP17_11_8 5526077365a9SGeert Uytterhoeven IP17_7_4 5527077365a9SGeert Uytterhoeven IP17_3_0 )) 5528077365a9SGeert Uytterhoeven }, 5529d5ea70eaSGeert Uytterhoeven { PINMUX_CFG_REG_VAR("IPSR18", 0xe6060248, 32, 5530d5ea70eaSGeert Uytterhoeven GROUP(-24, 4, 4), 5531d5ea70eaSGeert Uytterhoeven GROUP( 5532d5ea70eaSGeert Uytterhoeven /* IP18_31_8 RESERVED */ 5533077365a9SGeert Uytterhoeven IP18_7_4 5534077365a9SGeert Uytterhoeven IP18_3_0 )) 5535077365a9SGeert Uytterhoeven }, 5536077365a9SGeert Uytterhoeven #undef F_ 5537077365a9SGeert Uytterhoeven #undef FM 5538077365a9SGeert Uytterhoeven 5539077365a9SGeert Uytterhoeven #define F_(x, y) x, 5540077365a9SGeert Uytterhoeven #define FM(x) FN_##x, 5541077365a9SGeert Uytterhoeven { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32, 55425e0857fdSGeert Uytterhoeven GROUP(3, 2, 3, 1, 1, 1, 1, 1, 2, 1, -1, 2, 55435e0857fdSGeert Uytterhoeven 1, 1, 1, 2, 2, 1, 2, -3), 5544077365a9SGeert Uytterhoeven GROUP( 5545077365a9SGeert Uytterhoeven MOD_SEL0_31_30_29 5546077365a9SGeert Uytterhoeven MOD_SEL0_28_27 5547077365a9SGeert Uytterhoeven MOD_SEL0_26_25_24 5548077365a9SGeert Uytterhoeven MOD_SEL0_23 5549077365a9SGeert Uytterhoeven MOD_SEL0_22 5550077365a9SGeert Uytterhoeven MOD_SEL0_21 5551077365a9SGeert Uytterhoeven MOD_SEL0_20 5552077365a9SGeert Uytterhoeven MOD_SEL0_19 5553077365a9SGeert Uytterhoeven MOD_SEL0_18_17 5554077365a9SGeert Uytterhoeven MOD_SEL0_16 55555e0857fdSGeert Uytterhoeven /* RESERVED 15 */ 5556077365a9SGeert Uytterhoeven MOD_SEL0_14_13 5557077365a9SGeert Uytterhoeven MOD_SEL0_12 5558077365a9SGeert Uytterhoeven MOD_SEL0_11 5559077365a9SGeert Uytterhoeven MOD_SEL0_10 5560077365a9SGeert Uytterhoeven MOD_SEL0_9_8 5561077365a9SGeert Uytterhoeven MOD_SEL0_7_6 5562077365a9SGeert Uytterhoeven MOD_SEL0_5 5563077365a9SGeert Uytterhoeven MOD_SEL0_4_3 55645e0857fdSGeert Uytterhoeven /* RESERVED 2, 1, 0 */ )) 5565077365a9SGeert Uytterhoeven }, 5566077365a9SGeert Uytterhoeven { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32, 5567077365a9SGeert Uytterhoeven GROUP(2, 3, 1, 2, 3, 1, 1, 2, 1, 2, 1, 1, 55685e0857fdSGeert Uytterhoeven 1, 1, 1, -2, 1, 1, 1, 1, 1, 1, 1), 5569077365a9SGeert Uytterhoeven GROUP( 5570077365a9SGeert Uytterhoeven MOD_SEL1_31_30 5571077365a9SGeert Uytterhoeven MOD_SEL1_29_28_27 5572077365a9SGeert Uytterhoeven MOD_SEL1_26 5573077365a9SGeert Uytterhoeven MOD_SEL1_25_24 5574077365a9SGeert Uytterhoeven MOD_SEL1_23_22_21 5575077365a9SGeert Uytterhoeven MOD_SEL1_20 5576077365a9SGeert Uytterhoeven MOD_SEL1_19 5577077365a9SGeert Uytterhoeven MOD_SEL1_18_17 5578077365a9SGeert Uytterhoeven MOD_SEL1_16 5579077365a9SGeert Uytterhoeven MOD_SEL1_15_14 5580077365a9SGeert Uytterhoeven MOD_SEL1_13 5581077365a9SGeert Uytterhoeven MOD_SEL1_12 5582077365a9SGeert Uytterhoeven MOD_SEL1_11 5583077365a9SGeert Uytterhoeven MOD_SEL1_10 5584077365a9SGeert Uytterhoeven MOD_SEL1_9 55855e0857fdSGeert Uytterhoeven /* RESERVED 8, 7 */ 5586077365a9SGeert Uytterhoeven MOD_SEL1_6 5587077365a9SGeert Uytterhoeven MOD_SEL1_5 5588077365a9SGeert Uytterhoeven MOD_SEL1_4 5589077365a9SGeert Uytterhoeven MOD_SEL1_3 5590077365a9SGeert Uytterhoeven MOD_SEL1_2 5591077365a9SGeert Uytterhoeven MOD_SEL1_1 5592077365a9SGeert Uytterhoeven MOD_SEL1_0 )) 5593077365a9SGeert Uytterhoeven }, 5594077365a9SGeert Uytterhoeven { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32, 55955e0857fdSGeert Uytterhoeven GROUP(1, 1, 1, 2, 1, 3, -1, 1, 1, 1, 1, 1, 55965e0857fdSGeert Uytterhoeven -16, 1), 5597077365a9SGeert Uytterhoeven GROUP( 5598077365a9SGeert Uytterhoeven MOD_SEL2_31 5599077365a9SGeert Uytterhoeven MOD_SEL2_30 5600077365a9SGeert Uytterhoeven MOD_SEL2_29 5601077365a9SGeert Uytterhoeven MOD_SEL2_28_27 5602077365a9SGeert Uytterhoeven MOD_SEL2_26 5603077365a9SGeert Uytterhoeven MOD_SEL2_25_24_23 5604077365a9SGeert Uytterhoeven /* RESERVED 22 */ 5605077365a9SGeert Uytterhoeven MOD_SEL2_21 5606077365a9SGeert Uytterhoeven MOD_SEL2_20 5607077365a9SGeert Uytterhoeven MOD_SEL2_19 5608077365a9SGeert Uytterhoeven MOD_SEL2_18 5609077365a9SGeert Uytterhoeven MOD_SEL2_17 56105e0857fdSGeert Uytterhoeven /* RESERVED 16-1 */ 5611077365a9SGeert Uytterhoeven MOD_SEL2_0 )) 5612077365a9SGeert Uytterhoeven }, 5613077365a9SGeert Uytterhoeven { }, 5614077365a9SGeert Uytterhoeven }; 5615077365a9SGeert Uytterhoeven 5616077365a9SGeert Uytterhoeven static const struct pinmux_drive_reg pinmux_drive_regs[] = { 5617077365a9SGeert Uytterhoeven { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) { 5618077365a9SGeert Uytterhoeven { PIN_QSPI0_SPCLK, 28, 2 }, /* QSPI0_SPCLK */ 5619077365a9SGeert Uytterhoeven { PIN_QSPI0_MOSI_IO0, 24, 2 }, /* QSPI0_MOSI_IO0 */ 5620077365a9SGeert Uytterhoeven { PIN_QSPI0_MISO_IO1, 20, 2 }, /* QSPI0_MISO_IO1 */ 5621077365a9SGeert Uytterhoeven { PIN_QSPI0_IO2, 16, 2 }, /* QSPI0_IO2 */ 5622077365a9SGeert Uytterhoeven { PIN_QSPI0_IO3, 12, 2 }, /* QSPI0_IO3 */ 5623077365a9SGeert Uytterhoeven { PIN_QSPI0_SSL, 8, 2 }, /* QSPI0_SSL */ 5624077365a9SGeert Uytterhoeven { PIN_QSPI1_SPCLK, 4, 2 }, /* QSPI1_SPCLK */ 5625077365a9SGeert Uytterhoeven { PIN_QSPI1_MOSI_IO0, 0, 2 }, /* QSPI1_MOSI_IO0 */ 5626077365a9SGeert Uytterhoeven } }, 5627077365a9SGeert Uytterhoeven { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) { 5628077365a9SGeert Uytterhoeven { PIN_QSPI1_MISO_IO1, 28, 2 }, /* QSPI1_MISO_IO1 */ 5629077365a9SGeert Uytterhoeven { PIN_QSPI1_IO2, 24, 2 }, /* QSPI1_IO2 */ 5630077365a9SGeert Uytterhoeven { PIN_QSPI1_IO3, 20, 2 }, /* QSPI1_IO3 */ 5631077365a9SGeert Uytterhoeven { PIN_QSPI1_SSL, 16, 2 }, /* QSPI1_SSL */ 5632077365a9SGeert Uytterhoeven { PIN_RPC_INT_N, 12, 2 }, /* RPC_INT# */ 5633077365a9SGeert Uytterhoeven { PIN_RPC_WP_N, 8, 2 }, /* RPC_WP# */ 5634077365a9SGeert Uytterhoeven { PIN_RPC_RESET_N, 4, 2 }, /* RPC_RESET# */ 5635077365a9SGeert Uytterhoeven { PIN_AVB_RX_CTL, 0, 3 }, /* AVB_RX_CTL */ 5636077365a9SGeert Uytterhoeven } }, 5637077365a9SGeert Uytterhoeven { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) { 5638077365a9SGeert Uytterhoeven { PIN_AVB_RXC, 28, 3 }, /* AVB_RXC */ 5639077365a9SGeert Uytterhoeven { PIN_AVB_RD0, 24, 3 }, /* AVB_RD0 */ 5640077365a9SGeert Uytterhoeven { PIN_AVB_RD1, 20, 3 }, /* AVB_RD1 */ 5641077365a9SGeert Uytterhoeven { PIN_AVB_RD2, 16, 3 }, /* AVB_RD2 */ 5642077365a9SGeert Uytterhoeven { PIN_AVB_RD3, 12, 3 }, /* AVB_RD3 */ 5643077365a9SGeert Uytterhoeven { PIN_AVB_TX_CTL, 8, 3 }, /* AVB_TX_CTL */ 5644077365a9SGeert Uytterhoeven { PIN_AVB_TXC, 4, 3 }, /* AVB_TXC */ 5645077365a9SGeert Uytterhoeven { PIN_AVB_TD0, 0, 3 }, /* AVB_TD0 */ 5646077365a9SGeert Uytterhoeven } }, 5647077365a9SGeert Uytterhoeven { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) { 5648077365a9SGeert Uytterhoeven { PIN_AVB_TD1, 28, 3 }, /* AVB_TD1 */ 5649077365a9SGeert Uytterhoeven { PIN_AVB_TD2, 24, 3 }, /* AVB_TD2 */ 5650077365a9SGeert Uytterhoeven { PIN_AVB_TD3, 20, 3 }, /* AVB_TD3 */ 5651077365a9SGeert Uytterhoeven { PIN_AVB_TXCREFCLK, 16, 3 }, /* AVB_TXCREFCLK */ 5652077365a9SGeert Uytterhoeven { PIN_AVB_MDIO, 12, 3 }, /* AVB_MDIO */ 5653077365a9SGeert Uytterhoeven { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */ 5654077365a9SGeert Uytterhoeven { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */ 5655077365a9SGeert Uytterhoeven { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */ 5656077365a9SGeert Uytterhoeven } }, 5657077365a9SGeert Uytterhoeven { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) { 5658077365a9SGeert Uytterhoeven { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */ 5659077365a9SGeert Uytterhoeven { RCAR_GP_PIN(2, 13), 24, 3 }, /* AVB_AVTP_MATCH */ 5660077365a9SGeert Uytterhoeven { RCAR_GP_PIN(2, 14), 20, 3 }, /* AVB_AVTP_CAPTURE */ 5661077365a9SGeert Uytterhoeven { RCAR_GP_PIN(2, 0), 16, 3 }, /* IRQ0 */ 5662077365a9SGeert Uytterhoeven { RCAR_GP_PIN(2, 1), 12, 3 }, /* IRQ1 */ 5663077365a9SGeert Uytterhoeven { RCAR_GP_PIN(2, 2), 8, 3 }, /* IRQ2 */ 5664077365a9SGeert Uytterhoeven { RCAR_GP_PIN(2, 3), 4, 3 }, /* IRQ3 */ 5665077365a9SGeert Uytterhoeven { RCAR_GP_PIN(2, 4), 0, 3 }, /* IRQ4 */ 5666077365a9SGeert Uytterhoeven } }, 5667077365a9SGeert Uytterhoeven { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) { 5668077365a9SGeert Uytterhoeven { RCAR_GP_PIN(2, 5), 28, 3 }, /* IRQ5 */ 5669077365a9SGeert Uytterhoeven { RCAR_GP_PIN(2, 6), 24, 3 }, /* PWM0 */ 5670077365a9SGeert Uytterhoeven { RCAR_GP_PIN(2, 7), 20, 3 }, /* PWM1 */ 5671077365a9SGeert Uytterhoeven { RCAR_GP_PIN(2, 8), 16, 3 }, /* PWM2 */ 5672077365a9SGeert Uytterhoeven { RCAR_GP_PIN(1, 0), 12, 3 }, /* A0 */ 5673077365a9SGeert Uytterhoeven { RCAR_GP_PIN(1, 1), 8, 3 }, /* A1 */ 5674077365a9SGeert Uytterhoeven { RCAR_GP_PIN(1, 2), 4, 3 }, /* A2 */ 5675077365a9SGeert Uytterhoeven { RCAR_GP_PIN(1, 3), 0, 3 }, /* A3 */ 5676077365a9SGeert Uytterhoeven } }, 5677077365a9SGeert Uytterhoeven { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) { 5678077365a9SGeert Uytterhoeven { RCAR_GP_PIN(1, 4), 28, 3 }, /* A4 */ 5679077365a9SGeert Uytterhoeven { RCAR_GP_PIN(1, 5), 24, 3 }, /* A5 */ 5680077365a9SGeert Uytterhoeven { RCAR_GP_PIN(1, 6), 20, 3 }, /* A6 */ 5681077365a9SGeert Uytterhoeven { RCAR_GP_PIN(1, 7), 16, 3 }, /* A7 */ 5682077365a9SGeert Uytterhoeven { RCAR_GP_PIN(1, 8), 12, 3 }, /* A8 */ 5683077365a9SGeert Uytterhoeven { RCAR_GP_PIN(1, 9), 8, 3 }, /* A9 */ 5684077365a9SGeert Uytterhoeven { RCAR_GP_PIN(1, 10), 4, 3 }, /* A10 */ 5685077365a9SGeert Uytterhoeven { RCAR_GP_PIN(1, 11), 0, 3 }, /* A11 */ 5686077365a9SGeert Uytterhoeven } }, 5687077365a9SGeert Uytterhoeven { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) { 5688077365a9SGeert Uytterhoeven { RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */ 5689077365a9SGeert Uytterhoeven { RCAR_GP_PIN(1, 13), 24, 3 }, /* A13 */ 5690077365a9SGeert Uytterhoeven { RCAR_GP_PIN(1, 14), 20, 3 }, /* A14 */ 5691077365a9SGeert Uytterhoeven { RCAR_GP_PIN(1, 15), 16, 3 }, /* A15 */ 5692077365a9SGeert Uytterhoeven { RCAR_GP_PIN(1, 16), 12, 3 }, /* A16 */ 5693077365a9SGeert Uytterhoeven { RCAR_GP_PIN(1, 17), 8, 3 }, /* A17 */ 5694077365a9SGeert Uytterhoeven { RCAR_GP_PIN(1, 18), 4, 3 }, /* A18 */ 5695077365a9SGeert Uytterhoeven { RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */ 5696077365a9SGeert Uytterhoeven } }, 5697077365a9SGeert Uytterhoeven { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) { 5698077365a9SGeert Uytterhoeven { RCAR_GP_PIN(1, 28), 28, 3 }, /* CLKOUT */ 5699077365a9SGeert Uytterhoeven { RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */ 5700077365a9SGeert Uytterhoeven { RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */ 5701077365a9SGeert Uytterhoeven { RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */ 5702077365a9SGeert Uytterhoeven { RCAR_GP_PIN(1, 23), 12, 3 }, /* RD */ 5703077365a9SGeert Uytterhoeven { RCAR_GP_PIN(1, 24), 8, 3 }, /* RD_WR */ 5704077365a9SGeert Uytterhoeven { RCAR_GP_PIN(1, 25), 4, 3 }, /* WE0 */ 5705077365a9SGeert Uytterhoeven { RCAR_GP_PIN(1, 26), 0, 3 }, /* WE1 */ 5706077365a9SGeert Uytterhoeven } }, 5707077365a9SGeert Uytterhoeven { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) { 5708077365a9SGeert Uytterhoeven { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */ 5709077365a9SGeert Uytterhoeven { PIN_PRESETOUT_N, 24, 3 }, /* PRESETOUT# */ 5710077365a9SGeert Uytterhoeven { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */ 5711077365a9SGeert Uytterhoeven { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */ 5712077365a9SGeert Uytterhoeven { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */ 5713077365a9SGeert Uytterhoeven { RCAR_GP_PIN(0, 3), 8, 3 }, /* D3 */ 5714077365a9SGeert Uytterhoeven { RCAR_GP_PIN(0, 4), 4, 3 }, /* D4 */ 5715077365a9SGeert Uytterhoeven { RCAR_GP_PIN(0, 5), 0, 3 }, /* D5 */ 5716077365a9SGeert Uytterhoeven } }, 5717077365a9SGeert Uytterhoeven { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) { 5718077365a9SGeert Uytterhoeven { RCAR_GP_PIN(0, 6), 28, 3 }, /* D6 */ 5719077365a9SGeert Uytterhoeven { RCAR_GP_PIN(0, 7), 24, 3 }, /* D7 */ 5720077365a9SGeert Uytterhoeven { RCAR_GP_PIN(0, 8), 20, 3 }, /* D8 */ 5721077365a9SGeert Uytterhoeven { RCAR_GP_PIN(0, 9), 16, 3 }, /* D9 */ 5722077365a9SGeert Uytterhoeven { RCAR_GP_PIN(0, 10), 12, 3 }, /* D10 */ 5723077365a9SGeert Uytterhoeven { RCAR_GP_PIN(0, 11), 8, 3 }, /* D11 */ 5724077365a9SGeert Uytterhoeven { RCAR_GP_PIN(0, 12), 4, 3 }, /* D12 */ 5725077365a9SGeert Uytterhoeven { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */ 5726077365a9SGeert Uytterhoeven } }, 5727077365a9SGeert Uytterhoeven { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) { 5728077365a9SGeert Uytterhoeven { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */ 5729077365a9SGeert Uytterhoeven { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */ 5730077365a9SGeert Uytterhoeven { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */ 5731077365a9SGeert Uytterhoeven { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */ 5732077365a9SGeert Uytterhoeven { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */ 5733077365a9SGeert Uytterhoeven { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */ 5734077365a9SGeert Uytterhoeven { PIN_DU_DOTCLKIN0, 4, 2 }, /* DU_DOTCLKIN0 */ 5735077365a9SGeert Uytterhoeven { PIN_DU_DOTCLKIN1, 0, 2 }, /* DU_DOTCLKIN1 */ 5736077365a9SGeert Uytterhoeven } }, 5737077365a9SGeert Uytterhoeven { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) { 5738077365a9SGeert Uytterhoeven #ifdef CONFIG_PINCTRL_PFC_R8A77951 5739077365a9SGeert Uytterhoeven { PIN_DU_DOTCLKIN2, 28, 2 }, /* DU_DOTCLKIN2 */ 5740077365a9SGeert Uytterhoeven #endif 5741077365a9SGeert Uytterhoeven { PIN_DU_DOTCLKIN3, 24, 2 }, /* DU_DOTCLKIN3 */ 5742077365a9SGeert Uytterhoeven { PIN_FSCLKST_N, 20, 2 }, /* FSCLKST# */ 5743077365a9SGeert Uytterhoeven { PIN_TMS, 4, 2 }, /* TMS */ 5744077365a9SGeert Uytterhoeven } }, 5745077365a9SGeert Uytterhoeven { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) { 5746077365a9SGeert Uytterhoeven { PIN_TDO, 28, 2 }, /* TDO */ 5747077365a9SGeert Uytterhoeven { PIN_ASEBRK, 24, 2 }, /* ASEBRK */ 5748077365a9SGeert Uytterhoeven { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */ 5749077365a9SGeert Uytterhoeven { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */ 5750077365a9SGeert Uytterhoeven { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */ 5751077365a9SGeert Uytterhoeven { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */ 5752077365a9SGeert Uytterhoeven { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */ 5753077365a9SGeert Uytterhoeven { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */ 5754077365a9SGeert Uytterhoeven } }, 5755077365a9SGeert Uytterhoeven { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) { 5756077365a9SGeert Uytterhoeven { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */ 5757077365a9SGeert Uytterhoeven { RCAR_GP_PIN(3, 7), 24, 3 }, /* SD1_CMD */ 5758077365a9SGeert Uytterhoeven { RCAR_GP_PIN(3, 8), 20, 3 }, /* SD1_DAT0 */ 5759077365a9SGeert Uytterhoeven { RCAR_GP_PIN(3, 9), 16, 3 }, /* SD1_DAT1 */ 5760077365a9SGeert Uytterhoeven { RCAR_GP_PIN(3, 10), 12, 3 }, /* SD1_DAT2 */ 5761077365a9SGeert Uytterhoeven { RCAR_GP_PIN(3, 11), 8, 3 }, /* SD1_DAT3 */ 5762077365a9SGeert Uytterhoeven { RCAR_GP_PIN(4, 0), 4, 3 }, /* SD2_CLK */ 5763077365a9SGeert Uytterhoeven { RCAR_GP_PIN(4, 1), 0, 3 }, /* SD2_CMD */ 5764077365a9SGeert Uytterhoeven } }, 5765077365a9SGeert Uytterhoeven { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) { 5766077365a9SGeert Uytterhoeven { RCAR_GP_PIN(4, 2), 28, 3 }, /* SD2_DAT0 */ 5767077365a9SGeert Uytterhoeven { RCAR_GP_PIN(4, 3), 24, 3 }, /* SD2_DAT1 */ 5768077365a9SGeert Uytterhoeven { RCAR_GP_PIN(4, 4), 20, 3 }, /* SD2_DAT2 */ 5769077365a9SGeert Uytterhoeven { RCAR_GP_PIN(4, 5), 16, 3 }, /* SD2_DAT3 */ 5770077365a9SGeert Uytterhoeven { RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */ 5771077365a9SGeert Uytterhoeven { RCAR_GP_PIN(4, 7), 8, 3 }, /* SD3_CLK */ 5772077365a9SGeert Uytterhoeven { RCAR_GP_PIN(4, 8), 4, 3 }, /* SD3_CMD */ 5773077365a9SGeert Uytterhoeven { RCAR_GP_PIN(4, 9), 0, 3 }, /* SD3_DAT0 */ 5774077365a9SGeert Uytterhoeven } }, 5775077365a9SGeert Uytterhoeven { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) { 5776077365a9SGeert Uytterhoeven { RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */ 5777077365a9SGeert Uytterhoeven { RCAR_GP_PIN(4, 11), 24, 3 }, /* SD3_DAT2 */ 5778077365a9SGeert Uytterhoeven { RCAR_GP_PIN(4, 12), 20, 3 }, /* SD3_DAT3 */ 5779077365a9SGeert Uytterhoeven { RCAR_GP_PIN(4, 13), 16, 3 }, /* SD3_DAT4 */ 5780077365a9SGeert Uytterhoeven { RCAR_GP_PIN(4, 14), 12, 3 }, /* SD3_DAT5 */ 5781077365a9SGeert Uytterhoeven { RCAR_GP_PIN(4, 15), 8, 3 }, /* SD3_DAT6 */ 5782077365a9SGeert Uytterhoeven { RCAR_GP_PIN(4, 16), 4, 3 }, /* SD3_DAT7 */ 5783077365a9SGeert Uytterhoeven { RCAR_GP_PIN(4, 17), 0, 3 }, /* SD3_DS */ 5784077365a9SGeert Uytterhoeven } }, 5785077365a9SGeert Uytterhoeven { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) { 5786077365a9SGeert Uytterhoeven { RCAR_GP_PIN(3, 12), 28, 3 }, /* SD0_CD */ 5787077365a9SGeert Uytterhoeven { RCAR_GP_PIN(3, 13), 24, 3 }, /* SD0_WP */ 5788077365a9SGeert Uytterhoeven { RCAR_GP_PIN(3, 14), 20, 3 }, /* SD1_CD */ 5789077365a9SGeert Uytterhoeven { RCAR_GP_PIN(3, 15), 16, 3 }, /* SD1_WP */ 5790077365a9SGeert Uytterhoeven { RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */ 5791077365a9SGeert Uytterhoeven { RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */ 5792077365a9SGeert Uytterhoeven { RCAR_GP_PIN(5, 2), 4, 3 }, /* TX0 */ 5793077365a9SGeert Uytterhoeven { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */ 5794077365a9SGeert Uytterhoeven } }, 5795077365a9SGeert Uytterhoeven { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) { 5796077365a9SGeert Uytterhoeven { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0 */ 5797077365a9SGeert Uytterhoeven { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */ 5798077365a9SGeert Uytterhoeven { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */ 5799077365a9SGeert Uytterhoeven { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */ 5800077365a9SGeert Uytterhoeven { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1 */ 5801077365a9SGeert Uytterhoeven { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */ 5802077365a9SGeert Uytterhoeven { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */ 5803077365a9SGeert Uytterhoeven { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */ 5804077365a9SGeert Uytterhoeven } }, 5805077365a9SGeert Uytterhoeven { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) { 5806077365a9SGeert Uytterhoeven { RCAR_GP_PIN(5, 12), 28, 3 }, /* HSCK0 */ 5807077365a9SGeert Uytterhoeven { RCAR_GP_PIN(5, 13), 24, 3 }, /* HRX0 */ 5808077365a9SGeert Uytterhoeven { RCAR_GP_PIN(5, 14), 20, 3 }, /* HTX0 */ 5809077365a9SGeert Uytterhoeven { RCAR_GP_PIN(5, 15), 16, 3 }, /* HCTS0 */ 5810077365a9SGeert Uytterhoeven { RCAR_GP_PIN(5, 16), 12, 3 }, /* HRTS0 */ 5811077365a9SGeert Uytterhoeven { RCAR_GP_PIN(5, 17), 8, 3 }, /* MSIOF0_SCK */ 5812077365a9SGeert Uytterhoeven { RCAR_GP_PIN(5, 18), 4, 3 }, /* MSIOF0_SYNC */ 5813077365a9SGeert Uytterhoeven { RCAR_GP_PIN(5, 19), 0, 3 }, /* MSIOF0_SS1 */ 5814077365a9SGeert Uytterhoeven } }, 5815077365a9SGeert Uytterhoeven { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) { 5816077365a9SGeert Uytterhoeven { RCAR_GP_PIN(5, 20), 28, 3 }, /* MSIOF0_TXD */ 5817077365a9SGeert Uytterhoeven { RCAR_GP_PIN(5, 21), 24, 3 }, /* MSIOF0_SS2 */ 5818077365a9SGeert Uytterhoeven { RCAR_GP_PIN(5, 22), 20, 3 }, /* MSIOF0_RXD */ 5819077365a9SGeert Uytterhoeven { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */ 5820077365a9SGeert Uytterhoeven { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */ 5821077365a9SGeert Uytterhoeven { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */ 5822077365a9SGeert Uytterhoeven { PIN_MLB_REF, 4, 3 }, /* MLB_REF */ 5823077365a9SGeert Uytterhoeven { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */ 5824077365a9SGeert Uytterhoeven } }, 5825077365a9SGeert Uytterhoeven { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) { 5826077365a9SGeert Uytterhoeven { RCAR_GP_PIN(6, 1), 28, 3 }, /* SSI_WS01239 */ 5827077365a9SGeert Uytterhoeven { RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */ 5828077365a9SGeert Uytterhoeven { RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */ 5829077365a9SGeert Uytterhoeven { RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */ 5830077365a9SGeert Uytterhoeven { RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK349 */ 5831077365a9SGeert Uytterhoeven { RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS349 */ 5832077365a9SGeert Uytterhoeven { RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */ 5833077365a9SGeert Uytterhoeven { RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */ 5834077365a9SGeert Uytterhoeven } }, 5835077365a9SGeert Uytterhoeven { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) { 5836077365a9SGeert Uytterhoeven { RCAR_GP_PIN(6, 9), 28, 3 }, /* SSI_WS4 */ 5837077365a9SGeert Uytterhoeven { RCAR_GP_PIN(6, 10), 24, 3 }, /* SSI_SDATA4 */ 5838077365a9SGeert Uytterhoeven { RCAR_GP_PIN(6, 11), 20, 3 }, /* SSI_SCK5 */ 5839077365a9SGeert Uytterhoeven { RCAR_GP_PIN(6, 12), 16, 3 }, /* SSI_WS5 */ 5840077365a9SGeert Uytterhoeven { RCAR_GP_PIN(6, 13), 12, 3 }, /* SSI_SDATA5 */ 5841077365a9SGeert Uytterhoeven { RCAR_GP_PIN(6, 14), 8, 3 }, /* SSI_SCK6 */ 5842077365a9SGeert Uytterhoeven { RCAR_GP_PIN(6, 15), 4, 3 }, /* SSI_WS6 */ 5843077365a9SGeert Uytterhoeven { RCAR_GP_PIN(6, 16), 0, 3 }, /* SSI_SDATA6 */ 5844077365a9SGeert Uytterhoeven } }, 5845077365a9SGeert Uytterhoeven { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) { 5846077365a9SGeert Uytterhoeven { RCAR_GP_PIN(6, 17), 28, 3 }, /* SSI_SCK78 */ 5847077365a9SGeert Uytterhoeven { RCAR_GP_PIN(6, 18), 24, 3 }, /* SSI_WS78 */ 5848077365a9SGeert Uytterhoeven { RCAR_GP_PIN(6, 19), 20, 3 }, /* SSI_SDATA7 */ 5849077365a9SGeert Uytterhoeven { RCAR_GP_PIN(6, 20), 16, 3 }, /* SSI_SDATA8 */ 5850077365a9SGeert Uytterhoeven { RCAR_GP_PIN(6, 21), 12, 3 }, /* SSI_SDATA9 */ 5851077365a9SGeert Uytterhoeven { RCAR_GP_PIN(6, 22), 8, 3 }, /* AUDIO_CLKA */ 5852077365a9SGeert Uytterhoeven { RCAR_GP_PIN(6, 23), 4, 3 }, /* AUDIO_CLKB */ 5853077365a9SGeert Uytterhoeven { RCAR_GP_PIN(6, 24), 0, 3 }, /* USB0_PWEN */ 5854077365a9SGeert Uytterhoeven } }, 5855077365a9SGeert Uytterhoeven { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) { 5856077365a9SGeert Uytterhoeven { RCAR_GP_PIN(6, 25), 28, 3 }, /* USB0_OVC */ 5857077365a9SGeert Uytterhoeven { RCAR_GP_PIN(6, 26), 24, 3 }, /* USB1_PWEN */ 5858077365a9SGeert Uytterhoeven { RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */ 5859077365a9SGeert Uytterhoeven { RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */ 5860077365a9SGeert Uytterhoeven { RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */ 5861077365a9SGeert Uytterhoeven { RCAR_GP_PIN(6, 30), 8, 3 }, /* GP6_30/USB2_CH3_PWEN */ 5862077365a9SGeert Uytterhoeven { RCAR_GP_PIN(6, 31), 4, 3 }, /* GP6_31/USB2_CH3_OVC */ 5863077365a9SGeert Uytterhoeven } }, 5864077365a9SGeert Uytterhoeven { }, 5865077365a9SGeert Uytterhoeven }; 5866077365a9SGeert Uytterhoeven 5867077365a9SGeert Uytterhoeven enum ioctrl_regs { 5868077365a9SGeert Uytterhoeven POCCTRL, 5869077365a9SGeert Uytterhoeven TDSELCTRL, 5870077365a9SGeert Uytterhoeven }; 5871077365a9SGeert Uytterhoeven 5872077365a9SGeert Uytterhoeven static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { 5873077365a9SGeert Uytterhoeven [POCCTRL] = { 0xe6060380, }, 5874077365a9SGeert Uytterhoeven [TDSELCTRL] = { 0xe60603c0, }, 5875077365a9SGeert Uytterhoeven { /* sentinel */ }, 5876077365a9SGeert Uytterhoeven }; 5877077365a9SGeert Uytterhoeven 5878b67fc1c6SGeert Uytterhoeven static int r8a77951_pin_to_pocctrl(unsigned int pin, u32 *pocctrl) 5879077365a9SGeert Uytterhoeven { 5880077365a9SGeert Uytterhoeven int bit = -EINVAL; 5881077365a9SGeert Uytterhoeven 5882077365a9SGeert Uytterhoeven *pocctrl = pinmux_ioctrl_regs[POCCTRL].reg; 5883077365a9SGeert Uytterhoeven 5884077365a9SGeert Uytterhoeven if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11)) 5885077365a9SGeert Uytterhoeven bit = pin & 0x1f; 5886077365a9SGeert Uytterhoeven 5887077365a9SGeert Uytterhoeven if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17)) 5888077365a9SGeert Uytterhoeven bit = (pin & 0x1f) + 12; 5889077365a9SGeert Uytterhoeven 5890077365a9SGeert Uytterhoeven return bit; 5891077365a9SGeert Uytterhoeven } 5892077365a9SGeert Uytterhoeven 5893077365a9SGeert Uytterhoeven static const struct pinmux_bias_reg pinmux_bias_regs[] = { 5894077365a9SGeert Uytterhoeven { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) { 5895077365a9SGeert Uytterhoeven [ 0] = PIN_QSPI0_SPCLK, /* QSPI0_SPCLK */ 5896077365a9SGeert Uytterhoeven [ 1] = PIN_QSPI0_MOSI_IO0, /* QSPI0_MOSI_IO0 */ 5897077365a9SGeert Uytterhoeven [ 2] = PIN_QSPI0_MISO_IO1, /* QSPI0_MISO_IO1 */ 5898077365a9SGeert Uytterhoeven [ 3] = PIN_QSPI0_IO2, /* QSPI0_IO2 */ 5899077365a9SGeert Uytterhoeven [ 4] = PIN_QSPI0_IO3, /* QSPI0_IO3 */ 5900077365a9SGeert Uytterhoeven [ 5] = PIN_QSPI0_SSL, /* QSPI0_SSL */ 5901077365a9SGeert Uytterhoeven [ 6] = PIN_QSPI1_SPCLK, /* QSPI1_SPCLK */ 5902077365a9SGeert Uytterhoeven [ 7] = PIN_QSPI1_MOSI_IO0, /* QSPI1_MOSI_IO0 */ 5903077365a9SGeert Uytterhoeven [ 8] = PIN_QSPI1_MISO_IO1, /* QSPI1_MISO_IO1 */ 5904077365a9SGeert Uytterhoeven [ 9] = PIN_QSPI1_IO2, /* QSPI1_IO2 */ 5905077365a9SGeert Uytterhoeven [10] = PIN_QSPI1_IO3, /* QSPI1_IO3 */ 5906077365a9SGeert Uytterhoeven [11] = PIN_QSPI1_SSL, /* QSPI1_SSL */ 5907077365a9SGeert Uytterhoeven [12] = PIN_RPC_INT_N, /* RPC_INT# */ 5908077365a9SGeert Uytterhoeven [13] = PIN_RPC_WP_N, /* RPC_WP# */ 5909077365a9SGeert Uytterhoeven [14] = PIN_RPC_RESET_N, /* RPC_RESET# */ 5910077365a9SGeert Uytterhoeven [15] = PIN_AVB_RX_CTL, /* AVB_RX_CTL */ 5911077365a9SGeert Uytterhoeven [16] = PIN_AVB_RXC, /* AVB_RXC */ 5912077365a9SGeert Uytterhoeven [17] = PIN_AVB_RD0, /* AVB_RD0 */ 5913077365a9SGeert Uytterhoeven [18] = PIN_AVB_RD1, /* AVB_RD1 */ 5914077365a9SGeert Uytterhoeven [19] = PIN_AVB_RD2, /* AVB_RD2 */ 5915077365a9SGeert Uytterhoeven [20] = PIN_AVB_RD3, /* AVB_RD3 */ 5916077365a9SGeert Uytterhoeven [21] = PIN_AVB_TX_CTL, /* AVB_TX_CTL */ 5917077365a9SGeert Uytterhoeven [22] = PIN_AVB_TXC, /* AVB_TXC */ 5918077365a9SGeert Uytterhoeven [23] = PIN_AVB_TD0, /* AVB_TD0 */ 5919077365a9SGeert Uytterhoeven [24] = PIN_AVB_TD1, /* AVB_TD1 */ 5920077365a9SGeert Uytterhoeven [25] = PIN_AVB_TD2, /* AVB_TD2 */ 5921077365a9SGeert Uytterhoeven [26] = PIN_AVB_TD3, /* AVB_TD3 */ 5922077365a9SGeert Uytterhoeven [27] = PIN_AVB_TXCREFCLK, /* AVB_TXCREFCLK */ 5923077365a9SGeert Uytterhoeven [28] = PIN_AVB_MDIO, /* AVB_MDIO */ 5924077365a9SGeert Uytterhoeven [29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */ 5925077365a9SGeert Uytterhoeven [30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */ 5926077365a9SGeert Uytterhoeven [31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */ 5927077365a9SGeert Uytterhoeven } }, 5928077365a9SGeert Uytterhoeven { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) { 5929077365a9SGeert Uytterhoeven [ 0] = RCAR_GP_PIN(2, 12), /* AVB_LINK */ 5930077365a9SGeert Uytterhoeven [ 1] = RCAR_GP_PIN(2, 13), /* AVB_AVTP_MATCH_A */ 5931077365a9SGeert Uytterhoeven [ 2] = RCAR_GP_PIN(2, 14), /* AVB_AVTP_CAPTURE_A */ 5932077365a9SGeert Uytterhoeven [ 3] = RCAR_GP_PIN(2, 0), /* IRQ0 */ 5933077365a9SGeert Uytterhoeven [ 4] = RCAR_GP_PIN(2, 1), /* IRQ1 */ 5934077365a9SGeert Uytterhoeven [ 5] = RCAR_GP_PIN(2, 2), /* IRQ2 */ 5935077365a9SGeert Uytterhoeven [ 6] = RCAR_GP_PIN(2, 3), /* IRQ3 */ 5936077365a9SGeert Uytterhoeven [ 7] = RCAR_GP_PIN(2, 4), /* IRQ4 */ 5937077365a9SGeert Uytterhoeven [ 8] = RCAR_GP_PIN(2, 5), /* IRQ5 */ 5938077365a9SGeert Uytterhoeven [ 9] = RCAR_GP_PIN(2, 6), /* PWM0 */ 5939077365a9SGeert Uytterhoeven [10] = RCAR_GP_PIN(2, 7), /* PWM1_A */ 5940077365a9SGeert Uytterhoeven [11] = RCAR_GP_PIN(2, 8), /* PWM2_A */ 5941077365a9SGeert Uytterhoeven [12] = RCAR_GP_PIN(1, 0), /* A0 */ 5942077365a9SGeert Uytterhoeven [13] = RCAR_GP_PIN(1, 1), /* A1 */ 5943077365a9SGeert Uytterhoeven [14] = RCAR_GP_PIN(1, 2), /* A2 */ 5944077365a9SGeert Uytterhoeven [15] = RCAR_GP_PIN(1, 3), /* A3 */ 5945077365a9SGeert Uytterhoeven [16] = RCAR_GP_PIN(1, 4), /* A4 */ 5946077365a9SGeert Uytterhoeven [17] = RCAR_GP_PIN(1, 5), /* A5 */ 5947077365a9SGeert Uytterhoeven [18] = RCAR_GP_PIN(1, 6), /* A6 */ 5948077365a9SGeert Uytterhoeven [19] = RCAR_GP_PIN(1, 7), /* A7 */ 5949077365a9SGeert Uytterhoeven [20] = RCAR_GP_PIN(1, 8), /* A8 */ 5950077365a9SGeert Uytterhoeven [21] = RCAR_GP_PIN(1, 9), /* A9 */ 5951077365a9SGeert Uytterhoeven [22] = RCAR_GP_PIN(1, 10), /* A10 */ 5952077365a9SGeert Uytterhoeven [23] = RCAR_GP_PIN(1, 11), /* A11 */ 5953077365a9SGeert Uytterhoeven [24] = RCAR_GP_PIN(1, 12), /* A12 */ 5954077365a9SGeert Uytterhoeven [25] = RCAR_GP_PIN(1, 13), /* A13 */ 5955077365a9SGeert Uytterhoeven [26] = RCAR_GP_PIN(1, 14), /* A14 */ 5956077365a9SGeert Uytterhoeven [27] = RCAR_GP_PIN(1, 15), /* A15 */ 5957077365a9SGeert Uytterhoeven [28] = RCAR_GP_PIN(1, 16), /* A16 */ 5958077365a9SGeert Uytterhoeven [29] = RCAR_GP_PIN(1, 17), /* A17 */ 5959077365a9SGeert Uytterhoeven [30] = RCAR_GP_PIN(1, 18), /* A18 */ 5960077365a9SGeert Uytterhoeven [31] = RCAR_GP_PIN(1, 19), /* A19 */ 5961077365a9SGeert Uytterhoeven } }, 5962077365a9SGeert Uytterhoeven { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) { 5963077365a9SGeert Uytterhoeven [ 0] = RCAR_GP_PIN(1, 28), /* CLKOUT */ 5964077365a9SGeert Uytterhoeven [ 1] = RCAR_GP_PIN(1, 20), /* CS0_N */ 5965077365a9SGeert Uytterhoeven [ 2] = RCAR_GP_PIN(1, 21), /* CS1_N */ 5966077365a9SGeert Uytterhoeven [ 3] = RCAR_GP_PIN(1, 22), /* BS_N */ 5967077365a9SGeert Uytterhoeven [ 4] = RCAR_GP_PIN(1, 23), /* RD_N */ 5968077365a9SGeert Uytterhoeven [ 5] = RCAR_GP_PIN(1, 24), /* RD_WR_N */ 5969077365a9SGeert Uytterhoeven [ 6] = RCAR_GP_PIN(1, 25), /* WE0_N */ 5970077365a9SGeert Uytterhoeven [ 7] = RCAR_GP_PIN(1, 26), /* WE1_N */ 5971077365a9SGeert Uytterhoeven [ 8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */ 5972077365a9SGeert Uytterhoeven [ 9] = PIN_PRESETOUT_N, /* PRESETOUT# */ 5973077365a9SGeert Uytterhoeven [10] = RCAR_GP_PIN(0, 0), /* D0 */ 5974077365a9SGeert Uytterhoeven [11] = RCAR_GP_PIN(0, 1), /* D1 */ 5975077365a9SGeert Uytterhoeven [12] = RCAR_GP_PIN(0, 2), /* D2 */ 5976077365a9SGeert Uytterhoeven [13] = RCAR_GP_PIN(0, 3), /* D3 */ 5977077365a9SGeert Uytterhoeven [14] = RCAR_GP_PIN(0, 4), /* D4 */ 5978077365a9SGeert Uytterhoeven [15] = RCAR_GP_PIN(0, 5), /* D5 */ 5979077365a9SGeert Uytterhoeven [16] = RCAR_GP_PIN(0, 6), /* D6 */ 5980077365a9SGeert Uytterhoeven [17] = RCAR_GP_PIN(0, 7), /* D7 */ 5981077365a9SGeert Uytterhoeven [18] = RCAR_GP_PIN(0, 8), /* D8 */ 5982077365a9SGeert Uytterhoeven [19] = RCAR_GP_PIN(0, 9), /* D9 */ 5983077365a9SGeert Uytterhoeven [20] = RCAR_GP_PIN(0, 10), /* D10 */ 5984077365a9SGeert Uytterhoeven [21] = RCAR_GP_PIN(0, 11), /* D11 */ 5985077365a9SGeert Uytterhoeven [22] = RCAR_GP_PIN(0, 12), /* D12 */ 5986077365a9SGeert Uytterhoeven [23] = RCAR_GP_PIN(0, 13), /* D13 */ 5987077365a9SGeert Uytterhoeven [24] = RCAR_GP_PIN(0, 14), /* D14 */ 5988077365a9SGeert Uytterhoeven [25] = RCAR_GP_PIN(0, 15), /* D15 */ 5989077365a9SGeert Uytterhoeven [26] = RCAR_GP_PIN(7, 0), /* AVS1 */ 5990077365a9SGeert Uytterhoeven [27] = RCAR_GP_PIN(7, 1), /* AVS2 */ 5991077365a9SGeert Uytterhoeven [28] = RCAR_GP_PIN(7, 2), /* GP7_02 */ 5992077365a9SGeert Uytterhoeven [29] = RCAR_GP_PIN(7, 3), /* GP7_03 */ 5993077365a9SGeert Uytterhoeven [30] = PIN_DU_DOTCLKIN0, /* DU_DOTCLKIN0 */ 5994077365a9SGeert Uytterhoeven [31] = PIN_DU_DOTCLKIN1, /* DU_DOTCLKIN1 */ 5995077365a9SGeert Uytterhoeven } }, 5996077365a9SGeert Uytterhoeven { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) { 5997077365a9SGeert Uytterhoeven [ 0] = PIN_DU_DOTCLKIN2, /* DU_DOTCLKIN2 */ 5998077365a9SGeert Uytterhoeven [ 1] = PIN_DU_DOTCLKIN3, /* DU_DOTCLKIN3 */ 5999077365a9SGeert Uytterhoeven [ 2] = PIN_FSCLKST_N, /* FSCLKST# */ 6000077365a9SGeert Uytterhoeven [ 3] = PIN_EXTALR, /* EXTALR*/ 6001077365a9SGeert Uytterhoeven [ 4] = PIN_TRST_N, /* TRST# */ 6002077365a9SGeert Uytterhoeven [ 5] = PIN_TCK, /* TCK */ 6003077365a9SGeert Uytterhoeven [ 6] = PIN_TMS, /* TMS */ 6004077365a9SGeert Uytterhoeven [ 7] = PIN_TDI, /* TDI */ 6005077365a9SGeert Uytterhoeven [ 8] = SH_PFC_PIN_NONE, 6006077365a9SGeert Uytterhoeven [ 9] = PIN_ASEBRK, /* ASEBRK */ 6007077365a9SGeert Uytterhoeven [10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */ 6008077365a9SGeert Uytterhoeven [11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */ 6009077365a9SGeert Uytterhoeven [12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */ 6010077365a9SGeert Uytterhoeven [13] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */ 6011077365a9SGeert Uytterhoeven [14] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */ 6012077365a9SGeert Uytterhoeven [15] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */ 6013077365a9SGeert Uytterhoeven [16] = RCAR_GP_PIN(3, 6), /* SD1_CLK */ 6014077365a9SGeert Uytterhoeven [17] = RCAR_GP_PIN(3, 7), /* SD1_CMD */ 6015077365a9SGeert Uytterhoeven [18] = RCAR_GP_PIN(3, 8), /* SD1_DAT0 */ 6016077365a9SGeert Uytterhoeven [19] = RCAR_GP_PIN(3, 9), /* SD1_DAT1 */ 6017077365a9SGeert Uytterhoeven [20] = RCAR_GP_PIN(3, 10), /* SD1_DAT2 */ 6018077365a9SGeert Uytterhoeven [21] = RCAR_GP_PIN(3, 11), /* SD1_DAT3 */ 6019077365a9SGeert Uytterhoeven [22] = RCAR_GP_PIN(4, 0), /* SD2_CLK */ 6020077365a9SGeert Uytterhoeven [23] = RCAR_GP_PIN(4, 1), /* SD2_CMD */ 6021077365a9SGeert Uytterhoeven [24] = RCAR_GP_PIN(4, 2), /* SD2_DAT0 */ 6022077365a9SGeert Uytterhoeven [25] = RCAR_GP_PIN(4, 3), /* SD2_DAT1 */ 6023077365a9SGeert Uytterhoeven [26] = RCAR_GP_PIN(4, 4), /* SD2_DAT2 */ 6024077365a9SGeert Uytterhoeven [27] = RCAR_GP_PIN(4, 5), /* SD2_DAT3 */ 6025077365a9SGeert Uytterhoeven [28] = RCAR_GP_PIN(4, 6), /* SD2_DS */ 6026077365a9SGeert Uytterhoeven [29] = RCAR_GP_PIN(4, 7), /* SD3_CLK */ 6027077365a9SGeert Uytterhoeven [30] = RCAR_GP_PIN(4, 8), /* SD3_CMD */ 6028077365a9SGeert Uytterhoeven [31] = RCAR_GP_PIN(4, 9), /* SD3_DAT0 */ 6029077365a9SGeert Uytterhoeven } }, 6030077365a9SGeert Uytterhoeven { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) { 6031077365a9SGeert Uytterhoeven [ 0] = RCAR_GP_PIN(4, 10), /* SD3_DAT1 */ 6032077365a9SGeert Uytterhoeven [ 1] = RCAR_GP_PIN(4, 11), /* SD3_DAT2 */ 6033077365a9SGeert Uytterhoeven [ 2] = RCAR_GP_PIN(4, 12), /* SD3_DAT3 */ 6034077365a9SGeert Uytterhoeven [ 3] = RCAR_GP_PIN(4, 13), /* SD3_DAT4 */ 6035077365a9SGeert Uytterhoeven [ 4] = RCAR_GP_PIN(4, 14), /* SD3_DAT5 */ 6036077365a9SGeert Uytterhoeven [ 5] = RCAR_GP_PIN(4, 15), /* SD3_DAT6 */ 6037077365a9SGeert Uytterhoeven [ 6] = RCAR_GP_PIN(4, 16), /* SD3_DAT7 */ 6038077365a9SGeert Uytterhoeven [ 7] = RCAR_GP_PIN(4, 17), /* SD3_DS */ 6039077365a9SGeert Uytterhoeven [ 8] = RCAR_GP_PIN(3, 12), /* SD0_CD */ 6040077365a9SGeert Uytterhoeven [ 9] = RCAR_GP_PIN(3, 13), /* SD0_WP */ 6041077365a9SGeert Uytterhoeven [10] = RCAR_GP_PIN(3, 14), /* SD1_CD */ 6042077365a9SGeert Uytterhoeven [11] = RCAR_GP_PIN(3, 15), /* SD1_WP */ 6043077365a9SGeert Uytterhoeven [12] = RCAR_GP_PIN(5, 0), /* SCK0 */ 6044077365a9SGeert Uytterhoeven [13] = RCAR_GP_PIN(5, 1), /* RX0 */ 6045077365a9SGeert Uytterhoeven [14] = RCAR_GP_PIN(5, 2), /* TX0 */ 6046077365a9SGeert Uytterhoeven [15] = RCAR_GP_PIN(5, 3), /* CTS0_N */ 6047077365a9SGeert Uytterhoeven [16] = RCAR_GP_PIN(5, 4), /* RTS0_N */ 6048077365a9SGeert Uytterhoeven [17] = RCAR_GP_PIN(5, 5), /* RX1_A */ 6049077365a9SGeert Uytterhoeven [18] = RCAR_GP_PIN(5, 6), /* TX1_A */ 6050077365a9SGeert Uytterhoeven [19] = RCAR_GP_PIN(5, 7), /* CTS1_N */ 6051077365a9SGeert Uytterhoeven [20] = RCAR_GP_PIN(5, 8), /* RTS1_N */ 6052077365a9SGeert Uytterhoeven [21] = RCAR_GP_PIN(5, 9), /* SCK2 */ 6053077365a9SGeert Uytterhoeven [22] = RCAR_GP_PIN(5, 10), /* TX2_A */ 6054077365a9SGeert Uytterhoeven [23] = RCAR_GP_PIN(5, 11), /* RX2_A */ 6055077365a9SGeert Uytterhoeven [24] = RCAR_GP_PIN(5, 12), /* HSCK0 */ 6056077365a9SGeert Uytterhoeven [25] = RCAR_GP_PIN(5, 13), /* HRX0 */ 6057077365a9SGeert Uytterhoeven [26] = RCAR_GP_PIN(5, 14), /* HTX0 */ 6058077365a9SGeert Uytterhoeven [27] = RCAR_GP_PIN(5, 15), /* HCTS0_N */ 6059077365a9SGeert Uytterhoeven [28] = RCAR_GP_PIN(5, 16), /* HRTS0_N */ 6060077365a9SGeert Uytterhoeven [29] = RCAR_GP_PIN(5, 17), /* MSIOF0_SCK */ 6061077365a9SGeert Uytterhoeven [30] = RCAR_GP_PIN(5, 18), /* MSIOF0_SYNC */ 6062077365a9SGeert Uytterhoeven [31] = RCAR_GP_PIN(5, 19), /* MSIOF0_SS1 */ 6063077365a9SGeert Uytterhoeven } }, 6064077365a9SGeert Uytterhoeven { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) { 6065077365a9SGeert Uytterhoeven [ 0] = RCAR_GP_PIN(5, 20), /* MSIOF0_TXD */ 6066077365a9SGeert Uytterhoeven [ 1] = RCAR_GP_PIN(5, 21), /* MSIOF0_SS2 */ 6067077365a9SGeert Uytterhoeven [ 2] = RCAR_GP_PIN(5, 22), /* MSIOF0_RXD */ 6068077365a9SGeert Uytterhoeven [ 3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */ 6069077365a9SGeert Uytterhoeven [ 4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */ 6070077365a9SGeert Uytterhoeven [ 5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */ 6071077365a9SGeert Uytterhoeven [ 6] = PIN_MLB_REF, /* MLB_REF */ 6072077365a9SGeert Uytterhoeven [ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */ 6073077365a9SGeert Uytterhoeven [ 8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */ 6074077365a9SGeert Uytterhoeven [ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */ 6075077365a9SGeert Uytterhoeven [10] = RCAR_GP_PIN(6, 3), /* SSI_SDATA1_A */ 6076077365a9SGeert Uytterhoeven [11] = RCAR_GP_PIN(6, 4), /* SSI_SDATA2_A */ 6077077365a9SGeert Uytterhoeven [12] = RCAR_GP_PIN(6, 5), /* SSI_SCK349 */ 6078077365a9SGeert Uytterhoeven [13] = RCAR_GP_PIN(6, 6), /* SSI_WS349 */ 6079077365a9SGeert Uytterhoeven [14] = RCAR_GP_PIN(6, 7), /* SSI_SDATA3 */ 6080077365a9SGeert Uytterhoeven [15] = RCAR_GP_PIN(6, 8), /* SSI_SCK4 */ 6081077365a9SGeert Uytterhoeven [16] = RCAR_GP_PIN(6, 9), /* SSI_WS4 */ 6082077365a9SGeert Uytterhoeven [17] = RCAR_GP_PIN(6, 10), /* SSI_SDATA4 */ 6083077365a9SGeert Uytterhoeven [18] = RCAR_GP_PIN(6, 11), /* SSI_SCK5 */ 6084077365a9SGeert Uytterhoeven [19] = RCAR_GP_PIN(6, 12), /* SSI_WS5 */ 6085077365a9SGeert Uytterhoeven [20] = RCAR_GP_PIN(6, 13), /* SSI_SDATA5 */ 6086077365a9SGeert Uytterhoeven [21] = RCAR_GP_PIN(6, 14), /* SSI_SCK6 */ 6087077365a9SGeert Uytterhoeven [22] = RCAR_GP_PIN(6, 15), /* SSI_WS6 */ 6088077365a9SGeert Uytterhoeven [23] = RCAR_GP_PIN(6, 16), /* SSI_SDATA6 */ 6089077365a9SGeert Uytterhoeven [24] = RCAR_GP_PIN(6, 17), /* SSI_SCK78 */ 6090077365a9SGeert Uytterhoeven [25] = RCAR_GP_PIN(6, 18), /* SSI_WS78 */ 6091077365a9SGeert Uytterhoeven [26] = RCAR_GP_PIN(6, 19), /* SSI_SDATA7 */ 6092077365a9SGeert Uytterhoeven [27] = RCAR_GP_PIN(6, 20), /* SSI_SDATA8 */ 6093077365a9SGeert Uytterhoeven [28] = RCAR_GP_PIN(6, 21), /* SSI_SDATA9_A */ 6094077365a9SGeert Uytterhoeven [29] = RCAR_GP_PIN(6, 22), /* AUDIO_CLKA_A */ 6095077365a9SGeert Uytterhoeven [30] = RCAR_GP_PIN(6, 23), /* AUDIO_CLKB_B */ 6096077365a9SGeert Uytterhoeven [31] = RCAR_GP_PIN(6, 24), /* USB0_PWEN */ 6097077365a9SGeert Uytterhoeven } }, 6098077365a9SGeert Uytterhoeven { PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) { 6099077365a9SGeert Uytterhoeven [ 0] = RCAR_GP_PIN(6, 25), /* USB0_OVC */ 6100077365a9SGeert Uytterhoeven [ 1] = RCAR_GP_PIN(6, 26), /* USB1_PWEN */ 6101077365a9SGeert Uytterhoeven [ 2] = RCAR_GP_PIN(6, 27), /* USB1_OVC */ 6102077365a9SGeert Uytterhoeven [ 3] = RCAR_GP_PIN(6, 28), /* USB30_PWEN */ 6103077365a9SGeert Uytterhoeven [ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */ 6104077365a9SGeert Uytterhoeven [ 5] = RCAR_GP_PIN(6, 30), /* USB2_CH3_PWEN */ 6105077365a9SGeert Uytterhoeven [ 6] = RCAR_GP_PIN(6, 31), /* USB2_CH3_OVC */ 6106077365a9SGeert Uytterhoeven [ 7] = SH_PFC_PIN_NONE, 6107077365a9SGeert Uytterhoeven [ 8] = SH_PFC_PIN_NONE, 6108077365a9SGeert Uytterhoeven [ 9] = SH_PFC_PIN_NONE, 6109077365a9SGeert Uytterhoeven [10] = SH_PFC_PIN_NONE, 6110077365a9SGeert Uytterhoeven [11] = SH_PFC_PIN_NONE, 6111077365a9SGeert Uytterhoeven [12] = SH_PFC_PIN_NONE, 6112077365a9SGeert Uytterhoeven [13] = SH_PFC_PIN_NONE, 6113077365a9SGeert Uytterhoeven [14] = SH_PFC_PIN_NONE, 6114077365a9SGeert Uytterhoeven [15] = SH_PFC_PIN_NONE, 6115077365a9SGeert Uytterhoeven [16] = SH_PFC_PIN_NONE, 6116077365a9SGeert Uytterhoeven [17] = SH_PFC_PIN_NONE, 6117077365a9SGeert Uytterhoeven [18] = SH_PFC_PIN_NONE, 6118077365a9SGeert Uytterhoeven [19] = SH_PFC_PIN_NONE, 6119077365a9SGeert Uytterhoeven [20] = SH_PFC_PIN_NONE, 6120077365a9SGeert Uytterhoeven [21] = SH_PFC_PIN_NONE, 6121077365a9SGeert Uytterhoeven [22] = SH_PFC_PIN_NONE, 6122077365a9SGeert Uytterhoeven [23] = SH_PFC_PIN_NONE, 6123077365a9SGeert Uytterhoeven [24] = SH_PFC_PIN_NONE, 6124077365a9SGeert Uytterhoeven [25] = SH_PFC_PIN_NONE, 6125077365a9SGeert Uytterhoeven [26] = SH_PFC_PIN_NONE, 6126077365a9SGeert Uytterhoeven [27] = SH_PFC_PIN_NONE, 6127077365a9SGeert Uytterhoeven [28] = SH_PFC_PIN_NONE, 6128077365a9SGeert Uytterhoeven [29] = SH_PFC_PIN_NONE, 6129077365a9SGeert Uytterhoeven [30] = SH_PFC_PIN_NONE, 6130077365a9SGeert Uytterhoeven [31] = SH_PFC_PIN_NONE, 6131077365a9SGeert Uytterhoeven } }, 6132077365a9SGeert Uytterhoeven { /* sentinel */ }, 6133077365a9SGeert Uytterhoeven }; 6134077365a9SGeert Uytterhoeven 6135c614d12cSGeert Uytterhoeven static const struct sh_pfc_soc_operations r8a77951_pfc_ops = { 6136077365a9SGeert Uytterhoeven .pin_to_pocctrl = r8a77951_pin_to_pocctrl, 613727e768a4SGeert Uytterhoeven .get_bias = rcar_pinmux_get_bias, 613827e768a4SGeert Uytterhoeven .set_bias = rcar_pinmux_set_bias, 6139077365a9SGeert Uytterhoeven }; 6140077365a9SGeert Uytterhoeven 6141077365a9SGeert Uytterhoeven #ifdef CONFIG_PINCTRL_PFC_R8A774E1 6142077365a9SGeert Uytterhoeven const struct sh_pfc_soc_info r8a774e1_pinmux_info = { 6143077365a9SGeert Uytterhoeven .name = "r8a774e1_pfc", 6144c614d12cSGeert Uytterhoeven .ops = &r8a77951_pfc_ops, 6145077365a9SGeert Uytterhoeven .unlock_reg = 0xe6060000, /* PMMR */ 6146077365a9SGeert Uytterhoeven 6147077365a9SGeert Uytterhoeven .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 6148077365a9SGeert Uytterhoeven 6149077365a9SGeert Uytterhoeven .pins = pinmux_pins, 6150077365a9SGeert Uytterhoeven .nr_pins = ARRAY_SIZE(pinmux_pins), 6151077365a9SGeert Uytterhoeven .groups = pinmux_groups.common, 6152077365a9SGeert Uytterhoeven .nr_groups = ARRAY_SIZE(pinmux_groups.common), 6153077365a9SGeert Uytterhoeven .functions = pinmux_functions.common, 6154077365a9SGeert Uytterhoeven .nr_functions = ARRAY_SIZE(pinmux_functions.common), 6155077365a9SGeert Uytterhoeven 6156077365a9SGeert Uytterhoeven .cfg_regs = pinmux_config_regs, 6157077365a9SGeert Uytterhoeven .drive_regs = pinmux_drive_regs, 6158077365a9SGeert Uytterhoeven .bias_regs = pinmux_bias_regs, 6159077365a9SGeert Uytterhoeven .ioctrl_regs = pinmux_ioctrl_regs, 6160077365a9SGeert Uytterhoeven 6161077365a9SGeert Uytterhoeven .pinmux_data = pinmux_data, 6162077365a9SGeert Uytterhoeven .pinmux_data_size = ARRAY_SIZE(pinmux_data), 6163077365a9SGeert Uytterhoeven }; 6164077365a9SGeert Uytterhoeven #endif 6165077365a9SGeert Uytterhoeven 6166077365a9SGeert Uytterhoeven #ifdef CONFIG_PINCTRL_PFC_R8A77951 6167077365a9SGeert Uytterhoeven const struct sh_pfc_soc_info r8a77951_pinmux_info = { 6168077365a9SGeert Uytterhoeven .name = "r8a77951_pfc", 6169c614d12cSGeert Uytterhoeven .ops = &r8a77951_pfc_ops, 6170077365a9SGeert Uytterhoeven .unlock_reg = 0xe6060000, /* PMMR */ 6171077365a9SGeert Uytterhoeven 6172077365a9SGeert Uytterhoeven .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 6173077365a9SGeert Uytterhoeven 6174077365a9SGeert Uytterhoeven .pins = pinmux_pins, 6175077365a9SGeert Uytterhoeven .nr_pins = ARRAY_SIZE(pinmux_pins), 6176077365a9SGeert Uytterhoeven .groups = pinmux_groups.common, 6177077365a9SGeert Uytterhoeven .nr_groups = ARRAY_SIZE(pinmux_groups.common) + 6178077365a9SGeert Uytterhoeven ARRAY_SIZE(pinmux_groups.automotive), 6179077365a9SGeert Uytterhoeven .functions = pinmux_functions.common, 6180077365a9SGeert Uytterhoeven .nr_functions = ARRAY_SIZE(pinmux_functions.common) + 6181077365a9SGeert Uytterhoeven ARRAY_SIZE(pinmux_functions.automotive), 6182077365a9SGeert Uytterhoeven 6183077365a9SGeert Uytterhoeven .cfg_regs = pinmux_config_regs, 6184077365a9SGeert Uytterhoeven .drive_regs = pinmux_drive_regs, 6185077365a9SGeert Uytterhoeven .bias_regs = pinmux_bias_regs, 6186077365a9SGeert Uytterhoeven .ioctrl_regs = pinmux_ioctrl_regs, 6187077365a9SGeert Uytterhoeven 6188077365a9SGeert Uytterhoeven .pinmux_data = pinmux_data, 6189077365a9SGeert Uytterhoeven .pinmux_data_size = ARRAY_SIZE(pinmux_data), 6190077365a9SGeert Uytterhoeven }; 6191077365a9SGeert Uytterhoeven #endif 6192