1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * r8a7794/r8a7745 processor support - PFC hardware block. 4 * 5 * Copyright (C) 2014-2015 Renesas Electronics Corporation 6 * Copyright (C) 2015 Renesas Solutions Corp. 7 * Copyright (C) 2015-2017 Cogent Embedded, Inc. <source@cogentembedded.com> 8 */ 9 10 #include <linux/errno.h> 11 #include <linux/kernel.h> 12 #include <linux/sys_soc.h> 13 14 #include "core.h" 15 #include "sh_pfc.h" 16 17 #define CPU_ALL_GP(fn, sfx) \ 18 PORT_GP_CFG_32(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ 19 PORT_GP_CFG_26(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ 20 PORT_GP_CFG_32(2, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ 21 PORT_GP_CFG_32(3, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ 22 PORT_GP_CFG_32(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ 23 PORT_GP_CFG_7(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ 24 PORT_GP_1(5, 7, fn, sfx), \ 25 PORT_GP_1(5, 8, fn, sfx), \ 26 PORT_GP_1(5, 9, fn, sfx), \ 27 PORT_GP_CFG_1(5, 10, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ 28 PORT_GP_CFG_1(5, 11, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ 29 PORT_GP_CFG_1(5, 12, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ 30 PORT_GP_CFG_1(5, 13, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ 31 PORT_GP_CFG_1(5, 14, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ 32 PORT_GP_CFG_1(5, 15, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ 33 PORT_GP_CFG_1(5, 16, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ 34 PORT_GP_CFG_1(5, 17, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ 35 PORT_GP_CFG_1(5, 18, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ 36 PORT_GP_CFG_1(5, 19, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ 37 PORT_GP_CFG_1(5, 20, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ 38 PORT_GP_CFG_1(5, 21, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ 39 PORT_GP_CFG_1(5, 22, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ 40 PORT_GP_CFG_1(5, 23, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ 41 PORT_GP_1(5, 24, fn, sfx), \ 42 PORT_GP_1(5, 25, fn, sfx), \ 43 PORT_GP_1(5, 26, fn, sfx), \ 44 PORT_GP_1(5, 27, fn, sfx), \ 45 PORT_GP_CFG_1(6, 0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ 46 PORT_GP_CFG_1(6, 1, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ 47 PORT_GP_CFG_1(6, 2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ 48 PORT_GP_CFG_1(6, 3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ 49 PORT_GP_CFG_1(6, 4, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ 50 PORT_GP_CFG_1(6, 5, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ 51 PORT_GP_CFG_1(6, 6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ 52 PORT_GP_CFG_1(6, 7, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ 53 PORT_GP_CFG_1(6, 8, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ 54 PORT_GP_CFG_1(6, 9, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ 55 PORT_GP_CFG_1(6, 10, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ 56 PORT_GP_CFG_1(6, 11, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ 57 PORT_GP_CFG_1(6, 12, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ 58 PORT_GP_CFG_1(6, 13, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ 59 PORT_GP_CFG_1(6, 14, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ 60 PORT_GP_CFG_1(6, 15, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ 61 PORT_GP_CFG_1(6, 16, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ 62 PORT_GP_CFG_1(6, 17, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ 63 PORT_GP_CFG_1(6, 18, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ 64 PORT_GP_CFG_1(6, 19, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ 65 PORT_GP_CFG_1(6, 20, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ 66 PORT_GP_CFG_1(6, 21, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ 67 PORT_GP_CFG_1(6, 22, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ 68 PORT_GP_CFG_1(6, 23, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ 69 PORT_GP_CFG_1(6, 24, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ 70 PORT_GP_CFG_1(6, 25, fn, sfx, SH_PFC_PIN_CFG_PULL_UP) 71 72 #define CPU_ALL_NOGP(fn) \ 73 PIN_NOGP_CFG(ASEBRK_N_ACK, "ASEBRK#/ACK", fn, SH_PFC_PIN_CFG_PULL_DOWN), \ 74 PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP), \ 75 PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP), \ 76 PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP), \ 77 PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP) 78 79 enum { 80 PINMUX_RESERVED = 0, 81 82 PINMUX_DATA_BEGIN, 83 GP_ALL(DATA), 84 PINMUX_DATA_END, 85 86 PINMUX_FUNCTION_BEGIN, 87 GP_ALL(FN), 88 89 /* GPSR0 */ 90 FN_IP0_23_22, FN_IP0_24, FN_IP0_25, FN_IP0_27_26, FN_IP0_29_28, 91 FN_IP0_31_30, FN_IP1_1_0, FN_IP1_3_2, FN_IP1_5_4, FN_IP1_7_6, 92 FN_IP1_10_8, FN_IP1_12_11, FN_IP1_14_13, FN_IP1_17_15, FN_IP1_19_18, 93 FN_IP1_21_20, FN_IP1_23_22, FN_IP1_24, FN_A2, FN_IP1_26, FN_IP1_27, 94 FN_IP1_29_28, FN_IP1_31_30, FN_IP2_1_0, FN_IP2_3_2, FN_IP2_5_4, 95 FN_IP2_7_6, FN_IP2_9_8, FN_IP2_11_10, FN_IP2_13_12, FN_IP2_15_14, 96 FN_IP2_17_16, 97 98 /* GPSR1 */ 99 FN_IP2_20_18, FN_IP2_23_21, FN_IP2_26_24, FN_IP2_29_27, FN_IP2_31_30, 100 FN_IP3_1_0, FN_IP3_3_2, FN_IP3_5_4, FN_IP3_7_6, FN_IP3_9_8, FN_IP3_10, 101 FN_IP3_11, FN_IP3_12, FN_IP3_14_13, FN_IP3_17_15, FN_IP3_20_18, 102 FN_IP3_23_21, FN_IP3_26_24, FN_IP3_29_27, FN_IP3_30, FN_IP3_31, 103 FN_WE0_N, FN_WE1_N, FN_IP4_1_0 , FN_IP7_31, FN_DACK0, 104 105 /* GPSR2 */ 106 FN_IP4_4_2, FN_IP4_7_5, FN_IP4_9_8, FN_IP4_11_10, FN_IP4_13_12, 107 FN_IP4_15_14, FN_IP4_17_16, FN_IP4_19_18, FN_IP4_22_20, FN_IP4_25_23, 108 FN_IP4_27_26, FN_IP4_29_28, FN_IP4_31_30, FN_IP5_1_0, FN_IP5_3_2, 109 FN_IP5_5_4, FN_IP5_8_6, FN_IP5_11_9, FN_IP5_13_12, FN_IP5_15_14, 110 FN_IP5_17_16, FN_IP5_19_18, FN_IP5_21_20, FN_IP5_23_22, FN_IP5_25_24, 111 FN_IP5_27_26, FN_IP5_29_28, FN_IP5_31_30, FN_IP6_1_0, FN_IP6_3_2, 112 FN_IP6_5_4, FN_IP6_7_6, 113 114 /* GPSR3 */ 115 FN_IP6_8, FN_IP6_9, FN_IP6_10, FN_IP6_11, FN_IP6_12, FN_IP6_13, 116 FN_IP6_14, FN_IP6_15, FN_IP6_16, FN_IP6_19_17, FN_IP6_22_20, 117 FN_IP6_25_23, FN_IP6_28_26, FN_IP6_31_29, FN_IP7_2_0, FN_IP7_5_3, 118 FN_IP7_8_6, FN_IP7_11_9, FN_IP7_14_12, FN_IP7_17_15, FN_IP7_20_18, 119 FN_IP7_23_21, FN_IP7_26_24, FN_IP7_29_27, FN_IP8_2_0, FN_IP8_5_3, 120 FN_IP8_8_6, FN_IP8_11_9, FN_IP8_14_12, FN_IP8_16_15, FN_IP8_19_17, 121 FN_IP8_22_20, 122 123 /* GPSR4 */ 124 FN_IP8_25_23, FN_IP8_28_26, FN_IP8_31_29, FN_IP9_2_0, FN_IP9_5_3, 125 FN_IP9_8_6, FN_IP9_11_9, FN_IP9_14_12, FN_IP9_16_15, FN_IP9_18_17, 126 FN_IP9_21_19, FN_IP9_24_22, FN_IP9_27_25, FN_IP9_30_28, FN_IP10_2_0, 127 FN_IP10_5_3, FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_17_15, 128 FN_IP10_20_18, FN_IP10_23_21, FN_IP10_26_24, FN_IP10_29_27, 129 FN_IP10_31_30, FN_IP11_2_0, FN_IP11_5_3, FN_IP11_7_6, FN_IP11_10_8, 130 FN_IP11_13_11, FN_IP11_15_14, FN_IP11_17_16, 131 132 /* GPSR5 */ 133 FN_IP11_20_18, FN_IP11_23_21, FN_IP11_26_24, FN_IP11_29_27, FN_IP12_2_0, 134 FN_IP12_5_3, FN_IP12_8_6, FN_IP12_10_9, FN_IP12_12_11, FN_IP12_14_13, 135 FN_IP12_17_15, FN_IP12_20_18, FN_IP12_23_21, FN_IP12_26_24, 136 FN_IP12_29_27, FN_IP13_2_0, FN_IP13_5_3, FN_IP13_8_6, FN_IP13_11_9, 137 FN_IP13_14_12, FN_IP13_17_15, FN_IP13_20_18, FN_IP13_23_21, 138 FN_IP13_26_24, FN_USB0_PWEN, FN_USB0_OVC, FN_USB1_PWEN, FN_USB1_OVC, 139 140 /* GPSR6 */ 141 FN_SD0_CLK, FN_SD0_CMD, FN_SD0_DATA0, FN_SD0_DATA1, FN_SD0_DATA2, 142 FN_SD0_DATA3, FN_SD0_CD, FN_SD0_WP, FN_SD1_CLK, FN_SD1_CMD, 143 FN_SD1_DATA0, FN_SD1_DATA1, FN_SD1_DATA2, FN_SD1_DATA3, FN_IP0_0, 144 FN_IP0_9_8, FN_IP0_10, FN_IP0_11, FN_IP0_12, FN_IP0_13, FN_IP0_14, 145 FN_IP0_15, FN_IP0_16, FN_IP0_17, FN_IP0_19_18, FN_IP0_21_20, 146 147 /* IPSR0 */ 148 FN_SD1_CD, FN_CAN0_RX, FN_SD1_WP, FN_IRQ7, FN_CAN0_TX, FN_MMC_CLK, 149 FN_SD2_CLK, FN_MMC_CMD, FN_SD2_CMD, FN_MMC_D0, FN_SD2_DATA0, FN_MMC_D1, 150 FN_SD2_DATA1, FN_MMC_D2, FN_SD2_DATA2, FN_MMC_D3, FN_SD2_DATA3, 151 FN_MMC_D4, FN_SD2_CD, FN_MMC_D5, FN_SD2_WP, FN_MMC_D6, FN_SCIF0_RXD, 152 FN_I2C2_SCL_B, FN_CAN1_RX, FN_MMC_D7, FN_SCIF0_TXD, FN_I2C2_SDA_B, 153 FN_CAN1_TX, FN_D0, FN_SCIFA3_SCK_B, FN_IRQ4, FN_D1, FN_SCIFA3_RXD_B, 154 FN_D2, FN_SCIFA3_TXD_B, FN_D3, FN_I2C3_SCL_B, FN_SCIF5_RXD_B, FN_D4, 155 FN_I2C3_SDA_B, FN_SCIF5_TXD_B, FN_D5, FN_SCIF4_RXD_B, FN_I2C0_SCL_D, 156 157 /* IPSR1 */ 158 FN_D6, FN_SCIF4_TXD_B, FN_I2C0_SDA_D, 159 FN_D7, FN_IRQ3, FN_TCLK1, FN_PWM6_B, 160 FN_D8, FN_HSCIF2_HRX, FN_I2C1_SCL_B, 161 FN_D9, FN_HSCIF2_HTX, FN_I2C1_SDA_B, 162 FN_D10, FN_HSCIF2_HSCK, FN_SCIF1_SCK_C, FN_IRQ6, FN_PWM5_C, 163 FN_D11, FN_HSCIF2_HCTS_N, FN_SCIF1_RXD_C, FN_I2C1_SCL_D, 164 FN_D12, FN_HSCIF2_HRTS_N, FN_SCIF1_TXD_C, FN_I2C1_SDA_D, 165 FN_D13, FN_SCIFA1_SCK, FN_PWM2_C, FN_TCLK2_B, 166 FN_D14, FN_SCIFA1_RXD, FN_I2C5_SCL_B, 167 FN_D15, FN_SCIFA1_TXD, FN_I2C5_SDA_B, 168 FN_A0, FN_SCIFB1_SCK, FN_PWM3_B, 169 FN_A1, FN_SCIFB1_TXD, 170 FN_A3, FN_SCIFB0_SCK, 171 FN_A4, FN_SCIFB0_TXD, 172 FN_A5, FN_SCIFB0_RXD, FN_PWM4_B, FN_TPUTO3_C, 173 FN_A6, FN_SCIFB0_CTS_N, FN_SCIFA4_RXD_B, FN_TPUTO2_C, 174 175 /* IPSR2 */ 176 FN_A7, FN_SCIFB0_RTS_N, FN_SCIFA4_TXD_B, 177 FN_A8, FN_MSIOF1_RXD, FN_SCIFA0_RXD_B, 178 FN_A9, FN_MSIOF1_TXD, FN_SCIFA0_TXD_B, 179 FN_A10, FN_MSIOF1_SCK, FN_IIC0_SCL_B, 180 FN_A11, FN_MSIOF1_SYNC, FN_IIC0_SDA_B, 181 FN_A12, FN_MSIOF1_SS1, FN_SCIFA5_RXD_B, 182 FN_A13, FN_MSIOF1_SS2, FN_SCIFA5_TXD_B, 183 FN_A14, FN_MSIOF2_RXD, FN_HSCIF0_HRX_B, FN_DREQ1_N, 184 FN_A15, FN_MSIOF2_TXD, FN_HSCIF0_HTX_B, FN_DACK1, 185 FN_A16, FN_MSIOF2_SCK, FN_HSCIF0_HSCK_B, FN_SPEEDIN, FN_CAN_CLK_C, 186 FN_TPUTO2_B, 187 FN_A17, FN_MSIOF2_SYNC, FN_SCIF4_RXD_E, FN_CAN1_RX_B, 188 FN_A18, FN_MSIOF2_SS1, FN_SCIF4_TXD_E, FN_CAN1_TX_B, 189 FN_A19, FN_MSIOF2_SS2, FN_PWM4, FN_TPUTO2, 190 FN_A20, FN_SPCLK, 191 192 /* IPSR3 */ 193 FN_A21, FN_MOSI_IO0, 194 FN_A22, FN_MISO_IO1, FN_ATADIR1_N, 195 FN_A23, FN_IO2, FN_ATAWR1_N, 196 FN_A24, FN_IO3, FN_EX_WAIT2, 197 FN_A25, FN_SSL, FN_ATARD1_N, 198 FN_CS0_N, FN_VI1_DATA8, 199 FN_CS1_N_A26, FN_VI1_DATA9, 200 FN_EX_CS0_N, FN_VI1_DATA10, 201 FN_EX_CS1_N, FN_TPUTO3_B, FN_SCIFB2_RXD, FN_VI1_DATA11, 202 FN_EX_CS2_N, FN_PWM0, FN_SCIF4_RXD_C, FN_TS_SDATA_B, FN_TPUTO3, 203 FN_SCIFB2_TXD, 204 FN_EX_CS3_N, FN_SCIFA2_SCK, FN_SCIF4_TXD_C, FN_TS_SCK_B, FN_BPFCLK, 205 FN_SCIFB2_SCK, 206 FN_EX_CS4_N, FN_SCIFA2_RXD, FN_I2C2_SCL_E, FN_TS_SDEN_B, FN_FMCLK, 207 FN_SCIFB2_CTS_N, 208 FN_EX_CS5_N, FN_SCIFA2_TXD, FN_I2C2_SDA_E, FN_TS_SPSYNC_B, FN_FMIN, 209 FN_SCIFB2_RTS_N, 210 FN_BS_N, FN_DRACK0, FN_PWM1_C, FN_TPUTO0_C, FN_ATACS01_N, 211 FN_RD_N, FN_ATACS11_N, 212 FN_RD_WR_N, FN_ATAG1_N, 213 214 /* IPSR4 */ 215 FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK, 216 FN_DU0_DR0, FN_LCDOUT16, FN_SCIF5_RXD_C, FN_I2C2_SCL_D, 217 FN_DU0_DR1, FN_LCDOUT17, FN_SCIF5_TXD_C, FN_I2C2_SDA_D, 218 FN_DU0_DR2, FN_LCDOUT18, 219 FN_DU0_DR3, FN_LCDOUT19, 220 FN_DU0_DR4, FN_LCDOUT20, 221 FN_DU0_DR5, FN_LCDOUT21, 222 FN_DU0_DR6, FN_LCDOUT22, 223 FN_DU0_DR7, FN_LCDOUT23, 224 FN_DU0_DG0, FN_LCDOUT8, FN_SCIFA0_RXD_C, FN_I2C3_SCL_D, 225 FN_DU0_DG1, FN_LCDOUT9, FN_SCIFA0_TXD_C, FN_I2C3_SDA_D, 226 FN_DU0_DG2, FN_LCDOUT10, 227 FN_DU0_DG3, FN_LCDOUT11, 228 FN_DU0_DG4, FN_LCDOUT12, 229 230 /* IPSR5 */ 231 FN_DU0_DG5, FN_LCDOUT13, 232 FN_DU0_DG6, FN_LCDOUT14, 233 FN_DU0_DG7, FN_LCDOUT15, 234 FN_DU0_DB0, FN_LCDOUT0, FN_SCIFA4_RXD_C, FN_I2C4_SCL_D, FN_CAN0_RX_C, 235 FN_DU0_DB1, FN_LCDOUT1, FN_SCIFA4_TXD_C, FN_I2C4_SDA_D, FN_CAN0_TX_C, 236 FN_DU0_DB2, FN_LCDOUT2, 237 FN_DU0_DB3, FN_LCDOUT3, 238 FN_DU0_DB4, FN_LCDOUT4, 239 FN_DU0_DB5, FN_LCDOUT5, 240 FN_DU0_DB6, FN_LCDOUT6, 241 FN_DU0_DB7, FN_LCDOUT7, 242 FN_DU0_DOTCLKIN, FN_QSTVA_QVS, 243 FN_DU0_DOTCLKOUT0, FN_QCLK, 244 FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE, 245 FN_DU0_EXHSYNC_DU0_HSYNC, FN_QSTH_QHS, 246 247 /* IPSR6 */ 248 FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, 249 FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, 250 FN_DU0_DISP, FN_QPOLA, 251 FN_DU0_CDE, FN_QPOLB, 252 FN_VI0_CLK, FN_AVB_RX_CLK, 253 FN_VI0_DATA0_VI0_B0, FN_AVB_RX_DV, 254 FN_VI0_DATA1_VI0_B1, FN_AVB_RXD0, 255 FN_VI0_DATA2_VI0_B2, FN_AVB_RXD1, 256 FN_VI0_DATA3_VI0_B3, FN_AVB_RXD2, 257 FN_VI0_DATA4_VI0_B4, FN_AVB_RXD3, 258 FN_VI0_DATA5_VI0_B5, FN_AVB_RXD4, 259 FN_VI0_DATA6_VI0_B6, FN_AVB_RXD5, 260 FN_VI0_DATA7_VI0_B7, FN_AVB_RXD6, 261 FN_VI0_CLKENB, FN_I2C3_SCL, FN_SCIFA5_RXD_C, FN_IETX_C, FN_AVB_RXD7, 262 FN_VI0_FIELD, FN_I2C3_SDA, FN_SCIFA5_TXD_C, FN_IECLK_C, FN_AVB_RX_ER, 263 FN_VI0_HSYNC_N, FN_SCIF0_RXD_B, FN_I2C0_SCL_C, FN_IERX_C, FN_AVB_COL, 264 FN_VI0_VSYNC_N, FN_SCIF0_TXD_B, FN_I2C0_SDA_C, FN_AUDIO_CLKOUT_B, 265 FN_AVB_TX_EN, 266 FN_ETH_MDIO, FN_VI0_G0, FN_MSIOF2_RXD_B, FN_I2C5_SCL_D, FN_AVB_TX_CLK, 267 FN_ADIDATA, 268 269 /* IPSR7 */ 270 FN_ETH_CRS_DV, FN_VI0_G1, FN_MSIOF2_TXD_B, FN_I2C5_SDA_D, FN_AVB_TXD0, 271 FN_ADICS_SAMP, 272 FN_ETH_RX_ER, FN_VI0_G2, FN_MSIOF2_SCK_B, FN_CAN0_RX_B, FN_AVB_TXD1, 273 FN_ADICLK, 274 FN_ETH_RXD0, FN_VI0_G3, FN_MSIOF2_SYNC_B, FN_CAN0_TX_B, FN_AVB_TXD2, 275 FN_ADICHS0, 276 FN_ETH_RXD1, FN_VI0_G4, FN_MSIOF2_SS1_B, FN_SCIF4_RXD_D, FN_AVB_TXD3, 277 FN_ADICHS1, 278 FN_ETH_LINK, FN_VI0_G5, FN_MSIOF2_SS2_B, FN_SCIF4_TXD_D, FN_AVB_TXD4, 279 FN_ADICHS2, 280 FN_ETH_REFCLK, FN_VI0_G6, FN_SCIF2_SCK_C, FN_AVB_TXD5, FN_SSI_SCK5_B, 281 FN_ETH_TXD1, FN_VI0_G7, FN_SCIF2_RXD_C, FN_IIC0_SCL_D, FN_AVB_TXD6, 282 FN_SSI_WS5_B, 283 FN_ETH_TX_EN, FN_VI0_R0, FN_SCIF2_TXD_C, FN_IIC0_SDA_D, FN_AVB_TXD7, 284 FN_SSI_SDATA5_B, 285 FN_ETH_MAGIC, FN_VI0_R1, FN_SCIF3_SCK_B, FN_AVB_TX_ER, FN_SSI_SCK6_B, 286 FN_ETH_TXD0, FN_VI0_R2, FN_SCIF3_RXD_B, FN_I2C4_SCL_E, FN_AVB_GTX_CLK, 287 FN_SSI_WS6_B, 288 FN_DREQ0_N, FN_SCIFB1_RXD, 289 290 /* IPSR8 */ 291 FN_ETH_MDC, FN_VI0_R3, FN_SCIF3_TXD_B, FN_I2C4_SDA_E, FN_AVB_MDC, 292 FN_SSI_SDATA6_B, 293 FN_HSCIF0_HRX, FN_VI0_R4, FN_I2C1_SCL_C, FN_AUDIO_CLKA_B, FN_AVB_MDIO, 294 FN_SSI_SCK78_B, 295 FN_HSCIF0_HTX, FN_VI0_R5, FN_I2C1_SDA_C, FN_AUDIO_CLKB_B, FN_AVB_LINK, 296 FN_SSI_WS78_B, 297 FN_HSCIF0_HCTS_N, FN_VI0_R6, FN_SCIF0_RXD_D, FN_I2C0_SCL_E, 298 FN_AVB_MAGIC, FN_SSI_SDATA7_B, 299 FN_HSCIF0_HRTS_N, FN_VI0_R7, FN_SCIF0_TXD_D, FN_I2C0_SDA_E, 300 FN_AVB_PHY_INT, FN_SSI_SDATA8_B, 301 FN_HSCIF0_HSCK, FN_SCIF_CLK_B, FN_AVB_CRS, FN_AUDIO_CLKC_B, 302 FN_I2C0_SCL, FN_SCIF0_RXD_C, FN_PWM5, FN_TCLK1_B, FN_AVB_GTXREFCLK, 303 FN_CAN1_RX_D, FN_TPUTO0_B, 304 FN_I2C0_SDA, FN_SCIF0_TXD_C, FN_TPUTO0, FN_CAN_CLK, FN_DVC_MUTE, 305 FN_CAN1_TX_D, 306 FN_I2C1_SCL, FN_SCIF4_RXD, FN_PWM5_B, FN_DU1_DR0, FN_TS_SDATA_D, 307 FN_TPUTO1_B, 308 FN_I2C1_SDA, FN_SCIF4_TXD, FN_IRQ5, FN_DU1_DR1, FN_TS_SCK_D, 309 FN_BPFCLK_C, 310 FN_MSIOF0_RXD, FN_SCIF5_RXD, FN_I2C2_SCL_C, FN_DU1_DR2, FN_TS_SDEN_D, 311 FN_FMCLK_C, 312 313 /* IPSR9 */ 314 FN_MSIOF0_TXD, FN_SCIF5_TXD, FN_I2C2_SDA_C, FN_DU1_DR3, FN_TS_SPSYNC_D, 315 FN_FMIN_C, 316 FN_MSIOF0_SCK, FN_IRQ0, FN_TS_SDATA, FN_DU1_DR4, FN_TPUTO1_C, 317 FN_MSIOF0_SYNC, FN_PWM1, FN_TS_SCK, FN_DU1_DR5, FN_BPFCLK_B, 318 FN_MSIOF0_SS1, FN_SCIFA0_RXD, FN_TS_SDEN, FN_DU1_DR6, FN_FMCLK_B, 319 FN_MSIOF0_SS2, FN_SCIFA0_TXD, FN_TS_SPSYNC, FN_DU1_DR7, FN_FMIN_B, 320 FN_HSCIF1_HRX, FN_I2C4_SCL, FN_PWM6, FN_DU1_DG0, 321 FN_HSCIF1_HTX, FN_I2C4_SDA, FN_TPUTO1, FN_DU1_DG1, 322 FN_HSCIF1_HSCK, FN_PWM2, FN_IETX, FN_DU1_DG2, FN_REMOCON_B, 323 FN_SPEEDIN_B, 324 FN_HSCIF1_HCTS_N, FN_SCIFA4_RXD, FN_IECLK, FN_DU1_DG3, FN_SSI_SCK1_B, 325 FN_HSCIF1_HRTS_N, FN_SCIFA4_TXD, FN_IERX, FN_DU1_DG4, FN_SSI_WS1_B, 326 FN_SCIF1_SCK, FN_PWM3, FN_TCLK2, FN_DU1_DG5, FN_SSI_SDATA1_B, 327 328 /* IPSR10 */ 329 FN_SCIF1_RXD, FN_I2C5_SCL, FN_DU1_DG6, FN_SSI_SCK2_B, 330 FN_SCIF1_TXD, FN_I2C5_SDA, FN_DU1_DG7, FN_SSI_WS2_B, 331 FN_SCIF2_RXD, FN_IIC0_SCL, FN_DU1_DB0, FN_SSI_SDATA2_B, 332 FN_SCIF2_TXD, FN_IIC0_SDA, FN_DU1_DB1, FN_SSI_SCK9_B, 333 FN_SCIF2_SCK, FN_IRQ1, FN_DU1_DB2, FN_SSI_WS9_B, 334 FN_SCIF3_SCK, FN_IRQ2, FN_BPFCLK_D, FN_DU1_DB3, FN_SSI_SDATA9_B, 335 FN_SCIF3_RXD, FN_I2C1_SCL_E, FN_FMCLK_D, FN_DU1_DB4, FN_AUDIO_CLKA_C, 336 FN_SSI_SCK4_B, 337 FN_SCIF3_TXD, FN_I2C1_SDA_E, FN_FMIN_D, FN_DU1_DB5, FN_AUDIO_CLKB_C, 338 FN_SSI_WS4_B, 339 FN_I2C2_SCL, FN_SCIFA5_RXD, FN_DU1_DB6, FN_AUDIO_CLKC_C, 340 FN_SSI_SDATA4_B, 341 FN_I2C2_SDA, FN_SCIFA5_TXD, FN_DU1_DB7, FN_AUDIO_CLKOUT_C, 342 FN_SSI_SCK5, FN_SCIFA3_SCK, FN_DU1_DOTCLKIN, 343 344 /* IPSR11 */ 345 FN_SSI_WS5, FN_SCIFA3_RXD, FN_I2C3_SCL_C, FN_DU1_DOTCLKOUT0, 346 FN_SSI_SDATA5, FN_SCIFA3_TXD, FN_I2C3_SDA_C, FN_DU1_DOTCLKOUT1, 347 FN_SSI_SCK6, FN_SCIFA1_SCK_B, FN_DU1_EXHSYNC_DU1_HSYNC, 348 FN_SSI_WS6, FN_SCIFA1_RXD_B, FN_I2C4_SCL_C, FN_DU1_EXVSYNC_DU1_VSYNC, 349 FN_SSI_SDATA6, FN_SCIFA1_TXD_B, FN_I2C4_SDA_C, 350 FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, 351 FN_SSI_SCK78, FN_SCIFA2_SCK_B, FN_I2C5_SDA_C, FN_DU1_DISP, 352 FN_SSI_WS78, FN_SCIFA2_RXD_B, FN_I2C5_SCL_C, FN_DU1_CDE, 353 FN_SSI_SDATA7, FN_SCIFA2_TXD_B, FN_IRQ8, FN_AUDIO_CLKA_D, FN_CAN_CLK_D, 354 FN_SSI_SCK0129, FN_MSIOF1_RXD_B, FN_SCIF5_RXD_D, FN_ADIDATA_B, 355 FN_SSI_WS0129, FN_MSIOF1_TXD_B, FN_SCIF5_TXD_D, FN_ADICS_SAMP_B, 356 FN_SSI_SDATA0, FN_MSIOF1_SCK_B, FN_PWM0_B, FN_ADICLK_B, 357 358 /* IPSR12 */ 359 FN_SSI_SCK34, FN_MSIOF1_SYNC_B, FN_SCIFA1_SCK_C, FN_ADICHS0_B, 360 FN_DREQ1_N_B, 361 FN_SSI_WS34, FN_MSIOF1_SS1_B, FN_SCIFA1_RXD_C, FN_ADICHS1_B, 362 FN_CAN1_RX_C, FN_DACK1_B, 363 FN_SSI_SDATA3, FN_MSIOF1_SS2_B, FN_SCIFA1_TXD_C, FN_ADICHS2_B, 364 FN_CAN1_TX_C, FN_DREQ2_N, 365 FN_SSI_SCK4, FN_MLB_CLK, FN_IETX_B, FN_SSI_WS4, FN_MLB_SIG, FN_IECLK_B, 366 FN_SSI_SDATA4, FN_MLB_DAT, FN_IERX_B, 367 FN_SSI_SDATA8, FN_SCIF1_SCK_B, FN_PWM1_B, FN_IRQ9, FN_REMOCON, 368 FN_DACK2, FN_ETH_MDIO_B, 369 FN_SSI_SCK1, FN_SCIF1_RXD_B, FN_IIC0_SCL_C, FN_VI1_CLK, FN_CAN0_RX_D, 370 FN_ETH_CRS_DV_B, 371 FN_SSI_WS1, FN_SCIF1_TXD_B, FN_IIC0_SDA_C, FN_VI1_DATA0, FN_CAN0_TX_D, 372 FN_ETH_RX_ER_B, 373 FN_SSI_SDATA1, FN_HSCIF1_HRX_B, FN_VI1_DATA1, FN_ATAWR0_N, 374 FN_ETH_RXD0_B, 375 FN_SSI_SCK2, FN_HSCIF1_HTX_B, FN_VI1_DATA2, FN_ATAG0_N, FN_ETH_RXD1_B, 376 377 /* IPSR13 */ 378 FN_SSI_WS2, FN_HSCIF1_HCTS_N_B, FN_SCIFA0_RXD_D, FN_VI1_DATA3, 379 FN_ATACS00_N, FN_ETH_LINK_B, 380 FN_SSI_SDATA2, FN_HSCIF1_HRTS_N_B, FN_SCIFA0_TXD_D, FN_VI1_DATA4, 381 FN_ATACS10_N, FN_ETH_REFCLK_B, 382 FN_SSI_SCK9, FN_SCIF2_SCK_B, FN_PWM2_B, FN_VI1_DATA5, FN_EX_WAIT1, 383 FN_ETH_TXD1_B, 384 FN_SSI_WS9, FN_SCIF2_RXD_B, FN_I2C3_SCL_E, FN_VI1_DATA6, FN_ATARD0_N, 385 FN_ETH_TX_EN_B, 386 FN_SSI_SDATA9, FN_SCIF2_TXD_B, FN_I2C3_SDA_E, FN_VI1_DATA7, 387 FN_ATADIR0_N, FN_ETH_MAGIC_B, 388 FN_AUDIO_CLKA, FN_I2C0_SCL_B, FN_SCIFA4_RXD_D, FN_VI1_CLKENB, 389 FN_TS_SDATA_C, FN_ETH_TXD0_B, 390 FN_AUDIO_CLKB, FN_I2C0_SDA_B, FN_SCIFA4_TXD_D, FN_VI1_FIELD, 391 FN_TS_SCK_C, FN_BPFCLK_E, FN_ETH_MDC_B, 392 FN_AUDIO_CLKC, FN_I2C4_SCL_B, FN_SCIFA5_RXD_D, FN_VI1_HSYNC_N, 393 FN_TS_SDEN_C, FN_FMCLK_E, 394 FN_AUDIO_CLKOUT, FN_I2C4_SDA_B, FN_SCIFA5_TXD_D, FN_VI1_VSYNC_N, 395 FN_TS_SPSYNC_C, FN_FMIN_E, 396 397 /* MOD_SEL */ 398 FN_SEL_ADG_0, FN_SEL_ADG_1, FN_SEL_ADG_2, FN_SEL_ADG_3, 399 FN_SEL_CAN_0, FN_SEL_CAN_1, FN_SEL_CAN_2, FN_SEL_CAN_3, 400 FN_SEL_DARC_0, FN_SEL_DARC_1, FN_SEL_DARC_2, FN_SEL_DARC_3, 401 FN_SEL_DARC_4, 402 FN_SEL_ETH_0, FN_SEL_ETH_1, 403 FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2, FN_SEL_I2C00_3, 404 FN_SEL_I2C00_4, 405 FN_SEL_I2C01_0, FN_SEL_I2C01_1, FN_SEL_I2C01_2, FN_SEL_I2C01_3, 406 FN_SEL_I2C01_4, 407 FN_SEL_I2C02_0, FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3, 408 FN_SEL_I2C02_4, 409 FN_SEL_I2C03_0, FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3, 410 FN_SEL_I2C03_4, 411 FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2, FN_SEL_I2C04_3, 412 FN_SEL_I2C04_4, 413 FN_SEL_I2C05_0, FN_SEL_I2C05_1, FN_SEL_I2C05_2, FN_SEL_I2C05_3, 414 415 /* MOD_SEL2 */ 416 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 417 FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, FN_SEL_IIC0_3, 418 FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_MSI1_0, FN_SEL_MSI1_1, 419 FN_SEL_MSI2_0, FN_SEL_MSI2_1, FN_SEL_RAD_0, FN_SEL_RAD_1, 420 FN_SEL_RCN_0, FN_SEL_RCN_1, FN_SEL_RSP_0, FN_SEL_RSP_1, 421 FN_SEL_SCIFA0_0, FN_SEL_SCIFA0_1, FN_SEL_SCIFA0_2, FN_SEL_SCIFA0_3, 422 FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, 423 FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, 424 FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2, FN_SEL_SCIFA4_3, 425 FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, FN_SEL_SCIFA5_3, 426 FN_SEL_TMU_0, FN_SEL_TMU_1, 427 FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, 428 FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3, 429 FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3, 430 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, 431 432 /* MOD_SEL3 */ 433 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3, 434 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF2_0, 435 FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, 436 FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3, 437 FN_SEL_SCIF4_4, FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, 438 FN_SEL_SCIF5_3, FN_SEL_SSI1_0, FN_SEL_SSI1_1, FN_SEL_SSI2_0, 439 FN_SEL_SSI2_1, FN_SEL_SSI4_0, FN_SEL_SSI4_1, FN_SEL_SSI5_0, 440 FN_SEL_SSI5_1, FN_SEL_SSI6_0, FN_SEL_SSI6_1, FN_SEL_SSI7_0, 441 FN_SEL_SSI7_1, FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI9_0, 442 FN_SEL_SSI9_1, 443 PINMUX_FUNCTION_END, 444 445 PINMUX_MARK_BEGIN, 446 A2_MARK, WE0_N_MARK, WE1_N_MARK, DACK0_MARK, 447 448 USB0_PWEN_MARK, USB0_OVC_MARK, USB1_PWEN_MARK, USB1_OVC_MARK, 449 450 SD0_CLK_MARK, SD0_CMD_MARK, SD0_DATA0_MARK, SD0_DATA1_MARK, 451 SD0_DATA2_MARK, SD0_DATA3_MARK, SD0_CD_MARK, SD0_WP_MARK, 452 453 SD1_CLK_MARK, SD1_CMD_MARK, SD1_DATA0_MARK, SD1_DATA1_MARK, 454 SD1_DATA2_MARK, SD1_DATA3_MARK, 455 456 /* IPSR0 */ 457 SD1_CD_MARK, CAN0_RX_MARK, SD1_WP_MARK, IRQ7_MARK, CAN0_TX_MARK, 458 MMC_CLK_MARK, SD2_CLK_MARK, MMC_CMD_MARK, SD2_CMD_MARK, MMC_D0_MARK, 459 SD2_DATA0_MARK, MMC_D1_MARK, SD2_DATA1_MARK, MMC_D2_MARK, 460 SD2_DATA2_MARK, MMC_D3_MARK, SD2_DATA3_MARK, MMC_D4_MARK, SD2_CD_MARK, 461 MMC_D5_MARK, SD2_WP_MARK, MMC_D6_MARK, SCIF0_RXD_MARK, I2C2_SCL_B_MARK, 462 CAN1_RX_MARK, MMC_D7_MARK, SCIF0_TXD_MARK, I2C2_SDA_B_MARK, 463 CAN1_TX_MARK, D0_MARK, SCIFA3_SCK_B_MARK, IRQ4_MARK, D1_MARK, 464 SCIFA3_RXD_B_MARK, D2_MARK, SCIFA3_TXD_B_MARK, D3_MARK, I2C3_SCL_B_MARK, 465 SCIF5_RXD_B_MARK, D4_MARK, I2C3_SDA_B_MARK, SCIF5_TXD_B_MARK, D5_MARK, 466 SCIF4_RXD_B_MARK, I2C0_SCL_D_MARK, 467 468 /* IPSR1 */ 469 D6_MARK, SCIF4_TXD_B_MARK, I2C0_SDA_D_MARK, 470 D7_MARK, IRQ3_MARK, TCLK1_MARK, PWM6_B_MARK, 471 D8_MARK, HSCIF2_HRX_MARK, I2C1_SCL_B_MARK, 472 D9_MARK, HSCIF2_HTX_MARK, I2C1_SDA_B_MARK, 473 D10_MARK, HSCIF2_HSCK_MARK, SCIF1_SCK_C_MARK, IRQ6_MARK, PWM5_C_MARK, 474 D11_MARK, HSCIF2_HCTS_N_MARK, SCIF1_RXD_C_MARK, I2C1_SCL_D_MARK, 475 D12_MARK, HSCIF2_HRTS_N_MARK, SCIF1_TXD_C_MARK, I2C1_SDA_D_MARK, 476 D13_MARK, SCIFA1_SCK_MARK, PWM2_C_MARK, TCLK2_B_MARK, 477 D14_MARK, SCIFA1_RXD_MARK, I2C5_SCL_B_MARK, 478 D15_MARK, SCIFA1_TXD_MARK, I2C5_SDA_B_MARK, 479 A0_MARK, SCIFB1_SCK_MARK, PWM3_B_MARK, 480 A1_MARK, SCIFB1_TXD_MARK, 481 A3_MARK, SCIFB0_SCK_MARK, 482 A4_MARK, SCIFB0_TXD_MARK, 483 A5_MARK, SCIFB0_RXD_MARK, PWM4_B_MARK, TPUTO3_C_MARK, 484 A6_MARK, SCIFB0_CTS_N_MARK, SCIFA4_RXD_B_MARK, TPUTO2_C_MARK, 485 486 /* IPSR2 */ 487 A7_MARK, SCIFB0_RTS_N_MARK, SCIFA4_TXD_B_MARK, 488 A8_MARK, MSIOF1_RXD_MARK, SCIFA0_RXD_B_MARK, 489 A9_MARK, MSIOF1_TXD_MARK, SCIFA0_TXD_B_MARK, 490 A10_MARK, MSIOF1_SCK_MARK, IIC0_SCL_B_MARK, 491 A11_MARK, MSIOF1_SYNC_MARK, IIC0_SDA_B_MARK, 492 A12_MARK, MSIOF1_SS1_MARK, SCIFA5_RXD_B_MARK, 493 A13_MARK, MSIOF1_SS2_MARK, SCIFA5_TXD_B_MARK, 494 A14_MARK, MSIOF2_RXD_MARK, HSCIF0_HRX_B_MARK, DREQ1_N_MARK, 495 A15_MARK, MSIOF2_TXD_MARK, HSCIF0_HTX_B_MARK, DACK1_MARK, 496 A16_MARK, MSIOF2_SCK_MARK, HSCIF0_HSCK_B_MARK, SPEEDIN_MARK, 497 CAN_CLK_C_MARK, TPUTO2_B_MARK, 498 A17_MARK, MSIOF2_SYNC_MARK, SCIF4_RXD_E_MARK, CAN1_RX_B_MARK, 499 A18_MARK, MSIOF2_SS1_MARK, SCIF4_TXD_E_MARK, CAN1_TX_B_MARK, 500 A19_MARK, MSIOF2_SS2_MARK, PWM4_MARK, TPUTO2_MARK, 501 A20_MARK, SPCLK_MARK, 502 503 /* IPSR3 */ 504 A21_MARK, MOSI_IO0_MARK, 505 A22_MARK, MISO_IO1_MARK, ATADIR1_N_MARK, 506 A23_MARK, IO2_MARK, ATAWR1_N_MARK, 507 A24_MARK, IO3_MARK, EX_WAIT2_MARK, 508 A25_MARK, SSL_MARK, ATARD1_N_MARK, 509 CS0_N_MARK, VI1_DATA8_MARK, 510 CS1_N_A26_MARK, VI1_DATA9_MARK, 511 EX_CS0_N_MARK, VI1_DATA10_MARK, 512 EX_CS1_N_MARK, TPUTO3_B_MARK, SCIFB2_RXD_MARK, VI1_DATA11_MARK, 513 EX_CS2_N_MARK, PWM0_MARK, SCIF4_RXD_C_MARK, TS_SDATA_B_MARK, 514 TPUTO3_MARK, SCIFB2_TXD_MARK, 515 EX_CS3_N_MARK, SCIFA2_SCK_MARK, SCIF4_TXD_C_MARK, TS_SCK_B_MARK, 516 BPFCLK_MARK, SCIFB2_SCK_MARK, 517 EX_CS4_N_MARK, SCIFA2_RXD_MARK, I2C2_SCL_E_MARK, TS_SDEN_B_MARK, 518 FMCLK_MARK, SCIFB2_CTS_N_MARK, 519 EX_CS5_N_MARK, SCIFA2_TXD_MARK, I2C2_SDA_E_MARK, TS_SPSYNC_B_MARK, 520 FMIN_MARK, SCIFB2_RTS_N_MARK, 521 BS_N_MARK, DRACK0_MARK, PWM1_C_MARK, TPUTO0_C_MARK, ATACS01_N_MARK, 522 RD_N_MARK, ATACS11_N_MARK, 523 RD_WR_N_MARK, ATAG1_N_MARK, 524 525 /* IPSR4 */ 526 EX_WAIT0_MARK, CAN_CLK_B_MARK, SCIF_CLK_MARK, 527 DU0_DR0_MARK, LCDOUT16_MARK, SCIF5_RXD_C_MARK, I2C2_SCL_D_MARK, 528 DU0_DR1_MARK, LCDOUT17_MARK, SCIF5_TXD_C_MARK, I2C2_SDA_D_MARK, 529 DU0_DR2_MARK, LCDOUT18_MARK, 530 DU0_DR3_MARK, LCDOUT19_MARK, 531 DU0_DR4_MARK, LCDOUT20_MARK, 532 DU0_DR5_MARK, LCDOUT21_MARK, 533 DU0_DR6_MARK, LCDOUT22_MARK, 534 DU0_DR7_MARK, LCDOUT23_MARK, 535 DU0_DG0_MARK, LCDOUT8_MARK, SCIFA0_RXD_C_MARK, I2C3_SCL_D_MARK, 536 DU0_DG1_MARK, LCDOUT9_MARK, SCIFA0_TXD_C_MARK, I2C3_SDA_D_MARK, 537 DU0_DG2_MARK, LCDOUT10_MARK, 538 DU0_DG3_MARK, LCDOUT11_MARK, 539 DU0_DG4_MARK, LCDOUT12_MARK, 540 541 /* IPSR5 */ 542 DU0_DG5_MARK, LCDOUT13_MARK, 543 DU0_DG6_MARK, LCDOUT14_MARK, 544 DU0_DG7_MARK, LCDOUT15_MARK, 545 DU0_DB0_MARK, LCDOUT0_MARK, SCIFA4_RXD_C_MARK, I2C4_SCL_D_MARK, 546 CAN0_RX_C_MARK, 547 DU0_DB1_MARK, LCDOUT1_MARK, SCIFA4_TXD_C_MARK, I2C4_SDA_D_MARK, 548 CAN0_TX_C_MARK, 549 DU0_DB2_MARK, LCDOUT2_MARK, 550 DU0_DB3_MARK, LCDOUT3_MARK, 551 DU0_DB4_MARK, LCDOUT4_MARK, 552 DU0_DB5_MARK, LCDOUT5_MARK, 553 DU0_DB6_MARK, LCDOUT6_MARK, 554 DU0_DB7_MARK, LCDOUT7_MARK, 555 DU0_DOTCLKIN_MARK, QSTVA_QVS_MARK, 556 DU0_DOTCLKOUT0_MARK, QCLK_MARK, 557 DU0_DOTCLKOUT1_MARK, QSTVB_QVE_MARK, 558 DU0_EXHSYNC_DU0_HSYNC_MARK, QSTH_QHS_MARK, 559 560 /* IPSR6 */ 561 DU0_EXVSYNC_DU0_VSYNC_MARK, QSTB_QHE_MARK, 562 DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK, 563 DU0_DISP_MARK, QPOLA_MARK, DU0_CDE_MARK, QPOLB_MARK, 564 VI0_CLK_MARK, AVB_RX_CLK_MARK, VI0_DATA0_VI0_B0_MARK, AVB_RX_DV_MARK, 565 VI0_DATA1_VI0_B1_MARK, AVB_RXD0_MARK, 566 VI0_DATA2_VI0_B2_MARK, AVB_RXD1_MARK, 567 VI0_DATA3_VI0_B3_MARK, AVB_RXD2_MARK, 568 VI0_DATA4_VI0_B4_MARK, AVB_RXD3_MARK, 569 VI0_DATA5_VI0_B5_MARK, AVB_RXD4_MARK, 570 VI0_DATA6_VI0_B6_MARK, AVB_RXD5_MARK, 571 VI0_DATA7_VI0_B7_MARK, AVB_RXD6_MARK, 572 VI0_CLKENB_MARK, I2C3_SCL_MARK, SCIFA5_RXD_C_MARK, IETX_C_MARK, 573 AVB_RXD7_MARK, 574 VI0_FIELD_MARK, I2C3_SDA_MARK, SCIFA5_TXD_C_MARK, IECLK_C_MARK, 575 AVB_RX_ER_MARK, 576 VI0_HSYNC_N_MARK, SCIF0_RXD_B_MARK, I2C0_SCL_C_MARK, IERX_C_MARK, 577 AVB_COL_MARK, 578 VI0_VSYNC_N_MARK, SCIF0_TXD_B_MARK, I2C0_SDA_C_MARK, 579 AUDIO_CLKOUT_B_MARK, AVB_TX_EN_MARK, 580 ETH_MDIO_MARK, VI0_G0_MARK, MSIOF2_RXD_B_MARK, I2C5_SCL_D_MARK, 581 AVB_TX_CLK_MARK, ADIDATA_MARK, 582 583 /* IPSR7 */ 584 ETH_CRS_DV_MARK, VI0_G1_MARK, MSIOF2_TXD_B_MARK, I2C5_SDA_D_MARK, 585 AVB_TXD0_MARK, ADICS_SAMP_MARK, 586 ETH_RX_ER_MARK, VI0_G2_MARK, MSIOF2_SCK_B_MARK, CAN0_RX_B_MARK, 587 AVB_TXD1_MARK, ADICLK_MARK, 588 ETH_RXD0_MARK, VI0_G3_MARK, MSIOF2_SYNC_B_MARK, CAN0_TX_B_MARK, 589 AVB_TXD2_MARK, ADICHS0_MARK, 590 ETH_RXD1_MARK, VI0_G4_MARK, MSIOF2_SS1_B_MARK, SCIF4_RXD_D_MARK, 591 AVB_TXD3_MARK, ADICHS1_MARK, 592 ETH_LINK_MARK, VI0_G5_MARK, MSIOF2_SS2_B_MARK, SCIF4_TXD_D_MARK, 593 AVB_TXD4_MARK, ADICHS2_MARK, 594 ETH_REFCLK_MARK, VI0_G6_MARK, SCIF2_SCK_C_MARK, AVB_TXD5_MARK, 595 SSI_SCK5_B_MARK, 596 ETH_TXD1_MARK, VI0_G7_MARK, SCIF2_RXD_C_MARK, IIC0_SCL_D_MARK, 597 AVB_TXD6_MARK, SSI_WS5_B_MARK, 598 ETH_TX_EN_MARK, VI0_R0_MARK, SCIF2_TXD_C_MARK, IIC0_SDA_D_MARK, 599 AVB_TXD7_MARK, SSI_SDATA5_B_MARK, 600 ETH_MAGIC_MARK, VI0_R1_MARK, SCIF3_SCK_B_MARK, AVB_TX_ER_MARK, 601 SSI_SCK6_B_MARK, 602 ETH_TXD0_MARK, VI0_R2_MARK, SCIF3_RXD_B_MARK, I2C4_SCL_E_MARK, 603 AVB_GTX_CLK_MARK, SSI_WS6_B_MARK, 604 DREQ0_N_MARK, SCIFB1_RXD_MARK, 605 606 /* IPSR8 */ 607 ETH_MDC_MARK, VI0_R3_MARK, SCIF3_TXD_B_MARK, I2C4_SDA_E_MARK, 608 AVB_MDC_MARK, SSI_SDATA6_B_MARK, HSCIF0_HRX_MARK, VI0_R4_MARK, 609 I2C1_SCL_C_MARK, AUDIO_CLKA_B_MARK, AVB_MDIO_MARK, SSI_SCK78_B_MARK, 610 HSCIF0_HTX_MARK, VI0_R5_MARK, I2C1_SDA_C_MARK, AUDIO_CLKB_B_MARK, 611 AVB_LINK_MARK, SSI_WS78_B_MARK, HSCIF0_HCTS_N_MARK, VI0_R6_MARK, 612 SCIF0_RXD_D_MARK, I2C0_SCL_E_MARK, AVB_MAGIC_MARK, SSI_SDATA7_B_MARK, 613 HSCIF0_HRTS_N_MARK, VI0_R7_MARK, SCIF0_TXD_D_MARK, I2C0_SDA_E_MARK, 614 AVB_PHY_INT_MARK, SSI_SDATA8_B_MARK, 615 HSCIF0_HSCK_MARK, SCIF_CLK_B_MARK, AVB_CRS_MARK, AUDIO_CLKC_B_MARK, 616 I2C0_SCL_MARK, SCIF0_RXD_C_MARK, PWM5_MARK, TCLK1_B_MARK, 617 AVB_GTXREFCLK_MARK, CAN1_RX_D_MARK, TPUTO0_B_MARK, I2C0_SDA_MARK, 618 SCIF0_TXD_C_MARK, TPUTO0_MARK, CAN_CLK_MARK, DVC_MUTE_MARK, 619 CAN1_TX_D_MARK, 620 I2C1_SCL_MARK, SCIF4_RXD_MARK, PWM5_B_MARK, DU1_DR0_MARK, 621 TS_SDATA_D_MARK, TPUTO1_B_MARK, 622 I2C1_SDA_MARK, SCIF4_TXD_MARK, IRQ5_MARK, DU1_DR1_MARK, TS_SCK_D_MARK, 623 BPFCLK_C_MARK, 624 MSIOF0_RXD_MARK, SCIF5_RXD_MARK, I2C2_SCL_C_MARK, DU1_DR2_MARK, 625 TS_SDEN_D_MARK, FMCLK_C_MARK, 626 627 /* IPSR9 */ 628 MSIOF0_TXD_MARK, SCIF5_TXD_MARK, I2C2_SDA_C_MARK, DU1_DR3_MARK, 629 TS_SPSYNC_D_MARK, FMIN_C_MARK, 630 MSIOF0_SCK_MARK, IRQ0_MARK, TS_SDATA_MARK, DU1_DR4_MARK, TPUTO1_C_MARK, 631 MSIOF0_SYNC_MARK, PWM1_MARK, TS_SCK_MARK, DU1_DR5_MARK, BPFCLK_B_MARK, 632 MSIOF0_SS1_MARK, SCIFA0_RXD_MARK, TS_SDEN_MARK, DU1_DR6_MARK, 633 FMCLK_B_MARK, 634 MSIOF0_SS2_MARK, SCIFA0_TXD_MARK, TS_SPSYNC_MARK, DU1_DR7_MARK, 635 FMIN_B_MARK, 636 HSCIF1_HRX_MARK, I2C4_SCL_MARK, PWM6_MARK, DU1_DG0_MARK, 637 HSCIF1_HTX_MARK, I2C4_SDA_MARK, TPUTO1_MARK, DU1_DG1_MARK, 638 HSCIF1_HSCK_MARK, PWM2_MARK, IETX_MARK, DU1_DG2_MARK, REMOCON_B_MARK, 639 SPEEDIN_B_MARK, 640 HSCIF1_HCTS_N_MARK, SCIFA4_RXD_MARK, IECLK_MARK, DU1_DG3_MARK, 641 SSI_SCK1_B_MARK, 642 HSCIF1_HRTS_N_MARK, SCIFA4_TXD_MARK, IERX_MARK, DU1_DG4_MARK, 643 SSI_WS1_B_MARK, 644 SCIF1_SCK_MARK, PWM3_MARK, TCLK2_MARK, DU1_DG5_MARK, SSI_SDATA1_B_MARK, 645 CAN_TXCLK_MARK, 646 647 /* IPSR10 */ 648 SCIF1_RXD_MARK, I2C5_SCL_MARK, DU1_DG6_MARK, SSI_SCK2_B_MARK, 649 SCIF1_TXD_MARK, I2C5_SDA_MARK, DU1_DG7_MARK, SSI_WS2_B_MARK, 650 SCIF2_RXD_MARK, IIC0_SCL_MARK, DU1_DB0_MARK, SSI_SDATA2_B_MARK, 651 SCIF2_TXD_MARK, IIC0_SDA_MARK, DU1_DB1_MARK, SSI_SCK9_B_MARK, 652 SCIF2_SCK_MARK, IRQ1_MARK, DU1_DB2_MARK, SSI_WS9_B_MARK, 653 SCIF3_SCK_MARK, IRQ2_MARK, BPFCLK_D_MARK, DU1_DB3_MARK, 654 SSI_SDATA9_B_MARK, 655 SCIF3_RXD_MARK, I2C1_SCL_E_MARK, FMCLK_D_MARK, DU1_DB4_MARK, 656 AUDIO_CLKA_C_MARK, SSI_SCK4_B_MARK, 657 SCIF3_TXD_MARK, I2C1_SDA_E_MARK, FMIN_D_MARK, DU1_DB5_MARK, 658 AUDIO_CLKB_C_MARK, SSI_WS4_B_MARK, 659 I2C2_SCL_MARK, SCIFA5_RXD_MARK, DU1_DB6_MARK, AUDIO_CLKC_C_MARK, 660 SSI_SDATA4_B_MARK, 661 I2C2_SDA_MARK, SCIFA5_TXD_MARK, DU1_DB7_MARK, AUDIO_CLKOUT_C_MARK, 662 SSI_SCK5_MARK, SCIFA3_SCK_MARK, DU1_DOTCLKIN_MARK, 663 664 /* IPSR11 */ 665 SSI_WS5_MARK, SCIFA3_RXD_MARK, I2C3_SCL_C_MARK, DU1_DOTCLKOUT0_MARK, 666 SSI_SDATA5_MARK, SCIFA3_TXD_MARK, I2C3_SDA_C_MARK, DU1_DOTCLKOUT1_MARK, 667 SSI_SCK6_MARK, SCIFA1_SCK_B_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK, 668 SSI_WS6_MARK, SCIFA1_RXD_B_MARK, I2C4_SCL_C_MARK, 669 DU1_EXVSYNC_DU1_VSYNC_MARK, 670 SSI_SDATA6_MARK, SCIFA1_TXD_B_MARK, I2C4_SDA_C_MARK, 671 DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK, 672 SSI_SCK78_MARK, SCIFA2_SCK_B_MARK, I2C5_SDA_C_MARK, DU1_DISP_MARK, 673 SSI_WS78_MARK, SCIFA2_RXD_B_MARK, I2C5_SCL_C_MARK, DU1_CDE_MARK, 674 SSI_SDATA7_MARK, SCIFA2_TXD_B_MARK, IRQ8_MARK, AUDIO_CLKA_D_MARK, 675 CAN_CLK_D_MARK, 676 SSI_SCK0129_MARK, MSIOF1_RXD_B_MARK, SCIF5_RXD_D_MARK, ADIDATA_B_MARK, 677 SSI_WS0129_MARK, MSIOF1_TXD_B_MARK, SCIF5_TXD_D_MARK, ADICS_SAMP_B_MARK, 678 SSI_SDATA0_MARK, MSIOF1_SCK_B_MARK, PWM0_B_MARK, ADICLK_B_MARK, 679 680 /* IPSR12 */ 681 SSI_SCK34_MARK, MSIOF1_SYNC_B_MARK, SCIFA1_SCK_C_MARK, ADICHS0_B_MARK, 682 DREQ1_N_B_MARK, 683 SSI_WS34_MARK, MSIOF1_SS1_B_MARK, SCIFA1_RXD_C_MARK, ADICHS1_B_MARK, 684 CAN1_RX_C_MARK, DACK1_B_MARK, 685 SSI_SDATA3_MARK, MSIOF1_SS2_B_MARK, SCIFA1_TXD_C_MARK, ADICHS2_B_MARK, 686 CAN1_TX_C_MARK, DREQ2_N_MARK, 687 SSI_SCK4_MARK, MLB_CLK_MARK, IETX_B_MARK, 688 SSI_WS4_MARK, MLB_SIG_MARK, IECLK_B_MARK, 689 SSI_SDATA4_MARK, MLB_DAT_MARK, IERX_B_MARK, 690 SSI_SDATA8_MARK, SCIF1_SCK_B_MARK, PWM1_B_MARK, IRQ9_MARK, REMOCON_MARK, 691 DACK2_MARK, ETH_MDIO_B_MARK, 692 SSI_SCK1_MARK, SCIF1_RXD_B_MARK, IIC0_SCL_C_MARK, VI1_CLK_MARK, 693 CAN0_RX_D_MARK, ETH_CRS_DV_B_MARK, 694 SSI_WS1_MARK, SCIF1_TXD_B_MARK, IIC0_SDA_C_MARK, VI1_DATA0_MARK, 695 CAN0_TX_D_MARK, ETH_RX_ER_B_MARK, 696 SSI_SDATA1_MARK, HSCIF1_HRX_B_MARK, VI1_DATA1_MARK, ATAWR0_N_MARK, 697 ETH_RXD0_B_MARK, 698 SSI_SCK2_MARK, HSCIF1_HTX_B_MARK, VI1_DATA2_MARK, ATAG0_N_MARK, 699 ETH_RXD1_B_MARK, 700 701 /* IPSR13 */ 702 SSI_WS2_MARK, HSCIF1_HCTS_N_B_MARK, SCIFA0_RXD_D_MARK, VI1_DATA3_MARK, 703 ATACS00_N_MARK, ETH_LINK_B_MARK, 704 SSI_SDATA2_MARK, HSCIF1_HRTS_N_B_MARK, SCIFA0_TXD_D_MARK, 705 VI1_DATA4_MARK, ATACS10_N_MARK, ETH_REFCLK_B_MARK, 706 SSI_SCK9_MARK, SCIF2_SCK_B_MARK, PWM2_B_MARK, VI1_DATA5_MARK, 707 EX_WAIT1_MARK, ETH_TXD1_B_MARK, 708 SSI_WS9_MARK, SCIF2_RXD_B_MARK, I2C3_SCL_E_MARK, VI1_DATA6_MARK, 709 ATARD0_N_MARK, ETH_TX_EN_B_MARK, 710 SSI_SDATA9_MARK, SCIF2_TXD_B_MARK, I2C3_SDA_E_MARK, VI1_DATA7_MARK, 711 ATADIR0_N_MARK, ETH_MAGIC_B_MARK, 712 AUDIO_CLKA_MARK, I2C0_SCL_B_MARK, SCIFA4_RXD_D_MARK, VI1_CLKENB_MARK, 713 TS_SDATA_C_MARK, ETH_TXD0_B_MARK, 714 AUDIO_CLKB_MARK, I2C0_SDA_B_MARK, SCIFA4_TXD_D_MARK, VI1_FIELD_MARK, 715 TS_SCK_C_MARK, BPFCLK_E_MARK, ETH_MDC_B_MARK, 716 AUDIO_CLKC_MARK, I2C4_SCL_B_MARK, SCIFA5_RXD_D_MARK, VI1_HSYNC_N_MARK, 717 TS_SDEN_C_MARK, FMCLK_E_MARK, 718 AUDIO_CLKOUT_MARK, I2C4_SDA_B_MARK, SCIFA5_TXD_D_MARK, VI1_VSYNC_N_MARK, 719 TS_SPSYNC_C_MARK, FMIN_E_MARK, 720 PINMUX_MARK_END, 721 }; 722 723 static const u16 pinmux_data[] = { 724 PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */ 725 726 PINMUX_SINGLE(A2), 727 PINMUX_SINGLE(WE0_N), 728 PINMUX_SINGLE(WE1_N), 729 PINMUX_SINGLE(DACK0), 730 PINMUX_SINGLE(USB0_PWEN), 731 PINMUX_SINGLE(USB0_OVC), 732 PINMUX_SINGLE(USB1_PWEN), 733 PINMUX_SINGLE(USB1_OVC), 734 PINMUX_SINGLE(SD0_CLK), 735 PINMUX_SINGLE(SD0_CMD), 736 PINMUX_SINGLE(SD0_DATA0), 737 PINMUX_SINGLE(SD0_DATA1), 738 PINMUX_SINGLE(SD0_DATA2), 739 PINMUX_SINGLE(SD0_DATA3), 740 PINMUX_SINGLE(SD0_CD), 741 PINMUX_SINGLE(SD0_WP), 742 PINMUX_SINGLE(SD1_CLK), 743 PINMUX_SINGLE(SD1_CMD), 744 PINMUX_SINGLE(SD1_DATA0), 745 PINMUX_SINGLE(SD1_DATA1), 746 PINMUX_SINGLE(SD1_DATA2), 747 PINMUX_SINGLE(SD1_DATA3), 748 749 /* IPSR0 */ 750 PINMUX_IPSR_GPSR(IP0_0, SD1_CD), 751 PINMUX_IPSR_MSEL(IP0_0, CAN0_RX, SEL_CAN0_0), 752 PINMUX_IPSR_GPSR(IP0_9_8, SD1_WP), 753 PINMUX_IPSR_GPSR(IP0_9_8, IRQ7), 754 PINMUX_IPSR_MSEL(IP0_9_8, CAN0_TX, SEL_CAN0_0), 755 PINMUX_IPSR_GPSR(IP0_10, MMC_CLK), 756 PINMUX_IPSR_GPSR(IP0_10, SD2_CLK), 757 PINMUX_IPSR_GPSR(IP0_11, MMC_CMD), 758 PINMUX_IPSR_GPSR(IP0_11, SD2_CMD), 759 PINMUX_IPSR_GPSR(IP0_12, MMC_D0), 760 PINMUX_IPSR_GPSR(IP0_12, SD2_DATA0), 761 PINMUX_IPSR_GPSR(IP0_13, MMC_D1), 762 PINMUX_IPSR_GPSR(IP0_13, SD2_DATA1), 763 PINMUX_IPSR_GPSR(IP0_14, MMC_D2), 764 PINMUX_IPSR_GPSR(IP0_14, SD2_DATA2), 765 PINMUX_IPSR_GPSR(IP0_15, MMC_D3), 766 PINMUX_IPSR_GPSR(IP0_15, SD2_DATA3), 767 PINMUX_IPSR_GPSR(IP0_16, MMC_D4), 768 PINMUX_IPSR_GPSR(IP0_16, SD2_CD), 769 PINMUX_IPSR_GPSR(IP0_17, MMC_D5), 770 PINMUX_IPSR_GPSR(IP0_17, SD2_WP), 771 PINMUX_IPSR_GPSR(IP0_19_18, MMC_D6), 772 PINMUX_IPSR_MSEL(IP0_19_18, SCIF0_RXD, SEL_SCIF0_0), 773 PINMUX_IPSR_MSEL(IP0_19_18, I2C2_SCL_B, SEL_I2C02_1), 774 PINMUX_IPSR_MSEL(IP0_19_18, CAN1_RX, SEL_CAN1_0), 775 PINMUX_IPSR_GPSR(IP0_21_20, MMC_D7), 776 PINMUX_IPSR_MSEL(IP0_21_20, SCIF0_TXD, SEL_SCIF0_0), 777 PINMUX_IPSR_MSEL(IP0_21_20, I2C2_SDA_B, SEL_I2C02_1), 778 PINMUX_IPSR_MSEL(IP0_21_20, CAN1_TX, SEL_CAN1_0), 779 PINMUX_IPSR_GPSR(IP0_23_22, D0), 780 PINMUX_IPSR_MSEL(IP0_23_22, SCIFA3_SCK_B, SEL_SCIFA3_1), 781 PINMUX_IPSR_GPSR(IP0_23_22, IRQ4), 782 PINMUX_IPSR_GPSR(IP0_24, D1), 783 PINMUX_IPSR_MSEL(IP0_24, SCIFA3_RXD_B, SEL_SCIFA3_1), 784 PINMUX_IPSR_GPSR(IP0_25, D2), 785 PINMUX_IPSR_MSEL(IP0_25, SCIFA3_TXD_B, SEL_SCIFA3_1), 786 PINMUX_IPSR_GPSR(IP0_27_26, D3), 787 PINMUX_IPSR_MSEL(IP0_27_26, I2C3_SCL_B, SEL_I2C03_1), 788 PINMUX_IPSR_MSEL(IP0_27_26, SCIF5_RXD_B, SEL_SCIF5_1), 789 PINMUX_IPSR_GPSR(IP0_29_28, D4), 790 PINMUX_IPSR_MSEL(IP0_29_28, I2C3_SDA_B, SEL_I2C03_1), 791 PINMUX_IPSR_MSEL(IP0_29_28, SCIF5_TXD_B, SEL_SCIF5_1), 792 PINMUX_IPSR_GPSR(IP0_31_30, D5), 793 PINMUX_IPSR_MSEL(IP0_31_30, SCIF4_RXD_B, SEL_SCIF4_1), 794 PINMUX_IPSR_MSEL(IP0_31_30, I2C0_SCL_D, SEL_I2C00_3), 795 796 /* IPSR1 */ 797 PINMUX_IPSR_GPSR(IP1_1_0, D6), 798 PINMUX_IPSR_MSEL(IP1_1_0, SCIF4_TXD_B, SEL_SCIF4_1), 799 PINMUX_IPSR_MSEL(IP1_1_0, I2C0_SDA_D, SEL_I2C00_3), 800 PINMUX_IPSR_GPSR(IP1_3_2, D7), 801 PINMUX_IPSR_GPSR(IP1_3_2, IRQ3), 802 PINMUX_IPSR_MSEL(IP1_3_2, TCLK1, SEL_TMU_0), 803 PINMUX_IPSR_GPSR(IP1_3_2, PWM6_B), 804 PINMUX_IPSR_GPSR(IP1_5_4, D8), 805 PINMUX_IPSR_GPSR(IP1_5_4, HSCIF2_HRX), 806 PINMUX_IPSR_MSEL(IP1_5_4, I2C1_SCL_B, SEL_I2C01_1), 807 PINMUX_IPSR_GPSR(IP1_7_6, D9), 808 PINMUX_IPSR_GPSR(IP1_7_6, HSCIF2_HTX), 809 PINMUX_IPSR_MSEL(IP1_7_6, I2C1_SDA_B, SEL_I2C01_1), 810 PINMUX_IPSR_GPSR(IP1_10_8, D10), 811 PINMUX_IPSR_GPSR(IP1_10_8, HSCIF2_HSCK), 812 PINMUX_IPSR_MSEL(IP1_10_8, SCIF1_SCK_C, SEL_SCIF1_2), 813 PINMUX_IPSR_GPSR(IP1_10_8, IRQ6), 814 PINMUX_IPSR_GPSR(IP1_10_8, PWM5_C), 815 PINMUX_IPSR_GPSR(IP1_12_11, D11), 816 PINMUX_IPSR_GPSR(IP1_12_11, HSCIF2_HCTS_N), 817 PINMUX_IPSR_MSEL(IP1_12_11, SCIF1_RXD_C, SEL_SCIF1_2), 818 PINMUX_IPSR_MSEL(IP1_12_11, I2C1_SCL_D, SEL_I2C01_3), 819 PINMUX_IPSR_GPSR(IP1_14_13, D12), 820 PINMUX_IPSR_GPSR(IP1_14_13, HSCIF2_HRTS_N), 821 PINMUX_IPSR_MSEL(IP1_14_13, SCIF1_TXD_C, SEL_SCIF1_2), 822 PINMUX_IPSR_MSEL(IP1_14_13, I2C1_SDA_D, SEL_I2C01_3), 823 PINMUX_IPSR_GPSR(IP1_17_15, D13), 824 PINMUX_IPSR_MSEL(IP1_17_15, SCIFA1_SCK, SEL_SCIFA1_0), 825 PINMUX_IPSR_GPSR(IP1_17_15, PWM2_C), 826 PINMUX_IPSR_MSEL(IP1_17_15, TCLK2_B, SEL_TMU_1), 827 PINMUX_IPSR_GPSR(IP1_19_18, D14), 828 PINMUX_IPSR_MSEL(IP1_19_18, SCIFA1_RXD, SEL_SCIFA1_0), 829 PINMUX_IPSR_MSEL(IP1_19_18, I2C5_SCL_B, SEL_I2C05_1), 830 PINMUX_IPSR_GPSR(IP1_21_20, D15), 831 PINMUX_IPSR_MSEL(IP1_21_20, SCIFA1_TXD, SEL_SCIFA1_0), 832 PINMUX_IPSR_MSEL(IP1_21_20, I2C5_SDA_B, SEL_I2C05_1), 833 PINMUX_IPSR_GPSR(IP1_23_22, A0), 834 PINMUX_IPSR_GPSR(IP1_23_22, SCIFB1_SCK), 835 PINMUX_IPSR_GPSR(IP1_23_22, PWM3_B), 836 PINMUX_IPSR_GPSR(IP1_24, A1), 837 PINMUX_IPSR_GPSR(IP1_24, SCIFB1_TXD), 838 PINMUX_IPSR_GPSR(IP1_26, A3), 839 PINMUX_IPSR_GPSR(IP1_26, SCIFB0_SCK), 840 PINMUX_IPSR_GPSR(IP1_27, A4), 841 PINMUX_IPSR_GPSR(IP1_27, SCIFB0_TXD), 842 PINMUX_IPSR_GPSR(IP1_29_28, A5), 843 PINMUX_IPSR_GPSR(IP1_29_28, SCIFB0_RXD), 844 PINMUX_IPSR_GPSR(IP1_29_28, PWM4_B), 845 PINMUX_IPSR_GPSR(IP1_29_28, TPUTO3_C), 846 PINMUX_IPSR_GPSR(IP1_31_30, A6), 847 PINMUX_IPSR_GPSR(IP1_31_30, SCIFB0_CTS_N), 848 PINMUX_IPSR_MSEL(IP1_31_30, SCIFA4_RXD_B, SEL_SCIFA4_1), 849 PINMUX_IPSR_GPSR(IP1_31_30, TPUTO2_C), 850 851 /* IPSR2 */ 852 PINMUX_IPSR_GPSR(IP2_1_0, A7), 853 PINMUX_IPSR_GPSR(IP2_1_0, SCIFB0_RTS_N), 854 PINMUX_IPSR_MSEL(IP2_1_0, SCIFA4_TXD_B, SEL_SCIFA4_1), 855 PINMUX_IPSR_GPSR(IP2_3_2, A8), 856 PINMUX_IPSR_MSEL(IP2_3_2, MSIOF1_RXD, SEL_MSI1_0), 857 PINMUX_IPSR_MSEL(IP2_3_2, SCIFA0_RXD_B, SEL_SCIFA0_1), 858 PINMUX_IPSR_GPSR(IP2_5_4, A9), 859 PINMUX_IPSR_MSEL(IP2_5_4, MSIOF1_TXD, SEL_MSI1_0), 860 PINMUX_IPSR_MSEL(IP2_5_4, SCIFA0_TXD_B, SEL_SCIFA0_1), 861 PINMUX_IPSR_GPSR(IP2_7_6, A10), 862 PINMUX_IPSR_MSEL(IP2_7_6, MSIOF1_SCK, SEL_MSI1_0), 863 PINMUX_IPSR_MSEL(IP2_7_6, IIC0_SCL_B, SEL_IIC0_1), 864 PINMUX_IPSR_GPSR(IP2_9_8, A11), 865 PINMUX_IPSR_MSEL(IP2_9_8, MSIOF1_SYNC, SEL_MSI1_0), 866 PINMUX_IPSR_MSEL(IP2_9_8, IIC0_SDA_B, SEL_IIC0_1), 867 PINMUX_IPSR_GPSR(IP2_11_10, A12), 868 PINMUX_IPSR_MSEL(IP2_11_10, MSIOF1_SS1, SEL_MSI1_0), 869 PINMUX_IPSR_MSEL(IP2_11_10, SCIFA5_RXD_B, SEL_SCIFA5_1), 870 PINMUX_IPSR_GPSR(IP2_13_12, A13), 871 PINMUX_IPSR_MSEL(IP2_13_12, MSIOF1_SS2, SEL_MSI1_0), 872 PINMUX_IPSR_MSEL(IP2_13_12, SCIFA5_TXD_B, SEL_SCIFA5_1), 873 PINMUX_IPSR_GPSR(IP2_15_14, A14), 874 PINMUX_IPSR_MSEL(IP2_15_14, MSIOF2_RXD, SEL_MSI2_0), 875 PINMUX_IPSR_MSEL(IP2_15_14, HSCIF0_HRX_B, SEL_HSCIF0_1), 876 PINMUX_IPSR_MSEL(IP2_15_14, DREQ1_N, SEL_LBS_0), 877 PINMUX_IPSR_GPSR(IP2_17_16, A15), 878 PINMUX_IPSR_MSEL(IP2_17_16, MSIOF2_TXD, SEL_MSI2_0), 879 PINMUX_IPSR_MSEL(IP2_17_16, HSCIF0_HTX_B, SEL_HSCIF0_1), 880 PINMUX_IPSR_MSEL(IP2_17_16, DACK1, SEL_LBS_0), 881 PINMUX_IPSR_GPSR(IP2_20_18, A16), 882 PINMUX_IPSR_MSEL(IP2_20_18, MSIOF2_SCK, SEL_MSI2_0), 883 PINMUX_IPSR_MSEL(IP2_20_18, HSCIF0_HSCK_B, SEL_HSCIF0_1), 884 PINMUX_IPSR_MSEL(IP2_20_18, SPEEDIN, SEL_RSP_0), 885 PINMUX_IPSR_MSEL(IP2_20_18, CAN_CLK_C, SEL_CAN_2), 886 PINMUX_IPSR_GPSR(IP2_20_18, TPUTO2_B), 887 PINMUX_IPSR_GPSR(IP2_23_21, A17), 888 PINMUX_IPSR_MSEL(IP2_23_21, MSIOF2_SYNC, SEL_MSI2_0), 889 PINMUX_IPSR_MSEL(IP2_23_21, SCIF4_RXD_E, SEL_SCIF4_4), 890 PINMUX_IPSR_MSEL(IP2_23_21, CAN1_RX_B, SEL_CAN1_1), 891 PINMUX_IPSR_GPSR(IP2_26_24, A18), 892 PINMUX_IPSR_MSEL(IP2_26_24, MSIOF2_SS1, SEL_MSI2_0), 893 PINMUX_IPSR_MSEL(IP2_26_24, SCIF4_TXD_E, SEL_SCIF4_4), 894 PINMUX_IPSR_MSEL(IP2_26_24, CAN1_TX_B, SEL_CAN1_1), 895 PINMUX_IPSR_GPSR(IP2_29_27, A19), 896 PINMUX_IPSR_MSEL(IP2_29_27, MSIOF2_SS2, SEL_MSI2_0), 897 PINMUX_IPSR_GPSR(IP2_29_27, PWM4), 898 PINMUX_IPSR_GPSR(IP2_29_27, TPUTO2), 899 PINMUX_IPSR_GPSR(IP2_31_30, A20), 900 PINMUX_IPSR_GPSR(IP2_31_30, SPCLK), 901 902 /* IPSR3 */ 903 PINMUX_IPSR_GPSR(IP3_1_0, A21), 904 PINMUX_IPSR_GPSR(IP3_1_0, MOSI_IO0), 905 PINMUX_IPSR_GPSR(IP3_3_2, A22), 906 PINMUX_IPSR_GPSR(IP3_3_2, MISO_IO1), 907 PINMUX_IPSR_GPSR(IP3_3_2, ATADIR1_N), 908 PINMUX_IPSR_GPSR(IP3_5_4, A23), 909 PINMUX_IPSR_GPSR(IP3_5_4, IO2), 910 PINMUX_IPSR_GPSR(IP3_5_4, ATAWR1_N), 911 PINMUX_IPSR_GPSR(IP3_7_6, A24), 912 PINMUX_IPSR_GPSR(IP3_7_6, IO3), 913 PINMUX_IPSR_GPSR(IP3_7_6, EX_WAIT2), 914 PINMUX_IPSR_GPSR(IP3_9_8, A25), 915 PINMUX_IPSR_GPSR(IP3_9_8, SSL), 916 PINMUX_IPSR_GPSR(IP3_9_8, ATARD1_N), 917 PINMUX_IPSR_GPSR(IP3_10, CS0_N), 918 PINMUX_IPSR_GPSR(IP3_10, VI1_DATA8), 919 PINMUX_IPSR_GPSR(IP3_11, CS1_N_A26), 920 PINMUX_IPSR_GPSR(IP3_11, VI1_DATA9), 921 PINMUX_IPSR_GPSR(IP3_12, EX_CS0_N), 922 PINMUX_IPSR_GPSR(IP3_12, VI1_DATA10), 923 PINMUX_IPSR_GPSR(IP3_14_13, EX_CS1_N), 924 PINMUX_IPSR_GPSR(IP3_14_13, TPUTO3_B), 925 PINMUX_IPSR_GPSR(IP3_14_13, SCIFB2_RXD), 926 PINMUX_IPSR_GPSR(IP3_14_13, VI1_DATA11), 927 PINMUX_IPSR_GPSR(IP3_17_15, EX_CS2_N), 928 PINMUX_IPSR_GPSR(IP3_17_15, PWM0), 929 PINMUX_IPSR_MSEL(IP3_17_15, SCIF4_RXD_C, SEL_SCIF4_2), 930 PINMUX_IPSR_MSEL(IP3_17_15, TS_SDATA_B, SEL_TSIF0_1), 931 PINMUX_IPSR_GPSR(IP3_17_15, TPUTO3), 932 PINMUX_IPSR_GPSR(IP3_17_15, SCIFB2_TXD), 933 PINMUX_IPSR_GPSR(IP3_20_18, EX_CS3_N), 934 PINMUX_IPSR_MSEL(IP3_20_18, SCIFA2_SCK, SEL_SCIFA2_0), 935 PINMUX_IPSR_MSEL(IP3_20_18, SCIF4_TXD_C, SEL_SCIF4_2), 936 PINMUX_IPSR_MSEL(IP3_20_18, TS_SCK_B, SEL_TSIF0_1), 937 PINMUX_IPSR_MSEL(IP3_20_18, BPFCLK, SEL_DARC_0), 938 PINMUX_IPSR_GPSR(IP3_20_18, SCIFB2_SCK), 939 PINMUX_IPSR_GPSR(IP3_23_21, EX_CS4_N), 940 PINMUX_IPSR_MSEL(IP3_23_21, SCIFA2_RXD, SEL_SCIFA2_0), 941 PINMUX_IPSR_MSEL(IP3_23_21, I2C2_SCL_E, SEL_I2C02_4), 942 PINMUX_IPSR_MSEL(IP3_23_21, TS_SDEN_B, SEL_TSIF0_1), 943 PINMUX_IPSR_MSEL(IP3_23_21, FMCLK, SEL_DARC_0), 944 PINMUX_IPSR_GPSR(IP3_23_21, SCIFB2_CTS_N), 945 PINMUX_IPSR_GPSR(IP3_26_24, EX_CS5_N), 946 PINMUX_IPSR_MSEL(IP3_26_24, SCIFA2_TXD, SEL_SCIFA2_0), 947 PINMUX_IPSR_MSEL(IP3_26_24, I2C2_SDA_E, SEL_I2C02_4), 948 PINMUX_IPSR_MSEL(IP3_26_24, TS_SPSYNC_B, SEL_TSIF0_1), 949 PINMUX_IPSR_MSEL(IP3_26_24, FMIN, SEL_DARC_0), 950 PINMUX_IPSR_GPSR(IP3_26_24, SCIFB2_RTS_N), 951 PINMUX_IPSR_GPSR(IP3_29_27, BS_N), 952 PINMUX_IPSR_GPSR(IP3_29_27, DRACK0), 953 PINMUX_IPSR_GPSR(IP3_29_27, PWM1_C), 954 PINMUX_IPSR_GPSR(IP3_29_27, TPUTO0_C), 955 PINMUX_IPSR_GPSR(IP3_29_27, ATACS01_N), 956 PINMUX_IPSR_GPSR(IP3_30, RD_N), 957 PINMUX_IPSR_GPSR(IP3_30, ATACS11_N), 958 PINMUX_IPSR_GPSR(IP3_31, RD_WR_N), 959 PINMUX_IPSR_GPSR(IP3_31, ATAG1_N), 960 961 /* IPSR4 */ 962 PINMUX_IPSR_GPSR(IP4_1_0, EX_WAIT0), 963 PINMUX_IPSR_MSEL(IP4_1_0, CAN_CLK_B, SEL_CAN_1), 964 PINMUX_IPSR_MSEL(IP4_1_0, SCIF_CLK, SEL_SCIF0_0), 965 PINMUX_IPSR_GPSR(IP4_4_2, DU0_DR0), 966 PINMUX_IPSR_GPSR(IP4_4_2, LCDOUT16), 967 PINMUX_IPSR_MSEL(IP4_4_2, SCIF5_RXD_C, SEL_SCIF5_2), 968 PINMUX_IPSR_MSEL(IP4_4_2, I2C2_SCL_D, SEL_I2C02_3), 969 PINMUX_IPSR_GPSR(IP4_7_5, DU0_DR1), 970 PINMUX_IPSR_GPSR(IP4_7_5, LCDOUT17), 971 PINMUX_IPSR_MSEL(IP4_7_5, SCIF5_TXD_C, SEL_SCIF5_2), 972 PINMUX_IPSR_MSEL(IP4_7_5, I2C2_SDA_D, SEL_I2C02_3), 973 PINMUX_IPSR_GPSR(IP4_9_8, DU0_DR2), 974 PINMUX_IPSR_GPSR(IP4_9_8, LCDOUT18), 975 PINMUX_IPSR_GPSR(IP4_11_10, DU0_DR3), 976 PINMUX_IPSR_GPSR(IP4_11_10, LCDOUT19), 977 PINMUX_IPSR_GPSR(IP4_13_12, DU0_DR4), 978 PINMUX_IPSR_GPSR(IP4_13_12, LCDOUT20), 979 PINMUX_IPSR_GPSR(IP4_15_14, DU0_DR5), 980 PINMUX_IPSR_GPSR(IP4_15_14, LCDOUT21), 981 PINMUX_IPSR_GPSR(IP4_17_16, DU0_DR6), 982 PINMUX_IPSR_GPSR(IP4_17_16, LCDOUT22), 983 PINMUX_IPSR_GPSR(IP4_19_18, DU0_DR7), 984 PINMUX_IPSR_GPSR(IP4_19_18, LCDOUT23), 985 PINMUX_IPSR_GPSR(IP4_22_20, DU0_DG0), 986 PINMUX_IPSR_GPSR(IP4_22_20, LCDOUT8), 987 PINMUX_IPSR_MSEL(IP4_22_20, SCIFA0_RXD_C, SEL_SCIFA0_2), 988 PINMUX_IPSR_MSEL(IP4_22_20, I2C3_SCL_D, SEL_I2C03_3), 989 PINMUX_IPSR_GPSR(IP4_25_23, DU0_DG1), 990 PINMUX_IPSR_GPSR(IP4_25_23, LCDOUT9), 991 PINMUX_IPSR_MSEL(IP4_25_23, SCIFA0_TXD_C, SEL_SCIFA0_2), 992 PINMUX_IPSR_MSEL(IP4_25_23, I2C3_SDA_D, SEL_I2C03_3), 993 PINMUX_IPSR_GPSR(IP4_27_26, DU0_DG2), 994 PINMUX_IPSR_GPSR(IP4_27_26, LCDOUT10), 995 PINMUX_IPSR_GPSR(IP4_29_28, DU0_DG3), 996 PINMUX_IPSR_GPSR(IP4_29_28, LCDOUT11), 997 PINMUX_IPSR_GPSR(IP4_31_30, DU0_DG4), 998 PINMUX_IPSR_GPSR(IP4_31_30, LCDOUT12), 999 1000 /* IPSR5 */ 1001 PINMUX_IPSR_GPSR(IP5_1_0, DU0_DG5), 1002 PINMUX_IPSR_GPSR(IP5_1_0, LCDOUT13), 1003 PINMUX_IPSR_GPSR(IP5_3_2, DU0_DG6), 1004 PINMUX_IPSR_GPSR(IP5_3_2, LCDOUT14), 1005 PINMUX_IPSR_GPSR(IP5_5_4, DU0_DG7), 1006 PINMUX_IPSR_GPSR(IP5_5_4, LCDOUT15), 1007 PINMUX_IPSR_GPSR(IP5_8_6, DU0_DB0), 1008 PINMUX_IPSR_GPSR(IP5_8_6, LCDOUT0), 1009 PINMUX_IPSR_MSEL(IP5_8_6, SCIFA4_RXD_C, SEL_SCIFA4_2), 1010 PINMUX_IPSR_MSEL(IP5_8_6, I2C4_SCL_D, SEL_I2C04_3), 1011 PINMUX_IPSR_MSEL(IP7_8_6, CAN0_RX_C, SEL_CAN0_2), 1012 PINMUX_IPSR_GPSR(IP5_11_9, DU0_DB1), 1013 PINMUX_IPSR_GPSR(IP5_11_9, LCDOUT1), 1014 PINMUX_IPSR_MSEL(IP5_11_9, SCIFA4_TXD_C, SEL_SCIFA4_2), 1015 PINMUX_IPSR_MSEL(IP5_11_9, I2C4_SDA_D, SEL_I2C04_3), 1016 PINMUX_IPSR_MSEL(IP5_11_9, CAN0_TX_C, SEL_CAN0_2), 1017 PINMUX_IPSR_GPSR(IP5_13_12, DU0_DB2), 1018 PINMUX_IPSR_GPSR(IP5_13_12, LCDOUT2), 1019 PINMUX_IPSR_GPSR(IP5_15_14, DU0_DB3), 1020 PINMUX_IPSR_GPSR(IP5_15_14, LCDOUT3), 1021 PINMUX_IPSR_GPSR(IP5_17_16, DU0_DB4), 1022 PINMUX_IPSR_GPSR(IP5_17_16, LCDOUT4), 1023 PINMUX_IPSR_GPSR(IP5_19_18, DU0_DB5), 1024 PINMUX_IPSR_GPSR(IP5_19_18, LCDOUT5), 1025 PINMUX_IPSR_GPSR(IP5_21_20, DU0_DB6), 1026 PINMUX_IPSR_GPSR(IP5_21_20, LCDOUT6), 1027 PINMUX_IPSR_GPSR(IP5_23_22, DU0_DB7), 1028 PINMUX_IPSR_GPSR(IP5_23_22, LCDOUT7), 1029 PINMUX_IPSR_GPSR(IP5_25_24, DU0_DOTCLKIN), 1030 PINMUX_IPSR_GPSR(IP5_25_24, QSTVA_QVS), 1031 PINMUX_IPSR_GPSR(IP5_27_26, DU0_DOTCLKOUT0), 1032 PINMUX_IPSR_GPSR(IP5_27_26, QCLK), 1033 PINMUX_IPSR_GPSR(IP5_29_28, DU0_DOTCLKOUT1), 1034 PINMUX_IPSR_GPSR(IP5_29_28, QSTVB_QVE), 1035 PINMUX_IPSR_GPSR(IP5_31_30, DU0_EXHSYNC_DU0_HSYNC), 1036 PINMUX_IPSR_GPSR(IP5_31_30, QSTH_QHS), 1037 1038 /* IPSR6 */ 1039 PINMUX_IPSR_GPSR(IP6_1_0, DU0_EXVSYNC_DU0_VSYNC), 1040 PINMUX_IPSR_GPSR(IP6_1_0, QSTB_QHE), 1041 PINMUX_IPSR_GPSR(IP6_3_2, DU0_EXODDF_DU0_ODDF_DISP_CDE), 1042 PINMUX_IPSR_GPSR(IP6_3_2, QCPV_QDE), 1043 PINMUX_IPSR_GPSR(IP6_5_4, DU0_DISP), 1044 PINMUX_IPSR_GPSR(IP6_5_4, QPOLA), 1045 PINMUX_IPSR_GPSR(IP6_7_6, DU0_CDE), 1046 PINMUX_IPSR_GPSR(IP6_7_6, QPOLB), 1047 PINMUX_IPSR_GPSR(IP6_8, VI0_CLK), 1048 PINMUX_IPSR_GPSR(IP6_8, AVB_RX_CLK), 1049 PINMUX_IPSR_GPSR(IP6_9, VI0_DATA0_VI0_B0), 1050 PINMUX_IPSR_GPSR(IP6_9, AVB_RX_DV), 1051 PINMUX_IPSR_GPSR(IP6_10, VI0_DATA1_VI0_B1), 1052 PINMUX_IPSR_GPSR(IP6_10, AVB_RXD0), 1053 PINMUX_IPSR_GPSR(IP6_11, VI0_DATA2_VI0_B2), 1054 PINMUX_IPSR_GPSR(IP6_11, AVB_RXD1), 1055 PINMUX_IPSR_GPSR(IP6_12, VI0_DATA3_VI0_B3), 1056 PINMUX_IPSR_GPSR(IP6_12, AVB_RXD2), 1057 PINMUX_IPSR_GPSR(IP6_13, VI0_DATA4_VI0_B4), 1058 PINMUX_IPSR_GPSR(IP6_13, AVB_RXD3), 1059 PINMUX_IPSR_GPSR(IP6_14, VI0_DATA5_VI0_B5), 1060 PINMUX_IPSR_GPSR(IP6_14, AVB_RXD4), 1061 PINMUX_IPSR_GPSR(IP6_15, VI0_DATA6_VI0_B6), 1062 PINMUX_IPSR_GPSR(IP6_15, AVB_RXD5), 1063 PINMUX_IPSR_GPSR(IP6_16, VI0_DATA7_VI0_B7), 1064 PINMUX_IPSR_GPSR(IP6_16, AVB_RXD6), 1065 PINMUX_IPSR_GPSR(IP6_19_17, VI0_CLKENB), 1066 PINMUX_IPSR_MSEL(IP6_19_17, I2C3_SCL, SEL_I2C03_0), 1067 PINMUX_IPSR_MSEL(IP6_19_17, SCIFA5_RXD_C, SEL_SCIFA5_2), 1068 PINMUX_IPSR_MSEL(IP6_19_17, IETX_C, SEL_IEB_2), 1069 PINMUX_IPSR_GPSR(IP6_19_17, AVB_RXD7), 1070 PINMUX_IPSR_GPSR(IP6_22_20, VI0_FIELD), 1071 PINMUX_IPSR_MSEL(IP6_22_20, I2C3_SDA, SEL_I2C03_0), 1072 PINMUX_IPSR_MSEL(IP6_22_20, SCIFA5_TXD_C, SEL_SCIFA5_2), 1073 PINMUX_IPSR_MSEL(IP6_22_20, IECLK_C, SEL_IEB_2), 1074 PINMUX_IPSR_GPSR(IP6_22_20, AVB_RX_ER), 1075 PINMUX_IPSR_GPSR(IP6_25_23, VI0_HSYNC_N), 1076 PINMUX_IPSR_MSEL(IP6_25_23, SCIF0_RXD_B, SEL_SCIF0_1), 1077 PINMUX_IPSR_MSEL(IP6_25_23, I2C0_SCL_C, SEL_I2C00_2), 1078 PINMUX_IPSR_MSEL(IP6_25_23, IERX_C, SEL_IEB_2), 1079 PINMUX_IPSR_GPSR(IP6_25_23, AVB_COL), 1080 PINMUX_IPSR_GPSR(IP6_28_26, VI0_VSYNC_N), 1081 PINMUX_IPSR_MSEL(IP6_28_26, SCIF0_TXD_B, SEL_SCIF0_1), 1082 PINMUX_IPSR_MSEL(IP6_28_26, I2C0_SDA_C, SEL_I2C00_2), 1083 PINMUX_IPSR_MSEL(IP6_28_26, AUDIO_CLKOUT_B, SEL_ADG_1), 1084 PINMUX_IPSR_GPSR(IP6_28_26, AVB_TX_EN), 1085 PINMUX_IPSR_MSEL(IP6_31_29, ETH_MDIO, SEL_ETH_0), 1086 PINMUX_IPSR_GPSR(IP6_31_29, VI0_G0), 1087 PINMUX_IPSR_MSEL(IP6_31_29, MSIOF2_RXD_B, SEL_MSI2_1), 1088 PINMUX_IPSR_MSEL(IP6_31_29, I2C5_SCL_D, SEL_I2C05_3), 1089 PINMUX_IPSR_GPSR(IP6_31_29, AVB_TX_CLK), 1090 PINMUX_IPSR_MSEL(IP6_31_29, ADIDATA, SEL_RAD_0), 1091 1092 /* IPSR7 */ 1093 PINMUX_IPSR_MSEL(IP7_2_0, ETH_CRS_DV, SEL_ETH_0), 1094 PINMUX_IPSR_GPSR(IP7_2_0, VI0_G1), 1095 PINMUX_IPSR_MSEL(IP7_2_0, MSIOF2_TXD_B, SEL_MSI2_1), 1096 PINMUX_IPSR_MSEL(IP7_2_0, I2C5_SDA_D, SEL_I2C05_3), 1097 PINMUX_IPSR_GPSR(IP7_2_0, AVB_TXD0), 1098 PINMUX_IPSR_MSEL(IP7_2_0, ADICS_SAMP, SEL_RAD_0), 1099 PINMUX_IPSR_MSEL(IP7_5_3, ETH_RX_ER, SEL_ETH_0), 1100 PINMUX_IPSR_GPSR(IP7_5_3, VI0_G2), 1101 PINMUX_IPSR_MSEL(IP7_5_3, MSIOF2_SCK_B, SEL_MSI2_1), 1102 PINMUX_IPSR_MSEL(IP7_5_3, CAN0_RX_B, SEL_CAN0_1), 1103 PINMUX_IPSR_GPSR(IP7_5_3, AVB_TXD1), 1104 PINMUX_IPSR_MSEL(IP7_5_3, ADICLK, SEL_RAD_0), 1105 PINMUX_IPSR_MSEL(IP7_8_6, ETH_RXD0, SEL_ETH_0), 1106 PINMUX_IPSR_GPSR(IP7_8_6, VI0_G3), 1107 PINMUX_IPSR_MSEL(IP7_8_6, MSIOF2_SYNC_B, SEL_MSI2_1), 1108 PINMUX_IPSR_MSEL(IP7_8_6, CAN0_TX_B, SEL_CAN0_1), 1109 PINMUX_IPSR_GPSR(IP7_8_6, AVB_TXD2), 1110 PINMUX_IPSR_MSEL(IP7_8_6, ADICHS0, SEL_RAD_0), 1111 PINMUX_IPSR_MSEL(IP7_11_9, ETH_RXD1, SEL_ETH_0), 1112 PINMUX_IPSR_GPSR(IP7_11_9, VI0_G4), 1113 PINMUX_IPSR_MSEL(IP7_11_9, MSIOF2_SS1_B, SEL_MSI2_1), 1114 PINMUX_IPSR_MSEL(IP7_11_9, SCIF4_RXD_D, SEL_SCIF4_3), 1115 PINMUX_IPSR_GPSR(IP7_11_9, AVB_TXD3), 1116 PINMUX_IPSR_MSEL(IP7_11_9, ADICHS1, SEL_RAD_0), 1117 PINMUX_IPSR_MSEL(IP7_14_12, ETH_LINK, SEL_ETH_0), 1118 PINMUX_IPSR_GPSR(IP7_14_12, VI0_G5), 1119 PINMUX_IPSR_MSEL(IP7_14_12, MSIOF2_SS2_B, SEL_MSI2_1), 1120 PINMUX_IPSR_MSEL(IP7_14_12, SCIF4_TXD_D, SEL_SCIF4_3), 1121 PINMUX_IPSR_GPSR(IP7_14_12, AVB_TXD4), 1122 PINMUX_IPSR_MSEL(IP7_14_12, ADICHS2, SEL_RAD_0), 1123 PINMUX_IPSR_MSEL(IP7_17_15, ETH_REFCLK, SEL_ETH_0), 1124 PINMUX_IPSR_GPSR(IP7_17_15, VI0_G6), 1125 PINMUX_IPSR_MSEL(IP7_17_15, SCIF2_SCK_C, SEL_SCIF2_2), 1126 PINMUX_IPSR_GPSR(IP7_17_15, AVB_TXD5), 1127 PINMUX_IPSR_MSEL(IP7_17_15, SSI_SCK5_B, SEL_SSI5_1), 1128 PINMUX_IPSR_MSEL(IP7_20_18, ETH_TXD1, SEL_ETH_0), 1129 PINMUX_IPSR_GPSR(IP7_20_18, VI0_G7), 1130 PINMUX_IPSR_MSEL(IP7_20_18, SCIF2_RXD_C, SEL_SCIF2_2), 1131 PINMUX_IPSR_MSEL(IP7_20_18, IIC0_SCL_D, SEL_IIC0_3), 1132 PINMUX_IPSR_GPSR(IP7_20_18, AVB_TXD6), 1133 PINMUX_IPSR_MSEL(IP7_20_18, SSI_WS5_B, SEL_SSI5_1), 1134 PINMUX_IPSR_MSEL(IP7_23_21, ETH_TX_EN, SEL_ETH_0), 1135 PINMUX_IPSR_GPSR(IP7_23_21, VI0_R0), 1136 PINMUX_IPSR_MSEL(IP7_23_21, SCIF2_TXD_C, SEL_SCIF2_2), 1137 PINMUX_IPSR_MSEL(IP7_23_21, IIC0_SDA_D, SEL_IIC0_3), 1138 PINMUX_IPSR_GPSR(IP7_23_21, AVB_TXD7), 1139 PINMUX_IPSR_MSEL(IP7_23_21, SSI_SDATA5_B, SEL_SSI5_1), 1140 PINMUX_IPSR_MSEL(IP7_26_24, ETH_MAGIC, SEL_ETH_0), 1141 PINMUX_IPSR_GPSR(IP7_26_24, VI0_R1), 1142 PINMUX_IPSR_MSEL(IP7_26_24, SCIF3_SCK_B, SEL_SCIF3_1), 1143 PINMUX_IPSR_GPSR(IP7_26_24, AVB_TX_ER), 1144 PINMUX_IPSR_MSEL(IP7_26_24, SSI_SCK6_B, SEL_SSI6_1), 1145 PINMUX_IPSR_MSEL(IP7_29_27, ETH_TXD0, SEL_ETH_0), 1146 PINMUX_IPSR_GPSR(IP7_29_27, VI0_R2), 1147 PINMUX_IPSR_MSEL(IP7_29_27, SCIF3_RXD_B, SEL_SCIF3_1), 1148 PINMUX_IPSR_MSEL(IP7_29_27, I2C4_SCL_E, SEL_I2C04_4), 1149 PINMUX_IPSR_GPSR(IP7_29_27, AVB_GTX_CLK), 1150 PINMUX_IPSR_MSEL(IP7_29_27, SSI_WS6_B, SEL_SSI6_1), 1151 PINMUX_IPSR_GPSR(IP7_31, DREQ0_N), 1152 PINMUX_IPSR_GPSR(IP7_31, SCIFB1_RXD), 1153 1154 /* IPSR8 */ 1155 PINMUX_IPSR_MSEL(IP8_2_0, ETH_MDC, SEL_ETH_0), 1156 PINMUX_IPSR_GPSR(IP8_2_0, VI0_R3), 1157 PINMUX_IPSR_MSEL(IP8_2_0, SCIF3_TXD_B, SEL_SCIF3_1), 1158 PINMUX_IPSR_MSEL(IP8_2_0, I2C4_SDA_E, SEL_I2C04_4), 1159 PINMUX_IPSR_GPSR(IP8_2_0, AVB_MDC), 1160 PINMUX_IPSR_MSEL(IP8_2_0, SSI_SDATA6_B, SEL_SSI6_1), 1161 PINMUX_IPSR_MSEL(IP8_5_3, HSCIF0_HRX, SEL_HSCIF0_0), 1162 PINMUX_IPSR_GPSR(IP8_5_3, VI0_R4), 1163 PINMUX_IPSR_MSEL(IP8_5_3, I2C1_SCL_C, SEL_I2C01_2), 1164 PINMUX_IPSR_MSEL(IP8_5_3, AUDIO_CLKA_B, SEL_ADG_1), 1165 PINMUX_IPSR_GPSR(IP8_5_3, AVB_MDIO), 1166 PINMUX_IPSR_MSEL(IP8_5_3, SSI_SCK78_B, SEL_SSI7_1), 1167 PINMUX_IPSR_MSEL(IP8_8_6, HSCIF0_HTX, SEL_HSCIF0_0), 1168 PINMUX_IPSR_GPSR(IP8_8_6, VI0_R5), 1169 PINMUX_IPSR_MSEL(IP8_8_6, I2C1_SDA_C, SEL_I2C01_2), 1170 PINMUX_IPSR_MSEL(IP8_8_6, AUDIO_CLKB_B, SEL_ADG_1), 1171 PINMUX_IPSR_GPSR(IP8_5_3, AVB_LINK), 1172 PINMUX_IPSR_MSEL(IP8_8_6, SSI_WS78_B, SEL_SSI7_1), 1173 PINMUX_IPSR_GPSR(IP8_11_9, HSCIF0_HCTS_N), 1174 PINMUX_IPSR_GPSR(IP8_11_9, VI0_R6), 1175 PINMUX_IPSR_MSEL(IP8_11_9, SCIF0_RXD_D, SEL_SCIF0_3), 1176 PINMUX_IPSR_MSEL(IP8_11_9, I2C0_SCL_E, SEL_I2C00_4), 1177 PINMUX_IPSR_GPSR(IP8_11_9, AVB_MAGIC), 1178 PINMUX_IPSR_MSEL(IP8_11_9, SSI_SDATA7_B, SEL_SSI7_1), 1179 PINMUX_IPSR_GPSR(IP8_14_12, HSCIF0_HRTS_N), 1180 PINMUX_IPSR_GPSR(IP8_14_12, VI0_R7), 1181 PINMUX_IPSR_MSEL(IP8_14_12, SCIF0_TXD_D, SEL_SCIF0_3), 1182 PINMUX_IPSR_MSEL(IP8_14_12, I2C0_SDA_E, SEL_I2C00_4), 1183 PINMUX_IPSR_GPSR(IP8_14_12, AVB_PHY_INT), 1184 PINMUX_IPSR_MSEL(IP8_14_12, SSI_SDATA8_B, SEL_SSI8_1), 1185 PINMUX_IPSR_MSEL(IP8_16_15, HSCIF0_HSCK, SEL_HSCIF0_0), 1186 PINMUX_IPSR_MSEL(IP8_16_15, SCIF_CLK_B, SEL_SCIF0_1), 1187 PINMUX_IPSR_GPSR(IP8_16_15, AVB_CRS), 1188 PINMUX_IPSR_MSEL(IP8_16_15, AUDIO_CLKC_B, SEL_ADG_1), 1189 PINMUX_IPSR_MSEL(IP8_19_17, I2C0_SCL, SEL_I2C00_0), 1190 PINMUX_IPSR_MSEL(IP8_19_17, SCIF0_RXD_C, SEL_SCIF0_2), 1191 PINMUX_IPSR_GPSR(IP8_19_17, PWM5), 1192 PINMUX_IPSR_MSEL(IP8_19_17, TCLK1_B, SEL_TMU_1), 1193 PINMUX_IPSR_GPSR(IP8_19_17, AVB_GTXREFCLK), 1194 PINMUX_IPSR_MSEL(IP8_19_17, CAN1_RX_D, SEL_CAN1_3), 1195 PINMUX_IPSR_GPSR(IP8_19_17, TPUTO0_B), 1196 PINMUX_IPSR_MSEL(IP8_22_20, I2C0_SDA, SEL_I2C00_0), 1197 PINMUX_IPSR_MSEL(IP8_22_20, SCIF0_TXD_C, SEL_SCIF0_2), 1198 PINMUX_IPSR_GPSR(IP8_22_20, TPUTO0), 1199 PINMUX_IPSR_MSEL(IP8_22_20, CAN_CLK, SEL_CAN_0), 1200 PINMUX_IPSR_GPSR(IP8_22_20, DVC_MUTE), 1201 PINMUX_IPSR_MSEL(IP8_22_20, CAN1_TX_D, SEL_CAN1_3), 1202 PINMUX_IPSR_MSEL(IP8_25_23, I2C1_SCL, SEL_I2C01_0), 1203 PINMUX_IPSR_MSEL(IP8_25_23, SCIF4_RXD, SEL_SCIF4_0), 1204 PINMUX_IPSR_GPSR(IP8_25_23, PWM5_B), 1205 PINMUX_IPSR_GPSR(IP8_25_23, DU1_DR0), 1206 PINMUX_IPSR_MSEL(IP8_25_23, TS_SDATA_D, SEL_TSIF0_3), 1207 PINMUX_IPSR_GPSR(IP8_25_23, TPUTO1_B), 1208 PINMUX_IPSR_MSEL(IP8_28_26, I2C1_SDA, SEL_I2C01_0), 1209 PINMUX_IPSR_MSEL(IP8_28_26, SCIF4_TXD, SEL_SCIF4_0), 1210 PINMUX_IPSR_GPSR(IP8_28_26, IRQ5), 1211 PINMUX_IPSR_GPSR(IP8_28_26, DU1_DR1), 1212 PINMUX_IPSR_MSEL(IP8_28_26, TS_SCK_D, SEL_TSIF0_3), 1213 PINMUX_IPSR_MSEL(IP8_28_26, BPFCLK_C, SEL_DARC_2), 1214 PINMUX_IPSR_GPSR(IP8_31_29, MSIOF0_RXD), 1215 PINMUX_IPSR_MSEL(IP8_31_29, SCIF5_RXD, SEL_SCIF5_0), 1216 PINMUX_IPSR_MSEL(IP8_31_29, I2C2_SCL_C, SEL_I2C02_2), 1217 PINMUX_IPSR_GPSR(IP8_31_29, DU1_DR2), 1218 PINMUX_IPSR_MSEL(IP8_31_29, TS_SDEN_D, SEL_TSIF0_3), 1219 PINMUX_IPSR_MSEL(IP8_31_29, FMCLK_C, SEL_DARC_2), 1220 1221 /* IPSR9 */ 1222 PINMUX_IPSR_GPSR(IP9_2_0, MSIOF0_TXD), 1223 PINMUX_IPSR_MSEL(IP9_2_0, SCIF5_TXD, SEL_SCIF5_0), 1224 PINMUX_IPSR_MSEL(IP9_2_0, I2C2_SDA_C, SEL_I2C02_2), 1225 PINMUX_IPSR_GPSR(IP9_2_0, DU1_DR3), 1226 PINMUX_IPSR_MSEL(IP9_2_0, TS_SPSYNC_D, SEL_TSIF0_3), 1227 PINMUX_IPSR_MSEL(IP9_2_0, FMIN_C, SEL_DARC_2), 1228 PINMUX_IPSR_GPSR(IP9_5_3, MSIOF0_SCK), 1229 PINMUX_IPSR_GPSR(IP9_5_3, IRQ0), 1230 PINMUX_IPSR_MSEL(IP9_5_3, TS_SDATA, SEL_TSIF0_0), 1231 PINMUX_IPSR_GPSR(IP9_5_3, DU1_DR4), 1232 PINMUX_IPSR_GPSR(IP9_5_3, TPUTO1_C), 1233 PINMUX_IPSR_GPSR(IP9_8_6, MSIOF0_SYNC), 1234 PINMUX_IPSR_GPSR(IP9_8_6, PWM1), 1235 PINMUX_IPSR_MSEL(IP9_8_6, TS_SCK, SEL_TSIF0_0), 1236 PINMUX_IPSR_GPSR(IP9_8_6, DU1_DR5), 1237 PINMUX_IPSR_MSEL(IP9_8_6, BPFCLK_B, SEL_DARC_1), 1238 PINMUX_IPSR_GPSR(IP9_11_9, MSIOF0_SS1), 1239 PINMUX_IPSR_MSEL(IP9_11_9, SCIFA0_RXD, SEL_SCIFA0_0), 1240 PINMUX_IPSR_MSEL(IP9_11_9, TS_SDEN, SEL_TSIF0_0), 1241 PINMUX_IPSR_GPSR(IP9_11_9, DU1_DR6), 1242 PINMUX_IPSR_MSEL(IP9_11_9, FMCLK_B, SEL_DARC_1), 1243 PINMUX_IPSR_GPSR(IP9_14_12, MSIOF0_SS2), 1244 PINMUX_IPSR_MSEL(IP9_14_12, SCIFA0_TXD, SEL_SCIFA0_0), 1245 PINMUX_IPSR_MSEL(IP9_14_12, TS_SPSYNC, SEL_TSIF0_0), 1246 PINMUX_IPSR_GPSR(IP9_14_12, DU1_DR7), 1247 PINMUX_IPSR_MSEL(IP9_14_12, FMIN_B, SEL_DARC_1), 1248 PINMUX_IPSR_MSEL(IP9_16_15, HSCIF1_HRX, SEL_HSCIF1_0), 1249 PINMUX_IPSR_MSEL(IP9_16_15, I2C4_SCL, SEL_I2C04_0), 1250 PINMUX_IPSR_GPSR(IP9_16_15, PWM6), 1251 PINMUX_IPSR_GPSR(IP9_16_15, DU1_DG0), 1252 PINMUX_IPSR_MSEL(IP9_18_17, HSCIF1_HTX, SEL_HSCIF1_0), 1253 PINMUX_IPSR_MSEL(IP9_18_17, I2C4_SDA, SEL_I2C04_0), 1254 PINMUX_IPSR_GPSR(IP9_18_17, TPUTO1), 1255 PINMUX_IPSR_GPSR(IP9_18_17, DU1_DG1), 1256 PINMUX_IPSR_GPSR(IP9_21_19, HSCIF1_HSCK), 1257 PINMUX_IPSR_GPSR(IP9_21_19, PWM2), 1258 PINMUX_IPSR_MSEL(IP9_21_19, IETX, SEL_IEB_0), 1259 PINMUX_IPSR_GPSR(IP9_21_19, DU1_DG2), 1260 PINMUX_IPSR_MSEL(IP9_21_19, REMOCON_B, SEL_RCN_1), 1261 PINMUX_IPSR_MSEL(IP9_21_19, SPEEDIN_B, SEL_RSP_1), 1262 PINMUX_IPSR_MSEL(IP9_24_22, HSCIF1_HCTS_N, SEL_HSCIF1_0), 1263 PINMUX_IPSR_MSEL(IP9_24_22, SCIFA4_RXD, SEL_SCIFA4_0), 1264 PINMUX_IPSR_MSEL(IP9_24_22, IECLK, SEL_IEB_0), 1265 PINMUX_IPSR_GPSR(IP9_24_22, DU1_DG3), 1266 PINMUX_IPSR_MSEL(IP9_24_22, SSI_SCK1_B, SEL_SSI1_1), 1267 PINMUX_IPSR_MSEL(IP9_27_25, HSCIF1_HRTS_N, SEL_HSCIF1_0), 1268 PINMUX_IPSR_MSEL(IP9_27_25, SCIFA4_TXD, SEL_SCIFA4_0), 1269 PINMUX_IPSR_MSEL(IP9_27_25, IERX, SEL_IEB_0), 1270 PINMUX_IPSR_GPSR(IP9_27_25, DU1_DG4), 1271 PINMUX_IPSR_MSEL(IP9_27_25, SSI_WS1_B, SEL_SSI1_1), 1272 PINMUX_IPSR_MSEL(IP9_30_28, SCIF1_SCK, SEL_SCIF1_0), 1273 PINMUX_IPSR_GPSR(IP9_30_28, PWM3), 1274 PINMUX_IPSR_MSEL(IP9_30_28, TCLK2, SEL_TMU_0), 1275 PINMUX_IPSR_GPSR(IP9_30_28, DU1_DG5), 1276 PINMUX_IPSR_MSEL(IP9_30_28, SSI_SDATA1_B, SEL_SSI1_1), 1277 1278 /* IPSR10 */ 1279 PINMUX_IPSR_MSEL(IP10_2_0, SCIF1_RXD, SEL_SCIF1_0), 1280 PINMUX_IPSR_MSEL(IP10_2_0, I2C5_SCL, SEL_I2C05_0), 1281 PINMUX_IPSR_GPSR(IP10_2_0, DU1_DG6), 1282 PINMUX_IPSR_MSEL(IP10_2_0, SSI_SCK2_B, SEL_SSI2_1), 1283 PINMUX_IPSR_MSEL(IP10_5_3, SCIF1_TXD, SEL_SCIF1_0), 1284 PINMUX_IPSR_MSEL(IP10_5_3, I2C5_SDA, SEL_I2C05_0), 1285 PINMUX_IPSR_GPSR(IP10_5_3, DU1_DG7), 1286 PINMUX_IPSR_MSEL(IP10_5_3, SSI_WS2_B, SEL_SSI2_1), 1287 PINMUX_IPSR_MSEL(IP10_8_6, SCIF2_RXD, SEL_SCIF2_0), 1288 PINMUX_IPSR_MSEL(IP10_8_6, IIC0_SCL, SEL_IIC0_0), 1289 PINMUX_IPSR_GPSR(IP10_8_6, DU1_DB0), 1290 PINMUX_IPSR_MSEL(IP10_8_6, SSI_SDATA2_B, SEL_SSI2_1), 1291 PINMUX_IPSR_MSEL(IP10_11_9, SCIF2_TXD, SEL_SCIF2_0), 1292 PINMUX_IPSR_MSEL(IP10_11_9, IIC0_SDA, SEL_IIC0_0), 1293 PINMUX_IPSR_GPSR(IP10_11_9, DU1_DB1), 1294 PINMUX_IPSR_MSEL(IP10_11_9, SSI_SCK9_B, SEL_SSI9_1), 1295 PINMUX_IPSR_MSEL(IP10_14_12, SCIF2_SCK, SEL_SCIF2_0), 1296 PINMUX_IPSR_GPSR(IP10_14_12, IRQ1), 1297 PINMUX_IPSR_GPSR(IP10_14_12, DU1_DB2), 1298 PINMUX_IPSR_MSEL(IP10_14_12, SSI_WS9_B, SEL_SSI9_1), 1299 PINMUX_IPSR_MSEL(IP10_17_15, SCIF3_SCK, SEL_SCIF3_0), 1300 PINMUX_IPSR_GPSR(IP10_17_15, IRQ2), 1301 PINMUX_IPSR_MSEL(IP10_17_15, BPFCLK_D, SEL_DARC_3), 1302 PINMUX_IPSR_GPSR(IP10_17_15, DU1_DB3), 1303 PINMUX_IPSR_MSEL(IP10_17_15, SSI_SDATA9_B, SEL_SSI9_1), 1304 PINMUX_IPSR_MSEL(IP10_20_18, SCIF3_RXD, SEL_SCIF3_0), 1305 PINMUX_IPSR_MSEL(IP10_20_18, I2C1_SCL_E, SEL_I2C01_4), 1306 PINMUX_IPSR_MSEL(IP10_20_18, FMCLK_D, SEL_DARC_3), 1307 PINMUX_IPSR_GPSR(IP10_20_18, DU1_DB4), 1308 PINMUX_IPSR_MSEL(IP10_20_18, AUDIO_CLKA_C, SEL_ADG_2), 1309 PINMUX_IPSR_MSEL(IP10_20_18, SSI_SCK4_B, SEL_SSI4_1), 1310 PINMUX_IPSR_MSEL(IP10_23_21, SCIF3_TXD, SEL_SCIF3_0), 1311 PINMUX_IPSR_MSEL(IP10_23_21, I2C1_SDA_E, SEL_I2C01_4), 1312 PINMUX_IPSR_MSEL(IP10_23_21, FMIN_D, SEL_DARC_3), 1313 PINMUX_IPSR_GPSR(IP10_23_21, DU1_DB5), 1314 PINMUX_IPSR_MSEL(IP10_23_21, AUDIO_CLKB_C, SEL_ADG_2), 1315 PINMUX_IPSR_MSEL(IP10_23_21, SSI_WS4_B, SEL_SSI4_1), 1316 PINMUX_IPSR_MSEL(IP10_26_24, I2C2_SCL, SEL_I2C02_0), 1317 PINMUX_IPSR_MSEL(IP10_26_24, SCIFA5_RXD, SEL_SCIFA5_0), 1318 PINMUX_IPSR_GPSR(IP10_26_24, DU1_DB6), 1319 PINMUX_IPSR_MSEL(IP10_26_24, AUDIO_CLKC_C, SEL_ADG_2), 1320 PINMUX_IPSR_MSEL(IP10_26_24, SSI_SDATA4_B, SEL_SSI4_1), 1321 PINMUX_IPSR_MSEL(IP10_29_27, I2C2_SDA, SEL_I2C02_0), 1322 PINMUX_IPSR_MSEL(IP10_29_27, SCIFA5_TXD, SEL_SCIFA5_0), 1323 PINMUX_IPSR_GPSR(IP10_29_27, DU1_DB7), 1324 PINMUX_IPSR_MSEL(IP10_29_27, AUDIO_CLKOUT_C, SEL_ADG_2), 1325 PINMUX_IPSR_MSEL(IP10_31_30, SSI_SCK5, SEL_SSI5_0), 1326 PINMUX_IPSR_MSEL(IP10_31_30, SCIFA3_SCK, SEL_SCIFA3_0), 1327 PINMUX_IPSR_GPSR(IP10_31_30, DU1_DOTCLKIN), 1328 1329 /* IPSR11 */ 1330 PINMUX_IPSR_MSEL(IP11_2_0, SSI_WS5, SEL_SSI5_0), 1331 PINMUX_IPSR_MSEL(IP11_2_0, SCIFA3_RXD, SEL_SCIFA3_0), 1332 PINMUX_IPSR_MSEL(IP11_2_0, I2C3_SCL_C, SEL_I2C03_2), 1333 PINMUX_IPSR_GPSR(IP11_2_0, DU1_DOTCLKOUT0), 1334 PINMUX_IPSR_MSEL(IP11_5_3, SSI_SDATA5, SEL_SSI5_0), 1335 PINMUX_IPSR_MSEL(IP11_5_3, SCIFA3_TXD, SEL_SCIFA3_0), 1336 PINMUX_IPSR_MSEL(IP11_5_3, I2C3_SDA_C, SEL_I2C03_2), 1337 PINMUX_IPSR_GPSR(IP11_5_3, DU1_DOTCLKOUT1), 1338 PINMUX_IPSR_MSEL(IP11_7_6, SSI_SCK6, SEL_SSI6_0), 1339 PINMUX_IPSR_MSEL(IP11_7_6, SCIFA1_SCK_B, SEL_SCIFA1_1), 1340 PINMUX_IPSR_GPSR(IP11_7_6, DU1_EXHSYNC_DU1_HSYNC), 1341 PINMUX_IPSR_MSEL(IP11_10_8, SSI_WS6, SEL_SSI6_0), 1342 PINMUX_IPSR_MSEL(IP11_10_8, SCIFA1_RXD_B, SEL_SCIFA1_1), 1343 PINMUX_IPSR_MSEL(IP11_10_8, I2C4_SCL_C, SEL_I2C04_2), 1344 PINMUX_IPSR_GPSR(IP11_10_8, DU1_EXVSYNC_DU1_VSYNC), 1345 PINMUX_IPSR_MSEL(IP11_13_11, SSI_SDATA6, SEL_SSI6_0), 1346 PINMUX_IPSR_MSEL(IP11_13_11, SCIFA1_TXD_B, SEL_SCIFA1_1), 1347 PINMUX_IPSR_MSEL(IP11_13_11, I2C4_SDA_C, SEL_I2C04_2), 1348 PINMUX_IPSR_GPSR(IP11_13_11, DU1_EXODDF_DU1_ODDF_DISP_CDE), 1349 PINMUX_IPSR_MSEL(IP11_15_14, SSI_SCK78, SEL_SSI7_0), 1350 PINMUX_IPSR_MSEL(IP11_15_14, SCIFA2_SCK_B, SEL_SCIFA2_1), 1351 PINMUX_IPSR_MSEL(IP11_15_14, I2C5_SDA_C, SEL_I2C05_2), 1352 PINMUX_IPSR_GPSR(IP11_15_14, DU1_DISP), 1353 PINMUX_IPSR_MSEL(IP11_17_16, SSI_WS78, SEL_SSI7_0), 1354 PINMUX_IPSR_MSEL(IP11_17_16, SCIFA2_RXD_B, SEL_SCIFA2_1), 1355 PINMUX_IPSR_MSEL(IP11_17_16, I2C5_SCL_C, SEL_I2C05_2), 1356 PINMUX_IPSR_GPSR(IP11_17_16, DU1_CDE), 1357 PINMUX_IPSR_MSEL(IP11_20_18, SSI_SDATA7, SEL_SSI7_0), 1358 PINMUX_IPSR_MSEL(IP11_20_18, SCIFA2_TXD_B, SEL_SCIFA2_1), 1359 PINMUX_IPSR_GPSR(IP11_20_18, IRQ8), 1360 PINMUX_IPSR_MSEL(IP11_20_18, AUDIO_CLKA_D, SEL_ADG_3), 1361 PINMUX_IPSR_MSEL(IP11_20_18, CAN_CLK_D, SEL_CAN_3), 1362 PINMUX_IPSR_GPSR(IP11_23_21, SSI_SCK0129), 1363 PINMUX_IPSR_MSEL(IP11_23_21, MSIOF1_RXD_B, SEL_MSI1_1), 1364 PINMUX_IPSR_MSEL(IP11_23_21, SCIF5_RXD_D, SEL_SCIF5_3), 1365 PINMUX_IPSR_MSEL(IP11_23_21, ADIDATA_B, SEL_RAD_1), 1366 PINMUX_IPSR_GPSR(IP11_26_24, SSI_WS0129), 1367 PINMUX_IPSR_MSEL(IP11_26_24, MSIOF1_TXD_B, SEL_MSI1_1), 1368 PINMUX_IPSR_MSEL(IP11_26_24, SCIF5_TXD_D, SEL_SCIF5_3), 1369 PINMUX_IPSR_MSEL(IP11_26_24, ADICS_SAMP_B, SEL_RAD_1), 1370 PINMUX_IPSR_GPSR(IP11_29_27, SSI_SDATA0), 1371 PINMUX_IPSR_MSEL(IP11_29_27, MSIOF1_SCK_B, SEL_MSI1_1), 1372 PINMUX_IPSR_GPSR(IP11_29_27, PWM0_B), 1373 PINMUX_IPSR_MSEL(IP11_29_27, ADICLK_B, SEL_RAD_1), 1374 1375 /* IPSR12 */ 1376 PINMUX_IPSR_GPSR(IP12_2_0, SSI_SCK34), 1377 PINMUX_IPSR_MSEL(IP12_2_0, MSIOF1_SYNC_B, SEL_MSI1_1), 1378 PINMUX_IPSR_MSEL(IP12_2_0, SCIFA1_SCK_C, SEL_SCIFA1_2), 1379 PINMUX_IPSR_MSEL(IP12_2_0, ADICHS0_B, SEL_RAD_1), 1380 PINMUX_IPSR_MSEL(IP12_2_0, DREQ1_N_B, SEL_LBS_1), 1381 PINMUX_IPSR_GPSR(IP12_5_3, SSI_WS34), 1382 PINMUX_IPSR_MSEL(IP12_5_3, MSIOF1_SS1_B, SEL_MSI1_1), 1383 PINMUX_IPSR_MSEL(IP12_5_3, SCIFA1_RXD_C, SEL_SCIFA1_2), 1384 PINMUX_IPSR_MSEL(IP12_5_3, ADICHS1_B, SEL_RAD_1), 1385 PINMUX_IPSR_MSEL(IP12_5_3, CAN1_RX_C, SEL_CAN1_2), 1386 PINMUX_IPSR_MSEL(IP12_5_3, DACK1_B, SEL_LBS_1), 1387 PINMUX_IPSR_GPSR(IP12_8_6, SSI_SDATA3), 1388 PINMUX_IPSR_MSEL(IP12_8_6, MSIOF1_SS2_B, SEL_MSI1_1), 1389 PINMUX_IPSR_MSEL(IP12_8_6, SCIFA1_TXD_C, SEL_SCIFA1_2), 1390 PINMUX_IPSR_MSEL(IP12_8_6, ADICHS2_B, SEL_RAD_1), 1391 PINMUX_IPSR_MSEL(IP12_8_6, CAN1_TX_C, SEL_CAN1_2), 1392 PINMUX_IPSR_GPSR(IP12_8_6, DREQ2_N), 1393 PINMUX_IPSR_MSEL(IP12_10_9, SSI_SCK4, SEL_SSI4_0), 1394 PINMUX_IPSR_GPSR(IP12_10_9, MLB_CLK), 1395 PINMUX_IPSR_MSEL(IP12_10_9, IETX_B, SEL_IEB_1), 1396 PINMUX_IPSR_MSEL(IP12_12_11, SSI_WS4, SEL_SSI4_0), 1397 PINMUX_IPSR_GPSR(IP12_12_11, MLB_SIG), 1398 PINMUX_IPSR_MSEL(IP12_12_11, IECLK_B, SEL_IEB_1), 1399 PINMUX_IPSR_MSEL(IP12_14_13, SSI_SDATA4, SEL_SSI4_0), 1400 PINMUX_IPSR_GPSR(IP12_14_13, MLB_DAT), 1401 PINMUX_IPSR_MSEL(IP12_14_13, IERX_B, SEL_IEB_1), 1402 PINMUX_IPSR_MSEL(IP12_17_15, SSI_SDATA8, SEL_SSI8_0), 1403 PINMUX_IPSR_MSEL(IP12_17_15, SCIF1_SCK_B, SEL_SCIF1_1), 1404 PINMUX_IPSR_GPSR(IP12_17_15, PWM1_B), 1405 PINMUX_IPSR_GPSR(IP12_17_15, IRQ9), 1406 PINMUX_IPSR_MSEL(IP12_17_15, REMOCON, SEL_RCN_0), 1407 PINMUX_IPSR_GPSR(IP12_17_15, DACK2), 1408 PINMUX_IPSR_MSEL(IP12_17_15, ETH_MDIO_B, SEL_ETH_1), 1409 PINMUX_IPSR_MSEL(IP12_20_18, SSI_SCK1, SEL_SSI1_0), 1410 PINMUX_IPSR_MSEL(IP12_20_18, SCIF1_RXD_B, SEL_SCIF1_1), 1411 PINMUX_IPSR_MSEL(IP12_20_18, IIC0_SCL_C, SEL_IIC0_2), 1412 PINMUX_IPSR_GPSR(IP12_20_18, VI1_CLK), 1413 PINMUX_IPSR_MSEL(IP12_20_18, CAN0_RX_D, SEL_CAN0_3), 1414 PINMUX_IPSR_MSEL(IP12_20_18, ETH_CRS_DV_B, SEL_ETH_1), 1415 PINMUX_IPSR_MSEL(IP12_23_21, SSI_WS1, SEL_SSI1_0), 1416 PINMUX_IPSR_MSEL(IP12_23_21, SCIF1_TXD_B, SEL_SCIF1_1), 1417 PINMUX_IPSR_MSEL(IP12_23_21, IIC0_SDA_C, SEL_IIC0_2), 1418 PINMUX_IPSR_GPSR(IP12_23_21, VI1_DATA0), 1419 PINMUX_IPSR_MSEL(IP12_23_21, CAN0_TX_D, SEL_CAN0_3), 1420 PINMUX_IPSR_MSEL(IP12_23_21, ETH_RX_ER_B, SEL_ETH_1), 1421 PINMUX_IPSR_MSEL(IP12_26_24, SSI_SDATA1, SEL_SSI1_0), 1422 PINMUX_IPSR_MSEL(IP12_26_24, HSCIF1_HRX_B, SEL_HSCIF1_1), 1423 PINMUX_IPSR_GPSR(IP12_26_24, VI1_DATA1), 1424 PINMUX_IPSR_GPSR(IP12_26_24, ATAWR0_N), 1425 PINMUX_IPSR_MSEL(IP12_26_24, ETH_RXD0_B, SEL_ETH_1), 1426 PINMUX_IPSR_MSEL(IP12_29_27, SSI_SCK2, SEL_SSI2_0), 1427 PINMUX_IPSR_MSEL(IP12_29_27, HSCIF1_HTX_B, SEL_HSCIF1_1), 1428 PINMUX_IPSR_GPSR(IP12_29_27, VI1_DATA2), 1429 PINMUX_IPSR_GPSR(IP12_29_27, ATAG0_N), 1430 PINMUX_IPSR_MSEL(IP12_29_27, ETH_RXD1_B, SEL_ETH_1), 1431 1432 /* IPSR13 */ 1433 PINMUX_IPSR_MSEL(IP13_2_0, SSI_WS2, SEL_SSI2_0), 1434 PINMUX_IPSR_MSEL(IP13_2_0, HSCIF1_HCTS_N_B, SEL_HSCIF1_1), 1435 PINMUX_IPSR_MSEL(IP13_2_0, SCIFA0_RXD_D, SEL_SCIFA0_3), 1436 PINMUX_IPSR_GPSR(IP13_2_0, VI1_DATA3), 1437 PINMUX_IPSR_GPSR(IP13_2_0, ATACS00_N), 1438 PINMUX_IPSR_MSEL(IP13_2_0, ETH_LINK_B, SEL_ETH_1), 1439 PINMUX_IPSR_MSEL(IP13_5_3, SSI_SDATA2, SEL_SSI2_0), 1440 PINMUX_IPSR_MSEL(IP13_5_3, HSCIF1_HRTS_N_B, SEL_HSCIF1_1), 1441 PINMUX_IPSR_MSEL(IP13_5_3, SCIFA0_TXD_D, SEL_SCIFA0_3), 1442 PINMUX_IPSR_GPSR(IP13_5_3, VI1_DATA4), 1443 PINMUX_IPSR_GPSR(IP13_5_3, ATACS10_N), 1444 PINMUX_IPSR_MSEL(IP13_5_3, ETH_REFCLK_B, SEL_ETH_1), 1445 PINMUX_IPSR_MSEL(IP13_8_6, SSI_SCK9, SEL_SSI9_0), 1446 PINMUX_IPSR_MSEL(IP13_8_6, SCIF2_SCK_B, SEL_SCIF2_1), 1447 PINMUX_IPSR_GPSR(IP13_8_6, PWM2_B), 1448 PINMUX_IPSR_GPSR(IP13_8_6, VI1_DATA5), 1449 PINMUX_IPSR_GPSR(IP13_8_6, EX_WAIT1), 1450 PINMUX_IPSR_MSEL(IP13_8_6, ETH_TXD1_B, SEL_ETH_1), 1451 PINMUX_IPSR_MSEL(IP13_11_9, SSI_WS9, SEL_SSI9_0), 1452 PINMUX_IPSR_MSEL(IP13_11_9, SCIF2_RXD_B, SEL_SCIF2_1), 1453 PINMUX_IPSR_MSEL(IP13_11_9, I2C3_SCL_E, SEL_I2C03_4), 1454 PINMUX_IPSR_GPSR(IP13_11_9, VI1_DATA6), 1455 PINMUX_IPSR_GPSR(IP13_11_9, ATARD0_N), 1456 PINMUX_IPSR_MSEL(IP13_11_9, ETH_TX_EN_B, SEL_ETH_1), 1457 PINMUX_IPSR_MSEL(IP13_14_12, SSI_SDATA9, SEL_SSI9_0), 1458 PINMUX_IPSR_MSEL(IP13_14_12, SCIF2_TXD_B, SEL_SCIF2_1), 1459 PINMUX_IPSR_MSEL(IP13_14_12, I2C3_SDA_E, SEL_I2C03_4), 1460 PINMUX_IPSR_GPSR(IP13_14_12, VI1_DATA7), 1461 PINMUX_IPSR_GPSR(IP13_14_12, ATADIR0_N), 1462 PINMUX_IPSR_MSEL(IP13_14_12, ETH_MAGIC_B, SEL_ETH_1), 1463 PINMUX_IPSR_MSEL(IP13_17_15, AUDIO_CLKA, SEL_ADG_0), 1464 PINMUX_IPSR_MSEL(IP13_17_15, I2C0_SCL_B, SEL_I2C00_1), 1465 PINMUX_IPSR_MSEL(IP13_17_15, SCIFA4_RXD_D, SEL_SCIFA4_3), 1466 PINMUX_IPSR_GPSR(IP13_17_15, VI1_CLKENB), 1467 PINMUX_IPSR_MSEL(IP13_17_15, TS_SDATA_C, SEL_TSIF0_2), 1468 PINMUX_IPSR_MSEL(IP13_17_15, ETH_TXD0_B, SEL_ETH_1), 1469 PINMUX_IPSR_MSEL(IP13_20_18, AUDIO_CLKB, SEL_ADG_0), 1470 PINMUX_IPSR_MSEL(IP13_20_18, I2C0_SDA_B, SEL_I2C00_1), 1471 PINMUX_IPSR_MSEL(IP13_20_18, SCIFA4_TXD_D, SEL_SCIFA4_3), 1472 PINMUX_IPSR_GPSR(IP13_20_18, VI1_FIELD), 1473 PINMUX_IPSR_MSEL(IP13_20_18, TS_SCK_C, SEL_TSIF0_2), 1474 PINMUX_IPSR_MSEL(IP13_20_18, BPFCLK_E, SEL_DARC_4), 1475 PINMUX_IPSR_MSEL(IP13_20_18, ETH_MDC_B, SEL_ETH_1), 1476 PINMUX_IPSR_MSEL(IP13_23_21, AUDIO_CLKC, SEL_ADG_0), 1477 PINMUX_IPSR_MSEL(IP13_23_21, I2C4_SCL_B, SEL_I2C04_1), 1478 PINMUX_IPSR_MSEL(IP13_23_21, SCIFA5_RXD_D, SEL_SCIFA5_3), 1479 PINMUX_IPSR_GPSR(IP13_23_21, VI1_HSYNC_N), 1480 PINMUX_IPSR_MSEL(IP13_23_21, TS_SDEN_C, SEL_TSIF0_2), 1481 PINMUX_IPSR_MSEL(IP13_23_21, FMCLK_E, SEL_DARC_4), 1482 PINMUX_IPSR_MSEL(IP13_26_24, AUDIO_CLKOUT, SEL_ADG_0), 1483 PINMUX_IPSR_MSEL(IP13_26_24, I2C4_SDA_B, SEL_I2C04_1), 1484 PINMUX_IPSR_MSEL(IP13_26_24, SCIFA5_TXD_D, SEL_SCIFA5_3), 1485 PINMUX_IPSR_GPSR(IP13_26_24, VI1_VSYNC_N), 1486 PINMUX_IPSR_MSEL(IP13_26_24, TS_SPSYNC_C, SEL_TSIF0_2), 1487 PINMUX_IPSR_MSEL(IP13_26_24, FMIN_E, SEL_DARC_4), 1488 }; 1489 1490 /* 1491 * Pins not associated with a GPIO port. 1492 */ 1493 enum { 1494 GP_ASSIGN_LAST(), 1495 NOGP_ALL(), 1496 }; 1497 1498 static const struct sh_pfc_pin pinmux_pins[] = { 1499 PINMUX_GPIO_GP_ALL(), 1500 PINMUX_NOGP_ALL(), 1501 }; 1502 1503 /* - Audio Clock ------------------------------------------------------------ */ 1504 static const unsigned int audio_clka_pins[] = { 1505 /* CLKA */ 1506 RCAR_GP_PIN(5, 20), 1507 }; 1508 static const unsigned int audio_clka_mux[] = { 1509 AUDIO_CLKA_MARK, 1510 }; 1511 static const unsigned int audio_clka_b_pins[] = { 1512 /* CLKA */ 1513 RCAR_GP_PIN(3, 25), 1514 }; 1515 static const unsigned int audio_clka_b_mux[] = { 1516 AUDIO_CLKA_B_MARK, 1517 }; 1518 static const unsigned int audio_clka_c_pins[] = { 1519 /* CLKA */ 1520 RCAR_GP_PIN(4, 20), 1521 }; 1522 static const unsigned int audio_clka_c_mux[] = { 1523 AUDIO_CLKA_C_MARK, 1524 }; 1525 static const unsigned int audio_clka_d_pins[] = { 1526 /* CLKA */ 1527 RCAR_GP_PIN(5, 0), 1528 }; 1529 static const unsigned int audio_clka_d_mux[] = { 1530 AUDIO_CLKA_D_MARK, 1531 }; 1532 static const unsigned int audio_clkb_pins[] = { 1533 /* CLKB */ 1534 RCAR_GP_PIN(5, 21), 1535 }; 1536 static const unsigned int audio_clkb_mux[] = { 1537 AUDIO_CLKB_MARK, 1538 }; 1539 static const unsigned int audio_clkb_b_pins[] = { 1540 /* CLKB */ 1541 RCAR_GP_PIN(3, 26), 1542 }; 1543 static const unsigned int audio_clkb_b_mux[] = { 1544 AUDIO_CLKB_B_MARK, 1545 }; 1546 static const unsigned int audio_clkb_c_pins[] = { 1547 /* CLKB */ 1548 RCAR_GP_PIN(4, 21), 1549 }; 1550 static const unsigned int audio_clkb_c_mux[] = { 1551 AUDIO_CLKB_C_MARK, 1552 }; 1553 static const unsigned int audio_clkc_pins[] = { 1554 /* CLKC */ 1555 RCAR_GP_PIN(5, 22), 1556 }; 1557 static const unsigned int audio_clkc_mux[] = { 1558 AUDIO_CLKC_MARK, 1559 }; 1560 static const unsigned int audio_clkc_b_pins[] = { 1561 /* CLKC */ 1562 RCAR_GP_PIN(3, 29), 1563 }; 1564 static const unsigned int audio_clkc_b_mux[] = { 1565 AUDIO_CLKC_B_MARK, 1566 }; 1567 static const unsigned int audio_clkc_c_pins[] = { 1568 /* CLKC */ 1569 RCAR_GP_PIN(4, 22), 1570 }; 1571 static const unsigned int audio_clkc_c_mux[] = { 1572 AUDIO_CLKC_C_MARK, 1573 }; 1574 static const unsigned int audio_clkout_pins[] = { 1575 /* CLKOUT */ 1576 RCAR_GP_PIN(5, 23), 1577 }; 1578 static const unsigned int audio_clkout_mux[] = { 1579 AUDIO_CLKOUT_MARK, 1580 }; 1581 static const unsigned int audio_clkout_b_pins[] = { 1582 /* CLKOUT */ 1583 RCAR_GP_PIN(3, 12), 1584 }; 1585 static const unsigned int audio_clkout_b_mux[] = { 1586 AUDIO_CLKOUT_B_MARK, 1587 }; 1588 static const unsigned int audio_clkout_c_pins[] = { 1589 /* CLKOUT */ 1590 RCAR_GP_PIN(4, 23), 1591 }; 1592 static const unsigned int audio_clkout_c_mux[] = { 1593 AUDIO_CLKOUT_C_MARK, 1594 }; 1595 /* - AVB -------------------------------------------------------------------- */ 1596 static const unsigned int avb_link_pins[] = { 1597 RCAR_GP_PIN(3, 26), 1598 }; 1599 static const unsigned int avb_link_mux[] = { 1600 AVB_LINK_MARK, 1601 }; 1602 static const unsigned int avb_magic_pins[] = { 1603 RCAR_GP_PIN(3, 27), 1604 }; 1605 static const unsigned int avb_magic_mux[] = { 1606 AVB_MAGIC_MARK, 1607 }; 1608 static const unsigned int avb_phy_int_pins[] = { 1609 RCAR_GP_PIN(3, 28), 1610 }; 1611 static const unsigned int avb_phy_int_mux[] = { 1612 AVB_PHY_INT_MARK, 1613 }; 1614 static const unsigned int avb_mdio_pins[] = { 1615 RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25), 1616 }; 1617 static const unsigned int avb_mdio_mux[] = { 1618 AVB_MDC_MARK, AVB_MDIO_MARK, 1619 }; 1620 static const unsigned int avb_mii_pins[] = { 1621 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16), 1622 RCAR_GP_PIN(3, 17), 1623 1624 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4), 1625 RCAR_GP_PIN(3, 5), 1626 1627 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1), 1628 RCAR_GP_PIN(3, 29), RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 22), 1629 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 11), 1630 }; 1631 static const unsigned int avb_mii_mux[] = { 1632 AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK, 1633 AVB_TXD3_MARK, 1634 1635 AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK, 1636 AVB_RXD3_MARK, 1637 1638 AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK, 1639 AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_ER_MARK, 1640 AVB_TX_CLK_MARK, AVB_COL_MARK, 1641 }; 1642 static const unsigned int avb_gmii_pins[] = { 1643 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16), 1644 RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), 1645 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21), 1646 1647 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4), 1648 RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), 1649 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), 1650 1651 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1), 1652 RCAR_GP_PIN(3, 29), RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 30), 1653 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 13), 1654 RCAR_GP_PIN(3, 11), 1655 }; 1656 static const unsigned int avb_gmii_mux[] = { 1657 AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK, 1658 AVB_TXD3_MARK, AVB_TXD4_MARK, AVB_TXD5_MARK, 1659 AVB_TXD6_MARK, AVB_TXD7_MARK, 1660 1661 AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK, 1662 AVB_RXD3_MARK, AVB_RXD4_MARK, AVB_RXD5_MARK, 1663 AVB_RXD6_MARK, AVB_RXD7_MARK, 1664 1665 AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK, 1666 AVB_CRS_MARK, AVB_GTX_CLK_MARK, AVB_GTXREFCLK_MARK, 1667 AVB_TX_EN_MARK, AVB_TX_ER_MARK, AVB_TX_CLK_MARK, 1668 AVB_COL_MARK, 1669 }; 1670 1671 /* - CAN -------------------------------------------------------------------- */ 1672 static const unsigned int can0_data_pins[] = { 1673 /* TX, RX */ 1674 RCAR_GP_PIN(6, 15), RCAR_GP_PIN(6, 14), 1675 }; 1676 1677 static const unsigned int can0_data_mux[] = { 1678 CAN0_TX_MARK, CAN0_RX_MARK, 1679 }; 1680 1681 static const unsigned int can0_data_b_pins[] = { 1682 /* TX, RX */ 1683 RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 15), 1684 }; 1685 1686 static const unsigned int can0_data_b_mux[] = { 1687 CAN0_TX_B_MARK, CAN0_RX_B_MARK, 1688 }; 1689 1690 static const unsigned int can0_data_c_pins[] = { 1691 /* TX, RX */ 1692 RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 16), 1693 }; 1694 1695 static const unsigned int can0_data_c_mux[] = { 1696 CAN0_TX_C_MARK, CAN0_RX_C_MARK, 1697 }; 1698 1699 static const unsigned int can0_data_d_pins[] = { 1700 /* TX, RX */ 1701 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 11), 1702 }; 1703 1704 static const unsigned int can0_data_d_mux[] = { 1705 CAN0_TX_D_MARK, CAN0_RX_D_MARK, 1706 }; 1707 1708 static const unsigned int can1_data_pins[] = { 1709 /* TX, RX */ 1710 RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 24), 1711 }; 1712 1713 static const unsigned int can1_data_mux[] = { 1714 CAN1_TX_MARK, CAN1_RX_MARK, 1715 }; 1716 1717 static const unsigned int can1_data_b_pins[] = { 1718 /* TX, RX */ 1719 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 1), 1720 }; 1721 1722 static const unsigned int can1_data_b_mux[] = { 1723 CAN1_TX_B_MARK, CAN1_RX_B_MARK, 1724 }; 1725 1726 static const unsigned int can1_data_c_pins[] = { 1727 /* TX, RX */ 1728 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 5), 1729 }; 1730 1731 static const unsigned int can1_data_c_mux[] = { 1732 CAN1_TX_C_MARK, CAN1_RX_C_MARK, 1733 }; 1734 1735 static const unsigned int can1_data_d_pins[] = { 1736 /* TX, RX */ 1737 RCAR_GP_PIN(3, 31), RCAR_GP_PIN(3, 30), 1738 }; 1739 1740 static const unsigned int can1_data_d_mux[] = { 1741 CAN1_TX_D_MARK, CAN1_RX_D_MARK, 1742 }; 1743 1744 static const unsigned int can_clk_pins[] = { 1745 /* CLK */ 1746 RCAR_GP_PIN(3, 31), 1747 }; 1748 1749 static const unsigned int can_clk_mux[] = { 1750 CAN_CLK_MARK, 1751 }; 1752 1753 static const unsigned int can_clk_b_pins[] = { 1754 /* CLK */ 1755 RCAR_GP_PIN(1, 23), 1756 }; 1757 1758 static const unsigned int can_clk_b_mux[] = { 1759 CAN_CLK_B_MARK, 1760 }; 1761 1762 static const unsigned int can_clk_c_pins[] = { 1763 /* CLK */ 1764 RCAR_GP_PIN(1, 0), 1765 }; 1766 1767 static const unsigned int can_clk_c_mux[] = { 1768 CAN_CLK_C_MARK, 1769 }; 1770 1771 static const unsigned int can_clk_d_pins[] = { 1772 /* CLK */ 1773 RCAR_GP_PIN(5, 0), 1774 }; 1775 1776 static const unsigned int can_clk_d_mux[] = { 1777 CAN_CLK_D_MARK, 1778 }; 1779 1780 /* - DU --------------------------------------------------------------------- */ 1781 static const unsigned int du0_rgb666_pins[] = { 1782 /* R[7:2], G[7:2], B[7:2] */ 1783 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 5), 1784 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2), 1785 RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13), 1786 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10), 1787 RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22), RCAR_GP_PIN(2, 21), 1788 RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 18), 1789 }; 1790 static const unsigned int du0_rgb666_mux[] = { 1791 DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK, 1792 DU0_DR3_MARK, DU0_DR2_MARK, 1793 DU0_DG7_MARK, DU0_DG6_MARK, DU0_DG5_MARK, DU0_DG4_MARK, 1794 DU0_DG3_MARK, DU0_DG2_MARK, 1795 DU0_DB7_MARK, DU0_DB6_MARK, DU0_DB5_MARK, DU0_DB4_MARK, 1796 DU0_DB3_MARK, DU0_DB2_MARK, 1797 }; 1798 static const unsigned int du0_rgb888_pins[] = { 1799 /* R[7:0], G[7:0], B[7:0] */ 1800 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 5), 1801 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2), 1802 RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 0), 1803 RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13), 1804 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10), 1805 RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 8), 1806 RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22), RCAR_GP_PIN(2, 21), 1807 RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 18), 1808 RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 16), 1809 }; 1810 static const unsigned int du0_rgb888_mux[] = { 1811 DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK, 1812 DU0_DR3_MARK, DU0_DR2_MARK, DU0_DR1_MARK, DU0_DR0_MARK, 1813 DU0_DG7_MARK, DU0_DG6_MARK, DU0_DG5_MARK, DU0_DG4_MARK, 1814 DU0_DG3_MARK, DU0_DG2_MARK, DU0_DG1_MARK, DU0_DG0_MARK, 1815 DU0_DB7_MARK, DU0_DB6_MARK, DU0_DB5_MARK, DU0_DB4_MARK, 1816 DU0_DB3_MARK, DU0_DB2_MARK, DU0_DB1_MARK, DU0_DB0_MARK, 1817 }; 1818 static const unsigned int du0_clk0_out_pins[] = { 1819 /* DOTCLKOUT0 */ 1820 RCAR_GP_PIN(2, 25), 1821 }; 1822 static const unsigned int du0_clk0_out_mux[] = { 1823 DU0_DOTCLKOUT0_MARK 1824 }; 1825 static const unsigned int du0_clk1_out_pins[] = { 1826 /* DOTCLKOUT1 */ 1827 RCAR_GP_PIN(2, 26), 1828 }; 1829 static const unsigned int du0_clk1_out_mux[] = { 1830 DU0_DOTCLKOUT1_MARK 1831 }; 1832 static const unsigned int du0_clk_in_pins[] = { 1833 /* CLKIN */ 1834 RCAR_GP_PIN(2, 24), 1835 }; 1836 static const unsigned int du0_clk_in_mux[] = { 1837 DU0_DOTCLKIN_MARK 1838 }; 1839 static const unsigned int du0_sync_pins[] = { 1840 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */ 1841 RCAR_GP_PIN(2, 28), RCAR_GP_PIN(2, 27), 1842 }; 1843 static const unsigned int du0_sync_mux[] = { 1844 DU0_EXVSYNC_DU0_VSYNC_MARK, DU0_EXHSYNC_DU0_HSYNC_MARK 1845 }; 1846 static const unsigned int du0_oddf_pins[] = { 1847 /* EXODDF/ODDF/DISP/CDE */ 1848 RCAR_GP_PIN(2, 29), 1849 }; 1850 static const unsigned int du0_oddf_mux[] = { 1851 DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, 1852 }; 1853 static const unsigned int du0_cde_pins[] = { 1854 /* CDE */ 1855 RCAR_GP_PIN(2, 31), 1856 }; 1857 static const unsigned int du0_cde_mux[] = { 1858 DU0_CDE_MARK, 1859 }; 1860 static const unsigned int du0_disp_pins[] = { 1861 /* DISP */ 1862 RCAR_GP_PIN(2, 30), 1863 }; 1864 static const unsigned int du0_disp_mux[] = { 1865 DU0_DISP_MARK 1866 }; 1867 static const unsigned int du1_rgb666_pins[] = { 1868 /* R[7:2], G[7:2], B[7:2] */ 1869 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 5), 1870 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2), 1871 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13), 1872 RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 10), 1873 RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 21), 1874 RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 18), 1875 }; 1876 static const unsigned int du1_rgb666_mux[] = { 1877 DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK, 1878 DU1_DR3_MARK, DU1_DR2_MARK, 1879 DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK, 1880 DU1_DG3_MARK, DU1_DG2_MARK, 1881 DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK, 1882 DU1_DB3_MARK, DU1_DB2_MARK, 1883 }; 1884 static const unsigned int du1_rgb888_pins[] = { 1885 /* R[7:0], G[7:0], B[7:0] */ 1886 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 5), 1887 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2), 1888 RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 0), 1889 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13), 1890 RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 10), 1891 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 8), 1892 RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 21), 1893 RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 18), 1894 RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16), 1895 }; 1896 static const unsigned int du1_rgb888_mux[] = { 1897 DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK, 1898 DU1_DR3_MARK, DU1_DR2_MARK, DU1_DR1_MARK, DU1_DR0_MARK, 1899 DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK, 1900 DU1_DG3_MARK, DU1_DG2_MARK, DU1_DG1_MARK, DU1_DG0_MARK, 1901 DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK, 1902 DU1_DB3_MARK, DU1_DB2_MARK, DU1_DB1_MARK, DU1_DB0_MARK, 1903 }; 1904 static const unsigned int du1_clk0_out_pins[] = { 1905 /* DOTCLKOUT0 */ 1906 RCAR_GP_PIN(4, 25), 1907 }; 1908 static const unsigned int du1_clk0_out_mux[] = { 1909 DU1_DOTCLKOUT0_MARK 1910 }; 1911 static const unsigned int du1_clk1_out_pins[] = { 1912 /* DOTCLKOUT1 */ 1913 RCAR_GP_PIN(4, 26), 1914 }; 1915 static const unsigned int du1_clk1_out_mux[] = { 1916 DU1_DOTCLKOUT1_MARK 1917 }; 1918 static const unsigned int du1_clk_in_pins[] = { 1919 /* DOTCLKIN */ 1920 RCAR_GP_PIN(4, 24), 1921 }; 1922 static const unsigned int du1_clk_in_mux[] = { 1923 DU1_DOTCLKIN_MARK 1924 }; 1925 static const unsigned int du1_sync_pins[] = { 1926 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */ 1927 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 27), 1928 }; 1929 static const unsigned int du1_sync_mux[] = { 1930 DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK 1931 }; 1932 static const unsigned int du1_oddf_pins[] = { 1933 /* EXODDF/ODDF/DISP/CDE */ 1934 RCAR_GP_PIN(4, 29), 1935 }; 1936 static const unsigned int du1_oddf_mux[] = { 1937 DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK, 1938 }; 1939 static const unsigned int du1_cde_pins[] = { 1940 /* CDE */ 1941 RCAR_GP_PIN(4, 31), 1942 }; 1943 static const unsigned int du1_cde_mux[] = { 1944 DU1_CDE_MARK 1945 }; 1946 static const unsigned int du1_disp_pins[] = { 1947 /* DISP */ 1948 RCAR_GP_PIN(4, 30), 1949 }; 1950 static const unsigned int du1_disp_mux[] = { 1951 DU1_DISP_MARK 1952 }; 1953 /* - ETH -------------------------------------------------------------------- */ 1954 static const unsigned int eth_link_pins[] = { 1955 /* LINK */ 1956 RCAR_GP_PIN(3, 18), 1957 }; 1958 static const unsigned int eth_link_mux[] = { 1959 ETH_LINK_MARK, 1960 }; 1961 static const unsigned int eth_magic_pins[] = { 1962 /* MAGIC */ 1963 RCAR_GP_PIN(3, 22), 1964 }; 1965 static const unsigned int eth_magic_mux[] = { 1966 ETH_MAGIC_MARK, 1967 }; 1968 static const unsigned int eth_mdio_pins[] = { 1969 /* MDC, MDIO */ 1970 RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 13), 1971 }; 1972 static const unsigned int eth_mdio_mux[] = { 1973 ETH_MDC_MARK, ETH_MDIO_MARK, 1974 }; 1975 static const unsigned int eth_rmii_pins[] = { 1976 /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */ 1977 RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 15), 1978 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 20), 1979 RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 19), 1980 }; 1981 static const unsigned int eth_rmii_mux[] = { 1982 ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK, 1983 ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REFCLK_MARK, 1984 }; 1985 static const unsigned int eth_link_b_pins[] = { 1986 /* LINK */ 1987 RCAR_GP_PIN(5, 15), 1988 }; 1989 static const unsigned int eth_link_b_mux[] = { 1990 ETH_LINK_B_MARK, 1991 }; 1992 static const unsigned int eth_magic_b_pins[] = { 1993 /* MAGIC */ 1994 RCAR_GP_PIN(5, 19), 1995 }; 1996 static const unsigned int eth_magic_b_mux[] = { 1997 ETH_MAGIC_B_MARK, 1998 }; 1999 static const unsigned int eth_mdio_b_pins[] = { 2000 /* MDC, MDIO */ 2001 RCAR_GP_PIN(5, 21), RCAR_GP_PIN(5, 10), 2002 }; 2003 static const unsigned int eth_mdio_b_mux[] = { 2004 ETH_MDC_B_MARK, ETH_MDIO_B_MARK, 2005 }; 2006 static const unsigned int eth_rmii_b_pins[] = { 2007 /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */ 2008 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 12), 2009 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 17), 2010 RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 16), 2011 }; 2012 static const unsigned int eth_rmii_b_mux[] = { 2013 ETH_RXD0_B_MARK, ETH_RXD1_B_MARK, ETH_RX_ER_B_MARK, ETH_CRS_DV_B_MARK, 2014 ETH_TXD0_B_MARK, ETH_TXD1_B_MARK, ETH_TX_EN_B_MARK, ETH_REFCLK_B_MARK, 2015 }; 2016 /* - HSCIF0 ----------------------------------------------------------------- */ 2017 static const unsigned int hscif0_data_pins[] = { 2018 /* RX, TX */ 2019 RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26), 2020 }; 2021 static const unsigned int hscif0_data_mux[] = { 2022 HSCIF0_HRX_MARK, HSCIF0_HTX_MARK, 2023 }; 2024 static const unsigned int hscif0_clk_pins[] = { 2025 /* SCK */ 2026 RCAR_GP_PIN(3, 29), 2027 }; 2028 static const unsigned int hscif0_clk_mux[] = { 2029 HSCIF0_HSCK_MARK, 2030 }; 2031 static const unsigned int hscif0_ctrl_pins[] = { 2032 /* RTS, CTS */ 2033 RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 27), 2034 }; 2035 static const unsigned int hscif0_ctrl_mux[] = { 2036 HSCIF0_HRTS_N_MARK, HSCIF0_HCTS_N_MARK, 2037 }; 2038 static const unsigned int hscif0_data_b_pins[] = { 2039 /* RX, TX */ 2040 RCAR_GP_PIN(0, 30), RCAR_GP_PIN(0, 31), 2041 }; 2042 static const unsigned int hscif0_data_b_mux[] = { 2043 HSCIF0_HRX_B_MARK, HSCIF0_HTX_B_MARK, 2044 }; 2045 static const unsigned int hscif0_clk_b_pins[] = { 2046 /* SCK */ 2047 RCAR_GP_PIN(1, 0), 2048 }; 2049 static const unsigned int hscif0_clk_b_mux[] = { 2050 HSCIF0_HSCK_B_MARK, 2051 }; 2052 /* - HSCIF1 ----------------------------------------------------------------- */ 2053 static const unsigned int hscif1_data_pins[] = { 2054 /* RX, TX */ 2055 RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9), 2056 }; 2057 static const unsigned int hscif1_data_mux[] = { 2058 HSCIF1_HRX_MARK, HSCIF1_HTX_MARK, 2059 }; 2060 static const unsigned int hscif1_clk_pins[] = { 2061 /* SCK */ 2062 RCAR_GP_PIN(4, 10), 2063 }; 2064 static const unsigned int hscif1_clk_mux[] = { 2065 HSCIF1_HSCK_MARK, 2066 }; 2067 static const unsigned int hscif1_ctrl_pins[] = { 2068 /* RTS, CTS */ 2069 RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 11), 2070 }; 2071 static const unsigned int hscif1_ctrl_mux[] = { 2072 HSCIF1_HRTS_N_MARK, HSCIF1_HCTS_N_MARK, 2073 }; 2074 static const unsigned int hscif1_data_b_pins[] = { 2075 /* RX, TX */ 2076 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14), 2077 }; 2078 static const unsigned int hscif1_data_b_mux[] = { 2079 HSCIF1_HRX_B_MARK, HSCIF1_HTX_B_MARK, 2080 }; 2081 static const unsigned int hscif1_ctrl_b_pins[] = { 2082 /* RTS, CTS */ 2083 RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15), 2084 }; 2085 static const unsigned int hscif1_ctrl_b_mux[] = { 2086 HSCIF1_HRTS_N_B_MARK, HSCIF1_HCTS_N_B_MARK, 2087 }; 2088 /* - HSCIF2 ----------------------------------------------------------------- */ 2089 static const unsigned int hscif2_data_pins[] = { 2090 /* RX, TX */ 2091 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), 2092 }; 2093 static const unsigned int hscif2_data_mux[] = { 2094 HSCIF2_HRX_MARK, HSCIF2_HTX_MARK, 2095 }; 2096 static const unsigned int hscif2_clk_pins[] = { 2097 /* SCK */ 2098 RCAR_GP_PIN(0, 10), 2099 }; 2100 static const unsigned int hscif2_clk_mux[] = { 2101 HSCIF2_HSCK_MARK, 2102 }; 2103 static const unsigned int hscif2_ctrl_pins[] = { 2104 /* RTS, CTS */ 2105 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), 2106 }; 2107 static const unsigned int hscif2_ctrl_mux[] = { 2108 HSCIF2_HRTS_N_MARK, HSCIF2_HCTS_N_MARK, 2109 }; 2110 /* - I2C0 ------------------------------------------------------------------- */ 2111 static const unsigned int i2c0_pins[] = { 2112 /* SCL, SDA */ 2113 RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31), 2114 }; 2115 static const unsigned int i2c0_mux[] = { 2116 I2C0_SCL_MARK, I2C0_SDA_MARK, 2117 }; 2118 static const unsigned int i2c0_b_pins[] = { 2119 /* SCL, SDA */ 2120 RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21), 2121 }; 2122 static const unsigned int i2c0_b_mux[] = { 2123 I2C0_SCL_B_MARK, I2C0_SDA_B_MARK, 2124 }; 2125 static const unsigned int i2c0_c_pins[] = { 2126 /* SCL, SDA */ 2127 RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12), 2128 }; 2129 static const unsigned int i2c0_c_mux[] = { 2130 I2C0_SCL_C_MARK, I2C0_SDA_C_MARK, 2131 }; 2132 static const unsigned int i2c0_d_pins[] = { 2133 /* SCL, SDA */ 2134 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6), 2135 }; 2136 static const unsigned int i2c0_d_mux[] = { 2137 I2C0_SCL_D_MARK, I2C0_SDA_D_MARK, 2138 }; 2139 static const unsigned int i2c0_e_pins[] = { 2140 /* SCL, SDA */ 2141 RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), 2142 }; 2143 static const unsigned int i2c0_e_mux[] = { 2144 I2C0_SCL_E_MARK, I2C0_SDA_E_MARK, 2145 }; 2146 /* - I2C1 ------------------------------------------------------------------- */ 2147 static const unsigned int i2c1_pins[] = { 2148 /* SCL, SDA */ 2149 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1), 2150 }; 2151 static const unsigned int i2c1_mux[] = { 2152 I2C1_SCL_MARK, I2C1_SDA_MARK, 2153 }; 2154 static const unsigned int i2c1_b_pins[] = { 2155 /* SCL, SDA */ 2156 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), 2157 }; 2158 static const unsigned int i2c1_b_mux[] = { 2159 I2C1_SCL_B_MARK, I2C1_SDA_B_MARK, 2160 }; 2161 static const unsigned int i2c1_c_pins[] = { 2162 /* SCL, SDA */ 2163 RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26), 2164 }; 2165 static const unsigned int i2c1_c_mux[] = { 2166 I2C1_SCL_C_MARK, I2C1_SDA_C_MARK, 2167 }; 2168 static const unsigned int i2c1_d_pins[] = { 2169 /* SCL, SDA */ 2170 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 12), 2171 }; 2172 static const unsigned int i2c1_d_mux[] = { 2173 I2C1_SCL_D_MARK, I2C1_SDA_D_MARK, 2174 }; 2175 static const unsigned int i2c1_e_pins[] = { 2176 /* SCL, SDA */ 2177 RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21), 2178 }; 2179 static const unsigned int i2c1_e_mux[] = { 2180 I2C1_SCL_E_MARK, I2C1_SDA_E_MARK, 2181 }; 2182 /* - I2C2 ------------------------------------------------------------------- */ 2183 static const unsigned int i2c2_pins[] = { 2184 /* SCL, SDA */ 2185 RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23), 2186 }; 2187 static const unsigned int i2c2_mux[] = { 2188 I2C2_SCL_MARK, I2C2_SDA_MARK, 2189 }; 2190 static const unsigned int i2c2_b_pins[] = { 2191 /* SCL, SDA */ 2192 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25), 2193 }; 2194 static const unsigned int i2c2_b_mux[] = { 2195 I2C2_SCL_B_MARK, I2C2_SDA_B_MARK, 2196 }; 2197 static const unsigned int i2c2_c_pins[] = { 2198 /* SCL, SDA */ 2199 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), 2200 }; 2201 static const unsigned int i2c2_c_mux[] = { 2202 I2C2_SCL_C_MARK, I2C2_SDA_C_MARK, 2203 }; 2204 static const unsigned int i2c2_d_pins[] = { 2205 /* SCL, SDA */ 2206 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), 2207 }; 2208 static const unsigned int i2c2_d_mux[] = { 2209 I2C2_SCL_D_MARK, I2C2_SDA_D_MARK, 2210 }; 2211 static const unsigned int i2c2_e_pins[] = { 2212 /* SCL, SDA */ 2213 RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17), 2214 }; 2215 static const unsigned int i2c2_e_mux[] = { 2216 I2C2_SCL_E_MARK, I2C2_SDA_E_MARK, 2217 }; 2218 /* - I2C3 ------------------------------------------------------------------- */ 2219 static const unsigned int i2c3_pins[] = { 2220 /* SCL, SDA */ 2221 RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10), 2222 }; 2223 static const unsigned int i2c3_mux[] = { 2224 I2C3_SCL_MARK, I2C3_SDA_MARK, 2225 }; 2226 static const unsigned int i2c3_b_pins[] = { 2227 /* SCL, SDA */ 2228 RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4), 2229 }; 2230 static const unsigned int i2c3_b_mux[] = { 2231 I2C3_SCL_B_MARK, I2C3_SDA_B_MARK, 2232 }; 2233 static const unsigned int i2c3_c_pins[] = { 2234 /* SCL, SDA */ 2235 RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26), 2236 }; 2237 static const unsigned int i2c3_c_mux[] = { 2238 I2C3_SCL_C_MARK, I2C3_SDA_C_MARK, 2239 }; 2240 static const unsigned int i2c3_d_pins[] = { 2241 /* SCL, SDA */ 2242 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), 2243 }; 2244 static const unsigned int i2c3_d_mux[] = { 2245 I2C3_SCL_D_MARK, I2C3_SDA_D_MARK, 2246 }; 2247 static const unsigned int i2c3_e_pins[] = { 2248 /* SCL, SDA */ 2249 RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19), 2250 }; 2251 static const unsigned int i2c3_e_mux[] = { 2252 I2C3_SCL_E_MARK, I2C3_SDA_E_MARK, 2253 }; 2254 /* - I2C4 ------------------------------------------------------------------- */ 2255 static const unsigned int i2c4_pins[] = { 2256 /* SCL, SDA */ 2257 RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9), 2258 }; 2259 static const unsigned int i2c4_mux[] = { 2260 I2C4_SCL_MARK, I2C4_SDA_MARK, 2261 }; 2262 static const unsigned int i2c4_b_pins[] = { 2263 /* SCL, SDA */ 2264 RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23), 2265 }; 2266 static const unsigned int i2c4_b_mux[] = { 2267 I2C4_SCL_B_MARK, I2C4_SDA_B_MARK, 2268 }; 2269 static const unsigned int i2c4_c_pins[] = { 2270 /* SCL, SDA */ 2271 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29), 2272 }; 2273 static const unsigned int i2c4_c_mux[] = { 2274 I2C4_SCL_C_MARK, I2C4_SDA_C_MARK, 2275 }; 2276 static const unsigned int i2c4_d_pins[] = { 2277 /* SCL, SDA */ 2278 RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17), 2279 }; 2280 static const unsigned int i2c4_d_mux[] = { 2281 I2C4_SCL_D_MARK, I2C4_SDA_D_MARK, 2282 }; 2283 static const unsigned int i2c4_e_pins[] = { 2284 /* SCL, SDA */ 2285 RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24), 2286 }; 2287 static const unsigned int i2c4_e_mux[] = { 2288 I2C4_SCL_E_MARK, I2C4_SDA_E_MARK, 2289 }; 2290 /* - I2C5 ------------------------------------------------------------------- */ 2291 static const unsigned int i2c5_pins[] = { 2292 /* SCL, SDA */ 2293 RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15), 2294 }; 2295 static const unsigned int i2c5_mux[] = { 2296 I2C5_SCL_MARK, I2C5_SDA_MARK, 2297 }; 2298 static const unsigned int i2c5_b_pins[] = { 2299 /* SCL, SDA */ 2300 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), 2301 }; 2302 static const unsigned int i2c5_b_mux[] = { 2303 I2C5_SCL_B_MARK, I2C5_SDA_B_MARK, 2304 }; 2305 static const unsigned int i2c5_c_pins[] = { 2306 /* SCL, SDA */ 2307 RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30), 2308 }; 2309 static const unsigned int i2c5_c_mux[] = { 2310 I2C5_SCL_C_MARK, I2C5_SDA_C_MARK, 2311 }; 2312 static const unsigned int i2c5_d_pins[] = { 2313 /* SCL, SDA */ 2314 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14), 2315 }; 2316 static const unsigned int i2c5_d_mux[] = { 2317 I2C5_SCL_D_MARK, I2C5_SDA_D_MARK, 2318 }; 2319 /* - INTC ------------------------------------------------------------------- */ 2320 static const unsigned int intc_irq0_pins[] = { 2321 /* IRQ0 */ 2322 RCAR_GP_PIN(4, 4), 2323 }; 2324 static const unsigned int intc_irq0_mux[] = { 2325 IRQ0_MARK, 2326 }; 2327 static const unsigned int intc_irq1_pins[] = { 2328 /* IRQ1 */ 2329 RCAR_GP_PIN(4, 18), 2330 }; 2331 static const unsigned int intc_irq1_mux[] = { 2332 IRQ1_MARK, 2333 }; 2334 static const unsigned int intc_irq2_pins[] = { 2335 /* IRQ2 */ 2336 RCAR_GP_PIN(4, 19), 2337 }; 2338 static const unsigned int intc_irq2_mux[] = { 2339 IRQ2_MARK, 2340 }; 2341 static const unsigned int intc_irq3_pins[] = { 2342 /* IRQ3 */ 2343 RCAR_GP_PIN(0, 7), 2344 }; 2345 static const unsigned int intc_irq3_mux[] = { 2346 IRQ3_MARK, 2347 }; 2348 static const unsigned int intc_irq4_pins[] = { 2349 /* IRQ4 */ 2350 RCAR_GP_PIN(0, 0), 2351 }; 2352 static const unsigned int intc_irq4_mux[] = { 2353 IRQ4_MARK, 2354 }; 2355 static const unsigned int intc_irq5_pins[] = { 2356 /* IRQ5 */ 2357 RCAR_GP_PIN(4, 1), 2358 }; 2359 static const unsigned int intc_irq5_mux[] = { 2360 IRQ5_MARK, 2361 }; 2362 static const unsigned int intc_irq6_pins[] = { 2363 /* IRQ6 */ 2364 RCAR_GP_PIN(0, 10), 2365 }; 2366 static const unsigned int intc_irq6_mux[] = { 2367 IRQ6_MARK, 2368 }; 2369 static const unsigned int intc_irq7_pins[] = { 2370 /* IRQ7 */ 2371 RCAR_GP_PIN(6, 15), 2372 }; 2373 static const unsigned int intc_irq7_mux[] = { 2374 IRQ7_MARK, 2375 }; 2376 static const unsigned int intc_irq8_pins[] = { 2377 /* IRQ8 */ 2378 RCAR_GP_PIN(5, 0), 2379 }; 2380 static const unsigned int intc_irq8_mux[] = { 2381 IRQ8_MARK, 2382 }; 2383 static const unsigned int intc_irq9_pins[] = { 2384 /* IRQ9 */ 2385 RCAR_GP_PIN(5, 10), 2386 }; 2387 static const unsigned int intc_irq9_mux[] = { 2388 IRQ9_MARK, 2389 }; 2390 /* - MMCIF ------------------------------------------------------------------ */ 2391 static const unsigned int mmc_data1_pins[] = { 2392 /* D[0] */ 2393 RCAR_GP_PIN(6, 18), 2394 }; 2395 static const unsigned int mmc_data1_mux[] = { 2396 MMC_D0_MARK, 2397 }; 2398 static const unsigned int mmc_data4_pins[] = { 2399 /* D[0:3] */ 2400 RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19), 2401 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21), 2402 }; 2403 static const unsigned int mmc_data4_mux[] = { 2404 MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK, 2405 }; 2406 static const unsigned int mmc_data8_pins[] = { 2407 /* D[0:7] */ 2408 RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19), 2409 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21), 2410 RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23), 2411 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25), 2412 }; 2413 static const unsigned int mmc_data8_mux[] = { 2414 MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK, 2415 MMC_D4_MARK, MMC_D5_MARK, MMC_D6_MARK, MMC_D7_MARK, 2416 }; 2417 static const unsigned int mmc_ctrl_pins[] = { 2418 /* CLK, CMD */ 2419 RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17), 2420 }; 2421 static const unsigned int mmc_ctrl_mux[] = { 2422 MMC_CLK_MARK, MMC_CMD_MARK, 2423 }; 2424 /* - MSIOF0 ----------------------------------------------------------------- */ 2425 static const unsigned int msiof0_clk_pins[] = { 2426 /* SCK */ 2427 RCAR_GP_PIN(4, 4), 2428 }; 2429 static const unsigned int msiof0_clk_mux[] = { 2430 MSIOF0_SCK_MARK, 2431 }; 2432 static const unsigned int msiof0_sync_pins[] = { 2433 /* SYNC */ 2434 RCAR_GP_PIN(4, 5), 2435 }; 2436 static const unsigned int msiof0_sync_mux[] = { 2437 MSIOF0_SYNC_MARK, 2438 }; 2439 static const unsigned int msiof0_ss1_pins[] = { 2440 /* SS1 */ 2441 RCAR_GP_PIN(4, 6), 2442 }; 2443 static const unsigned int msiof0_ss1_mux[] = { 2444 MSIOF0_SS1_MARK, 2445 }; 2446 static const unsigned int msiof0_ss2_pins[] = { 2447 /* SS2 */ 2448 RCAR_GP_PIN(4, 7), 2449 }; 2450 static const unsigned int msiof0_ss2_mux[] = { 2451 MSIOF0_SS2_MARK, 2452 }; 2453 static const unsigned int msiof0_rx_pins[] = { 2454 /* RXD */ 2455 RCAR_GP_PIN(4, 2), 2456 }; 2457 static const unsigned int msiof0_rx_mux[] = { 2458 MSIOF0_RXD_MARK, 2459 }; 2460 static const unsigned int msiof0_tx_pins[] = { 2461 /* TXD */ 2462 RCAR_GP_PIN(4, 3), 2463 }; 2464 static const unsigned int msiof0_tx_mux[] = { 2465 MSIOF0_TXD_MARK, 2466 }; 2467 /* - MSIOF1 ----------------------------------------------------------------- */ 2468 static const unsigned int msiof1_clk_pins[] = { 2469 /* SCK */ 2470 RCAR_GP_PIN(0, 26), 2471 }; 2472 static const unsigned int msiof1_clk_mux[] = { 2473 MSIOF1_SCK_MARK, 2474 }; 2475 static const unsigned int msiof1_sync_pins[] = { 2476 /* SYNC */ 2477 RCAR_GP_PIN(0, 27), 2478 }; 2479 static const unsigned int msiof1_sync_mux[] = { 2480 MSIOF1_SYNC_MARK, 2481 }; 2482 static const unsigned int msiof1_ss1_pins[] = { 2483 /* SS1 */ 2484 RCAR_GP_PIN(0, 28), 2485 }; 2486 static const unsigned int msiof1_ss1_mux[] = { 2487 MSIOF1_SS1_MARK, 2488 }; 2489 static const unsigned int msiof1_ss2_pins[] = { 2490 /* SS2 */ 2491 RCAR_GP_PIN(0, 29), 2492 }; 2493 static const unsigned int msiof1_ss2_mux[] = { 2494 MSIOF1_SS2_MARK, 2495 }; 2496 static const unsigned int msiof1_rx_pins[] = { 2497 /* RXD */ 2498 RCAR_GP_PIN(0, 24), 2499 }; 2500 static const unsigned int msiof1_rx_mux[] = { 2501 MSIOF1_RXD_MARK, 2502 }; 2503 static const unsigned int msiof1_tx_pins[] = { 2504 /* TXD */ 2505 RCAR_GP_PIN(0, 25), 2506 }; 2507 static const unsigned int msiof1_tx_mux[] = { 2508 MSIOF1_TXD_MARK, 2509 }; 2510 static const unsigned int msiof1_clk_b_pins[] = { 2511 /* SCK */ 2512 RCAR_GP_PIN(5, 3), 2513 }; 2514 static const unsigned int msiof1_clk_b_mux[] = { 2515 MSIOF1_SCK_B_MARK, 2516 }; 2517 static const unsigned int msiof1_sync_b_pins[] = { 2518 /* SYNC */ 2519 RCAR_GP_PIN(5, 4), 2520 }; 2521 static const unsigned int msiof1_sync_b_mux[] = { 2522 MSIOF1_SYNC_B_MARK, 2523 }; 2524 static const unsigned int msiof1_ss1_b_pins[] = { 2525 /* SS1 */ 2526 RCAR_GP_PIN(5, 5), 2527 }; 2528 static const unsigned int msiof1_ss1_b_mux[] = { 2529 MSIOF1_SS1_B_MARK, 2530 }; 2531 static const unsigned int msiof1_ss2_b_pins[] = { 2532 /* SS2 */ 2533 RCAR_GP_PIN(5, 6), 2534 }; 2535 static const unsigned int msiof1_ss2_b_mux[] = { 2536 MSIOF1_SS2_B_MARK, 2537 }; 2538 static const unsigned int msiof1_rx_b_pins[] = { 2539 /* RXD */ 2540 RCAR_GP_PIN(5, 1), 2541 }; 2542 static const unsigned int msiof1_rx_b_mux[] = { 2543 MSIOF1_RXD_B_MARK, 2544 }; 2545 static const unsigned int msiof1_tx_b_pins[] = { 2546 /* TXD */ 2547 RCAR_GP_PIN(5, 2), 2548 }; 2549 static const unsigned int msiof1_tx_b_mux[] = { 2550 MSIOF1_TXD_B_MARK, 2551 }; 2552 /* - MSIOF2 ----------------------------------------------------------------- */ 2553 static const unsigned int msiof2_clk_pins[] = { 2554 /* SCK */ 2555 RCAR_GP_PIN(1, 0), 2556 }; 2557 static const unsigned int msiof2_clk_mux[] = { 2558 MSIOF2_SCK_MARK, 2559 }; 2560 static const unsigned int msiof2_sync_pins[] = { 2561 /* SYNC */ 2562 RCAR_GP_PIN(1, 1), 2563 }; 2564 static const unsigned int msiof2_sync_mux[] = { 2565 MSIOF2_SYNC_MARK, 2566 }; 2567 static const unsigned int msiof2_ss1_pins[] = { 2568 /* SS1 */ 2569 RCAR_GP_PIN(1, 2), 2570 }; 2571 static const unsigned int msiof2_ss1_mux[] = { 2572 MSIOF2_SS1_MARK, 2573 }; 2574 static const unsigned int msiof2_ss2_pins[] = { 2575 /* SS2 */ 2576 RCAR_GP_PIN(1, 3), 2577 }; 2578 static const unsigned int msiof2_ss2_mux[] = { 2579 MSIOF2_SS2_MARK, 2580 }; 2581 static const unsigned int msiof2_rx_pins[] = { 2582 /* RXD */ 2583 RCAR_GP_PIN(0, 30), 2584 }; 2585 static const unsigned int msiof2_rx_mux[] = { 2586 MSIOF2_RXD_MARK, 2587 }; 2588 static const unsigned int msiof2_tx_pins[] = { 2589 /* TXD */ 2590 RCAR_GP_PIN(0, 31), 2591 }; 2592 static const unsigned int msiof2_tx_mux[] = { 2593 MSIOF2_TXD_MARK, 2594 }; 2595 static const unsigned int msiof2_clk_b_pins[] = { 2596 /* SCK */ 2597 RCAR_GP_PIN(3, 15), 2598 }; 2599 static const unsigned int msiof2_clk_b_mux[] = { 2600 MSIOF2_SCK_B_MARK, 2601 }; 2602 static const unsigned int msiof2_sync_b_pins[] = { 2603 /* SYNC */ 2604 RCAR_GP_PIN(3, 16), 2605 }; 2606 static const unsigned int msiof2_sync_b_mux[] = { 2607 MSIOF2_SYNC_B_MARK, 2608 }; 2609 static const unsigned int msiof2_ss1_b_pins[] = { 2610 /* SS1 */ 2611 RCAR_GP_PIN(3, 17), 2612 }; 2613 static const unsigned int msiof2_ss1_b_mux[] = { 2614 MSIOF2_SS1_B_MARK, 2615 }; 2616 static const unsigned int msiof2_ss2_b_pins[] = { 2617 /* SS2 */ 2618 RCAR_GP_PIN(3, 18), 2619 }; 2620 static const unsigned int msiof2_ss2_b_mux[] = { 2621 MSIOF2_SS2_B_MARK, 2622 }; 2623 static const unsigned int msiof2_rx_b_pins[] = { 2624 /* RXD */ 2625 RCAR_GP_PIN(3, 13), 2626 }; 2627 static const unsigned int msiof2_rx_b_mux[] = { 2628 MSIOF2_RXD_B_MARK, 2629 }; 2630 static const unsigned int msiof2_tx_b_pins[] = { 2631 /* TXD */ 2632 RCAR_GP_PIN(3, 14), 2633 }; 2634 static const unsigned int msiof2_tx_b_mux[] = { 2635 MSIOF2_TXD_B_MARK, 2636 }; 2637 /* - PWM -------------------------------------------------------------------- */ 2638 static const unsigned int pwm0_pins[] = { 2639 RCAR_GP_PIN(1, 14), 2640 }; 2641 static const unsigned int pwm0_mux[] = { 2642 PWM0_MARK, 2643 }; 2644 static const unsigned int pwm0_b_pins[] = { 2645 RCAR_GP_PIN(5, 3), 2646 }; 2647 static const unsigned int pwm0_b_mux[] = { 2648 PWM0_B_MARK, 2649 }; 2650 static const unsigned int pwm1_pins[] = { 2651 RCAR_GP_PIN(4, 5), 2652 }; 2653 static const unsigned int pwm1_mux[] = { 2654 PWM1_MARK, 2655 }; 2656 static const unsigned int pwm1_b_pins[] = { 2657 RCAR_GP_PIN(5, 10), 2658 }; 2659 static const unsigned int pwm1_b_mux[] = { 2660 PWM1_B_MARK, 2661 }; 2662 static const unsigned int pwm1_c_pins[] = { 2663 RCAR_GP_PIN(1, 18), 2664 }; 2665 static const unsigned int pwm1_c_mux[] = { 2666 PWM1_C_MARK, 2667 }; 2668 static const unsigned int pwm2_pins[] = { 2669 RCAR_GP_PIN(4, 10), 2670 }; 2671 static const unsigned int pwm2_mux[] = { 2672 PWM2_MARK, 2673 }; 2674 static const unsigned int pwm2_b_pins[] = { 2675 RCAR_GP_PIN(5, 17), 2676 }; 2677 static const unsigned int pwm2_b_mux[] = { 2678 PWM2_B_MARK, 2679 }; 2680 static const unsigned int pwm2_c_pins[] = { 2681 RCAR_GP_PIN(0, 13), 2682 }; 2683 static const unsigned int pwm2_c_mux[] = { 2684 PWM2_C_MARK, 2685 }; 2686 static const unsigned int pwm3_pins[] = { 2687 RCAR_GP_PIN(4, 13), 2688 }; 2689 static const unsigned int pwm3_mux[] = { 2690 PWM3_MARK, 2691 }; 2692 static const unsigned int pwm3_b_pins[] = { 2693 RCAR_GP_PIN(0, 16), 2694 }; 2695 static const unsigned int pwm3_b_mux[] = { 2696 PWM3_B_MARK, 2697 }; 2698 static const unsigned int pwm4_pins[] = { 2699 RCAR_GP_PIN(1, 3), 2700 }; 2701 static const unsigned int pwm4_mux[] = { 2702 PWM4_MARK, 2703 }; 2704 static const unsigned int pwm4_b_pins[] = { 2705 RCAR_GP_PIN(0, 21), 2706 }; 2707 static const unsigned int pwm4_b_mux[] = { 2708 PWM4_B_MARK, 2709 }; 2710 static const unsigned int pwm5_pins[] = { 2711 RCAR_GP_PIN(3, 30), 2712 }; 2713 static const unsigned int pwm5_mux[] = { 2714 PWM5_MARK, 2715 }; 2716 static const unsigned int pwm5_b_pins[] = { 2717 RCAR_GP_PIN(4, 0), 2718 }; 2719 static const unsigned int pwm5_b_mux[] = { 2720 PWM5_B_MARK, 2721 }; 2722 static const unsigned int pwm5_c_pins[] = { 2723 RCAR_GP_PIN(0, 10), 2724 }; 2725 static const unsigned int pwm5_c_mux[] = { 2726 PWM5_C_MARK, 2727 }; 2728 static const unsigned int pwm6_pins[] = { 2729 RCAR_GP_PIN(4, 8), 2730 }; 2731 static const unsigned int pwm6_mux[] = { 2732 PWM6_MARK, 2733 }; 2734 static const unsigned int pwm6_b_pins[] = { 2735 RCAR_GP_PIN(0, 7), 2736 }; 2737 static const unsigned int pwm6_b_mux[] = { 2738 PWM6_B_MARK, 2739 }; 2740 /* - QSPI ------------------------------------------------------------------- */ 2741 static const unsigned int qspi_ctrl_pins[] = { 2742 /* SPCLK, SSL */ 2743 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 9), 2744 }; 2745 static const unsigned int qspi_ctrl_mux[] = { 2746 SPCLK_MARK, SSL_MARK, 2747 }; 2748 static const unsigned int qspi_data2_pins[] = { 2749 /* MOSI_IO0, MISO_IO1 */ 2750 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), 2751 }; 2752 static const unsigned int qspi_data2_mux[] = { 2753 MOSI_IO0_MARK, MISO_IO1_MARK, 2754 }; 2755 static const unsigned int qspi_data4_pins[] = { 2756 /* MOSI_IO0, MISO_IO1, IO2, IO3 */ 2757 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 2758 RCAR_GP_PIN(1, 8), 2759 }; 2760 static const unsigned int qspi_data4_mux[] = { 2761 MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK, 2762 }; 2763 /* - SCIF0 ------------------------------------------------------------------ */ 2764 static const unsigned int scif0_data_pins[] = { 2765 /* RX, TX */ 2766 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25), 2767 }; 2768 static const unsigned int scif0_data_mux[] = { 2769 SCIF0_RXD_MARK, SCIF0_TXD_MARK, 2770 }; 2771 static const unsigned int scif0_data_b_pins[] = { 2772 /* RX, TX */ 2773 RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12), 2774 }; 2775 static const unsigned int scif0_data_b_mux[] = { 2776 SCIF0_RXD_B_MARK, SCIF0_TXD_B_MARK, 2777 }; 2778 static const unsigned int scif0_data_c_pins[] = { 2779 /* RX, TX */ 2780 RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31), 2781 }; 2782 static const unsigned int scif0_data_c_mux[] = { 2783 SCIF0_RXD_C_MARK, SCIF0_TXD_C_MARK, 2784 }; 2785 static const unsigned int scif0_data_d_pins[] = { 2786 /* RX, TX */ 2787 RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), 2788 }; 2789 static const unsigned int scif0_data_d_mux[] = { 2790 SCIF0_RXD_D_MARK, SCIF0_TXD_D_MARK, 2791 }; 2792 /* - SCIF1 ------------------------------------------------------------------ */ 2793 static const unsigned int scif1_data_pins[] = { 2794 /* RX, TX */ 2795 RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15), 2796 }; 2797 static const unsigned int scif1_data_mux[] = { 2798 SCIF1_RXD_MARK, SCIF1_TXD_MARK, 2799 }; 2800 static const unsigned int scif1_clk_pins[] = { 2801 /* SCK */ 2802 RCAR_GP_PIN(4, 13), 2803 }; 2804 static const unsigned int scif1_clk_mux[] = { 2805 SCIF1_SCK_MARK, 2806 }; 2807 static const unsigned int scif1_data_b_pins[] = { 2808 /* RX, TX */ 2809 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 12), 2810 }; 2811 static const unsigned int scif1_data_b_mux[] = { 2812 SCIF1_RXD_B_MARK, SCIF1_TXD_B_MARK, 2813 }; 2814 static const unsigned int scif1_clk_b_pins[] = { 2815 /* SCK */ 2816 RCAR_GP_PIN(5, 10), 2817 }; 2818 static const unsigned int scif1_clk_b_mux[] = { 2819 SCIF1_SCK_B_MARK, 2820 }; 2821 static const unsigned int scif1_data_c_pins[] = { 2822 /* RX, TX */ 2823 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 12), 2824 }; 2825 static const unsigned int scif1_data_c_mux[] = { 2826 SCIF1_RXD_C_MARK, SCIF1_TXD_C_MARK, 2827 }; 2828 static const unsigned int scif1_clk_c_pins[] = { 2829 /* SCK */ 2830 RCAR_GP_PIN(0, 10), 2831 }; 2832 static const unsigned int scif1_clk_c_mux[] = { 2833 SCIF1_SCK_C_MARK, 2834 }; 2835 /* - SCIF2 ------------------------------------------------------------------ */ 2836 static const unsigned int scif2_data_pins[] = { 2837 /* RX, TX */ 2838 RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17), 2839 }; 2840 static const unsigned int scif2_data_mux[] = { 2841 SCIF2_RXD_MARK, SCIF2_TXD_MARK, 2842 }; 2843 static const unsigned int scif2_clk_pins[] = { 2844 /* SCK */ 2845 RCAR_GP_PIN(4, 18), 2846 }; 2847 static const unsigned int scif2_clk_mux[] = { 2848 SCIF2_SCK_MARK, 2849 }; 2850 static const unsigned int scif2_data_b_pins[] = { 2851 /* RX, TX */ 2852 RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19), 2853 }; 2854 static const unsigned int scif2_data_b_mux[] = { 2855 SCIF2_RXD_B_MARK, SCIF2_TXD_B_MARK, 2856 }; 2857 static const unsigned int scif2_clk_b_pins[] = { 2858 /* SCK */ 2859 RCAR_GP_PIN(5, 17), 2860 }; 2861 static const unsigned int scif2_clk_b_mux[] = { 2862 SCIF2_SCK_B_MARK, 2863 }; 2864 static const unsigned int scif2_data_c_pins[] = { 2865 /* RX, TX */ 2866 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21), 2867 }; 2868 static const unsigned int scif2_data_c_mux[] = { 2869 SCIF2_RXD_C_MARK, SCIF2_TXD_C_MARK, 2870 }; 2871 static const unsigned int scif2_clk_c_pins[] = { 2872 /* SCK */ 2873 RCAR_GP_PIN(3, 19), 2874 }; 2875 static const unsigned int scif2_clk_c_mux[] = { 2876 SCIF2_SCK_C_MARK, 2877 }; 2878 /* - SCIF3 ------------------------------------------------------------------ */ 2879 static const unsigned int scif3_data_pins[] = { 2880 /* RX, TX */ 2881 RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21), 2882 }; 2883 static const unsigned int scif3_data_mux[] = { 2884 SCIF3_RXD_MARK, SCIF3_TXD_MARK, 2885 }; 2886 static const unsigned int scif3_clk_pins[] = { 2887 /* SCK */ 2888 RCAR_GP_PIN(4, 19), 2889 }; 2890 static const unsigned int scif3_clk_mux[] = { 2891 SCIF3_SCK_MARK, 2892 }; 2893 static const unsigned int scif3_data_b_pins[] = { 2894 /* RX, TX */ 2895 RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24), 2896 }; 2897 static const unsigned int scif3_data_b_mux[] = { 2898 SCIF3_RXD_B_MARK, SCIF3_TXD_B_MARK, 2899 }; 2900 static const unsigned int scif3_clk_b_pins[] = { 2901 /* SCK */ 2902 RCAR_GP_PIN(3, 22), 2903 }; 2904 static const unsigned int scif3_clk_b_mux[] = { 2905 SCIF3_SCK_B_MARK, 2906 }; 2907 /* - SCIF4 ------------------------------------------------------------------ */ 2908 static const unsigned int scif4_data_pins[] = { 2909 /* RX, TX */ 2910 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1), 2911 }; 2912 static const unsigned int scif4_data_mux[] = { 2913 SCIF4_RXD_MARK, SCIF4_TXD_MARK, 2914 }; 2915 static const unsigned int scif4_data_b_pins[] = { 2916 /* RX, TX */ 2917 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6), 2918 }; 2919 static const unsigned int scif4_data_b_mux[] = { 2920 SCIF4_RXD_B_MARK, SCIF4_TXD_B_MARK, 2921 }; 2922 static const unsigned int scif4_data_c_pins[] = { 2923 /* RX, TX */ 2924 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), 2925 }; 2926 static const unsigned int scif4_data_c_mux[] = { 2927 SCIF4_RXD_C_MARK, SCIF4_TXD_C_MARK, 2928 }; 2929 static const unsigned int scif4_data_d_pins[] = { 2930 /* RX, TX */ 2931 RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18), 2932 }; 2933 static const unsigned int scif4_data_d_mux[] = { 2934 SCIF4_RXD_D_MARK, SCIF4_TXD_D_MARK, 2935 }; 2936 static const unsigned int scif4_data_e_pins[] = { 2937 /* RX, TX */ 2938 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2), 2939 }; 2940 static const unsigned int scif4_data_e_mux[] = { 2941 SCIF4_RXD_E_MARK, SCIF4_TXD_E_MARK, 2942 }; 2943 /* - SCIF5 ------------------------------------------------------------------ */ 2944 static const unsigned int scif5_data_pins[] = { 2945 /* RX, TX */ 2946 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), 2947 }; 2948 static const unsigned int scif5_data_mux[] = { 2949 SCIF5_RXD_MARK, SCIF5_TXD_MARK, 2950 }; 2951 static const unsigned int scif5_data_b_pins[] = { 2952 /* RX, TX */ 2953 RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4), 2954 }; 2955 static const unsigned int scif5_data_b_mux[] = { 2956 SCIF5_RXD_B_MARK, SCIF5_TXD_B_MARK, 2957 }; 2958 static const unsigned int scif5_data_c_pins[] = { 2959 /* RX, TX */ 2960 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 11), 2961 }; 2962 static const unsigned int scif5_data_c_mux[] = { 2963 SCIF5_RXD_C_MARK, SCIF5_TXD_C_MARK, 2964 }; 2965 static const unsigned int scif5_data_d_pins[] = { 2966 /* RX, TX */ 2967 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), 2968 }; 2969 static const unsigned int scif5_data_d_mux[] = { 2970 SCIF5_RXD_D_MARK, SCIF5_TXD_D_MARK, 2971 }; 2972 /* - SCIFA0 ----------------------------------------------------------------- */ 2973 static const unsigned int scifa0_data_pins[] = { 2974 /* RXD, TXD */ 2975 RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7), 2976 }; 2977 static const unsigned int scifa0_data_mux[] = { 2978 SCIFA0_RXD_MARK, SCIFA0_TXD_MARK, 2979 }; 2980 static const unsigned int scifa0_data_b_pins[] = { 2981 /* RXD, TXD */ 2982 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25), 2983 }; 2984 static const unsigned int scifa0_data_b_mux[] = { 2985 SCIFA0_RXD_B_MARK, SCIFA0_TXD_B_MARK 2986 }; 2987 static const unsigned int scifa0_data_c_pins[] = { 2988 /* RXD, TXD */ 2989 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), 2990 }; 2991 static const unsigned int scifa0_data_c_mux[] = { 2992 SCIFA0_RXD_C_MARK, SCIFA0_TXD_C_MARK 2993 }; 2994 static const unsigned int scifa0_data_d_pins[] = { 2995 /* RXD, TXD */ 2996 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16), 2997 }; 2998 static const unsigned int scifa0_data_d_mux[] = { 2999 SCIFA0_RXD_D_MARK, SCIFA0_TXD_D_MARK 3000 }; 3001 /* - SCIFA1 ----------------------------------------------------------------- */ 3002 static const unsigned int scifa1_data_pins[] = { 3003 /* RXD, TXD */ 3004 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), 3005 }; 3006 static const unsigned int scifa1_data_mux[] = { 3007 SCIFA1_RXD_MARK, SCIFA1_TXD_MARK, 3008 }; 3009 static const unsigned int scifa1_clk_pins[] = { 3010 /* SCK */ 3011 RCAR_GP_PIN(0, 13), 3012 }; 3013 static const unsigned int scifa1_clk_mux[] = { 3014 SCIFA1_SCK_MARK, 3015 }; 3016 static const unsigned int scifa1_data_b_pins[] = { 3017 /* RXD, TXD */ 3018 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29), 3019 }; 3020 static const unsigned int scifa1_data_b_mux[] = { 3021 SCIFA1_RXD_B_MARK, SCIFA1_TXD_B_MARK, 3022 }; 3023 static const unsigned int scifa1_clk_b_pins[] = { 3024 /* SCK */ 3025 RCAR_GP_PIN(4, 27), 3026 }; 3027 static const unsigned int scifa1_clk_b_mux[] = { 3028 SCIFA1_SCK_B_MARK, 3029 }; 3030 static const unsigned int scifa1_data_c_pins[] = { 3031 /* RXD, TXD */ 3032 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6), 3033 }; 3034 static const unsigned int scifa1_data_c_mux[] = { 3035 SCIFA1_RXD_C_MARK, SCIFA1_TXD_C_MARK, 3036 }; 3037 static const unsigned int scifa1_clk_c_pins[] = { 3038 /* SCK */ 3039 RCAR_GP_PIN(5, 4), 3040 }; 3041 static const unsigned int scifa1_clk_c_mux[] = { 3042 SCIFA1_SCK_C_MARK, 3043 }; 3044 /* - SCIFA2 ----------------------------------------------------------------- */ 3045 static const unsigned int scifa2_data_pins[] = { 3046 /* RXD, TXD */ 3047 RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17), 3048 }; 3049 static const unsigned int scifa2_data_mux[] = { 3050 SCIFA2_RXD_MARK, SCIFA2_TXD_MARK, 3051 }; 3052 static const unsigned int scifa2_clk_pins[] = { 3053 /* SCK */ 3054 RCAR_GP_PIN(1, 15), 3055 }; 3056 static const unsigned int scifa2_clk_mux[] = { 3057 SCIFA2_SCK_MARK, 3058 }; 3059 static const unsigned int scifa2_data_b_pins[] = { 3060 /* RXD, TXD */ 3061 RCAR_GP_PIN(4, 31), RCAR_GP_PIN(5, 0), 3062 }; 3063 static const unsigned int scifa2_data_b_mux[] = { 3064 SCIFA2_RXD_B_MARK, SCIFA2_TXD_B_MARK, 3065 }; 3066 static const unsigned int scifa2_clk_b_pins[] = { 3067 /* SCK */ 3068 RCAR_GP_PIN(4, 30), 3069 }; 3070 static const unsigned int scifa2_clk_b_mux[] = { 3071 SCIFA2_SCK_B_MARK, 3072 }; 3073 /* - SCIFA3 ----------------------------------------------------------------- */ 3074 static const unsigned int scifa3_data_pins[] = { 3075 /* RXD, TXD */ 3076 RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26), 3077 }; 3078 static const unsigned int scifa3_data_mux[] = { 3079 SCIFA3_RXD_MARK, SCIFA3_TXD_MARK, 3080 }; 3081 static const unsigned int scifa3_clk_pins[] = { 3082 /* SCK */ 3083 RCAR_GP_PIN(4, 24), 3084 }; 3085 static const unsigned int scifa3_clk_mux[] = { 3086 SCIFA3_SCK_MARK, 3087 }; 3088 static const unsigned int scifa3_data_b_pins[] = { 3089 /* RXD, TXD */ 3090 RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2), 3091 }; 3092 static const unsigned int scifa3_data_b_mux[] = { 3093 SCIFA3_RXD_B_MARK, SCIFA3_TXD_B_MARK, 3094 }; 3095 static const unsigned int scifa3_clk_b_pins[] = { 3096 /* SCK */ 3097 RCAR_GP_PIN(0, 0), 3098 }; 3099 static const unsigned int scifa3_clk_b_mux[] = { 3100 SCIFA3_SCK_B_MARK, 3101 }; 3102 /* - SCIFA4 ----------------------------------------------------------------- */ 3103 static const unsigned int scifa4_data_pins[] = { 3104 /* RXD, TXD */ 3105 RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 12), 3106 }; 3107 static const unsigned int scifa4_data_mux[] = { 3108 SCIFA4_RXD_MARK, SCIFA4_TXD_MARK, 3109 }; 3110 static const unsigned int scifa4_data_b_pins[] = { 3111 /* RXD, TXD */ 3112 RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 23), 3113 }; 3114 static const unsigned int scifa4_data_b_mux[] = { 3115 SCIFA4_RXD_B_MARK, SCIFA4_TXD_B_MARK, 3116 }; 3117 static const unsigned int scifa4_data_c_pins[] = { 3118 /* RXD, TXD */ 3119 RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17), 3120 }; 3121 static const unsigned int scifa4_data_c_mux[] = { 3122 SCIFA4_RXD_C_MARK, SCIFA4_TXD_C_MARK, 3123 }; 3124 static const unsigned int scifa4_data_d_pins[] = { 3125 /* RXD, TXD */ 3126 RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21), 3127 }; 3128 static const unsigned int scifa4_data_d_mux[] = { 3129 SCIFA4_RXD_D_MARK, SCIFA4_TXD_D_MARK, 3130 }; 3131 /* - SCIFA5 ----------------------------------------------------------------- */ 3132 static const unsigned int scifa5_data_pins[] = { 3133 /* RXD, TXD */ 3134 RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23), 3135 }; 3136 static const unsigned int scifa5_data_mux[] = { 3137 SCIFA5_RXD_MARK, SCIFA5_TXD_MARK, 3138 }; 3139 static const unsigned int scifa5_data_b_pins[] = { 3140 /* RXD, TXD */ 3141 RCAR_GP_PIN(0, 28), RCAR_GP_PIN(0, 29), 3142 }; 3143 static const unsigned int scifa5_data_b_mux[] = { 3144 SCIFA5_RXD_B_MARK, SCIFA5_TXD_B_MARK, 3145 }; 3146 static const unsigned int scifa5_data_c_pins[] = { 3147 /* RXD, TXD */ 3148 RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10), 3149 }; 3150 static const unsigned int scifa5_data_c_mux[] = { 3151 SCIFA5_RXD_C_MARK, SCIFA5_TXD_C_MARK, 3152 }; 3153 static const unsigned int scifa5_data_d_pins[] = { 3154 /* RXD, TXD */ 3155 RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23), 3156 }; 3157 static const unsigned int scifa5_data_d_mux[] = { 3158 SCIFA5_RXD_D_MARK, SCIFA5_TXD_D_MARK, 3159 }; 3160 /* - SCIFB0 ----------------------------------------------------------------- */ 3161 static const unsigned int scifb0_data_pins[] = { 3162 /* RXD, TXD */ 3163 RCAR_GP_PIN(0, 21), RCAR_GP_PIN(0, 20), 3164 }; 3165 static const unsigned int scifb0_data_mux[] = { 3166 SCIFB0_RXD_MARK, SCIFB0_TXD_MARK, 3167 }; 3168 static const unsigned int scifb0_clk_pins[] = { 3169 /* SCK */ 3170 RCAR_GP_PIN(0, 19), 3171 }; 3172 static const unsigned int scifb0_clk_mux[] = { 3173 SCIFB0_SCK_MARK, 3174 }; 3175 static const unsigned int scifb0_ctrl_pins[] = { 3176 /* RTS, CTS */ 3177 RCAR_GP_PIN(0, 23), RCAR_GP_PIN(0, 22), 3178 }; 3179 static const unsigned int scifb0_ctrl_mux[] = { 3180 SCIFB0_RTS_N_MARK, SCIFB0_CTS_N_MARK, 3181 }; 3182 /* - SCIFB1 ----------------------------------------------------------------- */ 3183 static const unsigned int scifb1_data_pins[] = { 3184 /* RXD, TXD */ 3185 RCAR_GP_PIN(1, 24), RCAR_GP_PIN(0, 17), 3186 }; 3187 static const unsigned int scifb1_data_mux[] = { 3188 SCIFB1_RXD_MARK, SCIFB1_TXD_MARK, 3189 }; 3190 static const unsigned int scifb1_clk_pins[] = { 3191 /* SCK */ 3192 RCAR_GP_PIN(0, 16), 3193 }; 3194 static const unsigned int scifb1_clk_mux[] = { 3195 SCIFB1_SCK_MARK, 3196 }; 3197 /* - SCIFB2 ----------------------------------------------------------------- */ 3198 static const unsigned int scifb2_data_pins[] = { 3199 /* RXD, TXD */ 3200 RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14), 3201 }; 3202 static const unsigned int scifb2_data_mux[] = { 3203 SCIFB2_RXD_MARK, SCIFB2_TXD_MARK, 3204 }; 3205 static const unsigned int scifb2_clk_pins[] = { 3206 /* SCK */ 3207 RCAR_GP_PIN(1, 15), 3208 }; 3209 static const unsigned int scifb2_clk_mux[] = { 3210 SCIFB2_SCK_MARK, 3211 }; 3212 static const unsigned int scifb2_ctrl_pins[] = { 3213 /* RTS, CTS */ 3214 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16), 3215 }; 3216 static const unsigned int scifb2_ctrl_mux[] = { 3217 SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK, 3218 }; 3219 /* - SCIF Clock ------------------------------------------------------------- */ 3220 static const unsigned int scif_clk_pins[] = { 3221 /* SCIF_CLK */ 3222 RCAR_GP_PIN(1, 23), 3223 }; 3224 static const unsigned int scif_clk_mux[] = { 3225 SCIF_CLK_MARK, 3226 }; 3227 static const unsigned int scif_clk_b_pins[] = { 3228 /* SCIF_CLK */ 3229 RCAR_GP_PIN(3, 29), 3230 }; 3231 static const unsigned int scif_clk_b_mux[] = { 3232 SCIF_CLK_B_MARK, 3233 }; 3234 /* - SDHI0 ------------------------------------------------------------------ */ 3235 static const unsigned int sdhi0_data1_pins[] = { 3236 /* D0 */ 3237 RCAR_GP_PIN(6, 2), 3238 }; 3239 static const unsigned int sdhi0_data1_mux[] = { 3240 SD0_DATA0_MARK, 3241 }; 3242 static const unsigned int sdhi0_data4_pins[] = { 3243 /* D[0:3] */ 3244 RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3), 3245 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5), 3246 }; 3247 static const unsigned int sdhi0_data4_mux[] = { 3248 SD0_DATA0_MARK, SD0_DATA1_MARK, SD0_DATA2_MARK, SD0_DATA3_MARK, 3249 }; 3250 static const unsigned int sdhi0_ctrl_pins[] = { 3251 /* CLK, CMD */ 3252 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1), 3253 }; 3254 static const unsigned int sdhi0_ctrl_mux[] = { 3255 SD0_CLK_MARK, SD0_CMD_MARK, 3256 }; 3257 static const unsigned int sdhi0_cd_pins[] = { 3258 /* CD */ 3259 RCAR_GP_PIN(6, 6), 3260 }; 3261 static const unsigned int sdhi0_cd_mux[] = { 3262 SD0_CD_MARK, 3263 }; 3264 static const unsigned int sdhi0_wp_pins[] = { 3265 /* WP */ 3266 RCAR_GP_PIN(6, 7), 3267 }; 3268 static const unsigned int sdhi0_wp_mux[] = { 3269 SD0_WP_MARK, 3270 }; 3271 /* - SDHI1 ------------------------------------------------------------------ */ 3272 static const unsigned int sdhi1_data1_pins[] = { 3273 /* D0 */ 3274 RCAR_GP_PIN(6, 10), 3275 }; 3276 static const unsigned int sdhi1_data1_mux[] = { 3277 SD1_DATA0_MARK, 3278 }; 3279 static const unsigned int sdhi1_data4_pins[] = { 3280 /* D[0:3] */ 3281 RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11), 3282 RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13), 3283 }; 3284 static const unsigned int sdhi1_data4_mux[] = { 3285 SD1_DATA0_MARK, SD1_DATA1_MARK, SD1_DATA2_MARK, SD1_DATA3_MARK, 3286 }; 3287 static const unsigned int sdhi1_ctrl_pins[] = { 3288 /* CLK, CMD */ 3289 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), 3290 }; 3291 static const unsigned int sdhi1_ctrl_mux[] = { 3292 SD1_CLK_MARK, SD1_CMD_MARK, 3293 }; 3294 static const unsigned int sdhi1_cd_pins[] = { 3295 /* CD */ 3296 RCAR_GP_PIN(6, 14), 3297 }; 3298 static const unsigned int sdhi1_cd_mux[] = { 3299 SD1_CD_MARK, 3300 }; 3301 static const unsigned int sdhi1_wp_pins[] = { 3302 /* WP */ 3303 RCAR_GP_PIN(6, 15), 3304 }; 3305 static const unsigned int sdhi1_wp_mux[] = { 3306 SD1_WP_MARK, 3307 }; 3308 /* - SDHI2 ------------------------------------------------------------------ */ 3309 static const unsigned int sdhi2_data1_pins[] = { 3310 /* D0 */ 3311 RCAR_GP_PIN(6, 18), 3312 }; 3313 static const unsigned int sdhi2_data1_mux[] = { 3314 SD2_DATA0_MARK, 3315 }; 3316 static const unsigned int sdhi2_data4_pins[] = { 3317 /* D[0:3] */ 3318 RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19), 3319 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21), 3320 }; 3321 static const unsigned int sdhi2_data4_mux[] = { 3322 SD2_DATA0_MARK, SD2_DATA1_MARK, SD2_DATA2_MARK, SD2_DATA3_MARK, 3323 }; 3324 static const unsigned int sdhi2_ctrl_pins[] = { 3325 /* CLK, CMD */ 3326 RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17), 3327 }; 3328 static const unsigned int sdhi2_ctrl_mux[] = { 3329 SD2_CLK_MARK, SD2_CMD_MARK, 3330 }; 3331 static const unsigned int sdhi2_cd_pins[] = { 3332 /* CD */ 3333 RCAR_GP_PIN(6, 22), 3334 }; 3335 static const unsigned int sdhi2_cd_mux[] = { 3336 SD2_CD_MARK, 3337 }; 3338 static const unsigned int sdhi2_wp_pins[] = { 3339 /* WP */ 3340 RCAR_GP_PIN(6, 23), 3341 }; 3342 static const unsigned int sdhi2_wp_mux[] = { 3343 SD2_WP_MARK, 3344 }; 3345 /* - SSI -------------------------------------------------------------------- */ 3346 static const unsigned int ssi0_data_pins[] = { 3347 /* SDATA0 */ 3348 RCAR_GP_PIN(5, 3), 3349 }; 3350 static const unsigned int ssi0_data_mux[] = { 3351 SSI_SDATA0_MARK, 3352 }; 3353 static const unsigned int ssi0129_ctrl_pins[] = { 3354 /* SCK0129, WS0129 */ 3355 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), 3356 }; 3357 static const unsigned int ssi0129_ctrl_mux[] = { 3358 SSI_SCK0129_MARK, SSI_WS0129_MARK, 3359 }; 3360 static const unsigned int ssi1_data_pins[] = { 3361 /* SDATA1 */ 3362 RCAR_GP_PIN(5, 13), 3363 }; 3364 static const unsigned int ssi1_data_mux[] = { 3365 SSI_SDATA1_MARK, 3366 }; 3367 static const unsigned int ssi1_ctrl_pins[] = { 3368 /* SCK1, WS1 */ 3369 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 12), 3370 }; 3371 static const unsigned int ssi1_ctrl_mux[] = { 3372 SSI_SCK1_MARK, SSI_WS1_MARK, 3373 }; 3374 static const unsigned int ssi1_data_b_pins[] = { 3375 /* SDATA1 */ 3376 RCAR_GP_PIN(4, 13), 3377 }; 3378 static const unsigned int ssi1_data_b_mux[] = { 3379 SSI_SDATA1_B_MARK, 3380 }; 3381 static const unsigned int ssi1_ctrl_b_pins[] = { 3382 /* SCK1, WS1 */ 3383 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12), 3384 }; 3385 static const unsigned int ssi1_ctrl_b_mux[] = { 3386 SSI_SCK1_B_MARK, SSI_WS1_B_MARK, 3387 }; 3388 static const unsigned int ssi2_data_pins[] = { 3389 /* SDATA2 */ 3390 RCAR_GP_PIN(5, 16), 3391 }; 3392 static const unsigned int ssi2_data_mux[] = { 3393 SSI_SDATA2_MARK, 3394 }; 3395 static const unsigned int ssi2_ctrl_pins[] = { 3396 /* SCK2, WS2 */ 3397 RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15), 3398 }; 3399 static const unsigned int ssi2_ctrl_mux[] = { 3400 SSI_SCK2_MARK, SSI_WS2_MARK, 3401 }; 3402 static const unsigned int ssi2_data_b_pins[] = { 3403 /* SDATA2 */ 3404 RCAR_GP_PIN(4, 16), 3405 }; 3406 static const unsigned int ssi2_data_b_mux[] = { 3407 SSI_SDATA2_B_MARK, 3408 }; 3409 static const unsigned int ssi2_ctrl_b_pins[] = { 3410 /* SCK2, WS2 */ 3411 RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15), 3412 }; 3413 static const unsigned int ssi2_ctrl_b_mux[] = { 3414 SSI_SCK2_B_MARK, SSI_WS2_B_MARK, 3415 }; 3416 static const unsigned int ssi3_data_pins[] = { 3417 /* SDATA3 */ 3418 RCAR_GP_PIN(5, 6), 3419 }; 3420 static const unsigned int ssi3_data_mux[] = { 3421 SSI_SDATA3_MARK 3422 }; 3423 static const unsigned int ssi34_ctrl_pins[] = { 3424 /* SCK34, WS34 */ 3425 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5), 3426 }; 3427 static const unsigned int ssi34_ctrl_mux[] = { 3428 SSI_SCK34_MARK, SSI_WS34_MARK, 3429 }; 3430 static const unsigned int ssi4_data_pins[] = { 3431 /* SDATA4 */ 3432 RCAR_GP_PIN(5, 9), 3433 }; 3434 static const unsigned int ssi4_data_mux[] = { 3435 SSI_SDATA4_MARK, 3436 }; 3437 static const unsigned int ssi4_ctrl_pins[] = { 3438 /* SCK4, WS4 */ 3439 RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8), 3440 }; 3441 static const unsigned int ssi4_ctrl_mux[] = { 3442 SSI_SCK4_MARK, SSI_WS4_MARK, 3443 }; 3444 static const unsigned int ssi4_data_b_pins[] = { 3445 /* SDATA4 */ 3446 RCAR_GP_PIN(4, 22), 3447 }; 3448 static const unsigned int ssi4_data_b_mux[] = { 3449 SSI_SDATA4_B_MARK, 3450 }; 3451 static const unsigned int ssi4_ctrl_b_pins[] = { 3452 /* SCK4, WS4 */ 3453 RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21), 3454 }; 3455 static const unsigned int ssi4_ctrl_b_mux[] = { 3456 SSI_SCK4_B_MARK, SSI_WS4_B_MARK, 3457 }; 3458 static const unsigned int ssi5_data_pins[] = { 3459 /* SDATA5 */ 3460 RCAR_GP_PIN(4, 26), 3461 }; 3462 static const unsigned int ssi5_data_mux[] = { 3463 SSI_SDATA5_MARK, 3464 }; 3465 static const unsigned int ssi5_ctrl_pins[] = { 3466 /* SCK5, WS5 */ 3467 RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 25), 3468 }; 3469 static const unsigned int ssi5_ctrl_mux[] = { 3470 SSI_SCK5_MARK, SSI_WS5_MARK, 3471 }; 3472 static const unsigned int ssi5_data_b_pins[] = { 3473 /* SDATA5 */ 3474 RCAR_GP_PIN(3, 21), 3475 }; 3476 static const unsigned int ssi5_data_b_mux[] = { 3477 SSI_SDATA5_B_MARK, 3478 }; 3479 static const unsigned int ssi5_ctrl_b_pins[] = { 3480 /* SCK5, WS5 */ 3481 RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20), 3482 }; 3483 static const unsigned int ssi5_ctrl_b_mux[] = { 3484 SSI_SCK5_B_MARK, SSI_WS5_B_MARK, 3485 }; 3486 static const unsigned int ssi6_data_pins[] = { 3487 /* SDATA6 */ 3488 RCAR_GP_PIN(4, 29), 3489 }; 3490 static const unsigned int ssi6_data_mux[] = { 3491 SSI_SDATA6_MARK, 3492 }; 3493 static const unsigned int ssi6_ctrl_pins[] = { 3494 /* SCK6, WS6 */ 3495 RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28), 3496 }; 3497 static const unsigned int ssi6_ctrl_mux[] = { 3498 SSI_SCK6_MARK, SSI_WS6_MARK, 3499 }; 3500 static const unsigned int ssi6_data_b_pins[] = { 3501 /* SDATA6 */ 3502 RCAR_GP_PIN(3, 24), 3503 }; 3504 static const unsigned int ssi6_data_b_mux[] = { 3505 SSI_SDATA6_B_MARK, 3506 }; 3507 static const unsigned int ssi6_ctrl_b_pins[] = { 3508 /* SCK6, WS6 */ 3509 RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23), 3510 }; 3511 static const unsigned int ssi6_ctrl_b_mux[] = { 3512 SSI_SCK6_B_MARK, SSI_WS6_B_MARK, 3513 }; 3514 static const unsigned int ssi7_data_pins[] = { 3515 /* SDATA7 */ 3516 RCAR_GP_PIN(5, 0), 3517 }; 3518 static const unsigned int ssi7_data_mux[] = { 3519 SSI_SDATA7_MARK, 3520 }; 3521 static const unsigned int ssi78_ctrl_pins[] = { 3522 /* SCK78, WS78 */ 3523 RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 31), 3524 }; 3525 static const unsigned int ssi78_ctrl_mux[] = { 3526 SSI_SCK78_MARK, SSI_WS78_MARK, 3527 }; 3528 static const unsigned int ssi7_data_b_pins[] = { 3529 /* SDATA7 */ 3530 RCAR_GP_PIN(3, 27), 3531 }; 3532 static const unsigned int ssi7_data_b_mux[] = { 3533 SSI_SDATA7_B_MARK, 3534 }; 3535 static const unsigned int ssi78_ctrl_b_pins[] = { 3536 /* SCK78, WS78 */ 3537 RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26), 3538 }; 3539 static const unsigned int ssi78_ctrl_b_mux[] = { 3540 SSI_SCK78_B_MARK, SSI_WS78_B_MARK, 3541 }; 3542 static const unsigned int ssi8_data_pins[] = { 3543 /* SDATA8 */ 3544 RCAR_GP_PIN(5, 10), 3545 }; 3546 static const unsigned int ssi8_data_mux[] = { 3547 SSI_SDATA8_MARK, 3548 }; 3549 static const unsigned int ssi8_data_b_pins[] = { 3550 /* SDATA8 */ 3551 RCAR_GP_PIN(3, 28), 3552 }; 3553 static const unsigned int ssi8_data_b_mux[] = { 3554 SSI_SDATA8_B_MARK, 3555 }; 3556 static const unsigned int ssi9_data_pins[] = { 3557 /* SDATA9 */ 3558 RCAR_GP_PIN(5, 19), 3559 }; 3560 static const unsigned int ssi9_data_mux[] = { 3561 SSI_SDATA9_MARK, 3562 }; 3563 static const unsigned int ssi9_ctrl_pins[] = { 3564 /* SCK9, WS9 */ 3565 RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18), 3566 }; 3567 static const unsigned int ssi9_ctrl_mux[] = { 3568 SSI_SCK9_MARK, SSI_WS9_MARK, 3569 }; 3570 static const unsigned int ssi9_data_b_pins[] = { 3571 /* SDATA9 */ 3572 RCAR_GP_PIN(4, 19), 3573 }; 3574 static const unsigned int ssi9_data_b_mux[] = { 3575 SSI_SDATA9_B_MARK, 3576 }; 3577 static const unsigned int ssi9_ctrl_b_pins[] = { 3578 /* SCK9, WS9 */ 3579 RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18), 3580 }; 3581 static const unsigned int ssi9_ctrl_b_mux[] = { 3582 SSI_SCK9_B_MARK, SSI_WS9_B_MARK, 3583 }; 3584 /* - TPU -------------------------------------------------------------------- */ 3585 static const unsigned int tpu_to0_pins[] = { 3586 RCAR_GP_PIN(3, 31), 3587 }; 3588 static const unsigned int tpu_to0_mux[] = { 3589 TPUTO0_MARK, 3590 }; 3591 static const unsigned int tpu_to0_b_pins[] = { 3592 RCAR_GP_PIN(3, 30), 3593 }; 3594 static const unsigned int tpu_to0_b_mux[] = { 3595 TPUTO0_B_MARK, 3596 }; 3597 static const unsigned int tpu_to0_c_pins[] = { 3598 RCAR_GP_PIN(1, 18), 3599 }; 3600 static const unsigned int tpu_to0_c_mux[] = { 3601 TPUTO0_C_MARK, 3602 }; 3603 static const unsigned int tpu_to1_pins[] = { 3604 RCAR_GP_PIN(4, 9), 3605 }; 3606 static const unsigned int tpu_to1_mux[] = { 3607 TPUTO1_MARK, 3608 }; 3609 static const unsigned int tpu_to1_b_pins[] = { 3610 RCAR_GP_PIN(4, 0), 3611 }; 3612 static const unsigned int tpu_to1_b_mux[] = { 3613 TPUTO1_B_MARK, 3614 }; 3615 static const unsigned int tpu_to1_c_pins[] = { 3616 RCAR_GP_PIN(4, 4), 3617 }; 3618 static const unsigned int tpu_to1_c_mux[] = { 3619 TPUTO1_C_MARK, 3620 }; 3621 static const unsigned int tpu_to2_pins[] = { 3622 RCAR_GP_PIN(1, 3), 3623 }; 3624 static const unsigned int tpu_to2_mux[] = { 3625 TPUTO2_MARK, 3626 }; 3627 static const unsigned int tpu_to2_b_pins[] = { 3628 RCAR_GP_PIN(1, 0), 3629 }; 3630 static const unsigned int tpu_to2_b_mux[] = { 3631 TPUTO2_B_MARK, 3632 }; 3633 static const unsigned int tpu_to2_c_pins[] = { 3634 RCAR_GP_PIN(0, 22), 3635 }; 3636 static const unsigned int tpu_to2_c_mux[] = { 3637 TPUTO2_C_MARK, 3638 }; 3639 static const unsigned int tpu_to3_pins[] = { 3640 RCAR_GP_PIN(1, 14), 3641 }; 3642 static const unsigned int tpu_to3_mux[] = { 3643 TPUTO3_MARK, 3644 }; 3645 static const unsigned int tpu_to3_b_pins[] = { 3646 RCAR_GP_PIN(1, 13), 3647 }; 3648 static const unsigned int tpu_to3_b_mux[] = { 3649 TPUTO3_B_MARK, 3650 }; 3651 static const unsigned int tpu_to3_c_pins[] = { 3652 RCAR_GP_PIN(0, 21), 3653 }; 3654 static const unsigned int tpu_to3_c_mux[] = { 3655 TPUTO3_C_MARK, 3656 }; 3657 /* - USB0 ------------------------------------------------------------------- */ 3658 static const unsigned int usb0_pins[] = { 3659 RCAR_GP_PIN(5, 24), /* PWEN */ 3660 RCAR_GP_PIN(5, 25), /* OVC */ 3661 }; 3662 static const unsigned int usb0_mux[] = { 3663 USB0_PWEN_MARK, 3664 USB0_OVC_MARK, 3665 }; 3666 /* - USB1 ------------------------------------------------------------------- */ 3667 static const unsigned int usb1_pins[] = { 3668 RCAR_GP_PIN(5, 26), /* PWEN */ 3669 RCAR_GP_PIN(5, 27), /* OVC */ 3670 }; 3671 static const unsigned int usb1_mux[] = { 3672 USB1_PWEN_MARK, 3673 USB1_OVC_MARK, 3674 }; 3675 /* - VIN0 ------------------------------------------------------------------- */ 3676 static const union vin_data vin0_data_pins = { 3677 .data24 = { 3678 /* B */ 3679 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2), 3680 RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4), 3681 RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6), 3682 RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8), 3683 /* G */ 3684 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14), 3685 RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16), 3686 RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18), 3687 RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20), 3688 /* R */ 3689 RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 22), 3690 RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24), 3691 RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26), 3692 RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), 3693 }, 3694 }; 3695 static const union vin_data vin0_data_mux = { 3696 .data24 = { 3697 /* B */ 3698 VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK, 3699 VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK, 3700 VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK, 3701 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK, 3702 /* G */ 3703 VI0_G0_MARK, VI0_G1_MARK, 3704 VI0_G2_MARK, VI0_G3_MARK, 3705 VI0_G4_MARK, VI0_G5_MARK, 3706 VI0_G6_MARK, VI0_G7_MARK, 3707 /* R */ 3708 VI0_R0_MARK, VI0_R1_MARK, 3709 VI0_R2_MARK, VI0_R3_MARK, 3710 VI0_R4_MARK, VI0_R5_MARK, 3711 VI0_R6_MARK, VI0_R7_MARK, 3712 }, 3713 }; 3714 static const unsigned int vin0_data18_pins[] = { 3715 /* B */ 3716 RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4), 3717 RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6), 3718 RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8), 3719 /* G */ 3720 RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16), 3721 RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18), 3722 RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20), 3723 /* R */ 3724 RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24), 3725 RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26), 3726 RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), 3727 }; 3728 static const unsigned int vin0_data18_mux[] = { 3729 /* B */ 3730 VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK, 3731 VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK, 3732 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK, 3733 /* G */ 3734 VI0_G2_MARK, VI0_G3_MARK, 3735 VI0_G4_MARK, VI0_G5_MARK, 3736 VI0_G6_MARK, VI0_G7_MARK, 3737 /* R */ 3738 VI0_R2_MARK, VI0_R3_MARK, 3739 VI0_R4_MARK, VI0_R5_MARK, 3740 VI0_R6_MARK, VI0_R7_MARK, 3741 }; 3742 static const unsigned int vin0_sync_pins[] = { 3743 RCAR_GP_PIN(3, 11), /* HSYNC */ 3744 RCAR_GP_PIN(3, 12), /* VSYNC */ 3745 }; 3746 static const unsigned int vin0_sync_mux[] = { 3747 VI0_HSYNC_N_MARK, 3748 VI0_VSYNC_N_MARK, 3749 }; 3750 static const unsigned int vin0_field_pins[] = { 3751 RCAR_GP_PIN(3, 10), 3752 }; 3753 static const unsigned int vin0_field_mux[] = { 3754 VI0_FIELD_MARK, 3755 }; 3756 static const unsigned int vin0_clkenb_pins[] = { 3757 RCAR_GP_PIN(3, 9), 3758 }; 3759 static const unsigned int vin0_clkenb_mux[] = { 3760 VI0_CLKENB_MARK, 3761 }; 3762 static const unsigned int vin0_clk_pins[] = { 3763 RCAR_GP_PIN(3, 0), 3764 }; 3765 static const unsigned int vin0_clk_mux[] = { 3766 VI0_CLK_MARK, 3767 }; 3768 /* - VIN1 ------------------------------------------------------------------- */ 3769 static const union vin_data12 vin1_data_pins = { 3770 .data12 = { 3771 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13), 3772 RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15), 3773 RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 17), 3774 RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19), 3775 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 11), 3776 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), 3777 }, 3778 }; 3779 static const union vin_data12 vin1_data_mux = { 3780 .data12 = { 3781 VI1_DATA0_MARK, VI1_DATA1_MARK, 3782 VI1_DATA2_MARK, VI1_DATA3_MARK, 3783 VI1_DATA4_MARK, VI1_DATA5_MARK, 3784 VI1_DATA6_MARK, VI1_DATA7_MARK, 3785 VI1_DATA8_MARK, VI1_DATA9_MARK, 3786 VI1_DATA10_MARK, VI1_DATA11_MARK, 3787 }, 3788 }; 3789 static const unsigned int vin1_sync_pins[] = { 3790 RCAR_GP_PIN(5, 22), /* HSYNC */ 3791 RCAR_GP_PIN(5, 23), /* VSYNC */ 3792 }; 3793 static const unsigned int vin1_sync_mux[] = { 3794 VI1_HSYNC_N_MARK, 3795 VI1_VSYNC_N_MARK, 3796 }; 3797 static const unsigned int vin1_field_pins[] = { 3798 RCAR_GP_PIN(5, 21), 3799 }; 3800 static const unsigned int vin1_field_mux[] = { 3801 VI1_FIELD_MARK, 3802 }; 3803 static const unsigned int vin1_clkenb_pins[] = { 3804 RCAR_GP_PIN(5, 20), 3805 }; 3806 static const unsigned int vin1_clkenb_mux[] = { 3807 VI1_CLKENB_MARK, 3808 }; 3809 static const unsigned int vin1_clk_pins[] = { 3810 RCAR_GP_PIN(5, 11), 3811 }; 3812 static const unsigned int vin1_clk_mux[] = { 3813 VI1_CLK_MARK, 3814 }; 3815 3816 static const struct sh_pfc_pin_group pinmux_groups[] = { 3817 SH_PFC_PIN_GROUP(audio_clka), 3818 SH_PFC_PIN_GROUP(audio_clka_b), 3819 SH_PFC_PIN_GROUP(audio_clka_c), 3820 SH_PFC_PIN_GROUP(audio_clka_d), 3821 SH_PFC_PIN_GROUP(audio_clkb), 3822 SH_PFC_PIN_GROUP(audio_clkb_b), 3823 SH_PFC_PIN_GROUP(audio_clkb_c), 3824 SH_PFC_PIN_GROUP(audio_clkc), 3825 SH_PFC_PIN_GROUP(audio_clkc_b), 3826 SH_PFC_PIN_GROUP(audio_clkc_c), 3827 SH_PFC_PIN_GROUP(audio_clkout), 3828 SH_PFC_PIN_GROUP(audio_clkout_b), 3829 SH_PFC_PIN_GROUP(audio_clkout_c), 3830 SH_PFC_PIN_GROUP(avb_link), 3831 SH_PFC_PIN_GROUP(avb_magic), 3832 SH_PFC_PIN_GROUP(avb_phy_int), 3833 SH_PFC_PIN_GROUP(avb_mdio), 3834 SH_PFC_PIN_GROUP(avb_mii), 3835 SH_PFC_PIN_GROUP(avb_gmii), 3836 SH_PFC_PIN_GROUP(can0_data), 3837 SH_PFC_PIN_GROUP(can0_data_b), 3838 SH_PFC_PIN_GROUP(can0_data_c), 3839 SH_PFC_PIN_GROUP(can0_data_d), 3840 SH_PFC_PIN_GROUP(can1_data), 3841 SH_PFC_PIN_GROUP(can1_data_b), 3842 SH_PFC_PIN_GROUP(can1_data_c), 3843 SH_PFC_PIN_GROUP(can1_data_d), 3844 SH_PFC_PIN_GROUP(can_clk), 3845 SH_PFC_PIN_GROUP(can_clk_b), 3846 SH_PFC_PIN_GROUP(can_clk_c), 3847 SH_PFC_PIN_GROUP(can_clk_d), 3848 SH_PFC_PIN_GROUP(du0_rgb666), 3849 SH_PFC_PIN_GROUP(du0_rgb888), 3850 SH_PFC_PIN_GROUP(du0_clk0_out), 3851 SH_PFC_PIN_GROUP(du0_clk1_out), 3852 SH_PFC_PIN_GROUP(du0_clk_in), 3853 SH_PFC_PIN_GROUP(du0_sync), 3854 SH_PFC_PIN_GROUP(du0_oddf), 3855 SH_PFC_PIN_GROUP(du0_cde), 3856 SH_PFC_PIN_GROUP(du0_disp), 3857 SH_PFC_PIN_GROUP(du1_rgb666), 3858 SH_PFC_PIN_GROUP(du1_rgb888), 3859 SH_PFC_PIN_GROUP(du1_clk0_out), 3860 SH_PFC_PIN_GROUP(du1_clk1_out), 3861 SH_PFC_PIN_GROUP(du1_clk_in), 3862 SH_PFC_PIN_GROUP(du1_sync), 3863 SH_PFC_PIN_GROUP(du1_oddf), 3864 SH_PFC_PIN_GROUP(du1_cde), 3865 SH_PFC_PIN_GROUP(du1_disp), 3866 SH_PFC_PIN_GROUP(eth_link), 3867 SH_PFC_PIN_GROUP(eth_magic), 3868 SH_PFC_PIN_GROUP(eth_mdio), 3869 SH_PFC_PIN_GROUP(eth_rmii), 3870 SH_PFC_PIN_GROUP(eth_link_b), 3871 SH_PFC_PIN_GROUP(eth_magic_b), 3872 SH_PFC_PIN_GROUP(eth_mdio_b), 3873 SH_PFC_PIN_GROUP(eth_rmii_b), 3874 SH_PFC_PIN_GROUP(hscif0_data), 3875 SH_PFC_PIN_GROUP(hscif0_clk), 3876 SH_PFC_PIN_GROUP(hscif0_ctrl), 3877 SH_PFC_PIN_GROUP(hscif0_data_b), 3878 SH_PFC_PIN_GROUP(hscif0_clk_b), 3879 SH_PFC_PIN_GROUP(hscif1_data), 3880 SH_PFC_PIN_GROUP(hscif1_clk), 3881 SH_PFC_PIN_GROUP(hscif1_ctrl), 3882 SH_PFC_PIN_GROUP(hscif1_data_b), 3883 SH_PFC_PIN_GROUP(hscif1_ctrl_b), 3884 SH_PFC_PIN_GROUP(hscif2_data), 3885 SH_PFC_PIN_GROUP(hscif2_clk), 3886 SH_PFC_PIN_GROUP(hscif2_ctrl), 3887 SH_PFC_PIN_GROUP(i2c0), 3888 SH_PFC_PIN_GROUP(i2c0_b), 3889 SH_PFC_PIN_GROUP(i2c0_c), 3890 SH_PFC_PIN_GROUP(i2c0_d), 3891 SH_PFC_PIN_GROUP(i2c0_e), 3892 SH_PFC_PIN_GROUP(i2c1), 3893 SH_PFC_PIN_GROUP(i2c1_b), 3894 SH_PFC_PIN_GROUP(i2c1_c), 3895 SH_PFC_PIN_GROUP(i2c1_d), 3896 SH_PFC_PIN_GROUP(i2c1_e), 3897 SH_PFC_PIN_GROUP(i2c2), 3898 SH_PFC_PIN_GROUP(i2c2_b), 3899 SH_PFC_PIN_GROUP(i2c2_c), 3900 SH_PFC_PIN_GROUP(i2c2_d), 3901 SH_PFC_PIN_GROUP(i2c2_e), 3902 SH_PFC_PIN_GROUP(i2c3), 3903 SH_PFC_PIN_GROUP(i2c3_b), 3904 SH_PFC_PIN_GROUP(i2c3_c), 3905 SH_PFC_PIN_GROUP(i2c3_d), 3906 SH_PFC_PIN_GROUP(i2c3_e), 3907 SH_PFC_PIN_GROUP(i2c4), 3908 SH_PFC_PIN_GROUP(i2c4_b), 3909 SH_PFC_PIN_GROUP(i2c4_c), 3910 SH_PFC_PIN_GROUP(i2c4_d), 3911 SH_PFC_PIN_GROUP(i2c4_e), 3912 SH_PFC_PIN_GROUP(i2c5), 3913 SH_PFC_PIN_GROUP(i2c5_b), 3914 SH_PFC_PIN_GROUP(i2c5_c), 3915 SH_PFC_PIN_GROUP(i2c5_d), 3916 SH_PFC_PIN_GROUP(intc_irq0), 3917 SH_PFC_PIN_GROUP(intc_irq1), 3918 SH_PFC_PIN_GROUP(intc_irq2), 3919 SH_PFC_PIN_GROUP(intc_irq3), 3920 SH_PFC_PIN_GROUP(intc_irq4), 3921 SH_PFC_PIN_GROUP(intc_irq5), 3922 SH_PFC_PIN_GROUP(intc_irq6), 3923 SH_PFC_PIN_GROUP(intc_irq7), 3924 SH_PFC_PIN_GROUP(intc_irq8), 3925 SH_PFC_PIN_GROUP(intc_irq9), 3926 SH_PFC_PIN_GROUP(mmc_data1), 3927 SH_PFC_PIN_GROUP(mmc_data4), 3928 SH_PFC_PIN_GROUP(mmc_data8), 3929 SH_PFC_PIN_GROUP(mmc_ctrl), 3930 SH_PFC_PIN_GROUP(msiof0_clk), 3931 SH_PFC_PIN_GROUP(msiof0_sync), 3932 SH_PFC_PIN_GROUP(msiof0_ss1), 3933 SH_PFC_PIN_GROUP(msiof0_ss2), 3934 SH_PFC_PIN_GROUP(msiof0_rx), 3935 SH_PFC_PIN_GROUP(msiof0_tx), 3936 SH_PFC_PIN_GROUP(msiof1_clk), 3937 SH_PFC_PIN_GROUP(msiof1_sync), 3938 SH_PFC_PIN_GROUP(msiof1_ss1), 3939 SH_PFC_PIN_GROUP(msiof1_ss2), 3940 SH_PFC_PIN_GROUP(msiof1_rx), 3941 SH_PFC_PIN_GROUP(msiof1_tx), 3942 SH_PFC_PIN_GROUP(msiof1_clk_b), 3943 SH_PFC_PIN_GROUP(msiof1_sync_b), 3944 SH_PFC_PIN_GROUP(msiof1_ss1_b), 3945 SH_PFC_PIN_GROUP(msiof1_ss2_b), 3946 SH_PFC_PIN_GROUP(msiof1_rx_b), 3947 SH_PFC_PIN_GROUP(msiof1_tx_b), 3948 SH_PFC_PIN_GROUP(msiof2_clk), 3949 SH_PFC_PIN_GROUP(msiof2_sync), 3950 SH_PFC_PIN_GROUP(msiof2_ss1), 3951 SH_PFC_PIN_GROUP(msiof2_ss2), 3952 SH_PFC_PIN_GROUP(msiof2_rx), 3953 SH_PFC_PIN_GROUP(msiof2_tx), 3954 SH_PFC_PIN_GROUP(msiof2_clk_b), 3955 SH_PFC_PIN_GROUP(msiof2_sync_b), 3956 SH_PFC_PIN_GROUP(msiof2_ss1_b), 3957 SH_PFC_PIN_GROUP(msiof2_ss2_b), 3958 SH_PFC_PIN_GROUP(msiof2_rx_b), 3959 SH_PFC_PIN_GROUP(msiof2_tx_b), 3960 SH_PFC_PIN_GROUP(pwm0), 3961 SH_PFC_PIN_GROUP(pwm0_b), 3962 SH_PFC_PIN_GROUP(pwm1), 3963 SH_PFC_PIN_GROUP(pwm1_b), 3964 SH_PFC_PIN_GROUP(pwm1_c), 3965 SH_PFC_PIN_GROUP(pwm2), 3966 SH_PFC_PIN_GROUP(pwm2_b), 3967 SH_PFC_PIN_GROUP(pwm2_c), 3968 SH_PFC_PIN_GROUP(pwm3), 3969 SH_PFC_PIN_GROUP(pwm3_b), 3970 SH_PFC_PIN_GROUP(pwm4), 3971 SH_PFC_PIN_GROUP(pwm4_b), 3972 SH_PFC_PIN_GROUP(pwm5), 3973 SH_PFC_PIN_GROUP(pwm5_b), 3974 SH_PFC_PIN_GROUP(pwm5_c), 3975 SH_PFC_PIN_GROUP(pwm6), 3976 SH_PFC_PIN_GROUP(pwm6_b), 3977 SH_PFC_PIN_GROUP(qspi_ctrl), 3978 SH_PFC_PIN_GROUP(qspi_data2), 3979 SH_PFC_PIN_GROUP(qspi_data4), 3980 SH_PFC_PIN_GROUP(scif0_data), 3981 SH_PFC_PIN_GROUP(scif0_data_b), 3982 SH_PFC_PIN_GROUP(scif0_data_c), 3983 SH_PFC_PIN_GROUP(scif0_data_d), 3984 SH_PFC_PIN_GROUP(scif1_data), 3985 SH_PFC_PIN_GROUP(scif1_clk), 3986 SH_PFC_PIN_GROUP(scif1_data_b), 3987 SH_PFC_PIN_GROUP(scif1_clk_b), 3988 SH_PFC_PIN_GROUP(scif1_data_c), 3989 SH_PFC_PIN_GROUP(scif1_clk_c), 3990 SH_PFC_PIN_GROUP(scif2_data), 3991 SH_PFC_PIN_GROUP(scif2_clk), 3992 SH_PFC_PIN_GROUP(scif2_data_b), 3993 SH_PFC_PIN_GROUP(scif2_clk_b), 3994 SH_PFC_PIN_GROUP(scif2_data_c), 3995 SH_PFC_PIN_GROUP(scif2_clk_c), 3996 SH_PFC_PIN_GROUP(scif3_data), 3997 SH_PFC_PIN_GROUP(scif3_clk), 3998 SH_PFC_PIN_GROUP(scif3_data_b), 3999 SH_PFC_PIN_GROUP(scif3_clk_b), 4000 SH_PFC_PIN_GROUP(scif4_data), 4001 SH_PFC_PIN_GROUP(scif4_data_b), 4002 SH_PFC_PIN_GROUP(scif4_data_c), 4003 SH_PFC_PIN_GROUP(scif4_data_d), 4004 SH_PFC_PIN_GROUP(scif4_data_e), 4005 SH_PFC_PIN_GROUP(scif5_data), 4006 SH_PFC_PIN_GROUP(scif5_data_b), 4007 SH_PFC_PIN_GROUP(scif5_data_c), 4008 SH_PFC_PIN_GROUP(scif5_data_d), 4009 SH_PFC_PIN_GROUP(scifa0_data), 4010 SH_PFC_PIN_GROUP(scifa0_data_b), 4011 SH_PFC_PIN_GROUP(scifa0_data_c), 4012 SH_PFC_PIN_GROUP(scifa0_data_d), 4013 SH_PFC_PIN_GROUP(scifa1_data), 4014 SH_PFC_PIN_GROUP(scifa1_clk), 4015 SH_PFC_PIN_GROUP(scifa1_data_b), 4016 SH_PFC_PIN_GROUP(scifa1_clk_b), 4017 SH_PFC_PIN_GROUP(scifa1_data_c), 4018 SH_PFC_PIN_GROUP(scifa1_clk_c), 4019 SH_PFC_PIN_GROUP(scifa2_data), 4020 SH_PFC_PIN_GROUP(scifa2_clk), 4021 SH_PFC_PIN_GROUP(scifa2_data_b), 4022 SH_PFC_PIN_GROUP(scifa2_clk_b), 4023 SH_PFC_PIN_GROUP(scifa3_data), 4024 SH_PFC_PIN_GROUP(scifa3_clk), 4025 SH_PFC_PIN_GROUP(scifa3_data_b), 4026 SH_PFC_PIN_GROUP(scifa3_clk_b), 4027 SH_PFC_PIN_GROUP(scifa4_data), 4028 SH_PFC_PIN_GROUP(scifa4_data_b), 4029 SH_PFC_PIN_GROUP(scifa4_data_c), 4030 SH_PFC_PIN_GROUP(scifa4_data_d), 4031 SH_PFC_PIN_GROUP(scifa5_data), 4032 SH_PFC_PIN_GROUP(scifa5_data_b), 4033 SH_PFC_PIN_GROUP(scifa5_data_c), 4034 SH_PFC_PIN_GROUP(scifa5_data_d), 4035 SH_PFC_PIN_GROUP(scifb0_data), 4036 SH_PFC_PIN_GROUP(scifb0_clk), 4037 SH_PFC_PIN_GROUP(scifb0_ctrl), 4038 SH_PFC_PIN_GROUP(scifb1_data), 4039 SH_PFC_PIN_GROUP(scifb1_clk), 4040 SH_PFC_PIN_GROUP(scifb2_data), 4041 SH_PFC_PIN_GROUP(scifb2_clk), 4042 SH_PFC_PIN_GROUP(scifb2_ctrl), 4043 SH_PFC_PIN_GROUP(scif_clk), 4044 SH_PFC_PIN_GROUP(scif_clk_b), 4045 SH_PFC_PIN_GROUP(sdhi0_data1), 4046 SH_PFC_PIN_GROUP(sdhi0_data4), 4047 SH_PFC_PIN_GROUP(sdhi0_ctrl), 4048 SH_PFC_PIN_GROUP(sdhi0_cd), 4049 SH_PFC_PIN_GROUP(sdhi0_wp), 4050 SH_PFC_PIN_GROUP(sdhi1_data1), 4051 SH_PFC_PIN_GROUP(sdhi1_data4), 4052 SH_PFC_PIN_GROUP(sdhi1_ctrl), 4053 SH_PFC_PIN_GROUP(sdhi1_cd), 4054 SH_PFC_PIN_GROUP(sdhi1_wp), 4055 SH_PFC_PIN_GROUP(sdhi2_data1), 4056 SH_PFC_PIN_GROUP(sdhi2_data4), 4057 SH_PFC_PIN_GROUP(sdhi2_ctrl), 4058 SH_PFC_PIN_GROUP(sdhi2_cd), 4059 SH_PFC_PIN_GROUP(sdhi2_wp), 4060 SH_PFC_PIN_GROUP(ssi0_data), 4061 SH_PFC_PIN_GROUP(ssi0129_ctrl), 4062 SH_PFC_PIN_GROUP(ssi1_data), 4063 SH_PFC_PIN_GROUP(ssi1_ctrl), 4064 SH_PFC_PIN_GROUP(ssi1_data_b), 4065 SH_PFC_PIN_GROUP(ssi1_ctrl_b), 4066 SH_PFC_PIN_GROUP(ssi2_data), 4067 SH_PFC_PIN_GROUP(ssi2_ctrl), 4068 SH_PFC_PIN_GROUP(ssi2_data_b), 4069 SH_PFC_PIN_GROUP(ssi2_ctrl_b), 4070 SH_PFC_PIN_GROUP(ssi3_data), 4071 SH_PFC_PIN_GROUP(ssi34_ctrl), 4072 SH_PFC_PIN_GROUP(ssi4_data), 4073 SH_PFC_PIN_GROUP(ssi4_ctrl), 4074 SH_PFC_PIN_GROUP(ssi4_data_b), 4075 SH_PFC_PIN_GROUP(ssi4_ctrl_b), 4076 SH_PFC_PIN_GROUP(ssi5_data), 4077 SH_PFC_PIN_GROUP(ssi5_ctrl), 4078 SH_PFC_PIN_GROUP(ssi5_data_b), 4079 SH_PFC_PIN_GROUP(ssi5_ctrl_b), 4080 SH_PFC_PIN_GROUP(ssi6_data), 4081 SH_PFC_PIN_GROUP(ssi6_ctrl), 4082 SH_PFC_PIN_GROUP(ssi6_data_b), 4083 SH_PFC_PIN_GROUP(ssi6_ctrl_b), 4084 SH_PFC_PIN_GROUP(ssi7_data), 4085 SH_PFC_PIN_GROUP(ssi78_ctrl), 4086 SH_PFC_PIN_GROUP(ssi7_data_b), 4087 SH_PFC_PIN_GROUP(ssi78_ctrl_b), 4088 SH_PFC_PIN_GROUP(ssi8_data), 4089 SH_PFC_PIN_GROUP(ssi8_data_b), 4090 SH_PFC_PIN_GROUP(ssi9_data), 4091 SH_PFC_PIN_GROUP(ssi9_ctrl), 4092 SH_PFC_PIN_GROUP(ssi9_data_b), 4093 SH_PFC_PIN_GROUP(ssi9_ctrl_b), 4094 SH_PFC_PIN_GROUP(tpu_to0), 4095 SH_PFC_PIN_GROUP(tpu_to0_b), 4096 SH_PFC_PIN_GROUP(tpu_to0_c), 4097 SH_PFC_PIN_GROUP(tpu_to1), 4098 SH_PFC_PIN_GROUP(tpu_to1_b), 4099 SH_PFC_PIN_GROUP(tpu_to1_c), 4100 SH_PFC_PIN_GROUP(tpu_to2), 4101 SH_PFC_PIN_GROUP(tpu_to2_b), 4102 SH_PFC_PIN_GROUP(tpu_to2_c), 4103 SH_PFC_PIN_GROUP(tpu_to3), 4104 SH_PFC_PIN_GROUP(tpu_to3_b), 4105 SH_PFC_PIN_GROUP(tpu_to3_c), 4106 SH_PFC_PIN_GROUP(usb0), 4107 SH_PFC_PIN_GROUP(usb1), 4108 VIN_DATA_PIN_GROUP(vin0_data, 24), 4109 VIN_DATA_PIN_GROUP(vin0_data, 20), 4110 SH_PFC_PIN_GROUP(vin0_data18), 4111 VIN_DATA_PIN_GROUP(vin0_data, 16), 4112 VIN_DATA_PIN_GROUP(vin0_data, 12), 4113 VIN_DATA_PIN_GROUP(vin0_data, 10), 4114 VIN_DATA_PIN_GROUP(vin0_data, 8), 4115 SH_PFC_PIN_GROUP(vin0_sync), 4116 SH_PFC_PIN_GROUP(vin0_field), 4117 SH_PFC_PIN_GROUP(vin0_clkenb), 4118 SH_PFC_PIN_GROUP(vin0_clk), 4119 VIN_DATA_PIN_GROUP(vin1_data, 12), 4120 VIN_DATA_PIN_GROUP(vin1_data, 10), 4121 VIN_DATA_PIN_GROUP(vin1_data, 8), 4122 SH_PFC_PIN_GROUP(vin1_sync), 4123 SH_PFC_PIN_GROUP(vin1_field), 4124 SH_PFC_PIN_GROUP(vin1_clkenb), 4125 SH_PFC_PIN_GROUP(vin1_clk), 4126 }; 4127 4128 static const char * const audio_clk_groups[] = { 4129 "audio_clka", 4130 "audio_clka_b", 4131 "audio_clka_c", 4132 "audio_clka_d", 4133 "audio_clkb", 4134 "audio_clkb_b", 4135 "audio_clkb_c", 4136 "audio_clkc", 4137 "audio_clkc_b", 4138 "audio_clkc_c", 4139 "audio_clkout", 4140 "audio_clkout_b", 4141 "audio_clkout_c", 4142 }; 4143 4144 static const char * const avb_groups[] = { 4145 "avb_link", 4146 "avb_magic", 4147 "avb_phy_int", 4148 "avb_mdio", 4149 "avb_mii", 4150 "avb_gmii", 4151 }; 4152 4153 static const char * const can0_groups[] = { 4154 "can0_data", 4155 "can0_data_b", 4156 "can0_data_c", 4157 "can0_data_d", 4158 /* 4159 * Retained for backwards compatibility, use can_clk_groups in new 4160 * designs. 4161 */ 4162 "can_clk", 4163 "can_clk_b", 4164 "can_clk_c", 4165 "can_clk_d", 4166 }; 4167 4168 static const char * const can1_groups[] = { 4169 "can1_data", 4170 "can1_data_b", 4171 "can1_data_c", 4172 "can1_data_d", 4173 /* 4174 * Retained for backwards compatibility, use can_clk_groups in new 4175 * designs. 4176 */ 4177 "can_clk", 4178 "can_clk_b", 4179 "can_clk_c", 4180 "can_clk_d", 4181 }; 4182 4183 /* 4184 * can_clk_groups allows for independent configuration, use can_clk function 4185 * in new designs. 4186 */ 4187 static const char * const can_clk_groups[] = { 4188 "can_clk", 4189 "can_clk_b", 4190 "can_clk_c", 4191 "can_clk_d", 4192 }; 4193 4194 static const char * const du0_groups[] = { 4195 "du0_rgb666", 4196 "du0_rgb888", 4197 "du0_clk0_out", 4198 "du0_clk1_out", 4199 "du0_clk_in", 4200 "du0_sync", 4201 "du0_oddf", 4202 "du0_cde", 4203 "du0_disp", 4204 }; 4205 4206 static const char * const du1_groups[] = { 4207 "du1_rgb666", 4208 "du1_rgb888", 4209 "du1_clk0_out", 4210 "du1_clk1_out", 4211 "du1_clk_in", 4212 "du1_sync", 4213 "du1_oddf", 4214 "du1_cde", 4215 "du1_disp", 4216 }; 4217 4218 static const char * const eth_groups[] = { 4219 "eth_link", 4220 "eth_magic", 4221 "eth_mdio", 4222 "eth_rmii", 4223 "eth_link_b", 4224 "eth_magic_b", 4225 "eth_mdio_b", 4226 "eth_rmii_b", 4227 }; 4228 4229 static const char * const hscif0_groups[] = { 4230 "hscif0_data", 4231 "hscif0_clk", 4232 "hscif0_ctrl", 4233 "hscif0_data_b", 4234 "hscif0_clk_b", 4235 }; 4236 4237 static const char * const hscif1_groups[] = { 4238 "hscif1_data", 4239 "hscif1_clk", 4240 "hscif1_ctrl", 4241 "hscif1_data_b", 4242 "hscif1_ctrl_b", 4243 }; 4244 4245 static const char * const hscif2_groups[] = { 4246 "hscif2_data", 4247 "hscif2_clk", 4248 "hscif2_ctrl", 4249 }; 4250 4251 static const char * const i2c0_groups[] = { 4252 "i2c0", 4253 "i2c0_b", 4254 "i2c0_c", 4255 "i2c0_d", 4256 "i2c0_e", 4257 }; 4258 4259 static const char * const i2c1_groups[] = { 4260 "i2c1", 4261 "i2c1_b", 4262 "i2c1_c", 4263 "i2c1_d", 4264 "i2c1_e", 4265 }; 4266 4267 static const char * const i2c2_groups[] = { 4268 "i2c2", 4269 "i2c2_b", 4270 "i2c2_c", 4271 "i2c2_d", 4272 "i2c2_e", 4273 }; 4274 4275 static const char * const i2c3_groups[] = { 4276 "i2c3", 4277 "i2c3_b", 4278 "i2c3_c", 4279 "i2c3_d", 4280 "i2c3_e", 4281 }; 4282 4283 static const char * const i2c4_groups[] = { 4284 "i2c4", 4285 "i2c4_b", 4286 "i2c4_c", 4287 "i2c4_d", 4288 "i2c4_e", 4289 }; 4290 4291 static const char * const i2c5_groups[] = { 4292 "i2c5", 4293 "i2c5_b", 4294 "i2c5_c", 4295 "i2c5_d", 4296 }; 4297 4298 static const char * const intc_groups[] = { 4299 "intc_irq0", 4300 "intc_irq1", 4301 "intc_irq2", 4302 "intc_irq3", 4303 "intc_irq4", 4304 "intc_irq5", 4305 "intc_irq6", 4306 "intc_irq7", 4307 "intc_irq8", 4308 "intc_irq9", 4309 }; 4310 4311 static const char * const mmc_groups[] = { 4312 "mmc_data1", 4313 "mmc_data4", 4314 "mmc_data8", 4315 "mmc_ctrl", 4316 }; 4317 4318 static const char * const msiof0_groups[] = { 4319 "msiof0_clk", 4320 "msiof0_sync", 4321 "msiof0_ss1", 4322 "msiof0_ss2", 4323 "msiof0_rx", 4324 "msiof0_tx", 4325 }; 4326 4327 static const char * const msiof1_groups[] = { 4328 "msiof1_clk", 4329 "msiof1_sync", 4330 "msiof1_ss1", 4331 "msiof1_ss2", 4332 "msiof1_rx", 4333 "msiof1_tx", 4334 "msiof1_clk_b", 4335 "msiof1_sync_b", 4336 "msiof1_ss1_b", 4337 "msiof1_ss2_b", 4338 "msiof1_rx_b", 4339 "msiof1_tx_b", 4340 }; 4341 4342 static const char * const msiof2_groups[] = { 4343 "msiof2_clk", 4344 "msiof2_sync", 4345 "msiof2_ss1", 4346 "msiof2_ss2", 4347 "msiof2_rx", 4348 "msiof2_tx", 4349 "msiof2_clk_b", 4350 "msiof2_sync_b", 4351 "msiof2_ss1_b", 4352 "msiof2_ss2_b", 4353 "msiof2_rx_b", 4354 "msiof2_tx_b", 4355 }; 4356 4357 static const char * const pwm0_groups[] = { 4358 "pwm0", 4359 "pwm0_b", 4360 }; 4361 4362 static const char * const pwm1_groups[] = { 4363 "pwm1", 4364 "pwm1_b", 4365 "pwm1_c", 4366 }; 4367 4368 static const char * const pwm2_groups[] = { 4369 "pwm2", 4370 "pwm2_b", 4371 "pwm2_c", 4372 }; 4373 4374 static const char * const pwm3_groups[] = { 4375 "pwm3", 4376 "pwm3_b", 4377 }; 4378 4379 static const char * const pwm4_groups[] = { 4380 "pwm4", 4381 "pwm4_b", 4382 }; 4383 4384 static const char * const pwm5_groups[] = { 4385 "pwm5", 4386 "pwm5_b", 4387 "pwm5_c", 4388 }; 4389 4390 static const char * const pwm6_groups[] = { 4391 "pwm6", 4392 "pwm6_b", 4393 }; 4394 4395 static const char * const qspi_groups[] = { 4396 "qspi_ctrl", 4397 "qspi_data2", 4398 "qspi_data4", 4399 }; 4400 4401 static const char * const scif0_groups[] = { 4402 "scif0_data", 4403 "scif0_data_b", 4404 "scif0_data_c", 4405 "scif0_data_d", 4406 }; 4407 4408 static const char * const scif1_groups[] = { 4409 "scif1_data", 4410 "scif1_clk", 4411 "scif1_data_b", 4412 "scif1_clk_b", 4413 "scif1_data_c", 4414 "scif1_clk_c", 4415 }; 4416 4417 static const char * const scif2_groups[] = { 4418 "scif2_data", 4419 "scif2_clk", 4420 "scif2_data_b", 4421 "scif2_clk_b", 4422 "scif2_data_c", 4423 "scif2_clk_c", 4424 }; 4425 4426 static const char * const scif3_groups[] = { 4427 "scif3_data", 4428 "scif3_clk", 4429 "scif3_data_b", 4430 "scif3_clk_b", 4431 }; 4432 4433 static const char * const scif4_groups[] = { 4434 "scif4_data", 4435 "scif4_data_b", 4436 "scif4_data_c", 4437 "scif4_data_d", 4438 "scif4_data_e", 4439 }; 4440 4441 static const char * const scif5_groups[] = { 4442 "scif5_data", 4443 "scif5_data_b", 4444 "scif5_data_c", 4445 "scif5_data_d", 4446 }; 4447 4448 static const char * const scifa0_groups[] = { 4449 "scifa0_data", 4450 "scifa0_data_b", 4451 "scifa0_data_c", 4452 "scifa0_data_d", 4453 }; 4454 4455 static const char * const scifa1_groups[] = { 4456 "scifa1_data", 4457 "scifa1_clk", 4458 "scifa1_data_b", 4459 "scifa1_clk_b", 4460 "scifa1_data_c", 4461 "scifa1_clk_c", 4462 }; 4463 4464 static const char * const scifa2_groups[] = { 4465 "scifa2_data", 4466 "scifa2_clk", 4467 "scifa2_data_b", 4468 "scifa2_clk_b", 4469 }; 4470 4471 static const char * const scifa3_groups[] = { 4472 "scifa3_data", 4473 "scifa3_clk", 4474 "scifa3_data_b", 4475 "scifa3_clk_b", 4476 }; 4477 4478 static const char * const scifa4_groups[] = { 4479 "scifa4_data", 4480 "scifa4_data_b", 4481 "scifa4_data_c", 4482 "scifa4_data_d", 4483 }; 4484 4485 static const char * const scifa5_groups[] = { 4486 "scifa5_data", 4487 "scifa5_data_b", 4488 "scifa5_data_c", 4489 "scifa5_data_d", 4490 }; 4491 4492 static const char * const scifb0_groups[] = { 4493 "scifb0_data", 4494 "scifb0_clk", 4495 "scifb0_ctrl", 4496 }; 4497 4498 static const char * const scifb1_groups[] = { 4499 "scifb1_data", 4500 "scifb1_clk", 4501 }; 4502 4503 static const char * const scifb2_groups[] = { 4504 "scifb2_data", 4505 "scifb2_clk", 4506 "scifb2_ctrl", 4507 }; 4508 4509 static const char * const scif_clk_groups[] = { 4510 "scif_clk", 4511 "scif_clk_b", 4512 }; 4513 4514 static const char * const sdhi0_groups[] = { 4515 "sdhi0_data1", 4516 "sdhi0_data4", 4517 "sdhi0_ctrl", 4518 "sdhi0_cd", 4519 "sdhi0_wp", 4520 }; 4521 4522 static const char * const sdhi1_groups[] = { 4523 "sdhi1_data1", 4524 "sdhi1_data4", 4525 "sdhi1_ctrl", 4526 "sdhi1_cd", 4527 "sdhi1_wp", 4528 }; 4529 4530 static const char * const sdhi2_groups[] = { 4531 "sdhi2_data1", 4532 "sdhi2_data4", 4533 "sdhi2_ctrl", 4534 "sdhi2_cd", 4535 "sdhi2_wp", 4536 }; 4537 4538 static const char * const ssi_groups[] = { 4539 "ssi0_data", 4540 "ssi0129_ctrl", 4541 "ssi1_data", 4542 "ssi1_ctrl", 4543 "ssi1_data_b", 4544 "ssi1_ctrl_b", 4545 "ssi2_data", 4546 "ssi2_ctrl", 4547 "ssi2_data_b", 4548 "ssi2_ctrl_b", 4549 "ssi3_data", 4550 "ssi34_ctrl", 4551 "ssi4_data", 4552 "ssi4_ctrl", 4553 "ssi4_data_b", 4554 "ssi4_ctrl_b", 4555 "ssi5_data", 4556 "ssi5_ctrl", 4557 "ssi5_data_b", 4558 "ssi5_ctrl_b", 4559 "ssi6_data", 4560 "ssi6_ctrl", 4561 "ssi6_data_b", 4562 "ssi6_ctrl_b", 4563 "ssi7_data", 4564 "ssi78_ctrl", 4565 "ssi7_data_b", 4566 "ssi78_ctrl_b", 4567 "ssi8_data", 4568 "ssi8_data_b", 4569 "ssi9_data", 4570 "ssi9_ctrl", 4571 "ssi9_data_b", 4572 "ssi9_ctrl_b", 4573 }; 4574 4575 static const char * const tpu_groups[] = { 4576 "tpu_to0", 4577 "tpu_to0_b", 4578 "tpu_to0_c", 4579 "tpu_to1", 4580 "tpu_to1_b", 4581 "tpu_to1_c", 4582 "tpu_to2", 4583 "tpu_to2_b", 4584 "tpu_to2_c", 4585 "tpu_to3", 4586 "tpu_to3_b", 4587 "tpu_to3_c", 4588 }; 4589 4590 static const char * const usb0_groups[] = { 4591 "usb0", 4592 }; 4593 4594 static const char * const usb1_groups[] = { 4595 "usb1", 4596 }; 4597 4598 static const char * const vin0_groups[] = { 4599 "vin0_data24", 4600 "vin0_data20", 4601 "vin0_data18", 4602 "vin0_data16", 4603 "vin0_data12", 4604 "vin0_data10", 4605 "vin0_data8", 4606 "vin0_sync", 4607 "vin0_field", 4608 "vin0_clkenb", 4609 "vin0_clk", 4610 }; 4611 4612 static const char * const vin1_groups[] = { 4613 "vin1_data12", 4614 "vin1_data10", 4615 "vin1_data8", 4616 "vin1_sync", 4617 "vin1_field", 4618 "vin1_clkenb", 4619 "vin1_clk", 4620 }; 4621 4622 static const struct sh_pfc_function pinmux_functions[] = { 4623 SH_PFC_FUNCTION(audio_clk), 4624 SH_PFC_FUNCTION(avb), 4625 SH_PFC_FUNCTION(can0), 4626 SH_PFC_FUNCTION(can1), 4627 SH_PFC_FUNCTION(can_clk), 4628 SH_PFC_FUNCTION(du0), 4629 SH_PFC_FUNCTION(du1), 4630 SH_PFC_FUNCTION(eth), 4631 SH_PFC_FUNCTION(hscif0), 4632 SH_PFC_FUNCTION(hscif1), 4633 SH_PFC_FUNCTION(hscif2), 4634 SH_PFC_FUNCTION(i2c0), 4635 SH_PFC_FUNCTION(i2c1), 4636 SH_PFC_FUNCTION(i2c2), 4637 SH_PFC_FUNCTION(i2c3), 4638 SH_PFC_FUNCTION(i2c4), 4639 SH_PFC_FUNCTION(i2c5), 4640 SH_PFC_FUNCTION(intc), 4641 SH_PFC_FUNCTION(mmc), 4642 SH_PFC_FUNCTION(msiof0), 4643 SH_PFC_FUNCTION(msiof1), 4644 SH_PFC_FUNCTION(msiof2), 4645 SH_PFC_FUNCTION(pwm0), 4646 SH_PFC_FUNCTION(pwm1), 4647 SH_PFC_FUNCTION(pwm2), 4648 SH_PFC_FUNCTION(pwm3), 4649 SH_PFC_FUNCTION(pwm4), 4650 SH_PFC_FUNCTION(pwm5), 4651 SH_PFC_FUNCTION(pwm6), 4652 SH_PFC_FUNCTION(qspi), 4653 SH_PFC_FUNCTION(scif0), 4654 SH_PFC_FUNCTION(scif1), 4655 SH_PFC_FUNCTION(scif2), 4656 SH_PFC_FUNCTION(scif3), 4657 SH_PFC_FUNCTION(scif4), 4658 SH_PFC_FUNCTION(scif5), 4659 SH_PFC_FUNCTION(scifa0), 4660 SH_PFC_FUNCTION(scifa1), 4661 SH_PFC_FUNCTION(scifa2), 4662 SH_PFC_FUNCTION(scifa3), 4663 SH_PFC_FUNCTION(scifa4), 4664 SH_PFC_FUNCTION(scifa5), 4665 SH_PFC_FUNCTION(scifb0), 4666 SH_PFC_FUNCTION(scifb1), 4667 SH_PFC_FUNCTION(scifb2), 4668 SH_PFC_FUNCTION(scif_clk), 4669 SH_PFC_FUNCTION(sdhi0), 4670 SH_PFC_FUNCTION(sdhi1), 4671 SH_PFC_FUNCTION(sdhi2), 4672 SH_PFC_FUNCTION(ssi), 4673 SH_PFC_FUNCTION(tpu), 4674 SH_PFC_FUNCTION(usb0), 4675 SH_PFC_FUNCTION(usb1), 4676 SH_PFC_FUNCTION(vin0), 4677 SH_PFC_FUNCTION(vin1), 4678 }; 4679 4680 static const struct pinmux_cfg_reg pinmux_config_regs[] = { 4681 { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1, GROUP( 4682 GP_0_31_FN, FN_IP2_17_16, 4683 GP_0_30_FN, FN_IP2_15_14, 4684 GP_0_29_FN, FN_IP2_13_12, 4685 GP_0_28_FN, FN_IP2_11_10, 4686 GP_0_27_FN, FN_IP2_9_8, 4687 GP_0_26_FN, FN_IP2_7_6, 4688 GP_0_25_FN, FN_IP2_5_4, 4689 GP_0_24_FN, FN_IP2_3_2, 4690 GP_0_23_FN, FN_IP2_1_0, 4691 GP_0_22_FN, FN_IP1_31_30, 4692 GP_0_21_FN, FN_IP1_29_28, 4693 GP_0_20_FN, FN_IP1_27, 4694 GP_0_19_FN, FN_IP1_26, 4695 GP_0_18_FN, FN_A2, 4696 GP_0_17_FN, FN_IP1_24, 4697 GP_0_16_FN, FN_IP1_23_22, 4698 GP_0_15_FN, FN_IP1_21_20, 4699 GP_0_14_FN, FN_IP1_19_18, 4700 GP_0_13_FN, FN_IP1_17_15, 4701 GP_0_12_FN, FN_IP1_14_13, 4702 GP_0_11_FN, FN_IP1_12_11, 4703 GP_0_10_FN, FN_IP1_10_8, 4704 GP_0_9_FN, FN_IP1_7_6, 4705 GP_0_8_FN, FN_IP1_5_4, 4706 GP_0_7_FN, FN_IP1_3_2, 4707 GP_0_6_FN, FN_IP1_1_0, 4708 GP_0_5_FN, FN_IP0_31_30, 4709 GP_0_4_FN, FN_IP0_29_28, 4710 GP_0_3_FN, FN_IP0_27_26, 4711 GP_0_2_FN, FN_IP0_25, 4712 GP_0_1_FN, FN_IP0_24, 4713 GP_0_0_FN, FN_IP0_23_22, )) 4714 }, 4715 { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1, GROUP( 4716 0, 0, 4717 0, 0, 4718 0, 0, 4719 0, 0, 4720 0, 0, 4721 0, 0, 4722 GP_1_25_FN, FN_DACK0, 4723 GP_1_24_FN, FN_IP7_31, 4724 GP_1_23_FN, FN_IP4_1_0, 4725 GP_1_22_FN, FN_WE1_N, 4726 GP_1_21_FN, FN_WE0_N, 4727 GP_1_20_FN, FN_IP3_31, 4728 GP_1_19_FN, FN_IP3_30, 4729 GP_1_18_FN, FN_IP3_29_27, 4730 GP_1_17_FN, FN_IP3_26_24, 4731 GP_1_16_FN, FN_IP3_23_21, 4732 GP_1_15_FN, FN_IP3_20_18, 4733 GP_1_14_FN, FN_IP3_17_15, 4734 GP_1_13_FN, FN_IP3_14_13, 4735 GP_1_12_FN, FN_IP3_12, 4736 GP_1_11_FN, FN_IP3_11, 4737 GP_1_10_FN, FN_IP3_10, 4738 GP_1_9_FN, FN_IP3_9_8, 4739 GP_1_8_FN, FN_IP3_7_6, 4740 GP_1_7_FN, FN_IP3_5_4, 4741 GP_1_6_FN, FN_IP3_3_2, 4742 GP_1_5_FN, FN_IP3_1_0, 4743 GP_1_4_FN, FN_IP2_31_30, 4744 GP_1_3_FN, FN_IP2_29_27, 4745 GP_1_2_FN, FN_IP2_26_24, 4746 GP_1_1_FN, FN_IP2_23_21, 4747 GP_1_0_FN, FN_IP2_20_18, )) 4748 }, 4749 { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1, GROUP( 4750 GP_2_31_FN, FN_IP6_7_6, 4751 GP_2_30_FN, FN_IP6_5_4, 4752 GP_2_29_FN, FN_IP6_3_2, 4753 GP_2_28_FN, FN_IP6_1_0, 4754 GP_2_27_FN, FN_IP5_31_30, 4755 GP_2_26_FN, FN_IP5_29_28, 4756 GP_2_25_FN, FN_IP5_27_26, 4757 GP_2_24_FN, FN_IP5_25_24, 4758 GP_2_23_FN, FN_IP5_23_22, 4759 GP_2_22_FN, FN_IP5_21_20, 4760 GP_2_21_FN, FN_IP5_19_18, 4761 GP_2_20_FN, FN_IP5_17_16, 4762 GP_2_19_FN, FN_IP5_15_14, 4763 GP_2_18_FN, FN_IP5_13_12, 4764 GP_2_17_FN, FN_IP5_11_9, 4765 GP_2_16_FN, FN_IP5_8_6, 4766 GP_2_15_FN, FN_IP5_5_4, 4767 GP_2_14_FN, FN_IP5_3_2, 4768 GP_2_13_FN, FN_IP5_1_0, 4769 GP_2_12_FN, FN_IP4_31_30, 4770 GP_2_11_FN, FN_IP4_29_28, 4771 GP_2_10_FN, FN_IP4_27_26, 4772 GP_2_9_FN, FN_IP4_25_23, 4773 GP_2_8_FN, FN_IP4_22_20, 4774 GP_2_7_FN, FN_IP4_19_18, 4775 GP_2_6_FN, FN_IP4_17_16, 4776 GP_2_5_FN, FN_IP4_15_14, 4777 GP_2_4_FN, FN_IP4_13_12, 4778 GP_2_3_FN, FN_IP4_11_10, 4779 GP_2_2_FN, FN_IP4_9_8, 4780 GP_2_1_FN, FN_IP4_7_5, 4781 GP_2_0_FN, FN_IP4_4_2 )) 4782 }, 4783 { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1, GROUP( 4784 GP_3_31_FN, FN_IP8_22_20, 4785 GP_3_30_FN, FN_IP8_19_17, 4786 GP_3_29_FN, FN_IP8_16_15, 4787 GP_3_28_FN, FN_IP8_14_12, 4788 GP_3_27_FN, FN_IP8_11_9, 4789 GP_3_26_FN, FN_IP8_8_6, 4790 GP_3_25_FN, FN_IP8_5_3, 4791 GP_3_24_FN, FN_IP8_2_0, 4792 GP_3_23_FN, FN_IP7_29_27, 4793 GP_3_22_FN, FN_IP7_26_24, 4794 GP_3_21_FN, FN_IP7_23_21, 4795 GP_3_20_FN, FN_IP7_20_18, 4796 GP_3_19_FN, FN_IP7_17_15, 4797 GP_3_18_FN, FN_IP7_14_12, 4798 GP_3_17_FN, FN_IP7_11_9, 4799 GP_3_16_FN, FN_IP7_8_6, 4800 GP_3_15_FN, FN_IP7_5_3, 4801 GP_3_14_FN, FN_IP7_2_0, 4802 GP_3_13_FN, FN_IP6_31_29, 4803 GP_3_12_FN, FN_IP6_28_26, 4804 GP_3_11_FN, FN_IP6_25_23, 4805 GP_3_10_FN, FN_IP6_22_20, 4806 GP_3_9_FN, FN_IP6_19_17, 4807 GP_3_8_FN, FN_IP6_16, 4808 GP_3_7_FN, FN_IP6_15, 4809 GP_3_6_FN, FN_IP6_14, 4810 GP_3_5_FN, FN_IP6_13, 4811 GP_3_4_FN, FN_IP6_12, 4812 GP_3_3_FN, FN_IP6_11, 4813 GP_3_2_FN, FN_IP6_10, 4814 GP_3_1_FN, FN_IP6_9, 4815 GP_3_0_FN, FN_IP6_8 )) 4816 }, 4817 { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1, GROUP( 4818 GP_4_31_FN, FN_IP11_17_16, 4819 GP_4_30_FN, FN_IP11_15_14, 4820 GP_4_29_FN, FN_IP11_13_11, 4821 GP_4_28_FN, FN_IP11_10_8, 4822 GP_4_27_FN, FN_IP11_7_6, 4823 GP_4_26_FN, FN_IP11_5_3, 4824 GP_4_25_FN, FN_IP11_2_0, 4825 GP_4_24_FN, FN_IP10_31_30, 4826 GP_4_23_FN, FN_IP10_29_27, 4827 GP_4_22_FN, FN_IP10_26_24, 4828 GP_4_21_FN, FN_IP10_23_21, 4829 GP_4_20_FN, FN_IP10_20_18, 4830 GP_4_19_FN, FN_IP10_17_15, 4831 GP_4_18_FN, FN_IP10_14_12, 4832 GP_4_17_FN, FN_IP10_11_9, 4833 GP_4_16_FN, FN_IP10_8_6, 4834 GP_4_15_FN, FN_IP10_5_3, 4835 GP_4_14_FN, FN_IP10_2_0, 4836 GP_4_13_FN, FN_IP9_30_28, 4837 GP_4_12_FN, FN_IP9_27_25, 4838 GP_4_11_FN, FN_IP9_24_22, 4839 GP_4_10_FN, FN_IP9_21_19, 4840 GP_4_9_FN, FN_IP9_18_17, 4841 GP_4_8_FN, FN_IP9_16_15, 4842 GP_4_7_FN, FN_IP9_14_12, 4843 GP_4_6_FN, FN_IP9_11_9, 4844 GP_4_5_FN, FN_IP9_8_6, 4845 GP_4_4_FN, FN_IP9_5_3, 4846 GP_4_3_FN, FN_IP9_2_0, 4847 GP_4_2_FN, FN_IP8_31_29, 4848 GP_4_1_FN, FN_IP8_28_26, 4849 GP_4_0_FN, FN_IP8_25_23 )) 4850 }, 4851 { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1, GROUP( 4852 0, 0, 4853 0, 0, 4854 0, 0, 4855 0, 0, 4856 GP_5_27_FN, FN_USB1_OVC, 4857 GP_5_26_FN, FN_USB1_PWEN, 4858 GP_5_25_FN, FN_USB0_OVC, 4859 GP_5_24_FN, FN_USB0_PWEN, 4860 GP_5_23_FN, FN_IP13_26_24, 4861 GP_5_22_FN, FN_IP13_23_21, 4862 GP_5_21_FN, FN_IP13_20_18, 4863 GP_5_20_FN, FN_IP13_17_15, 4864 GP_5_19_FN, FN_IP13_14_12, 4865 GP_5_18_FN, FN_IP13_11_9, 4866 GP_5_17_FN, FN_IP13_8_6, 4867 GP_5_16_FN, FN_IP13_5_3, 4868 GP_5_15_FN, FN_IP13_2_0, 4869 GP_5_14_FN, FN_IP12_29_27, 4870 GP_5_13_FN, FN_IP12_26_24, 4871 GP_5_12_FN, FN_IP12_23_21, 4872 GP_5_11_FN, FN_IP12_20_18, 4873 GP_5_10_FN, FN_IP12_17_15, 4874 GP_5_9_FN, FN_IP12_14_13, 4875 GP_5_8_FN, FN_IP12_12_11, 4876 GP_5_7_FN, FN_IP12_10_9, 4877 GP_5_6_FN, FN_IP12_8_6, 4878 GP_5_5_FN, FN_IP12_5_3, 4879 GP_5_4_FN, FN_IP12_2_0, 4880 GP_5_3_FN, FN_IP11_29_27, 4881 GP_5_2_FN, FN_IP11_26_24, 4882 GP_5_1_FN, FN_IP11_23_21, 4883 GP_5_0_FN, FN_IP11_20_18 )) 4884 }, 4885 { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1, GROUP( 4886 0, 0, 4887 0, 0, 4888 0, 0, 4889 0, 0, 4890 0, 0, 4891 0, 0, 4892 GP_6_25_FN, FN_IP0_21_20, 4893 GP_6_24_FN, FN_IP0_19_18, 4894 GP_6_23_FN, FN_IP0_17, 4895 GP_6_22_FN, FN_IP0_16, 4896 GP_6_21_FN, FN_IP0_15, 4897 GP_6_20_FN, FN_IP0_14, 4898 GP_6_19_FN, FN_IP0_13, 4899 GP_6_18_FN, FN_IP0_12, 4900 GP_6_17_FN, FN_IP0_11, 4901 GP_6_16_FN, FN_IP0_10, 4902 GP_6_15_FN, FN_IP0_9_8, 4903 GP_6_14_FN, FN_IP0_0, 4904 GP_6_13_FN, FN_SD1_DATA3, 4905 GP_6_12_FN, FN_SD1_DATA2, 4906 GP_6_11_FN, FN_SD1_DATA1, 4907 GP_6_10_FN, FN_SD1_DATA0, 4908 GP_6_9_FN, FN_SD1_CMD, 4909 GP_6_8_FN, FN_SD1_CLK, 4910 GP_6_7_FN, FN_SD0_WP, 4911 GP_6_6_FN, FN_SD0_CD, 4912 GP_6_5_FN, FN_SD0_DATA3, 4913 GP_6_4_FN, FN_SD0_DATA2, 4914 GP_6_3_FN, FN_SD0_DATA1, 4915 GP_6_2_FN, FN_SD0_DATA0, 4916 GP_6_1_FN, FN_SD0_CMD, 4917 GP_6_0_FN, FN_SD0_CLK )) 4918 }, 4919 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32, 4920 GROUP(2, 2, 2, 1, 1, 2, 2, 2, 1, 1, 1, 1, 4921 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1), 4922 GROUP( 4923 /* IP0_31_30 [2] */ 4924 FN_D5, FN_SCIF4_RXD_B, FN_I2C0_SCL_D, 0, 4925 /* IP0_29_28 [2] */ 4926 FN_D4, FN_I2C3_SDA_B, FN_SCIF5_TXD_B, 0, 4927 /* IP0_27_26 [2] */ 4928 FN_D3, FN_I2C3_SCL_B, FN_SCIF5_RXD_B, 0, 4929 /* IP0_25 [1] */ 4930 FN_D2, FN_SCIFA3_TXD_B, 4931 /* IP0_24 [1] */ 4932 FN_D1, FN_SCIFA3_RXD_B, 4933 /* IP0_23_22 [2] */ 4934 FN_D0, FN_SCIFA3_SCK_B, FN_IRQ4, 0, 4935 /* IP0_21_20 [2] */ 4936 FN_MMC_D7, FN_SCIF0_TXD, FN_I2C2_SDA_B, FN_CAN1_TX, 4937 /* IP0_19_18 [2] */ 4938 FN_MMC_D6, FN_SCIF0_RXD, FN_I2C2_SCL_B, FN_CAN1_RX, 4939 /* IP0_17 [1] */ 4940 FN_MMC_D5, FN_SD2_WP, 4941 /* IP0_16 [1] */ 4942 FN_MMC_D4, FN_SD2_CD, 4943 /* IP0_15 [1] */ 4944 FN_MMC_D3, FN_SD2_DATA3, 4945 /* IP0_14 [1] */ 4946 FN_MMC_D2, FN_SD2_DATA2, 4947 /* IP0_13 [1] */ 4948 FN_MMC_D1, FN_SD2_DATA1, 4949 /* IP0_12 [1] */ 4950 FN_MMC_D0, FN_SD2_DATA0, 4951 /* IP0_11 [1] */ 4952 FN_MMC_CMD, FN_SD2_CMD, 4953 /* IP0_10 [1] */ 4954 FN_MMC_CLK, FN_SD2_CLK, 4955 /* IP0_9_8 [2] */ 4956 FN_SD1_WP, FN_IRQ7, FN_CAN0_TX, 0, 4957 /* IP0_7 [1] */ 4958 0, 0, 4959 /* IP0_6 [1] */ 4960 0, 0, 4961 /* IP0_5 [1] */ 4962 0, 0, 4963 /* IP0_4 [1] */ 4964 0, 0, 4965 /* IP0_3 [1] */ 4966 0, 0, 4967 /* IP0_2 [1] */ 4968 0, 0, 4969 /* IP0_1 [1] */ 4970 0, 0, 4971 /* IP0_0 [1] */ 4972 FN_SD1_CD, FN_CAN0_RX, )) 4973 }, 4974 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32, 4975 GROUP(2, 2, 1, 1, 1, 1, 2, 2, 2, 3, 2, 2, 4976 3, 2, 2, 2, 2), 4977 GROUP( 4978 /* IP1_31_30 [2] */ 4979 FN_A6, FN_SCIFB0_CTS_N, FN_SCIFA4_RXD_B, FN_TPUTO2_C, 4980 /* IP1_29_28 [2] */ 4981 FN_A5, FN_SCIFB0_RXD, FN_PWM4_B, FN_TPUTO3_C, 4982 /* IP1_27 [1] */ 4983 FN_A4, FN_SCIFB0_TXD, 4984 /* IP1_26 [1] */ 4985 FN_A3, FN_SCIFB0_SCK, 4986 /* IP1_25 [1] */ 4987 0, 0, 4988 /* IP1_24 [1] */ 4989 FN_A1, FN_SCIFB1_TXD, 4990 /* IP1_23_22 [2] */ 4991 FN_A0, FN_SCIFB1_SCK, FN_PWM3_B, 0, 4992 /* IP1_21_20 [2] */ 4993 FN_D15, FN_SCIFA1_TXD, FN_I2C5_SDA_B, 0, 4994 /* IP1_19_18 [2] */ 4995 FN_D14, FN_SCIFA1_RXD, FN_I2C5_SCL_B, 0, 4996 /* IP1_17_15 [3] */ 4997 FN_D13, FN_SCIFA1_SCK, 0, FN_PWM2_C, FN_TCLK2_B, 4998 0, 0, 0, 4999 /* IP1_14_13 [2] */ 5000 FN_D12, FN_HSCIF2_HRTS_N, FN_SCIF1_TXD_C, FN_I2C1_SDA_D, 5001 /* IP1_12_11 [2] */ 5002 FN_D11, FN_HSCIF2_HCTS_N, FN_SCIF1_RXD_C, FN_I2C1_SCL_D, 5003 /* IP1_10_8 [3] */ 5004 FN_D10, FN_HSCIF2_HSCK, FN_SCIF1_SCK_C, FN_IRQ6, FN_PWM5_C, 5005 0, 0, 0, 5006 /* IP1_7_6 [2] */ 5007 FN_D9, FN_HSCIF2_HTX, FN_I2C1_SDA_B, 0, 5008 /* IP1_5_4 [2] */ 5009 FN_D8, FN_HSCIF2_HRX, FN_I2C1_SCL_B, 0, 5010 /* IP1_3_2 [2] */ 5011 FN_D7, FN_IRQ3, FN_TCLK1, FN_PWM6_B, 5012 /* IP1_1_0 [2] */ 5013 FN_D6, FN_SCIF4_TXD_B, FN_I2C0_SDA_D, 0, )) 5014 }, 5015 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32, 5016 GROUP(2, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2), 5017 GROUP( 5018 /* IP2_31_30 [2] */ 5019 FN_A20, FN_SPCLK, 0, 0, 5020 /* IP2_29_27 [3] */ 5021 FN_A19, FN_MSIOF2_SS2, FN_PWM4, FN_TPUTO2, 5022 0, 0, 0, 0, 5023 /* IP2_26_24 [3] */ 5024 FN_A18, FN_MSIOF2_SS1, FN_SCIF4_TXD_E, FN_CAN1_TX_B, 5025 0, 0, 0, 0, 5026 /* IP2_23_21 [3] */ 5027 FN_A17, FN_MSIOF2_SYNC, FN_SCIF4_RXD_E, FN_CAN1_RX_B, 5028 0, 0, 0, 0, 5029 /* IP2_20_18 [3] */ 5030 FN_A16, FN_MSIOF2_SCK, FN_HSCIF0_HSCK_B, FN_SPEEDIN, 5031 0, FN_CAN_CLK_C, FN_TPUTO2_B, 0, 5032 /* IP2_17_16 [2] */ 5033 FN_A15, FN_MSIOF2_TXD, FN_HSCIF0_HTX_B, FN_DACK1, 5034 /* IP2_15_14 [2] */ 5035 FN_A14, FN_MSIOF2_RXD, FN_HSCIF0_HRX_B, FN_DREQ1_N, 5036 /* IP2_13_12 [2] */ 5037 FN_A13, FN_MSIOF1_SS2, FN_SCIFA5_TXD_B, 0, 5038 /* IP2_11_10 [2] */ 5039 FN_A12, FN_MSIOF1_SS1, FN_SCIFA5_RXD_B, 0, 5040 /* IP2_9_8 [2] */ 5041 FN_A11, FN_MSIOF1_SYNC, FN_IIC0_SDA_B, 0, 5042 /* IP2_7_6 [2] */ 5043 FN_A10, FN_MSIOF1_SCK, FN_IIC0_SCL_B, 0, 5044 /* IP2_5_4 [2] */ 5045 FN_A9, FN_MSIOF1_TXD, FN_SCIFA0_TXD_B, 0, 5046 /* IP2_3_2 [2] */ 5047 FN_A8, FN_MSIOF1_RXD, FN_SCIFA0_RXD_B, 0, 5048 /* IP2_1_0 [2] */ 5049 FN_A7, FN_SCIFB0_RTS_N, FN_SCIFA4_TXD_B, 0, )) 5050 }, 5051 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32, 5052 GROUP(1, 1, 3, 3, 3, 3, 3, 2, 1, 1, 1, 2, 5053 2, 2, 2, 2), 5054 GROUP( 5055 /* IP3_31 [1] */ 5056 FN_RD_WR_N, FN_ATAG1_N, 5057 /* IP3_30 [1] */ 5058 FN_RD_N, FN_ATACS11_N, 5059 /* IP3_29_27 [3] */ 5060 FN_BS_N, FN_DRACK0, FN_PWM1_C, FN_TPUTO0_C, FN_ATACS01_N, 5061 0, 0, 0, 5062 /* IP3_26_24 [3] */ 5063 FN_EX_CS5_N, FN_SCIFA2_TXD, FN_I2C2_SDA_E, FN_TS_SPSYNC_B, 5064 0, FN_FMIN, FN_SCIFB2_RTS_N, 0, 5065 /* IP3_23_21 [3] */ 5066 FN_EX_CS4_N, FN_SCIFA2_RXD, FN_I2C2_SCL_E, FN_TS_SDEN_B, 5067 0, FN_FMCLK, FN_SCIFB2_CTS_N, 0, 5068 /* IP3_20_18 [3] */ 5069 FN_EX_CS3_N, FN_SCIFA2_SCK, FN_SCIF4_TXD_C, FN_TS_SCK_B, 5070 0, FN_BPFCLK, FN_SCIFB2_SCK, 0, 5071 /* IP3_17_15 [3] */ 5072 FN_EX_CS2_N, FN_PWM0, FN_SCIF4_RXD_C, FN_TS_SDATA_B, 5073 0, FN_TPUTO3, FN_SCIFB2_TXD, 0, 5074 /* IP3_14_13 [2] */ 5075 FN_EX_CS1_N, FN_TPUTO3_B, FN_SCIFB2_RXD, FN_VI1_DATA11, 5076 /* IP3_12 [1] */ 5077 FN_EX_CS0_N, FN_VI1_DATA10, 5078 /* IP3_11 [1] */ 5079 FN_CS1_N_A26, FN_VI1_DATA9, 5080 /* IP3_10 [1] */ 5081 FN_CS0_N, FN_VI1_DATA8, 5082 /* IP3_9_8 [2] */ 5083 FN_A25, FN_SSL, FN_ATARD1_N, 0, 5084 /* IP3_7_6 [2] */ 5085 FN_A24, FN_IO3, FN_EX_WAIT2, 0, 5086 /* IP3_5_4 [2] */ 5087 FN_A23, FN_IO2, 0, FN_ATAWR1_N, 5088 /* IP3_3_2 [2] */ 5089 FN_A22, FN_MISO_IO1, 0, FN_ATADIR1_N, 5090 /* IP3_1_0 [2] */ 5091 FN_A21, FN_MOSI_IO0, 0, 0, )) 5092 }, 5093 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32, 5094 GROUP(2, 2, 2, 3, 3, 2, 2, 2, 2, 2, 2, 3, 3, 2), 5095 GROUP( 5096 /* IP4_31_30 [2] */ 5097 FN_DU0_DG4, FN_LCDOUT12, 0, 0, 5098 /* IP4_29_28 [2] */ 5099 FN_DU0_DG3, FN_LCDOUT11, 0, 0, 5100 /* IP4_27_26 [2] */ 5101 FN_DU0_DG2, FN_LCDOUT10, 0, 0, 5102 /* IP4_25_23 [3] */ 5103 FN_DU0_DG1, FN_LCDOUT9, FN_SCIFA0_TXD_C, FN_I2C3_SDA_D, 5104 0, 0, 0, 0, 5105 /* IP4_22_20 [3] */ 5106 FN_DU0_DG0, FN_LCDOUT8, FN_SCIFA0_RXD_C, FN_I2C3_SCL_D, 5107 0, 0, 0, 0, 5108 /* IP4_19_18 [2] */ 5109 FN_DU0_DR7, FN_LCDOUT23, 0, 0, 5110 /* IP4_17_16 [2] */ 5111 FN_DU0_DR6, FN_LCDOUT22, 0, 0, 5112 /* IP4_15_14 [2] */ 5113 FN_DU0_DR5, FN_LCDOUT21, 0, 0, 5114 /* IP4_13_12 [2] */ 5115 FN_DU0_DR4, FN_LCDOUT20, 0, 0, 5116 /* IP4_11_10 [2] */ 5117 FN_DU0_DR3, FN_LCDOUT19, 0, 0, 5118 /* IP4_9_8 [2] */ 5119 FN_DU0_DR2, FN_LCDOUT18, 0, 0, 5120 /* IP4_7_5 [3] */ 5121 FN_DU0_DR1, FN_LCDOUT17, FN_SCIF5_TXD_C, FN_I2C2_SDA_D, 5122 0, 0, 0, 0, 5123 /* IP4_4_2 [3] */ 5124 FN_DU0_DR0, FN_LCDOUT16, FN_SCIF5_RXD_C, FN_I2C2_SCL_D, 5125 0, 0, 0, 0, 5126 /* IP4_1_0 [2] */ 5127 FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK, 0, )) 5128 }, 5129 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32, 5130 GROUP(2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 5131 2, 2, 2), 5132 GROUP( 5133 /* IP5_31_30 [2] */ 5134 FN_DU0_EXHSYNC_DU0_HSYNC, FN_QSTH_QHS, 0, 0, 5135 /* IP5_29_28 [2] */ 5136 FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE, 0, 0, 5137 /* IP5_27_26 [2] */ 5138 FN_DU0_DOTCLKOUT0, FN_QCLK, 0, 0, 5139 /* IP5_25_24 [2] */ 5140 FN_DU0_DOTCLKIN, FN_QSTVA_QVS, 0, 0, 5141 /* IP5_23_22 [2] */ 5142 FN_DU0_DB7, FN_LCDOUT7, 0, 0, 5143 /* IP5_21_20 [2] */ 5144 FN_DU0_DB6, FN_LCDOUT6, 0, 0, 5145 /* IP5_19_18 [2] */ 5146 FN_DU0_DB5, FN_LCDOUT5, 0, 0, 5147 /* IP5_17_16 [2] */ 5148 FN_DU0_DB4, FN_LCDOUT4, 0, 0, 5149 /* IP5_15_14 [2] */ 5150 FN_DU0_DB3, FN_LCDOUT3, 0, 0, 5151 /* IP5_13_12 [2] */ 5152 FN_DU0_DB2, FN_LCDOUT2, 0, 0, 5153 /* IP5_11_9 [3] */ 5154 FN_DU0_DB1, FN_LCDOUT1, FN_SCIFA4_TXD_C, FN_I2C4_SDA_D, 5155 FN_CAN0_TX_C, 0, 0, 0, 5156 /* IP5_8_6 [3] */ 5157 FN_DU0_DB0, FN_LCDOUT0, FN_SCIFA4_RXD_C, FN_I2C4_SCL_D, 5158 FN_CAN0_RX_C, 0, 0, 0, 5159 /* IP5_5_4 [2] */ 5160 FN_DU0_DG7, FN_LCDOUT15, 0, 0, 5161 /* IP5_3_2 [2] */ 5162 FN_DU0_DG6, FN_LCDOUT14, 0, 0, 5163 /* IP5_1_0 [2] */ 5164 FN_DU0_DG5, FN_LCDOUT13, 0, 0, )) 5165 }, 5166 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32, 5167 GROUP(3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 5168 1, 1, 2, 2, 2, 2), 5169 GROUP( 5170 /* IP6_31_29 [3] */ 5171 FN_ETH_MDIO, FN_VI0_G0, FN_MSIOF2_RXD_B, FN_I2C5_SCL_D, 5172 FN_AVB_TX_CLK, FN_ADIDATA, 0, 0, 5173 /* IP6_28_26 [3] */ 5174 FN_VI0_VSYNC_N, FN_SCIF0_TXD_B, FN_I2C0_SDA_C, 5175 FN_AUDIO_CLKOUT_B, FN_AVB_TX_EN, 0, 0, 0, 5176 /* IP6_25_23 [3] */ 5177 FN_VI0_HSYNC_N, FN_SCIF0_RXD_B, FN_I2C0_SCL_C, FN_IERX_C, 5178 FN_AVB_COL, 0, 0, 0, 5179 /* IP6_22_20 [3] */ 5180 FN_VI0_FIELD, FN_I2C3_SDA, FN_SCIFA5_TXD_C, FN_IECLK_C, 5181 FN_AVB_RX_ER, 0, 0, 0, 5182 /* IP6_19_17 [3] */ 5183 FN_VI0_CLKENB, FN_I2C3_SCL, FN_SCIFA5_RXD_C, FN_IETX_C, 5184 FN_AVB_RXD7, 0, 0, 0, 5185 /* IP6_16 [1] */ 5186 FN_VI0_DATA7_VI0_B7, FN_AVB_RXD6, 5187 /* IP6_15 [1] */ 5188 FN_VI0_DATA6_VI0_B6, FN_AVB_RXD5, 5189 /* IP6_14 [1] */ 5190 FN_VI0_DATA5_VI0_B5, FN_AVB_RXD4, 5191 /* IP6_13 [1] */ 5192 FN_VI0_DATA4_VI0_B4, FN_AVB_RXD3, 5193 /* IP6_12 [1] */ 5194 FN_VI0_DATA3_VI0_B3, FN_AVB_RXD2, 5195 /* IP6_11 [1] */ 5196 FN_VI0_DATA2_VI0_B2, FN_AVB_RXD1, 5197 /* IP6_10 [1] */ 5198 FN_VI0_DATA1_VI0_B1, FN_AVB_RXD0, 5199 /* IP6_9 [1] */ 5200 FN_VI0_DATA0_VI0_B0, FN_AVB_RX_DV, 5201 /* IP6_8 [1] */ 5202 FN_VI0_CLK, FN_AVB_RX_CLK, 5203 /* IP6_7_6 [2] */ 5204 FN_DU0_CDE, FN_QPOLB, 0, 0, 5205 /* IP6_5_4 [2] */ 5206 FN_DU0_DISP, FN_QPOLA, 0, 0, 5207 /* IP6_3_2 [2] */ 5208 FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, 0, 5209 0, 5210 /* IP6_1_0 [2] */ 5211 FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, 0, 0, )) 5212 }, 5213 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32, 5214 GROUP(1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3), 5215 GROUP( 5216 /* IP7_31 [1] */ 5217 FN_DREQ0_N, FN_SCIFB1_RXD, 5218 /* IP7_30 [1] */ 5219 0, 0, 5220 /* IP7_29_27 [3] */ 5221 FN_ETH_TXD0, FN_VI0_R2, FN_SCIF3_RXD_B, FN_I2C4_SCL_E, 5222 FN_AVB_GTX_CLK, FN_SSI_WS6_B, 0, 0, 5223 /* IP7_26_24 [3] */ 5224 FN_ETH_MAGIC, FN_VI0_R1, FN_SCIF3_SCK_B, FN_AVB_TX_ER, 5225 FN_SSI_SCK6_B, 0, 0, 0, 5226 /* IP7_23_21 [3] */ 5227 FN_ETH_TX_EN, FN_VI0_R0, FN_SCIF2_TXD_C, FN_IIC0_SDA_D, 5228 FN_AVB_TXD7, FN_SSI_SDATA5_B, 0, 0, 5229 /* IP7_20_18 [3] */ 5230 FN_ETH_TXD1, FN_VI0_G7, FN_SCIF2_RXD_C, FN_IIC0_SCL_D, 5231 FN_AVB_TXD6, FN_SSI_WS5_B, 0, 0, 5232 /* IP7_17_15 [3] */ 5233 FN_ETH_REFCLK, FN_VI0_G6, FN_SCIF2_SCK_C, FN_AVB_TXD5, 5234 FN_SSI_SCK5_B, 0, 0, 0, 5235 /* IP7_14_12 [3] */ 5236 FN_ETH_LINK, FN_VI0_G5, FN_MSIOF2_SS2_B, FN_SCIF4_TXD_D, 5237 FN_AVB_TXD4, FN_ADICHS2, 0, 0, 5238 /* IP7_11_9 [3] */ 5239 FN_ETH_RXD1, FN_VI0_G4, FN_MSIOF2_SS1_B, FN_SCIF4_RXD_D, 5240 FN_AVB_TXD3, FN_ADICHS1, 0, 0, 5241 /* IP7_8_6 [3] */ 5242 FN_ETH_RXD0, FN_VI0_G3, FN_MSIOF2_SYNC_B, FN_CAN0_TX_B, 5243 FN_AVB_TXD2, FN_ADICHS0, 0, 0, 5244 /* IP7_5_3 [3] */ 5245 FN_ETH_RX_ER, FN_VI0_G2, FN_MSIOF2_SCK_B, FN_CAN0_RX_B, 5246 FN_AVB_TXD1, FN_ADICLK, 0, 0, 5247 /* IP7_2_0 [3] */ 5248 FN_ETH_CRS_DV, FN_VI0_G1, FN_MSIOF2_TXD_B, FN_I2C5_SDA_D, 5249 FN_AVB_TXD0, FN_ADICS_SAMP, 0, 0, )) 5250 }, 5251 { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32, 5252 GROUP(3, 3, 3, 3, 3, 2, 3, 3, 3, 3, 3), 5253 GROUP( 5254 /* IP8_31_29 [3] */ 5255 FN_MSIOF0_RXD, FN_SCIF5_RXD, FN_I2C2_SCL_C, FN_DU1_DR2, 5256 0, FN_TS_SDEN_D, FN_FMCLK_C, 0, 5257 /* IP8_28_26 [3] */ 5258 FN_I2C1_SDA, FN_SCIF4_TXD, FN_IRQ5, FN_DU1_DR1, 5259 0, FN_TS_SCK_D, FN_BPFCLK_C, 0, 5260 /* IP8_25_23 [3] */ 5261 FN_I2C1_SCL, FN_SCIF4_RXD, FN_PWM5_B, FN_DU1_DR0, 5262 0, FN_TS_SDATA_D, FN_TPUTO1_B, 0, 5263 /* IP8_22_20 [3] */ 5264 FN_I2C0_SDA, FN_SCIF0_TXD_C, FN_TPUTO0, FN_CAN_CLK, 5265 FN_DVC_MUTE, FN_CAN1_TX_D, 0, 0, 5266 /* IP8_19_17 [3] */ 5267 FN_I2C0_SCL, FN_SCIF0_RXD_C, FN_PWM5, FN_TCLK1_B, 5268 FN_AVB_GTXREFCLK, FN_CAN1_RX_D, FN_TPUTO0_B, 0, 5269 /* IP8_16_15 [2] */ 5270 FN_HSCIF0_HSCK, FN_SCIF_CLK_B, FN_AVB_CRS, FN_AUDIO_CLKC_B, 5271 /* IP8_14_12 [3] */ 5272 FN_HSCIF0_HRTS_N, FN_VI0_R7, FN_SCIF0_TXD_D, FN_I2C0_SDA_E, 5273 FN_AVB_PHY_INT, FN_SSI_SDATA8_B, 0, 0, 5274 /* IP8_11_9 [3] */ 5275 FN_HSCIF0_HCTS_N, FN_VI0_R6, FN_SCIF0_RXD_D, FN_I2C0_SCL_E, 5276 FN_AVB_MAGIC, FN_SSI_SDATA7_B, 0, 0, 5277 /* IP8_8_6 [3] */ 5278 FN_HSCIF0_HTX, FN_VI0_R5, FN_I2C1_SDA_C, FN_AUDIO_CLKB_B, 5279 FN_AVB_LINK, FN_SSI_WS78_B, 0, 0, 5280 /* IP8_5_3 [3] */ 5281 FN_HSCIF0_HRX, FN_VI0_R4, FN_I2C1_SCL_C, FN_AUDIO_CLKA_B, 5282 FN_AVB_MDIO, FN_SSI_SCK78_B, 0, 0, 5283 /* IP8_2_0 [3] */ 5284 FN_ETH_MDC, FN_VI0_R3, FN_SCIF3_TXD_B, FN_I2C4_SDA_E, 5285 FN_AVB_MDC, FN_SSI_SDATA6_B, 0, 0, )) 5286 }, 5287 { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32, 5288 GROUP(1, 3, 3, 3, 3, 2, 2, 3, 3, 3, 3, 3), 5289 GROUP( 5290 /* IP9_31 [1] */ 5291 0, 0, 5292 /* IP9_30_28 [3] */ 5293 FN_SCIF1_SCK, FN_PWM3, FN_TCLK2, FN_DU1_DG5, 5294 FN_SSI_SDATA1_B, 0, 0, 0, 5295 /* IP9_27_25 [3] */ 5296 FN_HSCIF1_HRTS_N, FN_SCIFA4_TXD, FN_IERX, FN_DU1_DG4, 5297 FN_SSI_WS1_B, 0, 0, 0, 5298 /* IP9_24_22 [3] */ 5299 FN_HSCIF1_HCTS_N, FN_SCIFA4_RXD, FN_IECLK, FN_DU1_DG3, 5300 FN_SSI_SCK1_B, 0, 0, 0, 5301 /* IP9_21_19 [3] */ 5302 FN_HSCIF1_HSCK, FN_PWM2, FN_IETX, FN_DU1_DG2, 5303 FN_REMOCON_B, FN_SPEEDIN_B, 0, 0, 5304 /* IP9_18_17 [2] */ 5305 FN_HSCIF1_HTX, FN_I2C4_SDA, FN_TPUTO1, FN_DU1_DG1, 5306 /* IP9_16_15 [2] */ 5307 FN_HSCIF1_HRX, FN_I2C4_SCL, FN_PWM6, FN_DU1_DG0, 5308 /* IP9_14_12 [3] */ 5309 FN_MSIOF0_SS2, FN_SCIFA0_TXD, FN_TS_SPSYNC, FN_DU1_DR7, 5310 0, FN_FMIN_B, 0, 0, 5311 /* IP9_11_9 [3] */ 5312 FN_MSIOF0_SS1, FN_SCIFA0_RXD, FN_TS_SDEN, FN_DU1_DR6, 5313 0, FN_FMCLK_B, 0, 0, 5314 /* IP9_8_6 [3] */ 5315 FN_MSIOF0_SYNC, FN_PWM1, FN_TS_SCK, FN_DU1_DR5, 5316 0, FN_BPFCLK_B, 0, 0, 5317 /* IP9_5_3 [3] */ 5318 FN_MSIOF0_SCK, FN_IRQ0, FN_TS_SDATA, FN_DU1_DR4, 5319 0, FN_TPUTO1_C, 0, 0, 5320 /* IP9_2_0 [3] */ 5321 FN_MSIOF0_TXD, FN_SCIF5_TXD, FN_I2C2_SDA_C, FN_DU1_DR3, 5322 0, FN_TS_SPSYNC_D, FN_FMIN_C, 0, )) 5323 }, 5324 { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32, 5325 GROUP(2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3), 5326 GROUP( 5327 /* IP10_31_30 [2] */ 5328 FN_SSI_SCK5, FN_SCIFA3_SCK, FN_DU1_DOTCLKIN, 0, 5329 /* IP10_29_27 [3] */ 5330 FN_I2C2_SDA, FN_SCIFA5_TXD, FN_DU1_DB7, FN_AUDIO_CLKOUT_C, 5331 0, 0, 0, 0, 5332 /* IP10_26_24 [3] */ 5333 FN_I2C2_SCL, FN_SCIFA5_RXD, FN_DU1_DB6, FN_AUDIO_CLKC_C, 5334 FN_SSI_SDATA4_B, 0, 0, 0, 5335 /* IP10_23_21 [3] */ 5336 FN_SCIF3_TXD, FN_I2C1_SDA_E, FN_FMIN_D, FN_DU1_DB5, 5337 FN_AUDIO_CLKB_C, FN_SSI_WS4_B, 0, 0, 5338 /* IP10_20_18 [3] */ 5339 FN_SCIF3_RXD, FN_I2C1_SCL_E, FN_FMCLK_D, FN_DU1_DB4, 5340 FN_AUDIO_CLKA_C, FN_SSI_SCK4_B, 0, 0, 5341 /* IP10_17_15 [3] */ 5342 FN_SCIF3_SCK, FN_IRQ2, FN_BPFCLK_D, FN_DU1_DB3, 5343 FN_SSI_SDATA9_B, 0, 0, 0, 5344 /* IP10_14_12 [3] */ 5345 FN_SCIF2_SCK, FN_IRQ1, FN_DU1_DB2, FN_SSI_WS9_B, 5346 0, 0, 0, 0, 5347 /* IP10_11_9 [3] */ 5348 FN_SCIF2_TXD, FN_IIC0_SDA, FN_DU1_DB1, FN_SSI_SCK9_B, 5349 0, 0, 0, 0, 5350 /* IP10_8_6 [3] */ 5351 FN_SCIF2_RXD, FN_IIC0_SCL, FN_DU1_DB0, FN_SSI_SDATA2_B, 5352 0, 0, 0, 0, 5353 /* IP10_5_3 [3] */ 5354 FN_SCIF1_TXD, FN_I2C5_SDA, FN_DU1_DG7, FN_SSI_WS2_B, 5355 0, 0, 0, 0, 5356 /* IP10_2_0 [3] */ 5357 FN_SCIF1_RXD, FN_I2C5_SCL, FN_DU1_DG6, FN_SSI_SCK2_B, 5358 0, 0, 0, 0, )) 5359 }, 5360 { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32, 5361 GROUP(2, 3, 3, 3, 3, 2, 2, 3, 3, 2, 3, 3), 5362 GROUP( 5363 /* IP11_31_30 [2] */ 5364 0, 0, 0, 0, 5365 /* IP11_29_27 [3] */ 5366 FN_SSI_SDATA0, FN_MSIOF1_SCK_B, FN_PWM0_B, FN_ADICLK_B, 5367 0, 0, 0, 0, 5368 /* IP11_26_24 [3] */ 5369 FN_SSI_WS0129, FN_MSIOF1_TXD_B, FN_SCIF5_TXD_D, FN_ADICS_SAMP_B, 5370 0, 0, 0, 0, 5371 /* IP11_23_21 [3] */ 5372 FN_SSI_SCK0129, FN_MSIOF1_RXD_B, FN_SCIF5_RXD_D, FN_ADIDATA_B, 5373 0, 0, 0, 0, 5374 /* IP11_20_18 [3] */ 5375 FN_SSI_SDATA7, FN_SCIFA2_TXD_B, FN_IRQ8, FN_AUDIO_CLKA_D, 5376 FN_CAN_CLK_D, 0, 0, 0, 5377 /* IP11_17_16 [2] */ 5378 FN_SSI_WS78, FN_SCIFA2_RXD_B, FN_I2C5_SCL_C, FN_DU1_CDE, 5379 /* IP11_15_14 [2] */ 5380 FN_SSI_SCK78, FN_SCIFA2_SCK_B, FN_I2C5_SDA_C, FN_DU1_DISP, 5381 /* IP11_13_11 [3] */ 5382 FN_SSI_SDATA6, FN_SCIFA1_TXD_B, FN_I2C4_SDA_C, 5383 FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, 0, 0, 0, 0, 5384 /* IP11_10_8 [3] */ 5385 FN_SSI_WS6, FN_SCIFA1_RXD_B, FN_I2C4_SCL_C, 5386 FN_DU1_EXVSYNC_DU1_VSYNC, 0, 0, 0, 0, 5387 /* IP11_7_6 [2] */ 5388 FN_SSI_SCK6, FN_SCIFA1_SCK_B, FN_DU1_EXHSYNC_DU1_HSYNC, 0, 5389 /* IP11_5_3 [3] */ 5390 FN_SSI_SDATA5, FN_SCIFA3_TXD, FN_I2C3_SDA_C, FN_DU1_DOTCLKOUT1, 5391 0, 0, 0, 0, 5392 /* IP11_2_0 [3] */ 5393 FN_SSI_WS5, FN_SCIFA3_RXD, FN_I2C3_SCL_C, FN_DU1_DOTCLKOUT0, 5394 0, 0, 0, 0, )) 5395 }, 5396 { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32, 5397 GROUP(2, 3, 3, 3, 3, 3, 2, 2, 2, 3, 3, 3), 5398 GROUP( 5399 /* IP12_31_30 [2] */ 5400 0, 0, 0, 0, 5401 /* IP12_29_27 [3] */ 5402 FN_SSI_SCK2, FN_HSCIF1_HTX_B, FN_VI1_DATA2, 0, 5403 FN_ATAG0_N, FN_ETH_RXD1_B, 0, 0, 5404 /* IP12_26_24 [3] */ 5405 FN_SSI_SDATA1, FN_HSCIF1_HRX_B, FN_VI1_DATA1, 0, 5406 FN_ATAWR0_N, FN_ETH_RXD0_B, 0, 0, 5407 /* IP12_23_21 [3] */ 5408 FN_SSI_WS1, FN_SCIF1_TXD_B, FN_IIC0_SDA_C, FN_VI1_DATA0, 5409 FN_CAN0_TX_D, 0, FN_ETH_RX_ER_B, 0, 5410 /* IP12_20_18 [3] */ 5411 FN_SSI_SCK1, FN_SCIF1_RXD_B, FN_IIC0_SCL_C, FN_VI1_CLK, 5412 FN_CAN0_RX_D, 0, FN_ETH_CRS_DV_B, 0, 5413 /* IP12_17_15 [3] */ 5414 FN_SSI_SDATA8, FN_SCIF1_SCK_B, FN_PWM1_B, FN_IRQ9, 5415 FN_REMOCON, FN_DACK2, FN_ETH_MDIO_B, 0, 5416 /* IP12_14_13 [2] */ 5417 FN_SSI_SDATA4, FN_MLB_DAT, FN_IERX_B, 0, 5418 /* IP12_12_11 [2] */ 5419 FN_SSI_WS4, FN_MLB_SIG, FN_IECLK_B, 0, 5420 /* IP12_10_9 [2] */ 5421 FN_SSI_SCK4, FN_MLB_CLK, FN_IETX_B, 0, 5422 /* IP12_8_6 [3] */ 5423 FN_SSI_SDATA3, FN_MSIOF1_SS2_B, FN_SCIFA1_TXD_C, FN_ADICHS2_B, 5424 FN_CAN1_TX_C, FN_DREQ2_N, 0, 0, 5425 /* IP12_5_3 [3] */ 5426 FN_SSI_WS34, FN_MSIOF1_SS1_B, FN_SCIFA1_RXD_C, FN_ADICHS1_B, 5427 FN_CAN1_RX_C, FN_DACK1_B, 0, 0, 5428 /* IP12_2_0 [3] */ 5429 FN_SSI_SCK34, FN_MSIOF1_SYNC_B, FN_SCIFA1_SCK_C, FN_ADICHS0_B, 5430 0, FN_DREQ1_N_B, 0, 0, )) 5431 }, 5432 { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32, 5433 GROUP(1, 1, 1, 1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3), 5434 GROUP( 5435 /* IP13_31 [1] */ 5436 0, 0, 5437 /* IP13_30 [1] */ 5438 0, 0, 5439 /* IP13_29 [1] */ 5440 0, 0, 5441 /* IP13_28 [1] */ 5442 0, 0, 5443 /* IP13_27 [1] */ 5444 0, 0, 5445 /* IP13_26_24 [3] */ 5446 FN_AUDIO_CLKOUT, FN_I2C4_SDA_B, FN_SCIFA5_TXD_D, FN_VI1_VSYNC_N, 5447 FN_TS_SPSYNC_C, 0, FN_FMIN_E, 0, 5448 /* IP13_23_21 [3] */ 5449 FN_AUDIO_CLKC, FN_I2C4_SCL_B, FN_SCIFA5_RXD_D, FN_VI1_HSYNC_N, 5450 FN_TS_SDEN_C, 0, FN_FMCLK_E, 0, 5451 /* IP13_20_18 [3] */ 5452 FN_AUDIO_CLKB, FN_I2C0_SDA_B, FN_SCIFA4_TXD_D, FN_VI1_FIELD, 5453 FN_TS_SCK_C, 0, FN_BPFCLK_E, FN_ETH_MDC_B, 5454 /* IP13_17_15 [3] */ 5455 FN_AUDIO_CLKA, FN_I2C0_SCL_B, FN_SCIFA4_RXD_D, FN_VI1_CLKENB, 5456 FN_TS_SDATA_C, 0, FN_ETH_TXD0_B, 0, 5457 /* IP13_14_12 [3] */ 5458 FN_SSI_SDATA9, FN_SCIF2_TXD_B, FN_I2C3_SDA_E, FN_VI1_DATA7, 5459 FN_ATADIR0_N, FN_ETH_MAGIC_B, 0, 0, 5460 /* IP13_11_9 [3] */ 5461 FN_SSI_WS9, FN_SCIF2_RXD_B, FN_I2C3_SCL_E, FN_VI1_DATA6, 5462 FN_ATARD0_N, FN_ETH_TX_EN_B, 0, 0, 5463 /* IP13_8_6 [3] */ 5464 FN_SSI_SCK9, FN_SCIF2_SCK_B, FN_PWM2_B, FN_VI1_DATA5, 5465 0, FN_EX_WAIT1, FN_ETH_TXD1_B, 0, 5466 /* IP13_5_3 [2] */ 5467 FN_SSI_SDATA2, FN_HSCIF1_HRTS_N_B, FN_SCIFA0_TXD_D, 5468 FN_VI1_DATA4, 0, FN_ATACS10_N, FN_ETH_REFCLK_B, 0, 5469 /* IP13_2_0 [3] */ 5470 FN_SSI_WS2, FN_HSCIF1_HCTS_N_B, FN_SCIFA0_RXD_D, FN_VI1_DATA3, 5471 0, FN_ATACS00_N, FN_ETH_LINK_B, 0, )) 5472 }, 5473 { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32, 5474 GROUP(2, 1, 2, 3, 4, 1, 1, 3, 3, 3, 3, 3, 2, 1), 5475 GROUP( 5476 /* SEL_ADG [2] */ 5477 FN_SEL_ADG_0, FN_SEL_ADG_1, FN_SEL_ADG_2, FN_SEL_ADG_3, 5478 /* RESERVED [1] */ 5479 0, 0, 5480 /* SEL_CAN [2] */ 5481 FN_SEL_CAN_0, FN_SEL_CAN_1, FN_SEL_CAN_2, FN_SEL_CAN_3, 5482 /* SEL_DARC [3] */ 5483 FN_SEL_DARC_0, FN_SEL_DARC_1, FN_SEL_DARC_2, FN_SEL_DARC_3, 5484 FN_SEL_DARC_4, 0, 0, 0, 5485 /* RESERVED [4] */ 5486 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5487 /* SEL_ETH [1] */ 5488 FN_SEL_ETH_0, FN_SEL_ETH_1, 5489 /* RESERVED [1] */ 5490 0, 0, 5491 /* SEL_IC200 [3] */ 5492 FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2, FN_SEL_I2C00_3, 5493 FN_SEL_I2C00_4, 0, 0, 0, 5494 /* SEL_I2C01 [3] */ 5495 FN_SEL_I2C01_0, FN_SEL_I2C01_1, FN_SEL_I2C01_2, FN_SEL_I2C01_3, 5496 FN_SEL_I2C01_4, 0, 0, 0, 5497 /* SEL_I2C02 [3] */ 5498 FN_SEL_I2C02_0, FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3, 5499 FN_SEL_I2C02_4, 0, 0, 0, 5500 /* SEL_I2C03 [3] */ 5501 FN_SEL_I2C03_0, FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3, 5502 FN_SEL_I2C03_4, 0, 0, 0, 5503 /* SEL_I2C04 [3] */ 5504 FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2, FN_SEL_I2C04_3, 5505 FN_SEL_I2C04_4, 0, 0, 0, 5506 /* SEL_I2C05 [2] */ 5507 FN_SEL_I2C05_0, FN_SEL_I2C05_1, FN_SEL_I2C05_2, FN_SEL_I2C05_3, 5508 /* RESERVED [1] */ 5509 0, 0, )) 5510 }, 5511 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32, 5512 GROUP(2, 2, 1, 1, 1, 1, 1, 1, 2, 2, 1, 1, 5513 2, 2, 1, 1, 2, 2, 2, 1, 1, 2), 5514 GROUP( 5515 /* SEL_IEB [2] */ 5516 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0, 5517 /* SEL_IIC0 [2] */ 5518 FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, FN_SEL_IIC0_3, 5519 /* SEL_LBS [1] */ 5520 FN_SEL_LBS_0, FN_SEL_LBS_1, 5521 /* SEL_MSI1 [1] */ 5522 FN_SEL_MSI1_0, FN_SEL_MSI1_1, 5523 /* SEL_MSI2 [1] */ 5524 FN_SEL_MSI2_0, FN_SEL_MSI2_1, 5525 /* SEL_RAD [1] */ 5526 FN_SEL_RAD_0, FN_SEL_RAD_1, 5527 /* SEL_RCN [1] */ 5528 FN_SEL_RCN_0, FN_SEL_RCN_1, 5529 /* SEL_RSP [1] */ 5530 FN_SEL_RSP_0, FN_SEL_RSP_1, 5531 /* SEL_SCIFA0 [2] */ 5532 FN_SEL_SCIFA0_0, FN_SEL_SCIFA0_1, FN_SEL_SCIFA0_2, 5533 FN_SEL_SCIFA0_3, 5534 /* SEL_SCIFA1 [2] */ 5535 FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, 0, 5536 /* SEL_SCIFA2 [1] */ 5537 FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, 5538 /* SEL_SCIFA3 [1] */ 5539 FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, 5540 /* SEL_SCIFA4 [2] */ 5541 FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2, 5542 FN_SEL_SCIFA4_3, 5543 /* SEL_SCIFA5 [2] */ 5544 FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, 5545 FN_SEL_SCIFA5_3, 5546 /* RESERVED [1] */ 5547 0, 0, 5548 /* SEL_TMU [1] */ 5549 FN_SEL_TMU_0, FN_SEL_TMU_1, 5550 /* SEL_TSIF0 [2] */ 5551 FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, 5552 /* SEL_CAN0 [2] */ 5553 FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3, 5554 /* SEL_CAN1 [2] */ 5555 FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3, 5556 /* SEL_HSCIF0 [1] */ 5557 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, 5558 /* SEL_HSCIF1 [1] */ 5559 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, 5560 /* RESERVED [2] */ 5561 0, 0, 0, 0, )) 5562 }, 5563 { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32, 5564 GROUP(2, 2, 2, 1, 3, 2, 1, 1, 1, 1, 1, 1, 5565 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), 5566 GROUP( 5567 /* SEL_SCIF0 [2] */ 5568 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3, 5569 /* SEL_SCIF1 [2] */ 5570 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, 0, 5571 /* SEL_SCIF2 [2] */ 5572 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, 0, 5573 /* SEL_SCIF3 [1] */ 5574 FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, 5575 /* SEL_SCIF4 [3] */ 5576 FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3, 5577 FN_SEL_SCIF4_4, 0, 0, 0, 5578 /* SEL_SCIF5 [2] */ 5579 FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3, 5580 /* SEL_SSI1 [1] */ 5581 FN_SEL_SSI1_0, FN_SEL_SSI1_1, 5582 /* SEL_SSI2 [1] */ 5583 FN_SEL_SSI2_0, FN_SEL_SSI2_1, 5584 /* SEL_SSI4 [1] */ 5585 FN_SEL_SSI4_0, FN_SEL_SSI4_1, 5586 /* SEL_SSI5 [1] */ 5587 FN_SEL_SSI5_0, FN_SEL_SSI5_1, 5588 /* SEL_SSI6 [1] */ 5589 FN_SEL_SSI6_0, FN_SEL_SSI6_1, 5590 /* SEL_SSI7 [1] */ 5591 FN_SEL_SSI7_0, FN_SEL_SSI7_1, 5592 /* SEL_SSI8 [1] */ 5593 FN_SEL_SSI8_0, FN_SEL_SSI8_1, 5594 /* SEL_SSI9 [1] */ 5595 FN_SEL_SSI9_0, FN_SEL_SSI9_1, 5596 /* RESERVED [1] */ 5597 0, 0, 5598 /* RESERVED [1] */ 5599 0, 0, 5600 /* RESERVED [1] */ 5601 0, 0, 5602 /* RESERVED [1] */ 5603 0, 0, 5604 /* RESERVED [1] */ 5605 0, 0, 5606 /* RESERVED [1] */ 5607 0, 0, 5608 /* RESERVED [1] */ 5609 0, 0, 5610 /* RESERVED [1] */ 5611 0, 0, 5612 /* RESERVED [1] */ 5613 0, 0, 5614 /* RESERVED [1] */ 5615 0, 0, 5616 /* RESERVED [1] */ 5617 0, 0, 5618 /* RESERVED [1] */ 5619 0, 0, )) 5620 }, 5621 { }, 5622 }; 5623 5624 static int r8a7794_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl) 5625 { 5626 if (pin < RCAR_GP_PIN(6, 0) || pin > RCAR_GP_PIN(6, 23)) 5627 return -EINVAL; 5628 5629 *pocctrl = 0xe606006c; 5630 5631 switch (pin & 0x1f) { 5632 case 6: return 23; 5633 case 7: return 16; 5634 case 14: return 15; 5635 case 15: return 8; 5636 case 0 ... 5: 5637 case 8 ... 13: 5638 return 22 - (pin & 0x1f); 5639 case 16 ... 23: 5640 return 47 - (pin & 0x1f); 5641 } 5642 5643 return -EINVAL; 5644 } 5645 5646 static const struct pinmux_bias_reg pinmux_bias_regs[] = { 5647 { PINMUX_BIAS_REG("PUPR0", 0xe6060100, "N/A", 0) { 5648 [ 0] = RCAR_GP_PIN(0, 0), /* D0 */ 5649 [ 1] = RCAR_GP_PIN(0, 1), /* D1 */ 5650 [ 2] = RCAR_GP_PIN(0, 2), /* D2 */ 5651 [ 3] = RCAR_GP_PIN(0, 3), /* D3 */ 5652 [ 4] = RCAR_GP_PIN(0, 4), /* D4 */ 5653 [ 5] = RCAR_GP_PIN(0, 5), /* D5 */ 5654 [ 6] = RCAR_GP_PIN(0, 6), /* D6 */ 5655 [ 7] = RCAR_GP_PIN(0, 7), /* D7 */ 5656 [ 8] = RCAR_GP_PIN(0, 8), /* D8 */ 5657 [ 9] = RCAR_GP_PIN(0, 9), /* D9 */ 5658 [10] = RCAR_GP_PIN(0, 10), /* D10 */ 5659 [11] = RCAR_GP_PIN(0, 11), /* D11 */ 5660 [12] = RCAR_GP_PIN(0, 12), /* D12 */ 5661 [13] = RCAR_GP_PIN(0, 13), /* D13 */ 5662 [14] = RCAR_GP_PIN(0, 14), /* D14 */ 5663 [15] = RCAR_GP_PIN(0, 15), /* D15 */ 5664 [16] = RCAR_GP_PIN(0, 16), /* A0 */ 5665 [17] = RCAR_GP_PIN(0, 17), /* A1 */ 5666 [18] = RCAR_GP_PIN(0, 18), /* A2 */ 5667 [19] = RCAR_GP_PIN(0, 19), /* A3 */ 5668 [20] = RCAR_GP_PIN(0, 20), /* A4 */ 5669 [21] = RCAR_GP_PIN(0, 21), /* A5 */ 5670 [22] = RCAR_GP_PIN(0, 22), /* A6 */ 5671 [23] = RCAR_GP_PIN(0, 23), /* A7 */ 5672 [24] = RCAR_GP_PIN(0, 24), /* A8 */ 5673 [25] = RCAR_GP_PIN(0, 25), /* A9 */ 5674 [26] = RCAR_GP_PIN(0, 26), /* A10 */ 5675 [27] = RCAR_GP_PIN(0, 27), /* A11 */ 5676 [28] = RCAR_GP_PIN(0, 28), /* A12 */ 5677 [29] = RCAR_GP_PIN(0, 29), /* A13 */ 5678 [30] = RCAR_GP_PIN(0, 30), /* A14 */ 5679 [31] = RCAR_GP_PIN(0, 31), /* A15 */ 5680 } }, 5681 { PINMUX_BIAS_REG("PUPR1", 0xe6060104, "N/A", 0) { 5682 /* PUPR1 pull-up pins */ 5683 [ 0] = RCAR_GP_PIN(1, 0), /* A16 */ 5684 [ 1] = RCAR_GP_PIN(1, 1), /* A17 */ 5685 [ 2] = RCAR_GP_PIN(1, 2), /* A18 */ 5686 [ 3] = RCAR_GP_PIN(1, 3), /* A19 */ 5687 [ 4] = RCAR_GP_PIN(1, 4), /* A20 */ 5688 [ 5] = RCAR_GP_PIN(1, 5), /* A21 */ 5689 [ 6] = RCAR_GP_PIN(1, 6), /* A22 */ 5690 [ 7] = RCAR_GP_PIN(1, 7), /* A23 */ 5691 [ 8] = RCAR_GP_PIN(1, 8), /* A24 */ 5692 [ 9] = RCAR_GP_PIN(1, 9), /* A25 */ 5693 [10] = RCAR_GP_PIN(1, 10), /* CS0# */ 5694 [11] = RCAR_GP_PIN(1, 12), /* EX_CS0# */ 5695 [12] = RCAR_GP_PIN(1, 14), /* EX_CS2# */ 5696 [13] = RCAR_GP_PIN(1, 16), /* EX_CS4# */ 5697 [14] = RCAR_GP_PIN(1, 18), /* BS# */ 5698 [15] = RCAR_GP_PIN(1, 19), /* RD# */ 5699 [16] = RCAR_GP_PIN(1, 20), /* RD/WR# */ 5700 [17] = RCAR_GP_PIN(1, 21), /* WE0# */ 5701 [18] = RCAR_GP_PIN(1, 22), /* WE1# */ 5702 [19] = RCAR_GP_PIN(1, 23), /* EX_WAIT0 */ 5703 [20] = RCAR_GP_PIN(1, 24), /* DREQ0# */ 5704 [21] = RCAR_GP_PIN(1, 25), /* DACK0 */ 5705 [22] = PIN_TRST_N, /* TRST# */ 5706 [23] = PIN_TCK, /* TCK */ 5707 [24] = PIN_TMS, /* TMS */ 5708 [25] = PIN_TDI, /* TDI */ 5709 [26] = RCAR_GP_PIN(1, 11), /* CS1#/A26 */ 5710 [27] = RCAR_GP_PIN(1, 13), /* EX_CS1# */ 5711 [28] = RCAR_GP_PIN(1, 15), /* EX_CS3# */ 5712 [29] = RCAR_GP_PIN(1, 17), /* EX_CS5# */ 5713 [30] = SH_PFC_PIN_NONE, 5714 [31] = SH_PFC_PIN_NONE, 5715 } }, 5716 { PINMUX_BIAS_REG("N/A", 0, "PUPR1", 0xe6060104) { 5717 /* PUPR1 pull-down pins */ 5718 [ 0] = SH_PFC_PIN_NONE, 5719 [ 1] = SH_PFC_PIN_NONE, 5720 [ 2] = SH_PFC_PIN_NONE, 5721 [ 3] = SH_PFC_PIN_NONE, 5722 [ 4] = SH_PFC_PIN_NONE, 5723 [ 5] = SH_PFC_PIN_NONE, 5724 [ 6] = SH_PFC_PIN_NONE, 5725 [ 7] = SH_PFC_PIN_NONE, 5726 [ 8] = SH_PFC_PIN_NONE, 5727 [ 9] = SH_PFC_PIN_NONE, 5728 [10] = SH_PFC_PIN_NONE, 5729 [11] = SH_PFC_PIN_NONE, 5730 [12] = SH_PFC_PIN_NONE, 5731 [13] = SH_PFC_PIN_NONE, 5732 [14] = SH_PFC_PIN_NONE, 5733 [15] = SH_PFC_PIN_NONE, 5734 [16] = SH_PFC_PIN_NONE, 5735 [17] = SH_PFC_PIN_NONE, 5736 [18] = SH_PFC_PIN_NONE, 5737 [19] = SH_PFC_PIN_NONE, 5738 [20] = SH_PFC_PIN_NONE, 5739 [21] = SH_PFC_PIN_NONE, 5740 [22] = SH_PFC_PIN_NONE, 5741 [23] = SH_PFC_PIN_NONE, 5742 [24] = SH_PFC_PIN_NONE, 5743 [25] = SH_PFC_PIN_NONE, 5744 [26] = SH_PFC_PIN_NONE, 5745 [27] = SH_PFC_PIN_NONE, 5746 [28] = SH_PFC_PIN_NONE, 5747 [29] = SH_PFC_PIN_NONE, 5748 [30] = PIN_ASEBRK_N_ACK, /* ASEBRK#/ACK */ 5749 [31] = SH_PFC_PIN_NONE, 5750 } }, 5751 { PINMUX_BIAS_REG("PUPR2", 0xe6060108, "N/A", 0) { 5752 [ 0] = RCAR_GP_PIN(2, 0), /* DU0_DR0 */ 5753 [ 1] = RCAR_GP_PIN(2, 1), /* DU0_DR1 */ 5754 [ 2] = RCAR_GP_PIN(2, 2), /* DU0_DR2 */ 5755 [ 3] = RCAR_GP_PIN(2, 3), /* DU0_DR3 */ 5756 [ 4] = RCAR_GP_PIN(2, 4), /* DU0_DR4 */ 5757 [ 5] = RCAR_GP_PIN(2, 5), /* DU0_DR5 */ 5758 [ 6] = RCAR_GP_PIN(2, 6), /* DU0_DR6 */ 5759 [ 7] = RCAR_GP_PIN(2, 7), /* DU0_DR7 */ 5760 [ 8] = RCAR_GP_PIN(2, 8), /* DU0_DG0 */ 5761 [ 9] = RCAR_GP_PIN(2, 9), /* DU0_DG1 */ 5762 [10] = RCAR_GP_PIN(2, 10), /* DU0_DG2 */ 5763 [11] = RCAR_GP_PIN(2, 11), /* DU0_DG3 */ 5764 [12] = RCAR_GP_PIN(2, 12), /* DU0_DG4 */ 5765 [13] = RCAR_GP_PIN(2, 13), /* DU0_DG5 */ 5766 [14] = RCAR_GP_PIN(2, 14), /* DU0_DG6 */ 5767 [15] = RCAR_GP_PIN(2, 15), /* DU0_DG7 */ 5768 [16] = RCAR_GP_PIN(2, 16), /* DU0_DB0 */ 5769 [17] = RCAR_GP_PIN(2, 17), /* DU0_DB1 */ 5770 [18] = RCAR_GP_PIN(2, 18), /* DU0_DB2 */ 5771 [19] = RCAR_GP_PIN(2, 19), /* DU0_DB3 */ 5772 [20] = RCAR_GP_PIN(2, 20), /* DU0_DB4 */ 5773 [21] = RCAR_GP_PIN(2, 21), /* DU0_DB5 */ 5774 [22] = RCAR_GP_PIN(2, 22), /* DU0_DB6 */ 5775 [23] = RCAR_GP_PIN(2, 23), /* DU0_DB7 */ 5776 [24] = RCAR_GP_PIN(2, 24), /* DU0_DOTCLKIN */ 5777 [25] = RCAR_GP_PIN(2, 25), /* DU0_DOTCLKOUT0 */ 5778 [26] = RCAR_GP_PIN(2, 26), /* DU0_DOTCLKOUT1 */ 5779 [27] = RCAR_GP_PIN(2, 27), /* DU0_EXHSYNC/DU0_HSYNC */ 5780 [28] = RCAR_GP_PIN(2, 28), /* DU0_EXVSYNC/DU0_VSYNC */ 5781 [29] = RCAR_GP_PIN(2, 29), /* DU0_EXODDF/DU0_ODDF_DISP_CDE */ 5782 [30] = RCAR_GP_PIN(2, 30), /* DU0_DISP */ 5783 [31] = RCAR_GP_PIN(2, 31), /* DU0_CDE */ 5784 } }, 5785 { PINMUX_BIAS_REG("PUPR3", 0xe606010c, "N/A", 0) { 5786 [ 0] = RCAR_GP_PIN(3, 2), /* VI0_DATA1_VI0_B1 */ 5787 [ 1] = RCAR_GP_PIN(3, 3), /* VI0_DATA2_VI0_B2 */ 5788 [ 2] = RCAR_GP_PIN(3, 4), /* VI0_DATA3_VI0_B3 */ 5789 [ 3] = RCAR_GP_PIN(3, 5), /* VI0_DATA4_VI0_B4 */ 5790 [ 4] = RCAR_GP_PIN(3, 6), /* VI0_DATA5_VI0_B5 */ 5791 [ 5] = RCAR_GP_PIN(3, 7), /* VI0_DATA6_VI0_B6 */ 5792 [ 6] = RCAR_GP_PIN(3, 8), /* VI0_DATA7_VI0_B7 */ 5793 [ 7] = RCAR_GP_PIN(3, 9), /* VI0_CLKENB */ 5794 [ 8] = RCAR_GP_PIN(3, 10), /* VI0_FIELD */ 5795 [ 9] = RCAR_GP_PIN(3, 11), /* VI0_HSYNC# */ 5796 [10] = RCAR_GP_PIN(3, 12), /* VI0_VSYNC# */ 5797 [11] = RCAR_GP_PIN(3, 13), /* ETH_MDIO */ 5798 [12] = RCAR_GP_PIN(3, 14), /* ETH_CRS_DV */ 5799 [13] = RCAR_GP_PIN(3, 15), /* ETH_RX_ER */ 5800 [14] = RCAR_GP_PIN(3, 16), /* ETH_RXD0 */ 5801 [15] = RCAR_GP_PIN(3, 17), /* ETH_RXD1 */ 5802 [16] = RCAR_GP_PIN(3, 18), /* ETH_LINK */ 5803 [17] = RCAR_GP_PIN(3, 19), /* ETH_REF_CLK */ 5804 [18] = RCAR_GP_PIN(3, 20), /* ETH_TXD1 */ 5805 [19] = RCAR_GP_PIN(3, 21), /* ETH_TX_EN */ 5806 [20] = RCAR_GP_PIN(3, 22), /* ETH_MAGIC */ 5807 [21] = RCAR_GP_PIN(3, 23), /* ETH_TXD0 */ 5808 [22] = RCAR_GP_PIN(3, 24), /* ETH_MDC */ 5809 [23] = RCAR_GP_PIN(3, 25), /* HSCIF0_HRX */ 5810 [24] = RCAR_GP_PIN(3, 26), /* HSCIF0_HTX */ 5811 [25] = RCAR_GP_PIN(3, 27), /* HSCIF0_HCTS# */ 5812 [26] = RCAR_GP_PIN(3, 28), /* HSCIF0_HRTS# */ 5813 [27] = RCAR_GP_PIN(3, 29), /* HSCIF0_HSCK */ 5814 [28] = RCAR_GP_PIN(3, 30), /* I2C0_SCL */ 5815 [29] = RCAR_GP_PIN(3, 31), /* I2C0_SDA */ 5816 [30] = RCAR_GP_PIN(4, 0), /* I2C1_SCL */ 5817 [31] = RCAR_GP_PIN(4, 1), /* I2C1_SDA */ 5818 } }, 5819 { PINMUX_BIAS_REG("PUPR4", 0xe6060110, "N/A", 0) { 5820 [ 0] = RCAR_GP_PIN(4, 2), /* MSIOF0_RXD */ 5821 [ 1] = RCAR_GP_PIN(4, 3), /* MSIOF0_TXD */ 5822 [ 2] = RCAR_GP_PIN(4, 4), /* MSIOF0_SCK */ 5823 [ 3] = RCAR_GP_PIN(4, 5), /* MSIOF0_SYNC */ 5824 [ 4] = RCAR_GP_PIN(4, 6), /* MSIOF0_SS1 */ 5825 [ 5] = RCAR_GP_PIN(4, 7), /* MSIOF0_SS2 */ 5826 [ 6] = RCAR_GP_PIN(4, 8), /* HSCIF1_HRX */ 5827 [ 7] = RCAR_GP_PIN(4, 9), /* HSCIF1_HTX */ 5828 [ 8] = RCAR_GP_PIN(4, 10), /* HSCIF1_HSCK */ 5829 [ 9] = RCAR_GP_PIN(4, 11), /* HSCIF1_HCTS# */ 5830 [10] = RCAR_GP_PIN(4, 12), /* HSCIF1_HRTS# */ 5831 [11] = RCAR_GP_PIN(4, 13), /* SCIF1_SCK */ 5832 [12] = RCAR_GP_PIN(4, 14), /* SCIF1_RXD */ 5833 [13] = RCAR_GP_PIN(4, 15), /* SCIF1_TXD */ 5834 [14] = RCAR_GP_PIN(4, 16), /* SCIF2_RXD */ 5835 [15] = RCAR_GP_PIN(4, 17), /* SCIF2_TXD */ 5836 [16] = RCAR_GP_PIN(4, 18), /* SCIF2_SCK */ 5837 [17] = RCAR_GP_PIN(4, 19), /* SCIF3_SCK */ 5838 [18] = RCAR_GP_PIN(4, 20), /* SCIF3_RXD */ 5839 [19] = RCAR_GP_PIN(4, 21), /* SCIF3_TXD */ 5840 [20] = RCAR_GP_PIN(4, 22), /* I2C2_SCL */ 5841 [21] = RCAR_GP_PIN(4, 23), /* I2C2_SDA */ 5842 [22] = RCAR_GP_PIN(4, 24), /* SSI_SCK5 */ 5843 [23] = RCAR_GP_PIN(4, 25), /* SSI_WS5 */ 5844 [24] = RCAR_GP_PIN(4, 26), /* SSI_SDATA5 */ 5845 [25] = RCAR_GP_PIN(4, 27), /* SSI_SCK6 */ 5846 [26] = RCAR_GP_PIN(4, 28), /* SSI_WS6 */ 5847 [27] = RCAR_GP_PIN(4, 29), /* SSI_SDATA6 */ 5848 [28] = RCAR_GP_PIN(4, 30), /* SSI_SCK78 */ 5849 [29] = RCAR_GP_PIN(4, 31), /* SSI_WS78 */ 5850 [30] = RCAR_GP_PIN(5, 0), /* SSI_SDATA7 */ 5851 [31] = RCAR_GP_PIN(5, 1), /* SSI_SCK0129 */ 5852 } }, 5853 { PINMUX_BIAS_REG("PUPR5", 0xe6060114, "N/A", 0) { 5854 [ 0] = RCAR_GP_PIN(5, 2), /* SSI_WS0129 */ 5855 [ 1] = RCAR_GP_PIN(5, 3), /* SSI_SDATA0 */ 5856 [ 2] = RCAR_GP_PIN(5, 4), /* SSI_SCK34 */ 5857 [ 3] = RCAR_GP_PIN(5, 5), /* SSI_WS34 */ 5858 [ 4] = RCAR_GP_PIN(5, 6), /* SSI_SDATA3 */ 5859 [ 5] = SH_PFC_PIN_NONE, 5860 [ 6] = SH_PFC_PIN_NONE, 5861 [ 7] = SH_PFC_PIN_NONE, 5862 [ 8] = RCAR_GP_PIN(5, 10), /* SSI_SDATA8 */ 5863 [ 9] = RCAR_GP_PIN(5, 11), /* SSI_SCK1 */ 5864 [10] = RCAR_GP_PIN(5, 12), /* SSI_WS1 */ 5865 [11] = RCAR_GP_PIN(5, 13), /* SSI_SDATA1 */ 5866 [12] = RCAR_GP_PIN(5, 14), /* SSI_SCK2 */ 5867 [13] = RCAR_GP_PIN(5, 15), /* SSI_WS2 */ 5868 [14] = RCAR_GP_PIN(5, 16), /* SSI_SDATA2 */ 5869 [15] = RCAR_GP_PIN(5, 17), /* SSI_SCK9 */ 5870 [16] = RCAR_GP_PIN(5, 18), /* SSI_WS9 */ 5871 [17] = RCAR_GP_PIN(5, 19), /* SSI_SDATA9 */ 5872 [18] = RCAR_GP_PIN(5, 20), /* AUDIO_CLKA */ 5873 [19] = RCAR_GP_PIN(5, 21), /* AUDIO_CLKB */ 5874 [20] = RCAR_GP_PIN(5, 22), /* AUDIO_CLKC */ 5875 [21] = RCAR_GP_PIN(5, 23), /* AUDIO_CLKOUT */ 5876 [22] = RCAR_GP_PIN(3, 0), /* VI0_CLK */ 5877 [23] = RCAR_GP_PIN(3, 1), /* VI0_DATA0_VI0_B0 */ 5878 [24] = SH_PFC_PIN_NONE, 5879 [25] = SH_PFC_PIN_NONE, 5880 [26] = SH_PFC_PIN_NONE, 5881 [27] = SH_PFC_PIN_NONE, 5882 [28] = SH_PFC_PIN_NONE, 5883 [29] = SH_PFC_PIN_NONE, 5884 [30] = SH_PFC_PIN_NONE, 5885 [31] = SH_PFC_PIN_NONE, 5886 } }, 5887 { PINMUX_BIAS_REG("PUPR6", 0xe6060118, "N/A", 0) { 5888 [ 0] = RCAR_GP_PIN(6, 1), /* SD0_CMD */ 5889 [ 1] = RCAR_GP_PIN(6, 2), /* SD0_DATA0 */ 5890 [ 2] = RCAR_GP_PIN(6, 3), /* SD0_DATA1 */ 5891 [ 3] = RCAR_GP_PIN(6, 4), /* SD0_DATA2 */ 5892 [ 4] = RCAR_GP_PIN(6, 5), /* SD0_DATA3 */ 5893 [ 5] = RCAR_GP_PIN(6, 6), /* SD0_CD */ 5894 [ 6] = RCAR_GP_PIN(6, 7), /* SD0_WP */ 5895 [ 7] = RCAR_GP_PIN(6, 9), /* SD1_CMD */ 5896 [ 8] = RCAR_GP_PIN(6, 10), /* SD1_DATA0 */ 5897 [ 9] = RCAR_GP_PIN(6, 11), /* SD1_DATA1 */ 5898 [10] = RCAR_GP_PIN(6, 12), /* SD1_DATA2 */ 5899 [11] = RCAR_GP_PIN(6, 13), /* SD1_DATA3 */ 5900 [12] = RCAR_GP_PIN(6, 14), /* SD1_CD */ 5901 [13] = RCAR_GP_PIN(6, 15), /* SD1_WP */ 5902 [14] = SH_PFC_PIN_NONE, 5903 [15] = RCAR_GP_PIN(6, 17), /* MMC_CMD */ 5904 [16] = RCAR_GP_PIN(6, 18), /* MMC_D0 */ 5905 [17] = RCAR_GP_PIN(6, 19), /* MMC_D1 */ 5906 [18] = RCAR_GP_PIN(6, 20), /* MMC_D2 */ 5907 [19] = RCAR_GP_PIN(6, 21), /* MMC_D3 */ 5908 [20] = RCAR_GP_PIN(6, 22), /* MMC_D4 */ 5909 [21] = RCAR_GP_PIN(6, 23), /* MMC_D5 */ 5910 [22] = RCAR_GP_PIN(6, 24), /* MMC_D6 */ 5911 [23] = RCAR_GP_PIN(6, 25), /* MMC_D7 */ 5912 [24] = SH_PFC_PIN_NONE, 5913 [25] = SH_PFC_PIN_NONE, 5914 [26] = SH_PFC_PIN_NONE, 5915 [27] = SH_PFC_PIN_NONE, 5916 [28] = SH_PFC_PIN_NONE, 5917 [29] = SH_PFC_PIN_NONE, 5918 [30] = SH_PFC_PIN_NONE, 5919 [31] = SH_PFC_PIN_NONE, 5920 } }, 5921 { /* sentinel */ } 5922 }; 5923 5924 static const struct soc_device_attribute r8a7794_tdsel[] = { 5925 { .soc_id = "r8a7794", .revision = "ES1.0" }, 5926 { /* sentinel */ } 5927 }; 5928 5929 static int r8a7794_pinmux_soc_init(struct sh_pfc *pfc) 5930 { 5931 /* Initialize TDSEL on old revisions */ 5932 if (soc_device_match(r8a7794_tdsel)) 5933 sh_pfc_write(pfc, 0xe6060068, 0x55555500); 5934 5935 return 0; 5936 } 5937 5938 static const struct sh_pfc_soc_operations r8a7794_pfc_ops = { 5939 .init = r8a7794_pinmux_soc_init, 5940 .pin_to_pocctrl = r8a7794_pin_to_pocctrl, 5941 .get_bias = rcar_pinmux_get_bias, 5942 .set_bias = rcar_pinmux_set_bias, 5943 }; 5944 5945 #ifdef CONFIG_PINCTRL_PFC_R8A7745 5946 const struct sh_pfc_soc_info r8a7745_pinmux_info = { 5947 .name = "r8a77450_pfc", 5948 .ops = &r8a7794_pfc_ops, 5949 .unlock_reg = 0xe6060000, /* PMMR */ 5950 5951 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 5952 5953 .pins = pinmux_pins, 5954 .nr_pins = ARRAY_SIZE(pinmux_pins), 5955 .groups = pinmux_groups, 5956 .nr_groups = ARRAY_SIZE(pinmux_groups), 5957 .functions = pinmux_functions, 5958 .nr_functions = ARRAY_SIZE(pinmux_functions), 5959 5960 .cfg_regs = pinmux_config_regs, 5961 .bias_regs = pinmux_bias_regs, 5962 5963 .pinmux_data = pinmux_data, 5964 .pinmux_data_size = ARRAY_SIZE(pinmux_data), 5965 }; 5966 #endif 5967 5968 #ifdef CONFIG_PINCTRL_PFC_R8A7794 5969 const struct sh_pfc_soc_info r8a7794_pinmux_info = { 5970 .name = "r8a77940_pfc", 5971 .ops = &r8a7794_pfc_ops, 5972 .unlock_reg = 0xe6060000, /* PMMR */ 5973 5974 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 5975 5976 .pins = pinmux_pins, 5977 .nr_pins = ARRAY_SIZE(pinmux_pins), 5978 .groups = pinmux_groups, 5979 .nr_groups = ARRAY_SIZE(pinmux_groups), 5980 .functions = pinmux_functions, 5981 .nr_functions = ARRAY_SIZE(pinmux_functions), 5982 5983 .cfg_regs = pinmux_config_regs, 5984 .bias_regs = pinmux_bias_regs, 5985 5986 .pinmux_data = pinmux_data, 5987 .pinmux_data_size = ARRAY_SIZE(pinmux_data), 5988 }; 5989 #endif 5990