1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * r8a7794/r8a7745 processor support - PFC hardware block.
4  *
5  * Copyright (C) 2014-2015 Renesas Electronics Corporation
6  * Copyright (C) 2015 Renesas Solutions Corp.
7  * Copyright (C) 2015-2017 Cogent Embedded, Inc. <source@cogentembedded.com>
8  */
9 
10 #include <linux/errno.h>
11 #include <linux/kernel.h>
12 #include <linux/sys_soc.h>
13 
14 #include "core.h"
15 #include "sh_pfc.h"
16 
17 #define CPU_ALL_GP(fn, sfx)						\
18 	PORT_GP_CFG_32(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),		\
19 	PORT_GP_CFG_26(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),		\
20 	PORT_GP_CFG_32(2, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),		\
21 	PORT_GP_CFG_32(3, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),		\
22 	PORT_GP_CFG_32(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),		\
23 	PORT_GP_CFG_7(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),		\
24 	PORT_GP_1(5, 7, fn, sfx),					\
25 	PORT_GP_1(5, 8, fn, sfx),					\
26 	PORT_GP_1(5, 9, fn, sfx),					\
27 	PORT_GP_CFG_1(5, 10, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),		\
28 	PORT_GP_CFG_1(5, 11, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),		\
29 	PORT_GP_CFG_1(5, 12, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),		\
30 	PORT_GP_CFG_1(5, 13, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),		\
31 	PORT_GP_CFG_1(5, 14, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),		\
32 	PORT_GP_CFG_1(5, 15, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),		\
33 	PORT_GP_CFG_1(5, 16, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),		\
34 	PORT_GP_CFG_1(5, 17, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),		\
35 	PORT_GP_CFG_1(5, 18, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),		\
36 	PORT_GP_CFG_1(5, 19, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),		\
37 	PORT_GP_CFG_1(5, 20, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),		\
38 	PORT_GP_CFG_1(5, 21, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),		\
39 	PORT_GP_CFG_1(5, 22, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),		\
40 	PORT_GP_CFG_1(5, 23, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),		\
41 	PORT_GP_1(5, 24, fn, sfx),					\
42 	PORT_GP_1(5, 25, fn, sfx),					\
43 	PORT_GP_1(5, 26, fn, sfx),					\
44 	PORT_GP_1(5, 27, fn, sfx),					\
45 	PORT_GP_CFG_1(6, 0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),	\
46 	PORT_GP_CFG_1(6, 1, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP),	\
47 	PORT_GP_CFG_1(6, 2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP),	\
48 	PORT_GP_CFG_1(6, 3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP),	\
49 	PORT_GP_CFG_1(6, 4, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP),	\
50 	PORT_GP_CFG_1(6, 5, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP),	\
51 	PORT_GP_CFG_1(6, 6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP),	\
52 	PORT_GP_CFG_1(6, 7, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP),	\
53 	PORT_GP_CFG_1(6, 8, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),	\
54 	PORT_GP_CFG_1(6, 9, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP),	\
55 	PORT_GP_CFG_1(6, 10, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP),	\
56 	PORT_GP_CFG_1(6, 11, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP),	\
57 	PORT_GP_CFG_1(6, 12, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP),	\
58 	PORT_GP_CFG_1(6, 13, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP),	\
59 	PORT_GP_CFG_1(6, 14, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP),	\
60 	PORT_GP_CFG_1(6, 15, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP),	\
61 	PORT_GP_CFG_1(6, 16, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),	\
62 	PORT_GP_CFG_1(6, 17, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP),	\
63 	PORT_GP_CFG_1(6, 18, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP),	\
64 	PORT_GP_CFG_1(6, 19, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP),	\
65 	PORT_GP_CFG_1(6, 20, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP),	\
66 	PORT_GP_CFG_1(6, 21, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP),	\
67 	PORT_GP_CFG_1(6, 22, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP),	\
68 	PORT_GP_CFG_1(6, 23, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP),	\
69 	PORT_GP_CFG_1(6, 24, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),		\
70 	PORT_GP_CFG_1(6, 25, fn, sfx, SH_PFC_PIN_CFG_PULL_UP)
71 
72 #define CPU_ALL_NOGP(fn)						\
73 	PIN_NOGP_CFG(ASEBRK_N_ACK, "ASEBRK#/ACK", fn, SH_PFC_PIN_CFG_PULL_DOWN),	\
74 	PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP),		\
75 	PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP),		\
76 	PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP),		\
77 	PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP)
78 
79 enum {
80 	PINMUX_RESERVED = 0,
81 
82 	PINMUX_DATA_BEGIN,
83 	GP_ALL(DATA),
84 	PINMUX_DATA_END,
85 
86 	PINMUX_FUNCTION_BEGIN,
87 	GP_ALL(FN),
88 
89 	/* GPSR0 */
90 	FN_IP0_23_22, FN_IP0_24, FN_IP0_25, FN_IP0_27_26, FN_IP0_29_28,
91 	FN_IP0_31_30, FN_IP1_1_0, FN_IP1_3_2, FN_IP1_5_4, FN_IP1_7_6,
92 	FN_IP1_10_8, FN_IP1_12_11, FN_IP1_14_13, FN_IP1_17_15, FN_IP1_19_18,
93 	FN_IP1_21_20, FN_IP1_23_22, FN_IP1_24, FN_A2, FN_IP1_26, FN_IP1_27,
94 	FN_IP1_29_28, FN_IP1_31_30, FN_IP2_1_0, FN_IP2_3_2, FN_IP2_5_4,
95 	FN_IP2_7_6, FN_IP2_9_8, FN_IP2_11_10, FN_IP2_13_12, FN_IP2_15_14,
96 	FN_IP2_17_16,
97 
98 	/* GPSR1 */
99 	FN_IP2_20_18, FN_IP2_23_21, FN_IP2_26_24, FN_IP2_29_27, FN_IP2_31_30,
100 	FN_IP3_1_0, FN_IP3_3_2, FN_IP3_5_4, FN_IP3_7_6, FN_IP3_9_8, FN_IP3_10,
101 	FN_IP3_11, FN_IP3_12, FN_IP3_14_13, FN_IP3_17_15, FN_IP3_20_18,
102 	FN_IP3_23_21, FN_IP3_26_24, FN_IP3_29_27, FN_IP3_30, FN_IP3_31,
103 	FN_WE0_N, FN_WE1_N, FN_IP4_1_0 , FN_IP7_31, FN_DACK0,
104 
105 	/* GPSR2 */
106 	FN_IP4_4_2, FN_IP4_7_5, FN_IP4_9_8, FN_IP4_11_10, FN_IP4_13_12,
107 	FN_IP4_15_14, FN_IP4_17_16, FN_IP4_19_18, FN_IP4_22_20, FN_IP4_25_23,
108 	FN_IP4_27_26, FN_IP4_29_28, FN_IP4_31_30, FN_IP5_1_0, FN_IP5_3_2,
109 	FN_IP5_5_4, FN_IP5_8_6, FN_IP5_11_9, FN_IP5_13_12, FN_IP5_15_14,
110 	FN_IP5_17_16, FN_IP5_19_18, FN_IP5_21_20, FN_IP5_23_22, FN_IP5_25_24,
111 	FN_IP5_27_26, FN_IP5_29_28, FN_IP5_31_30, FN_IP6_1_0, FN_IP6_3_2,
112 	FN_IP6_5_4, FN_IP6_7_6,
113 
114 	/* GPSR3 */
115 	FN_IP6_8, FN_IP6_9, FN_IP6_10, FN_IP6_11, FN_IP6_12, FN_IP6_13,
116 	FN_IP6_14, FN_IP6_15, FN_IP6_16, FN_IP6_19_17, FN_IP6_22_20,
117 	FN_IP6_25_23, FN_IP6_28_26, FN_IP6_31_29, FN_IP7_2_0, FN_IP7_5_3,
118 	FN_IP7_8_6, FN_IP7_11_9, FN_IP7_14_12, FN_IP7_17_15, FN_IP7_20_18,
119 	FN_IP7_23_21, FN_IP7_26_24, FN_IP7_29_27, FN_IP8_2_0, FN_IP8_5_3,
120 	FN_IP8_8_6, FN_IP8_11_9, FN_IP8_14_12, FN_IP8_16_15, FN_IP8_19_17,
121 	FN_IP8_22_20,
122 
123 	/* GPSR4 */
124 	FN_IP8_25_23, FN_IP8_28_26, FN_IP8_31_29, FN_IP9_2_0, FN_IP9_5_3,
125 	FN_IP9_8_6, FN_IP9_11_9, FN_IP9_14_12, FN_IP9_16_15, FN_IP9_18_17,
126 	FN_IP9_21_19, FN_IP9_24_22, FN_IP9_27_25, FN_IP9_30_28, FN_IP10_2_0,
127 	FN_IP10_5_3, FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_17_15,
128 	FN_IP10_20_18, FN_IP10_23_21, FN_IP10_26_24, FN_IP10_29_27,
129 	FN_IP10_31_30, FN_IP11_2_0, FN_IP11_5_3, FN_IP11_7_6, FN_IP11_10_8,
130 	FN_IP11_13_11, FN_IP11_15_14, FN_IP11_17_16,
131 
132 	/* GPSR5 */
133 	FN_IP11_20_18, FN_IP11_23_21, FN_IP11_26_24, FN_IP11_29_27, FN_IP12_2_0,
134 	FN_IP12_5_3, FN_IP12_8_6, FN_IP12_10_9, FN_IP12_12_11, FN_IP12_14_13,
135 	FN_IP12_17_15, FN_IP12_20_18, FN_IP12_23_21, FN_IP12_26_24,
136 	FN_IP12_29_27, FN_IP13_2_0, FN_IP13_5_3, FN_IP13_8_6, FN_IP13_11_9,
137 	FN_IP13_14_12, FN_IP13_17_15, FN_IP13_20_18, FN_IP13_23_21,
138 	FN_IP13_26_24, FN_USB0_PWEN, FN_USB0_OVC, FN_USB1_PWEN, FN_USB1_OVC,
139 
140 	/* GPSR6 */
141 	FN_SD0_CLK, FN_SD0_CMD, FN_SD0_DATA0, FN_SD0_DATA1, FN_SD0_DATA2,
142 	FN_SD0_DATA3, FN_SD0_CD, FN_SD0_WP, FN_SD1_CLK, FN_SD1_CMD,
143 	FN_SD1_DATA0, FN_SD1_DATA1, FN_SD1_DATA2, FN_SD1_DATA3, FN_IP0_0,
144 	FN_IP0_9_8, FN_IP0_10, FN_IP0_11, FN_IP0_12, FN_IP0_13, FN_IP0_14,
145 	FN_IP0_15, FN_IP0_16, FN_IP0_17, FN_IP0_19_18, FN_IP0_21_20,
146 
147 	/* IPSR0 */
148 	FN_SD1_CD, FN_CAN0_RX, FN_SD1_WP, FN_IRQ7, FN_CAN0_TX, FN_MMC_CLK,
149 	FN_SD2_CLK, FN_MMC_CMD, FN_SD2_CMD, FN_MMC_D0, FN_SD2_DATA0, FN_MMC_D1,
150 	FN_SD2_DATA1, FN_MMC_D2, FN_SD2_DATA2, FN_MMC_D3, FN_SD2_DATA3,
151 	FN_MMC_D4, FN_SD2_CD, FN_MMC_D5, FN_SD2_WP, FN_MMC_D6, FN_SCIF0_RXD,
152 	FN_I2C2_SCL_B, FN_CAN1_RX, FN_MMC_D7, FN_SCIF0_TXD, FN_I2C2_SDA_B,
153 	FN_CAN1_TX, FN_D0, FN_SCIFA3_SCK_B, FN_IRQ4, FN_D1, FN_SCIFA3_RXD_B,
154 	FN_D2, FN_SCIFA3_TXD_B, FN_D3, FN_I2C3_SCL_B, FN_SCIF5_RXD_B, FN_D4,
155 	FN_I2C3_SDA_B, FN_SCIF5_TXD_B, FN_D5, FN_SCIF4_RXD_B, FN_I2C0_SCL_D,
156 
157 	/* IPSR1 */
158 	FN_D6, FN_SCIF4_TXD_B, FN_I2C0_SDA_D,
159 	FN_D7, FN_IRQ3, FN_TCLK1, FN_PWM6_B,
160 	FN_D8, FN_HSCIF2_HRX, FN_I2C1_SCL_B,
161 	FN_D9, FN_HSCIF2_HTX, FN_I2C1_SDA_B,
162 	FN_D10, FN_HSCIF2_HSCK, FN_SCIF1_SCK_C, FN_IRQ6, FN_PWM5_C,
163 	FN_D11, FN_HSCIF2_HCTS_N, FN_SCIF1_RXD_C, FN_I2C1_SCL_D,
164 	FN_D12, FN_HSCIF2_HRTS_N, FN_SCIF1_TXD_C, FN_I2C1_SDA_D,
165 	FN_D13, FN_SCIFA1_SCK, FN_PWM2_C, FN_TCLK2_B,
166 	FN_D14, FN_SCIFA1_RXD, FN_I2C5_SCL_B,
167 	FN_D15, FN_SCIFA1_TXD, FN_I2C5_SDA_B,
168 	FN_A0, FN_SCIFB1_SCK, FN_PWM3_B,
169 	FN_A1, FN_SCIFB1_TXD,
170 	FN_A3, FN_SCIFB0_SCK,
171 	FN_A4, FN_SCIFB0_TXD,
172 	FN_A5, FN_SCIFB0_RXD, FN_PWM4_B, FN_TPUTO3_C,
173 	FN_A6, FN_SCIFB0_CTS_N, FN_SCIFA4_RXD_B, FN_TPUTO2_C,
174 
175 	/* IPSR2 */
176 	FN_A7, FN_SCIFB0_RTS_N, FN_SCIFA4_TXD_B,
177 	FN_A8, FN_MSIOF1_RXD, FN_SCIFA0_RXD_B,
178 	FN_A9, FN_MSIOF1_TXD, FN_SCIFA0_TXD_B,
179 	FN_A10, FN_MSIOF1_SCK, FN_IIC0_SCL_B,
180 	FN_A11, FN_MSIOF1_SYNC, FN_IIC0_SDA_B,
181 	FN_A12, FN_MSIOF1_SS1, FN_SCIFA5_RXD_B,
182 	FN_A13, FN_MSIOF1_SS2, FN_SCIFA5_TXD_B,
183 	FN_A14, FN_MSIOF2_RXD, FN_HSCIF0_HRX_B, FN_DREQ1_N,
184 	FN_A15, FN_MSIOF2_TXD, FN_HSCIF0_HTX_B, FN_DACK1,
185 	FN_A16, FN_MSIOF2_SCK, FN_HSCIF0_HSCK_B, FN_SPEEDIN, FN_CAN_CLK_C,
186 	FN_TPUTO2_B,
187 	FN_A17, FN_MSIOF2_SYNC, FN_SCIF4_RXD_E, FN_CAN1_RX_B,
188 	FN_A18, FN_MSIOF2_SS1, FN_SCIF4_TXD_E, FN_CAN1_TX_B,
189 	FN_A19, FN_MSIOF2_SS2, FN_PWM4, FN_TPUTO2,
190 	FN_A20, FN_SPCLK,
191 
192 	/* IPSR3 */
193 	FN_A21, FN_MOSI_IO0,
194 	FN_A22, FN_MISO_IO1, FN_ATADIR1_N,
195 	FN_A23, FN_IO2, FN_ATAWR1_N,
196 	FN_A24, FN_IO3, FN_EX_WAIT2,
197 	FN_A25, FN_SSL, FN_ATARD1_N,
198 	FN_CS0_N, FN_VI1_DATA8,
199 	FN_CS1_N_A26, FN_VI1_DATA9,
200 	FN_EX_CS0_N, FN_VI1_DATA10,
201 	FN_EX_CS1_N, FN_TPUTO3_B, FN_SCIFB2_RXD, FN_VI1_DATA11,
202 	FN_EX_CS2_N, FN_PWM0, FN_SCIF4_RXD_C, FN_TS_SDATA_B, FN_TPUTO3,
203 	FN_SCIFB2_TXD,
204 	FN_EX_CS3_N, FN_SCIFA2_SCK, FN_SCIF4_TXD_C, FN_TS_SCK_B, FN_BPFCLK,
205 	FN_SCIFB2_SCK,
206 	FN_EX_CS4_N, FN_SCIFA2_RXD, FN_I2C2_SCL_E, FN_TS_SDEN_B, FN_FMCLK,
207 	FN_SCIFB2_CTS_N,
208 	FN_EX_CS5_N, FN_SCIFA2_TXD, FN_I2C2_SDA_E, FN_TS_SPSYNC_B, FN_FMIN,
209 	FN_SCIFB2_RTS_N,
210 	FN_BS_N, FN_DRACK0, FN_PWM1_C, FN_TPUTO0_C, FN_ATACS01_N,
211 	FN_RD_N, FN_ATACS11_N,
212 	FN_RD_WR_N, FN_ATAG1_N,
213 
214 	/* IPSR4 */
215 	FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK,
216 	FN_DU0_DR0, FN_LCDOUT16, FN_SCIF5_RXD_C, FN_I2C2_SCL_D,
217 	FN_DU0_DR1, FN_LCDOUT17, FN_SCIF5_TXD_C, FN_I2C2_SDA_D,
218 	FN_DU0_DR2, FN_LCDOUT18,
219 	FN_DU0_DR3, FN_LCDOUT19,
220 	FN_DU0_DR4, FN_LCDOUT20,
221 	FN_DU0_DR5, FN_LCDOUT21,
222 	FN_DU0_DR6, FN_LCDOUT22,
223 	FN_DU0_DR7, FN_LCDOUT23,
224 	FN_DU0_DG0, FN_LCDOUT8, FN_SCIFA0_RXD_C, FN_I2C3_SCL_D,
225 	FN_DU0_DG1, FN_LCDOUT9, FN_SCIFA0_TXD_C, FN_I2C3_SDA_D,
226 	FN_DU0_DG2, FN_LCDOUT10,
227 	FN_DU0_DG3, FN_LCDOUT11,
228 	FN_DU0_DG4, FN_LCDOUT12,
229 
230 	/* IPSR5 */
231 	FN_DU0_DG5, FN_LCDOUT13,
232 	FN_DU0_DG6, FN_LCDOUT14,
233 	FN_DU0_DG7, FN_LCDOUT15,
234 	FN_DU0_DB0, FN_LCDOUT0, FN_SCIFA4_RXD_C, FN_I2C4_SCL_D, FN_CAN0_RX_C,
235 	FN_DU0_DB1, FN_LCDOUT1, FN_SCIFA4_TXD_C, FN_I2C4_SDA_D, FN_CAN0_TX_C,
236 	FN_DU0_DB2, FN_LCDOUT2,
237 	FN_DU0_DB3, FN_LCDOUT3,
238 	FN_DU0_DB4, FN_LCDOUT4,
239 	FN_DU0_DB5, FN_LCDOUT5,
240 	FN_DU0_DB6, FN_LCDOUT6,
241 	FN_DU0_DB7, FN_LCDOUT7,
242 	FN_DU0_DOTCLKIN, FN_QSTVA_QVS,
243 	FN_DU0_DOTCLKOUT0, FN_QCLK,
244 	FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE,
245 	FN_DU0_EXHSYNC_DU0_HSYNC, FN_QSTH_QHS,
246 
247 	/* IPSR6 */
248 	FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE,
249 	FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE,
250 	FN_DU0_DISP, FN_QPOLA,
251 	FN_DU0_CDE, FN_QPOLB,
252 	FN_VI0_CLK, FN_AVB_RX_CLK,
253 	FN_VI0_DATA0_VI0_B0, FN_AVB_RX_DV,
254 	FN_VI0_DATA1_VI0_B1, FN_AVB_RXD0,
255 	FN_VI0_DATA2_VI0_B2, FN_AVB_RXD1,
256 	FN_VI0_DATA3_VI0_B3, FN_AVB_RXD2,
257 	FN_VI0_DATA4_VI0_B4, FN_AVB_RXD3,
258 	FN_VI0_DATA5_VI0_B5, FN_AVB_RXD4,
259 	FN_VI0_DATA6_VI0_B6, FN_AVB_RXD5,
260 	FN_VI0_DATA7_VI0_B7, FN_AVB_RXD6,
261 	FN_VI0_CLKENB, FN_I2C3_SCL, FN_SCIFA5_RXD_C, FN_IETX_C, FN_AVB_RXD7,
262 	FN_VI0_FIELD, FN_I2C3_SDA, FN_SCIFA5_TXD_C, FN_IECLK_C, FN_AVB_RX_ER,
263 	FN_VI0_HSYNC_N, FN_SCIF0_RXD_B, FN_I2C0_SCL_C, FN_IERX_C, FN_AVB_COL,
264 	FN_VI0_VSYNC_N, FN_SCIF0_TXD_B, FN_I2C0_SDA_C, FN_AUDIO_CLKOUT_B,
265 	FN_AVB_TX_EN,
266 	FN_ETH_MDIO, FN_VI0_G0, FN_MSIOF2_RXD_B, FN_I2C5_SCL_D, FN_AVB_TX_CLK,
267 	FN_ADIDATA,
268 
269 	/* IPSR7 */
270 	FN_ETH_CRS_DV, FN_VI0_G1, FN_MSIOF2_TXD_B, FN_I2C5_SDA_D, FN_AVB_TXD0,
271 	FN_ADICS_SAMP,
272 	FN_ETH_RX_ER, FN_VI0_G2, FN_MSIOF2_SCK_B, FN_CAN0_RX_B, FN_AVB_TXD1,
273 	FN_ADICLK,
274 	FN_ETH_RXD0, FN_VI0_G3,	FN_MSIOF2_SYNC_B, FN_CAN0_TX_B, FN_AVB_TXD2,
275 	FN_ADICHS0,
276 	FN_ETH_RXD1, FN_VI0_G4, FN_MSIOF2_SS1_B, FN_SCIF4_RXD_D, FN_AVB_TXD3,
277 	FN_ADICHS1,
278 	FN_ETH_LINK, FN_VI0_G5, FN_MSIOF2_SS2_B, FN_SCIF4_TXD_D, FN_AVB_TXD4,
279 	FN_ADICHS2,
280 	FN_ETH_REFCLK, FN_VI0_G6, FN_SCIF2_SCK_C, FN_AVB_TXD5, FN_SSI_SCK5_B,
281 	FN_ETH_TXD1, FN_VI0_G7, FN_SCIF2_RXD_C, FN_IIC0_SCL_D, FN_AVB_TXD6,
282 	FN_SSI_WS5_B,
283 	FN_ETH_TX_EN, FN_VI0_R0, FN_SCIF2_TXD_C, FN_IIC0_SDA_D, FN_AVB_TXD7,
284 	FN_SSI_SDATA5_B,
285 	FN_ETH_MAGIC, FN_VI0_R1, FN_SCIF3_SCK_B, FN_AVB_TX_ER, FN_SSI_SCK6_B,
286 	FN_ETH_TXD0, FN_VI0_R2, FN_SCIF3_RXD_B, FN_I2C4_SCL_E, FN_AVB_GTX_CLK,
287 	FN_SSI_WS6_B,
288 	FN_DREQ0_N, FN_SCIFB1_RXD,
289 
290 	/* IPSR8 */
291 	FN_ETH_MDC, FN_VI0_R3, FN_SCIF3_TXD_B, FN_I2C4_SDA_E, FN_AVB_MDC,
292 	FN_SSI_SDATA6_B,
293 	FN_HSCIF0_HRX, FN_VI0_R4, FN_I2C1_SCL_C, FN_AUDIO_CLKA_B, FN_AVB_MDIO,
294 	FN_SSI_SCK78_B,
295 	FN_HSCIF0_HTX, FN_VI0_R5, FN_I2C1_SDA_C, FN_AUDIO_CLKB_B, FN_AVB_LINK,
296 	FN_SSI_WS78_B,
297 	FN_HSCIF0_HCTS_N, FN_VI0_R6, FN_SCIF0_RXD_D, FN_I2C0_SCL_E,
298 	FN_AVB_MAGIC, FN_SSI_SDATA7_B,
299 	FN_HSCIF0_HRTS_N, FN_VI0_R7, FN_SCIF0_TXD_D, FN_I2C0_SDA_E,
300 	FN_AVB_PHY_INT, FN_SSI_SDATA8_B,
301 	FN_HSCIF0_HSCK, FN_SCIF_CLK_B, FN_AVB_CRS, FN_AUDIO_CLKC_B,
302 	FN_I2C0_SCL, FN_SCIF0_RXD_C, FN_PWM5, FN_TCLK1_B, FN_AVB_GTXREFCLK,
303 	FN_CAN1_RX_D, FN_TPUTO0_B,
304 	FN_I2C0_SDA, FN_SCIF0_TXD_C, FN_TPUTO0, FN_CAN_CLK, FN_DVC_MUTE,
305 	FN_CAN1_TX_D,
306 	FN_I2C1_SCL, FN_SCIF4_RXD, FN_PWM5_B, FN_DU1_DR0, FN_TS_SDATA_D,
307 	FN_TPUTO1_B,
308 	FN_I2C1_SDA, FN_SCIF4_TXD, FN_IRQ5, FN_DU1_DR1, FN_TS_SCK_D,
309 	FN_BPFCLK_C,
310 	FN_MSIOF0_RXD, FN_SCIF5_RXD, FN_I2C2_SCL_C, FN_DU1_DR2, FN_TS_SDEN_D,
311 	FN_FMCLK_C,
312 
313 	/* IPSR9 */
314 	FN_MSIOF0_TXD, FN_SCIF5_TXD, FN_I2C2_SDA_C, FN_DU1_DR3, FN_TS_SPSYNC_D,
315 	FN_FMIN_C,
316 	FN_MSIOF0_SCK, FN_IRQ0, FN_TS_SDATA, FN_DU1_DR4, FN_TPUTO1_C,
317 	FN_MSIOF0_SYNC, FN_PWM1, FN_TS_SCK, FN_DU1_DR5, FN_BPFCLK_B,
318 	FN_MSIOF0_SS1, FN_SCIFA0_RXD, FN_TS_SDEN, FN_DU1_DR6, FN_FMCLK_B,
319 	FN_MSIOF0_SS2, FN_SCIFA0_TXD, FN_TS_SPSYNC, FN_DU1_DR7, FN_FMIN_B,
320 	FN_HSCIF1_HRX, FN_I2C4_SCL, FN_PWM6, FN_DU1_DG0,
321 	FN_HSCIF1_HTX, FN_I2C4_SDA, FN_TPUTO1, FN_DU1_DG1,
322 	FN_HSCIF1_HSCK, FN_PWM2, FN_IETX, FN_DU1_DG2, FN_REMOCON_B,
323 	FN_SPEEDIN_B,
324 	FN_HSCIF1_HCTS_N, FN_SCIFA4_RXD, FN_IECLK, FN_DU1_DG3, FN_SSI_SCK1_B,
325 	FN_HSCIF1_HRTS_N, FN_SCIFA4_TXD, FN_IERX, FN_DU1_DG4, FN_SSI_WS1_B,
326 	FN_SCIF1_SCK, FN_PWM3, FN_TCLK2, FN_DU1_DG5, FN_SSI_SDATA1_B,
327 
328 	/* IPSR10 */
329 	FN_SCIF1_RXD, FN_I2C5_SCL, FN_DU1_DG6, FN_SSI_SCK2_B,
330 	FN_SCIF1_TXD, FN_I2C5_SDA, FN_DU1_DG7, FN_SSI_WS2_B,
331 	FN_SCIF2_RXD, FN_IIC0_SCL, FN_DU1_DB0, FN_SSI_SDATA2_B,
332 	FN_SCIF2_TXD, FN_IIC0_SDA, FN_DU1_DB1, FN_SSI_SCK9_B,
333 	FN_SCIF2_SCK, FN_IRQ1, FN_DU1_DB2, FN_SSI_WS9_B,
334 	FN_SCIF3_SCK, FN_IRQ2, FN_BPFCLK_D, FN_DU1_DB3, FN_SSI_SDATA9_B,
335 	FN_SCIF3_RXD, FN_I2C1_SCL_E, FN_FMCLK_D, FN_DU1_DB4, FN_AUDIO_CLKA_C,
336 	FN_SSI_SCK4_B,
337 	FN_SCIF3_TXD, FN_I2C1_SDA_E, FN_FMIN_D, FN_DU1_DB5, FN_AUDIO_CLKB_C,
338 	FN_SSI_WS4_B,
339 	FN_I2C2_SCL, FN_SCIFA5_RXD, FN_DU1_DB6, FN_AUDIO_CLKC_C,
340 	FN_SSI_SDATA4_B,
341 	FN_I2C2_SDA, FN_SCIFA5_TXD, FN_DU1_DB7, FN_AUDIO_CLKOUT_C,
342 	FN_SSI_SCK5, FN_SCIFA3_SCK, FN_DU1_DOTCLKIN,
343 
344 	/* IPSR11 */
345 	FN_SSI_WS5, FN_SCIFA3_RXD, FN_I2C3_SCL_C, FN_DU1_DOTCLKOUT0,
346 	FN_SSI_SDATA5, FN_SCIFA3_TXD, FN_I2C3_SDA_C, FN_DU1_DOTCLKOUT1,
347 	FN_SSI_SCK6, FN_SCIFA1_SCK_B, FN_DU1_EXHSYNC_DU1_HSYNC,
348 	FN_SSI_WS6, FN_SCIFA1_RXD_B, FN_I2C4_SCL_C, FN_DU1_EXVSYNC_DU1_VSYNC,
349 	FN_SSI_SDATA6, FN_SCIFA1_TXD_B, FN_I2C4_SDA_C,
350 	FN_DU1_EXODDF_DU1_ODDF_DISP_CDE,
351 	FN_SSI_SCK78, FN_SCIFA2_SCK_B, FN_I2C5_SDA_C, FN_DU1_DISP,
352 	FN_SSI_WS78, FN_SCIFA2_RXD_B, FN_I2C5_SCL_C, FN_DU1_CDE,
353 	FN_SSI_SDATA7, FN_SCIFA2_TXD_B, FN_IRQ8, FN_AUDIO_CLKA_D, FN_CAN_CLK_D,
354 	FN_SSI_SCK0129, FN_MSIOF1_RXD_B, FN_SCIF5_RXD_D, FN_ADIDATA_B,
355 	FN_SSI_WS0129, FN_MSIOF1_TXD_B, FN_SCIF5_TXD_D, FN_ADICS_SAMP_B,
356 	FN_SSI_SDATA0, FN_MSIOF1_SCK_B, FN_PWM0_B, FN_ADICLK_B,
357 
358 	/* IPSR12 */
359 	FN_SSI_SCK34, FN_MSIOF1_SYNC_B, FN_SCIFA1_SCK_C, FN_ADICHS0_B,
360 	FN_DREQ1_N_B,
361 	FN_SSI_WS34, FN_MSIOF1_SS1_B, FN_SCIFA1_RXD_C, FN_ADICHS1_B,
362 	FN_CAN1_RX_C, FN_DACK1_B,
363 	FN_SSI_SDATA3, FN_MSIOF1_SS2_B, FN_SCIFA1_TXD_C, FN_ADICHS2_B,
364 	FN_CAN1_TX_C, FN_DREQ2_N,
365 	FN_SSI_SCK4, FN_MLB_CLK, FN_IETX_B, FN_SSI_WS4, FN_MLB_SIG, FN_IECLK_B,
366 	FN_SSI_SDATA4, FN_MLB_DAT, FN_IERX_B,
367 	FN_SSI_SDATA8, FN_SCIF1_SCK_B, FN_PWM1_B, FN_IRQ9, FN_REMOCON,
368 	FN_DACK2, FN_ETH_MDIO_B,
369 	FN_SSI_SCK1, FN_SCIF1_RXD_B, FN_IIC0_SCL_C, FN_VI1_CLK, FN_CAN0_RX_D,
370 	FN_ETH_CRS_DV_B,
371 	FN_SSI_WS1, FN_SCIF1_TXD_B, FN_IIC0_SDA_C, FN_VI1_DATA0, FN_CAN0_TX_D,
372 	FN_ETH_RX_ER_B,
373 	FN_SSI_SDATA1, FN_HSCIF1_HRX_B, FN_VI1_DATA1, FN_ATAWR0_N,
374 	FN_ETH_RXD0_B,
375 	FN_SSI_SCK2, FN_HSCIF1_HTX_B, FN_VI1_DATA2, FN_ATAG0_N, FN_ETH_RXD1_B,
376 
377 	/* IPSR13 */
378 	FN_SSI_WS2, FN_HSCIF1_HCTS_N_B, FN_SCIFA0_RXD_D, FN_VI1_DATA3,
379 	FN_ATACS00_N, FN_ETH_LINK_B,
380 	FN_SSI_SDATA2, FN_HSCIF1_HRTS_N_B, FN_SCIFA0_TXD_D, FN_VI1_DATA4,
381 	FN_ATACS10_N, FN_ETH_REFCLK_B,
382 	FN_SSI_SCK9, FN_SCIF2_SCK_B, FN_PWM2_B, FN_VI1_DATA5, FN_EX_WAIT1,
383 	FN_ETH_TXD1_B,
384 	FN_SSI_WS9, FN_SCIF2_RXD_B, FN_I2C3_SCL_E, FN_VI1_DATA6, FN_ATARD0_N,
385 	FN_ETH_TX_EN_B,
386 	FN_SSI_SDATA9, FN_SCIF2_TXD_B, FN_I2C3_SDA_E, FN_VI1_DATA7,
387 	FN_ATADIR0_N, FN_ETH_MAGIC_B,
388 	FN_AUDIO_CLKA, FN_I2C0_SCL_B, FN_SCIFA4_RXD_D, FN_VI1_CLKENB,
389 	FN_TS_SDATA_C, FN_ETH_TXD0_B,
390 	FN_AUDIO_CLKB, FN_I2C0_SDA_B, FN_SCIFA4_TXD_D, FN_VI1_FIELD,
391 	FN_TS_SCK_C, FN_BPFCLK_E, FN_ETH_MDC_B,
392 	FN_AUDIO_CLKC, FN_I2C4_SCL_B, FN_SCIFA5_RXD_D, FN_VI1_HSYNC_N,
393 	FN_TS_SDEN_C, FN_FMCLK_E,
394 	FN_AUDIO_CLKOUT, FN_I2C4_SDA_B, FN_SCIFA5_TXD_D, FN_VI1_VSYNC_N,
395 	FN_TS_SPSYNC_C, FN_FMIN_E,
396 
397 	/* MOD_SEL */
398 	FN_SEL_ADG_0, FN_SEL_ADG_1, FN_SEL_ADG_2, FN_SEL_ADG_3,
399 	FN_SEL_CAN_0, FN_SEL_CAN_1, FN_SEL_CAN_2, FN_SEL_CAN_3,
400 	FN_SEL_DARC_0, FN_SEL_DARC_1, FN_SEL_DARC_2, FN_SEL_DARC_3,
401 	FN_SEL_DARC_4,
402 	FN_SEL_ETH_0, FN_SEL_ETH_1,
403 	FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2,	FN_SEL_I2C00_3,
404 	FN_SEL_I2C00_4,
405 	FN_SEL_I2C01_0, FN_SEL_I2C01_1,	FN_SEL_I2C01_2, FN_SEL_I2C01_3,
406 	FN_SEL_I2C01_4,
407 	FN_SEL_I2C02_0, FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3,
408 	FN_SEL_I2C02_4,
409 	FN_SEL_I2C03_0, FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3,
410 	FN_SEL_I2C03_4,
411 	FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2,	FN_SEL_I2C04_3,
412 	FN_SEL_I2C04_4,
413 	FN_SEL_I2C05_0, FN_SEL_I2C05_1,	FN_SEL_I2C05_2, FN_SEL_I2C05_3,
414 
415 	/* MOD_SEL2 */
416 	FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2,
417 	FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, FN_SEL_IIC0_3,
418 	FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_MSI1_0, FN_SEL_MSI1_1,
419 	FN_SEL_MSI2_0, FN_SEL_MSI2_1, FN_SEL_RAD_0, FN_SEL_RAD_1,
420 	FN_SEL_RCN_0, FN_SEL_RCN_1, FN_SEL_RSP_0, FN_SEL_RSP_1,
421 	FN_SEL_SCIFA0_0, FN_SEL_SCIFA0_1, FN_SEL_SCIFA0_2, FN_SEL_SCIFA0_3,
422 	FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2,
423 	FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1,
424 	FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2, FN_SEL_SCIFA4_3,
425 	FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, FN_SEL_SCIFA5_3,
426 	FN_SEL_TMU_0, FN_SEL_TMU_1,
427 	FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
428 	FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
429 	FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
430 	FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
431 
432 	/* MOD_SEL3 */
433 	FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
434 	FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF2_0,
435 	FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF3_0, FN_SEL_SCIF3_1,
436 	FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
437 	FN_SEL_SCIF4_4, FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2,
438 	FN_SEL_SCIF5_3, FN_SEL_SSI1_0, FN_SEL_SSI1_1, FN_SEL_SSI2_0,
439 	FN_SEL_SSI2_1, FN_SEL_SSI4_0, FN_SEL_SSI4_1, FN_SEL_SSI5_0,
440 	FN_SEL_SSI5_1, FN_SEL_SSI6_0, FN_SEL_SSI6_1, FN_SEL_SSI7_0,
441 	FN_SEL_SSI7_1, FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI9_0,
442 	FN_SEL_SSI9_1,
443 	PINMUX_FUNCTION_END,
444 
445 	PINMUX_MARK_BEGIN,
446 	A2_MARK, WE0_N_MARK, WE1_N_MARK, DACK0_MARK,
447 
448 	USB0_PWEN_MARK, USB0_OVC_MARK, USB1_PWEN_MARK, USB1_OVC_MARK,
449 
450 	SD0_CLK_MARK, SD0_CMD_MARK, SD0_DATA0_MARK, SD0_DATA1_MARK,
451 	SD0_DATA2_MARK, SD0_DATA3_MARK, SD0_CD_MARK, SD0_WP_MARK,
452 
453 	SD1_CLK_MARK, SD1_CMD_MARK, SD1_DATA0_MARK, SD1_DATA1_MARK,
454 	SD1_DATA2_MARK, SD1_DATA3_MARK,
455 
456 	/* IPSR0 */
457 	SD1_CD_MARK, CAN0_RX_MARK, SD1_WP_MARK, IRQ7_MARK, CAN0_TX_MARK,
458 	MMC_CLK_MARK, SD2_CLK_MARK, MMC_CMD_MARK, SD2_CMD_MARK, MMC_D0_MARK,
459 	SD2_DATA0_MARK, MMC_D1_MARK, SD2_DATA1_MARK, MMC_D2_MARK,
460 	SD2_DATA2_MARK, MMC_D3_MARK, SD2_DATA3_MARK, MMC_D4_MARK, SD2_CD_MARK,
461 	MMC_D5_MARK, SD2_WP_MARK, MMC_D6_MARK, SCIF0_RXD_MARK, I2C2_SCL_B_MARK,
462 	CAN1_RX_MARK, MMC_D7_MARK, SCIF0_TXD_MARK, I2C2_SDA_B_MARK,
463 	CAN1_TX_MARK, D0_MARK, SCIFA3_SCK_B_MARK, IRQ4_MARK, D1_MARK,
464 	SCIFA3_RXD_B_MARK, D2_MARK, SCIFA3_TXD_B_MARK, D3_MARK, I2C3_SCL_B_MARK,
465 	SCIF5_RXD_B_MARK, D4_MARK, I2C3_SDA_B_MARK, SCIF5_TXD_B_MARK, D5_MARK,
466 	SCIF4_RXD_B_MARK, I2C0_SCL_D_MARK,
467 
468 	/* IPSR1 */
469 	D6_MARK, SCIF4_TXD_B_MARK, I2C0_SDA_D_MARK,
470 	D7_MARK, IRQ3_MARK, TCLK1_MARK, PWM6_B_MARK,
471 	D8_MARK, HSCIF2_HRX_MARK, I2C1_SCL_B_MARK,
472 	D9_MARK, HSCIF2_HTX_MARK, I2C1_SDA_B_MARK,
473 	D10_MARK, HSCIF2_HSCK_MARK, SCIF1_SCK_C_MARK, IRQ6_MARK, PWM5_C_MARK,
474 	D11_MARK, HSCIF2_HCTS_N_MARK, SCIF1_RXD_C_MARK, I2C1_SCL_D_MARK,
475 	D12_MARK, HSCIF2_HRTS_N_MARK, SCIF1_TXD_C_MARK, I2C1_SDA_D_MARK,
476 	D13_MARK, SCIFA1_SCK_MARK, PWM2_C_MARK, TCLK2_B_MARK,
477 	D14_MARK, SCIFA1_RXD_MARK, I2C5_SCL_B_MARK,
478 	D15_MARK, SCIFA1_TXD_MARK, I2C5_SDA_B_MARK,
479 	A0_MARK, SCIFB1_SCK_MARK, PWM3_B_MARK,
480 	A1_MARK, SCIFB1_TXD_MARK,
481 	A3_MARK, SCIFB0_SCK_MARK,
482 	A4_MARK, SCIFB0_TXD_MARK,
483 	A5_MARK, SCIFB0_RXD_MARK, PWM4_B_MARK, TPUTO3_C_MARK,
484 	A6_MARK, SCIFB0_CTS_N_MARK, SCIFA4_RXD_B_MARK, TPUTO2_C_MARK,
485 
486 	/* IPSR2 */
487 	A7_MARK, SCIFB0_RTS_N_MARK, SCIFA4_TXD_B_MARK,
488 	A8_MARK, MSIOF1_RXD_MARK, SCIFA0_RXD_B_MARK,
489 	A9_MARK, MSIOF1_TXD_MARK, SCIFA0_TXD_B_MARK,
490 	A10_MARK, MSIOF1_SCK_MARK, IIC0_SCL_B_MARK,
491 	A11_MARK, MSIOF1_SYNC_MARK, IIC0_SDA_B_MARK,
492 	A12_MARK, MSIOF1_SS1_MARK, SCIFA5_RXD_B_MARK,
493 	A13_MARK, MSIOF1_SS2_MARK, SCIFA5_TXD_B_MARK,
494 	A14_MARK, MSIOF2_RXD_MARK, HSCIF0_HRX_B_MARK, DREQ1_N_MARK,
495 	A15_MARK, MSIOF2_TXD_MARK, HSCIF0_HTX_B_MARK, DACK1_MARK,
496 	A16_MARK, MSIOF2_SCK_MARK, HSCIF0_HSCK_B_MARK, SPEEDIN_MARK,
497 	CAN_CLK_C_MARK, TPUTO2_B_MARK,
498 	A17_MARK, MSIOF2_SYNC_MARK, SCIF4_RXD_E_MARK, CAN1_RX_B_MARK,
499 	A18_MARK, MSIOF2_SS1_MARK, SCIF4_TXD_E_MARK, CAN1_TX_B_MARK,
500 	A19_MARK, MSIOF2_SS2_MARK, PWM4_MARK, TPUTO2_MARK,
501 	A20_MARK, SPCLK_MARK,
502 
503 	/* IPSR3 */
504 	A21_MARK, MOSI_IO0_MARK,
505 	A22_MARK, MISO_IO1_MARK, ATADIR1_N_MARK,
506 	A23_MARK, IO2_MARK, ATAWR1_N_MARK,
507 	A24_MARK, IO3_MARK, EX_WAIT2_MARK,
508 	A25_MARK, SSL_MARK, ATARD1_N_MARK,
509 	CS0_N_MARK, VI1_DATA8_MARK,
510 	CS1_N_A26_MARK, VI1_DATA9_MARK,
511 	EX_CS0_N_MARK, VI1_DATA10_MARK,
512 	EX_CS1_N_MARK, TPUTO3_B_MARK, SCIFB2_RXD_MARK, VI1_DATA11_MARK,
513 	EX_CS2_N_MARK, PWM0_MARK, SCIF4_RXD_C_MARK, TS_SDATA_B_MARK,
514 	TPUTO3_MARK, SCIFB2_TXD_MARK,
515 	EX_CS3_N_MARK, SCIFA2_SCK_MARK, SCIF4_TXD_C_MARK, TS_SCK_B_MARK,
516 	BPFCLK_MARK, SCIFB2_SCK_MARK,
517 	EX_CS4_N_MARK, SCIFA2_RXD_MARK, I2C2_SCL_E_MARK, TS_SDEN_B_MARK,
518 	FMCLK_MARK, SCIFB2_CTS_N_MARK,
519 	EX_CS5_N_MARK, SCIFA2_TXD_MARK, I2C2_SDA_E_MARK, TS_SPSYNC_B_MARK,
520 	FMIN_MARK, SCIFB2_RTS_N_MARK,
521 	BS_N_MARK, DRACK0_MARK, PWM1_C_MARK, TPUTO0_C_MARK, ATACS01_N_MARK,
522 	RD_N_MARK, ATACS11_N_MARK,
523 	RD_WR_N_MARK, ATAG1_N_MARK,
524 
525 	/* IPSR4 */
526 	EX_WAIT0_MARK, CAN_CLK_B_MARK, SCIF_CLK_MARK,
527 	DU0_DR0_MARK, LCDOUT16_MARK, SCIF5_RXD_C_MARK, I2C2_SCL_D_MARK,
528 	DU0_DR1_MARK, LCDOUT17_MARK, SCIF5_TXD_C_MARK, I2C2_SDA_D_MARK,
529 	DU0_DR2_MARK, LCDOUT18_MARK,
530 	DU0_DR3_MARK, LCDOUT19_MARK,
531 	DU0_DR4_MARK, LCDOUT20_MARK,
532 	DU0_DR5_MARK, LCDOUT21_MARK,
533 	DU0_DR6_MARK, LCDOUT22_MARK,
534 	DU0_DR7_MARK, LCDOUT23_MARK,
535 	DU0_DG0_MARK, LCDOUT8_MARK, SCIFA0_RXD_C_MARK, I2C3_SCL_D_MARK,
536 	DU0_DG1_MARK, LCDOUT9_MARK, SCIFA0_TXD_C_MARK, I2C3_SDA_D_MARK,
537 	DU0_DG2_MARK, LCDOUT10_MARK,
538 	DU0_DG3_MARK, LCDOUT11_MARK,
539 	DU0_DG4_MARK, LCDOUT12_MARK,
540 
541 	/* IPSR5 */
542 	DU0_DG5_MARK, LCDOUT13_MARK,
543 	DU0_DG6_MARK, LCDOUT14_MARK,
544 	DU0_DG7_MARK, LCDOUT15_MARK,
545 	DU0_DB0_MARK, LCDOUT0_MARK, SCIFA4_RXD_C_MARK, I2C4_SCL_D_MARK,
546 	CAN0_RX_C_MARK,
547 	DU0_DB1_MARK, LCDOUT1_MARK, SCIFA4_TXD_C_MARK, I2C4_SDA_D_MARK,
548 	CAN0_TX_C_MARK,
549 	DU0_DB2_MARK, LCDOUT2_MARK,
550 	DU0_DB3_MARK, LCDOUT3_MARK,
551 	DU0_DB4_MARK, LCDOUT4_MARK,
552 	DU0_DB5_MARK, LCDOUT5_MARK,
553 	DU0_DB6_MARK, LCDOUT6_MARK,
554 	DU0_DB7_MARK, LCDOUT7_MARK,
555 	DU0_DOTCLKIN_MARK, QSTVA_QVS_MARK,
556 	DU0_DOTCLKOUT0_MARK, QCLK_MARK,
557 	DU0_DOTCLKOUT1_MARK, QSTVB_QVE_MARK,
558 	DU0_EXHSYNC_DU0_HSYNC_MARK, QSTH_QHS_MARK,
559 
560 	/* IPSR6 */
561 	DU0_EXVSYNC_DU0_VSYNC_MARK, QSTB_QHE_MARK,
562 	DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK,
563 	DU0_DISP_MARK, QPOLA_MARK, DU0_CDE_MARK, QPOLB_MARK,
564 	VI0_CLK_MARK, AVB_RX_CLK_MARK, VI0_DATA0_VI0_B0_MARK, AVB_RX_DV_MARK,
565 	VI0_DATA1_VI0_B1_MARK, AVB_RXD0_MARK,
566 	VI0_DATA2_VI0_B2_MARK, AVB_RXD1_MARK,
567 	VI0_DATA3_VI0_B3_MARK, AVB_RXD2_MARK,
568 	VI0_DATA4_VI0_B4_MARK, AVB_RXD3_MARK,
569 	VI0_DATA5_VI0_B5_MARK, AVB_RXD4_MARK,
570 	VI0_DATA6_VI0_B6_MARK, AVB_RXD5_MARK,
571 	VI0_DATA7_VI0_B7_MARK, AVB_RXD6_MARK,
572 	VI0_CLKENB_MARK, I2C3_SCL_MARK, SCIFA5_RXD_C_MARK, IETX_C_MARK,
573 	AVB_RXD7_MARK,
574 	VI0_FIELD_MARK, I2C3_SDA_MARK, SCIFA5_TXD_C_MARK, IECLK_C_MARK,
575 	AVB_RX_ER_MARK,
576 	VI0_HSYNC_N_MARK, SCIF0_RXD_B_MARK, I2C0_SCL_C_MARK, IERX_C_MARK,
577 	AVB_COL_MARK,
578 	VI0_VSYNC_N_MARK, SCIF0_TXD_B_MARK, I2C0_SDA_C_MARK,
579 	AUDIO_CLKOUT_B_MARK, AVB_TX_EN_MARK,
580 	ETH_MDIO_MARK, VI0_G0_MARK, MSIOF2_RXD_B_MARK, I2C5_SCL_D_MARK,
581 	AVB_TX_CLK_MARK, ADIDATA_MARK,
582 
583 	/* IPSR7 */
584 	ETH_CRS_DV_MARK, VI0_G1_MARK, MSIOF2_TXD_B_MARK, I2C5_SDA_D_MARK,
585 	AVB_TXD0_MARK, ADICS_SAMP_MARK,
586 	ETH_RX_ER_MARK, VI0_G2_MARK, MSIOF2_SCK_B_MARK, CAN0_RX_B_MARK,
587 	AVB_TXD1_MARK, ADICLK_MARK,
588 	ETH_RXD0_MARK, VI0_G3_MARK, MSIOF2_SYNC_B_MARK, CAN0_TX_B_MARK,
589 	AVB_TXD2_MARK, ADICHS0_MARK,
590 	ETH_RXD1_MARK, VI0_G4_MARK, MSIOF2_SS1_B_MARK, SCIF4_RXD_D_MARK,
591 	AVB_TXD3_MARK, ADICHS1_MARK,
592 	ETH_LINK_MARK, VI0_G5_MARK, MSIOF2_SS2_B_MARK, SCIF4_TXD_D_MARK,
593 	AVB_TXD4_MARK, ADICHS2_MARK,
594 	ETH_REFCLK_MARK, VI0_G6_MARK, SCIF2_SCK_C_MARK, AVB_TXD5_MARK,
595 	SSI_SCK5_B_MARK,
596 	ETH_TXD1_MARK, VI0_G7_MARK, SCIF2_RXD_C_MARK, IIC0_SCL_D_MARK,
597 	AVB_TXD6_MARK, SSI_WS5_B_MARK,
598 	ETH_TX_EN_MARK, VI0_R0_MARK, SCIF2_TXD_C_MARK, IIC0_SDA_D_MARK,
599 	AVB_TXD7_MARK, SSI_SDATA5_B_MARK,
600 	ETH_MAGIC_MARK, VI0_R1_MARK, SCIF3_SCK_B_MARK, AVB_TX_ER_MARK,
601 	SSI_SCK6_B_MARK,
602 	ETH_TXD0_MARK, VI0_R2_MARK, SCIF3_RXD_B_MARK, I2C4_SCL_E_MARK,
603 	AVB_GTX_CLK_MARK, SSI_WS6_B_MARK,
604 	DREQ0_N_MARK, SCIFB1_RXD_MARK,
605 
606 	/* IPSR8 */
607 	ETH_MDC_MARK, VI0_R3_MARK, SCIF3_TXD_B_MARK, I2C4_SDA_E_MARK,
608 	AVB_MDC_MARK, SSI_SDATA6_B_MARK, HSCIF0_HRX_MARK, VI0_R4_MARK,
609 	I2C1_SCL_C_MARK, AUDIO_CLKA_B_MARK, AVB_MDIO_MARK, SSI_SCK78_B_MARK,
610 	HSCIF0_HTX_MARK, VI0_R5_MARK, I2C1_SDA_C_MARK, AUDIO_CLKB_B_MARK,
611 	AVB_LINK_MARK, SSI_WS78_B_MARK, HSCIF0_HCTS_N_MARK, VI0_R6_MARK,
612 	SCIF0_RXD_D_MARK, I2C0_SCL_E_MARK, AVB_MAGIC_MARK, SSI_SDATA7_B_MARK,
613 	HSCIF0_HRTS_N_MARK, VI0_R7_MARK, SCIF0_TXD_D_MARK, I2C0_SDA_E_MARK,
614 	AVB_PHY_INT_MARK, SSI_SDATA8_B_MARK,
615 	HSCIF0_HSCK_MARK, SCIF_CLK_B_MARK, AVB_CRS_MARK, AUDIO_CLKC_B_MARK,
616 	I2C0_SCL_MARK, SCIF0_RXD_C_MARK, PWM5_MARK, TCLK1_B_MARK,
617 	AVB_GTXREFCLK_MARK, CAN1_RX_D_MARK, TPUTO0_B_MARK, I2C0_SDA_MARK,
618 	SCIF0_TXD_C_MARK, TPUTO0_MARK, CAN_CLK_MARK, DVC_MUTE_MARK,
619 	CAN1_TX_D_MARK,
620 	I2C1_SCL_MARK, SCIF4_RXD_MARK, PWM5_B_MARK, DU1_DR0_MARK,
621 	TS_SDATA_D_MARK, TPUTO1_B_MARK,
622 	I2C1_SDA_MARK, SCIF4_TXD_MARK, IRQ5_MARK, DU1_DR1_MARK,	TS_SCK_D_MARK,
623 	BPFCLK_C_MARK,
624 	MSIOF0_RXD_MARK, SCIF5_RXD_MARK, I2C2_SCL_C_MARK, DU1_DR2_MARK,
625 	TS_SDEN_D_MARK, FMCLK_C_MARK,
626 
627 	/* IPSR9 */
628 	MSIOF0_TXD_MARK, SCIF5_TXD_MARK, I2C2_SDA_C_MARK, DU1_DR3_MARK,
629 	TS_SPSYNC_D_MARK, FMIN_C_MARK,
630 	MSIOF0_SCK_MARK, IRQ0_MARK, TS_SDATA_MARK, DU1_DR4_MARK, TPUTO1_C_MARK,
631 	MSIOF0_SYNC_MARK, PWM1_MARK, TS_SCK_MARK, DU1_DR5_MARK, BPFCLK_B_MARK,
632 	MSIOF0_SS1_MARK, SCIFA0_RXD_MARK, TS_SDEN_MARK, DU1_DR6_MARK,
633 	FMCLK_B_MARK,
634 	MSIOF0_SS2_MARK, SCIFA0_TXD_MARK, TS_SPSYNC_MARK, DU1_DR7_MARK,
635 	FMIN_B_MARK,
636 	HSCIF1_HRX_MARK, I2C4_SCL_MARK, PWM6_MARK, DU1_DG0_MARK,
637 	HSCIF1_HTX_MARK, I2C4_SDA_MARK, TPUTO1_MARK, DU1_DG1_MARK,
638 	HSCIF1_HSCK_MARK, PWM2_MARK, IETX_MARK, DU1_DG2_MARK, REMOCON_B_MARK,
639 	SPEEDIN_B_MARK,
640 	HSCIF1_HCTS_N_MARK, SCIFA4_RXD_MARK, IECLK_MARK, DU1_DG3_MARK,
641 	SSI_SCK1_B_MARK,
642 	HSCIF1_HRTS_N_MARK, SCIFA4_TXD_MARK, IERX_MARK, DU1_DG4_MARK,
643 	SSI_WS1_B_MARK,
644 	SCIF1_SCK_MARK, PWM3_MARK, TCLK2_MARK, DU1_DG5_MARK, SSI_SDATA1_B_MARK,
645 	CAN_TXCLK_MARK,
646 
647 	/* IPSR10 */
648 	SCIF1_RXD_MARK, I2C5_SCL_MARK, DU1_DG6_MARK, SSI_SCK2_B_MARK,
649 	SCIF1_TXD_MARK, I2C5_SDA_MARK, DU1_DG7_MARK, SSI_WS2_B_MARK,
650 	SCIF2_RXD_MARK, IIC0_SCL_MARK, DU1_DB0_MARK, SSI_SDATA2_B_MARK,
651 	SCIF2_TXD_MARK, IIC0_SDA_MARK, DU1_DB1_MARK, SSI_SCK9_B_MARK,
652 	SCIF2_SCK_MARK, IRQ1_MARK, DU1_DB2_MARK, SSI_WS9_B_MARK,
653 	SCIF3_SCK_MARK, IRQ2_MARK, BPFCLK_D_MARK, DU1_DB3_MARK,
654 	SSI_SDATA9_B_MARK,
655 	SCIF3_RXD_MARK, I2C1_SCL_E_MARK, FMCLK_D_MARK, DU1_DB4_MARK,
656 	AUDIO_CLKA_C_MARK, SSI_SCK4_B_MARK,
657 	SCIF3_TXD_MARK, I2C1_SDA_E_MARK, FMIN_D_MARK, DU1_DB5_MARK,
658 	AUDIO_CLKB_C_MARK, SSI_WS4_B_MARK,
659 	I2C2_SCL_MARK, SCIFA5_RXD_MARK, DU1_DB6_MARK, AUDIO_CLKC_C_MARK,
660 	SSI_SDATA4_B_MARK,
661 	I2C2_SDA_MARK, SCIFA5_TXD_MARK, DU1_DB7_MARK, AUDIO_CLKOUT_C_MARK,
662 	SSI_SCK5_MARK, SCIFA3_SCK_MARK, DU1_DOTCLKIN_MARK,
663 
664 	/* IPSR11 */
665 	SSI_WS5_MARK, SCIFA3_RXD_MARK, I2C3_SCL_C_MARK, DU1_DOTCLKOUT0_MARK,
666 	SSI_SDATA5_MARK, SCIFA3_TXD_MARK, I2C3_SDA_C_MARK, DU1_DOTCLKOUT1_MARK,
667 	SSI_SCK6_MARK, SCIFA1_SCK_B_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK,
668 	SSI_WS6_MARK, SCIFA1_RXD_B_MARK, I2C4_SCL_C_MARK,
669 	DU1_EXVSYNC_DU1_VSYNC_MARK,
670 	SSI_SDATA6_MARK, SCIFA1_TXD_B_MARK, I2C4_SDA_C_MARK,
671 	DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
672 	SSI_SCK78_MARK, SCIFA2_SCK_B_MARK, I2C5_SDA_C_MARK, DU1_DISP_MARK,
673 	SSI_WS78_MARK, SCIFA2_RXD_B_MARK, I2C5_SCL_C_MARK, DU1_CDE_MARK,
674 	SSI_SDATA7_MARK, SCIFA2_TXD_B_MARK, IRQ8_MARK, AUDIO_CLKA_D_MARK,
675 	CAN_CLK_D_MARK,
676 	SSI_SCK0129_MARK, MSIOF1_RXD_B_MARK, SCIF5_RXD_D_MARK, ADIDATA_B_MARK,
677 	SSI_WS0129_MARK, MSIOF1_TXD_B_MARK, SCIF5_TXD_D_MARK, ADICS_SAMP_B_MARK,
678 	SSI_SDATA0_MARK, MSIOF1_SCK_B_MARK, PWM0_B_MARK, ADICLK_B_MARK,
679 
680 	/* IPSR12 */
681 	SSI_SCK34_MARK, MSIOF1_SYNC_B_MARK, SCIFA1_SCK_C_MARK, ADICHS0_B_MARK,
682 	DREQ1_N_B_MARK,
683 	SSI_WS34_MARK, MSIOF1_SS1_B_MARK, SCIFA1_RXD_C_MARK, ADICHS1_B_MARK,
684 	CAN1_RX_C_MARK, DACK1_B_MARK,
685 	SSI_SDATA3_MARK, MSIOF1_SS2_B_MARK, SCIFA1_TXD_C_MARK, ADICHS2_B_MARK,
686 	CAN1_TX_C_MARK, DREQ2_N_MARK,
687 	SSI_SCK4_MARK, MLB_CLK_MARK, IETX_B_MARK,
688 	SSI_WS4_MARK, MLB_SIG_MARK, IECLK_B_MARK,
689 	SSI_SDATA4_MARK, MLB_DAT_MARK, IERX_B_MARK,
690 	SSI_SDATA8_MARK, SCIF1_SCK_B_MARK, PWM1_B_MARK, IRQ9_MARK, REMOCON_MARK,
691 	DACK2_MARK, ETH_MDIO_B_MARK,
692 	SSI_SCK1_MARK, SCIF1_RXD_B_MARK, IIC0_SCL_C_MARK, VI1_CLK_MARK,
693 	CAN0_RX_D_MARK, ETH_CRS_DV_B_MARK,
694 	SSI_WS1_MARK, SCIF1_TXD_B_MARK, IIC0_SDA_C_MARK, VI1_DATA0_MARK,
695 	CAN0_TX_D_MARK, ETH_RX_ER_B_MARK,
696 	SSI_SDATA1_MARK, HSCIF1_HRX_B_MARK, VI1_DATA1_MARK, ATAWR0_N_MARK,
697 	ETH_RXD0_B_MARK,
698 	SSI_SCK2_MARK, HSCIF1_HTX_B_MARK, VI1_DATA2_MARK, ATAG0_N_MARK,
699 	ETH_RXD1_B_MARK,
700 
701 	/* IPSR13 */
702 	SSI_WS2_MARK, HSCIF1_HCTS_N_B_MARK, SCIFA0_RXD_D_MARK, VI1_DATA3_MARK,
703 	ATACS00_N_MARK, ETH_LINK_B_MARK,
704 	SSI_SDATA2_MARK, HSCIF1_HRTS_N_B_MARK, SCIFA0_TXD_D_MARK,
705 	VI1_DATA4_MARK, ATACS10_N_MARK, ETH_REFCLK_B_MARK,
706 	SSI_SCK9_MARK, SCIF2_SCK_B_MARK, PWM2_B_MARK, VI1_DATA5_MARK,
707 	EX_WAIT1_MARK, ETH_TXD1_B_MARK,
708 	SSI_WS9_MARK, SCIF2_RXD_B_MARK, I2C3_SCL_E_MARK, VI1_DATA6_MARK,
709 	ATARD0_N_MARK, ETH_TX_EN_B_MARK,
710 	SSI_SDATA9_MARK, SCIF2_TXD_B_MARK, I2C3_SDA_E_MARK, VI1_DATA7_MARK,
711 	ATADIR0_N_MARK, ETH_MAGIC_B_MARK,
712 	AUDIO_CLKA_MARK, I2C0_SCL_B_MARK, SCIFA4_RXD_D_MARK, VI1_CLKENB_MARK,
713 	TS_SDATA_C_MARK, ETH_TXD0_B_MARK,
714 	AUDIO_CLKB_MARK, I2C0_SDA_B_MARK, SCIFA4_TXD_D_MARK, VI1_FIELD_MARK,
715 	TS_SCK_C_MARK, BPFCLK_E_MARK, ETH_MDC_B_MARK,
716 	AUDIO_CLKC_MARK, I2C4_SCL_B_MARK, SCIFA5_RXD_D_MARK, VI1_HSYNC_N_MARK,
717 	TS_SDEN_C_MARK, FMCLK_E_MARK,
718 	AUDIO_CLKOUT_MARK, I2C4_SDA_B_MARK, SCIFA5_TXD_D_MARK, VI1_VSYNC_N_MARK,
719 	TS_SPSYNC_C_MARK, FMIN_E_MARK,
720 	PINMUX_MARK_END,
721 };
722 
723 static const u16 pinmux_data[] = {
724 	PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
725 
726 	PINMUX_SINGLE(A2),
727 	PINMUX_SINGLE(WE0_N),
728 	PINMUX_SINGLE(WE1_N),
729 	PINMUX_SINGLE(DACK0),
730 	PINMUX_SINGLE(USB0_PWEN),
731 	PINMUX_SINGLE(USB0_OVC),
732 	PINMUX_SINGLE(USB1_PWEN),
733 	PINMUX_SINGLE(USB1_OVC),
734 	PINMUX_SINGLE(SD0_CLK),
735 	PINMUX_SINGLE(SD0_CMD),
736 	PINMUX_SINGLE(SD0_DATA0),
737 	PINMUX_SINGLE(SD0_DATA1),
738 	PINMUX_SINGLE(SD0_DATA2),
739 	PINMUX_SINGLE(SD0_DATA3),
740 	PINMUX_SINGLE(SD0_CD),
741 	PINMUX_SINGLE(SD0_WP),
742 	PINMUX_SINGLE(SD1_CLK),
743 	PINMUX_SINGLE(SD1_CMD),
744 	PINMUX_SINGLE(SD1_DATA0),
745 	PINMUX_SINGLE(SD1_DATA1),
746 	PINMUX_SINGLE(SD1_DATA2),
747 	PINMUX_SINGLE(SD1_DATA3),
748 
749 	/* IPSR0 */
750 	PINMUX_IPSR_GPSR(IP0_0, SD1_CD),
751 	PINMUX_IPSR_MSEL(IP0_0, CAN0_RX, SEL_CAN0_0),
752 	PINMUX_IPSR_GPSR(IP0_9_8, SD1_WP),
753 	PINMUX_IPSR_GPSR(IP0_9_8, IRQ7),
754 	PINMUX_IPSR_MSEL(IP0_9_8, CAN0_TX, SEL_CAN0_0),
755 	PINMUX_IPSR_GPSR(IP0_10, MMC_CLK),
756 	PINMUX_IPSR_GPSR(IP0_10, SD2_CLK),
757 	PINMUX_IPSR_GPSR(IP0_11, MMC_CMD),
758 	PINMUX_IPSR_GPSR(IP0_11, SD2_CMD),
759 	PINMUX_IPSR_GPSR(IP0_12, MMC_D0),
760 	PINMUX_IPSR_GPSR(IP0_12, SD2_DATA0),
761 	PINMUX_IPSR_GPSR(IP0_13, MMC_D1),
762 	PINMUX_IPSR_GPSR(IP0_13, SD2_DATA1),
763 	PINMUX_IPSR_GPSR(IP0_14, MMC_D2),
764 	PINMUX_IPSR_GPSR(IP0_14, SD2_DATA2),
765 	PINMUX_IPSR_GPSR(IP0_15, MMC_D3),
766 	PINMUX_IPSR_GPSR(IP0_15, SD2_DATA3),
767 	PINMUX_IPSR_GPSR(IP0_16, MMC_D4),
768 	PINMUX_IPSR_GPSR(IP0_16, SD2_CD),
769 	PINMUX_IPSR_GPSR(IP0_17, MMC_D5),
770 	PINMUX_IPSR_GPSR(IP0_17, SD2_WP),
771 	PINMUX_IPSR_GPSR(IP0_19_18, MMC_D6),
772 	PINMUX_IPSR_MSEL(IP0_19_18, SCIF0_RXD, SEL_SCIF0_0),
773 	PINMUX_IPSR_MSEL(IP0_19_18, I2C2_SCL_B, SEL_I2C02_1),
774 	PINMUX_IPSR_MSEL(IP0_19_18, CAN1_RX, SEL_CAN1_0),
775 	PINMUX_IPSR_GPSR(IP0_21_20, MMC_D7),
776 	PINMUX_IPSR_MSEL(IP0_21_20, SCIF0_TXD, SEL_SCIF0_0),
777 	PINMUX_IPSR_MSEL(IP0_21_20, I2C2_SDA_B, SEL_I2C02_1),
778 	PINMUX_IPSR_MSEL(IP0_21_20, CAN1_TX, SEL_CAN1_0),
779 	PINMUX_IPSR_GPSR(IP0_23_22, D0),
780 	PINMUX_IPSR_MSEL(IP0_23_22, SCIFA3_SCK_B, SEL_SCIFA3_1),
781 	PINMUX_IPSR_GPSR(IP0_23_22, IRQ4),
782 	PINMUX_IPSR_GPSR(IP0_24, D1),
783 	PINMUX_IPSR_MSEL(IP0_24, SCIFA3_RXD_B, SEL_SCIFA3_1),
784 	PINMUX_IPSR_GPSR(IP0_25, D2),
785 	PINMUX_IPSR_MSEL(IP0_25, SCIFA3_TXD_B, SEL_SCIFA3_1),
786 	PINMUX_IPSR_GPSR(IP0_27_26, D3),
787 	PINMUX_IPSR_MSEL(IP0_27_26, I2C3_SCL_B, SEL_I2C03_1),
788 	PINMUX_IPSR_MSEL(IP0_27_26, SCIF5_RXD_B, SEL_SCIF5_1),
789 	PINMUX_IPSR_GPSR(IP0_29_28, D4),
790 	PINMUX_IPSR_MSEL(IP0_29_28, I2C3_SDA_B, SEL_I2C03_1),
791 	PINMUX_IPSR_MSEL(IP0_29_28, SCIF5_TXD_B, SEL_SCIF5_1),
792 	PINMUX_IPSR_GPSR(IP0_31_30, D5),
793 	PINMUX_IPSR_MSEL(IP0_31_30, SCIF4_RXD_B, SEL_SCIF4_1),
794 	PINMUX_IPSR_MSEL(IP0_31_30, I2C0_SCL_D, SEL_I2C00_3),
795 
796 	/* IPSR1 */
797 	PINMUX_IPSR_GPSR(IP1_1_0, D6),
798 	PINMUX_IPSR_MSEL(IP1_1_0, SCIF4_TXD_B, SEL_SCIF4_1),
799 	PINMUX_IPSR_MSEL(IP1_1_0, I2C0_SDA_D, SEL_I2C00_3),
800 	PINMUX_IPSR_GPSR(IP1_3_2, D7),
801 	PINMUX_IPSR_GPSR(IP1_3_2, IRQ3),
802 	PINMUX_IPSR_MSEL(IP1_3_2, TCLK1, SEL_TMU_0),
803 	PINMUX_IPSR_GPSR(IP1_3_2, PWM6_B),
804 	PINMUX_IPSR_GPSR(IP1_5_4, D8),
805 	PINMUX_IPSR_GPSR(IP1_5_4, HSCIF2_HRX),
806 	PINMUX_IPSR_MSEL(IP1_5_4, I2C1_SCL_B, SEL_I2C01_1),
807 	PINMUX_IPSR_GPSR(IP1_7_6, D9),
808 	PINMUX_IPSR_GPSR(IP1_7_6, HSCIF2_HTX),
809 	PINMUX_IPSR_MSEL(IP1_7_6, I2C1_SDA_B, SEL_I2C01_1),
810 	PINMUX_IPSR_GPSR(IP1_10_8, D10),
811 	PINMUX_IPSR_GPSR(IP1_10_8, HSCIF2_HSCK),
812 	PINMUX_IPSR_MSEL(IP1_10_8, SCIF1_SCK_C, SEL_SCIF1_2),
813 	PINMUX_IPSR_GPSR(IP1_10_8, IRQ6),
814 	PINMUX_IPSR_GPSR(IP1_10_8, PWM5_C),
815 	PINMUX_IPSR_GPSR(IP1_12_11, D11),
816 	PINMUX_IPSR_GPSR(IP1_12_11, HSCIF2_HCTS_N),
817 	PINMUX_IPSR_MSEL(IP1_12_11, SCIF1_RXD_C, SEL_SCIF1_2),
818 	PINMUX_IPSR_MSEL(IP1_12_11, I2C1_SCL_D, SEL_I2C01_3),
819 	PINMUX_IPSR_GPSR(IP1_14_13, D12),
820 	PINMUX_IPSR_GPSR(IP1_14_13, HSCIF2_HRTS_N),
821 	PINMUX_IPSR_MSEL(IP1_14_13, SCIF1_TXD_C, SEL_SCIF1_2),
822 	PINMUX_IPSR_MSEL(IP1_14_13, I2C1_SDA_D, SEL_I2C01_3),
823 	PINMUX_IPSR_GPSR(IP1_17_15, D13),
824 	PINMUX_IPSR_MSEL(IP1_17_15, SCIFA1_SCK, SEL_SCIFA1_0),
825 	PINMUX_IPSR_GPSR(IP1_17_15, PWM2_C),
826 	PINMUX_IPSR_MSEL(IP1_17_15, TCLK2_B, SEL_TMU_1),
827 	PINMUX_IPSR_GPSR(IP1_19_18, D14),
828 	PINMUX_IPSR_MSEL(IP1_19_18, SCIFA1_RXD, SEL_SCIFA1_0),
829 	PINMUX_IPSR_MSEL(IP1_19_18, I2C5_SCL_B, SEL_I2C05_1),
830 	PINMUX_IPSR_GPSR(IP1_21_20, D15),
831 	PINMUX_IPSR_MSEL(IP1_21_20, SCIFA1_TXD, SEL_SCIFA1_0),
832 	PINMUX_IPSR_MSEL(IP1_21_20, I2C5_SDA_B, SEL_I2C05_1),
833 	PINMUX_IPSR_GPSR(IP1_23_22, A0),
834 	PINMUX_IPSR_GPSR(IP1_23_22, SCIFB1_SCK),
835 	PINMUX_IPSR_GPSR(IP1_23_22, PWM3_B),
836 	PINMUX_IPSR_GPSR(IP1_24, A1),
837 	PINMUX_IPSR_GPSR(IP1_24, SCIFB1_TXD),
838 	PINMUX_IPSR_GPSR(IP1_26, A3),
839 	PINMUX_IPSR_GPSR(IP1_26, SCIFB0_SCK),
840 	PINMUX_IPSR_GPSR(IP1_27, A4),
841 	PINMUX_IPSR_GPSR(IP1_27, SCIFB0_TXD),
842 	PINMUX_IPSR_GPSR(IP1_29_28, A5),
843 	PINMUX_IPSR_GPSR(IP1_29_28, SCIFB0_RXD),
844 	PINMUX_IPSR_GPSR(IP1_29_28, PWM4_B),
845 	PINMUX_IPSR_GPSR(IP1_29_28, TPUTO3_C),
846 	PINMUX_IPSR_GPSR(IP1_31_30, A6),
847 	PINMUX_IPSR_GPSR(IP1_31_30, SCIFB0_CTS_N),
848 	PINMUX_IPSR_MSEL(IP1_31_30, SCIFA4_RXD_B, SEL_SCIFA4_1),
849 	PINMUX_IPSR_GPSR(IP1_31_30, TPUTO2_C),
850 
851 	/* IPSR2 */
852 	PINMUX_IPSR_GPSR(IP2_1_0, A7),
853 	PINMUX_IPSR_GPSR(IP2_1_0, SCIFB0_RTS_N),
854 	PINMUX_IPSR_MSEL(IP2_1_0, SCIFA4_TXD_B, SEL_SCIFA4_1),
855 	PINMUX_IPSR_GPSR(IP2_3_2, A8),
856 	PINMUX_IPSR_MSEL(IP2_3_2, MSIOF1_RXD, SEL_MSI1_0),
857 	PINMUX_IPSR_MSEL(IP2_3_2, SCIFA0_RXD_B, SEL_SCIFA0_1),
858 	PINMUX_IPSR_GPSR(IP2_5_4, A9),
859 	PINMUX_IPSR_MSEL(IP2_5_4, MSIOF1_TXD, SEL_MSI1_0),
860 	PINMUX_IPSR_MSEL(IP2_5_4, SCIFA0_TXD_B, SEL_SCIFA0_1),
861 	PINMUX_IPSR_GPSR(IP2_7_6, A10),
862 	PINMUX_IPSR_MSEL(IP2_7_6, MSIOF1_SCK, SEL_MSI1_0),
863 	PINMUX_IPSR_MSEL(IP2_7_6, IIC0_SCL_B, SEL_IIC0_1),
864 	PINMUX_IPSR_GPSR(IP2_9_8, A11),
865 	PINMUX_IPSR_MSEL(IP2_9_8, MSIOF1_SYNC, SEL_MSI1_0),
866 	PINMUX_IPSR_MSEL(IP2_9_8, IIC0_SDA_B, SEL_IIC0_1),
867 	PINMUX_IPSR_GPSR(IP2_11_10, A12),
868 	PINMUX_IPSR_MSEL(IP2_11_10, MSIOF1_SS1, SEL_MSI1_0),
869 	PINMUX_IPSR_MSEL(IP2_11_10, SCIFA5_RXD_B, SEL_SCIFA5_1),
870 	PINMUX_IPSR_GPSR(IP2_13_12, A13),
871 	PINMUX_IPSR_MSEL(IP2_13_12, MSIOF1_SS2, SEL_MSI1_0),
872 	PINMUX_IPSR_MSEL(IP2_13_12, SCIFA5_TXD_B, SEL_SCIFA5_1),
873 	PINMUX_IPSR_GPSR(IP2_15_14, A14),
874 	PINMUX_IPSR_MSEL(IP2_15_14, MSIOF2_RXD, SEL_MSI2_0),
875 	PINMUX_IPSR_MSEL(IP2_15_14, HSCIF0_HRX_B, SEL_HSCIF0_1),
876 	PINMUX_IPSR_MSEL(IP2_15_14, DREQ1_N, SEL_LBS_0),
877 	PINMUX_IPSR_GPSR(IP2_17_16, A15),
878 	PINMUX_IPSR_MSEL(IP2_17_16, MSIOF2_TXD, SEL_MSI2_0),
879 	PINMUX_IPSR_MSEL(IP2_17_16, HSCIF0_HTX_B, SEL_HSCIF0_1),
880 	PINMUX_IPSR_MSEL(IP2_17_16, DACK1, SEL_LBS_0),
881 	PINMUX_IPSR_GPSR(IP2_20_18, A16),
882 	PINMUX_IPSR_MSEL(IP2_20_18, MSIOF2_SCK, SEL_MSI2_0),
883 	PINMUX_IPSR_MSEL(IP2_20_18, HSCIF0_HSCK_B, SEL_HSCIF0_1),
884 	PINMUX_IPSR_MSEL(IP2_20_18, SPEEDIN, SEL_RSP_0),
885 	PINMUX_IPSR_MSEL(IP2_20_18, CAN_CLK_C, SEL_CAN_2),
886 	PINMUX_IPSR_GPSR(IP2_20_18, TPUTO2_B),
887 	PINMUX_IPSR_GPSR(IP2_23_21, A17),
888 	PINMUX_IPSR_MSEL(IP2_23_21, MSIOF2_SYNC, SEL_MSI2_0),
889 	PINMUX_IPSR_MSEL(IP2_23_21, SCIF4_RXD_E, SEL_SCIF4_4),
890 	PINMUX_IPSR_MSEL(IP2_23_21, CAN1_RX_B, SEL_CAN1_1),
891 	PINMUX_IPSR_GPSR(IP2_26_24, A18),
892 	PINMUX_IPSR_MSEL(IP2_26_24, MSIOF2_SS1, SEL_MSI2_0),
893 	PINMUX_IPSR_MSEL(IP2_26_24, SCIF4_TXD_E, SEL_SCIF4_4),
894 	PINMUX_IPSR_MSEL(IP2_26_24, CAN1_TX_B, SEL_CAN1_1),
895 	PINMUX_IPSR_GPSR(IP2_29_27, A19),
896 	PINMUX_IPSR_MSEL(IP2_29_27, MSIOF2_SS2, SEL_MSI2_0),
897 	PINMUX_IPSR_GPSR(IP2_29_27, PWM4),
898 	PINMUX_IPSR_GPSR(IP2_29_27, TPUTO2),
899 	PINMUX_IPSR_GPSR(IP2_31_30, A20),
900 	PINMUX_IPSR_GPSR(IP2_31_30, SPCLK),
901 
902 	/* IPSR3 */
903 	PINMUX_IPSR_GPSR(IP3_1_0, A21),
904 	PINMUX_IPSR_GPSR(IP3_1_0, MOSI_IO0),
905 	PINMUX_IPSR_GPSR(IP3_3_2, A22),
906 	PINMUX_IPSR_GPSR(IP3_3_2, MISO_IO1),
907 	PINMUX_IPSR_GPSR(IP3_3_2, ATADIR1_N),
908 	PINMUX_IPSR_GPSR(IP3_5_4, A23),
909 	PINMUX_IPSR_GPSR(IP3_5_4, IO2),
910 	PINMUX_IPSR_GPSR(IP3_5_4, ATAWR1_N),
911 	PINMUX_IPSR_GPSR(IP3_7_6, A24),
912 	PINMUX_IPSR_GPSR(IP3_7_6, IO3),
913 	PINMUX_IPSR_GPSR(IP3_7_6, EX_WAIT2),
914 	PINMUX_IPSR_GPSR(IP3_9_8, A25),
915 	PINMUX_IPSR_GPSR(IP3_9_8, SSL),
916 	PINMUX_IPSR_GPSR(IP3_9_8, ATARD1_N),
917 	PINMUX_IPSR_GPSR(IP3_10, CS0_N),
918 	PINMUX_IPSR_GPSR(IP3_10, VI1_DATA8),
919 	PINMUX_IPSR_GPSR(IP3_11, CS1_N_A26),
920 	PINMUX_IPSR_GPSR(IP3_11, VI1_DATA9),
921 	PINMUX_IPSR_GPSR(IP3_12, EX_CS0_N),
922 	PINMUX_IPSR_GPSR(IP3_12, VI1_DATA10),
923 	PINMUX_IPSR_GPSR(IP3_14_13, EX_CS1_N),
924 	PINMUX_IPSR_GPSR(IP3_14_13, TPUTO3_B),
925 	PINMUX_IPSR_GPSR(IP3_14_13, SCIFB2_RXD),
926 	PINMUX_IPSR_GPSR(IP3_14_13, VI1_DATA11),
927 	PINMUX_IPSR_GPSR(IP3_17_15, EX_CS2_N),
928 	PINMUX_IPSR_GPSR(IP3_17_15, PWM0),
929 	PINMUX_IPSR_MSEL(IP3_17_15, SCIF4_RXD_C, SEL_SCIF4_2),
930 	PINMUX_IPSR_MSEL(IP3_17_15, TS_SDATA_B, SEL_TSIF0_1),
931 	PINMUX_IPSR_GPSR(IP3_17_15, TPUTO3),
932 	PINMUX_IPSR_GPSR(IP3_17_15, SCIFB2_TXD),
933 	PINMUX_IPSR_GPSR(IP3_20_18, EX_CS3_N),
934 	PINMUX_IPSR_MSEL(IP3_20_18, SCIFA2_SCK, SEL_SCIFA2_0),
935 	PINMUX_IPSR_MSEL(IP3_20_18, SCIF4_TXD_C, SEL_SCIF4_2),
936 	PINMUX_IPSR_MSEL(IP3_20_18, TS_SCK_B, SEL_TSIF0_1),
937 	PINMUX_IPSR_MSEL(IP3_20_18, BPFCLK, SEL_DARC_0),
938 	PINMUX_IPSR_GPSR(IP3_20_18, SCIFB2_SCK),
939 	PINMUX_IPSR_GPSR(IP3_23_21, EX_CS4_N),
940 	PINMUX_IPSR_MSEL(IP3_23_21, SCIFA2_RXD, SEL_SCIFA2_0),
941 	PINMUX_IPSR_MSEL(IP3_23_21, I2C2_SCL_E, SEL_I2C02_4),
942 	PINMUX_IPSR_MSEL(IP3_23_21, TS_SDEN_B, SEL_TSIF0_1),
943 	PINMUX_IPSR_MSEL(IP3_23_21, FMCLK, SEL_DARC_0),
944 	PINMUX_IPSR_GPSR(IP3_23_21, SCIFB2_CTS_N),
945 	PINMUX_IPSR_GPSR(IP3_26_24, EX_CS5_N),
946 	PINMUX_IPSR_MSEL(IP3_26_24, SCIFA2_TXD, SEL_SCIFA2_0),
947 	PINMUX_IPSR_MSEL(IP3_26_24, I2C2_SDA_E, SEL_I2C02_4),
948 	PINMUX_IPSR_MSEL(IP3_26_24, TS_SPSYNC_B, SEL_TSIF0_1),
949 	PINMUX_IPSR_MSEL(IP3_26_24, FMIN, SEL_DARC_0),
950 	PINMUX_IPSR_GPSR(IP3_26_24, SCIFB2_RTS_N),
951 	PINMUX_IPSR_GPSR(IP3_29_27, BS_N),
952 	PINMUX_IPSR_GPSR(IP3_29_27, DRACK0),
953 	PINMUX_IPSR_GPSR(IP3_29_27, PWM1_C),
954 	PINMUX_IPSR_GPSR(IP3_29_27, TPUTO0_C),
955 	PINMUX_IPSR_GPSR(IP3_29_27, ATACS01_N),
956 	PINMUX_IPSR_GPSR(IP3_30, RD_N),
957 	PINMUX_IPSR_GPSR(IP3_30, ATACS11_N),
958 	PINMUX_IPSR_GPSR(IP3_31, RD_WR_N),
959 	PINMUX_IPSR_GPSR(IP3_31, ATAG1_N),
960 
961 	/* IPSR4 */
962 	PINMUX_IPSR_GPSR(IP4_1_0, EX_WAIT0),
963 	PINMUX_IPSR_MSEL(IP4_1_0, CAN_CLK_B, SEL_CAN_1),
964 	PINMUX_IPSR_MSEL(IP4_1_0, SCIF_CLK, SEL_SCIF0_0),
965 	PINMUX_IPSR_GPSR(IP4_4_2, DU0_DR0),
966 	PINMUX_IPSR_GPSR(IP4_4_2, LCDOUT16),
967 	PINMUX_IPSR_MSEL(IP4_4_2, SCIF5_RXD_C, SEL_SCIF5_2),
968 	PINMUX_IPSR_MSEL(IP4_4_2, I2C2_SCL_D, SEL_I2C02_3),
969 	PINMUX_IPSR_GPSR(IP4_7_5, DU0_DR1),
970 	PINMUX_IPSR_GPSR(IP4_7_5, LCDOUT17),
971 	PINMUX_IPSR_MSEL(IP4_7_5, SCIF5_TXD_C, SEL_SCIF5_2),
972 	PINMUX_IPSR_MSEL(IP4_7_5, I2C2_SDA_D, SEL_I2C02_3),
973 	PINMUX_IPSR_GPSR(IP4_9_8, DU0_DR2),
974 	PINMUX_IPSR_GPSR(IP4_9_8, LCDOUT18),
975 	PINMUX_IPSR_GPSR(IP4_11_10, DU0_DR3),
976 	PINMUX_IPSR_GPSR(IP4_11_10, LCDOUT19),
977 	PINMUX_IPSR_GPSR(IP4_13_12, DU0_DR4),
978 	PINMUX_IPSR_GPSR(IP4_13_12, LCDOUT20),
979 	PINMUX_IPSR_GPSR(IP4_15_14, DU0_DR5),
980 	PINMUX_IPSR_GPSR(IP4_15_14, LCDOUT21),
981 	PINMUX_IPSR_GPSR(IP4_17_16, DU0_DR6),
982 	PINMUX_IPSR_GPSR(IP4_17_16, LCDOUT22),
983 	PINMUX_IPSR_GPSR(IP4_19_18, DU0_DR7),
984 	PINMUX_IPSR_GPSR(IP4_19_18, LCDOUT23),
985 	PINMUX_IPSR_GPSR(IP4_22_20, DU0_DG0),
986 	PINMUX_IPSR_GPSR(IP4_22_20, LCDOUT8),
987 	PINMUX_IPSR_MSEL(IP4_22_20, SCIFA0_RXD_C, SEL_SCIFA0_2),
988 	PINMUX_IPSR_MSEL(IP4_22_20, I2C3_SCL_D, SEL_I2C03_3),
989 	PINMUX_IPSR_GPSR(IP4_25_23, DU0_DG1),
990 	PINMUX_IPSR_GPSR(IP4_25_23, LCDOUT9),
991 	PINMUX_IPSR_MSEL(IP4_25_23, SCIFA0_TXD_C, SEL_SCIFA0_2),
992 	PINMUX_IPSR_MSEL(IP4_25_23, I2C3_SDA_D, SEL_I2C03_3),
993 	PINMUX_IPSR_GPSR(IP4_27_26, DU0_DG2),
994 	PINMUX_IPSR_GPSR(IP4_27_26, LCDOUT10),
995 	PINMUX_IPSR_GPSR(IP4_29_28, DU0_DG3),
996 	PINMUX_IPSR_GPSR(IP4_29_28, LCDOUT11),
997 	PINMUX_IPSR_GPSR(IP4_31_30, DU0_DG4),
998 	PINMUX_IPSR_GPSR(IP4_31_30, LCDOUT12),
999 
1000 	/* IPSR5 */
1001 	PINMUX_IPSR_GPSR(IP5_1_0, DU0_DG5),
1002 	PINMUX_IPSR_GPSR(IP5_1_0, LCDOUT13),
1003 	PINMUX_IPSR_GPSR(IP5_3_2, DU0_DG6),
1004 	PINMUX_IPSR_GPSR(IP5_3_2, LCDOUT14),
1005 	PINMUX_IPSR_GPSR(IP5_5_4, DU0_DG7),
1006 	PINMUX_IPSR_GPSR(IP5_5_4, LCDOUT15),
1007 	PINMUX_IPSR_GPSR(IP5_8_6, DU0_DB0),
1008 	PINMUX_IPSR_GPSR(IP5_8_6, LCDOUT0),
1009 	PINMUX_IPSR_MSEL(IP5_8_6, SCIFA4_RXD_C, SEL_SCIFA4_2),
1010 	PINMUX_IPSR_MSEL(IP5_8_6, I2C4_SCL_D, SEL_I2C04_3),
1011 	PINMUX_IPSR_MSEL(IP7_8_6, CAN0_RX_C, SEL_CAN0_2),
1012 	PINMUX_IPSR_GPSR(IP5_11_9, DU0_DB1),
1013 	PINMUX_IPSR_GPSR(IP5_11_9, LCDOUT1),
1014 	PINMUX_IPSR_MSEL(IP5_11_9, SCIFA4_TXD_C, SEL_SCIFA4_2),
1015 	PINMUX_IPSR_MSEL(IP5_11_9, I2C4_SDA_D, SEL_I2C04_3),
1016 	PINMUX_IPSR_MSEL(IP5_11_9, CAN0_TX_C, SEL_CAN0_2),
1017 	PINMUX_IPSR_GPSR(IP5_13_12, DU0_DB2),
1018 	PINMUX_IPSR_GPSR(IP5_13_12, LCDOUT2),
1019 	PINMUX_IPSR_GPSR(IP5_15_14, DU0_DB3),
1020 	PINMUX_IPSR_GPSR(IP5_15_14, LCDOUT3),
1021 	PINMUX_IPSR_GPSR(IP5_17_16, DU0_DB4),
1022 	PINMUX_IPSR_GPSR(IP5_17_16, LCDOUT4),
1023 	PINMUX_IPSR_GPSR(IP5_19_18, DU0_DB5),
1024 	PINMUX_IPSR_GPSR(IP5_19_18, LCDOUT5),
1025 	PINMUX_IPSR_GPSR(IP5_21_20, DU0_DB6),
1026 	PINMUX_IPSR_GPSR(IP5_21_20, LCDOUT6),
1027 	PINMUX_IPSR_GPSR(IP5_23_22, DU0_DB7),
1028 	PINMUX_IPSR_GPSR(IP5_23_22, LCDOUT7),
1029 	PINMUX_IPSR_GPSR(IP5_25_24, DU0_DOTCLKIN),
1030 	PINMUX_IPSR_GPSR(IP5_25_24, QSTVA_QVS),
1031 	PINMUX_IPSR_GPSR(IP5_27_26, DU0_DOTCLKOUT0),
1032 	PINMUX_IPSR_GPSR(IP5_27_26, QCLK),
1033 	PINMUX_IPSR_GPSR(IP5_29_28, DU0_DOTCLKOUT1),
1034 	PINMUX_IPSR_GPSR(IP5_29_28, QSTVB_QVE),
1035 	PINMUX_IPSR_GPSR(IP5_31_30, DU0_EXHSYNC_DU0_HSYNC),
1036 	PINMUX_IPSR_GPSR(IP5_31_30, QSTH_QHS),
1037 
1038 	/* IPSR6 */
1039 	PINMUX_IPSR_GPSR(IP6_1_0, DU0_EXVSYNC_DU0_VSYNC),
1040 	PINMUX_IPSR_GPSR(IP6_1_0, QSTB_QHE),
1041 	PINMUX_IPSR_GPSR(IP6_3_2, DU0_EXODDF_DU0_ODDF_DISP_CDE),
1042 	PINMUX_IPSR_GPSR(IP6_3_2, QCPV_QDE),
1043 	PINMUX_IPSR_GPSR(IP6_5_4, DU0_DISP),
1044 	PINMUX_IPSR_GPSR(IP6_5_4, QPOLA),
1045 	PINMUX_IPSR_GPSR(IP6_7_6, DU0_CDE),
1046 	PINMUX_IPSR_GPSR(IP6_7_6, QPOLB),
1047 	PINMUX_IPSR_GPSR(IP6_8, VI0_CLK),
1048 	PINMUX_IPSR_GPSR(IP6_8, AVB_RX_CLK),
1049 	PINMUX_IPSR_GPSR(IP6_9, VI0_DATA0_VI0_B0),
1050 	PINMUX_IPSR_GPSR(IP6_9, AVB_RX_DV),
1051 	PINMUX_IPSR_GPSR(IP6_10, VI0_DATA1_VI0_B1),
1052 	PINMUX_IPSR_GPSR(IP6_10, AVB_RXD0),
1053 	PINMUX_IPSR_GPSR(IP6_11, VI0_DATA2_VI0_B2),
1054 	PINMUX_IPSR_GPSR(IP6_11, AVB_RXD1),
1055 	PINMUX_IPSR_GPSR(IP6_12, VI0_DATA3_VI0_B3),
1056 	PINMUX_IPSR_GPSR(IP6_12, AVB_RXD2),
1057 	PINMUX_IPSR_GPSR(IP6_13, VI0_DATA4_VI0_B4),
1058 	PINMUX_IPSR_GPSR(IP6_13, AVB_RXD3),
1059 	PINMUX_IPSR_GPSR(IP6_14, VI0_DATA5_VI0_B5),
1060 	PINMUX_IPSR_GPSR(IP6_14, AVB_RXD4),
1061 	PINMUX_IPSR_GPSR(IP6_15, VI0_DATA6_VI0_B6),
1062 	PINMUX_IPSR_GPSR(IP6_15, AVB_RXD5),
1063 	PINMUX_IPSR_GPSR(IP6_16, VI0_DATA7_VI0_B7),
1064 	PINMUX_IPSR_GPSR(IP6_16, AVB_RXD6),
1065 	PINMUX_IPSR_GPSR(IP6_19_17, VI0_CLKENB),
1066 	PINMUX_IPSR_MSEL(IP6_19_17, I2C3_SCL, SEL_I2C03_0),
1067 	PINMUX_IPSR_MSEL(IP6_19_17, SCIFA5_RXD_C, SEL_SCIFA5_2),
1068 	PINMUX_IPSR_MSEL(IP6_19_17, IETX_C, SEL_IEB_2),
1069 	PINMUX_IPSR_GPSR(IP6_19_17, AVB_RXD7),
1070 	PINMUX_IPSR_GPSR(IP6_22_20, VI0_FIELD),
1071 	PINMUX_IPSR_MSEL(IP6_22_20, I2C3_SDA, SEL_I2C03_0),
1072 	PINMUX_IPSR_MSEL(IP6_22_20, SCIFA5_TXD_C, SEL_SCIFA5_2),
1073 	PINMUX_IPSR_MSEL(IP6_22_20, IECLK_C, SEL_IEB_2),
1074 	PINMUX_IPSR_GPSR(IP6_22_20, AVB_RX_ER),
1075 	PINMUX_IPSR_GPSR(IP6_25_23, VI0_HSYNC_N),
1076 	PINMUX_IPSR_MSEL(IP6_25_23, SCIF0_RXD_B, SEL_SCIF0_1),
1077 	PINMUX_IPSR_MSEL(IP6_25_23, I2C0_SCL_C, SEL_I2C00_2),
1078 	PINMUX_IPSR_MSEL(IP6_25_23, IERX_C, SEL_IEB_2),
1079 	PINMUX_IPSR_GPSR(IP6_25_23, AVB_COL),
1080 	PINMUX_IPSR_GPSR(IP6_28_26, VI0_VSYNC_N),
1081 	PINMUX_IPSR_MSEL(IP6_28_26, SCIF0_TXD_B, SEL_SCIF0_1),
1082 	PINMUX_IPSR_MSEL(IP6_28_26, I2C0_SDA_C, SEL_I2C00_2),
1083 	PINMUX_IPSR_MSEL(IP6_28_26, AUDIO_CLKOUT_B, SEL_ADG_1),
1084 	PINMUX_IPSR_GPSR(IP6_28_26, AVB_TX_EN),
1085 	PINMUX_IPSR_MSEL(IP6_31_29, ETH_MDIO, SEL_ETH_0),
1086 	PINMUX_IPSR_GPSR(IP6_31_29, VI0_G0),
1087 	PINMUX_IPSR_MSEL(IP6_31_29, MSIOF2_RXD_B, SEL_MSI2_1),
1088 	PINMUX_IPSR_MSEL(IP6_31_29, I2C5_SCL_D, SEL_I2C05_3),
1089 	PINMUX_IPSR_GPSR(IP6_31_29, AVB_TX_CLK),
1090 	PINMUX_IPSR_MSEL(IP6_31_29, ADIDATA, SEL_RAD_0),
1091 
1092 	/* IPSR7 */
1093 	PINMUX_IPSR_MSEL(IP7_2_0, ETH_CRS_DV, SEL_ETH_0),
1094 	PINMUX_IPSR_GPSR(IP7_2_0, VI0_G1),
1095 	PINMUX_IPSR_MSEL(IP7_2_0, MSIOF2_TXD_B, SEL_MSI2_1),
1096 	PINMUX_IPSR_MSEL(IP7_2_0, I2C5_SDA_D, SEL_I2C05_3),
1097 	PINMUX_IPSR_GPSR(IP7_2_0, AVB_TXD0),
1098 	PINMUX_IPSR_MSEL(IP7_2_0, ADICS_SAMP, SEL_RAD_0),
1099 	PINMUX_IPSR_MSEL(IP7_5_3, ETH_RX_ER, SEL_ETH_0),
1100 	PINMUX_IPSR_GPSR(IP7_5_3, VI0_G2),
1101 	PINMUX_IPSR_MSEL(IP7_5_3, MSIOF2_SCK_B, SEL_MSI2_1),
1102 	PINMUX_IPSR_MSEL(IP7_5_3, CAN0_RX_B, SEL_CAN0_1),
1103 	PINMUX_IPSR_GPSR(IP7_5_3, AVB_TXD1),
1104 	PINMUX_IPSR_MSEL(IP7_5_3, ADICLK, SEL_RAD_0),
1105 	PINMUX_IPSR_MSEL(IP7_8_6, ETH_RXD0, SEL_ETH_0),
1106 	PINMUX_IPSR_GPSR(IP7_8_6, VI0_G3),
1107 	PINMUX_IPSR_MSEL(IP7_8_6, MSIOF2_SYNC_B, SEL_MSI2_1),
1108 	PINMUX_IPSR_MSEL(IP7_8_6, CAN0_TX_B, SEL_CAN0_1),
1109 	PINMUX_IPSR_GPSR(IP7_8_6, AVB_TXD2),
1110 	PINMUX_IPSR_MSEL(IP7_8_6, ADICHS0, SEL_RAD_0),
1111 	PINMUX_IPSR_MSEL(IP7_11_9, ETH_RXD1, SEL_ETH_0),
1112 	PINMUX_IPSR_GPSR(IP7_11_9, VI0_G4),
1113 	PINMUX_IPSR_MSEL(IP7_11_9, MSIOF2_SS1_B, SEL_MSI2_1),
1114 	PINMUX_IPSR_MSEL(IP7_11_9, SCIF4_RXD_D, SEL_SCIF4_3),
1115 	PINMUX_IPSR_GPSR(IP7_11_9, AVB_TXD3),
1116 	PINMUX_IPSR_MSEL(IP7_11_9, ADICHS1, SEL_RAD_0),
1117 	PINMUX_IPSR_MSEL(IP7_14_12, ETH_LINK, SEL_ETH_0),
1118 	PINMUX_IPSR_GPSR(IP7_14_12, VI0_G5),
1119 	PINMUX_IPSR_MSEL(IP7_14_12, MSIOF2_SS2_B, SEL_MSI2_1),
1120 	PINMUX_IPSR_MSEL(IP7_14_12, SCIF4_TXD_D, SEL_SCIF4_3),
1121 	PINMUX_IPSR_GPSR(IP7_14_12, AVB_TXD4),
1122 	PINMUX_IPSR_MSEL(IP7_14_12, ADICHS2, SEL_RAD_0),
1123 	PINMUX_IPSR_MSEL(IP7_17_15, ETH_REFCLK, SEL_ETH_0),
1124 	PINMUX_IPSR_GPSR(IP7_17_15, VI0_G6),
1125 	PINMUX_IPSR_MSEL(IP7_17_15, SCIF2_SCK_C, SEL_SCIF2_2),
1126 	PINMUX_IPSR_GPSR(IP7_17_15, AVB_TXD5),
1127 	PINMUX_IPSR_MSEL(IP7_17_15, SSI_SCK5_B, SEL_SSI5_1),
1128 	PINMUX_IPSR_MSEL(IP7_20_18, ETH_TXD1, SEL_ETH_0),
1129 	PINMUX_IPSR_GPSR(IP7_20_18, VI0_G7),
1130 	PINMUX_IPSR_MSEL(IP7_20_18, SCIF2_RXD_C, SEL_SCIF2_2),
1131 	PINMUX_IPSR_MSEL(IP7_20_18, IIC0_SCL_D, SEL_IIC0_3),
1132 	PINMUX_IPSR_GPSR(IP7_20_18, AVB_TXD6),
1133 	PINMUX_IPSR_MSEL(IP7_20_18, SSI_WS5_B, SEL_SSI5_1),
1134 	PINMUX_IPSR_MSEL(IP7_23_21, ETH_TX_EN, SEL_ETH_0),
1135 	PINMUX_IPSR_GPSR(IP7_23_21, VI0_R0),
1136 	PINMUX_IPSR_MSEL(IP7_23_21, SCIF2_TXD_C, SEL_SCIF2_2),
1137 	PINMUX_IPSR_MSEL(IP7_23_21, IIC0_SDA_D, SEL_IIC0_3),
1138 	PINMUX_IPSR_GPSR(IP7_23_21, AVB_TXD7),
1139 	PINMUX_IPSR_MSEL(IP7_23_21, SSI_SDATA5_B, SEL_SSI5_1),
1140 	PINMUX_IPSR_MSEL(IP7_26_24, ETH_MAGIC, SEL_ETH_0),
1141 	PINMUX_IPSR_GPSR(IP7_26_24, VI0_R1),
1142 	PINMUX_IPSR_MSEL(IP7_26_24, SCIF3_SCK_B, SEL_SCIF3_1),
1143 	PINMUX_IPSR_GPSR(IP7_26_24, AVB_TX_ER),
1144 	PINMUX_IPSR_MSEL(IP7_26_24, SSI_SCK6_B, SEL_SSI6_1),
1145 	PINMUX_IPSR_MSEL(IP7_29_27, ETH_TXD0, SEL_ETH_0),
1146 	PINMUX_IPSR_GPSR(IP7_29_27, VI0_R2),
1147 	PINMUX_IPSR_MSEL(IP7_29_27, SCIF3_RXD_B, SEL_SCIF3_1),
1148 	PINMUX_IPSR_MSEL(IP7_29_27, I2C4_SCL_E, SEL_I2C04_4),
1149 	PINMUX_IPSR_GPSR(IP7_29_27, AVB_GTX_CLK),
1150 	PINMUX_IPSR_MSEL(IP7_29_27, SSI_WS6_B, SEL_SSI6_1),
1151 	PINMUX_IPSR_GPSR(IP7_31, DREQ0_N),
1152 	PINMUX_IPSR_GPSR(IP7_31, SCIFB1_RXD),
1153 
1154 	/* IPSR8 */
1155 	PINMUX_IPSR_MSEL(IP8_2_0, ETH_MDC, SEL_ETH_0),
1156 	PINMUX_IPSR_GPSR(IP8_2_0, VI0_R3),
1157 	PINMUX_IPSR_MSEL(IP8_2_0, SCIF3_TXD_B, SEL_SCIF3_1),
1158 	PINMUX_IPSR_MSEL(IP8_2_0, I2C4_SDA_E, SEL_I2C04_4),
1159 	PINMUX_IPSR_GPSR(IP8_2_0, AVB_MDC),
1160 	PINMUX_IPSR_MSEL(IP8_2_0, SSI_SDATA6_B, SEL_SSI6_1),
1161 	PINMUX_IPSR_MSEL(IP8_5_3, HSCIF0_HRX, SEL_HSCIF0_0),
1162 	PINMUX_IPSR_GPSR(IP8_5_3, VI0_R4),
1163 	PINMUX_IPSR_MSEL(IP8_5_3, I2C1_SCL_C, SEL_I2C01_2),
1164 	PINMUX_IPSR_MSEL(IP8_5_3, AUDIO_CLKA_B, SEL_ADG_1),
1165 	PINMUX_IPSR_GPSR(IP8_5_3, AVB_MDIO),
1166 	PINMUX_IPSR_MSEL(IP8_5_3, SSI_SCK78_B, SEL_SSI7_1),
1167 	PINMUX_IPSR_MSEL(IP8_8_6, HSCIF0_HTX, SEL_HSCIF0_0),
1168 	PINMUX_IPSR_GPSR(IP8_8_6, VI0_R5),
1169 	PINMUX_IPSR_MSEL(IP8_8_6, I2C1_SDA_C, SEL_I2C01_2),
1170 	PINMUX_IPSR_MSEL(IP8_8_6, AUDIO_CLKB_B, SEL_ADG_1),
1171 	PINMUX_IPSR_GPSR(IP8_5_3, AVB_LINK),
1172 	PINMUX_IPSR_MSEL(IP8_8_6, SSI_WS78_B, SEL_SSI7_1),
1173 	PINMUX_IPSR_GPSR(IP8_11_9, HSCIF0_HCTS_N),
1174 	PINMUX_IPSR_GPSR(IP8_11_9, VI0_R6),
1175 	PINMUX_IPSR_MSEL(IP8_11_9, SCIF0_RXD_D, SEL_SCIF0_3),
1176 	PINMUX_IPSR_MSEL(IP8_11_9, I2C0_SCL_E, SEL_I2C00_4),
1177 	PINMUX_IPSR_GPSR(IP8_11_9, AVB_MAGIC),
1178 	PINMUX_IPSR_MSEL(IP8_11_9, SSI_SDATA7_B, SEL_SSI7_1),
1179 	PINMUX_IPSR_GPSR(IP8_14_12, HSCIF0_HRTS_N),
1180 	PINMUX_IPSR_GPSR(IP8_14_12, VI0_R7),
1181 	PINMUX_IPSR_MSEL(IP8_14_12, SCIF0_TXD_D, SEL_SCIF0_3),
1182 	PINMUX_IPSR_MSEL(IP8_14_12, I2C0_SDA_E, SEL_I2C00_4),
1183 	PINMUX_IPSR_GPSR(IP8_14_12, AVB_PHY_INT),
1184 	PINMUX_IPSR_MSEL(IP8_14_12, SSI_SDATA8_B, SEL_SSI8_1),
1185 	PINMUX_IPSR_MSEL(IP8_16_15, HSCIF0_HSCK, SEL_HSCIF0_0),
1186 	PINMUX_IPSR_MSEL(IP8_16_15, SCIF_CLK_B, SEL_SCIF0_1),
1187 	PINMUX_IPSR_GPSR(IP8_16_15, AVB_CRS),
1188 	PINMUX_IPSR_MSEL(IP8_16_15, AUDIO_CLKC_B, SEL_ADG_1),
1189 	PINMUX_IPSR_MSEL(IP8_19_17, I2C0_SCL, SEL_I2C00_0),
1190 	PINMUX_IPSR_MSEL(IP8_19_17, SCIF0_RXD_C, SEL_SCIF0_2),
1191 	PINMUX_IPSR_GPSR(IP8_19_17, PWM5),
1192 	PINMUX_IPSR_MSEL(IP8_19_17, TCLK1_B, SEL_TMU_1),
1193 	PINMUX_IPSR_GPSR(IP8_19_17, AVB_GTXREFCLK),
1194 	PINMUX_IPSR_MSEL(IP8_19_17, CAN1_RX_D, SEL_CAN1_3),
1195 	PINMUX_IPSR_GPSR(IP8_19_17, TPUTO0_B),
1196 	PINMUX_IPSR_MSEL(IP8_22_20, I2C0_SDA, SEL_I2C00_0),
1197 	PINMUX_IPSR_MSEL(IP8_22_20, SCIF0_TXD_C, SEL_SCIF0_2),
1198 	PINMUX_IPSR_GPSR(IP8_22_20, TPUTO0),
1199 	PINMUX_IPSR_MSEL(IP8_22_20, CAN_CLK, SEL_CAN_0),
1200 	PINMUX_IPSR_GPSR(IP8_22_20, DVC_MUTE),
1201 	PINMUX_IPSR_MSEL(IP8_22_20, CAN1_TX_D, SEL_CAN1_3),
1202 	PINMUX_IPSR_MSEL(IP8_25_23, I2C1_SCL, SEL_I2C01_0),
1203 	PINMUX_IPSR_MSEL(IP8_25_23, SCIF4_RXD, SEL_SCIF4_0),
1204 	PINMUX_IPSR_GPSR(IP8_25_23, PWM5_B),
1205 	PINMUX_IPSR_GPSR(IP8_25_23, DU1_DR0),
1206 	PINMUX_IPSR_MSEL(IP8_25_23, TS_SDATA_D, SEL_TSIF0_3),
1207 	PINMUX_IPSR_GPSR(IP8_25_23, TPUTO1_B),
1208 	PINMUX_IPSR_MSEL(IP8_28_26, I2C1_SDA, SEL_I2C01_0),
1209 	PINMUX_IPSR_MSEL(IP8_28_26, SCIF4_TXD, SEL_SCIF4_0),
1210 	PINMUX_IPSR_GPSR(IP8_28_26, IRQ5),
1211 	PINMUX_IPSR_GPSR(IP8_28_26, DU1_DR1),
1212 	PINMUX_IPSR_MSEL(IP8_28_26, TS_SCK_D, SEL_TSIF0_3),
1213 	PINMUX_IPSR_MSEL(IP8_28_26, BPFCLK_C, SEL_DARC_2),
1214 	PINMUX_IPSR_GPSR(IP8_31_29, MSIOF0_RXD),
1215 	PINMUX_IPSR_MSEL(IP8_31_29, SCIF5_RXD, SEL_SCIF5_0),
1216 	PINMUX_IPSR_MSEL(IP8_31_29, I2C2_SCL_C, SEL_I2C02_2),
1217 	PINMUX_IPSR_GPSR(IP8_31_29, DU1_DR2),
1218 	PINMUX_IPSR_MSEL(IP8_31_29, TS_SDEN_D, SEL_TSIF0_3),
1219 	PINMUX_IPSR_MSEL(IP8_31_29, FMCLK_C, SEL_DARC_2),
1220 
1221 	/* IPSR9 */
1222 	PINMUX_IPSR_GPSR(IP9_2_0, MSIOF0_TXD),
1223 	PINMUX_IPSR_MSEL(IP9_2_0, SCIF5_TXD, SEL_SCIF5_0),
1224 	PINMUX_IPSR_MSEL(IP9_2_0, I2C2_SDA_C, SEL_I2C02_2),
1225 	PINMUX_IPSR_GPSR(IP9_2_0, DU1_DR3),
1226 	PINMUX_IPSR_MSEL(IP9_2_0, TS_SPSYNC_D, SEL_TSIF0_3),
1227 	PINMUX_IPSR_MSEL(IP9_2_0, FMIN_C, SEL_DARC_2),
1228 	PINMUX_IPSR_GPSR(IP9_5_3, MSIOF0_SCK),
1229 	PINMUX_IPSR_GPSR(IP9_5_3, IRQ0),
1230 	PINMUX_IPSR_MSEL(IP9_5_3, TS_SDATA, SEL_TSIF0_0),
1231 	PINMUX_IPSR_GPSR(IP9_5_3, DU1_DR4),
1232 	PINMUX_IPSR_GPSR(IP9_5_3, TPUTO1_C),
1233 	PINMUX_IPSR_GPSR(IP9_8_6, MSIOF0_SYNC),
1234 	PINMUX_IPSR_GPSR(IP9_8_6, PWM1),
1235 	PINMUX_IPSR_MSEL(IP9_8_6, TS_SCK, SEL_TSIF0_0),
1236 	PINMUX_IPSR_GPSR(IP9_8_6, DU1_DR5),
1237 	PINMUX_IPSR_MSEL(IP9_8_6, BPFCLK_B, SEL_DARC_1),
1238 	PINMUX_IPSR_GPSR(IP9_11_9, MSIOF0_SS1),
1239 	PINMUX_IPSR_MSEL(IP9_11_9, SCIFA0_RXD, SEL_SCIFA0_0),
1240 	PINMUX_IPSR_MSEL(IP9_11_9, TS_SDEN, SEL_TSIF0_0),
1241 	PINMUX_IPSR_GPSR(IP9_11_9, DU1_DR6),
1242 	PINMUX_IPSR_MSEL(IP9_11_9, FMCLK_B, SEL_DARC_1),
1243 	PINMUX_IPSR_GPSR(IP9_14_12, MSIOF0_SS2),
1244 	PINMUX_IPSR_MSEL(IP9_14_12, SCIFA0_TXD, SEL_SCIFA0_0),
1245 	PINMUX_IPSR_MSEL(IP9_14_12, TS_SPSYNC, SEL_TSIF0_0),
1246 	PINMUX_IPSR_GPSR(IP9_14_12, DU1_DR7),
1247 	PINMUX_IPSR_MSEL(IP9_14_12, FMIN_B, SEL_DARC_1),
1248 	PINMUX_IPSR_MSEL(IP9_16_15, HSCIF1_HRX, SEL_HSCIF1_0),
1249 	PINMUX_IPSR_MSEL(IP9_16_15, I2C4_SCL, SEL_I2C04_0),
1250 	PINMUX_IPSR_GPSR(IP9_16_15, PWM6),
1251 	PINMUX_IPSR_GPSR(IP9_16_15, DU1_DG0),
1252 	PINMUX_IPSR_MSEL(IP9_18_17, HSCIF1_HTX, SEL_HSCIF1_0),
1253 	PINMUX_IPSR_MSEL(IP9_18_17, I2C4_SDA, SEL_I2C04_0),
1254 	PINMUX_IPSR_GPSR(IP9_18_17, TPUTO1),
1255 	PINMUX_IPSR_GPSR(IP9_18_17, DU1_DG1),
1256 	PINMUX_IPSR_GPSR(IP9_21_19, HSCIF1_HSCK),
1257 	PINMUX_IPSR_GPSR(IP9_21_19, PWM2),
1258 	PINMUX_IPSR_MSEL(IP9_21_19, IETX, SEL_IEB_0),
1259 	PINMUX_IPSR_GPSR(IP9_21_19, DU1_DG2),
1260 	PINMUX_IPSR_MSEL(IP9_21_19, REMOCON_B, SEL_RCN_1),
1261 	PINMUX_IPSR_MSEL(IP9_21_19, SPEEDIN_B, SEL_RSP_1),
1262 	PINMUX_IPSR_MSEL(IP9_24_22, HSCIF1_HCTS_N, SEL_HSCIF1_0),
1263 	PINMUX_IPSR_MSEL(IP9_24_22, SCIFA4_RXD, SEL_SCIFA4_0),
1264 	PINMUX_IPSR_MSEL(IP9_24_22, IECLK, SEL_IEB_0),
1265 	PINMUX_IPSR_GPSR(IP9_24_22, DU1_DG3),
1266 	PINMUX_IPSR_MSEL(IP9_24_22, SSI_SCK1_B, SEL_SSI1_1),
1267 	PINMUX_IPSR_MSEL(IP9_27_25, HSCIF1_HRTS_N, SEL_HSCIF1_0),
1268 	PINMUX_IPSR_MSEL(IP9_27_25, SCIFA4_TXD, SEL_SCIFA4_0),
1269 	PINMUX_IPSR_MSEL(IP9_27_25, IERX, SEL_IEB_0),
1270 	PINMUX_IPSR_GPSR(IP9_27_25, DU1_DG4),
1271 	PINMUX_IPSR_MSEL(IP9_27_25, SSI_WS1_B, SEL_SSI1_1),
1272 	PINMUX_IPSR_MSEL(IP9_30_28, SCIF1_SCK, SEL_SCIF1_0),
1273 	PINMUX_IPSR_GPSR(IP9_30_28, PWM3),
1274 	PINMUX_IPSR_MSEL(IP9_30_28, TCLK2, SEL_TMU_0),
1275 	PINMUX_IPSR_GPSR(IP9_30_28, DU1_DG5),
1276 	PINMUX_IPSR_MSEL(IP9_30_28, SSI_SDATA1_B, SEL_SSI1_1),
1277 
1278 	/* IPSR10 */
1279 	PINMUX_IPSR_MSEL(IP10_2_0, SCIF1_RXD, SEL_SCIF1_0),
1280 	PINMUX_IPSR_MSEL(IP10_2_0, I2C5_SCL, SEL_I2C05_0),
1281 	PINMUX_IPSR_GPSR(IP10_2_0, DU1_DG6),
1282 	PINMUX_IPSR_MSEL(IP10_2_0, SSI_SCK2_B, SEL_SSI2_1),
1283 	PINMUX_IPSR_MSEL(IP10_5_3, SCIF1_TXD, SEL_SCIF1_0),
1284 	PINMUX_IPSR_MSEL(IP10_5_3, I2C5_SDA, SEL_I2C05_0),
1285 	PINMUX_IPSR_GPSR(IP10_5_3, DU1_DG7),
1286 	PINMUX_IPSR_MSEL(IP10_5_3, SSI_WS2_B, SEL_SSI2_1),
1287 	PINMUX_IPSR_MSEL(IP10_8_6, SCIF2_RXD, SEL_SCIF2_0),
1288 	PINMUX_IPSR_MSEL(IP10_8_6, IIC0_SCL, SEL_IIC0_0),
1289 	PINMUX_IPSR_GPSR(IP10_8_6, DU1_DB0),
1290 	PINMUX_IPSR_MSEL(IP10_8_6, SSI_SDATA2_B, SEL_SSI2_1),
1291 	PINMUX_IPSR_MSEL(IP10_11_9, SCIF2_TXD, SEL_SCIF2_0),
1292 	PINMUX_IPSR_MSEL(IP10_11_9, IIC0_SDA, SEL_IIC0_0),
1293 	PINMUX_IPSR_GPSR(IP10_11_9, DU1_DB1),
1294 	PINMUX_IPSR_MSEL(IP10_11_9, SSI_SCK9_B, SEL_SSI9_1),
1295 	PINMUX_IPSR_MSEL(IP10_14_12, SCIF2_SCK, SEL_SCIF2_0),
1296 	PINMUX_IPSR_GPSR(IP10_14_12, IRQ1),
1297 	PINMUX_IPSR_GPSR(IP10_14_12, DU1_DB2),
1298 	PINMUX_IPSR_MSEL(IP10_14_12, SSI_WS9_B, SEL_SSI9_1),
1299 	PINMUX_IPSR_MSEL(IP10_17_15, SCIF3_SCK, SEL_SCIF3_0),
1300 	PINMUX_IPSR_GPSR(IP10_17_15, IRQ2),
1301 	PINMUX_IPSR_MSEL(IP10_17_15, BPFCLK_D, SEL_DARC_3),
1302 	PINMUX_IPSR_GPSR(IP10_17_15, DU1_DB3),
1303 	PINMUX_IPSR_MSEL(IP10_17_15, SSI_SDATA9_B, SEL_SSI9_1),
1304 	PINMUX_IPSR_MSEL(IP10_20_18, SCIF3_RXD, SEL_SCIF3_0),
1305 	PINMUX_IPSR_MSEL(IP10_20_18, I2C1_SCL_E, SEL_I2C01_4),
1306 	PINMUX_IPSR_MSEL(IP10_20_18, FMCLK_D, SEL_DARC_3),
1307 	PINMUX_IPSR_GPSR(IP10_20_18, DU1_DB4),
1308 	PINMUX_IPSR_MSEL(IP10_20_18, AUDIO_CLKA_C, SEL_ADG_2),
1309 	PINMUX_IPSR_MSEL(IP10_20_18, SSI_SCK4_B, SEL_SSI4_1),
1310 	PINMUX_IPSR_MSEL(IP10_23_21, SCIF3_TXD, SEL_SCIF3_0),
1311 	PINMUX_IPSR_MSEL(IP10_23_21, I2C1_SDA_E, SEL_I2C01_4),
1312 	PINMUX_IPSR_MSEL(IP10_23_21, FMIN_D, SEL_DARC_3),
1313 	PINMUX_IPSR_GPSR(IP10_23_21, DU1_DB5),
1314 	PINMUX_IPSR_MSEL(IP10_23_21, AUDIO_CLKB_C, SEL_ADG_2),
1315 	PINMUX_IPSR_MSEL(IP10_23_21, SSI_WS4_B, SEL_SSI4_1),
1316 	PINMUX_IPSR_MSEL(IP10_26_24, I2C2_SCL, SEL_I2C02_0),
1317 	PINMUX_IPSR_MSEL(IP10_26_24, SCIFA5_RXD, SEL_SCIFA5_0),
1318 	PINMUX_IPSR_GPSR(IP10_26_24, DU1_DB6),
1319 	PINMUX_IPSR_MSEL(IP10_26_24, AUDIO_CLKC_C, SEL_ADG_2),
1320 	PINMUX_IPSR_MSEL(IP10_26_24, SSI_SDATA4_B, SEL_SSI4_1),
1321 	PINMUX_IPSR_MSEL(IP10_29_27, I2C2_SDA, SEL_I2C02_0),
1322 	PINMUX_IPSR_MSEL(IP10_29_27, SCIFA5_TXD, SEL_SCIFA5_0),
1323 	PINMUX_IPSR_GPSR(IP10_29_27, DU1_DB7),
1324 	PINMUX_IPSR_MSEL(IP10_29_27, AUDIO_CLKOUT_C, SEL_ADG_2),
1325 	PINMUX_IPSR_MSEL(IP10_31_30, SSI_SCK5, SEL_SSI5_0),
1326 	PINMUX_IPSR_MSEL(IP10_31_30, SCIFA3_SCK, SEL_SCIFA3_0),
1327 	PINMUX_IPSR_GPSR(IP10_31_30, DU1_DOTCLKIN),
1328 
1329 	/* IPSR11 */
1330 	PINMUX_IPSR_MSEL(IP11_2_0, SSI_WS5, SEL_SSI5_0),
1331 	PINMUX_IPSR_MSEL(IP11_2_0, SCIFA3_RXD, SEL_SCIFA3_0),
1332 	PINMUX_IPSR_MSEL(IP11_2_0, I2C3_SCL_C, SEL_I2C03_2),
1333 	PINMUX_IPSR_GPSR(IP11_2_0, DU1_DOTCLKOUT0),
1334 	PINMUX_IPSR_MSEL(IP11_5_3, SSI_SDATA5, SEL_SSI5_0),
1335 	PINMUX_IPSR_MSEL(IP11_5_3, SCIFA3_TXD, SEL_SCIFA3_0),
1336 	PINMUX_IPSR_MSEL(IP11_5_3, I2C3_SDA_C, SEL_I2C03_2),
1337 	PINMUX_IPSR_GPSR(IP11_5_3, DU1_DOTCLKOUT1),
1338 	PINMUX_IPSR_MSEL(IP11_7_6, SSI_SCK6, SEL_SSI6_0),
1339 	PINMUX_IPSR_MSEL(IP11_7_6, SCIFA1_SCK_B, SEL_SCIFA1_1),
1340 	PINMUX_IPSR_GPSR(IP11_7_6, DU1_EXHSYNC_DU1_HSYNC),
1341 	PINMUX_IPSR_MSEL(IP11_10_8, SSI_WS6, SEL_SSI6_0),
1342 	PINMUX_IPSR_MSEL(IP11_10_8, SCIFA1_RXD_B, SEL_SCIFA1_1),
1343 	PINMUX_IPSR_MSEL(IP11_10_8, I2C4_SCL_C, SEL_I2C04_2),
1344 	PINMUX_IPSR_GPSR(IP11_10_8, DU1_EXVSYNC_DU1_VSYNC),
1345 	PINMUX_IPSR_MSEL(IP11_13_11, SSI_SDATA6, SEL_SSI6_0),
1346 	PINMUX_IPSR_MSEL(IP11_13_11, SCIFA1_TXD_B, SEL_SCIFA1_1),
1347 	PINMUX_IPSR_MSEL(IP11_13_11, I2C4_SDA_C, SEL_I2C04_2),
1348 	PINMUX_IPSR_GPSR(IP11_13_11, DU1_EXODDF_DU1_ODDF_DISP_CDE),
1349 	PINMUX_IPSR_MSEL(IP11_15_14, SSI_SCK78, SEL_SSI7_0),
1350 	PINMUX_IPSR_MSEL(IP11_15_14, SCIFA2_SCK_B, SEL_SCIFA2_1),
1351 	PINMUX_IPSR_MSEL(IP11_15_14, I2C5_SDA_C, SEL_I2C05_2),
1352 	PINMUX_IPSR_GPSR(IP11_15_14, DU1_DISP),
1353 	PINMUX_IPSR_MSEL(IP11_17_16, SSI_WS78, SEL_SSI7_0),
1354 	PINMUX_IPSR_MSEL(IP11_17_16, SCIFA2_RXD_B, SEL_SCIFA2_1),
1355 	PINMUX_IPSR_MSEL(IP11_17_16, I2C5_SCL_C, SEL_I2C05_2),
1356 	PINMUX_IPSR_GPSR(IP11_17_16, DU1_CDE),
1357 	PINMUX_IPSR_MSEL(IP11_20_18, SSI_SDATA7, SEL_SSI7_0),
1358 	PINMUX_IPSR_MSEL(IP11_20_18, SCIFA2_TXD_B, SEL_SCIFA2_1),
1359 	PINMUX_IPSR_GPSR(IP11_20_18, IRQ8),
1360 	PINMUX_IPSR_MSEL(IP11_20_18, AUDIO_CLKA_D, SEL_ADG_3),
1361 	PINMUX_IPSR_MSEL(IP11_20_18, CAN_CLK_D, SEL_CAN_3),
1362 	PINMUX_IPSR_GPSR(IP11_23_21, SSI_SCK0129),
1363 	PINMUX_IPSR_MSEL(IP11_23_21, MSIOF1_RXD_B, SEL_MSI1_1),
1364 	PINMUX_IPSR_MSEL(IP11_23_21, SCIF5_RXD_D, SEL_SCIF5_3),
1365 	PINMUX_IPSR_MSEL(IP11_23_21, ADIDATA_B, SEL_RAD_1),
1366 	PINMUX_IPSR_GPSR(IP11_26_24, SSI_WS0129),
1367 	PINMUX_IPSR_MSEL(IP11_26_24, MSIOF1_TXD_B, SEL_MSI1_1),
1368 	PINMUX_IPSR_MSEL(IP11_26_24, SCIF5_TXD_D, SEL_SCIF5_3),
1369 	PINMUX_IPSR_MSEL(IP11_26_24, ADICS_SAMP_B, SEL_RAD_1),
1370 	PINMUX_IPSR_GPSR(IP11_29_27, SSI_SDATA0),
1371 	PINMUX_IPSR_MSEL(IP11_29_27, MSIOF1_SCK_B, SEL_MSI1_1),
1372 	PINMUX_IPSR_GPSR(IP11_29_27, PWM0_B),
1373 	PINMUX_IPSR_MSEL(IP11_29_27, ADICLK_B, SEL_RAD_1),
1374 
1375 	/* IPSR12 */
1376 	PINMUX_IPSR_GPSR(IP12_2_0, SSI_SCK34),
1377 	PINMUX_IPSR_MSEL(IP12_2_0, MSIOF1_SYNC_B, SEL_MSI1_1),
1378 	PINMUX_IPSR_MSEL(IP12_2_0, SCIFA1_SCK_C, SEL_SCIFA1_2),
1379 	PINMUX_IPSR_MSEL(IP12_2_0, ADICHS0_B, SEL_RAD_1),
1380 	PINMUX_IPSR_MSEL(IP12_2_0, DREQ1_N_B, SEL_LBS_1),
1381 	PINMUX_IPSR_GPSR(IP12_5_3, SSI_WS34),
1382 	PINMUX_IPSR_MSEL(IP12_5_3, MSIOF1_SS1_B, SEL_MSI1_1),
1383 	PINMUX_IPSR_MSEL(IP12_5_3, SCIFA1_RXD_C, SEL_SCIFA1_2),
1384 	PINMUX_IPSR_MSEL(IP12_5_3, ADICHS1_B, SEL_RAD_1),
1385 	PINMUX_IPSR_MSEL(IP12_5_3, CAN1_RX_C, SEL_CAN1_2),
1386 	PINMUX_IPSR_MSEL(IP12_5_3, DACK1_B, SEL_LBS_1),
1387 	PINMUX_IPSR_GPSR(IP12_8_6, SSI_SDATA3),
1388 	PINMUX_IPSR_MSEL(IP12_8_6, MSIOF1_SS2_B, SEL_MSI1_1),
1389 	PINMUX_IPSR_MSEL(IP12_8_6, SCIFA1_TXD_C, SEL_SCIFA1_2),
1390 	PINMUX_IPSR_MSEL(IP12_8_6, ADICHS2_B, SEL_RAD_1),
1391 	PINMUX_IPSR_MSEL(IP12_8_6, CAN1_TX_C, SEL_CAN1_2),
1392 	PINMUX_IPSR_GPSR(IP12_8_6, DREQ2_N),
1393 	PINMUX_IPSR_MSEL(IP12_10_9, SSI_SCK4, SEL_SSI4_0),
1394 	PINMUX_IPSR_GPSR(IP12_10_9, MLB_CLK),
1395 	PINMUX_IPSR_MSEL(IP12_10_9, IETX_B, SEL_IEB_1),
1396 	PINMUX_IPSR_MSEL(IP12_12_11, SSI_WS4, SEL_SSI4_0),
1397 	PINMUX_IPSR_GPSR(IP12_12_11, MLB_SIG),
1398 	PINMUX_IPSR_MSEL(IP12_12_11, IECLK_B, SEL_IEB_1),
1399 	PINMUX_IPSR_MSEL(IP12_14_13, SSI_SDATA4, SEL_SSI4_0),
1400 	PINMUX_IPSR_GPSR(IP12_14_13, MLB_DAT),
1401 	PINMUX_IPSR_MSEL(IP12_14_13, IERX_B, SEL_IEB_1),
1402 	PINMUX_IPSR_MSEL(IP12_17_15, SSI_SDATA8, SEL_SSI8_0),
1403 	PINMUX_IPSR_MSEL(IP12_17_15, SCIF1_SCK_B, SEL_SCIF1_1),
1404 	PINMUX_IPSR_GPSR(IP12_17_15, PWM1_B),
1405 	PINMUX_IPSR_GPSR(IP12_17_15, IRQ9),
1406 	PINMUX_IPSR_MSEL(IP12_17_15, REMOCON, SEL_RCN_0),
1407 	PINMUX_IPSR_GPSR(IP12_17_15, DACK2),
1408 	PINMUX_IPSR_MSEL(IP12_17_15, ETH_MDIO_B, SEL_ETH_1),
1409 	PINMUX_IPSR_MSEL(IP12_20_18, SSI_SCK1, SEL_SSI1_0),
1410 	PINMUX_IPSR_MSEL(IP12_20_18, SCIF1_RXD_B, SEL_SCIF1_1),
1411 	PINMUX_IPSR_MSEL(IP12_20_18, IIC0_SCL_C, SEL_IIC0_2),
1412 	PINMUX_IPSR_GPSR(IP12_20_18, VI1_CLK),
1413 	PINMUX_IPSR_MSEL(IP12_20_18, CAN0_RX_D, SEL_CAN0_3),
1414 	PINMUX_IPSR_MSEL(IP12_20_18, ETH_CRS_DV_B, SEL_ETH_1),
1415 	PINMUX_IPSR_MSEL(IP12_23_21, SSI_WS1, SEL_SSI1_0),
1416 	PINMUX_IPSR_MSEL(IP12_23_21, SCIF1_TXD_B, SEL_SCIF1_1),
1417 	PINMUX_IPSR_MSEL(IP12_23_21, IIC0_SDA_C, SEL_IIC0_2),
1418 	PINMUX_IPSR_GPSR(IP12_23_21, VI1_DATA0),
1419 	PINMUX_IPSR_MSEL(IP12_23_21, CAN0_TX_D, SEL_CAN0_3),
1420 	PINMUX_IPSR_MSEL(IP12_23_21, ETH_RX_ER_B, SEL_ETH_1),
1421 	PINMUX_IPSR_MSEL(IP12_26_24, SSI_SDATA1, SEL_SSI1_0),
1422 	PINMUX_IPSR_MSEL(IP12_26_24, HSCIF1_HRX_B, SEL_HSCIF1_1),
1423 	PINMUX_IPSR_GPSR(IP12_26_24, VI1_DATA1),
1424 	PINMUX_IPSR_GPSR(IP12_26_24, ATAWR0_N),
1425 	PINMUX_IPSR_MSEL(IP12_26_24, ETH_RXD0_B, SEL_ETH_1),
1426 	PINMUX_IPSR_MSEL(IP12_29_27, SSI_SCK2, SEL_SSI2_0),
1427 	PINMUX_IPSR_MSEL(IP12_29_27, HSCIF1_HTX_B, SEL_HSCIF1_1),
1428 	PINMUX_IPSR_GPSR(IP12_29_27, VI1_DATA2),
1429 	PINMUX_IPSR_GPSR(IP12_29_27, ATAG0_N),
1430 	PINMUX_IPSR_MSEL(IP12_29_27, ETH_RXD1_B, SEL_ETH_1),
1431 
1432 	/* IPSR13 */
1433 	PINMUX_IPSR_MSEL(IP13_2_0, SSI_WS2, SEL_SSI2_0),
1434 	PINMUX_IPSR_MSEL(IP13_2_0, HSCIF1_HCTS_N_B, SEL_HSCIF1_1),
1435 	PINMUX_IPSR_MSEL(IP13_2_0, SCIFA0_RXD_D, SEL_SCIFA0_3),
1436 	PINMUX_IPSR_GPSR(IP13_2_0, VI1_DATA3),
1437 	PINMUX_IPSR_GPSR(IP13_2_0, ATACS00_N),
1438 	PINMUX_IPSR_MSEL(IP13_2_0, ETH_LINK_B, SEL_ETH_1),
1439 	PINMUX_IPSR_MSEL(IP13_5_3, SSI_SDATA2, SEL_SSI2_0),
1440 	PINMUX_IPSR_MSEL(IP13_5_3, HSCIF1_HRTS_N_B, SEL_HSCIF1_1),
1441 	PINMUX_IPSR_MSEL(IP13_5_3, SCIFA0_TXD_D, SEL_SCIFA0_3),
1442 	PINMUX_IPSR_GPSR(IP13_5_3, VI1_DATA4),
1443 	PINMUX_IPSR_GPSR(IP13_5_3, ATACS10_N),
1444 	PINMUX_IPSR_MSEL(IP13_5_3, ETH_REFCLK_B, SEL_ETH_1),
1445 	PINMUX_IPSR_MSEL(IP13_8_6, SSI_SCK9, SEL_SSI9_0),
1446 	PINMUX_IPSR_MSEL(IP13_8_6, SCIF2_SCK_B, SEL_SCIF2_1),
1447 	PINMUX_IPSR_GPSR(IP13_8_6, PWM2_B),
1448 	PINMUX_IPSR_GPSR(IP13_8_6, VI1_DATA5),
1449 	PINMUX_IPSR_GPSR(IP13_8_6, EX_WAIT1),
1450 	PINMUX_IPSR_MSEL(IP13_8_6, ETH_TXD1_B, SEL_ETH_1),
1451 	PINMUX_IPSR_MSEL(IP13_11_9, SSI_WS9, SEL_SSI9_0),
1452 	PINMUX_IPSR_MSEL(IP13_11_9, SCIF2_RXD_B, SEL_SCIF2_1),
1453 	PINMUX_IPSR_MSEL(IP13_11_9, I2C3_SCL_E, SEL_I2C03_4),
1454 	PINMUX_IPSR_GPSR(IP13_11_9, VI1_DATA6),
1455 	PINMUX_IPSR_GPSR(IP13_11_9, ATARD0_N),
1456 	PINMUX_IPSR_MSEL(IP13_11_9, ETH_TX_EN_B, SEL_ETH_1),
1457 	PINMUX_IPSR_MSEL(IP13_14_12, SSI_SDATA9, SEL_SSI9_0),
1458 	PINMUX_IPSR_MSEL(IP13_14_12, SCIF2_TXD_B, SEL_SCIF2_1),
1459 	PINMUX_IPSR_MSEL(IP13_14_12, I2C3_SDA_E, SEL_I2C03_4),
1460 	PINMUX_IPSR_GPSR(IP13_14_12, VI1_DATA7),
1461 	PINMUX_IPSR_GPSR(IP13_14_12, ATADIR0_N),
1462 	PINMUX_IPSR_MSEL(IP13_14_12, ETH_MAGIC_B, SEL_ETH_1),
1463 	PINMUX_IPSR_MSEL(IP13_17_15, AUDIO_CLKA, SEL_ADG_0),
1464 	PINMUX_IPSR_MSEL(IP13_17_15, I2C0_SCL_B, SEL_I2C00_1),
1465 	PINMUX_IPSR_MSEL(IP13_17_15, SCIFA4_RXD_D, SEL_SCIFA4_3),
1466 	PINMUX_IPSR_GPSR(IP13_17_15, VI1_CLKENB),
1467 	PINMUX_IPSR_MSEL(IP13_17_15, TS_SDATA_C, SEL_TSIF0_2),
1468 	PINMUX_IPSR_MSEL(IP13_17_15, ETH_TXD0_B, SEL_ETH_1),
1469 	PINMUX_IPSR_MSEL(IP13_20_18, AUDIO_CLKB, SEL_ADG_0),
1470 	PINMUX_IPSR_MSEL(IP13_20_18, I2C0_SDA_B, SEL_I2C00_1),
1471 	PINMUX_IPSR_MSEL(IP13_20_18, SCIFA4_TXD_D, SEL_SCIFA4_3),
1472 	PINMUX_IPSR_GPSR(IP13_20_18, VI1_FIELD),
1473 	PINMUX_IPSR_MSEL(IP13_20_18, TS_SCK_C, SEL_TSIF0_2),
1474 	PINMUX_IPSR_MSEL(IP13_20_18, BPFCLK_E, SEL_DARC_4),
1475 	PINMUX_IPSR_MSEL(IP13_20_18, ETH_MDC_B, SEL_ETH_1),
1476 	PINMUX_IPSR_MSEL(IP13_23_21, AUDIO_CLKC, SEL_ADG_0),
1477 	PINMUX_IPSR_MSEL(IP13_23_21, I2C4_SCL_B, SEL_I2C04_1),
1478 	PINMUX_IPSR_MSEL(IP13_23_21, SCIFA5_RXD_D, SEL_SCIFA5_3),
1479 	PINMUX_IPSR_GPSR(IP13_23_21, VI1_HSYNC_N),
1480 	PINMUX_IPSR_MSEL(IP13_23_21, TS_SDEN_C, SEL_TSIF0_2),
1481 	PINMUX_IPSR_MSEL(IP13_23_21, FMCLK_E, SEL_DARC_4),
1482 	PINMUX_IPSR_MSEL(IP13_26_24, AUDIO_CLKOUT, SEL_ADG_0),
1483 	PINMUX_IPSR_MSEL(IP13_26_24, I2C4_SDA_B, SEL_I2C04_1),
1484 	PINMUX_IPSR_MSEL(IP13_26_24, SCIFA5_TXD_D, SEL_SCIFA5_3),
1485 	PINMUX_IPSR_GPSR(IP13_26_24, VI1_VSYNC_N),
1486 	PINMUX_IPSR_MSEL(IP13_26_24, TS_SPSYNC_C, SEL_TSIF0_2),
1487 	PINMUX_IPSR_MSEL(IP13_26_24, FMIN_E, SEL_DARC_4),
1488 };
1489 
1490 /*
1491  * Pins not associated with a GPIO port.
1492  */
1493 enum {
1494 	GP_ASSIGN_LAST(),
1495 	NOGP_ALL(),
1496 };
1497 
1498 static const struct sh_pfc_pin pinmux_pins[] = {
1499 	PINMUX_GPIO_GP_ALL(),
1500 	PINMUX_NOGP_ALL(),
1501 };
1502 
1503 /* - Audio Clock ------------------------------------------------------------ */
1504 static const unsigned int audio_clka_pins[] = {
1505 	/* CLKA */
1506 	RCAR_GP_PIN(5, 20),
1507 };
1508 static const unsigned int audio_clka_mux[] = {
1509 	AUDIO_CLKA_MARK,
1510 };
1511 static const unsigned int audio_clka_b_pins[] = {
1512 	/* CLKA */
1513 	RCAR_GP_PIN(3, 25),
1514 };
1515 static const unsigned int audio_clka_b_mux[] = {
1516 	AUDIO_CLKA_B_MARK,
1517 };
1518 static const unsigned int audio_clka_c_pins[] = {
1519 	/* CLKA */
1520 	RCAR_GP_PIN(4, 20),
1521 };
1522 static const unsigned int audio_clka_c_mux[] = {
1523 	AUDIO_CLKA_C_MARK,
1524 };
1525 static const unsigned int audio_clka_d_pins[] = {
1526 	/* CLKA */
1527 	RCAR_GP_PIN(5, 0),
1528 };
1529 static const unsigned int audio_clka_d_mux[] = {
1530 	AUDIO_CLKA_D_MARK,
1531 };
1532 static const unsigned int audio_clkb_pins[] = {
1533 	/* CLKB */
1534 	RCAR_GP_PIN(5, 21),
1535 };
1536 static const unsigned int audio_clkb_mux[] = {
1537 	AUDIO_CLKB_MARK,
1538 };
1539 static const unsigned int audio_clkb_b_pins[] = {
1540 	/* CLKB */
1541 	RCAR_GP_PIN(3, 26),
1542 };
1543 static const unsigned int audio_clkb_b_mux[] = {
1544 	AUDIO_CLKB_B_MARK,
1545 };
1546 static const unsigned int audio_clkb_c_pins[] = {
1547 	/* CLKB */
1548 	RCAR_GP_PIN(4, 21),
1549 };
1550 static const unsigned int audio_clkb_c_mux[] = {
1551 	AUDIO_CLKB_C_MARK,
1552 };
1553 static const unsigned int audio_clkc_pins[] = {
1554 	/* CLKC */
1555 	RCAR_GP_PIN(5, 22),
1556 };
1557 static const unsigned int audio_clkc_mux[] = {
1558 	AUDIO_CLKC_MARK,
1559 };
1560 static const unsigned int audio_clkc_b_pins[] = {
1561 	/* CLKC */
1562 	RCAR_GP_PIN(3, 29),
1563 };
1564 static const unsigned int audio_clkc_b_mux[] = {
1565 	AUDIO_CLKC_B_MARK,
1566 };
1567 static const unsigned int audio_clkc_c_pins[] = {
1568 	/* CLKC */
1569 	RCAR_GP_PIN(4, 22),
1570 };
1571 static const unsigned int audio_clkc_c_mux[] = {
1572 	AUDIO_CLKC_C_MARK,
1573 };
1574 static const unsigned int audio_clkout_pins[] = {
1575 	/* CLKOUT */
1576 	RCAR_GP_PIN(5, 23),
1577 };
1578 static const unsigned int audio_clkout_mux[] = {
1579 	AUDIO_CLKOUT_MARK,
1580 };
1581 static const unsigned int audio_clkout_b_pins[] = {
1582 	/* CLKOUT */
1583 	RCAR_GP_PIN(3, 12),
1584 };
1585 static const unsigned int audio_clkout_b_mux[] = {
1586 	AUDIO_CLKOUT_B_MARK,
1587 };
1588 static const unsigned int audio_clkout_c_pins[] = {
1589 	/* CLKOUT */
1590 	RCAR_GP_PIN(4, 23),
1591 };
1592 static const unsigned int audio_clkout_c_mux[] = {
1593 	AUDIO_CLKOUT_C_MARK,
1594 };
1595 /* - AVB -------------------------------------------------------------------- */
1596 static const unsigned int avb_link_pins[] = {
1597 	RCAR_GP_PIN(3, 26),
1598 };
1599 static const unsigned int avb_link_mux[] = {
1600 	AVB_LINK_MARK,
1601 };
1602 static const unsigned int avb_magic_pins[] = {
1603 	RCAR_GP_PIN(3, 27),
1604 };
1605 static const unsigned int avb_magic_mux[] = {
1606 	AVB_MAGIC_MARK,
1607 };
1608 static const unsigned int avb_phy_int_pins[] = {
1609 	RCAR_GP_PIN(3, 28),
1610 };
1611 static const unsigned int avb_phy_int_mux[] = {
1612 	AVB_PHY_INT_MARK,
1613 };
1614 static const unsigned int avb_mdio_pins[] = {
1615 	RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25),
1616 };
1617 static const unsigned int avb_mdio_mux[] = {
1618 	AVB_MDC_MARK, AVB_MDIO_MARK,
1619 };
1620 static const unsigned int avb_mii_pins[] = {
1621 	RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
1622 	RCAR_GP_PIN(3, 17),
1623 
1624 	RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
1625 	RCAR_GP_PIN(3, 5),
1626 
1627 	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
1628 	RCAR_GP_PIN(3, 29), RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 22),
1629 	RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 11),
1630 };
1631 static const unsigned int avb_mii_mux[] = {
1632 	AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
1633 	AVB_TXD3_MARK,
1634 
1635 	AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
1636 	AVB_RXD3_MARK,
1637 
1638 	AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
1639 	AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_ER_MARK,
1640 	AVB_TX_CLK_MARK, AVB_COL_MARK,
1641 };
1642 static const unsigned int avb_gmii_pins[] = {
1643 	RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
1644 	RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
1645 	RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
1646 
1647 	RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
1648 	RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
1649 	RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1650 
1651 	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
1652 	RCAR_GP_PIN(3, 29), RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 30),
1653 	RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 13),
1654 	RCAR_GP_PIN(3, 11),
1655 };
1656 static const unsigned int avb_gmii_mux[] = {
1657 	AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
1658 	AVB_TXD3_MARK, AVB_TXD4_MARK, AVB_TXD5_MARK,
1659 	AVB_TXD6_MARK, AVB_TXD7_MARK,
1660 
1661 	AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
1662 	AVB_RXD3_MARK, AVB_RXD4_MARK, AVB_RXD5_MARK,
1663 	AVB_RXD6_MARK, AVB_RXD7_MARK,
1664 
1665 	AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
1666 	AVB_CRS_MARK, AVB_GTX_CLK_MARK, AVB_GTXREFCLK_MARK,
1667 	AVB_TX_EN_MARK, AVB_TX_ER_MARK, AVB_TX_CLK_MARK,
1668 	AVB_COL_MARK,
1669 };
1670 
1671 /* - CAN -------------------------------------------------------------------- */
1672 static const unsigned int can0_data_pins[] = {
1673 	/* TX, RX */
1674 	RCAR_GP_PIN(6, 15), RCAR_GP_PIN(6, 14),
1675 };
1676 
1677 static const unsigned int can0_data_mux[] = {
1678 	CAN0_TX_MARK, CAN0_RX_MARK,
1679 };
1680 
1681 static const unsigned int can0_data_b_pins[] = {
1682 	/* TX, RX */
1683 	RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 15),
1684 };
1685 
1686 static const unsigned int can0_data_b_mux[] = {
1687 	CAN0_TX_B_MARK, CAN0_RX_B_MARK,
1688 };
1689 
1690 static const unsigned int can0_data_c_pins[] = {
1691 	/* TX, RX */
1692 	RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 16),
1693 };
1694 
1695 static const unsigned int can0_data_c_mux[] = {
1696 	CAN0_TX_C_MARK, CAN0_RX_C_MARK,
1697 };
1698 
1699 static const unsigned int can0_data_d_pins[] = {
1700 	/* TX, RX */
1701 	RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 11),
1702 };
1703 
1704 static const unsigned int can0_data_d_mux[] = {
1705 	CAN0_TX_D_MARK, CAN0_RX_D_MARK,
1706 };
1707 
1708 static const unsigned int can1_data_pins[] = {
1709 	/* TX, RX */
1710 	RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 24),
1711 };
1712 
1713 static const unsigned int can1_data_mux[] = {
1714 	CAN1_TX_MARK, CAN1_RX_MARK,
1715 };
1716 
1717 static const unsigned int can1_data_b_pins[] = {
1718 	/* TX, RX */
1719 	RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 1),
1720 };
1721 
1722 static const unsigned int can1_data_b_mux[] = {
1723 	CAN1_TX_B_MARK, CAN1_RX_B_MARK,
1724 };
1725 
1726 static const unsigned int can1_data_c_pins[] = {
1727 	/* TX, RX */
1728 	RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 5),
1729 };
1730 
1731 static const unsigned int can1_data_c_mux[] = {
1732 	CAN1_TX_C_MARK, CAN1_RX_C_MARK,
1733 };
1734 
1735 static const unsigned int can1_data_d_pins[] = {
1736 	/* TX, RX */
1737 	RCAR_GP_PIN(3, 31), RCAR_GP_PIN(3, 30),
1738 };
1739 
1740 static const unsigned int can1_data_d_mux[] = {
1741 	CAN1_TX_D_MARK, CAN1_RX_D_MARK,
1742 };
1743 
1744 static const unsigned int can_clk_pins[] = {
1745 	/* CLK */
1746 	RCAR_GP_PIN(3, 31),
1747 };
1748 
1749 static const unsigned int can_clk_mux[] = {
1750 	CAN_CLK_MARK,
1751 };
1752 
1753 static const unsigned int can_clk_b_pins[] = {
1754 	/* CLK */
1755 	RCAR_GP_PIN(1, 23),
1756 };
1757 
1758 static const unsigned int can_clk_b_mux[] = {
1759 	CAN_CLK_B_MARK,
1760 };
1761 
1762 static const unsigned int can_clk_c_pins[] = {
1763 	/* CLK */
1764 	RCAR_GP_PIN(1, 0),
1765 };
1766 
1767 static const unsigned int can_clk_c_mux[] = {
1768 	CAN_CLK_C_MARK,
1769 };
1770 
1771 static const unsigned int can_clk_d_pins[] = {
1772 	/* CLK */
1773 	RCAR_GP_PIN(5, 0),
1774 };
1775 
1776 static const unsigned int can_clk_d_mux[] = {
1777 	CAN_CLK_D_MARK,
1778 };
1779 
1780 /* - DU --------------------------------------------------------------------- */
1781 static const unsigned int du0_rgb666_pins[] = {
1782 	/* R[7:2], G[7:2], B[7:2] */
1783 	RCAR_GP_PIN(2, 7),  RCAR_GP_PIN(2, 6),  RCAR_GP_PIN(2, 5),
1784 	RCAR_GP_PIN(2, 4),  RCAR_GP_PIN(2, 3),  RCAR_GP_PIN(2, 2),
1785 	RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
1786 	RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
1787 	RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22), RCAR_GP_PIN(2, 21),
1788 	RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 18),
1789 };
1790 static const unsigned int du0_rgb666_mux[] = {
1791 	DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK,
1792 	DU0_DR3_MARK, DU0_DR2_MARK,
1793 	DU0_DG7_MARK, DU0_DG6_MARK, DU0_DG5_MARK, DU0_DG4_MARK,
1794 	DU0_DG3_MARK, DU0_DG2_MARK,
1795 	DU0_DB7_MARK, DU0_DB6_MARK, DU0_DB5_MARK, DU0_DB4_MARK,
1796 	DU0_DB3_MARK, DU0_DB2_MARK,
1797 };
1798 static const unsigned int du0_rgb888_pins[] = {
1799 	/* R[7:0], G[7:0], B[7:0] */
1800 	RCAR_GP_PIN(2, 7),  RCAR_GP_PIN(2, 6),  RCAR_GP_PIN(2, 5),
1801 	RCAR_GP_PIN(2, 4),  RCAR_GP_PIN(2, 3),  RCAR_GP_PIN(2, 2),
1802 	RCAR_GP_PIN(2, 1),  RCAR_GP_PIN(2, 0),
1803 	RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
1804 	RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
1805 	RCAR_GP_PIN(2, 9),  RCAR_GP_PIN(2, 8),
1806 	RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22), RCAR_GP_PIN(2, 21),
1807 	RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 18),
1808 	RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 16),
1809 };
1810 static const unsigned int du0_rgb888_mux[] = {
1811 	DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK,
1812 	DU0_DR3_MARK, DU0_DR2_MARK, DU0_DR1_MARK, DU0_DR0_MARK,
1813 	DU0_DG7_MARK, DU0_DG6_MARK, DU0_DG5_MARK, DU0_DG4_MARK,
1814 	DU0_DG3_MARK, DU0_DG2_MARK, DU0_DG1_MARK, DU0_DG0_MARK,
1815 	DU0_DB7_MARK, DU0_DB6_MARK, DU0_DB5_MARK, DU0_DB4_MARK,
1816 	DU0_DB3_MARK, DU0_DB2_MARK, DU0_DB1_MARK, DU0_DB0_MARK,
1817 };
1818 static const unsigned int du0_clk0_out_pins[] = {
1819 	/* DOTCLKOUT0 */
1820 	RCAR_GP_PIN(2, 25),
1821 };
1822 static const unsigned int du0_clk0_out_mux[] = {
1823 	DU0_DOTCLKOUT0_MARK
1824 };
1825 static const unsigned int du0_clk1_out_pins[] = {
1826 	/* DOTCLKOUT1 */
1827 	RCAR_GP_PIN(2, 26),
1828 };
1829 static const unsigned int du0_clk1_out_mux[] = {
1830 	DU0_DOTCLKOUT1_MARK
1831 };
1832 static const unsigned int du0_clk_in_pins[] = {
1833 	/* CLKIN */
1834 	RCAR_GP_PIN(2, 24),
1835 };
1836 static const unsigned int du0_clk_in_mux[] = {
1837 	DU0_DOTCLKIN_MARK
1838 };
1839 static const unsigned int du0_sync_pins[] = {
1840 	/* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
1841 	RCAR_GP_PIN(2, 28), RCAR_GP_PIN(2, 27),
1842 };
1843 static const unsigned int du0_sync_mux[] = {
1844 	DU0_EXVSYNC_DU0_VSYNC_MARK, DU0_EXHSYNC_DU0_HSYNC_MARK
1845 };
1846 static const unsigned int du0_oddf_pins[] = {
1847 	/* EXODDF/ODDF/DISP/CDE */
1848 	RCAR_GP_PIN(2, 29),
1849 };
1850 static const unsigned int du0_oddf_mux[] = {
1851 	DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK,
1852 };
1853 static const unsigned int du0_cde_pins[] = {
1854 	/* CDE */
1855 	RCAR_GP_PIN(2, 31),
1856 };
1857 static const unsigned int du0_cde_mux[] = {
1858 	DU0_CDE_MARK,
1859 };
1860 static const unsigned int du0_disp_pins[] = {
1861 	/* DISP */
1862 	RCAR_GP_PIN(2, 30),
1863 };
1864 static const unsigned int du0_disp_mux[] = {
1865 	DU0_DISP_MARK
1866 };
1867 static const unsigned int du1_rgb666_pins[] = {
1868 	/* R[7:2], G[7:2], B[7:2] */
1869 	RCAR_GP_PIN(4, 7),  RCAR_GP_PIN(4, 6),  RCAR_GP_PIN(4, 5),
1870 	RCAR_GP_PIN(4, 4),  RCAR_GP_PIN(4, 3),  RCAR_GP_PIN(4, 2),
1871 	RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13),
1872 	RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 10),
1873 	RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 21),
1874 	RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 18),
1875 };
1876 static const unsigned int du1_rgb666_mux[] = {
1877 	DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
1878 	DU1_DR3_MARK, DU1_DR2_MARK,
1879 	DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
1880 	DU1_DG3_MARK, DU1_DG2_MARK,
1881 	DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
1882 	DU1_DB3_MARK, DU1_DB2_MARK,
1883 };
1884 static const unsigned int du1_rgb888_pins[] = {
1885 	/* R[7:0], G[7:0], B[7:0] */
1886 	RCAR_GP_PIN(4, 7),  RCAR_GP_PIN(4, 6),  RCAR_GP_PIN(4, 5),
1887 	RCAR_GP_PIN(4, 4),  RCAR_GP_PIN(4, 3),  RCAR_GP_PIN(4, 2),
1888 	RCAR_GP_PIN(4, 1),  RCAR_GP_PIN(4, 0),
1889 	RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13),
1890 	RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 10),
1891 	RCAR_GP_PIN(4, 9),  RCAR_GP_PIN(4, 8),
1892 	RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 21),
1893 	RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 18),
1894 	RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16),
1895 };
1896 static const unsigned int du1_rgb888_mux[] = {
1897 	DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
1898 	DU1_DR3_MARK, DU1_DR2_MARK, DU1_DR1_MARK, DU1_DR0_MARK,
1899 	DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
1900 	DU1_DG3_MARK, DU1_DG2_MARK, DU1_DG1_MARK, DU1_DG0_MARK,
1901 	DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
1902 	DU1_DB3_MARK, DU1_DB2_MARK, DU1_DB1_MARK, DU1_DB0_MARK,
1903 };
1904 static const unsigned int du1_clk0_out_pins[] = {
1905 	/* DOTCLKOUT0 */
1906 	RCAR_GP_PIN(4, 25),
1907 };
1908 static const unsigned int du1_clk0_out_mux[] = {
1909 	DU1_DOTCLKOUT0_MARK
1910 };
1911 static const unsigned int du1_clk1_out_pins[] = {
1912 	/* DOTCLKOUT1 */
1913 	RCAR_GP_PIN(4, 26),
1914 };
1915 static const unsigned int du1_clk1_out_mux[] = {
1916 	DU1_DOTCLKOUT1_MARK
1917 };
1918 static const unsigned int du1_clk_in_pins[] = {
1919 	/* DOTCLKIN */
1920 	RCAR_GP_PIN(4, 24),
1921 };
1922 static const unsigned int du1_clk_in_mux[] = {
1923 	DU1_DOTCLKIN_MARK
1924 };
1925 static const unsigned int du1_sync_pins[] = {
1926 	/* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
1927 	RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 27),
1928 };
1929 static const unsigned int du1_sync_mux[] = {
1930 	DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK
1931 };
1932 static const unsigned int du1_oddf_pins[] = {
1933 	/* EXODDF/ODDF/DISP/CDE */
1934 	RCAR_GP_PIN(4, 29),
1935 };
1936 static const unsigned int du1_oddf_mux[] = {
1937 	DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
1938 };
1939 static const unsigned int du1_cde_pins[] = {
1940 	/* CDE */
1941 	RCAR_GP_PIN(4, 31),
1942 };
1943 static const unsigned int du1_cde_mux[] = {
1944 	DU1_CDE_MARK
1945 };
1946 static const unsigned int du1_disp_pins[] = {
1947 	/* DISP */
1948 	RCAR_GP_PIN(4, 30),
1949 };
1950 static const unsigned int du1_disp_mux[] = {
1951 	DU1_DISP_MARK
1952 };
1953 /* - ETH -------------------------------------------------------------------- */
1954 static const unsigned int eth_link_pins[] = {
1955 	/* LINK */
1956 	RCAR_GP_PIN(3, 18),
1957 };
1958 static const unsigned int eth_link_mux[] = {
1959 	ETH_LINK_MARK,
1960 };
1961 static const unsigned int eth_magic_pins[] = {
1962 	/* MAGIC */
1963 	RCAR_GP_PIN(3, 22),
1964 };
1965 static const unsigned int eth_magic_mux[] = {
1966 	ETH_MAGIC_MARK,
1967 };
1968 static const unsigned int eth_mdio_pins[] = {
1969 	/* MDC, MDIO */
1970 	RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 13),
1971 };
1972 static const unsigned int eth_mdio_mux[] = {
1973 	ETH_MDC_MARK, ETH_MDIO_MARK,
1974 };
1975 static const unsigned int eth_rmii_pins[] = {
1976 	/* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */
1977 	RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 15),
1978 	RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 20),
1979 	RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 19),
1980 };
1981 static const unsigned int eth_rmii_mux[] = {
1982 	ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK,
1983 	ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REFCLK_MARK,
1984 };
1985 static const unsigned int eth_link_b_pins[] = {
1986 	/* LINK */
1987 	RCAR_GP_PIN(5, 15),
1988 };
1989 static const unsigned int eth_link_b_mux[] = {
1990 	ETH_LINK_B_MARK,
1991 };
1992 static const unsigned int eth_magic_b_pins[] = {
1993 	/* MAGIC */
1994 	RCAR_GP_PIN(5, 19),
1995 };
1996 static const unsigned int eth_magic_b_mux[] = {
1997 	ETH_MAGIC_B_MARK,
1998 };
1999 static const unsigned int eth_mdio_b_pins[] = {
2000 	/* MDC, MDIO */
2001 	RCAR_GP_PIN(5, 21), RCAR_GP_PIN(5, 10),
2002 };
2003 static const unsigned int eth_mdio_b_mux[] = {
2004 	ETH_MDC_B_MARK, ETH_MDIO_B_MARK,
2005 };
2006 static const unsigned int eth_rmii_b_pins[] = {
2007 	/* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */
2008 	RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 12),
2009 	RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 17),
2010 	RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 16),
2011 };
2012 static const unsigned int eth_rmii_b_mux[] = {
2013 	ETH_RXD0_B_MARK, ETH_RXD1_B_MARK, ETH_RX_ER_B_MARK, ETH_CRS_DV_B_MARK,
2014 	ETH_TXD0_B_MARK, ETH_TXD1_B_MARK, ETH_TX_EN_B_MARK, ETH_REFCLK_B_MARK,
2015 };
2016 /* - HSCIF0 ----------------------------------------------------------------- */
2017 static const unsigned int hscif0_data_pins[] = {
2018 	/* RX, TX */
2019 	RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
2020 };
2021 static const unsigned int hscif0_data_mux[] = {
2022 	HSCIF0_HRX_MARK, HSCIF0_HTX_MARK,
2023 };
2024 static const unsigned int hscif0_clk_pins[] = {
2025 	/* SCK */
2026 	RCAR_GP_PIN(3, 29),
2027 };
2028 static const unsigned int hscif0_clk_mux[] = {
2029 	HSCIF0_HSCK_MARK,
2030 };
2031 static const unsigned int hscif0_ctrl_pins[] = {
2032 	/* RTS, CTS */
2033 	RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 27),
2034 };
2035 static const unsigned int hscif0_ctrl_mux[] = {
2036 	HSCIF0_HRTS_N_MARK, HSCIF0_HCTS_N_MARK,
2037 };
2038 static const unsigned int hscif0_data_b_pins[] = {
2039 	/* RX, TX */
2040 	RCAR_GP_PIN(0, 30), RCAR_GP_PIN(0, 31),
2041 };
2042 static const unsigned int hscif0_data_b_mux[] = {
2043 	HSCIF0_HRX_B_MARK, HSCIF0_HTX_B_MARK,
2044 };
2045 static const unsigned int hscif0_clk_b_pins[] = {
2046 	/* SCK */
2047 	RCAR_GP_PIN(1, 0),
2048 };
2049 static const unsigned int hscif0_clk_b_mux[] = {
2050 	HSCIF0_HSCK_B_MARK,
2051 };
2052 /* - HSCIF1 ----------------------------------------------------------------- */
2053 static const unsigned int hscif1_data_pins[] = {
2054 	/* RX, TX */
2055 	RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
2056 };
2057 static const unsigned int hscif1_data_mux[] = {
2058 	HSCIF1_HRX_MARK, HSCIF1_HTX_MARK,
2059 };
2060 static const unsigned int hscif1_clk_pins[] = {
2061 	/* SCK */
2062 	RCAR_GP_PIN(4, 10),
2063 };
2064 static const unsigned int hscif1_clk_mux[] = {
2065 	HSCIF1_HSCK_MARK,
2066 };
2067 static const unsigned int hscif1_ctrl_pins[] = {
2068 	/* RTS, CTS */
2069 	RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 11),
2070 };
2071 static const unsigned int hscif1_ctrl_mux[] = {
2072 	HSCIF1_HRTS_N_MARK, HSCIF1_HCTS_N_MARK,
2073 };
2074 static const unsigned int hscif1_data_b_pins[] = {
2075 	/* RX, TX */
2076 	RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
2077 };
2078 static const unsigned int hscif1_data_b_mux[] = {
2079 	HSCIF1_HRX_B_MARK, HSCIF1_HTX_B_MARK,
2080 };
2081 static const unsigned int hscif1_ctrl_b_pins[] = {
2082 	/* RTS, CTS */
2083 	RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
2084 };
2085 static const unsigned int hscif1_ctrl_b_mux[] = {
2086 	HSCIF1_HRTS_N_B_MARK, HSCIF1_HCTS_N_B_MARK,
2087 };
2088 /* - HSCIF2 ----------------------------------------------------------------- */
2089 static const unsigned int hscif2_data_pins[] = {
2090 	/* RX, TX */
2091 	RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
2092 };
2093 static const unsigned int hscif2_data_mux[] = {
2094 	HSCIF2_HRX_MARK, HSCIF2_HTX_MARK,
2095 };
2096 static const unsigned int hscif2_clk_pins[] = {
2097 	/* SCK */
2098 	RCAR_GP_PIN(0, 10),
2099 };
2100 static const unsigned int hscif2_clk_mux[] = {
2101 	HSCIF2_HSCK_MARK,
2102 };
2103 static const unsigned int hscif2_ctrl_pins[] = {
2104 	/* RTS, CTS */
2105 	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11),
2106 };
2107 static const unsigned int hscif2_ctrl_mux[] = {
2108 	HSCIF2_HRTS_N_MARK, HSCIF2_HCTS_N_MARK,
2109 };
2110 /* - I2C0 ------------------------------------------------------------------- */
2111 static const unsigned int i2c0_pins[] = {
2112 	/* SCL, SDA */
2113 	RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31),
2114 };
2115 static const unsigned int i2c0_mux[] = {
2116 	I2C0_SCL_MARK, I2C0_SDA_MARK,
2117 };
2118 static const unsigned int i2c0_b_pins[] = {
2119 	/* SCL, SDA */
2120 	RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21),
2121 };
2122 static const unsigned int i2c0_b_mux[] = {
2123 	I2C0_SCL_B_MARK, I2C0_SDA_B_MARK,
2124 };
2125 static const unsigned int i2c0_c_pins[] = {
2126 	/* SCL, SDA */
2127 	RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12),
2128 };
2129 static const unsigned int i2c0_c_mux[] = {
2130 	I2C0_SCL_C_MARK, I2C0_SDA_C_MARK,
2131 };
2132 static const unsigned int i2c0_d_pins[] = {
2133 	/* SCL, SDA */
2134 	RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
2135 };
2136 static const unsigned int i2c0_d_mux[] = {
2137 	I2C0_SCL_D_MARK, I2C0_SDA_D_MARK,
2138 };
2139 static const unsigned int i2c0_e_pins[] = {
2140 	/* SCL, SDA */
2141 	RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28),
2142 };
2143 static const unsigned int i2c0_e_mux[] = {
2144 	I2C0_SCL_E_MARK, I2C0_SDA_E_MARK,
2145 };
2146 /* - I2C1 ------------------------------------------------------------------- */
2147 static const unsigned int i2c1_pins[] = {
2148 	/* SCL, SDA */
2149 	RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
2150 };
2151 static const unsigned int i2c1_mux[] = {
2152 	I2C1_SCL_MARK, I2C1_SDA_MARK,
2153 };
2154 static const unsigned int i2c1_b_pins[] = {
2155 	/* SCL, SDA */
2156 	RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
2157 };
2158 static const unsigned int i2c1_b_mux[] = {
2159 	I2C1_SCL_B_MARK, I2C1_SDA_B_MARK,
2160 };
2161 static const unsigned int i2c1_c_pins[] = {
2162 	/* SCL, SDA */
2163 	RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
2164 };
2165 static const unsigned int i2c1_c_mux[] = {
2166 	I2C1_SCL_C_MARK, I2C1_SDA_C_MARK,
2167 };
2168 static const unsigned int i2c1_d_pins[] = {
2169 	/* SCL, SDA */
2170 	RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 12),
2171 };
2172 static const unsigned int i2c1_d_mux[] = {
2173 	I2C1_SCL_D_MARK, I2C1_SDA_D_MARK,
2174 };
2175 static const unsigned int i2c1_e_pins[] = {
2176 	/* SCL, SDA */
2177 	RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
2178 };
2179 static const unsigned int i2c1_e_mux[] = {
2180 	I2C1_SCL_E_MARK, I2C1_SDA_E_MARK,
2181 };
2182 /* - I2C2 ------------------------------------------------------------------- */
2183 static const unsigned int i2c2_pins[] = {
2184 	/* SCL, SDA */
2185 	RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
2186 };
2187 static const unsigned int i2c2_mux[] = {
2188 	I2C2_SCL_MARK, I2C2_SDA_MARK,
2189 };
2190 static const unsigned int i2c2_b_pins[] = {
2191 	/* SCL, SDA */
2192 	RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
2193 };
2194 static const unsigned int i2c2_b_mux[] = {
2195 	I2C2_SCL_B_MARK, I2C2_SDA_B_MARK,
2196 };
2197 static const unsigned int i2c2_c_pins[] = {
2198 	/* SCL, SDA */
2199 	RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
2200 };
2201 static const unsigned int i2c2_c_mux[] = {
2202 	I2C2_SCL_C_MARK, I2C2_SDA_C_MARK,
2203 };
2204 static const unsigned int i2c2_d_pins[] = {
2205 	/* SCL, SDA */
2206 	RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
2207 };
2208 static const unsigned int i2c2_d_mux[] = {
2209 	I2C2_SCL_D_MARK, I2C2_SDA_D_MARK,
2210 };
2211 static const unsigned int i2c2_e_pins[] = {
2212 	/* SCL, SDA */
2213 	RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17),
2214 };
2215 static const unsigned int i2c2_e_mux[] = {
2216 	I2C2_SCL_E_MARK, I2C2_SDA_E_MARK,
2217 };
2218 /* - I2C3 ------------------------------------------------------------------- */
2219 static const unsigned int i2c3_pins[] = {
2220 	/* SCL, SDA */
2221 	RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10),
2222 };
2223 static const unsigned int i2c3_mux[] = {
2224 	I2C3_SCL_MARK, I2C3_SDA_MARK,
2225 };
2226 static const unsigned int i2c3_b_pins[] = {
2227 	/* SCL, SDA */
2228 	RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4),
2229 };
2230 static const unsigned int i2c3_b_mux[] = {
2231 	I2C3_SCL_B_MARK, I2C3_SDA_B_MARK,
2232 };
2233 static const unsigned int i2c3_c_pins[] = {
2234 	/* SCL, SDA */
2235 	RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
2236 };
2237 static const unsigned int i2c3_c_mux[] = {
2238 	I2C3_SCL_C_MARK, I2C3_SDA_C_MARK,
2239 };
2240 static const unsigned int i2c3_d_pins[] = {
2241 	/* SCL, SDA */
2242 	RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
2243 };
2244 static const unsigned int i2c3_d_mux[] = {
2245 	I2C3_SCL_D_MARK, I2C3_SDA_D_MARK,
2246 };
2247 static const unsigned int i2c3_e_pins[] = {
2248 	/* SCL, SDA */
2249 	RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19),
2250 };
2251 static const unsigned int i2c3_e_mux[] = {
2252 	I2C3_SCL_E_MARK, I2C3_SDA_E_MARK,
2253 };
2254 /* - I2C4 ------------------------------------------------------------------- */
2255 static const unsigned int i2c4_pins[] = {
2256 	/* SCL, SDA */
2257 	RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
2258 };
2259 static const unsigned int i2c4_mux[] = {
2260 	I2C4_SCL_MARK, I2C4_SDA_MARK,
2261 };
2262 static const unsigned int i2c4_b_pins[] = {
2263 	/* SCL, SDA */
2264 	RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
2265 };
2266 static const unsigned int i2c4_b_mux[] = {
2267 	I2C4_SCL_B_MARK, I2C4_SDA_B_MARK,
2268 };
2269 static const unsigned int i2c4_c_pins[] = {
2270 	/* SCL, SDA */
2271 	RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
2272 };
2273 static const unsigned int i2c4_c_mux[] = {
2274 	I2C4_SCL_C_MARK, I2C4_SDA_C_MARK,
2275 };
2276 static const unsigned int i2c4_d_pins[] = {
2277 	/* SCL, SDA */
2278 	RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
2279 };
2280 static const unsigned int i2c4_d_mux[] = {
2281 	I2C4_SCL_D_MARK, I2C4_SDA_D_MARK,
2282 };
2283 static const unsigned int i2c4_e_pins[] = {
2284 	/* SCL, SDA */
2285 	RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24),
2286 };
2287 static const unsigned int i2c4_e_mux[] = {
2288 	I2C4_SCL_E_MARK, I2C4_SDA_E_MARK,
2289 };
2290 /* - I2C5 ------------------------------------------------------------------- */
2291 static const unsigned int i2c5_pins[] = {
2292 	/* SCL, SDA */
2293 	RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
2294 };
2295 static const unsigned int i2c5_mux[] = {
2296 	I2C5_SCL_MARK, I2C5_SDA_MARK,
2297 };
2298 static const unsigned int i2c5_b_pins[] = {
2299 	/* SCL, SDA */
2300 	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2301 };
2302 static const unsigned int i2c5_b_mux[] = {
2303 	I2C5_SCL_B_MARK, I2C5_SDA_B_MARK,
2304 };
2305 static const unsigned int i2c5_c_pins[] = {
2306 	/* SCL, SDA */
2307 	RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30),
2308 };
2309 static const unsigned int i2c5_c_mux[] = {
2310 	I2C5_SCL_C_MARK, I2C5_SDA_C_MARK,
2311 };
2312 static const unsigned int i2c5_d_pins[] = {
2313 	/* SCL, SDA */
2314 	RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
2315 };
2316 static const unsigned int i2c5_d_mux[] = {
2317 	I2C5_SCL_D_MARK, I2C5_SDA_D_MARK,
2318 };
2319 /* - INTC ------------------------------------------------------------------- */
2320 static const unsigned int intc_irq0_pins[] = {
2321 	/* IRQ0 */
2322 	RCAR_GP_PIN(4, 4),
2323 };
2324 static const unsigned int intc_irq0_mux[] = {
2325 	IRQ0_MARK,
2326 };
2327 static const unsigned int intc_irq1_pins[] = {
2328 	/* IRQ1 */
2329 	RCAR_GP_PIN(4, 18),
2330 };
2331 static const unsigned int intc_irq1_mux[] = {
2332 	IRQ1_MARK,
2333 };
2334 static const unsigned int intc_irq2_pins[] = {
2335 	/* IRQ2 */
2336 	RCAR_GP_PIN(4, 19),
2337 };
2338 static const unsigned int intc_irq2_mux[] = {
2339 	IRQ2_MARK,
2340 };
2341 static const unsigned int intc_irq3_pins[] = {
2342 	/* IRQ3 */
2343 	RCAR_GP_PIN(0, 7),
2344 };
2345 static const unsigned int intc_irq3_mux[] = {
2346 	IRQ3_MARK,
2347 };
2348 static const unsigned int intc_irq4_pins[] = {
2349 	/* IRQ4 */
2350 	RCAR_GP_PIN(0, 0),
2351 };
2352 static const unsigned int intc_irq4_mux[] = {
2353 	IRQ4_MARK,
2354 };
2355 static const unsigned int intc_irq5_pins[] = {
2356 	/* IRQ5 */
2357 	RCAR_GP_PIN(4, 1),
2358 };
2359 static const unsigned int intc_irq5_mux[] = {
2360 	IRQ5_MARK,
2361 };
2362 static const unsigned int intc_irq6_pins[] = {
2363 	/* IRQ6 */
2364 	RCAR_GP_PIN(0, 10),
2365 };
2366 static const unsigned int intc_irq6_mux[] = {
2367 	IRQ6_MARK,
2368 };
2369 static const unsigned int intc_irq7_pins[] = {
2370 	/* IRQ7 */
2371 	RCAR_GP_PIN(6, 15),
2372 };
2373 static const unsigned int intc_irq7_mux[] = {
2374 	IRQ7_MARK,
2375 };
2376 static const unsigned int intc_irq8_pins[] = {
2377 	/* IRQ8 */
2378 	RCAR_GP_PIN(5, 0),
2379 };
2380 static const unsigned int intc_irq8_mux[] = {
2381 	IRQ8_MARK,
2382 };
2383 static const unsigned int intc_irq9_pins[] = {
2384 	/* IRQ9 */
2385 	RCAR_GP_PIN(5, 10),
2386 };
2387 static const unsigned int intc_irq9_mux[] = {
2388 	IRQ9_MARK,
2389 };
2390 /* - MMCIF ------------------------------------------------------------------ */
2391 static const unsigned int mmc_data_pins[] = {
2392 	/* D[0:7] */
2393 	RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
2394 	RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
2395 	RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23),
2396 	RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
2397 };
2398 static const unsigned int mmc_data_mux[] = {
2399 	MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
2400 	MMC_D4_MARK, MMC_D5_MARK, MMC_D6_MARK, MMC_D7_MARK,
2401 };
2402 static const unsigned int mmc_ctrl_pins[] = {
2403 	/* CLK, CMD */
2404 	RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17),
2405 };
2406 static const unsigned int mmc_ctrl_mux[] = {
2407 	MMC_CLK_MARK, MMC_CMD_MARK,
2408 };
2409 /* - MSIOF0 ----------------------------------------------------------------- */
2410 static const unsigned int msiof0_clk_pins[] = {
2411 	/* SCK */
2412 	RCAR_GP_PIN(4, 4),
2413 };
2414 static const unsigned int msiof0_clk_mux[] = {
2415 	MSIOF0_SCK_MARK,
2416 };
2417 static const unsigned int msiof0_sync_pins[] = {
2418 	/* SYNC */
2419 	RCAR_GP_PIN(4, 5),
2420 };
2421 static const unsigned int msiof0_sync_mux[] = {
2422 	MSIOF0_SYNC_MARK,
2423 };
2424 static const unsigned int msiof0_ss1_pins[] = {
2425 	/* SS1 */
2426 	RCAR_GP_PIN(4, 6),
2427 };
2428 static const unsigned int msiof0_ss1_mux[] = {
2429 	MSIOF0_SS1_MARK,
2430 };
2431 static const unsigned int msiof0_ss2_pins[] = {
2432 	/* SS2 */
2433 	RCAR_GP_PIN(4, 7),
2434 };
2435 static const unsigned int msiof0_ss2_mux[] = {
2436 	MSIOF0_SS2_MARK,
2437 };
2438 static const unsigned int msiof0_rx_pins[] = {
2439 	/* RXD */
2440 	RCAR_GP_PIN(4, 2),
2441 };
2442 static const unsigned int msiof0_rx_mux[] = {
2443 	MSIOF0_RXD_MARK,
2444 };
2445 static const unsigned int msiof0_tx_pins[] = {
2446 	/* TXD */
2447 	RCAR_GP_PIN(4, 3),
2448 };
2449 static const unsigned int msiof0_tx_mux[] = {
2450 	MSIOF0_TXD_MARK,
2451 };
2452 /* - MSIOF1 ----------------------------------------------------------------- */
2453 static const unsigned int msiof1_clk_pins[] = {
2454 	/* SCK */
2455 	RCAR_GP_PIN(0, 26),
2456 };
2457 static const unsigned int msiof1_clk_mux[] = {
2458 	MSIOF1_SCK_MARK,
2459 };
2460 static const unsigned int msiof1_sync_pins[] = {
2461 	/* SYNC */
2462 	RCAR_GP_PIN(0, 27),
2463 };
2464 static const unsigned int msiof1_sync_mux[] = {
2465 	MSIOF1_SYNC_MARK,
2466 };
2467 static const unsigned int msiof1_ss1_pins[] = {
2468 	/* SS1 */
2469 	RCAR_GP_PIN(0, 28),
2470 };
2471 static const unsigned int msiof1_ss1_mux[] = {
2472 	MSIOF1_SS1_MARK,
2473 };
2474 static const unsigned int msiof1_ss2_pins[] = {
2475 	/* SS2 */
2476 	RCAR_GP_PIN(0, 29),
2477 };
2478 static const unsigned int msiof1_ss2_mux[] = {
2479 	MSIOF1_SS2_MARK,
2480 };
2481 static const unsigned int msiof1_rx_pins[] = {
2482 	/* RXD */
2483 	RCAR_GP_PIN(0, 24),
2484 };
2485 static const unsigned int msiof1_rx_mux[] = {
2486 	MSIOF1_RXD_MARK,
2487 };
2488 static const unsigned int msiof1_tx_pins[] = {
2489 	/* TXD */
2490 	RCAR_GP_PIN(0, 25),
2491 };
2492 static const unsigned int msiof1_tx_mux[] = {
2493 	MSIOF1_TXD_MARK,
2494 };
2495 static const unsigned int msiof1_clk_b_pins[] = {
2496 	/* SCK */
2497 	RCAR_GP_PIN(5, 3),
2498 };
2499 static const unsigned int msiof1_clk_b_mux[] = {
2500 	MSIOF1_SCK_B_MARK,
2501 };
2502 static const unsigned int msiof1_sync_b_pins[] = {
2503 	/* SYNC */
2504 	RCAR_GP_PIN(5, 4),
2505 };
2506 static const unsigned int msiof1_sync_b_mux[] = {
2507 	MSIOF1_SYNC_B_MARK,
2508 };
2509 static const unsigned int msiof1_ss1_b_pins[] = {
2510 	/* SS1 */
2511 	RCAR_GP_PIN(5, 5),
2512 };
2513 static const unsigned int msiof1_ss1_b_mux[] = {
2514 	MSIOF1_SS1_B_MARK,
2515 };
2516 static const unsigned int msiof1_ss2_b_pins[] = {
2517 	/* SS2 */
2518 	RCAR_GP_PIN(5, 6),
2519 };
2520 static const unsigned int msiof1_ss2_b_mux[] = {
2521 	MSIOF1_SS2_B_MARK,
2522 };
2523 static const unsigned int msiof1_rx_b_pins[] = {
2524 	/* RXD */
2525 	RCAR_GP_PIN(5, 1),
2526 };
2527 static const unsigned int msiof1_rx_b_mux[] = {
2528 	MSIOF1_RXD_B_MARK,
2529 };
2530 static const unsigned int msiof1_tx_b_pins[] = {
2531 	/* TXD */
2532 	RCAR_GP_PIN(5, 2),
2533 };
2534 static const unsigned int msiof1_tx_b_mux[] = {
2535 	MSIOF1_TXD_B_MARK,
2536 };
2537 /* - MSIOF2 ----------------------------------------------------------------- */
2538 static const unsigned int msiof2_clk_pins[] = {
2539 	/* SCK */
2540 	RCAR_GP_PIN(1, 0),
2541 };
2542 static const unsigned int msiof2_clk_mux[] = {
2543 	MSIOF2_SCK_MARK,
2544 };
2545 static const unsigned int msiof2_sync_pins[] = {
2546 	/* SYNC */
2547 	RCAR_GP_PIN(1, 1),
2548 };
2549 static const unsigned int msiof2_sync_mux[] = {
2550 	MSIOF2_SYNC_MARK,
2551 };
2552 static const unsigned int msiof2_ss1_pins[] = {
2553 	/* SS1 */
2554 	RCAR_GP_PIN(1, 2),
2555 };
2556 static const unsigned int msiof2_ss1_mux[] = {
2557 	MSIOF2_SS1_MARK,
2558 };
2559 static const unsigned int msiof2_ss2_pins[] = {
2560 	/* SS2 */
2561 	RCAR_GP_PIN(1, 3),
2562 };
2563 static const unsigned int msiof2_ss2_mux[] = {
2564 	MSIOF2_SS2_MARK,
2565 };
2566 static const unsigned int msiof2_rx_pins[] = {
2567 	/* RXD */
2568 	RCAR_GP_PIN(0, 30),
2569 };
2570 static const unsigned int msiof2_rx_mux[] = {
2571 	MSIOF2_RXD_MARK,
2572 };
2573 static const unsigned int msiof2_tx_pins[] = {
2574 	/* TXD */
2575 	RCAR_GP_PIN(0, 31),
2576 };
2577 static const unsigned int msiof2_tx_mux[] = {
2578 	MSIOF2_TXD_MARK,
2579 };
2580 static const unsigned int msiof2_clk_b_pins[] = {
2581 	/* SCK */
2582 	RCAR_GP_PIN(3, 15),
2583 };
2584 static const unsigned int msiof2_clk_b_mux[] = {
2585 	MSIOF2_SCK_B_MARK,
2586 };
2587 static const unsigned int msiof2_sync_b_pins[] = {
2588 	/* SYNC */
2589 	RCAR_GP_PIN(3, 16),
2590 };
2591 static const unsigned int msiof2_sync_b_mux[] = {
2592 	MSIOF2_SYNC_B_MARK,
2593 };
2594 static const unsigned int msiof2_ss1_b_pins[] = {
2595 	/* SS1 */
2596 	RCAR_GP_PIN(3, 17),
2597 };
2598 static const unsigned int msiof2_ss1_b_mux[] = {
2599 	MSIOF2_SS1_B_MARK,
2600 };
2601 static const unsigned int msiof2_ss2_b_pins[] = {
2602 	/* SS2 */
2603 	RCAR_GP_PIN(3, 18),
2604 };
2605 static const unsigned int msiof2_ss2_b_mux[] = {
2606 	MSIOF2_SS2_B_MARK,
2607 };
2608 static const unsigned int msiof2_rx_b_pins[] = {
2609 	/* RXD */
2610 	RCAR_GP_PIN(3, 13),
2611 };
2612 static const unsigned int msiof2_rx_b_mux[] = {
2613 	MSIOF2_RXD_B_MARK,
2614 };
2615 static const unsigned int msiof2_tx_b_pins[] = {
2616 	/* TXD */
2617 	RCAR_GP_PIN(3, 14),
2618 };
2619 static const unsigned int msiof2_tx_b_mux[] = {
2620 	MSIOF2_TXD_B_MARK,
2621 };
2622 /* - PWM -------------------------------------------------------------------- */
2623 static const unsigned int pwm0_pins[] = {
2624 	RCAR_GP_PIN(1, 14),
2625 };
2626 static const unsigned int pwm0_mux[] = {
2627 	PWM0_MARK,
2628 };
2629 static const unsigned int pwm0_b_pins[] = {
2630 	RCAR_GP_PIN(5, 3),
2631 };
2632 static const unsigned int pwm0_b_mux[] = {
2633 	PWM0_B_MARK,
2634 };
2635 static const unsigned int pwm1_pins[] = {
2636 	RCAR_GP_PIN(4, 5),
2637 };
2638 static const unsigned int pwm1_mux[] = {
2639 	PWM1_MARK,
2640 };
2641 static const unsigned int pwm1_b_pins[] = {
2642 	RCAR_GP_PIN(5, 10),
2643 };
2644 static const unsigned int pwm1_b_mux[] = {
2645 	PWM1_B_MARK,
2646 };
2647 static const unsigned int pwm1_c_pins[] = {
2648 	RCAR_GP_PIN(1, 18),
2649 };
2650 static const unsigned int pwm1_c_mux[] = {
2651 	PWM1_C_MARK,
2652 };
2653 static const unsigned int pwm2_pins[] = {
2654 	RCAR_GP_PIN(4, 10),
2655 };
2656 static const unsigned int pwm2_mux[] = {
2657 	PWM2_MARK,
2658 };
2659 static const unsigned int pwm2_b_pins[] = {
2660 	RCAR_GP_PIN(5, 17),
2661 };
2662 static const unsigned int pwm2_b_mux[] = {
2663 	PWM2_B_MARK,
2664 };
2665 static const unsigned int pwm2_c_pins[] = {
2666 	RCAR_GP_PIN(0, 13),
2667 };
2668 static const unsigned int pwm2_c_mux[] = {
2669 	PWM2_C_MARK,
2670 };
2671 static const unsigned int pwm3_pins[] = {
2672 	RCAR_GP_PIN(4, 13),
2673 };
2674 static const unsigned int pwm3_mux[] = {
2675 	PWM3_MARK,
2676 };
2677 static const unsigned int pwm3_b_pins[] = {
2678 	RCAR_GP_PIN(0, 16),
2679 };
2680 static const unsigned int pwm3_b_mux[] = {
2681 	PWM3_B_MARK,
2682 };
2683 static const unsigned int pwm4_pins[] = {
2684 	RCAR_GP_PIN(1, 3),
2685 };
2686 static const unsigned int pwm4_mux[] = {
2687 	PWM4_MARK,
2688 };
2689 static const unsigned int pwm4_b_pins[] = {
2690 	RCAR_GP_PIN(0, 21),
2691 };
2692 static const unsigned int pwm4_b_mux[] = {
2693 	PWM4_B_MARK,
2694 };
2695 static const unsigned int pwm5_pins[] = {
2696 	RCAR_GP_PIN(3, 30),
2697 };
2698 static const unsigned int pwm5_mux[] = {
2699 	PWM5_MARK,
2700 };
2701 static const unsigned int pwm5_b_pins[] = {
2702 	RCAR_GP_PIN(4, 0),
2703 };
2704 static const unsigned int pwm5_b_mux[] = {
2705 	PWM5_B_MARK,
2706 };
2707 static const unsigned int pwm5_c_pins[] = {
2708 	RCAR_GP_PIN(0, 10),
2709 };
2710 static const unsigned int pwm5_c_mux[] = {
2711 	PWM5_C_MARK,
2712 };
2713 static const unsigned int pwm6_pins[] = {
2714 	RCAR_GP_PIN(4, 8),
2715 };
2716 static const unsigned int pwm6_mux[] = {
2717 	PWM6_MARK,
2718 };
2719 static const unsigned int pwm6_b_pins[] = {
2720 	RCAR_GP_PIN(0, 7),
2721 };
2722 static const unsigned int pwm6_b_mux[] = {
2723 	PWM6_B_MARK,
2724 };
2725 /* - QSPI ------------------------------------------------------------------- */
2726 static const unsigned int qspi_ctrl_pins[] = {
2727 	/* SPCLK, SSL */
2728 	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 9),
2729 };
2730 static const unsigned int qspi_ctrl_mux[] = {
2731 	SPCLK_MARK, SSL_MARK,
2732 };
2733 static const unsigned int qspi_data_pins[] = {
2734 	/* MOSI_IO0, MISO_IO1, IO2, IO3 */
2735 	RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
2736 	RCAR_GP_PIN(1, 8),
2737 };
2738 static const unsigned int qspi_data_mux[] = {
2739 	MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,
2740 };
2741 /* - SCIF0 ------------------------------------------------------------------ */
2742 static const unsigned int scif0_data_pins[] = {
2743 	/* RX, TX */
2744 	RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
2745 };
2746 static const unsigned int scif0_data_mux[] = {
2747 	SCIF0_RXD_MARK, SCIF0_TXD_MARK,
2748 };
2749 static const unsigned int scif0_data_b_pins[] = {
2750 	/* RX, TX */
2751 	RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12),
2752 };
2753 static const unsigned int scif0_data_b_mux[] = {
2754 	SCIF0_RXD_B_MARK, SCIF0_TXD_B_MARK,
2755 };
2756 static const unsigned int scif0_data_c_pins[] = {
2757 	/* RX, TX */
2758 	RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31),
2759 };
2760 static const unsigned int scif0_data_c_mux[] = {
2761 	SCIF0_RXD_C_MARK, SCIF0_TXD_C_MARK,
2762 };
2763 static const unsigned int scif0_data_d_pins[] = {
2764 	/* RX, TX */
2765 	RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28),
2766 };
2767 static const unsigned int scif0_data_d_mux[] = {
2768 	SCIF0_RXD_D_MARK, SCIF0_TXD_D_MARK,
2769 };
2770 /* - SCIF1 ------------------------------------------------------------------ */
2771 static const unsigned int scif1_data_pins[] = {
2772 	/* RX, TX */
2773 	RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
2774 };
2775 static const unsigned int scif1_data_mux[] = {
2776 	SCIF1_RXD_MARK, SCIF1_TXD_MARK,
2777 };
2778 static const unsigned int scif1_clk_pins[] = {
2779 	/* SCK */
2780 	RCAR_GP_PIN(4, 13),
2781 };
2782 static const unsigned int scif1_clk_mux[] = {
2783 	SCIF1_SCK_MARK,
2784 };
2785 static const unsigned int scif1_data_b_pins[] = {
2786 	/* RX, TX */
2787 	RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 12),
2788 };
2789 static const unsigned int scif1_data_b_mux[] = {
2790 	SCIF1_RXD_B_MARK, SCIF1_TXD_B_MARK,
2791 };
2792 static const unsigned int scif1_clk_b_pins[] = {
2793 	/* SCK */
2794 	RCAR_GP_PIN(5, 10),
2795 };
2796 static const unsigned int scif1_clk_b_mux[] = {
2797 	SCIF1_SCK_B_MARK,
2798 };
2799 static const unsigned int scif1_data_c_pins[] = {
2800 	/* RX, TX */
2801 	RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 12),
2802 };
2803 static const unsigned int scif1_data_c_mux[] = {
2804 	SCIF1_RXD_C_MARK, SCIF1_TXD_C_MARK,
2805 };
2806 static const unsigned int scif1_clk_c_pins[] = {
2807 	/* SCK */
2808 	RCAR_GP_PIN(0, 10),
2809 };
2810 static const unsigned int scif1_clk_c_mux[] = {
2811 	SCIF1_SCK_C_MARK,
2812 };
2813 /* - SCIF2 ------------------------------------------------------------------ */
2814 static const unsigned int scif2_data_pins[] = {
2815 	/* RX, TX */
2816 	RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
2817 };
2818 static const unsigned int scif2_data_mux[] = {
2819 	SCIF2_RXD_MARK, SCIF2_TXD_MARK,
2820 };
2821 static const unsigned int scif2_clk_pins[] = {
2822 	/* SCK */
2823 	RCAR_GP_PIN(4, 18),
2824 };
2825 static const unsigned int scif2_clk_mux[] = {
2826 	SCIF2_SCK_MARK,
2827 };
2828 static const unsigned int scif2_data_b_pins[] = {
2829 	/* RX, TX */
2830 	RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19),
2831 };
2832 static const unsigned int scif2_data_b_mux[] = {
2833 	SCIF2_RXD_B_MARK, SCIF2_TXD_B_MARK,
2834 };
2835 static const unsigned int scif2_clk_b_pins[] = {
2836 	/* SCK */
2837 	RCAR_GP_PIN(5, 17),
2838 };
2839 static const unsigned int scif2_clk_b_mux[] = {
2840 	SCIF2_SCK_B_MARK,
2841 };
2842 static const unsigned int scif2_data_c_pins[] = {
2843 	/* RX, TX */
2844 	RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
2845 };
2846 static const unsigned int scif2_data_c_mux[] = {
2847 	SCIF2_RXD_C_MARK, SCIF2_TXD_C_MARK,
2848 };
2849 static const unsigned int scif2_clk_c_pins[] = {
2850 	/* SCK */
2851 	RCAR_GP_PIN(3, 19),
2852 };
2853 static const unsigned int scif2_clk_c_mux[] = {
2854 	SCIF2_SCK_C_MARK,
2855 };
2856 /* - SCIF3 ------------------------------------------------------------------ */
2857 static const unsigned int scif3_data_pins[] = {
2858 	/* RX, TX */
2859 	RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
2860 };
2861 static const unsigned int scif3_data_mux[] = {
2862 	SCIF3_RXD_MARK, SCIF3_TXD_MARK,
2863 };
2864 static const unsigned int scif3_clk_pins[] = {
2865 	/* SCK */
2866 	RCAR_GP_PIN(4, 19),
2867 };
2868 static const unsigned int scif3_clk_mux[] = {
2869 	SCIF3_SCK_MARK,
2870 };
2871 static const unsigned int scif3_data_b_pins[] = {
2872 	/* RX, TX */
2873 	RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24),
2874 };
2875 static const unsigned int scif3_data_b_mux[] = {
2876 	SCIF3_RXD_B_MARK, SCIF3_TXD_B_MARK,
2877 };
2878 static const unsigned int scif3_clk_b_pins[] = {
2879 	/* SCK */
2880 	RCAR_GP_PIN(3, 22),
2881 };
2882 static const unsigned int scif3_clk_b_mux[] = {
2883 	SCIF3_SCK_B_MARK,
2884 };
2885 /* - SCIF4 ------------------------------------------------------------------ */
2886 static const unsigned int scif4_data_pins[] = {
2887 	/* RX, TX */
2888 	RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
2889 };
2890 static const unsigned int scif4_data_mux[] = {
2891 	SCIF4_RXD_MARK, SCIF4_TXD_MARK,
2892 };
2893 static const unsigned int scif4_data_b_pins[] = {
2894 	/* RX, TX */
2895 	RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
2896 };
2897 static const unsigned int scif4_data_b_mux[] = {
2898 	SCIF4_RXD_B_MARK, SCIF4_TXD_B_MARK,
2899 };
2900 static const unsigned int scif4_data_c_pins[] = {
2901 	/* RX, TX */
2902 	RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
2903 };
2904 static const unsigned int scif4_data_c_mux[] = {
2905 	SCIF4_RXD_C_MARK, SCIF4_TXD_C_MARK,
2906 };
2907 static const unsigned int scif4_data_d_pins[] = {
2908 	/* RX, TX */
2909 	RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18),
2910 };
2911 static const unsigned int scif4_data_d_mux[] = {
2912 	SCIF4_RXD_D_MARK, SCIF4_TXD_D_MARK,
2913 };
2914 static const unsigned int scif4_data_e_pins[] = {
2915 	/* RX, TX */
2916 	RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2),
2917 };
2918 static const unsigned int scif4_data_e_mux[] = {
2919 	SCIF4_RXD_E_MARK, SCIF4_TXD_E_MARK,
2920 };
2921 /* - SCIF5 ------------------------------------------------------------------ */
2922 static const unsigned int scif5_data_pins[] = {
2923 	/* RX, TX */
2924 	RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
2925 };
2926 static const unsigned int scif5_data_mux[] = {
2927 	SCIF5_RXD_MARK, SCIF5_TXD_MARK,
2928 };
2929 static const unsigned int scif5_data_b_pins[] = {
2930 	/* RX, TX */
2931 	RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4),
2932 };
2933 static const unsigned int scif5_data_b_mux[] = {
2934 	SCIF5_RXD_B_MARK, SCIF5_TXD_B_MARK,
2935 };
2936 static const unsigned int scif5_data_c_pins[] = {
2937 	/* RX, TX */
2938 	RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 11),
2939 };
2940 static const unsigned int scif5_data_c_mux[] = {
2941 	SCIF5_RXD_C_MARK, SCIF5_TXD_C_MARK,
2942 };
2943 static const unsigned int scif5_data_d_pins[] = {
2944 	/* RX, TX */
2945 	RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2946 };
2947 static const unsigned int scif5_data_d_mux[] = {
2948 	SCIF5_RXD_D_MARK, SCIF5_TXD_D_MARK,
2949 };
2950 /* - SCIFA0 ----------------------------------------------------------------- */
2951 static const unsigned int scifa0_data_pins[] = {
2952 	/* RXD, TXD */
2953 	RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
2954 };
2955 static const unsigned int scifa0_data_mux[] = {
2956 	SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
2957 };
2958 static const unsigned int scifa0_data_b_pins[] = {
2959 	/* RXD, TXD */
2960 	RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
2961 };
2962 static const unsigned int scifa0_data_b_mux[] = {
2963 	SCIFA0_RXD_B_MARK, SCIFA0_TXD_B_MARK
2964 };
2965 static const unsigned int scifa0_data_c_pins[] = {
2966 	/* RXD, TXD */
2967 	RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
2968 };
2969 static const unsigned int scifa0_data_c_mux[] = {
2970 	SCIFA0_RXD_C_MARK, SCIFA0_TXD_C_MARK
2971 };
2972 static const unsigned int scifa0_data_d_pins[] = {
2973 	/* RXD, TXD */
2974 	RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
2975 };
2976 static const unsigned int scifa0_data_d_mux[] = {
2977 	SCIFA0_RXD_D_MARK, SCIFA0_TXD_D_MARK
2978 };
2979 /* - SCIFA1 ----------------------------------------------------------------- */
2980 static const unsigned int scifa1_data_pins[] = {
2981 	/* RXD, TXD */
2982 	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2983 };
2984 static const unsigned int scifa1_data_mux[] = {
2985 	SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
2986 };
2987 static const unsigned int scifa1_clk_pins[] = {
2988 	/* SCK */
2989 	RCAR_GP_PIN(0, 13),
2990 };
2991 static const unsigned int scifa1_clk_mux[] = {
2992 	SCIFA1_SCK_MARK,
2993 };
2994 static const unsigned int scifa1_data_b_pins[] = {
2995 	/* RXD, TXD */
2996 	RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
2997 };
2998 static const unsigned int scifa1_data_b_mux[] = {
2999 	SCIFA1_RXD_B_MARK, SCIFA1_TXD_B_MARK,
3000 };
3001 static const unsigned int scifa1_clk_b_pins[] = {
3002 	/* SCK */
3003 	RCAR_GP_PIN(4, 27),
3004 };
3005 static const unsigned int scifa1_clk_b_mux[] = {
3006 	SCIFA1_SCK_B_MARK,
3007 };
3008 static const unsigned int scifa1_data_c_pins[] = {
3009 	/* RXD, TXD */
3010 	RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
3011 };
3012 static const unsigned int scifa1_data_c_mux[] = {
3013 	SCIFA1_RXD_C_MARK, SCIFA1_TXD_C_MARK,
3014 };
3015 static const unsigned int scifa1_clk_c_pins[] = {
3016 	/* SCK */
3017 	RCAR_GP_PIN(5, 4),
3018 };
3019 static const unsigned int scifa1_clk_c_mux[] = {
3020 	SCIFA1_SCK_C_MARK,
3021 };
3022 /* - SCIFA2 ----------------------------------------------------------------- */
3023 static const unsigned int scifa2_data_pins[] = {
3024 	/* RXD, TXD */
3025 	RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17),
3026 };
3027 static const unsigned int scifa2_data_mux[] = {
3028 	SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
3029 };
3030 static const unsigned int scifa2_clk_pins[] = {
3031 	/* SCK */
3032 	RCAR_GP_PIN(1, 15),
3033 };
3034 static const unsigned int scifa2_clk_mux[] = {
3035 	SCIFA2_SCK_MARK,
3036 };
3037 static const unsigned int scifa2_data_b_pins[] = {
3038 	/* RXD, TXD */
3039 	RCAR_GP_PIN(4, 31), RCAR_GP_PIN(5, 0),
3040 };
3041 static const unsigned int scifa2_data_b_mux[] = {
3042 	SCIFA2_RXD_B_MARK, SCIFA2_TXD_B_MARK,
3043 };
3044 static const unsigned int scifa2_clk_b_pins[] = {
3045 	/* SCK */
3046 	RCAR_GP_PIN(4, 30),
3047 };
3048 static const unsigned int scifa2_clk_b_mux[] = {
3049 	SCIFA2_SCK_B_MARK,
3050 };
3051 /* - SCIFA3 ----------------------------------------------------------------- */
3052 static const unsigned int scifa3_data_pins[] = {
3053 	/* RXD, TXD */
3054 	RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
3055 };
3056 static const unsigned int scifa3_data_mux[] = {
3057 	SCIFA3_RXD_MARK, SCIFA3_TXD_MARK,
3058 };
3059 static const unsigned int scifa3_clk_pins[] = {
3060 	/* SCK */
3061 	RCAR_GP_PIN(4, 24),
3062 };
3063 static const unsigned int scifa3_clk_mux[] = {
3064 	SCIFA3_SCK_MARK,
3065 };
3066 static const unsigned int scifa3_data_b_pins[] = {
3067 	/* RXD, TXD */
3068 	RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2),
3069 };
3070 static const unsigned int scifa3_data_b_mux[] = {
3071 	SCIFA3_RXD_B_MARK, SCIFA3_TXD_B_MARK,
3072 };
3073 static const unsigned int scifa3_clk_b_pins[] = {
3074 	/* SCK */
3075 	RCAR_GP_PIN(0, 0),
3076 };
3077 static const unsigned int scifa3_clk_b_mux[] = {
3078 	SCIFA3_SCK_B_MARK,
3079 };
3080 /* - SCIFA4 ----------------------------------------------------------------- */
3081 static const unsigned int scifa4_data_pins[] = {
3082 	/* RXD, TXD */
3083 	RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 12),
3084 };
3085 static const unsigned int scifa4_data_mux[] = {
3086 	SCIFA4_RXD_MARK, SCIFA4_TXD_MARK,
3087 };
3088 static const unsigned int scifa4_data_b_pins[] = {
3089 	/* RXD, TXD */
3090 	RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 23),
3091 };
3092 static const unsigned int scifa4_data_b_mux[] = {
3093 	SCIFA4_RXD_B_MARK, SCIFA4_TXD_B_MARK,
3094 };
3095 static const unsigned int scifa4_data_c_pins[] = {
3096 	/* RXD, TXD */
3097 	RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
3098 };
3099 static const unsigned int scifa4_data_c_mux[] = {
3100 	SCIFA4_RXD_C_MARK, SCIFA4_TXD_C_MARK,
3101 };
3102 static const unsigned int scifa4_data_d_pins[] = {
3103 	/* RXD, TXD */
3104 	RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21),
3105 };
3106 static const unsigned int scifa4_data_d_mux[] = {
3107 	SCIFA4_RXD_D_MARK, SCIFA4_TXD_D_MARK,
3108 };
3109 /* - SCIFA5 ----------------------------------------------------------------- */
3110 static const unsigned int scifa5_data_pins[] = {
3111 	/* RXD, TXD */
3112 	RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
3113 };
3114 static const unsigned int scifa5_data_mux[] = {
3115 	SCIFA5_RXD_MARK, SCIFA5_TXD_MARK,
3116 };
3117 static const unsigned int scifa5_data_b_pins[] = {
3118 	/* RXD, TXD */
3119 	RCAR_GP_PIN(0, 28), RCAR_GP_PIN(0, 29),
3120 };
3121 static const unsigned int scifa5_data_b_mux[] = {
3122 	SCIFA5_RXD_B_MARK, SCIFA5_TXD_B_MARK,
3123 };
3124 static const unsigned int scifa5_data_c_pins[] = {
3125 	/* RXD, TXD */
3126 	RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10),
3127 };
3128 static const unsigned int scifa5_data_c_mux[] = {
3129 	SCIFA5_RXD_C_MARK, SCIFA5_TXD_C_MARK,
3130 };
3131 static const unsigned int scifa5_data_d_pins[] = {
3132 	/* RXD, TXD */
3133 	RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
3134 };
3135 static const unsigned int scifa5_data_d_mux[] = {
3136 	SCIFA5_RXD_D_MARK, SCIFA5_TXD_D_MARK,
3137 };
3138 /* - SCIFB0 ----------------------------------------------------------------- */
3139 static const unsigned int scifb0_data_pins[] = {
3140 	/* RXD, TXD */
3141 	RCAR_GP_PIN(0, 21), RCAR_GP_PIN(0, 20),
3142 };
3143 static const unsigned int scifb0_data_mux[] = {
3144 	SCIFB0_RXD_MARK, SCIFB0_TXD_MARK,
3145 };
3146 static const unsigned int scifb0_clk_pins[] = {
3147 	/* SCK */
3148 	RCAR_GP_PIN(0, 19),
3149 };
3150 static const unsigned int scifb0_clk_mux[] = {
3151 	SCIFB0_SCK_MARK,
3152 };
3153 static const unsigned int scifb0_ctrl_pins[] = {
3154 	/* RTS, CTS */
3155 	RCAR_GP_PIN(0, 23), RCAR_GP_PIN(0, 22),
3156 };
3157 static const unsigned int scifb0_ctrl_mux[] = {
3158 	SCIFB0_RTS_N_MARK, SCIFB0_CTS_N_MARK,
3159 };
3160 /* - SCIFB1 ----------------------------------------------------------------- */
3161 static const unsigned int scifb1_data_pins[] = {
3162 	/* RXD, TXD */
3163 	RCAR_GP_PIN(1, 24), RCAR_GP_PIN(0, 17),
3164 };
3165 static const unsigned int scifb1_data_mux[] = {
3166 	SCIFB1_RXD_MARK, SCIFB1_TXD_MARK,
3167 };
3168 static const unsigned int scifb1_clk_pins[] = {
3169 	/* SCK */
3170 	RCAR_GP_PIN(0, 16),
3171 };
3172 static const unsigned int scifb1_clk_mux[] = {
3173 	SCIFB1_SCK_MARK,
3174 };
3175 /* - SCIFB2 ----------------------------------------------------------------- */
3176 static const unsigned int scifb2_data_pins[] = {
3177 	/* RXD, TXD */
3178 	RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
3179 };
3180 static const unsigned int scifb2_data_mux[] = {
3181 	SCIFB2_RXD_MARK, SCIFB2_TXD_MARK,
3182 };
3183 static const unsigned int scifb2_clk_pins[] = {
3184 	/* SCK */
3185 	RCAR_GP_PIN(1, 15),
3186 };
3187 static const unsigned int scifb2_clk_mux[] = {
3188 	SCIFB2_SCK_MARK,
3189 };
3190 static const unsigned int scifb2_ctrl_pins[] = {
3191 	/* RTS, CTS */
3192 	RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
3193 };
3194 static const unsigned int scifb2_ctrl_mux[] = {
3195 	SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK,
3196 };
3197 /* - SCIF Clock ------------------------------------------------------------- */
3198 static const unsigned int scif_clk_pins[] = {
3199 	/* SCIF_CLK */
3200 	RCAR_GP_PIN(1, 23),
3201 };
3202 static const unsigned int scif_clk_mux[] = {
3203 	SCIF_CLK_MARK,
3204 };
3205 static const unsigned int scif_clk_b_pins[] = {
3206 	/* SCIF_CLK */
3207 	RCAR_GP_PIN(3, 29),
3208 };
3209 static const unsigned int scif_clk_b_mux[] = {
3210 	SCIF_CLK_B_MARK,
3211 };
3212 /* - SDHI0 ------------------------------------------------------------------ */
3213 static const unsigned int sdhi0_data_pins[] = {
3214 	/* D[0:3] */
3215 	RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
3216 	RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5),
3217 };
3218 static const unsigned int sdhi0_data_mux[] = {
3219 	SD0_DATA0_MARK, SD0_DATA1_MARK, SD0_DATA2_MARK, SD0_DATA3_MARK,
3220 };
3221 static const unsigned int sdhi0_ctrl_pins[] = {
3222 	/* CLK, CMD */
3223 	RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3224 };
3225 static const unsigned int sdhi0_ctrl_mux[] = {
3226 	SD0_CLK_MARK, SD0_CMD_MARK,
3227 };
3228 static const unsigned int sdhi0_cd_pins[] = {
3229 	/* CD */
3230 	RCAR_GP_PIN(6, 6),
3231 };
3232 static const unsigned int sdhi0_cd_mux[] = {
3233 	SD0_CD_MARK,
3234 };
3235 static const unsigned int sdhi0_wp_pins[] = {
3236 	/* WP */
3237 	RCAR_GP_PIN(6, 7),
3238 };
3239 static const unsigned int sdhi0_wp_mux[] = {
3240 	SD0_WP_MARK,
3241 };
3242 /* - SDHI1 ------------------------------------------------------------------ */
3243 static const unsigned int sdhi1_data_pins[] = {
3244 	/* D[0:3] */
3245 	RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11),
3246 	RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13),
3247 };
3248 static const unsigned int sdhi1_data_mux[] = {
3249 	SD1_DATA0_MARK, SD1_DATA1_MARK, SD1_DATA2_MARK, SD1_DATA3_MARK,
3250 };
3251 static const unsigned int sdhi1_ctrl_pins[] = {
3252 	/* CLK, CMD */
3253 	RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
3254 };
3255 static const unsigned int sdhi1_ctrl_mux[] = {
3256 	SD1_CLK_MARK, SD1_CMD_MARK,
3257 };
3258 static const unsigned int sdhi1_cd_pins[] = {
3259 	/* CD */
3260 	RCAR_GP_PIN(6, 14),
3261 };
3262 static const unsigned int sdhi1_cd_mux[] = {
3263 	SD1_CD_MARK,
3264 };
3265 static const unsigned int sdhi1_wp_pins[] = {
3266 	/* WP */
3267 	RCAR_GP_PIN(6, 15),
3268 };
3269 static const unsigned int sdhi1_wp_mux[] = {
3270 	SD1_WP_MARK,
3271 };
3272 /* - SDHI2 ------------------------------------------------------------------ */
3273 static const unsigned int sdhi2_data_pins[] = {
3274 	/* D[0:3] */
3275 	RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
3276 	RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
3277 };
3278 static const unsigned int sdhi2_data_mux[] = {
3279 	SD2_DATA0_MARK, SD2_DATA1_MARK, SD2_DATA2_MARK, SD2_DATA3_MARK,
3280 };
3281 static const unsigned int sdhi2_ctrl_pins[] = {
3282 	/* CLK, CMD */
3283 	RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17),
3284 };
3285 static const unsigned int sdhi2_ctrl_mux[] = {
3286 	SD2_CLK_MARK, SD2_CMD_MARK,
3287 };
3288 static const unsigned int sdhi2_cd_pins[] = {
3289 	/* CD */
3290 	RCAR_GP_PIN(6, 22),
3291 };
3292 static const unsigned int sdhi2_cd_mux[] = {
3293 	SD2_CD_MARK,
3294 };
3295 static const unsigned int sdhi2_wp_pins[] = {
3296 	/* WP */
3297 	RCAR_GP_PIN(6, 23),
3298 };
3299 static const unsigned int sdhi2_wp_mux[] = {
3300 	SD2_WP_MARK,
3301 };
3302 /* - SSI -------------------------------------------------------------------- */
3303 static const unsigned int ssi0_data_pins[] = {
3304 	/* SDATA0 */
3305 	RCAR_GP_PIN(5, 3),
3306 };
3307 static const unsigned int ssi0_data_mux[] = {
3308 	SSI_SDATA0_MARK,
3309 };
3310 static const unsigned int ssi0129_ctrl_pins[] = {
3311 	/* SCK0129, WS0129 */
3312 	RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
3313 };
3314 static const unsigned int ssi0129_ctrl_mux[] = {
3315 	SSI_SCK0129_MARK, SSI_WS0129_MARK,
3316 };
3317 static const unsigned int ssi1_data_pins[] = {
3318 	/* SDATA1 */
3319 	RCAR_GP_PIN(5, 13),
3320 };
3321 static const unsigned int ssi1_data_mux[] = {
3322 	SSI_SDATA1_MARK,
3323 };
3324 static const unsigned int ssi1_ctrl_pins[] = {
3325 	/* SCK1, WS1 */
3326 	RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 12),
3327 };
3328 static const unsigned int ssi1_ctrl_mux[] = {
3329 	SSI_SCK1_MARK, SSI_WS1_MARK,
3330 };
3331 static const unsigned int ssi1_data_b_pins[] = {
3332 	/* SDATA1 */
3333 	RCAR_GP_PIN(4, 13),
3334 };
3335 static const unsigned int ssi1_data_b_mux[] = {
3336 	SSI_SDATA1_B_MARK,
3337 };
3338 static const unsigned int ssi1_ctrl_b_pins[] = {
3339 	/* SCK1, WS1 */
3340 	RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3341 };
3342 static const unsigned int ssi1_ctrl_b_mux[] = {
3343 	SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
3344 };
3345 static const unsigned int ssi2_data_pins[] = {
3346 	/* SDATA2 */
3347 	RCAR_GP_PIN(5, 16),
3348 };
3349 static const unsigned int ssi2_data_mux[] = {
3350 	SSI_SDATA2_MARK,
3351 };
3352 static const unsigned int ssi2_ctrl_pins[] = {
3353 	/* SCK2, WS2 */
3354 	RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
3355 };
3356 static const unsigned int ssi2_ctrl_mux[] = {
3357 	SSI_SCK2_MARK, SSI_WS2_MARK,
3358 };
3359 static const unsigned int ssi2_data_b_pins[] = {
3360 	/* SDATA2 */
3361 	RCAR_GP_PIN(4, 16),
3362 };
3363 static const unsigned int ssi2_data_b_mux[] = {
3364 	SSI_SDATA2_B_MARK,
3365 };
3366 static const unsigned int ssi2_ctrl_b_pins[] = {
3367 	/* SCK2, WS2 */
3368 	RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
3369 };
3370 static const unsigned int ssi2_ctrl_b_mux[] = {
3371 	SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
3372 };
3373 static const unsigned int ssi3_data_pins[] = {
3374 	/* SDATA3 */
3375 	RCAR_GP_PIN(5, 6),
3376 };
3377 static const unsigned int ssi3_data_mux[] = {
3378 	SSI_SDATA3_MARK
3379 };
3380 static const unsigned int ssi34_ctrl_pins[] = {
3381 	/* SCK34, WS34 */
3382 	RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
3383 };
3384 static const unsigned int ssi34_ctrl_mux[] = {
3385 	SSI_SCK34_MARK, SSI_WS34_MARK,
3386 };
3387 static const unsigned int ssi4_data_pins[] = {
3388 	/* SDATA4 */
3389 	RCAR_GP_PIN(5, 9),
3390 };
3391 static const unsigned int ssi4_data_mux[] = {
3392 	SSI_SDATA4_MARK,
3393 };
3394 static const unsigned int ssi4_ctrl_pins[] = {
3395 	/* SCK4, WS4 */
3396 	RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
3397 };
3398 static const unsigned int ssi4_ctrl_mux[] = {
3399 	SSI_SCK4_MARK, SSI_WS4_MARK,
3400 };
3401 static const unsigned int ssi4_data_b_pins[] = {
3402 	/* SDATA4 */
3403 	RCAR_GP_PIN(4, 22),
3404 };
3405 static const unsigned int ssi4_data_b_mux[] = {
3406 	SSI_SDATA4_B_MARK,
3407 };
3408 static const unsigned int ssi4_ctrl_b_pins[] = {
3409 	/* SCK4, WS4 */
3410 	RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
3411 };
3412 static const unsigned int ssi4_ctrl_b_mux[] = {
3413 	SSI_SCK4_B_MARK, SSI_WS4_B_MARK,
3414 };
3415 static const unsigned int ssi5_data_pins[] = {
3416 	/* SDATA5 */
3417 	RCAR_GP_PIN(4, 26),
3418 };
3419 static const unsigned int ssi5_data_mux[] = {
3420 	SSI_SDATA5_MARK,
3421 };
3422 static const unsigned int ssi5_ctrl_pins[] = {
3423 	/* SCK5, WS5 */
3424 	RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 25),
3425 };
3426 static const unsigned int ssi5_ctrl_mux[] = {
3427 	SSI_SCK5_MARK, SSI_WS5_MARK,
3428 };
3429 static const unsigned int ssi5_data_b_pins[] = {
3430 	/* SDATA5 */
3431 	RCAR_GP_PIN(3, 21),
3432 };
3433 static const unsigned int ssi5_data_b_mux[] = {
3434 	SSI_SDATA5_B_MARK,
3435 };
3436 static const unsigned int ssi5_ctrl_b_pins[] = {
3437 	/* SCK5, WS5 */
3438 	RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20),
3439 };
3440 static const unsigned int ssi5_ctrl_b_mux[] = {
3441 	SSI_SCK5_B_MARK, SSI_WS5_B_MARK,
3442 };
3443 static const unsigned int ssi6_data_pins[] = {
3444 	/* SDATA6 */
3445 	RCAR_GP_PIN(4, 29),
3446 };
3447 static const unsigned int ssi6_data_mux[] = {
3448 	SSI_SDATA6_MARK,
3449 };
3450 static const unsigned int ssi6_ctrl_pins[] = {
3451 	/* SCK6, WS6 */
3452 	RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28),
3453 };
3454 static const unsigned int ssi6_ctrl_mux[] = {
3455 	SSI_SCK6_MARK, SSI_WS6_MARK,
3456 };
3457 static const unsigned int ssi6_data_b_pins[] = {
3458 	/* SDATA6 */
3459 	RCAR_GP_PIN(3, 24),
3460 };
3461 static const unsigned int ssi6_data_b_mux[] = {
3462 	SSI_SDATA6_B_MARK,
3463 };
3464 static const unsigned int ssi6_ctrl_b_pins[] = {
3465 	/* SCK6, WS6 */
3466 	RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23),
3467 };
3468 static const unsigned int ssi6_ctrl_b_mux[] = {
3469 	SSI_SCK6_B_MARK, SSI_WS6_B_MARK,
3470 };
3471 static const unsigned int ssi7_data_pins[] = {
3472 	/* SDATA7 */
3473 	RCAR_GP_PIN(5, 0),
3474 };
3475 static const unsigned int ssi7_data_mux[] = {
3476 	SSI_SDATA7_MARK,
3477 };
3478 static const unsigned int ssi78_ctrl_pins[] = {
3479 	/* SCK78, WS78 */
3480 	RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 31),
3481 };
3482 static const unsigned int ssi78_ctrl_mux[] = {
3483 	SSI_SCK78_MARK, SSI_WS78_MARK,
3484 };
3485 static const unsigned int ssi7_data_b_pins[] = {
3486 	/* SDATA7 */
3487 	RCAR_GP_PIN(3, 27),
3488 };
3489 static const unsigned int ssi7_data_b_mux[] = {
3490 	SSI_SDATA7_B_MARK,
3491 };
3492 static const unsigned int ssi78_ctrl_b_pins[] = {
3493 	/* SCK78, WS78 */
3494 	RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
3495 };
3496 static const unsigned int ssi78_ctrl_b_mux[] = {
3497 	SSI_SCK78_B_MARK, SSI_WS78_B_MARK,
3498 };
3499 static const unsigned int ssi8_data_pins[] = {
3500 	/* SDATA8 */
3501 	RCAR_GP_PIN(5, 10),
3502 };
3503 static const unsigned int ssi8_data_mux[] = {
3504 	SSI_SDATA8_MARK,
3505 };
3506 static const unsigned int ssi8_data_b_pins[] = {
3507 	/* SDATA8 */
3508 	RCAR_GP_PIN(3, 28),
3509 };
3510 static const unsigned int ssi8_data_b_mux[] = {
3511 	SSI_SDATA8_B_MARK,
3512 };
3513 static const unsigned int ssi9_data_pins[] = {
3514 	/* SDATA9 */
3515 	RCAR_GP_PIN(5, 19),
3516 };
3517 static const unsigned int ssi9_data_mux[] = {
3518 	SSI_SDATA9_MARK,
3519 };
3520 static const unsigned int ssi9_ctrl_pins[] = {
3521 	/* SCK9, WS9 */
3522 	RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18),
3523 };
3524 static const unsigned int ssi9_ctrl_mux[] = {
3525 	SSI_SCK9_MARK, SSI_WS9_MARK,
3526 };
3527 static const unsigned int ssi9_data_b_pins[] = {
3528 	/* SDATA9 */
3529 	RCAR_GP_PIN(4, 19),
3530 };
3531 static const unsigned int ssi9_data_b_mux[] = {
3532 	SSI_SDATA9_B_MARK,
3533 };
3534 static const unsigned int ssi9_ctrl_b_pins[] = {
3535 	/* SCK9, WS9 */
3536 	RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18),
3537 };
3538 static const unsigned int ssi9_ctrl_b_mux[] = {
3539 	SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
3540 };
3541 /* - TPU -------------------------------------------------------------------- */
3542 static const unsigned int tpu_to0_pins[] = {
3543 	RCAR_GP_PIN(3, 31),
3544 };
3545 static const unsigned int tpu_to0_mux[] = {
3546 	TPUTO0_MARK,
3547 };
3548 static const unsigned int tpu_to0_b_pins[] = {
3549 	RCAR_GP_PIN(3, 30),
3550 };
3551 static const unsigned int tpu_to0_b_mux[] = {
3552 	TPUTO0_B_MARK,
3553 };
3554 static const unsigned int tpu_to0_c_pins[] = {
3555 	RCAR_GP_PIN(1, 18),
3556 };
3557 static const unsigned int tpu_to0_c_mux[] = {
3558 	TPUTO0_C_MARK,
3559 };
3560 static const unsigned int tpu_to1_pins[] = {
3561 	RCAR_GP_PIN(4, 9),
3562 };
3563 static const unsigned int tpu_to1_mux[] = {
3564 	TPUTO1_MARK,
3565 };
3566 static const unsigned int tpu_to1_b_pins[] = {
3567 	RCAR_GP_PIN(4, 0),
3568 };
3569 static const unsigned int tpu_to1_b_mux[] = {
3570 	TPUTO1_B_MARK,
3571 };
3572 static const unsigned int tpu_to1_c_pins[] = {
3573 	RCAR_GP_PIN(4, 4),
3574 };
3575 static const unsigned int tpu_to1_c_mux[] = {
3576 	TPUTO1_C_MARK,
3577 };
3578 static const unsigned int tpu_to2_pins[] = {
3579 	RCAR_GP_PIN(1, 3),
3580 };
3581 static const unsigned int tpu_to2_mux[] = {
3582 	TPUTO2_MARK,
3583 };
3584 static const unsigned int tpu_to2_b_pins[] = {
3585 	RCAR_GP_PIN(1, 0),
3586 };
3587 static const unsigned int tpu_to2_b_mux[] = {
3588 	TPUTO2_B_MARK,
3589 };
3590 static const unsigned int tpu_to2_c_pins[] = {
3591 	RCAR_GP_PIN(0, 22),
3592 };
3593 static const unsigned int tpu_to2_c_mux[] = {
3594 	TPUTO2_C_MARK,
3595 };
3596 static const unsigned int tpu_to3_pins[] = {
3597 	RCAR_GP_PIN(1, 14),
3598 };
3599 static const unsigned int tpu_to3_mux[] = {
3600 	TPUTO3_MARK,
3601 };
3602 static const unsigned int tpu_to3_b_pins[] = {
3603 	RCAR_GP_PIN(1, 13),
3604 };
3605 static const unsigned int tpu_to3_b_mux[] = {
3606 	TPUTO3_B_MARK,
3607 };
3608 static const unsigned int tpu_to3_c_pins[] = {
3609 	RCAR_GP_PIN(0, 21),
3610 };
3611 static const unsigned int tpu_to3_c_mux[] = {
3612 	TPUTO3_C_MARK,
3613 };
3614 /* - USB0 ------------------------------------------------------------------- */
3615 static const unsigned int usb0_pins[] = {
3616 	RCAR_GP_PIN(5, 24), /* PWEN */
3617 	RCAR_GP_PIN(5, 25), /* OVC */
3618 };
3619 static const unsigned int usb0_mux[] = {
3620 	USB0_PWEN_MARK,
3621 	USB0_OVC_MARK,
3622 };
3623 /* - USB1 ------------------------------------------------------------------- */
3624 static const unsigned int usb1_pins[] = {
3625 	RCAR_GP_PIN(5, 26), /* PWEN */
3626 	RCAR_GP_PIN(5, 27), /* OVC */
3627 };
3628 static const unsigned int usb1_mux[] = {
3629 	USB1_PWEN_MARK,
3630 	USB1_OVC_MARK,
3631 };
3632 /* - VIN0 ------------------------------------------------------------------- */
3633 static const unsigned int vin0_data_pins[] = {
3634 	/* B */
3635 	RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2),
3636 	RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
3637 	RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
3638 	RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8),
3639 	/* G */
3640 	RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
3641 	RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
3642 	RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18),
3643 	RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20),
3644 	/* R */
3645 	RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 22),
3646 	RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24),
3647 	RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
3648 	RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28),
3649 };
3650 static const unsigned int vin0_data_mux[] = {
3651 	/* B */
3652 	VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
3653 	VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
3654 	VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
3655 	VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
3656 	/* G */
3657 	VI0_G0_MARK, VI0_G1_MARK,
3658 	VI0_G2_MARK, VI0_G3_MARK,
3659 	VI0_G4_MARK, VI0_G5_MARK,
3660 	VI0_G6_MARK, VI0_G7_MARK,
3661 	/* R */
3662 	VI0_R0_MARK, VI0_R1_MARK,
3663 	VI0_R2_MARK, VI0_R3_MARK,
3664 	VI0_R4_MARK, VI0_R5_MARK,
3665 	VI0_R6_MARK, VI0_R7_MARK,
3666 };
3667 static const unsigned int vin0_data18_pins[] = {
3668 	/* B */
3669 	RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
3670 	RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
3671 	RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8),
3672 	/* G */
3673 	RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
3674 	RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18),
3675 	RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20),
3676 	/* R */
3677 	RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24),
3678 	RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
3679 	RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28),
3680 };
3681 static const unsigned int vin0_data18_mux[] = {
3682 	/* B */
3683 	VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
3684 	VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
3685 	VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
3686 	/* G */
3687 	VI0_G2_MARK, VI0_G3_MARK,
3688 	VI0_G4_MARK, VI0_G5_MARK,
3689 	VI0_G6_MARK, VI0_G7_MARK,
3690 	/* R */
3691 	VI0_R2_MARK, VI0_R3_MARK,
3692 	VI0_R4_MARK, VI0_R5_MARK,
3693 	VI0_R6_MARK, VI0_R7_MARK,
3694 };
3695 static const unsigned int vin0_sync_pins[] = {
3696 	RCAR_GP_PIN(3, 11), /* HSYNC */
3697 	RCAR_GP_PIN(3, 12), /* VSYNC */
3698 };
3699 static const unsigned int vin0_sync_mux[] = {
3700 	VI0_HSYNC_N_MARK,
3701 	VI0_VSYNC_N_MARK,
3702 };
3703 static const unsigned int vin0_field_pins[] = {
3704 	RCAR_GP_PIN(3, 10),
3705 };
3706 static const unsigned int vin0_field_mux[] = {
3707 	VI0_FIELD_MARK,
3708 };
3709 static const unsigned int vin0_clkenb_pins[] = {
3710 	RCAR_GP_PIN(3, 9),
3711 };
3712 static const unsigned int vin0_clkenb_mux[] = {
3713 	VI0_CLKENB_MARK,
3714 };
3715 static const unsigned int vin0_clk_pins[] = {
3716 	RCAR_GP_PIN(3, 0),
3717 };
3718 static const unsigned int vin0_clk_mux[] = {
3719 	VI0_CLK_MARK,
3720 };
3721 /* - VIN1 ------------------------------------------------------------------- */
3722 static const unsigned int vin1_data_pins[] = {
3723 	RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13),
3724 	RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
3725 	RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 17),
3726 	RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19),
3727 	RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 11),
3728 	RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
3729 };
3730 static const unsigned int vin1_data_mux[] = {
3731 	VI1_DATA0_MARK, VI1_DATA1_MARK,
3732 	VI1_DATA2_MARK, VI1_DATA3_MARK,
3733 	VI1_DATA4_MARK, VI1_DATA5_MARK,
3734 	VI1_DATA6_MARK, VI1_DATA7_MARK,
3735 	VI1_DATA8_MARK, VI1_DATA9_MARK,
3736 	VI1_DATA10_MARK, VI1_DATA11_MARK,
3737 };
3738 static const unsigned int vin1_sync_pins[] = {
3739 	RCAR_GP_PIN(5, 22), /* HSYNC */
3740 	RCAR_GP_PIN(5, 23), /* VSYNC */
3741 };
3742 static const unsigned int vin1_sync_mux[] = {
3743 	VI1_HSYNC_N_MARK,
3744 	VI1_VSYNC_N_MARK,
3745 };
3746 static const unsigned int vin1_field_pins[] = {
3747 	RCAR_GP_PIN(5, 21),
3748 };
3749 static const unsigned int vin1_field_mux[] = {
3750 	VI1_FIELD_MARK,
3751 };
3752 static const unsigned int vin1_clkenb_pins[] = {
3753 	RCAR_GP_PIN(5, 20),
3754 };
3755 static const unsigned int vin1_clkenb_mux[] = {
3756 	VI1_CLKENB_MARK,
3757 };
3758 static const unsigned int vin1_clk_pins[] = {
3759 	RCAR_GP_PIN(5, 11),
3760 };
3761 static const unsigned int vin1_clk_mux[] = {
3762 	VI1_CLK_MARK,
3763 };
3764 
3765 static const struct sh_pfc_pin_group pinmux_groups[] = {
3766 	SH_PFC_PIN_GROUP(audio_clka),
3767 	SH_PFC_PIN_GROUP(audio_clka_b),
3768 	SH_PFC_PIN_GROUP(audio_clka_c),
3769 	SH_PFC_PIN_GROUP(audio_clka_d),
3770 	SH_PFC_PIN_GROUP(audio_clkb),
3771 	SH_PFC_PIN_GROUP(audio_clkb_b),
3772 	SH_PFC_PIN_GROUP(audio_clkb_c),
3773 	SH_PFC_PIN_GROUP(audio_clkc),
3774 	SH_PFC_PIN_GROUP(audio_clkc_b),
3775 	SH_PFC_PIN_GROUP(audio_clkc_c),
3776 	SH_PFC_PIN_GROUP(audio_clkout),
3777 	SH_PFC_PIN_GROUP(audio_clkout_b),
3778 	SH_PFC_PIN_GROUP(audio_clkout_c),
3779 	SH_PFC_PIN_GROUP(avb_link),
3780 	SH_PFC_PIN_GROUP(avb_magic),
3781 	SH_PFC_PIN_GROUP(avb_phy_int),
3782 	SH_PFC_PIN_GROUP(avb_mdio),
3783 	SH_PFC_PIN_GROUP(avb_mii),
3784 	SH_PFC_PIN_GROUP(avb_gmii),
3785 	SH_PFC_PIN_GROUP(can0_data),
3786 	SH_PFC_PIN_GROUP(can0_data_b),
3787 	SH_PFC_PIN_GROUP(can0_data_c),
3788 	SH_PFC_PIN_GROUP(can0_data_d),
3789 	SH_PFC_PIN_GROUP(can1_data),
3790 	SH_PFC_PIN_GROUP(can1_data_b),
3791 	SH_PFC_PIN_GROUP(can1_data_c),
3792 	SH_PFC_PIN_GROUP(can1_data_d),
3793 	SH_PFC_PIN_GROUP(can_clk),
3794 	SH_PFC_PIN_GROUP(can_clk_b),
3795 	SH_PFC_PIN_GROUP(can_clk_c),
3796 	SH_PFC_PIN_GROUP(can_clk_d),
3797 	SH_PFC_PIN_GROUP(du0_rgb666),
3798 	SH_PFC_PIN_GROUP(du0_rgb888),
3799 	SH_PFC_PIN_GROUP(du0_clk0_out),
3800 	SH_PFC_PIN_GROUP(du0_clk1_out),
3801 	SH_PFC_PIN_GROUP(du0_clk_in),
3802 	SH_PFC_PIN_GROUP(du0_sync),
3803 	SH_PFC_PIN_GROUP(du0_oddf),
3804 	SH_PFC_PIN_GROUP(du0_cde),
3805 	SH_PFC_PIN_GROUP(du0_disp),
3806 	SH_PFC_PIN_GROUP(du1_rgb666),
3807 	SH_PFC_PIN_GROUP(du1_rgb888),
3808 	SH_PFC_PIN_GROUP(du1_clk0_out),
3809 	SH_PFC_PIN_GROUP(du1_clk1_out),
3810 	SH_PFC_PIN_GROUP(du1_clk_in),
3811 	SH_PFC_PIN_GROUP(du1_sync),
3812 	SH_PFC_PIN_GROUP(du1_oddf),
3813 	SH_PFC_PIN_GROUP(du1_cde),
3814 	SH_PFC_PIN_GROUP(du1_disp),
3815 	SH_PFC_PIN_GROUP(eth_link),
3816 	SH_PFC_PIN_GROUP(eth_magic),
3817 	SH_PFC_PIN_GROUP(eth_mdio),
3818 	SH_PFC_PIN_GROUP(eth_rmii),
3819 	SH_PFC_PIN_GROUP(eth_link_b),
3820 	SH_PFC_PIN_GROUP(eth_magic_b),
3821 	SH_PFC_PIN_GROUP(eth_mdio_b),
3822 	SH_PFC_PIN_GROUP(eth_rmii_b),
3823 	SH_PFC_PIN_GROUP(hscif0_data),
3824 	SH_PFC_PIN_GROUP(hscif0_clk),
3825 	SH_PFC_PIN_GROUP(hscif0_ctrl),
3826 	SH_PFC_PIN_GROUP(hscif0_data_b),
3827 	SH_PFC_PIN_GROUP(hscif0_clk_b),
3828 	SH_PFC_PIN_GROUP(hscif1_data),
3829 	SH_PFC_PIN_GROUP(hscif1_clk),
3830 	SH_PFC_PIN_GROUP(hscif1_ctrl),
3831 	SH_PFC_PIN_GROUP(hscif1_data_b),
3832 	SH_PFC_PIN_GROUP(hscif1_ctrl_b),
3833 	SH_PFC_PIN_GROUP(hscif2_data),
3834 	SH_PFC_PIN_GROUP(hscif2_clk),
3835 	SH_PFC_PIN_GROUP(hscif2_ctrl),
3836 	SH_PFC_PIN_GROUP(i2c0),
3837 	SH_PFC_PIN_GROUP(i2c0_b),
3838 	SH_PFC_PIN_GROUP(i2c0_c),
3839 	SH_PFC_PIN_GROUP(i2c0_d),
3840 	SH_PFC_PIN_GROUP(i2c0_e),
3841 	SH_PFC_PIN_GROUP(i2c1),
3842 	SH_PFC_PIN_GROUP(i2c1_b),
3843 	SH_PFC_PIN_GROUP(i2c1_c),
3844 	SH_PFC_PIN_GROUP(i2c1_d),
3845 	SH_PFC_PIN_GROUP(i2c1_e),
3846 	SH_PFC_PIN_GROUP(i2c2),
3847 	SH_PFC_PIN_GROUP(i2c2_b),
3848 	SH_PFC_PIN_GROUP(i2c2_c),
3849 	SH_PFC_PIN_GROUP(i2c2_d),
3850 	SH_PFC_PIN_GROUP(i2c2_e),
3851 	SH_PFC_PIN_GROUP(i2c3),
3852 	SH_PFC_PIN_GROUP(i2c3_b),
3853 	SH_PFC_PIN_GROUP(i2c3_c),
3854 	SH_PFC_PIN_GROUP(i2c3_d),
3855 	SH_PFC_PIN_GROUP(i2c3_e),
3856 	SH_PFC_PIN_GROUP(i2c4),
3857 	SH_PFC_PIN_GROUP(i2c4_b),
3858 	SH_PFC_PIN_GROUP(i2c4_c),
3859 	SH_PFC_PIN_GROUP(i2c4_d),
3860 	SH_PFC_PIN_GROUP(i2c4_e),
3861 	SH_PFC_PIN_GROUP(i2c5),
3862 	SH_PFC_PIN_GROUP(i2c5_b),
3863 	SH_PFC_PIN_GROUP(i2c5_c),
3864 	SH_PFC_PIN_GROUP(i2c5_d),
3865 	SH_PFC_PIN_GROUP(intc_irq0),
3866 	SH_PFC_PIN_GROUP(intc_irq1),
3867 	SH_PFC_PIN_GROUP(intc_irq2),
3868 	SH_PFC_PIN_GROUP(intc_irq3),
3869 	SH_PFC_PIN_GROUP(intc_irq4),
3870 	SH_PFC_PIN_GROUP(intc_irq5),
3871 	SH_PFC_PIN_GROUP(intc_irq6),
3872 	SH_PFC_PIN_GROUP(intc_irq7),
3873 	SH_PFC_PIN_GROUP(intc_irq8),
3874 	SH_PFC_PIN_GROUP(intc_irq9),
3875 	BUS_DATA_PIN_GROUP(mmc_data, 1),
3876 	BUS_DATA_PIN_GROUP(mmc_data, 4),
3877 	BUS_DATA_PIN_GROUP(mmc_data, 8),
3878 	SH_PFC_PIN_GROUP(mmc_ctrl),
3879 	SH_PFC_PIN_GROUP(msiof0_clk),
3880 	SH_PFC_PIN_GROUP(msiof0_sync),
3881 	SH_PFC_PIN_GROUP(msiof0_ss1),
3882 	SH_PFC_PIN_GROUP(msiof0_ss2),
3883 	SH_PFC_PIN_GROUP(msiof0_rx),
3884 	SH_PFC_PIN_GROUP(msiof0_tx),
3885 	SH_PFC_PIN_GROUP(msiof1_clk),
3886 	SH_PFC_PIN_GROUP(msiof1_sync),
3887 	SH_PFC_PIN_GROUP(msiof1_ss1),
3888 	SH_PFC_PIN_GROUP(msiof1_ss2),
3889 	SH_PFC_PIN_GROUP(msiof1_rx),
3890 	SH_PFC_PIN_GROUP(msiof1_tx),
3891 	SH_PFC_PIN_GROUP(msiof1_clk_b),
3892 	SH_PFC_PIN_GROUP(msiof1_sync_b),
3893 	SH_PFC_PIN_GROUP(msiof1_ss1_b),
3894 	SH_PFC_PIN_GROUP(msiof1_ss2_b),
3895 	SH_PFC_PIN_GROUP(msiof1_rx_b),
3896 	SH_PFC_PIN_GROUP(msiof1_tx_b),
3897 	SH_PFC_PIN_GROUP(msiof2_clk),
3898 	SH_PFC_PIN_GROUP(msiof2_sync),
3899 	SH_PFC_PIN_GROUP(msiof2_ss1),
3900 	SH_PFC_PIN_GROUP(msiof2_ss2),
3901 	SH_PFC_PIN_GROUP(msiof2_rx),
3902 	SH_PFC_PIN_GROUP(msiof2_tx),
3903 	SH_PFC_PIN_GROUP(msiof2_clk_b),
3904 	SH_PFC_PIN_GROUP(msiof2_sync_b),
3905 	SH_PFC_PIN_GROUP(msiof2_ss1_b),
3906 	SH_PFC_PIN_GROUP(msiof2_ss2_b),
3907 	SH_PFC_PIN_GROUP(msiof2_rx_b),
3908 	SH_PFC_PIN_GROUP(msiof2_tx_b),
3909 	SH_PFC_PIN_GROUP(pwm0),
3910 	SH_PFC_PIN_GROUP(pwm0_b),
3911 	SH_PFC_PIN_GROUP(pwm1),
3912 	SH_PFC_PIN_GROUP(pwm1_b),
3913 	SH_PFC_PIN_GROUP(pwm1_c),
3914 	SH_PFC_PIN_GROUP(pwm2),
3915 	SH_PFC_PIN_GROUP(pwm2_b),
3916 	SH_PFC_PIN_GROUP(pwm2_c),
3917 	SH_PFC_PIN_GROUP(pwm3),
3918 	SH_PFC_PIN_GROUP(pwm3_b),
3919 	SH_PFC_PIN_GROUP(pwm4),
3920 	SH_PFC_PIN_GROUP(pwm4_b),
3921 	SH_PFC_PIN_GROUP(pwm5),
3922 	SH_PFC_PIN_GROUP(pwm5_b),
3923 	SH_PFC_PIN_GROUP(pwm5_c),
3924 	SH_PFC_PIN_GROUP(pwm6),
3925 	SH_PFC_PIN_GROUP(pwm6_b),
3926 	SH_PFC_PIN_GROUP(qspi_ctrl),
3927 	BUS_DATA_PIN_GROUP(qspi_data, 2),
3928 	BUS_DATA_PIN_GROUP(qspi_data, 4),
3929 	SH_PFC_PIN_GROUP(scif0_data),
3930 	SH_PFC_PIN_GROUP(scif0_data_b),
3931 	SH_PFC_PIN_GROUP(scif0_data_c),
3932 	SH_PFC_PIN_GROUP(scif0_data_d),
3933 	SH_PFC_PIN_GROUP(scif1_data),
3934 	SH_PFC_PIN_GROUP(scif1_clk),
3935 	SH_PFC_PIN_GROUP(scif1_data_b),
3936 	SH_PFC_PIN_GROUP(scif1_clk_b),
3937 	SH_PFC_PIN_GROUP(scif1_data_c),
3938 	SH_PFC_PIN_GROUP(scif1_clk_c),
3939 	SH_PFC_PIN_GROUP(scif2_data),
3940 	SH_PFC_PIN_GROUP(scif2_clk),
3941 	SH_PFC_PIN_GROUP(scif2_data_b),
3942 	SH_PFC_PIN_GROUP(scif2_clk_b),
3943 	SH_PFC_PIN_GROUP(scif2_data_c),
3944 	SH_PFC_PIN_GROUP(scif2_clk_c),
3945 	SH_PFC_PIN_GROUP(scif3_data),
3946 	SH_PFC_PIN_GROUP(scif3_clk),
3947 	SH_PFC_PIN_GROUP(scif3_data_b),
3948 	SH_PFC_PIN_GROUP(scif3_clk_b),
3949 	SH_PFC_PIN_GROUP(scif4_data),
3950 	SH_PFC_PIN_GROUP(scif4_data_b),
3951 	SH_PFC_PIN_GROUP(scif4_data_c),
3952 	SH_PFC_PIN_GROUP(scif4_data_d),
3953 	SH_PFC_PIN_GROUP(scif4_data_e),
3954 	SH_PFC_PIN_GROUP(scif5_data),
3955 	SH_PFC_PIN_GROUP(scif5_data_b),
3956 	SH_PFC_PIN_GROUP(scif5_data_c),
3957 	SH_PFC_PIN_GROUP(scif5_data_d),
3958 	SH_PFC_PIN_GROUP(scifa0_data),
3959 	SH_PFC_PIN_GROUP(scifa0_data_b),
3960 	SH_PFC_PIN_GROUP(scifa0_data_c),
3961 	SH_PFC_PIN_GROUP(scifa0_data_d),
3962 	SH_PFC_PIN_GROUP(scifa1_data),
3963 	SH_PFC_PIN_GROUP(scifa1_clk),
3964 	SH_PFC_PIN_GROUP(scifa1_data_b),
3965 	SH_PFC_PIN_GROUP(scifa1_clk_b),
3966 	SH_PFC_PIN_GROUP(scifa1_data_c),
3967 	SH_PFC_PIN_GROUP(scifa1_clk_c),
3968 	SH_PFC_PIN_GROUP(scifa2_data),
3969 	SH_PFC_PIN_GROUP(scifa2_clk),
3970 	SH_PFC_PIN_GROUP(scifa2_data_b),
3971 	SH_PFC_PIN_GROUP(scifa2_clk_b),
3972 	SH_PFC_PIN_GROUP(scifa3_data),
3973 	SH_PFC_PIN_GROUP(scifa3_clk),
3974 	SH_PFC_PIN_GROUP(scifa3_data_b),
3975 	SH_PFC_PIN_GROUP(scifa3_clk_b),
3976 	SH_PFC_PIN_GROUP(scifa4_data),
3977 	SH_PFC_PIN_GROUP(scifa4_data_b),
3978 	SH_PFC_PIN_GROUP(scifa4_data_c),
3979 	SH_PFC_PIN_GROUP(scifa4_data_d),
3980 	SH_PFC_PIN_GROUP(scifa5_data),
3981 	SH_PFC_PIN_GROUP(scifa5_data_b),
3982 	SH_PFC_PIN_GROUP(scifa5_data_c),
3983 	SH_PFC_PIN_GROUP(scifa5_data_d),
3984 	SH_PFC_PIN_GROUP(scifb0_data),
3985 	SH_PFC_PIN_GROUP(scifb0_clk),
3986 	SH_PFC_PIN_GROUP(scifb0_ctrl),
3987 	SH_PFC_PIN_GROUP(scifb1_data),
3988 	SH_PFC_PIN_GROUP(scifb1_clk),
3989 	SH_PFC_PIN_GROUP(scifb2_data),
3990 	SH_PFC_PIN_GROUP(scifb2_clk),
3991 	SH_PFC_PIN_GROUP(scifb2_ctrl),
3992 	SH_PFC_PIN_GROUP(scif_clk),
3993 	SH_PFC_PIN_GROUP(scif_clk_b),
3994 	BUS_DATA_PIN_GROUP(sdhi0_data, 1),
3995 	BUS_DATA_PIN_GROUP(sdhi0_data, 4),
3996 	SH_PFC_PIN_GROUP(sdhi0_ctrl),
3997 	SH_PFC_PIN_GROUP(sdhi0_cd),
3998 	SH_PFC_PIN_GROUP(sdhi0_wp),
3999 	BUS_DATA_PIN_GROUP(sdhi1_data, 1),
4000 	BUS_DATA_PIN_GROUP(sdhi1_data, 4),
4001 	SH_PFC_PIN_GROUP(sdhi1_ctrl),
4002 	SH_PFC_PIN_GROUP(sdhi1_cd),
4003 	SH_PFC_PIN_GROUP(sdhi1_wp),
4004 	BUS_DATA_PIN_GROUP(sdhi2_data, 1),
4005 	BUS_DATA_PIN_GROUP(sdhi2_data, 4),
4006 	SH_PFC_PIN_GROUP(sdhi2_ctrl),
4007 	SH_PFC_PIN_GROUP(sdhi2_cd),
4008 	SH_PFC_PIN_GROUP(sdhi2_wp),
4009 	SH_PFC_PIN_GROUP(ssi0_data),
4010 	SH_PFC_PIN_GROUP(ssi0129_ctrl),
4011 	SH_PFC_PIN_GROUP(ssi1_data),
4012 	SH_PFC_PIN_GROUP(ssi1_ctrl),
4013 	SH_PFC_PIN_GROUP(ssi1_data_b),
4014 	SH_PFC_PIN_GROUP(ssi1_ctrl_b),
4015 	SH_PFC_PIN_GROUP(ssi2_data),
4016 	SH_PFC_PIN_GROUP(ssi2_ctrl),
4017 	SH_PFC_PIN_GROUP(ssi2_data_b),
4018 	SH_PFC_PIN_GROUP(ssi2_ctrl_b),
4019 	SH_PFC_PIN_GROUP(ssi3_data),
4020 	SH_PFC_PIN_GROUP(ssi34_ctrl),
4021 	SH_PFC_PIN_GROUP(ssi4_data),
4022 	SH_PFC_PIN_GROUP(ssi4_ctrl),
4023 	SH_PFC_PIN_GROUP(ssi4_data_b),
4024 	SH_PFC_PIN_GROUP(ssi4_ctrl_b),
4025 	SH_PFC_PIN_GROUP(ssi5_data),
4026 	SH_PFC_PIN_GROUP(ssi5_ctrl),
4027 	SH_PFC_PIN_GROUP(ssi5_data_b),
4028 	SH_PFC_PIN_GROUP(ssi5_ctrl_b),
4029 	SH_PFC_PIN_GROUP(ssi6_data),
4030 	SH_PFC_PIN_GROUP(ssi6_ctrl),
4031 	SH_PFC_PIN_GROUP(ssi6_data_b),
4032 	SH_PFC_PIN_GROUP(ssi6_ctrl_b),
4033 	SH_PFC_PIN_GROUP(ssi7_data),
4034 	SH_PFC_PIN_GROUP(ssi78_ctrl),
4035 	SH_PFC_PIN_GROUP(ssi7_data_b),
4036 	SH_PFC_PIN_GROUP(ssi78_ctrl_b),
4037 	SH_PFC_PIN_GROUP(ssi8_data),
4038 	SH_PFC_PIN_GROUP(ssi8_data_b),
4039 	SH_PFC_PIN_GROUP(ssi9_data),
4040 	SH_PFC_PIN_GROUP(ssi9_ctrl),
4041 	SH_PFC_PIN_GROUP(ssi9_data_b),
4042 	SH_PFC_PIN_GROUP(ssi9_ctrl_b),
4043 	SH_PFC_PIN_GROUP(tpu_to0),
4044 	SH_PFC_PIN_GROUP(tpu_to0_b),
4045 	SH_PFC_PIN_GROUP(tpu_to0_c),
4046 	SH_PFC_PIN_GROUP(tpu_to1),
4047 	SH_PFC_PIN_GROUP(tpu_to1_b),
4048 	SH_PFC_PIN_GROUP(tpu_to1_c),
4049 	SH_PFC_PIN_GROUP(tpu_to2),
4050 	SH_PFC_PIN_GROUP(tpu_to2_b),
4051 	SH_PFC_PIN_GROUP(tpu_to2_c),
4052 	SH_PFC_PIN_GROUP(tpu_to3),
4053 	SH_PFC_PIN_GROUP(tpu_to3_b),
4054 	SH_PFC_PIN_GROUP(tpu_to3_c),
4055 	SH_PFC_PIN_GROUP(usb0),
4056 	SH_PFC_PIN_GROUP(usb1),
4057 	BUS_DATA_PIN_GROUP(vin0_data, 24),
4058 	BUS_DATA_PIN_GROUP(vin0_data, 20),
4059 	SH_PFC_PIN_GROUP(vin0_data18),
4060 	BUS_DATA_PIN_GROUP(vin0_data, 16),
4061 	BUS_DATA_PIN_GROUP(vin0_data, 12),
4062 	BUS_DATA_PIN_GROUP(vin0_data, 10),
4063 	BUS_DATA_PIN_GROUP(vin0_data, 8),
4064 	SH_PFC_PIN_GROUP(vin0_sync),
4065 	SH_PFC_PIN_GROUP(vin0_field),
4066 	SH_PFC_PIN_GROUP(vin0_clkenb),
4067 	SH_PFC_PIN_GROUP(vin0_clk),
4068 	BUS_DATA_PIN_GROUP(vin1_data, 12),
4069 	BUS_DATA_PIN_GROUP(vin1_data, 10),
4070 	BUS_DATA_PIN_GROUP(vin1_data, 8),
4071 	SH_PFC_PIN_GROUP(vin1_sync),
4072 	SH_PFC_PIN_GROUP(vin1_field),
4073 	SH_PFC_PIN_GROUP(vin1_clkenb),
4074 	SH_PFC_PIN_GROUP(vin1_clk),
4075 };
4076 
4077 static const char * const audio_clk_groups[] = {
4078 	"audio_clka",
4079 	"audio_clka_b",
4080 	"audio_clka_c",
4081 	"audio_clka_d",
4082 	"audio_clkb",
4083 	"audio_clkb_b",
4084 	"audio_clkb_c",
4085 	"audio_clkc",
4086 	"audio_clkc_b",
4087 	"audio_clkc_c",
4088 	"audio_clkout",
4089 	"audio_clkout_b",
4090 	"audio_clkout_c",
4091 };
4092 
4093 static const char * const avb_groups[] = {
4094 	"avb_link",
4095 	"avb_magic",
4096 	"avb_phy_int",
4097 	"avb_mdio",
4098 	"avb_mii",
4099 	"avb_gmii",
4100 };
4101 
4102 static const char * const can0_groups[] = {
4103 	"can0_data",
4104 	"can0_data_b",
4105 	"can0_data_c",
4106 	"can0_data_d",
4107 	/*
4108 	 * Retained for backwards compatibility, use can_clk_groups in new
4109 	 * designs.
4110 	 */
4111 	"can_clk",
4112 	"can_clk_b",
4113 	"can_clk_c",
4114 	"can_clk_d",
4115 };
4116 
4117 static const char * const can1_groups[] = {
4118 	"can1_data",
4119 	"can1_data_b",
4120 	"can1_data_c",
4121 	"can1_data_d",
4122 	/*
4123 	 * Retained for backwards compatibility, use can_clk_groups in new
4124 	 * designs.
4125 	 */
4126 	"can_clk",
4127 	"can_clk_b",
4128 	"can_clk_c",
4129 	"can_clk_d",
4130 };
4131 
4132 /*
4133  * can_clk_groups allows for independent configuration, use can_clk function
4134  * in new designs.
4135  */
4136 static const char * const can_clk_groups[] = {
4137 	"can_clk",
4138 	"can_clk_b",
4139 	"can_clk_c",
4140 	"can_clk_d",
4141 };
4142 
4143 static const char * const du0_groups[] = {
4144 	"du0_rgb666",
4145 	"du0_rgb888",
4146 	"du0_clk0_out",
4147 	"du0_clk1_out",
4148 	"du0_clk_in",
4149 	"du0_sync",
4150 	"du0_oddf",
4151 	"du0_cde",
4152 	"du0_disp",
4153 };
4154 
4155 static const char * const du1_groups[] = {
4156 	"du1_rgb666",
4157 	"du1_rgb888",
4158 	"du1_clk0_out",
4159 	"du1_clk1_out",
4160 	"du1_clk_in",
4161 	"du1_sync",
4162 	"du1_oddf",
4163 	"du1_cde",
4164 	"du1_disp",
4165 };
4166 
4167 static const char * const eth_groups[] = {
4168 	"eth_link",
4169 	"eth_magic",
4170 	"eth_mdio",
4171 	"eth_rmii",
4172 	"eth_link_b",
4173 	"eth_magic_b",
4174 	"eth_mdio_b",
4175 	"eth_rmii_b",
4176 };
4177 
4178 static const char * const hscif0_groups[] = {
4179 	"hscif0_data",
4180 	"hscif0_clk",
4181 	"hscif0_ctrl",
4182 	"hscif0_data_b",
4183 	"hscif0_clk_b",
4184 };
4185 
4186 static const char * const hscif1_groups[] = {
4187 	"hscif1_data",
4188 	"hscif1_clk",
4189 	"hscif1_ctrl",
4190 	"hscif1_data_b",
4191 	"hscif1_ctrl_b",
4192 };
4193 
4194 static const char * const hscif2_groups[] = {
4195 	"hscif2_data",
4196 	"hscif2_clk",
4197 	"hscif2_ctrl",
4198 };
4199 
4200 static const char * const i2c0_groups[] = {
4201 	"i2c0",
4202 	"i2c0_b",
4203 	"i2c0_c",
4204 	"i2c0_d",
4205 	"i2c0_e",
4206 };
4207 
4208 static const char * const i2c1_groups[] = {
4209 	"i2c1",
4210 	"i2c1_b",
4211 	"i2c1_c",
4212 	"i2c1_d",
4213 	"i2c1_e",
4214 };
4215 
4216 static const char * const i2c2_groups[] = {
4217 	"i2c2",
4218 	"i2c2_b",
4219 	"i2c2_c",
4220 	"i2c2_d",
4221 	"i2c2_e",
4222 };
4223 
4224 static const char * const i2c3_groups[] = {
4225 	"i2c3",
4226 	"i2c3_b",
4227 	"i2c3_c",
4228 	"i2c3_d",
4229 	"i2c3_e",
4230 };
4231 
4232 static const char * const i2c4_groups[] = {
4233 	"i2c4",
4234 	"i2c4_b",
4235 	"i2c4_c",
4236 	"i2c4_d",
4237 	"i2c4_e",
4238 };
4239 
4240 static const char * const i2c5_groups[] = {
4241 	"i2c5",
4242 	"i2c5_b",
4243 	"i2c5_c",
4244 	"i2c5_d",
4245 };
4246 
4247 static const char * const intc_groups[] = {
4248 	"intc_irq0",
4249 	"intc_irq1",
4250 	"intc_irq2",
4251 	"intc_irq3",
4252 	"intc_irq4",
4253 	"intc_irq5",
4254 	"intc_irq6",
4255 	"intc_irq7",
4256 	"intc_irq8",
4257 	"intc_irq9",
4258 };
4259 
4260 static const char * const mmc_groups[] = {
4261 	"mmc_data1",
4262 	"mmc_data4",
4263 	"mmc_data8",
4264 	"mmc_ctrl",
4265 };
4266 
4267 static const char * const msiof0_groups[] = {
4268 	"msiof0_clk",
4269 	"msiof0_sync",
4270 	"msiof0_ss1",
4271 	"msiof0_ss2",
4272 	"msiof0_rx",
4273 	"msiof0_tx",
4274 };
4275 
4276 static const char * const msiof1_groups[] = {
4277 	"msiof1_clk",
4278 	"msiof1_sync",
4279 	"msiof1_ss1",
4280 	"msiof1_ss2",
4281 	"msiof1_rx",
4282 	"msiof1_tx",
4283 	"msiof1_clk_b",
4284 	"msiof1_sync_b",
4285 	"msiof1_ss1_b",
4286 	"msiof1_ss2_b",
4287 	"msiof1_rx_b",
4288 	"msiof1_tx_b",
4289 };
4290 
4291 static const char * const msiof2_groups[] = {
4292 	"msiof2_clk",
4293 	"msiof2_sync",
4294 	"msiof2_ss1",
4295 	"msiof2_ss2",
4296 	"msiof2_rx",
4297 	"msiof2_tx",
4298 	"msiof2_clk_b",
4299 	"msiof2_sync_b",
4300 	"msiof2_ss1_b",
4301 	"msiof2_ss2_b",
4302 	"msiof2_rx_b",
4303 	"msiof2_tx_b",
4304 };
4305 
4306 static const char * const pwm0_groups[] = {
4307 	"pwm0",
4308 	"pwm0_b",
4309 };
4310 
4311 static const char * const pwm1_groups[] = {
4312 	"pwm1",
4313 	"pwm1_b",
4314 	"pwm1_c",
4315 };
4316 
4317 static const char * const pwm2_groups[] = {
4318 	"pwm2",
4319 	"pwm2_b",
4320 	"pwm2_c",
4321 };
4322 
4323 static const char * const pwm3_groups[] = {
4324 	"pwm3",
4325 	"pwm3_b",
4326 };
4327 
4328 static const char * const pwm4_groups[] = {
4329 	"pwm4",
4330 	"pwm4_b",
4331 };
4332 
4333 static const char * const pwm5_groups[] = {
4334 	"pwm5",
4335 	"pwm5_b",
4336 	"pwm5_c",
4337 };
4338 
4339 static const char * const pwm6_groups[] = {
4340 	"pwm6",
4341 	"pwm6_b",
4342 };
4343 
4344 static const char * const qspi_groups[] = {
4345 	"qspi_ctrl",
4346 	"qspi_data2",
4347 	"qspi_data4",
4348 };
4349 
4350 static const char * const scif0_groups[] = {
4351 	"scif0_data",
4352 	"scif0_data_b",
4353 	"scif0_data_c",
4354 	"scif0_data_d",
4355 };
4356 
4357 static const char * const scif1_groups[] = {
4358 	"scif1_data",
4359 	"scif1_clk",
4360 	"scif1_data_b",
4361 	"scif1_clk_b",
4362 	"scif1_data_c",
4363 	"scif1_clk_c",
4364 };
4365 
4366 static const char * const scif2_groups[] = {
4367 	"scif2_data",
4368 	"scif2_clk",
4369 	"scif2_data_b",
4370 	"scif2_clk_b",
4371 	"scif2_data_c",
4372 	"scif2_clk_c",
4373 };
4374 
4375 static const char * const scif3_groups[] = {
4376 	"scif3_data",
4377 	"scif3_clk",
4378 	"scif3_data_b",
4379 	"scif3_clk_b",
4380 };
4381 
4382 static const char * const scif4_groups[] = {
4383 	"scif4_data",
4384 	"scif4_data_b",
4385 	"scif4_data_c",
4386 	"scif4_data_d",
4387 	"scif4_data_e",
4388 };
4389 
4390 static const char * const scif5_groups[] = {
4391 	"scif5_data",
4392 	"scif5_data_b",
4393 	"scif5_data_c",
4394 	"scif5_data_d",
4395 };
4396 
4397 static const char * const scifa0_groups[] = {
4398 	"scifa0_data",
4399 	"scifa0_data_b",
4400 	"scifa0_data_c",
4401 	"scifa0_data_d",
4402 };
4403 
4404 static const char * const scifa1_groups[] = {
4405 	"scifa1_data",
4406 	"scifa1_clk",
4407 	"scifa1_data_b",
4408 	"scifa1_clk_b",
4409 	"scifa1_data_c",
4410 	"scifa1_clk_c",
4411 };
4412 
4413 static const char * const scifa2_groups[] = {
4414 	"scifa2_data",
4415 	"scifa2_clk",
4416 	"scifa2_data_b",
4417 	"scifa2_clk_b",
4418 };
4419 
4420 static const char * const scifa3_groups[] = {
4421 	"scifa3_data",
4422 	"scifa3_clk",
4423 	"scifa3_data_b",
4424 	"scifa3_clk_b",
4425 };
4426 
4427 static const char * const scifa4_groups[] = {
4428 	"scifa4_data",
4429 	"scifa4_data_b",
4430 	"scifa4_data_c",
4431 	"scifa4_data_d",
4432 };
4433 
4434 static const char * const scifa5_groups[] = {
4435 	"scifa5_data",
4436 	"scifa5_data_b",
4437 	"scifa5_data_c",
4438 	"scifa5_data_d",
4439 };
4440 
4441 static const char * const scifb0_groups[] = {
4442 	"scifb0_data",
4443 	"scifb0_clk",
4444 	"scifb0_ctrl",
4445 };
4446 
4447 static const char * const scifb1_groups[] = {
4448 	"scifb1_data",
4449 	"scifb1_clk",
4450 };
4451 
4452 static const char * const scifb2_groups[] = {
4453 	"scifb2_data",
4454 	"scifb2_clk",
4455 	"scifb2_ctrl",
4456 };
4457 
4458 static const char * const scif_clk_groups[] = {
4459 	"scif_clk",
4460 	"scif_clk_b",
4461 };
4462 
4463 static const char * const sdhi0_groups[] = {
4464 	"sdhi0_data1",
4465 	"sdhi0_data4",
4466 	"sdhi0_ctrl",
4467 	"sdhi0_cd",
4468 	"sdhi0_wp",
4469 };
4470 
4471 static const char * const sdhi1_groups[] = {
4472 	"sdhi1_data1",
4473 	"sdhi1_data4",
4474 	"sdhi1_ctrl",
4475 	"sdhi1_cd",
4476 	"sdhi1_wp",
4477 };
4478 
4479 static const char * const sdhi2_groups[] = {
4480 	"sdhi2_data1",
4481 	"sdhi2_data4",
4482 	"sdhi2_ctrl",
4483 	"sdhi2_cd",
4484 	"sdhi2_wp",
4485 };
4486 
4487 static const char * const ssi_groups[] = {
4488 	"ssi0_data",
4489 	"ssi0129_ctrl",
4490 	"ssi1_data",
4491 	"ssi1_ctrl",
4492 	"ssi1_data_b",
4493 	"ssi1_ctrl_b",
4494 	"ssi2_data",
4495 	"ssi2_ctrl",
4496 	"ssi2_data_b",
4497 	"ssi2_ctrl_b",
4498 	"ssi3_data",
4499 	"ssi34_ctrl",
4500 	"ssi4_data",
4501 	"ssi4_ctrl",
4502 	"ssi4_data_b",
4503 	"ssi4_ctrl_b",
4504 	"ssi5_data",
4505 	"ssi5_ctrl",
4506 	"ssi5_data_b",
4507 	"ssi5_ctrl_b",
4508 	"ssi6_data",
4509 	"ssi6_ctrl",
4510 	"ssi6_data_b",
4511 	"ssi6_ctrl_b",
4512 	"ssi7_data",
4513 	"ssi78_ctrl",
4514 	"ssi7_data_b",
4515 	"ssi78_ctrl_b",
4516 	"ssi8_data",
4517 	"ssi8_data_b",
4518 	"ssi9_data",
4519 	"ssi9_ctrl",
4520 	"ssi9_data_b",
4521 	"ssi9_ctrl_b",
4522 };
4523 
4524 static const char * const tpu_groups[] = {
4525 	"tpu_to0",
4526 	"tpu_to0_b",
4527 	"tpu_to0_c",
4528 	"tpu_to1",
4529 	"tpu_to1_b",
4530 	"tpu_to1_c",
4531 	"tpu_to2",
4532 	"tpu_to2_b",
4533 	"tpu_to2_c",
4534 	"tpu_to3",
4535 	"tpu_to3_b",
4536 	"tpu_to3_c",
4537 };
4538 
4539 static const char * const usb0_groups[] = {
4540 	"usb0",
4541 };
4542 
4543 static const char * const usb1_groups[] = {
4544 	"usb1",
4545 };
4546 
4547 static const char * const vin0_groups[] = {
4548 	"vin0_data24",
4549 	"vin0_data20",
4550 	"vin0_data18",
4551 	"vin0_data16",
4552 	"vin0_data12",
4553 	"vin0_data10",
4554 	"vin0_data8",
4555 	"vin0_sync",
4556 	"vin0_field",
4557 	"vin0_clkenb",
4558 	"vin0_clk",
4559 };
4560 
4561 static const char * const vin1_groups[] = {
4562 	"vin1_data12",
4563 	"vin1_data10",
4564 	"vin1_data8",
4565 	"vin1_sync",
4566 	"vin1_field",
4567 	"vin1_clkenb",
4568 	"vin1_clk",
4569 };
4570 
4571 static const struct sh_pfc_function pinmux_functions[] = {
4572 	SH_PFC_FUNCTION(audio_clk),
4573 	SH_PFC_FUNCTION(avb),
4574 	SH_PFC_FUNCTION(can0),
4575 	SH_PFC_FUNCTION(can1),
4576 	SH_PFC_FUNCTION(can_clk),
4577 	SH_PFC_FUNCTION(du0),
4578 	SH_PFC_FUNCTION(du1),
4579 	SH_PFC_FUNCTION(eth),
4580 	SH_PFC_FUNCTION(hscif0),
4581 	SH_PFC_FUNCTION(hscif1),
4582 	SH_PFC_FUNCTION(hscif2),
4583 	SH_PFC_FUNCTION(i2c0),
4584 	SH_PFC_FUNCTION(i2c1),
4585 	SH_PFC_FUNCTION(i2c2),
4586 	SH_PFC_FUNCTION(i2c3),
4587 	SH_PFC_FUNCTION(i2c4),
4588 	SH_PFC_FUNCTION(i2c5),
4589 	SH_PFC_FUNCTION(intc),
4590 	SH_PFC_FUNCTION(mmc),
4591 	SH_PFC_FUNCTION(msiof0),
4592 	SH_PFC_FUNCTION(msiof1),
4593 	SH_PFC_FUNCTION(msiof2),
4594 	SH_PFC_FUNCTION(pwm0),
4595 	SH_PFC_FUNCTION(pwm1),
4596 	SH_PFC_FUNCTION(pwm2),
4597 	SH_PFC_FUNCTION(pwm3),
4598 	SH_PFC_FUNCTION(pwm4),
4599 	SH_PFC_FUNCTION(pwm5),
4600 	SH_PFC_FUNCTION(pwm6),
4601 	SH_PFC_FUNCTION(qspi),
4602 	SH_PFC_FUNCTION(scif0),
4603 	SH_PFC_FUNCTION(scif1),
4604 	SH_PFC_FUNCTION(scif2),
4605 	SH_PFC_FUNCTION(scif3),
4606 	SH_PFC_FUNCTION(scif4),
4607 	SH_PFC_FUNCTION(scif5),
4608 	SH_PFC_FUNCTION(scifa0),
4609 	SH_PFC_FUNCTION(scifa1),
4610 	SH_PFC_FUNCTION(scifa2),
4611 	SH_PFC_FUNCTION(scifa3),
4612 	SH_PFC_FUNCTION(scifa4),
4613 	SH_PFC_FUNCTION(scifa5),
4614 	SH_PFC_FUNCTION(scifb0),
4615 	SH_PFC_FUNCTION(scifb1),
4616 	SH_PFC_FUNCTION(scifb2),
4617 	SH_PFC_FUNCTION(scif_clk),
4618 	SH_PFC_FUNCTION(sdhi0),
4619 	SH_PFC_FUNCTION(sdhi1),
4620 	SH_PFC_FUNCTION(sdhi2),
4621 	SH_PFC_FUNCTION(ssi),
4622 	SH_PFC_FUNCTION(tpu),
4623 	SH_PFC_FUNCTION(usb0),
4624 	SH_PFC_FUNCTION(usb1),
4625 	SH_PFC_FUNCTION(vin0),
4626 	SH_PFC_FUNCTION(vin1),
4627 };
4628 
4629 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4630 	{ PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1, GROUP(
4631 		GP_0_31_FN, FN_IP2_17_16,
4632 		GP_0_30_FN, FN_IP2_15_14,
4633 		GP_0_29_FN, FN_IP2_13_12,
4634 		GP_0_28_FN, FN_IP2_11_10,
4635 		GP_0_27_FN, FN_IP2_9_8,
4636 		GP_0_26_FN, FN_IP2_7_6,
4637 		GP_0_25_FN, FN_IP2_5_4,
4638 		GP_0_24_FN, FN_IP2_3_2,
4639 		GP_0_23_FN, FN_IP2_1_0,
4640 		GP_0_22_FN, FN_IP1_31_30,
4641 		GP_0_21_FN, FN_IP1_29_28,
4642 		GP_0_20_FN, FN_IP1_27,
4643 		GP_0_19_FN, FN_IP1_26,
4644 		GP_0_18_FN, FN_A2,
4645 		GP_0_17_FN, FN_IP1_24,
4646 		GP_0_16_FN, FN_IP1_23_22,
4647 		GP_0_15_FN, FN_IP1_21_20,
4648 		GP_0_14_FN, FN_IP1_19_18,
4649 		GP_0_13_FN, FN_IP1_17_15,
4650 		GP_0_12_FN, FN_IP1_14_13,
4651 		GP_0_11_FN, FN_IP1_12_11,
4652 		GP_0_10_FN, FN_IP1_10_8,
4653 		GP_0_9_FN, FN_IP1_7_6,
4654 		GP_0_8_FN, FN_IP1_5_4,
4655 		GP_0_7_FN, FN_IP1_3_2,
4656 		GP_0_6_FN, FN_IP1_1_0,
4657 		GP_0_5_FN, FN_IP0_31_30,
4658 		GP_0_4_FN, FN_IP0_29_28,
4659 		GP_0_3_FN, FN_IP0_27_26,
4660 		GP_0_2_FN, FN_IP0_25,
4661 		GP_0_1_FN, FN_IP0_24,
4662 		GP_0_0_FN, FN_IP0_23_22, ))
4663 	},
4664 	{ PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1, GROUP(
4665 		0, 0,
4666 		0, 0,
4667 		0, 0,
4668 		0, 0,
4669 		0, 0,
4670 		0, 0,
4671 		GP_1_25_FN, FN_DACK0,
4672 		GP_1_24_FN, FN_IP7_31,
4673 		GP_1_23_FN, FN_IP4_1_0,
4674 		GP_1_22_FN, FN_WE1_N,
4675 		GP_1_21_FN, FN_WE0_N,
4676 		GP_1_20_FN, FN_IP3_31,
4677 		GP_1_19_FN, FN_IP3_30,
4678 		GP_1_18_FN, FN_IP3_29_27,
4679 		GP_1_17_FN, FN_IP3_26_24,
4680 		GP_1_16_FN, FN_IP3_23_21,
4681 		GP_1_15_FN, FN_IP3_20_18,
4682 		GP_1_14_FN, FN_IP3_17_15,
4683 		GP_1_13_FN, FN_IP3_14_13,
4684 		GP_1_12_FN, FN_IP3_12,
4685 		GP_1_11_FN, FN_IP3_11,
4686 		GP_1_10_FN, FN_IP3_10,
4687 		GP_1_9_FN, FN_IP3_9_8,
4688 		GP_1_8_FN, FN_IP3_7_6,
4689 		GP_1_7_FN, FN_IP3_5_4,
4690 		GP_1_6_FN, FN_IP3_3_2,
4691 		GP_1_5_FN, FN_IP3_1_0,
4692 		GP_1_4_FN, FN_IP2_31_30,
4693 		GP_1_3_FN, FN_IP2_29_27,
4694 		GP_1_2_FN, FN_IP2_26_24,
4695 		GP_1_1_FN, FN_IP2_23_21,
4696 		GP_1_0_FN, FN_IP2_20_18, ))
4697 	},
4698 	{ PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1, GROUP(
4699 		GP_2_31_FN, FN_IP6_7_6,
4700 		GP_2_30_FN, FN_IP6_5_4,
4701 		GP_2_29_FN, FN_IP6_3_2,
4702 		GP_2_28_FN, FN_IP6_1_0,
4703 		GP_2_27_FN, FN_IP5_31_30,
4704 		GP_2_26_FN, FN_IP5_29_28,
4705 		GP_2_25_FN, FN_IP5_27_26,
4706 		GP_2_24_FN, FN_IP5_25_24,
4707 		GP_2_23_FN, FN_IP5_23_22,
4708 		GP_2_22_FN, FN_IP5_21_20,
4709 		GP_2_21_FN, FN_IP5_19_18,
4710 		GP_2_20_FN, FN_IP5_17_16,
4711 		GP_2_19_FN, FN_IP5_15_14,
4712 		GP_2_18_FN, FN_IP5_13_12,
4713 		GP_2_17_FN, FN_IP5_11_9,
4714 		GP_2_16_FN, FN_IP5_8_6,
4715 		GP_2_15_FN, FN_IP5_5_4,
4716 		GP_2_14_FN, FN_IP5_3_2,
4717 		GP_2_13_FN, FN_IP5_1_0,
4718 		GP_2_12_FN, FN_IP4_31_30,
4719 		GP_2_11_FN, FN_IP4_29_28,
4720 		GP_2_10_FN, FN_IP4_27_26,
4721 		GP_2_9_FN, FN_IP4_25_23,
4722 		GP_2_8_FN, FN_IP4_22_20,
4723 		GP_2_7_FN, FN_IP4_19_18,
4724 		GP_2_6_FN, FN_IP4_17_16,
4725 		GP_2_5_FN, FN_IP4_15_14,
4726 		GP_2_4_FN, FN_IP4_13_12,
4727 		GP_2_3_FN, FN_IP4_11_10,
4728 		GP_2_2_FN, FN_IP4_9_8,
4729 		GP_2_1_FN, FN_IP4_7_5,
4730 		GP_2_0_FN, FN_IP4_4_2 ))
4731 	},
4732 	{ PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1, GROUP(
4733 		GP_3_31_FN, FN_IP8_22_20,
4734 		GP_3_30_FN, FN_IP8_19_17,
4735 		GP_3_29_FN, FN_IP8_16_15,
4736 		GP_3_28_FN, FN_IP8_14_12,
4737 		GP_3_27_FN, FN_IP8_11_9,
4738 		GP_3_26_FN, FN_IP8_8_6,
4739 		GP_3_25_FN, FN_IP8_5_3,
4740 		GP_3_24_FN, FN_IP8_2_0,
4741 		GP_3_23_FN, FN_IP7_29_27,
4742 		GP_3_22_FN, FN_IP7_26_24,
4743 		GP_3_21_FN, FN_IP7_23_21,
4744 		GP_3_20_FN, FN_IP7_20_18,
4745 		GP_3_19_FN, FN_IP7_17_15,
4746 		GP_3_18_FN, FN_IP7_14_12,
4747 		GP_3_17_FN, FN_IP7_11_9,
4748 		GP_3_16_FN, FN_IP7_8_6,
4749 		GP_3_15_FN, FN_IP7_5_3,
4750 		GP_3_14_FN, FN_IP7_2_0,
4751 		GP_3_13_FN, FN_IP6_31_29,
4752 		GP_3_12_FN, FN_IP6_28_26,
4753 		GP_3_11_FN, FN_IP6_25_23,
4754 		GP_3_10_FN, FN_IP6_22_20,
4755 		GP_3_9_FN, FN_IP6_19_17,
4756 		GP_3_8_FN, FN_IP6_16,
4757 		GP_3_7_FN, FN_IP6_15,
4758 		GP_3_6_FN, FN_IP6_14,
4759 		GP_3_5_FN, FN_IP6_13,
4760 		GP_3_4_FN, FN_IP6_12,
4761 		GP_3_3_FN, FN_IP6_11,
4762 		GP_3_2_FN, FN_IP6_10,
4763 		GP_3_1_FN, FN_IP6_9,
4764 		GP_3_0_FN, FN_IP6_8 ))
4765 	},
4766 	{ PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1, GROUP(
4767 		GP_4_31_FN, FN_IP11_17_16,
4768 		GP_4_30_FN, FN_IP11_15_14,
4769 		GP_4_29_FN, FN_IP11_13_11,
4770 		GP_4_28_FN, FN_IP11_10_8,
4771 		GP_4_27_FN, FN_IP11_7_6,
4772 		GP_4_26_FN, FN_IP11_5_3,
4773 		GP_4_25_FN, FN_IP11_2_0,
4774 		GP_4_24_FN, FN_IP10_31_30,
4775 		GP_4_23_FN, FN_IP10_29_27,
4776 		GP_4_22_FN, FN_IP10_26_24,
4777 		GP_4_21_FN, FN_IP10_23_21,
4778 		GP_4_20_FN, FN_IP10_20_18,
4779 		GP_4_19_FN, FN_IP10_17_15,
4780 		GP_4_18_FN, FN_IP10_14_12,
4781 		GP_4_17_FN, FN_IP10_11_9,
4782 		GP_4_16_FN, FN_IP10_8_6,
4783 		GP_4_15_FN, FN_IP10_5_3,
4784 		GP_4_14_FN, FN_IP10_2_0,
4785 		GP_4_13_FN, FN_IP9_30_28,
4786 		GP_4_12_FN, FN_IP9_27_25,
4787 		GP_4_11_FN, FN_IP9_24_22,
4788 		GP_4_10_FN, FN_IP9_21_19,
4789 		GP_4_9_FN, FN_IP9_18_17,
4790 		GP_4_8_FN, FN_IP9_16_15,
4791 		GP_4_7_FN, FN_IP9_14_12,
4792 		GP_4_6_FN, FN_IP9_11_9,
4793 		GP_4_5_FN, FN_IP9_8_6,
4794 		GP_4_4_FN, FN_IP9_5_3,
4795 		GP_4_3_FN, FN_IP9_2_0,
4796 		GP_4_2_FN, FN_IP8_31_29,
4797 		GP_4_1_FN, FN_IP8_28_26,
4798 		GP_4_0_FN, FN_IP8_25_23 ))
4799 	},
4800 	{ PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1, GROUP(
4801 		0, 0,
4802 		0, 0,
4803 		0, 0,
4804 		0, 0,
4805 		GP_5_27_FN, FN_USB1_OVC,
4806 		GP_5_26_FN, FN_USB1_PWEN,
4807 		GP_5_25_FN, FN_USB0_OVC,
4808 		GP_5_24_FN, FN_USB0_PWEN,
4809 		GP_5_23_FN, FN_IP13_26_24,
4810 		GP_5_22_FN, FN_IP13_23_21,
4811 		GP_5_21_FN, FN_IP13_20_18,
4812 		GP_5_20_FN, FN_IP13_17_15,
4813 		GP_5_19_FN, FN_IP13_14_12,
4814 		GP_5_18_FN, FN_IP13_11_9,
4815 		GP_5_17_FN, FN_IP13_8_6,
4816 		GP_5_16_FN, FN_IP13_5_3,
4817 		GP_5_15_FN, FN_IP13_2_0,
4818 		GP_5_14_FN, FN_IP12_29_27,
4819 		GP_5_13_FN, FN_IP12_26_24,
4820 		GP_5_12_FN, FN_IP12_23_21,
4821 		GP_5_11_FN, FN_IP12_20_18,
4822 		GP_5_10_FN, FN_IP12_17_15,
4823 		GP_5_9_FN, FN_IP12_14_13,
4824 		GP_5_8_FN, FN_IP12_12_11,
4825 		GP_5_7_FN, FN_IP12_10_9,
4826 		GP_5_6_FN, FN_IP12_8_6,
4827 		GP_5_5_FN, FN_IP12_5_3,
4828 		GP_5_4_FN, FN_IP12_2_0,
4829 		GP_5_3_FN, FN_IP11_29_27,
4830 		GP_5_2_FN, FN_IP11_26_24,
4831 		GP_5_1_FN, FN_IP11_23_21,
4832 		GP_5_0_FN, FN_IP11_20_18 ))
4833 	},
4834 	{ PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1, GROUP(
4835 		0, 0,
4836 		0, 0,
4837 		0, 0,
4838 		0, 0,
4839 		0, 0,
4840 		0, 0,
4841 		GP_6_25_FN, FN_IP0_21_20,
4842 		GP_6_24_FN, FN_IP0_19_18,
4843 		GP_6_23_FN, FN_IP0_17,
4844 		GP_6_22_FN, FN_IP0_16,
4845 		GP_6_21_FN, FN_IP0_15,
4846 		GP_6_20_FN, FN_IP0_14,
4847 		GP_6_19_FN, FN_IP0_13,
4848 		GP_6_18_FN, FN_IP0_12,
4849 		GP_6_17_FN, FN_IP0_11,
4850 		GP_6_16_FN, FN_IP0_10,
4851 		GP_6_15_FN, FN_IP0_9_8,
4852 		GP_6_14_FN, FN_IP0_0,
4853 		GP_6_13_FN, FN_SD1_DATA3,
4854 		GP_6_12_FN, FN_SD1_DATA2,
4855 		GP_6_11_FN, FN_SD1_DATA1,
4856 		GP_6_10_FN, FN_SD1_DATA0,
4857 		GP_6_9_FN, FN_SD1_CMD,
4858 		GP_6_8_FN, FN_SD1_CLK,
4859 		GP_6_7_FN, FN_SD0_WP,
4860 		GP_6_6_FN, FN_SD0_CD,
4861 		GP_6_5_FN, FN_SD0_DATA3,
4862 		GP_6_4_FN, FN_SD0_DATA2,
4863 		GP_6_3_FN, FN_SD0_DATA1,
4864 		GP_6_2_FN, FN_SD0_DATA0,
4865 		GP_6_1_FN, FN_SD0_CMD,
4866 		GP_6_0_FN, FN_SD0_CLK ))
4867 	},
4868 	{ PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
4869 			     GROUP(2, 2, 2, 1, 1, 2, 2, 2, 1, 1, 1, 1,
4870 				   1, 1, 1, 1, 2, -7, 1),
4871 			     GROUP(
4872 		/* IP0_31_30 [2] */
4873 		FN_D5, FN_SCIF4_RXD_B, FN_I2C0_SCL_D, 0,
4874 		/* IP0_29_28 [2] */
4875 		FN_D4, FN_I2C3_SDA_B, FN_SCIF5_TXD_B, 0,
4876 		/* IP0_27_26 [2] */
4877 		FN_D3, FN_I2C3_SCL_B, FN_SCIF5_RXD_B, 0,
4878 		/* IP0_25 [1] */
4879 		FN_D2, FN_SCIFA3_TXD_B,
4880 		/* IP0_24 [1] */
4881 		FN_D1, FN_SCIFA3_RXD_B,
4882 		/* IP0_23_22 [2] */
4883 		FN_D0, FN_SCIFA3_SCK_B, FN_IRQ4, 0,
4884 		/* IP0_21_20 [2] */
4885 		FN_MMC_D7, FN_SCIF0_TXD, FN_I2C2_SDA_B, FN_CAN1_TX,
4886 		/* IP0_19_18 [2] */
4887 		FN_MMC_D6, FN_SCIF0_RXD, FN_I2C2_SCL_B,	FN_CAN1_RX,
4888 		/* IP0_17 [1] */
4889 		FN_MMC_D5, FN_SD2_WP,
4890 		/* IP0_16 [1] */
4891 		FN_MMC_D4, FN_SD2_CD,
4892 		/* IP0_15 [1] */
4893 		FN_MMC_D3, FN_SD2_DATA3,
4894 		/* IP0_14 [1] */
4895 		FN_MMC_D2, FN_SD2_DATA2,
4896 		/* IP0_13 [1] */
4897 		FN_MMC_D1, FN_SD2_DATA1,
4898 		/* IP0_12 [1] */
4899 		FN_MMC_D0, FN_SD2_DATA0,
4900 		/* IP0_11 [1] */
4901 		FN_MMC_CMD, FN_SD2_CMD,
4902 		/* IP0_10 [1] */
4903 		FN_MMC_CLK, FN_SD2_CLK,
4904 		/* IP0_9_8 [2] */
4905 		FN_SD1_WP, FN_IRQ7, FN_CAN0_TX, 0,
4906 		/* IP0_7_1 [7] RESERVED */
4907 		/* IP0_0 [1] */
4908 		FN_SD1_CD, FN_CAN0_RX, ))
4909 	},
4910 	{ PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
4911 			     GROUP(2, 2, 1, 1, -1, 1, 2, 2, 2, 3, 2, 2,
4912 				   3, 2, 2, 2, 2),
4913 			     GROUP(
4914 		/* IP1_31_30 [2] */
4915 		FN_A6, FN_SCIFB0_CTS_N, FN_SCIFA4_RXD_B, FN_TPUTO2_C,
4916 		/* IP1_29_28 [2] */
4917 		FN_A5, FN_SCIFB0_RXD, FN_PWM4_B, FN_TPUTO3_C,
4918 		/* IP1_27 [1] */
4919 		FN_A4, FN_SCIFB0_TXD,
4920 		/* IP1_26 [1] */
4921 		FN_A3, FN_SCIFB0_SCK,
4922 		/* IP1_25 [1] RESERVED */
4923 		/* IP1_24 [1] */
4924 		FN_A1, FN_SCIFB1_TXD,
4925 		/* IP1_23_22 [2] */
4926 		FN_A0, FN_SCIFB1_SCK, FN_PWM3_B, 0,
4927 		/* IP1_21_20 [2] */
4928 		FN_D15, FN_SCIFA1_TXD, FN_I2C5_SDA_B, 0,
4929 		/* IP1_19_18 [2] */
4930 		FN_D14, FN_SCIFA1_RXD, FN_I2C5_SCL_B, 0,
4931 		/* IP1_17_15 [3] */
4932 		FN_D13, FN_SCIFA1_SCK, 0, FN_PWM2_C, FN_TCLK2_B,
4933 		0, 0, 0,
4934 		/* IP1_14_13 [2] */
4935 		FN_D12, FN_HSCIF2_HRTS_N, FN_SCIF1_TXD_C, FN_I2C1_SDA_D,
4936 		/* IP1_12_11 [2] */
4937 		FN_D11, FN_HSCIF2_HCTS_N, FN_SCIF1_RXD_C, FN_I2C1_SCL_D,
4938 		/* IP1_10_8 [3] */
4939 		FN_D10, FN_HSCIF2_HSCK, FN_SCIF1_SCK_C, FN_IRQ6, FN_PWM5_C,
4940 		0, 0, 0,
4941 		/* IP1_7_6 [2] */
4942 		FN_D9, FN_HSCIF2_HTX, FN_I2C1_SDA_B, 0,
4943 		/* IP1_5_4 [2] */
4944 		FN_D8, FN_HSCIF2_HRX, FN_I2C1_SCL_B, 0,
4945 		/* IP1_3_2 [2] */
4946 		FN_D7, FN_IRQ3, FN_TCLK1, FN_PWM6_B,
4947 		/* IP1_1_0 [2] */
4948 		FN_D6, FN_SCIF4_TXD_B, FN_I2C0_SDA_D, 0, ))
4949 	},
4950 	{ PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
4951 			     GROUP(2, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2),
4952 			     GROUP(
4953 		/* IP2_31_30 [2] */
4954 		FN_A20, FN_SPCLK, 0, 0,
4955 		/* IP2_29_27 [3] */
4956 		FN_A19, FN_MSIOF2_SS2, FN_PWM4, FN_TPUTO2,
4957 		0, 0, 0, 0,
4958 		/* IP2_26_24 [3] */
4959 		FN_A18, FN_MSIOF2_SS1, FN_SCIF4_TXD_E, FN_CAN1_TX_B,
4960 		0, 0, 0, 0,
4961 		/* IP2_23_21 [3] */
4962 		FN_A17, FN_MSIOF2_SYNC, FN_SCIF4_RXD_E, FN_CAN1_RX_B,
4963 		0, 0, 0, 0,
4964 		/* IP2_20_18 [3] */
4965 		FN_A16, FN_MSIOF2_SCK, FN_HSCIF0_HSCK_B, FN_SPEEDIN,
4966 		0, FN_CAN_CLK_C, FN_TPUTO2_B, 0,
4967 		/* IP2_17_16 [2] */
4968 		FN_A15, FN_MSIOF2_TXD, FN_HSCIF0_HTX_B, FN_DACK1,
4969 		/* IP2_15_14 [2] */
4970 		FN_A14, FN_MSIOF2_RXD, FN_HSCIF0_HRX_B, FN_DREQ1_N,
4971 		/* IP2_13_12 [2] */
4972 		FN_A13, FN_MSIOF1_SS2, FN_SCIFA5_TXD_B, 0,
4973 		/* IP2_11_10 [2] */
4974 		FN_A12, FN_MSIOF1_SS1, FN_SCIFA5_RXD_B, 0,
4975 		/* IP2_9_8 [2] */
4976 		FN_A11, FN_MSIOF1_SYNC, FN_IIC0_SDA_B, 0,
4977 		/* IP2_7_6 [2] */
4978 		FN_A10, FN_MSIOF1_SCK, FN_IIC0_SCL_B, 0,
4979 		/* IP2_5_4 [2] */
4980 		FN_A9, FN_MSIOF1_TXD, FN_SCIFA0_TXD_B, 0,
4981 		/* IP2_3_2 [2] */
4982 		FN_A8, FN_MSIOF1_RXD, FN_SCIFA0_RXD_B, 0,
4983 		/* IP2_1_0 [2] */
4984 		FN_A7, FN_SCIFB0_RTS_N, FN_SCIFA4_TXD_B, 0, ))
4985 	},
4986 	{ PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
4987 			     GROUP(1, 1, 3, 3, 3, 3, 3, 2, 1, 1, 1, 2,
4988 				   2, 2, 2, 2),
4989 			     GROUP(
4990 		/* IP3_31 [1] */
4991 		FN_RD_WR_N, FN_ATAG1_N,
4992 		/* IP3_30 [1] */
4993 		FN_RD_N, FN_ATACS11_N,
4994 		/* IP3_29_27 [3] */
4995 		FN_BS_N, FN_DRACK0, FN_PWM1_C, FN_TPUTO0_C, FN_ATACS01_N,
4996 		0, 0, 0,
4997 		/* IP3_26_24 [3] */
4998 		FN_EX_CS5_N, FN_SCIFA2_TXD, FN_I2C2_SDA_E, FN_TS_SPSYNC_B,
4999 		0, FN_FMIN, FN_SCIFB2_RTS_N, 0,
5000 		/* IP3_23_21 [3] */
5001 		FN_EX_CS4_N, FN_SCIFA2_RXD, FN_I2C2_SCL_E, FN_TS_SDEN_B,
5002 		0, FN_FMCLK, FN_SCIFB2_CTS_N, 0,
5003 		/* IP3_20_18 [3] */
5004 		FN_EX_CS3_N, FN_SCIFA2_SCK, FN_SCIF4_TXD_C, FN_TS_SCK_B,
5005 		0, FN_BPFCLK, FN_SCIFB2_SCK, 0,
5006 		/* IP3_17_15 [3] */
5007 		FN_EX_CS2_N, FN_PWM0, FN_SCIF4_RXD_C, FN_TS_SDATA_B,
5008 		0, FN_TPUTO3, FN_SCIFB2_TXD, 0,
5009 		/* IP3_14_13 [2] */
5010 		FN_EX_CS1_N, FN_TPUTO3_B, FN_SCIFB2_RXD, FN_VI1_DATA11,
5011 		/* IP3_12 [1] */
5012 		FN_EX_CS0_N, FN_VI1_DATA10,
5013 		/* IP3_11 [1] */
5014 		FN_CS1_N_A26, FN_VI1_DATA9,
5015 		/* IP3_10 [1] */
5016 		FN_CS0_N, FN_VI1_DATA8,
5017 		/* IP3_9_8 [2] */
5018 		FN_A25, FN_SSL, FN_ATARD1_N, 0,
5019 		/* IP3_7_6 [2] */
5020 		FN_A24, FN_IO3, FN_EX_WAIT2, 0,
5021 		/* IP3_5_4 [2] */
5022 		FN_A23, FN_IO2, 0, FN_ATAWR1_N,
5023 		/* IP3_3_2 [2] */
5024 		FN_A22, FN_MISO_IO1, 0, FN_ATADIR1_N,
5025 		/* IP3_1_0 [2] */
5026 		FN_A21, FN_MOSI_IO0, 0, 0, ))
5027 	},
5028 	{ PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
5029 			     GROUP(2, 2, 2, 3, 3, 2, 2, 2, 2, 2, 2, 3, 3, 2),
5030 			     GROUP(
5031 		/* IP4_31_30 [2] */
5032 		FN_DU0_DG4, FN_LCDOUT12, 0, 0,
5033 		/* IP4_29_28 [2] */
5034 		FN_DU0_DG3, FN_LCDOUT11, 0, 0,
5035 		/* IP4_27_26 [2] */
5036 		FN_DU0_DG2, FN_LCDOUT10, 0, 0,
5037 		/* IP4_25_23 [3] */
5038 		FN_DU0_DG1, FN_LCDOUT9, FN_SCIFA0_TXD_C, FN_I2C3_SDA_D,
5039 		0, 0, 0, 0,
5040 		/* IP4_22_20 [3] */
5041 		FN_DU0_DG0, FN_LCDOUT8, FN_SCIFA0_RXD_C, FN_I2C3_SCL_D,
5042 		0, 0, 0, 0,
5043 		/* IP4_19_18 [2] */
5044 		FN_DU0_DR7, FN_LCDOUT23, 0, 0,
5045 		/* IP4_17_16 [2] */
5046 		FN_DU0_DR6, FN_LCDOUT22, 0, 0,
5047 		/* IP4_15_14 [2] */
5048 		FN_DU0_DR5, FN_LCDOUT21, 0, 0,
5049 		/* IP4_13_12 [2] */
5050 		FN_DU0_DR4, FN_LCDOUT20, 0, 0,
5051 		/* IP4_11_10 [2] */
5052 		FN_DU0_DR3, FN_LCDOUT19, 0, 0,
5053 		/* IP4_9_8 [2] */
5054 		FN_DU0_DR2, FN_LCDOUT18, 0, 0,
5055 		/* IP4_7_5 [3] */
5056 		FN_DU0_DR1, FN_LCDOUT17, FN_SCIF5_TXD_C, FN_I2C2_SDA_D,
5057 		0, 0, 0, 0,
5058 		/* IP4_4_2 [3] */
5059 		FN_DU0_DR0, FN_LCDOUT16, FN_SCIF5_RXD_C, FN_I2C2_SCL_D,
5060 		0, 0, 0, 0,
5061 		/* IP4_1_0 [2] */
5062 		FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK, 0, ))
5063 	},
5064 	{ PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
5065 			     GROUP(2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3,
5066 				   2, 2, 2),
5067 			     GROUP(
5068 		/* IP5_31_30 [2] */
5069 		FN_DU0_EXHSYNC_DU0_HSYNC, FN_QSTH_QHS, 0, 0,
5070 		/* IP5_29_28 [2] */
5071 		FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE, 0, 0,
5072 		/* IP5_27_26 [2] */
5073 		FN_DU0_DOTCLKOUT0, FN_QCLK, 0, 0,
5074 		/* IP5_25_24 [2] */
5075 		FN_DU0_DOTCLKIN, FN_QSTVA_QVS, 0, 0,
5076 		/* IP5_23_22 [2] */
5077 		FN_DU0_DB7, FN_LCDOUT7, 0, 0,
5078 		/* IP5_21_20 [2] */
5079 		FN_DU0_DB6, FN_LCDOUT6, 0, 0,
5080 		/* IP5_19_18 [2] */
5081 		FN_DU0_DB5, FN_LCDOUT5, 0, 0,
5082 		/* IP5_17_16 [2] */
5083 		FN_DU0_DB4, FN_LCDOUT4, 0, 0,
5084 		/* IP5_15_14 [2] */
5085 		FN_DU0_DB3, FN_LCDOUT3, 0, 0,
5086 		/* IP5_13_12 [2] */
5087 		FN_DU0_DB2, FN_LCDOUT2, 0, 0,
5088 		/* IP5_11_9 [3] */
5089 		FN_DU0_DB1, FN_LCDOUT1, FN_SCIFA4_TXD_C, FN_I2C4_SDA_D,
5090 		FN_CAN0_TX_C, 0, 0, 0,
5091 		/* IP5_8_6 [3] */
5092 		FN_DU0_DB0, FN_LCDOUT0, FN_SCIFA4_RXD_C, FN_I2C4_SCL_D,
5093 		FN_CAN0_RX_C, 0, 0, 0,
5094 		/* IP5_5_4 [2] */
5095 		FN_DU0_DG7, FN_LCDOUT15, 0, 0,
5096 		/* IP5_3_2 [2] */
5097 		FN_DU0_DG6, FN_LCDOUT14, 0, 0,
5098 		/* IP5_1_0 [2] */
5099 		FN_DU0_DG5, FN_LCDOUT13, 0, 0, ))
5100 	},
5101 	{ PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
5102 			     GROUP(3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1,
5103 				   1, 1, 2, 2, 2, 2),
5104 			     GROUP(
5105 		/* IP6_31_29 [3] */
5106 		FN_ETH_MDIO, FN_VI0_G0, FN_MSIOF2_RXD_B, FN_I2C5_SCL_D,
5107 		FN_AVB_TX_CLK, FN_ADIDATA, 0, 0,
5108 		/* IP6_28_26 [3] */
5109 		FN_VI0_VSYNC_N, FN_SCIF0_TXD_B, FN_I2C0_SDA_C,
5110 		FN_AUDIO_CLKOUT_B, FN_AVB_TX_EN, 0, 0, 0,
5111 		/* IP6_25_23 [3] */
5112 		FN_VI0_HSYNC_N, FN_SCIF0_RXD_B, FN_I2C0_SCL_C, FN_IERX_C,
5113 		FN_AVB_COL, 0, 0, 0,
5114 		/* IP6_22_20 [3] */
5115 		FN_VI0_FIELD, FN_I2C3_SDA, FN_SCIFA5_TXD_C, FN_IECLK_C,
5116 		FN_AVB_RX_ER, 0, 0, 0,
5117 		/* IP6_19_17 [3] */
5118 		FN_VI0_CLKENB, FN_I2C3_SCL, FN_SCIFA5_RXD_C, FN_IETX_C,
5119 		FN_AVB_RXD7, 0, 0, 0,
5120 		/* IP6_16 [1] */
5121 		FN_VI0_DATA7_VI0_B7, FN_AVB_RXD6,
5122 		/* IP6_15 [1] */
5123 		FN_VI0_DATA6_VI0_B6, FN_AVB_RXD5,
5124 		/* IP6_14 [1] */
5125 		FN_VI0_DATA5_VI0_B5, FN_AVB_RXD4,
5126 		/* IP6_13 [1] */
5127 		FN_VI0_DATA4_VI0_B4, FN_AVB_RXD3,
5128 		/* IP6_12 [1] */
5129 		FN_VI0_DATA3_VI0_B3, FN_AVB_RXD2,
5130 		/* IP6_11 [1] */
5131 		FN_VI0_DATA2_VI0_B2, FN_AVB_RXD1,
5132 		/* IP6_10 [1] */
5133 		FN_VI0_DATA1_VI0_B1, FN_AVB_RXD0,
5134 		/* IP6_9 [1] */
5135 		FN_VI0_DATA0_VI0_B0, FN_AVB_RX_DV,
5136 		/* IP6_8 [1] */
5137 		FN_VI0_CLK, FN_AVB_RX_CLK,
5138 		/* IP6_7_6 [2] */
5139 		FN_DU0_CDE, FN_QPOLB, 0, 0,
5140 		/* IP6_5_4 [2] */
5141 		FN_DU0_DISP, FN_QPOLA, 0, 0,
5142 		/* IP6_3_2 [2] */
5143 		FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, 0,
5144 		0,
5145 		/* IP6_1_0 [2] */
5146 		FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, 0, 0, ))
5147 	},
5148 	{ PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
5149 			     GROUP(1, -1, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3),
5150 			     GROUP(
5151 		/* IP7_31 [1] */
5152 		FN_DREQ0_N, FN_SCIFB1_RXD,
5153 		/* IP7_30 [1] RESERVED */
5154 		/* IP7_29_27 [3] */
5155 		FN_ETH_TXD0, FN_VI0_R2, FN_SCIF3_RXD_B, FN_I2C4_SCL_E,
5156 		FN_AVB_GTX_CLK, FN_SSI_WS6_B, 0, 0,
5157 		/* IP7_26_24 [3] */
5158 		FN_ETH_MAGIC, FN_VI0_R1, FN_SCIF3_SCK_B, FN_AVB_TX_ER,
5159 		FN_SSI_SCK6_B, 0, 0, 0,
5160 		/* IP7_23_21 [3] */
5161 		FN_ETH_TX_EN, FN_VI0_R0, FN_SCIF2_TXD_C, FN_IIC0_SDA_D,
5162 		FN_AVB_TXD7, FN_SSI_SDATA5_B, 0, 0,
5163 		/* IP7_20_18 [3] */
5164 		FN_ETH_TXD1, FN_VI0_G7, FN_SCIF2_RXD_C, FN_IIC0_SCL_D,
5165 		FN_AVB_TXD6, FN_SSI_WS5_B, 0, 0,
5166 		/* IP7_17_15 [3] */
5167 		FN_ETH_REFCLK, FN_VI0_G6, FN_SCIF2_SCK_C, FN_AVB_TXD5,
5168 		FN_SSI_SCK5_B, 0, 0, 0,
5169 		/* IP7_14_12 [3] */
5170 		FN_ETH_LINK, FN_VI0_G5, FN_MSIOF2_SS2_B, FN_SCIF4_TXD_D,
5171 		FN_AVB_TXD4, FN_ADICHS2, 0, 0,
5172 		/* IP7_11_9 [3] */
5173 		FN_ETH_RXD1, FN_VI0_G4, FN_MSIOF2_SS1_B, FN_SCIF4_RXD_D,
5174 		FN_AVB_TXD3, FN_ADICHS1, 0, 0,
5175 		/* IP7_8_6 [3] */
5176 		FN_ETH_RXD0, FN_VI0_G3, FN_MSIOF2_SYNC_B, FN_CAN0_TX_B,
5177 		FN_AVB_TXD2, FN_ADICHS0, 0, 0,
5178 		/* IP7_5_3 [3] */
5179 		FN_ETH_RX_ER, FN_VI0_G2, FN_MSIOF2_SCK_B, FN_CAN0_RX_B,
5180 		FN_AVB_TXD1, FN_ADICLK, 0, 0,
5181 		/* IP7_2_0 [3] */
5182 		FN_ETH_CRS_DV, FN_VI0_G1, FN_MSIOF2_TXD_B, FN_I2C5_SDA_D,
5183 		FN_AVB_TXD0, FN_ADICS_SAMP, 0, 0, ))
5184 	},
5185 	{ PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
5186 			     GROUP(3, 3, 3, 3, 3, 2, 3, 3, 3, 3, 3),
5187 			     GROUP(
5188 		/* IP8_31_29 [3] */
5189 		FN_MSIOF0_RXD, FN_SCIF5_RXD, FN_I2C2_SCL_C, FN_DU1_DR2,
5190 		0, FN_TS_SDEN_D, FN_FMCLK_C, 0,
5191 		/* IP8_28_26 [3] */
5192 		FN_I2C1_SDA, FN_SCIF4_TXD, FN_IRQ5, FN_DU1_DR1,
5193 		0, FN_TS_SCK_D, FN_BPFCLK_C, 0,
5194 		/* IP8_25_23 [3] */
5195 		FN_I2C1_SCL, FN_SCIF4_RXD, FN_PWM5_B, FN_DU1_DR0,
5196 		0, FN_TS_SDATA_D, FN_TPUTO1_B, 0,
5197 		/* IP8_22_20 [3] */
5198 		FN_I2C0_SDA, FN_SCIF0_TXD_C, FN_TPUTO0, FN_CAN_CLK,
5199 		FN_DVC_MUTE, FN_CAN1_TX_D, 0, 0,
5200 		/* IP8_19_17 [3] */
5201 		FN_I2C0_SCL, FN_SCIF0_RXD_C, FN_PWM5, FN_TCLK1_B,
5202 		FN_AVB_GTXREFCLK, FN_CAN1_RX_D, FN_TPUTO0_B, 0,
5203 		/* IP8_16_15 [2] */
5204 		FN_HSCIF0_HSCK, FN_SCIF_CLK_B, FN_AVB_CRS, FN_AUDIO_CLKC_B,
5205 		/* IP8_14_12 [3] */
5206 		FN_HSCIF0_HRTS_N, FN_VI0_R7, FN_SCIF0_TXD_D, FN_I2C0_SDA_E,
5207 		FN_AVB_PHY_INT, FN_SSI_SDATA8_B, 0, 0,
5208 		/* IP8_11_9 [3] */
5209 		FN_HSCIF0_HCTS_N, FN_VI0_R6, FN_SCIF0_RXD_D, FN_I2C0_SCL_E,
5210 		FN_AVB_MAGIC, FN_SSI_SDATA7_B, 0, 0,
5211 		/* IP8_8_6 [3] */
5212 		FN_HSCIF0_HTX, FN_VI0_R5, FN_I2C1_SDA_C, FN_AUDIO_CLKB_B,
5213 		FN_AVB_LINK, FN_SSI_WS78_B, 0, 0,
5214 		/* IP8_5_3 [3] */
5215 		FN_HSCIF0_HRX, FN_VI0_R4, FN_I2C1_SCL_C, FN_AUDIO_CLKA_B,
5216 		FN_AVB_MDIO, FN_SSI_SCK78_B, 0, 0,
5217 		/* IP8_2_0 [3] */
5218 		FN_ETH_MDC, FN_VI0_R3, FN_SCIF3_TXD_B, FN_I2C4_SDA_E,
5219 		FN_AVB_MDC, FN_SSI_SDATA6_B, 0, 0, ))
5220 	},
5221 	{ PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
5222 			     GROUP(-1, 3, 3, 3, 3, 2, 2, 3, 3, 3, 3, 3),
5223 			     GROUP(
5224 		/* IP9_31 [1] RESERVED */
5225 		/* IP9_30_28 [3] */
5226 		FN_SCIF1_SCK, FN_PWM3, FN_TCLK2, FN_DU1_DG5,
5227 		FN_SSI_SDATA1_B, 0, 0, 0,
5228 		/* IP9_27_25 [3] */
5229 		FN_HSCIF1_HRTS_N, FN_SCIFA4_TXD, FN_IERX, FN_DU1_DG4,
5230 		FN_SSI_WS1_B, 0, 0, 0,
5231 		/* IP9_24_22 [3] */
5232 		FN_HSCIF1_HCTS_N, FN_SCIFA4_RXD, FN_IECLK, FN_DU1_DG3,
5233 		FN_SSI_SCK1_B, 0, 0, 0,
5234 		/* IP9_21_19 [3] */
5235 		FN_HSCIF1_HSCK, FN_PWM2, FN_IETX, FN_DU1_DG2,
5236 		FN_REMOCON_B, FN_SPEEDIN_B, 0, 0,
5237 		/* IP9_18_17 [2] */
5238 		FN_HSCIF1_HTX, FN_I2C4_SDA, FN_TPUTO1, FN_DU1_DG1,
5239 		/* IP9_16_15 [2] */
5240 		FN_HSCIF1_HRX, FN_I2C4_SCL, FN_PWM6, FN_DU1_DG0,
5241 		/* IP9_14_12 [3] */
5242 		FN_MSIOF0_SS2, FN_SCIFA0_TXD, FN_TS_SPSYNC, FN_DU1_DR7,
5243 		0, FN_FMIN_B, 0, 0,
5244 		/* IP9_11_9 [3] */
5245 		FN_MSIOF0_SS1, FN_SCIFA0_RXD, FN_TS_SDEN, FN_DU1_DR6,
5246 		0, FN_FMCLK_B, 0, 0,
5247 		/* IP9_8_6 [3] */
5248 		FN_MSIOF0_SYNC, FN_PWM1, FN_TS_SCK, FN_DU1_DR5,
5249 		0, FN_BPFCLK_B, 0, 0,
5250 		/* IP9_5_3 [3] */
5251 		FN_MSIOF0_SCK, FN_IRQ0, FN_TS_SDATA, FN_DU1_DR4,
5252 		0, FN_TPUTO1_C, 0, 0,
5253 		/* IP9_2_0 [3] */
5254 		FN_MSIOF0_TXD, FN_SCIF5_TXD, FN_I2C2_SDA_C, FN_DU1_DR3,
5255 		0, FN_TS_SPSYNC_D, FN_FMIN_C, 0, ))
5256 	},
5257 	{ PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32,
5258 			     GROUP(2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3),
5259 			     GROUP(
5260 		/* IP10_31_30 [2] */
5261 		FN_SSI_SCK5, FN_SCIFA3_SCK, FN_DU1_DOTCLKIN, 0,
5262 		/* IP10_29_27 [3] */
5263 		FN_I2C2_SDA, FN_SCIFA5_TXD, FN_DU1_DB7, FN_AUDIO_CLKOUT_C,
5264 		0, 0, 0, 0,
5265 		/* IP10_26_24 [3] */
5266 		FN_I2C2_SCL, FN_SCIFA5_RXD, FN_DU1_DB6, FN_AUDIO_CLKC_C,
5267 		FN_SSI_SDATA4_B, 0, 0, 0,
5268 		/* IP10_23_21 [3] */
5269 		FN_SCIF3_TXD, FN_I2C1_SDA_E, FN_FMIN_D, FN_DU1_DB5,
5270 		FN_AUDIO_CLKB_C, FN_SSI_WS4_B, 0, 0,
5271 		/* IP10_20_18 [3] */
5272 		FN_SCIF3_RXD, FN_I2C1_SCL_E, FN_FMCLK_D, FN_DU1_DB4,
5273 		FN_AUDIO_CLKA_C, FN_SSI_SCK4_B, 0, 0,
5274 		/* IP10_17_15 [3] */
5275 		FN_SCIF3_SCK, FN_IRQ2, FN_BPFCLK_D, FN_DU1_DB3,
5276 		FN_SSI_SDATA9_B, 0, 0, 0,
5277 		/* IP10_14_12 [3] */
5278 		FN_SCIF2_SCK, FN_IRQ1, FN_DU1_DB2, FN_SSI_WS9_B,
5279 		0, 0, 0, 0,
5280 		/* IP10_11_9 [3] */
5281 		FN_SCIF2_TXD, FN_IIC0_SDA, FN_DU1_DB1, FN_SSI_SCK9_B,
5282 		0, 0, 0, 0,
5283 		/* IP10_8_6 [3] */
5284 		FN_SCIF2_RXD, FN_IIC0_SCL, FN_DU1_DB0, FN_SSI_SDATA2_B,
5285 		0, 0, 0, 0,
5286 		/* IP10_5_3 [3] */
5287 		FN_SCIF1_TXD, FN_I2C5_SDA, FN_DU1_DG7, FN_SSI_WS2_B,
5288 		0, 0, 0, 0,
5289 		/* IP10_2_0 [3] */
5290 		FN_SCIF1_RXD, FN_I2C5_SCL, FN_DU1_DG6, FN_SSI_SCK2_B,
5291 		0, 0, 0, 0, ))
5292 	},
5293 	{ PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
5294 			     GROUP(-2, 3, 3, 3, 3, 2, 2, 3, 3, 2, 3, 3),
5295 			     GROUP(
5296 		/* IP11_31_30 [2] RESERVED */
5297 		/* IP11_29_27 [3] */
5298 		FN_SSI_SDATA0, FN_MSIOF1_SCK_B, FN_PWM0_B, FN_ADICLK_B,
5299 		0, 0, 0, 0,
5300 		/* IP11_26_24 [3] */
5301 		FN_SSI_WS0129, FN_MSIOF1_TXD_B, FN_SCIF5_TXD_D, FN_ADICS_SAMP_B,
5302 		0, 0, 0, 0,
5303 		/* IP11_23_21 [3] */
5304 		FN_SSI_SCK0129, FN_MSIOF1_RXD_B, FN_SCIF5_RXD_D, FN_ADIDATA_B,
5305 		0, 0, 0, 0,
5306 		/* IP11_20_18 [3] */
5307 		FN_SSI_SDATA7, FN_SCIFA2_TXD_B, FN_IRQ8, FN_AUDIO_CLKA_D,
5308 		FN_CAN_CLK_D, 0, 0, 0,
5309 		/* IP11_17_16 [2] */
5310 		FN_SSI_WS78, FN_SCIFA2_RXD_B, FN_I2C5_SCL_C, FN_DU1_CDE,
5311 		/* IP11_15_14 [2] */
5312 		FN_SSI_SCK78, FN_SCIFA2_SCK_B, FN_I2C5_SDA_C, FN_DU1_DISP,
5313 		/* IP11_13_11 [3] */
5314 		FN_SSI_SDATA6, FN_SCIFA1_TXD_B, FN_I2C4_SDA_C,
5315 		FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, 0, 0, 0, 0,
5316 		/* IP11_10_8 [3] */
5317 		FN_SSI_WS6, FN_SCIFA1_RXD_B, FN_I2C4_SCL_C,
5318 		FN_DU1_EXVSYNC_DU1_VSYNC, 0, 0, 0, 0,
5319 		/* IP11_7_6 [2] */
5320 		FN_SSI_SCK6, FN_SCIFA1_SCK_B, FN_DU1_EXHSYNC_DU1_HSYNC, 0,
5321 		/* IP11_5_3 [3] */
5322 		FN_SSI_SDATA5, FN_SCIFA3_TXD, FN_I2C3_SDA_C, FN_DU1_DOTCLKOUT1,
5323 		0, 0, 0, 0,
5324 		/* IP11_2_0 [3] */
5325 		FN_SSI_WS5, FN_SCIFA3_RXD, FN_I2C3_SCL_C, FN_DU1_DOTCLKOUT0,
5326 		0, 0, 0, 0, ))
5327 	},
5328 	{ PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
5329 			     GROUP(-2, 3, 3, 3, 3, 3, 2, 2, 2, 3, 3, 3),
5330 			     GROUP(
5331 		/* IP12_31_30 [2] RESERVED */
5332 		/* IP12_29_27 [3] */
5333 		FN_SSI_SCK2, FN_HSCIF1_HTX_B, FN_VI1_DATA2, 0,
5334 		FN_ATAG0_N, FN_ETH_RXD1_B, 0, 0,
5335 		/* IP12_26_24 [3] */
5336 		FN_SSI_SDATA1, FN_HSCIF1_HRX_B, FN_VI1_DATA1, 0,
5337 		FN_ATAWR0_N, FN_ETH_RXD0_B, 0, 0,
5338 		/* IP12_23_21 [3] */
5339 		FN_SSI_WS1, FN_SCIF1_TXD_B, FN_IIC0_SDA_C, FN_VI1_DATA0,
5340 		FN_CAN0_TX_D, 0, FN_ETH_RX_ER_B, 0,
5341 		/* IP12_20_18 [3] */
5342 		FN_SSI_SCK1, FN_SCIF1_RXD_B, FN_IIC0_SCL_C, FN_VI1_CLK,
5343 		FN_CAN0_RX_D, 0, FN_ETH_CRS_DV_B, 0,
5344 		/* IP12_17_15 [3] */
5345 		FN_SSI_SDATA8, FN_SCIF1_SCK_B, FN_PWM1_B, FN_IRQ9,
5346 		FN_REMOCON, FN_DACK2, FN_ETH_MDIO_B, 0,
5347 		/* IP12_14_13 [2] */
5348 		FN_SSI_SDATA4, FN_MLB_DAT, FN_IERX_B, 0,
5349 		/* IP12_12_11 [2] */
5350 		FN_SSI_WS4, FN_MLB_SIG, FN_IECLK_B, 0,
5351 		/* IP12_10_9 [2] */
5352 		FN_SSI_SCK4, FN_MLB_CLK, FN_IETX_B, 0,
5353 		/* IP12_8_6 [3] */
5354 		FN_SSI_SDATA3, FN_MSIOF1_SS2_B, FN_SCIFA1_TXD_C, FN_ADICHS2_B,
5355 		FN_CAN1_TX_C, FN_DREQ2_N, 0, 0,
5356 		/* IP12_5_3 [3] */
5357 		FN_SSI_WS34, FN_MSIOF1_SS1_B, FN_SCIFA1_RXD_C, FN_ADICHS1_B,
5358 		FN_CAN1_RX_C, FN_DACK1_B, 0, 0,
5359 		/* IP12_2_0 [3] */
5360 		FN_SSI_SCK34, FN_MSIOF1_SYNC_B, FN_SCIFA1_SCK_C, FN_ADICHS0_B,
5361 		0, FN_DREQ1_N_B, 0, 0, ))
5362 	},
5363 	{ PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
5364 			     GROUP(-5, 3, 3, 3, 3, 3, 3, 3, 3, 3),
5365 			     GROUP(
5366 		/* IP13_31_27 [5] RESERVED */
5367 		/* IP13_26_24 [3] */
5368 		FN_AUDIO_CLKOUT, FN_I2C4_SDA_B, FN_SCIFA5_TXD_D, FN_VI1_VSYNC_N,
5369 		FN_TS_SPSYNC_C, 0, FN_FMIN_E, 0,
5370 		/* IP13_23_21 [3] */
5371 		FN_AUDIO_CLKC, FN_I2C4_SCL_B, FN_SCIFA5_RXD_D, FN_VI1_HSYNC_N,
5372 		FN_TS_SDEN_C, 0, FN_FMCLK_E, 0,
5373 		/* IP13_20_18 [3] */
5374 		FN_AUDIO_CLKB, FN_I2C0_SDA_B, FN_SCIFA4_TXD_D, FN_VI1_FIELD,
5375 		FN_TS_SCK_C, 0, FN_BPFCLK_E, FN_ETH_MDC_B,
5376 		/* IP13_17_15 [3] */
5377 		FN_AUDIO_CLKA, FN_I2C0_SCL_B, FN_SCIFA4_RXD_D, FN_VI1_CLKENB,
5378 		FN_TS_SDATA_C, 0, FN_ETH_TXD0_B, 0,
5379 		/* IP13_14_12 [3] */
5380 		FN_SSI_SDATA9, FN_SCIF2_TXD_B, FN_I2C3_SDA_E, FN_VI1_DATA7,
5381 		FN_ATADIR0_N, FN_ETH_MAGIC_B, 0, 0,
5382 		/* IP13_11_9 [3] */
5383 		FN_SSI_WS9, FN_SCIF2_RXD_B, FN_I2C3_SCL_E, FN_VI1_DATA6,
5384 		FN_ATARD0_N, FN_ETH_TX_EN_B, 0, 0,
5385 		/* IP13_8_6 [3] */
5386 		FN_SSI_SCK9, FN_SCIF2_SCK_B, FN_PWM2_B, FN_VI1_DATA5,
5387 		0, FN_EX_WAIT1, FN_ETH_TXD1_B, 0,
5388 		/* IP13_5_3 [2] */
5389 		FN_SSI_SDATA2, FN_HSCIF1_HRTS_N_B, FN_SCIFA0_TXD_D,
5390 		FN_VI1_DATA4, 0, FN_ATACS10_N, FN_ETH_REFCLK_B, 0,
5391 		/* IP13_2_0 [3] */
5392 		FN_SSI_WS2, FN_HSCIF1_HCTS_N_B, FN_SCIFA0_RXD_D, FN_VI1_DATA3,
5393 		0, FN_ATACS00_N, FN_ETH_LINK_B, 0, ))
5394 	},
5395 	{ PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
5396 			     GROUP(2, -1, 2, 3, -4, 1, -1,
5397 				   3, 3, 3, 3, 3, 2, -1),
5398 			     GROUP(
5399 		/* SEL_ADG [2] */
5400 		FN_SEL_ADG_0, FN_SEL_ADG_1, FN_SEL_ADG_2, FN_SEL_ADG_3,
5401 		/* RESERVED [1] */
5402 		/* SEL_CAN [2] */
5403 		FN_SEL_CAN_0, FN_SEL_CAN_1, FN_SEL_CAN_2, FN_SEL_CAN_3,
5404 		/* SEL_DARC [3] */
5405 		FN_SEL_DARC_0, FN_SEL_DARC_1, FN_SEL_DARC_2, FN_SEL_DARC_3,
5406 		FN_SEL_DARC_4, 0, 0, 0,
5407 		/* RESERVED [4] */
5408 		/* SEL_ETH [1] */
5409 		FN_SEL_ETH_0, FN_SEL_ETH_1,
5410 		/* RESERVED [1] */
5411 		/* SEL_IC200 [3] */
5412 		FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2, FN_SEL_I2C00_3,
5413 		FN_SEL_I2C00_4, 0, 0, 0,
5414 		/* SEL_I2C01 [3] */
5415 		FN_SEL_I2C01_0, FN_SEL_I2C01_1, FN_SEL_I2C01_2, FN_SEL_I2C01_3,
5416 		FN_SEL_I2C01_4, 0, 0, 0,
5417 		/* SEL_I2C02 [3] */
5418 		FN_SEL_I2C02_0, FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3,
5419 		FN_SEL_I2C02_4, 0, 0, 0,
5420 		/* SEL_I2C03 [3] */
5421 		FN_SEL_I2C03_0, FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3,
5422 		FN_SEL_I2C03_4, 0, 0, 0,
5423 		/* SEL_I2C04 [3] */
5424 		FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2, FN_SEL_I2C04_3,
5425 		FN_SEL_I2C04_4, 0, 0, 0,
5426 		/* SEL_I2C05 [2] */
5427 		FN_SEL_I2C05_0, FN_SEL_I2C05_1, FN_SEL_I2C05_2, FN_SEL_I2C05_3,
5428 		/* RESERVED [1] */ ))
5429 	},
5430 	{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
5431 			     GROUP(2, 2, 1, 1, 1, 1, 1, 1, 2, 2, 1, 1,
5432 				   2, 2, -1, 1, 2, 2, 2, 1, 1, -2),
5433 			     GROUP(
5434 		/* SEL_IEB [2] */
5435 		FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
5436 		/* SEL_IIC0 [2] */
5437 		FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, FN_SEL_IIC0_3,
5438 		/* SEL_LBS [1] */
5439 		FN_SEL_LBS_0, FN_SEL_LBS_1,
5440 		/* SEL_MSI1 [1] */
5441 		FN_SEL_MSI1_0, FN_SEL_MSI1_1,
5442 		/* SEL_MSI2 [1] */
5443 		FN_SEL_MSI2_0, FN_SEL_MSI2_1,
5444 		/* SEL_RAD [1] */
5445 		FN_SEL_RAD_0, FN_SEL_RAD_1,
5446 		/* SEL_RCN [1] */
5447 		FN_SEL_RCN_0, FN_SEL_RCN_1,
5448 		/* SEL_RSP [1] */
5449 		FN_SEL_RSP_0, FN_SEL_RSP_1,
5450 		/* SEL_SCIFA0 [2] */
5451 		FN_SEL_SCIFA0_0, FN_SEL_SCIFA0_1, FN_SEL_SCIFA0_2,
5452 		FN_SEL_SCIFA0_3,
5453 		/* SEL_SCIFA1 [2] */
5454 		FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, 0,
5455 		/* SEL_SCIFA2 [1] */
5456 		FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
5457 		/* SEL_SCIFA3 [1] */
5458 		FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1,
5459 		/* SEL_SCIFA4 [2] */
5460 		FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2,
5461 		FN_SEL_SCIFA4_3,
5462 		/* SEL_SCIFA5 [2] */
5463 		FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2,
5464 		FN_SEL_SCIFA5_3,
5465 		/* RESERVED [1] */
5466 		/* SEL_TMU [1] */
5467 		FN_SEL_TMU_0, FN_SEL_TMU_1,
5468 		/* SEL_TSIF0 [2] */
5469 		FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
5470 		/* SEL_CAN0 [2] */
5471 		FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
5472 		/* SEL_CAN1 [2] */
5473 		FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
5474 		/* SEL_HSCIF0 [1] */
5475 		FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1,
5476 		/* SEL_HSCIF1 [1] */
5477 		FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
5478 		/* RESERVED [2] */ ))
5479 	},
5480 	{ PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
5481 			     GROUP(2, 2, 2, 1, 3, 2, 1, 1, 1, 1, 1, 1,
5482 				   1, 1, -12),
5483 			     GROUP(
5484 		/* SEL_SCIF0 [2] */
5485 		FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
5486 		/* SEL_SCIF1 [2] */
5487 		FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, 0,
5488 		/* SEL_SCIF2 [2] */
5489 		FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, 0,
5490 		/* SEL_SCIF3 [1] */
5491 		FN_SEL_SCIF3_0, FN_SEL_SCIF3_1,
5492 		/* SEL_SCIF4 [3] */
5493 		FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
5494 		FN_SEL_SCIF4_4, 0, 0, 0,
5495 		/* SEL_SCIF5 [2] */
5496 		FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3,
5497 		/* SEL_SSI1 [1] */
5498 		FN_SEL_SSI1_0, FN_SEL_SSI1_1,
5499 		/* SEL_SSI2 [1] */
5500 		FN_SEL_SSI2_0, FN_SEL_SSI2_1,
5501 		/* SEL_SSI4 [1] */
5502 		FN_SEL_SSI4_0, FN_SEL_SSI4_1,
5503 		/* SEL_SSI5 [1] */
5504 		FN_SEL_SSI5_0, FN_SEL_SSI5_1,
5505 		/* SEL_SSI6 [1] */
5506 		FN_SEL_SSI6_0, FN_SEL_SSI6_1,
5507 		/* SEL_SSI7 [1] */
5508 		FN_SEL_SSI7_0, FN_SEL_SSI7_1,
5509 		/* SEL_SSI8 [1] */
5510 		FN_SEL_SSI8_0, FN_SEL_SSI8_1,
5511 		/* SEL_SSI9 [1] */
5512 		FN_SEL_SSI9_0, FN_SEL_SSI9_1,
5513 		/* RESERVED [12] */ ))
5514 	},
5515 	{ /* sentinel */ }
5516 };
5517 
5518 static int r8a7794_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
5519 {
5520 	if (pin < RCAR_GP_PIN(6, 0) || pin > RCAR_GP_PIN(6, 23))
5521 		return -EINVAL;
5522 
5523 	*pocctrl = 0xe606006c;
5524 
5525 	switch (pin & 0x1f) {
5526 	case 6: return 23;
5527 	case 7: return 16;
5528 	case 14: return 15;
5529 	case 15: return 8;
5530 	case 0 ... 5:
5531 	case 8 ... 13:
5532 		return 22 - (pin & 0x1f);
5533 	case 16 ... 23:
5534 		return 47 - (pin & 0x1f);
5535 	}
5536 
5537 	return -EINVAL;
5538 }
5539 
5540 static const struct pinmux_bias_reg pinmux_bias_regs[] = {
5541 	{ PINMUX_BIAS_REG("PUPR0", 0xe6060100, "N/A", 0) {
5542 		[ 0] = RCAR_GP_PIN(0, 0),	/* D0 */
5543 		[ 1] = RCAR_GP_PIN(0, 1),	/* D1 */
5544 		[ 2] = RCAR_GP_PIN(0, 2),	/* D2 */
5545 		[ 3] = RCAR_GP_PIN(0, 3),	/* D3 */
5546 		[ 4] = RCAR_GP_PIN(0, 4),	/* D4 */
5547 		[ 5] = RCAR_GP_PIN(0, 5),	/* D5 */
5548 		[ 6] = RCAR_GP_PIN(0, 6),	/* D6 */
5549 		[ 7] = RCAR_GP_PIN(0, 7),	/* D7 */
5550 		[ 8] = RCAR_GP_PIN(0, 8),	/* D8 */
5551 		[ 9] = RCAR_GP_PIN(0, 9),	/* D9 */
5552 		[10] = RCAR_GP_PIN(0, 10),	/* D10 */
5553 		[11] = RCAR_GP_PIN(0, 11),	/* D11 */
5554 		[12] = RCAR_GP_PIN(0, 12),	/* D12 */
5555 		[13] = RCAR_GP_PIN(0, 13),	/* D13 */
5556 		[14] = RCAR_GP_PIN(0, 14),	/* D14 */
5557 		[15] = RCAR_GP_PIN(0, 15),	/* D15 */
5558 		[16] = RCAR_GP_PIN(0, 16),	/* A0 */
5559 		[17] = RCAR_GP_PIN(0, 17),	/* A1 */
5560 		[18] = RCAR_GP_PIN(0, 18),	/* A2 */
5561 		[19] = RCAR_GP_PIN(0, 19),	/* A3 */
5562 		[20] = RCAR_GP_PIN(0, 20),	/* A4 */
5563 		[21] = RCAR_GP_PIN(0, 21),	/* A5 */
5564 		[22] = RCAR_GP_PIN(0, 22),	/* A6 */
5565 		[23] = RCAR_GP_PIN(0, 23),	/* A7 */
5566 		[24] = RCAR_GP_PIN(0, 24),	/* A8 */
5567 		[25] = RCAR_GP_PIN(0, 25),	/* A9 */
5568 		[26] = RCAR_GP_PIN(0, 26),	/* A10 */
5569 		[27] = RCAR_GP_PIN(0, 27),	/* A11 */
5570 		[28] = RCAR_GP_PIN(0, 28),	/* A12 */
5571 		[29] = RCAR_GP_PIN(0, 29),	/* A13 */
5572 		[30] = RCAR_GP_PIN(0, 30),	/* A14 */
5573 		[31] = RCAR_GP_PIN(0, 31),	/* A15 */
5574 	} },
5575 	{ PINMUX_BIAS_REG("PUPR1", 0xe6060104, "N/A", 0) {
5576 		/* PUPR1 pull-up pins */
5577 		[ 0] = RCAR_GP_PIN(1, 0),	/* A16 */
5578 		[ 1] = RCAR_GP_PIN(1, 1),	/* A17 */
5579 		[ 2] = RCAR_GP_PIN(1, 2),	/* A18 */
5580 		[ 3] = RCAR_GP_PIN(1, 3),	/* A19 */
5581 		[ 4] = RCAR_GP_PIN(1, 4),	/* A20 */
5582 		[ 5] = RCAR_GP_PIN(1, 5),	/* A21 */
5583 		[ 6] = RCAR_GP_PIN(1, 6),	/* A22 */
5584 		[ 7] = RCAR_GP_PIN(1, 7),	/* A23 */
5585 		[ 8] = RCAR_GP_PIN(1, 8),	/* A24 */
5586 		[ 9] = RCAR_GP_PIN(1, 9),	/* A25 */
5587 		[10] = RCAR_GP_PIN(1, 10),	/* CS0# */
5588 		[11] = RCAR_GP_PIN(1, 12),	/* EX_CS0# */
5589 		[12] = RCAR_GP_PIN(1, 14),	/* EX_CS2# */
5590 		[13] = RCAR_GP_PIN(1, 16),	/* EX_CS4# */
5591 		[14] = RCAR_GP_PIN(1, 18),	/* BS# */
5592 		[15] = RCAR_GP_PIN(1, 19),	/* RD# */
5593 		[16] = RCAR_GP_PIN(1, 20),	/* RD/WR# */
5594 		[17] = RCAR_GP_PIN(1, 21),	/* WE0# */
5595 		[18] = RCAR_GP_PIN(1, 22),	/* WE1# */
5596 		[19] = RCAR_GP_PIN(1, 23),	/* EX_WAIT0 */
5597 		[20] = RCAR_GP_PIN(1, 24),	/* DREQ0# */
5598 		[21] = RCAR_GP_PIN(1, 25),	/* DACK0 */
5599 		[22] = PIN_TRST_N,		/* TRST# */
5600 		[23] = PIN_TCK,			/* TCK */
5601 		[24] = PIN_TMS,			/* TMS */
5602 		[25] = PIN_TDI,			/* TDI */
5603 		[26] = RCAR_GP_PIN(1, 11),	/* CS1#/A26 */
5604 		[27] = RCAR_GP_PIN(1, 13),	/* EX_CS1# */
5605 		[28] = RCAR_GP_PIN(1, 15),	/* EX_CS3# */
5606 		[29] = RCAR_GP_PIN(1, 17),	/* EX_CS5# */
5607 		[30] = SH_PFC_PIN_NONE,
5608 		[31] = SH_PFC_PIN_NONE,
5609 	} },
5610 	{ PINMUX_BIAS_REG("N/A", 0, "PUPR1", 0xe6060104) {
5611 		/* PUPR1 pull-down pins */
5612 		[ 0] = SH_PFC_PIN_NONE,
5613 		[ 1] = SH_PFC_PIN_NONE,
5614 		[ 2] = SH_PFC_PIN_NONE,
5615 		[ 3] = SH_PFC_PIN_NONE,
5616 		[ 4] = SH_PFC_PIN_NONE,
5617 		[ 5] = SH_PFC_PIN_NONE,
5618 		[ 6] = SH_PFC_PIN_NONE,
5619 		[ 7] = SH_PFC_PIN_NONE,
5620 		[ 8] = SH_PFC_PIN_NONE,
5621 		[ 9] = SH_PFC_PIN_NONE,
5622 		[10] = SH_PFC_PIN_NONE,
5623 		[11] = SH_PFC_PIN_NONE,
5624 		[12] = SH_PFC_PIN_NONE,
5625 		[13] = SH_PFC_PIN_NONE,
5626 		[14] = SH_PFC_PIN_NONE,
5627 		[15] = SH_PFC_PIN_NONE,
5628 		[16] = SH_PFC_PIN_NONE,
5629 		[17] = SH_PFC_PIN_NONE,
5630 		[18] = SH_PFC_PIN_NONE,
5631 		[19] = SH_PFC_PIN_NONE,
5632 		[20] = SH_PFC_PIN_NONE,
5633 		[21] = SH_PFC_PIN_NONE,
5634 		[22] = SH_PFC_PIN_NONE,
5635 		[23] = SH_PFC_PIN_NONE,
5636 		[24] = SH_PFC_PIN_NONE,
5637 		[25] = SH_PFC_PIN_NONE,
5638 		[26] = SH_PFC_PIN_NONE,
5639 		[27] = SH_PFC_PIN_NONE,
5640 		[28] = SH_PFC_PIN_NONE,
5641 		[29] = SH_PFC_PIN_NONE,
5642 		[30] = PIN_ASEBRK_N_ACK,	/* ASEBRK#/ACK */
5643 		[31] = SH_PFC_PIN_NONE,
5644 	} },
5645 	{ PINMUX_BIAS_REG("PUPR2", 0xe6060108, "N/A", 0) {
5646 		[ 0] = RCAR_GP_PIN(2, 0),	/* DU0_DR0 */
5647 		[ 1] = RCAR_GP_PIN(2, 1),	/* DU0_DR1 */
5648 		[ 2] = RCAR_GP_PIN(2, 2),	/* DU0_DR2 */
5649 		[ 3] = RCAR_GP_PIN(2, 3),	/* DU0_DR3 */
5650 		[ 4] = RCAR_GP_PIN(2, 4),	/* DU0_DR4 */
5651 		[ 5] = RCAR_GP_PIN(2, 5),	/* DU0_DR5 */
5652 		[ 6] = RCAR_GP_PIN(2, 6),	/* DU0_DR6 */
5653 		[ 7] = RCAR_GP_PIN(2, 7),	/* DU0_DR7 */
5654 		[ 8] = RCAR_GP_PIN(2, 8),	/* DU0_DG0 */
5655 		[ 9] = RCAR_GP_PIN(2, 9),	/* DU0_DG1 */
5656 		[10] = RCAR_GP_PIN(2, 10),	/* DU0_DG2 */
5657 		[11] = RCAR_GP_PIN(2, 11),	/* DU0_DG3 */
5658 		[12] = RCAR_GP_PIN(2, 12),	/* DU0_DG4 */
5659 		[13] = RCAR_GP_PIN(2, 13),	/* DU0_DG5 */
5660 		[14] = RCAR_GP_PIN(2, 14),	/* DU0_DG6 */
5661 		[15] = RCAR_GP_PIN(2, 15),	/* DU0_DG7 */
5662 		[16] = RCAR_GP_PIN(2, 16),	/* DU0_DB0 */
5663 		[17] = RCAR_GP_PIN(2, 17),	/* DU0_DB1 */
5664 		[18] = RCAR_GP_PIN(2, 18),	/* DU0_DB2 */
5665 		[19] = RCAR_GP_PIN(2, 19),	/* DU0_DB3 */
5666 		[20] = RCAR_GP_PIN(2, 20),	/* DU0_DB4 */
5667 		[21] = RCAR_GP_PIN(2, 21),	/* DU0_DB5 */
5668 		[22] = RCAR_GP_PIN(2, 22),	/* DU0_DB6 */
5669 		[23] = RCAR_GP_PIN(2, 23),	/* DU0_DB7 */
5670 		[24] = RCAR_GP_PIN(2, 24),	/* DU0_DOTCLKIN */
5671 		[25] = RCAR_GP_PIN(2, 25),	/* DU0_DOTCLKOUT0 */
5672 		[26] = RCAR_GP_PIN(2, 26),	/* DU0_DOTCLKOUT1 */
5673 		[27] = RCAR_GP_PIN(2, 27),	/* DU0_EXHSYNC/DU0_HSYNC */
5674 		[28] = RCAR_GP_PIN(2, 28),	/* DU0_EXVSYNC/DU0_VSYNC */
5675 		[29] = RCAR_GP_PIN(2, 29),	/* DU0_EXODDF/DU0_ODDF_DISP_CDE */
5676 		[30] = RCAR_GP_PIN(2, 30),	/* DU0_DISP */
5677 		[31] = RCAR_GP_PIN(2, 31),	/* DU0_CDE */
5678 	} },
5679 	{ PINMUX_BIAS_REG("PUPR3", 0xe606010c, "N/A", 0) {
5680 		[ 0] = RCAR_GP_PIN(3, 2),	/* VI0_DATA1_VI0_B1 */
5681 		[ 1] = RCAR_GP_PIN(3, 3),	/* VI0_DATA2_VI0_B2 */
5682 		[ 2] = RCAR_GP_PIN(3, 4),	/* VI0_DATA3_VI0_B3 */
5683 		[ 3] = RCAR_GP_PIN(3, 5),	/* VI0_DATA4_VI0_B4 */
5684 		[ 4] = RCAR_GP_PIN(3, 6),	/* VI0_DATA5_VI0_B5 */
5685 		[ 5] = RCAR_GP_PIN(3, 7),	/* VI0_DATA6_VI0_B6 */
5686 		[ 6] = RCAR_GP_PIN(3, 8),	/* VI0_DATA7_VI0_B7 */
5687 		[ 7] = RCAR_GP_PIN(3, 9),	/* VI0_CLKENB */
5688 		[ 8] = RCAR_GP_PIN(3, 10),	/* VI0_FIELD */
5689 		[ 9] = RCAR_GP_PIN(3, 11),	/* VI0_HSYNC# */
5690 		[10] = RCAR_GP_PIN(3, 12),	/* VI0_VSYNC# */
5691 		[11] = RCAR_GP_PIN(3, 13),	/* ETH_MDIO */
5692 		[12] = RCAR_GP_PIN(3, 14),	/* ETH_CRS_DV */
5693 		[13] = RCAR_GP_PIN(3, 15),	/* ETH_RX_ER */
5694 		[14] = RCAR_GP_PIN(3, 16),	/* ETH_RXD0 */
5695 		[15] = RCAR_GP_PIN(3, 17),	/* ETH_RXD1 */
5696 		[16] = RCAR_GP_PIN(3, 18),	/* ETH_LINK */
5697 		[17] = RCAR_GP_PIN(3, 19),	/* ETH_REF_CLK */
5698 		[18] = RCAR_GP_PIN(3, 20),	/* ETH_TXD1 */
5699 		[19] = RCAR_GP_PIN(3, 21),	/* ETH_TX_EN */
5700 		[20] = RCAR_GP_PIN(3, 22),	/* ETH_MAGIC */
5701 		[21] = RCAR_GP_PIN(3, 23),	/* ETH_TXD0 */
5702 		[22] = RCAR_GP_PIN(3, 24),	/* ETH_MDC */
5703 		[23] = RCAR_GP_PIN(3, 25),	/* HSCIF0_HRX */
5704 		[24] = RCAR_GP_PIN(3, 26),	/* HSCIF0_HTX */
5705 		[25] = RCAR_GP_PIN(3, 27),	/* HSCIF0_HCTS# */
5706 		[26] = RCAR_GP_PIN(3, 28),	/* HSCIF0_HRTS# */
5707 		[27] = RCAR_GP_PIN(3, 29),	/* HSCIF0_HSCK */
5708 		[28] = RCAR_GP_PIN(3, 30),	/* I2C0_SCL */
5709 		[29] = RCAR_GP_PIN(3, 31),	/* I2C0_SDA */
5710 		[30] = RCAR_GP_PIN(4, 0),	/* I2C1_SCL */
5711 		[31] = RCAR_GP_PIN(4, 1),	/* I2C1_SDA */
5712 	} },
5713 	{ PINMUX_BIAS_REG("PUPR4", 0xe6060110, "N/A", 0) {
5714 		[ 0] = RCAR_GP_PIN(4, 2),	/* MSIOF0_RXD */
5715 		[ 1] = RCAR_GP_PIN(4, 3),	/* MSIOF0_TXD */
5716 		[ 2] = RCAR_GP_PIN(4, 4),	/* MSIOF0_SCK */
5717 		[ 3] = RCAR_GP_PIN(4, 5),	/* MSIOF0_SYNC */
5718 		[ 4] = RCAR_GP_PIN(4, 6),	/* MSIOF0_SS1 */
5719 		[ 5] = RCAR_GP_PIN(4, 7),	/* MSIOF0_SS2 */
5720 		[ 6] = RCAR_GP_PIN(4, 8),	/* HSCIF1_HRX */
5721 		[ 7] = RCAR_GP_PIN(4, 9),	/* HSCIF1_HTX */
5722 		[ 8] = RCAR_GP_PIN(4, 10),	/* HSCIF1_HSCK */
5723 		[ 9] = RCAR_GP_PIN(4, 11),	/* HSCIF1_HCTS# */
5724 		[10] = RCAR_GP_PIN(4, 12),	/* HSCIF1_HRTS# */
5725 		[11] = RCAR_GP_PIN(4, 13),	/* SCIF1_SCK */
5726 		[12] = RCAR_GP_PIN(4, 14),	/* SCIF1_RXD */
5727 		[13] = RCAR_GP_PIN(4, 15),	/* SCIF1_TXD */
5728 		[14] = RCAR_GP_PIN(4, 16),	/* SCIF2_RXD */
5729 		[15] = RCAR_GP_PIN(4, 17),	/* SCIF2_TXD */
5730 		[16] = RCAR_GP_PIN(4, 18),	/* SCIF2_SCK */
5731 		[17] = RCAR_GP_PIN(4, 19),	/* SCIF3_SCK */
5732 		[18] = RCAR_GP_PIN(4, 20),	/* SCIF3_RXD */
5733 		[19] = RCAR_GP_PIN(4, 21),	/* SCIF3_TXD */
5734 		[20] = RCAR_GP_PIN(4, 22),	/* I2C2_SCL */
5735 		[21] = RCAR_GP_PIN(4, 23),	/* I2C2_SDA */
5736 		[22] = RCAR_GP_PIN(4, 24),	/* SSI_SCK5 */
5737 		[23] = RCAR_GP_PIN(4, 25),	/* SSI_WS5 */
5738 		[24] = RCAR_GP_PIN(4, 26),	/* SSI_SDATA5 */
5739 		[25] = RCAR_GP_PIN(4, 27),	/* SSI_SCK6 */
5740 		[26] = RCAR_GP_PIN(4, 28),	/* SSI_WS6 */
5741 		[27] = RCAR_GP_PIN(4, 29),	/* SSI_SDATA6 */
5742 		[28] = RCAR_GP_PIN(4, 30),	/* SSI_SCK78 */
5743 		[29] = RCAR_GP_PIN(4, 31),	/* SSI_WS78 */
5744 		[30] = RCAR_GP_PIN(5, 0),	/* SSI_SDATA7 */
5745 		[31] = RCAR_GP_PIN(5, 1),	/* SSI_SCK0129 */
5746 	} },
5747 	{ PINMUX_BIAS_REG("PUPR5", 0xe6060114, "N/A", 0) {
5748 		[ 0] = RCAR_GP_PIN(5, 2),	/* SSI_WS0129 */
5749 		[ 1] = RCAR_GP_PIN(5, 3),	/* SSI_SDATA0 */
5750 		[ 2] = RCAR_GP_PIN(5, 4),	/* SSI_SCK34 */
5751 		[ 3] = RCAR_GP_PIN(5, 5),	/* SSI_WS34 */
5752 		[ 4] = RCAR_GP_PIN(5, 6),	/* SSI_SDATA3 */
5753 		[ 5] = SH_PFC_PIN_NONE,
5754 		[ 6] = SH_PFC_PIN_NONE,
5755 		[ 7] = SH_PFC_PIN_NONE,
5756 		[ 8] = RCAR_GP_PIN(5, 10),	/* SSI_SDATA8 */
5757 		[ 9] = RCAR_GP_PIN(5, 11),	/* SSI_SCK1 */
5758 		[10] = RCAR_GP_PIN(5, 12),	/* SSI_WS1 */
5759 		[11] = RCAR_GP_PIN(5, 13),	/* SSI_SDATA1 */
5760 		[12] = RCAR_GP_PIN(5, 14),	/* SSI_SCK2 */
5761 		[13] = RCAR_GP_PIN(5, 15),	/* SSI_WS2 */
5762 		[14] = RCAR_GP_PIN(5, 16),	/* SSI_SDATA2 */
5763 		[15] = RCAR_GP_PIN(5, 17),	/* SSI_SCK9 */
5764 		[16] = RCAR_GP_PIN(5, 18),	/* SSI_WS9 */
5765 		[17] = RCAR_GP_PIN(5, 19),	/* SSI_SDATA9 */
5766 		[18] = RCAR_GP_PIN(5, 20),	/* AUDIO_CLKA */
5767 		[19] = RCAR_GP_PIN(5, 21),	/* AUDIO_CLKB */
5768 		[20] = RCAR_GP_PIN(5, 22),	/* AUDIO_CLKC */
5769 		[21] = RCAR_GP_PIN(5, 23),	/* AUDIO_CLKOUT */
5770 		[22] = RCAR_GP_PIN(3, 0),	/* VI0_CLK */
5771 		[23] = RCAR_GP_PIN(3, 1),	/* VI0_DATA0_VI0_B0 */
5772 		[24] = SH_PFC_PIN_NONE,
5773 		[25] = SH_PFC_PIN_NONE,
5774 		[26] = SH_PFC_PIN_NONE,
5775 		[27] = SH_PFC_PIN_NONE,
5776 		[28] = SH_PFC_PIN_NONE,
5777 		[29] = SH_PFC_PIN_NONE,
5778 		[30] = SH_PFC_PIN_NONE,
5779 		[31] = SH_PFC_PIN_NONE,
5780 	} },
5781 	{ PINMUX_BIAS_REG("PUPR6", 0xe6060118, "N/A", 0) {
5782 		[ 0] = RCAR_GP_PIN(6, 1),	/* SD0_CMD */
5783 		[ 1] = RCAR_GP_PIN(6, 2),	/* SD0_DATA0 */
5784 		[ 2] = RCAR_GP_PIN(6, 3),	/* SD0_DATA1 */
5785 		[ 3] = RCAR_GP_PIN(6, 4),	/* SD0_DATA2 */
5786 		[ 4] = RCAR_GP_PIN(6, 5),	/* SD0_DATA3 */
5787 		[ 5] = RCAR_GP_PIN(6, 6),	/* SD0_CD */
5788 		[ 6] = RCAR_GP_PIN(6, 7),	/* SD0_WP */
5789 		[ 7] = RCAR_GP_PIN(6, 9),	/* SD1_CMD */
5790 		[ 8] = RCAR_GP_PIN(6, 10),	/* SD1_DATA0 */
5791 		[ 9] = RCAR_GP_PIN(6, 11),	/* SD1_DATA1 */
5792 		[10] = RCAR_GP_PIN(6, 12),	/* SD1_DATA2 */
5793 		[11] = RCAR_GP_PIN(6, 13),	/* SD1_DATA3 */
5794 		[12] = RCAR_GP_PIN(6, 14),	/* SD1_CD */
5795 		[13] = RCAR_GP_PIN(6, 15),	/* SD1_WP */
5796 		[14] = SH_PFC_PIN_NONE,
5797 		[15] = RCAR_GP_PIN(6, 17),	/* MMC_CMD */
5798 		[16] = RCAR_GP_PIN(6, 18),	/* MMC_D0 */
5799 		[17] = RCAR_GP_PIN(6, 19),	/* MMC_D1 */
5800 		[18] = RCAR_GP_PIN(6, 20),	/* MMC_D2 */
5801 		[19] = RCAR_GP_PIN(6, 21),	/* MMC_D3 */
5802 		[20] = RCAR_GP_PIN(6, 22),	/* MMC_D4 */
5803 		[21] = RCAR_GP_PIN(6, 23),	/* MMC_D5 */
5804 		[22] = RCAR_GP_PIN(6, 24),	/* MMC_D6 */
5805 		[23] = RCAR_GP_PIN(6, 25),	/* MMC_D7 */
5806 		[24] = SH_PFC_PIN_NONE,
5807 		[25] = SH_PFC_PIN_NONE,
5808 		[26] = SH_PFC_PIN_NONE,
5809 		[27] = SH_PFC_PIN_NONE,
5810 		[28] = SH_PFC_PIN_NONE,
5811 		[29] = SH_PFC_PIN_NONE,
5812 		[30] = SH_PFC_PIN_NONE,
5813 		[31] = SH_PFC_PIN_NONE,
5814 	} },
5815 	{ /* sentinel */ }
5816 };
5817 
5818 static const struct soc_device_attribute r8a7794_tdsel[] = {
5819 	{ .soc_id = "r8a7794", .revision = "ES1.0" },
5820 	{ /* sentinel */ }
5821 };
5822 
5823 static int r8a7794_pinmux_soc_init(struct sh_pfc *pfc)
5824 {
5825 	/* Initialize TDSEL on old revisions */
5826 	if (soc_device_match(r8a7794_tdsel))
5827 		sh_pfc_write(pfc, 0xe6060068, 0x55555500);
5828 
5829 	return 0;
5830 }
5831 
5832 static const struct sh_pfc_soc_operations r8a7794_pfc_ops = {
5833 	.init = r8a7794_pinmux_soc_init,
5834 	.pin_to_pocctrl = r8a7794_pin_to_pocctrl,
5835 	.get_bias = rcar_pinmux_get_bias,
5836 	.set_bias = rcar_pinmux_set_bias,
5837 };
5838 
5839 #ifdef CONFIG_PINCTRL_PFC_R8A7745
5840 const struct sh_pfc_soc_info r8a7745_pinmux_info = {
5841 	.name = "r8a77450_pfc",
5842 	.ops = &r8a7794_pfc_ops,
5843 	.unlock_reg = 0xe6060000, /* PMMR */
5844 
5845 	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
5846 
5847 	.pins = pinmux_pins,
5848 	.nr_pins = ARRAY_SIZE(pinmux_pins),
5849 	.groups = pinmux_groups,
5850 	.nr_groups = ARRAY_SIZE(pinmux_groups),
5851 	.functions = pinmux_functions,
5852 	.nr_functions = ARRAY_SIZE(pinmux_functions),
5853 
5854 	.cfg_regs = pinmux_config_regs,
5855 	.bias_regs = pinmux_bias_regs,
5856 
5857 	.pinmux_data = pinmux_data,
5858 	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
5859 };
5860 #endif
5861 
5862 #ifdef CONFIG_PINCTRL_PFC_R8A7794
5863 const struct sh_pfc_soc_info r8a7794_pinmux_info = {
5864 	.name = "r8a77940_pfc",
5865 	.ops = &r8a7794_pfc_ops,
5866 	.unlock_reg = 0xe6060000, /* PMMR */
5867 
5868 	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
5869 
5870 	.pins = pinmux_pins,
5871 	.nr_pins = ARRAY_SIZE(pinmux_pins),
5872 	.groups = pinmux_groups,
5873 	.nr_groups = ARRAY_SIZE(pinmux_groups),
5874 	.functions = pinmux_functions,
5875 	.nr_functions = ARRAY_SIZE(pinmux_functions),
5876 
5877 	.cfg_regs = pinmux_config_regs,
5878 	.bias_regs = pinmux_bias_regs,
5879 
5880 	.pinmux_data = pinmux_data,
5881 	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
5882 };
5883 #endif
5884