1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * r8a7791/r8a7743 processor support - PFC hardware block. 4 * 5 * Copyright (C) 2013 Renesas Electronics Corporation 6 * Copyright (C) 2014-2017 Cogent Embedded, Inc. 7 */ 8 9 #include <linux/errno.h> 10 #include <linux/kernel.h> 11 12 #include "sh_pfc.h" 13 14 /* 15 * Pins 0-23 assigned to GPIO bank 6 can be used for SD interfaces in 16 * which case they support both 3.3V and 1.8V signalling. 17 */ 18 #define CPU_ALL_GP(fn, sfx) \ 19 PORT_GP_32(0, fn, sfx), \ 20 PORT_GP_26(1, fn, sfx), \ 21 PORT_GP_32(2, fn, sfx), \ 22 PORT_GP_32(3, fn, sfx), \ 23 PORT_GP_32(4, fn, sfx), \ 24 PORT_GP_32(5, fn, sfx), \ 25 PORT_GP_CFG_24(6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ 26 PORT_GP_1(6, 24, fn, sfx), \ 27 PORT_GP_1(6, 25, fn, sfx), \ 28 PORT_GP_1(6, 26, fn, sfx), \ 29 PORT_GP_1(6, 27, fn, sfx), \ 30 PORT_GP_1(6, 28, fn, sfx), \ 31 PORT_GP_1(6, 29, fn, sfx), \ 32 PORT_GP_1(6, 30, fn, sfx), \ 33 PORT_GP_1(6, 31, fn, sfx), \ 34 PORT_GP_26(7, fn, sfx) 35 36 enum { 37 PINMUX_RESERVED = 0, 38 39 PINMUX_DATA_BEGIN, 40 GP_ALL(DATA), 41 PINMUX_DATA_END, 42 43 PINMUX_FUNCTION_BEGIN, 44 GP_ALL(FN), 45 46 /* GPSR0 */ 47 FN_IP0_0, FN_IP0_1, FN_IP0_2, FN_IP0_3, FN_IP0_4, FN_IP0_5, 48 FN_IP0_6, FN_IP0_7, FN_IP0_8, FN_IP0_9, FN_IP0_10, FN_IP0_11, 49 FN_IP0_12, FN_IP0_13, FN_IP0_14, FN_IP0_15, FN_IP0_18_16, FN_IP0_20_19, 50 FN_IP0_22_21, FN_IP0_24_23, FN_IP0_26_25, FN_IP0_28_27, FN_IP0_30_29, 51 FN_IP1_1_0, FN_IP1_3_2, FN_IP1_5_4, FN_IP1_7_6, FN_IP1_10_8, 52 FN_IP1_13_11, FN_IP1_16_14, FN_IP1_19_17, FN_IP1_22_20, 53 54 /* GPSR1 */ 55 FN_IP1_25_23, FN_IP1_28_26, FN_IP1_31_29, FN_IP2_2_0, FN_IP2_4_3, 56 FN_IP2_6_5, FN_IP2_9_7, FN_IP2_12_10, FN_IP2_15_13, FN_IP2_18_16, 57 FN_IP2_20_19, FN_IP2_22_21, FN_EX_CS0_N, FN_IP2_24_23, FN_IP2_26_25, 58 FN_IP2_29_27, FN_IP3_2_0, FN_IP3_5_3, FN_IP3_8_6, FN_RD_N, 59 FN_IP3_11_9, FN_IP3_13_12, FN_IP3_15_14 , FN_IP3_17_16 , FN_IP3_19_18, 60 FN_IP3_21_20, 61 62 /* GPSR2 */ 63 FN_IP3_27_25, FN_IP3_30_28, FN_IP4_1_0, FN_IP4_4_2, FN_IP4_7_5, 64 FN_IP4_9_8, FN_IP4_12_10, FN_IP4_15_13, FN_IP4_18_16, FN_IP4_19, 65 FN_IP4_20, FN_IP4_21, FN_IP4_23_22, FN_IP4_25_24, FN_IP4_27_26, 66 FN_IP4_30_28, FN_IP5_2_0, FN_IP5_5_3, FN_IP5_8_6, FN_IP5_11_9, 67 FN_IP5_14_12, FN_IP5_16_15, FN_IP5_19_17, FN_IP5_21_20, FN_IP5_23_22, 68 FN_IP5_25_24, FN_IP5_28_26, FN_IP5_31_29, FN_AUDIO_CLKA, FN_IP6_2_0, 69 FN_IP6_5_3, FN_IP6_7_6, 70 71 /* GPSR3 */ 72 FN_IP7_5_3, FN_IP7_8_6, FN_IP7_10_9, FN_IP7_12_11, FN_IP7_14_13, 73 FN_IP7_16_15, FN_IP7_18_17, FN_IP7_20_19, FN_IP7_23_21, FN_IP7_26_24, 74 FN_IP7_29_27, FN_IP8_2_0, FN_IP8_5_3, FN_IP8_8_6, FN_IP8_11_9, 75 FN_IP8_14_12, FN_IP8_17_15, FN_IP8_20_18, FN_IP8_23_21, FN_IP8_25_24, 76 FN_IP8_27_26, FN_IP8_30_28, FN_IP9_2_0, FN_IP9_5_3, FN_IP9_6, FN_IP9_7, 77 FN_IP9_10_8, FN_IP9_11, FN_IP9_12, FN_IP9_15_13, FN_IP9_16, 78 FN_IP9_18_17, 79 80 /* GPSR4 */ 81 FN_VI0_CLK, FN_IP9_20_19, FN_IP9_22_21, FN_IP9_24_23, FN_IP9_26_25, 82 FN_VI0_DATA0_VI0_B0, FN_VI0_DATA1_VI0_B1, FN_VI0_DATA2_VI0_B2, 83 FN_IP9_28_27, FN_VI0_DATA4_VI0_B4, FN_VI0_DATA5_VI0_B5, 84 FN_VI0_DATA6_VI0_B6, FN_VI0_DATA7_VI0_B7, FN_IP9_31_29, FN_IP10_2_0, 85 FN_IP10_5_3, FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_16_15, 86 FN_IP10_18_17, FN_IP10_21_19, FN_IP10_24_22, FN_IP10_26_25, 87 FN_IP10_28_27, FN_IP10_31_29, FN_IP11_2_0, FN_IP11_5_3, FN_IP11_8_6, 88 FN_IP15_1_0, FN_IP15_3_2, FN_IP15_5_4, 89 90 /* GPSR5 */ 91 FN_IP11_11_9, FN_IP11_14_12, FN_IP11_16_15, FN_IP11_18_17, FN_IP11_19, 92 FN_IP11_20, FN_IP11_21, FN_IP11_22, FN_IP11_23, FN_IP11_24, 93 FN_IP11_25, FN_IP11_26, FN_IP11_27, FN_IP11_29_28, FN_IP11_31_30, 94 FN_IP12_1_0, FN_IP12_3_2, FN_IP12_6_4, FN_IP12_9_7, FN_IP12_12_10, 95 FN_IP12_15_13, FN_IP12_17_16, FN_IP12_19_18, FN_IP12_21_20, 96 FN_IP12_23_22, FN_IP12_26_24, FN_IP12_29_27, FN_IP13_2_0, FN_IP13_4_3, 97 FN_IP13_6_5, FN_IP13_9_7, FN_IP3_24_22, 98 99 /* GPSR6 */ 100 FN_IP13_10, FN_IP13_11, FN_IP13_12, FN_IP13_13, FN_IP13_14, 101 FN_IP13_15, FN_IP13_18_16, FN_IP13_21_19, 102 FN_IP13_22, FN_IP13_24_23, FN_SD1_CLK, 103 FN_IP13_25, FN_IP13_26, FN_IP13_27, FN_IP13_30_28, FN_IP14_1_0, 104 FN_IP14_2, FN_IP14_3, FN_IP14_4, FN_IP14_5, FN_IP14_6, FN_IP14_7, 105 FN_IP14_10_8, FN_IP14_13_11, FN_IP14_16_14, FN_IP14_19_17, 106 FN_IP14_22_20, FN_IP14_25_23, FN_IP14_28_26, FN_IP14_31_29, 107 FN_USB1_OVC, FN_DU0_DOTCLKIN, 108 109 /* GPSR7 */ 110 FN_IP15_17_15, FN_IP15_20_18, FN_IP15_23_21, FN_IP15_26_24, 111 FN_IP15_29_27, FN_IP16_2_0, FN_IP16_5_3, FN_IP16_7_6, FN_IP16_9_8, 112 FN_IP16_11_10, FN_IP6_9_8, FN_IP6_11_10, FN_IP6_13_12, FN_IP6_15_14, 113 FN_IP6_18_16, FN_IP6_20_19, FN_IP6_23_21, FN_IP6_26_24, FN_IP6_29_27, 114 FN_IP7_2_0, FN_IP15_8_6, FN_IP15_11_9, FN_IP15_14_12, 115 FN_USB0_PWEN, FN_USB0_OVC, FN_USB1_PWEN, 116 117 /* IPSR0 */ 118 FN_D0, FN_D1, FN_D2, FN_D3, FN_D4, FN_D5, FN_D6, FN_D7, FN_D8, 119 FN_D9, FN_D10, FN_D11, FN_D12, FN_D13, FN_D14, FN_D15, 120 FN_A0, FN_ATAWR0_N_C, FN_MSIOF0_SCK_B, FN_I2C0_SCL_C, FN_PWM2_B, 121 FN_A1, FN_MSIOF0_SYNC_B, FN_A2, FN_MSIOF0_SS1_B, 122 FN_A3, FN_MSIOF0_SS2_B, FN_A4, FN_MSIOF0_TXD_B, 123 FN_A5, FN_MSIOF0_RXD_B, FN_A6, FN_MSIOF1_SCK, 124 125 /* IPSR1 */ 126 FN_A7, FN_MSIOF1_SYNC, FN_A8, FN_MSIOF1_SS1, FN_I2C0_SCL, 127 FN_A9, FN_MSIOF1_SS2, FN_I2C0_SDA, 128 FN_A10, FN_MSIOF1_TXD, FN_MSIOF1_TXD_D, 129 FN_A11, FN_MSIOF1_RXD, FN_I2C3_SCL_D, FN_MSIOF1_RXD_D, 130 FN_A12, FN_FMCLK, FN_I2C3_SDA_D, FN_MSIOF1_SCK_D, 131 FN_A13, FN_ATAG0_N_C, FN_BPFCLK, FN_MSIOF1_SS1_D, 132 FN_A14, FN_ATADIR0_N_C, FN_FMIN, FN_FMIN_C, FN_MSIOF1_SYNC_D, 133 FN_A15, FN_BPFCLK_C, 134 FN_A16, FN_DREQ2_B, FN_FMCLK_C, FN_SCIFA1_SCK_B, 135 FN_A17, FN_DACK2_B, FN_I2C0_SDA_C, 136 FN_A18, FN_DREQ1, FN_SCIFA1_RXD_C, FN_SCIFB1_RXD_C, 137 138 /* IPSR2 */ 139 FN_A19, FN_DACK1, FN_SCIFA1_TXD_C, FN_SCIFB1_TXD_C, FN_SCIFB1_SCK_B, 140 FN_A20, FN_SPCLK, 141 FN_A21, FN_ATAWR0_N_B, FN_MOSI_IO0, 142 FN_A22, FN_MISO_IO1, FN_FMCLK_B, FN_TX0, FN_SCIFA0_TXD, 143 FN_A23, FN_IO2, FN_BPFCLK_B, FN_RX0, FN_SCIFA0_RXD, 144 FN_A24, FN_DREQ2, FN_IO3, FN_TX1, FN_SCIFA1_TXD, 145 FN_A25, FN_DACK2, FN_SSL, FN_DREQ1_C, FN_RX1, FN_SCIFA1_RXD, 146 FN_CS0_N, FN_ATAG0_N_B, FN_I2C1_SCL, 147 FN_CS1_N_A26, FN_ATADIR0_N_B, FN_I2C1_SDA, 148 FN_EX_CS1_N, FN_MSIOF2_SCK, 149 FN_EX_CS2_N, FN_ATAWR0_N, FN_MSIOF2_SYNC, 150 FN_EX_CS3_N, FN_ATADIR0_N, FN_MSIOF2_TXD, FN_ATAG0_N, FN_EX_WAIT1, 151 152 /* IPSR3 */ 153 FN_EX_CS4_N, FN_ATARD0_N, FN_MSIOF2_RXD, FN_EX_WAIT2, 154 FN_EX_CS5_N, FN_ATACS00_N, FN_MSIOF2_SS1, FN_HRX1_B, 155 FN_SCIFB1_RXD_B, FN_PWM1, FN_TPU_TO1, 156 FN_BS_N, FN_ATACS10_N, FN_MSIOF2_SS2, FN_HTX1_B, 157 FN_SCIFB1_TXD_B, FN_PWM2, FN_TPU_TO2, 158 FN_RD_WR_N, FN_HRX2_B, FN_FMIN_B, FN_SCIFB0_RXD_B, FN_DREQ1_D, 159 FN_WE0_N, FN_HCTS2_N_B, FN_SCIFB0_TXD_B, 160 FN_WE1_N, FN_ATARD0_N_B, FN_HTX2_B, FN_SCIFB0_RTS_N_B, 161 FN_EX_WAIT0, FN_HRTS2_N_B, FN_SCIFB0_CTS_N_B, 162 FN_DREQ0, FN_PWM3, FN_TPU_TO3, 163 FN_DACK0, FN_DRACK0, FN_REMOCON, 164 FN_SPEEDIN, FN_HSCK0_C, FN_HSCK2_C, FN_SCIFB0_SCK_B, 165 FN_SCIFB2_SCK_B, FN_DREQ2_C, FN_HTX2_D, 166 FN_SSI_SCK0129, FN_HRX0_C, FN_HRX2_C, FN_SCIFB0_RXD_C, FN_SCIFB2_RXD_C, 167 FN_SSI_WS0129, FN_HTX0_C, FN_HTX2_C, FN_SCIFB0_TXD_C, FN_SCIFB2_TXD_C, 168 169 /* IPSR4 */ 170 FN_SSI_SDATA0, FN_I2C0_SCL_B, FN_IIC0_SCL_B, FN_MSIOF2_SCK_C, 171 FN_SSI_SCK1, FN_I2C0_SDA_B, FN_IIC0_SDA_B, FN_MSIOF2_SYNC_C, 172 FN_GLO_I0_D, 173 FN_SSI_WS1, FN_I2C1_SCL_B, FN_IIC1_SCL_B, FN_MSIOF2_TXD_C, FN_GLO_I1_D, 174 FN_SSI_SDATA1, FN_I2C1_SDA_B, FN_IIC1_SDA_B, FN_MSIOF2_RXD_C, 175 FN_SSI_SCK2, FN_I2C2_SCL, FN_GPS_CLK_B, FN_GLO_Q0_D, FN_HSCK1_E, 176 FN_SSI_WS2, FN_I2C2_SDA, FN_GPS_SIGN_B, FN_RX2_E, 177 FN_GLO_Q1_D, FN_HCTS1_N_E, 178 FN_SSI_SDATA2, FN_GPS_MAG_B, FN_TX2_E, FN_HRTS1_N_E, 179 FN_SSI_SCK34, FN_SSI_WS34, FN_SSI_SDATA3, 180 FN_SSI_SCK4, FN_GLO_SS_D, 181 FN_SSI_WS4, FN_GLO_RFON_D, 182 FN_SSI_SDATA4, FN_MSIOF2_SCK_D, 183 FN_SSI_SCK5, FN_MSIOF1_SCK_C, FN_TS_SDATA0, FN_GLO_I0, 184 FN_MSIOF2_SYNC_D, FN_VI1_R2_B, 185 186 /* IPSR5 */ 187 FN_SSI_WS5, FN_MSIOF1_SYNC_C, FN_TS_SCK0, FN_GLO_I1, 188 FN_MSIOF2_TXD_D, FN_VI1_R3_B, 189 FN_SSI_SDATA5, FN_MSIOF1_TXD_C, FN_TS_SDEN0, FN_GLO_Q0, 190 FN_MSIOF2_SS1_D, FN_VI1_R4_B, 191 FN_SSI_SCK6, FN_MSIOF1_RXD_C, FN_TS_SPSYNC0, FN_GLO_Q1, 192 FN_MSIOF2_RXD_D, FN_VI1_R5_B, 193 FN_SSI_WS6, FN_GLO_SCLK, FN_MSIOF2_SS2_D, FN_VI1_R6_B, 194 FN_SSI_SDATA6, FN_STP_IVCXO27_0_B, FN_GLO_SDATA, FN_VI1_R7_B, 195 FN_SSI_SCK78, FN_STP_ISCLK_0_B, FN_GLO_SS, 196 FN_SSI_WS78, FN_TX0_D, FN_STP_ISD_0_B, FN_GLO_RFON, 197 FN_SSI_SDATA7, FN_RX0_D, FN_STP_ISEN_0_B, 198 FN_SSI_SDATA8, FN_TX1_D, FN_STP_ISSYNC_0_B, 199 FN_SSI_SCK9, FN_RX1_D, FN_GLO_SCLK_D, 200 FN_SSI_WS9, FN_TX3_D, FN_CAN0_TX_D, FN_GLO_SDATA_D, 201 FN_SSI_SDATA9, FN_RX3_D, FN_CAN0_RX_D, 202 203 /* IPSR6 */ 204 FN_AUDIO_CLKB, FN_STP_OPWM_0_B, FN_MSIOF1_SCK_B, 205 FN_SCIF_CLK, FN_DVC_MUTE, FN_BPFCLK_E, 206 FN_AUDIO_CLKC, FN_SCIFB0_SCK_C, FN_MSIOF1_SYNC_B, FN_RX2, 207 FN_SCIFA2_RXD, FN_FMIN_E, 208 FN_AUDIO_CLKOUT, FN_MSIOF1_SS1_B, FN_TX2, FN_SCIFA2_TXD, 209 FN_IRQ0, FN_SCIFB1_RXD_D, FN_INTC_IRQ0_N, 210 FN_IRQ1, FN_SCIFB1_SCK_C, FN_INTC_IRQ1_N, 211 FN_IRQ2, FN_SCIFB1_TXD_D, FN_INTC_IRQ2_N, 212 FN_IRQ3, FN_I2C4_SCL_C, FN_MSIOF2_TXD_E, FN_INTC_IRQ3_N, 213 FN_IRQ4, FN_HRX1_C, FN_I2C4_SDA_C, FN_MSIOF2_RXD_E, FN_INTC_IRQ4_N, 214 FN_IRQ5, FN_HTX1_C, FN_I2C1_SCL_E, FN_MSIOF2_SCK_E, 215 FN_IRQ6, FN_HSCK1_C, FN_MSIOF1_SS2_B, FN_I2C1_SDA_E, FN_MSIOF2_SYNC_E, 216 FN_IRQ7, FN_HCTS1_N_C, FN_MSIOF1_TXD_B, FN_GPS_CLK_C, FN_GPS_CLK_D, 217 FN_IRQ8, FN_HRTS1_N_C, FN_MSIOF1_RXD_B, FN_GPS_SIGN_C, FN_GPS_SIGN_D, 218 219 /* IPSR7 */ 220 FN_IRQ9, FN_DU1_DOTCLKIN_B, FN_CAN_CLK_D, FN_GPS_MAG_C, 221 FN_SCIF_CLK_B, FN_GPS_MAG_D, 222 FN_DU1_DR0, FN_LCDOUT0, FN_VI1_DATA0_B, FN_TX0_B, 223 FN_SCIFA0_TXD_B, FN_MSIOF2_SCK_B, 224 FN_DU1_DR1, FN_LCDOUT1, FN_VI1_DATA1_B, FN_RX0_B, 225 FN_SCIFA0_RXD_B, FN_MSIOF2_SYNC_B, 226 FN_DU1_DR2, FN_LCDOUT2, FN_SSI_SCK0129_B, 227 FN_DU1_DR3, FN_LCDOUT3, FN_SSI_WS0129_B, 228 FN_DU1_DR4, FN_LCDOUT4, FN_SSI_SDATA0_B, 229 FN_DU1_DR5, FN_LCDOUT5, FN_SSI_SCK1_B, 230 FN_DU1_DR6, FN_LCDOUT6, FN_SSI_WS1_B, 231 FN_DU1_DR7, FN_LCDOUT7, FN_SSI_SDATA1_B, 232 FN_DU1_DG0, FN_LCDOUT8, FN_VI1_DATA2_B, FN_TX1_B, 233 FN_SCIFA1_TXD_B, FN_MSIOF2_SS1_B, 234 FN_DU1_DG1, FN_LCDOUT9, FN_VI1_DATA3_B, FN_RX1_B, 235 FN_SCIFA1_RXD_B, FN_MSIOF2_SS2_B, 236 FN_DU1_DG2, FN_LCDOUT10, FN_VI1_DATA4_B, FN_SCIF1_SCK_B, 237 FN_SCIFA1_SCK, FN_SSI_SCK78_B, 238 239 /* IPSR8 */ 240 FN_DU1_DG3, FN_LCDOUT11, FN_VI1_DATA5_B, FN_SSI_WS78_B, 241 FN_DU1_DG4, FN_LCDOUT12, FN_VI1_DATA6_B, FN_HRX0_B, 242 FN_SCIFB2_RXD_B, FN_SSI_SDATA7_B, 243 FN_DU1_DG5, FN_LCDOUT13, FN_VI1_DATA7_B, FN_HCTS0_N_B, 244 FN_SCIFB2_TXD_B, FN_SSI_SDATA8_B, 245 FN_DU1_DG6, FN_LCDOUT14, FN_HRTS0_N_B, 246 FN_SCIFB2_CTS_N_B, FN_SSI_SCK9_B, 247 FN_DU1_DG7, FN_LCDOUT15, FN_HTX0_B, FN_SCIFB2_RTS_N_B, FN_SSI_WS9_B, 248 FN_DU1_DB0, FN_LCDOUT16, FN_VI1_CLK_B, FN_TX2_B, 249 FN_SCIFA2_TXD_B, FN_MSIOF2_TXD_B, 250 FN_DU1_DB1, FN_LCDOUT17, FN_VI1_HSYNC_N_B, FN_RX2_B, 251 FN_SCIFA2_RXD_B, FN_MSIOF2_RXD_B, 252 FN_DU1_DB2, FN_LCDOUT18, FN_VI1_VSYNC_N_B, FN_SCIF2_SCK_B, 253 FN_SCIFA2_SCK, FN_SSI_SDATA9_B, 254 FN_DU1_DB3, FN_LCDOUT19, FN_VI1_CLKENB_B, 255 FN_DU1_DB4, FN_LCDOUT20, FN_VI1_FIELD_B, FN_CAN1_RX, 256 FN_DU1_DB5, FN_LCDOUT21, FN_TX3, FN_SCIFA3_TXD, FN_CAN1_TX, 257 258 /* IPSR9 */ 259 FN_DU1_DB6, FN_LCDOUT22, FN_I2C3_SCL_C, FN_RX3, FN_SCIFA3_RXD, 260 FN_DU1_DB7, FN_LCDOUT23, FN_I2C3_SDA_C, FN_SCIF3_SCK, FN_SCIFA3_SCK, 261 FN_DU1_DOTCLKIN, FN_QSTVA_QVS, 262 FN_DU1_DOTCLKOUT0, FN_QCLK, 263 FN_DU1_DOTCLKOUT1, FN_QSTVB_QVE, FN_CAN0_TX, 264 FN_TX3_B, FN_I2C2_SCL_B, FN_PWM4, 265 FN_DU1_EXHSYNC_DU1_HSYNC, FN_QSTH_QHS, 266 FN_DU1_EXVSYNC_DU1_VSYNC, FN_QSTB_QHE, 267 FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_QCPV_QDE, 268 FN_CAN0_RX, FN_RX3_B, FN_I2C2_SDA_B, 269 FN_DU1_DISP, FN_QPOLA, 270 FN_DU1_CDE, FN_QPOLB, FN_PWM4_B, 271 FN_VI0_CLKENB, FN_TX4, FN_SCIFA4_TXD, FN_TS_SDATA0_D, 272 FN_VI0_FIELD, FN_RX4, FN_SCIFA4_RXD, FN_TS_SCK0_D, 273 FN_VI0_HSYNC_N, FN_TX5, FN_SCIFA5_TXD, FN_TS_SDEN0_D, 274 FN_VI0_VSYNC_N, FN_RX5, FN_SCIFA5_RXD, FN_TS_SPSYNC0_D, 275 FN_VI0_DATA3_VI0_B3, FN_SCIF3_SCK_B, FN_SCIFA3_SCK_B, 276 FN_VI0_G0, FN_IIC1_SCL, FN_STP_IVCXO27_0_C, FN_I2C4_SCL, 277 FN_HCTS2_N, FN_SCIFB2_CTS_N, FN_ATAWR1_N, 278 279 /* IPSR10 */ 280 FN_VI0_G1, FN_IIC1_SDA, FN_STP_ISCLK_0_C, FN_I2C4_SDA, 281 FN_HRTS2_N, FN_SCIFB2_RTS_N, FN_ATADIR1_N, 282 FN_VI0_G2, FN_VI2_HSYNC_N, FN_STP_ISD_0_C, FN_I2C3_SCL_B, 283 FN_HSCK2, FN_SCIFB2_SCK, FN_ATARD1_N, 284 FN_VI0_G3, FN_VI2_VSYNC_N, FN_STP_ISEN_0_C, FN_I2C3_SDA_B, 285 FN_HRX2, FN_SCIFB2_RXD, FN_ATACS01_N, 286 FN_VI0_G4, FN_VI2_CLKENB, FN_STP_ISSYNC_0_C, 287 FN_HTX2, FN_SCIFB2_TXD, FN_SCIFB0_SCK_D, 288 FN_VI0_G5, FN_VI2_FIELD, FN_STP_OPWM_0_C, FN_FMCLK_D, 289 FN_CAN0_TX_E, FN_HTX1_D, FN_SCIFB0_TXD_D, 290 FN_VI0_G6, FN_VI2_CLK, FN_BPFCLK_D, 291 FN_VI0_G7, FN_VI2_DATA0, FN_FMIN_D, 292 FN_VI0_R0, FN_VI2_DATA1, FN_GLO_I0_B, 293 FN_TS_SDATA0_C, FN_ATACS11_N, 294 FN_VI0_R1, FN_VI2_DATA2, FN_GLO_I1_B, 295 FN_TS_SCK0_C, FN_ATAG1_N, 296 FN_VI0_R2, FN_VI2_DATA3, FN_GLO_Q0_B, FN_TS_SDEN0_C, 297 FN_VI0_R3, FN_VI2_DATA4, FN_GLO_Q1_B, FN_TS_SPSYNC0_C, 298 FN_VI0_R4, FN_VI2_DATA5, FN_GLO_SCLK_B, FN_TX0_C, FN_I2C1_SCL_D, 299 300 /* IPSR11 */ 301 FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C, FN_I2C1_SDA_D, 302 FN_VI0_R6, FN_VI2_DATA7, FN_GLO_SS_B, FN_TX1_C, FN_I2C4_SCL_B, 303 FN_VI0_R7, FN_GLO_RFON_B, FN_RX1_C, FN_CAN0_RX_E, 304 FN_I2C4_SDA_B, FN_HRX1_D, FN_SCIFB0_RXD_D, 305 FN_VI1_HSYNC_N, FN_AVB_RXD0, FN_TS_SDATA0_B, FN_TX4_B, FN_SCIFA4_TXD_B, 306 FN_VI1_VSYNC_N, FN_AVB_RXD1, FN_TS_SCK0_B, FN_RX4_B, FN_SCIFA4_RXD_B, 307 FN_VI1_CLKENB, FN_AVB_RXD2, FN_TS_SDEN0_B, 308 FN_VI1_FIELD, FN_AVB_RXD3, FN_TS_SPSYNC0_B, 309 FN_VI1_CLK, FN_AVB_RXD4, FN_VI1_DATA0, FN_AVB_RXD5, 310 FN_VI1_DATA1, FN_AVB_RXD6, FN_VI1_DATA2, FN_AVB_RXD7, 311 FN_VI1_DATA3, FN_AVB_RX_ER, FN_VI1_DATA4, FN_AVB_MDIO, 312 FN_VI1_DATA5, FN_AVB_RX_DV, FN_VI1_DATA6, FN_AVB_MAGIC, 313 FN_VI1_DATA7, FN_AVB_MDC, 314 FN_ETH_MDIO, FN_AVB_RX_CLK, FN_I2C2_SCL_C, 315 FN_ETH_CRS_DV, FN_AVB_LINK, FN_I2C2_SDA_C, 316 317 /* IPSR12 */ 318 FN_ETH_RX_ER, FN_AVB_CRS, FN_I2C3_SCL, FN_IIC0_SCL, 319 FN_ETH_RXD0, FN_AVB_PHY_INT, FN_I2C3_SDA, FN_IIC0_SDA, 320 FN_ETH_RXD1, FN_AVB_GTXREFCLK, FN_CAN0_TX_C, 321 FN_I2C2_SCL_D, FN_MSIOF1_RXD_E, 322 FN_ETH_LINK, FN_AVB_TXD0, FN_CAN0_RX_C, FN_I2C2_SDA_D, FN_MSIOF1_SCK_E, 323 FN_ETH_REFCLK, FN_AVB_TXD1, FN_SCIFA3_RXD_B, 324 FN_CAN1_RX_C, FN_MSIOF1_SYNC_E, 325 FN_ETH_TXD1, FN_AVB_TXD2, FN_SCIFA3_TXD_B, 326 FN_CAN1_TX_C, FN_MSIOF1_TXD_E, 327 FN_ETH_TX_EN, FN_AVB_TXD3, FN_TCLK1_B, FN_CAN_CLK_B, 328 FN_ETH_MAGIC, FN_AVB_TXD4, FN_IETX_C, 329 FN_ETH_TXD0, FN_AVB_TXD5, FN_IECLK_C, 330 FN_ETH_MDC, FN_AVB_TXD6, FN_IERX_C, 331 FN_STP_IVCXO27_0, FN_AVB_TXD7, FN_SCIFB2_TXD_D, 332 FN_ADIDATA_B, FN_MSIOF0_SYNC_C, 333 FN_STP_ISCLK_0, FN_AVB_TX_EN, FN_SCIFB2_RXD_D, 334 FN_ADICS_SAMP_B, FN_MSIOF0_SCK_C, 335 336 /* IPSR13 */ 337 FN_STP_ISD_0, FN_AVB_TX_ER, FN_SCIFB2_SCK_C, 338 FN_ADICLK_B, FN_MSIOF0_SS1_C, 339 FN_STP_ISEN_0, FN_AVB_TX_CLK, FN_ADICHS0_B, FN_MSIOF0_SS2_C, 340 FN_STP_ISSYNC_0, FN_AVB_COL, FN_ADICHS1_B, FN_MSIOF0_RXD_C, 341 FN_STP_OPWM_0, FN_AVB_GTX_CLK, FN_PWM0_B, 342 FN_ADICHS2_B, FN_MSIOF0_TXD_C, 343 FN_SD0_CLK, FN_SPCLK_B, FN_SD0_CMD, FN_MOSI_IO0_B, 344 FN_SD0_DATA0, FN_MISO_IO1_B, FN_SD0_DATA1, FN_IO2_B, 345 FN_SD0_DATA2, FN_IO3_B, FN_SD0_DATA3, FN_SSL_B, 346 FN_SD0_CD, FN_MMC_D6_B, FN_SIM0_RST_B, FN_CAN0_RX_F, 347 FN_SCIFA5_TXD_B, FN_TX3_C, 348 FN_SD0_WP, FN_MMC_D7_B, FN_SIM0_D_B, FN_CAN0_TX_F, 349 FN_SCIFA5_RXD_B, FN_RX3_C, 350 FN_SD1_CMD, FN_REMOCON_B, FN_SD1_DATA0, FN_SPEEDIN_B, 351 FN_SD1_DATA1, FN_IETX_B, FN_SD1_DATA2, FN_IECLK_B, 352 FN_SD1_DATA3, FN_IERX_B, 353 FN_SD1_CD, FN_PWM0, FN_TPU_TO0, FN_I2C1_SCL_C, 354 355 /* IPSR14 */ 356 FN_SD1_WP, FN_PWM1_B, FN_I2C1_SDA_C, 357 FN_SD2_CLK, FN_MMC_CLK, FN_SD2_CMD, FN_MMC_CMD, 358 FN_SD2_DATA0, FN_MMC_D0, FN_SD2_DATA1, FN_MMC_D1, 359 FN_SD2_DATA2, FN_MMC_D2, FN_SD2_DATA3, FN_MMC_D3, 360 FN_SD2_CD, FN_MMC_D4, FN_IIC1_SCL_C, FN_TX5_B, FN_SCIFA5_TXD_C, 361 FN_SD2_WP, FN_MMC_D5, FN_IIC1_SDA_C, FN_RX5_B, FN_SCIFA5_RXD_C, 362 FN_MSIOF0_SCK, FN_RX2_C, FN_ADIDATA, FN_VI1_CLK_C, FN_VI1_G0_B, 363 FN_MSIOF0_SYNC, FN_TX2_C, FN_ADICS_SAMP, FN_VI1_CLKENB_C, FN_VI1_G1_B, 364 FN_MSIOF0_TXD, FN_ADICLK, FN_VI1_FIELD_C, FN_VI1_G2_B, 365 FN_MSIOF0_RXD, FN_ADICHS0, FN_VI1_DATA0_C, FN_VI1_G3_B, 366 FN_MSIOF0_SS1, FN_MMC_D6, FN_ADICHS1, FN_TX0_E, 367 FN_VI1_HSYNC_N_C, FN_IIC0_SCL_C, FN_VI1_G4_B, 368 FN_MSIOF0_SS2, FN_MMC_D7, FN_ADICHS2, FN_RX0_E, 369 FN_VI1_VSYNC_N_C, FN_IIC0_SDA_C, FN_VI1_G5_B, 370 371 /* IPSR15 */ 372 FN_SIM0_RST, FN_IETX, FN_CAN1_TX_D, 373 FN_SIM0_CLK, FN_IECLK, FN_CAN_CLK_C, 374 FN_SIM0_D, FN_IERX, FN_CAN1_RX_D, 375 FN_GPS_CLK, FN_DU1_DOTCLKIN_C, FN_AUDIO_CLKB_B, 376 FN_PWM5_B, FN_SCIFA3_TXD_C, 377 FN_GPS_SIGN, FN_TX4_C, FN_SCIFA4_TXD_C, FN_PWM5, 378 FN_VI1_G6_B, FN_SCIFA3_RXD_C, 379 FN_GPS_MAG, FN_RX4_C, FN_SCIFA4_RXD_C, FN_PWM6, 380 FN_VI1_G7_B, FN_SCIFA3_SCK_C, 381 FN_HCTS0_N, FN_SCIFB0_CTS_N, FN_GLO_I0_C, FN_TCLK1, FN_VI1_DATA1_C, 382 FN_HRTS0_N, FN_SCIFB0_RTS_N, FN_GLO_I1_C, FN_VI1_DATA2_C, 383 FN_HSCK0, FN_SCIFB0_SCK, FN_GLO_Q0_C, FN_CAN_CLK, 384 FN_TCLK2, FN_VI1_DATA3_C, 385 FN_HRX0, FN_SCIFB0_RXD, FN_GLO_Q1_C, FN_CAN0_RX_B, FN_VI1_DATA4_C, 386 FN_HTX0, FN_SCIFB0_TXD, FN_GLO_SCLK_C, FN_CAN0_TX_B, FN_VI1_DATA5_C, 387 388 /* IPSR16 */ 389 FN_HRX1, FN_SCIFB1_RXD, FN_VI1_R0_B, FN_GLO_SDATA_C, FN_VI1_DATA6_C, 390 FN_HTX1, FN_SCIFB1_TXD, FN_VI1_R1_B, FN_GLO_SS_C, FN_VI1_DATA7_C, 391 FN_HSCK1, FN_SCIFB1_SCK, FN_MLB_CLK, FN_GLO_RFON_C, 392 FN_HCTS1_N, FN_SCIFB1_CTS_N, FN_MLB_SIG, FN_CAN1_TX_B, 393 FN_HRTS1_N, FN_SCIFB1_RTS_N, FN_MLB_DAT, FN_CAN1_RX_B, 394 395 /* MOD_SEL */ 396 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3, 397 FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, FN_SEL_SCIFB_3, 398 FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, FN_SEL_SCIFB2_3, 399 FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3, 400 FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, 401 FN_SEL_SSI9_0, FN_SEL_SSI9_1, 402 FN_SEL_SCFA_0, FN_SEL_SCFA_1, 403 FN_SEL_QSP_0, FN_SEL_QSP_1, 404 FN_SEL_SSI7_0, FN_SEL_SSI7_1, 405 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2, FN_SEL_HSCIF1_3, 406 FN_SEL_HSCIF1_4, 407 FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2, 408 FN_SEL_TMU1_0, FN_SEL_TMU1_1, 409 FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_LBS_2, FN_SEL_LBS_3, 410 FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, 411 FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2, 412 413 /* MOD_SEL2 */ 414 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3, 415 FN_SEL_SCIF0_4, 416 FN_SEL_SCIF_0, FN_SEL_SCIF_1, 417 FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3, 418 FN_SEL_CAN0_4, FN_SEL_CAN0_5, 419 FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3, 420 FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, 421 FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, 422 FN_SEL_ADG_0, FN_SEL_ADG_1, 423 FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3, FN_SEL_FM_4, 424 FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, 425 FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3, 426 FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2, 427 FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2, 428 FN_SEL_SIM_0, FN_SEL_SIM_1, 429 FN_SEL_SSI8_0, FN_SEL_SSI8_1, 430 431 /* MOD_SEL3 */ 432 FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1, FN_SEL_HSCIF2_2, FN_SEL_HSCIF2_3, 433 FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2, FN_SEL_CANCLK_3, 434 FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, 435 FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, 436 FN_SEL_I2C4_0, FN_SEL_I2C4_1, FN_SEL_I2C4_2, 437 FN_SEL_I2C3_0, FN_SEL_I2C3_1, FN_SEL_I2C3_2, FN_SEL_I2C3_3, 438 FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3, 439 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 440 FN_SEL_MMC_0, FN_SEL_MMC_1, 441 FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, 442 FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3, 443 FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, FN_SEL_I2C1_3, 444 FN_SEL_I2C1_4, 445 FN_SEL_I2C0_0, FN_SEL_I2C0_1, FN_SEL_I2C0_2, 446 447 /* MOD_SEL4 */ 448 FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3, 449 FN_SEL_SOF1_4, 450 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, 451 FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2, 452 FN_SEL_RAD_0, FN_SEL_RAD_1, 453 FN_SEL_RCN_0, FN_SEL_RCN_1, 454 FN_SEL_RSP_0, FN_SEL_RSP_1, 455 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF2_3, 456 FN_SEL_SCIF2_4, 457 FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2, FN_SEL_SOF2_3, 458 FN_SEL_SOF2_4, 459 FN_SEL_SSI1_0, FN_SEL_SSI1_1, 460 FN_SEL_SSI0_0, FN_SEL_SSI0_1, 461 FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2, 462 PINMUX_FUNCTION_END, 463 464 PINMUX_MARK_BEGIN, 465 466 EX_CS0_N_MARK, RD_N_MARK, 467 468 AUDIO_CLKA_MARK, 469 470 VI0_CLK_MARK, VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK, 471 VI0_DATA2_VI0_B2_MARK, VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK, 472 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK, 473 474 SD1_CLK_MARK, 475 476 USB0_PWEN_MARK, USB0_OVC_MARK, USB1_PWEN_MARK, USB1_OVC_MARK, 477 DU0_DOTCLKIN_MARK, 478 479 /* IPSR0 */ 480 D0_MARK, D1_MARK, D2_MARK, D3_MARK, D4_MARK, D5_MARK, 481 D6_MARK, D7_MARK, D8_MARK, 482 D9_MARK, D10_MARK, D11_MARK, D12_MARK, D13_MARK, D14_MARK, D15_MARK, 483 A0_MARK, ATAWR0_N_C_MARK, MSIOF0_SCK_B_MARK, I2C0_SCL_C_MARK, 484 PWM2_B_MARK, 485 A1_MARK, MSIOF0_SYNC_B_MARK, A2_MARK, MSIOF0_SS1_B_MARK, 486 A3_MARK, MSIOF0_SS2_B_MARK, A4_MARK, MSIOF0_TXD_B_MARK, 487 A5_MARK, MSIOF0_RXD_B_MARK, A6_MARK, MSIOF1_SCK_MARK, 488 489 /* IPSR1 */ 490 A7_MARK, MSIOF1_SYNC_MARK, A8_MARK, MSIOF1_SS1_MARK, I2C0_SCL_MARK, 491 A9_MARK, MSIOF1_SS2_MARK, I2C0_SDA_MARK, 492 A10_MARK, MSIOF1_TXD_MARK, MSIOF1_TXD_D_MARK, 493 A11_MARK, MSIOF1_RXD_MARK, I2C3_SCL_D_MARK, MSIOF1_RXD_D_MARK, 494 A12_MARK, FMCLK_MARK, I2C3_SDA_D_MARK, MSIOF1_SCK_D_MARK, 495 A13_MARK, ATAG0_N_C_MARK, BPFCLK_MARK, MSIOF1_SS1_D_MARK, 496 A14_MARK, ATADIR0_N_C_MARK, FMIN_MARK, FMIN_C_MARK, MSIOF1_SYNC_D_MARK, 497 A15_MARK, BPFCLK_C_MARK, 498 A16_MARK, DREQ2_B_MARK, FMCLK_C_MARK, SCIFA1_SCK_B_MARK, 499 A17_MARK, DACK2_B_MARK, I2C0_SDA_C_MARK, 500 A18_MARK, DREQ1_MARK, SCIFA1_RXD_C_MARK, SCIFB1_RXD_C_MARK, 501 502 /* IPSR2 */ 503 A19_MARK, DACK1_MARK, SCIFA1_TXD_C_MARK, 504 SCIFB1_TXD_C_MARK, SCIFB1_SCK_B_MARK, 505 A20_MARK, SPCLK_MARK, 506 A21_MARK, ATAWR0_N_B_MARK, MOSI_IO0_MARK, 507 A22_MARK, MISO_IO1_MARK, FMCLK_B_MARK, TX0_MARK, SCIFA0_TXD_MARK, 508 A23_MARK, IO2_MARK, BPFCLK_B_MARK, RX0_MARK, SCIFA0_RXD_MARK, 509 A24_MARK, DREQ2_MARK, IO3_MARK, TX1_MARK, SCIFA1_TXD_MARK, 510 A25_MARK, DACK2_MARK, SSL_MARK, DREQ1_C_MARK, 511 RX1_MARK, SCIFA1_RXD_MARK, 512 CS0_N_MARK, ATAG0_N_B_MARK, I2C1_SCL_MARK, 513 CS1_N_A26_MARK, ATADIR0_N_B_MARK, I2C1_SDA_MARK, 514 EX_CS1_N_MARK, MSIOF2_SCK_MARK, 515 EX_CS2_N_MARK, ATAWR0_N_MARK, MSIOF2_SYNC_MARK, 516 EX_CS3_N_MARK, ATADIR0_N_MARK, MSIOF2_TXD_MARK, 517 ATAG0_N_MARK, EX_WAIT1_MARK, 518 519 /* IPSR3 */ 520 EX_CS4_N_MARK, ATARD0_N_MARK, MSIOF2_RXD_MARK, EX_WAIT2_MARK, 521 EX_CS5_N_MARK, ATACS00_N_MARK, MSIOF2_SS1_MARK, HRX1_B_MARK, 522 SCIFB1_RXD_B_MARK, PWM1_MARK, TPU_TO1_MARK, 523 BS_N_MARK, ATACS10_N_MARK, MSIOF2_SS2_MARK, HTX1_B_MARK, 524 SCIFB1_TXD_B_MARK, PWM2_MARK, TPU_TO2_MARK, 525 RD_WR_N_MARK, HRX2_B_MARK, FMIN_B_MARK, 526 SCIFB0_RXD_B_MARK, DREQ1_D_MARK, 527 WE0_N_MARK, HCTS2_N_B_MARK, SCIFB0_TXD_B_MARK, 528 WE1_N_MARK, ATARD0_N_B_MARK, HTX2_B_MARK, SCIFB0_RTS_N_B_MARK, 529 EX_WAIT0_MARK, HRTS2_N_B_MARK, SCIFB0_CTS_N_B_MARK, 530 DREQ0_MARK, PWM3_MARK, TPU_TO3_MARK, 531 DACK0_MARK, DRACK0_MARK, REMOCON_MARK, 532 SPEEDIN_MARK, HSCK0_C_MARK, HSCK2_C_MARK, SCIFB0_SCK_B_MARK, 533 SCIFB2_SCK_B_MARK, DREQ2_C_MARK, HTX2_D_MARK, 534 SSI_SCK0129_MARK, HRX0_C_MARK, HRX2_C_MARK, 535 SCIFB0_RXD_C_MARK, SCIFB2_RXD_C_MARK, 536 SSI_WS0129_MARK, HTX0_C_MARK, HTX2_C_MARK, 537 SCIFB0_TXD_C_MARK, SCIFB2_TXD_C_MARK, 538 539 /* IPSR4 */ 540 SSI_SDATA0_MARK, I2C0_SCL_B_MARK, IIC0_SCL_B_MARK, MSIOF2_SCK_C_MARK, 541 SSI_SCK1_MARK, I2C0_SDA_B_MARK, IIC0_SDA_B_MARK, 542 MSIOF2_SYNC_C_MARK, GLO_I0_D_MARK, 543 SSI_WS1_MARK, I2C1_SCL_B_MARK, IIC1_SCL_B_MARK, 544 MSIOF2_TXD_C_MARK, GLO_I1_D_MARK, 545 SSI_SDATA1_MARK, I2C1_SDA_B_MARK, IIC1_SDA_B_MARK, MSIOF2_RXD_C_MARK, 546 SSI_SCK2_MARK, I2C2_SCL_MARK, GPS_CLK_B_MARK, GLO_Q0_D_MARK, 547 HSCK1_E_MARK, 548 SSI_WS2_MARK, I2C2_SDA_MARK, GPS_SIGN_B_MARK, RX2_E_MARK, 549 GLO_Q1_D_MARK, HCTS1_N_E_MARK, 550 SSI_SDATA2_MARK, GPS_MAG_B_MARK, TX2_E_MARK, HRTS1_N_E_MARK, 551 SSI_SCK34_MARK, SSI_WS34_MARK, SSI_SDATA3_MARK, 552 SSI_SCK4_MARK, GLO_SS_D_MARK, 553 SSI_WS4_MARK, GLO_RFON_D_MARK, 554 SSI_SDATA4_MARK, MSIOF2_SCK_D_MARK, 555 SSI_SCK5_MARK, MSIOF1_SCK_C_MARK, TS_SDATA0_MARK, GLO_I0_MARK, 556 MSIOF2_SYNC_D_MARK, VI1_R2_B_MARK, 557 558 /* IPSR5 */ 559 SSI_WS5_MARK, MSIOF1_SYNC_C_MARK, TS_SCK0_MARK, GLO_I1_MARK, 560 MSIOF2_TXD_D_MARK, VI1_R3_B_MARK, 561 SSI_SDATA5_MARK, MSIOF1_TXD_C_MARK, TS_SDEN0_MARK, GLO_Q0_MARK, 562 MSIOF2_SS1_D_MARK, VI1_R4_B_MARK, 563 SSI_SCK6_MARK, MSIOF1_RXD_C_MARK, TS_SPSYNC0_MARK, GLO_Q1_MARK, 564 MSIOF2_RXD_D_MARK, VI1_R5_B_MARK, 565 SSI_WS6_MARK, GLO_SCLK_MARK, MSIOF2_SS2_D_MARK, VI1_R6_B_MARK, 566 SSI_SDATA6_MARK, STP_IVCXO27_0_B_MARK, GLO_SDATA_MARK, VI1_R7_B_MARK, 567 SSI_SCK78_MARK, STP_ISCLK_0_B_MARK, GLO_SS_MARK, 568 SSI_WS78_MARK, TX0_D_MARK, STP_ISD_0_B_MARK, GLO_RFON_MARK, 569 SSI_SDATA7_MARK, RX0_D_MARK, STP_ISEN_0_B_MARK, 570 SSI_SDATA8_MARK, TX1_D_MARK, STP_ISSYNC_0_B_MARK, 571 SSI_SCK9_MARK, RX1_D_MARK, GLO_SCLK_D_MARK, 572 SSI_WS9_MARK, TX3_D_MARK, CAN0_TX_D_MARK, GLO_SDATA_D_MARK, 573 SSI_SDATA9_MARK, RX3_D_MARK, CAN0_RX_D_MARK, 574 575 /* IPSR6 */ 576 AUDIO_CLKB_MARK, STP_OPWM_0_B_MARK, MSIOF1_SCK_B_MARK, 577 SCIF_CLK_MARK, DVC_MUTE_MARK, BPFCLK_E_MARK, 578 AUDIO_CLKC_MARK, SCIFB0_SCK_C_MARK, MSIOF1_SYNC_B_MARK, RX2_MARK, 579 SCIFA2_RXD_MARK, FMIN_E_MARK, 580 AUDIO_CLKOUT_MARK, MSIOF1_SS1_B_MARK, TX2_MARK, SCIFA2_TXD_MARK, 581 IRQ0_MARK, SCIFB1_RXD_D_MARK, INTC_IRQ0_N_MARK, 582 IRQ1_MARK, SCIFB1_SCK_C_MARK, INTC_IRQ1_N_MARK, 583 IRQ2_MARK, SCIFB1_TXD_D_MARK, INTC_IRQ2_N_MARK, 584 IRQ3_MARK, I2C4_SCL_C_MARK, MSIOF2_TXD_E_MARK, INTC_IRQ3_N_MARK, 585 IRQ4_MARK, HRX1_C_MARK, I2C4_SDA_C_MARK, 586 MSIOF2_RXD_E_MARK, INTC_IRQ4_N_MARK, 587 IRQ5_MARK, HTX1_C_MARK, I2C1_SCL_E_MARK, MSIOF2_SCK_E_MARK, 588 IRQ6_MARK, HSCK1_C_MARK, MSIOF1_SS2_B_MARK, 589 I2C1_SDA_E_MARK, MSIOF2_SYNC_E_MARK, 590 IRQ7_MARK, HCTS1_N_C_MARK, MSIOF1_TXD_B_MARK, 591 GPS_CLK_C_MARK, GPS_CLK_D_MARK, 592 IRQ8_MARK, HRTS1_N_C_MARK, MSIOF1_RXD_B_MARK, 593 GPS_SIGN_C_MARK, GPS_SIGN_D_MARK, 594 595 /* IPSR7 */ 596 IRQ9_MARK, DU1_DOTCLKIN_B_MARK, CAN_CLK_D_MARK, GPS_MAG_C_MARK, 597 SCIF_CLK_B_MARK, GPS_MAG_D_MARK, 598 DU1_DR0_MARK, LCDOUT0_MARK, VI1_DATA0_B_MARK, TX0_B_MARK, 599 SCIFA0_TXD_B_MARK, MSIOF2_SCK_B_MARK, 600 DU1_DR1_MARK, LCDOUT1_MARK, VI1_DATA1_B_MARK, RX0_B_MARK, 601 SCIFA0_RXD_B_MARK, MSIOF2_SYNC_B_MARK, 602 DU1_DR2_MARK, LCDOUT2_MARK, SSI_SCK0129_B_MARK, 603 DU1_DR3_MARK, LCDOUT3_MARK, SSI_WS0129_B_MARK, 604 DU1_DR4_MARK, LCDOUT4_MARK, SSI_SDATA0_B_MARK, 605 DU1_DR5_MARK, LCDOUT5_MARK, SSI_SCK1_B_MARK, 606 DU1_DR6_MARK, LCDOUT6_MARK, SSI_WS1_B_MARK, 607 DU1_DR7_MARK, LCDOUT7_MARK, SSI_SDATA1_B_MARK, 608 DU1_DG0_MARK, LCDOUT8_MARK, VI1_DATA2_B_MARK, TX1_B_MARK, 609 SCIFA1_TXD_B_MARK, MSIOF2_SS1_B_MARK, 610 DU1_DG1_MARK, LCDOUT9_MARK, VI1_DATA3_B_MARK, RX1_B_MARK, 611 SCIFA1_RXD_B_MARK, MSIOF2_SS2_B_MARK, 612 DU1_DG2_MARK, LCDOUT10_MARK, VI1_DATA4_B_MARK, SCIF1_SCK_B_MARK, 613 SCIFA1_SCK_MARK, SSI_SCK78_B_MARK, 614 615 /* IPSR8 */ 616 DU1_DG3_MARK, LCDOUT11_MARK, VI1_DATA5_B_MARK, SSI_WS78_B_MARK, 617 DU1_DG4_MARK, LCDOUT12_MARK, VI1_DATA6_B_MARK, HRX0_B_MARK, 618 SCIFB2_RXD_B_MARK, SSI_SDATA7_B_MARK, 619 DU1_DG5_MARK, LCDOUT13_MARK, VI1_DATA7_B_MARK, HCTS0_N_B_MARK, 620 SCIFB2_TXD_B_MARK, SSI_SDATA8_B_MARK, 621 DU1_DG6_MARK, LCDOUT14_MARK, HRTS0_N_B_MARK, 622 SCIFB2_CTS_N_B_MARK, SSI_SCK9_B_MARK, 623 DU1_DG7_MARK, LCDOUT15_MARK, HTX0_B_MARK, 624 SCIFB2_RTS_N_B_MARK, SSI_WS9_B_MARK, 625 DU1_DB0_MARK, LCDOUT16_MARK, VI1_CLK_B_MARK, TX2_B_MARK, 626 SCIFA2_TXD_B_MARK, MSIOF2_TXD_B_MARK, 627 DU1_DB1_MARK, LCDOUT17_MARK, VI1_HSYNC_N_B_MARK, RX2_B_MARK, 628 SCIFA2_RXD_B_MARK, MSIOF2_RXD_B_MARK, 629 DU1_DB2_MARK, LCDOUT18_MARK, VI1_VSYNC_N_B_MARK, SCIF2_SCK_B_MARK, 630 SCIFA2_SCK_MARK, SSI_SDATA9_B_MARK, 631 DU1_DB3_MARK, LCDOUT19_MARK, VI1_CLKENB_B_MARK, 632 DU1_DB4_MARK, LCDOUT20_MARK, VI1_FIELD_B_MARK, CAN1_RX_MARK, 633 DU1_DB5_MARK, LCDOUT21_MARK, TX3_MARK, SCIFA3_TXD_MARK, CAN1_TX_MARK, 634 635 /* IPSR9 */ 636 DU1_DB6_MARK, LCDOUT22_MARK, I2C3_SCL_C_MARK, RX3_MARK, SCIFA3_RXD_MARK, 637 DU1_DB7_MARK, LCDOUT23_MARK, I2C3_SDA_C_MARK, 638 SCIF3_SCK_MARK, SCIFA3_SCK_MARK, 639 DU1_DOTCLKIN_MARK, QSTVA_QVS_MARK, 640 DU1_DOTCLKOUT0_MARK, QCLK_MARK, 641 DU1_DOTCLKOUT1_MARK, QSTVB_QVE_MARK, CAN0_TX_MARK, 642 TX3_B_MARK, I2C2_SCL_B_MARK, PWM4_MARK, 643 DU1_EXHSYNC_DU1_HSYNC_MARK, QSTH_QHS_MARK, 644 DU1_EXVSYNC_DU1_VSYNC_MARK, QSTB_QHE_MARK, 645 DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK, 646 CAN0_RX_MARK, RX3_B_MARK, I2C2_SDA_B_MARK, 647 DU1_DISP_MARK, QPOLA_MARK, 648 DU1_CDE_MARK, QPOLB_MARK, PWM4_B_MARK, 649 VI0_CLKENB_MARK, TX4_MARK, SCIFA4_TXD_MARK, TS_SDATA0_D_MARK, 650 VI0_FIELD_MARK, RX4_MARK, SCIFA4_RXD_MARK, TS_SCK0_D_MARK, 651 VI0_HSYNC_N_MARK, TX5_MARK, SCIFA5_TXD_MARK, TS_SDEN0_D_MARK, 652 VI0_VSYNC_N_MARK, RX5_MARK, SCIFA5_RXD_MARK, TS_SPSYNC0_D_MARK, 653 VI0_DATA3_VI0_B3_MARK, SCIF3_SCK_B_MARK, SCIFA3_SCK_B_MARK, 654 VI0_G0_MARK, IIC1_SCL_MARK, STP_IVCXO27_0_C_MARK, I2C4_SCL_MARK, 655 HCTS2_N_MARK, SCIFB2_CTS_N_MARK, ATAWR1_N_MARK, 656 657 /* IPSR10 */ 658 VI0_G1_MARK, IIC1_SDA_MARK, STP_ISCLK_0_C_MARK, I2C4_SDA_MARK, 659 HRTS2_N_MARK, SCIFB2_RTS_N_MARK, ATADIR1_N_MARK, 660 VI0_G2_MARK, VI2_HSYNC_N_MARK, STP_ISD_0_C_MARK, I2C3_SCL_B_MARK, 661 HSCK2_MARK, SCIFB2_SCK_MARK, ATARD1_N_MARK, 662 VI0_G3_MARK, VI2_VSYNC_N_MARK, STP_ISEN_0_C_MARK, I2C3_SDA_B_MARK, 663 HRX2_MARK, SCIFB2_RXD_MARK, ATACS01_N_MARK, 664 VI0_G4_MARK, VI2_CLKENB_MARK, STP_ISSYNC_0_C_MARK, 665 HTX2_MARK, SCIFB2_TXD_MARK, SCIFB0_SCK_D_MARK, 666 VI0_G5_MARK, VI2_FIELD_MARK, STP_OPWM_0_C_MARK, FMCLK_D_MARK, 667 CAN0_TX_E_MARK, HTX1_D_MARK, SCIFB0_TXD_D_MARK, 668 VI0_G6_MARK, VI2_CLK_MARK, BPFCLK_D_MARK, 669 VI0_G7_MARK, VI2_DATA0_MARK, FMIN_D_MARK, 670 VI0_R0_MARK, VI2_DATA1_MARK, GLO_I0_B_MARK, 671 TS_SDATA0_C_MARK, ATACS11_N_MARK, 672 VI0_R1_MARK, VI2_DATA2_MARK, GLO_I1_B_MARK, 673 TS_SCK0_C_MARK, ATAG1_N_MARK, 674 VI0_R2_MARK, VI2_DATA3_MARK, GLO_Q0_B_MARK, TS_SDEN0_C_MARK, 675 VI0_R3_MARK, VI2_DATA4_MARK, GLO_Q1_B_MARK, TS_SPSYNC0_C_MARK, 676 VI0_R4_MARK, VI2_DATA5_MARK, GLO_SCLK_B_MARK, TX0_C_MARK, 677 I2C1_SCL_D_MARK, 678 679 /* IPSR11 */ 680 VI0_R5_MARK, VI2_DATA6_MARK, GLO_SDATA_B_MARK, RX0_C_MARK, 681 I2C1_SDA_D_MARK, 682 VI0_R6_MARK, VI2_DATA7_MARK, GLO_SS_B_MARK, TX1_C_MARK, I2C4_SCL_B_MARK, 683 VI0_R7_MARK, GLO_RFON_B_MARK, RX1_C_MARK, CAN0_RX_E_MARK, 684 I2C4_SDA_B_MARK, HRX1_D_MARK, SCIFB0_RXD_D_MARK, 685 VI1_HSYNC_N_MARK, AVB_RXD0_MARK, TS_SDATA0_B_MARK, 686 TX4_B_MARK, SCIFA4_TXD_B_MARK, 687 VI1_VSYNC_N_MARK, AVB_RXD1_MARK, TS_SCK0_B_MARK, 688 RX4_B_MARK, SCIFA4_RXD_B_MARK, 689 VI1_CLKENB_MARK, AVB_RXD2_MARK, TS_SDEN0_B_MARK, 690 VI1_FIELD_MARK, AVB_RXD3_MARK, TS_SPSYNC0_B_MARK, 691 VI1_CLK_MARK, AVB_RXD4_MARK, VI1_DATA0_MARK, AVB_RXD5_MARK, 692 VI1_DATA1_MARK, AVB_RXD6_MARK, VI1_DATA2_MARK, AVB_RXD7_MARK, 693 VI1_DATA3_MARK, AVB_RX_ER_MARK, VI1_DATA4_MARK, AVB_MDIO_MARK, 694 VI1_DATA5_MARK, AVB_RX_DV_MARK, VI1_DATA6_MARK, AVB_MAGIC_MARK, 695 VI1_DATA7_MARK, AVB_MDC_MARK, 696 ETH_MDIO_MARK, AVB_RX_CLK_MARK, I2C2_SCL_C_MARK, 697 ETH_CRS_DV_MARK, AVB_LINK_MARK, I2C2_SDA_C_MARK, 698 699 /* IPSR12 */ 700 ETH_RX_ER_MARK, AVB_CRS_MARK, I2C3_SCL_MARK, IIC0_SCL_MARK, 701 ETH_RXD0_MARK, AVB_PHY_INT_MARK, I2C3_SDA_MARK, IIC0_SDA_MARK, 702 ETH_RXD1_MARK, AVB_GTXREFCLK_MARK, CAN0_TX_C_MARK, 703 I2C2_SCL_D_MARK, MSIOF1_RXD_E_MARK, 704 ETH_LINK_MARK, AVB_TXD0_MARK, CAN0_RX_C_MARK, 705 I2C2_SDA_D_MARK, MSIOF1_SCK_E_MARK, 706 ETH_REFCLK_MARK, AVB_TXD1_MARK, SCIFA3_RXD_B_MARK, 707 CAN1_RX_C_MARK, MSIOF1_SYNC_E_MARK, 708 ETH_TXD1_MARK, AVB_TXD2_MARK, SCIFA3_TXD_B_MARK, 709 CAN1_TX_C_MARK, MSIOF1_TXD_E_MARK, 710 ETH_TX_EN_MARK, AVB_TXD3_MARK, TCLK1_B_MARK, CAN_CLK_B_MARK, 711 ETH_MAGIC_MARK, AVB_TXD4_MARK, IETX_C_MARK, 712 ETH_TXD0_MARK, AVB_TXD5_MARK, IECLK_C_MARK, 713 ETH_MDC_MARK, AVB_TXD6_MARK, IERX_C_MARK, 714 STP_IVCXO27_0_MARK, AVB_TXD7_MARK, SCIFB2_TXD_D_MARK, 715 ADIDATA_B_MARK, MSIOF0_SYNC_C_MARK, 716 STP_ISCLK_0_MARK, AVB_TX_EN_MARK, SCIFB2_RXD_D_MARK, 717 ADICS_SAMP_B_MARK, MSIOF0_SCK_C_MARK, 718 719 /* IPSR13 */ 720 STP_ISD_0_MARK, AVB_TX_ER_MARK, SCIFB2_SCK_C_MARK, 721 ADICLK_B_MARK, MSIOF0_SS1_C_MARK, 722 STP_ISEN_0_MARK, AVB_TX_CLK_MARK, ADICHS0_B_MARK, MSIOF0_SS2_C_MARK, 723 STP_ISSYNC_0_MARK, AVB_COL_MARK, ADICHS1_B_MARK, MSIOF0_RXD_C_MARK, 724 STP_OPWM_0_MARK, AVB_GTX_CLK_MARK, PWM0_B_MARK, 725 ADICHS2_B_MARK, MSIOF0_TXD_C_MARK, 726 SD0_CLK_MARK, SPCLK_B_MARK, SD0_CMD_MARK, MOSI_IO0_B_MARK, 727 SD0_DATA0_MARK, MISO_IO1_B_MARK, SD0_DATA1_MARK, IO2_B_MARK, 728 SD0_DATA2_MARK, IO3_B_MARK, SD0_DATA3_MARK, SSL_B_MARK, 729 SD0_CD_MARK, MMC_D6_B_MARK, SIM0_RST_B_MARK, CAN0_RX_F_MARK, 730 SCIFA5_TXD_B_MARK, TX3_C_MARK, 731 SD0_WP_MARK, MMC_D7_B_MARK, SIM0_D_B_MARK, CAN0_TX_F_MARK, 732 SCIFA5_RXD_B_MARK, RX3_C_MARK, 733 SD1_CMD_MARK, REMOCON_B_MARK, SD1_DATA0_MARK, SPEEDIN_B_MARK, 734 SD1_DATA1_MARK, IETX_B_MARK, SD1_DATA2_MARK, IECLK_B_MARK, 735 SD1_DATA3_MARK, IERX_B_MARK, 736 SD1_CD_MARK, PWM0_MARK, TPU_TO0_MARK, I2C1_SCL_C_MARK, 737 738 /* IPSR14 */ 739 SD1_WP_MARK, PWM1_B_MARK, I2C1_SDA_C_MARK, 740 SD2_CLK_MARK, MMC_CLK_MARK, SD2_CMD_MARK, MMC_CMD_MARK, 741 SD2_DATA0_MARK, MMC_D0_MARK, SD2_DATA1_MARK, MMC_D1_MARK, 742 SD2_DATA2_MARK, MMC_D2_MARK, SD2_DATA3_MARK, MMC_D3_MARK, 743 SD2_CD_MARK, MMC_D4_MARK, IIC1_SCL_C_MARK, TX5_B_MARK, 744 SCIFA5_TXD_C_MARK, 745 SD2_WP_MARK, MMC_D5_MARK, IIC1_SDA_C_MARK, RX5_B_MARK, 746 SCIFA5_RXD_C_MARK, 747 MSIOF0_SCK_MARK, RX2_C_MARK, ADIDATA_MARK, 748 VI1_CLK_C_MARK, VI1_G0_B_MARK, 749 MSIOF0_SYNC_MARK, TX2_C_MARK, ADICS_SAMP_MARK, 750 VI1_CLKENB_C_MARK, VI1_G1_B_MARK, 751 MSIOF0_TXD_MARK, ADICLK_MARK, VI1_FIELD_C_MARK, VI1_G2_B_MARK, 752 MSIOF0_RXD_MARK, ADICHS0_MARK, VI1_DATA0_C_MARK, VI1_G3_B_MARK, 753 MSIOF0_SS1_MARK, MMC_D6_MARK, ADICHS1_MARK, TX0_E_MARK, 754 VI1_HSYNC_N_C_MARK, IIC0_SCL_C_MARK, VI1_G4_B_MARK, 755 MSIOF0_SS2_MARK, MMC_D7_MARK, ADICHS2_MARK, RX0_E_MARK, 756 VI1_VSYNC_N_C_MARK, IIC0_SDA_C_MARK, VI1_G5_B_MARK, 757 758 /* IPSR15 */ 759 SIM0_RST_MARK, IETX_MARK, CAN1_TX_D_MARK, 760 SIM0_CLK_MARK, IECLK_MARK, CAN_CLK_C_MARK, 761 SIM0_D_MARK, IERX_MARK, CAN1_RX_D_MARK, 762 GPS_CLK_MARK, DU1_DOTCLKIN_C_MARK, AUDIO_CLKB_B_MARK, 763 PWM5_B_MARK, SCIFA3_TXD_C_MARK, 764 GPS_SIGN_MARK, TX4_C_MARK, SCIFA4_TXD_C_MARK, PWM5_MARK, 765 VI1_G6_B_MARK, SCIFA3_RXD_C_MARK, 766 GPS_MAG_MARK, RX4_C_MARK, SCIFA4_RXD_C_MARK, PWM6_MARK, 767 VI1_G7_B_MARK, SCIFA3_SCK_C_MARK, 768 HCTS0_N_MARK, SCIFB0_CTS_N_MARK, GLO_I0_C_MARK, 769 TCLK1_MARK, VI1_DATA1_C_MARK, 770 HRTS0_N_MARK, SCIFB0_RTS_N_MARK, GLO_I1_C_MARK, VI1_DATA2_C_MARK, 771 HSCK0_MARK, SCIFB0_SCK_MARK, GLO_Q0_C_MARK, CAN_CLK_MARK, 772 TCLK2_MARK, VI1_DATA3_C_MARK, 773 HRX0_MARK, SCIFB0_RXD_MARK, GLO_Q1_C_MARK, 774 CAN0_RX_B_MARK, VI1_DATA4_C_MARK, 775 HTX0_MARK, SCIFB0_TXD_MARK, GLO_SCLK_C_MARK, 776 CAN0_TX_B_MARK, VI1_DATA5_C_MARK, 777 778 /* IPSR16 */ 779 HRX1_MARK, SCIFB1_RXD_MARK, VI1_R0_B_MARK, 780 GLO_SDATA_C_MARK, VI1_DATA6_C_MARK, 781 HTX1_MARK, SCIFB1_TXD_MARK, VI1_R1_B_MARK, 782 GLO_SS_C_MARK, VI1_DATA7_C_MARK, 783 HSCK1_MARK, SCIFB1_SCK_MARK, MLB_CLK_MARK, GLO_RFON_C_MARK, 784 HCTS1_N_MARK, SCIFB1_CTS_N_MARK, MLB_SIG_MARK, CAN1_TX_B_MARK, 785 HRTS1_N_MARK, SCIFB1_RTS_N_MARK, MLB_DAT_MARK, CAN1_RX_B_MARK, 786 PINMUX_MARK_END, 787 }; 788 789 static const u16 pinmux_data[] = { 790 PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */ 791 792 PINMUX_SINGLE(EX_CS0_N), 793 PINMUX_SINGLE(RD_N), 794 PINMUX_SINGLE(AUDIO_CLKA), 795 PINMUX_SINGLE(VI0_CLK), 796 PINMUX_SINGLE(VI0_DATA0_VI0_B0), 797 PINMUX_SINGLE(VI0_DATA1_VI0_B1), 798 PINMUX_SINGLE(VI0_DATA2_VI0_B2), 799 PINMUX_SINGLE(VI0_DATA4_VI0_B4), 800 PINMUX_SINGLE(VI0_DATA5_VI0_B5), 801 PINMUX_SINGLE(VI0_DATA6_VI0_B6), 802 PINMUX_SINGLE(VI0_DATA7_VI0_B7), 803 PINMUX_SINGLE(USB0_PWEN), 804 PINMUX_SINGLE(USB0_OVC), 805 PINMUX_SINGLE(USB1_PWEN), 806 PINMUX_SINGLE(USB1_OVC), 807 PINMUX_SINGLE(DU0_DOTCLKIN), 808 PINMUX_SINGLE(SD1_CLK), 809 810 /* IPSR0 */ 811 PINMUX_IPSR_GPSR(IP0_0, D0), 812 PINMUX_IPSR_GPSR(IP0_1, D1), 813 PINMUX_IPSR_GPSR(IP0_2, D2), 814 PINMUX_IPSR_GPSR(IP0_3, D3), 815 PINMUX_IPSR_GPSR(IP0_4, D4), 816 PINMUX_IPSR_GPSR(IP0_5, D5), 817 PINMUX_IPSR_GPSR(IP0_6, D6), 818 PINMUX_IPSR_GPSR(IP0_7, D7), 819 PINMUX_IPSR_GPSR(IP0_8, D8), 820 PINMUX_IPSR_GPSR(IP0_9, D9), 821 PINMUX_IPSR_GPSR(IP0_10, D10), 822 PINMUX_IPSR_GPSR(IP0_11, D11), 823 PINMUX_IPSR_GPSR(IP0_12, D12), 824 PINMUX_IPSR_GPSR(IP0_13, D13), 825 PINMUX_IPSR_GPSR(IP0_14, D14), 826 PINMUX_IPSR_GPSR(IP0_15, D15), 827 PINMUX_IPSR_GPSR(IP0_18_16, A0), 828 PINMUX_IPSR_MSEL(IP0_18_16, ATAWR0_N_C, SEL_LBS_2), 829 PINMUX_IPSR_MSEL(IP0_18_16, MSIOF0_SCK_B, SEL_SOF0_1), 830 PINMUX_IPSR_MSEL(IP0_18_16, I2C0_SCL_C, SEL_I2C0_2), 831 PINMUX_IPSR_GPSR(IP0_18_16, PWM2_B), 832 PINMUX_IPSR_GPSR(IP0_20_19, A1), 833 PINMUX_IPSR_MSEL(IP0_20_19, MSIOF0_SYNC_B, SEL_SOF0_1), 834 PINMUX_IPSR_GPSR(IP0_22_21, A2), 835 PINMUX_IPSR_MSEL(IP0_22_21, MSIOF0_SS1_B, SEL_SOF0_1), 836 PINMUX_IPSR_GPSR(IP0_24_23, A3), 837 PINMUX_IPSR_MSEL(IP0_24_23, MSIOF0_SS2_B, SEL_SOF0_1), 838 PINMUX_IPSR_GPSR(IP0_26_25, A4), 839 PINMUX_IPSR_MSEL(IP0_26_25, MSIOF0_TXD_B, SEL_SOF0_1), 840 PINMUX_IPSR_GPSR(IP0_28_27, A5), 841 PINMUX_IPSR_MSEL(IP0_28_27, MSIOF0_RXD_B, SEL_SOF0_1), 842 PINMUX_IPSR_GPSR(IP0_30_29, A6), 843 PINMUX_IPSR_MSEL(IP0_30_29, MSIOF1_SCK, SEL_SOF1_0), 844 845 /* IPSR1 */ 846 PINMUX_IPSR_GPSR(IP1_1_0, A7), 847 PINMUX_IPSR_MSEL(IP1_1_0, MSIOF1_SYNC, SEL_SOF1_0), 848 PINMUX_IPSR_GPSR(IP1_3_2, A8), 849 PINMUX_IPSR_MSEL(IP1_3_2, MSIOF1_SS1, SEL_SOF1_0), 850 PINMUX_IPSR_MSEL(IP1_3_2, I2C0_SCL, SEL_I2C0_0), 851 PINMUX_IPSR_GPSR(IP1_5_4, A9), 852 PINMUX_IPSR_MSEL(IP1_5_4, MSIOF1_SS2, SEL_SOF1_0), 853 PINMUX_IPSR_MSEL(IP1_5_4, I2C0_SDA, SEL_I2C0_0), 854 PINMUX_IPSR_GPSR(IP1_7_6, A10), 855 PINMUX_IPSR_MSEL(IP1_7_6, MSIOF1_TXD, SEL_SOF1_0), 856 PINMUX_IPSR_MSEL(IP1_7_6, MSIOF1_TXD_D, SEL_SOF1_3), 857 PINMUX_IPSR_GPSR(IP1_10_8, A11), 858 PINMUX_IPSR_MSEL(IP1_10_8, MSIOF1_RXD, SEL_SOF1_0), 859 PINMUX_IPSR_MSEL(IP1_10_8, I2C3_SCL_D, SEL_I2C3_3), 860 PINMUX_IPSR_MSEL(IP1_10_8, MSIOF1_RXD_D, SEL_SOF1_3), 861 PINMUX_IPSR_GPSR(IP1_13_11, A12), 862 PINMUX_IPSR_MSEL(IP1_13_11, FMCLK, SEL_FM_0), 863 PINMUX_IPSR_MSEL(IP1_13_11, I2C3_SDA_D, SEL_I2C3_3), 864 PINMUX_IPSR_MSEL(IP1_13_11, MSIOF1_SCK_D, SEL_SOF1_3), 865 PINMUX_IPSR_GPSR(IP1_16_14, A13), 866 PINMUX_IPSR_MSEL(IP1_16_14, ATAG0_N_C, SEL_LBS_2), 867 PINMUX_IPSR_MSEL(IP1_16_14, BPFCLK, SEL_FM_0), 868 PINMUX_IPSR_MSEL(IP1_16_14, MSIOF1_SS1_D, SEL_SOF1_3), 869 PINMUX_IPSR_GPSR(IP1_19_17, A14), 870 PINMUX_IPSR_MSEL(IP1_19_17, ATADIR0_N_C, SEL_LBS_2), 871 PINMUX_IPSR_MSEL(IP1_19_17, FMIN, SEL_FM_0), 872 PINMUX_IPSR_MSEL(IP1_19_17, FMIN_C, SEL_FM_2), 873 PINMUX_IPSR_MSEL(IP1_19_17, MSIOF1_SYNC_D, SEL_SOF1_3), 874 PINMUX_IPSR_GPSR(IP1_22_20, A15), 875 PINMUX_IPSR_MSEL(IP1_22_20, BPFCLK_C, SEL_FM_2), 876 PINMUX_IPSR_GPSR(IP1_25_23, A16), 877 PINMUX_IPSR_MSEL(IP1_25_23, DREQ2_B, SEL_LBS_1), 878 PINMUX_IPSR_MSEL(IP1_25_23, FMCLK_C, SEL_FM_2), 879 PINMUX_IPSR_MSEL(IP1_25_23, SCIFA1_SCK_B, SEL_SCIFA1_1), 880 PINMUX_IPSR_GPSR(IP1_28_26, A17), 881 PINMUX_IPSR_MSEL(IP1_28_26, DACK2_B, SEL_LBS_1), 882 PINMUX_IPSR_MSEL(IP1_28_26, I2C0_SDA_C, SEL_I2C0_2), 883 PINMUX_IPSR_GPSR(IP1_31_29, A18), 884 PINMUX_IPSR_MSEL(IP1_31_29, DREQ1, SEL_LBS_0), 885 PINMUX_IPSR_MSEL(IP1_31_29, SCIFA1_RXD_C, SEL_SCIFA1_2), 886 PINMUX_IPSR_MSEL(IP1_31_29, SCIFB1_RXD_C, SEL_SCIFB1_2), 887 888 /* IPSR2 */ 889 PINMUX_IPSR_GPSR(IP2_2_0, A19), 890 PINMUX_IPSR_GPSR(IP2_2_0, DACK1), 891 PINMUX_IPSR_MSEL(IP2_2_0, SCIFA1_TXD_C, SEL_SCIFA1_2), 892 PINMUX_IPSR_MSEL(IP2_2_0, SCIFB1_TXD_C, SEL_SCIFB1_2), 893 PINMUX_IPSR_MSEL(IP2_2_0, SCIFB1_SCK_B, SEL_SCIFB1_1), 894 PINMUX_IPSR_GPSR(IP2_2_0, A20), 895 PINMUX_IPSR_MSEL(IP2_4_3, SPCLK, SEL_QSP_0), 896 PINMUX_IPSR_GPSR(IP2_6_5, A21), 897 PINMUX_IPSR_MSEL(IP2_6_5, ATAWR0_N_B, SEL_LBS_1), 898 PINMUX_IPSR_MSEL(IP2_6_5, MOSI_IO0, SEL_QSP_0), 899 PINMUX_IPSR_GPSR(IP2_9_7, A22), 900 PINMUX_IPSR_MSEL(IP2_9_7, MISO_IO1, SEL_QSP_0), 901 PINMUX_IPSR_MSEL(IP2_9_7, FMCLK_B, SEL_FM_1), 902 PINMUX_IPSR_MSEL(IP2_9_7, TX0, SEL_SCIF0_0), 903 PINMUX_IPSR_MSEL(IP2_9_7, SCIFA0_TXD, SEL_SCFA_0), 904 PINMUX_IPSR_GPSR(IP2_12_10, A23), 905 PINMUX_IPSR_MSEL(IP2_12_10, IO2, SEL_QSP_0), 906 PINMUX_IPSR_MSEL(IP2_12_10, BPFCLK_B, SEL_FM_1), 907 PINMUX_IPSR_MSEL(IP2_12_10, RX0, SEL_SCIF0_0), 908 PINMUX_IPSR_MSEL(IP2_12_10, SCIFA0_RXD, SEL_SCFA_0), 909 PINMUX_IPSR_GPSR(IP2_15_13, A24), 910 PINMUX_IPSR_MSEL(IP2_15_13, DREQ2, SEL_LBS_0), 911 PINMUX_IPSR_MSEL(IP2_15_13, IO3, SEL_QSP_0), 912 PINMUX_IPSR_MSEL(IP2_15_13, TX1, SEL_SCIF1_0), 913 PINMUX_IPSR_MSEL(IP2_15_13, SCIFA1_TXD, SEL_SCIFA1_0), 914 PINMUX_IPSR_GPSR(IP2_18_16, A25), 915 PINMUX_IPSR_MSEL(IP2_18_16, DACK2, SEL_LBS_0), 916 PINMUX_IPSR_MSEL(IP2_18_16, SSL, SEL_QSP_0), 917 PINMUX_IPSR_MSEL(IP2_18_16, DREQ1_C, SEL_LBS_2), 918 PINMUX_IPSR_MSEL(IP2_18_16, RX1, SEL_SCIF1_0), 919 PINMUX_IPSR_MSEL(IP2_18_16, SCIFA1_RXD, SEL_SCIFA1_0), 920 PINMUX_IPSR_GPSR(IP2_20_19, CS0_N), 921 PINMUX_IPSR_MSEL(IP2_20_19, ATAG0_N_B, SEL_LBS_1), 922 PINMUX_IPSR_MSEL(IP2_20_19, I2C1_SCL, SEL_I2C1_0), 923 PINMUX_IPSR_GPSR(IP2_22_21, CS1_N_A26), 924 PINMUX_IPSR_MSEL(IP2_22_21, ATADIR0_N_B, SEL_LBS_1), 925 PINMUX_IPSR_MSEL(IP2_22_21, I2C1_SDA, SEL_I2C1_0), 926 PINMUX_IPSR_GPSR(IP2_24_23, EX_CS1_N), 927 PINMUX_IPSR_MSEL(IP2_24_23, MSIOF2_SCK, SEL_SOF2_0), 928 PINMUX_IPSR_GPSR(IP2_26_25, EX_CS2_N), 929 PINMUX_IPSR_MSEL(IP2_26_25, ATAWR0_N, SEL_LBS_0), 930 PINMUX_IPSR_MSEL(IP2_26_25, MSIOF2_SYNC, SEL_SOF2_0), 931 PINMUX_IPSR_GPSR(IP2_29_27, EX_CS3_N), 932 PINMUX_IPSR_MSEL(IP2_29_27, ATADIR0_N, SEL_LBS_0), 933 PINMUX_IPSR_MSEL(IP2_29_27, MSIOF2_TXD, SEL_SOF2_0), 934 PINMUX_IPSR_MSEL(IP2_29_27, ATAG0_N, SEL_LBS_0), 935 PINMUX_IPSR_GPSR(IP2_29_27, EX_WAIT1), 936 937 /* IPSR3 */ 938 PINMUX_IPSR_GPSR(IP3_2_0, EX_CS4_N), 939 PINMUX_IPSR_MSEL(IP3_2_0, ATARD0_N, SEL_LBS_0), 940 PINMUX_IPSR_MSEL(IP3_2_0, MSIOF2_RXD, SEL_SOF2_0), 941 PINMUX_IPSR_GPSR(IP3_2_0, EX_WAIT2), 942 PINMUX_IPSR_GPSR(IP3_5_3, EX_CS5_N), 943 PINMUX_IPSR_GPSR(IP3_5_3, ATACS00_N), 944 PINMUX_IPSR_MSEL(IP3_5_3, MSIOF2_SS1, SEL_SOF2_0), 945 PINMUX_IPSR_MSEL(IP3_5_3, HRX1_B, SEL_HSCIF1_1), 946 PINMUX_IPSR_MSEL(IP3_5_3, SCIFB1_RXD_B, SEL_SCIFB1_1), 947 PINMUX_IPSR_GPSR(IP3_5_3, PWM1), 948 PINMUX_IPSR_GPSR(IP3_5_3, TPU_TO1), 949 PINMUX_IPSR_GPSR(IP3_8_6, BS_N), 950 PINMUX_IPSR_GPSR(IP3_8_6, ATACS10_N), 951 PINMUX_IPSR_MSEL(IP3_8_6, MSIOF2_SS2, SEL_SOF2_0), 952 PINMUX_IPSR_MSEL(IP3_8_6, HTX1_B, SEL_HSCIF1_1), 953 PINMUX_IPSR_MSEL(IP3_8_6, SCIFB1_TXD_B, SEL_SCIFB1_1), 954 PINMUX_IPSR_GPSR(IP3_8_6, PWM2), 955 PINMUX_IPSR_GPSR(IP3_8_6, TPU_TO2), 956 PINMUX_IPSR_GPSR(IP3_11_9, RD_WR_N), 957 PINMUX_IPSR_MSEL(IP3_11_9, HRX2_B, SEL_HSCIF2_1), 958 PINMUX_IPSR_MSEL(IP3_11_9, FMIN_B, SEL_FM_1), 959 PINMUX_IPSR_MSEL(IP3_11_9, SCIFB0_RXD_B, SEL_SCIFB_1), 960 PINMUX_IPSR_MSEL(IP3_11_9, DREQ1_D, SEL_LBS_1), 961 PINMUX_IPSR_GPSR(IP3_13_12, WE0_N), 962 PINMUX_IPSR_MSEL(IP3_13_12, HCTS2_N_B, SEL_HSCIF2_1), 963 PINMUX_IPSR_MSEL(IP3_13_12, SCIFB0_TXD_B, SEL_SCIFB_1), 964 PINMUX_IPSR_GPSR(IP3_15_14, WE1_N), 965 PINMUX_IPSR_MSEL(IP3_15_14, ATARD0_N_B, SEL_LBS_1), 966 PINMUX_IPSR_MSEL(IP3_15_14, HTX2_B, SEL_HSCIF2_1), 967 PINMUX_IPSR_MSEL(IP3_15_14, SCIFB0_RTS_N_B, SEL_SCIFB_1), 968 PINMUX_IPSR_GPSR(IP3_17_16, EX_WAIT0), 969 PINMUX_IPSR_MSEL(IP3_17_16, HRTS2_N_B, SEL_HSCIF2_1), 970 PINMUX_IPSR_MSEL(IP3_17_16, SCIFB0_CTS_N_B, SEL_SCIFB_1), 971 PINMUX_IPSR_GPSR(IP3_19_18, DREQ0), 972 PINMUX_IPSR_GPSR(IP3_19_18, PWM3), 973 PINMUX_IPSR_GPSR(IP3_19_18, TPU_TO3), 974 PINMUX_IPSR_GPSR(IP3_21_20, DACK0), 975 PINMUX_IPSR_GPSR(IP3_21_20, DRACK0), 976 PINMUX_IPSR_MSEL(IP3_21_20, REMOCON, SEL_RCN_0), 977 PINMUX_IPSR_MSEL(IP3_24_22, SPEEDIN, SEL_RSP_0), 978 PINMUX_IPSR_MSEL(IP3_24_22, HSCK0_C, SEL_HSCIF0_2), 979 PINMUX_IPSR_MSEL(IP3_24_22, HSCK2_C, SEL_HSCIF2_2), 980 PINMUX_IPSR_MSEL(IP3_24_22, SCIFB0_SCK_B, SEL_SCIFB_1), 981 PINMUX_IPSR_MSEL(IP3_24_22, SCIFB2_SCK_B, SEL_SCIFB2_1), 982 PINMUX_IPSR_MSEL(IP3_24_22, DREQ2_C, SEL_LBS_2), 983 PINMUX_IPSR_MSEL(IP3_30_28, HTX2_C, SEL_HSCIF2_2), 984 PINMUX_IPSR_MSEL(IP3_27_25, SSI_SCK0129, SEL_SSI0_0), 985 PINMUX_IPSR_MSEL(IP3_27_25, HRX0_C, SEL_HSCIF0_2), 986 PINMUX_IPSR_MSEL(IP3_27_25, HRX2_C, SEL_HSCIF2_2), 987 PINMUX_IPSR_MSEL(IP3_27_25, SCIFB0_RXD_C, SEL_SCIFB_2), 988 PINMUX_IPSR_MSEL(IP3_27_25, SCIFB2_RXD_C, SEL_SCIFB2_2), 989 PINMUX_IPSR_MSEL(IP3_30_28, SSI_WS0129, SEL_SSI0_0), 990 PINMUX_IPSR_MSEL(IP3_30_28, HTX0_C, SEL_HSCIF0_2), 991 PINMUX_IPSR_MSEL(IP3_30_28, HTX2_C, SEL_HSCIF2_2), 992 PINMUX_IPSR_MSEL(IP3_30_28, SCIFB0_TXD_C, SEL_SCIFB_2), 993 PINMUX_IPSR_MSEL(IP3_30_28, SCIFB2_TXD_C, SEL_SCIFB2_2), 994 995 /* IPSR4 */ 996 PINMUX_IPSR_MSEL(IP4_1_0, SSI_SDATA0, SEL_SSI0_0), 997 PINMUX_IPSR_MSEL(IP4_1_0, I2C0_SCL_B, SEL_I2C0_1), 998 PINMUX_IPSR_MSEL(IP4_1_0, IIC0_SCL_B, SEL_IIC0_1), 999 PINMUX_IPSR_MSEL(IP4_1_0, MSIOF2_SCK_C, SEL_SOF2_2), 1000 PINMUX_IPSR_MSEL(IP4_4_2, SSI_SCK1, SEL_SSI1_0), 1001 PINMUX_IPSR_MSEL(IP4_4_2, I2C0_SDA_B, SEL_I2C0_1), 1002 PINMUX_IPSR_MSEL(IP4_4_2, IIC0_SDA_B, SEL_IIC0_1), 1003 PINMUX_IPSR_MSEL(IP4_4_2, MSIOF2_SYNC_C, SEL_SOF2_2), 1004 PINMUX_IPSR_MSEL(IP4_4_2, GLO_I0_D, SEL_GPS_3), 1005 PINMUX_IPSR_MSEL(IP4_7_5, SSI_WS1, SEL_SSI1_0), 1006 PINMUX_IPSR_MSEL(IP4_7_5, I2C1_SCL_B, SEL_I2C1_1), 1007 PINMUX_IPSR_MSEL(IP4_7_5, IIC1_SCL_B, SEL_IIC1_1), 1008 PINMUX_IPSR_MSEL(IP4_7_5, MSIOF2_TXD_C, SEL_SOF2_2), 1009 PINMUX_IPSR_MSEL(IP4_7_5, GLO_I1_D, SEL_GPS_3), 1010 PINMUX_IPSR_MSEL(IP4_9_8, SSI_SDATA1, SEL_SSI1_0), 1011 PINMUX_IPSR_MSEL(IP4_9_8, I2C1_SDA_B, SEL_I2C1_1), 1012 PINMUX_IPSR_MSEL(IP4_9_8, IIC1_SDA_B, SEL_IIC1_1), 1013 PINMUX_IPSR_MSEL(IP4_9_8, MSIOF2_RXD_C, SEL_SOF2_2), 1014 PINMUX_IPSR_GPSR(IP4_12_10, SSI_SCK2), 1015 PINMUX_IPSR_MSEL(IP4_12_10, I2C2_SCL, SEL_I2C2_0), 1016 PINMUX_IPSR_MSEL(IP4_12_10, GPS_CLK_B, SEL_GPS_1), 1017 PINMUX_IPSR_MSEL(IP4_12_10, GLO_Q0_D, SEL_GPS_3), 1018 PINMUX_IPSR_MSEL(IP4_12_10, HSCK1_E, SEL_HSCIF1_4), 1019 PINMUX_IPSR_GPSR(IP4_15_13, SSI_WS2), 1020 PINMUX_IPSR_MSEL(IP4_15_13, I2C2_SDA, SEL_I2C2_0), 1021 PINMUX_IPSR_MSEL(IP4_15_13, GPS_SIGN_B, SEL_GPS_1), 1022 PINMUX_IPSR_MSEL(IP4_15_13, RX2_E, SEL_SCIF2_4), 1023 PINMUX_IPSR_MSEL(IP4_15_13, GLO_Q1_D, SEL_GPS_3), 1024 PINMUX_IPSR_MSEL(IP4_15_13, HCTS1_N_E, SEL_HSCIF1_4), 1025 PINMUX_IPSR_GPSR(IP4_18_16, SSI_SDATA2), 1026 PINMUX_IPSR_MSEL(IP4_18_16, GPS_MAG_B, SEL_GPS_1), 1027 PINMUX_IPSR_MSEL(IP4_18_16, TX2_E, SEL_SCIF2_4), 1028 PINMUX_IPSR_MSEL(IP4_18_16, HRTS1_N_E, SEL_HSCIF1_4), 1029 PINMUX_IPSR_GPSR(IP4_19, SSI_SCK34), 1030 PINMUX_IPSR_GPSR(IP4_20, SSI_WS34), 1031 PINMUX_IPSR_GPSR(IP4_21, SSI_SDATA3), 1032 PINMUX_IPSR_GPSR(IP4_23_22, SSI_SCK4), 1033 PINMUX_IPSR_MSEL(IP4_23_22, GLO_SS_D, SEL_GPS_3), 1034 PINMUX_IPSR_GPSR(IP4_25_24, SSI_WS4), 1035 PINMUX_IPSR_MSEL(IP4_25_24, GLO_RFON_D, SEL_GPS_3), 1036 PINMUX_IPSR_GPSR(IP4_27_26, SSI_SDATA4), 1037 PINMUX_IPSR_MSEL(IP4_27_26, MSIOF2_SCK_D, SEL_SOF2_3), 1038 PINMUX_IPSR_GPSR(IP4_30_28, SSI_SCK5), 1039 PINMUX_IPSR_MSEL(IP4_30_28, MSIOF1_SCK_C, SEL_SOF1_2), 1040 PINMUX_IPSR_MSEL(IP4_30_28, TS_SDATA0, SEL_TSIF0_0), 1041 PINMUX_IPSR_MSEL(IP4_30_28, GLO_I0, SEL_GPS_0), 1042 PINMUX_IPSR_MSEL(IP4_30_28, MSIOF2_SYNC_D, SEL_SOF2_3), 1043 PINMUX_IPSR_GPSR(IP4_30_28, VI1_R2_B), 1044 1045 /* IPSR5 */ 1046 PINMUX_IPSR_GPSR(IP5_2_0, SSI_WS5), 1047 PINMUX_IPSR_MSEL(IP5_2_0, MSIOF1_SYNC_C, SEL_SOF1_2), 1048 PINMUX_IPSR_MSEL(IP5_2_0, TS_SCK0, SEL_TSIF0_0), 1049 PINMUX_IPSR_MSEL(IP5_2_0, GLO_I1, SEL_GPS_0), 1050 PINMUX_IPSR_MSEL(IP5_2_0, MSIOF2_TXD_D, SEL_SOF2_3), 1051 PINMUX_IPSR_GPSR(IP5_2_0, VI1_R3_B), 1052 PINMUX_IPSR_GPSR(IP5_5_3, SSI_SDATA5), 1053 PINMUX_IPSR_MSEL(IP5_5_3, MSIOF1_TXD_C, SEL_SOF1_2), 1054 PINMUX_IPSR_MSEL(IP5_5_3, TS_SDEN0, SEL_TSIF0_0), 1055 PINMUX_IPSR_MSEL(IP5_5_3, GLO_Q0, SEL_GPS_0), 1056 PINMUX_IPSR_MSEL(IP5_5_3, MSIOF2_SS1_D, SEL_SOF2_3), 1057 PINMUX_IPSR_GPSR(IP5_5_3, VI1_R4_B), 1058 PINMUX_IPSR_GPSR(IP5_8_6, SSI_SCK6), 1059 PINMUX_IPSR_MSEL(IP5_8_6, MSIOF1_RXD_C, SEL_SOF1_2), 1060 PINMUX_IPSR_MSEL(IP5_8_6, TS_SPSYNC0, SEL_TSIF0_0), 1061 PINMUX_IPSR_MSEL(IP5_8_6, GLO_Q1, SEL_GPS_0), 1062 PINMUX_IPSR_MSEL(IP5_8_6, MSIOF2_RXD_D, SEL_SOF2_3), 1063 PINMUX_IPSR_GPSR(IP5_8_6, VI1_R5_B), 1064 PINMUX_IPSR_GPSR(IP5_11_9, SSI_WS6), 1065 PINMUX_IPSR_MSEL(IP5_11_9, GLO_SCLK, SEL_GPS_0), 1066 PINMUX_IPSR_MSEL(IP5_11_9, MSIOF2_SS2_D, SEL_SOF2_3), 1067 PINMUX_IPSR_GPSR(IP5_11_9, VI1_R6_B), 1068 PINMUX_IPSR_GPSR(IP5_14_12, SSI_SDATA6), 1069 PINMUX_IPSR_MSEL(IP5_14_12, STP_IVCXO27_0_B, SEL_SSP_1), 1070 PINMUX_IPSR_MSEL(IP5_14_12, GLO_SDATA, SEL_GPS_0), 1071 PINMUX_IPSR_GPSR(IP5_14_12, VI1_R7_B), 1072 PINMUX_IPSR_MSEL(IP5_16_15, SSI_SCK78, SEL_SSI7_0), 1073 PINMUX_IPSR_MSEL(IP5_16_15, STP_ISCLK_0_B, SEL_SSP_1), 1074 PINMUX_IPSR_MSEL(IP5_16_15, GLO_SS, SEL_GPS_0), 1075 PINMUX_IPSR_MSEL(IP5_19_17, SSI_WS78, SEL_SSI7_0), 1076 PINMUX_IPSR_MSEL(IP5_19_17, TX0_D, SEL_SCIF0_3), 1077 PINMUX_IPSR_MSEL(IP5_19_17, STP_ISD_0_B, SEL_SSP_1), 1078 PINMUX_IPSR_MSEL(IP5_19_17, GLO_RFON, SEL_GPS_0), 1079 PINMUX_IPSR_MSEL(IP5_21_20, SSI_SDATA7, SEL_SSI7_0), 1080 PINMUX_IPSR_MSEL(IP5_21_20, RX0_D, SEL_SCIF0_3), 1081 PINMUX_IPSR_MSEL(IP5_21_20, STP_ISEN_0_B, SEL_SSP_1), 1082 PINMUX_IPSR_MSEL(IP5_23_22, SSI_SDATA8, SEL_SSI8_0), 1083 PINMUX_IPSR_MSEL(IP5_23_22, TX1_D, SEL_SCIF1_3), 1084 PINMUX_IPSR_MSEL(IP5_23_22, STP_ISSYNC_0_B, SEL_SSP_1), 1085 PINMUX_IPSR_MSEL(IP5_25_24, SSI_SCK9, SEL_SSI9_0), 1086 PINMUX_IPSR_MSEL(IP5_25_24, RX1_D, SEL_SCIF1_3), 1087 PINMUX_IPSR_MSEL(IP5_25_24, GLO_SCLK_D, SEL_GPS_3), 1088 PINMUX_IPSR_MSEL(IP5_28_26, SSI_WS9, SEL_SSI9_0), 1089 PINMUX_IPSR_MSEL(IP5_28_26, TX3_D, SEL_SCIF3_3), 1090 PINMUX_IPSR_MSEL(IP5_28_26, CAN0_TX_D, SEL_CAN0_3), 1091 PINMUX_IPSR_MSEL(IP5_28_26, GLO_SDATA_D, SEL_GPS_3), 1092 PINMUX_IPSR_MSEL(IP5_31_29, SSI_SDATA9, SEL_SSI9_0), 1093 PINMUX_IPSR_MSEL(IP5_31_29, RX3_D, SEL_SCIF3_3), 1094 PINMUX_IPSR_MSEL(IP5_31_29, CAN0_RX_D, SEL_CAN0_3), 1095 1096 /* IPSR6 */ 1097 PINMUX_IPSR_MSEL(IP6_2_0, AUDIO_CLKB, SEL_ADG_0), 1098 PINMUX_IPSR_MSEL(IP6_2_0, STP_OPWM_0_B, SEL_SSP_1), 1099 PINMUX_IPSR_MSEL(IP6_2_0, MSIOF1_SCK_B, SEL_SOF1_1), 1100 PINMUX_IPSR_MSEL(IP6_2_0, SCIF_CLK, SEL_SCIF_0), 1101 PINMUX_IPSR_GPSR(IP6_2_0, DVC_MUTE), 1102 PINMUX_IPSR_MSEL(IP6_2_0, BPFCLK_E, SEL_FM_4), 1103 PINMUX_IPSR_GPSR(IP6_5_3, AUDIO_CLKC), 1104 PINMUX_IPSR_MSEL(IP6_5_3, SCIFB0_SCK_C, SEL_SCIFB_2), 1105 PINMUX_IPSR_MSEL(IP6_5_3, MSIOF1_SYNC_B, SEL_SOF1_1), 1106 PINMUX_IPSR_MSEL(IP6_5_3, RX2, SEL_SCIF2_0), 1107 PINMUX_IPSR_MSEL(IP6_5_3, SCIFA2_RXD, SEL_SCIFA2_0), 1108 PINMUX_IPSR_MSEL(IP6_5_3, FMIN_E, SEL_FM_4), 1109 PINMUX_IPSR_GPSR(IP6_7_6, AUDIO_CLKOUT), 1110 PINMUX_IPSR_MSEL(IP6_7_6, MSIOF1_SS1_B, SEL_SOF1_1), 1111 PINMUX_IPSR_MSEL(IP6_7_6, TX2, SEL_SCIF2_0), 1112 PINMUX_IPSR_MSEL(IP6_7_6, SCIFA2_TXD, SEL_SCIFA2_0), 1113 PINMUX_IPSR_GPSR(IP6_9_8, IRQ0), 1114 PINMUX_IPSR_MSEL(IP6_9_8, SCIFB1_RXD_D, SEL_SCIFB1_3), 1115 PINMUX_IPSR_GPSR(IP6_9_8, INTC_IRQ0_N), 1116 PINMUX_IPSR_GPSR(IP6_11_10, IRQ1), 1117 PINMUX_IPSR_MSEL(IP6_11_10, SCIFB1_SCK_C, SEL_SCIFB1_2), 1118 PINMUX_IPSR_GPSR(IP6_11_10, INTC_IRQ1_N), 1119 PINMUX_IPSR_GPSR(IP6_13_12, IRQ2), 1120 PINMUX_IPSR_MSEL(IP6_13_12, SCIFB1_TXD_D, SEL_SCIFB1_3), 1121 PINMUX_IPSR_GPSR(IP6_13_12, INTC_IRQ2_N), 1122 PINMUX_IPSR_GPSR(IP6_15_14, IRQ3), 1123 PINMUX_IPSR_MSEL(IP6_15_14, I2C4_SCL_C, SEL_I2C4_2), 1124 PINMUX_IPSR_MSEL(IP6_15_14, MSIOF2_TXD_E, SEL_SOF2_4), 1125 PINMUX_IPSR_GPSR(IP6_15_14, INTC_IRQ4_N), 1126 PINMUX_IPSR_GPSR(IP6_18_16, IRQ4), 1127 PINMUX_IPSR_MSEL(IP6_18_16, HRX1_C, SEL_HSCIF1_2), 1128 PINMUX_IPSR_MSEL(IP6_18_16, I2C4_SDA_C, SEL_I2C4_2), 1129 PINMUX_IPSR_MSEL(IP6_18_16, MSIOF2_RXD_E, SEL_SOF2_4), 1130 PINMUX_IPSR_GPSR(IP6_18_16, INTC_IRQ4_N), 1131 PINMUX_IPSR_GPSR(IP6_20_19, IRQ5), 1132 PINMUX_IPSR_MSEL(IP6_20_19, HTX1_C, SEL_HSCIF1_2), 1133 PINMUX_IPSR_MSEL(IP6_20_19, I2C1_SCL_E, SEL_I2C1_4), 1134 PINMUX_IPSR_MSEL(IP6_20_19, MSIOF2_SCK_E, SEL_SOF2_4), 1135 PINMUX_IPSR_GPSR(IP6_23_21, IRQ6), 1136 PINMUX_IPSR_MSEL(IP6_23_21, HSCK1_C, SEL_HSCIF1_2), 1137 PINMUX_IPSR_MSEL(IP6_23_21, MSIOF1_SS2_B, SEL_SOF1_1), 1138 PINMUX_IPSR_MSEL(IP6_23_21, I2C1_SDA_E, SEL_I2C1_4), 1139 PINMUX_IPSR_MSEL(IP6_23_21, MSIOF2_SYNC_E, SEL_SOF2_4), 1140 PINMUX_IPSR_GPSR(IP6_26_24, IRQ7), 1141 PINMUX_IPSR_MSEL(IP6_26_24, HCTS1_N_C, SEL_HSCIF1_2), 1142 PINMUX_IPSR_MSEL(IP6_26_24, MSIOF1_TXD_B, SEL_SOF1_1), 1143 PINMUX_IPSR_MSEL(IP6_26_24, GPS_CLK_C, SEL_GPS_2), 1144 PINMUX_IPSR_MSEL(IP6_26_24, GPS_CLK_D, SEL_GPS_3), 1145 PINMUX_IPSR_GPSR(IP6_29_27, IRQ8), 1146 PINMUX_IPSR_MSEL(IP6_29_27, HRTS1_N_C, SEL_HSCIF1_2), 1147 PINMUX_IPSR_MSEL(IP6_29_27, MSIOF1_RXD_B, SEL_SOF1_1), 1148 PINMUX_IPSR_MSEL(IP6_29_27, GPS_SIGN_C, SEL_GPS_2), 1149 PINMUX_IPSR_MSEL(IP6_29_27, GPS_SIGN_D, SEL_GPS_3), 1150 1151 /* IPSR7 */ 1152 PINMUX_IPSR_GPSR(IP7_2_0, IRQ9), 1153 PINMUX_IPSR_MSEL(IP7_2_0, DU1_DOTCLKIN_B, SEL_DIS_1), 1154 PINMUX_IPSR_MSEL(IP7_2_0, CAN_CLK_D, SEL_CANCLK_3), 1155 PINMUX_IPSR_MSEL(IP7_2_0, GPS_MAG_C, SEL_GPS_2), 1156 PINMUX_IPSR_MSEL(IP7_2_0, SCIF_CLK_B, SEL_SCIF_1), 1157 PINMUX_IPSR_MSEL(IP7_2_0, GPS_MAG_D, SEL_GPS_3), 1158 PINMUX_IPSR_GPSR(IP7_5_3, DU1_DR0), 1159 PINMUX_IPSR_GPSR(IP7_5_3, LCDOUT0), 1160 PINMUX_IPSR_MSEL(IP7_5_3, VI1_DATA0_B, SEL_VI1_1), 1161 PINMUX_IPSR_MSEL(IP7_5_3, TX0_B, SEL_SCIF0_1), 1162 PINMUX_IPSR_MSEL(IP7_5_3, SCIFA0_TXD_B, SEL_SCFA_1), 1163 PINMUX_IPSR_MSEL(IP7_5_3, MSIOF2_SCK_B, SEL_SOF2_1), 1164 PINMUX_IPSR_GPSR(IP7_8_6, DU1_DR1), 1165 PINMUX_IPSR_GPSR(IP7_8_6, LCDOUT1), 1166 PINMUX_IPSR_MSEL(IP7_8_6, VI1_DATA1_B, SEL_VI1_1), 1167 PINMUX_IPSR_MSEL(IP7_8_6, RX0_B, SEL_SCIF0_1), 1168 PINMUX_IPSR_MSEL(IP7_8_6, SCIFA0_RXD_B, SEL_SCFA_1), 1169 PINMUX_IPSR_MSEL(IP7_8_6, MSIOF2_SYNC_B, SEL_SOF2_1), 1170 PINMUX_IPSR_GPSR(IP7_10_9, DU1_DR2), 1171 PINMUX_IPSR_GPSR(IP7_10_9, LCDOUT2), 1172 PINMUX_IPSR_MSEL(IP7_10_9, SSI_SCK0129_B, SEL_SSI0_1), 1173 PINMUX_IPSR_GPSR(IP7_12_11, DU1_DR3), 1174 PINMUX_IPSR_GPSR(IP7_12_11, LCDOUT3), 1175 PINMUX_IPSR_MSEL(IP7_12_11, SSI_WS0129_B, SEL_SSI0_1), 1176 PINMUX_IPSR_GPSR(IP7_14_13, DU1_DR4), 1177 PINMUX_IPSR_GPSR(IP7_14_13, LCDOUT4), 1178 PINMUX_IPSR_MSEL(IP7_14_13, SSI_SDATA0_B, SEL_SSI0_1), 1179 PINMUX_IPSR_GPSR(IP7_16_15, DU1_DR5), 1180 PINMUX_IPSR_GPSR(IP7_16_15, LCDOUT5), 1181 PINMUX_IPSR_MSEL(IP7_16_15, SSI_SCK1_B, SEL_SSI1_1), 1182 PINMUX_IPSR_GPSR(IP7_18_17, DU1_DR6), 1183 PINMUX_IPSR_GPSR(IP7_18_17, LCDOUT6), 1184 PINMUX_IPSR_MSEL(IP7_18_17, SSI_WS1_B, SEL_SSI1_1), 1185 PINMUX_IPSR_GPSR(IP7_20_19, DU1_DR7), 1186 PINMUX_IPSR_GPSR(IP7_20_19, LCDOUT7), 1187 PINMUX_IPSR_MSEL(IP7_20_19, SSI_SDATA1_B, SEL_SSI1_1), 1188 PINMUX_IPSR_GPSR(IP7_23_21, DU1_DG0), 1189 PINMUX_IPSR_GPSR(IP7_23_21, LCDOUT8), 1190 PINMUX_IPSR_MSEL(IP7_23_21, VI1_DATA2_B, SEL_VI1_1), 1191 PINMUX_IPSR_MSEL(IP7_23_21, TX1_B, SEL_SCIF1_1), 1192 PINMUX_IPSR_MSEL(IP7_23_21, SCIFA1_TXD_B, SEL_SCIFA1_1), 1193 PINMUX_IPSR_MSEL(IP7_23_21, MSIOF2_SS1_B, SEL_SOF2_1), 1194 PINMUX_IPSR_GPSR(IP7_26_24, DU1_DG1), 1195 PINMUX_IPSR_GPSR(IP7_26_24, LCDOUT9), 1196 PINMUX_IPSR_MSEL(IP7_26_24, VI1_DATA3_B, SEL_VI1_1), 1197 PINMUX_IPSR_MSEL(IP7_26_24, RX1_B, SEL_SCIF1_1), 1198 PINMUX_IPSR_MSEL(IP7_26_24, SCIFA1_RXD_B, SEL_SCIFA1_1), 1199 PINMUX_IPSR_MSEL(IP7_26_24, MSIOF2_SS2_B, SEL_SOF2_1), 1200 PINMUX_IPSR_GPSR(IP7_29_27, DU1_DG2), 1201 PINMUX_IPSR_GPSR(IP7_29_27, LCDOUT10), 1202 PINMUX_IPSR_MSEL(IP7_29_27, VI1_DATA4_B, SEL_VI1_1), 1203 PINMUX_IPSR_GPSR(IP7_29_27, SCIF1_SCK_B), 1204 PINMUX_IPSR_MSEL(IP7_29_27, SCIFA1_SCK, SEL_SCIFA1_0), 1205 PINMUX_IPSR_MSEL(IP7_29_27, SSI_SCK78_B, SEL_SSI7_1), 1206 1207 /* IPSR8 */ 1208 PINMUX_IPSR_GPSR(IP8_2_0, DU1_DG3), 1209 PINMUX_IPSR_GPSR(IP8_2_0, LCDOUT11), 1210 PINMUX_IPSR_MSEL(IP8_2_0, VI1_DATA5_B, SEL_VI1_1), 1211 PINMUX_IPSR_MSEL(IP8_2_0, SSI_WS78_B, SEL_SSI7_1), 1212 PINMUX_IPSR_GPSR(IP8_5_3, DU1_DG4), 1213 PINMUX_IPSR_GPSR(IP8_5_3, LCDOUT12), 1214 PINMUX_IPSR_MSEL(IP8_5_3, VI1_DATA6_B, SEL_VI1_1), 1215 PINMUX_IPSR_MSEL(IP8_5_3, HRX0_B, SEL_HSCIF0_1), 1216 PINMUX_IPSR_MSEL(IP8_5_3, SCIFB2_RXD_B, SEL_SCIFB2_1), 1217 PINMUX_IPSR_MSEL(IP8_5_3, SSI_SDATA7_B, SEL_SSI7_1), 1218 PINMUX_IPSR_GPSR(IP8_8_6, DU1_DG5), 1219 PINMUX_IPSR_GPSR(IP8_8_6, LCDOUT13), 1220 PINMUX_IPSR_MSEL(IP8_8_6, VI1_DATA7_B, SEL_VI1_1), 1221 PINMUX_IPSR_MSEL(IP8_8_6, HCTS0_N_B, SEL_HSCIF0_1), 1222 PINMUX_IPSR_MSEL(IP8_8_6, SCIFB2_TXD_B, SEL_SCIFB2_1), 1223 PINMUX_IPSR_MSEL(IP8_8_6, SSI_SDATA8_B, SEL_SSI8_1), 1224 PINMUX_IPSR_GPSR(IP8_11_9, DU1_DG6), 1225 PINMUX_IPSR_GPSR(IP8_11_9, LCDOUT14), 1226 PINMUX_IPSR_MSEL(IP8_11_9, HRTS0_N_B, SEL_HSCIF0_1), 1227 PINMUX_IPSR_MSEL(IP8_11_9, SCIFB2_CTS_N_B, SEL_SCIFB2_1), 1228 PINMUX_IPSR_MSEL(IP8_11_9, SSI_SCK9_B, SEL_SSI9_1), 1229 PINMUX_IPSR_GPSR(IP8_14_12, DU1_DG7), 1230 PINMUX_IPSR_GPSR(IP8_14_12, LCDOUT15), 1231 PINMUX_IPSR_MSEL(IP8_14_12, HTX0_B, SEL_HSCIF0_1), 1232 PINMUX_IPSR_MSEL(IP8_14_12, SCIFB2_RTS_N_B, SEL_SCIFB2_1), 1233 PINMUX_IPSR_MSEL(IP8_14_12, SSI_WS9_B, SEL_SSI9_1), 1234 PINMUX_IPSR_GPSR(IP8_17_15, DU1_DB0), 1235 PINMUX_IPSR_GPSR(IP8_17_15, LCDOUT16), 1236 PINMUX_IPSR_MSEL(IP8_17_15, VI1_CLK_B, SEL_VI1_1), 1237 PINMUX_IPSR_MSEL(IP8_17_15, TX2_B, SEL_SCIF2_1), 1238 PINMUX_IPSR_MSEL(IP8_17_15, SCIFA2_TXD_B, SEL_SCIFA2_1), 1239 PINMUX_IPSR_MSEL(IP8_17_15, MSIOF2_TXD_B, SEL_SOF2_1), 1240 PINMUX_IPSR_GPSR(IP8_20_18, DU1_DB1), 1241 PINMUX_IPSR_GPSR(IP8_20_18, LCDOUT17), 1242 PINMUX_IPSR_MSEL(IP8_20_18, VI1_HSYNC_N_B, SEL_VI1_1), 1243 PINMUX_IPSR_MSEL(IP8_20_18, RX2_B, SEL_SCIF2_1), 1244 PINMUX_IPSR_MSEL(IP8_20_18, SCIFA2_RXD_B, SEL_SCIFA2_1), 1245 PINMUX_IPSR_MSEL(IP8_20_18, MSIOF2_RXD_B, SEL_SOF2_1), 1246 PINMUX_IPSR_GPSR(IP8_23_21, DU1_DB2), 1247 PINMUX_IPSR_GPSR(IP8_23_21, LCDOUT18), 1248 PINMUX_IPSR_MSEL(IP8_23_21, VI1_VSYNC_N_B, SEL_VI1_1), 1249 PINMUX_IPSR_GPSR(IP8_23_21, SCIF2_SCK_B), 1250 PINMUX_IPSR_MSEL(IP8_23_21, SCIFA2_SCK, SEL_SCIFA2_1), 1251 PINMUX_IPSR_MSEL(IP8_23_21, SSI_SDATA9_B, SEL_SSI9_1), 1252 PINMUX_IPSR_GPSR(IP8_25_24, DU1_DB3), 1253 PINMUX_IPSR_GPSR(IP8_25_24, LCDOUT19), 1254 PINMUX_IPSR_MSEL(IP8_25_24, VI1_CLKENB_B, SEL_VI1_1), 1255 PINMUX_IPSR_GPSR(IP8_27_26, DU1_DB4), 1256 PINMUX_IPSR_GPSR(IP8_27_26, LCDOUT20), 1257 PINMUX_IPSR_MSEL(IP8_27_26, VI1_FIELD_B, SEL_VI1_1), 1258 PINMUX_IPSR_MSEL(IP8_27_26, CAN1_RX, SEL_CAN1_0), 1259 PINMUX_IPSR_GPSR(IP8_30_28, DU1_DB5), 1260 PINMUX_IPSR_GPSR(IP8_30_28, LCDOUT21), 1261 PINMUX_IPSR_MSEL(IP8_30_28, TX3, SEL_SCIF3_0), 1262 PINMUX_IPSR_MSEL(IP8_30_28, SCIFA3_TXD, SEL_SCIFA3_0), 1263 PINMUX_IPSR_MSEL(IP8_30_28, CAN1_TX, SEL_CAN1_0), 1264 1265 /* IPSR9 */ 1266 PINMUX_IPSR_GPSR(IP9_2_0, DU1_DB6), 1267 PINMUX_IPSR_GPSR(IP9_2_0, LCDOUT22), 1268 PINMUX_IPSR_MSEL(IP9_2_0, I2C3_SCL_C, SEL_I2C3_2), 1269 PINMUX_IPSR_MSEL(IP9_2_0, RX3, SEL_SCIF3_0), 1270 PINMUX_IPSR_MSEL(IP9_2_0, SCIFA3_RXD, SEL_SCIFA3_0), 1271 PINMUX_IPSR_GPSR(IP9_5_3, DU1_DB7), 1272 PINMUX_IPSR_GPSR(IP9_5_3, LCDOUT23), 1273 PINMUX_IPSR_MSEL(IP9_5_3, I2C3_SDA_C, SEL_I2C3_2), 1274 PINMUX_IPSR_MSEL(IP9_5_3, SCIF3_SCK, SEL_SCIF3_0), 1275 PINMUX_IPSR_MSEL(IP9_5_3, SCIFA3_SCK, SEL_SCIFA3_0), 1276 PINMUX_IPSR_MSEL(IP9_6, DU1_DOTCLKIN, SEL_DIS_0), 1277 PINMUX_IPSR_GPSR(IP9_6, QSTVA_QVS), 1278 PINMUX_IPSR_GPSR(IP9_7, DU1_DOTCLKOUT0), 1279 PINMUX_IPSR_GPSR(IP9_7, QCLK), 1280 PINMUX_IPSR_GPSR(IP9_10_8, DU1_DOTCLKOUT1), 1281 PINMUX_IPSR_GPSR(IP9_10_8, QSTVB_QVE), 1282 PINMUX_IPSR_MSEL(IP9_10_8, CAN0_TX, SEL_CAN0_0), 1283 PINMUX_IPSR_MSEL(IP9_10_8, TX3_B, SEL_SCIF3_1), 1284 PINMUX_IPSR_MSEL(IP9_10_8, I2C2_SCL_B, SEL_I2C2_1), 1285 PINMUX_IPSR_GPSR(IP9_10_8, PWM4), 1286 PINMUX_IPSR_GPSR(IP9_11, DU1_EXHSYNC_DU1_HSYNC), 1287 PINMUX_IPSR_GPSR(IP9_11, QSTH_QHS), 1288 PINMUX_IPSR_GPSR(IP9_12, DU1_EXVSYNC_DU1_VSYNC), 1289 PINMUX_IPSR_GPSR(IP9_12, QSTB_QHE), 1290 PINMUX_IPSR_GPSR(IP9_15_13, DU1_EXODDF_DU1_ODDF_DISP_CDE), 1291 PINMUX_IPSR_GPSR(IP9_15_13, QCPV_QDE), 1292 PINMUX_IPSR_MSEL(IP9_15_13, CAN0_RX, SEL_CAN0_0), 1293 PINMUX_IPSR_MSEL(IP9_15_13, RX3_B, SEL_SCIF3_1), 1294 PINMUX_IPSR_MSEL(IP9_15_13, I2C2_SDA_B, SEL_I2C2_1), 1295 PINMUX_IPSR_GPSR(IP9_16, DU1_DISP), 1296 PINMUX_IPSR_GPSR(IP9_16, QPOLA), 1297 PINMUX_IPSR_GPSR(IP9_18_17, DU1_CDE), 1298 PINMUX_IPSR_GPSR(IP9_18_17, QPOLB), 1299 PINMUX_IPSR_GPSR(IP9_18_17, PWM4_B), 1300 PINMUX_IPSR_GPSR(IP9_20_19, VI0_CLKENB), 1301 PINMUX_IPSR_MSEL(IP9_20_19, TX4, SEL_SCIF4_0), 1302 PINMUX_IPSR_MSEL(IP9_20_19, SCIFA4_TXD, SEL_SCIFA4_0), 1303 PINMUX_IPSR_MSEL(IP9_20_19, TS_SDATA0_D, SEL_TSIF0_3), 1304 PINMUX_IPSR_GPSR(IP9_22_21, VI0_FIELD), 1305 PINMUX_IPSR_MSEL(IP9_22_21, RX4, SEL_SCIF4_0), 1306 PINMUX_IPSR_MSEL(IP9_22_21, SCIFA4_RXD, SEL_SCIFA4_0), 1307 PINMUX_IPSR_MSEL(IP9_22_21, TS_SCK0_D, SEL_TSIF0_3), 1308 PINMUX_IPSR_GPSR(IP9_24_23, VI0_HSYNC_N), 1309 PINMUX_IPSR_MSEL(IP9_24_23, TX5, SEL_SCIF5_0), 1310 PINMUX_IPSR_MSEL(IP9_24_23, SCIFA5_TXD, SEL_SCIFA5_0), 1311 PINMUX_IPSR_MSEL(IP9_24_23, TS_SDEN0_D, SEL_TSIF0_3), 1312 PINMUX_IPSR_GPSR(IP9_26_25, VI0_VSYNC_N), 1313 PINMUX_IPSR_MSEL(IP9_26_25, RX5, SEL_SCIF5_0), 1314 PINMUX_IPSR_MSEL(IP9_26_25, SCIFA5_RXD, SEL_SCIFA5_0), 1315 PINMUX_IPSR_MSEL(IP9_26_25, TS_SPSYNC0_D, SEL_TSIF0_3), 1316 PINMUX_IPSR_GPSR(IP9_28_27, VI0_DATA3_VI0_B3), 1317 PINMUX_IPSR_MSEL(IP9_28_27, SCIF3_SCK_B, SEL_SCIF3_1), 1318 PINMUX_IPSR_MSEL(IP9_28_27, SCIFA3_SCK_B, SEL_SCIFA3_1), 1319 PINMUX_IPSR_GPSR(IP9_31_29, VI0_G0), 1320 PINMUX_IPSR_MSEL(IP9_31_29, IIC1_SCL, SEL_IIC1_0), 1321 PINMUX_IPSR_MSEL(IP9_31_29, STP_IVCXO27_0_C, SEL_SSP_2), 1322 PINMUX_IPSR_MSEL(IP9_31_29, I2C4_SCL, SEL_I2C4_0), 1323 PINMUX_IPSR_MSEL(IP9_31_29, HCTS2_N, SEL_HSCIF2_0), 1324 PINMUX_IPSR_MSEL(IP9_31_29, SCIFB2_CTS_N, SEL_SCIFB2_0), 1325 PINMUX_IPSR_GPSR(IP9_31_29, ATAWR1_N), 1326 1327 /* IPSR10 */ 1328 PINMUX_IPSR_GPSR(IP10_2_0, VI0_G1), 1329 PINMUX_IPSR_MSEL(IP10_2_0, IIC1_SDA, SEL_IIC1_0), 1330 PINMUX_IPSR_MSEL(IP10_2_0, STP_ISCLK_0_C, SEL_SSP_2), 1331 PINMUX_IPSR_MSEL(IP10_2_0, I2C4_SDA, SEL_I2C4_0), 1332 PINMUX_IPSR_MSEL(IP10_2_0, HRTS2_N, SEL_HSCIF2_0), 1333 PINMUX_IPSR_MSEL(IP10_2_0, SCIFB2_RTS_N, SEL_SCIFB2_0), 1334 PINMUX_IPSR_GPSR(IP10_2_0, ATADIR1_N), 1335 PINMUX_IPSR_GPSR(IP10_5_3, VI0_G2), 1336 PINMUX_IPSR_GPSR(IP10_5_3, VI2_HSYNC_N), 1337 PINMUX_IPSR_MSEL(IP10_5_3, STP_ISD_0_C, SEL_SSP_2), 1338 PINMUX_IPSR_MSEL(IP10_5_3, I2C3_SCL_B, SEL_I2C3_1), 1339 PINMUX_IPSR_MSEL(IP10_5_3, HSCK2, SEL_HSCIF2_0), 1340 PINMUX_IPSR_MSEL(IP10_5_3, SCIFB2_SCK, SEL_SCIFB2_0), 1341 PINMUX_IPSR_GPSR(IP10_5_3, ATARD1_N), 1342 PINMUX_IPSR_GPSR(IP10_8_6, VI0_G3), 1343 PINMUX_IPSR_GPSR(IP10_8_6, VI2_VSYNC_N), 1344 PINMUX_IPSR_MSEL(IP10_8_6, STP_ISEN_0_C, SEL_SSP_2), 1345 PINMUX_IPSR_MSEL(IP10_8_6, I2C3_SDA_B, SEL_I2C3_1), 1346 PINMUX_IPSR_MSEL(IP10_8_6, HRX2, SEL_HSCIF2_0), 1347 PINMUX_IPSR_MSEL(IP10_8_6, SCIFB2_RXD, SEL_SCIFB2_0), 1348 PINMUX_IPSR_GPSR(IP10_8_6, ATACS01_N), 1349 PINMUX_IPSR_GPSR(IP10_11_9, VI0_G4), 1350 PINMUX_IPSR_GPSR(IP10_11_9, VI2_CLKENB), 1351 PINMUX_IPSR_MSEL(IP10_11_9, STP_ISSYNC_0_C, SEL_SSP_2), 1352 PINMUX_IPSR_MSEL(IP10_11_9, HTX2, SEL_HSCIF2_0), 1353 PINMUX_IPSR_MSEL(IP10_11_9, SCIFB2_TXD, SEL_SCIFB2_0), 1354 PINMUX_IPSR_MSEL(IP10_11_9, SCIFB0_SCK_D, SEL_SCIFB_3), 1355 PINMUX_IPSR_GPSR(IP10_14_12, VI0_G5), 1356 PINMUX_IPSR_GPSR(IP10_14_12, VI2_FIELD), 1357 PINMUX_IPSR_MSEL(IP10_14_12, STP_OPWM_0_C, SEL_SSP_2), 1358 PINMUX_IPSR_MSEL(IP10_14_12, FMCLK_D, SEL_FM_3), 1359 PINMUX_IPSR_MSEL(IP10_14_12, CAN0_TX_E, SEL_CAN0_4), 1360 PINMUX_IPSR_MSEL(IP10_14_12, HTX1_D, SEL_HSCIF1_3), 1361 PINMUX_IPSR_MSEL(IP10_14_12, SCIFB0_TXD_D, SEL_SCIFB_3), 1362 PINMUX_IPSR_GPSR(IP10_16_15, VI0_G6), 1363 PINMUX_IPSR_GPSR(IP10_16_15, VI2_CLK), 1364 PINMUX_IPSR_MSEL(IP10_16_15, BPFCLK_D, SEL_FM_3), 1365 PINMUX_IPSR_GPSR(IP10_18_17, VI0_G7), 1366 PINMUX_IPSR_GPSR(IP10_18_17, VI2_DATA0), 1367 PINMUX_IPSR_MSEL(IP10_18_17, FMIN_D, SEL_FM_3), 1368 PINMUX_IPSR_GPSR(IP10_21_19, VI0_R0), 1369 PINMUX_IPSR_GPSR(IP10_21_19, VI2_DATA1), 1370 PINMUX_IPSR_MSEL(IP10_21_19, GLO_I0_B, SEL_GPS_1), 1371 PINMUX_IPSR_MSEL(IP10_21_19, TS_SDATA0_C, SEL_TSIF0_2), 1372 PINMUX_IPSR_GPSR(IP10_21_19, ATACS11_N), 1373 PINMUX_IPSR_GPSR(IP10_24_22, VI0_R1), 1374 PINMUX_IPSR_GPSR(IP10_24_22, VI2_DATA2), 1375 PINMUX_IPSR_MSEL(IP10_24_22, GLO_I1_B, SEL_GPS_1), 1376 PINMUX_IPSR_MSEL(IP10_24_22, TS_SCK0_C, SEL_TSIF0_2), 1377 PINMUX_IPSR_GPSR(IP10_24_22, ATAG1_N), 1378 PINMUX_IPSR_GPSR(IP10_26_25, VI0_R2), 1379 PINMUX_IPSR_GPSR(IP10_26_25, VI2_DATA3), 1380 PINMUX_IPSR_MSEL(IP10_26_25, GLO_Q0_B, SEL_GPS_1), 1381 PINMUX_IPSR_MSEL(IP10_26_25, TS_SDEN0_C, SEL_TSIF0_2), 1382 PINMUX_IPSR_GPSR(IP10_28_27, VI0_R3), 1383 PINMUX_IPSR_GPSR(IP10_28_27, VI2_DATA4), 1384 PINMUX_IPSR_MSEL(IP10_28_27, GLO_Q1_B, SEL_GPS_1), 1385 PINMUX_IPSR_MSEL(IP10_28_27, TS_SPSYNC0_C, SEL_TSIF0_2), 1386 PINMUX_IPSR_GPSR(IP10_31_29, VI0_R4), 1387 PINMUX_IPSR_GPSR(IP10_31_29, VI2_DATA5), 1388 PINMUX_IPSR_MSEL(IP10_31_29, GLO_SCLK_B, SEL_GPS_1), 1389 PINMUX_IPSR_MSEL(IP10_31_29, TX0_C, SEL_SCIF0_2), 1390 PINMUX_IPSR_MSEL(IP10_31_29, I2C1_SCL_D, SEL_I2C1_3), 1391 1392 /* IPSR11 */ 1393 PINMUX_IPSR_GPSR(IP11_2_0, VI0_R5), 1394 PINMUX_IPSR_GPSR(IP11_2_0, VI2_DATA6), 1395 PINMUX_IPSR_MSEL(IP11_2_0, GLO_SDATA_B, SEL_GPS_1), 1396 PINMUX_IPSR_MSEL(IP11_2_0, RX0_C, SEL_SCIF0_2), 1397 PINMUX_IPSR_MSEL(IP11_2_0, I2C1_SDA_D, SEL_I2C1_3), 1398 PINMUX_IPSR_GPSR(IP11_5_3, VI0_R6), 1399 PINMUX_IPSR_GPSR(IP11_5_3, VI2_DATA7), 1400 PINMUX_IPSR_MSEL(IP11_5_3, GLO_SS_B, SEL_GPS_1), 1401 PINMUX_IPSR_MSEL(IP11_5_3, TX1_C, SEL_SCIF1_2), 1402 PINMUX_IPSR_MSEL(IP11_5_3, I2C4_SCL_B, SEL_I2C4_1), 1403 PINMUX_IPSR_GPSR(IP11_8_6, VI0_R7), 1404 PINMUX_IPSR_MSEL(IP11_8_6, GLO_RFON_B, SEL_GPS_1), 1405 PINMUX_IPSR_MSEL(IP11_8_6, RX1_C, SEL_SCIF1_2), 1406 PINMUX_IPSR_MSEL(IP11_8_6, CAN0_RX_E, SEL_CAN0_4), 1407 PINMUX_IPSR_MSEL(IP11_8_6, I2C4_SDA_B, SEL_I2C4_1), 1408 PINMUX_IPSR_MSEL(IP11_8_6, HRX1_D, SEL_HSCIF1_3), 1409 PINMUX_IPSR_MSEL(IP11_8_6, SCIFB0_RXD_D, SEL_SCIFB_3), 1410 PINMUX_IPSR_MSEL(IP11_11_9, VI1_HSYNC_N, SEL_VI1_0), 1411 PINMUX_IPSR_GPSR(IP11_11_9, AVB_RXD0), 1412 PINMUX_IPSR_MSEL(IP11_11_9, TS_SDATA0_B, SEL_TSIF0_1), 1413 PINMUX_IPSR_MSEL(IP11_11_9, TX4_B, SEL_SCIF4_1), 1414 PINMUX_IPSR_MSEL(IP11_11_9, SCIFA4_TXD_B, SEL_SCIFA4_1), 1415 PINMUX_IPSR_MSEL(IP11_14_12, VI1_VSYNC_N, SEL_VI1_0), 1416 PINMUX_IPSR_GPSR(IP11_14_12, AVB_RXD1), 1417 PINMUX_IPSR_MSEL(IP11_14_12, TS_SCK0_B, SEL_TSIF0_1), 1418 PINMUX_IPSR_MSEL(IP11_14_12, RX4_B, SEL_SCIF4_1), 1419 PINMUX_IPSR_MSEL(IP11_14_12, SCIFA4_RXD_B, SEL_SCIFA4_1), 1420 PINMUX_IPSR_MSEL(IP11_16_15, VI1_CLKENB, SEL_VI1_0), 1421 PINMUX_IPSR_GPSR(IP11_16_15, AVB_RXD2), 1422 PINMUX_IPSR_MSEL(IP11_16_15, TS_SDEN0_B, SEL_TSIF0_1), 1423 PINMUX_IPSR_MSEL(IP11_18_17, VI1_FIELD, SEL_VI1_0), 1424 PINMUX_IPSR_GPSR(IP11_18_17, AVB_RXD3), 1425 PINMUX_IPSR_MSEL(IP11_18_17, TS_SPSYNC0_B, SEL_TSIF0_1), 1426 PINMUX_IPSR_MSEL(IP11_19, VI1_CLK, SEL_VI1_0), 1427 PINMUX_IPSR_GPSR(IP11_19, AVB_RXD4), 1428 PINMUX_IPSR_MSEL(IP11_20, VI1_DATA0, SEL_VI1_0), 1429 PINMUX_IPSR_GPSR(IP11_20, AVB_RXD5), 1430 PINMUX_IPSR_MSEL(IP11_21, VI1_DATA1, SEL_VI1_0), 1431 PINMUX_IPSR_GPSR(IP11_21, AVB_RXD6), 1432 PINMUX_IPSR_MSEL(IP11_22, VI1_DATA2, SEL_VI1_0), 1433 PINMUX_IPSR_GPSR(IP11_22, AVB_RXD7), 1434 PINMUX_IPSR_MSEL(IP11_23, VI1_DATA3, SEL_VI1_0), 1435 PINMUX_IPSR_GPSR(IP11_23, AVB_RX_ER), 1436 PINMUX_IPSR_MSEL(IP11_24, VI1_DATA4, SEL_VI1_0), 1437 PINMUX_IPSR_GPSR(IP11_24, AVB_MDIO), 1438 PINMUX_IPSR_MSEL(IP11_25, VI1_DATA5, SEL_VI1_0), 1439 PINMUX_IPSR_GPSR(IP11_25, AVB_RX_DV), 1440 PINMUX_IPSR_MSEL(IP11_26, VI1_DATA6, SEL_VI1_0), 1441 PINMUX_IPSR_GPSR(IP11_26, AVB_MAGIC), 1442 PINMUX_IPSR_MSEL(IP11_27, VI1_DATA7, SEL_VI1_0), 1443 PINMUX_IPSR_GPSR(IP11_27, AVB_MDC), 1444 PINMUX_IPSR_GPSR(IP11_29_28, ETH_MDIO), 1445 PINMUX_IPSR_GPSR(IP11_29_28, AVB_RX_CLK), 1446 PINMUX_IPSR_MSEL(IP11_29_28, I2C2_SCL_C, SEL_I2C2_2), 1447 PINMUX_IPSR_GPSR(IP11_31_30, ETH_CRS_DV), 1448 PINMUX_IPSR_GPSR(IP11_31_30, AVB_LINK), 1449 PINMUX_IPSR_MSEL(IP11_31_30, I2C2_SDA_C, SEL_I2C2_2), 1450 1451 /* IPSR12 */ 1452 PINMUX_IPSR_GPSR(IP12_1_0, ETH_RX_ER), 1453 PINMUX_IPSR_GPSR(IP12_1_0, AVB_CRS), 1454 PINMUX_IPSR_MSEL(IP12_1_0, I2C3_SCL, SEL_I2C3_0), 1455 PINMUX_IPSR_MSEL(IP12_1_0, IIC0_SCL, SEL_IIC0_0), 1456 PINMUX_IPSR_GPSR(IP12_3_2, ETH_RXD0), 1457 PINMUX_IPSR_GPSR(IP12_3_2, AVB_PHY_INT), 1458 PINMUX_IPSR_MSEL(IP12_3_2, I2C3_SDA, SEL_I2C3_0), 1459 PINMUX_IPSR_MSEL(IP12_3_2, IIC0_SDA, SEL_IIC0_0), 1460 PINMUX_IPSR_GPSR(IP12_6_4, ETH_RXD1), 1461 PINMUX_IPSR_GPSR(IP12_6_4, AVB_GTXREFCLK), 1462 PINMUX_IPSR_MSEL(IP12_6_4, CAN0_TX_C, SEL_CAN0_2), 1463 PINMUX_IPSR_MSEL(IP12_6_4, I2C2_SCL_D, SEL_I2C2_3), 1464 PINMUX_IPSR_MSEL(IP12_6_4, MSIOF1_RXD_E, SEL_SOF1_4), 1465 PINMUX_IPSR_GPSR(IP12_9_7, ETH_LINK), 1466 PINMUX_IPSR_GPSR(IP12_9_7, AVB_TXD0), 1467 PINMUX_IPSR_MSEL(IP12_9_7, CAN0_RX_C, SEL_CAN0_2), 1468 PINMUX_IPSR_MSEL(IP12_9_7, I2C2_SDA_D, SEL_I2C2_3), 1469 PINMUX_IPSR_MSEL(IP12_9_7, MSIOF1_SCK_E, SEL_SOF1_4), 1470 PINMUX_IPSR_GPSR(IP12_12_10, ETH_REFCLK), 1471 PINMUX_IPSR_GPSR(IP12_12_10, AVB_TXD1), 1472 PINMUX_IPSR_MSEL(IP12_12_10, SCIFA3_RXD_B, SEL_SCIFA3_1), 1473 PINMUX_IPSR_MSEL(IP12_12_10, CAN1_RX_C, SEL_CAN1_2), 1474 PINMUX_IPSR_MSEL(IP12_12_10, MSIOF1_SYNC_E, SEL_SOF1_4), 1475 PINMUX_IPSR_GPSR(IP12_15_13, ETH_TXD1), 1476 PINMUX_IPSR_GPSR(IP12_15_13, AVB_TXD2), 1477 PINMUX_IPSR_MSEL(IP12_15_13, SCIFA3_TXD_B, SEL_SCIFA3_1), 1478 PINMUX_IPSR_MSEL(IP12_15_13, CAN1_TX_C, SEL_CAN1_2), 1479 PINMUX_IPSR_MSEL(IP12_15_13, MSIOF1_TXD_E, SEL_SOF1_4), 1480 PINMUX_IPSR_GPSR(IP12_17_16, ETH_TX_EN), 1481 PINMUX_IPSR_GPSR(IP12_17_16, AVB_TXD3), 1482 PINMUX_IPSR_MSEL(IP12_17_16, TCLK1_B, SEL_TMU1_0), 1483 PINMUX_IPSR_MSEL(IP12_17_16, CAN_CLK_B, SEL_CANCLK_1), 1484 PINMUX_IPSR_GPSR(IP12_19_18, ETH_MAGIC), 1485 PINMUX_IPSR_GPSR(IP12_19_18, AVB_TXD4), 1486 PINMUX_IPSR_MSEL(IP12_19_18, IETX_C, SEL_IEB_2), 1487 PINMUX_IPSR_GPSR(IP12_21_20, ETH_TXD0), 1488 PINMUX_IPSR_GPSR(IP12_21_20, AVB_TXD5), 1489 PINMUX_IPSR_MSEL(IP12_21_20, IECLK_C, SEL_IEB_2), 1490 PINMUX_IPSR_GPSR(IP12_23_22, ETH_MDC), 1491 PINMUX_IPSR_GPSR(IP12_23_22, AVB_TXD6), 1492 PINMUX_IPSR_MSEL(IP12_23_22, IERX_C, SEL_IEB_2), 1493 PINMUX_IPSR_MSEL(IP12_26_24, STP_IVCXO27_0, SEL_SSP_0), 1494 PINMUX_IPSR_GPSR(IP12_26_24, AVB_TXD7), 1495 PINMUX_IPSR_MSEL(IP12_26_24, SCIFB2_TXD_D, SEL_SCIFB2_3), 1496 PINMUX_IPSR_MSEL(IP12_26_24, ADIDATA_B, SEL_RAD_1), 1497 PINMUX_IPSR_MSEL(IP12_26_24, MSIOF0_SYNC_C, SEL_SOF0_2), 1498 PINMUX_IPSR_MSEL(IP12_29_27, STP_ISCLK_0, SEL_SSP_0), 1499 PINMUX_IPSR_GPSR(IP12_29_27, AVB_TX_EN), 1500 PINMUX_IPSR_MSEL(IP12_29_27, SCIFB2_RXD_D, SEL_SCIFB2_3), 1501 PINMUX_IPSR_MSEL(IP12_29_27, ADICS_SAMP_B, SEL_RAD_1), 1502 PINMUX_IPSR_MSEL(IP12_29_27, MSIOF0_SCK_C, SEL_SOF0_2), 1503 1504 /* IPSR13 */ 1505 PINMUX_IPSR_MSEL(IP13_2_0, STP_ISD_0, SEL_SSP_0), 1506 PINMUX_IPSR_GPSR(IP13_2_0, AVB_TX_ER), 1507 PINMUX_IPSR_MSEL(IP13_2_0, SCIFB2_SCK_C, SEL_SCIFB2_2), 1508 PINMUX_IPSR_MSEL(IP13_2_0, ADICLK_B, SEL_RAD_1), 1509 PINMUX_IPSR_MSEL(IP13_2_0, MSIOF0_SS1_C, SEL_SOF0_2), 1510 PINMUX_IPSR_MSEL(IP13_4_3, STP_ISEN_0, SEL_SSP_0), 1511 PINMUX_IPSR_GPSR(IP13_4_3, AVB_TX_CLK), 1512 PINMUX_IPSR_MSEL(IP13_4_3, ADICHS0_B, SEL_RAD_1), 1513 PINMUX_IPSR_MSEL(IP13_4_3, MSIOF0_SS2_C, SEL_SOF0_2), 1514 PINMUX_IPSR_MSEL(IP13_6_5, STP_ISSYNC_0, SEL_SSP_0), 1515 PINMUX_IPSR_GPSR(IP13_6_5, AVB_COL), 1516 PINMUX_IPSR_MSEL(IP13_6_5, ADICHS1_B, SEL_RAD_1), 1517 PINMUX_IPSR_MSEL(IP13_6_5, MSIOF0_RXD_C, SEL_SOF0_2), 1518 PINMUX_IPSR_MSEL(IP13_9_7, STP_OPWM_0, SEL_SSP_0), 1519 PINMUX_IPSR_GPSR(IP13_9_7, AVB_GTX_CLK), 1520 PINMUX_IPSR_GPSR(IP13_9_7, PWM0_B), 1521 PINMUX_IPSR_MSEL(IP13_9_7, ADICHS2_B, SEL_RAD_1), 1522 PINMUX_IPSR_MSEL(IP13_9_7, MSIOF0_TXD_C, SEL_SOF0_2), 1523 PINMUX_IPSR_GPSR(IP13_10, SD0_CLK), 1524 PINMUX_IPSR_MSEL(IP13_10, SPCLK_B, SEL_QSP_1), 1525 PINMUX_IPSR_GPSR(IP13_11, SD0_CMD), 1526 PINMUX_IPSR_MSEL(IP13_11, MOSI_IO0_B, SEL_QSP_1), 1527 PINMUX_IPSR_GPSR(IP13_12, SD0_DATA0), 1528 PINMUX_IPSR_MSEL(IP13_12, MISO_IO1_B, SEL_QSP_1), 1529 PINMUX_IPSR_GPSR(IP13_13, SD0_DATA1), 1530 PINMUX_IPSR_MSEL(IP13_13, IO2_B, SEL_QSP_1), 1531 PINMUX_IPSR_GPSR(IP13_14, SD0_DATA2), 1532 PINMUX_IPSR_MSEL(IP13_14, IO3_B, SEL_QSP_1), 1533 PINMUX_IPSR_GPSR(IP13_15, SD0_DATA3), 1534 PINMUX_IPSR_MSEL(IP13_15, SSL_B, SEL_QSP_1), 1535 PINMUX_IPSR_GPSR(IP13_18_16, SD0_CD), 1536 PINMUX_IPSR_MSEL(IP13_18_16, MMC_D6_B, SEL_MMC_1), 1537 PINMUX_IPSR_MSEL(IP13_18_16, SIM0_RST_B, SEL_SIM_1), 1538 PINMUX_IPSR_MSEL(IP13_18_16, CAN0_RX_F, SEL_CAN0_5), 1539 PINMUX_IPSR_MSEL(IP13_18_16, SCIFA5_TXD_B, SEL_SCIFA5_1), 1540 PINMUX_IPSR_MSEL(IP13_18_16, TX3_C, SEL_SCIF3_2), 1541 PINMUX_IPSR_GPSR(IP13_21_19, SD0_WP), 1542 PINMUX_IPSR_MSEL(IP13_21_19, MMC_D7_B, SEL_MMC_1), 1543 PINMUX_IPSR_MSEL(IP13_21_19, SIM0_D_B, SEL_SIM_1), 1544 PINMUX_IPSR_MSEL(IP13_21_19, CAN0_TX_F, SEL_CAN0_5), 1545 PINMUX_IPSR_MSEL(IP13_21_19, SCIFA5_RXD_B, SEL_SCIFA5_1), 1546 PINMUX_IPSR_MSEL(IP13_21_19, RX3_C, SEL_SCIF3_2), 1547 PINMUX_IPSR_GPSR(IP13_22, SD1_CMD), 1548 PINMUX_IPSR_MSEL(IP13_22, REMOCON_B, SEL_RCN_1), 1549 PINMUX_IPSR_GPSR(IP13_24_23, SD1_DATA0), 1550 PINMUX_IPSR_MSEL(IP13_24_23, SPEEDIN_B, SEL_RSP_1), 1551 PINMUX_IPSR_GPSR(IP13_25, SD1_DATA1), 1552 PINMUX_IPSR_MSEL(IP13_25, IETX_B, SEL_IEB_1), 1553 PINMUX_IPSR_GPSR(IP13_26, SD1_DATA2), 1554 PINMUX_IPSR_MSEL(IP13_26, IECLK_B, SEL_IEB_1), 1555 PINMUX_IPSR_GPSR(IP13_27, SD1_DATA3), 1556 PINMUX_IPSR_MSEL(IP13_27, IERX_B, SEL_IEB_1), 1557 PINMUX_IPSR_GPSR(IP13_30_28, SD1_CD), 1558 PINMUX_IPSR_GPSR(IP13_30_28, PWM0), 1559 PINMUX_IPSR_GPSR(IP13_30_28, TPU_TO0), 1560 PINMUX_IPSR_MSEL(IP13_30_28, I2C1_SCL_C, SEL_I2C1_2), 1561 1562 /* IPSR14 */ 1563 PINMUX_IPSR_GPSR(IP14_1_0, SD1_WP), 1564 PINMUX_IPSR_GPSR(IP14_1_0, PWM1_B), 1565 PINMUX_IPSR_MSEL(IP14_1_0, I2C1_SDA_C, SEL_I2C1_2), 1566 PINMUX_IPSR_GPSR(IP14_2, SD2_CLK), 1567 PINMUX_IPSR_GPSR(IP14_2, MMC_CLK), 1568 PINMUX_IPSR_GPSR(IP14_3, SD2_CMD), 1569 PINMUX_IPSR_GPSR(IP14_3, MMC_CMD), 1570 PINMUX_IPSR_GPSR(IP14_4, SD2_DATA0), 1571 PINMUX_IPSR_GPSR(IP14_4, MMC_D0), 1572 PINMUX_IPSR_GPSR(IP14_5, SD2_DATA1), 1573 PINMUX_IPSR_GPSR(IP14_5, MMC_D1), 1574 PINMUX_IPSR_GPSR(IP14_6, SD2_DATA2), 1575 PINMUX_IPSR_GPSR(IP14_6, MMC_D2), 1576 PINMUX_IPSR_GPSR(IP14_7, SD2_DATA3), 1577 PINMUX_IPSR_GPSR(IP14_7, MMC_D3), 1578 PINMUX_IPSR_GPSR(IP14_10_8, SD2_CD), 1579 PINMUX_IPSR_GPSR(IP14_10_8, MMC_D4), 1580 PINMUX_IPSR_MSEL(IP14_10_8, IIC1_SCL_C, SEL_IIC1_2), 1581 PINMUX_IPSR_MSEL(IP14_10_8, TX5_B, SEL_SCIF5_1), 1582 PINMUX_IPSR_MSEL(IP14_10_8, SCIFA5_TXD_C, SEL_SCIFA5_2), 1583 PINMUX_IPSR_GPSR(IP14_13_11, SD2_WP), 1584 PINMUX_IPSR_GPSR(IP14_13_11, MMC_D5), 1585 PINMUX_IPSR_MSEL(IP14_13_11, IIC1_SDA_C, SEL_IIC1_2), 1586 PINMUX_IPSR_MSEL(IP14_13_11, RX5_B, SEL_SCIF5_1), 1587 PINMUX_IPSR_MSEL(IP14_13_11, SCIFA5_RXD_C, SEL_SCIFA5_2), 1588 PINMUX_IPSR_MSEL(IP14_16_14, MSIOF0_SCK, SEL_SOF0_0), 1589 PINMUX_IPSR_MSEL(IP14_16_14, RX2_C, SEL_SCIF2_2), 1590 PINMUX_IPSR_MSEL(IP14_16_14, ADIDATA, SEL_RAD_0), 1591 PINMUX_IPSR_MSEL(IP14_16_14, VI1_CLK_C, SEL_VI1_2), 1592 PINMUX_IPSR_GPSR(IP14_16_14, VI1_G0_B), 1593 PINMUX_IPSR_MSEL(IP14_19_17, MSIOF0_SYNC, SEL_SOF0_0), 1594 PINMUX_IPSR_MSEL(IP14_19_17, TX2_C, SEL_SCIF2_2), 1595 PINMUX_IPSR_MSEL(IP14_19_17, ADICS_SAMP, SEL_RAD_0), 1596 PINMUX_IPSR_MSEL(IP14_19_17, VI1_CLKENB_C, SEL_VI1_2), 1597 PINMUX_IPSR_GPSR(IP14_19_17, VI1_G1_B), 1598 PINMUX_IPSR_MSEL(IP14_22_20, MSIOF0_TXD, SEL_SOF0_0), 1599 PINMUX_IPSR_MSEL(IP14_22_20, ADICLK, SEL_RAD_0), 1600 PINMUX_IPSR_MSEL(IP14_22_20, VI1_FIELD_C, SEL_VI1_2), 1601 PINMUX_IPSR_GPSR(IP14_22_20, VI1_G2_B), 1602 PINMUX_IPSR_MSEL(IP14_25_23, MSIOF0_RXD, SEL_SOF0_0), 1603 PINMUX_IPSR_MSEL(IP14_25_23, ADICHS0, SEL_RAD_0), 1604 PINMUX_IPSR_MSEL(IP14_25_23, VI1_DATA0_C, SEL_VI1_2), 1605 PINMUX_IPSR_GPSR(IP14_25_23, VI1_G3_B), 1606 PINMUX_IPSR_MSEL(IP14_28_26, MSIOF0_SS1, SEL_SOF0_0), 1607 PINMUX_IPSR_MSEL(IP14_28_26, MMC_D6, SEL_MMC_0), 1608 PINMUX_IPSR_MSEL(IP14_28_26, ADICHS1, SEL_RAD_0), 1609 PINMUX_IPSR_MSEL(IP14_28_26, TX0_E, SEL_SCIF0_4), 1610 PINMUX_IPSR_MSEL(IP14_28_26, VI1_HSYNC_N_C, SEL_VI1_2), 1611 PINMUX_IPSR_MSEL(IP14_28_26, IIC0_SCL_C, SEL_IIC0_2), 1612 PINMUX_IPSR_GPSR(IP14_28_26, VI1_G4_B), 1613 PINMUX_IPSR_MSEL(IP14_31_29, MSIOF0_SS2, SEL_SOF0_0), 1614 PINMUX_IPSR_MSEL(IP14_31_29, MMC_D7, SEL_MMC_0), 1615 PINMUX_IPSR_MSEL(IP14_31_29, ADICHS2, SEL_RAD_0), 1616 PINMUX_IPSR_MSEL(IP14_31_29, RX0_E, SEL_SCIF0_4), 1617 PINMUX_IPSR_MSEL(IP14_31_29, VI1_VSYNC_N_C, SEL_VI1_2), 1618 PINMUX_IPSR_MSEL(IP14_31_29, IIC0_SDA_C, SEL_IIC0_2), 1619 PINMUX_IPSR_GPSR(IP14_31_29, VI1_G5_B), 1620 1621 /* IPSR15 */ 1622 PINMUX_IPSR_MSEL(IP15_1_0, SIM0_RST, SEL_SIM_0), 1623 PINMUX_IPSR_MSEL(IP15_1_0, IETX, SEL_IEB_0), 1624 PINMUX_IPSR_MSEL(IP15_1_0, CAN1_TX_D, SEL_CAN1_3), 1625 PINMUX_IPSR_GPSR(IP15_3_2, SIM0_CLK), 1626 PINMUX_IPSR_MSEL(IP15_3_2, IECLK, SEL_IEB_0), 1627 PINMUX_IPSR_MSEL(IP15_3_2, CAN_CLK_C, SEL_CANCLK_2), 1628 PINMUX_IPSR_MSEL(IP15_5_4, SIM0_D, SEL_SIM_0), 1629 PINMUX_IPSR_MSEL(IP15_5_4, IERX, SEL_IEB_0), 1630 PINMUX_IPSR_MSEL(IP15_5_4, CAN1_RX_D, SEL_CAN1_3), 1631 PINMUX_IPSR_MSEL(IP15_8_6, GPS_CLK, SEL_GPS_0), 1632 PINMUX_IPSR_MSEL(IP15_8_6, DU1_DOTCLKIN_C, SEL_DIS_2), 1633 PINMUX_IPSR_MSEL(IP15_8_6, AUDIO_CLKB_B, SEL_ADG_1), 1634 PINMUX_IPSR_GPSR(IP15_8_6, PWM5_B), 1635 PINMUX_IPSR_MSEL(IP15_8_6, SCIFA3_TXD_C, SEL_SCIFA3_2), 1636 PINMUX_IPSR_MSEL(IP15_11_9, GPS_SIGN, SEL_GPS_0), 1637 PINMUX_IPSR_MSEL(IP15_11_9, TX4_C, SEL_SCIF4_2), 1638 PINMUX_IPSR_MSEL(IP15_11_9, SCIFA4_TXD_C, SEL_SCIFA4_2), 1639 PINMUX_IPSR_GPSR(IP15_11_9, PWM5), 1640 PINMUX_IPSR_GPSR(IP15_11_9, VI1_G6_B), 1641 PINMUX_IPSR_MSEL(IP15_11_9, SCIFA3_RXD_C, SEL_SCIFA3_2), 1642 PINMUX_IPSR_MSEL(IP15_14_12, GPS_MAG, SEL_GPS_0), 1643 PINMUX_IPSR_MSEL(IP15_14_12, RX4_C, SEL_SCIF4_2), 1644 PINMUX_IPSR_MSEL(IP15_14_12, SCIFA4_RXD_C, SEL_SCIFA4_2), 1645 PINMUX_IPSR_GPSR(IP15_14_12, PWM6), 1646 PINMUX_IPSR_GPSR(IP15_14_12, VI1_G7_B), 1647 PINMUX_IPSR_MSEL(IP15_14_12, SCIFA3_SCK_C, SEL_SCIFA3_2), 1648 PINMUX_IPSR_MSEL(IP15_17_15, HCTS0_N, SEL_HSCIF0_0), 1649 PINMUX_IPSR_MSEL(IP15_17_15, SCIFB0_CTS_N, SEL_SCIFB_0), 1650 PINMUX_IPSR_MSEL(IP15_17_15, GLO_I0_C, SEL_GPS_2), 1651 PINMUX_IPSR_MSEL(IP15_17_15, TCLK1, SEL_TMU1_0), 1652 PINMUX_IPSR_MSEL(IP15_17_15, VI1_DATA1_C, SEL_VI1_2), 1653 PINMUX_IPSR_MSEL(IP15_20_18, HRTS0_N, SEL_HSCIF0_0), 1654 PINMUX_IPSR_MSEL(IP15_20_18, SCIFB0_RTS_N, SEL_SCIFB_0), 1655 PINMUX_IPSR_MSEL(IP15_20_18, GLO_I1_C, SEL_GPS_2), 1656 PINMUX_IPSR_MSEL(IP15_20_18, VI1_DATA2_C, SEL_VI1_2), 1657 PINMUX_IPSR_MSEL(IP15_23_21, HSCK0, SEL_HSCIF0_0), 1658 PINMUX_IPSR_MSEL(IP15_23_21, SCIFB0_SCK, SEL_SCIFB_0), 1659 PINMUX_IPSR_MSEL(IP15_23_21, GLO_Q0_C, SEL_GPS_2), 1660 PINMUX_IPSR_MSEL(IP15_23_21, CAN_CLK, SEL_CANCLK_0), 1661 PINMUX_IPSR_GPSR(IP15_23_21, TCLK2), 1662 PINMUX_IPSR_MSEL(IP15_23_21, VI1_DATA3_C, SEL_VI1_2), 1663 PINMUX_IPSR_MSEL(IP15_26_24, HRX0, SEL_HSCIF0_0), 1664 PINMUX_IPSR_MSEL(IP15_26_24, SCIFB0_RXD, SEL_SCIFB_0), 1665 PINMUX_IPSR_MSEL(IP15_26_24, GLO_Q1_C, SEL_GPS_2), 1666 PINMUX_IPSR_MSEL(IP15_26_24, CAN0_RX_B, SEL_CAN0_1), 1667 PINMUX_IPSR_MSEL(IP15_26_24, VI1_DATA4_C, SEL_VI1_2), 1668 PINMUX_IPSR_MSEL(IP15_29_27, HTX0, SEL_HSCIF0_0), 1669 PINMUX_IPSR_MSEL(IP15_29_27, SCIFB0_TXD, SEL_SCIFB_0), 1670 PINMUX_IPSR_MSEL(IP15_29_27, GLO_SCLK_C, SEL_GPS_2), 1671 PINMUX_IPSR_MSEL(IP15_29_27, CAN0_TX_B, SEL_CAN0_1), 1672 PINMUX_IPSR_MSEL(IP15_29_27, VI1_DATA5_C, SEL_VI1_2), 1673 1674 /* IPSR16 */ 1675 PINMUX_IPSR_MSEL(IP16_2_0, HRX1, SEL_HSCIF1_0), 1676 PINMUX_IPSR_MSEL(IP16_2_0, SCIFB1_RXD, SEL_SCIFB1_0), 1677 PINMUX_IPSR_GPSR(IP16_2_0, VI1_R0_B), 1678 PINMUX_IPSR_MSEL(IP16_2_0, GLO_SDATA_C, SEL_GPS_2), 1679 PINMUX_IPSR_MSEL(IP16_2_0, VI1_DATA6_C, SEL_VI1_2), 1680 PINMUX_IPSR_MSEL(IP16_5_3, HTX1, SEL_HSCIF1_0), 1681 PINMUX_IPSR_MSEL(IP16_5_3, SCIFB1_TXD, SEL_SCIFB1_0), 1682 PINMUX_IPSR_GPSR(IP16_5_3, VI1_R1_B), 1683 PINMUX_IPSR_MSEL(IP16_5_3, GLO_SS_C, SEL_GPS_2), 1684 PINMUX_IPSR_MSEL(IP16_5_3, VI1_DATA7_C, SEL_VI1_2), 1685 PINMUX_IPSR_MSEL(IP16_7_6, HSCK1, SEL_HSCIF1_0), 1686 PINMUX_IPSR_MSEL(IP16_7_6, SCIFB1_SCK, SEL_SCIFB1_0), 1687 PINMUX_IPSR_GPSR(IP16_7_6, MLB_CLK), 1688 PINMUX_IPSR_MSEL(IP16_7_6, GLO_RFON_C, SEL_GPS_2), 1689 PINMUX_IPSR_MSEL(IP16_9_8, HCTS1_N, SEL_HSCIF1_0), 1690 PINMUX_IPSR_GPSR(IP16_9_8, SCIFB1_CTS_N), 1691 PINMUX_IPSR_GPSR(IP16_9_8, MLB_SIG), 1692 PINMUX_IPSR_MSEL(IP16_9_8, CAN1_TX_B, SEL_CAN1_1), 1693 PINMUX_IPSR_MSEL(IP16_11_10, HRTS1_N, SEL_HSCIF1_0), 1694 PINMUX_IPSR_GPSR(IP16_11_10, SCIFB1_RTS_N), 1695 PINMUX_IPSR_GPSR(IP16_11_10, MLB_DAT), 1696 PINMUX_IPSR_MSEL(IP16_11_10, CAN1_RX_B, SEL_CAN1_1), 1697 }; 1698 1699 static const struct sh_pfc_pin pinmux_pins[] = { 1700 PINMUX_GPIO_GP_ALL(), 1701 }; 1702 1703 #if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793) 1704 /* - ADI -------------------------------------------------------------------- */ 1705 static const unsigned int adi_common_pins[] = { 1706 /* ADIDATA, ADICS/SAMP, ADICLK */ 1707 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26), 1708 }; 1709 static const unsigned int adi_common_mux[] = { 1710 /* ADIDATA, ADICS/SAMP, ADICLK */ 1711 ADIDATA_MARK, ADICS_SAMP_MARK, ADICLK_MARK, 1712 }; 1713 static const unsigned int adi_chsel0_pins[] = { 1714 /* ADICHS 0 */ 1715 RCAR_GP_PIN(6, 27), 1716 }; 1717 static const unsigned int adi_chsel0_mux[] = { 1718 /* ADICHS 0 */ 1719 ADICHS0_MARK, 1720 }; 1721 static const unsigned int adi_chsel1_pins[] = { 1722 /* ADICHS 1 */ 1723 RCAR_GP_PIN(6, 28), 1724 }; 1725 static const unsigned int adi_chsel1_mux[] = { 1726 /* ADICHS 1 */ 1727 ADICHS1_MARK, 1728 }; 1729 static const unsigned int adi_chsel2_pins[] = { 1730 /* ADICHS 2 */ 1731 RCAR_GP_PIN(6, 29), 1732 }; 1733 static const unsigned int adi_chsel2_mux[] = { 1734 /* ADICHS 2 */ 1735 ADICHS2_MARK, 1736 }; 1737 static const unsigned int adi_common_b_pins[] = { 1738 /* ADIDATA B, ADICS/SAMP B, ADICLK B */ 1739 RCAR_GP_PIN(5, 25), RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 27), 1740 }; 1741 static const unsigned int adi_common_b_mux[] = { 1742 /* ADIDATA B, ADICS/SAMP B, ADICLK B */ 1743 ADIDATA_B_MARK, ADICS_SAMP_B_MARK, ADICLK_B_MARK, 1744 }; 1745 static const unsigned int adi_chsel0_b_pins[] = { 1746 /* ADICHS B 0 */ 1747 RCAR_GP_PIN(5, 28), 1748 }; 1749 static const unsigned int adi_chsel0_b_mux[] = { 1750 /* ADICHS B 0 */ 1751 ADICHS0_B_MARK, 1752 }; 1753 static const unsigned int adi_chsel1_b_pins[] = { 1754 /* ADICHS B 1 */ 1755 RCAR_GP_PIN(5, 29), 1756 }; 1757 static const unsigned int adi_chsel1_b_mux[] = { 1758 /* ADICHS B 1 */ 1759 ADICHS1_B_MARK, 1760 }; 1761 static const unsigned int adi_chsel2_b_pins[] = { 1762 /* ADICHS B 2 */ 1763 RCAR_GP_PIN(5, 30), 1764 }; 1765 static const unsigned int adi_chsel2_b_mux[] = { 1766 /* ADICHS B 2 */ 1767 ADICHS2_B_MARK, 1768 }; 1769 #endif /* CONFIG_PINCTRL_PFC_R8A7791 || CONFIG_PINCTRL_PFC_R8A7793 */ 1770 1771 /* - Audio Clock ------------------------------------------------------------ */ 1772 static const unsigned int audio_clk_a_pins[] = { 1773 /* CLK */ 1774 RCAR_GP_PIN(2, 28), 1775 }; 1776 1777 static const unsigned int audio_clk_a_mux[] = { 1778 AUDIO_CLKA_MARK, 1779 }; 1780 1781 static const unsigned int audio_clk_b_pins[] = { 1782 /* CLK */ 1783 RCAR_GP_PIN(2, 29), 1784 }; 1785 1786 static const unsigned int audio_clk_b_mux[] = { 1787 AUDIO_CLKB_MARK, 1788 }; 1789 1790 static const unsigned int audio_clk_b_b_pins[] = { 1791 /* CLK */ 1792 RCAR_GP_PIN(7, 20), 1793 }; 1794 1795 static const unsigned int audio_clk_b_b_mux[] = { 1796 AUDIO_CLKB_B_MARK, 1797 }; 1798 1799 static const unsigned int audio_clk_c_pins[] = { 1800 /* CLK */ 1801 RCAR_GP_PIN(2, 30), 1802 }; 1803 1804 static const unsigned int audio_clk_c_mux[] = { 1805 AUDIO_CLKC_MARK, 1806 }; 1807 1808 static const unsigned int audio_clkout_pins[] = { 1809 /* CLK */ 1810 RCAR_GP_PIN(2, 31), 1811 }; 1812 1813 static const unsigned int audio_clkout_mux[] = { 1814 AUDIO_CLKOUT_MARK, 1815 }; 1816 1817 /* - AVB -------------------------------------------------------------------- */ 1818 static const unsigned int avb_link_pins[] = { 1819 RCAR_GP_PIN(5, 14), 1820 }; 1821 static const unsigned int avb_link_mux[] = { 1822 AVB_LINK_MARK, 1823 }; 1824 static const unsigned int avb_magic_pins[] = { 1825 RCAR_GP_PIN(5, 11), 1826 }; 1827 static const unsigned int avb_magic_mux[] = { 1828 AVB_MAGIC_MARK, 1829 }; 1830 static const unsigned int avb_phy_int_pins[] = { 1831 RCAR_GP_PIN(5, 16), 1832 }; 1833 static const unsigned int avb_phy_int_mux[] = { 1834 AVB_PHY_INT_MARK, 1835 }; 1836 static const unsigned int avb_mdio_pins[] = { 1837 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 9), 1838 }; 1839 static const unsigned int avb_mdio_mux[] = { 1840 AVB_MDC_MARK, AVB_MDIO_MARK, 1841 }; 1842 static const unsigned int avb_mii_pins[] = { 1843 RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 20), 1844 RCAR_GP_PIN(5, 21), 1845 1846 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), 1847 RCAR_GP_PIN(5, 3), 1848 1849 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 10), 1850 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 27), 1851 RCAR_GP_PIN(5, 28), RCAR_GP_PIN(5, 29), 1852 }; 1853 static const unsigned int avb_mii_mux[] = { 1854 AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK, 1855 AVB_TXD3_MARK, 1856 1857 AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK, 1858 AVB_RXD3_MARK, 1859 1860 AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK, 1861 AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_ER_MARK, 1862 AVB_TX_CLK_MARK, AVB_COL_MARK, 1863 }; 1864 static const unsigned int avb_gmii_pins[] = { 1865 RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 20), 1866 RCAR_GP_PIN(5, 21), RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23), 1867 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25), 1868 1869 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), 1870 RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5), 1871 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7), 1872 1873 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 10), 1874 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 30), RCAR_GP_PIN(5, 17), 1875 RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 27), RCAR_GP_PIN(5, 28), 1876 RCAR_GP_PIN(5, 29), 1877 }; 1878 static const unsigned int avb_gmii_mux[] = { 1879 AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK, 1880 AVB_TXD3_MARK, AVB_TXD4_MARK, AVB_TXD5_MARK, 1881 AVB_TXD6_MARK, AVB_TXD7_MARK, 1882 1883 AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK, 1884 AVB_RXD3_MARK, AVB_RXD4_MARK, AVB_RXD5_MARK, 1885 AVB_RXD6_MARK, AVB_RXD7_MARK, 1886 1887 AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK, 1888 AVB_CRS_MARK, AVB_GTX_CLK_MARK, AVB_GTXREFCLK_MARK, 1889 AVB_TX_EN_MARK, AVB_TX_ER_MARK, AVB_TX_CLK_MARK, 1890 AVB_COL_MARK, 1891 }; 1892 1893 /* - CAN -------------------------------------------------------------------- */ 1894 1895 static const unsigned int can0_data_pins[] = { 1896 /* TX, RX */ 1897 RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 29), 1898 }; 1899 1900 static const unsigned int can0_data_mux[] = { 1901 CAN0_TX_MARK, CAN0_RX_MARK, 1902 }; 1903 1904 static const unsigned int can0_data_b_pins[] = { 1905 /* TX, RX */ 1906 RCAR_GP_PIN(7, 4), RCAR_GP_PIN(7, 3), 1907 }; 1908 1909 static const unsigned int can0_data_b_mux[] = { 1910 CAN0_TX_B_MARK, CAN0_RX_B_MARK, 1911 }; 1912 1913 static const unsigned int can0_data_c_pins[] = { 1914 /* TX, RX */ 1915 RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18), 1916 }; 1917 1918 static const unsigned int can0_data_c_mux[] = { 1919 CAN0_TX_C_MARK, CAN0_RX_C_MARK, 1920 }; 1921 1922 static const unsigned int can0_data_d_pins[] = { 1923 /* TX, RX */ 1924 RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 27), 1925 }; 1926 1927 static const unsigned int can0_data_d_mux[] = { 1928 CAN0_TX_D_MARK, CAN0_RX_D_MARK, 1929 }; 1930 1931 static const unsigned int can0_data_e_pins[] = { 1932 /* TX, RX */ 1933 RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 28), 1934 }; 1935 1936 static const unsigned int can0_data_e_mux[] = { 1937 CAN0_TX_E_MARK, CAN0_RX_E_MARK, 1938 }; 1939 1940 static const unsigned int can0_data_f_pins[] = { 1941 /* TX, RX */ 1942 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6), 1943 }; 1944 1945 static const unsigned int can0_data_f_mux[] = { 1946 CAN0_TX_F_MARK, CAN0_RX_F_MARK, 1947 }; 1948 1949 static const unsigned int can1_data_pins[] = { 1950 /* TX, RX */ 1951 RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 20), 1952 }; 1953 1954 static const unsigned int can1_data_mux[] = { 1955 CAN1_TX_MARK, CAN1_RX_MARK, 1956 }; 1957 1958 static const unsigned int can1_data_b_pins[] = { 1959 /* TX, RX */ 1960 RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9), 1961 }; 1962 1963 static const unsigned int can1_data_b_mux[] = { 1964 CAN1_TX_B_MARK, CAN1_RX_B_MARK, 1965 }; 1966 1967 static const unsigned int can1_data_c_pins[] = { 1968 /* TX, RX */ 1969 RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 19), 1970 }; 1971 1972 static const unsigned int can1_data_c_mux[] = { 1973 CAN1_TX_C_MARK, CAN1_RX_C_MARK, 1974 }; 1975 1976 static const unsigned int can1_data_d_pins[] = { 1977 /* TX, RX */ 1978 RCAR_GP_PIN(4, 29), RCAR_GP_PIN(4, 31), 1979 }; 1980 1981 static const unsigned int can1_data_d_mux[] = { 1982 CAN1_TX_D_MARK, CAN1_RX_D_MARK, 1983 }; 1984 1985 static const unsigned int can_clk_pins[] = { 1986 /* CLK */ 1987 RCAR_GP_PIN(7, 2), 1988 }; 1989 1990 static const unsigned int can_clk_mux[] = { 1991 CAN_CLK_MARK, 1992 }; 1993 1994 static const unsigned int can_clk_b_pins[] = { 1995 /* CLK */ 1996 RCAR_GP_PIN(5, 21), 1997 }; 1998 1999 static const unsigned int can_clk_b_mux[] = { 2000 CAN_CLK_B_MARK, 2001 }; 2002 2003 static const unsigned int can_clk_c_pins[] = { 2004 /* CLK */ 2005 RCAR_GP_PIN(4, 30), 2006 }; 2007 2008 static const unsigned int can_clk_c_mux[] = { 2009 CAN_CLK_C_MARK, 2010 }; 2011 2012 static const unsigned int can_clk_d_pins[] = { 2013 /* CLK */ 2014 RCAR_GP_PIN(7, 19), 2015 }; 2016 2017 static const unsigned int can_clk_d_mux[] = { 2018 CAN_CLK_D_MARK, 2019 }; 2020 2021 /* - DU --------------------------------------------------------------------- */ 2022 static const unsigned int du_rgb666_pins[] = { 2023 /* R[7:2], G[7:2], B[7:2] */ 2024 RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 5), 2025 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 2), 2026 RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13), 2027 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 10), 2028 RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21), 2029 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 18), 2030 }; 2031 static const unsigned int du_rgb666_mux[] = { 2032 DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK, 2033 DU1_DR3_MARK, DU1_DR2_MARK, 2034 DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK, 2035 DU1_DG3_MARK, DU1_DG2_MARK, 2036 DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK, 2037 DU1_DB3_MARK, DU1_DB2_MARK, 2038 }; 2039 static const unsigned int du_rgb888_pins[] = { 2040 /* R[7:0], G[7:0], B[7:0] */ 2041 RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 5), 2042 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 2), 2043 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0), 2044 RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13), 2045 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 10), 2046 RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8), 2047 RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21), 2048 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 18), 2049 RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16), 2050 }; 2051 static const unsigned int du_rgb888_mux[] = { 2052 DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK, 2053 DU1_DR3_MARK, DU1_DR2_MARK, DU1_DR1_MARK, DU1_DR0_MARK, 2054 DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK, 2055 DU1_DG3_MARK, DU1_DG2_MARK, DU1_DG1_MARK, DU1_DG0_MARK, 2056 DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK, 2057 DU1_DB3_MARK, DU1_DB2_MARK, DU1_DB1_MARK, DU1_DB0_MARK, 2058 }; 2059 static const unsigned int du_clk_out_0_pins[] = { 2060 /* CLKOUT */ 2061 RCAR_GP_PIN(3, 25), 2062 }; 2063 static const unsigned int du_clk_out_0_mux[] = { 2064 DU1_DOTCLKOUT0_MARK 2065 }; 2066 static const unsigned int du_clk_out_1_pins[] = { 2067 /* CLKOUT */ 2068 RCAR_GP_PIN(3, 26), 2069 }; 2070 static const unsigned int du_clk_out_1_mux[] = { 2071 DU1_DOTCLKOUT1_MARK 2072 }; 2073 static const unsigned int du_sync_pins[] = { 2074 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */ 2075 RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 27), 2076 }; 2077 static const unsigned int du_sync_mux[] = { 2078 DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK 2079 }; 2080 static const unsigned int du_oddf_pins[] = { 2081 /* EXDISP/EXODDF/EXCDE */ 2082 RCAR_GP_PIN(3, 29), 2083 }; 2084 static const unsigned int du_oddf_mux[] = { 2085 DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK, 2086 }; 2087 static const unsigned int du_cde_pins[] = { 2088 /* CDE */ 2089 RCAR_GP_PIN(3, 31), 2090 }; 2091 static const unsigned int du_cde_mux[] = { 2092 DU1_CDE_MARK, 2093 }; 2094 static const unsigned int du_disp_pins[] = { 2095 /* DISP */ 2096 RCAR_GP_PIN(3, 30), 2097 }; 2098 static const unsigned int du_disp_mux[] = { 2099 DU1_DISP_MARK, 2100 }; 2101 static const unsigned int du0_clk_in_pins[] = { 2102 /* CLKIN */ 2103 RCAR_GP_PIN(6, 31), 2104 }; 2105 static const unsigned int du0_clk_in_mux[] = { 2106 DU0_DOTCLKIN_MARK 2107 }; 2108 static const unsigned int du1_clk_in_pins[] = { 2109 /* CLKIN */ 2110 RCAR_GP_PIN(3, 24), 2111 }; 2112 static const unsigned int du1_clk_in_mux[] = { 2113 DU1_DOTCLKIN_MARK 2114 }; 2115 static const unsigned int du1_clk_in_b_pins[] = { 2116 /* CLKIN */ 2117 RCAR_GP_PIN(7, 19), 2118 }; 2119 static const unsigned int du1_clk_in_b_mux[] = { 2120 DU1_DOTCLKIN_B_MARK, 2121 }; 2122 static const unsigned int du1_clk_in_c_pins[] = { 2123 /* CLKIN */ 2124 RCAR_GP_PIN(7, 20), 2125 }; 2126 static const unsigned int du1_clk_in_c_mux[] = { 2127 DU1_DOTCLKIN_C_MARK, 2128 }; 2129 /* - ETH -------------------------------------------------------------------- */ 2130 static const unsigned int eth_link_pins[] = { 2131 /* LINK */ 2132 RCAR_GP_PIN(5, 18), 2133 }; 2134 static const unsigned int eth_link_mux[] = { 2135 ETH_LINK_MARK, 2136 }; 2137 static const unsigned int eth_magic_pins[] = { 2138 /* MAGIC */ 2139 RCAR_GP_PIN(5, 22), 2140 }; 2141 static const unsigned int eth_magic_mux[] = { 2142 ETH_MAGIC_MARK, 2143 }; 2144 static const unsigned int eth_mdio_pins[] = { 2145 /* MDC, MDIO */ 2146 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 13), 2147 }; 2148 static const unsigned int eth_mdio_mux[] = { 2149 ETH_MDC_MARK, ETH_MDIO_MARK, 2150 }; 2151 static const unsigned int eth_rmii_pins[] = { 2152 /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */ 2153 RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 15), 2154 RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 23), RCAR_GP_PIN(5, 20), 2155 RCAR_GP_PIN(5, 21), RCAR_GP_PIN(5, 19), 2156 }; 2157 static const unsigned int eth_rmii_mux[] = { 2158 ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK, 2159 ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REFCLK_MARK, 2160 }; 2161 2162 /* - HSCIF0 ----------------------------------------------------------------- */ 2163 static const unsigned int hscif0_data_pins[] = { 2164 /* RX, TX */ 2165 RCAR_GP_PIN(7, 3), RCAR_GP_PIN(7, 4), 2166 }; 2167 static const unsigned int hscif0_data_mux[] = { 2168 HRX0_MARK, HTX0_MARK, 2169 }; 2170 static const unsigned int hscif0_clk_pins[] = { 2171 /* SCK */ 2172 RCAR_GP_PIN(7, 2), 2173 }; 2174 static const unsigned int hscif0_clk_mux[] = { 2175 HSCK0_MARK, 2176 }; 2177 static const unsigned int hscif0_ctrl_pins[] = { 2178 /* RTS, CTS */ 2179 RCAR_GP_PIN(7, 1), RCAR_GP_PIN(7, 0), 2180 }; 2181 static const unsigned int hscif0_ctrl_mux[] = { 2182 HRTS0_N_MARK, HCTS0_N_MARK, 2183 }; 2184 static const unsigned int hscif0_data_b_pins[] = { 2185 /* RX, TX */ 2186 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 15), 2187 }; 2188 static const unsigned int hscif0_data_b_mux[] = { 2189 HRX0_B_MARK, HTX0_B_MARK, 2190 }; 2191 static const unsigned int hscif0_ctrl_b_pins[] = { 2192 /* RTS, CTS */ 2193 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13), 2194 }; 2195 static const unsigned int hscif0_ctrl_b_mux[] = { 2196 HRTS0_N_B_MARK, HCTS0_N_B_MARK, 2197 }; 2198 static const unsigned int hscif0_data_c_pins[] = { 2199 /* RX, TX */ 2200 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), 2201 }; 2202 static const unsigned int hscif0_data_c_mux[] = { 2203 HRX0_C_MARK, HTX0_C_MARK, 2204 }; 2205 static const unsigned int hscif0_clk_c_pins[] = { 2206 /* SCK */ 2207 RCAR_GP_PIN(5, 31), 2208 }; 2209 static const unsigned int hscif0_clk_c_mux[] = { 2210 HSCK0_C_MARK, 2211 }; 2212 /* - HSCIF1 ----------------------------------------------------------------- */ 2213 static const unsigned int hscif1_data_pins[] = { 2214 /* RX, TX */ 2215 RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6), 2216 }; 2217 static const unsigned int hscif1_data_mux[] = { 2218 HRX1_MARK, HTX1_MARK, 2219 }; 2220 static const unsigned int hscif1_clk_pins[] = { 2221 /* SCK */ 2222 RCAR_GP_PIN(7, 7), 2223 }; 2224 static const unsigned int hscif1_clk_mux[] = { 2225 HSCK1_MARK, 2226 }; 2227 static const unsigned int hscif1_ctrl_pins[] = { 2228 /* RTS, CTS */ 2229 RCAR_GP_PIN(7, 9), RCAR_GP_PIN(7, 8), 2230 }; 2231 static const unsigned int hscif1_ctrl_mux[] = { 2232 HRTS1_N_MARK, HCTS1_N_MARK, 2233 }; 2234 static const unsigned int hscif1_data_b_pins[] = { 2235 /* RX, TX */ 2236 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18), 2237 }; 2238 static const unsigned int hscif1_data_b_mux[] = { 2239 HRX1_B_MARK, HTX1_B_MARK, 2240 }; 2241 static const unsigned int hscif1_data_c_pins[] = { 2242 /* RX, TX */ 2243 RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 15), 2244 }; 2245 static const unsigned int hscif1_data_c_mux[] = { 2246 HRX1_C_MARK, HTX1_C_MARK, 2247 }; 2248 static const unsigned int hscif1_clk_c_pins[] = { 2249 /* SCK */ 2250 RCAR_GP_PIN(7, 16), 2251 }; 2252 static const unsigned int hscif1_clk_c_mux[] = { 2253 HSCK1_C_MARK, 2254 }; 2255 static const unsigned int hscif1_ctrl_c_pins[] = { 2256 /* RTS, CTS */ 2257 RCAR_GP_PIN(7, 18), RCAR_GP_PIN(7, 17), 2258 }; 2259 static const unsigned int hscif1_ctrl_c_mux[] = { 2260 HRTS1_N_C_MARK, HCTS1_N_C_MARK, 2261 }; 2262 static const unsigned int hscif1_data_d_pins[] = { 2263 /* RX, TX */ 2264 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 18), 2265 }; 2266 static const unsigned int hscif1_data_d_mux[] = { 2267 HRX1_D_MARK, HTX1_D_MARK, 2268 }; 2269 static const unsigned int hscif1_data_e_pins[] = { 2270 /* RX, TX */ 2271 RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 15), 2272 }; 2273 static const unsigned int hscif1_data_e_mux[] = { 2274 HRX1_C_MARK, HTX1_C_MARK, 2275 }; 2276 static const unsigned int hscif1_clk_e_pins[] = { 2277 /* SCK */ 2278 RCAR_GP_PIN(2, 6), 2279 }; 2280 static const unsigned int hscif1_clk_e_mux[] = { 2281 HSCK1_E_MARK, 2282 }; 2283 static const unsigned int hscif1_ctrl_e_pins[] = { 2284 /* RTS, CTS */ 2285 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 7), 2286 }; 2287 static const unsigned int hscif1_ctrl_e_mux[] = { 2288 HRTS1_N_E_MARK, HCTS1_N_E_MARK, 2289 }; 2290 /* - HSCIF2 ----------------------------------------------------------------- */ 2291 static const unsigned int hscif2_data_pins[] = { 2292 /* RX, TX */ 2293 RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17), 2294 }; 2295 static const unsigned int hscif2_data_mux[] = { 2296 HRX2_MARK, HTX2_MARK, 2297 }; 2298 static const unsigned int hscif2_clk_pins[] = { 2299 /* SCK */ 2300 RCAR_GP_PIN(4, 15), 2301 }; 2302 static const unsigned int hscif2_clk_mux[] = { 2303 HSCK2_MARK, 2304 }; 2305 static const unsigned int hscif2_ctrl_pins[] = { 2306 /* RTS, CTS */ 2307 RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13), 2308 }; 2309 static const unsigned int hscif2_ctrl_mux[] = { 2310 HRTS2_N_MARK, HCTS2_N_MARK, 2311 }; 2312 static const unsigned int hscif2_data_b_pins[] = { 2313 /* RX, TX */ 2314 RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 22), 2315 }; 2316 static const unsigned int hscif2_data_b_mux[] = { 2317 HRX2_B_MARK, HTX2_B_MARK, 2318 }; 2319 static const unsigned int hscif2_ctrl_b_pins[] = { 2320 /* RTS, CTS */ 2321 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 21), 2322 }; 2323 static const unsigned int hscif2_ctrl_b_mux[] = { 2324 HRTS2_N_B_MARK, HCTS2_N_B_MARK, 2325 }; 2326 static const unsigned int hscif2_data_c_pins[] = { 2327 /* RX, TX */ 2328 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), 2329 }; 2330 static const unsigned int hscif2_data_c_mux[] = { 2331 HRX2_C_MARK, HTX2_C_MARK, 2332 }; 2333 static const unsigned int hscif2_clk_c_pins[] = { 2334 /* SCK */ 2335 RCAR_GP_PIN(5, 31), 2336 }; 2337 static const unsigned int hscif2_clk_c_mux[] = { 2338 HSCK2_C_MARK, 2339 }; 2340 static const unsigned int hscif2_data_d_pins[] = { 2341 /* RX, TX */ 2342 RCAR_GP_PIN(1, 20), RCAR_GP_PIN(5, 31), 2343 }; 2344 static const unsigned int hscif2_data_d_mux[] = { 2345 HRX2_B_MARK, HTX2_D_MARK, 2346 }; 2347 /* - I2C0 ------------------------------------------------------------------- */ 2348 static const unsigned int i2c0_pins[] = { 2349 /* SCL, SDA */ 2350 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25), 2351 }; 2352 static const unsigned int i2c0_mux[] = { 2353 I2C0_SCL_MARK, I2C0_SDA_MARK, 2354 }; 2355 static const unsigned int i2c0_b_pins[] = { 2356 /* SCL, SDA */ 2357 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), 2358 }; 2359 static const unsigned int i2c0_b_mux[] = { 2360 I2C0_SCL_B_MARK, I2C0_SDA_B_MARK, 2361 }; 2362 static const unsigned int i2c0_c_pins[] = { 2363 /* SCL, SDA */ 2364 RCAR_GP_PIN(0, 16), RCAR_GP_PIN(1, 1), 2365 }; 2366 static const unsigned int i2c0_c_mux[] = { 2367 I2C0_SCL_C_MARK, I2C0_SDA_C_MARK, 2368 }; 2369 /* - I2C1 ------------------------------------------------------------------- */ 2370 static const unsigned int i2c1_pins[] = { 2371 /* SCL, SDA */ 2372 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 11), 2373 }; 2374 static const unsigned int i2c1_mux[] = { 2375 I2C1_SCL_MARK, I2C1_SDA_MARK, 2376 }; 2377 static const unsigned int i2c1_b_pins[] = { 2378 /* SCL, SDA */ 2379 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), 2380 }; 2381 static const unsigned int i2c1_b_mux[] = { 2382 I2C1_SCL_B_MARK, I2C1_SDA_B_MARK, 2383 }; 2384 static const unsigned int i2c1_c_pins[] = { 2385 /* SCL, SDA */ 2386 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15), 2387 }; 2388 static const unsigned int i2c1_c_mux[] = { 2389 I2C1_SCL_C_MARK, I2C1_SDA_C_MARK, 2390 }; 2391 static const unsigned int i2c1_d_pins[] = { 2392 /* SCL, SDA */ 2393 RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26), 2394 }; 2395 static const unsigned int i2c1_d_mux[] = { 2396 I2C1_SCL_D_MARK, I2C1_SDA_D_MARK, 2397 }; 2398 static const unsigned int i2c1_e_pins[] = { 2399 /* SCL, SDA */ 2400 RCAR_GP_PIN(7, 15), RCAR_GP_PIN(7, 16), 2401 }; 2402 static const unsigned int i2c1_e_mux[] = { 2403 I2C1_SCL_E_MARK, I2C1_SDA_E_MARK, 2404 }; 2405 /* - I2C2 ------------------------------------------------------------------- */ 2406 static const unsigned int i2c2_pins[] = { 2407 /* SCL, SDA */ 2408 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), 2409 }; 2410 static const unsigned int i2c2_mux[] = { 2411 I2C2_SCL_MARK, I2C2_SDA_MARK, 2412 }; 2413 static const unsigned int i2c2_b_pins[] = { 2414 /* SCL, SDA */ 2415 RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 29), 2416 }; 2417 static const unsigned int i2c2_b_mux[] = { 2418 I2C2_SCL_B_MARK, I2C2_SDA_B_MARK, 2419 }; 2420 static const unsigned int i2c2_c_pins[] = { 2421 /* SCL, SDA */ 2422 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14), 2423 }; 2424 static const unsigned int i2c2_c_mux[] = { 2425 I2C2_SCL_C_MARK, I2C2_SDA_C_MARK, 2426 }; 2427 static const unsigned int i2c2_d_pins[] = { 2428 /* SCL, SDA */ 2429 RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18), 2430 }; 2431 static const unsigned int i2c2_d_mux[] = { 2432 I2C2_SCL_D_MARK, I2C2_SDA_D_MARK, 2433 }; 2434 /* - I2C3 ------------------------------------------------------------------- */ 2435 static const unsigned int i2c3_pins[] = { 2436 /* SCL, SDA */ 2437 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16), 2438 }; 2439 static const unsigned int i2c3_mux[] = { 2440 I2C3_SCL_MARK, I2C3_SDA_MARK, 2441 }; 2442 static const unsigned int i2c3_b_pins[] = { 2443 /* SCL, SDA */ 2444 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16), 2445 }; 2446 static const unsigned int i2c3_b_mux[] = { 2447 I2C3_SCL_B_MARK, I2C3_SDA_B_MARK, 2448 }; 2449 static const unsigned int i2c3_c_pins[] = { 2450 /* SCL, SDA */ 2451 RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23), 2452 }; 2453 static const unsigned int i2c3_c_mux[] = { 2454 I2C3_SCL_C_MARK, I2C3_SDA_C_MARK, 2455 }; 2456 static const unsigned int i2c3_d_pins[] = { 2457 /* SCL, SDA */ 2458 RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28), 2459 }; 2460 static const unsigned int i2c3_d_mux[] = { 2461 I2C3_SCL_D_MARK, I2C3_SDA_D_MARK, 2462 }; 2463 /* - I2C4 ------------------------------------------------------------------- */ 2464 static const unsigned int i2c4_pins[] = { 2465 /* SCL, SDA */ 2466 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14), 2467 }; 2468 static const unsigned int i2c4_mux[] = { 2469 I2C4_SCL_MARK, I2C4_SDA_MARK, 2470 }; 2471 static const unsigned int i2c4_b_pins[] = { 2472 /* SCL, SDA */ 2473 RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28), 2474 }; 2475 static const unsigned int i2c4_b_mux[] = { 2476 I2C4_SCL_B_MARK, I2C4_SDA_B_MARK, 2477 }; 2478 static const unsigned int i2c4_c_pins[] = { 2479 /* SCL, SDA */ 2480 RCAR_GP_PIN(7, 13), RCAR_GP_PIN(7, 14), 2481 }; 2482 static const unsigned int i2c4_c_mux[] = { 2483 I2C4_SCL_C_MARK, I2C4_SDA_C_MARK, 2484 }; 2485 /* - I2C7 ------------------------------------------------------------------- */ 2486 static const unsigned int i2c7_pins[] = { 2487 /* SCL, SDA */ 2488 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16), 2489 }; 2490 static const unsigned int i2c7_mux[] = { 2491 IIC0_SCL_MARK, IIC0_SDA_MARK, 2492 }; 2493 static const unsigned int i2c7_b_pins[] = { 2494 /* SCL, SDA */ 2495 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), 2496 }; 2497 static const unsigned int i2c7_b_mux[] = { 2498 IIC0_SCL_B_MARK, IIC0_SDA_B_MARK, 2499 }; 2500 static const unsigned int i2c7_c_pins[] = { 2501 /* SCL, SDA */ 2502 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29), 2503 }; 2504 static const unsigned int i2c7_c_mux[] = { 2505 IIC0_SCL_C_MARK, IIC0_SDA_C_MARK, 2506 }; 2507 /* - I2C8 ------------------------------------------------------------------- */ 2508 static const unsigned int i2c8_pins[] = { 2509 /* SCL, SDA */ 2510 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14), 2511 }; 2512 static const unsigned int i2c8_mux[] = { 2513 IIC1_SCL_MARK, IIC1_SDA_MARK, 2514 }; 2515 static const unsigned int i2c8_b_pins[] = { 2516 /* SCL, SDA */ 2517 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), 2518 }; 2519 static const unsigned int i2c8_b_mux[] = { 2520 IIC1_SCL_B_MARK, IIC1_SDA_B_MARK, 2521 }; 2522 static const unsigned int i2c8_c_pins[] = { 2523 /* SCL, SDA */ 2524 RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23), 2525 }; 2526 static const unsigned int i2c8_c_mux[] = { 2527 IIC1_SCL_C_MARK, IIC1_SDA_C_MARK, 2528 }; 2529 /* - INTC ------------------------------------------------------------------- */ 2530 static const unsigned int intc_irq0_pins[] = { 2531 /* IRQ */ 2532 RCAR_GP_PIN(7, 10), 2533 }; 2534 static const unsigned int intc_irq0_mux[] = { 2535 IRQ0_MARK, 2536 }; 2537 static const unsigned int intc_irq1_pins[] = { 2538 /* IRQ */ 2539 RCAR_GP_PIN(7, 11), 2540 }; 2541 static const unsigned int intc_irq1_mux[] = { 2542 IRQ1_MARK, 2543 }; 2544 static const unsigned int intc_irq2_pins[] = { 2545 /* IRQ */ 2546 RCAR_GP_PIN(7, 12), 2547 }; 2548 static const unsigned int intc_irq2_mux[] = { 2549 IRQ2_MARK, 2550 }; 2551 static const unsigned int intc_irq3_pins[] = { 2552 /* IRQ */ 2553 RCAR_GP_PIN(7, 13), 2554 }; 2555 static const unsigned int intc_irq3_mux[] = { 2556 IRQ3_MARK, 2557 }; 2558 2559 #if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793) 2560 /* - MLB+ ------------------------------------------------------------------- */ 2561 static const unsigned int mlb_3pin_pins[] = { 2562 RCAR_GP_PIN(7, 7), RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9), 2563 }; 2564 static const unsigned int mlb_3pin_mux[] = { 2565 MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK, 2566 }; 2567 #endif /* CONFIG_PINCTRL_PFC_R8A7791 || CONFIG_PINCTRL_PFC_R8A7793 */ 2568 2569 /* - MMCIF ------------------------------------------------------------------ */ 2570 static const unsigned int mmc_data1_pins[] = { 2571 /* D[0] */ 2572 RCAR_GP_PIN(6, 18), 2573 }; 2574 static const unsigned int mmc_data1_mux[] = { 2575 MMC_D0_MARK, 2576 }; 2577 static const unsigned int mmc_data4_pins[] = { 2578 /* D[0:3] */ 2579 RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19), 2580 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21), 2581 }; 2582 static const unsigned int mmc_data4_mux[] = { 2583 MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK, 2584 }; 2585 static const unsigned int mmc_data8_pins[] = { 2586 /* D[0:7] */ 2587 RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19), 2588 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21), 2589 RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23), 2590 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29), 2591 }; 2592 static const unsigned int mmc_data8_mux[] = { 2593 MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK, 2594 MMC_D4_MARK, MMC_D5_MARK, MMC_D6_MARK, MMC_D7_MARK, 2595 }; 2596 static const unsigned int mmc_data8_b_pins[] = { 2597 /* D[0:7] */ 2598 RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19), 2599 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21), 2600 RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23), 2601 RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 7), 2602 }; 2603 static const unsigned int mmc_data8_b_mux[] = { 2604 MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK, 2605 MMC_D4_MARK, MMC_D5_MARK, MMC_D6_B_MARK, MMC_D7_B_MARK, 2606 }; 2607 static const unsigned int mmc_ctrl_pins[] = { 2608 /* CLK, CMD */ 2609 RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17), 2610 }; 2611 static const unsigned int mmc_ctrl_mux[] = { 2612 MMC_CLK_MARK, MMC_CMD_MARK, 2613 }; 2614 /* - MSIOF0 ----------------------------------------------------------------- */ 2615 static const unsigned int msiof0_clk_pins[] = { 2616 /* SCK */ 2617 RCAR_GP_PIN(6, 24), 2618 }; 2619 static const unsigned int msiof0_clk_mux[] = { 2620 MSIOF0_SCK_MARK, 2621 }; 2622 static const unsigned int msiof0_sync_pins[] = { 2623 /* SYNC */ 2624 RCAR_GP_PIN(6, 25), 2625 }; 2626 static const unsigned int msiof0_sync_mux[] = { 2627 MSIOF0_SYNC_MARK, 2628 }; 2629 static const unsigned int msiof0_ss1_pins[] = { 2630 /* SS1 */ 2631 RCAR_GP_PIN(6, 28), 2632 }; 2633 static const unsigned int msiof0_ss1_mux[] = { 2634 MSIOF0_SS1_MARK, 2635 }; 2636 static const unsigned int msiof0_ss2_pins[] = { 2637 /* SS2 */ 2638 RCAR_GP_PIN(6, 29), 2639 }; 2640 static const unsigned int msiof0_ss2_mux[] = { 2641 MSIOF0_SS2_MARK, 2642 }; 2643 static const unsigned int msiof0_rx_pins[] = { 2644 /* RXD */ 2645 RCAR_GP_PIN(6, 27), 2646 }; 2647 static const unsigned int msiof0_rx_mux[] = { 2648 MSIOF0_RXD_MARK, 2649 }; 2650 static const unsigned int msiof0_tx_pins[] = { 2651 /* TXD */ 2652 RCAR_GP_PIN(6, 26), 2653 }; 2654 static const unsigned int msiof0_tx_mux[] = { 2655 MSIOF0_TXD_MARK, 2656 }; 2657 2658 static const unsigned int msiof0_clk_b_pins[] = { 2659 /* SCK */ 2660 RCAR_GP_PIN(0, 16), 2661 }; 2662 static const unsigned int msiof0_clk_b_mux[] = { 2663 MSIOF0_SCK_B_MARK, 2664 }; 2665 static const unsigned int msiof0_sync_b_pins[] = { 2666 /* SYNC */ 2667 RCAR_GP_PIN(0, 17), 2668 }; 2669 static const unsigned int msiof0_sync_b_mux[] = { 2670 MSIOF0_SYNC_B_MARK, 2671 }; 2672 static const unsigned int msiof0_ss1_b_pins[] = { 2673 /* SS1 */ 2674 RCAR_GP_PIN(0, 18), 2675 }; 2676 static const unsigned int msiof0_ss1_b_mux[] = { 2677 MSIOF0_SS1_B_MARK, 2678 }; 2679 static const unsigned int msiof0_ss2_b_pins[] = { 2680 /* SS2 */ 2681 RCAR_GP_PIN(0, 19), 2682 }; 2683 static const unsigned int msiof0_ss2_b_mux[] = { 2684 MSIOF0_SS2_B_MARK, 2685 }; 2686 static const unsigned int msiof0_rx_b_pins[] = { 2687 /* RXD */ 2688 RCAR_GP_PIN(0, 21), 2689 }; 2690 static const unsigned int msiof0_rx_b_mux[] = { 2691 MSIOF0_RXD_B_MARK, 2692 }; 2693 static const unsigned int msiof0_tx_b_pins[] = { 2694 /* TXD */ 2695 RCAR_GP_PIN(0, 20), 2696 }; 2697 static const unsigned int msiof0_tx_b_mux[] = { 2698 MSIOF0_TXD_B_MARK, 2699 }; 2700 2701 static const unsigned int msiof0_clk_c_pins[] = { 2702 /* SCK */ 2703 RCAR_GP_PIN(5, 26), 2704 }; 2705 static const unsigned int msiof0_clk_c_mux[] = { 2706 MSIOF0_SCK_C_MARK, 2707 }; 2708 static const unsigned int msiof0_sync_c_pins[] = { 2709 /* SYNC */ 2710 RCAR_GP_PIN(5, 25), 2711 }; 2712 static const unsigned int msiof0_sync_c_mux[] = { 2713 MSIOF0_SYNC_C_MARK, 2714 }; 2715 static const unsigned int msiof0_ss1_c_pins[] = { 2716 /* SS1 */ 2717 RCAR_GP_PIN(5, 27), 2718 }; 2719 static const unsigned int msiof0_ss1_c_mux[] = { 2720 MSIOF0_SS1_C_MARK, 2721 }; 2722 static const unsigned int msiof0_ss2_c_pins[] = { 2723 /* SS2 */ 2724 RCAR_GP_PIN(5, 28), 2725 }; 2726 static const unsigned int msiof0_ss2_c_mux[] = { 2727 MSIOF0_SS2_C_MARK, 2728 }; 2729 static const unsigned int msiof0_rx_c_pins[] = { 2730 /* RXD */ 2731 RCAR_GP_PIN(5, 29), 2732 }; 2733 static const unsigned int msiof0_rx_c_mux[] = { 2734 MSIOF0_RXD_C_MARK, 2735 }; 2736 static const unsigned int msiof0_tx_c_pins[] = { 2737 /* TXD */ 2738 RCAR_GP_PIN(5, 30), 2739 }; 2740 static const unsigned int msiof0_tx_c_mux[] = { 2741 MSIOF0_TXD_C_MARK, 2742 }; 2743 /* - MSIOF1 ----------------------------------------------------------------- */ 2744 static const unsigned int msiof1_clk_pins[] = { 2745 /* SCK */ 2746 RCAR_GP_PIN(0, 22), 2747 }; 2748 static const unsigned int msiof1_clk_mux[] = { 2749 MSIOF1_SCK_MARK, 2750 }; 2751 static const unsigned int msiof1_sync_pins[] = { 2752 /* SYNC */ 2753 RCAR_GP_PIN(0, 23), 2754 }; 2755 static const unsigned int msiof1_sync_mux[] = { 2756 MSIOF1_SYNC_MARK, 2757 }; 2758 static const unsigned int msiof1_ss1_pins[] = { 2759 /* SS1 */ 2760 RCAR_GP_PIN(0, 24), 2761 }; 2762 static const unsigned int msiof1_ss1_mux[] = { 2763 MSIOF1_SS1_MARK, 2764 }; 2765 static const unsigned int msiof1_ss2_pins[] = { 2766 /* SS2 */ 2767 RCAR_GP_PIN(0, 25), 2768 }; 2769 static const unsigned int msiof1_ss2_mux[] = { 2770 MSIOF1_SS2_MARK, 2771 }; 2772 static const unsigned int msiof1_rx_pins[] = { 2773 /* RXD */ 2774 RCAR_GP_PIN(0, 27), 2775 }; 2776 static const unsigned int msiof1_rx_mux[] = { 2777 MSIOF1_RXD_MARK, 2778 }; 2779 static const unsigned int msiof1_tx_pins[] = { 2780 /* TXD */ 2781 RCAR_GP_PIN(0, 26), 2782 }; 2783 static const unsigned int msiof1_tx_mux[] = { 2784 MSIOF1_TXD_MARK, 2785 }; 2786 2787 static const unsigned int msiof1_clk_b_pins[] = { 2788 /* SCK */ 2789 RCAR_GP_PIN(2, 29), 2790 }; 2791 static const unsigned int msiof1_clk_b_mux[] = { 2792 MSIOF1_SCK_B_MARK, 2793 }; 2794 static const unsigned int msiof1_sync_b_pins[] = { 2795 /* SYNC */ 2796 RCAR_GP_PIN(2, 30), 2797 }; 2798 static const unsigned int msiof1_sync_b_mux[] = { 2799 MSIOF1_SYNC_B_MARK, 2800 }; 2801 static const unsigned int msiof1_ss1_b_pins[] = { 2802 /* SS1 */ 2803 RCAR_GP_PIN(2, 31), 2804 }; 2805 static const unsigned int msiof1_ss1_b_mux[] = { 2806 MSIOF1_SS1_B_MARK, 2807 }; 2808 static const unsigned int msiof1_ss2_b_pins[] = { 2809 /* SS2 */ 2810 RCAR_GP_PIN(7, 16), 2811 }; 2812 static const unsigned int msiof1_ss2_b_mux[] = { 2813 MSIOF1_SS2_B_MARK, 2814 }; 2815 static const unsigned int msiof1_rx_b_pins[] = { 2816 /* RXD */ 2817 RCAR_GP_PIN(7, 18), 2818 }; 2819 static const unsigned int msiof1_rx_b_mux[] = { 2820 MSIOF1_RXD_B_MARK, 2821 }; 2822 static const unsigned int msiof1_tx_b_pins[] = { 2823 /* TXD */ 2824 RCAR_GP_PIN(7, 17), 2825 }; 2826 static const unsigned int msiof1_tx_b_mux[] = { 2827 MSIOF1_TXD_B_MARK, 2828 }; 2829 2830 static const unsigned int msiof1_clk_c_pins[] = { 2831 /* SCK */ 2832 RCAR_GP_PIN(2, 15), 2833 }; 2834 static const unsigned int msiof1_clk_c_mux[] = { 2835 MSIOF1_SCK_C_MARK, 2836 }; 2837 static const unsigned int msiof1_sync_c_pins[] = { 2838 /* SYNC */ 2839 RCAR_GP_PIN(2, 16), 2840 }; 2841 static const unsigned int msiof1_sync_c_mux[] = { 2842 MSIOF1_SYNC_C_MARK, 2843 }; 2844 static const unsigned int msiof1_rx_c_pins[] = { 2845 /* RXD */ 2846 RCAR_GP_PIN(2, 18), 2847 }; 2848 static const unsigned int msiof1_rx_c_mux[] = { 2849 MSIOF1_RXD_C_MARK, 2850 }; 2851 static const unsigned int msiof1_tx_c_pins[] = { 2852 /* TXD */ 2853 RCAR_GP_PIN(2, 17), 2854 }; 2855 static const unsigned int msiof1_tx_c_mux[] = { 2856 MSIOF1_TXD_C_MARK, 2857 }; 2858 2859 static const unsigned int msiof1_clk_d_pins[] = { 2860 /* SCK */ 2861 RCAR_GP_PIN(0, 28), 2862 }; 2863 static const unsigned int msiof1_clk_d_mux[] = { 2864 MSIOF1_SCK_D_MARK, 2865 }; 2866 static const unsigned int msiof1_sync_d_pins[] = { 2867 /* SYNC */ 2868 RCAR_GP_PIN(0, 30), 2869 }; 2870 static const unsigned int msiof1_sync_d_mux[] = { 2871 MSIOF1_SYNC_D_MARK, 2872 }; 2873 static const unsigned int msiof1_ss1_d_pins[] = { 2874 /* SS1 */ 2875 RCAR_GP_PIN(0, 29), 2876 }; 2877 static const unsigned int msiof1_ss1_d_mux[] = { 2878 MSIOF1_SS1_D_MARK, 2879 }; 2880 static const unsigned int msiof1_rx_d_pins[] = { 2881 /* RXD */ 2882 RCAR_GP_PIN(0, 27), 2883 }; 2884 static const unsigned int msiof1_rx_d_mux[] = { 2885 MSIOF1_RXD_D_MARK, 2886 }; 2887 static const unsigned int msiof1_tx_d_pins[] = { 2888 /* TXD */ 2889 RCAR_GP_PIN(0, 26), 2890 }; 2891 static const unsigned int msiof1_tx_d_mux[] = { 2892 MSIOF1_TXD_D_MARK, 2893 }; 2894 2895 static const unsigned int msiof1_clk_e_pins[] = { 2896 /* SCK */ 2897 RCAR_GP_PIN(5, 18), 2898 }; 2899 static const unsigned int msiof1_clk_e_mux[] = { 2900 MSIOF1_SCK_E_MARK, 2901 }; 2902 static const unsigned int msiof1_sync_e_pins[] = { 2903 /* SYNC */ 2904 RCAR_GP_PIN(5, 19), 2905 }; 2906 static const unsigned int msiof1_sync_e_mux[] = { 2907 MSIOF1_SYNC_E_MARK, 2908 }; 2909 static const unsigned int msiof1_rx_e_pins[] = { 2910 /* RXD */ 2911 RCAR_GP_PIN(5, 17), 2912 }; 2913 static const unsigned int msiof1_rx_e_mux[] = { 2914 MSIOF1_RXD_E_MARK, 2915 }; 2916 static const unsigned int msiof1_tx_e_pins[] = { 2917 /* TXD */ 2918 RCAR_GP_PIN(5, 20), 2919 }; 2920 static const unsigned int msiof1_tx_e_mux[] = { 2921 MSIOF1_TXD_E_MARK, 2922 }; 2923 /* - MSIOF2 ----------------------------------------------------------------- */ 2924 static const unsigned int msiof2_clk_pins[] = { 2925 /* SCK */ 2926 RCAR_GP_PIN(1, 13), 2927 }; 2928 static const unsigned int msiof2_clk_mux[] = { 2929 MSIOF2_SCK_MARK, 2930 }; 2931 static const unsigned int msiof2_sync_pins[] = { 2932 /* SYNC */ 2933 RCAR_GP_PIN(1, 14), 2934 }; 2935 static const unsigned int msiof2_sync_mux[] = { 2936 MSIOF2_SYNC_MARK, 2937 }; 2938 static const unsigned int msiof2_ss1_pins[] = { 2939 /* SS1 */ 2940 RCAR_GP_PIN(1, 17), 2941 }; 2942 static const unsigned int msiof2_ss1_mux[] = { 2943 MSIOF2_SS1_MARK, 2944 }; 2945 static const unsigned int msiof2_ss2_pins[] = { 2946 /* SS2 */ 2947 RCAR_GP_PIN(1, 18), 2948 }; 2949 static const unsigned int msiof2_ss2_mux[] = { 2950 MSIOF2_SS2_MARK, 2951 }; 2952 static const unsigned int msiof2_rx_pins[] = { 2953 /* RXD */ 2954 RCAR_GP_PIN(1, 16), 2955 }; 2956 static const unsigned int msiof2_rx_mux[] = { 2957 MSIOF2_RXD_MARK, 2958 }; 2959 static const unsigned int msiof2_tx_pins[] = { 2960 /* TXD */ 2961 RCAR_GP_PIN(1, 15), 2962 }; 2963 static const unsigned int msiof2_tx_mux[] = { 2964 MSIOF2_TXD_MARK, 2965 }; 2966 2967 static const unsigned int msiof2_clk_b_pins[] = { 2968 /* SCK */ 2969 RCAR_GP_PIN(3, 0), 2970 }; 2971 static const unsigned int msiof2_clk_b_mux[] = { 2972 MSIOF2_SCK_B_MARK, 2973 }; 2974 static const unsigned int msiof2_sync_b_pins[] = { 2975 /* SYNC */ 2976 RCAR_GP_PIN(3, 1), 2977 }; 2978 static const unsigned int msiof2_sync_b_mux[] = { 2979 MSIOF2_SYNC_B_MARK, 2980 }; 2981 static const unsigned int msiof2_ss1_b_pins[] = { 2982 /* SS1 */ 2983 RCAR_GP_PIN(3, 8), 2984 }; 2985 static const unsigned int msiof2_ss1_b_mux[] = { 2986 MSIOF2_SS1_B_MARK, 2987 }; 2988 static const unsigned int msiof2_ss2_b_pins[] = { 2989 /* SS2 */ 2990 RCAR_GP_PIN(3, 9), 2991 }; 2992 static const unsigned int msiof2_ss2_b_mux[] = { 2993 MSIOF2_SS2_B_MARK, 2994 }; 2995 static const unsigned int msiof2_rx_b_pins[] = { 2996 /* RXD */ 2997 RCAR_GP_PIN(3, 17), 2998 }; 2999 static const unsigned int msiof2_rx_b_mux[] = { 3000 MSIOF2_RXD_B_MARK, 3001 }; 3002 static const unsigned int msiof2_tx_b_pins[] = { 3003 /* TXD */ 3004 RCAR_GP_PIN(3, 16), 3005 }; 3006 static const unsigned int msiof2_tx_b_mux[] = { 3007 MSIOF2_TXD_B_MARK, 3008 }; 3009 3010 static const unsigned int msiof2_clk_c_pins[] = { 3011 /* SCK */ 3012 RCAR_GP_PIN(2, 2), 3013 }; 3014 static const unsigned int msiof2_clk_c_mux[] = { 3015 MSIOF2_SCK_C_MARK, 3016 }; 3017 static const unsigned int msiof2_sync_c_pins[] = { 3018 /* SYNC */ 3019 RCAR_GP_PIN(2, 3), 3020 }; 3021 static const unsigned int msiof2_sync_c_mux[] = { 3022 MSIOF2_SYNC_C_MARK, 3023 }; 3024 static const unsigned int msiof2_rx_c_pins[] = { 3025 /* RXD */ 3026 RCAR_GP_PIN(2, 5), 3027 }; 3028 static const unsigned int msiof2_rx_c_mux[] = { 3029 MSIOF2_RXD_C_MARK, 3030 }; 3031 static const unsigned int msiof2_tx_c_pins[] = { 3032 /* TXD */ 3033 RCAR_GP_PIN(2, 4), 3034 }; 3035 static const unsigned int msiof2_tx_c_mux[] = { 3036 MSIOF2_TXD_C_MARK, 3037 }; 3038 3039 static const unsigned int msiof2_clk_d_pins[] = { 3040 /* SCK */ 3041 RCAR_GP_PIN(2, 14), 3042 }; 3043 static const unsigned int msiof2_clk_d_mux[] = { 3044 MSIOF2_SCK_D_MARK, 3045 }; 3046 static const unsigned int msiof2_sync_d_pins[] = { 3047 /* SYNC */ 3048 RCAR_GP_PIN(2, 15), 3049 }; 3050 static const unsigned int msiof2_sync_d_mux[] = { 3051 MSIOF2_SYNC_D_MARK, 3052 }; 3053 static const unsigned int msiof2_ss1_d_pins[] = { 3054 /* SS1 */ 3055 RCAR_GP_PIN(2, 17), 3056 }; 3057 static const unsigned int msiof2_ss1_d_mux[] = { 3058 MSIOF2_SS1_D_MARK, 3059 }; 3060 static const unsigned int msiof2_ss2_d_pins[] = { 3061 /* SS2 */ 3062 RCAR_GP_PIN(2, 19), 3063 }; 3064 static const unsigned int msiof2_ss2_d_mux[] = { 3065 MSIOF2_SS2_D_MARK, 3066 }; 3067 static const unsigned int msiof2_rx_d_pins[] = { 3068 /* RXD */ 3069 RCAR_GP_PIN(2, 18), 3070 }; 3071 static const unsigned int msiof2_rx_d_mux[] = { 3072 MSIOF2_RXD_D_MARK, 3073 }; 3074 static const unsigned int msiof2_tx_d_pins[] = { 3075 /* TXD */ 3076 RCAR_GP_PIN(2, 16), 3077 }; 3078 static const unsigned int msiof2_tx_d_mux[] = { 3079 MSIOF2_TXD_D_MARK, 3080 }; 3081 3082 static const unsigned int msiof2_clk_e_pins[] = { 3083 /* SCK */ 3084 RCAR_GP_PIN(7, 15), 3085 }; 3086 static const unsigned int msiof2_clk_e_mux[] = { 3087 MSIOF2_SCK_E_MARK, 3088 }; 3089 static const unsigned int msiof2_sync_e_pins[] = { 3090 /* SYNC */ 3091 RCAR_GP_PIN(7, 16), 3092 }; 3093 static const unsigned int msiof2_sync_e_mux[] = { 3094 MSIOF2_SYNC_E_MARK, 3095 }; 3096 static const unsigned int msiof2_rx_e_pins[] = { 3097 /* RXD */ 3098 RCAR_GP_PIN(7, 14), 3099 }; 3100 static const unsigned int msiof2_rx_e_mux[] = { 3101 MSIOF2_RXD_E_MARK, 3102 }; 3103 static const unsigned int msiof2_tx_e_pins[] = { 3104 /* TXD */ 3105 RCAR_GP_PIN(7, 13), 3106 }; 3107 static const unsigned int msiof2_tx_e_mux[] = { 3108 MSIOF2_TXD_E_MARK, 3109 }; 3110 /* - PWM -------------------------------------------------------------------- */ 3111 static const unsigned int pwm0_pins[] = { 3112 RCAR_GP_PIN(6, 14), 3113 }; 3114 static const unsigned int pwm0_mux[] = { 3115 PWM0_MARK, 3116 }; 3117 static const unsigned int pwm0_b_pins[] = { 3118 RCAR_GP_PIN(5, 30), 3119 }; 3120 static const unsigned int pwm0_b_mux[] = { 3121 PWM0_B_MARK, 3122 }; 3123 static const unsigned int pwm1_pins[] = { 3124 RCAR_GP_PIN(1, 17), 3125 }; 3126 static const unsigned int pwm1_mux[] = { 3127 PWM1_MARK, 3128 }; 3129 static const unsigned int pwm1_b_pins[] = { 3130 RCAR_GP_PIN(6, 15), 3131 }; 3132 static const unsigned int pwm1_b_mux[] = { 3133 PWM1_B_MARK, 3134 }; 3135 static const unsigned int pwm2_pins[] = { 3136 RCAR_GP_PIN(1, 18), 3137 }; 3138 static const unsigned int pwm2_mux[] = { 3139 PWM2_MARK, 3140 }; 3141 static const unsigned int pwm2_b_pins[] = { 3142 RCAR_GP_PIN(0, 16), 3143 }; 3144 static const unsigned int pwm2_b_mux[] = { 3145 PWM2_B_MARK, 3146 }; 3147 static const unsigned int pwm3_pins[] = { 3148 RCAR_GP_PIN(1, 24), 3149 }; 3150 static const unsigned int pwm3_mux[] = { 3151 PWM3_MARK, 3152 }; 3153 static const unsigned int pwm4_pins[] = { 3154 RCAR_GP_PIN(3, 26), 3155 }; 3156 static const unsigned int pwm4_mux[] = { 3157 PWM4_MARK, 3158 }; 3159 static const unsigned int pwm4_b_pins[] = { 3160 RCAR_GP_PIN(3, 31), 3161 }; 3162 static const unsigned int pwm4_b_mux[] = { 3163 PWM4_B_MARK, 3164 }; 3165 static const unsigned int pwm5_pins[] = { 3166 RCAR_GP_PIN(7, 21), 3167 }; 3168 static const unsigned int pwm5_mux[] = { 3169 PWM5_MARK, 3170 }; 3171 static const unsigned int pwm5_b_pins[] = { 3172 RCAR_GP_PIN(7, 20), 3173 }; 3174 static const unsigned int pwm5_b_mux[] = { 3175 PWM5_B_MARK, 3176 }; 3177 static const unsigned int pwm6_pins[] = { 3178 RCAR_GP_PIN(7, 22), 3179 }; 3180 static const unsigned int pwm6_mux[] = { 3181 PWM6_MARK, 3182 }; 3183 /* - QSPI ------------------------------------------------------------------- */ 3184 static const unsigned int qspi_ctrl_pins[] = { 3185 /* SPCLK, SSL */ 3186 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 9), 3187 }; 3188 static const unsigned int qspi_ctrl_mux[] = { 3189 SPCLK_MARK, SSL_MARK, 3190 }; 3191 static const unsigned int qspi_data2_pins[] = { 3192 /* MOSI_IO0, MISO_IO1 */ 3193 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), 3194 }; 3195 static const unsigned int qspi_data2_mux[] = { 3196 MOSI_IO0_MARK, MISO_IO1_MARK, 3197 }; 3198 static const unsigned int qspi_data4_pins[] = { 3199 /* MOSI_IO0, MISO_IO1, IO2, IO3 */ 3200 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 3201 RCAR_GP_PIN(1, 8), 3202 }; 3203 static const unsigned int qspi_data4_mux[] = { 3204 MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK, 3205 }; 3206 3207 static const unsigned int qspi_ctrl_b_pins[] = { 3208 /* SPCLK, SSL */ 3209 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 5), 3210 }; 3211 static const unsigned int qspi_ctrl_b_mux[] = { 3212 SPCLK_B_MARK, SSL_B_MARK, 3213 }; 3214 static const unsigned int qspi_data2_b_pins[] = { 3215 /* MOSI_IO0, MISO_IO1 */ 3216 RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 2), 3217 }; 3218 static const unsigned int qspi_data2_b_mux[] = { 3219 MOSI_IO0_B_MARK, MISO_IO1_B_MARK, 3220 }; 3221 static const unsigned int qspi_data4_b_pins[] = { 3222 /* MOSI_IO0, MISO_IO1, IO2, IO3 */ 3223 RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3), 3224 RCAR_GP_PIN(6, 4), 3225 }; 3226 static const unsigned int qspi_data4_b_mux[] = { 3227 MOSI_IO0_B_MARK, MISO_IO1_B_MARK, IO2_B_MARK, IO3_B_MARK, 3228 }; 3229 /* - SCIF0 ------------------------------------------------------------------ */ 3230 static const unsigned int scif0_data_pins[] = { 3231 /* RX, TX */ 3232 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), 3233 }; 3234 static const unsigned int scif0_data_mux[] = { 3235 RX0_MARK, TX0_MARK, 3236 }; 3237 static const unsigned int scif0_data_b_pins[] = { 3238 /* RX, TX */ 3239 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0), 3240 }; 3241 static const unsigned int scif0_data_b_mux[] = { 3242 RX0_B_MARK, TX0_B_MARK, 3243 }; 3244 static const unsigned int scif0_data_c_pins[] = { 3245 /* RX, TX */ 3246 RCAR_GP_PIN(4, 26), RCAR_GP_PIN(4, 25), 3247 }; 3248 static const unsigned int scif0_data_c_mux[] = { 3249 RX0_C_MARK, TX0_C_MARK, 3250 }; 3251 static const unsigned int scif0_data_d_pins[] = { 3252 /* RX, TX */ 3253 RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22), 3254 }; 3255 static const unsigned int scif0_data_d_mux[] = { 3256 RX0_D_MARK, TX0_D_MARK, 3257 }; 3258 static const unsigned int scif0_data_e_pins[] = { 3259 /* RX, TX */ 3260 RCAR_GP_PIN(6, 29), RCAR_GP_PIN(6, 28), 3261 }; 3262 static const unsigned int scif0_data_e_mux[] = { 3263 RX0_E_MARK, TX0_E_MARK, 3264 }; 3265 /* - SCIF1 ------------------------------------------------------------------ */ 3266 static const unsigned int scif1_data_pins[] = { 3267 /* RX, TX */ 3268 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8), 3269 }; 3270 static const unsigned int scif1_data_mux[] = { 3271 RX1_MARK, TX1_MARK, 3272 }; 3273 static const unsigned int scif1_data_b_pins[] = { 3274 /* RX, TX */ 3275 RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8), 3276 }; 3277 static const unsigned int scif1_data_b_mux[] = { 3278 RX1_B_MARK, TX1_B_MARK, 3279 }; 3280 static const unsigned int scif1_clk_b_pins[] = { 3281 /* SCK */ 3282 RCAR_GP_PIN(3, 10), 3283 }; 3284 static const unsigned int scif1_clk_b_mux[] = { 3285 SCIF1_SCK_B_MARK, 3286 }; 3287 static const unsigned int scif1_data_c_pins[] = { 3288 /* RX, TX */ 3289 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 27), 3290 }; 3291 static const unsigned int scif1_data_c_mux[] = { 3292 RX1_C_MARK, TX1_C_MARK, 3293 }; 3294 static const unsigned int scif1_data_d_pins[] = { 3295 /* RX, TX */ 3296 RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 24), 3297 }; 3298 static const unsigned int scif1_data_d_mux[] = { 3299 RX1_D_MARK, TX1_D_MARK, 3300 }; 3301 /* - SCIF2 ------------------------------------------------------------------ */ 3302 static const unsigned int scif2_data_pins[] = { 3303 /* RX, TX */ 3304 RCAR_GP_PIN(2, 30), RCAR_GP_PIN(2, 31), 3305 }; 3306 static const unsigned int scif2_data_mux[] = { 3307 RX2_MARK, TX2_MARK, 3308 }; 3309 static const unsigned int scif2_data_b_pins[] = { 3310 /* RX, TX */ 3311 RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16), 3312 }; 3313 static const unsigned int scif2_data_b_mux[] = { 3314 RX2_B_MARK, TX2_B_MARK, 3315 }; 3316 static const unsigned int scif2_clk_b_pins[] = { 3317 /* SCK */ 3318 RCAR_GP_PIN(3, 18), 3319 }; 3320 static const unsigned int scif2_clk_b_mux[] = { 3321 SCIF2_SCK_B_MARK, 3322 }; 3323 static const unsigned int scif2_data_c_pins[] = { 3324 /* RX, TX */ 3325 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25), 3326 }; 3327 static const unsigned int scif2_data_c_mux[] = { 3328 RX2_C_MARK, TX2_C_MARK, 3329 }; 3330 static const unsigned int scif2_data_e_pins[] = { 3331 /* RX, TX */ 3332 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), 3333 }; 3334 static const unsigned int scif2_data_e_mux[] = { 3335 RX2_E_MARK, TX2_E_MARK, 3336 }; 3337 /* - SCIF3 ------------------------------------------------------------------ */ 3338 static const unsigned int scif3_data_pins[] = { 3339 /* RX, TX */ 3340 RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21), 3341 }; 3342 static const unsigned int scif3_data_mux[] = { 3343 RX3_MARK, TX3_MARK, 3344 }; 3345 static const unsigned int scif3_clk_pins[] = { 3346 /* SCK */ 3347 RCAR_GP_PIN(3, 23), 3348 }; 3349 static const unsigned int scif3_clk_mux[] = { 3350 SCIF3_SCK_MARK, 3351 }; 3352 static const unsigned int scif3_data_b_pins[] = { 3353 /* RX, TX */ 3354 RCAR_GP_PIN(3, 29), RCAR_GP_PIN(3, 26), 3355 }; 3356 static const unsigned int scif3_data_b_mux[] = { 3357 RX3_B_MARK, TX3_B_MARK, 3358 }; 3359 static const unsigned int scif3_clk_b_pins[] = { 3360 /* SCK */ 3361 RCAR_GP_PIN(4, 8), 3362 }; 3363 static const unsigned int scif3_clk_b_mux[] = { 3364 SCIF3_SCK_B_MARK, 3365 }; 3366 static const unsigned int scif3_data_c_pins[] = { 3367 /* RX, TX */ 3368 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6), 3369 }; 3370 static const unsigned int scif3_data_c_mux[] = { 3371 RX3_C_MARK, TX3_C_MARK, 3372 }; 3373 static const unsigned int scif3_data_d_pins[] = { 3374 /* RX, TX */ 3375 RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 26), 3376 }; 3377 static const unsigned int scif3_data_d_mux[] = { 3378 RX3_D_MARK, TX3_D_MARK, 3379 }; 3380 /* - SCIF4 ------------------------------------------------------------------ */ 3381 static const unsigned int scif4_data_pins[] = { 3382 /* RX, TX */ 3383 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 1), 3384 }; 3385 static const unsigned int scif4_data_mux[] = { 3386 RX4_MARK, TX4_MARK, 3387 }; 3388 static const unsigned int scif4_data_b_pins[] = { 3389 /* RX, TX */ 3390 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 0), 3391 }; 3392 static const unsigned int scif4_data_b_mux[] = { 3393 RX4_B_MARK, TX4_B_MARK, 3394 }; 3395 static const unsigned int scif4_data_c_pins[] = { 3396 /* RX, TX */ 3397 RCAR_GP_PIN(7, 22), RCAR_GP_PIN(7, 21), 3398 }; 3399 static const unsigned int scif4_data_c_mux[] = { 3400 RX4_C_MARK, TX4_C_MARK, 3401 }; 3402 /* - SCIF5 ------------------------------------------------------------------ */ 3403 static const unsigned int scif5_data_pins[] = { 3404 /* RX, TX */ 3405 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 3), 3406 }; 3407 static const unsigned int scif5_data_mux[] = { 3408 RX5_MARK, TX5_MARK, 3409 }; 3410 static const unsigned int scif5_data_b_pins[] = { 3411 /* RX, TX */ 3412 RCAR_GP_PIN(6, 23), RCAR_GP_PIN(6, 22), 3413 }; 3414 static const unsigned int scif5_data_b_mux[] = { 3415 RX5_B_MARK, TX5_B_MARK, 3416 }; 3417 /* - SCIFA0 ----------------------------------------------------------------- */ 3418 static const unsigned int scifa0_data_pins[] = { 3419 /* RXD, TXD */ 3420 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), 3421 }; 3422 static const unsigned int scifa0_data_mux[] = { 3423 SCIFA0_RXD_MARK, SCIFA0_TXD_MARK, 3424 }; 3425 static const unsigned int scifa0_data_b_pins[] = { 3426 /* RXD, TXD */ 3427 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0), 3428 }; 3429 static const unsigned int scifa0_data_b_mux[] = { 3430 SCIFA0_RXD_B_MARK, SCIFA0_TXD_B_MARK 3431 }; 3432 /* - SCIFA1 ----------------------------------------------------------------- */ 3433 static const unsigned int scifa1_data_pins[] = { 3434 /* RXD, TXD */ 3435 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8), 3436 }; 3437 static const unsigned int scifa1_data_mux[] = { 3438 SCIFA1_RXD_MARK, SCIFA1_TXD_MARK, 3439 }; 3440 static const unsigned int scifa1_clk_pins[] = { 3441 /* SCK */ 3442 RCAR_GP_PIN(3, 10), 3443 }; 3444 static const unsigned int scifa1_clk_mux[] = { 3445 SCIFA1_SCK_MARK, 3446 }; 3447 static const unsigned int scifa1_data_b_pins[] = { 3448 /* RXD, TXD */ 3449 RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8), 3450 }; 3451 static const unsigned int scifa1_data_b_mux[] = { 3452 SCIFA1_RXD_B_MARK, SCIFA1_TXD_B_MARK, 3453 }; 3454 static const unsigned int scifa1_clk_b_pins[] = { 3455 /* SCK */ 3456 RCAR_GP_PIN(1, 0), 3457 }; 3458 static const unsigned int scifa1_clk_b_mux[] = { 3459 SCIFA1_SCK_B_MARK, 3460 }; 3461 static const unsigned int scifa1_data_c_pins[] = { 3462 /* RXD, TXD */ 3463 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), 3464 }; 3465 static const unsigned int scifa1_data_c_mux[] = { 3466 SCIFA1_RXD_C_MARK, SCIFA1_TXD_C_MARK, 3467 }; 3468 /* - SCIFA2 ----------------------------------------------------------------- */ 3469 static const unsigned int scifa2_data_pins[] = { 3470 /* RXD, TXD */ 3471 RCAR_GP_PIN(2, 30), RCAR_GP_PIN(2, 31), 3472 }; 3473 static const unsigned int scifa2_data_mux[] = { 3474 SCIFA2_RXD_MARK, SCIFA2_TXD_MARK, 3475 }; 3476 static const unsigned int scifa2_clk_pins[] = { 3477 /* SCK */ 3478 RCAR_GP_PIN(3, 18), 3479 }; 3480 static const unsigned int scifa2_clk_mux[] = { 3481 SCIFA2_SCK_MARK, 3482 }; 3483 static const unsigned int scifa2_data_b_pins[] = { 3484 /* RXD, TXD */ 3485 RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16), 3486 }; 3487 static const unsigned int scifa2_data_b_mux[] = { 3488 SCIFA2_RXD_B_MARK, SCIFA2_TXD_B_MARK, 3489 }; 3490 /* - SCIFA3 ----------------------------------------------------------------- */ 3491 static const unsigned int scifa3_data_pins[] = { 3492 /* RXD, TXD */ 3493 RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21), 3494 }; 3495 static const unsigned int scifa3_data_mux[] = { 3496 SCIFA3_RXD_MARK, SCIFA3_TXD_MARK, 3497 }; 3498 static const unsigned int scifa3_clk_pins[] = { 3499 /* SCK */ 3500 RCAR_GP_PIN(3, 23), 3501 }; 3502 static const unsigned int scifa3_clk_mux[] = { 3503 SCIFA3_SCK_MARK, 3504 }; 3505 static const unsigned int scifa3_data_b_pins[] = { 3506 /* RXD, TXD */ 3507 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 20), 3508 }; 3509 static const unsigned int scifa3_data_b_mux[] = { 3510 SCIFA3_RXD_B_MARK, SCIFA3_TXD_B_MARK, 3511 }; 3512 static const unsigned int scifa3_clk_b_pins[] = { 3513 /* SCK */ 3514 RCAR_GP_PIN(4, 8), 3515 }; 3516 static const unsigned int scifa3_clk_b_mux[] = { 3517 SCIFA3_SCK_B_MARK, 3518 }; 3519 static const unsigned int scifa3_data_c_pins[] = { 3520 /* RXD, TXD */ 3521 RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 20), 3522 }; 3523 static const unsigned int scifa3_data_c_mux[] = { 3524 SCIFA3_RXD_C_MARK, SCIFA3_TXD_C_MARK, 3525 }; 3526 static const unsigned int scifa3_clk_c_pins[] = { 3527 /* SCK */ 3528 RCAR_GP_PIN(7, 22), 3529 }; 3530 static const unsigned int scifa3_clk_c_mux[] = { 3531 SCIFA3_SCK_C_MARK, 3532 }; 3533 /* - SCIFA4 ----------------------------------------------------------------- */ 3534 static const unsigned int scifa4_data_pins[] = { 3535 /* RXD, TXD */ 3536 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 1), 3537 }; 3538 static const unsigned int scifa4_data_mux[] = { 3539 SCIFA4_RXD_MARK, SCIFA4_TXD_MARK, 3540 }; 3541 static const unsigned int scifa4_data_b_pins[] = { 3542 /* RXD, TXD */ 3543 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 0), 3544 }; 3545 static const unsigned int scifa4_data_b_mux[] = { 3546 SCIFA4_RXD_B_MARK, SCIFA4_TXD_B_MARK, 3547 }; 3548 static const unsigned int scifa4_data_c_pins[] = { 3549 /* RXD, TXD */ 3550 RCAR_GP_PIN(7, 22), RCAR_GP_PIN(7, 21), 3551 }; 3552 static const unsigned int scifa4_data_c_mux[] = { 3553 SCIFA4_RXD_C_MARK, SCIFA4_TXD_C_MARK, 3554 }; 3555 /* - SCIFA5 ----------------------------------------------------------------- */ 3556 static const unsigned int scifa5_data_pins[] = { 3557 /* RXD, TXD */ 3558 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 3), 3559 }; 3560 static const unsigned int scifa5_data_mux[] = { 3561 SCIFA5_RXD_MARK, SCIFA5_TXD_MARK, 3562 }; 3563 static const unsigned int scifa5_data_b_pins[] = { 3564 /* RXD, TXD */ 3565 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6), 3566 }; 3567 static const unsigned int scifa5_data_b_mux[] = { 3568 SCIFA5_RXD_B_MARK, SCIFA5_TXD_B_MARK, 3569 }; 3570 static const unsigned int scifa5_data_c_pins[] = { 3571 /* RXD, TXD */ 3572 RCAR_GP_PIN(6, 23), RCAR_GP_PIN(6, 22), 3573 }; 3574 static const unsigned int scifa5_data_c_mux[] = { 3575 SCIFA5_RXD_C_MARK, SCIFA5_TXD_C_MARK, 3576 }; 3577 /* - SCIFB0 ----------------------------------------------------------------- */ 3578 static const unsigned int scifb0_data_pins[] = { 3579 /* RXD, TXD */ 3580 RCAR_GP_PIN(7, 3), RCAR_GP_PIN(7, 4), 3581 }; 3582 static const unsigned int scifb0_data_mux[] = { 3583 SCIFB0_RXD_MARK, SCIFB0_TXD_MARK, 3584 }; 3585 static const unsigned int scifb0_clk_pins[] = { 3586 /* SCK */ 3587 RCAR_GP_PIN(7, 2), 3588 }; 3589 static const unsigned int scifb0_clk_mux[] = { 3590 SCIFB0_SCK_MARK, 3591 }; 3592 static const unsigned int scifb0_ctrl_pins[] = { 3593 /* RTS, CTS */ 3594 RCAR_GP_PIN(7, 1), RCAR_GP_PIN(7, 0), 3595 }; 3596 static const unsigned int scifb0_ctrl_mux[] = { 3597 SCIFB0_RTS_N_MARK, SCIFB0_CTS_N_MARK, 3598 }; 3599 static const unsigned int scifb0_data_b_pins[] = { 3600 /* RXD, TXD */ 3601 RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21), 3602 }; 3603 static const unsigned int scifb0_data_b_mux[] = { 3604 SCIFB0_RXD_B_MARK, SCIFB0_TXD_B_MARK, 3605 }; 3606 static const unsigned int scifb0_clk_b_pins[] = { 3607 /* SCK */ 3608 RCAR_GP_PIN(5, 31), 3609 }; 3610 static const unsigned int scifb0_clk_b_mux[] = { 3611 SCIFB0_SCK_B_MARK, 3612 }; 3613 static const unsigned int scifb0_ctrl_b_pins[] = { 3614 /* RTS, CTS */ 3615 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 23), 3616 }; 3617 static const unsigned int scifb0_ctrl_b_mux[] = { 3618 SCIFB0_RTS_N_B_MARK, SCIFB0_CTS_N_B_MARK, 3619 }; 3620 static const unsigned int scifb0_data_c_pins[] = { 3621 /* RXD, TXD */ 3622 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), 3623 }; 3624 static const unsigned int scifb0_data_c_mux[] = { 3625 SCIFB0_RXD_C_MARK, SCIFB0_TXD_C_MARK, 3626 }; 3627 static const unsigned int scifb0_clk_c_pins[] = { 3628 /* SCK */ 3629 RCAR_GP_PIN(2, 30), 3630 }; 3631 static const unsigned int scifb0_clk_c_mux[] = { 3632 SCIFB0_SCK_C_MARK, 3633 }; 3634 static const unsigned int scifb0_data_d_pins[] = { 3635 /* RXD, TXD */ 3636 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 18), 3637 }; 3638 static const unsigned int scifb0_data_d_mux[] = { 3639 SCIFB0_RXD_D_MARK, SCIFB0_TXD_D_MARK, 3640 }; 3641 static const unsigned int scifb0_clk_d_pins[] = { 3642 /* SCK */ 3643 RCAR_GP_PIN(4, 17), 3644 }; 3645 static const unsigned int scifb0_clk_d_mux[] = { 3646 SCIFB0_SCK_D_MARK, 3647 }; 3648 /* - SCIFB1 ----------------------------------------------------------------- */ 3649 static const unsigned int scifb1_data_pins[] = { 3650 /* RXD, TXD */ 3651 RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6), 3652 }; 3653 static const unsigned int scifb1_data_mux[] = { 3654 SCIFB1_RXD_MARK, SCIFB1_TXD_MARK, 3655 }; 3656 static const unsigned int scifb1_clk_pins[] = { 3657 /* SCK */ 3658 RCAR_GP_PIN(7, 7), 3659 }; 3660 static const unsigned int scifb1_clk_mux[] = { 3661 SCIFB1_SCK_MARK, 3662 }; 3663 static const unsigned int scifb1_ctrl_pins[] = { 3664 /* RTS, CTS */ 3665 RCAR_GP_PIN(7, 9), RCAR_GP_PIN(7, 8), 3666 }; 3667 static const unsigned int scifb1_ctrl_mux[] = { 3668 SCIFB1_RTS_N_MARK, SCIFB1_CTS_N_MARK, 3669 }; 3670 static const unsigned int scifb1_data_b_pins[] = { 3671 /* RXD, TXD */ 3672 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18), 3673 }; 3674 static const unsigned int scifb1_data_b_mux[] = { 3675 SCIFB1_RXD_B_MARK, SCIFB1_TXD_B_MARK, 3676 }; 3677 static const unsigned int scifb1_clk_b_pins[] = { 3678 /* SCK */ 3679 RCAR_GP_PIN(1, 3), 3680 }; 3681 static const unsigned int scifb1_clk_b_mux[] = { 3682 SCIFB1_SCK_B_MARK, 3683 }; 3684 static const unsigned int scifb1_data_c_pins[] = { 3685 /* RXD, TXD */ 3686 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), 3687 }; 3688 static const unsigned int scifb1_data_c_mux[] = { 3689 SCIFB1_RXD_C_MARK, SCIFB1_TXD_C_MARK, 3690 }; 3691 static const unsigned int scifb1_clk_c_pins[] = { 3692 /* SCK */ 3693 RCAR_GP_PIN(7, 11), 3694 }; 3695 static const unsigned int scifb1_clk_c_mux[] = { 3696 SCIFB1_SCK_C_MARK, 3697 }; 3698 static const unsigned int scifb1_data_d_pins[] = { 3699 /* RXD, TXD */ 3700 RCAR_GP_PIN(7, 10), RCAR_GP_PIN(7, 12), 3701 }; 3702 static const unsigned int scifb1_data_d_mux[] = { 3703 SCIFB1_RXD_D_MARK, SCIFB1_TXD_D_MARK, 3704 }; 3705 /* - SCIFB2 ----------------------------------------------------------------- */ 3706 static const unsigned int scifb2_data_pins[] = { 3707 /* RXD, TXD */ 3708 RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17), 3709 }; 3710 static const unsigned int scifb2_data_mux[] = { 3711 SCIFB2_RXD_MARK, SCIFB2_TXD_MARK, 3712 }; 3713 static const unsigned int scifb2_clk_pins[] = { 3714 /* SCK */ 3715 RCAR_GP_PIN(4, 15), 3716 }; 3717 static const unsigned int scifb2_clk_mux[] = { 3718 SCIFB2_SCK_MARK, 3719 }; 3720 static const unsigned int scifb2_ctrl_pins[] = { 3721 /* RTS, CTS */ 3722 RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13), 3723 }; 3724 static const unsigned int scifb2_ctrl_mux[] = { 3725 SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK, 3726 }; 3727 static const unsigned int scifb2_data_b_pins[] = { 3728 /* RXD, TXD */ 3729 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13), 3730 }; 3731 static const unsigned int scifb2_data_b_mux[] = { 3732 SCIFB2_RXD_B_MARK, SCIFB2_TXD_B_MARK, 3733 }; 3734 static const unsigned int scifb2_clk_b_pins[] = { 3735 /* SCK */ 3736 RCAR_GP_PIN(5, 31), 3737 }; 3738 static const unsigned int scifb2_clk_b_mux[] = { 3739 SCIFB2_SCK_B_MARK, 3740 }; 3741 static const unsigned int scifb2_ctrl_b_pins[] = { 3742 /* RTS, CTS */ 3743 RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14), 3744 }; 3745 static const unsigned int scifb2_ctrl_b_mux[] = { 3746 SCIFB2_RTS_N_B_MARK, SCIFB2_CTS_N_B_MARK, 3747 }; 3748 static const unsigned int scifb2_data_c_pins[] = { 3749 /* RXD, TXD */ 3750 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), 3751 }; 3752 static const unsigned int scifb2_data_c_mux[] = { 3753 SCIFB2_RXD_C_MARK, SCIFB2_TXD_C_MARK, 3754 }; 3755 static const unsigned int scifb2_clk_c_pins[] = { 3756 /* SCK */ 3757 RCAR_GP_PIN(5, 27), 3758 }; 3759 static const unsigned int scifb2_clk_c_mux[] = { 3760 SCIFB2_SCK_C_MARK, 3761 }; 3762 static const unsigned int scifb2_data_d_pins[] = { 3763 /* RXD, TXD */ 3764 RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 25), 3765 }; 3766 static const unsigned int scifb2_data_d_mux[] = { 3767 SCIFB2_RXD_D_MARK, SCIFB2_TXD_D_MARK, 3768 }; 3769 3770 /* - SCIF Clock ------------------------------------------------------------- */ 3771 static const unsigned int scif_clk_pins[] = { 3772 /* SCIF_CLK */ 3773 RCAR_GP_PIN(2, 29), 3774 }; 3775 static const unsigned int scif_clk_mux[] = { 3776 SCIF_CLK_MARK, 3777 }; 3778 static const unsigned int scif_clk_b_pins[] = { 3779 /* SCIF_CLK */ 3780 RCAR_GP_PIN(7, 19), 3781 }; 3782 static const unsigned int scif_clk_b_mux[] = { 3783 SCIF_CLK_B_MARK, 3784 }; 3785 3786 /* - SDHI0 ------------------------------------------------------------------ */ 3787 static const unsigned int sdhi0_data1_pins[] = { 3788 /* D0 */ 3789 RCAR_GP_PIN(6, 2), 3790 }; 3791 static const unsigned int sdhi0_data1_mux[] = { 3792 SD0_DATA0_MARK, 3793 }; 3794 static const unsigned int sdhi0_data4_pins[] = { 3795 /* D[0:3] */ 3796 RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3), 3797 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5), 3798 }; 3799 static const unsigned int sdhi0_data4_mux[] = { 3800 SD0_DATA0_MARK, SD0_DATA1_MARK, SD0_DATA2_MARK, SD0_DATA3_MARK, 3801 }; 3802 static const unsigned int sdhi0_ctrl_pins[] = { 3803 /* CLK, CMD */ 3804 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1), 3805 }; 3806 static const unsigned int sdhi0_ctrl_mux[] = { 3807 SD0_CLK_MARK, SD0_CMD_MARK, 3808 }; 3809 static const unsigned int sdhi0_cd_pins[] = { 3810 /* CD */ 3811 RCAR_GP_PIN(6, 6), 3812 }; 3813 static const unsigned int sdhi0_cd_mux[] = { 3814 SD0_CD_MARK, 3815 }; 3816 static const unsigned int sdhi0_wp_pins[] = { 3817 /* WP */ 3818 RCAR_GP_PIN(6, 7), 3819 }; 3820 static const unsigned int sdhi0_wp_mux[] = { 3821 SD0_WP_MARK, 3822 }; 3823 /* - SDHI1 ------------------------------------------------------------------ */ 3824 static const unsigned int sdhi1_data1_pins[] = { 3825 /* D0 */ 3826 RCAR_GP_PIN(6, 10), 3827 }; 3828 static const unsigned int sdhi1_data1_mux[] = { 3829 SD1_DATA0_MARK, 3830 }; 3831 static const unsigned int sdhi1_data4_pins[] = { 3832 /* D[0:3] */ 3833 RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11), 3834 RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13), 3835 }; 3836 static const unsigned int sdhi1_data4_mux[] = { 3837 SD1_DATA0_MARK, SD1_DATA1_MARK, SD1_DATA2_MARK, SD1_DATA3_MARK, 3838 }; 3839 static const unsigned int sdhi1_ctrl_pins[] = { 3840 /* CLK, CMD */ 3841 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), 3842 }; 3843 static const unsigned int sdhi1_ctrl_mux[] = { 3844 SD1_CLK_MARK, SD1_CMD_MARK, 3845 }; 3846 static const unsigned int sdhi1_cd_pins[] = { 3847 /* CD */ 3848 RCAR_GP_PIN(6, 14), 3849 }; 3850 static const unsigned int sdhi1_cd_mux[] = { 3851 SD1_CD_MARK, 3852 }; 3853 static const unsigned int sdhi1_wp_pins[] = { 3854 /* WP */ 3855 RCAR_GP_PIN(6, 15), 3856 }; 3857 static const unsigned int sdhi1_wp_mux[] = { 3858 SD1_WP_MARK, 3859 }; 3860 /* - SDHI2 ------------------------------------------------------------------ */ 3861 static const unsigned int sdhi2_data1_pins[] = { 3862 /* D0 */ 3863 RCAR_GP_PIN(6, 18), 3864 }; 3865 static const unsigned int sdhi2_data1_mux[] = { 3866 SD2_DATA0_MARK, 3867 }; 3868 static const unsigned int sdhi2_data4_pins[] = { 3869 /* D[0:3] */ 3870 RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19), 3871 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21), 3872 }; 3873 static const unsigned int sdhi2_data4_mux[] = { 3874 SD2_DATA0_MARK, SD2_DATA1_MARK, SD2_DATA2_MARK, SD2_DATA3_MARK, 3875 }; 3876 static const unsigned int sdhi2_ctrl_pins[] = { 3877 /* CLK, CMD */ 3878 RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17), 3879 }; 3880 static const unsigned int sdhi2_ctrl_mux[] = { 3881 SD2_CLK_MARK, SD2_CMD_MARK, 3882 }; 3883 static const unsigned int sdhi2_cd_pins[] = { 3884 /* CD */ 3885 RCAR_GP_PIN(6, 22), 3886 }; 3887 static const unsigned int sdhi2_cd_mux[] = { 3888 SD2_CD_MARK, 3889 }; 3890 static const unsigned int sdhi2_wp_pins[] = { 3891 /* WP */ 3892 RCAR_GP_PIN(6, 23), 3893 }; 3894 static const unsigned int sdhi2_wp_mux[] = { 3895 SD2_WP_MARK, 3896 }; 3897 3898 /* - SSI -------------------------------------------------------------------- */ 3899 static const unsigned int ssi0_data_pins[] = { 3900 /* SDATA */ 3901 RCAR_GP_PIN(2, 2), 3902 }; 3903 3904 static const unsigned int ssi0_data_mux[] = { 3905 SSI_SDATA0_MARK, 3906 }; 3907 3908 static const unsigned int ssi0_data_b_pins[] = { 3909 /* SDATA */ 3910 RCAR_GP_PIN(3, 4), 3911 }; 3912 3913 static const unsigned int ssi0_data_b_mux[] = { 3914 SSI_SDATA0_B_MARK, 3915 }; 3916 3917 static const unsigned int ssi0129_ctrl_pins[] = { 3918 /* SCK, WS */ 3919 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), 3920 }; 3921 3922 static const unsigned int ssi0129_ctrl_mux[] = { 3923 SSI_SCK0129_MARK, SSI_WS0129_MARK, 3924 }; 3925 3926 static const unsigned int ssi0129_ctrl_b_pins[] = { 3927 /* SCK, WS */ 3928 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), 3929 }; 3930 3931 static const unsigned int ssi0129_ctrl_b_mux[] = { 3932 SSI_SCK0129_B_MARK, SSI_WS0129_B_MARK, 3933 }; 3934 3935 static const unsigned int ssi1_data_pins[] = { 3936 /* SDATA */ 3937 RCAR_GP_PIN(2, 5), 3938 }; 3939 3940 static const unsigned int ssi1_data_mux[] = { 3941 SSI_SDATA1_MARK, 3942 }; 3943 3944 static const unsigned int ssi1_data_b_pins[] = { 3945 /* SDATA */ 3946 RCAR_GP_PIN(3, 7), 3947 }; 3948 3949 static const unsigned int ssi1_data_b_mux[] = { 3950 SSI_SDATA1_B_MARK, 3951 }; 3952 3953 static const unsigned int ssi1_ctrl_pins[] = { 3954 /* SCK, WS */ 3955 RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4), 3956 }; 3957 3958 static const unsigned int ssi1_ctrl_mux[] = { 3959 SSI_SCK1_MARK, SSI_WS1_MARK, 3960 }; 3961 3962 static const unsigned int ssi1_ctrl_b_pins[] = { 3963 /* SCK, WS */ 3964 RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6), 3965 }; 3966 3967 static const unsigned int ssi1_ctrl_b_mux[] = { 3968 SSI_SCK1_B_MARK, SSI_WS1_B_MARK, 3969 }; 3970 3971 static const unsigned int ssi2_data_pins[] = { 3972 /* SDATA */ 3973 RCAR_GP_PIN(2, 8), 3974 }; 3975 3976 static const unsigned int ssi2_data_mux[] = { 3977 SSI_SDATA2_MARK, 3978 }; 3979 3980 static const unsigned int ssi2_ctrl_pins[] = { 3981 /* SCK, WS */ 3982 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), 3983 }; 3984 3985 static const unsigned int ssi2_ctrl_mux[] = { 3986 SSI_SCK2_MARK, SSI_WS2_MARK, 3987 }; 3988 3989 static const unsigned int ssi3_data_pins[] = { 3990 /* SDATA */ 3991 RCAR_GP_PIN(2, 11), 3992 }; 3993 3994 static const unsigned int ssi3_data_mux[] = { 3995 SSI_SDATA3_MARK, 3996 }; 3997 3998 static const unsigned int ssi34_ctrl_pins[] = { 3999 /* SCK, WS */ 4000 RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10), 4001 }; 4002 4003 static const unsigned int ssi34_ctrl_mux[] = { 4004 SSI_SCK34_MARK, SSI_WS34_MARK, 4005 }; 4006 4007 static const unsigned int ssi4_data_pins[] = { 4008 /* SDATA */ 4009 RCAR_GP_PIN(2, 14), 4010 }; 4011 4012 static const unsigned int ssi4_data_mux[] = { 4013 SSI_SDATA4_MARK, 4014 }; 4015 4016 static const unsigned int ssi4_ctrl_pins[] = { 4017 /* SCK, WS */ 4018 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13), 4019 }; 4020 4021 static const unsigned int ssi4_ctrl_mux[] = { 4022 SSI_SCK4_MARK, SSI_WS4_MARK, 4023 }; 4024 4025 static const unsigned int ssi5_data_pins[] = { 4026 /* SDATA */ 4027 RCAR_GP_PIN(2, 17), 4028 }; 4029 4030 static const unsigned int ssi5_data_mux[] = { 4031 SSI_SDATA5_MARK, 4032 }; 4033 4034 static const unsigned int ssi5_ctrl_pins[] = { 4035 /* SCK, WS */ 4036 RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16), 4037 }; 4038 4039 static const unsigned int ssi5_ctrl_mux[] = { 4040 SSI_SCK5_MARK, SSI_WS5_MARK, 4041 }; 4042 4043 static const unsigned int ssi6_data_pins[] = { 4044 /* SDATA */ 4045 RCAR_GP_PIN(2, 20), 4046 }; 4047 4048 static const unsigned int ssi6_data_mux[] = { 4049 SSI_SDATA6_MARK, 4050 }; 4051 4052 static const unsigned int ssi6_ctrl_pins[] = { 4053 /* SCK, WS */ 4054 RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19), 4055 }; 4056 4057 static const unsigned int ssi6_ctrl_mux[] = { 4058 SSI_SCK6_MARK, SSI_WS6_MARK, 4059 }; 4060 4061 static const unsigned int ssi7_data_pins[] = { 4062 /* SDATA */ 4063 RCAR_GP_PIN(2, 23), 4064 }; 4065 4066 static const unsigned int ssi7_data_mux[] = { 4067 SSI_SDATA7_MARK, 4068 }; 4069 4070 static const unsigned int ssi7_data_b_pins[] = { 4071 /* SDATA */ 4072 RCAR_GP_PIN(3, 12), 4073 }; 4074 4075 static const unsigned int ssi7_data_b_mux[] = { 4076 SSI_SDATA7_B_MARK, 4077 }; 4078 4079 static const unsigned int ssi78_ctrl_pins[] = { 4080 /* SCK, WS */ 4081 RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22), 4082 }; 4083 4084 static const unsigned int ssi78_ctrl_mux[] = { 4085 SSI_SCK78_MARK, SSI_WS78_MARK, 4086 }; 4087 4088 static const unsigned int ssi78_ctrl_b_pins[] = { 4089 /* SCK, WS */ 4090 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), 4091 }; 4092 4093 static const unsigned int ssi78_ctrl_b_mux[] = { 4094 SSI_SCK78_B_MARK, SSI_WS78_B_MARK, 4095 }; 4096 4097 static const unsigned int ssi8_data_pins[] = { 4098 /* SDATA */ 4099 RCAR_GP_PIN(2, 24), 4100 }; 4101 4102 static const unsigned int ssi8_data_mux[] = { 4103 SSI_SDATA8_MARK, 4104 }; 4105 4106 static const unsigned int ssi8_data_b_pins[] = { 4107 /* SDATA */ 4108 RCAR_GP_PIN(3, 13), 4109 }; 4110 4111 static const unsigned int ssi8_data_b_mux[] = { 4112 SSI_SDATA8_B_MARK, 4113 }; 4114 4115 static const unsigned int ssi9_data_pins[] = { 4116 /* SDATA */ 4117 RCAR_GP_PIN(2, 27), 4118 }; 4119 4120 static const unsigned int ssi9_data_mux[] = { 4121 SSI_SDATA9_MARK, 4122 }; 4123 4124 static const unsigned int ssi9_data_b_pins[] = { 4125 /* SDATA */ 4126 RCAR_GP_PIN(3, 18), 4127 }; 4128 4129 static const unsigned int ssi9_data_b_mux[] = { 4130 SSI_SDATA9_B_MARK, 4131 }; 4132 4133 static const unsigned int ssi9_ctrl_pins[] = { 4134 /* SCK, WS */ 4135 RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 26), 4136 }; 4137 4138 static const unsigned int ssi9_ctrl_mux[] = { 4139 SSI_SCK9_MARK, SSI_WS9_MARK, 4140 }; 4141 4142 static const unsigned int ssi9_ctrl_b_pins[] = { 4143 /* SCK, WS */ 4144 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), 4145 }; 4146 4147 static const unsigned int ssi9_ctrl_b_mux[] = { 4148 SSI_SCK9_B_MARK, SSI_WS9_B_MARK, 4149 }; 4150 4151 /* - TPU -------------------------------------------------------------------- */ 4152 static const unsigned int tpu_to0_pins[] = { 4153 RCAR_GP_PIN(6, 14), 4154 }; 4155 static const unsigned int tpu_to0_mux[] = { 4156 TPU_TO0_MARK, 4157 }; 4158 static const unsigned int tpu_to1_pins[] = { 4159 RCAR_GP_PIN(1, 17), 4160 }; 4161 static const unsigned int tpu_to1_mux[] = { 4162 TPU_TO1_MARK, 4163 }; 4164 static const unsigned int tpu_to2_pins[] = { 4165 RCAR_GP_PIN(1, 18), 4166 }; 4167 static const unsigned int tpu_to2_mux[] = { 4168 TPU_TO2_MARK, 4169 }; 4170 static const unsigned int tpu_to3_pins[] = { 4171 RCAR_GP_PIN(1, 24), 4172 }; 4173 static const unsigned int tpu_to3_mux[] = { 4174 TPU_TO3_MARK, 4175 }; 4176 4177 /* - USB0 ------------------------------------------------------------------- */ 4178 static const unsigned int usb0_pins[] = { 4179 RCAR_GP_PIN(7, 23), /* PWEN */ 4180 RCAR_GP_PIN(7, 24), /* OVC */ 4181 }; 4182 static const unsigned int usb0_mux[] = { 4183 USB0_PWEN_MARK, 4184 USB0_OVC_MARK, 4185 }; 4186 /* - USB1 ------------------------------------------------------------------- */ 4187 static const unsigned int usb1_pins[] = { 4188 RCAR_GP_PIN(7, 25), /* PWEN */ 4189 RCAR_GP_PIN(6, 30), /* OVC */ 4190 }; 4191 static const unsigned int usb1_mux[] = { 4192 USB1_PWEN_MARK, 4193 USB1_OVC_MARK, 4194 }; 4195 /* - VIN0 ------------------------------------------------------------------- */ 4196 static const union vin_data vin0_data_pins = { 4197 .data24 = { 4198 /* B */ 4199 RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 6), 4200 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8), 4201 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10), 4202 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12), 4203 /* G */ 4204 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14), 4205 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16), 4206 RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18), 4207 RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 20), 4208 /* R */ 4209 RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 22), 4210 RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24), 4211 RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26), 4212 RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28), 4213 }, 4214 }; 4215 static const union vin_data vin0_data_mux = { 4216 .data24 = { 4217 /* B */ 4218 VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK, 4219 VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK, 4220 VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK, 4221 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK, 4222 /* G */ 4223 VI0_G0_MARK, VI0_G1_MARK, 4224 VI0_G2_MARK, VI0_G3_MARK, 4225 VI0_G4_MARK, VI0_G5_MARK, 4226 VI0_G6_MARK, VI0_G7_MARK, 4227 /* R */ 4228 VI0_R0_MARK, VI0_R1_MARK, 4229 VI0_R2_MARK, VI0_R3_MARK, 4230 VI0_R4_MARK, VI0_R5_MARK, 4231 VI0_R6_MARK, VI0_R7_MARK, 4232 }, 4233 }; 4234 static const unsigned int vin0_data18_pins[] = { 4235 /* B */ 4236 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8), 4237 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10), 4238 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12), 4239 /* G */ 4240 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16), 4241 RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18), 4242 RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 20), 4243 /* R */ 4244 RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24), 4245 RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26), 4246 RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28), 4247 }; 4248 static const unsigned int vin0_data18_mux[] = { 4249 /* B */ 4250 VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK, 4251 VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK, 4252 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK, 4253 /* G */ 4254 VI0_G2_MARK, VI0_G3_MARK, 4255 VI0_G4_MARK, VI0_G5_MARK, 4256 VI0_G6_MARK, VI0_G7_MARK, 4257 /* R */ 4258 VI0_R2_MARK, VI0_R3_MARK, 4259 VI0_R4_MARK, VI0_R5_MARK, 4260 VI0_R6_MARK, VI0_R7_MARK, 4261 }; 4262 static const unsigned int vin0_sync_pins[] = { 4263 RCAR_GP_PIN(4, 3), /* HSYNC */ 4264 RCAR_GP_PIN(4, 4), /* VSYNC */ 4265 }; 4266 static const unsigned int vin0_sync_mux[] = { 4267 VI0_HSYNC_N_MARK, 4268 VI0_VSYNC_N_MARK, 4269 }; 4270 static const unsigned int vin0_field_pins[] = { 4271 RCAR_GP_PIN(4, 2), 4272 }; 4273 static const unsigned int vin0_field_mux[] = { 4274 VI0_FIELD_MARK, 4275 }; 4276 static const unsigned int vin0_clkenb_pins[] = { 4277 RCAR_GP_PIN(4, 1), 4278 }; 4279 static const unsigned int vin0_clkenb_mux[] = { 4280 VI0_CLKENB_MARK, 4281 }; 4282 static const unsigned int vin0_clk_pins[] = { 4283 RCAR_GP_PIN(4, 0), 4284 }; 4285 static const unsigned int vin0_clk_mux[] = { 4286 VI0_CLK_MARK, 4287 }; 4288 /* - VIN1 ----------------------------------------------------------------- */ 4289 static const unsigned int vin1_data8_pins[] = { 4290 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6), 4291 RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8), 4292 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10), 4293 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 12), 4294 }; 4295 static const unsigned int vin1_data8_mux[] = { 4296 VI1_DATA0_MARK, VI1_DATA1_MARK, 4297 VI1_DATA2_MARK, VI1_DATA3_MARK, 4298 VI1_DATA4_MARK, VI1_DATA5_MARK, 4299 VI1_DATA6_MARK, VI1_DATA7_MARK, 4300 }; 4301 static const unsigned int vin1_sync_pins[] = { 4302 RCAR_GP_PIN(5, 0), /* HSYNC */ 4303 RCAR_GP_PIN(5, 1), /* VSYNC */ 4304 }; 4305 static const unsigned int vin1_sync_mux[] = { 4306 VI1_HSYNC_N_MARK, 4307 VI1_VSYNC_N_MARK, 4308 }; 4309 static const unsigned int vin1_field_pins[] = { 4310 RCAR_GP_PIN(5, 3), 4311 }; 4312 static const unsigned int vin1_field_mux[] = { 4313 VI1_FIELD_MARK, 4314 }; 4315 static const unsigned int vin1_clkenb_pins[] = { 4316 RCAR_GP_PIN(5, 2), 4317 }; 4318 static const unsigned int vin1_clkenb_mux[] = { 4319 VI1_CLKENB_MARK, 4320 }; 4321 static const unsigned int vin1_clk_pins[] = { 4322 RCAR_GP_PIN(5, 4), 4323 }; 4324 static const unsigned int vin1_clk_mux[] = { 4325 VI1_CLK_MARK, 4326 }; 4327 static const union vin_data vin1_data_b_pins = { 4328 .data24 = { 4329 /* B */ 4330 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1), 4331 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), 4332 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), 4333 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13), 4334 /* G */ 4335 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25), 4336 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27), 4337 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29), 4338 RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 22), 4339 /* R */ 4340 RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6), 4341 RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16), 4342 RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18), 4343 RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20), 4344 }, 4345 }; 4346 static const union vin_data vin1_data_b_mux = { 4347 .data24 = { 4348 /* B */ 4349 VI1_DATA0_B_MARK, VI1_DATA1_B_MARK, 4350 VI1_DATA2_B_MARK, VI1_DATA3_B_MARK, 4351 VI1_DATA4_B_MARK, VI1_DATA5_B_MARK, 4352 VI1_DATA6_B_MARK, VI1_DATA7_B_MARK, 4353 /* G */ 4354 VI1_G0_B_MARK, VI1_G1_B_MARK, 4355 VI1_G2_B_MARK, VI1_G3_B_MARK, 4356 VI1_G4_B_MARK, VI1_G5_B_MARK, 4357 VI1_G6_B_MARK, VI1_G7_B_MARK, 4358 /* R */ 4359 VI1_R0_B_MARK, VI1_R1_B_MARK, 4360 VI1_R2_B_MARK, VI1_R3_B_MARK, 4361 VI1_R4_B_MARK, VI1_R5_B_MARK, 4362 VI1_R6_B_MARK, VI1_R7_B_MARK, 4363 }, 4364 }; 4365 static const unsigned int vin1_data18_b_pins[] = { 4366 /* B */ 4367 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), 4368 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), 4369 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13), 4370 /* G */ 4371 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27), 4372 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29), 4373 RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 22), 4374 /* R */ 4375 RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16), 4376 RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18), 4377 RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20), 4378 }; 4379 static const unsigned int vin1_data18_b_mux[] = { 4380 /* B */ 4381 VI1_DATA2_B_MARK, VI1_DATA3_B_MARK, 4382 VI1_DATA4_B_MARK, VI1_DATA5_B_MARK, 4383 VI1_DATA6_B_MARK, VI1_DATA7_B_MARK, 4384 /* G */ 4385 VI1_G2_B_MARK, VI1_G3_B_MARK, 4386 VI1_G4_B_MARK, VI1_G5_B_MARK, 4387 VI1_G6_B_MARK, VI1_G7_B_MARK, 4388 /* R */ 4389 VI1_R2_B_MARK, VI1_R3_B_MARK, 4390 VI1_R4_B_MARK, VI1_R5_B_MARK, 4391 VI1_R6_B_MARK, VI1_R7_B_MARK, 4392 }; 4393 static const unsigned int vin1_sync_b_pins[] = { 4394 RCAR_GP_PIN(3, 17), /* HSYNC */ 4395 RCAR_GP_PIN(3, 18), /* VSYNC */ 4396 }; 4397 static const unsigned int vin1_sync_b_mux[] = { 4398 VI1_HSYNC_N_B_MARK, 4399 VI1_VSYNC_N_B_MARK, 4400 }; 4401 static const unsigned int vin1_field_b_pins[] = { 4402 RCAR_GP_PIN(3, 20), 4403 }; 4404 static const unsigned int vin1_field_b_mux[] = { 4405 VI1_FIELD_B_MARK, 4406 }; 4407 static const unsigned int vin1_clkenb_b_pins[] = { 4408 RCAR_GP_PIN(3, 19), 4409 }; 4410 static const unsigned int vin1_clkenb_b_mux[] = { 4411 VI1_CLKENB_B_MARK, 4412 }; 4413 static const unsigned int vin1_clk_b_pins[] = { 4414 RCAR_GP_PIN(3, 16), 4415 }; 4416 static const unsigned int vin1_clk_b_mux[] = { 4417 VI1_CLK_B_MARK, 4418 }; 4419 /* - VIN2 ----------------------------------------------------------------- */ 4420 static const unsigned int vin2_data8_pins[] = { 4421 RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21), 4422 RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23), 4423 RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 25), 4424 RCAR_GP_PIN(4, 26), RCAR_GP_PIN(4, 27), 4425 }; 4426 static const unsigned int vin2_data8_mux[] = { 4427 VI2_DATA0_MARK, VI2_DATA1_MARK, 4428 VI2_DATA2_MARK, VI2_DATA3_MARK, 4429 VI2_DATA4_MARK, VI2_DATA5_MARK, 4430 VI2_DATA6_MARK, VI2_DATA7_MARK, 4431 }; 4432 static const unsigned int vin2_sync_pins[] = { 4433 RCAR_GP_PIN(4, 15), /* HSYNC */ 4434 RCAR_GP_PIN(4, 16), /* VSYNC */ 4435 }; 4436 static const unsigned int vin2_sync_mux[] = { 4437 VI2_HSYNC_N_MARK, 4438 VI2_VSYNC_N_MARK, 4439 }; 4440 static const unsigned int vin2_field_pins[] = { 4441 RCAR_GP_PIN(4, 18), 4442 }; 4443 static const unsigned int vin2_field_mux[] = { 4444 VI2_FIELD_MARK, 4445 }; 4446 static const unsigned int vin2_clkenb_pins[] = { 4447 RCAR_GP_PIN(4, 17), 4448 }; 4449 static const unsigned int vin2_clkenb_mux[] = { 4450 VI2_CLKENB_MARK, 4451 }; 4452 static const unsigned int vin2_clk_pins[] = { 4453 RCAR_GP_PIN(4, 19), 4454 }; 4455 static const unsigned int vin2_clk_mux[] = { 4456 VI2_CLK_MARK, 4457 }; 4458 4459 static const struct { 4460 struct sh_pfc_pin_group common[346]; 4461 #if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793) 4462 struct sh_pfc_pin_group automotive[9]; 4463 #endif 4464 } pinmux_groups = { 4465 .common = { 4466 SH_PFC_PIN_GROUP(audio_clk_a), 4467 SH_PFC_PIN_GROUP(audio_clk_b), 4468 SH_PFC_PIN_GROUP(audio_clk_b_b), 4469 SH_PFC_PIN_GROUP(audio_clk_c), 4470 SH_PFC_PIN_GROUP(audio_clkout), 4471 SH_PFC_PIN_GROUP(avb_link), 4472 SH_PFC_PIN_GROUP(avb_magic), 4473 SH_PFC_PIN_GROUP(avb_phy_int), 4474 SH_PFC_PIN_GROUP(avb_mdio), 4475 SH_PFC_PIN_GROUP(avb_mii), 4476 SH_PFC_PIN_GROUP(avb_gmii), 4477 SH_PFC_PIN_GROUP(can0_data), 4478 SH_PFC_PIN_GROUP(can0_data_b), 4479 SH_PFC_PIN_GROUP(can0_data_c), 4480 SH_PFC_PIN_GROUP(can0_data_d), 4481 SH_PFC_PIN_GROUP(can0_data_e), 4482 SH_PFC_PIN_GROUP(can0_data_f), 4483 SH_PFC_PIN_GROUP(can1_data), 4484 SH_PFC_PIN_GROUP(can1_data_b), 4485 SH_PFC_PIN_GROUP(can1_data_c), 4486 SH_PFC_PIN_GROUP(can1_data_d), 4487 SH_PFC_PIN_GROUP(can_clk), 4488 SH_PFC_PIN_GROUP(can_clk_b), 4489 SH_PFC_PIN_GROUP(can_clk_c), 4490 SH_PFC_PIN_GROUP(can_clk_d), 4491 SH_PFC_PIN_GROUP(du_rgb666), 4492 SH_PFC_PIN_GROUP(du_rgb888), 4493 SH_PFC_PIN_GROUP(du_clk_out_0), 4494 SH_PFC_PIN_GROUP(du_clk_out_1), 4495 SH_PFC_PIN_GROUP(du_sync), 4496 SH_PFC_PIN_GROUP(du_oddf), 4497 SH_PFC_PIN_GROUP(du_cde), 4498 SH_PFC_PIN_GROUP(du_disp), 4499 SH_PFC_PIN_GROUP(du0_clk_in), 4500 SH_PFC_PIN_GROUP(du1_clk_in), 4501 SH_PFC_PIN_GROUP(du1_clk_in_b), 4502 SH_PFC_PIN_GROUP(du1_clk_in_c), 4503 SH_PFC_PIN_GROUP(eth_link), 4504 SH_PFC_PIN_GROUP(eth_magic), 4505 SH_PFC_PIN_GROUP(eth_mdio), 4506 SH_PFC_PIN_GROUP(eth_rmii), 4507 SH_PFC_PIN_GROUP(hscif0_data), 4508 SH_PFC_PIN_GROUP(hscif0_clk), 4509 SH_PFC_PIN_GROUP(hscif0_ctrl), 4510 SH_PFC_PIN_GROUP(hscif0_data_b), 4511 SH_PFC_PIN_GROUP(hscif0_ctrl_b), 4512 SH_PFC_PIN_GROUP(hscif0_data_c), 4513 SH_PFC_PIN_GROUP(hscif0_clk_c), 4514 SH_PFC_PIN_GROUP(hscif1_data), 4515 SH_PFC_PIN_GROUP(hscif1_clk), 4516 SH_PFC_PIN_GROUP(hscif1_ctrl), 4517 SH_PFC_PIN_GROUP(hscif1_data_b), 4518 SH_PFC_PIN_GROUP(hscif1_data_c), 4519 SH_PFC_PIN_GROUP(hscif1_clk_c), 4520 SH_PFC_PIN_GROUP(hscif1_ctrl_c), 4521 SH_PFC_PIN_GROUP(hscif1_data_d), 4522 SH_PFC_PIN_GROUP(hscif1_data_e), 4523 SH_PFC_PIN_GROUP(hscif1_clk_e), 4524 SH_PFC_PIN_GROUP(hscif1_ctrl_e), 4525 SH_PFC_PIN_GROUP(hscif2_data), 4526 SH_PFC_PIN_GROUP(hscif2_clk), 4527 SH_PFC_PIN_GROUP(hscif2_ctrl), 4528 SH_PFC_PIN_GROUP(hscif2_data_b), 4529 SH_PFC_PIN_GROUP(hscif2_ctrl_b), 4530 SH_PFC_PIN_GROUP(hscif2_data_c), 4531 SH_PFC_PIN_GROUP(hscif2_clk_c), 4532 SH_PFC_PIN_GROUP(hscif2_data_d), 4533 SH_PFC_PIN_GROUP(i2c0), 4534 SH_PFC_PIN_GROUP(i2c0_b), 4535 SH_PFC_PIN_GROUP(i2c0_c), 4536 SH_PFC_PIN_GROUP(i2c1), 4537 SH_PFC_PIN_GROUP(i2c1_b), 4538 SH_PFC_PIN_GROUP(i2c1_c), 4539 SH_PFC_PIN_GROUP(i2c1_d), 4540 SH_PFC_PIN_GROUP(i2c1_e), 4541 SH_PFC_PIN_GROUP(i2c2), 4542 SH_PFC_PIN_GROUP(i2c2_b), 4543 SH_PFC_PIN_GROUP(i2c2_c), 4544 SH_PFC_PIN_GROUP(i2c2_d), 4545 SH_PFC_PIN_GROUP(i2c3), 4546 SH_PFC_PIN_GROUP(i2c3_b), 4547 SH_PFC_PIN_GROUP(i2c3_c), 4548 SH_PFC_PIN_GROUP(i2c3_d), 4549 SH_PFC_PIN_GROUP(i2c4), 4550 SH_PFC_PIN_GROUP(i2c4_b), 4551 SH_PFC_PIN_GROUP(i2c4_c), 4552 SH_PFC_PIN_GROUP(i2c7), 4553 SH_PFC_PIN_GROUP(i2c7_b), 4554 SH_PFC_PIN_GROUP(i2c7_c), 4555 SH_PFC_PIN_GROUP(i2c8), 4556 SH_PFC_PIN_GROUP(i2c8_b), 4557 SH_PFC_PIN_GROUP(i2c8_c), 4558 SH_PFC_PIN_GROUP(intc_irq0), 4559 SH_PFC_PIN_GROUP(intc_irq1), 4560 SH_PFC_PIN_GROUP(intc_irq2), 4561 SH_PFC_PIN_GROUP(intc_irq3), 4562 SH_PFC_PIN_GROUP(mmc_data1), 4563 SH_PFC_PIN_GROUP(mmc_data4), 4564 SH_PFC_PIN_GROUP(mmc_data8), 4565 SH_PFC_PIN_GROUP(mmc_data8_b), 4566 SH_PFC_PIN_GROUP(mmc_ctrl), 4567 SH_PFC_PIN_GROUP(msiof0_clk), 4568 SH_PFC_PIN_GROUP(msiof0_sync), 4569 SH_PFC_PIN_GROUP(msiof0_ss1), 4570 SH_PFC_PIN_GROUP(msiof0_ss2), 4571 SH_PFC_PIN_GROUP(msiof0_rx), 4572 SH_PFC_PIN_GROUP(msiof0_tx), 4573 SH_PFC_PIN_GROUP(msiof0_clk_b), 4574 SH_PFC_PIN_GROUP(msiof0_sync_b), 4575 SH_PFC_PIN_GROUP(msiof0_ss1_b), 4576 SH_PFC_PIN_GROUP(msiof0_ss2_b), 4577 SH_PFC_PIN_GROUP(msiof0_rx_b), 4578 SH_PFC_PIN_GROUP(msiof0_tx_b), 4579 SH_PFC_PIN_GROUP(msiof0_clk_c), 4580 SH_PFC_PIN_GROUP(msiof0_sync_c), 4581 SH_PFC_PIN_GROUP(msiof0_ss1_c), 4582 SH_PFC_PIN_GROUP(msiof0_ss2_c), 4583 SH_PFC_PIN_GROUP(msiof0_rx_c), 4584 SH_PFC_PIN_GROUP(msiof0_tx_c), 4585 SH_PFC_PIN_GROUP(msiof1_clk), 4586 SH_PFC_PIN_GROUP(msiof1_sync), 4587 SH_PFC_PIN_GROUP(msiof1_ss1), 4588 SH_PFC_PIN_GROUP(msiof1_ss2), 4589 SH_PFC_PIN_GROUP(msiof1_rx), 4590 SH_PFC_PIN_GROUP(msiof1_tx), 4591 SH_PFC_PIN_GROUP(msiof1_clk_b), 4592 SH_PFC_PIN_GROUP(msiof1_sync_b), 4593 SH_PFC_PIN_GROUP(msiof1_ss1_b), 4594 SH_PFC_PIN_GROUP(msiof1_ss2_b), 4595 SH_PFC_PIN_GROUP(msiof1_rx_b), 4596 SH_PFC_PIN_GROUP(msiof1_tx_b), 4597 SH_PFC_PIN_GROUP(msiof1_clk_c), 4598 SH_PFC_PIN_GROUP(msiof1_sync_c), 4599 SH_PFC_PIN_GROUP(msiof1_rx_c), 4600 SH_PFC_PIN_GROUP(msiof1_tx_c), 4601 SH_PFC_PIN_GROUP(msiof1_clk_d), 4602 SH_PFC_PIN_GROUP(msiof1_sync_d), 4603 SH_PFC_PIN_GROUP(msiof1_ss1_d), 4604 SH_PFC_PIN_GROUP(msiof1_rx_d), 4605 SH_PFC_PIN_GROUP(msiof1_tx_d), 4606 SH_PFC_PIN_GROUP(msiof1_clk_e), 4607 SH_PFC_PIN_GROUP(msiof1_sync_e), 4608 SH_PFC_PIN_GROUP(msiof1_rx_e), 4609 SH_PFC_PIN_GROUP(msiof1_tx_e), 4610 SH_PFC_PIN_GROUP(msiof2_clk), 4611 SH_PFC_PIN_GROUP(msiof2_sync), 4612 SH_PFC_PIN_GROUP(msiof2_ss1), 4613 SH_PFC_PIN_GROUP(msiof2_ss2), 4614 SH_PFC_PIN_GROUP(msiof2_rx), 4615 SH_PFC_PIN_GROUP(msiof2_tx), 4616 SH_PFC_PIN_GROUP(msiof2_clk_b), 4617 SH_PFC_PIN_GROUP(msiof2_sync_b), 4618 SH_PFC_PIN_GROUP(msiof2_ss1_b), 4619 SH_PFC_PIN_GROUP(msiof2_ss2_b), 4620 SH_PFC_PIN_GROUP(msiof2_rx_b), 4621 SH_PFC_PIN_GROUP(msiof2_tx_b), 4622 SH_PFC_PIN_GROUP(msiof2_clk_c), 4623 SH_PFC_PIN_GROUP(msiof2_sync_c), 4624 SH_PFC_PIN_GROUP(msiof2_rx_c), 4625 SH_PFC_PIN_GROUP(msiof2_tx_c), 4626 SH_PFC_PIN_GROUP(msiof2_clk_d), 4627 SH_PFC_PIN_GROUP(msiof2_sync_d), 4628 SH_PFC_PIN_GROUP(msiof2_ss1_d), 4629 SH_PFC_PIN_GROUP(msiof2_ss2_d), 4630 SH_PFC_PIN_GROUP(msiof2_rx_d), 4631 SH_PFC_PIN_GROUP(msiof2_tx_d), 4632 SH_PFC_PIN_GROUP(msiof2_clk_e), 4633 SH_PFC_PIN_GROUP(msiof2_sync_e), 4634 SH_PFC_PIN_GROUP(msiof2_rx_e), 4635 SH_PFC_PIN_GROUP(msiof2_tx_e), 4636 SH_PFC_PIN_GROUP(pwm0), 4637 SH_PFC_PIN_GROUP(pwm0_b), 4638 SH_PFC_PIN_GROUP(pwm1), 4639 SH_PFC_PIN_GROUP(pwm1_b), 4640 SH_PFC_PIN_GROUP(pwm2), 4641 SH_PFC_PIN_GROUP(pwm2_b), 4642 SH_PFC_PIN_GROUP(pwm3), 4643 SH_PFC_PIN_GROUP(pwm4), 4644 SH_PFC_PIN_GROUP(pwm4_b), 4645 SH_PFC_PIN_GROUP(pwm5), 4646 SH_PFC_PIN_GROUP(pwm5_b), 4647 SH_PFC_PIN_GROUP(pwm6), 4648 SH_PFC_PIN_GROUP(qspi_ctrl), 4649 SH_PFC_PIN_GROUP(qspi_data2), 4650 SH_PFC_PIN_GROUP(qspi_data4), 4651 SH_PFC_PIN_GROUP(qspi_ctrl_b), 4652 SH_PFC_PIN_GROUP(qspi_data2_b), 4653 SH_PFC_PIN_GROUP(qspi_data4_b), 4654 SH_PFC_PIN_GROUP(scif0_data), 4655 SH_PFC_PIN_GROUP(scif0_data_b), 4656 SH_PFC_PIN_GROUP(scif0_data_c), 4657 SH_PFC_PIN_GROUP(scif0_data_d), 4658 SH_PFC_PIN_GROUP(scif0_data_e), 4659 SH_PFC_PIN_GROUP(scif1_data), 4660 SH_PFC_PIN_GROUP(scif1_data_b), 4661 SH_PFC_PIN_GROUP(scif1_clk_b), 4662 SH_PFC_PIN_GROUP(scif1_data_c), 4663 SH_PFC_PIN_GROUP(scif1_data_d), 4664 SH_PFC_PIN_GROUP(scif2_data), 4665 SH_PFC_PIN_GROUP(scif2_data_b), 4666 SH_PFC_PIN_GROUP(scif2_clk_b), 4667 SH_PFC_PIN_GROUP(scif2_data_c), 4668 SH_PFC_PIN_GROUP(scif2_data_e), 4669 SH_PFC_PIN_GROUP(scif3_data), 4670 SH_PFC_PIN_GROUP(scif3_clk), 4671 SH_PFC_PIN_GROUP(scif3_data_b), 4672 SH_PFC_PIN_GROUP(scif3_clk_b), 4673 SH_PFC_PIN_GROUP(scif3_data_c), 4674 SH_PFC_PIN_GROUP(scif3_data_d), 4675 SH_PFC_PIN_GROUP(scif4_data), 4676 SH_PFC_PIN_GROUP(scif4_data_b), 4677 SH_PFC_PIN_GROUP(scif4_data_c), 4678 SH_PFC_PIN_GROUP(scif5_data), 4679 SH_PFC_PIN_GROUP(scif5_data_b), 4680 SH_PFC_PIN_GROUP(scifa0_data), 4681 SH_PFC_PIN_GROUP(scifa0_data_b), 4682 SH_PFC_PIN_GROUP(scifa1_data), 4683 SH_PFC_PIN_GROUP(scifa1_clk), 4684 SH_PFC_PIN_GROUP(scifa1_data_b), 4685 SH_PFC_PIN_GROUP(scifa1_clk_b), 4686 SH_PFC_PIN_GROUP(scifa1_data_c), 4687 SH_PFC_PIN_GROUP(scifa2_data), 4688 SH_PFC_PIN_GROUP(scifa2_clk), 4689 SH_PFC_PIN_GROUP(scifa2_data_b), 4690 SH_PFC_PIN_GROUP(scifa3_data), 4691 SH_PFC_PIN_GROUP(scifa3_clk), 4692 SH_PFC_PIN_GROUP(scifa3_data_b), 4693 SH_PFC_PIN_GROUP(scifa3_clk_b), 4694 SH_PFC_PIN_GROUP(scifa3_data_c), 4695 SH_PFC_PIN_GROUP(scifa3_clk_c), 4696 SH_PFC_PIN_GROUP(scifa4_data), 4697 SH_PFC_PIN_GROUP(scifa4_data_b), 4698 SH_PFC_PIN_GROUP(scifa4_data_c), 4699 SH_PFC_PIN_GROUP(scifa5_data), 4700 SH_PFC_PIN_GROUP(scifa5_data_b), 4701 SH_PFC_PIN_GROUP(scifa5_data_c), 4702 SH_PFC_PIN_GROUP(scifb0_data), 4703 SH_PFC_PIN_GROUP(scifb0_clk), 4704 SH_PFC_PIN_GROUP(scifb0_ctrl), 4705 SH_PFC_PIN_GROUP(scifb0_data_b), 4706 SH_PFC_PIN_GROUP(scifb0_clk_b), 4707 SH_PFC_PIN_GROUP(scifb0_ctrl_b), 4708 SH_PFC_PIN_GROUP(scifb0_data_c), 4709 SH_PFC_PIN_GROUP(scifb0_clk_c), 4710 SH_PFC_PIN_GROUP(scifb0_data_d), 4711 SH_PFC_PIN_GROUP(scifb0_clk_d), 4712 SH_PFC_PIN_GROUP(scifb1_data), 4713 SH_PFC_PIN_GROUP(scifb1_clk), 4714 SH_PFC_PIN_GROUP(scifb1_ctrl), 4715 SH_PFC_PIN_GROUP(scifb1_data_b), 4716 SH_PFC_PIN_GROUP(scifb1_clk_b), 4717 SH_PFC_PIN_GROUP(scifb1_data_c), 4718 SH_PFC_PIN_GROUP(scifb1_clk_c), 4719 SH_PFC_PIN_GROUP(scifb1_data_d), 4720 SH_PFC_PIN_GROUP(scifb2_data), 4721 SH_PFC_PIN_GROUP(scifb2_clk), 4722 SH_PFC_PIN_GROUP(scifb2_ctrl), 4723 SH_PFC_PIN_GROUP(scifb2_data_b), 4724 SH_PFC_PIN_GROUP(scifb2_clk_b), 4725 SH_PFC_PIN_GROUP(scifb2_ctrl_b), 4726 SH_PFC_PIN_GROUP(scifb2_data_c), 4727 SH_PFC_PIN_GROUP(scifb2_clk_c), 4728 SH_PFC_PIN_GROUP(scifb2_data_d), 4729 SH_PFC_PIN_GROUP(scif_clk), 4730 SH_PFC_PIN_GROUP(scif_clk_b), 4731 SH_PFC_PIN_GROUP(sdhi0_data1), 4732 SH_PFC_PIN_GROUP(sdhi0_data4), 4733 SH_PFC_PIN_GROUP(sdhi0_ctrl), 4734 SH_PFC_PIN_GROUP(sdhi0_cd), 4735 SH_PFC_PIN_GROUP(sdhi0_wp), 4736 SH_PFC_PIN_GROUP(sdhi1_data1), 4737 SH_PFC_PIN_GROUP(sdhi1_data4), 4738 SH_PFC_PIN_GROUP(sdhi1_ctrl), 4739 SH_PFC_PIN_GROUP(sdhi1_cd), 4740 SH_PFC_PIN_GROUP(sdhi1_wp), 4741 SH_PFC_PIN_GROUP(sdhi2_data1), 4742 SH_PFC_PIN_GROUP(sdhi2_data4), 4743 SH_PFC_PIN_GROUP(sdhi2_ctrl), 4744 SH_PFC_PIN_GROUP(sdhi2_cd), 4745 SH_PFC_PIN_GROUP(sdhi2_wp), 4746 SH_PFC_PIN_GROUP(ssi0_data), 4747 SH_PFC_PIN_GROUP(ssi0_data_b), 4748 SH_PFC_PIN_GROUP(ssi0129_ctrl), 4749 SH_PFC_PIN_GROUP(ssi0129_ctrl_b), 4750 SH_PFC_PIN_GROUP(ssi1_data), 4751 SH_PFC_PIN_GROUP(ssi1_data_b), 4752 SH_PFC_PIN_GROUP(ssi1_ctrl), 4753 SH_PFC_PIN_GROUP(ssi1_ctrl_b), 4754 SH_PFC_PIN_GROUP(ssi2_data), 4755 SH_PFC_PIN_GROUP(ssi2_ctrl), 4756 SH_PFC_PIN_GROUP(ssi3_data), 4757 SH_PFC_PIN_GROUP(ssi34_ctrl), 4758 SH_PFC_PIN_GROUP(ssi4_data), 4759 SH_PFC_PIN_GROUP(ssi4_ctrl), 4760 SH_PFC_PIN_GROUP(ssi5_data), 4761 SH_PFC_PIN_GROUP(ssi5_ctrl), 4762 SH_PFC_PIN_GROUP(ssi6_data), 4763 SH_PFC_PIN_GROUP(ssi6_ctrl), 4764 SH_PFC_PIN_GROUP(ssi7_data), 4765 SH_PFC_PIN_GROUP(ssi7_data_b), 4766 SH_PFC_PIN_GROUP(ssi78_ctrl), 4767 SH_PFC_PIN_GROUP(ssi78_ctrl_b), 4768 SH_PFC_PIN_GROUP(ssi8_data), 4769 SH_PFC_PIN_GROUP(ssi8_data_b), 4770 SH_PFC_PIN_GROUP(ssi9_data), 4771 SH_PFC_PIN_GROUP(ssi9_data_b), 4772 SH_PFC_PIN_GROUP(ssi9_ctrl), 4773 SH_PFC_PIN_GROUP(ssi9_ctrl_b), 4774 SH_PFC_PIN_GROUP(tpu_to0), 4775 SH_PFC_PIN_GROUP(tpu_to1), 4776 SH_PFC_PIN_GROUP(tpu_to2), 4777 SH_PFC_PIN_GROUP(tpu_to3), 4778 SH_PFC_PIN_GROUP(usb0), 4779 SH_PFC_PIN_GROUP(usb1), 4780 VIN_DATA_PIN_GROUP(vin0_data, 24), 4781 VIN_DATA_PIN_GROUP(vin0_data, 20), 4782 SH_PFC_PIN_GROUP(vin0_data18), 4783 VIN_DATA_PIN_GROUP(vin0_data, 16), 4784 VIN_DATA_PIN_GROUP(vin0_data, 12), 4785 VIN_DATA_PIN_GROUP(vin0_data, 10), 4786 VIN_DATA_PIN_GROUP(vin0_data, 8), 4787 SH_PFC_PIN_GROUP(vin0_sync), 4788 SH_PFC_PIN_GROUP(vin0_field), 4789 SH_PFC_PIN_GROUP(vin0_clkenb), 4790 SH_PFC_PIN_GROUP(vin0_clk), 4791 SH_PFC_PIN_GROUP(vin1_data8), 4792 SH_PFC_PIN_GROUP(vin1_sync), 4793 SH_PFC_PIN_GROUP(vin1_field), 4794 SH_PFC_PIN_GROUP(vin1_clkenb), 4795 SH_PFC_PIN_GROUP(vin1_clk), 4796 VIN_DATA_PIN_GROUP(vin1_data, 24, _b), 4797 VIN_DATA_PIN_GROUP(vin1_data, 20, _b), 4798 SH_PFC_PIN_GROUP(vin1_data18_b), 4799 VIN_DATA_PIN_GROUP(vin1_data, 16, _b), 4800 VIN_DATA_PIN_GROUP(vin1_data, 12, _b), 4801 VIN_DATA_PIN_GROUP(vin1_data, 10, _b), 4802 VIN_DATA_PIN_GROUP(vin1_data, 8, _b), 4803 SH_PFC_PIN_GROUP(vin1_sync_b), 4804 SH_PFC_PIN_GROUP(vin1_field_b), 4805 SH_PFC_PIN_GROUP(vin1_clkenb_b), 4806 SH_PFC_PIN_GROUP(vin1_clk_b), 4807 SH_PFC_PIN_GROUP(vin2_data8), 4808 SH_PFC_PIN_GROUP(vin2_sync), 4809 SH_PFC_PIN_GROUP(vin2_field), 4810 SH_PFC_PIN_GROUP(vin2_clkenb), 4811 SH_PFC_PIN_GROUP(vin2_clk), 4812 }, 4813 #if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793) 4814 .automotive = { 4815 SH_PFC_PIN_GROUP(adi_common), 4816 SH_PFC_PIN_GROUP(adi_chsel0), 4817 SH_PFC_PIN_GROUP(adi_chsel1), 4818 SH_PFC_PIN_GROUP(adi_chsel2), 4819 SH_PFC_PIN_GROUP(adi_common_b), 4820 SH_PFC_PIN_GROUP(adi_chsel0_b), 4821 SH_PFC_PIN_GROUP(adi_chsel1_b), 4822 SH_PFC_PIN_GROUP(adi_chsel2_b), 4823 SH_PFC_PIN_GROUP(mlb_3pin), 4824 } 4825 #endif /* CONFIG_PINCTRL_PFC_R8A7791 || CONFIG_PINCTRL_PFC_R8A7793 */ 4826 }; 4827 4828 #if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793) 4829 static const char * const adi_groups[] = { 4830 "adi_common", 4831 "adi_chsel0", 4832 "adi_chsel1", 4833 "adi_chsel2", 4834 "adi_common_b", 4835 "adi_chsel0_b", 4836 "adi_chsel1_b", 4837 "adi_chsel2_b", 4838 }; 4839 #endif /* CONFIG_PINCTRL_PFC_R8A7791 || CONFIG_PINCTRL_PFC_R8A7793 */ 4840 4841 static const char * const audio_clk_groups[] = { 4842 "audio_clk_a", 4843 "audio_clk_b", 4844 "audio_clk_b_b", 4845 "audio_clk_c", 4846 "audio_clkout", 4847 }; 4848 4849 static const char * const avb_groups[] = { 4850 "avb_link", 4851 "avb_magic", 4852 "avb_phy_int", 4853 "avb_mdio", 4854 "avb_mii", 4855 "avb_gmii", 4856 }; 4857 4858 static const char * const can0_groups[] = { 4859 "can0_data", 4860 "can0_data_b", 4861 "can0_data_c", 4862 "can0_data_d", 4863 "can0_data_e", 4864 "can0_data_f", 4865 /* 4866 * Retained for backwards compatibility, use can_clk_groups in new 4867 * designs. 4868 */ 4869 "can_clk", 4870 "can_clk_b", 4871 "can_clk_c", 4872 "can_clk_d", 4873 }; 4874 4875 static const char * const can1_groups[] = { 4876 "can1_data", 4877 "can1_data_b", 4878 "can1_data_c", 4879 "can1_data_d", 4880 /* 4881 * Retained for backwards compatibility, use can_clk_groups in new 4882 * designs. 4883 */ 4884 "can_clk", 4885 "can_clk_b", 4886 "can_clk_c", 4887 "can_clk_d", 4888 }; 4889 4890 /* 4891 * can_clk_groups allows for independent configuration, use can_clk function 4892 * in new designs. 4893 */ 4894 static const char * const can_clk_groups[] = { 4895 "can_clk", 4896 "can_clk_b", 4897 "can_clk_c", 4898 "can_clk_d", 4899 }; 4900 4901 static const char * const du_groups[] = { 4902 "du_rgb666", 4903 "du_rgb888", 4904 "du_clk_out_0", 4905 "du_clk_out_1", 4906 "du_sync", 4907 "du_oddf", 4908 "du_cde", 4909 "du_disp", 4910 }; 4911 4912 static const char * const du0_groups[] = { 4913 "du0_clk_in", 4914 }; 4915 4916 static const char * const du1_groups[] = { 4917 "du1_clk_in", 4918 "du1_clk_in_b", 4919 "du1_clk_in_c", 4920 }; 4921 4922 static const char * const eth_groups[] = { 4923 "eth_link", 4924 "eth_magic", 4925 "eth_mdio", 4926 "eth_rmii", 4927 }; 4928 4929 static const char * const hscif0_groups[] = { 4930 "hscif0_data", 4931 "hscif0_clk", 4932 "hscif0_ctrl", 4933 "hscif0_data_b", 4934 "hscif0_ctrl_b", 4935 "hscif0_data_c", 4936 "hscif0_clk_c", 4937 }; 4938 4939 static const char * const hscif1_groups[] = { 4940 "hscif1_data", 4941 "hscif1_clk", 4942 "hscif1_ctrl", 4943 "hscif1_data_b", 4944 "hscif1_data_c", 4945 "hscif1_clk_c", 4946 "hscif1_ctrl_c", 4947 "hscif1_data_d", 4948 "hscif1_data_e", 4949 "hscif1_clk_e", 4950 "hscif1_ctrl_e", 4951 }; 4952 4953 static const char * const hscif2_groups[] = { 4954 "hscif2_data", 4955 "hscif2_clk", 4956 "hscif2_ctrl", 4957 "hscif2_data_b", 4958 "hscif2_ctrl_b", 4959 "hscif2_data_c", 4960 "hscif2_clk_c", 4961 "hscif2_data_d", 4962 }; 4963 4964 static const char * const i2c0_groups[] = { 4965 "i2c0", 4966 "i2c0_b", 4967 "i2c0_c", 4968 }; 4969 4970 static const char * const i2c1_groups[] = { 4971 "i2c1", 4972 "i2c1_b", 4973 "i2c1_c", 4974 "i2c1_d", 4975 "i2c1_e", 4976 }; 4977 4978 static const char * const i2c2_groups[] = { 4979 "i2c2", 4980 "i2c2_b", 4981 "i2c2_c", 4982 "i2c2_d", 4983 }; 4984 4985 static const char * const i2c3_groups[] = { 4986 "i2c3", 4987 "i2c3_b", 4988 "i2c3_c", 4989 "i2c3_d", 4990 }; 4991 4992 static const char * const i2c4_groups[] = { 4993 "i2c4", 4994 "i2c4_b", 4995 "i2c4_c", 4996 }; 4997 4998 static const char * const i2c7_groups[] = { 4999 "i2c7", 5000 "i2c7_b", 5001 "i2c7_c", 5002 }; 5003 5004 static const char * const i2c8_groups[] = { 5005 "i2c8", 5006 "i2c8_b", 5007 "i2c8_c", 5008 }; 5009 5010 static const char * const intc_groups[] = { 5011 "intc_irq0", 5012 "intc_irq1", 5013 "intc_irq2", 5014 "intc_irq3", 5015 }; 5016 5017 #if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793) 5018 static const char * const mlb_groups[] = { 5019 "mlb_3pin", 5020 }; 5021 #endif /* CONFIG_PINCTRL_PFC_R8A7791 || CONFIG_PINCTRL_PFC_R8A7793 */ 5022 5023 static const char * const mmc_groups[] = { 5024 "mmc_data1", 5025 "mmc_data4", 5026 "mmc_data8", 5027 "mmc_data8_b", 5028 "mmc_ctrl", 5029 }; 5030 5031 static const char * const msiof0_groups[] = { 5032 "msiof0_clk", 5033 "msiof0_sync", 5034 "msiof0_ss1", 5035 "msiof0_ss2", 5036 "msiof0_rx", 5037 "msiof0_tx", 5038 "msiof0_clk_b", 5039 "msiof0_sync_b", 5040 "msiof0_ss1_b", 5041 "msiof0_ss2_b", 5042 "msiof0_rx_b", 5043 "msiof0_tx_b", 5044 "msiof0_clk_c", 5045 "msiof0_sync_c", 5046 "msiof0_ss1_c", 5047 "msiof0_ss2_c", 5048 "msiof0_rx_c", 5049 "msiof0_tx_c", 5050 }; 5051 5052 static const char * const msiof1_groups[] = { 5053 "msiof1_clk", 5054 "msiof1_sync", 5055 "msiof1_ss1", 5056 "msiof1_ss2", 5057 "msiof1_rx", 5058 "msiof1_tx", 5059 "msiof1_clk_b", 5060 "msiof1_sync_b", 5061 "msiof1_ss1_b", 5062 "msiof1_ss2_b", 5063 "msiof1_rx_b", 5064 "msiof1_tx_b", 5065 "msiof1_clk_c", 5066 "msiof1_sync_c", 5067 "msiof1_rx_c", 5068 "msiof1_tx_c", 5069 "msiof1_clk_d", 5070 "msiof1_sync_d", 5071 "msiof1_ss1_d", 5072 "msiof1_rx_d", 5073 "msiof1_tx_d", 5074 "msiof1_clk_e", 5075 "msiof1_sync_e", 5076 "msiof1_rx_e", 5077 "msiof1_tx_e", 5078 }; 5079 5080 static const char * const msiof2_groups[] = { 5081 "msiof2_clk", 5082 "msiof2_sync", 5083 "msiof2_ss1", 5084 "msiof2_ss2", 5085 "msiof2_rx", 5086 "msiof2_tx", 5087 "msiof2_clk_b", 5088 "msiof2_sync_b", 5089 "msiof2_ss1_b", 5090 "msiof2_ss2_b", 5091 "msiof2_rx_b", 5092 "msiof2_tx_b", 5093 "msiof2_clk_c", 5094 "msiof2_sync_c", 5095 "msiof2_rx_c", 5096 "msiof2_tx_c", 5097 "msiof2_clk_d", 5098 "msiof2_sync_d", 5099 "msiof2_ss1_d", 5100 "msiof2_ss2_d", 5101 "msiof2_rx_d", 5102 "msiof2_tx_d", 5103 "msiof2_clk_e", 5104 "msiof2_sync_e", 5105 "msiof2_rx_e", 5106 "msiof2_tx_e", 5107 }; 5108 5109 static const char * const pwm0_groups[] = { 5110 "pwm0", 5111 "pwm0_b", 5112 }; 5113 5114 static const char * const pwm1_groups[] = { 5115 "pwm1", 5116 "pwm1_b", 5117 }; 5118 5119 static const char * const pwm2_groups[] = { 5120 "pwm2", 5121 "pwm2_b", 5122 }; 5123 5124 static const char * const pwm3_groups[] = { 5125 "pwm3", 5126 }; 5127 5128 static const char * const pwm4_groups[] = { 5129 "pwm4", 5130 "pwm4_b", 5131 }; 5132 5133 static const char * const pwm5_groups[] = { 5134 "pwm5", 5135 "pwm5_b", 5136 }; 5137 5138 static const char * const pwm6_groups[] = { 5139 "pwm6", 5140 }; 5141 5142 static const char * const qspi_groups[] = { 5143 "qspi_ctrl", 5144 "qspi_data2", 5145 "qspi_data4", 5146 "qspi_ctrl_b", 5147 "qspi_data2_b", 5148 "qspi_data4_b", 5149 }; 5150 5151 static const char * const scif0_groups[] = { 5152 "scif0_data", 5153 "scif0_data_b", 5154 "scif0_data_c", 5155 "scif0_data_d", 5156 "scif0_data_e", 5157 }; 5158 5159 static const char * const scif1_groups[] = { 5160 "scif1_data", 5161 "scif1_data_b", 5162 "scif1_clk_b", 5163 "scif1_data_c", 5164 "scif1_data_d", 5165 }; 5166 5167 static const char * const scif2_groups[] = { 5168 "scif2_data", 5169 "scif2_data_b", 5170 "scif2_clk_b", 5171 "scif2_data_c", 5172 "scif2_data_e", 5173 }; 5174 static const char * const scif3_groups[] = { 5175 "scif3_data", 5176 "scif3_clk", 5177 "scif3_data_b", 5178 "scif3_clk_b", 5179 "scif3_data_c", 5180 "scif3_data_d", 5181 }; 5182 static const char * const scif4_groups[] = { 5183 "scif4_data", 5184 "scif4_data_b", 5185 "scif4_data_c", 5186 }; 5187 static const char * const scif5_groups[] = { 5188 "scif5_data", 5189 "scif5_data_b", 5190 }; 5191 static const char * const scifa0_groups[] = { 5192 "scifa0_data", 5193 "scifa0_data_b", 5194 }; 5195 static const char * const scifa1_groups[] = { 5196 "scifa1_data", 5197 "scifa1_clk", 5198 "scifa1_data_b", 5199 "scifa1_clk_b", 5200 "scifa1_data_c", 5201 }; 5202 static const char * const scifa2_groups[] = { 5203 "scifa2_data", 5204 "scifa2_clk", 5205 "scifa2_data_b", 5206 }; 5207 static const char * const scifa3_groups[] = { 5208 "scifa3_data", 5209 "scifa3_clk", 5210 "scifa3_data_b", 5211 "scifa3_clk_b", 5212 "scifa3_data_c", 5213 "scifa3_clk_c", 5214 }; 5215 static const char * const scifa4_groups[] = { 5216 "scifa4_data", 5217 "scifa4_data_b", 5218 "scifa4_data_c", 5219 }; 5220 static const char * const scifa5_groups[] = { 5221 "scifa5_data", 5222 "scifa5_data_b", 5223 "scifa5_data_c", 5224 }; 5225 static const char * const scifb0_groups[] = { 5226 "scifb0_data", 5227 "scifb0_clk", 5228 "scifb0_ctrl", 5229 "scifb0_data_b", 5230 "scifb0_clk_b", 5231 "scifb0_ctrl_b", 5232 "scifb0_data_c", 5233 "scifb0_clk_c", 5234 "scifb0_data_d", 5235 "scifb0_clk_d", 5236 }; 5237 static const char * const scifb1_groups[] = { 5238 "scifb1_data", 5239 "scifb1_clk", 5240 "scifb1_ctrl", 5241 "scifb1_data_b", 5242 "scifb1_clk_b", 5243 "scifb1_data_c", 5244 "scifb1_clk_c", 5245 "scifb1_data_d", 5246 }; 5247 static const char * const scifb2_groups[] = { 5248 "scifb2_data", 5249 "scifb2_clk", 5250 "scifb2_ctrl", 5251 "scifb2_data_b", 5252 "scifb2_clk_b", 5253 "scifb2_ctrl_b", 5254 "scifb2_data_c", 5255 "scifb2_clk_c", 5256 "scifb2_data_d", 5257 }; 5258 5259 static const char * const scif_clk_groups[] = { 5260 "scif_clk", 5261 "scif_clk_b", 5262 }; 5263 5264 static const char * const sdhi0_groups[] = { 5265 "sdhi0_data1", 5266 "sdhi0_data4", 5267 "sdhi0_ctrl", 5268 "sdhi0_cd", 5269 "sdhi0_wp", 5270 }; 5271 5272 static const char * const sdhi1_groups[] = { 5273 "sdhi1_data1", 5274 "sdhi1_data4", 5275 "sdhi1_ctrl", 5276 "sdhi1_cd", 5277 "sdhi1_wp", 5278 }; 5279 5280 static const char * const sdhi2_groups[] = { 5281 "sdhi2_data1", 5282 "sdhi2_data4", 5283 "sdhi2_ctrl", 5284 "sdhi2_cd", 5285 "sdhi2_wp", 5286 }; 5287 5288 static const char * const ssi_groups[] = { 5289 "ssi0_data", 5290 "ssi0_data_b", 5291 "ssi0129_ctrl", 5292 "ssi0129_ctrl_b", 5293 "ssi1_data", 5294 "ssi1_data_b", 5295 "ssi1_ctrl", 5296 "ssi1_ctrl_b", 5297 "ssi2_data", 5298 "ssi2_ctrl", 5299 "ssi3_data", 5300 "ssi34_ctrl", 5301 "ssi4_data", 5302 "ssi4_ctrl", 5303 "ssi5_data", 5304 "ssi5_ctrl", 5305 "ssi6_data", 5306 "ssi6_ctrl", 5307 "ssi7_data", 5308 "ssi7_data_b", 5309 "ssi78_ctrl", 5310 "ssi78_ctrl_b", 5311 "ssi8_data", 5312 "ssi8_data_b", 5313 "ssi9_data", 5314 "ssi9_data_b", 5315 "ssi9_ctrl", 5316 "ssi9_ctrl_b", 5317 }; 5318 5319 static const char * const tpu_groups[] = { 5320 "tpu_to0", 5321 "tpu_to1", 5322 "tpu_to2", 5323 "tpu_to3", 5324 }; 5325 5326 static const char * const usb0_groups[] = { 5327 "usb0", 5328 }; 5329 static const char * const usb1_groups[] = { 5330 "usb1", 5331 }; 5332 5333 static const char * const vin0_groups[] = { 5334 "vin0_data24", 5335 "vin0_data20", 5336 "vin0_data18", 5337 "vin0_data16", 5338 "vin0_data12", 5339 "vin0_data10", 5340 "vin0_data8", 5341 "vin0_sync", 5342 "vin0_field", 5343 "vin0_clkenb", 5344 "vin0_clk", 5345 }; 5346 5347 static const char * const vin1_groups[] = { 5348 "vin1_data8", 5349 "vin1_sync", 5350 "vin1_field", 5351 "vin1_clkenb", 5352 "vin1_clk", 5353 "vin1_data24_b", 5354 "vin1_data20_b", 5355 "vin1_data18_b", 5356 "vin1_data16_b", 5357 "vin1_data12_b", 5358 "vin1_data10_b", 5359 "vin1_data8_b", 5360 "vin1_sync_b", 5361 "vin1_field_b", 5362 "vin1_clkenb_b", 5363 "vin1_clk_b", 5364 }; 5365 5366 static const char * const vin2_groups[] = { 5367 "vin2_data8", 5368 "vin2_sync", 5369 "vin2_field", 5370 "vin2_clkenb", 5371 "vin2_clk", 5372 }; 5373 5374 static const struct { 5375 struct sh_pfc_function common[58]; 5376 #if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793) 5377 struct sh_pfc_function automotive[2]; 5378 #endif 5379 } pinmux_functions = { 5380 .common = { 5381 SH_PFC_FUNCTION(audio_clk), 5382 SH_PFC_FUNCTION(avb), 5383 SH_PFC_FUNCTION(can0), 5384 SH_PFC_FUNCTION(can1), 5385 SH_PFC_FUNCTION(can_clk), 5386 SH_PFC_FUNCTION(du), 5387 SH_PFC_FUNCTION(du0), 5388 SH_PFC_FUNCTION(du1), 5389 SH_PFC_FUNCTION(eth), 5390 SH_PFC_FUNCTION(hscif0), 5391 SH_PFC_FUNCTION(hscif1), 5392 SH_PFC_FUNCTION(hscif2), 5393 SH_PFC_FUNCTION(i2c0), 5394 SH_PFC_FUNCTION(i2c1), 5395 SH_PFC_FUNCTION(i2c2), 5396 SH_PFC_FUNCTION(i2c3), 5397 SH_PFC_FUNCTION(i2c4), 5398 SH_PFC_FUNCTION(i2c7), 5399 SH_PFC_FUNCTION(i2c8), 5400 SH_PFC_FUNCTION(intc), 5401 SH_PFC_FUNCTION(mmc), 5402 SH_PFC_FUNCTION(msiof0), 5403 SH_PFC_FUNCTION(msiof1), 5404 SH_PFC_FUNCTION(msiof2), 5405 SH_PFC_FUNCTION(pwm0), 5406 SH_PFC_FUNCTION(pwm1), 5407 SH_PFC_FUNCTION(pwm2), 5408 SH_PFC_FUNCTION(pwm3), 5409 SH_PFC_FUNCTION(pwm4), 5410 SH_PFC_FUNCTION(pwm5), 5411 SH_PFC_FUNCTION(pwm6), 5412 SH_PFC_FUNCTION(qspi), 5413 SH_PFC_FUNCTION(scif0), 5414 SH_PFC_FUNCTION(scif1), 5415 SH_PFC_FUNCTION(scif2), 5416 SH_PFC_FUNCTION(scif3), 5417 SH_PFC_FUNCTION(scif4), 5418 SH_PFC_FUNCTION(scif5), 5419 SH_PFC_FUNCTION(scifa0), 5420 SH_PFC_FUNCTION(scifa1), 5421 SH_PFC_FUNCTION(scifa2), 5422 SH_PFC_FUNCTION(scifa3), 5423 SH_PFC_FUNCTION(scifa4), 5424 SH_PFC_FUNCTION(scifa5), 5425 SH_PFC_FUNCTION(scifb0), 5426 SH_PFC_FUNCTION(scifb1), 5427 SH_PFC_FUNCTION(scifb2), 5428 SH_PFC_FUNCTION(scif_clk), 5429 SH_PFC_FUNCTION(sdhi0), 5430 SH_PFC_FUNCTION(sdhi1), 5431 SH_PFC_FUNCTION(sdhi2), 5432 SH_PFC_FUNCTION(ssi), 5433 SH_PFC_FUNCTION(tpu), 5434 SH_PFC_FUNCTION(usb0), 5435 SH_PFC_FUNCTION(usb1), 5436 SH_PFC_FUNCTION(vin0), 5437 SH_PFC_FUNCTION(vin1), 5438 SH_PFC_FUNCTION(vin2), 5439 }, 5440 #if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793) 5441 .automotive = { 5442 SH_PFC_FUNCTION(adi), 5443 SH_PFC_FUNCTION(mlb), 5444 } 5445 #endif /* CONFIG_PINCTRL_PFC_R8A7791 || CONFIG_PINCTRL_PFC_R8A7793 */ 5446 }; 5447 5448 static const struct pinmux_cfg_reg pinmux_config_regs[] = { 5449 { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1, GROUP( 5450 GP_0_31_FN, FN_IP1_22_20, 5451 GP_0_30_FN, FN_IP1_19_17, 5452 GP_0_29_FN, FN_IP1_16_14, 5453 GP_0_28_FN, FN_IP1_13_11, 5454 GP_0_27_FN, FN_IP1_10_8, 5455 GP_0_26_FN, FN_IP1_7_6, 5456 GP_0_25_FN, FN_IP1_5_4, 5457 GP_0_24_FN, FN_IP1_3_2, 5458 GP_0_23_FN, FN_IP1_1_0, 5459 GP_0_22_FN, FN_IP0_30_29, 5460 GP_0_21_FN, FN_IP0_28_27, 5461 GP_0_20_FN, FN_IP0_26_25, 5462 GP_0_19_FN, FN_IP0_24_23, 5463 GP_0_18_FN, FN_IP0_22_21, 5464 GP_0_17_FN, FN_IP0_20_19, 5465 GP_0_16_FN, FN_IP0_18_16, 5466 GP_0_15_FN, FN_IP0_15, 5467 GP_0_14_FN, FN_IP0_14, 5468 GP_0_13_FN, FN_IP0_13, 5469 GP_0_12_FN, FN_IP0_12, 5470 GP_0_11_FN, FN_IP0_11, 5471 GP_0_10_FN, FN_IP0_10, 5472 GP_0_9_FN, FN_IP0_9, 5473 GP_0_8_FN, FN_IP0_8, 5474 GP_0_7_FN, FN_IP0_7, 5475 GP_0_6_FN, FN_IP0_6, 5476 GP_0_5_FN, FN_IP0_5, 5477 GP_0_4_FN, FN_IP0_4, 5478 GP_0_3_FN, FN_IP0_3, 5479 GP_0_2_FN, FN_IP0_2, 5480 GP_0_1_FN, FN_IP0_1, 5481 GP_0_0_FN, FN_IP0_0, )) 5482 }, 5483 { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1, GROUP( 5484 0, 0, 5485 0, 0, 5486 0, 0, 5487 0, 0, 5488 0, 0, 5489 0, 0, 5490 GP_1_25_FN, FN_IP3_21_20, 5491 GP_1_24_FN, FN_IP3_19_18, 5492 GP_1_23_FN, FN_IP3_17_16, 5493 GP_1_22_FN, FN_IP3_15_14, 5494 GP_1_21_FN, FN_IP3_13_12, 5495 GP_1_20_FN, FN_IP3_11_9, 5496 GP_1_19_FN, FN_RD_N, 5497 GP_1_18_FN, FN_IP3_8_6, 5498 GP_1_17_FN, FN_IP3_5_3, 5499 GP_1_16_FN, FN_IP3_2_0, 5500 GP_1_15_FN, FN_IP2_29_27, 5501 GP_1_14_FN, FN_IP2_26_25, 5502 GP_1_13_FN, FN_IP2_24_23, 5503 GP_1_12_FN, FN_EX_CS0_N, 5504 GP_1_11_FN, FN_IP2_22_21, 5505 GP_1_10_FN, FN_IP2_20_19, 5506 GP_1_9_FN, FN_IP2_18_16, 5507 GP_1_8_FN, FN_IP2_15_13, 5508 GP_1_7_FN, FN_IP2_12_10, 5509 GP_1_6_FN, FN_IP2_9_7, 5510 GP_1_5_FN, FN_IP2_6_5, 5511 GP_1_4_FN, FN_IP2_4_3, 5512 GP_1_3_FN, FN_IP2_2_0, 5513 GP_1_2_FN, FN_IP1_31_29, 5514 GP_1_1_FN, FN_IP1_28_26, 5515 GP_1_0_FN, FN_IP1_25_23, )) 5516 }, 5517 { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1, GROUP( 5518 GP_2_31_FN, FN_IP6_7_6, 5519 GP_2_30_FN, FN_IP6_5_3, 5520 GP_2_29_FN, FN_IP6_2_0, 5521 GP_2_28_FN, FN_AUDIO_CLKA, 5522 GP_2_27_FN, FN_IP5_31_29, 5523 GP_2_26_FN, FN_IP5_28_26, 5524 GP_2_25_FN, FN_IP5_25_24, 5525 GP_2_24_FN, FN_IP5_23_22, 5526 GP_2_23_FN, FN_IP5_21_20, 5527 GP_2_22_FN, FN_IP5_19_17, 5528 GP_2_21_FN, FN_IP5_16_15, 5529 GP_2_20_FN, FN_IP5_14_12, 5530 GP_2_19_FN, FN_IP5_11_9, 5531 GP_2_18_FN, FN_IP5_8_6, 5532 GP_2_17_FN, FN_IP5_5_3, 5533 GP_2_16_FN, FN_IP5_2_0, 5534 GP_2_15_FN, FN_IP4_30_28, 5535 GP_2_14_FN, FN_IP4_27_26, 5536 GP_2_13_FN, FN_IP4_25_24, 5537 GP_2_12_FN, FN_IP4_23_22, 5538 GP_2_11_FN, FN_IP4_21, 5539 GP_2_10_FN, FN_IP4_20, 5540 GP_2_9_FN, FN_IP4_19, 5541 GP_2_8_FN, FN_IP4_18_16, 5542 GP_2_7_FN, FN_IP4_15_13, 5543 GP_2_6_FN, FN_IP4_12_10, 5544 GP_2_5_FN, FN_IP4_9_8, 5545 GP_2_4_FN, FN_IP4_7_5, 5546 GP_2_3_FN, FN_IP4_4_2, 5547 GP_2_2_FN, FN_IP4_1_0, 5548 GP_2_1_FN, FN_IP3_30_28, 5549 GP_2_0_FN, FN_IP3_27_25 )) 5550 }, 5551 { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1, GROUP( 5552 GP_3_31_FN, FN_IP9_18_17, 5553 GP_3_30_FN, FN_IP9_16, 5554 GP_3_29_FN, FN_IP9_15_13, 5555 GP_3_28_FN, FN_IP9_12, 5556 GP_3_27_FN, FN_IP9_11, 5557 GP_3_26_FN, FN_IP9_10_8, 5558 GP_3_25_FN, FN_IP9_7, 5559 GP_3_24_FN, FN_IP9_6, 5560 GP_3_23_FN, FN_IP9_5_3, 5561 GP_3_22_FN, FN_IP9_2_0, 5562 GP_3_21_FN, FN_IP8_30_28, 5563 GP_3_20_FN, FN_IP8_27_26, 5564 GP_3_19_FN, FN_IP8_25_24, 5565 GP_3_18_FN, FN_IP8_23_21, 5566 GP_3_17_FN, FN_IP8_20_18, 5567 GP_3_16_FN, FN_IP8_17_15, 5568 GP_3_15_FN, FN_IP8_14_12, 5569 GP_3_14_FN, FN_IP8_11_9, 5570 GP_3_13_FN, FN_IP8_8_6, 5571 GP_3_12_FN, FN_IP8_5_3, 5572 GP_3_11_FN, FN_IP8_2_0, 5573 GP_3_10_FN, FN_IP7_29_27, 5574 GP_3_9_FN, FN_IP7_26_24, 5575 GP_3_8_FN, FN_IP7_23_21, 5576 GP_3_7_FN, FN_IP7_20_19, 5577 GP_3_6_FN, FN_IP7_18_17, 5578 GP_3_5_FN, FN_IP7_16_15, 5579 GP_3_4_FN, FN_IP7_14_13, 5580 GP_3_3_FN, FN_IP7_12_11, 5581 GP_3_2_FN, FN_IP7_10_9, 5582 GP_3_1_FN, FN_IP7_8_6, 5583 GP_3_0_FN, FN_IP7_5_3 )) 5584 }, 5585 { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1, GROUP( 5586 GP_4_31_FN, FN_IP15_5_4, 5587 GP_4_30_FN, FN_IP15_3_2, 5588 GP_4_29_FN, FN_IP15_1_0, 5589 GP_4_28_FN, FN_IP11_8_6, 5590 GP_4_27_FN, FN_IP11_5_3, 5591 GP_4_26_FN, FN_IP11_2_0, 5592 GP_4_25_FN, FN_IP10_31_29, 5593 GP_4_24_FN, FN_IP10_28_27, 5594 GP_4_23_FN, FN_IP10_26_25, 5595 GP_4_22_FN, FN_IP10_24_22, 5596 GP_4_21_FN, FN_IP10_21_19, 5597 GP_4_20_FN, FN_IP10_18_17, 5598 GP_4_19_FN, FN_IP10_16_15, 5599 GP_4_18_FN, FN_IP10_14_12, 5600 GP_4_17_FN, FN_IP10_11_9, 5601 GP_4_16_FN, FN_IP10_8_6, 5602 GP_4_15_FN, FN_IP10_5_3, 5603 GP_4_14_FN, FN_IP10_2_0, 5604 GP_4_13_FN, FN_IP9_31_29, 5605 GP_4_12_FN, FN_VI0_DATA7_VI0_B7, 5606 GP_4_11_FN, FN_VI0_DATA6_VI0_B6, 5607 GP_4_10_FN, FN_VI0_DATA5_VI0_B5, 5608 GP_4_9_FN, FN_VI0_DATA4_VI0_B4, 5609 GP_4_8_FN, FN_IP9_28_27, 5610 GP_4_7_FN, FN_VI0_DATA2_VI0_B2, 5611 GP_4_6_FN, FN_VI0_DATA1_VI0_B1, 5612 GP_4_5_FN, FN_VI0_DATA0_VI0_B0, 5613 GP_4_4_FN, FN_IP9_26_25, 5614 GP_4_3_FN, FN_IP9_24_23, 5615 GP_4_2_FN, FN_IP9_22_21, 5616 GP_4_1_FN, FN_IP9_20_19, 5617 GP_4_0_FN, FN_VI0_CLK )) 5618 }, 5619 { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1, GROUP( 5620 GP_5_31_FN, FN_IP3_24_22, 5621 GP_5_30_FN, FN_IP13_9_7, 5622 GP_5_29_FN, FN_IP13_6_5, 5623 GP_5_28_FN, FN_IP13_4_3, 5624 GP_5_27_FN, FN_IP13_2_0, 5625 GP_5_26_FN, FN_IP12_29_27, 5626 GP_5_25_FN, FN_IP12_26_24, 5627 GP_5_24_FN, FN_IP12_23_22, 5628 GP_5_23_FN, FN_IP12_21_20, 5629 GP_5_22_FN, FN_IP12_19_18, 5630 GP_5_21_FN, FN_IP12_17_16, 5631 GP_5_20_FN, FN_IP12_15_13, 5632 GP_5_19_FN, FN_IP12_12_10, 5633 GP_5_18_FN, FN_IP12_9_7, 5634 GP_5_17_FN, FN_IP12_6_4, 5635 GP_5_16_FN, FN_IP12_3_2, 5636 GP_5_15_FN, FN_IP12_1_0, 5637 GP_5_14_FN, FN_IP11_31_30, 5638 GP_5_13_FN, FN_IP11_29_28, 5639 GP_5_12_FN, FN_IP11_27, 5640 GP_5_11_FN, FN_IP11_26, 5641 GP_5_10_FN, FN_IP11_25, 5642 GP_5_9_FN, FN_IP11_24, 5643 GP_5_8_FN, FN_IP11_23, 5644 GP_5_7_FN, FN_IP11_22, 5645 GP_5_6_FN, FN_IP11_21, 5646 GP_5_5_FN, FN_IP11_20, 5647 GP_5_4_FN, FN_IP11_19, 5648 GP_5_3_FN, FN_IP11_18_17, 5649 GP_5_2_FN, FN_IP11_16_15, 5650 GP_5_1_FN, FN_IP11_14_12, 5651 GP_5_0_FN, FN_IP11_11_9 )) 5652 }, 5653 { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1, GROUP( 5654 GP_6_31_FN, FN_DU0_DOTCLKIN, 5655 GP_6_30_FN, FN_USB1_OVC, 5656 GP_6_29_FN, FN_IP14_31_29, 5657 GP_6_28_FN, FN_IP14_28_26, 5658 GP_6_27_FN, FN_IP14_25_23, 5659 GP_6_26_FN, FN_IP14_22_20, 5660 GP_6_25_FN, FN_IP14_19_17, 5661 GP_6_24_FN, FN_IP14_16_14, 5662 GP_6_23_FN, FN_IP14_13_11, 5663 GP_6_22_FN, FN_IP14_10_8, 5664 GP_6_21_FN, FN_IP14_7, 5665 GP_6_20_FN, FN_IP14_6, 5666 GP_6_19_FN, FN_IP14_5, 5667 GP_6_18_FN, FN_IP14_4, 5668 GP_6_17_FN, FN_IP14_3, 5669 GP_6_16_FN, FN_IP14_2, 5670 GP_6_15_FN, FN_IP14_1_0, 5671 GP_6_14_FN, FN_IP13_30_28, 5672 GP_6_13_FN, FN_IP13_27, 5673 GP_6_12_FN, FN_IP13_26, 5674 GP_6_11_FN, FN_IP13_25, 5675 GP_6_10_FN, FN_IP13_24_23, 5676 GP_6_9_FN, FN_IP13_22, 5677 GP_6_8_FN, FN_SD1_CLK, 5678 GP_6_7_FN, FN_IP13_21_19, 5679 GP_6_6_FN, FN_IP13_18_16, 5680 GP_6_5_FN, FN_IP13_15, 5681 GP_6_4_FN, FN_IP13_14, 5682 GP_6_3_FN, FN_IP13_13, 5683 GP_6_2_FN, FN_IP13_12, 5684 GP_6_1_FN, FN_IP13_11, 5685 GP_6_0_FN, FN_IP13_10 )) 5686 }, 5687 { PINMUX_CFG_REG("GPSR7", 0xE6060074, 32, 1, GROUP( 5688 0, 0, 5689 0, 0, 5690 0, 0, 5691 0, 0, 5692 0, 0, 5693 0, 0, 5694 GP_7_25_FN, FN_USB1_PWEN, 5695 GP_7_24_FN, FN_USB0_OVC, 5696 GP_7_23_FN, FN_USB0_PWEN, 5697 GP_7_22_FN, FN_IP15_14_12, 5698 GP_7_21_FN, FN_IP15_11_9, 5699 GP_7_20_FN, FN_IP15_8_6, 5700 GP_7_19_FN, FN_IP7_2_0, 5701 GP_7_18_FN, FN_IP6_29_27, 5702 GP_7_17_FN, FN_IP6_26_24, 5703 GP_7_16_FN, FN_IP6_23_21, 5704 GP_7_15_FN, FN_IP6_20_19, 5705 GP_7_14_FN, FN_IP6_18_16, 5706 GP_7_13_FN, FN_IP6_15_14, 5707 GP_7_12_FN, FN_IP6_13_12, 5708 GP_7_11_FN, FN_IP6_11_10, 5709 GP_7_10_FN, FN_IP6_9_8, 5710 GP_7_9_FN, FN_IP16_11_10, 5711 GP_7_8_FN, FN_IP16_9_8, 5712 GP_7_7_FN, FN_IP16_7_6, 5713 GP_7_6_FN, FN_IP16_5_3, 5714 GP_7_5_FN, FN_IP16_2_0, 5715 GP_7_4_FN, FN_IP15_29_27, 5716 GP_7_3_FN, FN_IP15_26_24, 5717 GP_7_2_FN, FN_IP15_23_21, 5718 GP_7_1_FN, FN_IP15_20_18, 5719 GP_7_0_FN, FN_IP15_17_15 )) 5720 }, 5721 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32, 5722 GROUP(1, 2, 2, 2, 2, 2, 2, 3, 1, 1, 1, 1, 5723 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), 5724 GROUP( 5725 /* IP0_31 [1] */ 5726 0, 0, 5727 /* IP0_30_29 [2] */ 5728 FN_A6, FN_MSIOF1_SCK, 5729 0, 0, 5730 /* IP0_28_27 [2] */ 5731 FN_A5, FN_MSIOF0_RXD_B, 5732 0, 0, 5733 /* IP0_26_25 [2] */ 5734 FN_A4, FN_MSIOF0_TXD_B, 5735 0, 0, 5736 /* IP0_24_23 [2] */ 5737 FN_A3, FN_MSIOF0_SS2_B, 5738 0, 0, 5739 /* IP0_22_21 [2] */ 5740 FN_A2, FN_MSIOF0_SS1_B, 5741 0, 0, 5742 /* IP0_20_19 [2] */ 5743 FN_A1, FN_MSIOF0_SYNC_B, 5744 0, 0, 5745 /* IP0_18_16 [3] */ 5746 FN_A0, FN_ATAWR0_N_C, FN_MSIOF0_SCK_B, FN_I2C0_SCL_C, FN_PWM2_B, 5747 0, 0, 0, 5748 /* IP0_15 [1] */ 5749 FN_D15, 0, 5750 /* IP0_14 [1] */ 5751 FN_D14, 0, 5752 /* IP0_13 [1] */ 5753 FN_D13, 0, 5754 /* IP0_12 [1] */ 5755 FN_D12, 0, 5756 /* IP0_11 [1] */ 5757 FN_D11, 0, 5758 /* IP0_10 [1] */ 5759 FN_D10, 0, 5760 /* IP0_9 [1] */ 5761 FN_D9, 0, 5762 /* IP0_8 [1] */ 5763 FN_D8, 0, 5764 /* IP0_7 [1] */ 5765 FN_D7, 0, 5766 /* IP0_6 [1] */ 5767 FN_D6, 0, 5768 /* IP0_5 [1] */ 5769 FN_D5, 0, 5770 /* IP0_4 [1] */ 5771 FN_D4, 0, 5772 /* IP0_3 [1] */ 5773 FN_D3, 0, 5774 /* IP0_2 [1] */ 5775 FN_D2, 0, 5776 /* IP0_1 [1] */ 5777 FN_D1, 0, 5778 /* IP0_0 [1] */ 5779 FN_D0, 0, )) 5780 }, 5781 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32, 5782 GROUP(3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2), 5783 GROUP( 5784 /* IP1_31_29 [3] */ 5785 FN_A18, FN_DREQ1, FN_SCIFA1_RXD_C, 0, FN_SCIFB1_RXD_C, 5786 0, 0, 0, 5787 /* IP1_28_26 [3] */ 5788 FN_A17, FN_DACK2_B, 0, FN_I2C0_SDA_C, 5789 0, 0, 0, 0, 5790 /* IP1_25_23 [3] */ 5791 FN_A16, FN_DREQ2_B, FN_FMCLK_C, 0, FN_SCIFA1_SCK_B, 5792 0, 0, 0, 5793 /* IP1_22_20 [3] */ 5794 FN_A15, FN_BPFCLK_C, 5795 0, 0, 0, 0, 0, 0, 5796 /* IP1_19_17 [3] */ 5797 FN_A14, FN_ATADIR0_N_C, FN_FMIN, FN_FMIN_C, FN_MSIOF1_SYNC_D, 5798 0, 0, 0, 5799 /* IP1_16_14 [3] */ 5800 FN_A13, FN_ATAG0_N_C, FN_BPFCLK, FN_MSIOF1_SS1_D, 5801 0, 0, 0, 0, 5802 /* IP1_13_11 [3] */ 5803 FN_A12, FN_FMCLK, FN_I2C3_SDA_D, FN_MSIOF1_SCK_D, 5804 0, 0, 0, 0, 5805 /* IP1_10_8 [3] */ 5806 FN_A11, FN_MSIOF1_RXD, FN_I2C3_SCL_D, FN_MSIOF1_RXD_D, 5807 0, 0, 0, 0, 5808 /* IP1_7_6 [2] */ 5809 FN_A10, FN_MSIOF1_TXD, 0, FN_MSIOF1_TXD_D, 5810 /* IP1_5_4 [2] */ 5811 FN_A9, FN_MSIOF1_SS2, FN_I2C0_SDA, 0, 5812 /* IP1_3_2 [2] */ 5813 FN_A8, FN_MSIOF1_SS1, FN_I2C0_SCL, 0, 5814 /* IP1_1_0 [2] */ 5815 FN_A7, FN_MSIOF1_SYNC, 5816 0, 0, )) 5817 }, 5818 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32, 5819 GROUP(2, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2, 3), 5820 GROUP( 5821 /* IP2_31_30 [2] */ 5822 0, 0, 0, 0, 5823 /* IP2_29_27 [3] */ 5824 FN_EX_CS3_N, FN_ATADIR0_N, FN_MSIOF2_TXD, 5825 FN_ATAG0_N, 0, FN_EX_WAIT1, 5826 0, 0, 5827 /* IP2_26_25 [2] */ 5828 FN_EX_CS2_N, FN_ATAWR0_N, FN_MSIOF2_SYNC, 0, 5829 /* IP2_24_23 [2] */ 5830 FN_EX_CS1_N, FN_MSIOF2_SCK, 0, 0, 5831 /* IP2_22_21 [2] */ 5832 FN_CS1_N_A26, FN_ATADIR0_N_B, FN_I2C1_SDA, 0, 5833 /* IP2_20_19 [2] */ 5834 FN_CS0_N, FN_ATAG0_N_B, FN_I2C1_SCL, 0, 5835 /* IP2_18_16 [3] */ 5836 FN_A25, FN_DACK2, FN_SSL, FN_DREQ1_C, FN_RX1, FN_SCIFA1_RXD, 5837 0, 0, 5838 /* IP2_15_13 [3] */ 5839 FN_A24, FN_DREQ2, FN_IO3, FN_TX1, FN_SCIFA1_TXD, 5840 0, 0, 0, 5841 /* IP2_12_10 [3] */ 5842 FN_A23, FN_IO2, FN_BPFCLK_B, FN_RX0, FN_SCIFA0_RXD, 5843 0, 0, 0, 5844 /* IP2_9_7 [3] */ 5845 FN_A22, FN_MISO_IO1, FN_FMCLK_B, FN_TX0, FN_SCIFA0_TXD, 5846 0, 0, 0, 5847 /* IP2_6_5 [2] */ 5848 FN_A21, FN_ATAWR0_N_B, FN_MOSI_IO0, 0, 5849 /* IP2_4_3 [2] */ 5850 FN_A20, FN_SPCLK, 0, 0, 5851 /* IP2_2_0 [3] */ 5852 FN_A19, FN_DACK1, FN_SCIFA1_TXD_C, 0, 5853 FN_SCIFB1_TXD_C, 0, FN_SCIFB1_SCK_B, 0, )) 5854 }, 5855 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32, 5856 GROUP(1, 3, 3, 3, 2, 2, 2, 2, 2, 3, 3, 3, 3), 5857 GROUP( 5858 /* IP3_31 [1] */ 5859 0, 0, 5860 /* IP3_30_28 [3] */ 5861 FN_SSI_WS0129, FN_HTX0_C, FN_HTX2_C, 5862 FN_SCIFB0_TXD_C, FN_SCIFB2_TXD_C, 5863 0, 0, 0, 5864 /* IP3_27_25 [3] */ 5865 FN_SSI_SCK0129, FN_HRX0_C, FN_HRX2_C, 5866 FN_SCIFB0_RXD_C, FN_SCIFB2_RXD_C, 5867 0, 0, 0, 5868 /* IP3_24_22 [3] */ 5869 FN_SPEEDIN, 0, FN_HSCK0_C, FN_HSCK2_C, FN_SCIFB0_SCK_B, 5870 FN_SCIFB2_SCK_B, FN_DREQ2_C, FN_HTX2_D, 5871 /* IP3_21_20 [2] */ 5872 FN_DACK0, FN_DRACK0, FN_REMOCON, 0, 5873 /* IP3_19_18 [2] */ 5874 FN_DREQ0, FN_PWM3, FN_TPU_TO3, 0, 5875 /* IP3_17_16 [2] */ 5876 FN_EX_WAIT0, FN_HRTS2_N_B, FN_SCIFB0_CTS_N_B, 0, 5877 /* IP3_15_14 [2] */ 5878 FN_WE1_N, FN_ATARD0_N_B, FN_HTX2_B, FN_SCIFB0_RTS_N_B, 5879 /* IP3_13_12 [2] */ 5880 FN_WE0_N, FN_HCTS2_N_B, FN_SCIFB0_TXD_B, 0, 5881 /* IP3_11_9 [3] */ 5882 FN_RD_WR_N, FN_HRX2_B, FN_FMIN_B, FN_SCIFB0_RXD_B, FN_DREQ1_D, 5883 0, 0, 0, 5884 /* IP3_8_6 [3] */ 5885 FN_BS_N, FN_ATACS10_N, FN_MSIOF2_SS2, FN_HTX1_B, 5886 FN_SCIFB1_TXD_B, FN_PWM2, FN_TPU_TO2, 0, 5887 /* IP3_5_3 [3] */ 5888 FN_EX_CS5_N, FN_ATACS00_N, FN_MSIOF2_SS1, FN_HRX1_B, 5889 FN_SCIFB1_RXD_B, FN_PWM1, FN_TPU_TO1, 0, 5890 /* IP3_2_0 [3] */ 5891 FN_EX_CS4_N, FN_ATARD0_N, FN_MSIOF2_RXD, 0, FN_EX_WAIT2, 5892 0, 0, 0, )) 5893 }, 5894 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32, 5895 GROUP(1, 3, 2, 2, 2, 1, 1, 1, 3, 3, 3, 2, 5896 3, 3, 2), 5897 GROUP( 5898 /* IP4_31 [1] */ 5899 0, 0, 5900 /* IP4_30_28 [3] */ 5901 FN_SSI_SCK5, FN_MSIOF1_SCK_C, FN_TS_SDATA0, FN_GLO_I0, 5902 FN_MSIOF2_SYNC_D, FN_VI1_R2_B, 5903 0, 0, 5904 /* IP4_27_26 [2] */ 5905 FN_SSI_SDATA4, FN_MSIOF2_SCK_D, 0, 0, 5906 /* IP4_25_24 [2] */ 5907 FN_SSI_WS4, FN_GLO_RFON_D, 0, 0, 5908 /* IP4_23_22 [2] */ 5909 FN_SSI_SCK4, FN_GLO_SS_D, 0, 0, 5910 /* IP4_21 [1] */ 5911 FN_SSI_SDATA3, 0, 5912 /* IP4_20 [1] */ 5913 FN_SSI_WS34, 0, 5914 /* IP4_19 [1] */ 5915 FN_SSI_SCK34, 0, 5916 /* IP4_18_16 [3] */ 5917 FN_SSI_SDATA2, FN_GPS_MAG_B, FN_TX2_E, FN_HRTS1_N_E, 5918 0, 0, 0, 0, 5919 /* IP4_15_13 [3] */ 5920 FN_SSI_WS2, FN_I2C2_SDA, FN_GPS_SIGN_B, FN_RX2_E, 5921 FN_GLO_Q1_D, FN_HCTS1_N_E, 5922 0, 0, 5923 /* IP4_12_10 [3] */ 5924 FN_SSI_SCK2, FN_I2C2_SCL, FN_GPS_CLK_B, FN_GLO_Q0_D, FN_HSCK1_E, 5925 0, 0, 0, 5926 /* IP4_9_8 [2] */ 5927 FN_SSI_SDATA1, FN_I2C1_SDA_B, FN_IIC1_SDA_B, FN_MSIOF2_RXD_C, 5928 /* IP4_7_5 [3] */ 5929 FN_SSI_WS1, FN_I2C1_SCL_B, FN_IIC1_SCL_B, FN_MSIOF2_TXD_C, 5930 FN_GLO_I1_D, 0, 0, 0, 5931 /* IP4_4_2 [3] */ 5932 FN_SSI_SCK1, FN_I2C0_SDA_B, FN_IIC0_SDA_B, 5933 FN_MSIOF2_SYNC_C, FN_GLO_I0_D, 5934 0, 0, 0, 5935 /* IP4_1_0 [2] */ 5936 FN_SSI_SDATA0, FN_I2C0_SCL_B, FN_IIC0_SCL_B, FN_MSIOF2_SCK_C, 5937 )) 5938 }, 5939 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32, 5940 GROUP(3, 3, 2, 2, 2, 3, 2, 3, 3, 3, 3, 3), 5941 GROUP( 5942 /* IP5_31_29 [3] */ 5943 FN_SSI_SDATA9, FN_RX3_D, FN_CAN0_RX_D, 5944 0, 0, 0, 0, 0, 5945 /* IP5_28_26 [3] */ 5946 FN_SSI_WS9, FN_TX3_D, FN_CAN0_TX_D, FN_GLO_SDATA_D, 5947 0, 0, 0, 0, 5948 /* IP5_25_24 [2] */ 5949 FN_SSI_SCK9, FN_RX1_D, FN_GLO_SCLK_D, 0, 5950 /* IP5_23_22 [2] */ 5951 FN_SSI_SDATA8, FN_TX1_D, FN_STP_ISSYNC_0_B, 0, 5952 /* IP5_21_20 [2] */ 5953 FN_SSI_SDATA7, FN_RX0_D, FN_STP_ISEN_0_B, 0, 5954 /* IP5_19_17 [3] */ 5955 FN_SSI_WS78, FN_TX0_D, FN_STP_ISD_0_B, FN_GLO_RFON, 5956 0, 0, 0, 0, 5957 /* IP5_16_15 [2] */ 5958 FN_SSI_SCK78, FN_STP_ISCLK_0_B, FN_GLO_SS, 0, 5959 /* IP5_14_12 [3] */ 5960 FN_SSI_SDATA6, FN_STP_IVCXO27_0_B, FN_GLO_SDATA, FN_VI1_R7_B, 5961 0, 0, 0, 0, 5962 /* IP5_11_9 [3] */ 5963 FN_SSI_WS6, FN_GLO_SCLK, FN_MSIOF2_SS2_D, FN_VI1_R6_B, 5964 0, 0, 0, 0, 5965 /* IP5_8_6 [3] */ 5966 FN_SSI_SCK6, FN_MSIOF1_RXD_C, FN_TS_SPSYNC0, FN_GLO_Q1, 5967 FN_MSIOF2_RXD_D, FN_VI1_R5_B, 5968 0, 0, 5969 /* IP5_5_3 [3] */ 5970 FN_SSI_SDATA5, FN_MSIOF1_TXD_C, FN_TS_SDEN0, FN_GLO_Q0, 5971 FN_MSIOF2_SS1_D, FN_VI1_R4_B, 5972 0, 0, 5973 /* IP5_2_0 [3] */ 5974 FN_SSI_WS5, FN_MSIOF1_SYNC_C, FN_TS_SCK0, FN_GLO_I1, 5975 FN_MSIOF2_TXD_D, FN_VI1_R3_B, 5976 0, 0, )) 5977 }, 5978 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32, 5979 GROUP(2, 3, 3, 3, 2, 3, 2, 2, 2, 2, 2, 3, 3), 5980 GROUP( 5981 /* IP6_31_30 [2] */ 5982 0, 0, 0, 0, 5983 /* IP6_29_27 [3] */ 5984 FN_IRQ8, FN_HRTS1_N_C, FN_MSIOF1_RXD_B, 5985 FN_GPS_SIGN_C, FN_GPS_SIGN_D, 5986 0, 0, 0, 5987 /* IP6_26_24 [3] */ 5988 FN_IRQ7, FN_HCTS1_N_C, FN_MSIOF1_TXD_B, 5989 FN_GPS_CLK_C, FN_GPS_CLK_D, 5990 0, 0, 0, 5991 /* IP6_23_21 [3] */ 5992 FN_IRQ6, FN_HSCK1_C, FN_MSIOF1_SS2_B, 5993 FN_I2C1_SDA_E, FN_MSIOF2_SYNC_E, 5994 0, 0, 0, 5995 /* IP6_20_19 [2] */ 5996 FN_IRQ5, FN_HTX1_C, FN_I2C1_SCL_E, FN_MSIOF2_SCK_E, 5997 /* IP6_18_16 [3] */ 5998 FN_IRQ4, FN_HRX1_C, FN_I2C4_SDA_C, FN_MSIOF2_RXD_E, 5999 FN_INTC_IRQ4_N, 0, 0, 0, 6000 /* IP6_15_14 [2] */ 6001 FN_IRQ3, FN_I2C4_SCL_C, FN_MSIOF2_TXD_E, FN_INTC_IRQ3_N, 6002 /* IP6_13_12 [2] */ 6003 FN_IRQ2, FN_SCIFB1_TXD_D, FN_INTC_IRQ2_N, 0, 6004 /* IP6_11_10 [2] */ 6005 FN_IRQ1, FN_SCIFB1_SCK_C, FN_INTC_IRQ1_N, 0, 6006 /* IP6_9_8 [2] */ 6007 FN_IRQ0, FN_SCIFB1_RXD_D, FN_INTC_IRQ0_N, 0, 6008 /* IP6_7_6 [2] */ 6009 FN_AUDIO_CLKOUT, FN_MSIOF1_SS1_B, FN_TX2, FN_SCIFA2_TXD, 6010 /* IP6_5_3 [3] */ 6011 FN_AUDIO_CLKC, FN_SCIFB0_SCK_C, FN_MSIOF1_SYNC_B, FN_RX2, 6012 FN_SCIFA2_RXD, FN_FMIN_E, 6013 0, 0, 6014 /* IP6_2_0 [3] */ 6015 FN_AUDIO_CLKB, FN_STP_OPWM_0_B, FN_MSIOF1_SCK_B, 6016 FN_SCIF_CLK, FN_DVC_MUTE, FN_BPFCLK_E, 6017 0, 0, )) 6018 }, 6019 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32, 6020 GROUP(2, 3, 3, 3, 2, 2, 2, 2, 2, 2, 3, 3, 3), 6021 GROUP( 6022 /* IP7_31_30 [2] */ 6023 0, 0, 0, 0, 6024 /* IP7_29_27 [3] */ 6025 FN_DU1_DG2, FN_LCDOUT10, FN_VI1_DATA4_B, FN_SCIF1_SCK_B, 6026 FN_SCIFA1_SCK, FN_SSI_SCK78_B, 6027 0, 0, 6028 /* IP7_26_24 [3] */ 6029 FN_DU1_DG1, FN_LCDOUT9, FN_VI1_DATA3_B, FN_RX1_B, 6030 FN_SCIFA1_RXD_B, FN_MSIOF2_SS2_B, 6031 0, 0, 6032 /* IP7_23_21 [3] */ 6033 FN_DU1_DG0, FN_LCDOUT8, FN_VI1_DATA2_B, FN_TX1_B, 6034 FN_SCIFA1_TXD_B, FN_MSIOF2_SS1_B, 6035 0, 0, 6036 /* IP7_20_19 [2] */ 6037 FN_DU1_DR7, FN_LCDOUT7, FN_SSI_SDATA1_B, 0, 6038 /* IP7_18_17 [2] */ 6039 FN_DU1_DR6, FN_LCDOUT6, FN_SSI_WS1_B, 0, 6040 /* IP7_16_15 [2] */ 6041 FN_DU1_DR5, FN_LCDOUT5, FN_SSI_SCK1_B, 0, 6042 /* IP7_14_13 [2] */ 6043 FN_DU1_DR4, FN_LCDOUT4, FN_SSI_SDATA0_B, 0, 6044 /* IP7_12_11 [2] */ 6045 FN_DU1_DR3, FN_LCDOUT3, FN_SSI_WS0129_B, 0, 6046 /* IP7_10_9 [2] */ 6047 FN_DU1_DR2, FN_LCDOUT2, FN_SSI_SCK0129_B, 0, 6048 /* IP7_8_6 [3] */ 6049 FN_DU1_DR1, FN_LCDOUT1, FN_VI1_DATA1_B, FN_RX0_B, 6050 FN_SCIFA0_RXD_B, FN_MSIOF2_SYNC_B, 6051 0, 0, 6052 /* IP7_5_3 [3] */ 6053 FN_DU1_DR0, FN_LCDOUT0, FN_VI1_DATA0_B, FN_TX0_B, 6054 FN_SCIFA0_TXD_B, FN_MSIOF2_SCK_B, 6055 0, 0, 6056 /* IP7_2_0 [3] */ 6057 FN_IRQ9, FN_DU1_DOTCLKIN_B, FN_CAN_CLK_D, FN_GPS_MAG_C, 6058 FN_SCIF_CLK_B, FN_GPS_MAG_D, 6059 0, 0, )) 6060 }, 6061 { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32, 6062 GROUP(1, 3, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3), 6063 GROUP( 6064 /* IP8_31 [1] */ 6065 0, 0, 6066 /* IP8_30_28 [3] */ 6067 FN_DU1_DB5, FN_LCDOUT21, FN_TX3, FN_SCIFA3_TXD, FN_CAN1_TX, 6068 0, 0, 0, 6069 /* IP8_27_26 [2] */ 6070 FN_DU1_DB4, FN_LCDOUT20, FN_VI1_FIELD_B, FN_CAN1_RX, 6071 /* IP8_25_24 [2] */ 6072 FN_DU1_DB3, FN_LCDOUT19, FN_VI1_CLKENB_B, 0, 6073 /* IP8_23_21 [3] */ 6074 FN_DU1_DB2, FN_LCDOUT18, FN_VI1_VSYNC_N_B, FN_SCIF2_SCK_B, 6075 FN_SCIFA2_SCK, FN_SSI_SDATA9_B, 6076 0, 0, 6077 /* IP8_20_18 [3] */ 6078 FN_DU1_DB1, FN_LCDOUT17, FN_VI1_HSYNC_N_B, FN_RX2_B, 6079 FN_SCIFA2_RXD_B, FN_MSIOF2_RXD_B, 6080 0, 0, 6081 /* IP8_17_15 [3] */ 6082 FN_DU1_DB0, FN_LCDOUT16, FN_VI1_CLK_B, FN_TX2_B, 6083 FN_SCIFA2_TXD_B, FN_MSIOF2_TXD_B, 6084 0, 0, 6085 /* IP8_14_12 [3] */ 6086 FN_DU1_DG7, FN_LCDOUT15, FN_HTX0_B, 6087 FN_SCIFB2_RTS_N_B, FN_SSI_WS9_B, 6088 0, 0, 0, 6089 /* IP8_11_9 [3] */ 6090 FN_DU1_DG6, FN_LCDOUT14, FN_HRTS0_N_B, 6091 FN_SCIFB2_CTS_N_B, FN_SSI_SCK9_B, 6092 0, 0, 0, 6093 /* IP8_8_6 [3] */ 6094 FN_DU1_DG5, FN_LCDOUT13, FN_VI1_DATA7_B, FN_HCTS0_N_B, 6095 FN_SCIFB2_TXD_B, FN_SSI_SDATA8_B, 6096 0, 0, 6097 /* IP8_5_3 [3] */ 6098 FN_DU1_DG4, FN_LCDOUT12, FN_VI1_DATA6_B, FN_HRX0_B, 6099 FN_SCIFB2_RXD_B, FN_SSI_SDATA7_B, 6100 0, 0, 6101 /* IP8_2_0 [3] */ 6102 FN_DU1_DG3, FN_LCDOUT11, FN_VI1_DATA5_B, 0, FN_SSI_WS78_B, 6103 0, 0, 0, )) 6104 }, 6105 { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32, 6106 GROUP(3, 2, 2, 2, 2, 2, 2, 1, 3, 1, 1, 3, 6107 1, 1, 3, 3), 6108 GROUP( 6109 /* IP9_31_29 [3] */ 6110 FN_VI0_G0, FN_IIC1_SCL, FN_STP_IVCXO27_0_C, FN_I2C4_SCL, 6111 FN_HCTS2_N, FN_SCIFB2_CTS_N, FN_ATAWR1_N, 0, 6112 /* IP9_28_27 [2] */ 6113 FN_VI0_DATA3_VI0_B3, FN_SCIF3_SCK_B, FN_SCIFA3_SCK_B, 0, 6114 /* IP9_26_25 [2] */ 6115 FN_VI0_VSYNC_N, FN_RX5, FN_SCIFA5_RXD, FN_TS_SPSYNC0_D, 6116 /* IP9_24_23 [2] */ 6117 FN_VI0_HSYNC_N, FN_TX5, FN_SCIFA5_TXD, FN_TS_SDEN0_D, 6118 /* IP9_22_21 [2] */ 6119 FN_VI0_FIELD, FN_RX4, FN_SCIFA4_RXD, FN_TS_SCK0_D, 6120 /* IP9_20_19 [2] */ 6121 FN_VI0_CLKENB, FN_TX4, FN_SCIFA4_TXD, FN_TS_SDATA0_D, 6122 /* IP9_18_17 [2] */ 6123 FN_DU1_CDE, FN_QPOLB, FN_PWM4_B, 0, 6124 /* IP9_16 [1] */ 6125 FN_DU1_DISP, FN_QPOLA, 6126 /* IP9_15_13 [3] */ 6127 FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_QCPV_QDE, 6128 FN_CAN0_RX, FN_RX3_B, FN_I2C2_SDA_B, 6129 0, 0, 0, 6130 /* IP9_12 [1] */ 6131 FN_DU1_EXVSYNC_DU1_VSYNC, FN_QSTB_QHE, 6132 /* IP9_11 [1] */ 6133 FN_DU1_EXHSYNC_DU1_HSYNC, FN_QSTH_QHS, 6134 /* IP9_10_8 [3] */ 6135 FN_DU1_DOTCLKOUT1, FN_QSTVB_QVE, FN_CAN0_TX, 6136 FN_TX3_B, FN_I2C2_SCL_B, FN_PWM4, 6137 0, 0, 6138 /* IP9_7 [1] */ 6139 FN_DU1_DOTCLKOUT0, FN_QCLK, 6140 /* IP9_6 [1] */ 6141 FN_DU1_DOTCLKIN, FN_QSTVA_QVS, 6142 /* IP9_5_3 [3] */ 6143 FN_DU1_DB7, FN_LCDOUT23, FN_I2C3_SDA_C, 6144 FN_SCIF3_SCK, FN_SCIFA3_SCK, 6145 0, 0, 0, 6146 /* IP9_2_0 [3] */ 6147 FN_DU1_DB6, FN_LCDOUT22, FN_I2C3_SCL_C, FN_RX3, FN_SCIFA3_RXD, 6148 0, 0, 0, )) 6149 }, 6150 { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32, 6151 GROUP(3, 2, 2, 3, 3, 2, 2, 3, 3, 3, 3, 3), 6152 GROUP( 6153 /* IP10_31_29 [3] */ 6154 FN_VI0_R4, FN_VI2_DATA5, FN_GLO_SCLK_B, FN_TX0_C, FN_I2C1_SCL_D, 6155 0, 0, 0, 6156 /* IP10_28_27 [2] */ 6157 FN_VI0_R3, FN_VI2_DATA4, FN_GLO_Q1_B, FN_TS_SPSYNC0_C, 6158 /* IP10_26_25 [2] */ 6159 FN_VI0_R2, FN_VI2_DATA3, FN_GLO_Q0_B, FN_TS_SDEN0_C, 6160 /* IP10_24_22 [3] */ 6161 FN_VI0_R1, FN_VI2_DATA2, FN_GLO_I1_B, FN_TS_SCK0_C, FN_ATAG1_N, 6162 0, 0, 0, 6163 /* IP10_21_19 [3] */ 6164 FN_VI0_R0, FN_VI2_DATA1, FN_GLO_I0_B, 6165 FN_TS_SDATA0_C, FN_ATACS11_N, 6166 0, 0, 0, 6167 /* IP10_18_17 [2] */ 6168 FN_VI0_G7, FN_VI2_DATA0, FN_FMIN_D, 0, 6169 /* IP10_16_15 [2] */ 6170 FN_VI0_G6, FN_VI2_CLK, FN_BPFCLK_D, 0, 6171 /* IP10_14_12 [3] */ 6172 FN_VI0_G5, FN_VI2_FIELD, FN_STP_OPWM_0_C, FN_FMCLK_D, 6173 FN_CAN0_TX_E, FN_HTX1_D, FN_SCIFB0_TXD_D, 0, 6174 /* IP10_11_9 [3] */ 6175 FN_VI0_G4, FN_VI2_CLKENB, FN_STP_ISSYNC_0_C, 6176 FN_HTX2, FN_SCIFB2_TXD, FN_SCIFB0_SCK_D, 6177 0, 0, 6178 /* IP10_8_6 [3] */ 6179 FN_VI0_G3, FN_VI2_VSYNC_N, FN_STP_ISEN_0_C, FN_I2C3_SDA_B, 6180 FN_HRX2, FN_SCIFB2_RXD, FN_ATACS01_N, 0, 6181 /* IP10_5_3 [3] */ 6182 FN_VI0_G2, FN_VI2_HSYNC_N, FN_STP_ISD_0_C, FN_I2C3_SCL_B, 6183 FN_HSCK2, FN_SCIFB2_SCK, FN_ATARD1_N, 0, 6184 /* IP10_2_0 [3] */ 6185 FN_VI0_G1, FN_IIC1_SDA, FN_STP_ISCLK_0_C, FN_I2C4_SDA, 6186 FN_HRTS2_N, FN_SCIFB2_RTS_N, FN_ATADIR1_N, 0, )) 6187 }, 6188 { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32, 6189 GROUP(2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 6190 2, 3, 3, 3, 3, 3), 6191 GROUP( 6192 /* IP11_31_30 [2] */ 6193 FN_ETH_CRS_DV, FN_AVB_LINK, FN_I2C2_SDA_C, 0, 6194 /* IP11_29_28 [2] */ 6195 FN_ETH_MDIO, FN_AVB_RX_CLK, FN_I2C2_SCL_C, 0, 6196 /* IP11_27 [1] */ 6197 FN_VI1_DATA7, FN_AVB_MDC, 6198 /* IP11_26 [1] */ 6199 FN_VI1_DATA6, FN_AVB_MAGIC, 6200 /* IP11_25 [1] */ 6201 FN_VI1_DATA5, FN_AVB_RX_DV, 6202 /* IP11_24 [1] */ 6203 FN_VI1_DATA4, FN_AVB_MDIO, 6204 /* IP11_23 [1] */ 6205 FN_VI1_DATA3, FN_AVB_RX_ER, 6206 /* IP11_22 [1] */ 6207 FN_VI1_DATA2, FN_AVB_RXD7, 6208 /* IP11_21 [1] */ 6209 FN_VI1_DATA1, FN_AVB_RXD6, 6210 /* IP11_20 [1] */ 6211 FN_VI1_DATA0, FN_AVB_RXD5, 6212 /* IP11_19 [1] */ 6213 FN_VI1_CLK, FN_AVB_RXD4, 6214 /* IP11_18_17 [2] */ 6215 FN_VI1_FIELD, FN_AVB_RXD3, FN_TS_SPSYNC0_B, 0, 6216 /* IP11_16_15 [2] */ 6217 FN_VI1_CLKENB, FN_AVB_RXD2, FN_TS_SDEN0_B, 0, 6218 /* IP11_14_12 [3] */ 6219 FN_VI1_VSYNC_N, FN_AVB_RXD1, FN_TS_SCK0_B, 6220 FN_RX4_B, FN_SCIFA4_RXD_B, 6221 0, 0, 0, 6222 /* IP11_11_9 [3] */ 6223 FN_VI1_HSYNC_N, FN_AVB_RXD0, FN_TS_SDATA0_B, 6224 FN_TX4_B, FN_SCIFA4_TXD_B, 6225 0, 0, 0, 6226 /* IP11_8_6 [3] */ 6227 FN_VI0_R7, FN_GLO_RFON_B, FN_RX1_C, FN_CAN0_RX_E, 6228 FN_I2C4_SDA_B, FN_HRX1_D, FN_SCIFB0_RXD_D, 0, 6229 /* IP11_5_3 [3] */ 6230 FN_VI0_R6, FN_VI2_DATA7, FN_GLO_SS_B, FN_TX1_C, FN_I2C4_SCL_B, 6231 0, 0, 0, 6232 /* IP11_2_0 [3] */ 6233 FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C, 6234 FN_I2C1_SDA_D, 0, 0, 0, )) 6235 }, 6236 { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32, 6237 GROUP(2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2), 6238 GROUP( 6239 /* IP12_31_30 [2] */ 6240 0, 0, 0, 0, 6241 /* IP12_29_27 [3] */ 6242 FN_STP_ISCLK_0, FN_AVB_TX_EN, FN_SCIFB2_RXD_D, 6243 FN_ADICS_SAMP_B, FN_MSIOF0_SCK_C, 6244 0, 0, 0, 6245 /* IP12_26_24 [3] */ 6246 FN_STP_IVCXO27_0, FN_AVB_TXD7, FN_SCIFB2_TXD_D, 6247 FN_ADIDATA_B, FN_MSIOF0_SYNC_C, 6248 0, 0, 0, 6249 /* IP12_23_22 [2] */ 6250 FN_ETH_MDC, FN_AVB_TXD6, FN_IERX_C, 0, 6251 /* IP12_21_20 [2] */ 6252 FN_ETH_TXD0, FN_AVB_TXD5, FN_IECLK_C, 0, 6253 /* IP12_19_18 [2] */ 6254 FN_ETH_MAGIC, FN_AVB_TXD4, FN_IETX_C, 0, 6255 /* IP12_17_16 [2] */ 6256 FN_ETH_TX_EN, FN_AVB_TXD3, FN_TCLK1_B, FN_CAN_CLK_B, 6257 /* IP12_15_13 [3] */ 6258 FN_ETH_TXD1, FN_AVB_TXD2, FN_SCIFA3_TXD_B, 6259 FN_CAN1_TX_C, FN_MSIOF1_TXD_E, 6260 0, 0, 0, 6261 /* IP12_12_10 [3] */ 6262 FN_ETH_REFCLK, FN_AVB_TXD1, FN_SCIFA3_RXD_B, 6263 FN_CAN1_RX_C, FN_MSIOF1_SYNC_E, 6264 0, 0, 0, 6265 /* IP12_9_7 [3] */ 6266 FN_ETH_LINK, FN_AVB_TXD0, FN_CAN0_RX_C, 6267 FN_I2C2_SDA_D, FN_MSIOF1_SCK_E, 6268 0, 0, 0, 6269 /* IP12_6_4 [3] */ 6270 FN_ETH_RXD1, FN_AVB_GTXREFCLK, FN_CAN0_TX_C, 6271 FN_I2C2_SCL_D, FN_MSIOF1_RXD_E, 6272 0, 0, 0, 6273 /* IP12_3_2 [2] */ 6274 FN_ETH_RXD0, FN_AVB_PHY_INT, FN_I2C3_SDA, FN_IIC0_SDA, 6275 /* IP12_1_0 [2] */ 6276 FN_ETH_RX_ER, FN_AVB_CRS, FN_I2C3_SCL, FN_IIC0_SCL, )) 6277 }, 6278 { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32, 6279 GROUP(1, 3, 1, 1, 1, 2, 1, 3, 3, 1, 1, 1, 6280 1, 1, 1, 3, 2, 2, 3), 6281 GROUP( 6282 /* IP13_31 [1] */ 6283 0, 0, 6284 /* IP13_30_28 [3] */ 6285 FN_SD1_CD, FN_PWM0, FN_TPU_TO0, FN_I2C1_SCL_C, 6286 0, 0, 0, 0, 6287 /* IP13_27 [1] */ 6288 FN_SD1_DATA3, FN_IERX_B, 6289 /* IP13_26 [1] */ 6290 FN_SD1_DATA2, FN_IECLK_B, 6291 /* IP13_25 [1] */ 6292 FN_SD1_DATA1, FN_IETX_B, 6293 /* IP13_24_23 [2] */ 6294 FN_SD1_DATA0, FN_SPEEDIN_B, 0, 0, 6295 /* IP13_22 [1] */ 6296 FN_SD1_CMD, FN_REMOCON_B, 6297 /* IP13_21_19 [3] */ 6298 FN_SD0_WP, FN_MMC_D7_B, FN_SIM0_D_B, FN_CAN0_TX_F, 6299 FN_SCIFA5_RXD_B, FN_RX3_C, 6300 0, 0, 6301 /* IP13_18_16 [3] */ 6302 FN_SD0_CD, FN_MMC_D6_B, FN_SIM0_RST_B, FN_CAN0_RX_F, 6303 FN_SCIFA5_TXD_B, FN_TX3_C, 6304 0, 0, 6305 /* IP13_15 [1] */ 6306 FN_SD0_DATA3, FN_SSL_B, 6307 /* IP13_14 [1] */ 6308 FN_SD0_DATA2, FN_IO3_B, 6309 /* IP13_13 [1] */ 6310 FN_SD0_DATA1, FN_IO2_B, 6311 /* IP13_12 [1] */ 6312 FN_SD0_DATA0, FN_MISO_IO1_B, 6313 /* IP13_11 [1] */ 6314 FN_SD0_CMD, FN_MOSI_IO0_B, 6315 /* IP13_10 [1] */ 6316 FN_SD0_CLK, FN_SPCLK_B, 6317 /* IP13_9_7 [3] */ 6318 FN_STP_OPWM_0, FN_AVB_GTX_CLK, FN_PWM0_B, 6319 FN_ADICHS2_B, FN_MSIOF0_TXD_C, 6320 0, 0, 0, 6321 /* IP13_6_5 [2] */ 6322 FN_STP_ISSYNC_0, FN_AVB_COL, FN_ADICHS1_B, FN_MSIOF0_RXD_C, 6323 /* IP13_4_3 [2] */ 6324 FN_STP_ISEN_0, FN_AVB_TX_CLK, FN_ADICHS0_B, FN_MSIOF0_SS2_C, 6325 /* IP13_2_0 [3] */ 6326 FN_STP_ISD_0, FN_AVB_TX_ER, FN_SCIFB2_SCK_C, 6327 FN_ADICLK_B, FN_MSIOF0_SS1_C, 6328 0, 0, 0, )) 6329 }, 6330 { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32, 6331 GROUP(3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 6332 1, 1, 2), 6333 GROUP( 6334 /* IP14_31_29 [3] */ 6335 FN_MSIOF0_SS2, FN_MMC_D7, FN_ADICHS2, FN_RX0_E, 6336 FN_VI1_VSYNC_N_C, FN_IIC0_SDA_C, FN_VI1_G5_B, 0, 6337 /* IP14_28_26 [3] */ 6338 FN_MSIOF0_SS1, FN_MMC_D6, FN_ADICHS1, FN_TX0_E, 6339 FN_VI1_HSYNC_N_C, FN_IIC0_SCL_C, FN_VI1_G4_B, 0, 6340 /* IP14_25_23 [3] */ 6341 FN_MSIOF0_RXD, FN_ADICHS0, 0, FN_VI1_DATA0_C, FN_VI1_G3_B, 6342 0, 0, 0, 6343 /* IP14_22_20 [3] */ 6344 FN_MSIOF0_TXD, FN_ADICLK, 0, FN_VI1_FIELD_C, FN_VI1_G2_B, 6345 0, 0, 0, 6346 /* IP14_19_17 [3] */ 6347 FN_MSIOF0_SYNC, FN_TX2_C, FN_ADICS_SAMP, 0, 6348 FN_VI1_CLKENB_C, FN_VI1_G1_B, 6349 0, 0, 6350 /* IP14_16_14 [3] */ 6351 FN_MSIOF0_SCK, FN_RX2_C, FN_ADIDATA, 0, 6352 FN_VI1_CLK_C, FN_VI1_G0_B, 6353 0, 0, 6354 /* IP14_13_11 [3] */ 6355 FN_SD2_WP, FN_MMC_D5, FN_IIC1_SDA_C, FN_RX5_B, FN_SCIFA5_RXD_C, 6356 0, 0, 0, 6357 /* IP14_10_8 [3] */ 6358 FN_SD2_CD, FN_MMC_D4, FN_IIC1_SCL_C, FN_TX5_B, FN_SCIFA5_TXD_C, 6359 0, 0, 0, 6360 /* IP14_7 [1] */ 6361 FN_SD2_DATA3, FN_MMC_D3, 6362 /* IP14_6 [1] */ 6363 FN_SD2_DATA2, FN_MMC_D2, 6364 /* IP14_5 [1] */ 6365 FN_SD2_DATA1, FN_MMC_D1, 6366 /* IP14_4 [1] */ 6367 FN_SD2_DATA0, FN_MMC_D0, 6368 /* IP14_3 [1] */ 6369 FN_SD2_CMD, FN_MMC_CMD, 6370 /* IP14_2 [1] */ 6371 FN_SD2_CLK, FN_MMC_CLK, 6372 /* IP14_1_0 [2] */ 6373 FN_SD1_WP, FN_PWM1_B, FN_I2C1_SDA_C, 0, )) 6374 }, 6375 { PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32, 6376 GROUP(2, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2), 6377 GROUP( 6378 /* IP15_31_30 [2] */ 6379 0, 0, 0, 0, 6380 /* IP15_29_27 [3] */ 6381 FN_HTX0, FN_SCIFB0_TXD, 0, FN_GLO_SCLK_C, 6382 FN_CAN0_TX_B, FN_VI1_DATA5_C, 6383 0, 0, 6384 /* IP15_26_24 [3] */ 6385 FN_HRX0, FN_SCIFB0_RXD, 0, FN_GLO_Q1_C, 6386 FN_CAN0_RX_B, FN_VI1_DATA4_C, 6387 0, 0, 6388 /* IP15_23_21 [3] */ 6389 FN_HSCK0, FN_SCIFB0_SCK, 0, FN_GLO_Q0_C, FN_CAN_CLK, 6390 FN_TCLK2, FN_VI1_DATA3_C, 0, 6391 /* IP15_20_18 [3] */ 6392 FN_HRTS0_N, FN_SCIFB0_RTS_N, 0, FN_GLO_I1_C, FN_VI1_DATA2_C, 6393 0, 0, 0, 6394 /* IP15_17_15 [3] */ 6395 FN_HCTS0_N, FN_SCIFB0_CTS_N, 0, FN_GLO_I0_C, 6396 FN_TCLK1, FN_VI1_DATA1_C, 6397 0, 0, 6398 /* IP15_14_12 [3] */ 6399 FN_GPS_MAG, FN_RX4_C, FN_SCIFA4_RXD_C, FN_PWM6, 6400 FN_VI1_G7_B, FN_SCIFA3_SCK_C, 6401 0, 0, 6402 /* IP15_11_9 [3] */ 6403 FN_GPS_SIGN, FN_TX4_C, FN_SCIFA4_TXD_C, FN_PWM5, 6404 FN_VI1_G6_B, FN_SCIFA3_RXD_C, 6405 0, 0, 6406 /* IP15_8_6 [3] */ 6407 FN_GPS_CLK, FN_DU1_DOTCLKIN_C, FN_AUDIO_CLKB_B, 6408 FN_PWM5_B, FN_SCIFA3_TXD_C, 6409 0, 0, 0, 6410 /* IP15_5_4 [2] */ 6411 FN_SIM0_D, FN_IERX, FN_CAN1_RX_D, 0, 6412 /* IP15_3_2 [2] */ 6413 FN_SIM0_CLK, FN_IECLK, FN_CAN_CLK_C, 0, 6414 /* IP15_1_0 [2] */ 6415 FN_SIM0_RST, FN_IETX, FN_CAN1_TX_D, 0, )) 6416 }, 6417 { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32, 6418 GROUP(4, 4, 4, 4, 4, 2, 2, 2, 3, 3), 6419 GROUP( 6420 /* IP16_31_28 [4] */ 6421 0, 0, 0, 0, 0, 0, 0, 0, 6422 0, 0, 0, 0, 0, 0, 0, 0, 6423 /* IP16_27_24 [4] */ 6424 0, 0, 0, 0, 0, 0, 0, 0, 6425 0, 0, 0, 0, 0, 0, 0, 0, 6426 /* IP16_23_20 [4] */ 6427 0, 0, 0, 0, 0, 0, 0, 0, 6428 0, 0, 0, 0, 0, 0, 0, 0, 6429 /* IP16_19_16 [4] */ 6430 0, 0, 0, 0, 0, 0, 0, 0, 6431 0, 0, 0, 0, 0, 0, 0, 0, 6432 /* IP16_15_12 [4] */ 6433 0, 0, 0, 0, 0, 0, 0, 0, 6434 0, 0, 0, 0, 0, 0, 0, 0, 6435 /* IP16_11_10 [2] */ 6436 FN_HRTS1_N, FN_SCIFB1_RTS_N, FN_MLB_DAT, FN_CAN1_RX_B, 6437 /* IP16_9_8 [2] */ 6438 FN_HCTS1_N, FN_SCIFB1_CTS_N, FN_MLB_SIG, FN_CAN1_TX_B, 6439 /* IP16_7_6 [2] */ 6440 FN_HSCK1, FN_SCIFB1_SCK, FN_MLB_CLK, FN_GLO_RFON_C, 6441 /* IP16_5_3 [3] */ 6442 FN_HTX1, FN_SCIFB1_TXD, FN_VI1_R1_B, 6443 FN_GLO_SS_C, FN_VI1_DATA7_C, 6444 0, 0, 0, 6445 /* IP16_2_0 [3] */ 6446 FN_HRX1, FN_SCIFB1_RXD, FN_VI1_R0_B, 6447 FN_GLO_SDATA_C, FN_VI1_DATA6_C, 6448 0, 0, 0, )) 6449 }, 6450 { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32, 6451 GROUP(1, 2, 2, 2, 3, 2, 1, 1, 1, 1, 3, 2, 6452 2, 2, 1, 2, 2, 2), 6453 GROUP( 6454 /* RESERVED [1] */ 6455 0, 0, 6456 /* SEL_SCIF1 [2] */ 6457 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3, 6458 /* SEL_SCIFB [2] */ 6459 FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, FN_SEL_SCIFB_3, 6460 /* SEL_SCIFB2 [2] */ 6461 FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, 6462 FN_SEL_SCIFB2_2, FN_SEL_SCIFB2_3, 6463 /* SEL_SCIFB1 [3] */ 6464 FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, 6465 FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3, 6466 0, 0, 0, 0, 6467 /* SEL_SCIFA1 [2] */ 6468 FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, 0, 6469 /* SEL_SSI9 [1] */ 6470 FN_SEL_SSI9_0, FN_SEL_SSI9_1, 6471 /* SEL_SCFA [1] */ 6472 FN_SEL_SCFA_0, FN_SEL_SCFA_1, 6473 /* SEL_QSP [1] */ 6474 FN_SEL_QSP_0, FN_SEL_QSP_1, 6475 /* SEL_SSI7 [1] */ 6476 FN_SEL_SSI7_0, FN_SEL_SSI7_1, 6477 /* SEL_HSCIF1 [3] */ 6478 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2, 6479 FN_SEL_HSCIF1_3, FN_SEL_HSCIF1_4, 6480 0, 0, 0, 6481 /* RESERVED [2] */ 6482 0, 0, 0, 0, 6483 /* SEL_VI1 [2] */ 6484 FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2, 0, 6485 /* RESERVED [2] */ 6486 0, 0, 0, 0, 6487 /* SEL_TMU [1] */ 6488 FN_SEL_TMU1_0, FN_SEL_TMU1_1, 6489 /* SEL_LBS [2] */ 6490 FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_LBS_2, FN_SEL_LBS_3, 6491 /* SEL_TSIF0 [2] */ 6492 FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, 6493 /* SEL_SOF0 [2] */ 6494 FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2, 0, )) 6495 }, 6496 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32, 6497 GROUP(3, 1, 1, 3, 2, 1, 1, 2, 2, 1, 3, 2, 6498 1, 2, 2, 2, 1, 1, 1), 6499 GROUP( 6500 /* SEL_SCIF0 [3] */ 6501 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, 6502 FN_SEL_SCIF0_3, FN_SEL_SCIF0_4, 6503 0, 0, 0, 6504 /* RESERVED [1] */ 6505 0, 0, 6506 /* SEL_SCIF [1] */ 6507 FN_SEL_SCIF_0, FN_SEL_SCIF_1, 6508 /* SEL_CAN0 [3] */ 6509 FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3, 6510 FN_SEL_CAN0_4, FN_SEL_CAN0_5, 6511 0, 0, 6512 /* SEL_CAN1 [2] */ 6513 FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3, 6514 /* RESERVED [1] */ 6515 0, 0, 6516 /* SEL_SCIFA2 [1] */ 6517 FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, 6518 /* SEL_SCIF4 [2] */ 6519 FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, 0, 6520 /* RESERVED [2] */ 6521 0, 0, 0, 0, 6522 /* SEL_ADG [1] */ 6523 FN_SEL_ADG_0, FN_SEL_ADG_1, 6524 /* SEL_FM [3] */ 6525 FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, 6526 FN_SEL_FM_3, FN_SEL_FM_4, 6527 0, 0, 0, 6528 /* SEL_SCIFA5 [2] */ 6529 FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, 0, 6530 /* RESERVED [1] */ 6531 0, 0, 6532 /* SEL_GPS [2] */ 6533 FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3, 6534 /* SEL_SCIFA4 [2] */ 6535 FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2, 0, 6536 /* SEL_SCIFA3 [2] */ 6537 FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2, 0, 6538 /* SEL_SIM [1] */ 6539 FN_SEL_SIM_0, FN_SEL_SIM_1, 6540 /* RESERVED [1] */ 6541 0, 0, 6542 /* SEL_SSI8 [1] */ 6543 FN_SEL_SSI8_0, FN_SEL_SSI8_1, )) 6544 }, 6545 { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32, 6546 GROUP(2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 2, 2, 6547 3, 2, 2, 2, 1), 6548 GROUP( 6549 /* SEL_HSCIF2 [2] */ 6550 FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1, 6551 FN_SEL_HSCIF2_2, FN_SEL_HSCIF2_3, 6552 /* SEL_CANCLK [2] */ 6553 FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, 6554 FN_SEL_CANCLK_2, FN_SEL_CANCLK_3, 6555 /* SEL_IIC1 [2] */ 6556 FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, 0, 6557 /* SEL_IIC0 [2] */ 6558 FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, 0, 6559 /* SEL_I2C4 [2] */ 6560 FN_SEL_I2C4_0, FN_SEL_I2C4_1, FN_SEL_I2C4_2, 0, 6561 /* SEL_I2C3 [2] */ 6562 FN_SEL_I2C3_0, FN_SEL_I2C3_1, FN_SEL_I2C3_2, FN_SEL_I2C3_3, 6563 /* SEL_SCIF3 [2] */ 6564 FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3, 6565 /* SEL_IEB [2] */ 6566 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0, 6567 /* SEL_MMC [1] */ 6568 FN_SEL_MMC_0, FN_SEL_MMC_1, 6569 /* SEL_SCIF5 [1] */ 6570 FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, 6571 /* RESERVED [2] */ 6572 0, 0, 0, 0, 6573 /* SEL_I2C2 [2] */ 6574 FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3, 6575 /* SEL_I2C1 [3] */ 6576 FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, FN_SEL_I2C1_3, 6577 FN_SEL_I2C1_4, 6578 0, 0, 0, 6579 /* SEL_I2C0 [2] */ 6580 FN_SEL_I2C0_0, FN_SEL_I2C0_1, FN_SEL_I2C0_2, 0, 6581 /* RESERVED [2] */ 6582 0, 0, 0, 0, 6583 /* RESERVED [2] */ 6584 0, 0, 0, 0, 6585 /* RESERVED [1] */ 6586 0, 0, )) 6587 }, 6588 { PINMUX_CFG_REG_VAR("MOD_SEL4", 0xE606009C, 32, 6589 GROUP(3, 2, 2, 1, 1, 1, 1, 3, 2, 2, 3, 1, 6590 1, 1, 2, 2, 2, 2), 6591 GROUP( 6592 /* SEL_SOF1 [3] */ 6593 FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3, 6594 FN_SEL_SOF1_4, 6595 0, 0, 0, 6596 /* SEL_HSCIF0 [2] */ 6597 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, 0, 6598 /* SEL_DIS [2] */ 6599 FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2, 0, 6600 /* RESERVED [1] */ 6601 0, 0, 6602 /* SEL_RAD [1] */ 6603 FN_SEL_RAD_0, FN_SEL_RAD_1, 6604 /* SEL_RCN [1] */ 6605 FN_SEL_RCN_0, FN_SEL_RCN_1, 6606 /* SEL_RSP [1] */ 6607 FN_SEL_RSP_0, FN_SEL_RSP_1, 6608 /* SEL_SCIF2 [3] */ 6609 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, 6610 FN_SEL_SCIF2_3, FN_SEL_SCIF2_4, 6611 0, 0, 0, 6612 /* RESERVED [2] */ 6613 0, 0, 0, 0, 6614 /* RESERVED [2] */ 6615 0, 0, 0, 0, 6616 /* SEL_SOF2 [3] */ 6617 FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2, 6618 FN_SEL_SOF2_3, FN_SEL_SOF2_4, 6619 0, 0, 0, 6620 /* RESERVED [1] */ 6621 0, 0, 6622 /* SEL_SSI1 [1] */ 6623 FN_SEL_SSI1_0, FN_SEL_SSI1_1, 6624 /* SEL_SSI0 [1] */ 6625 FN_SEL_SSI0_0, FN_SEL_SSI0_1, 6626 /* SEL_SSP [2] */ 6627 FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2, 0, 6628 /* RESERVED [2] */ 6629 0, 0, 0, 0, 6630 /* RESERVED [2] */ 6631 0, 0, 0, 0, 6632 /* RESERVED [2] */ 6633 0, 0, 0, 0, )) 6634 }, 6635 { }, 6636 }; 6637 6638 static int r8a7791_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl) 6639 { 6640 if (pin < RCAR_GP_PIN(6, 0) || pin > RCAR_GP_PIN(6, 23)) 6641 return -EINVAL; 6642 6643 *pocctrl = 0xe606008c; 6644 6645 return 31 - (pin & 0x1f); 6646 } 6647 6648 static const struct sh_pfc_soc_operations r8a7791_pinmux_ops = { 6649 .pin_to_pocctrl = r8a7791_pin_to_pocctrl, 6650 }; 6651 6652 #ifdef CONFIG_PINCTRL_PFC_R8A7743 6653 const struct sh_pfc_soc_info r8a7743_pinmux_info = { 6654 .name = "r8a77430_pfc", 6655 .ops = &r8a7791_pinmux_ops, 6656 .unlock_reg = 0xe6060000, /* PMMR */ 6657 6658 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 6659 6660 .pins = pinmux_pins, 6661 .nr_pins = ARRAY_SIZE(pinmux_pins), 6662 .groups = pinmux_groups.common, 6663 .nr_groups = ARRAY_SIZE(pinmux_groups.common), 6664 .functions = pinmux_functions.common, 6665 .nr_functions = ARRAY_SIZE(pinmux_functions.common), 6666 6667 .cfg_regs = pinmux_config_regs, 6668 6669 .pinmux_data = pinmux_data, 6670 .pinmux_data_size = ARRAY_SIZE(pinmux_data), 6671 }; 6672 #endif 6673 6674 #ifdef CONFIG_PINCTRL_PFC_R8A7744 6675 const struct sh_pfc_soc_info r8a7744_pinmux_info = { 6676 .name = "r8a77440_pfc", 6677 .ops = &r8a7791_pinmux_ops, 6678 .unlock_reg = 0xe6060000, /* PMMR */ 6679 6680 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 6681 6682 .pins = pinmux_pins, 6683 .nr_pins = ARRAY_SIZE(pinmux_pins), 6684 .groups = pinmux_groups.common, 6685 .nr_groups = ARRAY_SIZE(pinmux_groups.common), 6686 .functions = pinmux_functions.common, 6687 .nr_functions = ARRAY_SIZE(pinmux_functions.common), 6688 6689 .cfg_regs = pinmux_config_regs, 6690 6691 .pinmux_data = pinmux_data, 6692 .pinmux_data_size = ARRAY_SIZE(pinmux_data), 6693 }; 6694 #endif 6695 6696 #ifdef CONFIG_PINCTRL_PFC_R8A7791 6697 const struct sh_pfc_soc_info r8a7791_pinmux_info = { 6698 .name = "r8a77910_pfc", 6699 .ops = &r8a7791_pinmux_ops, 6700 .unlock_reg = 0xe6060000, /* PMMR */ 6701 6702 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 6703 6704 .pins = pinmux_pins, 6705 .nr_pins = ARRAY_SIZE(pinmux_pins), 6706 .groups = pinmux_groups.common, 6707 .nr_groups = ARRAY_SIZE(pinmux_groups.common) + 6708 ARRAY_SIZE(pinmux_groups.automotive), 6709 .functions = pinmux_functions.common, 6710 .nr_functions = ARRAY_SIZE(pinmux_functions.common) + 6711 ARRAY_SIZE(pinmux_functions.automotive), 6712 6713 .cfg_regs = pinmux_config_regs, 6714 6715 .pinmux_data = pinmux_data, 6716 .pinmux_data_size = ARRAY_SIZE(pinmux_data), 6717 }; 6718 #endif 6719 6720 #ifdef CONFIG_PINCTRL_PFC_R8A7793 6721 const struct sh_pfc_soc_info r8a7793_pinmux_info = { 6722 .name = "r8a77930_pfc", 6723 .ops = &r8a7791_pinmux_ops, 6724 .unlock_reg = 0xe6060000, /* PMMR */ 6725 6726 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 6727 6728 .pins = pinmux_pins, 6729 .nr_pins = ARRAY_SIZE(pinmux_pins), 6730 .groups = pinmux_groups.common, 6731 .nr_groups = ARRAY_SIZE(pinmux_groups.common) + 6732 ARRAY_SIZE(pinmux_groups.automotive), 6733 .functions = pinmux_functions.common, 6734 .nr_functions = ARRAY_SIZE(pinmux_functions.common) + 6735 ARRAY_SIZE(pinmux_functions.automotive), 6736 6737 .cfg_regs = pinmux_config_regs, 6738 6739 .pinmux_data = pinmux_data, 6740 .pinmux_data_size = ARRAY_SIZE(pinmux_data), 6741 }; 6742 #endif 6743