1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * r8a7791/r8a7743 processor support - PFC hardware block. 4 * 5 * Copyright (C) 2013 Renesas Electronics Corporation 6 * Copyright (C) 2014-2017 Cogent Embedded, Inc. 7 */ 8 9 #include <linux/errno.h> 10 #include <linux/kernel.h> 11 12 #include "sh_pfc.h" 13 14 /* 15 * Pins 0-23 assigned to GPIO bank 6 can be used for SD interfaces in 16 * which case they support both 3.3V and 1.8V signalling. 17 */ 18 #define CPU_ALL_GP(fn, sfx) \ 19 PORT_GP_CFG_32(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ 20 PORT_GP_CFG_26(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ 21 PORT_GP_CFG_32(2, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ 22 PORT_GP_CFG_32(3, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ 23 PORT_GP_CFG_32(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ 24 PORT_GP_CFG_32(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ 25 PORT_GP_CFG_24(6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ 26 PORT_GP_CFG_1(6, 24, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ 27 PORT_GP_CFG_1(6, 25, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ 28 PORT_GP_CFG_1(6, 26, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ 29 PORT_GP_CFG_1(6, 27, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ 30 PORT_GP_CFG_1(6, 28, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ 31 PORT_GP_CFG_1(6, 29, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ 32 PORT_GP_CFG_1(6, 30, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ 33 PORT_GP_CFG_1(6, 31, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ 34 PORT_GP_CFG_7(7, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ 35 PORT_GP_1(7, 7, fn, sfx), \ 36 PORT_GP_1(7, 8, fn, sfx), \ 37 PORT_GP_1(7, 9, fn, sfx), \ 38 PORT_GP_CFG_1(7, 10, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ 39 PORT_GP_CFG_1(7, 11, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ 40 PORT_GP_CFG_1(7, 12, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ 41 PORT_GP_CFG_1(7, 13, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ 42 PORT_GP_CFG_1(7, 14, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ 43 PORT_GP_CFG_1(7, 15, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ 44 PORT_GP_CFG_1(7, 16, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ 45 PORT_GP_CFG_1(7, 17, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ 46 PORT_GP_CFG_1(7, 18, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ 47 PORT_GP_CFG_1(7, 19, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ 48 PORT_GP_CFG_1(7, 20, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ 49 PORT_GP_CFG_1(7, 21, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ 50 PORT_GP_CFG_1(7, 22, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ 51 PORT_GP_CFG_1(7, 23, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ 52 PORT_GP_CFG_1(7, 24, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ 53 PORT_GP_CFG_1(7, 25, fn, sfx, SH_PFC_PIN_CFG_PULL_UP) 54 55 #define CPU_ALL_NOGP(fn) \ 56 PIN_NOGP_CFG(ASEBRK_N_ACK, "ASEBRK#/ACK", fn, SH_PFC_PIN_CFG_PULL_DOWN), \ 57 PIN_NOGP_CFG(AVS1, "AVS1", fn, SH_PFC_PIN_CFG_PULL_UP), \ 58 PIN_NOGP_CFG(AVS2, "AVS2", fn, SH_PFC_PIN_CFG_PULL_UP), \ 59 PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP), \ 60 PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP), \ 61 PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP), \ 62 PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP) 63 64 enum { 65 PINMUX_RESERVED = 0, 66 67 PINMUX_DATA_BEGIN, 68 GP_ALL(DATA), 69 PINMUX_DATA_END, 70 71 PINMUX_FUNCTION_BEGIN, 72 GP_ALL(FN), 73 74 /* GPSR0 */ 75 FN_IP0_0, FN_IP0_1, FN_IP0_2, FN_IP0_3, FN_IP0_4, FN_IP0_5, 76 FN_IP0_6, FN_IP0_7, FN_IP0_8, FN_IP0_9, FN_IP0_10, FN_IP0_11, 77 FN_IP0_12, FN_IP0_13, FN_IP0_14, FN_IP0_15, FN_IP0_18_16, FN_IP0_20_19, 78 FN_IP0_22_21, FN_IP0_24_23, FN_IP0_26_25, FN_IP0_28_27, FN_IP0_30_29, 79 FN_IP1_1_0, FN_IP1_3_2, FN_IP1_5_4, FN_IP1_7_6, FN_IP1_10_8, 80 FN_IP1_13_11, FN_IP1_16_14, FN_IP1_19_17, FN_IP1_22_20, 81 82 /* GPSR1 */ 83 FN_IP1_25_23, FN_IP1_28_26, FN_IP1_31_29, FN_IP2_2_0, FN_IP2_4_3, 84 FN_IP2_6_5, FN_IP2_9_7, FN_IP2_12_10, FN_IP2_15_13, FN_IP2_18_16, 85 FN_IP2_20_19, FN_IP2_22_21, FN_EX_CS0_N, FN_IP2_24_23, FN_IP2_26_25, 86 FN_IP2_29_27, FN_IP3_2_0, FN_IP3_5_3, FN_IP3_8_6, FN_RD_N, 87 FN_IP3_11_9, FN_IP3_13_12, FN_IP3_15_14 , FN_IP3_17_16 , FN_IP3_19_18, 88 FN_IP3_21_20, 89 90 /* GPSR2 */ 91 FN_IP3_27_25, FN_IP3_30_28, FN_IP4_1_0, FN_IP4_4_2, FN_IP4_7_5, 92 FN_IP4_9_8, FN_IP4_12_10, FN_IP4_15_13, FN_IP4_18_16, FN_IP4_19, 93 FN_IP4_20, FN_IP4_21, FN_IP4_23_22, FN_IP4_25_24, FN_IP4_27_26, 94 FN_IP4_30_28, FN_IP5_2_0, FN_IP5_5_3, FN_IP5_8_6, FN_IP5_11_9, 95 FN_IP5_14_12, FN_IP5_16_15, FN_IP5_19_17, FN_IP5_21_20, FN_IP5_23_22, 96 FN_IP5_25_24, FN_IP5_28_26, FN_IP5_31_29, FN_AUDIO_CLKA, FN_IP6_2_0, 97 FN_IP6_5_3, FN_IP6_7_6, 98 99 /* GPSR3 */ 100 FN_IP7_5_3, FN_IP7_8_6, FN_IP7_10_9, FN_IP7_12_11, FN_IP7_14_13, 101 FN_IP7_16_15, FN_IP7_18_17, FN_IP7_20_19, FN_IP7_23_21, FN_IP7_26_24, 102 FN_IP7_29_27, FN_IP8_2_0, FN_IP8_5_3, FN_IP8_8_6, FN_IP8_11_9, 103 FN_IP8_14_12, FN_IP8_17_15, FN_IP8_20_18, FN_IP8_23_21, FN_IP8_25_24, 104 FN_IP8_27_26, FN_IP8_30_28, FN_IP9_2_0, FN_IP9_5_3, FN_IP9_6, FN_IP9_7, 105 FN_IP9_10_8, FN_IP9_11, FN_IP9_12, FN_IP9_15_13, FN_IP9_16, 106 FN_IP9_18_17, 107 108 /* GPSR4 */ 109 FN_VI0_CLK, FN_IP9_20_19, FN_IP9_22_21, FN_IP9_24_23, FN_IP9_26_25, 110 FN_VI0_DATA0_VI0_B0, FN_VI0_DATA1_VI0_B1, FN_VI0_DATA2_VI0_B2, 111 FN_IP9_28_27, FN_VI0_DATA4_VI0_B4, FN_VI0_DATA5_VI0_B5, 112 FN_VI0_DATA6_VI0_B6, FN_VI0_DATA7_VI0_B7, FN_IP9_31_29, FN_IP10_2_0, 113 FN_IP10_5_3, FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_16_15, 114 FN_IP10_18_17, FN_IP10_21_19, FN_IP10_24_22, FN_IP10_26_25, 115 FN_IP10_28_27, FN_IP10_31_29, FN_IP11_2_0, FN_IP11_5_3, FN_IP11_8_6, 116 FN_IP15_1_0, FN_IP15_3_2, FN_IP15_5_4, 117 118 /* GPSR5 */ 119 FN_IP11_11_9, FN_IP11_14_12, FN_IP11_16_15, FN_IP11_18_17, FN_IP11_19, 120 FN_IP11_20, FN_IP11_21, FN_IP11_22, FN_IP11_23, FN_IP11_24, 121 FN_IP11_25, FN_IP11_26, FN_IP11_27, FN_IP11_29_28, FN_IP11_31_30, 122 FN_IP12_1_0, FN_IP12_3_2, FN_IP12_6_4, FN_IP12_9_7, FN_IP12_12_10, 123 FN_IP12_15_13, FN_IP12_17_16, FN_IP12_19_18, FN_IP12_21_20, 124 FN_IP12_23_22, FN_IP12_26_24, FN_IP12_29_27, FN_IP13_2_0, FN_IP13_4_3, 125 FN_IP13_6_5, FN_IP13_9_7, FN_IP3_24_22, 126 127 /* GPSR6 */ 128 FN_IP13_10, FN_IP13_11, FN_IP13_12, FN_IP13_13, FN_IP13_14, 129 FN_IP13_15, FN_IP13_18_16, FN_IP13_21_19, 130 FN_IP13_22, FN_IP13_24_23, FN_SD1_CLK, 131 FN_IP13_25, FN_IP13_26, FN_IP13_27, FN_IP13_30_28, FN_IP14_1_0, 132 FN_IP14_2, FN_IP14_3, FN_IP14_4, FN_IP14_5, FN_IP14_6, FN_IP14_7, 133 FN_IP14_10_8, FN_IP14_13_11, FN_IP14_16_14, FN_IP14_19_17, 134 FN_IP14_22_20, FN_IP14_25_23, FN_IP14_28_26, FN_IP14_31_29, 135 FN_USB1_OVC, FN_DU0_DOTCLKIN, 136 137 /* GPSR7 */ 138 FN_IP15_17_15, FN_IP15_20_18, FN_IP15_23_21, FN_IP15_26_24, 139 FN_IP15_29_27, FN_IP16_2_0, FN_IP16_5_3, FN_IP16_7_6, FN_IP16_9_8, 140 FN_IP16_11_10, FN_IP6_9_8, FN_IP6_11_10, FN_IP6_13_12, FN_IP6_15_14, 141 FN_IP6_18_16, FN_IP6_20_19, FN_IP6_23_21, FN_IP6_26_24, FN_IP6_29_27, 142 FN_IP7_2_0, FN_IP15_8_6, FN_IP15_11_9, FN_IP15_14_12, 143 FN_USB0_PWEN, FN_USB0_OVC, FN_USB1_PWEN, 144 145 /* IPSR0 */ 146 FN_D0, FN_D1, FN_D2, FN_D3, FN_D4, FN_D5, FN_D6, FN_D7, FN_D8, 147 FN_D9, FN_D10, FN_D11, FN_D12, FN_D13, FN_D14, FN_D15, 148 FN_A0, FN_ATAWR0_N_C, FN_MSIOF0_SCK_B, FN_I2C0_SCL_C, FN_PWM2_B, 149 FN_A1, FN_MSIOF0_SYNC_B, FN_A2, FN_MSIOF0_SS1_B, 150 FN_A3, FN_MSIOF0_SS2_B, FN_A4, FN_MSIOF0_TXD_B, 151 FN_A5, FN_MSIOF0_RXD_B, FN_A6, FN_MSIOF1_SCK, 152 153 /* IPSR1 */ 154 FN_A7, FN_MSIOF1_SYNC, FN_A8, FN_MSIOF1_SS1, FN_I2C0_SCL, 155 FN_A9, FN_MSIOF1_SS2, FN_I2C0_SDA, 156 FN_A10, FN_MSIOF1_TXD, FN_MSIOF1_TXD_D, 157 FN_A11, FN_MSIOF1_RXD, FN_I2C3_SCL_D, FN_MSIOF1_RXD_D, 158 FN_A12, FN_FMCLK, FN_I2C3_SDA_D, FN_MSIOF1_SCK_D, 159 FN_A13, FN_ATAG0_N_C, FN_BPFCLK, FN_MSIOF1_SS1_D, 160 FN_A14, FN_ATADIR0_N_C, FN_FMIN, FN_FMIN_C, FN_MSIOF1_SYNC_D, 161 FN_A15, FN_BPFCLK_C, 162 FN_A16, FN_DREQ2_B, FN_FMCLK_C, FN_SCIFA1_SCK_B, 163 FN_A17, FN_DACK2_B, FN_I2C0_SDA_C, 164 FN_A18, FN_DREQ1, FN_SCIFA1_RXD_C, FN_SCIFB1_RXD_C, 165 166 /* IPSR2 */ 167 FN_A19, FN_DACK1, FN_SCIFA1_TXD_C, FN_SCIFB1_TXD_C, FN_SCIFB1_SCK_B, 168 FN_A20, FN_SPCLK, 169 FN_A21, FN_ATAWR0_N_B, FN_MOSI_IO0, 170 FN_A22, FN_MISO_IO1, FN_FMCLK_B, FN_TX0, FN_SCIFA0_TXD, 171 FN_A23, FN_IO2, FN_BPFCLK_B, FN_RX0, FN_SCIFA0_RXD, 172 FN_A24, FN_DREQ2, FN_IO3, FN_TX1, FN_SCIFA1_TXD, 173 FN_A25, FN_DACK2, FN_SSL, FN_DREQ1_C, FN_RX1, FN_SCIFA1_RXD, 174 FN_CS0_N, FN_ATAG0_N_B, FN_I2C1_SCL, 175 FN_CS1_N_A26, FN_ATADIR0_N_B, FN_I2C1_SDA, 176 FN_EX_CS1_N, FN_MSIOF2_SCK, 177 FN_EX_CS2_N, FN_ATAWR0_N, FN_MSIOF2_SYNC, 178 FN_EX_CS3_N, FN_ATADIR0_N, FN_MSIOF2_TXD, FN_ATAG0_N, FN_EX_WAIT1, 179 180 /* IPSR3 */ 181 FN_EX_CS4_N, FN_ATARD0_N, FN_MSIOF2_RXD, FN_EX_WAIT2, 182 FN_EX_CS5_N, FN_ATACS00_N, FN_MSIOF2_SS1, FN_HRX1_B, 183 FN_SCIFB1_RXD_B, FN_PWM1, FN_TPU_TO1, 184 FN_BS_N, FN_ATACS10_N, FN_MSIOF2_SS2, FN_HTX1_B, 185 FN_SCIFB1_TXD_B, FN_PWM2, FN_TPU_TO2, 186 FN_RD_WR_N, FN_HRX2_B, FN_FMIN_B, FN_SCIFB0_RXD_B, FN_DREQ1_D, 187 FN_WE0_N, FN_HCTS2_N_B, FN_SCIFB0_TXD_B, 188 FN_WE1_N, FN_ATARD0_N_B, FN_HTX2_B, FN_SCIFB0_RTS_N_B, 189 FN_EX_WAIT0, FN_HRTS2_N_B, FN_SCIFB0_CTS_N_B, 190 FN_DREQ0, FN_PWM3, FN_TPU_TO3, 191 FN_DACK0, FN_DRACK0, FN_REMOCON, 192 FN_SPEEDIN, FN_HSCK0_C, FN_HSCK2_C, FN_SCIFB0_SCK_B, 193 FN_SCIFB2_SCK_B, FN_DREQ2_C, FN_HTX2_D, 194 FN_SSI_SCK0129, FN_HRX0_C, FN_HRX2_C, FN_SCIFB0_RXD_C, FN_SCIFB2_RXD_C, 195 FN_SSI_WS0129, FN_HTX0_C, FN_HTX2_C, FN_SCIFB0_TXD_C, FN_SCIFB2_TXD_C, 196 197 /* IPSR4 */ 198 FN_SSI_SDATA0, FN_I2C0_SCL_B, FN_IIC0_SCL_B, FN_MSIOF2_SCK_C, 199 FN_SSI_SCK1, FN_I2C0_SDA_B, FN_IIC0_SDA_B, FN_MSIOF2_SYNC_C, 200 FN_GLO_I0_D, 201 FN_SSI_WS1, FN_I2C1_SCL_B, FN_IIC1_SCL_B, FN_MSIOF2_TXD_C, FN_GLO_I1_D, 202 FN_SSI_SDATA1, FN_I2C1_SDA_B, FN_IIC1_SDA_B, FN_MSIOF2_RXD_C, 203 FN_SSI_SCK2, FN_I2C2_SCL, FN_GPS_CLK_B, FN_GLO_Q0_D, FN_HSCK1_E, 204 FN_SSI_WS2, FN_I2C2_SDA, FN_GPS_SIGN_B, FN_RX2_E, 205 FN_GLO_Q1_D, FN_HCTS1_N_E, 206 FN_SSI_SDATA2, FN_GPS_MAG_B, FN_TX2_E, FN_HRTS1_N_E, 207 FN_SSI_SCK34, FN_SSI_WS34, FN_SSI_SDATA3, 208 FN_SSI_SCK4, FN_GLO_SS_D, 209 FN_SSI_WS4, FN_GLO_RFON_D, 210 FN_SSI_SDATA4, FN_MSIOF2_SCK_D, 211 FN_SSI_SCK5, FN_MSIOF1_SCK_C, FN_TS_SDATA0, FN_GLO_I0, 212 FN_MSIOF2_SYNC_D, FN_VI1_R2_B, 213 214 /* IPSR5 */ 215 FN_SSI_WS5, FN_MSIOF1_SYNC_C, FN_TS_SCK0, FN_GLO_I1, 216 FN_MSIOF2_TXD_D, FN_VI1_R3_B, 217 FN_SSI_SDATA5, FN_MSIOF1_TXD_C, FN_TS_SDEN0, FN_GLO_Q0, 218 FN_MSIOF2_SS1_D, FN_VI1_R4_B, 219 FN_SSI_SCK6, FN_MSIOF1_RXD_C, FN_TS_SPSYNC0, FN_GLO_Q1, 220 FN_MSIOF2_RXD_D, FN_VI1_R5_B, 221 FN_SSI_WS6, FN_GLO_SCLK, FN_MSIOF2_SS2_D, FN_VI1_R6_B, 222 FN_SSI_SDATA6, FN_STP_IVCXO27_0_B, FN_GLO_SDATA, FN_VI1_R7_B, 223 FN_SSI_SCK78, FN_STP_ISCLK_0_B, FN_GLO_SS, 224 FN_SSI_WS78, FN_TX0_D, FN_STP_ISD_0_B, FN_GLO_RFON, 225 FN_SSI_SDATA7, FN_RX0_D, FN_STP_ISEN_0_B, 226 FN_SSI_SDATA8, FN_TX1_D, FN_STP_ISSYNC_0_B, 227 FN_SSI_SCK9, FN_RX1_D, FN_GLO_SCLK_D, 228 FN_SSI_WS9, FN_TX3_D, FN_CAN0_TX_D, FN_GLO_SDATA_D, 229 FN_SSI_SDATA9, FN_RX3_D, FN_CAN0_RX_D, 230 231 /* IPSR6 */ 232 FN_AUDIO_CLKB, FN_STP_OPWM_0_B, FN_MSIOF1_SCK_B, 233 FN_SCIF_CLK, FN_DVC_MUTE, FN_BPFCLK_E, 234 FN_AUDIO_CLKC, FN_SCIFB0_SCK_C, FN_MSIOF1_SYNC_B, FN_RX2, 235 FN_SCIFA2_RXD, FN_FMIN_E, 236 FN_AUDIO_CLKOUT, FN_MSIOF1_SS1_B, FN_TX2, FN_SCIFA2_TXD, 237 FN_IRQ0, FN_SCIFB1_RXD_D, 238 FN_IRQ1, FN_SCIFB1_SCK_C, 239 FN_IRQ2, FN_SCIFB1_TXD_D, 240 FN_IRQ3, FN_I2C4_SCL_C, FN_MSIOF2_TXD_E, 241 FN_IRQ4, FN_HRX1_C, FN_I2C4_SDA_C, FN_MSIOF2_RXD_E, 242 FN_IRQ5, FN_HTX1_C, FN_I2C1_SCL_E, FN_MSIOF2_SCK_E, 243 FN_IRQ6, FN_HSCK1_C, FN_MSIOF1_SS2_B, FN_I2C1_SDA_E, FN_MSIOF2_SYNC_E, 244 FN_IRQ7, FN_HCTS1_N_C, FN_MSIOF1_TXD_B, FN_GPS_CLK_C, FN_GPS_CLK_D, 245 FN_IRQ8, FN_HRTS1_N_C, FN_MSIOF1_RXD_B, FN_GPS_SIGN_C, FN_GPS_SIGN_D, 246 247 /* IPSR7 */ 248 FN_IRQ9, FN_DU1_DOTCLKIN_B, FN_CAN_CLK_D, FN_GPS_MAG_C, 249 FN_SCIF_CLK_B, FN_GPS_MAG_D, 250 FN_DU1_DR0, FN_LCDOUT0, FN_VI1_DATA0_B, FN_TX0_B, 251 FN_SCIFA0_TXD_B, FN_MSIOF2_SCK_B, 252 FN_DU1_DR1, FN_LCDOUT1, FN_VI1_DATA1_B, FN_RX0_B, 253 FN_SCIFA0_RXD_B, FN_MSIOF2_SYNC_B, 254 FN_DU1_DR2, FN_LCDOUT2, FN_SSI_SCK0129_B, 255 FN_DU1_DR3, FN_LCDOUT3, FN_SSI_WS0129_B, 256 FN_DU1_DR4, FN_LCDOUT4, FN_SSI_SDATA0_B, 257 FN_DU1_DR5, FN_LCDOUT5, FN_SSI_SCK1_B, 258 FN_DU1_DR6, FN_LCDOUT6, FN_SSI_WS1_B, 259 FN_DU1_DR7, FN_LCDOUT7, FN_SSI_SDATA1_B, 260 FN_DU1_DG0, FN_LCDOUT8, FN_VI1_DATA2_B, FN_TX1_B, 261 FN_SCIFA1_TXD_B, FN_MSIOF2_SS1_B, 262 FN_DU1_DG1, FN_LCDOUT9, FN_VI1_DATA3_B, FN_RX1_B, 263 FN_SCIFA1_RXD_B, FN_MSIOF2_SS2_B, 264 FN_DU1_DG2, FN_LCDOUT10, FN_VI1_DATA4_B, FN_SCIF1_SCK_B, 265 FN_SCIFA1_SCK, FN_SSI_SCK78_B, 266 267 /* IPSR8 */ 268 FN_DU1_DG3, FN_LCDOUT11, FN_VI1_DATA5_B, FN_SSI_WS78_B, 269 FN_DU1_DG4, FN_LCDOUT12, FN_VI1_DATA6_B, FN_HRX0_B, 270 FN_SCIFB2_RXD_B, FN_SSI_SDATA7_B, 271 FN_DU1_DG5, FN_LCDOUT13, FN_VI1_DATA7_B, FN_HCTS0_N_B, 272 FN_SCIFB2_TXD_B, FN_SSI_SDATA8_B, 273 FN_DU1_DG6, FN_LCDOUT14, FN_HRTS0_N_B, 274 FN_SCIFB2_CTS_N_B, FN_SSI_SCK9_B, 275 FN_DU1_DG7, FN_LCDOUT15, FN_HTX0_B, FN_SCIFB2_RTS_N_B, FN_SSI_WS9_B, 276 FN_DU1_DB0, FN_LCDOUT16, FN_VI1_CLK_B, FN_TX2_B, 277 FN_SCIFA2_TXD_B, FN_MSIOF2_TXD_B, 278 FN_DU1_DB1, FN_LCDOUT17, FN_VI1_HSYNC_N_B, FN_RX2_B, 279 FN_SCIFA2_RXD_B, FN_MSIOF2_RXD_B, 280 FN_DU1_DB2, FN_LCDOUT18, FN_VI1_VSYNC_N_B, FN_SCIF2_SCK_B, 281 FN_SCIFA2_SCK, FN_SSI_SDATA9_B, 282 FN_DU1_DB3, FN_LCDOUT19, FN_VI1_CLKENB_B, 283 FN_DU1_DB4, FN_LCDOUT20, FN_VI1_FIELD_B, FN_CAN1_RX, 284 FN_DU1_DB5, FN_LCDOUT21, FN_TX3, FN_SCIFA3_TXD, FN_CAN1_TX, 285 286 /* IPSR9 */ 287 FN_DU1_DB6, FN_LCDOUT22, FN_I2C3_SCL_C, FN_RX3, FN_SCIFA3_RXD, 288 FN_DU1_DB7, FN_LCDOUT23, FN_I2C3_SDA_C, FN_SCIF3_SCK, FN_SCIFA3_SCK, 289 FN_DU1_DOTCLKIN, FN_QSTVA_QVS, 290 FN_DU1_DOTCLKOUT0, FN_QCLK, 291 FN_DU1_DOTCLKOUT1, FN_QSTVB_QVE, FN_CAN0_TX, 292 FN_TX3_B, FN_I2C2_SCL_B, FN_PWM4, 293 FN_DU1_EXHSYNC_DU1_HSYNC, FN_QSTH_QHS, 294 FN_DU1_EXVSYNC_DU1_VSYNC, FN_QSTB_QHE, 295 FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_QCPV_QDE, 296 FN_CAN0_RX, FN_RX3_B, FN_I2C2_SDA_B, 297 FN_DU1_DISP, FN_QPOLA, 298 FN_DU1_CDE, FN_QPOLB, FN_PWM4_B, 299 FN_VI0_CLKENB, FN_TX4, FN_SCIFA4_TXD, FN_TS_SDATA0_D, 300 FN_VI0_FIELD, FN_RX4, FN_SCIFA4_RXD, FN_TS_SCK0_D, 301 FN_VI0_HSYNC_N, FN_TX5, FN_SCIFA5_TXD, FN_TS_SDEN0_D, 302 FN_VI0_VSYNC_N, FN_RX5, FN_SCIFA5_RXD, FN_TS_SPSYNC0_D, 303 FN_VI0_DATA3_VI0_B3, FN_SCIF3_SCK_B, FN_SCIFA3_SCK_B, 304 FN_VI0_G0, FN_IIC1_SCL, FN_STP_IVCXO27_0_C, FN_I2C4_SCL, 305 FN_HCTS2_N, FN_SCIFB2_CTS_N, FN_ATAWR1_N, 306 307 /* IPSR10 */ 308 FN_VI0_G1, FN_IIC1_SDA, FN_STP_ISCLK_0_C, FN_I2C4_SDA, 309 FN_HRTS2_N, FN_SCIFB2_RTS_N, FN_ATADIR1_N, 310 FN_VI0_G2, FN_VI2_HSYNC_N, FN_STP_ISD_0_C, FN_I2C3_SCL_B, 311 FN_HSCK2, FN_SCIFB2_SCK, FN_ATARD1_N, 312 FN_VI0_G3, FN_VI2_VSYNC_N, FN_STP_ISEN_0_C, FN_I2C3_SDA_B, 313 FN_HRX2, FN_SCIFB2_RXD, FN_ATACS01_N, 314 FN_VI0_G4, FN_VI2_CLKENB, FN_STP_ISSYNC_0_C, 315 FN_HTX2, FN_SCIFB2_TXD, FN_SCIFB0_SCK_D, 316 FN_VI0_G5, FN_VI2_FIELD, FN_STP_OPWM_0_C, FN_FMCLK_D, 317 FN_CAN0_TX_E, FN_HTX1_D, FN_SCIFB0_TXD_D, 318 FN_VI0_G6, FN_VI2_CLK, FN_BPFCLK_D, 319 FN_VI0_G7, FN_VI2_DATA0, FN_FMIN_D, 320 FN_VI0_R0, FN_VI2_DATA1, FN_GLO_I0_B, 321 FN_TS_SDATA0_C, FN_ATACS11_N, 322 FN_VI0_R1, FN_VI2_DATA2, FN_GLO_I1_B, 323 FN_TS_SCK0_C, FN_ATAG1_N, 324 FN_VI0_R2, FN_VI2_DATA3, FN_GLO_Q0_B, FN_TS_SDEN0_C, 325 FN_VI0_R3, FN_VI2_DATA4, FN_GLO_Q1_B, FN_TS_SPSYNC0_C, 326 FN_VI0_R4, FN_VI2_DATA5, FN_GLO_SCLK_B, FN_TX0_C, FN_I2C1_SCL_D, 327 328 /* IPSR11 */ 329 FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C, FN_I2C1_SDA_D, 330 FN_VI0_R6, FN_VI2_DATA7, FN_GLO_SS_B, FN_TX1_C, FN_I2C4_SCL_B, 331 FN_VI0_R7, FN_GLO_RFON_B, FN_RX1_C, FN_CAN0_RX_E, 332 FN_I2C4_SDA_B, FN_HRX1_D, FN_SCIFB0_RXD_D, 333 FN_VI1_HSYNC_N, FN_AVB_RXD0, FN_TS_SDATA0_B, FN_TX4_B, FN_SCIFA4_TXD_B, 334 FN_VI1_VSYNC_N, FN_AVB_RXD1, FN_TS_SCK0_B, FN_RX4_B, FN_SCIFA4_RXD_B, 335 FN_VI1_CLKENB, FN_AVB_RXD2, FN_TS_SDEN0_B, 336 FN_VI1_FIELD, FN_AVB_RXD3, FN_TS_SPSYNC0_B, 337 FN_VI1_CLK, FN_AVB_RXD4, FN_VI1_DATA0, FN_AVB_RXD5, 338 FN_VI1_DATA1, FN_AVB_RXD6, FN_VI1_DATA2, FN_AVB_RXD7, 339 FN_VI1_DATA3, FN_AVB_RX_ER, FN_VI1_DATA4, FN_AVB_MDIO, 340 FN_VI1_DATA5, FN_AVB_RX_DV, FN_VI1_DATA6, FN_AVB_MAGIC, 341 FN_VI1_DATA7, FN_AVB_MDC, 342 FN_ETH_MDIO, FN_AVB_RX_CLK, FN_I2C2_SCL_C, 343 FN_ETH_CRS_DV, FN_AVB_LINK, FN_I2C2_SDA_C, 344 345 /* IPSR12 */ 346 FN_ETH_RX_ER, FN_AVB_CRS, FN_I2C3_SCL, FN_IIC0_SCL, 347 FN_ETH_RXD0, FN_AVB_PHY_INT, FN_I2C3_SDA, FN_IIC0_SDA, 348 FN_ETH_RXD1, FN_AVB_GTXREFCLK, FN_CAN0_TX_C, 349 FN_I2C2_SCL_D, FN_MSIOF1_RXD_E, 350 FN_ETH_LINK, FN_AVB_TXD0, FN_CAN0_RX_C, FN_I2C2_SDA_D, FN_MSIOF1_SCK_E, 351 FN_ETH_REFCLK, FN_AVB_TXD1, FN_SCIFA3_RXD_B, 352 FN_CAN1_RX_C, FN_MSIOF1_SYNC_E, 353 FN_ETH_TXD1, FN_AVB_TXD2, FN_SCIFA3_TXD_B, 354 FN_CAN1_TX_C, FN_MSIOF1_TXD_E, 355 FN_ETH_TX_EN, FN_AVB_TXD3, FN_TCLK1_B, FN_CAN_CLK_B, 356 FN_ETH_MAGIC, FN_AVB_TXD4, FN_IETX_C, 357 FN_ETH_TXD0, FN_AVB_TXD5, FN_IECLK_C, 358 FN_ETH_MDC, FN_AVB_TXD6, FN_IERX_C, 359 FN_STP_IVCXO27_0, FN_AVB_TXD7, FN_SCIFB2_TXD_D, 360 FN_ADIDATA_B, FN_MSIOF0_SYNC_C, 361 FN_STP_ISCLK_0, FN_AVB_TX_EN, FN_SCIFB2_RXD_D, 362 FN_ADICS_SAMP_B, FN_MSIOF0_SCK_C, 363 364 /* IPSR13 */ 365 FN_STP_ISD_0, FN_AVB_TX_ER, FN_SCIFB2_SCK_C, 366 FN_ADICLK_B, FN_MSIOF0_SS1_C, 367 FN_STP_ISEN_0, FN_AVB_TX_CLK, FN_ADICHS0_B, FN_MSIOF0_SS2_C, 368 FN_STP_ISSYNC_0, FN_AVB_COL, FN_ADICHS1_B, FN_MSIOF0_RXD_C, 369 FN_STP_OPWM_0, FN_AVB_GTX_CLK, FN_PWM0_B, 370 FN_ADICHS2_B, FN_MSIOF0_TXD_C, 371 FN_SD0_CLK, FN_SPCLK_B, FN_SD0_CMD, FN_MOSI_IO0_B, 372 FN_SD0_DATA0, FN_MISO_IO1_B, FN_SD0_DATA1, FN_IO2_B, 373 FN_SD0_DATA2, FN_IO3_B, FN_SD0_DATA3, FN_SSL_B, 374 FN_SD0_CD, FN_MMC_D6_B, FN_SIM0_RST_B, FN_CAN0_RX_F, 375 FN_SCIFA5_TXD_B, FN_TX3_C, 376 FN_SD0_WP, FN_MMC_D7_B, FN_SIM0_D_B, FN_CAN0_TX_F, 377 FN_SCIFA5_RXD_B, FN_RX3_C, 378 FN_SD1_CMD, FN_REMOCON_B, FN_SD1_DATA0, FN_SPEEDIN_B, 379 FN_SD1_DATA1, FN_IETX_B, FN_SD1_DATA2, FN_IECLK_B, 380 FN_SD1_DATA3, FN_IERX_B, 381 FN_SD1_CD, FN_PWM0, FN_TPU_TO0, FN_I2C1_SCL_C, 382 383 /* IPSR14 */ 384 FN_SD1_WP, FN_PWM1_B, FN_I2C1_SDA_C, 385 FN_SD2_CLK, FN_MMC_CLK, FN_SD2_CMD, FN_MMC_CMD, 386 FN_SD2_DATA0, FN_MMC_D0, FN_SD2_DATA1, FN_MMC_D1, 387 FN_SD2_DATA2, FN_MMC_D2, FN_SD2_DATA3, FN_MMC_D3, 388 FN_SD2_CD, FN_MMC_D4, FN_IIC1_SCL_C, FN_TX5_B, FN_SCIFA5_TXD_C, 389 FN_SD2_WP, FN_MMC_D5, FN_IIC1_SDA_C, FN_RX5_B, FN_SCIFA5_RXD_C, 390 FN_MSIOF0_SCK, FN_RX2_C, FN_ADIDATA, FN_VI1_CLK_C, FN_VI1_G0_B, 391 FN_MSIOF0_SYNC, FN_TX2_C, FN_ADICS_SAMP, FN_VI1_CLKENB_C, FN_VI1_G1_B, 392 FN_MSIOF0_TXD, FN_ADICLK, FN_VI1_FIELD_C, FN_VI1_G2_B, 393 FN_MSIOF0_RXD, FN_ADICHS0, FN_VI1_DATA0_C, FN_VI1_G3_B, 394 FN_MSIOF0_SS1, FN_MMC_D6, FN_ADICHS1, FN_TX0_E, 395 FN_VI1_HSYNC_N_C, FN_IIC0_SCL_C, FN_VI1_G4_B, 396 FN_MSIOF0_SS2, FN_MMC_D7, FN_ADICHS2, FN_RX0_E, 397 FN_VI1_VSYNC_N_C, FN_IIC0_SDA_C, FN_VI1_G5_B, 398 399 /* IPSR15 */ 400 FN_SIM0_RST, FN_IETX, FN_CAN1_TX_D, 401 FN_SIM0_CLK, FN_IECLK, FN_CAN_CLK_C, 402 FN_SIM0_D, FN_IERX, FN_CAN1_RX_D, 403 FN_GPS_CLK, FN_DU1_DOTCLKIN_C, FN_AUDIO_CLKB_B, 404 FN_PWM5_B, FN_SCIFA3_TXD_C, 405 FN_GPS_SIGN, FN_TX4_C, FN_SCIFA4_TXD_C, FN_PWM5, 406 FN_VI1_G6_B, FN_SCIFA3_RXD_C, 407 FN_GPS_MAG, FN_RX4_C, FN_SCIFA4_RXD_C, FN_PWM6, 408 FN_VI1_G7_B, FN_SCIFA3_SCK_C, 409 FN_HCTS0_N, FN_SCIFB0_CTS_N, FN_GLO_I0_C, FN_TCLK1, FN_VI1_DATA1_C, 410 FN_HRTS0_N, FN_SCIFB0_RTS_N, FN_GLO_I1_C, FN_VI1_DATA2_C, 411 FN_HSCK0, FN_SCIFB0_SCK, FN_GLO_Q0_C, FN_CAN_CLK, 412 FN_TCLK2, FN_VI1_DATA3_C, 413 FN_HRX0, FN_SCIFB0_RXD, FN_GLO_Q1_C, FN_CAN0_RX_B, FN_VI1_DATA4_C, 414 FN_HTX0, FN_SCIFB0_TXD, FN_GLO_SCLK_C, FN_CAN0_TX_B, FN_VI1_DATA5_C, 415 416 /* IPSR16 */ 417 FN_HRX1, FN_SCIFB1_RXD, FN_VI1_R0_B, FN_GLO_SDATA_C, FN_VI1_DATA6_C, 418 FN_HTX1, FN_SCIFB1_TXD, FN_VI1_R1_B, FN_GLO_SS_C, FN_VI1_DATA7_C, 419 FN_HSCK1, FN_SCIFB1_SCK, FN_MLB_CLK, FN_GLO_RFON_C, 420 FN_HCTS1_N, FN_SCIFB1_CTS_N, FN_MLB_SIG, FN_CAN1_TX_B, 421 FN_HRTS1_N, FN_SCIFB1_RTS_N, FN_MLB_DAT, FN_CAN1_RX_B, 422 423 /* MOD_SEL */ 424 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3, 425 FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, FN_SEL_SCIFB_3, 426 FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, FN_SEL_SCIFB2_3, 427 FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3, 428 FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, 429 FN_SEL_SSI9_0, FN_SEL_SSI9_1, 430 FN_SEL_SCFA_0, FN_SEL_SCFA_1, 431 FN_SEL_QSP_0, FN_SEL_QSP_1, 432 FN_SEL_SSI7_0, FN_SEL_SSI7_1, 433 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2, FN_SEL_HSCIF1_3, 434 FN_SEL_HSCIF1_4, 435 FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2, 436 FN_SEL_TMU1_0, FN_SEL_TMU1_1, 437 FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_LBS_2, FN_SEL_LBS_3, 438 FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, 439 FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2, 440 441 /* MOD_SEL2 */ 442 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3, 443 FN_SEL_SCIF0_4, 444 FN_SEL_SCIF_0, FN_SEL_SCIF_1, 445 FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3, 446 FN_SEL_CAN0_4, FN_SEL_CAN0_5, 447 FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3, 448 FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, 449 FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, 450 FN_SEL_ADG_0, FN_SEL_ADG_1, 451 FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3, FN_SEL_FM_4, 452 FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, 453 FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3, 454 FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2, 455 FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2, 456 FN_SEL_SIM_0, FN_SEL_SIM_1, 457 FN_SEL_SSI8_0, FN_SEL_SSI8_1, 458 459 /* MOD_SEL3 */ 460 FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1, FN_SEL_HSCIF2_2, FN_SEL_HSCIF2_3, 461 FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2, FN_SEL_CANCLK_3, 462 FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, 463 FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, 464 FN_SEL_I2C4_0, FN_SEL_I2C4_1, FN_SEL_I2C4_2, 465 FN_SEL_I2C3_0, FN_SEL_I2C3_1, FN_SEL_I2C3_2, FN_SEL_I2C3_3, 466 FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3, 467 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 468 FN_SEL_MMC_0, FN_SEL_MMC_1, 469 FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, 470 FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3, 471 FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, FN_SEL_I2C1_3, 472 FN_SEL_I2C1_4, 473 FN_SEL_I2C0_0, FN_SEL_I2C0_1, FN_SEL_I2C0_2, 474 475 /* MOD_SEL4 */ 476 FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3, 477 FN_SEL_SOF1_4, 478 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, 479 FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2, 480 FN_SEL_RAD_0, FN_SEL_RAD_1, 481 FN_SEL_RCN_0, FN_SEL_RCN_1, 482 FN_SEL_RSP_0, FN_SEL_RSP_1, 483 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF2_3, 484 FN_SEL_SCIF2_4, 485 FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2, FN_SEL_SOF2_3, 486 FN_SEL_SOF2_4, 487 FN_SEL_SSI1_0, FN_SEL_SSI1_1, 488 FN_SEL_SSI0_0, FN_SEL_SSI0_1, 489 FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2, 490 PINMUX_FUNCTION_END, 491 492 PINMUX_MARK_BEGIN, 493 494 EX_CS0_N_MARK, RD_N_MARK, 495 496 AUDIO_CLKA_MARK, 497 498 VI0_CLK_MARK, VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK, 499 VI0_DATA2_VI0_B2_MARK, VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK, 500 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK, 501 502 SD1_CLK_MARK, 503 504 USB0_PWEN_MARK, USB0_OVC_MARK, USB1_PWEN_MARK, USB1_OVC_MARK, 505 DU0_DOTCLKIN_MARK, 506 507 /* IPSR0 */ 508 D0_MARK, D1_MARK, D2_MARK, D3_MARK, D4_MARK, D5_MARK, 509 D6_MARK, D7_MARK, D8_MARK, 510 D9_MARK, D10_MARK, D11_MARK, D12_MARK, D13_MARK, D14_MARK, D15_MARK, 511 A0_MARK, ATAWR0_N_C_MARK, MSIOF0_SCK_B_MARK, I2C0_SCL_C_MARK, 512 PWM2_B_MARK, 513 A1_MARK, MSIOF0_SYNC_B_MARK, A2_MARK, MSIOF0_SS1_B_MARK, 514 A3_MARK, MSIOF0_SS2_B_MARK, A4_MARK, MSIOF0_TXD_B_MARK, 515 A5_MARK, MSIOF0_RXD_B_MARK, A6_MARK, MSIOF1_SCK_MARK, 516 517 /* IPSR1 */ 518 A7_MARK, MSIOF1_SYNC_MARK, A8_MARK, MSIOF1_SS1_MARK, I2C0_SCL_MARK, 519 A9_MARK, MSIOF1_SS2_MARK, I2C0_SDA_MARK, 520 A10_MARK, MSIOF1_TXD_MARK, MSIOF1_TXD_D_MARK, 521 A11_MARK, MSIOF1_RXD_MARK, I2C3_SCL_D_MARK, MSIOF1_RXD_D_MARK, 522 A12_MARK, FMCLK_MARK, I2C3_SDA_D_MARK, MSIOF1_SCK_D_MARK, 523 A13_MARK, ATAG0_N_C_MARK, BPFCLK_MARK, MSIOF1_SS1_D_MARK, 524 A14_MARK, ATADIR0_N_C_MARK, FMIN_MARK, FMIN_C_MARK, MSIOF1_SYNC_D_MARK, 525 A15_MARK, BPFCLK_C_MARK, 526 A16_MARK, DREQ2_B_MARK, FMCLK_C_MARK, SCIFA1_SCK_B_MARK, 527 A17_MARK, DACK2_B_MARK, I2C0_SDA_C_MARK, 528 A18_MARK, DREQ1_MARK, SCIFA1_RXD_C_MARK, SCIFB1_RXD_C_MARK, 529 530 /* IPSR2 */ 531 A19_MARK, DACK1_MARK, SCIFA1_TXD_C_MARK, 532 SCIFB1_TXD_C_MARK, SCIFB1_SCK_B_MARK, 533 A20_MARK, SPCLK_MARK, 534 A21_MARK, ATAWR0_N_B_MARK, MOSI_IO0_MARK, 535 A22_MARK, MISO_IO1_MARK, FMCLK_B_MARK, TX0_MARK, SCIFA0_TXD_MARK, 536 A23_MARK, IO2_MARK, BPFCLK_B_MARK, RX0_MARK, SCIFA0_RXD_MARK, 537 A24_MARK, DREQ2_MARK, IO3_MARK, TX1_MARK, SCIFA1_TXD_MARK, 538 A25_MARK, DACK2_MARK, SSL_MARK, DREQ1_C_MARK, 539 RX1_MARK, SCIFA1_RXD_MARK, 540 CS0_N_MARK, ATAG0_N_B_MARK, I2C1_SCL_MARK, 541 CS1_N_A26_MARK, ATADIR0_N_B_MARK, I2C1_SDA_MARK, 542 EX_CS1_N_MARK, MSIOF2_SCK_MARK, 543 EX_CS2_N_MARK, ATAWR0_N_MARK, MSIOF2_SYNC_MARK, 544 EX_CS3_N_MARK, ATADIR0_N_MARK, MSIOF2_TXD_MARK, 545 ATAG0_N_MARK, EX_WAIT1_MARK, 546 547 /* IPSR3 */ 548 EX_CS4_N_MARK, ATARD0_N_MARK, MSIOF2_RXD_MARK, EX_WAIT2_MARK, 549 EX_CS5_N_MARK, ATACS00_N_MARK, MSIOF2_SS1_MARK, HRX1_B_MARK, 550 SCIFB1_RXD_B_MARK, PWM1_MARK, TPU_TO1_MARK, 551 BS_N_MARK, ATACS10_N_MARK, MSIOF2_SS2_MARK, HTX1_B_MARK, 552 SCIFB1_TXD_B_MARK, PWM2_MARK, TPU_TO2_MARK, 553 RD_WR_N_MARK, HRX2_B_MARK, FMIN_B_MARK, 554 SCIFB0_RXD_B_MARK, DREQ1_D_MARK, 555 WE0_N_MARK, HCTS2_N_B_MARK, SCIFB0_TXD_B_MARK, 556 WE1_N_MARK, ATARD0_N_B_MARK, HTX2_B_MARK, SCIFB0_RTS_N_B_MARK, 557 EX_WAIT0_MARK, HRTS2_N_B_MARK, SCIFB0_CTS_N_B_MARK, 558 DREQ0_MARK, PWM3_MARK, TPU_TO3_MARK, 559 DACK0_MARK, DRACK0_MARK, REMOCON_MARK, 560 SPEEDIN_MARK, HSCK0_C_MARK, HSCK2_C_MARK, SCIFB0_SCK_B_MARK, 561 SCIFB2_SCK_B_MARK, DREQ2_C_MARK, HTX2_D_MARK, 562 SSI_SCK0129_MARK, HRX0_C_MARK, HRX2_C_MARK, 563 SCIFB0_RXD_C_MARK, SCIFB2_RXD_C_MARK, 564 SSI_WS0129_MARK, HTX0_C_MARK, HTX2_C_MARK, 565 SCIFB0_TXD_C_MARK, SCIFB2_TXD_C_MARK, 566 567 /* IPSR4 */ 568 SSI_SDATA0_MARK, I2C0_SCL_B_MARK, IIC0_SCL_B_MARK, MSIOF2_SCK_C_MARK, 569 SSI_SCK1_MARK, I2C0_SDA_B_MARK, IIC0_SDA_B_MARK, 570 MSIOF2_SYNC_C_MARK, GLO_I0_D_MARK, 571 SSI_WS1_MARK, I2C1_SCL_B_MARK, IIC1_SCL_B_MARK, 572 MSIOF2_TXD_C_MARK, GLO_I1_D_MARK, 573 SSI_SDATA1_MARK, I2C1_SDA_B_MARK, IIC1_SDA_B_MARK, MSIOF2_RXD_C_MARK, 574 SSI_SCK2_MARK, I2C2_SCL_MARK, GPS_CLK_B_MARK, GLO_Q0_D_MARK, 575 HSCK1_E_MARK, 576 SSI_WS2_MARK, I2C2_SDA_MARK, GPS_SIGN_B_MARK, RX2_E_MARK, 577 GLO_Q1_D_MARK, HCTS1_N_E_MARK, 578 SSI_SDATA2_MARK, GPS_MAG_B_MARK, TX2_E_MARK, HRTS1_N_E_MARK, 579 SSI_SCK34_MARK, SSI_WS34_MARK, SSI_SDATA3_MARK, 580 SSI_SCK4_MARK, GLO_SS_D_MARK, 581 SSI_WS4_MARK, GLO_RFON_D_MARK, 582 SSI_SDATA4_MARK, MSIOF2_SCK_D_MARK, 583 SSI_SCK5_MARK, MSIOF1_SCK_C_MARK, TS_SDATA0_MARK, GLO_I0_MARK, 584 MSIOF2_SYNC_D_MARK, VI1_R2_B_MARK, 585 586 /* IPSR5 */ 587 SSI_WS5_MARK, MSIOF1_SYNC_C_MARK, TS_SCK0_MARK, GLO_I1_MARK, 588 MSIOF2_TXD_D_MARK, VI1_R3_B_MARK, 589 SSI_SDATA5_MARK, MSIOF1_TXD_C_MARK, TS_SDEN0_MARK, GLO_Q0_MARK, 590 MSIOF2_SS1_D_MARK, VI1_R4_B_MARK, 591 SSI_SCK6_MARK, MSIOF1_RXD_C_MARK, TS_SPSYNC0_MARK, GLO_Q1_MARK, 592 MSIOF2_RXD_D_MARK, VI1_R5_B_MARK, 593 SSI_WS6_MARK, GLO_SCLK_MARK, MSIOF2_SS2_D_MARK, VI1_R6_B_MARK, 594 SSI_SDATA6_MARK, STP_IVCXO27_0_B_MARK, GLO_SDATA_MARK, VI1_R7_B_MARK, 595 SSI_SCK78_MARK, STP_ISCLK_0_B_MARK, GLO_SS_MARK, 596 SSI_WS78_MARK, TX0_D_MARK, STP_ISD_0_B_MARK, GLO_RFON_MARK, 597 SSI_SDATA7_MARK, RX0_D_MARK, STP_ISEN_0_B_MARK, 598 SSI_SDATA8_MARK, TX1_D_MARK, STP_ISSYNC_0_B_MARK, 599 SSI_SCK9_MARK, RX1_D_MARK, GLO_SCLK_D_MARK, 600 SSI_WS9_MARK, TX3_D_MARK, CAN0_TX_D_MARK, GLO_SDATA_D_MARK, 601 SSI_SDATA9_MARK, RX3_D_MARK, CAN0_RX_D_MARK, 602 603 /* IPSR6 */ 604 AUDIO_CLKB_MARK, STP_OPWM_0_B_MARK, MSIOF1_SCK_B_MARK, 605 SCIF_CLK_MARK, DVC_MUTE_MARK, BPFCLK_E_MARK, 606 AUDIO_CLKC_MARK, SCIFB0_SCK_C_MARK, MSIOF1_SYNC_B_MARK, RX2_MARK, 607 SCIFA2_RXD_MARK, FMIN_E_MARK, 608 AUDIO_CLKOUT_MARK, MSIOF1_SS1_B_MARK, TX2_MARK, SCIFA2_TXD_MARK, 609 IRQ0_MARK, SCIFB1_RXD_D_MARK, 610 IRQ1_MARK, SCIFB1_SCK_C_MARK, 611 IRQ2_MARK, SCIFB1_TXD_D_MARK, 612 IRQ3_MARK, I2C4_SCL_C_MARK, MSIOF2_TXD_E_MARK, 613 IRQ4_MARK, HRX1_C_MARK, I2C4_SDA_C_MARK, 614 MSIOF2_RXD_E_MARK, 615 IRQ5_MARK, HTX1_C_MARK, I2C1_SCL_E_MARK, MSIOF2_SCK_E_MARK, 616 IRQ6_MARK, HSCK1_C_MARK, MSIOF1_SS2_B_MARK, 617 I2C1_SDA_E_MARK, MSIOF2_SYNC_E_MARK, 618 IRQ7_MARK, HCTS1_N_C_MARK, MSIOF1_TXD_B_MARK, 619 GPS_CLK_C_MARK, GPS_CLK_D_MARK, 620 IRQ8_MARK, HRTS1_N_C_MARK, MSIOF1_RXD_B_MARK, 621 GPS_SIGN_C_MARK, GPS_SIGN_D_MARK, 622 623 /* IPSR7 */ 624 IRQ9_MARK, DU1_DOTCLKIN_B_MARK, CAN_CLK_D_MARK, GPS_MAG_C_MARK, 625 SCIF_CLK_B_MARK, GPS_MAG_D_MARK, 626 DU1_DR0_MARK, LCDOUT0_MARK, VI1_DATA0_B_MARK, TX0_B_MARK, 627 SCIFA0_TXD_B_MARK, MSIOF2_SCK_B_MARK, 628 DU1_DR1_MARK, LCDOUT1_MARK, VI1_DATA1_B_MARK, RX0_B_MARK, 629 SCIFA0_RXD_B_MARK, MSIOF2_SYNC_B_MARK, 630 DU1_DR2_MARK, LCDOUT2_MARK, SSI_SCK0129_B_MARK, 631 DU1_DR3_MARK, LCDOUT3_MARK, SSI_WS0129_B_MARK, 632 DU1_DR4_MARK, LCDOUT4_MARK, SSI_SDATA0_B_MARK, 633 DU1_DR5_MARK, LCDOUT5_MARK, SSI_SCK1_B_MARK, 634 DU1_DR6_MARK, LCDOUT6_MARK, SSI_WS1_B_MARK, 635 DU1_DR7_MARK, LCDOUT7_MARK, SSI_SDATA1_B_MARK, 636 DU1_DG0_MARK, LCDOUT8_MARK, VI1_DATA2_B_MARK, TX1_B_MARK, 637 SCIFA1_TXD_B_MARK, MSIOF2_SS1_B_MARK, 638 DU1_DG1_MARK, LCDOUT9_MARK, VI1_DATA3_B_MARK, RX1_B_MARK, 639 SCIFA1_RXD_B_MARK, MSIOF2_SS2_B_MARK, 640 DU1_DG2_MARK, LCDOUT10_MARK, VI1_DATA4_B_MARK, SCIF1_SCK_B_MARK, 641 SCIFA1_SCK_MARK, SSI_SCK78_B_MARK, 642 643 /* IPSR8 */ 644 DU1_DG3_MARK, LCDOUT11_MARK, VI1_DATA5_B_MARK, SSI_WS78_B_MARK, 645 DU1_DG4_MARK, LCDOUT12_MARK, VI1_DATA6_B_MARK, HRX0_B_MARK, 646 SCIFB2_RXD_B_MARK, SSI_SDATA7_B_MARK, 647 DU1_DG5_MARK, LCDOUT13_MARK, VI1_DATA7_B_MARK, HCTS0_N_B_MARK, 648 SCIFB2_TXD_B_MARK, SSI_SDATA8_B_MARK, 649 DU1_DG6_MARK, LCDOUT14_MARK, HRTS0_N_B_MARK, 650 SCIFB2_CTS_N_B_MARK, SSI_SCK9_B_MARK, 651 DU1_DG7_MARK, LCDOUT15_MARK, HTX0_B_MARK, 652 SCIFB2_RTS_N_B_MARK, SSI_WS9_B_MARK, 653 DU1_DB0_MARK, LCDOUT16_MARK, VI1_CLK_B_MARK, TX2_B_MARK, 654 SCIFA2_TXD_B_MARK, MSIOF2_TXD_B_MARK, 655 DU1_DB1_MARK, LCDOUT17_MARK, VI1_HSYNC_N_B_MARK, RX2_B_MARK, 656 SCIFA2_RXD_B_MARK, MSIOF2_RXD_B_MARK, 657 DU1_DB2_MARK, LCDOUT18_MARK, VI1_VSYNC_N_B_MARK, SCIF2_SCK_B_MARK, 658 SCIFA2_SCK_MARK, SSI_SDATA9_B_MARK, 659 DU1_DB3_MARK, LCDOUT19_MARK, VI1_CLKENB_B_MARK, 660 DU1_DB4_MARK, LCDOUT20_MARK, VI1_FIELD_B_MARK, CAN1_RX_MARK, 661 DU1_DB5_MARK, LCDOUT21_MARK, TX3_MARK, SCIFA3_TXD_MARK, CAN1_TX_MARK, 662 663 /* IPSR9 */ 664 DU1_DB6_MARK, LCDOUT22_MARK, I2C3_SCL_C_MARK, RX3_MARK, SCIFA3_RXD_MARK, 665 DU1_DB7_MARK, LCDOUT23_MARK, I2C3_SDA_C_MARK, 666 SCIF3_SCK_MARK, SCIFA3_SCK_MARK, 667 DU1_DOTCLKIN_MARK, QSTVA_QVS_MARK, 668 DU1_DOTCLKOUT0_MARK, QCLK_MARK, 669 DU1_DOTCLKOUT1_MARK, QSTVB_QVE_MARK, CAN0_TX_MARK, 670 TX3_B_MARK, I2C2_SCL_B_MARK, PWM4_MARK, 671 DU1_EXHSYNC_DU1_HSYNC_MARK, QSTH_QHS_MARK, 672 DU1_EXVSYNC_DU1_VSYNC_MARK, QSTB_QHE_MARK, 673 DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK, 674 CAN0_RX_MARK, RX3_B_MARK, I2C2_SDA_B_MARK, 675 DU1_DISP_MARK, QPOLA_MARK, 676 DU1_CDE_MARK, QPOLB_MARK, PWM4_B_MARK, 677 VI0_CLKENB_MARK, TX4_MARK, SCIFA4_TXD_MARK, TS_SDATA0_D_MARK, 678 VI0_FIELD_MARK, RX4_MARK, SCIFA4_RXD_MARK, TS_SCK0_D_MARK, 679 VI0_HSYNC_N_MARK, TX5_MARK, SCIFA5_TXD_MARK, TS_SDEN0_D_MARK, 680 VI0_VSYNC_N_MARK, RX5_MARK, SCIFA5_RXD_MARK, TS_SPSYNC0_D_MARK, 681 VI0_DATA3_VI0_B3_MARK, SCIF3_SCK_B_MARK, SCIFA3_SCK_B_MARK, 682 VI0_G0_MARK, IIC1_SCL_MARK, STP_IVCXO27_0_C_MARK, I2C4_SCL_MARK, 683 HCTS2_N_MARK, SCIFB2_CTS_N_MARK, ATAWR1_N_MARK, 684 685 /* IPSR10 */ 686 VI0_G1_MARK, IIC1_SDA_MARK, STP_ISCLK_0_C_MARK, I2C4_SDA_MARK, 687 HRTS2_N_MARK, SCIFB2_RTS_N_MARK, ATADIR1_N_MARK, 688 VI0_G2_MARK, VI2_HSYNC_N_MARK, STP_ISD_0_C_MARK, I2C3_SCL_B_MARK, 689 HSCK2_MARK, SCIFB2_SCK_MARK, ATARD1_N_MARK, 690 VI0_G3_MARK, VI2_VSYNC_N_MARK, STP_ISEN_0_C_MARK, I2C3_SDA_B_MARK, 691 HRX2_MARK, SCIFB2_RXD_MARK, ATACS01_N_MARK, 692 VI0_G4_MARK, VI2_CLKENB_MARK, STP_ISSYNC_0_C_MARK, 693 HTX2_MARK, SCIFB2_TXD_MARK, SCIFB0_SCK_D_MARK, 694 VI0_G5_MARK, VI2_FIELD_MARK, STP_OPWM_0_C_MARK, FMCLK_D_MARK, 695 CAN0_TX_E_MARK, HTX1_D_MARK, SCIFB0_TXD_D_MARK, 696 VI0_G6_MARK, VI2_CLK_MARK, BPFCLK_D_MARK, 697 VI0_G7_MARK, VI2_DATA0_MARK, FMIN_D_MARK, 698 VI0_R0_MARK, VI2_DATA1_MARK, GLO_I0_B_MARK, 699 TS_SDATA0_C_MARK, ATACS11_N_MARK, 700 VI0_R1_MARK, VI2_DATA2_MARK, GLO_I1_B_MARK, 701 TS_SCK0_C_MARK, ATAG1_N_MARK, 702 VI0_R2_MARK, VI2_DATA3_MARK, GLO_Q0_B_MARK, TS_SDEN0_C_MARK, 703 VI0_R3_MARK, VI2_DATA4_MARK, GLO_Q1_B_MARK, TS_SPSYNC0_C_MARK, 704 VI0_R4_MARK, VI2_DATA5_MARK, GLO_SCLK_B_MARK, TX0_C_MARK, 705 I2C1_SCL_D_MARK, 706 707 /* IPSR11 */ 708 VI0_R5_MARK, VI2_DATA6_MARK, GLO_SDATA_B_MARK, RX0_C_MARK, 709 I2C1_SDA_D_MARK, 710 VI0_R6_MARK, VI2_DATA7_MARK, GLO_SS_B_MARK, TX1_C_MARK, I2C4_SCL_B_MARK, 711 VI0_R7_MARK, GLO_RFON_B_MARK, RX1_C_MARK, CAN0_RX_E_MARK, 712 I2C4_SDA_B_MARK, HRX1_D_MARK, SCIFB0_RXD_D_MARK, 713 VI1_HSYNC_N_MARK, AVB_RXD0_MARK, TS_SDATA0_B_MARK, 714 TX4_B_MARK, SCIFA4_TXD_B_MARK, 715 VI1_VSYNC_N_MARK, AVB_RXD1_MARK, TS_SCK0_B_MARK, 716 RX4_B_MARK, SCIFA4_RXD_B_MARK, 717 VI1_CLKENB_MARK, AVB_RXD2_MARK, TS_SDEN0_B_MARK, 718 VI1_FIELD_MARK, AVB_RXD3_MARK, TS_SPSYNC0_B_MARK, 719 VI1_CLK_MARK, AVB_RXD4_MARK, VI1_DATA0_MARK, AVB_RXD5_MARK, 720 VI1_DATA1_MARK, AVB_RXD6_MARK, VI1_DATA2_MARK, AVB_RXD7_MARK, 721 VI1_DATA3_MARK, AVB_RX_ER_MARK, VI1_DATA4_MARK, AVB_MDIO_MARK, 722 VI1_DATA5_MARK, AVB_RX_DV_MARK, VI1_DATA6_MARK, AVB_MAGIC_MARK, 723 VI1_DATA7_MARK, AVB_MDC_MARK, 724 ETH_MDIO_MARK, AVB_RX_CLK_MARK, I2C2_SCL_C_MARK, 725 ETH_CRS_DV_MARK, AVB_LINK_MARK, I2C2_SDA_C_MARK, 726 727 /* IPSR12 */ 728 ETH_RX_ER_MARK, AVB_CRS_MARK, I2C3_SCL_MARK, IIC0_SCL_MARK, 729 ETH_RXD0_MARK, AVB_PHY_INT_MARK, I2C3_SDA_MARK, IIC0_SDA_MARK, 730 ETH_RXD1_MARK, AVB_GTXREFCLK_MARK, CAN0_TX_C_MARK, 731 I2C2_SCL_D_MARK, MSIOF1_RXD_E_MARK, 732 ETH_LINK_MARK, AVB_TXD0_MARK, CAN0_RX_C_MARK, 733 I2C2_SDA_D_MARK, MSIOF1_SCK_E_MARK, 734 ETH_REFCLK_MARK, AVB_TXD1_MARK, SCIFA3_RXD_B_MARK, 735 CAN1_RX_C_MARK, MSIOF1_SYNC_E_MARK, 736 ETH_TXD1_MARK, AVB_TXD2_MARK, SCIFA3_TXD_B_MARK, 737 CAN1_TX_C_MARK, MSIOF1_TXD_E_MARK, 738 ETH_TX_EN_MARK, AVB_TXD3_MARK, TCLK1_B_MARK, CAN_CLK_B_MARK, 739 ETH_MAGIC_MARK, AVB_TXD4_MARK, IETX_C_MARK, 740 ETH_TXD0_MARK, AVB_TXD5_MARK, IECLK_C_MARK, 741 ETH_MDC_MARK, AVB_TXD6_MARK, IERX_C_MARK, 742 STP_IVCXO27_0_MARK, AVB_TXD7_MARK, SCIFB2_TXD_D_MARK, 743 ADIDATA_B_MARK, MSIOF0_SYNC_C_MARK, 744 STP_ISCLK_0_MARK, AVB_TX_EN_MARK, SCIFB2_RXD_D_MARK, 745 ADICS_SAMP_B_MARK, MSIOF0_SCK_C_MARK, 746 747 /* IPSR13 */ 748 STP_ISD_0_MARK, AVB_TX_ER_MARK, SCIFB2_SCK_C_MARK, 749 ADICLK_B_MARK, MSIOF0_SS1_C_MARK, 750 STP_ISEN_0_MARK, AVB_TX_CLK_MARK, ADICHS0_B_MARK, MSIOF0_SS2_C_MARK, 751 STP_ISSYNC_0_MARK, AVB_COL_MARK, ADICHS1_B_MARK, MSIOF0_RXD_C_MARK, 752 STP_OPWM_0_MARK, AVB_GTX_CLK_MARK, PWM0_B_MARK, 753 ADICHS2_B_MARK, MSIOF0_TXD_C_MARK, 754 SD0_CLK_MARK, SPCLK_B_MARK, SD0_CMD_MARK, MOSI_IO0_B_MARK, 755 SD0_DATA0_MARK, MISO_IO1_B_MARK, SD0_DATA1_MARK, IO2_B_MARK, 756 SD0_DATA2_MARK, IO3_B_MARK, SD0_DATA3_MARK, SSL_B_MARK, 757 SD0_CD_MARK, MMC_D6_B_MARK, SIM0_RST_B_MARK, CAN0_RX_F_MARK, 758 SCIFA5_TXD_B_MARK, TX3_C_MARK, 759 SD0_WP_MARK, MMC_D7_B_MARK, SIM0_D_B_MARK, CAN0_TX_F_MARK, 760 SCIFA5_RXD_B_MARK, RX3_C_MARK, 761 SD1_CMD_MARK, REMOCON_B_MARK, SD1_DATA0_MARK, SPEEDIN_B_MARK, 762 SD1_DATA1_MARK, IETX_B_MARK, SD1_DATA2_MARK, IECLK_B_MARK, 763 SD1_DATA3_MARK, IERX_B_MARK, 764 SD1_CD_MARK, PWM0_MARK, TPU_TO0_MARK, I2C1_SCL_C_MARK, 765 766 /* IPSR14 */ 767 SD1_WP_MARK, PWM1_B_MARK, I2C1_SDA_C_MARK, 768 SD2_CLK_MARK, MMC_CLK_MARK, SD2_CMD_MARK, MMC_CMD_MARK, 769 SD2_DATA0_MARK, MMC_D0_MARK, SD2_DATA1_MARK, MMC_D1_MARK, 770 SD2_DATA2_MARK, MMC_D2_MARK, SD2_DATA3_MARK, MMC_D3_MARK, 771 SD2_CD_MARK, MMC_D4_MARK, IIC1_SCL_C_MARK, TX5_B_MARK, 772 SCIFA5_TXD_C_MARK, 773 SD2_WP_MARK, MMC_D5_MARK, IIC1_SDA_C_MARK, RX5_B_MARK, 774 SCIFA5_RXD_C_MARK, 775 MSIOF0_SCK_MARK, RX2_C_MARK, ADIDATA_MARK, 776 VI1_CLK_C_MARK, VI1_G0_B_MARK, 777 MSIOF0_SYNC_MARK, TX2_C_MARK, ADICS_SAMP_MARK, 778 VI1_CLKENB_C_MARK, VI1_G1_B_MARK, 779 MSIOF0_TXD_MARK, ADICLK_MARK, VI1_FIELD_C_MARK, VI1_G2_B_MARK, 780 MSIOF0_RXD_MARK, ADICHS0_MARK, VI1_DATA0_C_MARK, VI1_G3_B_MARK, 781 MSIOF0_SS1_MARK, MMC_D6_MARK, ADICHS1_MARK, TX0_E_MARK, 782 VI1_HSYNC_N_C_MARK, IIC0_SCL_C_MARK, VI1_G4_B_MARK, 783 MSIOF0_SS2_MARK, MMC_D7_MARK, ADICHS2_MARK, RX0_E_MARK, 784 VI1_VSYNC_N_C_MARK, IIC0_SDA_C_MARK, VI1_G5_B_MARK, 785 786 /* IPSR15 */ 787 SIM0_RST_MARK, IETX_MARK, CAN1_TX_D_MARK, 788 SIM0_CLK_MARK, IECLK_MARK, CAN_CLK_C_MARK, 789 SIM0_D_MARK, IERX_MARK, CAN1_RX_D_MARK, 790 GPS_CLK_MARK, DU1_DOTCLKIN_C_MARK, AUDIO_CLKB_B_MARK, 791 PWM5_B_MARK, SCIFA3_TXD_C_MARK, 792 GPS_SIGN_MARK, TX4_C_MARK, SCIFA4_TXD_C_MARK, PWM5_MARK, 793 VI1_G6_B_MARK, SCIFA3_RXD_C_MARK, 794 GPS_MAG_MARK, RX4_C_MARK, SCIFA4_RXD_C_MARK, PWM6_MARK, 795 VI1_G7_B_MARK, SCIFA3_SCK_C_MARK, 796 HCTS0_N_MARK, SCIFB0_CTS_N_MARK, GLO_I0_C_MARK, 797 TCLK1_MARK, VI1_DATA1_C_MARK, 798 HRTS0_N_MARK, SCIFB0_RTS_N_MARK, GLO_I1_C_MARK, VI1_DATA2_C_MARK, 799 HSCK0_MARK, SCIFB0_SCK_MARK, GLO_Q0_C_MARK, CAN_CLK_MARK, 800 TCLK2_MARK, VI1_DATA3_C_MARK, 801 HRX0_MARK, SCIFB0_RXD_MARK, GLO_Q1_C_MARK, 802 CAN0_RX_B_MARK, VI1_DATA4_C_MARK, 803 HTX0_MARK, SCIFB0_TXD_MARK, GLO_SCLK_C_MARK, 804 CAN0_TX_B_MARK, VI1_DATA5_C_MARK, 805 806 /* IPSR16 */ 807 HRX1_MARK, SCIFB1_RXD_MARK, VI1_R0_B_MARK, 808 GLO_SDATA_C_MARK, VI1_DATA6_C_MARK, 809 HTX1_MARK, SCIFB1_TXD_MARK, VI1_R1_B_MARK, 810 GLO_SS_C_MARK, VI1_DATA7_C_MARK, 811 HSCK1_MARK, SCIFB1_SCK_MARK, MLB_CLK_MARK, GLO_RFON_C_MARK, 812 HCTS1_N_MARK, SCIFB1_CTS_N_MARK, MLB_SIG_MARK, CAN1_TX_B_MARK, 813 HRTS1_N_MARK, SCIFB1_RTS_N_MARK, MLB_DAT_MARK, CAN1_RX_B_MARK, 814 PINMUX_MARK_END, 815 }; 816 817 static const u16 pinmux_data[] = { 818 PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */ 819 820 PINMUX_SINGLE(EX_CS0_N), 821 PINMUX_SINGLE(RD_N), 822 PINMUX_SINGLE(AUDIO_CLKA), 823 PINMUX_SINGLE(VI0_CLK), 824 PINMUX_SINGLE(VI0_DATA0_VI0_B0), 825 PINMUX_SINGLE(VI0_DATA1_VI0_B1), 826 PINMUX_SINGLE(VI0_DATA2_VI0_B2), 827 PINMUX_SINGLE(VI0_DATA4_VI0_B4), 828 PINMUX_SINGLE(VI0_DATA5_VI0_B5), 829 PINMUX_SINGLE(VI0_DATA6_VI0_B6), 830 PINMUX_SINGLE(VI0_DATA7_VI0_B7), 831 PINMUX_SINGLE(USB0_PWEN), 832 PINMUX_SINGLE(USB0_OVC), 833 PINMUX_SINGLE(USB1_PWEN), 834 PINMUX_SINGLE(USB1_OVC), 835 PINMUX_SINGLE(DU0_DOTCLKIN), 836 PINMUX_SINGLE(SD1_CLK), 837 838 /* IPSR0 */ 839 PINMUX_IPSR_GPSR(IP0_0, D0), 840 PINMUX_IPSR_GPSR(IP0_1, D1), 841 PINMUX_IPSR_GPSR(IP0_2, D2), 842 PINMUX_IPSR_GPSR(IP0_3, D3), 843 PINMUX_IPSR_GPSR(IP0_4, D4), 844 PINMUX_IPSR_GPSR(IP0_5, D5), 845 PINMUX_IPSR_GPSR(IP0_6, D6), 846 PINMUX_IPSR_GPSR(IP0_7, D7), 847 PINMUX_IPSR_GPSR(IP0_8, D8), 848 PINMUX_IPSR_GPSR(IP0_9, D9), 849 PINMUX_IPSR_GPSR(IP0_10, D10), 850 PINMUX_IPSR_GPSR(IP0_11, D11), 851 PINMUX_IPSR_GPSR(IP0_12, D12), 852 PINMUX_IPSR_GPSR(IP0_13, D13), 853 PINMUX_IPSR_GPSR(IP0_14, D14), 854 PINMUX_IPSR_GPSR(IP0_15, D15), 855 PINMUX_IPSR_GPSR(IP0_18_16, A0), 856 PINMUX_IPSR_MSEL(IP0_18_16, ATAWR0_N_C, SEL_LBS_2), 857 PINMUX_IPSR_MSEL(IP0_18_16, MSIOF0_SCK_B, SEL_SOF0_1), 858 PINMUX_IPSR_MSEL(IP0_18_16, I2C0_SCL_C, SEL_I2C0_2), 859 PINMUX_IPSR_GPSR(IP0_18_16, PWM2_B), 860 PINMUX_IPSR_GPSR(IP0_20_19, A1), 861 PINMUX_IPSR_MSEL(IP0_20_19, MSIOF0_SYNC_B, SEL_SOF0_1), 862 PINMUX_IPSR_GPSR(IP0_22_21, A2), 863 PINMUX_IPSR_MSEL(IP0_22_21, MSIOF0_SS1_B, SEL_SOF0_1), 864 PINMUX_IPSR_GPSR(IP0_24_23, A3), 865 PINMUX_IPSR_MSEL(IP0_24_23, MSIOF0_SS2_B, SEL_SOF0_1), 866 PINMUX_IPSR_GPSR(IP0_26_25, A4), 867 PINMUX_IPSR_MSEL(IP0_26_25, MSIOF0_TXD_B, SEL_SOF0_1), 868 PINMUX_IPSR_GPSR(IP0_28_27, A5), 869 PINMUX_IPSR_MSEL(IP0_28_27, MSIOF0_RXD_B, SEL_SOF0_1), 870 PINMUX_IPSR_GPSR(IP0_30_29, A6), 871 PINMUX_IPSR_MSEL(IP0_30_29, MSIOF1_SCK, SEL_SOF1_0), 872 873 /* IPSR1 */ 874 PINMUX_IPSR_GPSR(IP1_1_0, A7), 875 PINMUX_IPSR_MSEL(IP1_1_0, MSIOF1_SYNC, SEL_SOF1_0), 876 PINMUX_IPSR_GPSR(IP1_3_2, A8), 877 PINMUX_IPSR_MSEL(IP1_3_2, MSIOF1_SS1, SEL_SOF1_0), 878 PINMUX_IPSR_MSEL(IP1_3_2, I2C0_SCL, SEL_I2C0_0), 879 PINMUX_IPSR_GPSR(IP1_5_4, A9), 880 PINMUX_IPSR_MSEL(IP1_5_4, MSIOF1_SS2, SEL_SOF1_0), 881 PINMUX_IPSR_MSEL(IP1_5_4, I2C0_SDA, SEL_I2C0_0), 882 PINMUX_IPSR_GPSR(IP1_7_6, A10), 883 PINMUX_IPSR_MSEL(IP1_7_6, MSIOF1_TXD, SEL_SOF1_0), 884 PINMUX_IPSR_MSEL(IP1_7_6, MSIOF1_TXD_D, SEL_SOF1_3), 885 PINMUX_IPSR_GPSR(IP1_10_8, A11), 886 PINMUX_IPSR_MSEL(IP1_10_8, MSIOF1_RXD, SEL_SOF1_0), 887 PINMUX_IPSR_MSEL(IP1_10_8, I2C3_SCL_D, SEL_I2C3_3), 888 PINMUX_IPSR_MSEL(IP1_10_8, MSIOF1_RXD_D, SEL_SOF1_3), 889 PINMUX_IPSR_GPSR(IP1_13_11, A12), 890 PINMUX_IPSR_MSEL(IP1_13_11, FMCLK, SEL_FM_0), 891 PINMUX_IPSR_MSEL(IP1_13_11, I2C3_SDA_D, SEL_I2C3_3), 892 PINMUX_IPSR_MSEL(IP1_13_11, MSIOF1_SCK_D, SEL_SOF1_3), 893 PINMUX_IPSR_GPSR(IP1_16_14, A13), 894 PINMUX_IPSR_MSEL(IP1_16_14, ATAG0_N_C, SEL_LBS_2), 895 PINMUX_IPSR_MSEL(IP1_16_14, BPFCLK, SEL_FM_0), 896 PINMUX_IPSR_MSEL(IP1_16_14, MSIOF1_SS1_D, SEL_SOF1_3), 897 PINMUX_IPSR_GPSR(IP1_19_17, A14), 898 PINMUX_IPSR_MSEL(IP1_19_17, ATADIR0_N_C, SEL_LBS_2), 899 PINMUX_IPSR_MSEL(IP1_19_17, FMIN, SEL_FM_0), 900 PINMUX_IPSR_MSEL(IP1_19_17, FMIN_C, SEL_FM_2), 901 PINMUX_IPSR_MSEL(IP1_19_17, MSIOF1_SYNC_D, SEL_SOF1_3), 902 PINMUX_IPSR_GPSR(IP1_22_20, A15), 903 PINMUX_IPSR_MSEL(IP1_22_20, BPFCLK_C, SEL_FM_2), 904 PINMUX_IPSR_GPSR(IP1_25_23, A16), 905 PINMUX_IPSR_MSEL(IP1_25_23, DREQ2_B, SEL_LBS_1), 906 PINMUX_IPSR_MSEL(IP1_25_23, FMCLK_C, SEL_FM_2), 907 PINMUX_IPSR_MSEL(IP1_25_23, SCIFA1_SCK_B, SEL_SCIFA1_1), 908 PINMUX_IPSR_GPSR(IP1_28_26, A17), 909 PINMUX_IPSR_MSEL(IP1_28_26, DACK2_B, SEL_LBS_1), 910 PINMUX_IPSR_MSEL(IP1_28_26, I2C0_SDA_C, SEL_I2C0_2), 911 PINMUX_IPSR_GPSR(IP1_31_29, A18), 912 PINMUX_IPSR_MSEL(IP1_31_29, DREQ1, SEL_LBS_0), 913 PINMUX_IPSR_MSEL(IP1_31_29, SCIFA1_RXD_C, SEL_SCIFA1_2), 914 PINMUX_IPSR_MSEL(IP1_31_29, SCIFB1_RXD_C, SEL_SCIFB1_2), 915 916 /* IPSR2 */ 917 PINMUX_IPSR_GPSR(IP2_2_0, A19), 918 PINMUX_IPSR_GPSR(IP2_2_0, DACK1), 919 PINMUX_IPSR_MSEL(IP2_2_0, SCIFA1_TXD_C, SEL_SCIFA1_2), 920 PINMUX_IPSR_MSEL(IP2_2_0, SCIFB1_TXD_C, SEL_SCIFB1_2), 921 PINMUX_IPSR_MSEL(IP2_2_0, SCIFB1_SCK_B, SEL_SCIFB1_1), 922 PINMUX_IPSR_GPSR(IP2_2_0, A20), 923 PINMUX_IPSR_MSEL(IP2_4_3, SPCLK, SEL_QSP_0), 924 PINMUX_IPSR_GPSR(IP2_6_5, A21), 925 PINMUX_IPSR_MSEL(IP2_6_5, ATAWR0_N_B, SEL_LBS_1), 926 PINMUX_IPSR_MSEL(IP2_6_5, MOSI_IO0, SEL_QSP_0), 927 PINMUX_IPSR_GPSR(IP2_9_7, A22), 928 PINMUX_IPSR_MSEL(IP2_9_7, MISO_IO1, SEL_QSP_0), 929 PINMUX_IPSR_MSEL(IP2_9_7, FMCLK_B, SEL_FM_1), 930 PINMUX_IPSR_MSEL(IP2_9_7, TX0, SEL_SCIF0_0), 931 PINMUX_IPSR_MSEL(IP2_9_7, SCIFA0_TXD, SEL_SCFA_0), 932 PINMUX_IPSR_GPSR(IP2_12_10, A23), 933 PINMUX_IPSR_MSEL(IP2_12_10, IO2, SEL_QSP_0), 934 PINMUX_IPSR_MSEL(IP2_12_10, BPFCLK_B, SEL_FM_1), 935 PINMUX_IPSR_MSEL(IP2_12_10, RX0, SEL_SCIF0_0), 936 PINMUX_IPSR_MSEL(IP2_12_10, SCIFA0_RXD, SEL_SCFA_0), 937 PINMUX_IPSR_GPSR(IP2_15_13, A24), 938 PINMUX_IPSR_MSEL(IP2_15_13, DREQ2, SEL_LBS_0), 939 PINMUX_IPSR_MSEL(IP2_15_13, IO3, SEL_QSP_0), 940 PINMUX_IPSR_MSEL(IP2_15_13, TX1, SEL_SCIF1_0), 941 PINMUX_IPSR_MSEL(IP2_15_13, SCIFA1_TXD, SEL_SCIFA1_0), 942 PINMUX_IPSR_GPSR(IP2_18_16, A25), 943 PINMUX_IPSR_MSEL(IP2_18_16, DACK2, SEL_LBS_0), 944 PINMUX_IPSR_MSEL(IP2_18_16, SSL, SEL_QSP_0), 945 PINMUX_IPSR_MSEL(IP2_18_16, DREQ1_C, SEL_LBS_2), 946 PINMUX_IPSR_MSEL(IP2_18_16, RX1, SEL_SCIF1_0), 947 PINMUX_IPSR_MSEL(IP2_18_16, SCIFA1_RXD, SEL_SCIFA1_0), 948 PINMUX_IPSR_GPSR(IP2_20_19, CS0_N), 949 PINMUX_IPSR_MSEL(IP2_20_19, ATAG0_N_B, SEL_LBS_1), 950 PINMUX_IPSR_MSEL(IP2_20_19, I2C1_SCL, SEL_I2C1_0), 951 PINMUX_IPSR_GPSR(IP2_22_21, CS1_N_A26), 952 PINMUX_IPSR_MSEL(IP2_22_21, ATADIR0_N_B, SEL_LBS_1), 953 PINMUX_IPSR_MSEL(IP2_22_21, I2C1_SDA, SEL_I2C1_0), 954 PINMUX_IPSR_GPSR(IP2_24_23, EX_CS1_N), 955 PINMUX_IPSR_MSEL(IP2_24_23, MSIOF2_SCK, SEL_SOF2_0), 956 PINMUX_IPSR_GPSR(IP2_26_25, EX_CS2_N), 957 PINMUX_IPSR_MSEL(IP2_26_25, ATAWR0_N, SEL_LBS_0), 958 PINMUX_IPSR_MSEL(IP2_26_25, MSIOF2_SYNC, SEL_SOF2_0), 959 PINMUX_IPSR_GPSR(IP2_29_27, EX_CS3_N), 960 PINMUX_IPSR_MSEL(IP2_29_27, ATADIR0_N, SEL_LBS_0), 961 PINMUX_IPSR_MSEL(IP2_29_27, MSIOF2_TXD, SEL_SOF2_0), 962 PINMUX_IPSR_MSEL(IP2_29_27, ATAG0_N, SEL_LBS_0), 963 PINMUX_IPSR_GPSR(IP2_29_27, EX_WAIT1), 964 965 /* IPSR3 */ 966 PINMUX_IPSR_GPSR(IP3_2_0, EX_CS4_N), 967 PINMUX_IPSR_MSEL(IP3_2_0, ATARD0_N, SEL_LBS_0), 968 PINMUX_IPSR_MSEL(IP3_2_0, MSIOF2_RXD, SEL_SOF2_0), 969 PINMUX_IPSR_GPSR(IP3_2_0, EX_WAIT2), 970 PINMUX_IPSR_GPSR(IP3_5_3, EX_CS5_N), 971 PINMUX_IPSR_GPSR(IP3_5_3, ATACS00_N), 972 PINMUX_IPSR_MSEL(IP3_5_3, MSIOF2_SS1, SEL_SOF2_0), 973 PINMUX_IPSR_MSEL(IP3_5_3, HRX1_B, SEL_HSCIF1_1), 974 PINMUX_IPSR_MSEL(IP3_5_3, SCIFB1_RXD_B, SEL_SCIFB1_1), 975 PINMUX_IPSR_GPSR(IP3_5_3, PWM1), 976 PINMUX_IPSR_GPSR(IP3_5_3, TPU_TO1), 977 PINMUX_IPSR_GPSR(IP3_8_6, BS_N), 978 PINMUX_IPSR_GPSR(IP3_8_6, ATACS10_N), 979 PINMUX_IPSR_MSEL(IP3_8_6, MSIOF2_SS2, SEL_SOF2_0), 980 PINMUX_IPSR_MSEL(IP3_8_6, HTX1_B, SEL_HSCIF1_1), 981 PINMUX_IPSR_MSEL(IP3_8_6, SCIFB1_TXD_B, SEL_SCIFB1_1), 982 PINMUX_IPSR_GPSR(IP3_8_6, PWM2), 983 PINMUX_IPSR_GPSR(IP3_8_6, TPU_TO2), 984 PINMUX_IPSR_GPSR(IP3_11_9, RD_WR_N), 985 PINMUX_IPSR_MSEL(IP3_11_9, HRX2_B, SEL_HSCIF2_1), 986 PINMUX_IPSR_MSEL(IP3_11_9, FMIN_B, SEL_FM_1), 987 PINMUX_IPSR_MSEL(IP3_11_9, SCIFB0_RXD_B, SEL_SCIFB_1), 988 PINMUX_IPSR_MSEL(IP3_11_9, DREQ1_D, SEL_LBS_1), 989 PINMUX_IPSR_GPSR(IP3_13_12, WE0_N), 990 PINMUX_IPSR_MSEL(IP3_13_12, HCTS2_N_B, SEL_HSCIF2_1), 991 PINMUX_IPSR_MSEL(IP3_13_12, SCIFB0_TXD_B, SEL_SCIFB_1), 992 PINMUX_IPSR_GPSR(IP3_15_14, WE1_N), 993 PINMUX_IPSR_MSEL(IP3_15_14, ATARD0_N_B, SEL_LBS_1), 994 PINMUX_IPSR_MSEL(IP3_15_14, HTX2_B, SEL_HSCIF2_1), 995 PINMUX_IPSR_MSEL(IP3_15_14, SCIFB0_RTS_N_B, SEL_SCIFB_1), 996 PINMUX_IPSR_GPSR(IP3_17_16, EX_WAIT0), 997 PINMUX_IPSR_MSEL(IP3_17_16, HRTS2_N_B, SEL_HSCIF2_1), 998 PINMUX_IPSR_MSEL(IP3_17_16, SCIFB0_CTS_N_B, SEL_SCIFB_1), 999 PINMUX_IPSR_GPSR(IP3_19_18, DREQ0), 1000 PINMUX_IPSR_GPSR(IP3_19_18, PWM3), 1001 PINMUX_IPSR_GPSR(IP3_19_18, TPU_TO3), 1002 PINMUX_IPSR_GPSR(IP3_21_20, DACK0), 1003 PINMUX_IPSR_GPSR(IP3_21_20, DRACK0), 1004 PINMUX_IPSR_MSEL(IP3_21_20, REMOCON, SEL_RCN_0), 1005 PINMUX_IPSR_MSEL(IP3_24_22, SPEEDIN, SEL_RSP_0), 1006 PINMUX_IPSR_MSEL(IP3_24_22, HSCK0_C, SEL_HSCIF0_2), 1007 PINMUX_IPSR_MSEL(IP3_24_22, HSCK2_C, SEL_HSCIF2_2), 1008 PINMUX_IPSR_MSEL(IP3_24_22, SCIFB0_SCK_B, SEL_SCIFB_1), 1009 PINMUX_IPSR_MSEL(IP3_24_22, SCIFB2_SCK_B, SEL_SCIFB2_1), 1010 PINMUX_IPSR_MSEL(IP3_24_22, DREQ2_C, SEL_LBS_2), 1011 PINMUX_IPSR_MSEL(IP3_30_28, HTX2_C, SEL_HSCIF2_2), 1012 PINMUX_IPSR_MSEL(IP3_27_25, SSI_SCK0129, SEL_SSI0_0), 1013 PINMUX_IPSR_MSEL(IP3_27_25, HRX0_C, SEL_HSCIF0_2), 1014 PINMUX_IPSR_MSEL(IP3_27_25, HRX2_C, SEL_HSCIF2_2), 1015 PINMUX_IPSR_MSEL(IP3_27_25, SCIFB0_RXD_C, SEL_SCIFB_2), 1016 PINMUX_IPSR_MSEL(IP3_27_25, SCIFB2_RXD_C, SEL_SCIFB2_2), 1017 PINMUX_IPSR_MSEL(IP3_30_28, SSI_WS0129, SEL_SSI0_0), 1018 PINMUX_IPSR_MSEL(IP3_30_28, HTX0_C, SEL_HSCIF0_2), 1019 PINMUX_IPSR_MSEL(IP3_30_28, HTX2_C, SEL_HSCIF2_2), 1020 PINMUX_IPSR_MSEL(IP3_30_28, SCIFB0_TXD_C, SEL_SCIFB_2), 1021 PINMUX_IPSR_MSEL(IP3_30_28, SCIFB2_TXD_C, SEL_SCIFB2_2), 1022 1023 /* IPSR4 */ 1024 PINMUX_IPSR_MSEL(IP4_1_0, SSI_SDATA0, SEL_SSI0_0), 1025 PINMUX_IPSR_MSEL(IP4_1_0, I2C0_SCL_B, SEL_I2C0_1), 1026 PINMUX_IPSR_MSEL(IP4_1_0, IIC0_SCL_B, SEL_IIC0_1), 1027 PINMUX_IPSR_MSEL(IP4_1_0, MSIOF2_SCK_C, SEL_SOF2_2), 1028 PINMUX_IPSR_MSEL(IP4_4_2, SSI_SCK1, SEL_SSI1_0), 1029 PINMUX_IPSR_MSEL(IP4_4_2, I2C0_SDA_B, SEL_I2C0_1), 1030 PINMUX_IPSR_MSEL(IP4_4_2, IIC0_SDA_B, SEL_IIC0_1), 1031 PINMUX_IPSR_MSEL(IP4_4_2, MSIOF2_SYNC_C, SEL_SOF2_2), 1032 PINMUX_IPSR_MSEL(IP4_4_2, GLO_I0_D, SEL_GPS_3), 1033 PINMUX_IPSR_MSEL(IP4_7_5, SSI_WS1, SEL_SSI1_0), 1034 PINMUX_IPSR_MSEL(IP4_7_5, I2C1_SCL_B, SEL_I2C1_1), 1035 PINMUX_IPSR_MSEL(IP4_7_5, IIC1_SCL_B, SEL_IIC1_1), 1036 PINMUX_IPSR_MSEL(IP4_7_5, MSIOF2_TXD_C, SEL_SOF2_2), 1037 PINMUX_IPSR_MSEL(IP4_7_5, GLO_I1_D, SEL_GPS_3), 1038 PINMUX_IPSR_MSEL(IP4_9_8, SSI_SDATA1, SEL_SSI1_0), 1039 PINMUX_IPSR_MSEL(IP4_9_8, I2C1_SDA_B, SEL_I2C1_1), 1040 PINMUX_IPSR_MSEL(IP4_9_8, IIC1_SDA_B, SEL_IIC1_1), 1041 PINMUX_IPSR_MSEL(IP4_9_8, MSIOF2_RXD_C, SEL_SOF2_2), 1042 PINMUX_IPSR_GPSR(IP4_12_10, SSI_SCK2), 1043 PINMUX_IPSR_MSEL(IP4_12_10, I2C2_SCL, SEL_I2C2_0), 1044 PINMUX_IPSR_MSEL(IP4_12_10, GPS_CLK_B, SEL_GPS_1), 1045 PINMUX_IPSR_MSEL(IP4_12_10, GLO_Q0_D, SEL_GPS_3), 1046 PINMUX_IPSR_MSEL(IP4_12_10, HSCK1_E, SEL_HSCIF1_4), 1047 PINMUX_IPSR_GPSR(IP4_15_13, SSI_WS2), 1048 PINMUX_IPSR_MSEL(IP4_15_13, I2C2_SDA, SEL_I2C2_0), 1049 PINMUX_IPSR_MSEL(IP4_15_13, GPS_SIGN_B, SEL_GPS_1), 1050 PINMUX_IPSR_MSEL(IP4_15_13, RX2_E, SEL_SCIF2_4), 1051 PINMUX_IPSR_MSEL(IP4_15_13, GLO_Q1_D, SEL_GPS_3), 1052 PINMUX_IPSR_MSEL(IP4_15_13, HCTS1_N_E, SEL_HSCIF1_4), 1053 PINMUX_IPSR_GPSR(IP4_18_16, SSI_SDATA2), 1054 PINMUX_IPSR_MSEL(IP4_18_16, GPS_MAG_B, SEL_GPS_1), 1055 PINMUX_IPSR_MSEL(IP4_18_16, TX2_E, SEL_SCIF2_4), 1056 PINMUX_IPSR_MSEL(IP4_18_16, HRTS1_N_E, SEL_HSCIF1_4), 1057 PINMUX_IPSR_GPSR(IP4_19, SSI_SCK34), 1058 PINMUX_IPSR_GPSR(IP4_20, SSI_WS34), 1059 PINMUX_IPSR_GPSR(IP4_21, SSI_SDATA3), 1060 PINMUX_IPSR_GPSR(IP4_23_22, SSI_SCK4), 1061 PINMUX_IPSR_MSEL(IP4_23_22, GLO_SS_D, SEL_GPS_3), 1062 PINMUX_IPSR_GPSR(IP4_25_24, SSI_WS4), 1063 PINMUX_IPSR_MSEL(IP4_25_24, GLO_RFON_D, SEL_GPS_3), 1064 PINMUX_IPSR_GPSR(IP4_27_26, SSI_SDATA4), 1065 PINMUX_IPSR_MSEL(IP4_27_26, MSIOF2_SCK_D, SEL_SOF2_3), 1066 PINMUX_IPSR_GPSR(IP4_30_28, SSI_SCK5), 1067 PINMUX_IPSR_MSEL(IP4_30_28, MSIOF1_SCK_C, SEL_SOF1_2), 1068 PINMUX_IPSR_MSEL(IP4_30_28, TS_SDATA0, SEL_TSIF0_0), 1069 PINMUX_IPSR_MSEL(IP4_30_28, GLO_I0, SEL_GPS_0), 1070 PINMUX_IPSR_MSEL(IP4_30_28, MSIOF2_SYNC_D, SEL_SOF2_3), 1071 PINMUX_IPSR_GPSR(IP4_30_28, VI1_R2_B), 1072 1073 /* IPSR5 */ 1074 PINMUX_IPSR_GPSR(IP5_2_0, SSI_WS5), 1075 PINMUX_IPSR_MSEL(IP5_2_0, MSIOF1_SYNC_C, SEL_SOF1_2), 1076 PINMUX_IPSR_MSEL(IP5_2_0, TS_SCK0, SEL_TSIF0_0), 1077 PINMUX_IPSR_MSEL(IP5_2_0, GLO_I1, SEL_GPS_0), 1078 PINMUX_IPSR_MSEL(IP5_2_0, MSIOF2_TXD_D, SEL_SOF2_3), 1079 PINMUX_IPSR_GPSR(IP5_2_0, VI1_R3_B), 1080 PINMUX_IPSR_GPSR(IP5_5_3, SSI_SDATA5), 1081 PINMUX_IPSR_MSEL(IP5_5_3, MSIOF1_TXD_C, SEL_SOF1_2), 1082 PINMUX_IPSR_MSEL(IP5_5_3, TS_SDEN0, SEL_TSIF0_0), 1083 PINMUX_IPSR_MSEL(IP5_5_3, GLO_Q0, SEL_GPS_0), 1084 PINMUX_IPSR_MSEL(IP5_5_3, MSIOF2_SS1_D, SEL_SOF2_3), 1085 PINMUX_IPSR_GPSR(IP5_5_3, VI1_R4_B), 1086 PINMUX_IPSR_GPSR(IP5_8_6, SSI_SCK6), 1087 PINMUX_IPSR_MSEL(IP5_8_6, MSIOF1_RXD_C, SEL_SOF1_2), 1088 PINMUX_IPSR_MSEL(IP5_8_6, TS_SPSYNC0, SEL_TSIF0_0), 1089 PINMUX_IPSR_MSEL(IP5_8_6, GLO_Q1, SEL_GPS_0), 1090 PINMUX_IPSR_MSEL(IP5_8_6, MSIOF2_RXD_D, SEL_SOF2_3), 1091 PINMUX_IPSR_GPSR(IP5_8_6, VI1_R5_B), 1092 PINMUX_IPSR_GPSR(IP5_11_9, SSI_WS6), 1093 PINMUX_IPSR_MSEL(IP5_11_9, GLO_SCLK, SEL_GPS_0), 1094 PINMUX_IPSR_MSEL(IP5_11_9, MSIOF2_SS2_D, SEL_SOF2_3), 1095 PINMUX_IPSR_GPSR(IP5_11_9, VI1_R6_B), 1096 PINMUX_IPSR_GPSR(IP5_14_12, SSI_SDATA6), 1097 PINMUX_IPSR_MSEL(IP5_14_12, STP_IVCXO27_0_B, SEL_SSP_1), 1098 PINMUX_IPSR_MSEL(IP5_14_12, GLO_SDATA, SEL_GPS_0), 1099 PINMUX_IPSR_GPSR(IP5_14_12, VI1_R7_B), 1100 PINMUX_IPSR_MSEL(IP5_16_15, SSI_SCK78, SEL_SSI7_0), 1101 PINMUX_IPSR_MSEL(IP5_16_15, STP_ISCLK_0_B, SEL_SSP_1), 1102 PINMUX_IPSR_MSEL(IP5_16_15, GLO_SS, SEL_GPS_0), 1103 PINMUX_IPSR_MSEL(IP5_19_17, SSI_WS78, SEL_SSI7_0), 1104 PINMUX_IPSR_MSEL(IP5_19_17, TX0_D, SEL_SCIF0_3), 1105 PINMUX_IPSR_MSEL(IP5_19_17, STP_ISD_0_B, SEL_SSP_1), 1106 PINMUX_IPSR_MSEL(IP5_19_17, GLO_RFON, SEL_GPS_0), 1107 PINMUX_IPSR_MSEL(IP5_21_20, SSI_SDATA7, SEL_SSI7_0), 1108 PINMUX_IPSR_MSEL(IP5_21_20, RX0_D, SEL_SCIF0_3), 1109 PINMUX_IPSR_MSEL(IP5_21_20, STP_ISEN_0_B, SEL_SSP_1), 1110 PINMUX_IPSR_MSEL(IP5_23_22, SSI_SDATA8, SEL_SSI8_0), 1111 PINMUX_IPSR_MSEL(IP5_23_22, TX1_D, SEL_SCIF1_3), 1112 PINMUX_IPSR_MSEL(IP5_23_22, STP_ISSYNC_0_B, SEL_SSP_1), 1113 PINMUX_IPSR_MSEL(IP5_25_24, SSI_SCK9, SEL_SSI9_0), 1114 PINMUX_IPSR_MSEL(IP5_25_24, RX1_D, SEL_SCIF1_3), 1115 PINMUX_IPSR_MSEL(IP5_25_24, GLO_SCLK_D, SEL_GPS_3), 1116 PINMUX_IPSR_MSEL(IP5_28_26, SSI_WS9, SEL_SSI9_0), 1117 PINMUX_IPSR_MSEL(IP5_28_26, TX3_D, SEL_SCIF3_3), 1118 PINMUX_IPSR_MSEL(IP5_28_26, CAN0_TX_D, SEL_CAN0_3), 1119 PINMUX_IPSR_MSEL(IP5_28_26, GLO_SDATA_D, SEL_GPS_3), 1120 PINMUX_IPSR_MSEL(IP5_31_29, SSI_SDATA9, SEL_SSI9_0), 1121 PINMUX_IPSR_MSEL(IP5_31_29, RX3_D, SEL_SCIF3_3), 1122 PINMUX_IPSR_MSEL(IP5_31_29, CAN0_RX_D, SEL_CAN0_3), 1123 1124 /* IPSR6 */ 1125 PINMUX_IPSR_MSEL(IP6_2_0, AUDIO_CLKB, SEL_ADG_0), 1126 PINMUX_IPSR_MSEL(IP6_2_0, STP_OPWM_0_B, SEL_SSP_1), 1127 PINMUX_IPSR_MSEL(IP6_2_0, MSIOF1_SCK_B, SEL_SOF1_1), 1128 PINMUX_IPSR_MSEL(IP6_2_0, SCIF_CLK, SEL_SCIF_0), 1129 PINMUX_IPSR_GPSR(IP6_2_0, DVC_MUTE), 1130 PINMUX_IPSR_MSEL(IP6_2_0, BPFCLK_E, SEL_FM_4), 1131 PINMUX_IPSR_GPSR(IP6_5_3, AUDIO_CLKC), 1132 PINMUX_IPSR_MSEL(IP6_5_3, SCIFB0_SCK_C, SEL_SCIFB_2), 1133 PINMUX_IPSR_MSEL(IP6_5_3, MSIOF1_SYNC_B, SEL_SOF1_1), 1134 PINMUX_IPSR_MSEL(IP6_5_3, RX2, SEL_SCIF2_0), 1135 PINMUX_IPSR_MSEL(IP6_5_3, SCIFA2_RXD, SEL_SCIFA2_0), 1136 PINMUX_IPSR_MSEL(IP6_5_3, FMIN_E, SEL_FM_4), 1137 PINMUX_IPSR_GPSR(IP6_7_6, AUDIO_CLKOUT), 1138 PINMUX_IPSR_MSEL(IP6_7_6, MSIOF1_SS1_B, SEL_SOF1_1), 1139 PINMUX_IPSR_MSEL(IP6_7_6, TX2, SEL_SCIF2_0), 1140 PINMUX_IPSR_MSEL(IP6_7_6, SCIFA2_TXD, SEL_SCIFA2_0), 1141 PINMUX_IPSR_GPSR(IP6_9_8, IRQ0), 1142 PINMUX_IPSR_MSEL(IP6_9_8, SCIFB1_RXD_D, SEL_SCIFB1_3), 1143 PINMUX_IPSR_GPSR(IP6_11_10, IRQ1), 1144 PINMUX_IPSR_MSEL(IP6_11_10, SCIFB1_SCK_C, SEL_SCIFB1_2), 1145 PINMUX_IPSR_GPSR(IP6_13_12, IRQ2), 1146 PINMUX_IPSR_MSEL(IP6_13_12, SCIFB1_TXD_D, SEL_SCIFB1_3), 1147 PINMUX_IPSR_GPSR(IP6_15_14, IRQ3), 1148 PINMUX_IPSR_MSEL(IP6_15_14, I2C4_SCL_C, SEL_I2C4_2), 1149 PINMUX_IPSR_MSEL(IP6_15_14, MSIOF2_TXD_E, SEL_SOF2_4), 1150 PINMUX_IPSR_GPSR(IP6_18_16, IRQ4), 1151 PINMUX_IPSR_MSEL(IP6_18_16, HRX1_C, SEL_HSCIF1_2), 1152 PINMUX_IPSR_MSEL(IP6_18_16, I2C4_SDA_C, SEL_I2C4_2), 1153 PINMUX_IPSR_MSEL(IP6_18_16, MSIOF2_RXD_E, SEL_SOF2_4), 1154 PINMUX_IPSR_GPSR(IP6_20_19, IRQ5), 1155 PINMUX_IPSR_MSEL(IP6_20_19, HTX1_C, SEL_HSCIF1_2), 1156 PINMUX_IPSR_MSEL(IP6_20_19, I2C1_SCL_E, SEL_I2C1_4), 1157 PINMUX_IPSR_MSEL(IP6_20_19, MSIOF2_SCK_E, SEL_SOF2_4), 1158 PINMUX_IPSR_GPSR(IP6_23_21, IRQ6), 1159 PINMUX_IPSR_MSEL(IP6_23_21, HSCK1_C, SEL_HSCIF1_2), 1160 PINMUX_IPSR_MSEL(IP6_23_21, MSIOF1_SS2_B, SEL_SOF1_1), 1161 PINMUX_IPSR_MSEL(IP6_23_21, I2C1_SDA_E, SEL_I2C1_4), 1162 PINMUX_IPSR_MSEL(IP6_23_21, MSIOF2_SYNC_E, SEL_SOF2_4), 1163 PINMUX_IPSR_GPSR(IP6_26_24, IRQ7), 1164 PINMUX_IPSR_MSEL(IP6_26_24, HCTS1_N_C, SEL_HSCIF1_2), 1165 PINMUX_IPSR_MSEL(IP6_26_24, MSIOF1_TXD_B, SEL_SOF1_1), 1166 PINMUX_IPSR_MSEL(IP6_26_24, GPS_CLK_C, SEL_GPS_2), 1167 PINMUX_IPSR_MSEL(IP6_26_24, GPS_CLK_D, SEL_GPS_3), 1168 PINMUX_IPSR_GPSR(IP6_29_27, IRQ8), 1169 PINMUX_IPSR_MSEL(IP6_29_27, HRTS1_N_C, SEL_HSCIF1_2), 1170 PINMUX_IPSR_MSEL(IP6_29_27, MSIOF1_RXD_B, SEL_SOF1_1), 1171 PINMUX_IPSR_MSEL(IP6_29_27, GPS_SIGN_C, SEL_GPS_2), 1172 PINMUX_IPSR_MSEL(IP6_29_27, GPS_SIGN_D, SEL_GPS_3), 1173 1174 /* IPSR7 */ 1175 PINMUX_IPSR_GPSR(IP7_2_0, IRQ9), 1176 PINMUX_IPSR_MSEL(IP7_2_0, DU1_DOTCLKIN_B, SEL_DIS_1), 1177 PINMUX_IPSR_MSEL(IP7_2_0, CAN_CLK_D, SEL_CANCLK_3), 1178 PINMUX_IPSR_MSEL(IP7_2_0, GPS_MAG_C, SEL_GPS_2), 1179 PINMUX_IPSR_MSEL(IP7_2_0, SCIF_CLK_B, SEL_SCIF_1), 1180 PINMUX_IPSR_MSEL(IP7_2_0, GPS_MAG_D, SEL_GPS_3), 1181 PINMUX_IPSR_GPSR(IP7_5_3, DU1_DR0), 1182 PINMUX_IPSR_GPSR(IP7_5_3, LCDOUT0), 1183 PINMUX_IPSR_MSEL(IP7_5_3, VI1_DATA0_B, SEL_VI1_1), 1184 PINMUX_IPSR_MSEL(IP7_5_3, TX0_B, SEL_SCIF0_1), 1185 PINMUX_IPSR_MSEL(IP7_5_3, SCIFA0_TXD_B, SEL_SCFA_1), 1186 PINMUX_IPSR_MSEL(IP7_5_3, MSIOF2_SCK_B, SEL_SOF2_1), 1187 PINMUX_IPSR_GPSR(IP7_8_6, DU1_DR1), 1188 PINMUX_IPSR_GPSR(IP7_8_6, LCDOUT1), 1189 PINMUX_IPSR_MSEL(IP7_8_6, VI1_DATA1_B, SEL_VI1_1), 1190 PINMUX_IPSR_MSEL(IP7_8_6, RX0_B, SEL_SCIF0_1), 1191 PINMUX_IPSR_MSEL(IP7_8_6, SCIFA0_RXD_B, SEL_SCFA_1), 1192 PINMUX_IPSR_MSEL(IP7_8_6, MSIOF2_SYNC_B, SEL_SOF2_1), 1193 PINMUX_IPSR_GPSR(IP7_10_9, DU1_DR2), 1194 PINMUX_IPSR_GPSR(IP7_10_9, LCDOUT2), 1195 PINMUX_IPSR_MSEL(IP7_10_9, SSI_SCK0129_B, SEL_SSI0_1), 1196 PINMUX_IPSR_GPSR(IP7_12_11, DU1_DR3), 1197 PINMUX_IPSR_GPSR(IP7_12_11, LCDOUT3), 1198 PINMUX_IPSR_MSEL(IP7_12_11, SSI_WS0129_B, SEL_SSI0_1), 1199 PINMUX_IPSR_GPSR(IP7_14_13, DU1_DR4), 1200 PINMUX_IPSR_GPSR(IP7_14_13, LCDOUT4), 1201 PINMUX_IPSR_MSEL(IP7_14_13, SSI_SDATA0_B, SEL_SSI0_1), 1202 PINMUX_IPSR_GPSR(IP7_16_15, DU1_DR5), 1203 PINMUX_IPSR_GPSR(IP7_16_15, LCDOUT5), 1204 PINMUX_IPSR_MSEL(IP7_16_15, SSI_SCK1_B, SEL_SSI1_1), 1205 PINMUX_IPSR_GPSR(IP7_18_17, DU1_DR6), 1206 PINMUX_IPSR_GPSR(IP7_18_17, LCDOUT6), 1207 PINMUX_IPSR_MSEL(IP7_18_17, SSI_WS1_B, SEL_SSI1_1), 1208 PINMUX_IPSR_GPSR(IP7_20_19, DU1_DR7), 1209 PINMUX_IPSR_GPSR(IP7_20_19, LCDOUT7), 1210 PINMUX_IPSR_MSEL(IP7_20_19, SSI_SDATA1_B, SEL_SSI1_1), 1211 PINMUX_IPSR_GPSR(IP7_23_21, DU1_DG0), 1212 PINMUX_IPSR_GPSR(IP7_23_21, LCDOUT8), 1213 PINMUX_IPSR_MSEL(IP7_23_21, VI1_DATA2_B, SEL_VI1_1), 1214 PINMUX_IPSR_MSEL(IP7_23_21, TX1_B, SEL_SCIF1_1), 1215 PINMUX_IPSR_MSEL(IP7_23_21, SCIFA1_TXD_B, SEL_SCIFA1_1), 1216 PINMUX_IPSR_MSEL(IP7_23_21, MSIOF2_SS1_B, SEL_SOF2_1), 1217 PINMUX_IPSR_GPSR(IP7_26_24, DU1_DG1), 1218 PINMUX_IPSR_GPSR(IP7_26_24, LCDOUT9), 1219 PINMUX_IPSR_MSEL(IP7_26_24, VI1_DATA3_B, SEL_VI1_1), 1220 PINMUX_IPSR_MSEL(IP7_26_24, RX1_B, SEL_SCIF1_1), 1221 PINMUX_IPSR_MSEL(IP7_26_24, SCIFA1_RXD_B, SEL_SCIFA1_1), 1222 PINMUX_IPSR_MSEL(IP7_26_24, MSIOF2_SS2_B, SEL_SOF2_1), 1223 PINMUX_IPSR_GPSR(IP7_29_27, DU1_DG2), 1224 PINMUX_IPSR_GPSR(IP7_29_27, LCDOUT10), 1225 PINMUX_IPSR_MSEL(IP7_29_27, VI1_DATA4_B, SEL_VI1_1), 1226 PINMUX_IPSR_GPSR(IP7_29_27, SCIF1_SCK_B), 1227 PINMUX_IPSR_MSEL(IP7_29_27, SCIFA1_SCK, SEL_SCIFA1_0), 1228 PINMUX_IPSR_MSEL(IP7_29_27, SSI_SCK78_B, SEL_SSI7_1), 1229 1230 /* IPSR8 */ 1231 PINMUX_IPSR_GPSR(IP8_2_0, DU1_DG3), 1232 PINMUX_IPSR_GPSR(IP8_2_0, LCDOUT11), 1233 PINMUX_IPSR_MSEL(IP8_2_0, VI1_DATA5_B, SEL_VI1_1), 1234 PINMUX_IPSR_MSEL(IP8_2_0, SSI_WS78_B, SEL_SSI7_1), 1235 PINMUX_IPSR_GPSR(IP8_5_3, DU1_DG4), 1236 PINMUX_IPSR_GPSR(IP8_5_3, LCDOUT12), 1237 PINMUX_IPSR_MSEL(IP8_5_3, VI1_DATA6_B, SEL_VI1_1), 1238 PINMUX_IPSR_MSEL(IP8_5_3, HRX0_B, SEL_HSCIF0_1), 1239 PINMUX_IPSR_MSEL(IP8_5_3, SCIFB2_RXD_B, SEL_SCIFB2_1), 1240 PINMUX_IPSR_MSEL(IP8_5_3, SSI_SDATA7_B, SEL_SSI7_1), 1241 PINMUX_IPSR_GPSR(IP8_8_6, DU1_DG5), 1242 PINMUX_IPSR_GPSR(IP8_8_6, LCDOUT13), 1243 PINMUX_IPSR_MSEL(IP8_8_6, VI1_DATA7_B, SEL_VI1_1), 1244 PINMUX_IPSR_MSEL(IP8_8_6, HCTS0_N_B, SEL_HSCIF0_1), 1245 PINMUX_IPSR_MSEL(IP8_8_6, SCIFB2_TXD_B, SEL_SCIFB2_1), 1246 PINMUX_IPSR_MSEL(IP8_8_6, SSI_SDATA8_B, SEL_SSI8_1), 1247 PINMUX_IPSR_GPSR(IP8_11_9, DU1_DG6), 1248 PINMUX_IPSR_GPSR(IP8_11_9, LCDOUT14), 1249 PINMUX_IPSR_MSEL(IP8_11_9, HRTS0_N_B, SEL_HSCIF0_1), 1250 PINMUX_IPSR_MSEL(IP8_11_9, SCIFB2_CTS_N_B, SEL_SCIFB2_1), 1251 PINMUX_IPSR_MSEL(IP8_11_9, SSI_SCK9_B, SEL_SSI9_1), 1252 PINMUX_IPSR_GPSR(IP8_14_12, DU1_DG7), 1253 PINMUX_IPSR_GPSR(IP8_14_12, LCDOUT15), 1254 PINMUX_IPSR_MSEL(IP8_14_12, HTX0_B, SEL_HSCIF0_1), 1255 PINMUX_IPSR_MSEL(IP8_14_12, SCIFB2_RTS_N_B, SEL_SCIFB2_1), 1256 PINMUX_IPSR_MSEL(IP8_14_12, SSI_WS9_B, SEL_SSI9_1), 1257 PINMUX_IPSR_GPSR(IP8_17_15, DU1_DB0), 1258 PINMUX_IPSR_GPSR(IP8_17_15, LCDOUT16), 1259 PINMUX_IPSR_MSEL(IP8_17_15, VI1_CLK_B, SEL_VI1_1), 1260 PINMUX_IPSR_MSEL(IP8_17_15, TX2_B, SEL_SCIF2_1), 1261 PINMUX_IPSR_MSEL(IP8_17_15, SCIFA2_TXD_B, SEL_SCIFA2_1), 1262 PINMUX_IPSR_MSEL(IP8_17_15, MSIOF2_TXD_B, SEL_SOF2_1), 1263 PINMUX_IPSR_GPSR(IP8_20_18, DU1_DB1), 1264 PINMUX_IPSR_GPSR(IP8_20_18, LCDOUT17), 1265 PINMUX_IPSR_MSEL(IP8_20_18, VI1_HSYNC_N_B, SEL_VI1_1), 1266 PINMUX_IPSR_MSEL(IP8_20_18, RX2_B, SEL_SCIF2_1), 1267 PINMUX_IPSR_MSEL(IP8_20_18, SCIFA2_RXD_B, SEL_SCIFA2_1), 1268 PINMUX_IPSR_MSEL(IP8_20_18, MSIOF2_RXD_B, SEL_SOF2_1), 1269 PINMUX_IPSR_GPSR(IP8_23_21, DU1_DB2), 1270 PINMUX_IPSR_GPSR(IP8_23_21, LCDOUT18), 1271 PINMUX_IPSR_MSEL(IP8_23_21, VI1_VSYNC_N_B, SEL_VI1_1), 1272 PINMUX_IPSR_GPSR(IP8_23_21, SCIF2_SCK_B), 1273 PINMUX_IPSR_MSEL(IP8_23_21, SCIFA2_SCK, SEL_SCIFA2_1), 1274 PINMUX_IPSR_MSEL(IP8_23_21, SSI_SDATA9_B, SEL_SSI9_1), 1275 PINMUX_IPSR_GPSR(IP8_25_24, DU1_DB3), 1276 PINMUX_IPSR_GPSR(IP8_25_24, LCDOUT19), 1277 PINMUX_IPSR_MSEL(IP8_25_24, VI1_CLKENB_B, SEL_VI1_1), 1278 PINMUX_IPSR_GPSR(IP8_27_26, DU1_DB4), 1279 PINMUX_IPSR_GPSR(IP8_27_26, LCDOUT20), 1280 PINMUX_IPSR_MSEL(IP8_27_26, VI1_FIELD_B, SEL_VI1_1), 1281 PINMUX_IPSR_MSEL(IP8_27_26, CAN1_RX, SEL_CAN1_0), 1282 PINMUX_IPSR_GPSR(IP8_30_28, DU1_DB5), 1283 PINMUX_IPSR_GPSR(IP8_30_28, LCDOUT21), 1284 PINMUX_IPSR_MSEL(IP8_30_28, TX3, SEL_SCIF3_0), 1285 PINMUX_IPSR_MSEL(IP8_30_28, SCIFA3_TXD, SEL_SCIFA3_0), 1286 PINMUX_IPSR_MSEL(IP8_30_28, CAN1_TX, SEL_CAN1_0), 1287 1288 /* IPSR9 */ 1289 PINMUX_IPSR_GPSR(IP9_2_0, DU1_DB6), 1290 PINMUX_IPSR_GPSR(IP9_2_0, LCDOUT22), 1291 PINMUX_IPSR_MSEL(IP9_2_0, I2C3_SCL_C, SEL_I2C3_2), 1292 PINMUX_IPSR_MSEL(IP9_2_0, RX3, SEL_SCIF3_0), 1293 PINMUX_IPSR_MSEL(IP9_2_0, SCIFA3_RXD, SEL_SCIFA3_0), 1294 PINMUX_IPSR_GPSR(IP9_5_3, DU1_DB7), 1295 PINMUX_IPSR_GPSR(IP9_5_3, LCDOUT23), 1296 PINMUX_IPSR_MSEL(IP9_5_3, I2C3_SDA_C, SEL_I2C3_2), 1297 PINMUX_IPSR_MSEL(IP9_5_3, SCIF3_SCK, SEL_SCIF3_0), 1298 PINMUX_IPSR_MSEL(IP9_5_3, SCIFA3_SCK, SEL_SCIFA3_0), 1299 PINMUX_IPSR_MSEL(IP9_6, DU1_DOTCLKIN, SEL_DIS_0), 1300 PINMUX_IPSR_GPSR(IP9_6, QSTVA_QVS), 1301 PINMUX_IPSR_GPSR(IP9_7, DU1_DOTCLKOUT0), 1302 PINMUX_IPSR_GPSR(IP9_7, QCLK), 1303 PINMUX_IPSR_GPSR(IP9_10_8, DU1_DOTCLKOUT1), 1304 PINMUX_IPSR_GPSR(IP9_10_8, QSTVB_QVE), 1305 PINMUX_IPSR_MSEL(IP9_10_8, CAN0_TX, SEL_CAN0_0), 1306 PINMUX_IPSR_MSEL(IP9_10_8, TX3_B, SEL_SCIF3_1), 1307 PINMUX_IPSR_MSEL(IP9_10_8, I2C2_SCL_B, SEL_I2C2_1), 1308 PINMUX_IPSR_GPSR(IP9_10_8, PWM4), 1309 PINMUX_IPSR_GPSR(IP9_11, DU1_EXHSYNC_DU1_HSYNC), 1310 PINMUX_IPSR_GPSR(IP9_11, QSTH_QHS), 1311 PINMUX_IPSR_GPSR(IP9_12, DU1_EXVSYNC_DU1_VSYNC), 1312 PINMUX_IPSR_GPSR(IP9_12, QSTB_QHE), 1313 PINMUX_IPSR_GPSR(IP9_15_13, DU1_EXODDF_DU1_ODDF_DISP_CDE), 1314 PINMUX_IPSR_GPSR(IP9_15_13, QCPV_QDE), 1315 PINMUX_IPSR_MSEL(IP9_15_13, CAN0_RX, SEL_CAN0_0), 1316 PINMUX_IPSR_MSEL(IP9_15_13, RX3_B, SEL_SCIF3_1), 1317 PINMUX_IPSR_MSEL(IP9_15_13, I2C2_SDA_B, SEL_I2C2_1), 1318 PINMUX_IPSR_GPSR(IP9_16, DU1_DISP), 1319 PINMUX_IPSR_GPSR(IP9_16, QPOLA), 1320 PINMUX_IPSR_GPSR(IP9_18_17, DU1_CDE), 1321 PINMUX_IPSR_GPSR(IP9_18_17, QPOLB), 1322 PINMUX_IPSR_GPSR(IP9_18_17, PWM4_B), 1323 PINMUX_IPSR_GPSR(IP9_20_19, VI0_CLKENB), 1324 PINMUX_IPSR_MSEL(IP9_20_19, TX4, SEL_SCIF4_0), 1325 PINMUX_IPSR_MSEL(IP9_20_19, SCIFA4_TXD, SEL_SCIFA4_0), 1326 PINMUX_IPSR_MSEL(IP9_20_19, TS_SDATA0_D, SEL_TSIF0_3), 1327 PINMUX_IPSR_GPSR(IP9_22_21, VI0_FIELD), 1328 PINMUX_IPSR_MSEL(IP9_22_21, RX4, SEL_SCIF4_0), 1329 PINMUX_IPSR_MSEL(IP9_22_21, SCIFA4_RXD, SEL_SCIFA4_0), 1330 PINMUX_IPSR_MSEL(IP9_22_21, TS_SCK0_D, SEL_TSIF0_3), 1331 PINMUX_IPSR_GPSR(IP9_24_23, VI0_HSYNC_N), 1332 PINMUX_IPSR_MSEL(IP9_24_23, TX5, SEL_SCIF5_0), 1333 PINMUX_IPSR_MSEL(IP9_24_23, SCIFA5_TXD, SEL_SCIFA5_0), 1334 PINMUX_IPSR_MSEL(IP9_24_23, TS_SDEN0_D, SEL_TSIF0_3), 1335 PINMUX_IPSR_GPSR(IP9_26_25, VI0_VSYNC_N), 1336 PINMUX_IPSR_MSEL(IP9_26_25, RX5, SEL_SCIF5_0), 1337 PINMUX_IPSR_MSEL(IP9_26_25, SCIFA5_RXD, SEL_SCIFA5_0), 1338 PINMUX_IPSR_MSEL(IP9_26_25, TS_SPSYNC0_D, SEL_TSIF0_3), 1339 PINMUX_IPSR_GPSR(IP9_28_27, VI0_DATA3_VI0_B3), 1340 PINMUX_IPSR_MSEL(IP9_28_27, SCIF3_SCK_B, SEL_SCIF3_1), 1341 PINMUX_IPSR_MSEL(IP9_28_27, SCIFA3_SCK_B, SEL_SCIFA3_1), 1342 PINMUX_IPSR_GPSR(IP9_31_29, VI0_G0), 1343 PINMUX_IPSR_MSEL(IP9_31_29, IIC1_SCL, SEL_IIC1_0), 1344 PINMUX_IPSR_MSEL(IP9_31_29, STP_IVCXO27_0_C, SEL_SSP_2), 1345 PINMUX_IPSR_MSEL(IP9_31_29, I2C4_SCL, SEL_I2C4_0), 1346 PINMUX_IPSR_MSEL(IP9_31_29, HCTS2_N, SEL_HSCIF2_0), 1347 PINMUX_IPSR_MSEL(IP9_31_29, SCIFB2_CTS_N, SEL_SCIFB2_0), 1348 PINMUX_IPSR_GPSR(IP9_31_29, ATAWR1_N), 1349 1350 /* IPSR10 */ 1351 PINMUX_IPSR_GPSR(IP10_2_0, VI0_G1), 1352 PINMUX_IPSR_MSEL(IP10_2_0, IIC1_SDA, SEL_IIC1_0), 1353 PINMUX_IPSR_MSEL(IP10_2_0, STP_ISCLK_0_C, SEL_SSP_2), 1354 PINMUX_IPSR_MSEL(IP10_2_0, I2C4_SDA, SEL_I2C4_0), 1355 PINMUX_IPSR_MSEL(IP10_2_0, HRTS2_N, SEL_HSCIF2_0), 1356 PINMUX_IPSR_MSEL(IP10_2_0, SCIFB2_RTS_N, SEL_SCIFB2_0), 1357 PINMUX_IPSR_GPSR(IP10_2_0, ATADIR1_N), 1358 PINMUX_IPSR_GPSR(IP10_5_3, VI0_G2), 1359 PINMUX_IPSR_GPSR(IP10_5_3, VI2_HSYNC_N), 1360 PINMUX_IPSR_MSEL(IP10_5_3, STP_ISD_0_C, SEL_SSP_2), 1361 PINMUX_IPSR_MSEL(IP10_5_3, I2C3_SCL_B, SEL_I2C3_1), 1362 PINMUX_IPSR_MSEL(IP10_5_3, HSCK2, SEL_HSCIF2_0), 1363 PINMUX_IPSR_MSEL(IP10_5_3, SCIFB2_SCK, SEL_SCIFB2_0), 1364 PINMUX_IPSR_GPSR(IP10_5_3, ATARD1_N), 1365 PINMUX_IPSR_GPSR(IP10_8_6, VI0_G3), 1366 PINMUX_IPSR_GPSR(IP10_8_6, VI2_VSYNC_N), 1367 PINMUX_IPSR_MSEL(IP10_8_6, STP_ISEN_0_C, SEL_SSP_2), 1368 PINMUX_IPSR_MSEL(IP10_8_6, I2C3_SDA_B, SEL_I2C3_1), 1369 PINMUX_IPSR_MSEL(IP10_8_6, HRX2, SEL_HSCIF2_0), 1370 PINMUX_IPSR_MSEL(IP10_8_6, SCIFB2_RXD, SEL_SCIFB2_0), 1371 PINMUX_IPSR_GPSR(IP10_8_6, ATACS01_N), 1372 PINMUX_IPSR_GPSR(IP10_11_9, VI0_G4), 1373 PINMUX_IPSR_GPSR(IP10_11_9, VI2_CLKENB), 1374 PINMUX_IPSR_MSEL(IP10_11_9, STP_ISSYNC_0_C, SEL_SSP_2), 1375 PINMUX_IPSR_MSEL(IP10_11_9, HTX2, SEL_HSCIF2_0), 1376 PINMUX_IPSR_MSEL(IP10_11_9, SCIFB2_TXD, SEL_SCIFB2_0), 1377 PINMUX_IPSR_MSEL(IP10_11_9, SCIFB0_SCK_D, SEL_SCIFB_3), 1378 PINMUX_IPSR_GPSR(IP10_14_12, VI0_G5), 1379 PINMUX_IPSR_GPSR(IP10_14_12, VI2_FIELD), 1380 PINMUX_IPSR_MSEL(IP10_14_12, STP_OPWM_0_C, SEL_SSP_2), 1381 PINMUX_IPSR_MSEL(IP10_14_12, FMCLK_D, SEL_FM_3), 1382 PINMUX_IPSR_MSEL(IP10_14_12, CAN0_TX_E, SEL_CAN0_4), 1383 PINMUX_IPSR_MSEL(IP10_14_12, HTX1_D, SEL_HSCIF1_3), 1384 PINMUX_IPSR_MSEL(IP10_14_12, SCIFB0_TXD_D, SEL_SCIFB_3), 1385 PINMUX_IPSR_GPSR(IP10_16_15, VI0_G6), 1386 PINMUX_IPSR_GPSR(IP10_16_15, VI2_CLK), 1387 PINMUX_IPSR_MSEL(IP10_16_15, BPFCLK_D, SEL_FM_3), 1388 PINMUX_IPSR_GPSR(IP10_18_17, VI0_G7), 1389 PINMUX_IPSR_GPSR(IP10_18_17, VI2_DATA0), 1390 PINMUX_IPSR_MSEL(IP10_18_17, FMIN_D, SEL_FM_3), 1391 PINMUX_IPSR_GPSR(IP10_21_19, VI0_R0), 1392 PINMUX_IPSR_GPSR(IP10_21_19, VI2_DATA1), 1393 PINMUX_IPSR_MSEL(IP10_21_19, GLO_I0_B, SEL_GPS_1), 1394 PINMUX_IPSR_MSEL(IP10_21_19, TS_SDATA0_C, SEL_TSIF0_2), 1395 PINMUX_IPSR_GPSR(IP10_21_19, ATACS11_N), 1396 PINMUX_IPSR_GPSR(IP10_24_22, VI0_R1), 1397 PINMUX_IPSR_GPSR(IP10_24_22, VI2_DATA2), 1398 PINMUX_IPSR_MSEL(IP10_24_22, GLO_I1_B, SEL_GPS_1), 1399 PINMUX_IPSR_MSEL(IP10_24_22, TS_SCK0_C, SEL_TSIF0_2), 1400 PINMUX_IPSR_GPSR(IP10_24_22, ATAG1_N), 1401 PINMUX_IPSR_GPSR(IP10_26_25, VI0_R2), 1402 PINMUX_IPSR_GPSR(IP10_26_25, VI2_DATA3), 1403 PINMUX_IPSR_MSEL(IP10_26_25, GLO_Q0_B, SEL_GPS_1), 1404 PINMUX_IPSR_MSEL(IP10_26_25, TS_SDEN0_C, SEL_TSIF0_2), 1405 PINMUX_IPSR_GPSR(IP10_28_27, VI0_R3), 1406 PINMUX_IPSR_GPSR(IP10_28_27, VI2_DATA4), 1407 PINMUX_IPSR_MSEL(IP10_28_27, GLO_Q1_B, SEL_GPS_1), 1408 PINMUX_IPSR_MSEL(IP10_28_27, TS_SPSYNC0_C, SEL_TSIF0_2), 1409 PINMUX_IPSR_GPSR(IP10_31_29, VI0_R4), 1410 PINMUX_IPSR_GPSR(IP10_31_29, VI2_DATA5), 1411 PINMUX_IPSR_MSEL(IP10_31_29, GLO_SCLK_B, SEL_GPS_1), 1412 PINMUX_IPSR_MSEL(IP10_31_29, TX0_C, SEL_SCIF0_2), 1413 PINMUX_IPSR_MSEL(IP10_31_29, I2C1_SCL_D, SEL_I2C1_3), 1414 1415 /* IPSR11 */ 1416 PINMUX_IPSR_GPSR(IP11_2_0, VI0_R5), 1417 PINMUX_IPSR_GPSR(IP11_2_0, VI2_DATA6), 1418 PINMUX_IPSR_MSEL(IP11_2_0, GLO_SDATA_B, SEL_GPS_1), 1419 PINMUX_IPSR_MSEL(IP11_2_0, RX0_C, SEL_SCIF0_2), 1420 PINMUX_IPSR_MSEL(IP11_2_0, I2C1_SDA_D, SEL_I2C1_3), 1421 PINMUX_IPSR_GPSR(IP11_5_3, VI0_R6), 1422 PINMUX_IPSR_GPSR(IP11_5_3, VI2_DATA7), 1423 PINMUX_IPSR_MSEL(IP11_5_3, GLO_SS_B, SEL_GPS_1), 1424 PINMUX_IPSR_MSEL(IP11_5_3, TX1_C, SEL_SCIF1_2), 1425 PINMUX_IPSR_MSEL(IP11_5_3, I2C4_SCL_B, SEL_I2C4_1), 1426 PINMUX_IPSR_GPSR(IP11_8_6, VI0_R7), 1427 PINMUX_IPSR_MSEL(IP11_8_6, GLO_RFON_B, SEL_GPS_1), 1428 PINMUX_IPSR_MSEL(IP11_8_6, RX1_C, SEL_SCIF1_2), 1429 PINMUX_IPSR_MSEL(IP11_8_6, CAN0_RX_E, SEL_CAN0_4), 1430 PINMUX_IPSR_MSEL(IP11_8_6, I2C4_SDA_B, SEL_I2C4_1), 1431 PINMUX_IPSR_MSEL(IP11_8_6, HRX1_D, SEL_HSCIF1_3), 1432 PINMUX_IPSR_MSEL(IP11_8_6, SCIFB0_RXD_D, SEL_SCIFB_3), 1433 PINMUX_IPSR_MSEL(IP11_11_9, VI1_HSYNC_N, SEL_VI1_0), 1434 PINMUX_IPSR_GPSR(IP11_11_9, AVB_RXD0), 1435 PINMUX_IPSR_MSEL(IP11_11_9, TS_SDATA0_B, SEL_TSIF0_1), 1436 PINMUX_IPSR_MSEL(IP11_11_9, TX4_B, SEL_SCIF4_1), 1437 PINMUX_IPSR_MSEL(IP11_11_9, SCIFA4_TXD_B, SEL_SCIFA4_1), 1438 PINMUX_IPSR_MSEL(IP11_14_12, VI1_VSYNC_N, SEL_VI1_0), 1439 PINMUX_IPSR_GPSR(IP11_14_12, AVB_RXD1), 1440 PINMUX_IPSR_MSEL(IP11_14_12, TS_SCK0_B, SEL_TSIF0_1), 1441 PINMUX_IPSR_MSEL(IP11_14_12, RX4_B, SEL_SCIF4_1), 1442 PINMUX_IPSR_MSEL(IP11_14_12, SCIFA4_RXD_B, SEL_SCIFA4_1), 1443 PINMUX_IPSR_MSEL(IP11_16_15, VI1_CLKENB, SEL_VI1_0), 1444 PINMUX_IPSR_GPSR(IP11_16_15, AVB_RXD2), 1445 PINMUX_IPSR_MSEL(IP11_16_15, TS_SDEN0_B, SEL_TSIF0_1), 1446 PINMUX_IPSR_MSEL(IP11_18_17, VI1_FIELD, SEL_VI1_0), 1447 PINMUX_IPSR_GPSR(IP11_18_17, AVB_RXD3), 1448 PINMUX_IPSR_MSEL(IP11_18_17, TS_SPSYNC0_B, SEL_TSIF0_1), 1449 PINMUX_IPSR_MSEL(IP11_19, VI1_CLK, SEL_VI1_0), 1450 PINMUX_IPSR_GPSR(IP11_19, AVB_RXD4), 1451 PINMUX_IPSR_MSEL(IP11_20, VI1_DATA0, SEL_VI1_0), 1452 PINMUX_IPSR_GPSR(IP11_20, AVB_RXD5), 1453 PINMUX_IPSR_MSEL(IP11_21, VI1_DATA1, SEL_VI1_0), 1454 PINMUX_IPSR_GPSR(IP11_21, AVB_RXD6), 1455 PINMUX_IPSR_MSEL(IP11_22, VI1_DATA2, SEL_VI1_0), 1456 PINMUX_IPSR_GPSR(IP11_22, AVB_RXD7), 1457 PINMUX_IPSR_MSEL(IP11_23, VI1_DATA3, SEL_VI1_0), 1458 PINMUX_IPSR_GPSR(IP11_23, AVB_RX_ER), 1459 PINMUX_IPSR_MSEL(IP11_24, VI1_DATA4, SEL_VI1_0), 1460 PINMUX_IPSR_GPSR(IP11_24, AVB_MDIO), 1461 PINMUX_IPSR_MSEL(IP11_25, VI1_DATA5, SEL_VI1_0), 1462 PINMUX_IPSR_GPSR(IP11_25, AVB_RX_DV), 1463 PINMUX_IPSR_MSEL(IP11_26, VI1_DATA6, SEL_VI1_0), 1464 PINMUX_IPSR_GPSR(IP11_26, AVB_MAGIC), 1465 PINMUX_IPSR_MSEL(IP11_27, VI1_DATA7, SEL_VI1_0), 1466 PINMUX_IPSR_GPSR(IP11_27, AVB_MDC), 1467 PINMUX_IPSR_GPSR(IP11_29_28, ETH_MDIO), 1468 PINMUX_IPSR_GPSR(IP11_29_28, AVB_RX_CLK), 1469 PINMUX_IPSR_MSEL(IP11_29_28, I2C2_SCL_C, SEL_I2C2_2), 1470 PINMUX_IPSR_GPSR(IP11_31_30, ETH_CRS_DV), 1471 PINMUX_IPSR_GPSR(IP11_31_30, AVB_LINK), 1472 PINMUX_IPSR_MSEL(IP11_31_30, I2C2_SDA_C, SEL_I2C2_2), 1473 1474 /* IPSR12 */ 1475 PINMUX_IPSR_GPSR(IP12_1_0, ETH_RX_ER), 1476 PINMUX_IPSR_GPSR(IP12_1_0, AVB_CRS), 1477 PINMUX_IPSR_MSEL(IP12_1_0, I2C3_SCL, SEL_I2C3_0), 1478 PINMUX_IPSR_MSEL(IP12_1_0, IIC0_SCL, SEL_IIC0_0), 1479 PINMUX_IPSR_GPSR(IP12_3_2, ETH_RXD0), 1480 PINMUX_IPSR_GPSR(IP12_3_2, AVB_PHY_INT), 1481 PINMUX_IPSR_MSEL(IP12_3_2, I2C3_SDA, SEL_I2C3_0), 1482 PINMUX_IPSR_MSEL(IP12_3_2, IIC0_SDA, SEL_IIC0_0), 1483 PINMUX_IPSR_GPSR(IP12_6_4, ETH_RXD1), 1484 PINMUX_IPSR_GPSR(IP12_6_4, AVB_GTXREFCLK), 1485 PINMUX_IPSR_MSEL(IP12_6_4, CAN0_TX_C, SEL_CAN0_2), 1486 PINMUX_IPSR_MSEL(IP12_6_4, I2C2_SCL_D, SEL_I2C2_3), 1487 PINMUX_IPSR_MSEL(IP12_6_4, MSIOF1_RXD_E, SEL_SOF1_4), 1488 PINMUX_IPSR_GPSR(IP12_9_7, ETH_LINK), 1489 PINMUX_IPSR_GPSR(IP12_9_7, AVB_TXD0), 1490 PINMUX_IPSR_MSEL(IP12_9_7, CAN0_RX_C, SEL_CAN0_2), 1491 PINMUX_IPSR_MSEL(IP12_9_7, I2C2_SDA_D, SEL_I2C2_3), 1492 PINMUX_IPSR_MSEL(IP12_9_7, MSIOF1_SCK_E, SEL_SOF1_4), 1493 PINMUX_IPSR_GPSR(IP12_12_10, ETH_REFCLK), 1494 PINMUX_IPSR_GPSR(IP12_12_10, AVB_TXD1), 1495 PINMUX_IPSR_MSEL(IP12_12_10, SCIFA3_RXD_B, SEL_SCIFA3_1), 1496 PINMUX_IPSR_MSEL(IP12_12_10, CAN1_RX_C, SEL_CAN1_2), 1497 PINMUX_IPSR_MSEL(IP12_12_10, MSIOF1_SYNC_E, SEL_SOF1_4), 1498 PINMUX_IPSR_GPSR(IP12_15_13, ETH_TXD1), 1499 PINMUX_IPSR_GPSR(IP12_15_13, AVB_TXD2), 1500 PINMUX_IPSR_MSEL(IP12_15_13, SCIFA3_TXD_B, SEL_SCIFA3_1), 1501 PINMUX_IPSR_MSEL(IP12_15_13, CAN1_TX_C, SEL_CAN1_2), 1502 PINMUX_IPSR_MSEL(IP12_15_13, MSIOF1_TXD_E, SEL_SOF1_4), 1503 PINMUX_IPSR_GPSR(IP12_17_16, ETH_TX_EN), 1504 PINMUX_IPSR_GPSR(IP12_17_16, AVB_TXD3), 1505 PINMUX_IPSR_MSEL(IP12_17_16, TCLK1_B, SEL_TMU1_0), 1506 PINMUX_IPSR_MSEL(IP12_17_16, CAN_CLK_B, SEL_CANCLK_1), 1507 PINMUX_IPSR_GPSR(IP12_19_18, ETH_MAGIC), 1508 PINMUX_IPSR_GPSR(IP12_19_18, AVB_TXD4), 1509 PINMUX_IPSR_MSEL(IP12_19_18, IETX_C, SEL_IEB_2), 1510 PINMUX_IPSR_GPSR(IP12_21_20, ETH_TXD0), 1511 PINMUX_IPSR_GPSR(IP12_21_20, AVB_TXD5), 1512 PINMUX_IPSR_MSEL(IP12_21_20, IECLK_C, SEL_IEB_2), 1513 PINMUX_IPSR_GPSR(IP12_23_22, ETH_MDC), 1514 PINMUX_IPSR_GPSR(IP12_23_22, AVB_TXD6), 1515 PINMUX_IPSR_MSEL(IP12_23_22, IERX_C, SEL_IEB_2), 1516 PINMUX_IPSR_MSEL(IP12_26_24, STP_IVCXO27_0, SEL_SSP_0), 1517 PINMUX_IPSR_GPSR(IP12_26_24, AVB_TXD7), 1518 PINMUX_IPSR_MSEL(IP12_26_24, SCIFB2_TXD_D, SEL_SCIFB2_3), 1519 PINMUX_IPSR_MSEL(IP12_26_24, ADIDATA_B, SEL_RAD_1), 1520 PINMUX_IPSR_MSEL(IP12_26_24, MSIOF0_SYNC_C, SEL_SOF0_2), 1521 PINMUX_IPSR_MSEL(IP12_29_27, STP_ISCLK_0, SEL_SSP_0), 1522 PINMUX_IPSR_GPSR(IP12_29_27, AVB_TX_EN), 1523 PINMUX_IPSR_MSEL(IP12_29_27, SCIFB2_RXD_D, SEL_SCIFB2_3), 1524 PINMUX_IPSR_MSEL(IP12_29_27, ADICS_SAMP_B, SEL_RAD_1), 1525 PINMUX_IPSR_MSEL(IP12_29_27, MSIOF0_SCK_C, SEL_SOF0_2), 1526 1527 /* IPSR13 */ 1528 PINMUX_IPSR_MSEL(IP13_2_0, STP_ISD_0, SEL_SSP_0), 1529 PINMUX_IPSR_GPSR(IP13_2_0, AVB_TX_ER), 1530 PINMUX_IPSR_MSEL(IP13_2_0, SCIFB2_SCK_C, SEL_SCIFB2_2), 1531 PINMUX_IPSR_MSEL(IP13_2_0, ADICLK_B, SEL_RAD_1), 1532 PINMUX_IPSR_MSEL(IP13_2_0, MSIOF0_SS1_C, SEL_SOF0_2), 1533 PINMUX_IPSR_MSEL(IP13_4_3, STP_ISEN_0, SEL_SSP_0), 1534 PINMUX_IPSR_GPSR(IP13_4_3, AVB_TX_CLK), 1535 PINMUX_IPSR_MSEL(IP13_4_3, ADICHS0_B, SEL_RAD_1), 1536 PINMUX_IPSR_MSEL(IP13_4_3, MSIOF0_SS2_C, SEL_SOF0_2), 1537 PINMUX_IPSR_MSEL(IP13_6_5, STP_ISSYNC_0, SEL_SSP_0), 1538 PINMUX_IPSR_GPSR(IP13_6_5, AVB_COL), 1539 PINMUX_IPSR_MSEL(IP13_6_5, ADICHS1_B, SEL_RAD_1), 1540 PINMUX_IPSR_MSEL(IP13_6_5, MSIOF0_RXD_C, SEL_SOF0_2), 1541 PINMUX_IPSR_MSEL(IP13_9_7, STP_OPWM_0, SEL_SSP_0), 1542 PINMUX_IPSR_GPSR(IP13_9_7, AVB_GTX_CLK), 1543 PINMUX_IPSR_GPSR(IP13_9_7, PWM0_B), 1544 PINMUX_IPSR_MSEL(IP13_9_7, ADICHS2_B, SEL_RAD_1), 1545 PINMUX_IPSR_MSEL(IP13_9_7, MSIOF0_TXD_C, SEL_SOF0_2), 1546 PINMUX_IPSR_GPSR(IP13_10, SD0_CLK), 1547 PINMUX_IPSR_MSEL(IP13_10, SPCLK_B, SEL_QSP_1), 1548 PINMUX_IPSR_GPSR(IP13_11, SD0_CMD), 1549 PINMUX_IPSR_MSEL(IP13_11, MOSI_IO0_B, SEL_QSP_1), 1550 PINMUX_IPSR_GPSR(IP13_12, SD0_DATA0), 1551 PINMUX_IPSR_MSEL(IP13_12, MISO_IO1_B, SEL_QSP_1), 1552 PINMUX_IPSR_GPSR(IP13_13, SD0_DATA1), 1553 PINMUX_IPSR_MSEL(IP13_13, IO2_B, SEL_QSP_1), 1554 PINMUX_IPSR_GPSR(IP13_14, SD0_DATA2), 1555 PINMUX_IPSR_MSEL(IP13_14, IO3_B, SEL_QSP_1), 1556 PINMUX_IPSR_GPSR(IP13_15, SD0_DATA3), 1557 PINMUX_IPSR_MSEL(IP13_15, SSL_B, SEL_QSP_1), 1558 PINMUX_IPSR_GPSR(IP13_18_16, SD0_CD), 1559 PINMUX_IPSR_MSEL(IP13_18_16, MMC_D6_B, SEL_MMC_1), 1560 PINMUX_IPSR_MSEL(IP13_18_16, SIM0_RST_B, SEL_SIM_1), 1561 PINMUX_IPSR_MSEL(IP13_18_16, CAN0_RX_F, SEL_CAN0_5), 1562 PINMUX_IPSR_MSEL(IP13_18_16, SCIFA5_TXD_B, SEL_SCIFA5_1), 1563 PINMUX_IPSR_MSEL(IP13_18_16, TX3_C, SEL_SCIF3_2), 1564 PINMUX_IPSR_GPSR(IP13_21_19, SD0_WP), 1565 PINMUX_IPSR_MSEL(IP13_21_19, MMC_D7_B, SEL_MMC_1), 1566 PINMUX_IPSR_MSEL(IP13_21_19, SIM0_D_B, SEL_SIM_1), 1567 PINMUX_IPSR_MSEL(IP13_21_19, CAN0_TX_F, SEL_CAN0_5), 1568 PINMUX_IPSR_MSEL(IP13_21_19, SCIFA5_RXD_B, SEL_SCIFA5_1), 1569 PINMUX_IPSR_MSEL(IP13_21_19, RX3_C, SEL_SCIF3_2), 1570 PINMUX_IPSR_GPSR(IP13_22, SD1_CMD), 1571 PINMUX_IPSR_MSEL(IP13_22, REMOCON_B, SEL_RCN_1), 1572 PINMUX_IPSR_GPSR(IP13_24_23, SD1_DATA0), 1573 PINMUX_IPSR_MSEL(IP13_24_23, SPEEDIN_B, SEL_RSP_1), 1574 PINMUX_IPSR_GPSR(IP13_25, SD1_DATA1), 1575 PINMUX_IPSR_MSEL(IP13_25, IETX_B, SEL_IEB_1), 1576 PINMUX_IPSR_GPSR(IP13_26, SD1_DATA2), 1577 PINMUX_IPSR_MSEL(IP13_26, IECLK_B, SEL_IEB_1), 1578 PINMUX_IPSR_GPSR(IP13_27, SD1_DATA3), 1579 PINMUX_IPSR_MSEL(IP13_27, IERX_B, SEL_IEB_1), 1580 PINMUX_IPSR_GPSR(IP13_30_28, SD1_CD), 1581 PINMUX_IPSR_GPSR(IP13_30_28, PWM0), 1582 PINMUX_IPSR_GPSR(IP13_30_28, TPU_TO0), 1583 PINMUX_IPSR_MSEL(IP13_30_28, I2C1_SCL_C, SEL_I2C1_2), 1584 1585 /* IPSR14 */ 1586 PINMUX_IPSR_GPSR(IP14_1_0, SD1_WP), 1587 PINMUX_IPSR_GPSR(IP14_1_0, PWM1_B), 1588 PINMUX_IPSR_MSEL(IP14_1_0, I2C1_SDA_C, SEL_I2C1_2), 1589 PINMUX_IPSR_GPSR(IP14_2, SD2_CLK), 1590 PINMUX_IPSR_GPSR(IP14_2, MMC_CLK), 1591 PINMUX_IPSR_GPSR(IP14_3, SD2_CMD), 1592 PINMUX_IPSR_GPSR(IP14_3, MMC_CMD), 1593 PINMUX_IPSR_GPSR(IP14_4, SD2_DATA0), 1594 PINMUX_IPSR_GPSR(IP14_4, MMC_D0), 1595 PINMUX_IPSR_GPSR(IP14_5, SD2_DATA1), 1596 PINMUX_IPSR_GPSR(IP14_5, MMC_D1), 1597 PINMUX_IPSR_GPSR(IP14_6, SD2_DATA2), 1598 PINMUX_IPSR_GPSR(IP14_6, MMC_D2), 1599 PINMUX_IPSR_GPSR(IP14_7, SD2_DATA3), 1600 PINMUX_IPSR_GPSR(IP14_7, MMC_D3), 1601 PINMUX_IPSR_GPSR(IP14_10_8, SD2_CD), 1602 PINMUX_IPSR_GPSR(IP14_10_8, MMC_D4), 1603 PINMUX_IPSR_MSEL(IP14_10_8, IIC1_SCL_C, SEL_IIC1_2), 1604 PINMUX_IPSR_MSEL(IP14_10_8, TX5_B, SEL_SCIF5_1), 1605 PINMUX_IPSR_MSEL(IP14_10_8, SCIFA5_TXD_C, SEL_SCIFA5_2), 1606 PINMUX_IPSR_GPSR(IP14_13_11, SD2_WP), 1607 PINMUX_IPSR_GPSR(IP14_13_11, MMC_D5), 1608 PINMUX_IPSR_MSEL(IP14_13_11, IIC1_SDA_C, SEL_IIC1_2), 1609 PINMUX_IPSR_MSEL(IP14_13_11, RX5_B, SEL_SCIF5_1), 1610 PINMUX_IPSR_MSEL(IP14_13_11, SCIFA5_RXD_C, SEL_SCIFA5_2), 1611 PINMUX_IPSR_MSEL(IP14_16_14, MSIOF0_SCK, SEL_SOF0_0), 1612 PINMUX_IPSR_MSEL(IP14_16_14, RX2_C, SEL_SCIF2_2), 1613 PINMUX_IPSR_MSEL(IP14_16_14, ADIDATA, SEL_RAD_0), 1614 PINMUX_IPSR_MSEL(IP14_16_14, VI1_CLK_C, SEL_VI1_2), 1615 PINMUX_IPSR_GPSR(IP14_16_14, VI1_G0_B), 1616 PINMUX_IPSR_MSEL(IP14_19_17, MSIOF0_SYNC, SEL_SOF0_0), 1617 PINMUX_IPSR_MSEL(IP14_19_17, TX2_C, SEL_SCIF2_2), 1618 PINMUX_IPSR_MSEL(IP14_19_17, ADICS_SAMP, SEL_RAD_0), 1619 PINMUX_IPSR_MSEL(IP14_19_17, VI1_CLKENB_C, SEL_VI1_2), 1620 PINMUX_IPSR_GPSR(IP14_19_17, VI1_G1_B), 1621 PINMUX_IPSR_MSEL(IP14_22_20, MSIOF0_TXD, SEL_SOF0_0), 1622 PINMUX_IPSR_MSEL(IP14_22_20, ADICLK, SEL_RAD_0), 1623 PINMUX_IPSR_MSEL(IP14_22_20, VI1_FIELD_C, SEL_VI1_2), 1624 PINMUX_IPSR_GPSR(IP14_22_20, VI1_G2_B), 1625 PINMUX_IPSR_MSEL(IP14_25_23, MSIOF0_RXD, SEL_SOF0_0), 1626 PINMUX_IPSR_MSEL(IP14_25_23, ADICHS0, SEL_RAD_0), 1627 PINMUX_IPSR_MSEL(IP14_25_23, VI1_DATA0_C, SEL_VI1_2), 1628 PINMUX_IPSR_GPSR(IP14_25_23, VI1_G3_B), 1629 PINMUX_IPSR_MSEL(IP14_28_26, MSIOF0_SS1, SEL_SOF0_0), 1630 PINMUX_IPSR_MSEL(IP14_28_26, MMC_D6, SEL_MMC_0), 1631 PINMUX_IPSR_MSEL(IP14_28_26, ADICHS1, SEL_RAD_0), 1632 PINMUX_IPSR_MSEL(IP14_28_26, TX0_E, SEL_SCIF0_4), 1633 PINMUX_IPSR_MSEL(IP14_28_26, VI1_HSYNC_N_C, SEL_VI1_2), 1634 PINMUX_IPSR_MSEL(IP14_28_26, IIC0_SCL_C, SEL_IIC0_2), 1635 PINMUX_IPSR_GPSR(IP14_28_26, VI1_G4_B), 1636 PINMUX_IPSR_MSEL(IP14_31_29, MSIOF0_SS2, SEL_SOF0_0), 1637 PINMUX_IPSR_MSEL(IP14_31_29, MMC_D7, SEL_MMC_0), 1638 PINMUX_IPSR_MSEL(IP14_31_29, ADICHS2, SEL_RAD_0), 1639 PINMUX_IPSR_MSEL(IP14_31_29, RX0_E, SEL_SCIF0_4), 1640 PINMUX_IPSR_MSEL(IP14_31_29, VI1_VSYNC_N_C, SEL_VI1_2), 1641 PINMUX_IPSR_MSEL(IP14_31_29, IIC0_SDA_C, SEL_IIC0_2), 1642 PINMUX_IPSR_GPSR(IP14_31_29, VI1_G5_B), 1643 1644 /* IPSR15 */ 1645 PINMUX_IPSR_MSEL(IP15_1_0, SIM0_RST, SEL_SIM_0), 1646 PINMUX_IPSR_MSEL(IP15_1_0, IETX, SEL_IEB_0), 1647 PINMUX_IPSR_MSEL(IP15_1_0, CAN1_TX_D, SEL_CAN1_3), 1648 PINMUX_IPSR_GPSR(IP15_3_2, SIM0_CLK), 1649 PINMUX_IPSR_MSEL(IP15_3_2, IECLK, SEL_IEB_0), 1650 PINMUX_IPSR_MSEL(IP15_3_2, CAN_CLK_C, SEL_CANCLK_2), 1651 PINMUX_IPSR_MSEL(IP15_5_4, SIM0_D, SEL_SIM_0), 1652 PINMUX_IPSR_MSEL(IP15_5_4, IERX, SEL_IEB_0), 1653 PINMUX_IPSR_MSEL(IP15_5_4, CAN1_RX_D, SEL_CAN1_3), 1654 PINMUX_IPSR_MSEL(IP15_8_6, GPS_CLK, SEL_GPS_0), 1655 PINMUX_IPSR_MSEL(IP15_8_6, DU1_DOTCLKIN_C, SEL_DIS_2), 1656 PINMUX_IPSR_MSEL(IP15_8_6, AUDIO_CLKB_B, SEL_ADG_1), 1657 PINMUX_IPSR_GPSR(IP15_8_6, PWM5_B), 1658 PINMUX_IPSR_MSEL(IP15_8_6, SCIFA3_TXD_C, SEL_SCIFA3_2), 1659 PINMUX_IPSR_MSEL(IP15_11_9, GPS_SIGN, SEL_GPS_0), 1660 PINMUX_IPSR_MSEL(IP15_11_9, TX4_C, SEL_SCIF4_2), 1661 PINMUX_IPSR_MSEL(IP15_11_9, SCIFA4_TXD_C, SEL_SCIFA4_2), 1662 PINMUX_IPSR_GPSR(IP15_11_9, PWM5), 1663 PINMUX_IPSR_GPSR(IP15_11_9, VI1_G6_B), 1664 PINMUX_IPSR_MSEL(IP15_11_9, SCIFA3_RXD_C, SEL_SCIFA3_2), 1665 PINMUX_IPSR_MSEL(IP15_14_12, GPS_MAG, SEL_GPS_0), 1666 PINMUX_IPSR_MSEL(IP15_14_12, RX4_C, SEL_SCIF4_2), 1667 PINMUX_IPSR_MSEL(IP15_14_12, SCIFA4_RXD_C, SEL_SCIFA4_2), 1668 PINMUX_IPSR_GPSR(IP15_14_12, PWM6), 1669 PINMUX_IPSR_GPSR(IP15_14_12, VI1_G7_B), 1670 PINMUX_IPSR_MSEL(IP15_14_12, SCIFA3_SCK_C, SEL_SCIFA3_2), 1671 PINMUX_IPSR_MSEL(IP15_17_15, HCTS0_N, SEL_HSCIF0_0), 1672 PINMUX_IPSR_MSEL(IP15_17_15, SCIFB0_CTS_N, SEL_SCIFB_0), 1673 PINMUX_IPSR_MSEL(IP15_17_15, GLO_I0_C, SEL_GPS_2), 1674 PINMUX_IPSR_MSEL(IP15_17_15, TCLK1, SEL_TMU1_0), 1675 PINMUX_IPSR_MSEL(IP15_17_15, VI1_DATA1_C, SEL_VI1_2), 1676 PINMUX_IPSR_MSEL(IP15_20_18, HRTS0_N, SEL_HSCIF0_0), 1677 PINMUX_IPSR_MSEL(IP15_20_18, SCIFB0_RTS_N, SEL_SCIFB_0), 1678 PINMUX_IPSR_MSEL(IP15_20_18, GLO_I1_C, SEL_GPS_2), 1679 PINMUX_IPSR_MSEL(IP15_20_18, VI1_DATA2_C, SEL_VI1_2), 1680 PINMUX_IPSR_MSEL(IP15_23_21, HSCK0, SEL_HSCIF0_0), 1681 PINMUX_IPSR_MSEL(IP15_23_21, SCIFB0_SCK, SEL_SCIFB_0), 1682 PINMUX_IPSR_MSEL(IP15_23_21, GLO_Q0_C, SEL_GPS_2), 1683 PINMUX_IPSR_MSEL(IP15_23_21, CAN_CLK, SEL_CANCLK_0), 1684 PINMUX_IPSR_GPSR(IP15_23_21, TCLK2), 1685 PINMUX_IPSR_MSEL(IP15_23_21, VI1_DATA3_C, SEL_VI1_2), 1686 PINMUX_IPSR_MSEL(IP15_26_24, HRX0, SEL_HSCIF0_0), 1687 PINMUX_IPSR_MSEL(IP15_26_24, SCIFB0_RXD, SEL_SCIFB_0), 1688 PINMUX_IPSR_MSEL(IP15_26_24, GLO_Q1_C, SEL_GPS_2), 1689 PINMUX_IPSR_MSEL(IP15_26_24, CAN0_RX_B, SEL_CAN0_1), 1690 PINMUX_IPSR_MSEL(IP15_26_24, VI1_DATA4_C, SEL_VI1_2), 1691 PINMUX_IPSR_MSEL(IP15_29_27, HTX0, SEL_HSCIF0_0), 1692 PINMUX_IPSR_MSEL(IP15_29_27, SCIFB0_TXD, SEL_SCIFB_0), 1693 PINMUX_IPSR_MSEL(IP15_29_27, GLO_SCLK_C, SEL_GPS_2), 1694 PINMUX_IPSR_MSEL(IP15_29_27, CAN0_TX_B, SEL_CAN0_1), 1695 PINMUX_IPSR_MSEL(IP15_29_27, VI1_DATA5_C, SEL_VI1_2), 1696 1697 /* IPSR16 */ 1698 PINMUX_IPSR_MSEL(IP16_2_0, HRX1, SEL_HSCIF1_0), 1699 PINMUX_IPSR_MSEL(IP16_2_0, SCIFB1_RXD, SEL_SCIFB1_0), 1700 PINMUX_IPSR_GPSR(IP16_2_0, VI1_R0_B), 1701 PINMUX_IPSR_MSEL(IP16_2_0, GLO_SDATA_C, SEL_GPS_2), 1702 PINMUX_IPSR_MSEL(IP16_2_0, VI1_DATA6_C, SEL_VI1_2), 1703 PINMUX_IPSR_MSEL(IP16_5_3, HTX1, SEL_HSCIF1_0), 1704 PINMUX_IPSR_MSEL(IP16_5_3, SCIFB1_TXD, SEL_SCIFB1_0), 1705 PINMUX_IPSR_GPSR(IP16_5_3, VI1_R1_B), 1706 PINMUX_IPSR_MSEL(IP16_5_3, GLO_SS_C, SEL_GPS_2), 1707 PINMUX_IPSR_MSEL(IP16_5_3, VI1_DATA7_C, SEL_VI1_2), 1708 PINMUX_IPSR_MSEL(IP16_7_6, HSCK1, SEL_HSCIF1_0), 1709 PINMUX_IPSR_MSEL(IP16_7_6, SCIFB1_SCK, SEL_SCIFB1_0), 1710 PINMUX_IPSR_GPSR(IP16_7_6, MLB_CLK), 1711 PINMUX_IPSR_MSEL(IP16_7_6, GLO_RFON_C, SEL_GPS_2), 1712 PINMUX_IPSR_MSEL(IP16_9_8, HCTS1_N, SEL_HSCIF1_0), 1713 PINMUX_IPSR_GPSR(IP16_9_8, SCIFB1_CTS_N), 1714 PINMUX_IPSR_GPSR(IP16_9_8, MLB_SIG), 1715 PINMUX_IPSR_MSEL(IP16_9_8, CAN1_TX_B, SEL_CAN1_1), 1716 PINMUX_IPSR_MSEL(IP16_11_10, HRTS1_N, SEL_HSCIF1_0), 1717 PINMUX_IPSR_GPSR(IP16_11_10, SCIFB1_RTS_N), 1718 PINMUX_IPSR_GPSR(IP16_11_10, MLB_DAT), 1719 PINMUX_IPSR_MSEL(IP16_11_10, CAN1_RX_B, SEL_CAN1_1), 1720 }; 1721 1722 /* 1723 * Pins not associated with a GPIO port. 1724 */ 1725 enum { 1726 GP_ASSIGN_LAST(), 1727 NOGP_ALL(), 1728 }; 1729 1730 static const struct sh_pfc_pin pinmux_pins[] = { 1731 PINMUX_GPIO_GP_ALL(), 1732 PINMUX_NOGP_ALL(), 1733 }; 1734 1735 #if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793) 1736 /* - ADI -------------------------------------------------------------------- */ 1737 static const unsigned int adi_common_pins[] = { 1738 /* ADIDATA, ADICS/SAMP, ADICLK */ 1739 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26), 1740 }; 1741 static const unsigned int adi_common_mux[] = { 1742 /* ADIDATA, ADICS/SAMP, ADICLK */ 1743 ADIDATA_MARK, ADICS_SAMP_MARK, ADICLK_MARK, 1744 }; 1745 static const unsigned int adi_chsel0_pins[] = { 1746 /* ADICHS 0 */ 1747 RCAR_GP_PIN(6, 27), 1748 }; 1749 static const unsigned int adi_chsel0_mux[] = { 1750 /* ADICHS 0 */ 1751 ADICHS0_MARK, 1752 }; 1753 static const unsigned int adi_chsel1_pins[] = { 1754 /* ADICHS 1 */ 1755 RCAR_GP_PIN(6, 28), 1756 }; 1757 static const unsigned int adi_chsel1_mux[] = { 1758 /* ADICHS 1 */ 1759 ADICHS1_MARK, 1760 }; 1761 static const unsigned int adi_chsel2_pins[] = { 1762 /* ADICHS 2 */ 1763 RCAR_GP_PIN(6, 29), 1764 }; 1765 static const unsigned int adi_chsel2_mux[] = { 1766 /* ADICHS 2 */ 1767 ADICHS2_MARK, 1768 }; 1769 static const unsigned int adi_common_b_pins[] = { 1770 /* ADIDATA B, ADICS/SAMP B, ADICLK B */ 1771 RCAR_GP_PIN(5, 25), RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 27), 1772 }; 1773 static const unsigned int adi_common_b_mux[] = { 1774 /* ADIDATA B, ADICS/SAMP B, ADICLK B */ 1775 ADIDATA_B_MARK, ADICS_SAMP_B_MARK, ADICLK_B_MARK, 1776 }; 1777 static const unsigned int adi_chsel0_b_pins[] = { 1778 /* ADICHS B 0 */ 1779 RCAR_GP_PIN(5, 28), 1780 }; 1781 static const unsigned int adi_chsel0_b_mux[] = { 1782 /* ADICHS B 0 */ 1783 ADICHS0_B_MARK, 1784 }; 1785 static const unsigned int adi_chsel1_b_pins[] = { 1786 /* ADICHS B 1 */ 1787 RCAR_GP_PIN(5, 29), 1788 }; 1789 static const unsigned int adi_chsel1_b_mux[] = { 1790 /* ADICHS B 1 */ 1791 ADICHS1_B_MARK, 1792 }; 1793 static const unsigned int adi_chsel2_b_pins[] = { 1794 /* ADICHS B 2 */ 1795 RCAR_GP_PIN(5, 30), 1796 }; 1797 static const unsigned int adi_chsel2_b_mux[] = { 1798 /* ADICHS B 2 */ 1799 ADICHS2_B_MARK, 1800 }; 1801 #endif /* CONFIG_PINCTRL_PFC_R8A7791 || CONFIG_PINCTRL_PFC_R8A7793 */ 1802 1803 /* - Audio Clock ------------------------------------------------------------ */ 1804 static const unsigned int audio_clk_a_pins[] = { 1805 /* CLK */ 1806 RCAR_GP_PIN(2, 28), 1807 }; 1808 1809 static const unsigned int audio_clk_a_mux[] = { 1810 AUDIO_CLKA_MARK, 1811 }; 1812 1813 static const unsigned int audio_clk_b_pins[] = { 1814 /* CLK */ 1815 RCAR_GP_PIN(2, 29), 1816 }; 1817 1818 static const unsigned int audio_clk_b_mux[] = { 1819 AUDIO_CLKB_MARK, 1820 }; 1821 1822 static const unsigned int audio_clk_b_b_pins[] = { 1823 /* CLK */ 1824 RCAR_GP_PIN(7, 20), 1825 }; 1826 1827 static const unsigned int audio_clk_b_b_mux[] = { 1828 AUDIO_CLKB_B_MARK, 1829 }; 1830 1831 static const unsigned int audio_clk_c_pins[] = { 1832 /* CLK */ 1833 RCAR_GP_PIN(2, 30), 1834 }; 1835 1836 static const unsigned int audio_clk_c_mux[] = { 1837 AUDIO_CLKC_MARK, 1838 }; 1839 1840 static const unsigned int audio_clkout_pins[] = { 1841 /* CLK */ 1842 RCAR_GP_PIN(2, 31), 1843 }; 1844 1845 static const unsigned int audio_clkout_mux[] = { 1846 AUDIO_CLKOUT_MARK, 1847 }; 1848 1849 /* - AVB -------------------------------------------------------------------- */ 1850 static const unsigned int avb_link_pins[] = { 1851 RCAR_GP_PIN(5, 14), 1852 }; 1853 static const unsigned int avb_link_mux[] = { 1854 AVB_LINK_MARK, 1855 }; 1856 static const unsigned int avb_magic_pins[] = { 1857 RCAR_GP_PIN(5, 11), 1858 }; 1859 static const unsigned int avb_magic_mux[] = { 1860 AVB_MAGIC_MARK, 1861 }; 1862 static const unsigned int avb_phy_int_pins[] = { 1863 RCAR_GP_PIN(5, 16), 1864 }; 1865 static const unsigned int avb_phy_int_mux[] = { 1866 AVB_PHY_INT_MARK, 1867 }; 1868 static const unsigned int avb_mdio_pins[] = { 1869 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 9), 1870 }; 1871 static const unsigned int avb_mdio_mux[] = { 1872 AVB_MDC_MARK, AVB_MDIO_MARK, 1873 }; 1874 static const unsigned int avb_mii_pins[] = { 1875 RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 20), 1876 RCAR_GP_PIN(5, 21), 1877 1878 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), 1879 RCAR_GP_PIN(5, 3), 1880 1881 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 10), 1882 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 27), 1883 RCAR_GP_PIN(5, 28), RCAR_GP_PIN(5, 29), 1884 }; 1885 static const unsigned int avb_mii_mux[] = { 1886 AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK, 1887 AVB_TXD3_MARK, 1888 1889 AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK, 1890 AVB_RXD3_MARK, 1891 1892 AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK, 1893 AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_ER_MARK, 1894 AVB_TX_CLK_MARK, AVB_COL_MARK, 1895 }; 1896 static const unsigned int avb_gmii_pins[] = { 1897 RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 20), 1898 RCAR_GP_PIN(5, 21), RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23), 1899 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25), 1900 1901 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), 1902 RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5), 1903 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7), 1904 1905 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 10), 1906 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 30), RCAR_GP_PIN(5, 17), 1907 RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 27), RCAR_GP_PIN(5, 28), 1908 RCAR_GP_PIN(5, 29), 1909 }; 1910 static const unsigned int avb_gmii_mux[] = { 1911 AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK, 1912 AVB_TXD3_MARK, AVB_TXD4_MARK, AVB_TXD5_MARK, 1913 AVB_TXD6_MARK, AVB_TXD7_MARK, 1914 1915 AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK, 1916 AVB_RXD3_MARK, AVB_RXD4_MARK, AVB_RXD5_MARK, 1917 AVB_RXD6_MARK, AVB_RXD7_MARK, 1918 1919 AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK, 1920 AVB_CRS_MARK, AVB_GTX_CLK_MARK, AVB_GTXREFCLK_MARK, 1921 AVB_TX_EN_MARK, AVB_TX_ER_MARK, AVB_TX_CLK_MARK, 1922 AVB_COL_MARK, 1923 }; 1924 1925 /* - CAN -------------------------------------------------------------------- */ 1926 1927 static const unsigned int can0_data_pins[] = { 1928 /* TX, RX */ 1929 RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 29), 1930 }; 1931 1932 static const unsigned int can0_data_mux[] = { 1933 CAN0_TX_MARK, CAN0_RX_MARK, 1934 }; 1935 1936 static const unsigned int can0_data_b_pins[] = { 1937 /* TX, RX */ 1938 RCAR_GP_PIN(7, 4), RCAR_GP_PIN(7, 3), 1939 }; 1940 1941 static const unsigned int can0_data_b_mux[] = { 1942 CAN0_TX_B_MARK, CAN0_RX_B_MARK, 1943 }; 1944 1945 static const unsigned int can0_data_c_pins[] = { 1946 /* TX, RX */ 1947 RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18), 1948 }; 1949 1950 static const unsigned int can0_data_c_mux[] = { 1951 CAN0_TX_C_MARK, CAN0_RX_C_MARK, 1952 }; 1953 1954 static const unsigned int can0_data_d_pins[] = { 1955 /* TX, RX */ 1956 RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 27), 1957 }; 1958 1959 static const unsigned int can0_data_d_mux[] = { 1960 CAN0_TX_D_MARK, CAN0_RX_D_MARK, 1961 }; 1962 1963 static const unsigned int can0_data_e_pins[] = { 1964 /* TX, RX */ 1965 RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 28), 1966 }; 1967 1968 static const unsigned int can0_data_e_mux[] = { 1969 CAN0_TX_E_MARK, CAN0_RX_E_MARK, 1970 }; 1971 1972 static const unsigned int can0_data_f_pins[] = { 1973 /* TX, RX */ 1974 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6), 1975 }; 1976 1977 static const unsigned int can0_data_f_mux[] = { 1978 CAN0_TX_F_MARK, CAN0_RX_F_MARK, 1979 }; 1980 1981 static const unsigned int can1_data_pins[] = { 1982 /* TX, RX */ 1983 RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 20), 1984 }; 1985 1986 static const unsigned int can1_data_mux[] = { 1987 CAN1_TX_MARK, CAN1_RX_MARK, 1988 }; 1989 1990 static const unsigned int can1_data_b_pins[] = { 1991 /* TX, RX */ 1992 RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9), 1993 }; 1994 1995 static const unsigned int can1_data_b_mux[] = { 1996 CAN1_TX_B_MARK, CAN1_RX_B_MARK, 1997 }; 1998 1999 static const unsigned int can1_data_c_pins[] = { 2000 /* TX, RX */ 2001 RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 19), 2002 }; 2003 2004 static const unsigned int can1_data_c_mux[] = { 2005 CAN1_TX_C_MARK, CAN1_RX_C_MARK, 2006 }; 2007 2008 static const unsigned int can1_data_d_pins[] = { 2009 /* TX, RX */ 2010 RCAR_GP_PIN(4, 29), RCAR_GP_PIN(4, 31), 2011 }; 2012 2013 static const unsigned int can1_data_d_mux[] = { 2014 CAN1_TX_D_MARK, CAN1_RX_D_MARK, 2015 }; 2016 2017 static const unsigned int can_clk_pins[] = { 2018 /* CLK */ 2019 RCAR_GP_PIN(7, 2), 2020 }; 2021 2022 static const unsigned int can_clk_mux[] = { 2023 CAN_CLK_MARK, 2024 }; 2025 2026 static const unsigned int can_clk_b_pins[] = { 2027 /* CLK */ 2028 RCAR_GP_PIN(5, 21), 2029 }; 2030 2031 static const unsigned int can_clk_b_mux[] = { 2032 CAN_CLK_B_MARK, 2033 }; 2034 2035 static const unsigned int can_clk_c_pins[] = { 2036 /* CLK */ 2037 RCAR_GP_PIN(4, 30), 2038 }; 2039 2040 static const unsigned int can_clk_c_mux[] = { 2041 CAN_CLK_C_MARK, 2042 }; 2043 2044 static const unsigned int can_clk_d_pins[] = { 2045 /* CLK */ 2046 RCAR_GP_PIN(7, 19), 2047 }; 2048 2049 static const unsigned int can_clk_d_mux[] = { 2050 CAN_CLK_D_MARK, 2051 }; 2052 2053 /* - DU --------------------------------------------------------------------- */ 2054 static const unsigned int du_rgb666_pins[] = { 2055 /* R[7:2], G[7:2], B[7:2] */ 2056 RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 5), 2057 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 2), 2058 RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13), 2059 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 10), 2060 RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21), 2061 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 18), 2062 }; 2063 static const unsigned int du_rgb666_mux[] = { 2064 DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK, 2065 DU1_DR3_MARK, DU1_DR2_MARK, 2066 DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK, 2067 DU1_DG3_MARK, DU1_DG2_MARK, 2068 DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK, 2069 DU1_DB3_MARK, DU1_DB2_MARK, 2070 }; 2071 static const unsigned int du_rgb888_pins[] = { 2072 /* R[7:0], G[7:0], B[7:0] */ 2073 RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 5), 2074 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 2), 2075 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0), 2076 RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13), 2077 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 10), 2078 RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8), 2079 RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21), 2080 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 18), 2081 RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16), 2082 }; 2083 static const unsigned int du_rgb888_mux[] = { 2084 DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK, 2085 DU1_DR3_MARK, DU1_DR2_MARK, DU1_DR1_MARK, DU1_DR0_MARK, 2086 DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK, 2087 DU1_DG3_MARK, DU1_DG2_MARK, DU1_DG1_MARK, DU1_DG0_MARK, 2088 DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK, 2089 DU1_DB3_MARK, DU1_DB2_MARK, DU1_DB1_MARK, DU1_DB0_MARK, 2090 }; 2091 static const unsigned int du_clk_out_0_pins[] = { 2092 /* CLKOUT */ 2093 RCAR_GP_PIN(3, 25), 2094 }; 2095 static const unsigned int du_clk_out_0_mux[] = { 2096 DU1_DOTCLKOUT0_MARK 2097 }; 2098 static const unsigned int du_clk_out_1_pins[] = { 2099 /* CLKOUT */ 2100 RCAR_GP_PIN(3, 26), 2101 }; 2102 static const unsigned int du_clk_out_1_mux[] = { 2103 DU1_DOTCLKOUT1_MARK 2104 }; 2105 static const unsigned int du_sync_pins[] = { 2106 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */ 2107 RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 27), 2108 }; 2109 static const unsigned int du_sync_mux[] = { 2110 DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK 2111 }; 2112 static const unsigned int du_oddf_pins[] = { 2113 /* EXDISP/EXODDF/EXCDE */ 2114 RCAR_GP_PIN(3, 29), 2115 }; 2116 static const unsigned int du_oddf_mux[] = { 2117 DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK, 2118 }; 2119 static const unsigned int du_cde_pins[] = { 2120 /* CDE */ 2121 RCAR_GP_PIN(3, 31), 2122 }; 2123 static const unsigned int du_cde_mux[] = { 2124 DU1_CDE_MARK, 2125 }; 2126 static const unsigned int du_disp_pins[] = { 2127 /* DISP */ 2128 RCAR_GP_PIN(3, 30), 2129 }; 2130 static const unsigned int du_disp_mux[] = { 2131 DU1_DISP_MARK, 2132 }; 2133 static const unsigned int du0_clk_in_pins[] = { 2134 /* CLKIN */ 2135 RCAR_GP_PIN(6, 31), 2136 }; 2137 static const unsigned int du0_clk_in_mux[] = { 2138 DU0_DOTCLKIN_MARK 2139 }; 2140 static const unsigned int du1_clk_in_pins[] = { 2141 /* CLKIN */ 2142 RCAR_GP_PIN(3, 24), 2143 }; 2144 static const unsigned int du1_clk_in_mux[] = { 2145 DU1_DOTCLKIN_MARK 2146 }; 2147 static const unsigned int du1_clk_in_b_pins[] = { 2148 /* CLKIN */ 2149 RCAR_GP_PIN(7, 19), 2150 }; 2151 static const unsigned int du1_clk_in_b_mux[] = { 2152 DU1_DOTCLKIN_B_MARK, 2153 }; 2154 static const unsigned int du1_clk_in_c_pins[] = { 2155 /* CLKIN */ 2156 RCAR_GP_PIN(7, 20), 2157 }; 2158 static const unsigned int du1_clk_in_c_mux[] = { 2159 DU1_DOTCLKIN_C_MARK, 2160 }; 2161 /* - ETH -------------------------------------------------------------------- */ 2162 static const unsigned int eth_link_pins[] = { 2163 /* LINK */ 2164 RCAR_GP_PIN(5, 18), 2165 }; 2166 static const unsigned int eth_link_mux[] = { 2167 ETH_LINK_MARK, 2168 }; 2169 static const unsigned int eth_magic_pins[] = { 2170 /* MAGIC */ 2171 RCAR_GP_PIN(5, 22), 2172 }; 2173 static const unsigned int eth_magic_mux[] = { 2174 ETH_MAGIC_MARK, 2175 }; 2176 static const unsigned int eth_mdio_pins[] = { 2177 /* MDC, MDIO */ 2178 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 13), 2179 }; 2180 static const unsigned int eth_mdio_mux[] = { 2181 ETH_MDC_MARK, ETH_MDIO_MARK, 2182 }; 2183 static const unsigned int eth_rmii_pins[] = { 2184 /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */ 2185 RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 15), 2186 RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 23), RCAR_GP_PIN(5, 20), 2187 RCAR_GP_PIN(5, 21), RCAR_GP_PIN(5, 19), 2188 }; 2189 static const unsigned int eth_rmii_mux[] = { 2190 ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK, 2191 ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REFCLK_MARK, 2192 }; 2193 2194 /* - HSCIF0 ----------------------------------------------------------------- */ 2195 static const unsigned int hscif0_data_pins[] = { 2196 /* RX, TX */ 2197 RCAR_GP_PIN(7, 3), RCAR_GP_PIN(7, 4), 2198 }; 2199 static const unsigned int hscif0_data_mux[] = { 2200 HRX0_MARK, HTX0_MARK, 2201 }; 2202 static const unsigned int hscif0_clk_pins[] = { 2203 /* SCK */ 2204 RCAR_GP_PIN(7, 2), 2205 }; 2206 static const unsigned int hscif0_clk_mux[] = { 2207 HSCK0_MARK, 2208 }; 2209 static const unsigned int hscif0_ctrl_pins[] = { 2210 /* RTS, CTS */ 2211 RCAR_GP_PIN(7, 1), RCAR_GP_PIN(7, 0), 2212 }; 2213 static const unsigned int hscif0_ctrl_mux[] = { 2214 HRTS0_N_MARK, HCTS0_N_MARK, 2215 }; 2216 static const unsigned int hscif0_data_b_pins[] = { 2217 /* RX, TX */ 2218 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 15), 2219 }; 2220 static const unsigned int hscif0_data_b_mux[] = { 2221 HRX0_B_MARK, HTX0_B_MARK, 2222 }; 2223 static const unsigned int hscif0_ctrl_b_pins[] = { 2224 /* RTS, CTS */ 2225 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13), 2226 }; 2227 static const unsigned int hscif0_ctrl_b_mux[] = { 2228 HRTS0_N_B_MARK, HCTS0_N_B_MARK, 2229 }; 2230 static const unsigned int hscif0_data_c_pins[] = { 2231 /* RX, TX */ 2232 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), 2233 }; 2234 static const unsigned int hscif0_data_c_mux[] = { 2235 HRX0_C_MARK, HTX0_C_MARK, 2236 }; 2237 static const unsigned int hscif0_clk_c_pins[] = { 2238 /* SCK */ 2239 RCAR_GP_PIN(5, 31), 2240 }; 2241 static const unsigned int hscif0_clk_c_mux[] = { 2242 HSCK0_C_MARK, 2243 }; 2244 /* - HSCIF1 ----------------------------------------------------------------- */ 2245 static const unsigned int hscif1_data_pins[] = { 2246 /* RX, TX */ 2247 RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6), 2248 }; 2249 static const unsigned int hscif1_data_mux[] = { 2250 HRX1_MARK, HTX1_MARK, 2251 }; 2252 static const unsigned int hscif1_clk_pins[] = { 2253 /* SCK */ 2254 RCAR_GP_PIN(7, 7), 2255 }; 2256 static const unsigned int hscif1_clk_mux[] = { 2257 HSCK1_MARK, 2258 }; 2259 static const unsigned int hscif1_ctrl_pins[] = { 2260 /* RTS, CTS */ 2261 RCAR_GP_PIN(7, 9), RCAR_GP_PIN(7, 8), 2262 }; 2263 static const unsigned int hscif1_ctrl_mux[] = { 2264 HRTS1_N_MARK, HCTS1_N_MARK, 2265 }; 2266 static const unsigned int hscif1_data_b_pins[] = { 2267 /* RX, TX */ 2268 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18), 2269 }; 2270 static const unsigned int hscif1_data_b_mux[] = { 2271 HRX1_B_MARK, HTX1_B_MARK, 2272 }; 2273 static const unsigned int hscif1_data_c_pins[] = { 2274 /* RX, TX */ 2275 RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 15), 2276 }; 2277 static const unsigned int hscif1_data_c_mux[] = { 2278 HRX1_C_MARK, HTX1_C_MARK, 2279 }; 2280 static const unsigned int hscif1_clk_c_pins[] = { 2281 /* SCK */ 2282 RCAR_GP_PIN(7, 16), 2283 }; 2284 static const unsigned int hscif1_clk_c_mux[] = { 2285 HSCK1_C_MARK, 2286 }; 2287 static const unsigned int hscif1_ctrl_c_pins[] = { 2288 /* RTS, CTS */ 2289 RCAR_GP_PIN(7, 18), RCAR_GP_PIN(7, 17), 2290 }; 2291 static const unsigned int hscif1_ctrl_c_mux[] = { 2292 HRTS1_N_C_MARK, HCTS1_N_C_MARK, 2293 }; 2294 static const unsigned int hscif1_data_d_pins[] = { 2295 /* RX, TX */ 2296 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 18), 2297 }; 2298 static const unsigned int hscif1_data_d_mux[] = { 2299 HRX1_D_MARK, HTX1_D_MARK, 2300 }; 2301 static const unsigned int hscif1_data_e_pins[] = { 2302 /* RX, TX */ 2303 RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 15), 2304 }; 2305 static const unsigned int hscif1_data_e_mux[] = { 2306 HRX1_C_MARK, HTX1_C_MARK, 2307 }; 2308 static const unsigned int hscif1_clk_e_pins[] = { 2309 /* SCK */ 2310 RCAR_GP_PIN(2, 6), 2311 }; 2312 static const unsigned int hscif1_clk_e_mux[] = { 2313 HSCK1_E_MARK, 2314 }; 2315 static const unsigned int hscif1_ctrl_e_pins[] = { 2316 /* RTS, CTS */ 2317 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 7), 2318 }; 2319 static const unsigned int hscif1_ctrl_e_mux[] = { 2320 HRTS1_N_E_MARK, HCTS1_N_E_MARK, 2321 }; 2322 /* - HSCIF2 ----------------------------------------------------------------- */ 2323 static const unsigned int hscif2_data_pins[] = { 2324 /* RX, TX */ 2325 RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17), 2326 }; 2327 static const unsigned int hscif2_data_mux[] = { 2328 HRX2_MARK, HTX2_MARK, 2329 }; 2330 static const unsigned int hscif2_clk_pins[] = { 2331 /* SCK */ 2332 RCAR_GP_PIN(4, 15), 2333 }; 2334 static const unsigned int hscif2_clk_mux[] = { 2335 HSCK2_MARK, 2336 }; 2337 static const unsigned int hscif2_ctrl_pins[] = { 2338 /* RTS, CTS */ 2339 RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13), 2340 }; 2341 static const unsigned int hscif2_ctrl_mux[] = { 2342 HRTS2_N_MARK, HCTS2_N_MARK, 2343 }; 2344 static const unsigned int hscif2_data_b_pins[] = { 2345 /* RX, TX */ 2346 RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 22), 2347 }; 2348 static const unsigned int hscif2_data_b_mux[] = { 2349 HRX2_B_MARK, HTX2_B_MARK, 2350 }; 2351 static const unsigned int hscif2_ctrl_b_pins[] = { 2352 /* RTS, CTS */ 2353 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 21), 2354 }; 2355 static const unsigned int hscif2_ctrl_b_mux[] = { 2356 HRTS2_N_B_MARK, HCTS2_N_B_MARK, 2357 }; 2358 static const unsigned int hscif2_data_c_pins[] = { 2359 /* RX, TX */ 2360 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), 2361 }; 2362 static const unsigned int hscif2_data_c_mux[] = { 2363 HRX2_C_MARK, HTX2_C_MARK, 2364 }; 2365 static const unsigned int hscif2_clk_c_pins[] = { 2366 /* SCK */ 2367 RCAR_GP_PIN(5, 31), 2368 }; 2369 static const unsigned int hscif2_clk_c_mux[] = { 2370 HSCK2_C_MARK, 2371 }; 2372 static const unsigned int hscif2_data_d_pins[] = { 2373 /* RX, TX */ 2374 RCAR_GP_PIN(1, 20), RCAR_GP_PIN(5, 31), 2375 }; 2376 static const unsigned int hscif2_data_d_mux[] = { 2377 HRX2_B_MARK, HTX2_D_MARK, 2378 }; 2379 /* - I2C0 ------------------------------------------------------------------- */ 2380 static const unsigned int i2c0_pins[] = { 2381 /* SCL, SDA */ 2382 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25), 2383 }; 2384 static const unsigned int i2c0_mux[] = { 2385 I2C0_SCL_MARK, I2C0_SDA_MARK, 2386 }; 2387 static const unsigned int i2c0_b_pins[] = { 2388 /* SCL, SDA */ 2389 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), 2390 }; 2391 static const unsigned int i2c0_b_mux[] = { 2392 I2C0_SCL_B_MARK, I2C0_SDA_B_MARK, 2393 }; 2394 static const unsigned int i2c0_c_pins[] = { 2395 /* SCL, SDA */ 2396 RCAR_GP_PIN(0, 16), RCAR_GP_PIN(1, 1), 2397 }; 2398 static const unsigned int i2c0_c_mux[] = { 2399 I2C0_SCL_C_MARK, I2C0_SDA_C_MARK, 2400 }; 2401 /* - I2C1 ------------------------------------------------------------------- */ 2402 static const unsigned int i2c1_pins[] = { 2403 /* SCL, SDA */ 2404 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 11), 2405 }; 2406 static const unsigned int i2c1_mux[] = { 2407 I2C1_SCL_MARK, I2C1_SDA_MARK, 2408 }; 2409 static const unsigned int i2c1_b_pins[] = { 2410 /* SCL, SDA */ 2411 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), 2412 }; 2413 static const unsigned int i2c1_b_mux[] = { 2414 I2C1_SCL_B_MARK, I2C1_SDA_B_MARK, 2415 }; 2416 static const unsigned int i2c1_c_pins[] = { 2417 /* SCL, SDA */ 2418 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15), 2419 }; 2420 static const unsigned int i2c1_c_mux[] = { 2421 I2C1_SCL_C_MARK, I2C1_SDA_C_MARK, 2422 }; 2423 static const unsigned int i2c1_d_pins[] = { 2424 /* SCL, SDA */ 2425 RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26), 2426 }; 2427 static const unsigned int i2c1_d_mux[] = { 2428 I2C1_SCL_D_MARK, I2C1_SDA_D_MARK, 2429 }; 2430 static const unsigned int i2c1_e_pins[] = { 2431 /* SCL, SDA */ 2432 RCAR_GP_PIN(7, 15), RCAR_GP_PIN(7, 16), 2433 }; 2434 static const unsigned int i2c1_e_mux[] = { 2435 I2C1_SCL_E_MARK, I2C1_SDA_E_MARK, 2436 }; 2437 /* - I2C2 ------------------------------------------------------------------- */ 2438 static const unsigned int i2c2_pins[] = { 2439 /* SCL, SDA */ 2440 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), 2441 }; 2442 static const unsigned int i2c2_mux[] = { 2443 I2C2_SCL_MARK, I2C2_SDA_MARK, 2444 }; 2445 static const unsigned int i2c2_b_pins[] = { 2446 /* SCL, SDA */ 2447 RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 29), 2448 }; 2449 static const unsigned int i2c2_b_mux[] = { 2450 I2C2_SCL_B_MARK, I2C2_SDA_B_MARK, 2451 }; 2452 static const unsigned int i2c2_c_pins[] = { 2453 /* SCL, SDA */ 2454 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14), 2455 }; 2456 static const unsigned int i2c2_c_mux[] = { 2457 I2C2_SCL_C_MARK, I2C2_SDA_C_MARK, 2458 }; 2459 static const unsigned int i2c2_d_pins[] = { 2460 /* SCL, SDA */ 2461 RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18), 2462 }; 2463 static const unsigned int i2c2_d_mux[] = { 2464 I2C2_SCL_D_MARK, I2C2_SDA_D_MARK, 2465 }; 2466 /* - I2C3 ------------------------------------------------------------------- */ 2467 static const unsigned int i2c3_pins[] = { 2468 /* SCL, SDA */ 2469 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16), 2470 }; 2471 static const unsigned int i2c3_mux[] = { 2472 I2C3_SCL_MARK, I2C3_SDA_MARK, 2473 }; 2474 static const unsigned int i2c3_b_pins[] = { 2475 /* SCL, SDA */ 2476 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16), 2477 }; 2478 static const unsigned int i2c3_b_mux[] = { 2479 I2C3_SCL_B_MARK, I2C3_SDA_B_MARK, 2480 }; 2481 static const unsigned int i2c3_c_pins[] = { 2482 /* SCL, SDA */ 2483 RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23), 2484 }; 2485 static const unsigned int i2c3_c_mux[] = { 2486 I2C3_SCL_C_MARK, I2C3_SDA_C_MARK, 2487 }; 2488 static const unsigned int i2c3_d_pins[] = { 2489 /* SCL, SDA */ 2490 RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28), 2491 }; 2492 static const unsigned int i2c3_d_mux[] = { 2493 I2C3_SCL_D_MARK, I2C3_SDA_D_MARK, 2494 }; 2495 /* - I2C4 ------------------------------------------------------------------- */ 2496 static const unsigned int i2c4_pins[] = { 2497 /* SCL, SDA */ 2498 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14), 2499 }; 2500 static const unsigned int i2c4_mux[] = { 2501 I2C4_SCL_MARK, I2C4_SDA_MARK, 2502 }; 2503 static const unsigned int i2c4_b_pins[] = { 2504 /* SCL, SDA */ 2505 RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28), 2506 }; 2507 static const unsigned int i2c4_b_mux[] = { 2508 I2C4_SCL_B_MARK, I2C4_SDA_B_MARK, 2509 }; 2510 static const unsigned int i2c4_c_pins[] = { 2511 /* SCL, SDA */ 2512 RCAR_GP_PIN(7, 13), RCAR_GP_PIN(7, 14), 2513 }; 2514 static const unsigned int i2c4_c_mux[] = { 2515 I2C4_SCL_C_MARK, I2C4_SDA_C_MARK, 2516 }; 2517 /* - I2C7 ------------------------------------------------------------------- */ 2518 static const unsigned int i2c7_pins[] = { 2519 /* SCL, SDA */ 2520 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16), 2521 }; 2522 static const unsigned int i2c7_mux[] = { 2523 IIC0_SCL_MARK, IIC0_SDA_MARK, 2524 }; 2525 static const unsigned int i2c7_b_pins[] = { 2526 /* SCL, SDA */ 2527 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), 2528 }; 2529 static const unsigned int i2c7_b_mux[] = { 2530 IIC0_SCL_B_MARK, IIC0_SDA_B_MARK, 2531 }; 2532 static const unsigned int i2c7_c_pins[] = { 2533 /* SCL, SDA */ 2534 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29), 2535 }; 2536 static const unsigned int i2c7_c_mux[] = { 2537 IIC0_SCL_C_MARK, IIC0_SDA_C_MARK, 2538 }; 2539 /* - I2C8 ------------------------------------------------------------------- */ 2540 static const unsigned int i2c8_pins[] = { 2541 /* SCL, SDA */ 2542 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14), 2543 }; 2544 static const unsigned int i2c8_mux[] = { 2545 IIC1_SCL_MARK, IIC1_SDA_MARK, 2546 }; 2547 static const unsigned int i2c8_b_pins[] = { 2548 /* SCL, SDA */ 2549 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), 2550 }; 2551 static const unsigned int i2c8_b_mux[] = { 2552 IIC1_SCL_B_MARK, IIC1_SDA_B_MARK, 2553 }; 2554 static const unsigned int i2c8_c_pins[] = { 2555 /* SCL, SDA */ 2556 RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23), 2557 }; 2558 static const unsigned int i2c8_c_mux[] = { 2559 IIC1_SCL_C_MARK, IIC1_SDA_C_MARK, 2560 }; 2561 /* - INTC ------------------------------------------------------------------- */ 2562 static const unsigned int intc_irq0_pins[] = { 2563 /* IRQ */ 2564 RCAR_GP_PIN(7, 10), 2565 }; 2566 static const unsigned int intc_irq0_mux[] = { 2567 IRQ0_MARK, 2568 }; 2569 static const unsigned int intc_irq1_pins[] = { 2570 /* IRQ */ 2571 RCAR_GP_PIN(7, 11), 2572 }; 2573 static const unsigned int intc_irq1_mux[] = { 2574 IRQ1_MARK, 2575 }; 2576 static const unsigned int intc_irq2_pins[] = { 2577 /* IRQ */ 2578 RCAR_GP_PIN(7, 12), 2579 }; 2580 static const unsigned int intc_irq2_mux[] = { 2581 IRQ2_MARK, 2582 }; 2583 static const unsigned int intc_irq3_pins[] = { 2584 /* IRQ */ 2585 RCAR_GP_PIN(7, 13), 2586 }; 2587 static const unsigned int intc_irq3_mux[] = { 2588 IRQ3_MARK, 2589 }; 2590 2591 #if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793) 2592 /* - MLB+ ------------------------------------------------------------------- */ 2593 static const unsigned int mlb_3pin_pins[] = { 2594 RCAR_GP_PIN(7, 7), RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9), 2595 }; 2596 static const unsigned int mlb_3pin_mux[] = { 2597 MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK, 2598 }; 2599 #endif /* CONFIG_PINCTRL_PFC_R8A7791 || CONFIG_PINCTRL_PFC_R8A7793 */ 2600 2601 /* - MMCIF ------------------------------------------------------------------ */ 2602 static const unsigned int mmc_data1_pins[] = { 2603 /* D[0] */ 2604 RCAR_GP_PIN(6, 18), 2605 }; 2606 static const unsigned int mmc_data1_mux[] = { 2607 MMC_D0_MARK, 2608 }; 2609 static const unsigned int mmc_data4_pins[] = { 2610 /* D[0:3] */ 2611 RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19), 2612 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21), 2613 }; 2614 static const unsigned int mmc_data4_mux[] = { 2615 MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK, 2616 }; 2617 static const unsigned int mmc_data8_pins[] = { 2618 /* D[0:7] */ 2619 RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19), 2620 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21), 2621 RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23), 2622 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29), 2623 }; 2624 static const unsigned int mmc_data8_mux[] = { 2625 MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK, 2626 MMC_D4_MARK, MMC_D5_MARK, MMC_D6_MARK, MMC_D7_MARK, 2627 }; 2628 static const unsigned int mmc_data8_b_pins[] = { 2629 /* D[0:7] */ 2630 RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19), 2631 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21), 2632 RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23), 2633 RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 7), 2634 }; 2635 static const unsigned int mmc_data8_b_mux[] = { 2636 MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK, 2637 MMC_D4_MARK, MMC_D5_MARK, MMC_D6_B_MARK, MMC_D7_B_MARK, 2638 }; 2639 static const unsigned int mmc_ctrl_pins[] = { 2640 /* CLK, CMD */ 2641 RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17), 2642 }; 2643 static const unsigned int mmc_ctrl_mux[] = { 2644 MMC_CLK_MARK, MMC_CMD_MARK, 2645 }; 2646 /* - MSIOF0 ----------------------------------------------------------------- */ 2647 static const unsigned int msiof0_clk_pins[] = { 2648 /* SCK */ 2649 RCAR_GP_PIN(6, 24), 2650 }; 2651 static const unsigned int msiof0_clk_mux[] = { 2652 MSIOF0_SCK_MARK, 2653 }; 2654 static const unsigned int msiof0_sync_pins[] = { 2655 /* SYNC */ 2656 RCAR_GP_PIN(6, 25), 2657 }; 2658 static const unsigned int msiof0_sync_mux[] = { 2659 MSIOF0_SYNC_MARK, 2660 }; 2661 static const unsigned int msiof0_ss1_pins[] = { 2662 /* SS1 */ 2663 RCAR_GP_PIN(6, 28), 2664 }; 2665 static const unsigned int msiof0_ss1_mux[] = { 2666 MSIOF0_SS1_MARK, 2667 }; 2668 static const unsigned int msiof0_ss2_pins[] = { 2669 /* SS2 */ 2670 RCAR_GP_PIN(6, 29), 2671 }; 2672 static const unsigned int msiof0_ss2_mux[] = { 2673 MSIOF0_SS2_MARK, 2674 }; 2675 static const unsigned int msiof0_rx_pins[] = { 2676 /* RXD */ 2677 RCAR_GP_PIN(6, 27), 2678 }; 2679 static const unsigned int msiof0_rx_mux[] = { 2680 MSIOF0_RXD_MARK, 2681 }; 2682 static const unsigned int msiof0_tx_pins[] = { 2683 /* TXD */ 2684 RCAR_GP_PIN(6, 26), 2685 }; 2686 static const unsigned int msiof0_tx_mux[] = { 2687 MSIOF0_TXD_MARK, 2688 }; 2689 2690 static const unsigned int msiof0_clk_b_pins[] = { 2691 /* SCK */ 2692 RCAR_GP_PIN(0, 16), 2693 }; 2694 static const unsigned int msiof0_clk_b_mux[] = { 2695 MSIOF0_SCK_B_MARK, 2696 }; 2697 static const unsigned int msiof0_sync_b_pins[] = { 2698 /* SYNC */ 2699 RCAR_GP_PIN(0, 17), 2700 }; 2701 static const unsigned int msiof0_sync_b_mux[] = { 2702 MSIOF0_SYNC_B_MARK, 2703 }; 2704 static const unsigned int msiof0_ss1_b_pins[] = { 2705 /* SS1 */ 2706 RCAR_GP_PIN(0, 18), 2707 }; 2708 static const unsigned int msiof0_ss1_b_mux[] = { 2709 MSIOF0_SS1_B_MARK, 2710 }; 2711 static const unsigned int msiof0_ss2_b_pins[] = { 2712 /* SS2 */ 2713 RCAR_GP_PIN(0, 19), 2714 }; 2715 static const unsigned int msiof0_ss2_b_mux[] = { 2716 MSIOF0_SS2_B_MARK, 2717 }; 2718 static const unsigned int msiof0_rx_b_pins[] = { 2719 /* RXD */ 2720 RCAR_GP_PIN(0, 21), 2721 }; 2722 static const unsigned int msiof0_rx_b_mux[] = { 2723 MSIOF0_RXD_B_MARK, 2724 }; 2725 static const unsigned int msiof0_tx_b_pins[] = { 2726 /* TXD */ 2727 RCAR_GP_PIN(0, 20), 2728 }; 2729 static const unsigned int msiof0_tx_b_mux[] = { 2730 MSIOF0_TXD_B_MARK, 2731 }; 2732 2733 static const unsigned int msiof0_clk_c_pins[] = { 2734 /* SCK */ 2735 RCAR_GP_PIN(5, 26), 2736 }; 2737 static const unsigned int msiof0_clk_c_mux[] = { 2738 MSIOF0_SCK_C_MARK, 2739 }; 2740 static const unsigned int msiof0_sync_c_pins[] = { 2741 /* SYNC */ 2742 RCAR_GP_PIN(5, 25), 2743 }; 2744 static const unsigned int msiof0_sync_c_mux[] = { 2745 MSIOF0_SYNC_C_MARK, 2746 }; 2747 static const unsigned int msiof0_ss1_c_pins[] = { 2748 /* SS1 */ 2749 RCAR_GP_PIN(5, 27), 2750 }; 2751 static const unsigned int msiof0_ss1_c_mux[] = { 2752 MSIOF0_SS1_C_MARK, 2753 }; 2754 static const unsigned int msiof0_ss2_c_pins[] = { 2755 /* SS2 */ 2756 RCAR_GP_PIN(5, 28), 2757 }; 2758 static const unsigned int msiof0_ss2_c_mux[] = { 2759 MSIOF0_SS2_C_MARK, 2760 }; 2761 static const unsigned int msiof0_rx_c_pins[] = { 2762 /* RXD */ 2763 RCAR_GP_PIN(5, 29), 2764 }; 2765 static const unsigned int msiof0_rx_c_mux[] = { 2766 MSIOF0_RXD_C_MARK, 2767 }; 2768 static const unsigned int msiof0_tx_c_pins[] = { 2769 /* TXD */ 2770 RCAR_GP_PIN(5, 30), 2771 }; 2772 static const unsigned int msiof0_tx_c_mux[] = { 2773 MSIOF0_TXD_C_MARK, 2774 }; 2775 /* - MSIOF1 ----------------------------------------------------------------- */ 2776 static const unsigned int msiof1_clk_pins[] = { 2777 /* SCK */ 2778 RCAR_GP_PIN(0, 22), 2779 }; 2780 static const unsigned int msiof1_clk_mux[] = { 2781 MSIOF1_SCK_MARK, 2782 }; 2783 static const unsigned int msiof1_sync_pins[] = { 2784 /* SYNC */ 2785 RCAR_GP_PIN(0, 23), 2786 }; 2787 static const unsigned int msiof1_sync_mux[] = { 2788 MSIOF1_SYNC_MARK, 2789 }; 2790 static const unsigned int msiof1_ss1_pins[] = { 2791 /* SS1 */ 2792 RCAR_GP_PIN(0, 24), 2793 }; 2794 static const unsigned int msiof1_ss1_mux[] = { 2795 MSIOF1_SS1_MARK, 2796 }; 2797 static const unsigned int msiof1_ss2_pins[] = { 2798 /* SS2 */ 2799 RCAR_GP_PIN(0, 25), 2800 }; 2801 static const unsigned int msiof1_ss2_mux[] = { 2802 MSIOF1_SS2_MARK, 2803 }; 2804 static const unsigned int msiof1_rx_pins[] = { 2805 /* RXD */ 2806 RCAR_GP_PIN(0, 27), 2807 }; 2808 static const unsigned int msiof1_rx_mux[] = { 2809 MSIOF1_RXD_MARK, 2810 }; 2811 static const unsigned int msiof1_tx_pins[] = { 2812 /* TXD */ 2813 RCAR_GP_PIN(0, 26), 2814 }; 2815 static const unsigned int msiof1_tx_mux[] = { 2816 MSIOF1_TXD_MARK, 2817 }; 2818 2819 static const unsigned int msiof1_clk_b_pins[] = { 2820 /* SCK */ 2821 RCAR_GP_PIN(2, 29), 2822 }; 2823 static const unsigned int msiof1_clk_b_mux[] = { 2824 MSIOF1_SCK_B_MARK, 2825 }; 2826 static const unsigned int msiof1_sync_b_pins[] = { 2827 /* SYNC */ 2828 RCAR_GP_PIN(2, 30), 2829 }; 2830 static const unsigned int msiof1_sync_b_mux[] = { 2831 MSIOF1_SYNC_B_MARK, 2832 }; 2833 static const unsigned int msiof1_ss1_b_pins[] = { 2834 /* SS1 */ 2835 RCAR_GP_PIN(2, 31), 2836 }; 2837 static const unsigned int msiof1_ss1_b_mux[] = { 2838 MSIOF1_SS1_B_MARK, 2839 }; 2840 static const unsigned int msiof1_ss2_b_pins[] = { 2841 /* SS2 */ 2842 RCAR_GP_PIN(7, 16), 2843 }; 2844 static const unsigned int msiof1_ss2_b_mux[] = { 2845 MSIOF1_SS2_B_MARK, 2846 }; 2847 static const unsigned int msiof1_rx_b_pins[] = { 2848 /* RXD */ 2849 RCAR_GP_PIN(7, 18), 2850 }; 2851 static const unsigned int msiof1_rx_b_mux[] = { 2852 MSIOF1_RXD_B_MARK, 2853 }; 2854 static const unsigned int msiof1_tx_b_pins[] = { 2855 /* TXD */ 2856 RCAR_GP_PIN(7, 17), 2857 }; 2858 static const unsigned int msiof1_tx_b_mux[] = { 2859 MSIOF1_TXD_B_MARK, 2860 }; 2861 2862 static const unsigned int msiof1_clk_c_pins[] = { 2863 /* SCK */ 2864 RCAR_GP_PIN(2, 15), 2865 }; 2866 static const unsigned int msiof1_clk_c_mux[] = { 2867 MSIOF1_SCK_C_MARK, 2868 }; 2869 static const unsigned int msiof1_sync_c_pins[] = { 2870 /* SYNC */ 2871 RCAR_GP_PIN(2, 16), 2872 }; 2873 static const unsigned int msiof1_sync_c_mux[] = { 2874 MSIOF1_SYNC_C_MARK, 2875 }; 2876 static const unsigned int msiof1_rx_c_pins[] = { 2877 /* RXD */ 2878 RCAR_GP_PIN(2, 18), 2879 }; 2880 static const unsigned int msiof1_rx_c_mux[] = { 2881 MSIOF1_RXD_C_MARK, 2882 }; 2883 static const unsigned int msiof1_tx_c_pins[] = { 2884 /* TXD */ 2885 RCAR_GP_PIN(2, 17), 2886 }; 2887 static const unsigned int msiof1_tx_c_mux[] = { 2888 MSIOF1_TXD_C_MARK, 2889 }; 2890 2891 static const unsigned int msiof1_clk_d_pins[] = { 2892 /* SCK */ 2893 RCAR_GP_PIN(0, 28), 2894 }; 2895 static const unsigned int msiof1_clk_d_mux[] = { 2896 MSIOF1_SCK_D_MARK, 2897 }; 2898 static const unsigned int msiof1_sync_d_pins[] = { 2899 /* SYNC */ 2900 RCAR_GP_PIN(0, 30), 2901 }; 2902 static const unsigned int msiof1_sync_d_mux[] = { 2903 MSIOF1_SYNC_D_MARK, 2904 }; 2905 static const unsigned int msiof1_ss1_d_pins[] = { 2906 /* SS1 */ 2907 RCAR_GP_PIN(0, 29), 2908 }; 2909 static const unsigned int msiof1_ss1_d_mux[] = { 2910 MSIOF1_SS1_D_MARK, 2911 }; 2912 static const unsigned int msiof1_rx_d_pins[] = { 2913 /* RXD */ 2914 RCAR_GP_PIN(0, 27), 2915 }; 2916 static const unsigned int msiof1_rx_d_mux[] = { 2917 MSIOF1_RXD_D_MARK, 2918 }; 2919 static const unsigned int msiof1_tx_d_pins[] = { 2920 /* TXD */ 2921 RCAR_GP_PIN(0, 26), 2922 }; 2923 static const unsigned int msiof1_tx_d_mux[] = { 2924 MSIOF1_TXD_D_MARK, 2925 }; 2926 2927 static const unsigned int msiof1_clk_e_pins[] = { 2928 /* SCK */ 2929 RCAR_GP_PIN(5, 18), 2930 }; 2931 static const unsigned int msiof1_clk_e_mux[] = { 2932 MSIOF1_SCK_E_MARK, 2933 }; 2934 static const unsigned int msiof1_sync_e_pins[] = { 2935 /* SYNC */ 2936 RCAR_GP_PIN(5, 19), 2937 }; 2938 static const unsigned int msiof1_sync_e_mux[] = { 2939 MSIOF1_SYNC_E_MARK, 2940 }; 2941 static const unsigned int msiof1_rx_e_pins[] = { 2942 /* RXD */ 2943 RCAR_GP_PIN(5, 17), 2944 }; 2945 static const unsigned int msiof1_rx_e_mux[] = { 2946 MSIOF1_RXD_E_MARK, 2947 }; 2948 static const unsigned int msiof1_tx_e_pins[] = { 2949 /* TXD */ 2950 RCAR_GP_PIN(5, 20), 2951 }; 2952 static const unsigned int msiof1_tx_e_mux[] = { 2953 MSIOF1_TXD_E_MARK, 2954 }; 2955 /* - MSIOF2 ----------------------------------------------------------------- */ 2956 static const unsigned int msiof2_clk_pins[] = { 2957 /* SCK */ 2958 RCAR_GP_PIN(1, 13), 2959 }; 2960 static const unsigned int msiof2_clk_mux[] = { 2961 MSIOF2_SCK_MARK, 2962 }; 2963 static const unsigned int msiof2_sync_pins[] = { 2964 /* SYNC */ 2965 RCAR_GP_PIN(1, 14), 2966 }; 2967 static const unsigned int msiof2_sync_mux[] = { 2968 MSIOF2_SYNC_MARK, 2969 }; 2970 static const unsigned int msiof2_ss1_pins[] = { 2971 /* SS1 */ 2972 RCAR_GP_PIN(1, 17), 2973 }; 2974 static const unsigned int msiof2_ss1_mux[] = { 2975 MSIOF2_SS1_MARK, 2976 }; 2977 static const unsigned int msiof2_ss2_pins[] = { 2978 /* SS2 */ 2979 RCAR_GP_PIN(1, 18), 2980 }; 2981 static const unsigned int msiof2_ss2_mux[] = { 2982 MSIOF2_SS2_MARK, 2983 }; 2984 static const unsigned int msiof2_rx_pins[] = { 2985 /* RXD */ 2986 RCAR_GP_PIN(1, 16), 2987 }; 2988 static const unsigned int msiof2_rx_mux[] = { 2989 MSIOF2_RXD_MARK, 2990 }; 2991 static const unsigned int msiof2_tx_pins[] = { 2992 /* TXD */ 2993 RCAR_GP_PIN(1, 15), 2994 }; 2995 static const unsigned int msiof2_tx_mux[] = { 2996 MSIOF2_TXD_MARK, 2997 }; 2998 2999 static const unsigned int msiof2_clk_b_pins[] = { 3000 /* SCK */ 3001 RCAR_GP_PIN(3, 0), 3002 }; 3003 static const unsigned int msiof2_clk_b_mux[] = { 3004 MSIOF2_SCK_B_MARK, 3005 }; 3006 static const unsigned int msiof2_sync_b_pins[] = { 3007 /* SYNC */ 3008 RCAR_GP_PIN(3, 1), 3009 }; 3010 static const unsigned int msiof2_sync_b_mux[] = { 3011 MSIOF2_SYNC_B_MARK, 3012 }; 3013 static const unsigned int msiof2_ss1_b_pins[] = { 3014 /* SS1 */ 3015 RCAR_GP_PIN(3, 8), 3016 }; 3017 static const unsigned int msiof2_ss1_b_mux[] = { 3018 MSIOF2_SS1_B_MARK, 3019 }; 3020 static const unsigned int msiof2_ss2_b_pins[] = { 3021 /* SS2 */ 3022 RCAR_GP_PIN(3, 9), 3023 }; 3024 static const unsigned int msiof2_ss2_b_mux[] = { 3025 MSIOF2_SS2_B_MARK, 3026 }; 3027 static const unsigned int msiof2_rx_b_pins[] = { 3028 /* RXD */ 3029 RCAR_GP_PIN(3, 17), 3030 }; 3031 static const unsigned int msiof2_rx_b_mux[] = { 3032 MSIOF2_RXD_B_MARK, 3033 }; 3034 static const unsigned int msiof2_tx_b_pins[] = { 3035 /* TXD */ 3036 RCAR_GP_PIN(3, 16), 3037 }; 3038 static const unsigned int msiof2_tx_b_mux[] = { 3039 MSIOF2_TXD_B_MARK, 3040 }; 3041 3042 static const unsigned int msiof2_clk_c_pins[] = { 3043 /* SCK */ 3044 RCAR_GP_PIN(2, 2), 3045 }; 3046 static const unsigned int msiof2_clk_c_mux[] = { 3047 MSIOF2_SCK_C_MARK, 3048 }; 3049 static const unsigned int msiof2_sync_c_pins[] = { 3050 /* SYNC */ 3051 RCAR_GP_PIN(2, 3), 3052 }; 3053 static const unsigned int msiof2_sync_c_mux[] = { 3054 MSIOF2_SYNC_C_MARK, 3055 }; 3056 static const unsigned int msiof2_rx_c_pins[] = { 3057 /* RXD */ 3058 RCAR_GP_PIN(2, 5), 3059 }; 3060 static const unsigned int msiof2_rx_c_mux[] = { 3061 MSIOF2_RXD_C_MARK, 3062 }; 3063 static const unsigned int msiof2_tx_c_pins[] = { 3064 /* TXD */ 3065 RCAR_GP_PIN(2, 4), 3066 }; 3067 static const unsigned int msiof2_tx_c_mux[] = { 3068 MSIOF2_TXD_C_MARK, 3069 }; 3070 3071 static const unsigned int msiof2_clk_d_pins[] = { 3072 /* SCK */ 3073 RCAR_GP_PIN(2, 14), 3074 }; 3075 static const unsigned int msiof2_clk_d_mux[] = { 3076 MSIOF2_SCK_D_MARK, 3077 }; 3078 static const unsigned int msiof2_sync_d_pins[] = { 3079 /* SYNC */ 3080 RCAR_GP_PIN(2, 15), 3081 }; 3082 static const unsigned int msiof2_sync_d_mux[] = { 3083 MSIOF2_SYNC_D_MARK, 3084 }; 3085 static const unsigned int msiof2_ss1_d_pins[] = { 3086 /* SS1 */ 3087 RCAR_GP_PIN(2, 17), 3088 }; 3089 static const unsigned int msiof2_ss1_d_mux[] = { 3090 MSIOF2_SS1_D_MARK, 3091 }; 3092 static const unsigned int msiof2_ss2_d_pins[] = { 3093 /* SS2 */ 3094 RCAR_GP_PIN(2, 19), 3095 }; 3096 static const unsigned int msiof2_ss2_d_mux[] = { 3097 MSIOF2_SS2_D_MARK, 3098 }; 3099 static const unsigned int msiof2_rx_d_pins[] = { 3100 /* RXD */ 3101 RCAR_GP_PIN(2, 18), 3102 }; 3103 static const unsigned int msiof2_rx_d_mux[] = { 3104 MSIOF2_RXD_D_MARK, 3105 }; 3106 static const unsigned int msiof2_tx_d_pins[] = { 3107 /* TXD */ 3108 RCAR_GP_PIN(2, 16), 3109 }; 3110 static const unsigned int msiof2_tx_d_mux[] = { 3111 MSIOF2_TXD_D_MARK, 3112 }; 3113 3114 static const unsigned int msiof2_clk_e_pins[] = { 3115 /* SCK */ 3116 RCAR_GP_PIN(7, 15), 3117 }; 3118 static const unsigned int msiof2_clk_e_mux[] = { 3119 MSIOF2_SCK_E_MARK, 3120 }; 3121 static const unsigned int msiof2_sync_e_pins[] = { 3122 /* SYNC */ 3123 RCAR_GP_PIN(7, 16), 3124 }; 3125 static const unsigned int msiof2_sync_e_mux[] = { 3126 MSIOF2_SYNC_E_MARK, 3127 }; 3128 static const unsigned int msiof2_rx_e_pins[] = { 3129 /* RXD */ 3130 RCAR_GP_PIN(7, 14), 3131 }; 3132 static const unsigned int msiof2_rx_e_mux[] = { 3133 MSIOF2_RXD_E_MARK, 3134 }; 3135 static const unsigned int msiof2_tx_e_pins[] = { 3136 /* TXD */ 3137 RCAR_GP_PIN(7, 13), 3138 }; 3139 static const unsigned int msiof2_tx_e_mux[] = { 3140 MSIOF2_TXD_E_MARK, 3141 }; 3142 /* - PWM -------------------------------------------------------------------- */ 3143 static const unsigned int pwm0_pins[] = { 3144 RCAR_GP_PIN(6, 14), 3145 }; 3146 static const unsigned int pwm0_mux[] = { 3147 PWM0_MARK, 3148 }; 3149 static const unsigned int pwm0_b_pins[] = { 3150 RCAR_GP_PIN(5, 30), 3151 }; 3152 static const unsigned int pwm0_b_mux[] = { 3153 PWM0_B_MARK, 3154 }; 3155 static const unsigned int pwm1_pins[] = { 3156 RCAR_GP_PIN(1, 17), 3157 }; 3158 static const unsigned int pwm1_mux[] = { 3159 PWM1_MARK, 3160 }; 3161 static const unsigned int pwm1_b_pins[] = { 3162 RCAR_GP_PIN(6, 15), 3163 }; 3164 static const unsigned int pwm1_b_mux[] = { 3165 PWM1_B_MARK, 3166 }; 3167 static const unsigned int pwm2_pins[] = { 3168 RCAR_GP_PIN(1, 18), 3169 }; 3170 static const unsigned int pwm2_mux[] = { 3171 PWM2_MARK, 3172 }; 3173 static const unsigned int pwm2_b_pins[] = { 3174 RCAR_GP_PIN(0, 16), 3175 }; 3176 static const unsigned int pwm2_b_mux[] = { 3177 PWM2_B_MARK, 3178 }; 3179 static const unsigned int pwm3_pins[] = { 3180 RCAR_GP_PIN(1, 24), 3181 }; 3182 static const unsigned int pwm3_mux[] = { 3183 PWM3_MARK, 3184 }; 3185 static const unsigned int pwm4_pins[] = { 3186 RCAR_GP_PIN(3, 26), 3187 }; 3188 static const unsigned int pwm4_mux[] = { 3189 PWM4_MARK, 3190 }; 3191 static const unsigned int pwm4_b_pins[] = { 3192 RCAR_GP_PIN(3, 31), 3193 }; 3194 static const unsigned int pwm4_b_mux[] = { 3195 PWM4_B_MARK, 3196 }; 3197 static const unsigned int pwm5_pins[] = { 3198 RCAR_GP_PIN(7, 21), 3199 }; 3200 static const unsigned int pwm5_mux[] = { 3201 PWM5_MARK, 3202 }; 3203 static const unsigned int pwm5_b_pins[] = { 3204 RCAR_GP_PIN(7, 20), 3205 }; 3206 static const unsigned int pwm5_b_mux[] = { 3207 PWM5_B_MARK, 3208 }; 3209 static const unsigned int pwm6_pins[] = { 3210 RCAR_GP_PIN(7, 22), 3211 }; 3212 static const unsigned int pwm6_mux[] = { 3213 PWM6_MARK, 3214 }; 3215 /* - QSPI ------------------------------------------------------------------- */ 3216 static const unsigned int qspi_ctrl_pins[] = { 3217 /* SPCLK, SSL */ 3218 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 9), 3219 }; 3220 static const unsigned int qspi_ctrl_mux[] = { 3221 SPCLK_MARK, SSL_MARK, 3222 }; 3223 static const unsigned int qspi_data2_pins[] = { 3224 /* MOSI_IO0, MISO_IO1 */ 3225 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), 3226 }; 3227 static const unsigned int qspi_data2_mux[] = { 3228 MOSI_IO0_MARK, MISO_IO1_MARK, 3229 }; 3230 static const unsigned int qspi_data4_pins[] = { 3231 /* MOSI_IO0, MISO_IO1, IO2, IO3 */ 3232 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 3233 RCAR_GP_PIN(1, 8), 3234 }; 3235 static const unsigned int qspi_data4_mux[] = { 3236 MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK, 3237 }; 3238 3239 static const unsigned int qspi_ctrl_b_pins[] = { 3240 /* SPCLK, SSL */ 3241 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 5), 3242 }; 3243 static const unsigned int qspi_ctrl_b_mux[] = { 3244 SPCLK_B_MARK, SSL_B_MARK, 3245 }; 3246 static const unsigned int qspi_data2_b_pins[] = { 3247 /* MOSI_IO0, MISO_IO1 */ 3248 RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 2), 3249 }; 3250 static const unsigned int qspi_data2_b_mux[] = { 3251 MOSI_IO0_B_MARK, MISO_IO1_B_MARK, 3252 }; 3253 static const unsigned int qspi_data4_b_pins[] = { 3254 /* MOSI_IO0, MISO_IO1, IO2, IO3 */ 3255 RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3), 3256 RCAR_GP_PIN(6, 4), 3257 }; 3258 static const unsigned int qspi_data4_b_mux[] = { 3259 MOSI_IO0_B_MARK, MISO_IO1_B_MARK, IO2_B_MARK, IO3_B_MARK, 3260 }; 3261 /* - SCIF0 ------------------------------------------------------------------ */ 3262 static const unsigned int scif0_data_pins[] = { 3263 /* RX, TX */ 3264 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), 3265 }; 3266 static const unsigned int scif0_data_mux[] = { 3267 RX0_MARK, TX0_MARK, 3268 }; 3269 static const unsigned int scif0_data_b_pins[] = { 3270 /* RX, TX */ 3271 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0), 3272 }; 3273 static const unsigned int scif0_data_b_mux[] = { 3274 RX0_B_MARK, TX0_B_MARK, 3275 }; 3276 static const unsigned int scif0_data_c_pins[] = { 3277 /* RX, TX */ 3278 RCAR_GP_PIN(4, 26), RCAR_GP_PIN(4, 25), 3279 }; 3280 static const unsigned int scif0_data_c_mux[] = { 3281 RX0_C_MARK, TX0_C_MARK, 3282 }; 3283 static const unsigned int scif0_data_d_pins[] = { 3284 /* RX, TX */ 3285 RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22), 3286 }; 3287 static const unsigned int scif0_data_d_mux[] = { 3288 RX0_D_MARK, TX0_D_MARK, 3289 }; 3290 static const unsigned int scif0_data_e_pins[] = { 3291 /* RX, TX */ 3292 RCAR_GP_PIN(6, 29), RCAR_GP_PIN(6, 28), 3293 }; 3294 static const unsigned int scif0_data_e_mux[] = { 3295 RX0_E_MARK, TX0_E_MARK, 3296 }; 3297 /* - SCIF1 ------------------------------------------------------------------ */ 3298 static const unsigned int scif1_data_pins[] = { 3299 /* RX, TX */ 3300 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8), 3301 }; 3302 static const unsigned int scif1_data_mux[] = { 3303 RX1_MARK, TX1_MARK, 3304 }; 3305 static const unsigned int scif1_data_b_pins[] = { 3306 /* RX, TX */ 3307 RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8), 3308 }; 3309 static const unsigned int scif1_data_b_mux[] = { 3310 RX1_B_MARK, TX1_B_MARK, 3311 }; 3312 static const unsigned int scif1_clk_b_pins[] = { 3313 /* SCK */ 3314 RCAR_GP_PIN(3, 10), 3315 }; 3316 static const unsigned int scif1_clk_b_mux[] = { 3317 SCIF1_SCK_B_MARK, 3318 }; 3319 static const unsigned int scif1_data_c_pins[] = { 3320 /* RX, TX */ 3321 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 27), 3322 }; 3323 static const unsigned int scif1_data_c_mux[] = { 3324 RX1_C_MARK, TX1_C_MARK, 3325 }; 3326 static const unsigned int scif1_data_d_pins[] = { 3327 /* RX, TX */ 3328 RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 24), 3329 }; 3330 static const unsigned int scif1_data_d_mux[] = { 3331 RX1_D_MARK, TX1_D_MARK, 3332 }; 3333 /* - SCIF2 ------------------------------------------------------------------ */ 3334 static const unsigned int scif2_data_pins[] = { 3335 /* RX, TX */ 3336 RCAR_GP_PIN(2, 30), RCAR_GP_PIN(2, 31), 3337 }; 3338 static const unsigned int scif2_data_mux[] = { 3339 RX2_MARK, TX2_MARK, 3340 }; 3341 static const unsigned int scif2_data_b_pins[] = { 3342 /* RX, TX */ 3343 RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16), 3344 }; 3345 static const unsigned int scif2_data_b_mux[] = { 3346 RX2_B_MARK, TX2_B_MARK, 3347 }; 3348 static const unsigned int scif2_clk_b_pins[] = { 3349 /* SCK */ 3350 RCAR_GP_PIN(3, 18), 3351 }; 3352 static const unsigned int scif2_clk_b_mux[] = { 3353 SCIF2_SCK_B_MARK, 3354 }; 3355 static const unsigned int scif2_data_c_pins[] = { 3356 /* RX, TX */ 3357 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25), 3358 }; 3359 static const unsigned int scif2_data_c_mux[] = { 3360 RX2_C_MARK, TX2_C_MARK, 3361 }; 3362 static const unsigned int scif2_data_e_pins[] = { 3363 /* RX, TX */ 3364 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), 3365 }; 3366 static const unsigned int scif2_data_e_mux[] = { 3367 RX2_E_MARK, TX2_E_MARK, 3368 }; 3369 /* - SCIF3 ------------------------------------------------------------------ */ 3370 static const unsigned int scif3_data_pins[] = { 3371 /* RX, TX */ 3372 RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21), 3373 }; 3374 static const unsigned int scif3_data_mux[] = { 3375 RX3_MARK, TX3_MARK, 3376 }; 3377 static const unsigned int scif3_clk_pins[] = { 3378 /* SCK */ 3379 RCAR_GP_PIN(3, 23), 3380 }; 3381 static const unsigned int scif3_clk_mux[] = { 3382 SCIF3_SCK_MARK, 3383 }; 3384 static const unsigned int scif3_data_b_pins[] = { 3385 /* RX, TX */ 3386 RCAR_GP_PIN(3, 29), RCAR_GP_PIN(3, 26), 3387 }; 3388 static const unsigned int scif3_data_b_mux[] = { 3389 RX3_B_MARK, TX3_B_MARK, 3390 }; 3391 static const unsigned int scif3_clk_b_pins[] = { 3392 /* SCK */ 3393 RCAR_GP_PIN(4, 8), 3394 }; 3395 static const unsigned int scif3_clk_b_mux[] = { 3396 SCIF3_SCK_B_MARK, 3397 }; 3398 static const unsigned int scif3_data_c_pins[] = { 3399 /* RX, TX */ 3400 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6), 3401 }; 3402 static const unsigned int scif3_data_c_mux[] = { 3403 RX3_C_MARK, TX3_C_MARK, 3404 }; 3405 static const unsigned int scif3_data_d_pins[] = { 3406 /* RX, TX */ 3407 RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 26), 3408 }; 3409 static const unsigned int scif3_data_d_mux[] = { 3410 RX3_D_MARK, TX3_D_MARK, 3411 }; 3412 /* - SCIF4 ------------------------------------------------------------------ */ 3413 static const unsigned int scif4_data_pins[] = { 3414 /* RX, TX */ 3415 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 1), 3416 }; 3417 static const unsigned int scif4_data_mux[] = { 3418 RX4_MARK, TX4_MARK, 3419 }; 3420 static const unsigned int scif4_data_b_pins[] = { 3421 /* RX, TX */ 3422 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 0), 3423 }; 3424 static const unsigned int scif4_data_b_mux[] = { 3425 RX4_B_MARK, TX4_B_MARK, 3426 }; 3427 static const unsigned int scif4_data_c_pins[] = { 3428 /* RX, TX */ 3429 RCAR_GP_PIN(7, 22), RCAR_GP_PIN(7, 21), 3430 }; 3431 static const unsigned int scif4_data_c_mux[] = { 3432 RX4_C_MARK, TX4_C_MARK, 3433 }; 3434 /* - SCIF5 ------------------------------------------------------------------ */ 3435 static const unsigned int scif5_data_pins[] = { 3436 /* RX, TX */ 3437 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 3), 3438 }; 3439 static const unsigned int scif5_data_mux[] = { 3440 RX5_MARK, TX5_MARK, 3441 }; 3442 static const unsigned int scif5_data_b_pins[] = { 3443 /* RX, TX */ 3444 RCAR_GP_PIN(6, 23), RCAR_GP_PIN(6, 22), 3445 }; 3446 static const unsigned int scif5_data_b_mux[] = { 3447 RX5_B_MARK, TX5_B_MARK, 3448 }; 3449 /* - SCIFA0 ----------------------------------------------------------------- */ 3450 static const unsigned int scifa0_data_pins[] = { 3451 /* RXD, TXD */ 3452 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), 3453 }; 3454 static const unsigned int scifa0_data_mux[] = { 3455 SCIFA0_RXD_MARK, SCIFA0_TXD_MARK, 3456 }; 3457 static const unsigned int scifa0_data_b_pins[] = { 3458 /* RXD, TXD */ 3459 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0), 3460 }; 3461 static const unsigned int scifa0_data_b_mux[] = { 3462 SCIFA0_RXD_B_MARK, SCIFA0_TXD_B_MARK 3463 }; 3464 /* - SCIFA1 ----------------------------------------------------------------- */ 3465 static const unsigned int scifa1_data_pins[] = { 3466 /* RXD, TXD */ 3467 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8), 3468 }; 3469 static const unsigned int scifa1_data_mux[] = { 3470 SCIFA1_RXD_MARK, SCIFA1_TXD_MARK, 3471 }; 3472 static const unsigned int scifa1_clk_pins[] = { 3473 /* SCK */ 3474 RCAR_GP_PIN(3, 10), 3475 }; 3476 static const unsigned int scifa1_clk_mux[] = { 3477 SCIFA1_SCK_MARK, 3478 }; 3479 static const unsigned int scifa1_data_b_pins[] = { 3480 /* RXD, TXD */ 3481 RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8), 3482 }; 3483 static const unsigned int scifa1_data_b_mux[] = { 3484 SCIFA1_RXD_B_MARK, SCIFA1_TXD_B_MARK, 3485 }; 3486 static const unsigned int scifa1_clk_b_pins[] = { 3487 /* SCK */ 3488 RCAR_GP_PIN(1, 0), 3489 }; 3490 static const unsigned int scifa1_clk_b_mux[] = { 3491 SCIFA1_SCK_B_MARK, 3492 }; 3493 static const unsigned int scifa1_data_c_pins[] = { 3494 /* RXD, TXD */ 3495 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), 3496 }; 3497 static const unsigned int scifa1_data_c_mux[] = { 3498 SCIFA1_RXD_C_MARK, SCIFA1_TXD_C_MARK, 3499 }; 3500 /* - SCIFA2 ----------------------------------------------------------------- */ 3501 static const unsigned int scifa2_data_pins[] = { 3502 /* RXD, TXD */ 3503 RCAR_GP_PIN(2, 30), RCAR_GP_PIN(2, 31), 3504 }; 3505 static const unsigned int scifa2_data_mux[] = { 3506 SCIFA2_RXD_MARK, SCIFA2_TXD_MARK, 3507 }; 3508 static const unsigned int scifa2_clk_pins[] = { 3509 /* SCK */ 3510 RCAR_GP_PIN(3, 18), 3511 }; 3512 static const unsigned int scifa2_clk_mux[] = { 3513 SCIFA2_SCK_MARK, 3514 }; 3515 static const unsigned int scifa2_data_b_pins[] = { 3516 /* RXD, TXD */ 3517 RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16), 3518 }; 3519 static const unsigned int scifa2_data_b_mux[] = { 3520 SCIFA2_RXD_B_MARK, SCIFA2_TXD_B_MARK, 3521 }; 3522 /* - SCIFA3 ----------------------------------------------------------------- */ 3523 static const unsigned int scifa3_data_pins[] = { 3524 /* RXD, TXD */ 3525 RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21), 3526 }; 3527 static const unsigned int scifa3_data_mux[] = { 3528 SCIFA3_RXD_MARK, SCIFA3_TXD_MARK, 3529 }; 3530 static const unsigned int scifa3_clk_pins[] = { 3531 /* SCK */ 3532 RCAR_GP_PIN(3, 23), 3533 }; 3534 static const unsigned int scifa3_clk_mux[] = { 3535 SCIFA3_SCK_MARK, 3536 }; 3537 static const unsigned int scifa3_data_b_pins[] = { 3538 /* RXD, TXD */ 3539 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 20), 3540 }; 3541 static const unsigned int scifa3_data_b_mux[] = { 3542 SCIFA3_RXD_B_MARK, SCIFA3_TXD_B_MARK, 3543 }; 3544 static const unsigned int scifa3_clk_b_pins[] = { 3545 /* SCK */ 3546 RCAR_GP_PIN(4, 8), 3547 }; 3548 static const unsigned int scifa3_clk_b_mux[] = { 3549 SCIFA3_SCK_B_MARK, 3550 }; 3551 static const unsigned int scifa3_data_c_pins[] = { 3552 /* RXD, TXD */ 3553 RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 20), 3554 }; 3555 static const unsigned int scifa3_data_c_mux[] = { 3556 SCIFA3_RXD_C_MARK, SCIFA3_TXD_C_MARK, 3557 }; 3558 static const unsigned int scifa3_clk_c_pins[] = { 3559 /* SCK */ 3560 RCAR_GP_PIN(7, 22), 3561 }; 3562 static const unsigned int scifa3_clk_c_mux[] = { 3563 SCIFA3_SCK_C_MARK, 3564 }; 3565 /* - SCIFA4 ----------------------------------------------------------------- */ 3566 static const unsigned int scifa4_data_pins[] = { 3567 /* RXD, TXD */ 3568 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 1), 3569 }; 3570 static const unsigned int scifa4_data_mux[] = { 3571 SCIFA4_RXD_MARK, SCIFA4_TXD_MARK, 3572 }; 3573 static const unsigned int scifa4_data_b_pins[] = { 3574 /* RXD, TXD */ 3575 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 0), 3576 }; 3577 static const unsigned int scifa4_data_b_mux[] = { 3578 SCIFA4_RXD_B_MARK, SCIFA4_TXD_B_MARK, 3579 }; 3580 static const unsigned int scifa4_data_c_pins[] = { 3581 /* RXD, TXD */ 3582 RCAR_GP_PIN(7, 22), RCAR_GP_PIN(7, 21), 3583 }; 3584 static const unsigned int scifa4_data_c_mux[] = { 3585 SCIFA4_RXD_C_MARK, SCIFA4_TXD_C_MARK, 3586 }; 3587 /* - SCIFA5 ----------------------------------------------------------------- */ 3588 static const unsigned int scifa5_data_pins[] = { 3589 /* RXD, TXD */ 3590 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 3), 3591 }; 3592 static const unsigned int scifa5_data_mux[] = { 3593 SCIFA5_RXD_MARK, SCIFA5_TXD_MARK, 3594 }; 3595 static const unsigned int scifa5_data_b_pins[] = { 3596 /* RXD, TXD */ 3597 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6), 3598 }; 3599 static const unsigned int scifa5_data_b_mux[] = { 3600 SCIFA5_RXD_B_MARK, SCIFA5_TXD_B_MARK, 3601 }; 3602 static const unsigned int scifa5_data_c_pins[] = { 3603 /* RXD, TXD */ 3604 RCAR_GP_PIN(6, 23), RCAR_GP_PIN(6, 22), 3605 }; 3606 static const unsigned int scifa5_data_c_mux[] = { 3607 SCIFA5_RXD_C_MARK, SCIFA5_TXD_C_MARK, 3608 }; 3609 /* - SCIFB0 ----------------------------------------------------------------- */ 3610 static const unsigned int scifb0_data_pins[] = { 3611 /* RXD, TXD */ 3612 RCAR_GP_PIN(7, 3), RCAR_GP_PIN(7, 4), 3613 }; 3614 static const unsigned int scifb0_data_mux[] = { 3615 SCIFB0_RXD_MARK, SCIFB0_TXD_MARK, 3616 }; 3617 static const unsigned int scifb0_clk_pins[] = { 3618 /* SCK */ 3619 RCAR_GP_PIN(7, 2), 3620 }; 3621 static const unsigned int scifb0_clk_mux[] = { 3622 SCIFB0_SCK_MARK, 3623 }; 3624 static const unsigned int scifb0_ctrl_pins[] = { 3625 /* RTS, CTS */ 3626 RCAR_GP_PIN(7, 1), RCAR_GP_PIN(7, 0), 3627 }; 3628 static const unsigned int scifb0_ctrl_mux[] = { 3629 SCIFB0_RTS_N_MARK, SCIFB0_CTS_N_MARK, 3630 }; 3631 static const unsigned int scifb0_data_b_pins[] = { 3632 /* RXD, TXD */ 3633 RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21), 3634 }; 3635 static const unsigned int scifb0_data_b_mux[] = { 3636 SCIFB0_RXD_B_MARK, SCIFB0_TXD_B_MARK, 3637 }; 3638 static const unsigned int scifb0_clk_b_pins[] = { 3639 /* SCK */ 3640 RCAR_GP_PIN(5, 31), 3641 }; 3642 static const unsigned int scifb0_clk_b_mux[] = { 3643 SCIFB0_SCK_B_MARK, 3644 }; 3645 static const unsigned int scifb0_ctrl_b_pins[] = { 3646 /* RTS, CTS */ 3647 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 23), 3648 }; 3649 static const unsigned int scifb0_ctrl_b_mux[] = { 3650 SCIFB0_RTS_N_B_MARK, SCIFB0_CTS_N_B_MARK, 3651 }; 3652 static const unsigned int scifb0_data_c_pins[] = { 3653 /* RXD, TXD */ 3654 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), 3655 }; 3656 static const unsigned int scifb0_data_c_mux[] = { 3657 SCIFB0_RXD_C_MARK, SCIFB0_TXD_C_MARK, 3658 }; 3659 static const unsigned int scifb0_clk_c_pins[] = { 3660 /* SCK */ 3661 RCAR_GP_PIN(2, 30), 3662 }; 3663 static const unsigned int scifb0_clk_c_mux[] = { 3664 SCIFB0_SCK_C_MARK, 3665 }; 3666 static const unsigned int scifb0_data_d_pins[] = { 3667 /* RXD, TXD */ 3668 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 18), 3669 }; 3670 static const unsigned int scifb0_data_d_mux[] = { 3671 SCIFB0_RXD_D_MARK, SCIFB0_TXD_D_MARK, 3672 }; 3673 static const unsigned int scifb0_clk_d_pins[] = { 3674 /* SCK */ 3675 RCAR_GP_PIN(4, 17), 3676 }; 3677 static const unsigned int scifb0_clk_d_mux[] = { 3678 SCIFB0_SCK_D_MARK, 3679 }; 3680 /* - SCIFB1 ----------------------------------------------------------------- */ 3681 static const unsigned int scifb1_data_pins[] = { 3682 /* RXD, TXD */ 3683 RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6), 3684 }; 3685 static const unsigned int scifb1_data_mux[] = { 3686 SCIFB1_RXD_MARK, SCIFB1_TXD_MARK, 3687 }; 3688 static const unsigned int scifb1_clk_pins[] = { 3689 /* SCK */ 3690 RCAR_GP_PIN(7, 7), 3691 }; 3692 static const unsigned int scifb1_clk_mux[] = { 3693 SCIFB1_SCK_MARK, 3694 }; 3695 static const unsigned int scifb1_ctrl_pins[] = { 3696 /* RTS, CTS */ 3697 RCAR_GP_PIN(7, 9), RCAR_GP_PIN(7, 8), 3698 }; 3699 static const unsigned int scifb1_ctrl_mux[] = { 3700 SCIFB1_RTS_N_MARK, SCIFB1_CTS_N_MARK, 3701 }; 3702 static const unsigned int scifb1_data_b_pins[] = { 3703 /* RXD, TXD */ 3704 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18), 3705 }; 3706 static const unsigned int scifb1_data_b_mux[] = { 3707 SCIFB1_RXD_B_MARK, SCIFB1_TXD_B_MARK, 3708 }; 3709 static const unsigned int scifb1_clk_b_pins[] = { 3710 /* SCK */ 3711 RCAR_GP_PIN(1, 3), 3712 }; 3713 static const unsigned int scifb1_clk_b_mux[] = { 3714 SCIFB1_SCK_B_MARK, 3715 }; 3716 static const unsigned int scifb1_data_c_pins[] = { 3717 /* RXD, TXD */ 3718 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), 3719 }; 3720 static const unsigned int scifb1_data_c_mux[] = { 3721 SCIFB1_RXD_C_MARK, SCIFB1_TXD_C_MARK, 3722 }; 3723 static const unsigned int scifb1_clk_c_pins[] = { 3724 /* SCK */ 3725 RCAR_GP_PIN(7, 11), 3726 }; 3727 static const unsigned int scifb1_clk_c_mux[] = { 3728 SCIFB1_SCK_C_MARK, 3729 }; 3730 static const unsigned int scifb1_data_d_pins[] = { 3731 /* RXD, TXD */ 3732 RCAR_GP_PIN(7, 10), RCAR_GP_PIN(7, 12), 3733 }; 3734 static const unsigned int scifb1_data_d_mux[] = { 3735 SCIFB1_RXD_D_MARK, SCIFB1_TXD_D_MARK, 3736 }; 3737 /* - SCIFB2 ----------------------------------------------------------------- */ 3738 static const unsigned int scifb2_data_pins[] = { 3739 /* RXD, TXD */ 3740 RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17), 3741 }; 3742 static const unsigned int scifb2_data_mux[] = { 3743 SCIFB2_RXD_MARK, SCIFB2_TXD_MARK, 3744 }; 3745 static const unsigned int scifb2_clk_pins[] = { 3746 /* SCK */ 3747 RCAR_GP_PIN(4, 15), 3748 }; 3749 static const unsigned int scifb2_clk_mux[] = { 3750 SCIFB2_SCK_MARK, 3751 }; 3752 static const unsigned int scifb2_ctrl_pins[] = { 3753 /* RTS, CTS */ 3754 RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13), 3755 }; 3756 static const unsigned int scifb2_ctrl_mux[] = { 3757 SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK, 3758 }; 3759 static const unsigned int scifb2_data_b_pins[] = { 3760 /* RXD, TXD */ 3761 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13), 3762 }; 3763 static const unsigned int scifb2_data_b_mux[] = { 3764 SCIFB2_RXD_B_MARK, SCIFB2_TXD_B_MARK, 3765 }; 3766 static const unsigned int scifb2_clk_b_pins[] = { 3767 /* SCK */ 3768 RCAR_GP_PIN(5, 31), 3769 }; 3770 static const unsigned int scifb2_clk_b_mux[] = { 3771 SCIFB2_SCK_B_MARK, 3772 }; 3773 static const unsigned int scifb2_ctrl_b_pins[] = { 3774 /* RTS, CTS */ 3775 RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14), 3776 }; 3777 static const unsigned int scifb2_ctrl_b_mux[] = { 3778 SCIFB2_RTS_N_B_MARK, SCIFB2_CTS_N_B_MARK, 3779 }; 3780 static const unsigned int scifb2_data_c_pins[] = { 3781 /* RXD, TXD */ 3782 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), 3783 }; 3784 static const unsigned int scifb2_data_c_mux[] = { 3785 SCIFB2_RXD_C_MARK, SCIFB2_TXD_C_MARK, 3786 }; 3787 static const unsigned int scifb2_clk_c_pins[] = { 3788 /* SCK */ 3789 RCAR_GP_PIN(5, 27), 3790 }; 3791 static const unsigned int scifb2_clk_c_mux[] = { 3792 SCIFB2_SCK_C_MARK, 3793 }; 3794 static const unsigned int scifb2_data_d_pins[] = { 3795 /* RXD, TXD */ 3796 RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 25), 3797 }; 3798 static const unsigned int scifb2_data_d_mux[] = { 3799 SCIFB2_RXD_D_MARK, SCIFB2_TXD_D_MARK, 3800 }; 3801 3802 /* - SCIF Clock ------------------------------------------------------------- */ 3803 static const unsigned int scif_clk_pins[] = { 3804 /* SCIF_CLK */ 3805 RCAR_GP_PIN(2, 29), 3806 }; 3807 static const unsigned int scif_clk_mux[] = { 3808 SCIF_CLK_MARK, 3809 }; 3810 static const unsigned int scif_clk_b_pins[] = { 3811 /* SCIF_CLK */ 3812 RCAR_GP_PIN(7, 19), 3813 }; 3814 static const unsigned int scif_clk_b_mux[] = { 3815 SCIF_CLK_B_MARK, 3816 }; 3817 3818 /* - SDHI0 ------------------------------------------------------------------ */ 3819 static const unsigned int sdhi0_data1_pins[] = { 3820 /* D0 */ 3821 RCAR_GP_PIN(6, 2), 3822 }; 3823 static const unsigned int sdhi0_data1_mux[] = { 3824 SD0_DATA0_MARK, 3825 }; 3826 static const unsigned int sdhi0_data4_pins[] = { 3827 /* D[0:3] */ 3828 RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3), 3829 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5), 3830 }; 3831 static const unsigned int sdhi0_data4_mux[] = { 3832 SD0_DATA0_MARK, SD0_DATA1_MARK, SD0_DATA2_MARK, SD0_DATA3_MARK, 3833 }; 3834 static const unsigned int sdhi0_ctrl_pins[] = { 3835 /* CLK, CMD */ 3836 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1), 3837 }; 3838 static const unsigned int sdhi0_ctrl_mux[] = { 3839 SD0_CLK_MARK, SD0_CMD_MARK, 3840 }; 3841 static const unsigned int sdhi0_cd_pins[] = { 3842 /* CD */ 3843 RCAR_GP_PIN(6, 6), 3844 }; 3845 static const unsigned int sdhi0_cd_mux[] = { 3846 SD0_CD_MARK, 3847 }; 3848 static const unsigned int sdhi0_wp_pins[] = { 3849 /* WP */ 3850 RCAR_GP_PIN(6, 7), 3851 }; 3852 static const unsigned int sdhi0_wp_mux[] = { 3853 SD0_WP_MARK, 3854 }; 3855 /* - SDHI1 ------------------------------------------------------------------ */ 3856 static const unsigned int sdhi1_data1_pins[] = { 3857 /* D0 */ 3858 RCAR_GP_PIN(6, 10), 3859 }; 3860 static const unsigned int sdhi1_data1_mux[] = { 3861 SD1_DATA0_MARK, 3862 }; 3863 static const unsigned int sdhi1_data4_pins[] = { 3864 /* D[0:3] */ 3865 RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11), 3866 RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13), 3867 }; 3868 static const unsigned int sdhi1_data4_mux[] = { 3869 SD1_DATA0_MARK, SD1_DATA1_MARK, SD1_DATA2_MARK, SD1_DATA3_MARK, 3870 }; 3871 static const unsigned int sdhi1_ctrl_pins[] = { 3872 /* CLK, CMD */ 3873 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), 3874 }; 3875 static const unsigned int sdhi1_ctrl_mux[] = { 3876 SD1_CLK_MARK, SD1_CMD_MARK, 3877 }; 3878 static const unsigned int sdhi1_cd_pins[] = { 3879 /* CD */ 3880 RCAR_GP_PIN(6, 14), 3881 }; 3882 static const unsigned int sdhi1_cd_mux[] = { 3883 SD1_CD_MARK, 3884 }; 3885 static const unsigned int sdhi1_wp_pins[] = { 3886 /* WP */ 3887 RCAR_GP_PIN(6, 15), 3888 }; 3889 static const unsigned int sdhi1_wp_mux[] = { 3890 SD1_WP_MARK, 3891 }; 3892 /* - SDHI2 ------------------------------------------------------------------ */ 3893 static const unsigned int sdhi2_data1_pins[] = { 3894 /* D0 */ 3895 RCAR_GP_PIN(6, 18), 3896 }; 3897 static const unsigned int sdhi2_data1_mux[] = { 3898 SD2_DATA0_MARK, 3899 }; 3900 static const unsigned int sdhi2_data4_pins[] = { 3901 /* D[0:3] */ 3902 RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19), 3903 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21), 3904 }; 3905 static const unsigned int sdhi2_data4_mux[] = { 3906 SD2_DATA0_MARK, SD2_DATA1_MARK, SD2_DATA2_MARK, SD2_DATA3_MARK, 3907 }; 3908 static const unsigned int sdhi2_ctrl_pins[] = { 3909 /* CLK, CMD */ 3910 RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17), 3911 }; 3912 static const unsigned int sdhi2_ctrl_mux[] = { 3913 SD2_CLK_MARK, SD2_CMD_MARK, 3914 }; 3915 static const unsigned int sdhi2_cd_pins[] = { 3916 /* CD */ 3917 RCAR_GP_PIN(6, 22), 3918 }; 3919 static const unsigned int sdhi2_cd_mux[] = { 3920 SD2_CD_MARK, 3921 }; 3922 static const unsigned int sdhi2_wp_pins[] = { 3923 /* WP */ 3924 RCAR_GP_PIN(6, 23), 3925 }; 3926 static const unsigned int sdhi2_wp_mux[] = { 3927 SD2_WP_MARK, 3928 }; 3929 3930 /* - SSI -------------------------------------------------------------------- */ 3931 static const unsigned int ssi0_data_pins[] = { 3932 /* SDATA */ 3933 RCAR_GP_PIN(2, 2), 3934 }; 3935 3936 static const unsigned int ssi0_data_mux[] = { 3937 SSI_SDATA0_MARK, 3938 }; 3939 3940 static const unsigned int ssi0_data_b_pins[] = { 3941 /* SDATA */ 3942 RCAR_GP_PIN(3, 4), 3943 }; 3944 3945 static const unsigned int ssi0_data_b_mux[] = { 3946 SSI_SDATA0_B_MARK, 3947 }; 3948 3949 static const unsigned int ssi0129_ctrl_pins[] = { 3950 /* SCK, WS */ 3951 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), 3952 }; 3953 3954 static const unsigned int ssi0129_ctrl_mux[] = { 3955 SSI_SCK0129_MARK, SSI_WS0129_MARK, 3956 }; 3957 3958 static const unsigned int ssi0129_ctrl_b_pins[] = { 3959 /* SCK, WS */ 3960 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), 3961 }; 3962 3963 static const unsigned int ssi0129_ctrl_b_mux[] = { 3964 SSI_SCK0129_B_MARK, SSI_WS0129_B_MARK, 3965 }; 3966 3967 static const unsigned int ssi1_data_pins[] = { 3968 /* SDATA */ 3969 RCAR_GP_PIN(2, 5), 3970 }; 3971 3972 static const unsigned int ssi1_data_mux[] = { 3973 SSI_SDATA1_MARK, 3974 }; 3975 3976 static const unsigned int ssi1_data_b_pins[] = { 3977 /* SDATA */ 3978 RCAR_GP_PIN(3, 7), 3979 }; 3980 3981 static const unsigned int ssi1_data_b_mux[] = { 3982 SSI_SDATA1_B_MARK, 3983 }; 3984 3985 static const unsigned int ssi1_ctrl_pins[] = { 3986 /* SCK, WS */ 3987 RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4), 3988 }; 3989 3990 static const unsigned int ssi1_ctrl_mux[] = { 3991 SSI_SCK1_MARK, SSI_WS1_MARK, 3992 }; 3993 3994 static const unsigned int ssi1_ctrl_b_pins[] = { 3995 /* SCK, WS */ 3996 RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6), 3997 }; 3998 3999 static const unsigned int ssi1_ctrl_b_mux[] = { 4000 SSI_SCK1_B_MARK, SSI_WS1_B_MARK, 4001 }; 4002 4003 static const unsigned int ssi2_data_pins[] = { 4004 /* SDATA */ 4005 RCAR_GP_PIN(2, 8), 4006 }; 4007 4008 static const unsigned int ssi2_data_mux[] = { 4009 SSI_SDATA2_MARK, 4010 }; 4011 4012 static const unsigned int ssi2_ctrl_pins[] = { 4013 /* SCK, WS */ 4014 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), 4015 }; 4016 4017 static const unsigned int ssi2_ctrl_mux[] = { 4018 SSI_SCK2_MARK, SSI_WS2_MARK, 4019 }; 4020 4021 static const unsigned int ssi3_data_pins[] = { 4022 /* SDATA */ 4023 RCAR_GP_PIN(2, 11), 4024 }; 4025 4026 static const unsigned int ssi3_data_mux[] = { 4027 SSI_SDATA3_MARK, 4028 }; 4029 4030 static const unsigned int ssi34_ctrl_pins[] = { 4031 /* SCK, WS */ 4032 RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10), 4033 }; 4034 4035 static const unsigned int ssi34_ctrl_mux[] = { 4036 SSI_SCK34_MARK, SSI_WS34_MARK, 4037 }; 4038 4039 static const unsigned int ssi4_data_pins[] = { 4040 /* SDATA */ 4041 RCAR_GP_PIN(2, 14), 4042 }; 4043 4044 static const unsigned int ssi4_data_mux[] = { 4045 SSI_SDATA4_MARK, 4046 }; 4047 4048 static const unsigned int ssi4_ctrl_pins[] = { 4049 /* SCK, WS */ 4050 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13), 4051 }; 4052 4053 static const unsigned int ssi4_ctrl_mux[] = { 4054 SSI_SCK4_MARK, SSI_WS4_MARK, 4055 }; 4056 4057 static const unsigned int ssi5_data_pins[] = { 4058 /* SDATA */ 4059 RCAR_GP_PIN(2, 17), 4060 }; 4061 4062 static const unsigned int ssi5_data_mux[] = { 4063 SSI_SDATA5_MARK, 4064 }; 4065 4066 static const unsigned int ssi5_ctrl_pins[] = { 4067 /* SCK, WS */ 4068 RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16), 4069 }; 4070 4071 static const unsigned int ssi5_ctrl_mux[] = { 4072 SSI_SCK5_MARK, SSI_WS5_MARK, 4073 }; 4074 4075 static const unsigned int ssi6_data_pins[] = { 4076 /* SDATA */ 4077 RCAR_GP_PIN(2, 20), 4078 }; 4079 4080 static const unsigned int ssi6_data_mux[] = { 4081 SSI_SDATA6_MARK, 4082 }; 4083 4084 static const unsigned int ssi6_ctrl_pins[] = { 4085 /* SCK, WS */ 4086 RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19), 4087 }; 4088 4089 static const unsigned int ssi6_ctrl_mux[] = { 4090 SSI_SCK6_MARK, SSI_WS6_MARK, 4091 }; 4092 4093 static const unsigned int ssi7_data_pins[] = { 4094 /* SDATA */ 4095 RCAR_GP_PIN(2, 23), 4096 }; 4097 4098 static const unsigned int ssi7_data_mux[] = { 4099 SSI_SDATA7_MARK, 4100 }; 4101 4102 static const unsigned int ssi7_data_b_pins[] = { 4103 /* SDATA */ 4104 RCAR_GP_PIN(3, 12), 4105 }; 4106 4107 static const unsigned int ssi7_data_b_mux[] = { 4108 SSI_SDATA7_B_MARK, 4109 }; 4110 4111 static const unsigned int ssi78_ctrl_pins[] = { 4112 /* SCK, WS */ 4113 RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22), 4114 }; 4115 4116 static const unsigned int ssi78_ctrl_mux[] = { 4117 SSI_SCK78_MARK, SSI_WS78_MARK, 4118 }; 4119 4120 static const unsigned int ssi78_ctrl_b_pins[] = { 4121 /* SCK, WS */ 4122 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), 4123 }; 4124 4125 static const unsigned int ssi78_ctrl_b_mux[] = { 4126 SSI_SCK78_B_MARK, SSI_WS78_B_MARK, 4127 }; 4128 4129 static const unsigned int ssi8_data_pins[] = { 4130 /* SDATA */ 4131 RCAR_GP_PIN(2, 24), 4132 }; 4133 4134 static const unsigned int ssi8_data_mux[] = { 4135 SSI_SDATA8_MARK, 4136 }; 4137 4138 static const unsigned int ssi8_data_b_pins[] = { 4139 /* SDATA */ 4140 RCAR_GP_PIN(3, 13), 4141 }; 4142 4143 static const unsigned int ssi8_data_b_mux[] = { 4144 SSI_SDATA8_B_MARK, 4145 }; 4146 4147 static const unsigned int ssi9_data_pins[] = { 4148 /* SDATA */ 4149 RCAR_GP_PIN(2, 27), 4150 }; 4151 4152 static const unsigned int ssi9_data_mux[] = { 4153 SSI_SDATA9_MARK, 4154 }; 4155 4156 static const unsigned int ssi9_data_b_pins[] = { 4157 /* SDATA */ 4158 RCAR_GP_PIN(3, 18), 4159 }; 4160 4161 static const unsigned int ssi9_data_b_mux[] = { 4162 SSI_SDATA9_B_MARK, 4163 }; 4164 4165 static const unsigned int ssi9_ctrl_pins[] = { 4166 /* SCK, WS */ 4167 RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 26), 4168 }; 4169 4170 static const unsigned int ssi9_ctrl_mux[] = { 4171 SSI_SCK9_MARK, SSI_WS9_MARK, 4172 }; 4173 4174 static const unsigned int ssi9_ctrl_b_pins[] = { 4175 /* SCK, WS */ 4176 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), 4177 }; 4178 4179 static const unsigned int ssi9_ctrl_b_mux[] = { 4180 SSI_SCK9_B_MARK, SSI_WS9_B_MARK, 4181 }; 4182 4183 /* - TPU -------------------------------------------------------------------- */ 4184 static const unsigned int tpu_to0_pins[] = { 4185 RCAR_GP_PIN(6, 14), 4186 }; 4187 static const unsigned int tpu_to0_mux[] = { 4188 TPU_TO0_MARK, 4189 }; 4190 static const unsigned int tpu_to1_pins[] = { 4191 RCAR_GP_PIN(1, 17), 4192 }; 4193 static const unsigned int tpu_to1_mux[] = { 4194 TPU_TO1_MARK, 4195 }; 4196 static const unsigned int tpu_to2_pins[] = { 4197 RCAR_GP_PIN(1, 18), 4198 }; 4199 static const unsigned int tpu_to2_mux[] = { 4200 TPU_TO2_MARK, 4201 }; 4202 static const unsigned int tpu_to3_pins[] = { 4203 RCAR_GP_PIN(1, 24), 4204 }; 4205 static const unsigned int tpu_to3_mux[] = { 4206 TPU_TO3_MARK, 4207 }; 4208 4209 /* - USB0 ------------------------------------------------------------------- */ 4210 static const unsigned int usb0_pins[] = { 4211 RCAR_GP_PIN(7, 23), /* PWEN */ 4212 RCAR_GP_PIN(7, 24), /* OVC */ 4213 }; 4214 static const unsigned int usb0_mux[] = { 4215 USB0_PWEN_MARK, 4216 USB0_OVC_MARK, 4217 }; 4218 /* - USB1 ------------------------------------------------------------------- */ 4219 static const unsigned int usb1_pins[] = { 4220 RCAR_GP_PIN(7, 25), /* PWEN */ 4221 RCAR_GP_PIN(6, 30), /* OVC */ 4222 }; 4223 static const unsigned int usb1_mux[] = { 4224 USB1_PWEN_MARK, 4225 USB1_OVC_MARK, 4226 }; 4227 /* - VIN0 ------------------------------------------------------------------- */ 4228 static const unsigned int vin0_data_pins[] = { 4229 /* B */ 4230 RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 6), 4231 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8), 4232 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10), 4233 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12), 4234 /* G */ 4235 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14), 4236 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16), 4237 RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18), 4238 RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 20), 4239 /* R */ 4240 RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 22), 4241 RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24), 4242 RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26), 4243 RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28), 4244 }; 4245 static const unsigned int vin0_data_mux[] = { 4246 /* B */ 4247 VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK, 4248 VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK, 4249 VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK, 4250 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK, 4251 /* G */ 4252 VI0_G0_MARK, VI0_G1_MARK, 4253 VI0_G2_MARK, VI0_G3_MARK, 4254 VI0_G4_MARK, VI0_G5_MARK, 4255 VI0_G6_MARK, VI0_G7_MARK, 4256 /* R */ 4257 VI0_R0_MARK, VI0_R1_MARK, 4258 VI0_R2_MARK, VI0_R3_MARK, 4259 VI0_R4_MARK, VI0_R5_MARK, 4260 VI0_R6_MARK, VI0_R7_MARK, 4261 }; 4262 static const unsigned int vin0_data18_pins[] = { 4263 /* B */ 4264 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8), 4265 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10), 4266 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12), 4267 /* G */ 4268 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16), 4269 RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18), 4270 RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 20), 4271 /* R */ 4272 RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24), 4273 RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26), 4274 RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28), 4275 }; 4276 static const unsigned int vin0_data18_mux[] = { 4277 /* B */ 4278 VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK, 4279 VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK, 4280 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK, 4281 /* G */ 4282 VI0_G2_MARK, VI0_G3_MARK, 4283 VI0_G4_MARK, VI0_G5_MARK, 4284 VI0_G6_MARK, VI0_G7_MARK, 4285 /* R */ 4286 VI0_R2_MARK, VI0_R3_MARK, 4287 VI0_R4_MARK, VI0_R5_MARK, 4288 VI0_R6_MARK, VI0_R7_MARK, 4289 }; 4290 static const unsigned int vin0_sync_pins[] = { 4291 RCAR_GP_PIN(4, 3), /* HSYNC */ 4292 RCAR_GP_PIN(4, 4), /* VSYNC */ 4293 }; 4294 static const unsigned int vin0_sync_mux[] = { 4295 VI0_HSYNC_N_MARK, 4296 VI0_VSYNC_N_MARK, 4297 }; 4298 static const unsigned int vin0_field_pins[] = { 4299 RCAR_GP_PIN(4, 2), 4300 }; 4301 static const unsigned int vin0_field_mux[] = { 4302 VI0_FIELD_MARK, 4303 }; 4304 static const unsigned int vin0_clkenb_pins[] = { 4305 RCAR_GP_PIN(4, 1), 4306 }; 4307 static const unsigned int vin0_clkenb_mux[] = { 4308 VI0_CLKENB_MARK, 4309 }; 4310 static const unsigned int vin0_clk_pins[] = { 4311 RCAR_GP_PIN(4, 0), 4312 }; 4313 static const unsigned int vin0_clk_mux[] = { 4314 VI0_CLK_MARK, 4315 }; 4316 /* - VIN1 ----------------------------------------------------------------- */ 4317 static const unsigned int vin1_data8_pins[] = { 4318 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6), 4319 RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8), 4320 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10), 4321 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 12), 4322 }; 4323 static const unsigned int vin1_data8_mux[] = { 4324 VI1_DATA0_MARK, VI1_DATA1_MARK, 4325 VI1_DATA2_MARK, VI1_DATA3_MARK, 4326 VI1_DATA4_MARK, VI1_DATA5_MARK, 4327 VI1_DATA6_MARK, VI1_DATA7_MARK, 4328 }; 4329 static const unsigned int vin1_sync_pins[] = { 4330 RCAR_GP_PIN(5, 0), /* HSYNC */ 4331 RCAR_GP_PIN(5, 1), /* VSYNC */ 4332 }; 4333 static const unsigned int vin1_sync_mux[] = { 4334 VI1_HSYNC_N_MARK, 4335 VI1_VSYNC_N_MARK, 4336 }; 4337 static const unsigned int vin1_field_pins[] = { 4338 RCAR_GP_PIN(5, 3), 4339 }; 4340 static const unsigned int vin1_field_mux[] = { 4341 VI1_FIELD_MARK, 4342 }; 4343 static const unsigned int vin1_clkenb_pins[] = { 4344 RCAR_GP_PIN(5, 2), 4345 }; 4346 static const unsigned int vin1_clkenb_mux[] = { 4347 VI1_CLKENB_MARK, 4348 }; 4349 static const unsigned int vin1_clk_pins[] = { 4350 RCAR_GP_PIN(5, 4), 4351 }; 4352 static const unsigned int vin1_clk_mux[] = { 4353 VI1_CLK_MARK, 4354 }; 4355 static const unsigned int vin1_data_b_pins[] = { 4356 /* B */ 4357 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1), 4358 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), 4359 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), 4360 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13), 4361 /* G */ 4362 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25), 4363 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27), 4364 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29), 4365 RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 22), 4366 /* R */ 4367 RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6), 4368 RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16), 4369 RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18), 4370 RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20), 4371 }; 4372 static const unsigned int vin1_data_b_mux[] = { 4373 /* B */ 4374 VI1_DATA0_B_MARK, VI1_DATA1_B_MARK, 4375 VI1_DATA2_B_MARK, VI1_DATA3_B_MARK, 4376 VI1_DATA4_B_MARK, VI1_DATA5_B_MARK, 4377 VI1_DATA6_B_MARK, VI1_DATA7_B_MARK, 4378 /* G */ 4379 VI1_G0_B_MARK, VI1_G1_B_MARK, 4380 VI1_G2_B_MARK, VI1_G3_B_MARK, 4381 VI1_G4_B_MARK, VI1_G5_B_MARK, 4382 VI1_G6_B_MARK, VI1_G7_B_MARK, 4383 /* R */ 4384 VI1_R0_B_MARK, VI1_R1_B_MARK, 4385 VI1_R2_B_MARK, VI1_R3_B_MARK, 4386 VI1_R4_B_MARK, VI1_R5_B_MARK, 4387 VI1_R6_B_MARK, VI1_R7_B_MARK, 4388 }; 4389 static const unsigned int vin1_data18_b_pins[] = { 4390 /* B */ 4391 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), 4392 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), 4393 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13), 4394 /* G */ 4395 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27), 4396 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29), 4397 RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 22), 4398 /* R */ 4399 RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16), 4400 RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18), 4401 RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20), 4402 }; 4403 static const unsigned int vin1_data18_b_mux[] = { 4404 /* B */ 4405 VI1_DATA2_B_MARK, VI1_DATA3_B_MARK, 4406 VI1_DATA4_B_MARK, VI1_DATA5_B_MARK, 4407 VI1_DATA6_B_MARK, VI1_DATA7_B_MARK, 4408 /* G */ 4409 VI1_G2_B_MARK, VI1_G3_B_MARK, 4410 VI1_G4_B_MARK, VI1_G5_B_MARK, 4411 VI1_G6_B_MARK, VI1_G7_B_MARK, 4412 /* R */ 4413 VI1_R2_B_MARK, VI1_R3_B_MARK, 4414 VI1_R4_B_MARK, VI1_R5_B_MARK, 4415 VI1_R6_B_MARK, VI1_R7_B_MARK, 4416 }; 4417 static const unsigned int vin1_sync_b_pins[] = { 4418 RCAR_GP_PIN(3, 17), /* HSYNC */ 4419 RCAR_GP_PIN(3, 18), /* VSYNC */ 4420 }; 4421 static const unsigned int vin1_sync_b_mux[] = { 4422 VI1_HSYNC_N_B_MARK, 4423 VI1_VSYNC_N_B_MARK, 4424 }; 4425 static const unsigned int vin1_field_b_pins[] = { 4426 RCAR_GP_PIN(3, 20), 4427 }; 4428 static const unsigned int vin1_field_b_mux[] = { 4429 VI1_FIELD_B_MARK, 4430 }; 4431 static const unsigned int vin1_clkenb_b_pins[] = { 4432 RCAR_GP_PIN(3, 19), 4433 }; 4434 static const unsigned int vin1_clkenb_b_mux[] = { 4435 VI1_CLKENB_B_MARK, 4436 }; 4437 static const unsigned int vin1_clk_b_pins[] = { 4438 RCAR_GP_PIN(3, 16), 4439 }; 4440 static const unsigned int vin1_clk_b_mux[] = { 4441 VI1_CLK_B_MARK, 4442 }; 4443 /* - VIN2 ----------------------------------------------------------------- */ 4444 static const unsigned int vin2_data8_pins[] = { 4445 RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21), 4446 RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23), 4447 RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 25), 4448 RCAR_GP_PIN(4, 26), RCAR_GP_PIN(4, 27), 4449 }; 4450 static const unsigned int vin2_data8_mux[] = { 4451 VI2_DATA0_MARK, VI2_DATA1_MARK, 4452 VI2_DATA2_MARK, VI2_DATA3_MARK, 4453 VI2_DATA4_MARK, VI2_DATA5_MARK, 4454 VI2_DATA6_MARK, VI2_DATA7_MARK, 4455 }; 4456 static const unsigned int vin2_sync_pins[] = { 4457 RCAR_GP_PIN(4, 15), /* HSYNC */ 4458 RCAR_GP_PIN(4, 16), /* VSYNC */ 4459 }; 4460 static const unsigned int vin2_sync_mux[] = { 4461 VI2_HSYNC_N_MARK, 4462 VI2_VSYNC_N_MARK, 4463 }; 4464 static const unsigned int vin2_field_pins[] = { 4465 RCAR_GP_PIN(4, 18), 4466 }; 4467 static const unsigned int vin2_field_mux[] = { 4468 VI2_FIELD_MARK, 4469 }; 4470 static const unsigned int vin2_clkenb_pins[] = { 4471 RCAR_GP_PIN(4, 17), 4472 }; 4473 static const unsigned int vin2_clkenb_mux[] = { 4474 VI2_CLKENB_MARK, 4475 }; 4476 static const unsigned int vin2_clk_pins[] = { 4477 RCAR_GP_PIN(4, 19), 4478 }; 4479 static const unsigned int vin2_clk_mux[] = { 4480 VI2_CLK_MARK, 4481 }; 4482 4483 static const struct { 4484 struct sh_pfc_pin_group common[346]; 4485 #if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793) 4486 struct sh_pfc_pin_group automotive[9]; 4487 #endif 4488 } pinmux_groups = { 4489 .common = { 4490 SH_PFC_PIN_GROUP(audio_clk_a), 4491 SH_PFC_PIN_GROUP(audio_clk_b), 4492 SH_PFC_PIN_GROUP(audio_clk_b_b), 4493 SH_PFC_PIN_GROUP(audio_clk_c), 4494 SH_PFC_PIN_GROUP(audio_clkout), 4495 SH_PFC_PIN_GROUP(avb_link), 4496 SH_PFC_PIN_GROUP(avb_magic), 4497 SH_PFC_PIN_GROUP(avb_phy_int), 4498 SH_PFC_PIN_GROUP(avb_mdio), 4499 SH_PFC_PIN_GROUP(avb_mii), 4500 SH_PFC_PIN_GROUP(avb_gmii), 4501 SH_PFC_PIN_GROUP(can0_data), 4502 SH_PFC_PIN_GROUP(can0_data_b), 4503 SH_PFC_PIN_GROUP(can0_data_c), 4504 SH_PFC_PIN_GROUP(can0_data_d), 4505 SH_PFC_PIN_GROUP(can0_data_e), 4506 SH_PFC_PIN_GROUP(can0_data_f), 4507 SH_PFC_PIN_GROUP(can1_data), 4508 SH_PFC_PIN_GROUP(can1_data_b), 4509 SH_PFC_PIN_GROUP(can1_data_c), 4510 SH_PFC_PIN_GROUP(can1_data_d), 4511 SH_PFC_PIN_GROUP(can_clk), 4512 SH_PFC_PIN_GROUP(can_clk_b), 4513 SH_PFC_PIN_GROUP(can_clk_c), 4514 SH_PFC_PIN_GROUP(can_clk_d), 4515 SH_PFC_PIN_GROUP(du_rgb666), 4516 SH_PFC_PIN_GROUP(du_rgb888), 4517 SH_PFC_PIN_GROUP(du_clk_out_0), 4518 SH_PFC_PIN_GROUP(du_clk_out_1), 4519 SH_PFC_PIN_GROUP(du_sync), 4520 SH_PFC_PIN_GROUP(du_oddf), 4521 SH_PFC_PIN_GROUP(du_cde), 4522 SH_PFC_PIN_GROUP(du_disp), 4523 SH_PFC_PIN_GROUP(du0_clk_in), 4524 SH_PFC_PIN_GROUP(du1_clk_in), 4525 SH_PFC_PIN_GROUP(du1_clk_in_b), 4526 SH_PFC_PIN_GROUP(du1_clk_in_c), 4527 SH_PFC_PIN_GROUP(eth_link), 4528 SH_PFC_PIN_GROUP(eth_magic), 4529 SH_PFC_PIN_GROUP(eth_mdio), 4530 SH_PFC_PIN_GROUP(eth_rmii), 4531 SH_PFC_PIN_GROUP(hscif0_data), 4532 SH_PFC_PIN_GROUP(hscif0_clk), 4533 SH_PFC_PIN_GROUP(hscif0_ctrl), 4534 SH_PFC_PIN_GROUP(hscif0_data_b), 4535 SH_PFC_PIN_GROUP(hscif0_ctrl_b), 4536 SH_PFC_PIN_GROUP(hscif0_data_c), 4537 SH_PFC_PIN_GROUP(hscif0_clk_c), 4538 SH_PFC_PIN_GROUP(hscif1_data), 4539 SH_PFC_PIN_GROUP(hscif1_clk), 4540 SH_PFC_PIN_GROUP(hscif1_ctrl), 4541 SH_PFC_PIN_GROUP(hscif1_data_b), 4542 SH_PFC_PIN_GROUP(hscif1_data_c), 4543 SH_PFC_PIN_GROUP(hscif1_clk_c), 4544 SH_PFC_PIN_GROUP(hscif1_ctrl_c), 4545 SH_PFC_PIN_GROUP(hscif1_data_d), 4546 SH_PFC_PIN_GROUP(hscif1_data_e), 4547 SH_PFC_PIN_GROUP(hscif1_clk_e), 4548 SH_PFC_PIN_GROUP(hscif1_ctrl_e), 4549 SH_PFC_PIN_GROUP(hscif2_data), 4550 SH_PFC_PIN_GROUP(hscif2_clk), 4551 SH_PFC_PIN_GROUP(hscif2_ctrl), 4552 SH_PFC_PIN_GROUP(hscif2_data_b), 4553 SH_PFC_PIN_GROUP(hscif2_ctrl_b), 4554 SH_PFC_PIN_GROUP(hscif2_data_c), 4555 SH_PFC_PIN_GROUP(hscif2_clk_c), 4556 SH_PFC_PIN_GROUP(hscif2_data_d), 4557 SH_PFC_PIN_GROUP(i2c0), 4558 SH_PFC_PIN_GROUP(i2c0_b), 4559 SH_PFC_PIN_GROUP(i2c0_c), 4560 SH_PFC_PIN_GROUP(i2c1), 4561 SH_PFC_PIN_GROUP(i2c1_b), 4562 SH_PFC_PIN_GROUP(i2c1_c), 4563 SH_PFC_PIN_GROUP(i2c1_d), 4564 SH_PFC_PIN_GROUP(i2c1_e), 4565 SH_PFC_PIN_GROUP(i2c2), 4566 SH_PFC_PIN_GROUP(i2c2_b), 4567 SH_PFC_PIN_GROUP(i2c2_c), 4568 SH_PFC_PIN_GROUP(i2c2_d), 4569 SH_PFC_PIN_GROUP(i2c3), 4570 SH_PFC_PIN_GROUP(i2c3_b), 4571 SH_PFC_PIN_GROUP(i2c3_c), 4572 SH_PFC_PIN_GROUP(i2c3_d), 4573 SH_PFC_PIN_GROUP(i2c4), 4574 SH_PFC_PIN_GROUP(i2c4_b), 4575 SH_PFC_PIN_GROUP(i2c4_c), 4576 SH_PFC_PIN_GROUP(i2c7), 4577 SH_PFC_PIN_GROUP(i2c7_b), 4578 SH_PFC_PIN_GROUP(i2c7_c), 4579 SH_PFC_PIN_GROUP(i2c8), 4580 SH_PFC_PIN_GROUP(i2c8_b), 4581 SH_PFC_PIN_GROUP(i2c8_c), 4582 SH_PFC_PIN_GROUP(intc_irq0), 4583 SH_PFC_PIN_GROUP(intc_irq1), 4584 SH_PFC_PIN_GROUP(intc_irq2), 4585 SH_PFC_PIN_GROUP(intc_irq3), 4586 SH_PFC_PIN_GROUP(mmc_data1), 4587 SH_PFC_PIN_GROUP(mmc_data4), 4588 SH_PFC_PIN_GROUP(mmc_data8), 4589 SH_PFC_PIN_GROUP(mmc_data8_b), 4590 SH_PFC_PIN_GROUP(mmc_ctrl), 4591 SH_PFC_PIN_GROUP(msiof0_clk), 4592 SH_PFC_PIN_GROUP(msiof0_sync), 4593 SH_PFC_PIN_GROUP(msiof0_ss1), 4594 SH_PFC_PIN_GROUP(msiof0_ss2), 4595 SH_PFC_PIN_GROUP(msiof0_rx), 4596 SH_PFC_PIN_GROUP(msiof0_tx), 4597 SH_PFC_PIN_GROUP(msiof0_clk_b), 4598 SH_PFC_PIN_GROUP(msiof0_sync_b), 4599 SH_PFC_PIN_GROUP(msiof0_ss1_b), 4600 SH_PFC_PIN_GROUP(msiof0_ss2_b), 4601 SH_PFC_PIN_GROUP(msiof0_rx_b), 4602 SH_PFC_PIN_GROUP(msiof0_tx_b), 4603 SH_PFC_PIN_GROUP(msiof0_clk_c), 4604 SH_PFC_PIN_GROUP(msiof0_sync_c), 4605 SH_PFC_PIN_GROUP(msiof0_ss1_c), 4606 SH_PFC_PIN_GROUP(msiof0_ss2_c), 4607 SH_PFC_PIN_GROUP(msiof0_rx_c), 4608 SH_PFC_PIN_GROUP(msiof0_tx_c), 4609 SH_PFC_PIN_GROUP(msiof1_clk), 4610 SH_PFC_PIN_GROUP(msiof1_sync), 4611 SH_PFC_PIN_GROUP(msiof1_ss1), 4612 SH_PFC_PIN_GROUP(msiof1_ss2), 4613 SH_PFC_PIN_GROUP(msiof1_rx), 4614 SH_PFC_PIN_GROUP(msiof1_tx), 4615 SH_PFC_PIN_GROUP(msiof1_clk_b), 4616 SH_PFC_PIN_GROUP(msiof1_sync_b), 4617 SH_PFC_PIN_GROUP(msiof1_ss1_b), 4618 SH_PFC_PIN_GROUP(msiof1_ss2_b), 4619 SH_PFC_PIN_GROUP(msiof1_rx_b), 4620 SH_PFC_PIN_GROUP(msiof1_tx_b), 4621 SH_PFC_PIN_GROUP(msiof1_clk_c), 4622 SH_PFC_PIN_GROUP(msiof1_sync_c), 4623 SH_PFC_PIN_GROUP(msiof1_rx_c), 4624 SH_PFC_PIN_GROUP(msiof1_tx_c), 4625 SH_PFC_PIN_GROUP(msiof1_clk_d), 4626 SH_PFC_PIN_GROUP(msiof1_sync_d), 4627 SH_PFC_PIN_GROUP(msiof1_ss1_d), 4628 SH_PFC_PIN_GROUP(msiof1_rx_d), 4629 SH_PFC_PIN_GROUP(msiof1_tx_d), 4630 SH_PFC_PIN_GROUP(msiof1_clk_e), 4631 SH_PFC_PIN_GROUP(msiof1_sync_e), 4632 SH_PFC_PIN_GROUP(msiof1_rx_e), 4633 SH_PFC_PIN_GROUP(msiof1_tx_e), 4634 SH_PFC_PIN_GROUP(msiof2_clk), 4635 SH_PFC_PIN_GROUP(msiof2_sync), 4636 SH_PFC_PIN_GROUP(msiof2_ss1), 4637 SH_PFC_PIN_GROUP(msiof2_ss2), 4638 SH_PFC_PIN_GROUP(msiof2_rx), 4639 SH_PFC_PIN_GROUP(msiof2_tx), 4640 SH_PFC_PIN_GROUP(msiof2_clk_b), 4641 SH_PFC_PIN_GROUP(msiof2_sync_b), 4642 SH_PFC_PIN_GROUP(msiof2_ss1_b), 4643 SH_PFC_PIN_GROUP(msiof2_ss2_b), 4644 SH_PFC_PIN_GROUP(msiof2_rx_b), 4645 SH_PFC_PIN_GROUP(msiof2_tx_b), 4646 SH_PFC_PIN_GROUP(msiof2_clk_c), 4647 SH_PFC_PIN_GROUP(msiof2_sync_c), 4648 SH_PFC_PIN_GROUP(msiof2_rx_c), 4649 SH_PFC_PIN_GROUP(msiof2_tx_c), 4650 SH_PFC_PIN_GROUP(msiof2_clk_d), 4651 SH_PFC_PIN_GROUP(msiof2_sync_d), 4652 SH_PFC_PIN_GROUP(msiof2_ss1_d), 4653 SH_PFC_PIN_GROUP(msiof2_ss2_d), 4654 SH_PFC_PIN_GROUP(msiof2_rx_d), 4655 SH_PFC_PIN_GROUP(msiof2_tx_d), 4656 SH_PFC_PIN_GROUP(msiof2_clk_e), 4657 SH_PFC_PIN_GROUP(msiof2_sync_e), 4658 SH_PFC_PIN_GROUP(msiof2_rx_e), 4659 SH_PFC_PIN_GROUP(msiof2_tx_e), 4660 SH_PFC_PIN_GROUP(pwm0), 4661 SH_PFC_PIN_GROUP(pwm0_b), 4662 SH_PFC_PIN_GROUP(pwm1), 4663 SH_PFC_PIN_GROUP(pwm1_b), 4664 SH_PFC_PIN_GROUP(pwm2), 4665 SH_PFC_PIN_GROUP(pwm2_b), 4666 SH_PFC_PIN_GROUP(pwm3), 4667 SH_PFC_PIN_GROUP(pwm4), 4668 SH_PFC_PIN_GROUP(pwm4_b), 4669 SH_PFC_PIN_GROUP(pwm5), 4670 SH_PFC_PIN_GROUP(pwm5_b), 4671 SH_PFC_PIN_GROUP(pwm6), 4672 SH_PFC_PIN_GROUP(qspi_ctrl), 4673 SH_PFC_PIN_GROUP(qspi_data2), 4674 SH_PFC_PIN_GROUP(qspi_data4), 4675 SH_PFC_PIN_GROUP(qspi_ctrl_b), 4676 SH_PFC_PIN_GROUP(qspi_data2_b), 4677 SH_PFC_PIN_GROUP(qspi_data4_b), 4678 SH_PFC_PIN_GROUP(scif0_data), 4679 SH_PFC_PIN_GROUP(scif0_data_b), 4680 SH_PFC_PIN_GROUP(scif0_data_c), 4681 SH_PFC_PIN_GROUP(scif0_data_d), 4682 SH_PFC_PIN_GROUP(scif0_data_e), 4683 SH_PFC_PIN_GROUP(scif1_data), 4684 SH_PFC_PIN_GROUP(scif1_data_b), 4685 SH_PFC_PIN_GROUP(scif1_clk_b), 4686 SH_PFC_PIN_GROUP(scif1_data_c), 4687 SH_PFC_PIN_GROUP(scif1_data_d), 4688 SH_PFC_PIN_GROUP(scif2_data), 4689 SH_PFC_PIN_GROUP(scif2_data_b), 4690 SH_PFC_PIN_GROUP(scif2_clk_b), 4691 SH_PFC_PIN_GROUP(scif2_data_c), 4692 SH_PFC_PIN_GROUP(scif2_data_e), 4693 SH_PFC_PIN_GROUP(scif3_data), 4694 SH_PFC_PIN_GROUP(scif3_clk), 4695 SH_PFC_PIN_GROUP(scif3_data_b), 4696 SH_PFC_PIN_GROUP(scif3_clk_b), 4697 SH_PFC_PIN_GROUP(scif3_data_c), 4698 SH_PFC_PIN_GROUP(scif3_data_d), 4699 SH_PFC_PIN_GROUP(scif4_data), 4700 SH_PFC_PIN_GROUP(scif4_data_b), 4701 SH_PFC_PIN_GROUP(scif4_data_c), 4702 SH_PFC_PIN_GROUP(scif5_data), 4703 SH_PFC_PIN_GROUP(scif5_data_b), 4704 SH_PFC_PIN_GROUP(scifa0_data), 4705 SH_PFC_PIN_GROUP(scifa0_data_b), 4706 SH_PFC_PIN_GROUP(scifa1_data), 4707 SH_PFC_PIN_GROUP(scifa1_clk), 4708 SH_PFC_PIN_GROUP(scifa1_data_b), 4709 SH_PFC_PIN_GROUP(scifa1_clk_b), 4710 SH_PFC_PIN_GROUP(scifa1_data_c), 4711 SH_PFC_PIN_GROUP(scifa2_data), 4712 SH_PFC_PIN_GROUP(scifa2_clk), 4713 SH_PFC_PIN_GROUP(scifa2_data_b), 4714 SH_PFC_PIN_GROUP(scifa3_data), 4715 SH_PFC_PIN_GROUP(scifa3_clk), 4716 SH_PFC_PIN_GROUP(scifa3_data_b), 4717 SH_PFC_PIN_GROUP(scifa3_clk_b), 4718 SH_PFC_PIN_GROUP(scifa3_data_c), 4719 SH_PFC_PIN_GROUP(scifa3_clk_c), 4720 SH_PFC_PIN_GROUP(scifa4_data), 4721 SH_PFC_PIN_GROUP(scifa4_data_b), 4722 SH_PFC_PIN_GROUP(scifa4_data_c), 4723 SH_PFC_PIN_GROUP(scifa5_data), 4724 SH_PFC_PIN_GROUP(scifa5_data_b), 4725 SH_PFC_PIN_GROUP(scifa5_data_c), 4726 SH_PFC_PIN_GROUP(scifb0_data), 4727 SH_PFC_PIN_GROUP(scifb0_clk), 4728 SH_PFC_PIN_GROUP(scifb0_ctrl), 4729 SH_PFC_PIN_GROUP(scifb0_data_b), 4730 SH_PFC_PIN_GROUP(scifb0_clk_b), 4731 SH_PFC_PIN_GROUP(scifb0_ctrl_b), 4732 SH_PFC_PIN_GROUP(scifb0_data_c), 4733 SH_PFC_PIN_GROUP(scifb0_clk_c), 4734 SH_PFC_PIN_GROUP(scifb0_data_d), 4735 SH_PFC_PIN_GROUP(scifb0_clk_d), 4736 SH_PFC_PIN_GROUP(scifb1_data), 4737 SH_PFC_PIN_GROUP(scifb1_clk), 4738 SH_PFC_PIN_GROUP(scifb1_ctrl), 4739 SH_PFC_PIN_GROUP(scifb1_data_b), 4740 SH_PFC_PIN_GROUP(scifb1_clk_b), 4741 SH_PFC_PIN_GROUP(scifb1_data_c), 4742 SH_PFC_PIN_GROUP(scifb1_clk_c), 4743 SH_PFC_PIN_GROUP(scifb1_data_d), 4744 SH_PFC_PIN_GROUP(scifb2_data), 4745 SH_PFC_PIN_GROUP(scifb2_clk), 4746 SH_PFC_PIN_GROUP(scifb2_ctrl), 4747 SH_PFC_PIN_GROUP(scifb2_data_b), 4748 SH_PFC_PIN_GROUP(scifb2_clk_b), 4749 SH_PFC_PIN_GROUP(scifb2_ctrl_b), 4750 SH_PFC_PIN_GROUP(scifb2_data_c), 4751 SH_PFC_PIN_GROUP(scifb2_clk_c), 4752 SH_PFC_PIN_GROUP(scifb2_data_d), 4753 SH_PFC_PIN_GROUP(scif_clk), 4754 SH_PFC_PIN_GROUP(scif_clk_b), 4755 SH_PFC_PIN_GROUP(sdhi0_data1), 4756 SH_PFC_PIN_GROUP(sdhi0_data4), 4757 SH_PFC_PIN_GROUP(sdhi0_ctrl), 4758 SH_PFC_PIN_GROUP(sdhi0_cd), 4759 SH_PFC_PIN_GROUP(sdhi0_wp), 4760 SH_PFC_PIN_GROUP(sdhi1_data1), 4761 SH_PFC_PIN_GROUP(sdhi1_data4), 4762 SH_PFC_PIN_GROUP(sdhi1_ctrl), 4763 SH_PFC_PIN_GROUP(sdhi1_cd), 4764 SH_PFC_PIN_GROUP(sdhi1_wp), 4765 SH_PFC_PIN_GROUP(sdhi2_data1), 4766 SH_PFC_PIN_GROUP(sdhi2_data4), 4767 SH_PFC_PIN_GROUP(sdhi2_ctrl), 4768 SH_PFC_PIN_GROUP(sdhi2_cd), 4769 SH_PFC_PIN_GROUP(sdhi2_wp), 4770 SH_PFC_PIN_GROUP(ssi0_data), 4771 SH_PFC_PIN_GROUP(ssi0_data_b), 4772 SH_PFC_PIN_GROUP(ssi0129_ctrl), 4773 SH_PFC_PIN_GROUP(ssi0129_ctrl_b), 4774 SH_PFC_PIN_GROUP(ssi1_data), 4775 SH_PFC_PIN_GROUP(ssi1_data_b), 4776 SH_PFC_PIN_GROUP(ssi1_ctrl), 4777 SH_PFC_PIN_GROUP(ssi1_ctrl_b), 4778 SH_PFC_PIN_GROUP(ssi2_data), 4779 SH_PFC_PIN_GROUP(ssi2_ctrl), 4780 SH_PFC_PIN_GROUP(ssi3_data), 4781 SH_PFC_PIN_GROUP(ssi34_ctrl), 4782 SH_PFC_PIN_GROUP(ssi4_data), 4783 SH_PFC_PIN_GROUP(ssi4_ctrl), 4784 SH_PFC_PIN_GROUP(ssi5_data), 4785 SH_PFC_PIN_GROUP(ssi5_ctrl), 4786 SH_PFC_PIN_GROUP(ssi6_data), 4787 SH_PFC_PIN_GROUP(ssi6_ctrl), 4788 SH_PFC_PIN_GROUP(ssi7_data), 4789 SH_PFC_PIN_GROUP(ssi7_data_b), 4790 SH_PFC_PIN_GROUP(ssi78_ctrl), 4791 SH_PFC_PIN_GROUP(ssi78_ctrl_b), 4792 SH_PFC_PIN_GROUP(ssi8_data), 4793 SH_PFC_PIN_GROUP(ssi8_data_b), 4794 SH_PFC_PIN_GROUP(ssi9_data), 4795 SH_PFC_PIN_GROUP(ssi9_data_b), 4796 SH_PFC_PIN_GROUP(ssi9_ctrl), 4797 SH_PFC_PIN_GROUP(ssi9_ctrl_b), 4798 SH_PFC_PIN_GROUP(tpu_to0), 4799 SH_PFC_PIN_GROUP(tpu_to1), 4800 SH_PFC_PIN_GROUP(tpu_to2), 4801 SH_PFC_PIN_GROUP(tpu_to3), 4802 SH_PFC_PIN_GROUP(usb0), 4803 SH_PFC_PIN_GROUP(usb1), 4804 BUS_DATA_PIN_GROUP(vin0_data, 24), 4805 BUS_DATA_PIN_GROUP(vin0_data, 20), 4806 SH_PFC_PIN_GROUP(vin0_data18), 4807 BUS_DATA_PIN_GROUP(vin0_data, 16), 4808 BUS_DATA_PIN_GROUP(vin0_data, 12), 4809 BUS_DATA_PIN_GROUP(vin0_data, 10), 4810 BUS_DATA_PIN_GROUP(vin0_data, 8), 4811 SH_PFC_PIN_GROUP(vin0_sync), 4812 SH_PFC_PIN_GROUP(vin0_field), 4813 SH_PFC_PIN_GROUP(vin0_clkenb), 4814 SH_PFC_PIN_GROUP(vin0_clk), 4815 SH_PFC_PIN_GROUP(vin1_data8), 4816 SH_PFC_PIN_GROUP(vin1_sync), 4817 SH_PFC_PIN_GROUP(vin1_field), 4818 SH_PFC_PIN_GROUP(vin1_clkenb), 4819 SH_PFC_PIN_GROUP(vin1_clk), 4820 BUS_DATA_PIN_GROUP(vin1_data, 24, _b), 4821 BUS_DATA_PIN_GROUP(vin1_data, 20, _b), 4822 SH_PFC_PIN_GROUP(vin1_data18_b), 4823 BUS_DATA_PIN_GROUP(vin1_data, 16, _b), 4824 BUS_DATA_PIN_GROUP(vin1_data, 12, _b), 4825 BUS_DATA_PIN_GROUP(vin1_data, 10, _b), 4826 BUS_DATA_PIN_GROUP(vin1_data, 8, _b), 4827 SH_PFC_PIN_GROUP(vin1_sync_b), 4828 SH_PFC_PIN_GROUP(vin1_field_b), 4829 SH_PFC_PIN_GROUP(vin1_clkenb_b), 4830 SH_PFC_PIN_GROUP(vin1_clk_b), 4831 SH_PFC_PIN_GROUP(vin2_data8), 4832 SH_PFC_PIN_GROUP(vin2_sync), 4833 SH_PFC_PIN_GROUP(vin2_field), 4834 SH_PFC_PIN_GROUP(vin2_clkenb), 4835 SH_PFC_PIN_GROUP(vin2_clk), 4836 }, 4837 #if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793) 4838 .automotive = { 4839 SH_PFC_PIN_GROUP(adi_common), 4840 SH_PFC_PIN_GROUP(adi_chsel0), 4841 SH_PFC_PIN_GROUP(adi_chsel1), 4842 SH_PFC_PIN_GROUP(adi_chsel2), 4843 SH_PFC_PIN_GROUP(adi_common_b), 4844 SH_PFC_PIN_GROUP(adi_chsel0_b), 4845 SH_PFC_PIN_GROUP(adi_chsel1_b), 4846 SH_PFC_PIN_GROUP(adi_chsel2_b), 4847 SH_PFC_PIN_GROUP(mlb_3pin), 4848 } 4849 #endif /* CONFIG_PINCTRL_PFC_R8A7791 || CONFIG_PINCTRL_PFC_R8A7793 */ 4850 }; 4851 4852 #if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793) 4853 static const char * const adi_groups[] = { 4854 "adi_common", 4855 "adi_chsel0", 4856 "adi_chsel1", 4857 "adi_chsel2", 4858 "adi_common_b", 4859 "adi_chsel0_b", 4860 "adi_chsel1_b", 4861 "adi_chsel2_b", 4862 }; 4863 #endif /* CONFIG_PINCTRL_PFC_R8A7791 || CONFIG_PINCTRL_PFC_R8A7793 */ 4864 4865 static const char * const audio_clk_groups[] = { 4866 "audio_clk_a", 4867 "audio_clk_b", 4868 "audio_clk_b_b", 4869 "audio_clk_c", 4870 "audio_clkout", 4871 }; 4872 4873 static const char * const avb_groups[] = { 4874 "avb_link", 4875 "avb_magic", 4876 "avb_phy_int", 4877 "avb_mdio", 4878 "avb_mii", 4879 "avb_gmii", 4880 }; 4881 4882 static const char * const can0_groups[] = { 4883 "can0_data", 4884 "can0_data_b", 4885 "can0_data_c", 4886 "can0_data_d", 4887 "can0_data_e", 4888 "can0_data_f", 4889 /* 4890 * Retained for backwards compatibility, use can_clk_groups in new 4891 * designs. 4892 */ 4893 "can_clk", 4894 "can_clk_b", 4895 "can_clk_c", 4896 "can_clk_d", 4897 }; 4898 4899 static const char * const can1_groups[] = { 4900 "can1_data", 4901 "can1_data_b", 4902 "can1_data_c", 4903 "can1_data_d", 4904 /* 4905 * Retained for backwards compatibility, use can_clk_groups in new 4906 * designs. 4907 */ 4908 "can_clk", 4909 "can_clk_b", 4910 "can_clk_c", 4911 "can_clk_d", 4912 }; 4913 4914 /* 4915 * can_clk_groups allows for independent configuration, use can_clk function 4916 * in new designs. 4917 */ 4918 static const char * const can_clk_groups[] = { 4919 "can_clk", 4920 "can_clk_b", 4921 "can_clk_c", 4922 "can_clk_d", 4923 }; 4924 4925 static const char * const du_groups[] = { 4926 "du_rgb666", 4927 "du_rgb888", 4928 "du_clk_out_0", 4929 "du_clk_out_1", 4930 "du_sync", 4931 "du_oddf", 4932 "du_cde", 4933 "du_disp", 4934 }; 4935 4936 static const char * const du0_groups[] = { 4937 "du0_clk_in", 4938 }; 4939 4940 static const char * const du1_groups[] = { 4941 "du1_clk_in", 4942 "du1_clk_in_b", 4943 "du1_clk_in_c", 4944 }; 4945 4946 static const char * const eth_groups[] = { 4947 "eth_link", 4948 "eth_magic", 4949 "eth_mdio", 4950 "eth_rmii", 4951 }; 4952 4953 static const char * const hscif0_groups[] = { 4954 "hscif0_data", 4955 "hscif0_clk", 4956 "hscif0_ctrl", 4957 "hscif0_data_b", 4958 "hscif0_ctrl_b", 4959 "hscif0_data_c", 4960 "hscif0_clk_c", 4961 }; 4962 4963 static const char * const hscif1_groups[] = { 4964 "hscif1_data", 4965 "hscif1_clk", 4966 "hscif1_ctrl", 4967 "hscif1_data_b", 4968 "hscif1_data_c", 4969 "hscif1_clk_c", 4970 "hscif1_ctrl_c", 4971 "hscif1_data_d", 4972 "hscif1_data_e", 4973 "hscif1_clk_e", 4974 "hscif1_ctrl_e", 4975 }; 4976 4977 static const char * const hscif2_groups[] = { 4978 "hscif2_data", 4979 "hscif2_clk", 4980 "hscif2_ctrl", 4981 "hscif2_data_b", 4982 "hscif2_ctrl_b", 4983 "hscif2_data_c", 4984 "hscif2_clk_c", 4985 "hscif2_data_d", 4986 }; 4987 4988 static const char * const i2c0_groups[] = { 4989 "i2c0", 4990 "i2c0_b", 4991 "i2c0_c", 4992 }; 4993 4994 static const char * const i2c1_groups[] = { 4995 "i2c1", 4996 "i2c1_b", 4997 "i2c1_c", 4998 "i2c1_d", 4999 "i2c1_e", 5000 }; 5001 5002 static const char * const i2c2_groups[] = { 5003 "i2c2", 5004 "i2c2_b", 5005 "i2c2_c", 5006 "i2c2_d", 5007 }; 5008 5009 static const char * const i2c3_groups[] = { 5010 "i2c3", 5011 "i2c3_b", 5012 "i2c3_c", 5013 "i2c3_d", 5014 }; 5015 5016 static const char * const i2c4_groups[] = { 5017 "i2c4", 5018 "i2c4_b", 5019 "i2c4_c", 5020 }; 5021 5022 static const char * const i2c7_groups[] = { 5023 "i2c7", 5024 "i2c7_b", 5025 "i2c7_c", 5026 }; 5027 5028 static const char * const i2c8_groups[] = { 5029 "i2c8", 5030 "i2c8_b", 5031 "i2c8_c", 5032 }; 5033 5034 static const char * const intc_groups[] = { 5035 "intc_irq0", 5036 "intc_irq1", 5037 "intc_irq2", 5038 "intc_irq3", 5039 }; 5040 5041 #if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793) 5042 static const char * const mlb_groups[] = { 5043 "mlb_3pin", 5044 }; 5045 #endif /* CONFIG_PINCTRL_PFC_R8A7791 || CONFIG_PINCTRL_PFC_R8A7793 */ 5046 5047 static const char * const mmc_groups[] = { 5048 "mmc_data1", 5049 "mmc_data4", 5050 "mmc_data8", 5051 "mmc_data8_b", 5052 "mmc_ctrl", 5053 }; 5054 5055 static const char * const msiof0_groups[] = { 5056 "msiof0_clk", 5057 "msiof0_sync", 5058 "msiof0_ss1", 5059 "msiof0_ss2", 5060 "msiof0_rx", 5061 "msiof0_tx", 5062 "msiof0_clk_b", 5063 "msiof0_sync_b", 5064 "msiof0_ss1_b", 5065 "msiof0_ss2_b", 5066 "msiof0_rx_b", 5067 "msiof0_tx_b", 5068 "msiof0_clk_c", 5069 "msiof0_sync_c", 5070 "msiof0_ss1_c", 5071 "msiof0_ss2_c", 5072 "msiof0_rx_c", 5073 "msiof0_tx_c", 5074 }; 5075 5076 static const char * const msiof1_groups[] = { 5077 "msiof1_clk", 5078 "msiof1_sync", 5079 "msiof1_ss1", 5080 "msiof1_ss2", 5081 "msiof1_rx", 5082 "msiof1_tx", 5083 "msiof1_clk_b", 5084 "msiof1_sync_b", 5085 "msiof1_ss1_b", 5086 "msiof1_ss2_b", 5087 "msiof1_rx_b", 5088 "msiof1_tx_b", 5089 "msiof1_clk_c", 5090 "msiof1_sync_c", 5091 "msiof1_rx_c", 5092 "msiof1_tx_c", 5093 "msiof1_clk_d", 5094 "msiof1_sync_d", 5095 "msiof1_ss1_d", 5096 "msiof1_rx_d", 5097 "msiof1_tx_d", 5098 "msiof1_clk_e", 5099 "msiof1_sync_e", 5100 "msiof1_rx_e", 5101 "msiof1_tx_e", 5102 }; 5103 5104 static const char * const msiof2_groups[] = { 5105 "msiof2_clk", 5106 "msiof2_sync", 5107 "msiof2_ss1", 5108 "msiof2_ss2", 5109 "msiof2_rx", 5110 "msiof2_tx", 5111 "msiof2_clk_b", 5112 "msiof2_sync_b", 5113 "msiof2_ss1_b", 5114 "msiof2_ss2_b", 5115 "msiof2_rx_b", 5116 "msiof2_tx_b", 5117 "msiof2_clk_c", 5118 "msiof2_sync_c", 5119 "msiof2_rx_c", 5120 "msiof2_tx_c", 5121 "msiof2_clk_d", 5122 "msiof2_sync_d", 5123 "msiof2_ss1_d", 5124 "msiof2_ss2_d", 5125 "msiof2_rx_d", 5126 "msiof2_tx_d", 5127 "msiof2_clk_e", 5128 "msiof2_sync_e", 5129 "msiof2_rx_e", 5130 "msiof2_tx_e", 5131 }; 5132 5133 static const char * const pwm0_groups[] = { 5134 "pwm0", 5135 "pwm0_b", 5136 }; 5137 5138 static const char * const pwm1_groups[] = { 5139 "pwm1", 5140 "pwm1_b", 5141 }; 5142 5143 static const char * const pwm2_groups[] = { 5144 "pwm2", 5145 "pwm2_b", 5146 }; 5147 5148 static const char * const pwm3_groups[] = { 5149 "pwm3", 5150 }; 5151 5152 static const char * const pwm4_groups[] = { 5153 "pwm4", 5154 "pwm4_b", 5155 }; 5156 5157 static const char * const pwm5_groups[] = { 5158 "pwm5", 5159 "pwm5_b", 5160 }; 5161 5162 static const char * const pwm6_groups[] = { 5163 "pwm6", 5164 }; 5165 5166 static const char * const qspi_groups[] = { 5167 "qspi_ctrl", 5168 "qspi_data2", 5169 "qspi_data4", 5170 "qspi_ctrl_b", 5171 "qspi_data2_b", 5172 "qspi_data4_b", 5173 }; 5174 5175 static const char * const scif0_groups[] = { 5176 "scif0_data", 5177 "scif0_data_b", 5178 "scif0_data_c", 5179 "scif0_data_d", 5180 "scif0_data_e", 5181 }; 5182 5183 static const char * const scif1_groups[] = { 5184 "scif1_data", 5185 "scif1_data_b", 5186 "scif1_clk_b", 5187 "scif1_data_c", 5188 "scif1_data_d", 5189 }; 5190 5191 static const char * const scif2_groups[] = { 5192 "scif2_data", 5193 "scif2_data_b", 5194 "scif2_clk_b", 5195 "scif2_data_c", 5196 "scif2_data_e", 5197 }; 5198 static const char * const scif3_groups[] = { 5199 "scif3_data", 5200 "scif3_clk", 5201 "scif3_data_b", 5202 "scif3_clk_b", 5203 "scif3_data_c", 5204 "scif3_data_d", 5205 }; 5206 static const char * const scif4_groups[] = { 5207 "scif4_data", 5208 "scif4_data_b", 5209 "scif4_data_c", 5210 }; 5211 static const char * const scif5_groups[] = { 5212 "scif5_data", 5213 "scif5_data_b", 5214 }; 5215 static const char * const scifa0_groups[] = { 5216 "scifa0_data", 5217 "scifa0_data_b", 5218 }; 5219 static const char * const scifa1_groups[] = { 5220 "scifa1_data", 5221 "scifa1_clk", 5222 "scifa1_data_b", 5223 "scifa1_clk_b", 5224 "scifa1_data_c", 5225 }; 5226 static const char * const scifa2_groups[] = { 5227 "scifa2_data", 5228 "scifa2_clk", 5229 "scifa2_data_b", 5230 }; 5231 static const char * const scifa3_groups[] = { 5232 "scifa3_data", 5233 "scifa3_clk", 5234 "scifa3_data_b", 5235 "scifa3_clk_b", 5236 "scifa3_data_c", 5237 "scifa3_clk_c", 5238 }; 5239 static const char * const scifa4_groups[] = { 5240 "scifa4_data", 5241 "scifa4_data_b", 5242 "scifa4_data_c", 5243 }; 5244 static const char * const scifa5_groups[] = { 5245 "scifa5_data", 5246 "scifa5_data_b", 5247 "scifa5_data_c", 5248 }; 5249 static const char * const scifb0_groups[] = { 5250 "scifb0_data", 5251 "scifb0_clk", 5252 "scifb0_ctrl", 5253 "scifb0_data_b", 5254 "scifb0_clk_b", 5255 "scifb0_ctrl_b", 5256 "scifb0_data_c", 5257 "scifb0_clk_c", 5258 "scifb0_data_d", 5259 "scifb0_clk_d", 5260 }; 5261 static const char * const scifb1_groups[] = { 5262 "scifb1_data", 5263 "scifb1_clk", 5264 "scifb1_ctrl", 5265 "scifb1_data_b", 5266 "scifb1_clk_b", 5267 "scifb1_data_c", 5268 "scifb1_clk_c", 5269 "scifb1_data_d", 5270 }; 5271 static const char * const scifb2_groups[] = { 5272 "scifb2_data", 5273 "scifb2_clk", 5274 "scifb2_ctrl", 5275 "scifb2_data_b", 5276 "scifb2_clk_b", 5277 "scifb2_ctrl_b", 5278 "scifb2_data_c", 5279 "scifb2_clk_c", 5280 "scifb2_data_d", 5281 }; 5282 5283 static const char * const scif_clk_groups[] = { 5284 "scif_clk", 5285 "scif_clk_b", 5286 }; 5287 5288 static const char * const sdhi0_groups[] = { 5289 "sdhi0_data1", 5290 "sdhi0_data4", 5291 "sdhi0_ctrl", 5292 "sdhi0_cd", 5293 "sdhi0_wp", 5294 }; 5295 5296 static const char * const sdhi1_groups[] = { 5297 "sdhi1_data1", 5298 "sdhi1_data4", 5299 "sdhi1_ctrl", 5300 "sdhi1_cd", 5301 "sdhi1_wp", 5302 }; 5303 5304 static const char * const sdhi2_groups[] = { 5305 "sdhi2_data1", 5306 "sdhi2_data4", 5307 "sdhi2_ctrl", 5308 "sdhi2_cd", 5309 "sdhi2_wp", 5310 }; 5311 5312 static const char * const ssi_groups[] = { 5313 "ssi0_data", 5314 "ssi0_data_b", 5315 "ssi0129_ctrl", 5316 "ssi0129_ctrl_b", 5317 "ssi1_data", 5318 "ssi1_data_b", 5319 "ssi1_ctrl", 5320 "ssi1_ctrl_b", 5321 "ssi2_data", 5322 "ssi2_ctrl", 5323 "ssi3_data", 5324 "ssi34_ctrl", 5325 "ssi4_data", 5326 "ssi4_ctrl", 5327 "ssi5_data", 5328 "ssi5_ctrl", 5329 "ssi6_data", 5330 "ssi6_ctrl", 5331 "ssi7_data", 5332 "ssi7_data_b", 5333 "ssi78_ctrl", 5334 "ssi78_ctrl_b", 5335 "ssi8_data", 5336 "ssi8_data_b", 5337 "ssi9_data", 5338 "ssi9_data_b", 5339 "ssi9_ctrl", 5340 "ssi9_ctrl_b", 5341 }; 5342 5343 static const char * const tpu_groups[] = { 5344 "tpu_to0", 5345 "tpu_to1", 5346 "tpu_to2", 5347 "tpu_to3", 5348 }; 5349 5350 static const char * const usb0_groups[] = { 5351 "usb0", 5352 }; 5353 static const char * const usb1_groups[] = { 5354 "usb1", 5355 }; 5356 5357 static const char * const vin0_groups[] = { 5358 "vin0_data24", 5359 "vin0_data20", 5360 "vin0_data18", 5361 "vin0_data16", 5362 "vin0_data12", 5363 "vin0_data10", 5364 "vin0_data8", 5365 "vin0_sync", 5366 "vin0_field", 5367 "vin0_clkenb", 5368 "vin0_clk", 5369 }; 5370 5371 static const char * const vin1_groups[] = { 5372 "vin1_data8", 5373 "vin1_sync", 5374 "vin1_field", 5375 "vin1_clkenb", 5376 "vin1_clk", 5377 "vin1_data24_b", 5378 "vin1_data20_b", 5379 "vin1_data18_b", 5380 "vin1_data16_b", 5381 "vin1_data12_b", 5382 "vin1_data10_b", 5383 "vin1_data8_b", 5384 "vin1_sync_b", 5385 "vin1_field_b", 5386 "vin1_clkenb_b", 5387 "vin1_clk_b", 5388 }; 5389 5390 static const char * const vin2_groups[] = { 5391 "vin2_data8", 5392 "vin2_sync", 5393 "vin2_field", 5394 "vin2_clkenb", 5395 "vin2_clk", 5396 }; 5397 5398 static const struct { 5399 struct sh_pfc_function common[58]; 5400 #if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793) 5401 struct sh_pfc_function automotive[2]; 5402 #endif 5403 } pinmux_functions = { 5404 .common = { 5405 SH_PFC_FUNCTION(audio_clk), 5406 SH_PFC_FUNCTION(avb), 5407 SH_PFC_FUNCTION(can0), 5408 SH_PFC_FUNCTION(can1), 5409 SH_PFC_FUNCTION(can_clk), 5410 SH_PFC_FUNCTION(du), 5411 SH_PFC_FUNCTION(du0), 5412 SH_PFC_FUNCTION(du1), 5413 SH_PFC_FUNCTION(eth), 5414 SH_PFC_FUNCTION(hscif0), 5415 SH_PFC_FUNCTION(hscif1), 5416 SH_PFC_FUNCTION(hscif2), 5417 SH_PFC_FUNCTION(i2c0), 5418 SH_PFC_FUNCTION(i2c1), 5419 SH_PFC_FUNCTION(i2c2), 5420 SH_PFC_FUNCTION(i2c3), 5421 SH_PFC_FUNCTION(i2c4), 5422 SH_PFC_FUNCTION(i2c7), 5423 SH_PFC_FUNCTION(i2c8), 5424 SH_PFC_FUNCTION(intc), 5425 SH_PFC_FUNCTION(mmc), 5426 SH_PFC_FUNCTION(msiof0), 5427 SH_PFC_FUNCTION(msiof1), 5428 SH_PFC_FUNCTION(msiof2), 5429 SH_PFC_FUNCTION(pwm0), 5430 SH_PFC_FUNCTION(pwm1), 5431 SH_PFC_FUNCTION(pwm2), 5432 SH_PFC_FUNCTION(pwm3), 5433 SH_PFC_FUNCTION(pwm4), 5434 SH_PFC_FUNCTION(pwm5), 5435 SH_PFC_FUNCTION(pwm6), 5436 SH_PFC_FUNCTION(qspi), 5437 SH_PFC_FUNCTION(scif0), 5438 SH_PFC_FUNCTION(scif1), 5439 SH_PFC_FUNCTION(scif2), 5440 SH_PFC_FUNCTION(scif3), 5441 SH_PFC_FUNCTION(scif4), 5442 SH_PFC_FUNCTION(scif5), 5443 SH_PFC_FUNCTION(scifa0), 5444 SH_PFC_FUNCTION(scifa1), 5445 SH_PFC_FUNCTION(scifa2), 5446 SH_PFC_FUNCTION(scifa3), 5447 SH_PFC_FUNCTION(scifa4), 5448 SH_PFC_FUNCTION(scifa5), 5449 SH_PFC_FUNCTION(scifb0), 5450 SH_PFC_FUNCTION(scifb1), 5451 SH_PFC_FUNCTION(scifb2), 5452 SH_PFC_FUNCTION(scif_clk), 5453 SH_PFC_FUNCTION(sdhi0), 5454 SH_PFC_FUNCTION(sdhi1), 5455 SH_PFC_FUNCTION(sdhi2), 5456 SH_PFC_FUNCTION(ssi), 5457 SH_PFC_FUNCTION(tpu), 5458 SH_PFC_FUNCTION(usb0), 5459 SH_PFC_FUNCTION(usb1), 5460 SH_PFC_FUNCTION(vin0), 5461 SH_PFC_FUNCTION(vin1), 5462 SH_PFC_FUNCTION(vin2), 5463 }, 5464 #if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793) 5465 .automotive = { 5466 SH_PFC_FUNCTION(adi), 5467 SH_PFC_FUNCTION(mlb), 5468 } 5469 #endif /* CONFIG_PINCTRL_PFC_R8A7791 || CONFIG_PINCTRL_PFC_R8A7793 */ 5470 }; 5471 5472 static const struct pinmux_cfg_reg pinmux_config_regs[] = { 5473 { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1, GROUP( 5474 GP_0_31_FN, FN_IP1_22_20, 5475 GP_0_30_FN, FN_IP1_19_17, 5476 GP_0_29_FN, FN_IP1_16_14, 5477 GP_0_28_FN, FN_IP1_13_11, 5478 GP_0_27_FN, FN_IP1_10_8, 5479 GP_0_26_FN, FN_IP1_7_6, 5480 GP_0_25_FN, FN_IP1_5_4, 5481 GP_0_24_FN, FN_IP1_3_2, 5482 GP_0_23_FN, FN_IP1_1_0, 5483 GP_0_22_FN, FN_IP0_30_29, 5484 GP_0_21_FN, FN_IP0_28_27, 5485 GP_0_20_FN, FN_IP0_26_25, 5486 GP_0_19_FN, FN_IP0_24_23, 5487 GP_0_18_FN, FN_IP0_22_21, 5488 GP_0_17_FN, FN_IP0_20_19, 5489 GP_0_16_FN, FN_IP0_18_16, 5490 GP_0_15_FN, FN_IP0_15, 5491 GP_0_14_FN, FN_IP0_14, 5492 GP_0_13_FN, FN_IP0_13, 5493 GP_0_12_FN, FN_IP0_12, 5494 GP_0_11_FN, FN_IP0_11, 5495 GP_0_10_FN, FN_IP0_10, 5496 GP_0_9_FN, FN_IP0_9, 5497 GP_0_8_FN, FN_IP0_8, 5498 GP_0_7_FN, FN_IP0_7, 5499 GP_0_6_FN, FN_IP0_6, 5500 GP_0_5_FN, FN_IP0_5, 5501 GP_0_4_FN, FN_IP0_4, 5502 GP_0_3_FN, FN_IP0_3, 5503 GP_0_2_FN, FN_IP0_2, 5504 GP_0_1_FN, FN_IP0_1, 5505 GP_0_0_FN, FN_IP0_0, )) 5506 }, 5507 { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1, GROUP( 5508 0, 0, 5509 0, 0, 5510 0, 0, 5511 0, 0, 5512 0, 0, 5513 0, 0, 5514 GP_1_25_FN, FN_IP3_21_20, 5515 GP_1_24_FN, FN_IP3_19_18, 5516 GP_1_23_FN, FN_IP3_17_16, 5517 GP_1_22_FN, FN_IP3_15_14, 5518 GP_1_21_FN, FN_IP3_13_12, 5519 GP_1_20_FN, FN_IP3_11_9, 5520 GP_1_19_FN, FN_RD_N, 5521 GP_1_18_FN, FN_IP3_8_6, 5522 GP_1_17_FN, FN_IP3_5_3, 5523 GP_1_16_FN, FN_IP3_2_0, 5524 GP_1_15_FN, FN_IP2_29_27, 5525 GP_1_14_FN, FN_IP2_26_25, 5526 GP_1_13_FN, FN_IP2_24_23, 5527 GP_1_12_FN, FN_EX_CS0_N, 5528 GP_1_11_FN, FN_IP2_22_21, 5529 GP_1_10_FN, FN_IP2_20_19, 5530 GP_1_9_FN, FN_IP2_18_16, 5531 GP_1_8_FN, FN_IP2_15_13, 5532 GP_1_7_FN, FN_IP2_12_10, 5533 GP_1_6_FN, FN_IP2_9_7, 5534 GP_1_5_FN, FN_IP2_6_5, 5535 GP_1_4_FN, FN_IP2_4_3, 5536 GP_1_3_FN, FN_IP2_2_0, 5537 GP_1_2_FN, FN_IP1_31_29, 5538 GP_1_1_FN, FN_IP1_28_26, 5539 GP_1_0_FN, FN_IP1_25_23, )) 5540 }, 5541 { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1, GROUP( 5542 GP_2_31_FN, FN_IP6_7_6, 5543 GP_2_30_FN, FN_IP6_5_3, 5544 GP_2_29_FN, FN_IP6_2_0, 5545 GP_2_28_FN, FN_AUDIO_CLKA, 5546 GP_2_27_FN, FN_IP5_31_29, 5547 GP_2_26_FN, FN_IP5_28_26, 5548 GP_2_25_FN, FN_IP5_25_24, 5549 GP_2_24_FN, FN_IP5_23_22, 5550 GP_2_23_FN, FN_IP5_21_20, 5551 GP_2_22_FN, FN_IP5_19_17, 5552 GP_2_21_FN, FN_IP5_16_15, 5553 GP_2_20_FN, FN_IP5_14_12, 5554 GP_2_19_FN, FN_IP5_11_9, 5555 GP_2_18_FN, FN_IP5_8_6, 5556 GP_2_17_FN, FN_IP5_5_3, 5557 GP_2_16_FN, FN_IP5_2_0, 5558 GP_2_15_FN, FN_IP4_30_28, 5559 GP_2_14_FN, FN_IP4_27_26, 5560 GP_2_13_FN, FN_IP4_25_24, 5561 GP_2_12_FN, FN_IP4_23_22, 5562 GP_2_11_FN, FN_IP4_21, 5563 GP_2_10_FN, FN_IP4_20, 5564 GP_2_9_FN, FN_IP4_19, 5565 GP_2_8_FN, FN_IP4_18_16, 5566 GP_2_7_FN, FN_IP4_15_13, 5567 GP_2_6_FN, FN_IP4_12_10, 5568 GP_2_5_FN, FN_IP4_9_8, 5569 GP_2_4_FN, FN_IP4_7_5, 5570 GP_2_3_FN, FN_IP4_4_2, 5571 GP_2_2_FN, FN_IP4_1_0, 5572 GP_2_1_FN, FN_IP3_30_28, 5573 GP_2_0_FN, FN_IP3_27_25 )) 5574 }, 5575 { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1, GROUP( 5576 GP_3_31_FN, FN_IP9_18_17, 5577 GP_3_30_FN, FN_IP9_16, 5578 GP_3_29_FN, FN_IP9_15_13, 5579 GP_3_28_FN, FN_IP9_12, 5580 GP_3_27_FN, FN_IP9_11, 5581 GP_3_26_FN, FN_IP9_10_8, 5582 GP_3_25_FN, FN_IP9_7, 5583 GP_3_24_FN, FN_IP9_6, 5584 GP_3_23_FN, FN_IP9_5_3, 5585 GP_3_22_FN, FN_IP9_2_0, 5586 GP_3_21_FN, FN_IP8_30_28, 5587 GP_3_20_FN, FN_IP8_27_26, 5588 GP_3_19_FN, FN_IP8_25_24, 5589 GP_3_18_FN, FN_IP8_23_21, 5590 GP_3_17_FN, FN_IP8_20_18, 5591 GP_3_16_FN, FN_IP8_17_15, 5592 GP_3_15_FN, FN_IP8_14_12, 5593 GP_3_14_FN, FN_IP8_11_9, 5594 GP_3_13_FN, FN_IP8_8_6, 5595 GP_3_12_FN, FN_IP8_5_3, 5596 GP_3_11_FN, FN_IP8_2_0, 5597 GP_3_10_FN, FN_IP7_29_27, 5598 GP_3_9_FN, FN_IP7_26_24, 5599 GP_3_8_FN, FN_IP7_23_21, 5600 GP_3_7_FN, FN_IP7_20_19, 5601 GP_3_6_FN, FN_IP7_18_17, 5602 GP_3_5_FN, FN_IP7_16_15, 5603 GP_3_4_FN, FN_IP7_14_13, 5604 GP_3_3_FN, FN_IP7_12_11, 5605 GP_3_2_FN, FN_IP7_10_9, 5606 GP_3_1_FN, FN_IP7_8_6, 5607 GP_3_0_FN, FN_IP7_5_3 )) 5608 }, 5609 { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1, GROUP( 5610 GP_4_31_FN, FN_IP15_5_4, 5611 GP_4_30_FN, FN_IP15_3_2, 5612 GP_4_29_FN, FN_IP15_1_0, 5613 GP_4_28_FN, FN_IP11_8_6, 5614 GP_4_27_FN, FN_IP11_5_3, 5615 GP_4_26_FN, FN_IP11_2_0, 5616 GP_4_25_FN, FN_IP10_31_29, 5617 GP_4_24_FN, FN_IP10_28_27, 5618 GP_4_23_FN, FN_IP10_26_25, 5619 GP_4_22_FN, FN_IP10_24_22, 5620 GP_4_21_FN, FN_IP10_21_19, 5621 GP_4_20_FN, FN_IP10_18_17, 5622 GP_4_19_FN, FN_IP10_16_15, 5623 GP_4_18_FN, FN_IP10_14_12, 5624 GP_4_17_FN, FN_IP10_11_9, 5625 GP_4_16_FN, FN_IP10_8_6, 5626 GP_4_15_FN, FN_IP10_5_3, 5627 GP_4_14_FN, FN_IP10_2_0, 5628 GP_4_13_FN, FN_IP9_31_29, 5629 GP_4_12_FN, FN_VI0_DATA7_VI0_B7, 5630 GP_4_11_FN, FN_VI0_DATA6_VI0_B6, 5631 GP_4_10_FN, FN_VI0_DATA5_VI0_B5, 5632 GP_4_9_FN, FN_VI0_DATA4_VI0_B4, 5633 GP_4_8_FN, FN_IP9_28_27, 5634 GP_4_7_FN, FN_VI0_DATA2_VI0_B2, 5635 GP_4_6_FN, FN_VI0_DATA1_VI0_B1, 5636 GP_4_5_FN, FN_VI0_DATA0_VI0_B0, 5637 GP_4_4_FN, FN_IP9_26_25, 5638 GP_4_3_FN, FN_IP9_24_23, 5639 GP_4_2_FN, FN_IP9_22_21, 5640 GP_4_1_FN, FN_IP9_20_19, 5641 GP_4_0_FN, FN_VI0_CLK )) 5642 }, 5643 { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1, GROUP( 5644 GP_5_31_FN, FN_IP3_24_22, 5645 GP_5_30_FN, FN_IP13_9_7, 5646 GP_5_29_FN, FN_IP13_6_5, 5647 GP_5_28_FN, FN_IP13_4_3, 5648 GP_5_27_FN, FN_IP13_2_0, 5649 GP_5_26_FN, FN_IP12_29_27, 5650 GP_5_25_FN, FN_IP12_26_24, 5651 GP_5_24_FN, FN_IP12_23_22, 5652 GP_5_23_FN, FN_IP12_21_20, 5653 GP_5_22_FN, FN_IP12_19_18, 5654 GP_5_21_FN, FN_IP12_17_16, 5655 GP_5_20_FN, FN_IP12_15_13, 5656 GP_5_19_FN, FN_IP12_12_10, 5657 GP_5_18_FN, FN_IP12_9_7, 5658 GP_5_17_FN, FN_IP12_6_4, 5659 GP_5_16_FN, FN_IP12_3_2, 5660 GP_5_15_FN, FN_IP12_1_0, 5661 GP_5_14_FN, FN_IP11_31_30, 5662 GP_5_13_FN, FN_IP11_29_28, 5663 GP_5_12_FN, FN_IP11_27, 5664 GP_5_11_FN, FN_IP11_26, 5665 GP_5_10_FN, FN_IP11_25, 5666 GP_5_9_FN, FN_IP11_24, 5667 GP_5_8_FN, FN_IP11_23, 5668 GP_5_7_FN, FN_IP11_22, 5669 GP_5_6_FN, FN_IP11_21, 5670 GP_5_5_FN, FN_IP11_20, 5671 GP_5_4_FN, FN_IP11_19, 5672 GP_5_3_FN, FN_IP11_18_17, 5673 GP_5_2_FN, FN_IP11_16_15, 5674 GP_5_1_FN, FN_IP11_14_12, 5675 GP_5_0_FN, FN_IP11_11_9 )) 5676 }, 5677 { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1, GROUP( 5678 GP_6_31_FN, FN_DU0_DOTCLKIN, 5679 GP_6_30_FN, FN_USB1_OVC, 5680 GP_6_29_FN, FN_IP14_31_29, 5681 GP_6_28_FN, FN_IP14_28_26, 5682 GP_6_27_FN, FN_IP14_25_23, 5683 GP_6_26_FN, FN_IP14_22_20, 5684 GP_6_25_FN, FN_IP14_19_17, 5685 GP_6_24_FN, FN_IP14_16_14, 5686 GP_6_23_FN, FN_IP14_13_11, 5687 GP_6_22_FN, FN_IP14_10_8, 5688 GP_6_21_FN, FN_IP14_7, 5689 GP_6_20_FN, FN_IP14_6, 5690 GP_6_19_FN, FN_IP14_5, 5691 GP_6_18_FN, FN_IP14_4, 5692 GP_6_17_FN, FN_IP14_3, 5693 GP_6_16_FN, FN_IP14_2, 5694 GP_6_15_FN, FN_IP14_1_0, 5695 GP_6_14_FN, FN_IP13_30_28, 5696 GP_6_13_FN, FN_IP13_27, 5697 GP_6_12_FN, FN_IP13_26, 5698 GP_6_11_FN, FN_IP13_25, 5699 GP_6_10_FN, FN_IP13_24_23, 5700 GP_6_9_FN, FN_IP13_22, 5701 GP_6_8_FN, FN_SD1_CLK, 5702 GP_6_7_FN, FN_IP13_21_19, 5703 GP_6_6_FN, FN_IP13_18_16, 5704 GP_6_5_FN, FN_IP13_15, 5705 GP_6_4_FN, FN_IP13_14, 5706 GP_6_3_FN, FN_IP13_13, 5707 GP_6_2_FN, FN_IP13_12, 5708 GP_6_1_FN, FN_IP13_11, 5709 GP_6_0_FN, FN_IP13_10 )) 5710 }, 5711 { PINMUX_CFG_REG("GPSR7", 0xE6060074, 32, 1, GROUP( 5712 0, 0, 5713 0, 0, 5714 0, 0, 5715 0, 0, 5716 0, 0, 5717 0, 0, 5718 GP_7_25_FN, FN_USB1_PWEN, 5719 GP_7_24_FN, FN_USB0_OVC, 5720 GP_7_23_FN, FN_USB0_PWEN, 5721 GP_7_22_FN, FN_IP15_14_12, 5722 GP_7_21_FN, FN_IP15_11_9, 5723 GP_7_20_FN, FN_IP15_8_6, 5724 GP_7_19_FN, FN_IP7_2_0, 5725 GP_7_18_FN, FN_IP6_29_27, 5726 GP_7_17_FN, FN_IP6_26_24, 5727 GP_7_16_FN, FN_IP6_23_21, 5728 GP_7_15_FN, FN_IP6_20_19, 5729 GP_7_14_FN, FN_IP6_18_16, 5730 GP_7_13_FN, FN_IP6_15_14, 5731 GP_7_12_FN, FN_IP6_13_12, 5732 GP_7_11_FN, FN_IP6_11_10, 5733 GP_7_10_FN, FN_IP6_9_8, 5734 GP_7_9_FN, FN_IP16_11_10, 5735 GP_7_8_FN, FN_IP16_9_8, 5736 GP_7_7_FN, FN_IP16_7_6, 5737 GP_7_6_FN, FN_IP16_5_3, 5738 GP_7_5_FN, FN_IP16_2_0, 5739 GP_7_4_FN, FN_IP15_29_27, 5740 GP_7_3_FN, FN_IP15_26_24, 5741 GP_7_2_FN, FN_IP15_23_21, 5742 GP_7_1_FN, FN_IP15_20_18, 5743 GP_7_0_FN, FN_IP15_17_15 )) 5744 }, 5745 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32, 5746 GROUP(1, 2, 2, 2, 2, 2, 2, 3, 1, 1, 1, 1, 5747 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), 5748 GROUP( 5749 /* IP0_31 [1] */ 5750 0, 0, 5751 /* IP0_30_29 [2] */ 5752 FN_A6, FN_MSIOF1_SCK, 5753 0, 0, 5754 /* IP0_28_27 [2] */ 5755 FN_A5, FN_MSIOF0_RXD_B, 5756 0, 0, 5757 /* IP0_26_25 [2] */ 5758 FN_A4, FN_MSIOF0_TXD_B, 5759 0, 0, 5760 /* IP0_24_23 [2] */ 5761 FN_A3, FN_MSIOF0_SS2_B, 5762 0, 0, 5763 /* IP0_22_21 [2] */ 5764 FN_A2, FN_MSIOF0_SS1_B, 5765 0, 0, 5766 /* IP0_20_19 [2] */ 5767 FN_A1, FN_MSIOF0_SYNC_B, 5768 0, 0, 5769 /* IP0_18_16 [3] */ 5770 FN_A0, FN_ATAWR0_N_C, FN_MSIOF0_SCK_B, FN_I2C0_SCL_C, FN_PWM2_B, 5771 0, 0, 0, 5772 /* IP0_15 [1] */ 5773 FN_D15, 0, 5774 /* IP0_14 [1] */ 5775 FN_D14, 0, 5776 /* IP0_13 [1] */ 5777 FN_D13, 0, 5778 /* IP0_12 [1] */ 5779 FN_D12, 0, 5780 /* IP0_11 [1] */ 5781 FN_D11, 0, 5782 /* IP0_10 [1] */ 5783 FN_D10, 0, 5784 /* IP0_9 [1] */ 5785 FN_D9, 0, 5786 /* IP0_8 [1] */ 5787 FN_D8, 0, 5788 /* IP0_7 [1] */ 5789 FN_D7, 0, 5790 /* IP0_6 [1] */ 5791 FN_D6, 0, 5792 /* IP0_5 [1] */ 5793 FN_D5, 0, 5794 /* IP0_4 [1] */ 5795 FN_D4, 0, 5796 /* IP0_3 [1] */ 5797 FN_D3, 0, 5798 /* IP0_2 [1] */ 5799 FN_D2, 0, 5800 /* IP0_1 [1] */ 5801 FN_D1, 0, 5802 /* IP0_0 [1] */ 5803 FN_D0, 0, )) 5804 }, 5805 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32, 5806 GROUP(3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2), 5807 GROUP( 5808 /* IP1_31_29 [3] */ 5809 FN_A18, FN_DREQ1, FN_SCIFA1_RXD_C, 0, FN_SCIFB1_RXD_C, 5810 0, 0, 0, 5811 /* IP1_28_26 [3] */ 5812 FN_A17, FN_DACK2_B, 0, FN_I2C0_SDA_C, 5813 0, 0, 0, 0, 5814 /* IP1_25_23 [3] */ 5815 FN_A16, FN_DREQ2_B, FN_FMCLK_C, 0, FN_SCIFA1_SCK_B, 5816 0, 0, 0, 5817 /* IP1_22_20 [3] */ 5818 FN_A15, FN_BPFCLK_C, 5819 0, 0, 0, 0, 0, 0, 5820 /* IP1_19_17 [3] */ 5821 FN_A14, FN_ATADIR0_N_C, FN_FMIN, FN_FMIN_C, FN_MSIOF1_SYNC_D, 5822 0, 0, 0, 5823 /* IP1_16_14 [3] */ 5824 FN_A13, FN_ATAG0_N_C, FN_BPFCLK, FN_MSIOF1_SS1_D, 5825 0, 0, 0, 0, 5826 /* IP1_13_11 [3] */ 5827 FN_A12, FN_FMCLK, FN_I2C3_SDA_D, FN_MSIOF1_SCK_D, 5828 0, 0, 0, 0, 5829 /* IP1_10_8 [3] */ 5830 FN_A11, FN_MSIOF1_RXD, FN_I2C3_SCL_D, FN_MSIOF1_RXD_D, 5831 0, 0, 0, 0, 5832 /* IP1_7_6 [2] */ 5833 FN_A10, FN_MSIOF1_TXD, 0, FN_MSIOF1_TXD_D, 5834 /* IP1_5_4 [2] */ 5835 FN_A9, FN_MSIOF1_SS2, FN_I2C0_SDA, 0, 5836 /* IP1_3_2 [2] */ 5837 FN_A8, FN_MSIOF1_SS1, FN_I2C0_SCL, 0, 5838 /* IP1_1_0 [2] */ 5839 FN_A7, FN_MSIOF1_SYNC, 5840 0, 0, )) 5841 }, 5842 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32, 5843 GROUP(2, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2, 3), 5844 GROUP( 5845 /* IP2_31_30 [2] */ 5846 0, 0, 0, 0, 5847 /* IP2_29_27 [3] */ 5848 FN_EX_CS3_N, FN_ATADIR0_N, FN_MSIOF2_TXD, 5849 FN_ATAG0_N, 0, FN_EX_WAIT1, 5850 0, 0, 5851 /* IP2_26_25 [2] */ 5852 FN_EX_CS2_N, FN_ATAWR0_N, FN_MSIOF2_SYNC, 0, 5853 /* IP2_24_23 [2] */ 5854 FN_EX_CS1_N, FN_MSIOF2_SCK, 0, 0, 5855 /* IP2_22_21 [2] */ 5856 FN_CS1_N_A26, FN_ATADIR0_N_B, FN_I2C1_SDA, 0, 5857 /* IP2_20_19 [2] */ 5858 FN_CS0_N, FN_ATAG0_N_B, FN_I2C1_SCL, 0, 5859 /* IP2_18_16 [3] */ 5860 FN_A25, FN_DACK2, FN_SSL, FN_DREQ1_C, FN_RX1, FN_SCIFA1_RXD, 5861 0, 0, 5862 /* IP2_15_13 [3] */ 5863 FN_A24, FN_DREQ2, FN_IO3, FN_TX1, FN_SCIFA1_TXD, 5864 0, 0, 0, 5865 /* IP2_12_10 [3] */ 5866 FN_A23, FN_IO2, FN_BPFCLK_B, FN_RX0, FN_SCIFA0_RXD, 5867 0, 0, 0, 5868 /* IP2_9_7 [3] */ 5869 FN_A22, FN_MISO_IO1, FN_FMCLK_B, FN_TX0, FN_SCIFA0_TXD, 5870 0, 0, 0, 5871 /* IP2_6_5 [2] */ 5872 FN_A21, FN_ATAWR0_N_B, FN_MOSI_IO0, 0, 5873 /* IP2_4_3 [2] */ 5874 FN_A20, FN_SPCLK, 0, 0, 5875 /* IP2_2_0 [3] */ 5876 FN_A19, FN_DACK1, FN_SCIFA1_TXD_C, 0, 5877 FN_SCIFB1_TXD_C, 0, FN_SCIFB1_SCK_B, 0, )) 5878 }, 5879 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32, 5880 GROUP(1, 3, 3, 3, 2, 2, 2, 2, 2, 3, 3, 3, 3), 5881 GROUP( 5882 /* IP3_31 [1] */ 5883 0, 0, 5884 /* IP3_30_28 [3] */ 5885 FN_SSI_WS0129, FN_HTX0_C, FN_HTX2_C, 5886 FN_SCIFB0_TXD_C, FN_SCIFB2_TXD_C, 5887 0, 0, 0, 5888 /* IP3_27_25 [3] */ 5889 FN_SSI_SCK0129, FN_HRX0_C, FN_HRX2_C, 5890 FN_SCIFB0_RXD_C, FN_SCIFB2_RXD_C, 5891 0, 0, 0, 5892 /* IP3_24_22 [3] */ 5893 FN_SPEEDIN, 0, FN_HSCK0_C, FN_HSCK2_C, FN_SCIFB0_SCK_B, 5894 FN_SCIFB2_SCK_B, FN_DREQ2_C, FN_HTX2_D, 5895 /* IP3_21_20 [2] */ 5896 FN_DACK0, FN_DRACK0, FN_REMOCON, 0, 5897 /* IP3_19_18 [2] */ 5898 FN_DREQ0, FN_PWM3, FN_TPU_TO3, 0, 5899 /* IP3_17_16 [2] */ 5900 FN_EX_WAIT0, FN_HRTS2_N_B, FN_SCIFB0_CTS_N_B, 0, 5901 /* IP3_15_14 [2] */ 5902 FN_WE1_N, FN_ATARD0_N_B, FN_HTX2_B, FN_SCIFB0_RTS_N_B, 5903 /* IP3_13_12 [2] */ 5904 FN_WE0_N, FN_HCTS2_N_B, FN_SCIFB0_TXD_B, 0, 5905 /* IP3_11_9 [3] */ 5906 FN_RD_WR_N, FN_HRX2_B, FN_FMIN_B, FN_SCIFB0_RXD_B, FN_DREQ1_D, 5907 0, 0, 0, 5908 /* IP3_8_6 [3] */ 5909 FN_BS_N, FN_ATACS10_N, FN_MSIOF2_SS2, FN_HTX1_B, 5910 FN_SCIFB1_TXD_B, FN_PWM2, FN_TPU_TO2, 0, 5911 /* IP3_5_3 [3] */ 5912 FN_EX_CS5_N, FN_ATACS00_N, FN_MSIOF2_SS1, FN_HRX1_B, 5913 FN_SCIFB1_RXD_B, FN_PWM1, FN_TPU_TO1, 0, 5914 /* IP3_2_0 [3] */ 5915 FN_EX_CS4_N, FN_ATARD0_N, FN_MSIOF2_RXD, 0, FN_EX_WAIT2, 5916 0, 0, 0, )) 5917 }, 5918 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32, 5919 GROUP(1, 3, 2, 2, 2, 1, 1, 1, 3, 3, 3, 2, 5920 3, 3, 2), 5921 GROUP( 5922 /* IP4_31 [1] */ 5923 0, 0, 5924 /* IP4_30_28 [3] */ 5925 FN_SSI_SCK5, FN_MSIOF1_SCK_C, FN_TS_SDATA0, FN_GLO_I0, 5926 FN_MSIOF2_SYNC_D, FN_VI1_R2_B, 5927 0, 0, 5928 /* IP4_27_26 [2] */ 5929 FN_SSI_SDATA4, FN_MSIOF2_SCK_D, 0, 0, 5930 /* IP4_25_24 [2] */ 5931 FN_SSI_WS4, FN_GLO_RFON_D, 0, 0, 5932 /* IP4_23_22 [2] */ 5933 FN_SSI_SCK4, FN_GLO_SS_D, 0, 0, 5934 /* IP4_21 [1] */ 5935 FN_SSI_SDATA3, 0, 5936 /* IP4_20 [1] */ 5937 FN_SSI_WS34, 0, 5938 /* IP4_19 [1] */ 5939 FN_SSI_SCK34, 0, 5940 /* IP4_18_16 [3] */ 5941 FN_SSI_SDATA2, FN_GPS_MAG_B, FN_TX2_E, FN_HRTS1_N_E, 5942 0, 0, 0, 0, 5943 /* IP4_15_13 [3] */ 5944 FN_SSI_WS2, FN_I2C2_SDA, FN_GPS_SIGN_B, FN_RX2_E, 5945 FN_GLO_Q1_D, FN_HCTS1_N_E, 5946 0, 0, 5947 /* IP4_12_10 [3] */ 5948 FN_SSI_SCK2, FN_I2C2_SCL, FN_GPS_CLK_B, FN_GLO_Q0_D, FN_HSCK1_E, 5949 0, 0, 0, 5950 /* IP4_9_8 [2] */ 5951 FN_SSI_SDATA1, FN_I2C1_SDA_B, FN_IIC1_SDA_B, FN_MSIOF2_RXD_C, 5952 /* IP4_7_5 [3] */ 5953 FN_SSI_WS1, FN_I2C1_SCL_B, FN_IIC1_SCL_B, FN_MSIOF2_TXD_C, 5954 FN_GLO_I1_D, 0, 0, 0, 5955 /* IP4_4_2 [3] */ 5956 FN_SSI_SCK1, FN_I2C0_SDA_B, FN_IIC0_SDA_B, 5957 FN_MSIOF2_SYNC_C, FN_GLO_I0_D, 5958 0, 0, 0, 5959 /* IP4_1_0 [2] */ 5960 FN_SSI_SDATA0, FN_I2C0_SCL_B, FN_IIC0_SCL_B, FN_MSIOF2_SCK_C, 5961 )) 5962 }, 5963 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32, 5964 GROUP(3, 3, 2, 2, 2, 3, 2, 3, 3, 3, 3, 3), 5965 GROUP( 5966 /* IP5_31_29 [3] */ 5967 FN_SSI_SDATA9, FN_RX3_D, FN_CAN0_RX_D, 5968 0, 0, 0, 0, 0, 5969 /* IP5_28_26 [3] */ 5970 FN_SSI_WS9, FN_TX3_D, FN_CAN0_TX_D, FN_GLO_SDATA_D, 5971 0, 0, 0, 0, 5972 /* IP5_25_24 [2] */ 5973 FN_SSI_SCK9, FN_RX1_D, FN_GLO_SCLK_D, 0, 5974 /* IP5_23_22 [2] */ 5975 FN_SSI_SDATA8, FN_TX1_D, FN_STP_ISSYNC_0_B, 0, 5976 /* IP5_21_20 [2] */ 5977 FN_SSI_SDATA7, FN_RX0_D, FN_STP_ISEN_0_B, 0, 5978 /* IP5_19_17 [3] */ 5979 FN_SSI_WS78, FN_TX0_D, FN_STP_ISD_0_B, FN_GLO_RFON, 5980 0, 0, 0, 0, 5981 /* IP5_16_15 [2] */ 5982 FN_SSI_SCK78, FN_STP_ISCLK_0_B, FN_GLO_SS, 0, 5983 /* IP5_14_12 [3] */ 5984 FN_SSI_SDATA6, FN_STP_IVCXO27_0_B, FN_GLO_SDATA, FN_VI1_R7_B, 5985 0, 0, 0, 0, 5986 /* IP5_11_9 [3] */ 5987 FN_SSI_WS6, FN_GLO_SCLK, FN_MSIOF2_SS2_D, FN_VI1_R6_B, 5988 0, 0, 0, 0, 5989 /* IP5_8_6 [3] */ 5990 FN_SSI_SCK6, FN_MSIOF1_RXD_C, FN_TS_SPSYNC0, FN_GLO_Q1, 5991 FN_MSIOF2_RXD_D, FN_VI1_R5_B, 5992 0, 0, 5993 /* IP5_5_3 [3] */ 5994 FN_SSI_SDATA5, FN_MSIOF1_TXD_C, FN_TS_SDEN0, FN_GLO_Q0, 5995 FN_MSIOF2_SS1_D, FN_VI1_R4_B, 5996 0, 0, 5997 /* IP5_2_0 [3] */ 5998 FN_SSI_WS5, FN_MSIOF1_SYNC_C, FN_TS_SCK0, FN_GLO_I1, 5999 FN_MSIOF2_TXD_D, FN_VI1_R3_B, 6000 0, 0, )) 6001 }, 6002 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32, 6003 GROUP(2, 3, 3, 3, 2, 3, 2, 2, 2, 2, 2, 3, 3), 6004 GROUP( 6005 /* IP6_31_30 [2] */ 6006 0, 0, 0, 0, 6007 /* IP6_29_27 [3] */ 6008 FN_IRQ8, FN_HRTS1_N_C, FN_MSIOF1_RXD_B, 6009 FN_GPS_SIGN_C, FN_GPS_SIGN_D, 6010 0, 0, 0, 6011 /* IP6_26_24 [3] */ 6012 FN_IRQ7, FN_HCTS1_N_C, FN_MSIOF1_TXD_B, 6013 FN_GPS_CLK_C, FN_GPS_CLK_D, 6014 0, 0, 0, 6015 /* IP6_23_21 [3] */ 6016 FN_IRQ6, FN_HSCK1_C, FN_MSIOF1_SS2_B, 6017 FN_I2C1_SDA_E, FN_MSIOF2_SYNC_E, 6018 0, 0, 0, 6019 /* IP6_20_19 [2] */ 6020 FN_IRQ5, FN_HTX1_C, FN_I2C1_SCL_E, FN_MSIOF2_SCK_E, 6021 /* IP6_18_16 [3] */ 6022 FN_IRQ4, FN_HRX1_C, FN_I2C4_SDA_C, FN_MSIOF2_RXD_E, 6023 0, 0, 0, 0, 6024 /* IP6_15_14 [2] */ 6025 FN_IRQ3, FN_I2C4_SCL_C, FN_MSIOF2_TXD_E, 0, 6026 /* IP6_13_12 [2] */ 6027 FN_IRQ2, FN_SCIFB1_TXD_D, 0, 0, 6028 /* IP6_11_10 [2] */ 6029 FN_IRQ1, FN_SCIFB1_SCK_C, 0, 0, 6030 /* IP6_9_8 [2] */ 6031 FN_IRQ0, FN_SCIFB1_RXD_D, 0, 0, 6032 /* IP6_7_6 [2] */ 6033 FN_AUDIO_CLKOUT, FN_MSIOF1_SS1_B, FN_TX2, FN_SCIFA2_TXD, 6034 /* IP6_5_3 [3] */ 6035 FN_AUDIO_CLKC, FN_SCIFB0_SCK_C, FN_MSIOF1_SYNC_B, FN_RX2, 6036 FN_SCIFA2_RXD, FN_FMIN_E, 6037 0, 0, 6038 /* IP6_2_0 [3] */ 6039 FN_AUDIO_CLKB, FN_STP_OPWM_0_B, FN_MSIOF1_SCK_B, 6040 FN_SCIF_CLK, FN_DVC_MUTE, FN_BPFCLK_E, 6041 0, 0, )) 6042 }, 6043 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32, 6044 GROUP(2, 3, 3, 3, 2, 2, 2, 2, 2, 2, 3, 3, 3), 6045 GROUP( 6046 /* IP7_31_30 [2] */ 6047 0, 0, 0, 0, 6048 /* IP7_29_27 [3] */ 6049 FN_DU1_DG2, FN_LCDOUT10, FN_VI1_DATA4_B, FN_SCIF1_SCK_B, 6050 FN_SCIFA1_SCK, FN_SSI_SCK78_B, 6051 0, 0, 6052 /* IP7_26_24 [3] */ 6053 FN_DU1_DG1, FN_LCDOUT9, FN_VI1_DATA3_B, FN_RX1_B, 6054 FN_SCIFA1_RXD_B, FN_MSIOF2_SS2_B, 6055 0, 0, 6056 /* IP7_23_21 [3] */ 6057 FN_DU1_DG0, FN_LCDOUT8, FN_VI1_DATA2_B, FN_TX1_B, 6058 FN_SCIFA1_TXD_B, FN_MSIOF2_SS1_B, 6059 0, 0, 6060 /* IP7_20_19 [2] */ 6061 FN_DU1_DR7, FN_LCDOUT7, FN_SSI_SDATA1_B, 0, 6062 /* IP7_18_17 [2] */ 6063 FN_DU1_DR6, FN_LCDOUT6, FN_SSI_WS1_B, 0, 6064 /* IP7_16_15 [2] */ 6065 FN_DU1_DR5, FN_LCDOUT5, FN_SSI_SCK1_B, 0, 6066 /* IP7_14_13 [2] */ 6067 FN_DU1_DR4, FN_LCDOUT4, FN_SSI_SDATA0_B, 0, 6068 /* IP7_12_11 [2] */ 6069 FN_DU1_DR3, FN_LCDOUT3, FN_SSI_WS0129_B, 0, 6070 /* IP7_10_9 [2] */ 6071 FN_DU1_DR2, FN_LCDOUT2, FN_SSI_SCK0129_B, 0, 6072 /* IP7_8_6 [3] */ 6073 FN_DU1_DR1, FN_LCDOUT1, FN_VI1_DATA1_B, FN_RX0_B, 6074 FN_SCIFA0_RXD_B, FN_MSIOF2_SYNC_B, 6075 0, 0, 6076 /* IP7_5_3 [3] */ 6077 FN_DU1_DR0, FN_LCDOUT0, FN_VI1_DATA0_B, FN_TX0_B, 6078 FN_SCIFA0_TXD_B, FN_MSIOF2_SCK_B, 6079 0, 0, 6080 /* IP7_2_0 [3] */ 6081 FN_IRQ9, FN_DU1_DOTCLKIN_B, FN_CAN_CLK_D, FN_GPS_MAG_C, 6082 FN_SCIF_CLK_B, FN_GPS_MAG_D, 6083 0, 0, )) 6084 }, 6085 { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32, 6086 GROUP(1, 3, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3), 6087 GROUP( 6088 /* IP8_31 [1] */ 6089 0, 0, 6090 /* IP8_30_28 [3] */ 6091 FN_DU1_DB5, FN_LCDOUT21, FN_TX3, FN_SCIFA3_TXD, FN_CAN1_TX, 6092 0, 0, 0, 6093 /* IP8_27_26 [2] */ 6094 FN_DU1_DB4, FN_LCDOUT20, FN_VI1_FIELD_B, FN_CAN1_RX, 6095 /* IP8_25_24 [2] */ 6096 FN_DU1_DB3, FN_LCDOUT19, FN_VI1_CLKENB_B, 0, 6097 /* IP8_23_21 [3] */ 6098 FN_DU1_DB2, FN_LCDOUT18, FN_VI1_VSYNC_N_B, FN_SCIF2_SCK_B, 6099 FN_SCIFA2_SCK, FN_SSI_SDATA9_B, 6100 0, 0, 6101 /* IP8_20_18 [3] */ 6102 FN_DU1_DB1, FN_LCDOUT17, FN_VI1_HSYNC_N_B, FN_RX2_B, 6103 FN_SCIFA2_RXD_B, FN_MSIOF2_RXD_B, 6104 0, 0, 6105 /* IP8_17_15 [3] */ 6106 FN_DU1_DB0, FN_LCDOUT16, FN_VI1_CLK_B, FN_TX2_B, 6107 FN_SCIFA2_TXD_B, FN_MSIOF2_TXD_B, 6108 0, 0, 6109 /* IP8_14_12 [3] */ 6110 FN_DU1_DG7, FN_LCDOUT15, FN_HTX0_B, 6111 FN_SCIFB2_RTS_N_B, FN_SSI_WS9_B, 6112 0, 0, 0, 6113 /* IP8_11_9 [3] */ 6114 FN_DU1_DG6, FN_LCDOUT14, FN_HRTS0_N_B, 6115 FN_SCIFB2_CTS_N_B, FN_SSI_SCK9_B, 6116 0, 0, 0, 6117 /* IP8_8_6 [3] */ 6118 FN_DU1_DG5, FN_LCDOUT13, FN_VI1_DATA7_B, FN_HCTS0_N_B, 6119 FN_SCIFB2_TXD_B, FN_SSI_SDATA8_B, 6120 0, 0, 6121 /* IP8_5_3 [3] */ 6122 FN_DU1_DG4, FN_LCDOUT12, FN_VI1_DATA6_B, FN_HRX0_B, 6123 FN_SCIFB2_RXD_B, FN_SSI_SDATA7_B, 6124 0, 0, 6125 /* IP8_2_0 [3] */ 6126 FN_DU1_DG3, FN_LCDOUT11, FN_VI1_DATA5_B, 0, FN_SSI_WS78_B, 6127 0, 0, 0, )) 6128 }, 6129 { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32, 6130 GROUP(3, 2, 2, 2, 2, 2, 2, 1, 3, 1, 1, 3, 6131 1, 1, 3, 3), 6132 GROUP( 6133 /* IP9_31_29 [3] */ 6134 FN_VI0_G0, FN_IIC1_SCL, FN_STP_IVCXO27_0_C, FN_I2C4_SCL, 6135 FN_HCTS2_N, FN_SCIFB2_CTS_N, FN_ATAWR1_N, 0, 6136 /* IP9_28_27 [2] */ 6137 FN_VI0_DATA3_VI0_B3, FN_SCIF3_SCK_B, FN_SCIFA3_SCK_B, 0, 6138 /* IP9_26_25 [2] */ 6139 FN_VI0_VSYNC_N, FN_RX5, FN_SCIFA5_RXD, FN_TS_SPSYNC0_D, 6140 /* IP9_24_23 [2] */ 6141 FN_VI0_HSYNC_N, FN_TX5, FN_SCIFA5_TXD, FN_TS_SDEN0_D, 6142 /* IP9_22_21 [2] */ 6143 FN_VI0_FIELD, FN_RX4, FN_SCIFA4_RXD, FN_TS_SCK0_D, 6144 /* IP9_20_19 [2] */ 6145 FN_VI0_CLKENB, FN_TX4, FN_SCIFA4_TXD, FN_TS_SDATA0_D, 6146 /* IP9_18_17 [2] */ 6147 FN_DU1_CDE, FN_QPOLB, FN_PWM4_B, 0, 6148 /* IP9_16 [1] */ 6149 FN_DU1_DISP, FN_QPOLA, 6150 /* IP9_15_13 [3] */ 6151 FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_QCPV_QDE, 6152 FN_CAN0_RX, FN_RX3_B, FN_I2C2_SDA_B, 6153 0, 0, 0, 6154 /* IP9_12 [1] */ 6155 FN_DU1_EXVSYNC_DU1_VSYNC, FN_QSTB_QHE, 6156 /* IP9_11 [1] */ 6157 FN_DU1_EXHSYNC_DU1_HSYNC, FN_QSTH_QHS, 6158 /* IP9_10_8 [3] */ 6159 FN_DU1_DOTCLKOUT1, FN_QSTVB_QVE, FN_CAN0_TX, 6160 FN_TX3_B, FN_I2C2_SCL_B, FN_PWM4, 6161 0, 0, 6162 /* IP9_7 [1] */ 6163 FN_DU1_DOTCLKOUT0, FN_QCLK, 6164 /* IP9_6 [1] */ 6165 FN_DU1_DOTCLKIN, FN_QSTVA_QVS, 6166 /* IP9_5_3 [3] */ 6167 FN_DU1_DB7, FN_LCDOUT23, FN_I2C3_SDA_C, 6168 FN_SCIF3_SCK, FN_SCIFA3_SCK, 6169 0, 0, 0, 6170 /* IP9_2_0 [3] */ 6171 FN_DU1_DB6, FN_LCDOUT22, FN_I2C3_SCL_C, FN_RX3, FN_SCIFA3_RXD, 6172 0, 0, 0, )) 6173 }, 6174 { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32, 6175 GROUP(3, 2, 2, 3, 3, 2, 2, 3, 3, 3, 3, 3), 6176 GROUP( 6177 /* IP10_31_29 [3] */ 6178 FN_VI0_R4, FN_VI2_DATA5, FN_GLO_SCLK_B, FN_TX0_C, FN_I2C1_SCL_D, 6179 0, 0, 0, 6180 /* IP10_28_27 [2] */ 6181 FN_VI0_R3, FN_VI2_DATA4, FN_GLO_Q1_B, FN_TS_SPSYNC0_C, 6182 /* IP10_26_25 [2] */ 6183 FN_VI0_R2, FN_VI2_DATA3, FN_GLO_Q0_B, FN_TS_SDEN0_C, 6184 /* IP10_24_22 [3] */ 6185 FN_VI0_R1, FN_VI2_DATA2, FN_GLO_I1_B, FN_TS_SCK0_C, FN_ATAG1_N, 6186 0, 0, 0, 6187 /* IP10_21_19 [3] */ 6188 FN_VI0_R0, FN_VI2_DATA1, FN_GLO_I0_B, 6189 FN_TS_SDATA0_C, FN_ATACS11_N, 6190 0, 0, 0, 6191 /* IP10_18_17 [2] */ 6192 FN_VI0_G7, FN_VI2_DATA0, FN_FMIN_D, 0, 6193 /* IP10_16_15 [2] */ 6194 FN_VI0_G6, FN_VI2_CLK, FN_BPFCLK_D, 0, 6195 /* IP10_14_12 [3] */ 6196 FN_VI0_G5, FN_VI2_FIELD, FN_STP_OPWM_0_C, FN_FMCLK_D, 6197 FN_CAN0_TX_E, FN_HTX1_D, FN_SCIFB0_TXD_D, 0, 6198 /* IP10_11_9 [3] */ 6199 FN_VI0_G4, FN_VI2_CLKENB, FN_STP_ISSYNC_0_C, 6200 FN_HTX2, FN_SCIFB2_TXD, FN_SCIFB0_SCK_D, 6201 0, 0, 6202 /* IP10_8_6 [3] */ 6203 FN_VI0_G3, FN_VI2_VSYNC_N, FN_STP_ISEN_0_C, FN_I2C3_SDA_B, 6204 FN_HRX2, FN_SCIFB2_RXD, FN_ATACS01_N, 0, 6205 /* IP10_5_3 [3] */ 6206 FN_VI0_G2, FN_VI2_HSYNC_N, FN_STP_ISD_0_C, FN_I2C3_SCL_B, 6207 FN_HSCK2, FN_SCIFB2_SCK, FN_ATARD1_N, 0, 6208 /* IP10_2_0 [3] */ 6209 FN_VI0_G1, FN_IIC1_SDA, FN_STP_ISCLK_0_C, FN_I2C4_SDA, 6210 FN_HRTS2_N, FN_SCIFB2_RTS_N, FN_ATADIR1_N, 0, )) 6211 }, 6212 { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32, 6213 GROUP(2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 6214 2, 3, 3, 3, 3, 3), 6215 GROUP( 6216 /* IP11_31_30 [2] */ 6217 FN_ETH_CRS_DV, FN_AVB_LINK, FN_I2C2_SDA_C, 0, 6218 /* IP11_29_28 [2] */ 6219 FN_ETH_MDIO, FN_AVB_RX_CLK, FN_I2C2_SCL_C, 0, 6220 /* IP11_27 [1] */ 6221 FN_VI1_DATA7, FN_AVB_MDC, 6222 /* IP11_26 [1] */ 6223 FN_VI1_DATA6, FN_AVB_MAGIC, 6224 /* IP11_25 [1] */ 6225 FN_VI1_DATA5, FN_AVB_RX_DV, 6226 /* IP11_24 [1] */ 6227 FN_VI1_DATA4, FN_AVB_MDIO, 6228 /* IP11_23 [1] */ 6229 FN_VI1_DATA3, FN_AVB_RX_ER, 6230 /* IP11_22 [1] */ 6231 FN_VI1_DATA2, FN_AVB_RXD7, 6232 /* IP11_21 [1] */ 6233 FN_VI1_DATA1, FN_AVB_RXD6, 6234 /* IP11_20 [1] */ 6235 FN_VI1_DATA0, FN_AVB_RXD5, 6236 /* IP11_19 [1] */ 6237 FN_VI1_CLK, FN_AVB_RXD4, 6238 /* IP11_18_17 [2] */ 6239 FN_VI1_FIELD, FN_AVB_RXD3, FN_TS_SPSYNC0_B, 0, 6240 /* IP11_16_15 [2] */ 6241 FN_VI1_CLKENB, FN_AVB_RXD2, FN_TS_SDEN0_B, 0, 6242 /* IP11_14_12 [3] */ 6243 FN_VI1_VSYNC_N, FN_AVB_RXD1, FN_TS_SCK0_B, 6244 FN_RX4_B, FN_SCIFA4_RXD_B, 6245 0, 0, 0, 6246 /* IP11_11_9 [3] */ 6247 FN_VI1_HSYNC_N, FN_AVB_RXD0, FN_TS_SDATA0_B, 6248 FN_TX4_B, FN_SCIFA4_TXD_B, 6249 0, 0, 0, 6250 /* IP11_8_6 [3] */ 6251 FN_VI0_R7, FN_GLO_RFON_B, FN_RX1_C, FN_CAN0_RX_E, 6252 FN_I2C4_SDA_B, FN_HRX1_D, FN_SCIFB0_RXD_D, 0, 6253 /* IP11_5_3 [3] */ 6254 FN_VI0_R6, FN_VI2_DATA7, FN_GLO_SS_B, FN_TX1_C, FN_I2C4_SCL_B, 6255 0, 0, 0, 6256 /* IP11_2_0 [3] */ 6257 FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C, 6258 FN_I2C1_SDA_D, 0, 0, 0, )) 6259 }, 6260 { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32, 6261 GROUP(2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2), 6262 GROUP( 6263 /* IP12_31_30 [2] */ 6264 0, 0, 0, 0, 6265 /* IP12_29_27 [3] */ 6266 FN_STP_ISCLK_0, FN_AVB_TX_EN, FN_SCIFB2_RXD_D, 6267 FN_ADICS_SAMP_B, FN_MSIOF0_SCK_C, 6268 0, 0, 0, 6269 /* IP12_26_24 [3] */ 6270 FN_STP_IVCXO27_0, FN_AVB_TXD7, FN_SCIFB2_TXD_D, 6271 FN_ADIDATA_B, FN_MSIOF0_SYNC_C, 6272 0, 0, 0, 6273 /* IP12_23_22 [2] */ 6274 FN_ETH_MDC, FN_AVB_TXD6, FN_IERX_C, 0, 6275 /* IP12_21_20 [2] */ 6276 FN_ETH_TXD0, FN_AVB_TXD5, FN_IECLK_C, 0, 6277 /* IP12_19_18 [2] */ 6278 FN_ETH_MAGIC, FN_AVB_TXD4, FN_IETX_C, 0, 6279 /* IP12_17_16 [2] */ 6280 FN_ETH_TX_EN, FN_AVB_TXD3, FN_TCLK1_B, FN_CAN_CLK_B, 6281 /* IP12_15_13 [3] */ 6282 FN_ETH_TXD1, FN_AVB_TXD2, FN_SCIFA3_TXD_B, 6283 FN_CAN1_TX_C, FN_MSIOF1_TXD_E, 6284 0, 0, 0, 6285 /* IP12_12_10 [3] */ 6286 FN_ETH_REFCLK, FN_AVB_TXD1, FN_SCIFA3_RXD_B, 6287 FN_CAN1_RX_C, FN_MSIOF1_SYNC_E, 6288 0, 0, 0, 6289 /* IP12_9_7 [3] */ 6290 FN_ETH_LINK, FN_AVB_TXD0, FN_CAN0_RX_C, 6291 FN_I2C2_SDA_D, FN_MSIOF1_SCK_E, 6292 0, 0, 0, 6293 /* IP12_6_4 [3] */ 6294 FN_ETH_RXD1, FN_AVB_GTXREFCLK, FN_CAN0_TX_C, 6295 FN_I2C2_SCL_D, FN_MSIOF1_RXD_E, 6296 0, 0, 0, 6297 /* IP12_3_2 [2] */ 6298 FN_ETH_RXD0, FN_AVB_PHY_INT, FN_I2C3_SDA, FN_IIC0_SDA, 6299 /* IP12_1_0 [2] */ 6300 FN_ETH_RX_ER, FN_AVB_CRS, FN_I2C3_SCL, FN_IIC0_SCL, )) 6301 }, 6302 { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32, 6303 GROUP(1, 3, 1, 1, 1, 2, 1, 3, 3, 1, 1, 1, 6304 1, 1, 1, 3, 2, 2, 3), 6305 GROUP( 6306 /* IP13_31 [1] */ 6307 0, 0, 6308 /* IP13_30_28 [3] */ 6309 FN_SD1_CD, FN_PWM0, FN_TPU_TO0, FN_I2C1_SCL_C, 6310 0, 0, 0, 0, 6311 /* IP13_27 [1] */ 6312 FN_SD1_DATA3, FN_IERX_B, 6313 /* IP13_26 [1] */ 6314 FN_SD1_DATA2, FN_IECLK_B, 6315 /* IP13_25 [1] */ 6316 FN_SD1_DATA1, FN_IETX_B, 6317 /* IP13_24_23 [2] */ 6318 FN_SD1_DATA0, FN_SPEEDIN_B, 0, 0, 6319 /* IP13_22 [1] */ 6320 FN_SD1_CMD, FN_REMOCON_B, 6321 /* IP13_21_19 [3] */ 6322 FN_SD0_WP, FN_MMC_D7_B, FN_SIM0_D_B, FN_CAN0_TX_F, 6323 FN_SCIFA5_RXD_B, FN_RX3_C, 6324 0, 0, 6325 /* IP13_18_16 [3] */ 6326 FN_SD0_CD, FN_MMC_D6_B, FN_SIM0_RST_B, FN_CAN0_RX_F, 6327 FN_SCIFA5_TXD_B, FN_TX3_C, 6328 0, 0, 6329 /* IP13_15 [1] */ 6330 FN_SD0_DATA3, FN_SSL_B, 6331 /* IP13_14 [1] */ 6332 FN_SD0_DATA2, FN_IO3_B, 6333 /* IP13_13 [1] */ 6334 FN_SD0_DATA1, FN_IO2_B, 6335 /* IP13_12 [1] */ 6336 FN_SD0_DATA0, FN_MISO_IO1_B, 6337 /* IP13_11 [1] */ 6338 FN_SD0_CMD, FN_MOSI_IO0_B, 6339 /* IP13_10 [1] */ 6340 FN_SD0_CLK, FN_SPCLK_B, 6341 /* IP13_9_7 [3] */ 6342 FN_STP_OPWM_0, FN_AVB_GTX_CLK, FN_PWM0_B, 6343 FN_ADICHS2_B, FN_MSIOF0_TXD_C, 6344 0, 0, 0, 6345 /* IP13_6_5 [2] */ 6346 FN_STP_ISSYNC_0, FN_AVB_COL, FN_ADICHS1_B, FN_MSIOF0_RXD_C, 6347 /* IP13_4_3 [2] */ 6348 FN_STP_ISEN_0, FN_AVB_TX_CLK, FN_ADICHS0_B, FN_MSIOF0_SS2_C, 6349 /* IP13_2_0 [3] */ 6350 FN_STP_ISD_0, FN_AVB_TX_ER, FN_SCIFB2_SCK_C, 6351 FN_ADICLK_B, FN_MSIOF0_SS1_C, 6352 0, 0, 0, )) 6353 }, 6354 { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32, 6355 GROUP(3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 6356 1, 1, 2), 6357 GROUP( 6358 /* IP14_31_29 [3] */ 6359 FN_MSIOF0_SS2, FN_MMC_D7, FN_ADICHS2, FN_RX0_E, 6360 FN_VI1_VSYNC_N_C, FN_IIC0_SDA_C, FN_VI1_G5_B, 0, 6361 /* IP14_28_26 [3] */ 6362 FN_MSIOF0_SS1, FN_MMC_D6, FN_ADICHS1, FN_TX0_E, 6363 FN_VI1_HSYNC_N_C, FN_IIC0_SCL_C, FN_VI1_G4_B, 0, 6364 /* IP14_25_23 [3] */ 6365 FN_MSIOF0_RXD, FN_ADICHS0, 0, FN_VI1_DATA0_C, FN_VI1_G3_B, 6366 0, 0, 0, 6367 /* IP14_22_20 [3] */ 6368 FN_MSIOF0_TXD, FN_ADICLK, 0, FN_VI1_FIELD_C, FN_VI1_G2_B, 6369 0, 0, 0, 6370 /* IP14_19_17 [3] */ 6371 FN_MSIOF0_SYNC, FN_TX2_C, FN_ADICS_SAMP, 0, 6372 FN_VI1_CLKENB_C, FN_VI1_G1_B, 6373 0, 0, 6374 /* IP14_16_14 [3] */ 6375 FN_MSIOF0_SCK, FN_RX2_C, FN_ADIDATA, 0, 6376 FN_VI1_CLK_C, FN_VI1_G0_B, 6377 0, 0, 6378 /* IP14_13_11 [3] */ 6379 FN_SD2_WP, FN_MMC_D5, FN_IIC1_SDA_C, FN_RX5_B, FN_SCIFA5_RXD_C, 6380 0, 0, 0, 6381 /* IP14_10_8 [3] */ 6382 FN_SD2_CD, FN_MMC_D4, FN_IIC1_SCL_C, FN_TX5_B, FN_SCIFA5_TXD_C, 6383 0, 0, 0, 6384 /* IP14_7 [1] */ 6385 FN_SD2_DATA3, FN_MMC_D3, 6386 /* IP14_6 [1] */ 6387 FN_SD2_DATA2, FN_MMC_D2, 6388 /* IP14_5 [1] */ 6389 FN_SD2_DATA1, FN_MMC_D1, 6390 /* IP14_4 [1] */ 6391 FN_SD2_DATA0, FN_MMC_D0, 6392 /* IP14_3 [1] */ 6393 FN_SD2_CMD, FN_MMC_CMD, 6394 /* IP14_2 [1] */ 6395 FN_SD2_CLK, FN_MMC_CLK, 6396 /* IP14_1_0 [2] */ 6397 FN_SD1_WP, FN_PWM1_B, FN_I2C1_SDA_C, 0, )) 6398 }, 6399 { PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32, 6400 GROUP(2, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2), 6401 GROUP( 6402 /* IP15_31_30 [2] */ 6403 0, 0, 0, 0, 6404 /* IP15_29_27 [3] */ 6405 FN_HTX0, FN_SCIFB0_TXD, 0, FN_GLO_SCLK_C, 6406 FN_CAN0_TX_B, FN_VI1_DATA5_C, 6407 0, 0, 6408 /* IP15_26_24 [3] */ 6409 FN_HRX0, FN_SCIFB0_RXD, 0, FN_GLO_Q1_C, 6410 FN_CAN0_RX_B, FN_VI1_DATA4_C, 6411 0, 0, 6412 /* IP15_23_21 [3] */ 6413 FN_HSCK0, FN_SCIFB0_SCK, 0, FN_GLO_Q0_C, FN_CAN_CLK, 6414 FN_TCLK2, FN_VI1_DATA3_C, 0, 6415 /* IP15_20_18 [3] */ 6416 FN_HRTS0_N, FN_SCIFB0_RTS_N, 0, FN_GLO_I1_C, FN_VI1_DATA2_C, 6417 0, 0, 0, 6418 /* IP15_17_15 [3] */ 6419 FN_HCTS0_N, FN_SCIFB0_CTS_N, 0, FN_GLO_I0_C, 6420 FN_TCLK1, FN_VI1_DATA1_C, 6421 0, 0, 6422 /* IP15_14_12 [3] */ 6423 FN_GPS_MAG, FN_RX4_C, FN_SCIFA4_RXD_C, FN_PWM6, 6424 FN_VI1_G7_B, FN_SCIFA3_SCK_C, 6425 0, 0, 6426 /* IP15_11_9 [3] */ 6427 FN_GPS_SIGN, FN_TX4_C, FN_SCIFA4_TXD_C, FN_PWM5, 6428 FN_VI1_G6_B, FN_SCIFA3_RXD_C, 6429 0, 0, 6430 /* IP15_8_6 [3] */ 6431 FN_GPS_CLK, FN_DU1_DOTCLKIN_C, FN_AUDIO_CLKB_B, 6432 FN_PWM5_B, FN_SCIFA3_TXD_C, 6433 0, 0, 0, 6434 /* IP15_5_4 [2] */ 6435 FN_SIM0_D, FN_IERX, FN_CAN1_RX_D, 0, 6436 /* IP15_3_2 [2] */ 6437 FN_SIM0_CLK, FN_IECLK, FN_CAN_CLK_C, 0, 6438 /* IP15_1_0 [2] */ 6439 FN_SIM0_RST, FN_IETX, FN_CAN1_TX_D, 0, )) 6440 }, 6441 { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32, 6442 GROUP(4, 4, 4, 4, 4, 2, 2, 2, 3, 3), 6443 GROUP( 6444 /* IP16_31_28 [4] */ 6445 0, 0, 0, 0, 0, 0, 0, 0, 6446 0, 0, 0, 0, 0, 0, 0, 0, 6447 /* IP16_27_24 [4] */ 6448 0, 0, 0, 0, 0, 0, 0, 0, 6449 0, 0, 0, 0, 0, 0, 0, 0, 6450 /* IP16_23_20 [4] */ 6451 0, 0, 0, 0, 0, 0, 0, 0, 6452 0, 0, 0, 0, 0, 0, 0, 0, 6453 /* IP16_19_16 [4] */ 6454 0, 0, 0, 0, 0, 0, 0, 0, 6455 0, 0, 0, 0, 0, 0, 0, 0, 6456 /* IP16_15_12 [4] */ 6457 0, 0, 0, 0, 0, 0, 0, 0, 6458 0, 0, 0, 0, 0, 0, 0, 0, 6459 /* IP16_11_10 [2] */ 6460 FN_HRTS1_N, FN_SCIFB1_RTS_N, FN_MLB_DAT, FN_CAN1_RX_B, 6461 /* IP16_9_8 [2] */ 6462 FN_HCTS1_N, FN_SCIFB1_CTS_N, FN_MLB_SIG, FN_CAN1_TX_B, 6463 /* IP16_7_6 [2] */ 6464 FN_HSCK1, FN_SCIFB1_SCK, FN_MLB_CLK, FN_GLO_RFON_C, 6465 /* IP16_5_3 [3] */ 6466 FN_HTX1, FN_SCIFB1_TXD, FN_VI1_R1_B, 6467 FN_GLO_SS_C, FN_VI1_DATA7_C, 6468 0, 0, 0, 6469 /* IP16_2_0 [3] */ 6470 FN_HRX1, FN_SCIFB1_RXD, FN_VI1_R0_B, 6471 FN_GLO_SDATA_C, FN_VI1_DATA6_C, 6472 0, 0, 0, )) 6473 }, 6474 { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32, 6475 GROUP(1, 2, 2, 2, 3, 2, 1, 1, 1, 1, 3, 2, 6476 2, 2, 1, 2, 2, 2), 6477 GROUP( 6478 /* RESERVED [1] */ 6479 0, 0, 6480 /* SEL_SCIF1 [2] */ 6481 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3, 6482 /* SEL_SCIFB [2] */ 6483 FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, FN_SEL_SCIFB_3, 6484 /* SEL_SCIFB2 [2] */ 6485 FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, 6486 FN_SEL_SCIFB2_2, FN_SEL_SCIFB2_3, 6487 /* SEL_SCIFB1 [3] */ 6488 FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, 6489 FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3, 6490 0, 0, 0, 0, 6491 /* SEL_SCIFA1 [2] */ 6492 FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, 0, 6493 /* SEL_SSI9 [1] */ 6494 FN_SEL_SSI9_0, FN_SEL_SSI9_1, 6495 /* SEL_SCFA [1] */ 6496 FN_SEL_SCFA_0, FN_SEL_SCFA_1, 6497 /* SEL_QSP [1] */ 6498 FN_SEL_QSP_0, FN_SEL_QSP_1, 6499 /* SEL_SSI7 [1] */ 6500 FN_SEL_SSI7_0, FN_SEL_SSI7_1, 6501 /* SEL_HSCIF1 [3] */ 6502 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2, 6503 FN_SEL_HSCIF1_3, FN_SEL_HSCIF1_4, 6504 0, 0, 0, 6505 /* RESERVED [2] */ 6506 0, 0, 0, 0, 6507 /* SEL_VI1 [2] */ 6508 FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2, 0, 6509 /* RESERVED [2] */ 6510 0, 0, 0, 0, 6511 /* SEL_TMU [1] */ 6512 FN_SEL_TMU1_0, FN_SEL_TMU1_1, 6513 /* SEL_LBS [2] */ 6514 FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_LBS_2, FN_SEL_LBS_3, 6515 /* SEL_TSIF0 [2] */ 6516 FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, 6517 /* SEL_SOF0 [2] */ 6518 FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2, 0, )) 6519 }, 6520 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32, 6521 GROUP(3, 1, 1, 3, 2, 1, 1, 2, 2, 1, 3, 2, 6522 1, 2, 2, 2, 1, 1, 1), 6523 GROUP( 6524 /* SEL_SCIF0 [3] */ 6525 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, 6526 FN_SEL_SCIF0_3, FN_SEL_SCIF0_4, 6527 0, 0, 0, 6528 /* RESERVED [1] */ 6529 0, 0, 6530 /* SEL_SCIF [1] */ 6531 FN_SEL_SCIF_0, FN_SEL_SCIF_1, 6532 /* SEL_CAN0 [3] */ 6533 FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3, 6534 FN_SEL_CAN0_4, FN_SEL_CAN0_5, 6535 0, 0, 6536 /* SEL_CAN1 [2] */ 6537 FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3, 6538 /* RESERVED [1] */ 6539 0, 0, 6540 /* SEL_SCIFA2 [1] */ 6541 FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, 6542 /* SEL_SCIF4 [2] */ 6543 FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, 0, 6544 /* RESERVED [2] */ 6545 0, 0, 0, 0, 6546 /* SEL_ADG [1] */ 6547 FN_SEL_ADG_0, FN_SEL_ADG_1, 6548 /* SEL_FM [3] */ 6549 FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, 6550 FN_SEL_FM_3, FN_SEL_FM_4, 6551 0, 0, 0, 6552 /* SEL_SCIFA5 [2] */ 6553 FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, 0, 6554 /* RESERVED [1] */ 6555 0, 0, 6556 /* SEL_GPS [2] */ 6557 FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3, 6558 /* SEL_SCIFA4 [2] */ 6559 FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2, 0, 6560 /* SEL_SCIFA3 [2] */ 6561 FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2, 0, 6562 /* SEL_SIM [1] */ 6563 FN_SEL_SIM_0, FN_SEL_SIM_1, 6564 /* RESERVED [1] */ 6565 0, 0, 6566 /* SEL_SSI8 [1] */ 6567 FN_SEL_SSI8_0, FN_SEL_SSI8_1, )) 6568 }, 6569 { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32, 6570 GROUP(2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 2, 2, 6571 3, 2, 2, 2, 1), 6572 GROUP( 6573 /* SEL_HSCIF2 [2] */ 6574 FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1, 6575 FN_SEL_HSCIF2_2, FN_SEL_HSCIF2_3, 6576 /* SEL_CANCLK [2] */ 6577 FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, 6578 FN_SEL_CANCLK_2, FN_SEL_CANCLK_3, 6579 /* SEL_IIC1 [2] */ 6580 FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, 0, 6581 /* SEL_IIC0 [2] */ 6582 FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, 0, 6583 /* SEL_I2C4 [2] */ 6584 FN_SEL_I2C4_0, FN_SEL_I2C4_1, FN_SEL_I2C4_2, 0, 6585 /* SEL_I2C3 [2] */ 6586 FN_SEL_I2C3_0, FN_SEL_I2C3_1, FN_SEL_I2C3_2, FN_SEL_I2C3_3, 6587 /* SEL_SCIF3 [2] */ 6588 FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3, 6589 /* SEL_IEB [2] */ 6590 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0, 6591 /* SEL_MMC [1] */ 6592 FN_SEL_MMC_0, FN_SEL_MMC_1, 6593 /* SEL_SCIF5 [1] */ 6594 FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, 6595 /* RESERVED [2] */ 6596 0, 0, 0, 0, 6597 /* SEL_I2C2 [2] */ 6598 FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3, 6599 /* SEL_I2C1 [3] */ 6600 FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, FN_SEL_I2C1_3, 6601 FN_SEL_I2C1_4, 6602 0, 0, 0, 6603 /* SEL_I2C0 [2] */ 6604 FN_SEL_I2C0_0, FN_SEL_I2C0_1, FN_SEL_I2C0_2, 0, 6605 /* RESERVED [2] */ 6606 0, 0, 0, 0, 6607 /* RESERVED [2] */ 6608 0, 0, 0, 0, 6609 /* RESERVED [1] */ 6610 0, 0, )) 6611 }, 6612 { PINMUX_CFG_REG_VAR("MOD_SEL4", 0xE606009C, 32, 6613 GROUP(3, 2, 2, 1, 1, 1, 1, 3, 2, 2, 3, 1, 6614 1, 1, 2, 2, 2, 2), 6615 GROUP( 6616 /* SEL_SOF1 [3] */ 6617 FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3, 6618 FN_SEL_SOF1_4, 6619 0, 0, 0, 6620 /* SEL_HSCIF0 [2] */ 6621 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, 0, 6622 /* SEL_DIS [2] */ 6623 FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2, 0, 6624 /* RESERVED [1] */ 6625 0, 0, 6626 /* SEL_RAD [1] */ 6627 FN_SEL_RAD_0, FN_SEL_RAD_1, 6628 /* SEL_RCN [1] */ 6629 FN_SEL_RCN_0, FN_SEL_RCN_1, 6630 /* SEL_RSP [1] */ 6631 FN_SEL_RSP_0, FN_SEL_RSP_1, 6632 /* SEL_SCIF2 [3] */ 6633 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, 6634 FN_SEL_SCIF2_3, FN_SEL_SCIF2_4, 6635 0, 0, 0, 6636 /* RESERVED [2] */ 6637 0, 0, 0, 0, 6638 /* RESERVED [2] */ 6639 0, 0, 0, 0, 6640 /* SEL_SOF2 [3] */ 6641 FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2, 6642 FN_SEL_SOF2_3, FN_SEL_SOF2_4, 6643 0, 0, 0, 6644 /* RESERVED [1] */ 6645 0, 0, 6646 /* SEL_SSI1 [1] */ 6647 FN_SEL_SSI1_0, FN_SEL_SSI1_1, 6648 /* SEL_SSI0 [1] */ 6649 FN_SEL_SSI0_0, FN_SEL_SSI0_1, 6650 /* SEL_SSP [2] */ 6651 FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2, 0, 6652 /* RESERVED [2] */ 6653 0, 0, 0, 0, 6654 /* RESERVED [2] */ 6655 0, 0, 0, 0, 6656 /* RESERVED [2] */ 6657 0, 0, 0, 0, )) 6658 }, 6659 { }, 6660 }; 6661 6662 static int r8a7791_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl) 6663 { 6664 if (pin < RCAR_GP_PIN(6, 0) || pin > RCAR_GP_PIN(6, 23)) 6665 return -EINVAL; 6666 6667 *pocctrl = 0xe606008c; 6668 6669 return 31 - (pin & 0x1f); 6670 } 6671 6672 static const struct pinmux_bias_reg pinmux_bias_regs[] = { 6673 { PINMUX_BIAS_REG("PUPR0", 0xe6060100, "N/A", 0) { 6674 [ 0] = RCAR_GP_PIN(1, 4), /* A20 */ 6675 [ 1] = RCAR_GP_PIN(1, 5), /* A21 */ 6676 [ 2] = RCAR_GP_PIN(1, 6), /* A22 */ 6677 [ 3] = RCAR_GP_PIN(1, 7), /* A23 */ 6678 [ 4] = RCAR_GP_PIN(1, 8), /* A24 */ 6679 [ 5] = RCAR_GP_PIN(6, 31), /* DU0_DOTCLKIN */ 6680 [ 6] = RCAR_GP_PIN(0, 0), /* D0 */ 6681 [ 7] = RCAR_GP_PIN(0, 1), /* D1 */ 6682 [ 8] = RCAR_GP_PIN(0, 2), /* D2 */ 6683 [ 9] = RCAR_GP_PIN(0, 3), /* D3 */ 6684 [10] = RCAR_GP_PIN(0, 4), /* D4 */ 6685 [11] = RCAR_GP_PIN(0, 5), /* D5 */ 6686 [12] = RCAR_GP_PIN(0, 6), /* D6 */ 6687 [13] = RCAR_GP_PIN(0, 7), /* D7 */ 6688 [14] = RCAR_GP_PIN(0, 8), /* D8 */ 6689 [15] = RCAR_GP_PIN(0, 9), /* D9 */ 6690 [16] = RCAR_GP_PIN(0, 10), /* D10 */ 6691 [17] = RCAR_GP_PIN(0, 11), /* D11 */ 6692 [18] = RCAR_GP_PIN(0, 12), /* D12 */ 6693 [19] = RCAR_GP_PIN(0, 13), /* D13 */ 6694 [20] = RCAR_GP_PIN(0, 14), /* D14 */ 6695 [21] = RCAR_GP_PIN(0, 15), /* D15 */ 6696 [22] = RCAR_GP_PIN(0, 16), /* A0 */ 6697 [23] = RCAR_GP_PIN(0, 17), /* A1 */ 6698 [24] = RCAR_GP_PIN(0, 18), /* A2 */ 6699 [25] = RCAR_GP_PIN(0, 19), /* A3 */ 6700 [26] = RCAR_GP_PIN(0, 20), /* A4 */ 6701 [27] = RCAR_GP_PIN(0, 21), /* A5 */ 6702 [28] = RCAR_GP_PIN(0, 22), /* A6 */ 6703 [29] = RCAR_GP_PIN(0, 23), /* A7 */ 6704 [30] = RCAR_GP_PIN(0, 24), /* A8 */ 6705 [31] = RCAR_GP_PIN(0, 25), /* A9 */ 6706 } }, 6707 { PINMUX_BIAS_REG("PUPR1", 0xe6060104, "N/A", 0) { 6708 [ 0] = RCAR_GP_PIN(0, 26), /* A10 */ 6709 [ 1] = RCAR_GP_PIN(0, 27), /* A11 */ 6710 [ 2] = RCAR_GP_PIN(0, 28), /* A12 */ 6711 [ 3] = RCAR_GP_PIN(0, 29), /* A13 */ 6712 [ 4] = RCAR_GP_PIN(0, 30), /* A14 */ 6713 [ 5] = RCAR_GP_PIN(0, 31), /* A15 */ 6714 [ 6] = RCAR_GP_PIN(1, 0), /* A16 */ 6715 [ 7] = RCAR_GP_PIN(1, 1), /* A17 */ 6716 [ 8] = RCAR_GP_PIN(1, 2), /* A18 */ 6717 [ 9] = RCAR_GP_PIN(1, 3), /* A19 */ 6718 [10] = PIN_TRST_N, /* TRST# */ 6719 [11] = PIN_TCK, /* TCK */ 6720 [12] = PIN_TMS, /* TMS */ 6721 [13] = PIN_TDI, /* TDI */ 6722 [14] = RCAR_GP_PIN(1, 11), /* CS1#/A26 */ 6723 [15] = RCAR_GP_PIN(1, 12), /* EX_CS0# */ 6724 [16] = RCAR_GP_PIN(1, 13), /* EX_CS1# */ 6725 [17] = RCAR_GP_PIN(1, 14), /* EX_CS2# */ 6726 [18] = RCAR_GP_PIN(1, 15), /* EX_CS3# */ 6727 [19] = RCAR_GP_PIN(1, 16), /* EX_CS4# */ 6728 [20] = RCAR_GP_PIN(1, 17), /* EX_CS5# */ 6729 [21] = RCAR_GP_PIN(1, 18), /* BS# */ 6730 [22] = RCAR_GP_PIN(1, 19), /* RD# */ 6731 [23] = RCAR_GP_PIN(1, 20), /* RD/WR# */ 6732 [24] = RCAR_GP_PIN(1, 21), /* WE0# */ 6733 [25] = RCAR_GP_PIN(1, 22), /* WE1# */ 6734 [26] = RCAR_GP_PIN(1, 23), /* EX_WAIT0 */ 6735 [27] = RCAR_GP_PIN(1, 24), /* DREQ0 */ 6736 [28] = RCAR_GP_PIN(1, 25), /* DACK0 */ 6737 [29] = RCAR_GP_PIN(5, 31), /* SPEEDIN */ 6738 [30] = RCAR_GP_PIN(2, 0), /* SSI_SCK0129 */ 6739 [31] = RCAR_GP_PIN(2, 1), /* SSI_WS0129 */ 6740 } }, 6741 { PINMUX_BIAS_REG("PUPR2", 0xe6060108, "N/A", 0) { 6742 [ 0] = RCAR_GP_PIN(2, 2), /* SSI_SDATA0 */ 6743 [ 1] = RCAR_GP_PIN(2, 3), /* SSI_SCK1 */ 6744 [ 2] = RCAR_GP_PIN(2, 4), /* SSI_WS1 */ 6745 [ 3] = RCAR_GP_PIN(2, 5), /* SSI_SDATA1 */ 6746 [ 4] = RCAR_GP_PIN(2, 6), /* SSI_SCK2 */ 6747 [ 5] = RCAR_GP_PIN(2, 7), /* SSI_WS2 */ 6748 [ 6] = RCAR_GP_PIN(2, 8), /* SSI_SDATA2 */ 6749 [ 7] = RCAR_GP_PIN(2, 9), /* SSI_SCK34 */ 6750 [ 8] = RCAR_GP_PIN(2, 10), /* SSI_WS34 */ 6751 [ 9] = RCAR_GP_PIN(2, 11), /* SSI_SDATA3 */ 6752 [10] = RCAR_GP_PIN(2, 12), /* SSI_SCK4 */ 6753 [11] = RCAR_GP_PIN(2, 13), /* SSI_WS4 */ 6754 [12] = RCAR_GP_PIN(2, 14), /* SSI_SDATA4 */ 6755 [13] = RCAR_GP_PIN(2, 15), /* SSI_SCK5 */ 6756 [14] = RCAR_GP_PIN(2, 16), /* SSI_WS5 */ 6757 [15] = RCAR_GP_PIN(2, 17), /* SSI_SDATA5 */ 6758 [16] = RCAR_GP_PIN(2, 18), /* SSI_SCK6 */ 6759 [17] = RCAR_GP_PIN(2, 19), /* SSI_WS6 */ 6760 [18] = RCAR_GP_PIN(2, 20), /* SSI_SDATA6 */ 6761 [19] = RCAR_GP_PIN(2, 21), /* SSI_SCK78 */ 6762 [20] = RCAR_GP_PIN(2, 22), /* SSI_WS78 */ 6763 [21] = RCAR_GP_PIN(2, 23), /* SSI_SDATA7 */ 6764 [22] = RCAR_GP_PIN(2, 24), /* SSI_SDATA8 */ 6765 [23] = RCAR_GP_PIN(2, 25), /* SSI_SCK9 */ 6766 [24] = RCAR_GP_PIN(2, 26), /* SSI_WS9 */ 6767 [25] = RCAR_GP_PIN(2, 27), /* SSI_SDATA9 */ 6768 [26] = RCAR_GP_PIN(2, 28), /* AUDIO_CLKA */ 6769 [27] = RCAR_GP_PIN(2, 29), /* AUDIO_CLKB */ 6770 [28] = RCAR_GP_PIN(2, 30), /* AUDIO_CLKC */ 6771 [29] = RCAR_GP_PIN(2, 31), /* AUDIO_CLKOUT */ 6772 [30] = RCAR_GP_PIN(7, 10), /* IRQ0 */ 6773 [31] = RCAR_GP_PIN(7, 11), /* IRQ1 */ 6774 } }, 6775 { PINMUX_BIAS_REG("PUPR3", 0xe606010c, "N/A", 0) { 6776 [ 0] = RCAR_GP_PIN(7, 12), /* IRQ2 */ 6777 [ 1] = RCAR_GP_PIN(7, 13), /* IRQ3 */ 6778 [ 2] = RCAR_GP_PIN(7, 14), /* IRQ4 */ 6779 [ 3] = RCAR_GP_PIN(7, 15), /* IRQ5 */ 6780 [ 4] = RCAR_GP_PIN(7, 16), /* IRQ6 */ 6781 [ 5] = RCAR_GP_PIN(7, 17), /* IRQ7 */ 6782 [ 6] = RCAR_GP_PIN(7, 18), /* IRQ8 */ 6783 [ 7] = RCAR_GP_PIN(7, 19), /* IRQ9 */ 6784 [ 8] = RCAR_GP_PIN(3, 0), /* DU1_DR0 */ 6785 [ 9] = RCAR_GP_PIN(3, 1), /* DU1_DR1 */ 6786 [10] = RCAR_GP_PIN(3, 2), /* DU1_DR2 */ 6787 [11] = RCAR_GP_PIN(3, 3), /* DU1_DR3 */ 6788 [12] = RCAR_GP_PIN(3, 4), /* DU1_DR4 */ 6789 [13] = RCAR_GP_PIN(3, 5), /* DU1_DR5 */ 6790 [14] = RCAR_GP_PIN(3, 6), /* DU1_DR6 */ 6791 [15] = RCAR_GP_PIN(3, 7), /* DU1_DR7 */ 6792 [16] = RCAR_GP_PIN(3, 8), /* DU1_DG0 */ 6793 [17] = RCAR_GP_PIN(3, 9), /* DU1_DG1 */ 6794 [18] = RCAR_GP_PIN(3, 10), /* DU1_DG2 */ 6795 [19] = RCAR_GP_PIN(3, 11), /* DU1_DG3 */ 6796 [20] = RCAR_GP_PIN(3, 12), /* DU1_DG4 */ 6797 [21] = RCAR_GP_PIN(3, 13), /* DU1_DG5 */ 6798 [22] = RCAR_GP_PIN(3, 14), /* DU1_DG6 */ 6799 [23] = RCAR_GP_PIN(3, 15), /* DU1_DG7 */ 6800 [24] = RCAR_GP_PIN(3, 16), /* DU1_DB0 */ 6801 [25] = RCAR_GP_PIN(3, 17), /* DU1_DB1 */ 6802 [26] = RCAR_GP_PIN(3, 18), /* DU1_DB2 */ 6803 [27] = RCAR_GP_PIN(3, 19), /* DU1_DB3 */ 6804 [28] = RCAR_GP_PIN(3, 20), /* DU1_DB4 */ 6805 [29] = RCAR_GP_PIN(3, 21), /* DU1_DB5 */ 6806 [30] = RCAR_GP_PIN(3, 22), /* DU1_DB6 */ 6807 [31] = RCAR_GP_PIN(3, 23), /* DU1_DB7 */ 6808 } }, 6809 { PINMUX_BIAS_REG("PUPR4", 0xe6060110, "N/A", 0) { 6810 [ 0] = RCAR_GP_PIN(3, 24), /* DU1_DOTCLKIN */ 6811 [ 1] = RCAR_GP_PIN(3, 25), /* DU1_DOTCLKOUT0 */ 6812 [ 2] = RCAR_GP_PIN(3, 26), /* DU1_DOTCLKOUT1 */ 6813 [ 3] = RCAR_GP_PIN(3, 27), /* DU1_EXHSYNC_DU1_HSYNC */ 6814 [ 4] = RCAR_GP_PIN(3, 28), /* DU1_EXVSYNC_DU1_VSYNC */ 6815 [ 5] = RCAR_GP_PIN(3, 29), /* DU1_EXODDF_DU1_ODDF_DISP_CDE */ 6816 [ 6] = RCAR_GP_PIN(3, 30), /* DU1_DISP */ 6817 [ 7] = RCAR_GP_PIN(3, 31), /* DU1_CDE */ 6818 [ 8] = RCAR_GP_PIN(4, 0), /* VI0_CLK */ 6819 [ 9] = RCAR_GP_PIN(4, 1), /* VI0_CLKENB */ 6820 [10] = RCAR_GP_PIN(4, 2), /* VI0_FIELD */ 6821 [11] = RCAR_GP_PIN(4, 3), /* VI0_HSYNC# */ 6822 [12] = RCAR_GP_PIN(4, 4), /* VI0_VSYNC# */ 6823 [13] = RCAR_GP_PIN(4, 5), /* VI0_DATA0_VI0_B0 */ 6824 [14] = RCAR_GP_PIN(4, 6), /* VI0_DATA1_VI0_B1 */ 6825 [15] = RCAR_GP_PIN(4, 7), /* VI0_DATA2_VI0_B2 */ 6826 [16] = RCAR_GP_PIN(4, 8), /* VI0_DATA3_VI0_B3 */ 6827 [17] = RCAR_GP_PIN(4, 9), /* VI0_DATA4_VI0_B4 */ 6828 [18] = RCAR_GP_PIN(4, 10), /* VI0_DATA5_VI0_B5 */ 6829 [19] = RCAR_GP_PIN(4, 11), /* VI0_DATA6_VI0_B6 */ 6830 [20] = RCAR_GP_PIN(4, 12), /* VI0_DATA7_VI0_B7 */ 6831 [21] = RCAR_GP_PIN(4, 13), /* VI0_G0 */ 6832 [22] = RCAR_GP_PIN(4, 14), /* VI0_G1 */ 6833 [23] = RCAR_GP_PIN(4, 15), /* VI0_G2 */ 6834 [24] = RCAR_GP_PIN(4, 16), /* VI0_G3 */ 6835 [25] = RCAR_GP_PIN(4, 17), /* VI0_G4 */ 6836 [26] = RCAR_GP_PIN(4, 18), /* VI0_G5 */ 6837 [27] = RCAR_GP_PIN(4, 19), /* VI0_G6 */ 6838 [28] = RCAR_GP_PIN(4, 20), /* VI0_G7 */ 6839 [29] = RCAR_GP_PIN(4, 21), /* VI0_R0 */ 6840 [30] = RCAR_GP_PIN(4, 22), /* VI0_R1 */ 6841 [31] = RCAR_GP_PIN(4, 23), /* VI0_R2 */ 6842 } }, 6843 { PINMUX_BIAS_REG("PUPR5", 0xe6060114, "N/A", 0) { 6844 [ 0] = RCAR_GP_PIN(4, 24), /* VI0_R3 */ 6845 [ 1] = RCAR_GP_PIN(4, 25), /* VI0_R4 */ 6846 [ 2] = RCAR_GP_PIN(4, 26), /* VI0_R5 */ 6847 [ 3] = RCAR_GP_PIN(4, 27), /* VI0_R6 */ 6848 [ 4] = RCAR_GP_PIN(4, 28), /* VI0_R7 */ 6849 [ 5] = RCAR_GP_PIN(5, 0), /* VI1_HSYNC# */ 6850 [ 6] = RCAR_GP_PIN(5, 1), /* VI1_VSYNC# */ 6851 [ 7] = RCAR_GP_PIN(5, 2), /* VI1_CLKENB */ 6852 [ 8] = RCAR_GP_PIN(5, 3), /* VI1_FIELD */ 6853 [ 9] = RCAR_GP_PIN(5, 4), /* VI1_CLK */ 6854 [10] = RCAR_GP_PIN(5, 5), /* VI1_DATA0 */ 6855 [11] = RCAR_GP_PIN(5, 6), /* VI1_DATA1 */ 6856 [12] = RCAR_GP_PIN(5, 7), /* VI1_DATA2 */ 6857 [13] = RCAR_GP_PIN(5, 8), /* VI1_DATA3 */ 6858 [14] = RCAR_GP_PIN(5, 9), /* VI1_DATA4 */ 6859 [15] = RCAR_GP_PIN(5, 10), /* VI1_DATA5 */ 6860 [16] = RCAR_GP_PIN(5, 11), /* VI1_DATA6 */ 6861 [17] = RCAR_GP_PIN(5, 12), /* VI1_DATA7 */ 6862 [18] = RCAR_GP_PIN(5, 13), /* ETH_MDIO */ 6863 [19] = RCAR_GP_PIN(5, 14), /* ETH_CRS_DV */ 6864 [20] = RCAR_GP_PIN(5, 15), /* ETH_RX_ER */ 6865 [21] = RCAR_GP_PIN(5, 16), /* ETH_RXD0 */ 6866 [22] = RCAR_GP_PIN(5, 17), /* ETH_RXD1 */ 6867 [23] = RCAR_GP_PIN(5, 18), /* ETH_LINK */ 6868 [24] = RCAR_GP_PIN(5, 19), /* ETH_REFCLK */ 6869 [25] = RCAR_GP_PIN(5, 20), /* ETH_TXD1 */ 6870 [26] = RCAR_GP_PIN(5, 21), /* ETH_TX_EN */ 6871 [27] = RCAR_GP_PIN(5, 22), /* ETH_MAGIC */ 6872 [28] = RCAR_GP_PIN(5, 23), /* ETH_TXD0 */ 6873 [29] = RCAR_GP_PIN(5, 24), /* ETH_MDC */ 6874 [30] = RCAR_GP_PIN(5, 25), /* STP_IVCXO27_0 */ 6875 [31] = RCAR_GP_PIN(5, 26), /* STP_ISCLK_0 */ 6876 } }, 6877 { PINMUX_BIAS_REG("PUPR6", 0xe6060118, "N/A", 0) { 6878 [ 0] = RCAR_GP_PIN(5, 27), /* STP_ISD_0 */ 6879 [ 1] = RCAR_GP_PIN(5, 28), /* STP_ISEN_0 */ 6880 [ 2] = RCAR_GP_PIN(5, 29), /* STP_ISSYNC_0 */ 6881 [ 3] = RCAR_GP_PIN(5, 30), /* STP_OPWM_0 */ 6882 [ 4] = RCAR_GP_PIN(6, 0), /* SD0_CLK */ 6883 [ 5] = RCAR_GP_PIN(6, 1), /* SD0_CMD */ 6884 [ 6] = RCAR_GP_PIN(6, 2), /* SD0_DATA0 */ 6885 [ 7] = RCAR_GP_PIN(6, 3), /* SD0_DATA1 */ 6886 [ 8] = RCAR_GP_PIN(6, 4), /* SD0_DATA2 */ 6887 [ 9] = RCAR_GP_PIN(6, 5), /* SD0_DATA3 */ 6888 [10] = RCAR_GP_PIN(6, 6), /* SD0_CD */ 6889 [11] = RCAR_GP_PIN(6, 7), /* SD0_WP */ 6890 [12] = RCAR_GP_PIN(6, 8), /* SD2_CLK */ 6891 [13] = RCAR_GP_PIN(6, 9), /* SD2_CMD */ 6892 [14] = RCAR_GP_PIN(6, 10), /* SD2_DATA0 */ 6893 [15] = RCAR_GP_PIN(6, 11), /* SD2_DATA1 */ 6894 [16] = RCAR_GP_PIN(6, 12), /* SD2_DATA2 */ 6895 [17] = RCAR_GP_PIN(6, 13), /* SD2_DATA3 */ 6896 [18] = RCAR_GP_PIN(6, 14), /* SD2_CD */ 6897 [19] = RCAR_GP_PIN(6, 15), /* SD2_WP */ 6898 [20] = RCAR_GP_PIN(6, 16), /* SD3_CLK */ 6899 [21] = RCAR_GP_PIN(6, 17), /* SD3_CMD */ 6900 [22] = RCAR_GP_PIN(6, 18), /* SD3_DATA0 */ 6901 [23] = RCAR_GP_PIN(6, 19), /* SD3_DATA1 */ 6902 [24] = RCAR_GP_PIN(6, 20), /* SD3_DATA2 */ 6903 [25] = RCAR_GP_PIN(6, 21), /* SD3_DATA3 */ 6904 [26] = RCAR_GP_PIN(6, 22), /* SD3_CD */ 6905 [27] = RCAR_GP_PIN(6, 23), /* SD3_WP */ 6906 [28] = RCAR_GP_PIN(6, 24), /* MSIOF0_SCK */ 6907 [29] = RCAR_GP_PIN(6, 25), /* MSIOF0_SYNC */ 6908 [30] = RCAR_GP_PIN(6, 26), /* MSIOF0_TXD */ 6909 [31] = RCAR_GP_PIN(6, 27), /* MSIOF0_RXD */ 6910 } }, 6911 { PINMUX_BIAS_REG("PUPR7", 0xe606011c, "N/A", 0) { 6912 /* PUPR7 pull-up pins */ 6913 [ 0] = RCAR_GP_PIN(6, 28), /* MSIOF0_SS1 */ 6914 [ 1] = RCAR_GP_PIN(6, 29), /* MSIOF0_SS2 */ 6915 [ 2] = RCAR_GP_PIN(4, 29), /* SIM0_RST */ 6916 [ 3] = RCAR_GP_PIN(4, 30), /* SIM0_CLK */ 6917 [ 4] = RCAR_GP_PIN(4, 31), /* SIM0_D */ 6918 [ 5] = RCAR_GP_PIN(7, 20), /* GPS_CLK */ 6919 [ 6] = RCAR_GP_PIN(7, 21), /* GPS_SIGN */ 6920 [ 7] = RCAR_GP_PIN(7, 22), /* GPS_MAG */ 6921 [ 8] = RCAR_GP_PIN(7, 0), /* HCTS0# */ 6922 [ 9] = RCAR_GP_PIN(7, 1), /* HRTS0# */ 6923 [10] = RCAR_GP_PIN(7, 2), /* HSCK0 */ 6924 [11] = RCAR_GP_PIN(7, 3), /* HRX0 */ 6925 [12] = RCAR_GP_PIN(7, 4), /* HTX0 */ 6926 [13] = RCAR_GP_PIN(7, 5), /* HRX1 */ 6927 [14] = RCAR_GP_PIN(7, 6), /* HTX1 */ 6928 [15] = SH_PFC_PIN_NONE, 6929 [16] = SH_PFC_PIN_NONE, 6930 [17] = SH_PFC_PIN_NONE, 6931 [18] = RCAR_GP_PIN(1, 9), /* A25 */ 6932 [19] = SH_PFC_PIN_NONE, 6933 [20] = RCAR_GP_PIN(1, 10), /* CS0# */ 6934 [21] = RCAR_GP_PIN(7, 23), /* USB0_PWEN */ 6935 [22] = RCAR_GP_PIN(7, 24), /* USB0_OVC */ 6936 [23] = RCAR_GP_PIN(7, 25), /* USB1_PWEN */ 6937 [24] = RCAR_GP_PIN(6, 30), /* USB1_OVC */ 6938 [25] = PIN_AVS1, /* AVS1 */ 6939 [26] = PIN_AVS2, /* AVS2 */ 6940 [27] = SH_PFC_PIN_NONE, 6941 [28] = SH_PFC_PIN_NONE, 6942 [29] = SH_PFC_PIN_NONE, 6943 [30] = SH_PFC_PIN_NONE, 6944 [31] = SH_PFC_PIN_NONE, 6945 } }, 6946 { PINMUX_BIAS_REG("N/A", 0, "PUPR7", 0xe606011c) { 6947 /* PUPR7 pull-down pins */ 6948 [ 0] = SH_PFC_PIN_NONE, 6949 [ 1] = SH_PFC_PIN_NONE, 6950 [ 2] = SH_PFC_PIN_NONE, 6951 [ 3] = SH_PFC_PIN_NONE, 6952 [ 4] = SH_PFC_PIN_NONE, 6953 [ 5] = SH_PFC_PIN_NONE, 6954 [ 6] = SH_PFC_PIN_NONE, 6955 [ 7] = SH_PFC_PIN_NONE, 6956 [ 8] = SH_PFC_PIN_NONE, 6957 [ 9] = SH_PFC_PIN_NONE, 6958 [10] = SH_PFC_PIN_NONE, 6959 [11] = SH_PFC_PIN_NONE, 6960 [12] = SH_PFC_PIN_NONE, 6961 [13] = SH_PFC_PIN_NONE, 6962 [14] = SH_PFC_PIN_NONE, 6963 [15] = SH_PFC_PIN_NONE, 6964 [16] = SH_PFC_PIN_NONE, 6965 [17] = SH_PFC_PIN_NONE, 6966 [18] = SH_PFC_PIN_NONE, 6967 [19] = PIN_ASEBRK_N_ACK, /* ASEBRK#/ACK */ 6968 [20] = SH_PFC_PIN_NONE, 6969 [21] = SH_PFC_PIN_NONE, 6970 [22] = SH_PFC_PIN_NONE, 6971 [23] = SH_PFC_PIN_NONE, 6972 [24] = SH_PFC_PIN_NONE, 6973 [25] = SH_PFC_PIN_NONE, 6974 [26] = SH_PFC_PIN_NONE, 6975 [27] = SH_PFC_PIN_NONE, 6976 [28] = SH_PFC_PIN_NONE, 6977 [29] = SH_PFC_PIN_NONE, 6978 [30] = SH_PFC_PIN_NONE, 6979 [31] = SH_PFC_PIN_NONE, 6980 } }, 6981 { /* sentinel */ }, 6982 }; 6983 6984 static const struct sh_pfc_soc_operations r8a7791_pfc_ops = { 6985 .pin_to_pocctrl = r8a7791_pin_to_pocctrl, 6986 .get_bias = rcar_pinmux_get_bias, 6987 .set_bias = rcar_pinmux_set_bias, 6988 }; 6989 6990 #ifdef CONFIG_PINCTRL_PFC_R8A7743 6991 const struct sh_pfc_soc_info r8a7743_pinmux_info = { 6992 .name = "r8a77430_pfc", 6993 .ops = &r8a7791_pfc_ops, 6994 .unlock_reg = 0xe6060000, /* PMMR */ 6995 6996 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 6997 6998 .pins = pinmux_pins, 6999 .nr_pins = ARRAY_SIZE(pinmux_pins), 7000 .groups = pinmux_groups.common, 7001 .nr_groups = ARRAY_SIZE(pinmux_groups.common), 7002 .functions = pinmux_functions.common, 7003 .nr_functions = ARRAY_SIZE(pinmux_functions.common), 7004 7005 .cfg_regs = pinmux_config_regs, 7006 .bias_regs = pinmux_bias_regs, 7007 7008 .pinmux_data = pinmux_data, 7009 .pinmux_data_size = ARRAY_SIZE(pinmux_data), 7010 }; 7011 #endif 7012 7013 #ifdef CONFIG_PINCTRL_PFC_R8A7744 7014 const struct sh_pfc_soc_info r8a7744_pinmux_info = { 7015 .name = "r8a77440_pfc", 7016 .ops = &r8a7791_pfc_ops, 7017 .unlock_reg = 0xe6060000, /* PMMR */ 7018 7019 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 7020 7021 .pins = pinmux_pins, 7022 .nr_pins = ARRAY_SIZE(pinmux_pins), 7023 .groups = pinmux_groups.common, 7024 .nr_groups = ARRAY_SIZE(pinmux_groups.common), 7025 .functions = pinmux_functions.common, 7026 .nr_functions = ARRAY_SIZE(pinmux_functions.common), 7027 7028 .cfg_regs = pinmux_config_regs, 7029 .bias_regs = pinmux_bias_regs, 7030 7031 .pinmux_data = pinmux_data, 7032 .pinmux_data_size = ARRAY_SIZE(pinmux_data), 7033 }; 7034 #endif 7035 7036 #ifdef CONFIG_PINCTRL_PFC_R8A7791 7037 const struct sh_pfc_soc_info r8a7791_pinmux_info = { 7038 .name = "r8a77910_pfc", 7039 .ops = &r8a7791_pfc_ops, 7040 .unlock_reg = 0xe6060000, /* PMMR */ 7041 7042 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 7043 7044 .pins = pinmux_pins, 7045 .nr_pins = ARRAY_SIZE(pinmux_pins), 7046 .groups = pinmux_groups.common, 7047 .nr_groups = ARRAY_SIZE(pinmux_groups.common) + 7048 ARRAY_SIZE(pinmux_groups.automotive), 7049 .functions = pinmux_functions.common, 7050 .nr_functions = ARRAY_SIZE(pinmux_functions.common) + 7051 ARRAY_SIZE(pinmux_functions.automotive), 7052 7053 .cfg_regs = pinmux_config_regs, 7054 .bias_regs = pinmux_bias_regs, 7055 7056 .pinmux_data = pinmux_data, 7057 .pinmux_data_size = ARRAY_SIZE(pinmux_data), 7058 }; 7059 #endif 7060 7061 #ifdef CONFIG_PINCTRL_PFC_R8A7793 7062 const struct sh_pfc_soc_info r8a7793_pinmux_info = { 7063 .name = "r8a77930_pfc", 7064 .ops = &r8a7791_pfc_ops, 7065 .unlock_reg = 0xe6060000, /* PMMR */ 7066 7067 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 7068 7069 .pins = pinmux_pins, 7070 .nr_pins = ARRAY_SIZE(pinmux_pins), 7071 .groups = pinmux_groups.common, 7072 .nr_groups = ARRAY_SIZE(pinmux_groups.common) + 7073 ARRAY_SIZE(pinmux_groups.automotive), 7074 .functions = pinmux_functions.common, 7075 .nr_functions = ARRAY_SIZE(pinmux_functions.common) + 7076 ARRAY_SIZE(pinmux_functions.automotive), 7077 7078 .cfg_regs = pinmux_config_regs, 7079 .bias_regs = pinmux_bias_regs, 7080 7081 .pinmux_data = pinmux_data, 7082 .pinmux_data_size = ARRAY_SIZE(pinmux_data), 7083 }; 7084 #endif 7085