1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * r8a7791/r8a7743 processor support - PFC hardware block. 4 * 5 * Copyright (C) 2013 Renesas Electronics Corporation 6 * Copyright (C) 2014-2017 Cogent Embedded, Inc. 7 */ 8 9 #include <linux/errno.h> 10 #include <linux/kernel.h> 11 12 #include "sh_pfc.h" 13 14 /* 15 * Pins 0-23 assigned to GPIO bank 6 can be used for SD interfaces in 16 * which case they support both 3.3V and 1.8V signalling. 17 */ 18 #define CPU_ALL_GP(fn, sfx) \ 19 PORT_GP_32(0, fn, sfx), \ 20 PORT_GP_26(1, fn, sfx), \ 21 PORT_GP_32(2, fn, sfx), \ 22 PORT_GP_32(3, fn, sfx), \ 23 PORT_GP_32(4, fn, sfx), \ 24 PORT_GP_32(5, fn, sfx), \ 25 PORT_GP_CFG_24(6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ 26 PORT_GP_1(6, 24, fn, sfx), \ 27 PORT_GP_1(6, 25, fn, sfx), \ 28 PORT_GP_1(6, 26, fn, sfx), \ 29 PORT_GP_1(6, 27, fn, sfx), \ 30 PORT_GP_1(6, 28, fn, sfx), \ 31 PORT_GP_1(6, 29, fn, sfx), \ 32 PORT_GP_1(6, 30, fn, sfx), \ 33 PORT_GP_1(6, 31, fn, sfx), \ 34 PORT_GP_26(7, fn, sfx) 35 36 enum { 37 PINMUX_RESERVED = 0, 38 39 PINMUX_DATA_BEGIN, 40 GP_ALL(DATA), 41 PINMUX_DATA_END, 42 43 PINMUX_FUNCTION_BEGIN, 44 GP_ALL(FN), 45 46 /* GPSR0 */ 47 FN_IP0_0, FN_IP0_1, FN_IP0_2, FN_IP0_3, FN_IP0_4, FN_IP0_5, 48 FN_IP0_6, FN_IP0_7, FN_IP0_8, FN_IP0_9, FN_IP0_10, FN_IP0_11, 49 FN_IP0_12, FN_IP0_13, FN_IP0_14, FN_IP0_15, FN_IP0_18_16, FN_IP0_20_19, 50 FN_IP0_22_21, FN_IP0_24_23, FN_IP0_26_25, FN_IP0_28_27, FN_IP0_30_29, 51 FN_IP1_1_0, FN_IP1_3_2, FN_IP1_5_4, FN_IP1_7_6, FN_IP1_10_8, 52 FN_IP1_13_11, FN_IP1_16_14, FN_IP1_19_17, FN_IP1_22_20, 53 54 /* GPSR1 */ 55 FN_IP1_25_23, FN_IP1_28_26, FN_IP1_31_29, FN_IP2_2_0, FN_IP2_4_3, 56 FN_IP2_6_5, FN_IP2_9_7, FN_IP2_12_10, FN_IP2_15_13, FN_IP2_18_16, 57 FN_IP2_20_19, FN_IP2_22_21, FN_EX_CS0_N, FN_IP2_24_23, FN_IP2_26_25, 58 FN_IP2_29_27, FN_IP3_2_0, FN_IP3_5_3, FN_IP3_8_6, FN_RD_N, 59 FN_IP3_11_9, FN_IP3_13_12, FN_IP3_15_14 , FN_IP3_17_16 , FN_IP3_19_18, 60 FN_IP3_21_20, 61 62 /* GPSR2 */ 63 FN_IP3_27_25, FN_IP3_30_28, FN_IP4_1_0, FN_IP4_4_2, FN_IP4_7_5, 64 FN_IP4_9_8, FN_IP4_12_10, FN_IP4_15_13, FN_IP4_18_16, FN_IP4_19, 65 FN_IP4_20, FN_IP4_21, FN_IP4_23_22, FN_IP4_25_24, FN_IP4_27_26, 66 FN_IP4_30_28, FN_IP5_2_0, FN_IP5_5_3, FN_IP5_8_6, FN_IP5_11_9, 67 FN_IP5_14_12, FN_IP5_16_15, FN_IP5_19_17, FN_IP5_21_20, FN_IP5_23_22, 68 FN_IP5_25_24, FN_IP5_28_26, FN_IP5_31_29, FN_AUDIO_CLKA, FN_IP6_2_0, 69 FN_IP6_5_3, FN_IP6_7_6, 70 71 /* GPSR3 */ 72 FN_IP7_5_3, FN_IP7_8_6, FN_IP7_10_9, FN_IP7_12_11, FN_IP7_14_13, 73 FN_IP7_16_15, FN_IP7_18_17, FN_IP7_20_19, FN_IP7_23_21, FN_IP7_26_24, 74 FN_IP7_29_27, FN_IP8_2_0, FN_IP8_5_3, FN_IP8_8_6, FN_IP8_11_9, 75 FN_IP8_14_12, FN_IP8_17_15, FN_IP8_20_18, FN_IP8_23_21, FN_IP8_25_24, 76 FN_IP8_27_26, FN_IP8_30_28, FN_IP9_2_0, FN_IP9_5_3, FN_IP9_6, FN_IP9_7, 77 FN_IP9_10_8, FN_IP9_11, FN_IP9_12, FN_IP9_15_13, FN_IP9_16, 78 FN_IP9_18_17, 79 80 /* GPSR4 */ 81 FN_VI0_CLK, FN_IP9_20_19, FN_IP9_22_21, FN_IP9_24_23, FN_IP9_26_25, 82 FN_VI0_DATA0_VI0_B0, FN_VI0_DATA1_VI0_B1, FN_VI0_DATA2_VI0_B2, 83 FN_IP9_28_27, FN_VI0_DATA4_VI0_B4, FN_VI0_DATA5_VI0_B5, 84 FN_VI0_DATA6_VI0_B6, FN_VI0_DATA7_VI0_B7, FN_IP9_31_29, FN_IP10_2_0, 85 FN_IP10_5_3, FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_16_15, 86 FN_IP10_18_17, FN_IP10_21_19, FN_IP10_24_22, FN_IP10_26_25, 87 FN_IP10_28_27, FN_IP10_31_29, FN_IP11_2_0, FN_IP11_5_3, FN_IP11_8_6, 88 FN_IP15_1_0, FN_IP15_3_2, FN_IP15_5_4, 89 90 /* GPSR5 */ 91 FN_IP11_11_9, FN_IP11_14_12, FN_IP11_16_15, FN_IP11_18_17, FN_IP11_19, 92 FN_IP11_20, FN_IP11_21, FN_IP11_22, FN_IP11_23, FN_IP11_24, 93 FN_IP11_25, FN_IP11_26, FN_IP11_27, FN_IP11_29_28, FN_IP11_31_30, 94 FN_IP12_1_0, FN_IP12_3_2, FN_IP12_6_4, FN_IP12_9_7, FN_IP12_12_10, 95 FN_IP12_15_13, FN_IP12_17_16, FN_IP12_19_18, FN_IP12_21_20, 96 FN_IP12_23_22, FN_IP12_26_24, FN_IP12_29_27, FN_IP13_2_0, FN_IP13_4_3, 97 FN_IP13_6_5, FN_IP13_9_7, FN_IP3_24_22, 98 99 /* GPSR6 */ 100 FN_IP13_10, FN_IP13_11, FN_IP13_12, FN_IP13_13, FN_IP13_14, 101 FN_IP13_15, FN_IP13_18_16, FN_IP13_21_19, 102 FN_IP13_22, FN_IP13_24_23, FN_SD1_CLK, 103 FN_IP13_25, FN_IP13_26, FN_IP13_27, FN_IP13_30_28, FN_IP14_1_0, 104 FN_IP14_2, FN_IP14_3, FN_IP14_4, FN_IP14_5, FN_IP14_6, FN_IP14_7, 105 FN_IP14_10_8, FN_IP14_13_11, FN_IP14_16_14, FN_IP14_19_17, 106 FN_IP14_22_20, FN_IP14_25_23, FN_IP14_28_26, FN_IP14_31_29, 107 FN_USB1_OVC, FN_DU0_DOTCLKIN, 108 109 /* GPSR7 */ 110 FN_IP15_17_15, FN_IP15_20_18, FN_IP15_23_21, FN_IP15_26_24, 111 FN_IP15_29_27, FN_IP16_2_0, FN_IP16_5_3, FN_IP16_7_6, FN_IP16_9_8, 112 FN_IP16_11_10, FN_IP6_9_8, FN_IP6_11_10, FN_IP6_13_12, FN_IP6_15_14, 113 FN_IP6_18_16, FN_IP6_20_19, FN_IP6_23_21, FN_IP6_26_24, FN_IP6_29_27, 114 FN_IP7_2_0, FN_IP15_8_6, FN_IP15_11_9, FN_IP15_14_12, 115 FN_USB0_PWEN, FN_USB0_OVC, FN_USB1_PWEN, 116 117 /* IPSR0 */ 118 FN_D0, FN_D1, FN_D2, FN_D3, FN_D4, FN_D5, FN_D6, FN_D7, FN_D8, 119 FN_D9, FN_D10, FN_D11, FN_D12, FN_D13, FN_D14, FN_D15, 120 FN_A0, FN_ATAWR0_N_C, FN_MSIOF0_SCK_B, FN_I2C0_SCL_C, FN_PWM2_B, 121 FN_A1, FN_MSIOF0_SYNC_B, FN_A2, FN_MSIOF0_SS1_B, 122 FN_A3, FN_MSIOF0_SS2_B, FN_A4, FN_MSIOF0_TXD_B, 123 FN_A5, FN_MSIOF0_RXD_B, FN_A6, FN_MSIOF1_SCK, 124 125 /* IPSR1 */ 126 FN_A7, FN_MSIOF1_SYNC, FN_A8, FN_MSIOF1_SS1, FN_I2C0_SCL, 127 FN_A9, FN_MSIOF1_SS2, FN_I2C0_SDA, 128 FN_A10, FN_MSIOF1_TXD, FN_MSIOF1_TXD_D, 129 FN_A11, FN_MSIOF1_RXD, FN_I2C3_SCL_D, FN_MSIOF1_RXD_D, 130 FN_A12, FN_FMCLK, FN_I2C3_SDA_D, FN_MSIOF1_SCK_D, 131 FN_A13, FN_ATAG0_N_C, FN_BPFCLK, FN_MSIOF1_SS1_D, 132 FN_A14, FN_ATADIR0_N_C, FN_FMIN, FN_FMIN_C, FN_MSIOF1_SYNC_D, 133 FN_A15, FN_BPFCLK_C, 134 FN_A16, FN_DREQ2_B, FN_FMCLK_C, FN_SCIFA1_SCK_B, 135 FN_A17, FN_DACK2_B, FN_I2C0_SDA_C, 136 FN_A18, FN_DREQ1, FN_SCIFA1_RXD_C, FN_SCIFB1_RXD_C, 137 138 /* IPSR2 */ 139 FN_A19, FN_DACK1, FN_SCIFA1_TXD_C, FN_SCIFB1_TXD_C, FN_SCIFB1_SCK_B, 140 FN_A20, FN_SPCLK, 141 FN_A21, FN_ATAWR0_N_B, FN_MOSI_IO0, 142 FN_A22, FN_MISO_IO1, FN_FMCLK_B, FN_TX0, FN_SCIFA0_TXD, 143 FN_A23, FN_IO2, FN_BPFCLK_B, FN_RX0, FN_SCIFA0_RXD, 144 FN_A24, FN_DREQ2, FN_IO3, FN_TX1, FN_SCIFA1_TXD, 145 FN_A25, FN_DACK2, FN_SSL, FN_DREQ1_C, FN_RX1, FN_SCIFA1_RXD, 146 FN_CS0_N, FN_ATAG0_N_B, FN_I2C1_SCL, 147 FN_CS1_N_A26, FN_ATADIR0_N_B, FN_I2C1_SDA, 148 FN_EX_CS1_N, FN_MSIOF2_SCK, 149 FN_EX_CS2_N, FN_ATAWR0_N, FN_MSIOF2_SYNC, 150 FN_EX_CS3_N, FN_ATADIR0_N, FN_MSIOF2_TXD, FN_ATAG0_N, FN_EX_WAIT1, 151 152 /* IPSR3 */ 153 FN_EX_CS4_N, FN_ATARD0_N, FN_MSIOF2_RXD, FN_EX_WAIT2, 154 FN_EX_CS5_N, FN_ATACS00_N, FN_MSIOF2_SS1, FN_HRX1_B, 155 FN_SCIFB1_RXD_B, FN_PWM1, FN_TPU_TO1, 156 FN_BS_N, FN_ATACS10_N, FN_MSIOF2_SS2, FN_HTX1_B, 157 FN_SCIFB1_TXD_B, FN_PWM2, FN_TPU_TO2, 158 FN_RD_WR_N, FN_HRX2_B, FN_FMIN_B, FN_SCIFB0_RXD_B, FN_DREQ1_D, 159 FN_WE0_N, FN_HCTS2_N_B, FN_SCIFB0_TXD_B, 160 FN_WE1_N, FN_ATARD0_N_B, FN_HTX2_B, FN_SCIFB0_RTS_N_B, 161 FN_EX_WAIT0, FN_HRTS2_N_B, FN_SCIFB0_CTS_N_B, 162 FN_DREQ0, FN_PWM3, FN_TPU_TO3, 163 FN_DACK0, FN_DRACK0, FN_REMOCON, 164 FN_SPEEDIN, FN_HSCK0_C, FN_HSCK2_C, FN_SCIFB0_SCK_B, 165 FN_SCIFB2_SCK_B, FN_DREQ2_C, FN_HTX2_D, 166 FN_SSI_SCK0129, FN_HRX0_C, FN_HRX2_C, FN_SCIFB0_RXD_C, FN_SCIFB2_RXD_C, 167 FN_SSI_WS0129, FN_HTX0_C, FN_HTX2_C, FN_SCIFB0_TXD_C, FN_SCIFB2_TXD_C, 168 169 /* IPSR4 */ 170 FN_SSI_SDATA0, FN_I2C0_SCL_B, FN_IIC0_SCL_B, FN_MSIOF2_SCK_C, 171 FN_SSI_SCK1, FN_I2C0_SDA_B, FN_IIC0_SDA_B, FN_MSIOF2_SYNC_C, 172 FN_GLO_I0_D, 173 FN_SSI_WS1, FN_I2C1_SCL_B, FN_IIC1_SCL_B, FN_MSIOF2_TXD_C, FN_GLO_I1_D, 174 FN_SSI_SDATA1, FN_I2C1_SDA_B, FN_IIC1_SDA_B, FN_MSIOF2_RXD_C, 175 FN_SSI_SCK2, FN_I2C2_SCL, FN_GPS_CLK_B, FN_GLO_Q0_D, FN_HSCK1_E, 176 FN_SSI_WS2, FN_I2C2_SDA, FN_GPS_SIGN_B, FN_RX2_E, 177 FN_GLO_Q1_D, FN_HCTS1_N_E, 178 FN_SSI_SDATA2, FN_GPS_MAG_B, FN_TX2_E, FN_HRTS1_N_E, 179 FN_SSI_SCK34, FN_SSI_WS34, FN_SSI_SDATA3, 180 FN_SSI_SCK4, FN_GLO_SS_D, 181 FN_SSI_WS4, FN_GLO_RFON_D, 182 FN_SSI_SDATA4, FN_MSIOF2_SCK_D, 183 FN_SSI_SCK5, FN_MSIOF1_SCK_C, FN_TS_SDATA0, FN_GLO_I0, 184 FN_MSIOF2_SYNC_D, FN_VI1_R2_B, 185 186 /* IPSR5 */ 187 FN_SSI_WS5, FN_MSIOF1_SYNC_C, FN_TS_SCK0, FN_GLO_I1, 188 FN_MSIOF2_TXD_D, FN_VI1_R3_B, 189 FN_SSI_SDATA5, FN_MSIOF1_TXD_C, FN_TS_SDEN0, FN_GLO_Q0, 190 FN_MSIOF2_SS1_D, FN_VI1_R4_B, 191 FN_SSI_SCK6, FN_MSIOF1_RXD_C, FN_TS_SPSYNC0, FN_GLO_Q1, 192 FN_MSIOF2_RXD_D, FN_VI1_R5_B, 193 FN_SSI_WS6, FN_GLO_SCLK, FN_MSIOF2_SS2_D, FN_VI1_R6_B, 194 FN_SSI_SDATA6, FN_STP_IVCXO27_0_B, FN_GLO_SDATA, FN_VI1_R7_B, 195 FN_SSI_SCK78, FN_STP_ISCLK_0_B, FN_GLO_SS, 196 FN_SSI_WS78, FN_TX0_D, FN_STP_ISD_0_B, FN_GLO_RFON, 197 FN_SSI_SDATA7, FN_RX0_D, FN_STP_ISEN_0_B, 198 FN_SSI_SDATA8, FN_TX1_D, FN_STP_ISSYNC_0_B, 199 FN_SSI_SCK9, FN_RX1_D, FN_GLO_SCLK_D, 200 FN_SSI_WS9, FN_TX3_D, FN_CAN0_TX_D, FN_GLO_SDATA_D, 201 FN_SSI_SDATA9, FN_RX3_D, FN_CAN0_RX_D, 202 203 /* IPSR6 */ 204 FN_AUDIO_CLKB, FN_STP_OPWM_0_B, FN_MSIOF1_SCK_B, 205 FN_SCIF_CLK, FN_DVC_MUTE, FN_BPFCLK_E, 206 FN_AUDIO_CLKC, FN_SCIFB0_SCK_C, FN_MSIOF1_SYNC_B, FN_RX2, 207 FN_SCIFA2_RXD, FN_FMIN_E, 208 FN_AUDIO_CLKOUT, FN_MSIOF1_SS1_B, FN_TX2, FN_SCIFA2_TXD, 209 FN_IRQ0, FN_SCIFB1_RXD_D, FN_INTC_IRQ0_N, 210 FN_IRQ1, FN_SCIFB1_SCK_C, FN_INTC_IRQ1_N, 211 FN_IRQ2, FN_SCIFB1_TXD_D, FN_INTC_IRQ2_N, 212 FN_IRQ3, FN_I2C4_SCL_C, FN_MSIOF2_TXD_E, FN_INTC_IRQ3_N, 213 FN_IRQ4, FN_HRX1_C, FN_I2C4_SDA_C, FN_MSIOF2_RXD_E, FN_INTC_IRQ4_N, 214 FN_IRQ5, FN_HTX1_C, FN_I2C1_SCL_E, FN_MSIOF2_SCK_E, 215 FN_IRQ6, FN_HSCK1_C, FN_MSIOF1_SS2_B, FN_I2C1_SDA_E, FN_MSIOF2_SYNC_E, 216 FN_IRQ7, FN_HCTS1_N_C, FN_MSIOF1_TXD_B, FN_GPS_CLK_C, FN_GPS_CLK_D, 217 FN_IRQ8, FN_HRTS1_N_C, FN_MSIOF1_RXD_B, FN_GPS_SIGN_C, FN_GPS_SIGN_D, 218 219 /* IPSR7 */ 220 FN_IRQ9, FN_DU1_DOTCLKIN_B, FN_CAN_CLK_D, FN_GPS_MAG_C, 221 FN_SCIF_CLK_B, FN_GPS_MAG_D, 222 FN_DU1_DR0, FN_LCDOUT0, FN_VI1_DATA0_B, FN_TX0_B, 223 FN_SCIFA0_TXD_B, FN_MSIOF2_SCK_B, 224 FN_DU1_DR1, FN_LCDOUT1, FN_VI1_DATA1_B, FN_RX0_B, 225 FN_SCIFA0_RXD_B, FN_MSIOF2_SYNC_B, 226 FN_DU1_DR2, FN_LCDOUT2, FN_SSI_SCK0129_B, 227 FN_DU1_DR3, FN_LCDOUT3, FN_SSI_WS0129_B, 228 FN_DU1_DR4, FN_LCDOUT4, FN_SSI_SDATA0_B, 229 FN_DU1_DR5, FN_LCDOUT5, FN_SSI_SCK1_B, 230 FN_DU1_DR6, FN_LCDOUT6, FN_SSI_WS1_B, 231 FN_DU1_DR7, FN_LCDOUT7, FN_SSI_SDATA1_B, 232 FN_DU1_DG0, FN_LCDOUT8, FN_VI1_DATA2_B, FN_TX1_B, 233 FN_SCIFA1_TXD_B, FN_MSIOF2_SS1_B, 234 FN_DU1_DG1, FN_LCDOUT9, FN_VI1_DATA3_B, FN_RX1_B, 235 FN_SCIFA1_RXD_B, FN_MSIOF2_SS2_B, 236 FN_DU1_DG2, FN_LCDOUT10, FN_VI1_DATA4_B, FN_SCIF1_SCK_B, 237 FN_SCIFA1_SCK, FN_SSI_SCK78_B, 238 239 /* IPSR8 */ 240 FN_DU1_DG3, FN_LCDOUT11, FN_VI1_DATA5_B, FN_SSI_WS78_B, 241 FN_DU1_DG4, FN_LCDOUT12, FN_VI1_DATA6_B, FN_HRX0_B, 242 FN_SCIFB2_RXD_B, FN_SSI_SDATA7_B, 243 FN_DU1_DG5, FN_LCDOUT13, FN_VI1_DATA7_B, FN_HCTS0_N_B, 244 FN_SCIFB2_TXD_B, FN_SSI_SDATA8_B, 245 FN_DU1_DG6, FN_LCDOUT14, FN_HRTS0_N_B, 246 FN_SCIFB2_CTS_N_B, FN_SSI_SCK9_B, 247 FN_DU1_DG7, FN_LCDOUT15, FN_HTX0_B, FN_SCIFB2_RTS_N_B, FN_SSI_WS9_B, 248 FN_DU1_DB0, FN_LCDOUT16, FN_VI1_CLK_B, FN_TX2_B, 249 FN_SCIFA2_TXD_B, FN_MSIOF2_TXD_B, 250 FN_DU1_DB1, FN_LCDOUT17, FN_VI1_HSYNC_N_B, FN_RX2_B, 251 FN_SCIFA2_RXD_B, FN_MSIOF2_RXD_B, 252 FN_DU1_DB2, FN_LCDOUT18, FN_VI1_VSYNC_N_B, FN_SCIF2_SCK_B, 253 FN_SCIFA2_SCK, FN_SSI_SDATA9_B, 254 FN_DU1_DB3, FN_LCDOUT19, FN_VI1_CLKENB_B, 255 FN_DU1_DB4, FN_LCDOUT20, FN_VI1_FIELD_B, FN_CAN1_RX, 256 FN_DU1_DB5, FN_LCDOUT21, FN_TX3, FN_SCIFA3_TXD, FN_CAN1_TX, 257 258 /* IPSR9 */ 259 FN_DU1_DB6, FN_LCDOUT22, FN_I2C3_SCL_C, FN_RX3, FN_SCIFA3_RXD, 260 FN_DU1_DB7, FN_LCDOUT23, FN_I2C3_SDA_C, FN_SCIF3_SCK, FN_SCIFA3_SCK, 261 FN_DU1_DOTCLKIN, FN_QSTVA_QVS, 262 FN_DU1_DOTCLKOUT0, FN_QCLK, 263 FN_DU1_DOTCLKOUT1, FN_QSTVB_QVE, FN_CAN0_TX, 264 FN_TX3_B, FN_I2C2_SCL_B, FN_PWM4, 265 FN_DU1_EXHSYNC_DU1_HSYNC, FN_QSTH_QHS, 266 FN_DU1_EXVSYNC_DU1_VSYNC, FN_QSTB_QHE, 267 FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_QCPV_QDE, 268 FN_CAN0_RX, FN_RX3_B, FN_I2C2_SDA_B, 269 FN_DU1_DISP, FN_QPOLA, 270 FN_DU1_CDE, FN_QPOLB, FN_PWM4_B, 271 FN_VI0_CLKENB, FN_TX4, FN_SCIFA4_TXD, FN_TS_SDATA0_D, 272 FN_VI0_FIELD, FN_RX4, FN_SCIFA4_RXD, FN_TS_SCK0_D, 273 FN_VI0_HSYNC_N, FN_TX5, FN_SCIFA5_TXD, FN_TS_SDEN0_D, 274 FN_VI0_VSYNC_N, FN_RX5, FN_SCIFA5_RXD, FN_TS_SPSYNC0_D, 275 FN_VI0_DATA3_VI0_B3, FN_SCIF3_SCK_B, FN_SCIFA3_SCK_B, 276 FN_VI0_G0, FN_IIC1_SCL, FN_STP_IVCXO27_0_C, FN_I2C4_SCL, 277 FN_HCTS2_N, FN_SCIFB2_CTS_N, FN_ATAWR1_N, 278 279 /* IPSR10 */ 280 FN_VI0_G1, FN_IIC1_SDA, FN_STP_ISCLK_0_C, FN_I2C4_SDA, 281 FN_HRTS2_N, FN_SCIFB2_RTS_N, FN_ATADIR1_N, 282 FN_VI0_G2, FN_VI2_HSYNC_N, FN_STP_ISD_0_C, FN_I2C3_SCL_B, 283 FN_HSCK2, FN_SCIFB2_SCK, FN_ATARD1_N, 284 FN_VI0_G3, FN_VI2_VSYNC_N, FN_STP_ISEN_0_C, FN_I2C3_SDA_B, 285 FN_HRX2, FN_SCIFB2_RXD, FN_ATACS01_N, 286 FN_VI0_G4, FN_VI2_CLKENB, FN_STP_ISSYNC_0_C, 287 FN_HTX2, FN_SCIFB2_TXD, FN_SCIFB0_SCK_D, 288 FN_VI0_G5, FN_VI2_FIELD, FN_STP_OPWM_0_C, FN_FMCLK_D, 289 FN_CAN0_TX_E, FN_HTX1_D, FN_SCIFB0_TXD_D, 290 FN_VI0_G6, FN_VI2_CLK, FN_BPFCLK_D, 291 FN_VI0_G7, FN_VI2_DATA0, FN_FMIN_D, 292 FN_VI0_R0, FN_VI2_DATA1, FN_GLO_I0_B, 293 FN_TS_SDATA0_C, FN_ATACS11_N, 294 FN_VI0_R1, FN_VI2_DATA2, FN_GLO_I1_B, 295 FN_TS_SCK0_C, FN_ATAG1_N, 296 FN_VI0_R2, FN_VI2_DATA3, FN_GLO_Q0_B, FN_TS_SDEN0_C, 297 FN_VI0_R3, FN_VI2_DATA4, FN_GLO_Q1_B, FN_TS_SPSYNC0_C, 298 FN_VI0_R4, FN_VI2_DATA5, FN_GLO_SCLK_B, FN_TX0_C, FN_I2C1_SCL_D, 299 300 /* IPSR11 */ 301 FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C, FN_I2C1_SDA_D, 302 FN_VI0_R6, FN_VI2_DATA7, FN_GLO_SS_B, FN_TX1_C, FN_I2C4_SCL_B, 303 FN_VI0_R7, FN_GLO_RFON_B, FN_RX1_C, FN_CAN0_RX_E, 304 FN_I2C4_SDA_B, FN_HRX1_D, FN_SCIFB0_RXD_D, 305 FN_VI1_HSYNC_N, FN_AVB_RXD0, FN_TS_SDATA0_B, FN_TX4_B, FN_SCIFA4_TXD_B, 306 FN_VI1_VSYNC_N, FN_AVB_RXD1, FN_TS_SCK0_B, FN_RX4_B, FN_SCIFA4_RXD_B, 307 FN_VI1_CLKENB, FN_AVB_RXD2, FN_TS_SDEN0_B, 308 FN_VI1_FIELD, FN_AVB_RXD3, FN_TS_SPSYNC0_B, 309 FN_VI1_CLK, FN_AVB_RXD4, FN_VI1_DATA0, FN_AVB_RXD5, 310 FN_VI1_DATA1, FN_AVB_RXD6, FN_VI1_DATA2, FN_AVB_RXD7, 311 FN_VI1_DATA3, FN_AVB_RX_ER, FN_VI1_DATA4, FN_AVB_MDIO, 312 FN_VI1_DATA5, FN_AVB_RX_DV, FN_VI1_DATA6, FN_AVB_MAGIC, 313 FN_VI1_DATA7, FN_AVB_MDC, 314 FN_ETH_MDIO, FN_AVB_RX_CLK, FN_I2C2_SCL_C, 315 FN_ETH_CRS_DV, FN_AVB_LINK, FN_I2C2_SDA_C, 316 317 /* IPSR12 */ 318 FN_ETH_RX_ER, FN_AVB_CRS, FN_I2C3_SCL, FN_IIC0_SCL, 319 FN_ETH_RXD0, FN_AVB_PHY_INT, FN_I2C3_SDA, FN_IIC0_SDA, 320 FN_ETH_RXD1, FN_AVB_GTXREFCLK, FN_CAN0_TX_C, 321 FN_I2C2_SCL_D, FN_MSIOF1_RXD_E, 322 FN_ETH_LINK, FN_AVB_TXD0, FN_CAN0_RX_C, FN_I2C2_SDA_D, FN_MSIOF1_SCK_E, 323 FN_ETH_REFCLK, FN_AVB_TXD1, FN_SCIFA3_RXD_B, 324 FN_CAN1_RX_C, FN_MSIOF1_SYNC_E, 325 FN_ETH_TXD1, FN_AVB_TXD2, FN_SCIFA3_TXD_B, 326 FN_CAN1_TX_C, FN_MSIOF1_TXD_E, 327 FN_ETH_TX_EN, FN_AVB_TXD3, FN_TCLK1_B, FN_CAN_CLK_B, 328 FN_ETH_MAGIC, FN_AVB_TXD4, FN_IETX_C, 329 FN_ETH_TXD0, FN_AVB_TXD5, FN_IECLK_C, 330 FN_ETH_MDC, FN_AVB_TXD6, FN_IERX_C, 331 FN_STP_IVCXO27_0, FN_AVB_TXD7, FN_SCIFB2_TXD_D, 332 FN_ADIDATA_B, FN_MSIOF0_SYNC_C, 333 FN_STP_ISCLK_0, FN_AVB_TX_EN, FN_SCIFB2_RXD_D, 334 FN_ADICS_SAMP_B, FN_MSIOF0_SCK_C, 335 336 /* IPSR13 */ 337 FN_STP_ISD_0, FN_AVB_TX_ER, FN_SCIFB2_SCK_C, 338 FN_ADICLK_B, FN_MSIOF0_SS1_C, 339 FN_STP_ISEN_0, FN_AVB_TX_CLK, FN_ADICHS0_B, FN_MSIOF0_SS2_C, 340 FN_STP_ISSYNC_0, FN_AVB_COL, FN_ADICHS1_B, FN_MSIOF0_RXD_C, 341 FN_STP_OPWM_0, FN_AVB_GTX_CLK, FN_PWM0_B, 342 FN_ADICHS2_B, FN_MSIOF0_TXD_C, 343 FN_SD0_CLK, FN_SPCLK_B, FN_SD0_CMD, FN_MOSI_IO0_B, 344 FN_SD0_DATA0, FN_MISO_IO1_B, FN_SD0_DATA1, FN_IO2_B, 345 FN_SD0_DATA2, FN_IO3_B, FN_SD0_DATA3, FN_SSL_B, 346 FN_SD0_CD, FN_MMC_D6_B, FN_SIM0_RST_B, FN_CAN0_RX_F, 347 FN_SCIFA5_TXD_B, FN_TX3_C, 348 FN_SD0_WP, FN_MMC_D7_B, FN_SIM0_D_B, FN_CAN0_TX_F, 349 FN_SCIFA5_RXD_B, FN_RX3_C, 350 FN_SD1_CMD, FN_REMOCON_B, FN_SD1_DATA0, FN_SPEEDIN_B, 351 FN_SD1_DATA1, FN_IETX_B, FN_SD1_DATA2, FN_IECLK_B, 352 FN_SD1_DATA3, FN_IERX_B, 353 FN_SD1_CD, FN_PWM0, FN_TPU_TO0, FN_I2C1_SCL_C, 354 355 /* IPSR14 */ 356 FN_SD1_WP, FN_PWM1_B, FN_I2C1_SDA_C, 357 FN_SD2_CLK, FN_MMC_CLK, FN_SD2_CMD, FN_MMC_CMD, 358 FN_SD2_DATA0, FN_MMC_D0, FN_SD2_DATA1, FN_MMC_D1, 359 FN_SD2_DATA2, FN_MMC_D2, FN_SD2_DATA3, FN_MMC_D3, 360 FN_SD2_CD, FN_MMC_D4, FN_IIC1_SCL_C, FN_TX5_B, FN_SCIFA5_TXD_C, 361 FN_SD2_WP, FN_MMC_D5, FN_IIC1_SDA_C, FN_RX5_B, FN_SCIFA5_RXD_C, 362 FN_MSIOF0_SCK, FN_RX2_C, FN_ADIDATA, FN_VI1_CLK_C, FN_VI1_G0_B, 363 FN_MSIOF0_SYNC, FN_TX2_C, FN_ADICS_SAMP, FN_VI1_CLKENB_C, FN_VI1_G1_B, 364 FN_MSIOF0_TXD, FN_ADICLK, FN_VI1_FIELD_C, FN_VI1_G2_B, 365 FN_MSIOF0_RXD, FN_ADICHS0, FN_VI1_DATA0_C, FN_VI1_G3_B, 366 FN_MSIOF0_SS1, FN_MMC_D6, FN_ADICHS1, FN_TX0_E, 367 FN_VI1_HSYNC_N_C, FN_IIC0_SCL_C, FN_VI1_G4_B, 368 FN_MSIOF0_SS2, FN_MMC_D7, FN_ADICHS2, FN_RX0_E, 369 FN_VI1_VSYNC_N_C, FN_IIC0_SDA_C, FN_VI1_G5_B, 370 371 /* IPSR15 */ 372 FN_SIM0_RST, FN_IETX, FN_CAN1_TX_D, 373 FN_SIM0_CLK, FN_IECLK, FN_CAN_CLK_C, 374 FN_SIM0_D, FN_IERX, FN_CAN1_RX_D, 375 FN_GPS_CLK, FN_DU1_DOTCLKIN_C, FN_AUDIO_CLKB_B, 376 FN_PWM5_B, FN_SCIFA3_TXD_C, 377 FN_GPS_SIGN, FN_TX4_C, FN_SCIFA4_TXD_C, FN_PWM5, 378 FN_VI1_G6_B, FN_SCIFA3_RXD_C, 379 FN_GPS_MAG, FN_RX4_C, FN_SCIFA4_RXD_C, FN_PWM6, 380 FN_VI1_G7_B, FN_SCIFA3_SCK_C, 381 FN_HCTS0_N, FN_SCIFB0_CTS_N, FN_GLO_I0_C, FN_TCLK1, FN_VI1_DATA1_C, 382 FN_HRTS0_N, FN_SCIFB0_RTS_N, FN_GLO_I1_C, FN_VI1_DATA2_C, 383 FN_HSCK0, FN_SCIFB0_SCK, FN_GLO_Q0_C, FN_CAN_CLK, 384 FN_TCLK2, FN_VI1_DATA3_C, 385 FN_HRX0, FN_SCIFB0_RXD, FN_GLO_Q1_C, FN_CAN0_RX_B, FN_VI1_DATA4_C, 386 FN_HTX0, FN_SCIFB0_TXD, FN_GLO_SCLK_C, FN_CAN0_TX_B, FN_VI1_DATA5_C, 387 388 /* IPSR16 */ 389 FN_HRX1, FN_SCIFB1_RXD, FN_VI1_R0_B, FN_GLO_SDATA_C, FN_VI1_DATA6_C, 390 FN_HTX1, FN_SCIFB1_TXD, FN_VI1_R1_B, FN_GLO_SS_C, FN_VI1_DATA7_C, 391 FN_HSCK1, FN_SCIFB1_SCK, FN_MLB_CLK, FN_GLO_RFON_C, 392 FN_HCTS1_N, FN_SCIFB1_CTS_N, FN_MLB_SIG, FN_CAN1_TX_B, 393 FN_HRTS1_N, FN_SCIFB1_RTS_N, FN_MLB_DAT, FN_CAN1_RX_B, 394 395 /* MOD_SEL */ 396 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3, 397 FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, FN_SEL_SCIFB_3, 398 FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, FN_SEL_SCIFB2_3, 399 FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3, 400 FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, 401 FN_SEL_SSI9_0, FN_SEL_SSI9_1, 402 FN_SEL_SCFA_0, FN_SEL_SCFA_1, 403 FN_SEL_QSP_0, FN_SEL_QSP_1, 404 FN_SEL_SSI7_0, FN_SEL_SSI7_1, 405 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2, FN_SEL_HSCIF1_3, 406 FN_SEL_HSCIF1_4, 407 FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2, 408 FN_SEL_TMU1_0, FN_SEL_TMU1_1, 409 FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_LBS_2, FN_SEL_LBS_3, 410 FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, 411 FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2, 412 413 /* MOD_SEL2 */ 414 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3, 415 FN_SEL_SCIF0_4, 416 FN_SEL_SCIF_0, FN_SEL_SCIF_1, 417 FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3, 418 FN_SEL_CAN0_4, FN_SEL_CAN0_5, 419 FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3, 420 FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, 421 FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, 422 FN_SEL_ADG_0, FN_SEL_ADG_1, 423 FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3, FN_SEL_FM_4, 424 FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, 425 FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3, 426 FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2, 427 FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2, 428 FN_SEL_SIM_0, FN_SEL_SIM_1, 429 FN_SEL_SSI8_0, FN_SEL_SSI8_1, 430 431 /* MOD_SEL3 */ 432 FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1, FN_SEL_HSCIF2_2, FN_SEL_HSCIF2_3, 433 FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2, FN_SEL_CANCLK_3, 434 FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, 435 FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, 436 FN_SEL_I2C4_0, FN_SEL_I2C4_1, FN_SEL_I2C4_2, 437 FN_SEL_I2C3_0, FN_SEL_I2C3_1, FN_SEL_I2C3_2, FN_SEL_I2C3_3, 438 FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3, 439 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 440 FN_SEL_MMC_0, FN_SEL_MMC_1, 441 FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, 442 FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3, 443 FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, FN_SEL_I2C1_3, 444 FN_SEL_I2C1_4, 445 FN_SEL_I2C0_0, FN_SEL_I2C0_1, FN_SEL_I2C0_2, 446 447 /* MOD_SEL4 */ 448 FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3, 449 FN_SEL_SOF1_4, 450 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, 451 FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2, 452 FN_SEL_RAD_0, FN_SEL_RAD_1, 453 FN_SEL_RCN_0, FN_SEL_RCN_1, 454 FN_SEL_RSP_0, FN_SEL_RSP_1, 455 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF2_3, 456 FN_SEL_SCIF2_4, 457 FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2, FN_SEL_SOF2_3, 458 FN_SEL_SOF2_4, 459 FN_SEL_SSI1_0, FN_SEL_SSI1_1, 460 FN_SEL_SSI0_0, FN_SEL_SSI0_1, 461 FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2, 462 PINMUX_FUNCTION_END, 463 464 PINMUX_MARK_BEGIN, 465 466 EX_CS0_N_MARK, RD_N_MARK, 467 468 AUDIO_CLKA_MARK, 469 470 VI0_CLK_MARK, VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK, 471 VI0_DATA2_VI0_B2_MARK, VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK, 472 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK, 473 474 SD1_CLK_MARK, 475 476 USB0_PWEN_MARK, USB0_OVC_MARK, USB1_PWEN_MARK, USB1_OVC_MARK, 477 DU0_DOTCLKIN_MARK, 478 479 /* IPSR0 */ 480 D0_MARK, D1_MARK, D2_MARK, D3_MARK, D4_MARK, D5_MARK, 481 D6_MARK, D7_MARK, D8_MARK, 482 D9_MARK, D10_MARK, D11_MARK, D12_MARK, D13_MARK, D14_MARK, D15_MARK, 483 A0_MARK, ATAWR0_N_C_MARK, MSIOF0_SCK_B_MARK, I2C0_SCL_C_MARK, 484 PWM2_B_MARK, 485 A1_MARK, MSIOF0_SYNC_B_MARK, A2_MARK, MSIOF0_SS1_B_MARK, 486 A3_MARK, MSIOF0_SS2_B_MARK, A4_MARK, MSIOF0_TXD_B_MARK, 487 A5_MARK, MSIOF0_RXD_B_MARK, A6_MARK, MSIOF1_SCK_MARK, 488 489 /* IPSR1 */ 490 A7_MARK, MSIOF1_SYNC_MARK, A8_MARK, MSIOF1_SS1_MARK, I2C0_SCL_MARK, 491 A9_MARK, MSIOF1_SS2_MARK, I2C0_SDA_MARK, 492 A10_MARK, MSIOF1_TXD_MARK, MSIOF1_TXD_D_MARK, 493 A11_MARK, MSIOF1_RXD_MARK, I2C3_SCL_D_MARK, MSIOF1_RXD_D_MARK, 494 A12_MARK, FMCLK_MARK, I2C3_SDA_D_MARK, MSIOF1_SCK_D_MARK, 495 A13_MARK, ATAG0_N_C_MARK, BPFCLK_MARK, MSIOF1_SS1_D_MARK, 496 A14_MARK, ATADIR0_N_C_MARK, FMIN_MARK, FMIN_C_MARK, MSIOF1_SYNC_D_MARK, 497 A15_MARK, BPFCLK_C_MARK, 498 A16_MARK, DREQ2_B_MARK, FMCLK_C_MARK, SCIFA1_SCK_B_MARK, 499 A17_MARK, DACK2_B_MARK, I2C0_SDA_C_MARK, 500 A18_MARK, DREQ1_MARK, SCIFA1_RXD_C_MARK, SCIFB1_RXD_C_MARK, 501 502 /* IPSR2 */ 503 A19_MARK, DACK1_MARK, SCIFA1_TXD_C_MARK, 504 SCIFB1_TXD_C_MARK, SCIFB1_SCK_B_MARK, 505 A20_MARK, SPCLK_MARK, 506 A21_MARK, ATAWR0_N_B_MARK, MOSI_IO0_MARK, 507 A22_MARK, MISO_IO1_MARK, FMCLK_B_MARK, TX0_MARK, SCIFA0_TXD_MARK, 508 A23_MARK, IO2_MARK, BPFCLK_B_MARK, RX0_MARK, SCIFA0_RXD_MARK, 509 A24_MARK, DREQ2_MARK, IO3_MARK, TX1_MARK, SCIFA1_TXD_MARK, 510 A25_MARK, DACK2_MARK, SSL_MARK, DREQ1_C_MARK, 511 RX1_MARK, SCIFA1_RXD_MARK, 512 CS0_N_MARK, ATAG0_N_B_MARK, I2C1_SCL_MARK, 513 CS1_N_A26_MARK, ATADIR0_N_B_MARK, I2C1_SDA_MARK, 514 EX_CS1_N_MARK, MSIOF2_SCK_MARK, 515 EX_CS2_N_MARK, ATAWR0_N_MARK, MSIOF2_SYNC_MARK, 516 EX_CS3_N_MARK, ATADIR0_N_MARK, MSIOF2_TXD_MARK, 517 ATAG0_N_MARK, EX_WAIT1_MARK, 518 519 /* IPSR3 */ 520 EX_CS4_N_MARK, ATARD0_N_MARK, MSIOF2_RXD_MARK, EX_WAIT2_MARK, 521 EX_CS5_N_MARK, ATACS00_N_MARK, MSIOF2_SS1_MARK, HRX1_B_MARK, 522 SCIFB1_RXD_B_MARK, PWM1_MARK, TPU_TO1_MARK, 523 BS_N_MARK, ATACS10_N_MARK, MSIOF2_SS2_MARK, HTX1_B_MARK, 524 SCIFB1_TXD_B_MARK, PWM2_MARK, TPU_TO2_MARK, 525 RD_WR_N_MARK, HRX2_B_MARK, FMIN_B_MARK, 526 SCIFB0_RXD_B_MARK, DREQ1_D_MARK, 527 WE0_N_MARK, HCTS2_N_B_MARK, SCIFB0_TXD_B_MARK, 528 WE1_N_MARK, ATARD0_N_B_MARK, HTX2_B_MARK, SCIFB0_RTS_N_B_MARK, 529 EX_WAIT0_MARK, HRTS2_N_B_MARK, SCIFB0_CTS_N_B_MARK, 530 DREQ0_MARK, PWM3_MARK, TPU_TO3_MARK, 531 DACK0_MARK, DRACK0_MARK, REMOCON_MARK, 532 SPEEDIN_MARK, HSCK0_C_MARK, HSCK2_C_MARK, SCIFB0_SCK_B_MARK, 533 SCIFB2_SCK_B_MARK, DREQ2_C_MARK, HTX2_D_MARK, 534 SSI_SCK0129_MARK, HRX0_C_MARK, HRX2_C_MARK, 535 SCIFB0_RXD_C_MARK, SCIFB2_RXD_C_MARK, 536 SSI_WS0129_MARK, HTX0_C_MARK, HTX2_C_MARK, 537 SCIFB0_TXD_C_MARK, SCIFB2_TXD_C_MARK, 538 539 /* IPSR4 */ 540 SSI_SDATA0_MARK, I2C0_SCL_B_MARK, IIC0_SCL_B_MARK, MSIOF2_SCK_C_MARK, 541 SSI_SCK1_MARK, I2C0_SDA_B_MARK, IIC0_SDA_B_MARK, 542 MSIOF2_SYNC_C_MARK, GLO_I0_D_MARK, 543 SSI_WS1_MARK, I2C1_SCL_B_MARK, IIC1_SCL_B_MARK, 544 MSIOF2_TXD_C_MARK, GLO_I1_D_MARK, 545 SSI_SDATA1_MARK, I2C1_SDA_B_MARK, IIC1_SDA_B_MARK, MSIOF2_RXD_C_MARK, 546 SSI_SCK2_MARK, I2C2_SCL_MARK, GPS_CLK_B_MARK, GLO_Q0_D_MARK, 547 HSCK1_E_MARK, 548 SSI_WS2_MARK, I2C2_SDA_MARK, GPS_SIGN_B_MARK, RX2_E_MARK, 549 GLO_Q1_D_MARK, HCTS1_N_E_MARK, 550 SSI_SDATA2_MARK, GPS_MAG_B_MARK, TX2_E_MARK, HRTS1_N_E_MARK, 551 SSI_SCK34_MARK, SSI_WS34_MARK, SSI_SDATA3_MARK, 552 SSI_SCK4_MARK, GLO_SS_D_MARK, 553 SSI_WS4_MARK, GLO_RFON_D_MARK, 554 SSI_SDATA4_MARK, MSIOF2_SCK_D_MARK, 555 SSI_SCK5_MARK, MSIOF1_SCK_C_MARK, TS_SDATA0_MARK, GLO_I0_MARK, 556 MSIOF2_SYNC_D_MARK, VI1_R2_B_MARK, 557 558 /* IPSR5 */ 559 SSI_WS5_MARK, MSIOF1_SYNC_C_MARK, TS_SCK0_MARK, GLO_I1_MARK, 560 MSIOF2_TXD_D_MARK, VI1_R3_B_MARK, 561 SSI_SDATA5_MARK, MSIOF1_TXD_C_MARK, TS_SDEN0_MARK, GLO_Q0_MARK, 562 MSIOF2_SS1_D_MARK, VI1_R4_B_MARK, 563 SSI_SCK6_MARK, MSIOF1_RXD_C_MARK, TS_SPSYNC0_MARK, GLO_Q1_MARK, 564 MSIOF2_RXD_D_MARK, VI1_R5_B_MARK, 565 SSI_WS6_MARK, GLO_SCLK_MARK, MSIOF2_SS2_D_MARK, VI1_R6_B_MARK, 566 SSI_SDATA6_MARK, STP_IVCXO27_0_B_MARK, GLO_SDATA_MARK, VI1_R7_B_MARK, 567 SSI_SCK78_MARK, STP_ISCLK_0_B_MARK, GLO_SS_MARK, 568 SSI_WS78_MARK, TX0_D_MARK, STP_ISD_0_B_MARK, GLO_RFON_MARK, 569 SSI_SDATA7_MARK, RX0_D_MARK, STP_ISEN_0_B_MARK, 570 SSI_SDATA8_MARK, TX1_D_MARK, STP_ISSYNC_0_B_MARK, 571 SSI_SCK9_MARK, RX1_D_MARK, GLO_SCLK_D_MARK, 572 SSI_WS9_MARK, TX3_D_MARK, CAN0_TX_D_MARK, GLO_SDATA_D_MARK, 573 SSI_SDATA9_MARK, RX3_D_MARK, CAN0_RX_D_MARK, 574 575 /* IPSR6 */ 576 AUDIO_CLKB_MARK, STP_OPWM_0_B_MARK, MSIOF1_SCK_B_MARK, 577 SCIF_CLK_MARK, DVC_MUTE_MARK, BPFCLK_E_MARK, 578 AUDIO_CLKC_MARK, SCIFB0_SCK_C_MARK, MSIOF1_SYNC_B_MARK, RX2_MARK, 579 SCIFA2_RXD_MARK, FMIN_E_MARK, 580 AUDIO_CLKOUT_MARK, MSIOF1_SS1_B_MARK, TX2_MARK, SCIFA2_TXD_MARK, 581 IRQ0_MARK, SCIFB1_RXD_D_MARK, INTC_IRQ0_N_MARK, 582 IRQ1_MARK, SCIFB1_SCK_C_MARK, INTC_IRQ1_N_MARK, 583 IRQ2_MARK, SCIFB1_TXD_D_MARK, INTC_IRQ2_N_MARK, 584 IRQ3_MARK, I2C4_SCL_C_MARK, MSIOF2_TXD_E_MARK, INTC_IRQ3_N_MARK, 585 IRQ4_MARK, HRX1_C_MARK, I2C4_SDA_C_MARK, 586 MSIOF2_RXD_E_MARK, INTC_IRQ4_N_MARK, 587 IRQ5_MARK, HTX1_C_MARK, I2C1_SCL_E_MARK, MSIOF2_SCK_E_MARK, 588 IRQ6_MARK, HSCK1_C_MARK, MSIOF1_SS2_B_MARK, 589 I2C1_SDA_E_MARK, MSIOF2_SYNC_E_MARK, 590 IRQ7_MARK, HCTS1_N_C_MARK, MSIOF1_TXD_B_MARK, 591 GPS_CLK_C_MARK, GPS_CLK_D_MARK, 592 IRQ8_MARK, HRTS1_N_C_MARK, MSIOF1_RXD_B_MARK, 593 GPS_SIGN_C_MARK, GPS_SIGN_D_MARK, 594 595 /* IPSR7 */ 596 IRQ9_MARK, DU1_DOTCLKIN_B_MARK, CAN_CLK_D_MARK, GPS_MAG_C_MARK, 597 SCIF_CLK_B_MARK, GPS_MAG_D_MARK, 598 DU1_DR0_MARK, LCDOUT0_MARK, VI1_DATA0_B_MARK, TX0_B_MARK, 599 SCIFA0_TXD_B_MARK, MSIOF2_SCK_B_MARK, 600 DU1_DR1_MARK, LCDOUT1_MARK, VI1_DATA1_B_MARK, RX0_B_MARK, 601 SCIFA0_RXD_B_MARK, MSIOF2_SYNC_B_MARK, 602 DU1_DR2_MARK, LCDOUT2_MARK, SSI_SCK0129_B_MARK, 603 DU1_DR3_MARK, LCDOUT3_MARK, SSI_WS0129_B_MARK, 604 DU1_DR4_MARK, LCDOUT4_MARK, SSI_SDATA0_B_MARK, 605 DU1_DR5_MARK, LCDOUT5_MARK, SSI_SCK1_B_MARK, 606 DU1_DR6_MARK, LCDOUT6_MARK, SSI_WS1_B_MARK, 607 DU1_DR7_MARK, LCDOUT7_MARK, SSI_SDATA1_B_MARK, 608 DU1_DG0_MARK, LCDOUT8_MARK, VI1_DATA2_B_MARK, TX1_B_MARK, 609 SCIFA1_TXD_B_MARK, MSIOF2_SS1_B_MARK, 610 DU1_DG1_MARK, LCDOUT9_MARK, VI1_DATA3_B_MARK, RX1_B_MARK, 611 SCIFA1_RXD_B_MARK, MSIOF2_SS2_B_MARK, 612 DU1_DG2_MARK, LCDOUT10_MARK, VI1_DATA4_B_MARK, SCIF1_SCK_B_MARK, 613 SCIFA1_SCK_MARK, SSI_SCK78_B_MARK, 614 615 /* IPSR8 */ 616 DU1_DG3_MARK, LCDOUT11_MARK, VI1_DATA5_B_MARK, SSI_WS78_B_MARK, 617 DU1_DG4_MARK, LCDOUT12_MARK, VI1_DATA6_B_MARK, HRX0_B_MARK, 618 SCIFB2_RXD_B_MARK, SSI_SDATA7_B_MARK, 619 DU1_DG5_MARK, LCDOUT13_MARK, VI1_DATA7_B_MARK, HCTS0_N_B_MARK, 620 SCIFB2_TXD_B_MARK, SSI_SDATA8_B_MARK, 621 DU1_DG6_MARK, LCDOUT14_MARK, HRTS0_N_B_MARK, 622 SCIFB2_CTS_N_B_MARK, SSI_SCK9_B_MARK, 623 DU1_DG7_MARK, LCDOUT15_MARK, HTX0_B_MARK, 624 SCIFB2_RTS_N_B_MARK, SSI_WS9_B_MARK, 625 DU1_DB0_MARK, LCDOUT16_MARK, VI1_CLK_B_MARK, TX2_B_MARK, 626 SCIFA2_TXD_B_MARK, MSIOF2_TXD_B_MARK, 627 DU1_DB1_MARK, LCDOUT17_MARK, VI1_HSYNC_N_B_MARK, RX2_B_MARK, 628 SCIFA2_RXD_B_MARK, MSIOF2_RXD_B_MARK, 629 DU1_DB2_MARK, LCDOUT18_MARK, VI1_VSYNC_N_B_MARK, SCIF2_SCK_B_MARK, 630 SCIFA2_SCK_MARK, SSI_SDATA9_B_MARK, 631 DU1_DB3_MARK, LCDOUT19_MARK, VI1_CLKENB_B_MARK, 632 DU1_DB4_MARK, LCDOUT20_MARK, VI1_FIELD_B_MARK, CAN1_RX_MARK, 633 DU1_DB5_MARK, LCDOUT21_MARK, TX3_MARK, SCIFA3_TXD_MARK, CAN1_TX_MARK, 634 635 /* IPSR9 */ 636 DU1_DB6_MARK, LCDOUT22_MARK, I2C3_SCL_C_MARK, RX3_MARK, SCIFA3_RXD_MARK, 637 DU1_DB7_MARK, LCDOUT23_MARK, I2C3_SDA_C_MARK, 638 SCIF3_SCK_MARK, SCIFA3_SCK_MARK, 639 DU1_DOTCLKIN_MARK, QSTVA_QVS_MARK, 640 DU1_DOTCLKOUT0_MARK, QCLK_MARK, 641 DU1_DOTCLKOUT1_MARK, QSTVB_QVE_MARK, CAN0_TX_MARK, 642 TX3_B_MARK, I2C2_SCL_B_MARK, PWM4_MARK, 643 DU1_EXHSYNC_DU1_HSYNC_MARK, QSTH_QHS_MARK, 644 DU1_EXVSYNC_DU1_VSYNC_MARK, QSTB_QHE_MARK, 645 DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK, 646 CAN0_RX_MARK, RX3_B_MARK, I2C2_SDA_B_MARK, 647 DU1_DISP_MARK, QPOLA_MARK, 648 DU1_CDE_MARK, QPOLB_MARK, PWM4_B_MARK, 649 VI0_CLKENB_MARK, TX4_MARK, SCIFA4_TXD_MARK, TS_SDATA0_D_MARK, 650 VI0_FIELD_MARK, RX4_MARK, SCIFA4_RXD_MARK, TS_SCK0_D_MARK, 651 VI0_HSYNC_N_MARK, TX5_MARK, SCIFA5_TXD_MARK, TS_SDEN0_D_MARK, 652 VI0_VSYNC_N_MARK, RX5_MARK, SCIFA5_RXD_MARK, TS_SPSYNC0_D_MARK, 653 VI0_DATA3_VI0_B3_MARK, SCIF3_SCK_B_MARK, SCIFA3_SCK_B_MARK, 654 VI0_G0_MARK, IIC1_SCL_MARK, STP_IVCXO27_0_C_MARK, I2C4_SCL_MARK, 655 HCTS2_N_MARK, SCIFB2_CTS_N_MARK, ATAWR1_N_MARK, 656 657 /* IPSR10 */ 658 VI0_G1_MARK, IIC1_SDA_MARK, STP_ISCLK_0_C_MARK, I2C4_SDA_MARK, 659 HRTS2_N_MARK, SCIFB2_RTS_N_MARK, ATADIR1_N_MARK, 660 VI0_G2_MARK, VI2_HSYNC_N_MARK, STP_ISD_0_C_MARK, I2C3_SCL_B_MARK, 661 HSCK2_MARK, SCIFB2_SCK_MARK, ATARD1_N_MARK, 662 VI0_G3_MARK, VI2_VSYNC_N_MARK, STP_ISEN_0_C_MARK, I2C3_SDA_B_MARK, 663 HRX2_MARK, SCIFB2_RXD_MARK, ATACS01_N_MARK, 664 VI0_G4_MARK, VI2_CLKENB_MARK, STP_ISSYNC_0_C_MARK, 665 HTX2_MARK, SCIFB2_TXD_MARK, SCIFB0_SCK_D_MARK, 666 VI0_G5_MARK, VI2_FIELD_MARK, STP_OPWM_0_C_MARK, FMCLK_D_MARK, 667 CAN0_TX_E_MARK, HTX1_D_MARK, SCIFB0_TXD_D_MARK, 668 VI0_G6_MARK, VI2_CLK_MARK, BPFCLK_D_MARK, 669 VI0_G7_MARK, VI2_DATA0_MARK, FMIN_D_MARK, 670 VI0_R0_MARK, VI2_DATA1_MARK, GLO_I0_B_MARK, 671 TS_SDATA0_C_MARK, ATACS11_N_MARK, 672 VI0_R1_MARK, VI2_DATA2_MARK, GLO_I1_B_MARK, 673 TS_SCK0_C_MARK, ATAG1_N_MARK, 674 VI0_R2_MARK, VI2_DATA3_MARK, GLO_Q0_B_MARK, TS_SDEN0_C_MARK, 675 VI0_R3_MARK, VI2_DATA4_MARK, GLO_Q1_B_MARK, TS_SPSYNC0_C_MARK, 676 VI0_R4_MARK, VI2_DATA5_MARK, GLO_SCLK_B_MARK, TX0_C_MARK, 677 I2C1_SCL_D_MARK, 678 679 /* IPSR11 */ 680 VI0_R5_MARK, VI2_DATA6_MARK, GLO_SDATA_B_MARK, RX0_C_MARK, 681 I2C1_SDA_D_MARK, 682 VI0_R6_MARK, VI2_DATA7_MARK, GLO_SS_B_MARK, TX1_C_MARK, I2C4_SCL_B_MARK, 683 VI0_R7_MARK, GLO_RFON_B_MARK, RX1_C_MARK, CAN0_RX_E_MARK, 684 I2C4_SDA_B_MARK, HRX1_D_MARK, SCIFB0_RXD_D_MARK, 685 VI1_HSYNC_N_MARK, AVB_RXD0_MARK, TS_SDATA0_B_MARK, 686 TX4_B_MARK, SCIFA4_TXD_B_MARK, 687 VI1_VSYNC_N_MARK, AVB_RXD1_MARK, TS_SCK0_B_MARK, 688 RX4_B_MARK, SCIFA4_RXD_B_MARK, 689 VI1_CLKENB_MARK, AVB_RXD2_MARK, TS_SDEN0_B_MARK, 690 VI1_FIELD_MARK, AVB_RXD3_MARK, TS_SPSYNC0_B_MARK, 691 VI1_CLK_MARK, AVB_RXD4_MARK, VI1_DATA0_MARK, AVB_RXD5_MARK, 692 VI1_DATA1_MARK, AVB_RXD6_MARK, VI1_DATA2_MARK, AVB_RXD7_MARK, 693 VI1_DATA3_MARK, AVB_RX_ER_MARK, VI1_DATA4_MARK, AVB_MDIO_MARK, 694 VI1_DATA5_MARK, AVB_RX_DV_MARK, VI1_DATA6_MARK, AVB_MAGIC_MARK, 695 VI1_DATA7_MARK, AVB_MDC_MARK, 696 ETH_MDIO_MARK, AVB_RX_CLK_MARK, I2C2_SCL_C_MARK, 697 ETH_CRS_DV_MARK, AVB_LINK_MARK, I2C2_SDA_C_MARK, 698 699 /* IPSR12 */ 700 ETH_RX_ER_MARK, AVB_CRS_MARK, I2C3_SCL_MARK, IIC0_SCL_MARK, 701 ETH_RXD0_MARK, AVB_PHY_INT_MARK, I2C3_SDA_MARK, IIC0_SDA_MARK, 702 ETH_RXD1_MARK, AVB_GTXREFCLK_MARK, CAN0_TX_C_MARK, 703 I2C2_SCL_D_MARK, MSIOF1_RXD_E_MARK, 704 ETH_LINK_MARK, AVB_TXD0_MARK, CAN0_RX_C_MARK, 705 I2C2_SDA_D_MARK, MSIOF1_SCK_E_MARK, 706 ETH_REFCLK_MARK, AVB_TXD1_MARK, SCIFA3_RXD_B_MARK, 707 CAN1_RX_C_MARK, MSIOF1_SYNC_E_MARK, 708 ETH_TXD1_MARK, AVB_TXD2_MARK, SCIFA3_TXD_B_MARK, 709 CAN1_TX_C_MARK, MSIOF1_TXD_E_MARK, 710 ETH_TX_EN_MARK, AVB_TXD3_MARK, TCLK1_B_MARK, CAN_CLK_B_MARK, 711 ETH_MAGIC_MARK, AVB_TXD4_MARK, IETX_C_MARK, 712 ETH_TXD0_MARK, AVB_TXD5_MARK, IECLK_C_MARK, 713 ETH_MDC_MARK, AVB_TXD6_MARK, IERX_C_MARK, 714 STP_IVCXO27_0_MARK, AVB_TXD7_MARK, SCIFB2_TXD_D_MARK, 715 ADIDATA_B_MARK, MSIOF0_SYNC_C_MARK, 716 STP_ISCLK_0_MARK, AVB_TX_EN_MARK, SCIFB2_RXD_D_MARK, 717 ADICS_SAMP_B_MARK, MSIOF0_SCK_C_MARK, 718 719 /* IPSR13 */ 720 STP_ISD_0_MARK, AVB_TX_ER_MARK, SCIFB2_SCK_C_MARK, 721 ADICLK_B_MARK, MSIOF0_SS1_C_MARK, 722 STP_ISEN_0_MARK, AVB_TX_CLK_MARK, ADICHS0_B_MARK, MSIOF0_SS2_C_MARK, 723 STP_ISSYNC_0_MARK, AVB_COL_MARK, ADICHS1_B_MARK, MSIOF0_RXD_C_MARK, 724 STP_OPWM_0_MARK, AVB_GTX_CLK_MARK, PWM0_B_MARK, 725 ADICHS2_B_MARK, MSIOF0_TXD_C_MARK, 726 SD0_CLK_MARK, SPCLK_B_MARK, SD0_CMD_MARK, MOSI_IO0_B_MARK, 727 SD0_DATA0_MARK, MISO_IO1_B_MARK, SD0_DATA1_MARK, IO2_B_MARK, 728 SD0_DATA2_MARK, IO3_B_MARK, SD0_DATA3_MARK, SSL_B_MARK, 729 SD0_CD_MARK, MMC_D6_B_MARK, SIM0_RST_B_MARK, CAN0_RX_F_MARK, 730 SCIFA5_TXD_B_MARK, TX3_C_MARK, 731 SD0_WP_MARK, MMC_D7_B_MARK, SIM0_D_B_MARK, CAN0_TX_F_MARK, 732 SCIFA5_RXD_B_MARK, RX3_C_MARK, 733 SD1_CMD_MARK, REMOCON_B_MARK, SD1_DATA0_MARK, SPEEDIN_B_MARK, 734 SD1_DATA1_MARK, IETX_B_MARK, SD1_DATA2_MARK, IECLK_B_MARK, 735 SD1_DATA3_MARK, IERX_B_MARK, 736 SD1_CD_MARK, PWM0_MARK, TPU_TO0_MARK, I2C1_SCL_C_MARK, 737 738 /* IPSR14 */ 739 SD1_WP_MARK, PWM1_B_MARK, I2C1_SDA_C_MARK, 740 SD2_CLK_MARK, MMC_CLK_MARK, SD2_CMD_MARK, MMC_CMD_MARK, 741 SD2_DATA0_MARK, MMC_D0_MARK, SD2_DATA1_MARK, MMC_D1_MARK, 742 SD2_DATA2_MARK, MMC_D2_MARK, SD2_DATA3_MARK, MMC_D3_MARK, 743 SD2_CD_MARK, MMC_D4_MARK, IIC1_SCL_C_MARK, TX5_B_MARK, 744 SCIFA5_TXD_C_MARK, 745 SD2_WP_MARK, MMC_D5_MARK, IIC1_SDA_C_MARK, RX5_B_MARK, 746 SCIFA5_RXD_C_MARK, 747 MSIOF0_SCK_MARK, RX2_C_MARK, ADIDATA_MARK, 748 VI1_CLK_C_MARK, VI1_G0_B_MARK, 749 MSIOF0_SYNC_MARK, TX2_C_MARK, ADICS_SAMP_MARK, 750 VI1_CLKENB_C_MARK, VI1_G1_B_MARK, 751 MSIOF0_TXD_MARK, ADICLK_MARK, VI1_FIELD_C_MARK, VI1_G2_B_MARK, 752 MSIOF0_RXD_MARK, ADICHS0_MARK, VI1_DATA0_C_MARK, VI1_G3_B_MARK, 753 MSIOF0_SS1_MARK, MMC_D6_MARK, ADICHS1_MARK, TX0_E_MARK, 754 VI1_HSYNC_N_C_MARK, IIC0_SCL_C_MARK, VI1_G4_B_MARK, 755 MSIOF0_SS2_MARK, MMC_D7_MARK, ADICHS2_MARK, RX0_E_MARK, 756 VI1_VSYNC_N_C_MARK, IIC0_SDA_C_MARK, VI1_G5_B_MARK, 757 758 /* IPSR15 */ 759 SIM0_RST_MARK, IETX_MARK, CAN1_TX_D_MARK, 760 SIM0_CLK_MARK, IECLK_MARK, CAN_CLK_C_MARK, 761 SIM0_D_MARK, IERX_MARK, CAN1_RX_D_MARK, 762 GPS_CLK_MARK, DU1_DOTCLKIN_C_MARK, AUDIO_CLKB_B_MARK, 763 PWM5_B_MARK, SCIFA3_TXD_C_MARK, 764 GPS_SIGN_MARK, TX4_C_MARK, SCIFA4_TXD_C_MARK, PWM5_MARK, 765 VI1_G6_B_MARK, SCIFA3_RXD_C_MARK, 766 GPS_MAG_MARK, RX4_C_MARK, SCIFA4_RXD_C_MARK, PWM6_MARK, 767 VI1_G7_B_MARK, SCIFA3_SCK_C_MARK, 768 HCTS0_N_MARK, SCIFB0_CTS_N_MARK, GLO_I0_C_MARK, 769 TCLK1_MARK, VI1_DATA1_C_MARK, 770 HRTS0_N_MARK, SCIFB0_RTS_N_MARK, GLO_I1_C_MARK, VI1_DATA2_C_MARK, 771 HSCK0_MARK, SCIFB0_SCK_MARK, GLO_Q0_C_MARK, CAN_CLK_MARK, 772 TCLK2_MARK, VI1_DATA3_C_MARK, 773 HRX0_MARK, SCIFB0_RXD_MARK, GLO_Q1_C_MARK, 774 CAN0_RX_B_MARK, VI1_DATA4_C_MARK, 775 HTX0_MARK, SCIFB0_TXD_MARK, GLO_SCLK_C_MARK, 776 CAN0_TX_B_MARK, VI1_DATA5_C_MARK, 777 778 /* IPSR16 */ 779 HRX1_MARK, SCIFB1_RXD_MARK, VI1_R0_B_MARK, 780 GLO_SDATA_C_MARK, VI1_DATA6_C_MARK, 781 HTX1_MARK, SCIFB1_TXD_MARK, VI1_R1_B_MARK, 782 GLO_SS_C_MARK, VI1_DATA7_C_MARK, 783 HSCK1_MARK, SCIFB1_SCK_MARK, MLB_CLK_MARK, GLO_RFON_C_MARK, 784 HCTS1_N_MARK, SCIFB1_CTS_N_MARK, MLB_SIG_MARK, CAN1_TX_B_MARK, 785 HRTS1_N_MARK, SCIFB1_RTS_N_MARK, MLB_DAT_MARK, CAN1_RX_B_MARK, 786 PINMUX_MARK_END, 787 }; 788 789 static const u16 pinmux_data[] = { 790 PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */ 791 792 PINMUX_SINGLE(EX_CS0_N), 793 PINMUX_SINGLE(RD_N), 794 PINMUX_SINGLE(AUDIO_CLKA), 795 PINMUX_SINGLE(VI0_CLK), 796 PINMUX_SINGLE(VI0_DATA0_VI0_B0), 797 PINMUX_SINGLE(VI0_DATA1_VI0_B1), 798 PINMUX_SINGLE(VI0_DATA2_VI0_B2), 799 PINMUX_SINGLE(VI0_DATA4_VI0_B4), 800 PINMUX_SINGLE(VI0_DATA5_VI0_B5), 801 PINMUX_SINGLE(VI0_DATA6_VI0_B6), 802 PINMUX_SINGLE(VI0_DATA7_VI0_B7), 803 PINMUX_SINGLE(USB0_PWEN), 804 PINMUX_SINGLE(USB0_OVC), 805 PINMUX_SINGLE(USB1_PWEN), 806 PINMUX_SINGLE(USB1_OVC), 807 PINMUX_SINGLE(DU0_DOTCLKIN), 808 PINMUX_SINGLE(SD1_CLK), 809 810 /* IPSR0 */ 811 PINMUX_IPSR_GPSR(IP0_0, D0), 812 PINMUX_IPSR_GPSR(IP0_1, D1), 813 PINMUX_IPSR_GPSR(IP0_2, D2), 814 PINMUX_IPSR_GPSR(IP0_3, D3), 815 PINMUX_IPSR_GPSR(IP0_4, D4), 816 PINMUX_IPSR_GPSR(IP0_5, D5), 817 PINMUX_IPSR_GPSR(IP0_6, D6), 818 PINMUX_IPSR_GPSR(IP0_7, D7), 819 PINMUX_IPSR_GPSR(IP0_8, D8), 820 PINMUX_IPSR_GPSR(IP0_9, D9), 821 PINMUX_IPSR_GPSR(IP0_10, D10), 822 PINMUX_IPSR_GPSR(IP0_11, D11), 823 PINMUX_IPSR_GPSR(IP0_12, D12), 824 PINMUX_IPSR_GPSR(IP0_13, D13), 825 PINMUX_IPSR_GPSR(IP0_14, D14), 826 PINMUX_IPSR_GPSR(IP0_15, D15), 827 PINMUX_IPSR_GPSR(IP0_18_16, A0), 828 PINMUX_IPSR_MSEL(IP0_18_16, ATAWR0_N_C, SEL_LBS_2), 829 PINMUX_IPSR_MSEL(IP0_18_16, MSIOF0_SCK_B, SEL_SOF0_1), 830 PINMUX_IPSR_MSEL(IP0_18_16, I2C0_SCL_C, SEL_I2C0_2), 831 PINMUX_IPSR_GPSR(IP0_18_16, PWM2_B), 832 PINMUX_IPSR_GPSR(IP0_20_19, A1), 833 PINMUX_IPSR_MSEL(IP0_20_19, MSIOF0_SYNC_B, SEL_SOF0_1), 834 PINMUX_IPSR_GPSR(IP0_22_21, A2), 835 PINMUX_IPSR_MSEL(IP0_22_21, MSIOF0_SS1_B, SEL_SOF0_1), 836 PINMUX_IPSR_GPSR(IP0_24_23, A3), 837 PINMUX_IPSR_MSEL(IP0_24_23, MSIOF0_SS2_B, SEL_SOF0_1), 838 PINMUX_IPSR_GPSR(IP0_26_25, A4), 839 PINMUX_IPSR_MSEL(IP0_26_25, MSIOF0_TXD_B, SEL_SOF0_1), 840 PINMUX_IPSR_GPSR(IP0_28_27, A5), 841 PINMUX_IPSR_MSEL(IP0_28_27, MSIOF0_RXD_B, SEL_SOF0_1), 842 PINMUX_IPSR_GPSR(IP0_30_29, A6), 843 PINMUX_IPSR_MSEL(IP0_30_29, MSIOF1_SCK, SEL_SOF1_0), 844 845 /* IPSR1 */ 846 PINMUX_IPSR_GPSR(IP1_1_0, A7), 847 PINMUX_IPSR_MSEL(IP1_1_0, MSIOF1_SYNC, SEL_SOF1_0), 848 PINMUX_IPSR_GPSR(IP1_3_2, A8), 849 PINMUX_IPSR_MSEL(IP1_3_2, MSIOF1_SS1, SEL_SOF1_0), 850 PINMUX_IPSR_MSEL(IP1_3_2, I2C0_SCL, SEL_I2C0_0), 851 PINMUX_IPSR_GPSR(IP1_5_4, A9), 852 PINMUX_IPSR_MSEL(IP1_5_4, MSIOF1_SS2, SEL_SOF1_0), 853 PINMUX_IPSR_MSEL(IP1_5_4, I2C0_SDA, SEL_I2C0_0), 854 PINMUX_IPSR_GPSR(IP1_7_6, A10), 855 PINMUX_IPSR_MSEL(IP1_7_6, MSIOF1_TXD, SEL_SOF1_0), 856 PINMUX_IPSR_MSEL(IP1_7_6, MSIOF1_TXD_D, SEL_SOF1_3), 857 PINMUX_IPSR_GPSR(IP1_10_8, A11), 858 PINMUX_IPSR_MSEL(IP1_10_8, MSIOF1_RXD, SEL_SOF1_0), 859 PINMUX_IPSR_MSEL(IP1_10_8, I2C3_SCL_D, SEL_I2C3_3), 860 PINMUX_IPSR_MSEL(IP1_10_8, MSIOF1_RXD_D, SEL_SOF1_3), 861 PINMUX_IPSR_GPSR(IP1_13_11, A12), 862 PINMUX_IPSR_MSEL(IP1_13_11, FMCLK, SEL_FM_0), 863 PINMUX_IPSR_MSEL(IP1_13_11, I2C3_SDA_D, SEL_I2C3_3), 864 PINMUX_IPSR_MSEL(IP1_13_11, MSIOF1_SCK_D, SEL_SOF1_3), 865 PINMUX_IPSR_GPSR(IP1_16_14, A13), 866 PINMUX_IPSR_MSEL(IP1_16_14, ATAG0_N_C, SEL_LBS_2), 867 PINMUX_IPSR_MSEL(IP1_16_14, BPFCLK, SEL_FM_0), 868 PINMUX_IPSR_MSEL(IP1_16_14, MSIOF1_SS1_D, SEL_SOF1_3), 869 PINMUX_IPSR_GPSR(IP1_19_17, A14), 870 PINMUX_IPSR_MSEL(IP1_19_17, ATADIR0_N_C, SEL_LBS_2), 871 PINMUX_IPSR_MSEL(IP1_19_17, FMIN, SEL_FM_0), 872 PINMUX_IPSR_MSEL(IP1_19_17, FMIN_C, SEL_FM_2), 873 PINMUX_IPSR_MSEL(IP1_19_17, MSIOF1_SYNC_D, SEL_SOF1_3), 874 PINMUX_IPSR_GPSR(IP1_22_20, A15), 875 PINMUX_IPSR_MSEL(IP1_22_20, BPFCLK_C, SEL_FM_2), 876 PINMUX_IPSR_GPSR(IP1_25_23, A16), 877 PINMUX_IPSR_MSEL(IP1_25_23, DREQ2_B, SEL_LBS_1), 878 PINMUX_IPSR_MSEL(IP1_25_23, FMCLK_C, SEL_FM_2), 879 PINMUX_IPSR_MSEL(IP1_25_23, SCIFA1_SCK_B, SEL_SCIFA1_1), 880 PINMUX_IPSR_GPSR(IP1_28_26, A17), 881 PINMUX_IPSR_MSEL(IP1_28_26, DACK2_B, SEL_LBS_1), 882 PINMUX_IPSR_MSEL(IP1_28_26, I2C0_SDA_C, SEL_I2C0_2), 883 PINMUX_IPSR_GPSR(IP1_31_29, A18), 884 PINMUX_IPSR_MSEL(IP1_31_29, DREQ1, SEL_LBS_0), 885 PINMUX_IPSR_MSEL(IP1_31_29, SCIFA1_RXD_C, SEL_SCIFA1_2), 886 PINMUX_IPSR_MSEL(IP1_31_29, SCIFB1_RXD_C, SEL_SCIFB1_2), 887 888 /* IPSR2 */ 889 PINMUX_IPSR_GPSR(IP2_2_0, A19), 890 PINMUX_IPSR_GPSR(IP2_2_0, DACK1), 891 PINMUX_IPSR_MSEL(IP2_2_0, SCIFA1_TXD_C, SEL_SCIFA1_2), 892 PINMUX_IPSR_MSEL(IP2_2_0, SCIFB1_TXD_C, SEL_SCIFB1_2), 893 PINMUX_IPSR_MSEL(IP2_2_0, SCIFB1_SCK_B, SEL_SCIFB1_1), 894 PINMUX_IPSR_GPSR(IP2_2_0, A20), 895 PINMUX_IPSR_MSEL(IP2_4_3, SPCLK, SEL_QSP_0), 896 PINMUX_IPSR_GPSR(IP2_6_5, A21), 897 PINMUX_IPSR_MSEL(IP2_6_5, ATAWR0_N_B, SEL_LBS_1), 898 PINMUX_IPSR_MSEL(IP2_6_5, MOSI_IO0, SEL_QSP_0), 899 PINMUX_IPSR_GPSR(IP2_9_7, A22), 900 PINMUX_IPSR_MSEL(IP2_9_7, MISO_IO1, SEL_QSP_0), 901 PINMUX_IPSR_MSEL(IP2_9_7, FMCLK_B, SEL_FM_1), 902 PINMUX_IPSR_MSEL(IP2_9_7, TX0, SEL_SCIF0_0), 903 PINMUX_IPSR_MSEL(IP2_9_7, SCIFA0_TXD, SEL_SCFA_0), 904 PINMUX_IPSR_GPSR(IP2_12_10, A23), 905 PINMUX_IPSR_MSEL(IP2_12_10, IO2, SEL_QSP_0), 906 PINMUX_IPSR_MSEL(IP2_12_10, BPFCLK_B, SEL_FM_1), 907 PINMUX_IPSR_MSEL(IP2_12_10, RX0, SEL_SCIF0_0), 908 PINMUX_IPSR_MSEL(IP2_12_10, SCIFA0_RXD, SEL_SCFA_0), 909 PINMUX_IPSR_GPSR(IP2_15_13, A24), 910 PINMUX_IPSR_MSEL(IP2_15_13, DREQ2, SEL_LBS_0), 911 PINMUX_IPSR_MSEL(IP2_15_13, IO3, SEL_QSP_0), 912 PINMUX_IPSR_MSEL(IP2_15_13, TX1, SEL_SCIF1_0), 913 PINMUX_IPSR_MSEL(IP2_15_13, SCIFA1_TXD, SEL_SCIFA1_0), 914 PINMUX_IPSR_GPSR(IP2_18_16, A25), 915 PINMUX_IPSR_MSEL(IP2_18_16, DACK2, SEL_LBS_0), 916 PINMUX_IPSR_MSEL(IP2_18_16, SSL, SEL_QSP_0), 917 PINMUX_IPSR_MSEL(IP2_18_16, DREQ1_C, SEL_LBS_2), 918 PINMUX_IPSR_MSEL(IP2_18_16, RX1, SEL_SCIF1_0), 919 PINMUX_IPSR_MSEL(IP2_18_16, SCIFA1_RXD, SEL_SCIFA1_0), 920 PINMUX_IPSR_GPSR(IP2_20_19, CS0_N), 921 PINMUX_IPSR_MSEL(IP2_20_19, ATAG0_N_B, SEL_LBS_1), 922 PINMUX_IPSR_MSEL(IP2_20_19, I2C1_SCL, SEL_I2C1_0), 923 PINMUX_IPSR_GPSR(IP2_22_21, CS1_N_A26), 924 PINMUX_IPSR_MSEL(IP2_22_21, ATADIR0_N_B, SEL_LBS_1), 925 PINMUX_IPSR_MSEL(IP2_22_21, I2C1_SDA, SEL_I2C1_0), 926 PINMUX_IPSR_GPSR(IP2_24_23, EX_CS1_N), 927 PINMUX_IPSR_MSEL(IP2_24_23, MSIOF2_SCK, SEL_SOF2_0), 928 PINMUX_IPSR_GPSR(IP2_26_25, EX_CS2_N), 929 PINMUX_IPSR_MSEL(IP2_26_25, ATAWR0_N, SEL_LBS_0), 930 PINMUX_IPSR_MSEL(IP2_26_25, MSIOF2_SYNC, SEL_SOF2_0), 931 PINMUX_IPSR_GPSR(IP2_29_27, EX_CS3_N), 932 PINMUX_IPSR_MSEL(IP2_29_27, ATADIR0_N, SEL_LBS_0), 933 PINMUX_IPSR_MSEL(IP2_29_27, MSIOF2_TXD, SEL_SOF2_0), 934 PINMUX_IPSR_MSEL(IP2_29_27, ATAG0_N, SEL_LBS_0), 935 PINMUX_IPSR_GPSR(IP2_29_27, EX_WAIT1), 936 937 /* IPSR3 */ 938 PINMUX_IPSR_GPSR(IP3_2_0, EX_CS4_N), 939 PINMUX_IPSR_MSEL(IP3_2_0, ATARD0_N, SEL_LBS_0), 940 PINMUX_IPSR_MSEL(IP3_2_0, MSIOF2_RXD, SEL_SOF2_0), 941 PINMUX_IPSR_GPSR(IP3_2_0, EX_WAIT2), 942 PINMUX_IPSR_GPSR(IP3_5_3, EX_CS5_N), 943 PINMUX_IPSR_GPSR(IP3_5_3, ATACS00_N), 944 PINMUX_IPSR_MSEL(IP3_5_3, MSIOF2_SS1, SEL_SOF2_0), 945 PINMUX_IPSR_MSEL(IP3_5_3, HRX1_B, SEL_HSCIF1_1), 946 PINMUX_IPSR_MSEL(IP3_5_3, SCIFB1_RXD_B, SEL_SCIFB1_1), 947 PINMUX_IPSR_GPSR(IP3_5_3, PWM1), 948 PINMUX_IPSR_GPSR(IP3_5_3, TPU_TO1), 949 PINMUX_IPSR_GPSR(IP3_8_6, BS_N), 950 PINMUX_IPSR_GPSR(IP3_8_6, ATACS10_N), 951 PINMUX_IPSR_MSEL(IP3_8_6, MSIOF2_SS2, SEL_SOF2_0), 952 PINMUX_IPSR_MSEL(IP3_8_6, HTX1_B, SEL_HSCIF1_1), 953 PINMUX_IPSR_MSEL(IP3_8_6, SCIFB1_TXD_B, SEL_SCIFB1_1), 954 PINMUX_IPSR_GPSR(IP3_8_6, PWM2), 955 PINMUX_IPSR_GPSR(IP3_8_6, TPU_TO2), 956 PINMUX_IPSR_GPSR(IP3_11_9, RD_WR_N), 957 PINMUX_IPSR_MSEL(IP3_11_9, HRX2_B, SEL_HSCIF2_1), 958 PINMUX_IPSR_MSEL(IP3_11_9, FMIN_B, SEL_FM_1), 959 PINMUX_IPSR_MSEL(IP3_11_9, SCIFB0_RXD_B, SEL_SCIFB_1), 960 PINMUX_IPSR_MSEL(IP3_11_9, DREQ1_D, SEL_LBS_1), 961 PINMUX_IPSR_GPSR(IP3_13_12, WE0_N), 962 PINMUX_IPSR_MSEL(IP3_13_12, HCTS2_N_B, SEL_HSCIF2_1), 963 PINMUX_IPSR_MSEL(IP3_13_12, SCIFB0_TXD_B, SEL_SCIFB_1), 964 PINMUX_IPSR_GPSR(IP3_15_14, WE1_N), 965 PINMUX_IPSR_MSEL(IP3_15_14, ATARD0_N_B, SEL_LBS_1), 966 PINMUX_IPSR_MSEL(IP3_15_14, HTX2_B, SEL_HSCIF2_1), 967 PINMUX_IPSR_MSEL(IP3_15_14, SCIFB0_RTS_N_B, SEL_SCIFB_1), 968 PINMUX_IPSR_GPSR(IP3_17_16, EX_WAIT0), 969 PINMUX_IPSR_MSEL(IP3_17_16, HRTS2_N_B, SEL_HSCIF2_1), 970 PINMUX_IPSR_MSEL(IP3_17_16, SCIFB0_CTS_N_B, SEL_SCIFB_1), 971 PINMUX_IPSR_GPSR(IP3_19_18, DREQ0), 972 PINMUX_IPSR_GPSR(IP3_19_18, PWM3), 973 PINMUX_IPSR_GPSR(IP3_19_18, TPU_TO3), 974 PINMUX_IPSR_GPSR(IP3_21_20, DACK0), 975 PINMUX_IPSR_GPSR(IP3_21_20, DRACK0), 976 PINMUX_IPSR_MSEL(IP3_21_20, REMOCON, SEL_RCN_0), 977 PINMUX_IPSR_MSEL(IP3_24_22, SPEEDIN, SEL_RSP_0), 978 PINMUX_IPSR_MSEL(IP3_24_22, HSCK0_C, SEL_HSCIF0_2), 979 PINMUX_IPSR_MSEL(IP3_24_22, HSCK2_C, SEL_HSCIF2_2), 980 PINMUX_IPSR_MSEL(IP3_24_22, SCIFB0_SCK_B, SEL_SCIFB_1), 981 PINMUX_IPSR_MSEL(IP3_24_22, SCIFB2_SCK_B, SEL_SCIFB2_1), 982 PINMUX_IPSR_MSEL(IP3_24_22, DREQ2_C, SEL_LBS_2), 983 PINMUX_IPSR_MSEL(IP3_30_28, HTX2_C, SEL_HSCIF2_2), 984 PINMUX_IPSR_MSEL(IP3_27_25, SSI_SCK0129, SEL_SSI0_0), 985 PINMUX_IPSR_MSEL(IP3_27_25, HRX0_C, SEL_HSCIF0_2), 986 PINMUX_IPSR_MSEL(IP3_27_25, HRX2_C, SEL_HSCIF2_2), 987 PINMUX_IPSR_MSEL(IP3_27_25, SCIFB0_RXD_C, SEL_SCIFB_2), 988 PINMUX_IPSR_MSEL(IP3_27_25, SCIFB2_RXD_C, SEL_SCIFB2_2), 989 PINMUX_IPSR_MSEL(IP3_30_28, SSI_WS0129, SEL_SSI0_0), 990 PINMUX_IPSR_MSEL(IP3_30_28, HTX0_C, SEL_HSCIF0_2), 991 PINMUX_IPSR_MSEL(IP3_30_28, HTX2_C, SEL_HSCIF2_2), 992 PINMUX_IPSR_MSEL(IP3_30_28, SCIFB0_TXD_C, SEL_SCIFB_2), 993 PINMUX_IPSR_MSEL(IP3_30_28, SCIFB2_TXD_C, SEL_SCIFB2_2), 994 995 /* IPSR4 */ 996 PINMUX_IPSR_MSEL(IP4_1_0, SSI_SDATA0, SEL_SSI0_0), 997 PINMUX_IPSR_MSEL(IP4_1_0, I2C0_SCL_B, SEL_I2C0_1), 998 PINMUX_IPSR_MSEL(IP4_1_0, IIC0_SCL_B, SEL_IIC0_1), 999 PINMUX_IPSR_MSEL(IP4_1_0, MSIOF2_SCK_C, SEL_SOF2_2), 1000 PINMUX_IPSR_MSEL(IP4_4_2, SSI_SCK1, SEL_SSI1_0), 1001 PINMUX_IPSR_MSEL(IP4_4_2, I2C0_SDA_B, SEL_I2C0_1), 1002 PINMUX_IPSR_MSEL(IP4_4_2, IIC0_SDA_B, SEL_IIC0_1), 1003 PINMUX_IPSR_MSEL(IP4_4_2, MSIOF2_SYNC_C, SEL_SOF2_2), 1004 PINMUX_IPSR_MSEL(IP4_4_2, GLO_I0_D, SEL_GPS_3), 1005 PINMUX_IPSR_MSEL(IP4_7_5, SSI_WS1, SEL_SSI1_0), 1006 PINMUX_IPSR_MSEL(IP4_7_5, I2C1_SCL_B, SEL_I2C1_1), 1007 PINMUX_IPSR_MSEL(IP4_7_5, IIC1_SCL_B, SEL_IIC1_1), 1008 PINMUX_IPSR_MSEL(IP4_7_5, MSIOF2_TXD_C, SEL_SOF2_2), 1009 PINMUX_IPSR_MSEL(IP4_7_5, GLO_I1_D, SEL_GPS_3), 1010 PINMUX_IPSR_MSEL(IP4_9_8, SSI_SDATA1, SEL_SSI1_0), 1011 PINMUX_IPSR_MSEL(IP4_9_8, I2C1_SDA_B, SEL_I2C1_1), 1012 PINMUX_IPSR_MSEL(IP4_9_8, IIC1_SDA_B, SEL_IIC1_1), 1013 PINMUX_IPSR_MSEL(IP4_9_8, MSIOF2_RXD_C, SEL_SOF2_2), 1014 PINMUX_IPSR_GPSR(IP4_12_10, SSI_SCK2), 1015 PINMUX_IPSR_MSEL(IP4_12_10, I2C2_SCL, SEL_I2C2_0), 1016 PINMUX_IPSR_MSEL(IP4_12_10, GPS_CLK_B, SEL_GPS_1), 1017 PINMUX_IPSR_MSEL(IP4_12_10, GLO_Q0_D, SEL_GPS_3), 1018 PINMUX_IPSR_MSEL(IP4_12_10, HSCK1_E, SEL_HSCIF1_4), 1019 PINMUX_IPSR_GPSR(IP4_15_13, SSI_WS2), 1020 PINMUX_IPSR_MSEL(IP4_15_13, I2C2_SDA, SEL_I2C2_0), 1021 PINMUX_IPSR_MSEL(IP4_15_13, GPS_SIGN_B, SEL_GPS_1), 1022 PINMUX_IPSR_MSEL(IP4_15_13, RX2_E, SEL_SCIF2_4), 1023 PINMUX_IPSR_MSEL(IP4_15_13, GLO_Q1_D, SEL_GPS_3), 1024 PINMUX_IPSR_MSEL(IP4_15_13, HCTS1_N_E, SEL_HSCIF1_4), 1025 PINMUX_IPSR_GPSR(IP4_18_16, SSI_SDATA2), 1026 PINMUX_IPSR_MSEL(IP4_18_16, GPS_MAG_B, SEL_GPS_1), 1027 PINMUX_IPSR_MSEL(IP4_18_16, TX2_E, SEL_SCIF2_4), 1028 PINMUX_IPSR_MSEL(IP4_18_16, HRTS1_N_E, SEL_HSCIF1_4), 1029 PINMUX_IPSR_GPSR(IP4_19, SSI_SCK34), 1030 PINMUX_IPSR_GPSR(IP4_20, SSI_WS34), 1031 PINMUX_IPSR_GPSR(IP4_21, SSI_SDATA3), 1032 PINMUX_IPSR_GPSR(IP4_23_22, SSI_SCK4), 1033 PINMUX_IPSR_MSEL(IP4_23_22, GLO_SS_D, SEL_GPS_3), 1034 PINMUX_IPSR_GPSR(IP4_25_24, SSI_WS4), 1035 PINMUX_IPSR_MSEL(IP4_25_24, GLO_RFON_D, SEL_GPS_3), 1036 PINMUX_IPSR_GPSR(IP4_27_26, SSI_SDATA4), 1037 PINMUX_IPSR_MSEL(IP4_27_26, MSIOF2_SCK_D, SEL_SOF2_3), 1038 PINMUX_IPSR_GPSR(IP4_30_28, SSI_SCK5), 1039 PINMUX_IPSR_MSEL(IP4_30_28, MSIOF1_SCK_C, SEL_SOF1_2), 1040 PINMUX_IPSR_MSEL(IP4_30_28, TS_SDATA0, SEL_TSIF0_0), 1041 PINMUX_IPSR_MSEL(IP4_30_28, GLO_I0, SEL_GPS_0), 1042 PINMUX_IPSR_MSEL(IP4_30_28, MSIOF2_SYNC_D, SEL_SOF2_3), 1043 PINMUX_IPSR_GPSR(IP4_30_28, VI1_R2_B), 1044 1045 /* IPSR5 */ 1046 PINMUX_IPSR_GPSR(IP5_2_0, SSI_WS5), 1047 PINMUX_IPSR_MSEL(IP5_2_0, MSIOF1_SYNC_C, SEL_SOF1_2), 1048 PINMUX_IPSR_MSEL(IP5_2_0, TS_SCK0, SEL_TSIF0_0), 1049 PINMUX_IPSR_MSEL(IP5_2_0, GLO_I1, SEL_GPS_0), 1050 PINMUX_IPSR_MSEL(IP5_2_0, MSIOF2_TXD_D, SEL_SOF2_3), 1051 PINMUX_IPSR_GPSR(IP5_2_0, VI1_R3_B), 1052 PINMUX_IPSR_GPSR(IP5_5_3, SSI_SDATA5), 1053 PINMUX_IPSR_MSEL(IP5_5_3, MSIOF1_TXD_C, SEL_SOF1_2), 1054 PINMUX_IPSR_MSEL(IP5_5_3, TS_SDEN0, SEL_TSIF0_0), 1055 PINMUX_IPSR_MSEL(IP5_5_3, GLO_Q0, SEL_GPS_0), 1056 PINMUX_IPSR_MSEL(IP5_5_3, MSIOF2_SS1_D, SEL_SOF2_3), 1057 PINMUX_IPSR_GPSR(IP5_5_3, VI1_R4_B), 1058 PINMUX_IPSR_GPSR(IP5_8_6, SSI_SCK6), 1059 PINMUX_IPSR_MSEL(IP5_8_6, MSIOF1_RXD_C, SEL_SOF1_2), 1060 PINMUX_IPSR_MSEL(IP5_8_6, TS_SPSYNC0, SEL_TSIF0_0), 1061 PINMUX_IPSR_MSEL(IP5_8_6, GLO_Q1, SEL_GPS_0), 1062 PINMUX_IPSR_MSEL(IP5_8_6, MSIOF2_RXD_D, SEL_SOF2_3), 1063 PINMUX_IPSR_GPSR(IP5_8_6, VI1_R5_B), 1064 PINMUX_IPSR_GPSR(IP5_11_9, SSI_WS6), 1065 PINMUX_IPSR_MSEL(IP5_11_9, GLO_SCLK, SEL_GPS_0), 1066 PINMUX_IPSR_MSEL(IP5_11_9, MSIOF2_SS2_D, SEL_SOF2_3), 1067 PINMUX_IPSR_GPSR(IP5_11_9, VI1_R6_B), 1068 PINMUX_IPSR_GPSR(IP5_14_12, SSI_SDATA6), 1069 PINMUX_IPSR_MSEL(IP5_14_12, STP_IVCXO27_0_B, SEL_SSP_1), 1070 PINMUX_IPSR_MSEL(IP5_14_12, GLO_SDATA, SEL_GPS_0), 1071 PINMUX_IPSR_GPSR(IP5_14_12, VI1_R7_B), 1072 PINMUX_IPSR_MSEL(IP5_16_15, SSI_SCK78, SEL_SSI7_0), 1073 PINMUX_IPSR_MSEL(IP5_16_15, STP_ISCLK_0_B, SEL_SSP_1), 1074 PINMUX_IPSR_MSEL(IP5_16_15, GLO_SS, SEL_GPS_0), 1075 PINMUX_IPSR_MSEL(IP5_19_17, SSI_WS78, SEL_SSI7_0), 1076 PINMUX_IPSR_MSEL(IP5_19_17, TX0_D, SEL_SCIF0_3), 1077 PINMUX_IPSR_MSEL(IP5_19_17, STP_ISD_0_B, SEL_SSP_1), 1078 PINMUX_IPSR_MSEL(IP5_19_17, GLO_RFON, SEL_GPS_0), 1079 PINMUX_IPSR_MSEL(IP5_21_20, SSI_SDATA7, SEL_SSI7_0), 1080 PINMUX_IPSR_MSEL(IP5_21_20, RX0_D, SEL_SCIF0_3), 1081 PINMUX_IPSR_MSEL(IP5_21_20, STP_ISEN_0_B, SEL_SSP_1), 1082 PINMUX_IPSR_MSEL(IP5_23_22, SSI_SDATA8, SEL_SSI8_0), 1083 PINMUX_IPSR_MSEL(IP5_23_22, TX1_D, SEL_SCIF1_3), 1084 PINMUX_IPSR_MSEL(IP5_23_22, STP_ISSYNC_0_B, SEL_SSP_1), 1085 PINMUX_IPSR_MSEL(IP5_25_24, SSI_SCK9, SEL_SSI9_0), 1086 PINMUX_IPSR_MSEL(IP5_25_24, RX1_D, SEL_SCIF1_3), 1087 PINMUX_IPSR_MSEL(IP5_25_24, GLO_SCLK_D, SEL_GPS_3), 1088 PINMUX_IPSR_MSEL(IP5_28_26, SSI_WS9, SEL_SSI9_0), 1089 PINMUX_IPSR_MSEL(IP5_28_26, TX3_D, SEL_SCIF3_3), 1090 PINMUX_IPSR_MSEL(IP5_28_26, CAN0_TX_D, SEL_CAN0_3), 1091 PINMUX_IPSR_MSEL(IP5_28_26, GLO_SDATA_D, SEL_GPS_3), 1092 PINMUX_IPSR_MSEL(IP5_31_29, SSI_SDATA9, SEL_SSI9_0), 1093 PINMUX_IPSR_MSEL(IP5_31_29, RX3_D, SEL_SCIF3_3), 1094 PINMUX_IPSR_MSEL(IP5_31_29, CAN0_RX_D, SEL_CAN0_3), 1095 1096 /* IPSR6 */ 1097 PINMUX_IPSR_MSEL(IP6_2_0, AUDIO_CLKB, SEL_ADG_0), 1098 PINMUX_IPSR_MSEL(IP6_2_0, STP_OPWM_0_B, SEL_SSP_1), 1099 PINMUX_IPSR_MSEL(IP6_2_0, MSIOF1_SCK_B, SEL_SOF1_1), 1100 PINMUX_IPSR_MSEL(IP6_2_0, SCIF_CLK, SEL_SCIF_0), 1101 PINMUX_IPSR_GPSR(IP6_2_0, DVC_MUTE), 1102 PINMUX_IPSR_MSEL(IP6_2_0, BPFCLK_E, SEL_FM_4), 1103 PINMUX_IPSR_GPSR(IP6_5_3, AUDIO_CLKC), 1104 PINMUX_IPSR_MSEL(IP6_5_3, SCIFB0_SCK_C, SEL_SCIFB_2), 1105 PINMUX_IPSR_MSEL(IP6_5_3, MSIOF1_SYNC_B, SEL_SOF1_1), 1106 PINMUX_IPSR_MSEL(IP6_5_3, RX2, SEL_SCIF2_0), 1107 PINMUX_IPSR_MSEL(IP6_5_3, SCIFA2_RXD, SEL_SCIFA2_0), 1108 PINMUX_IPSR_MSEL(IP6_5_3, FMIN_E, SEL_FM_4), 1109 PINMUX_IPSR_GPSR(IP6_7_6, AUDIO_CLKOUT), 1110 PINMUX_IPSR_MSEL(IP6_7_6, MSIOF1_SS1_B, SEL_SOF1_1), 1111 PINMUX_IPSR_MSEL(IP6_7_6, TX2, SEL_SCIF2_0), 1112 PINMUX_IPSR_MSEL(IP6_7_6, SCIFA2_TXD, SEL_SCIFA2_0), 1113 PINMUX_IPSR_GPSR(IP6_9_8, IRQ0), 1114 PINMUX_IPSR_MSEL(IP6_9_8, SCIFB1_RXD_D, SEL_SCIFB1_3), 1115 PINMUX_IPSR_GPSR(IP6_9_8, INTC_IRQ0_N), 1116 PINMUX_IPSR_GPSR(IP6_11_10, IRQ1), 1117 PINMUX_IPSR_MSEL(IP6_11_10, SCIFB1_SCK_C, SEL_SCIFB1_2), 1118 PINMUX_IPSR_GPSR(IP6_11_10, INTC_IRQ1_N), 1119 PINMUX_IPSR_GPSR(IP6_13_12, IRQ2), 1120 PINMUX_IPSR_MSEL(IP6_13_12, SCIFB1_TXD_D, SEL_SCIFB1_3), 1121 PINMUX_IPSR_GPSR(IP6_13_12, INTC_IRQ2_N), 1122 PINMUX_IPSR_GPSR(IP6_15_14, IRQ3), 1123 PINMUX_IPSR_MSEL(IP6_15_14, I2C4_SCL_C, SEL_I2C4_2), 1124 PINMUX_IPSR_MSEL(IP6_15_14, MSIOF2_TXD_E, SEL_SOF2_4), 1125 PINMUX_IPSR_GPSR(IP6_15_14, INTC_IRQ4_N), 1126 PINMUX_IPSR_GPSR(IP6_18_16, IRQ4), 1127 PINMUX_IPSR_MSEL(IP6_18_16, HRX1_C, SEL_HSCIF1_2), 1128 PINMUX_IPSR_MSEL(IP6_18_16, I2C4_SDA_C, SEL_I2C4_2), 1129 PINMUX_IPSR_MSEL(IP6_18_16, MSIOF2_RXD_E, SEL_SOF2_4), 1130 PINMUX_IPSR_GPSR(IP6_18_16, INTC_IRQ4_N), 1131 PINMUX_IPSR_GPSR(IP6_20_19, IRQ5), 1132 PINMUX_IPSR_MSEL(IP6_20_19, HTX1_C, SEL_HSCIF1_2), 1133 PINMUX_IPSR_MSEL(IP6_20_19, I2C1_SCL_E, SEL_I2C1_4), 1134 PINMUX_IPSR_MSEL(IP6_20_19, MSIOF2_SCK_E, SEL_SOF2_4), 1135 PINMUX_IPSR_GPSR(IP6_23_21, IRQ6), 1136 PINMUX_IPSR_MSEL(IP6_23_21, HSCK1_C, SEL_HSCIF1_2), 1137 PINMUX_IPSR_MSEL(IP6_23_21, MSIOF1_SS2_B, SEL_SOF1_1), 1138 PINMUX_IPSR_MSEL(IP6_23_21, I2C1_SDA_E, SEL_I2C1_4), 1139 PINMUX_IPSR_MSEL(IP6_23_21, MSIOF2_SYNC_E, SEL_SOF2_4), 1140 PINMUX_IPSR_GPSR(IP6_26_24, IRQ7), 1141 PINMUX_IPSR_MSEL(IP6_26_24, HCTS1_N_C, SEL_HSCIF1_2), 1142 PINMUX_IPSR_MSEL(IP6_26_24, MSIOF1_TXD_B, SEL_SOF1_1), 1143 PINMUX_IPSR_MSEL(IP6_26_24, GPS_CLK_C, SEL_GPS_2), 1144 PINMUX_IPSR_MSEL(IP6_26_24, GPS_CLK_D, SEL_GPS_3), 1145 PINMUX_IPSR_GPSR(IP6_29_27, IRQ8), 1146 PINMUX_IPSR_MSEL(IP6_29_27, HRTS1_N_C, SEL_HSCIF1_2), 1147 PINMUX_IPSR_MSEL(IP6_29_27, MSIOF1_RXD_B, SEL_SOF1_1), 1148 PINMUX_IPSR_MSEL(IP6_29_27, GPS_SIGN_C, SEL_GPS_2), 1149 PINMUX_IPSR_MSEL(IP6_29_27, GPS_SIGN_D, SEL_GPS_3), 1150 1151 /* IPSR7 */ 1152 PINMUX_IPSR_GPSR(IP7_2_0, IRQ9), 1153 PINMUX_IPSR_MSEL(IP7_2_0, DU1_DOTCLKIN_B, SEL_DIS_1), 1154 PINMUX_IPSR_MSEL(IP7_2_0, CAN_CLK_D, SEL_CANCLK_3), 1155 PINMUX_IPSR_MSEL(IP7_2_0, GPS_MAG_C, SEL_GPS_2), 1156 PINMUX_IPSR_MSEL(IP7_2_0, SCIF_CLK_B, SEL_SCIF_1), 1157 PINMUX_IPSR_MSEL(IP7_2_0, GPS_MAG_D, SEL_GPS_3), 1158 PINMUX_IPSR_GPSR(IP7_5_3, DU1_DR0), 1159 PINMUX_IPSR_GPSR(IP7_5_3, LCDOUT0), 1160 PINMUX_IPSR_MSEL(IP7_5_3, VI1_DATA0_B, SEL_VI1_1), 1161 PINMUX_IPSR_MSEL(IP7_5_3, TX0_B, SEL_SCIF0_1), 1162 PINMUX_IPSR_MSEL(IP7_5_3, SCIFA0_TXD_B, SEL_SCFA_1), 1163 PINMUX_IPSR_MSEL(IP7_5_3, MSIOF2_SCK_B, SEL_SOF2_1), 1164 PINMUX_IPSR_GPSR(IP7_8_6, DU1_DR1), 1165 PINMUX_IPSR_GPSR(IP7_8_6, LCDOUT1), 1166 PINMUX_IPSR_MSEL(IP7_8_6, VI1_DATA1_B, SEL_VI1_1), 1167 PINMUX_IPSR_MSEL(IP7_8_6, RX0_B, SEL_SCIF0_1), 1168 PINMUX_IPSR_MSEL(IP7_8_6, SCIFA0_RXD_B, SEL_SCFA_1), 1169 PINMUX_IPSR_MSEL(IP7_8_6, MSIOF2_SYNC_B, SEL_SOF2_1), 1170 PINMUX_IPSR_GPSR(IP7_10_9, DU1_DR2), 1171 PINMUX_IPSR_GPSR(IP7_10_9, LCDOUT2), 1172 PINMUX_IPSR_MSEL(IP7_10_9, SSI_SCK0129_B, SEL_SSI0_1), 1173 PINMUX_IPSR_GPSR(IP7_12_11, DU1_DR3), 1174 PINMUX_IPSR_GPSR(IP7_12_11, LCDOUT3), 1175 PINMUX_IPSR_MSEL(IP7_12_11, SSI_WS0129_B, SEL_SSI0_1), 1176 PINMUX_IPSR_GPSR(IP7_14_13, DU1_DR4), 1177 PINMUX_IPSR_GPSR(IP7_14_13, LCDOUT4), 1178 PINMUX_IPSR_MSEL(IP7_14_13, SSI_SDATA0_B, SEL_SSI0_1), 1179 PINMUX_IPSR_GPSR(IP7_16_15, DU1_DR5), 1180 PINMUX_IPSR_GPSR(IP7_16_15, LCDOUT5), 1181 PINMUX_IPSR_MSEL(IP7_16_15, SSI_SCK1_B, SEL_SSI1_1), 1182 PINMUX_IPSR_GPSR(IP7_18_17, DU1_DR6), 1183 PINMUX_IPSR_GPSR(IP7_18_17, LCDOUT6), 1184 PINMUX_IPSR_MSEL(IP7_18_17, SSI_WS1_B, SEL_SSI1_1), 1185 PINMUX_IPSR_GPSR(IP7_20_19, DU1_DR7), 1186 PINMUX_IPSR_GPSR(IP7_20_19, LCDOUT7), 1187 PINMUX_IPSR_MSEL(IP7_20_19, SSI_SDATA1_B, SEL_SSI1_1), 1188 PINMUX_IPSR_GPSR(IP7_23_21, DU1_DG0), 1189 PINMUX_IPSR_GPSR(IP7_23_21, LCDOUT8), 1190 PINMUX_IPSR_MSEL(IP7_23_21, VI1_DATA2_B, SEL_VI1_1), 1191 PINMUX_IPSR_MSEL(IP7_23_21, TX1_B, SEL_SCIF1_1), 1192 PINMUX_IPSR_MSEL(IP7_23_21, SCIFA1_TXD_B, SEL_SCIFA1_1), 1193 PINMUX_IPSR_MSEL(IP7_23_21, MSIOF2_SS1_B, SEL_SOF2_1), 1194 PINMUX_IPSR_GPSR(IP7_26_24, DU1_DG1), 1195 PINMUX_IPSR_GPSR(IP7_26_24, LCDOUT9), 1196 PINMUX_IPSR_MSEL(IP7_26_24, VI1_DATA3_B, SEL_VI1_1), 1197 PINMUX_IPSR_MSEL(IP7_26_24, RX1_B, SEL_SCIF1_1), 1198 PINMUX_IPSR_MSEL(IP7_26_24, SCIFA1_RXD_B, SEL_SCIFA1_1), 1199 PINMUX_IPSR_MSEL(IP7_26_24, MSIOF2_SS2_B, SEL_SOF2_1), 1200 PINMUX_IPSR_GPSR(IP7_29_27, DU1_DG2), 1201 PINMUX_IPSR_GPSR(IP7_29_27, LCDOUT10), 1202 PINMUX_IPSR_MSEL(IP7_29_27, VI1_DATA4_B, SEL_VI1_1), 1203 PINMUX_IPSR_GPSR(IP7_29_27, SCIF1_SCK_B), 1204 PINMUX_IPSR_MSEL(IP7_29_27, SCIFA1_SCK, SEL_SCIFA1_0), 1205 PINMUX_IPSR_MSEL(IP7_29_27, SSI_SCK78_B, SEL_SSI7_1), 1206 1207 /* IPSR8 */ 1208 PINMUX_IPSR_GPSR(IP8_2_0, DU1_DG3), 1209 PINMUX_IPSR_GPSR(IP8_2_0, LCDOUT11), 1210 PINMUX_IPSR_MSEL(IP8_2_0, VI1_DATA5_B, SEL_VI1_1), 1211 PINMUX_IPSR_MSEL(IP8_2_0, SSI_WS78_B, SEL_SSI7_1), 1212 PINMUX_IPSR_GPSR(IP8_5_3, DU1_DG4), 1213 PINMUX_IPSR_GPSR(IP8_5_3, LCDOUT12), 1214 PINMUX_IPSR_MSEL(IP8_5_3, VI1_DATA6_B, SEL_VI1_1), 1215 PINMUX_IPSR_MSEL(IP8_5_3, HRX0_B, SEL_HSCIF0_1), 1216 PINMUX_IPSR_MSEL(IP8_5_3, SCIFB2_RXD_B, SEL_SCIFB2_1), 1217 PINMUX_IPSR_MSEL(IP8_5_3, SSI_SDATA7_B, SEL_SSI7_1), 1218 PINMUX_IPSR_GPSR(IP8_8_6, DU1_DG5), 1219 PINMUX_IPSR_GPSR(IP8_8_6, LCDOUT13), 1220 PINMUX_IPSR_MSEL(IP8_8_6, VI1_DATA7_B, SEL_VI1_1), 1221 PINMUX_IPSR_MSEL(IP8_8_6, HCTS0_N_B, SEL_HSCIF0_1), 1222 PINMUX_IPSR_MSEL(IP8_8_6, SCIFB2_TXD_B, SEL_SCIFB2_1), 1223 PINMUX_IPSR_MSEL(IP8_8_6, SSI_SDATA8_B, SEL_SSI8_1), 1224 PINMUX_IPSR_GPSR(IP8_11_9, DU1_DG6), 1225 PINMUX_IPSR_GPSR(IP8_11_9, LCDOUT14), 1226 PINMUX_IPSR_MSEL(IP8_11_9, HRTS0_N_B, SEL_HSCIF0_1), 1227 PINMUX_IPSR_MSEL(IP8_11_9, SCIFB2_CTS_N_B, SEL_SCIFB2_1), 1228 PINMUX_IPSR_MSEL(IP8_11_9, SSI_SCK9_B, SEL_SSI9_1), 1229 PINMUX_IPSR_GPSR(IP8_14_12, DU1_DG7), 1230 PINMUX_IPSR_GPSR(IP8_14_12, LCDOUT15), 1231 PINMUX_IPSR_MSEL(IP8_14_12, HTX0_B, SEL_HSCIF0_1), 1232 PINMUX_IPSR_MSEL(IP8_14_12, SCIFB2_RTS_N_B, SEL_SCIFB2_1), 1233 PINMUX_IPSR_MSEL(IP8_14_12, SSI_WS9_B, SEL_SSI9_1), 1234 PINMUX_IPSR_GPSR(IP8_17_15, DU1_DB0), 1235 PINMUX_IPSR_GPSR(IP8_17_15, LCDOUT16), 1236 PINMUX_IPSR_MSEL(IP8_17_15, VI1_CLK_B, SEL_VI1_1), 1237 PINMUX_IPSR_MSEL(IP8_17_15, TX2_B, SEL_SCIF2_1), 1238 PINMUX_IPSR_MSEL(IP8_17_15, SCIFA2_TXD_B, SEL_SCIFA2_1), 1239 PINMUX_IPSR_MSEL(IP8_17_15, MSIOF2_TXD_B, SEL_SOF2_1), 1240 PINMUX_IPSR_GPSR(IP8_20_18, DU1_DB1), 1241 PINMUX_IPSR_GPSR(IP8_20_18, LCDOUT17), 1242 PINMUX_IPSR_MSEL(IP8_20_18, VI1_HSYNC_N_B, SEL_VI1_1), 1243 PINMUX_IPSR_MSEL(IP8_20_18, RX2_B, SEL_SCIF2_1), 1244 PINMUX_IPSR_MSEL(IP8_20_18, SCIFA2_RXD_B, SEL_SCIFA2_1), 1245 PINMUX_IPSR_MSEL(IP8_20_18, MSIOF2_RXD_B, SEL_SOF2_1), 1246 PINMUX_IPSR_GPSR(IP8_23_21, DU1_DB2), 1247 PINMUX_IPSR_GPSR(IP8_23_21, LCDOUT18), 1248 PINMUX_IPSR_MSEL(IP8_23_21, VI1_VSYNC_N_B, SEL_VI1_1), 1249 PINMUX_IPSR_GPSR(IP8_23_21, SCIF2_SCK_B), 1250 PINMUX_IPSR_MSEL(IP8_23_21, SCIFA2_SCK, SEL_SCIFA2_1), 1251 PINMUX_IPSR_MSEL(IP8_23_21, SSI_SDATA9_B, SEL_SSI9_1), 1252 PINMUX_IPSR_GPSR(IP8_25_24, DU1_DB3), 1253 PINMUX_IPSR_GPSR(IP8_25_24, LCDOUT19), 1254 PINMUX_IPSR_MSEL(IP8_25_24, VI1_CLKENB_B, SEL_VI1_1), 1255 PINMUX_IPSR_GPSR(IP8_27_26, DU1_DB4), 1256 PINMUX_IPSR_GPSR(IP8_27_26, LCDOUT20), 1257 PINMUX_IPSR_MSEL(IP8_27_26, VI1_FIELD_B, SEL_VI1_1), 1258 PINMUX_IPSR_MSEL(IP8_27_26, CAN1_RX, SEL_CAN1_0), 1259 PINMUX_IPSR_GPSR(IP8_30_28, DU1_DB5), 1260 PINMUX_IPSR_GPSR(IP8_30_28, LCDOUT21), 1261 PINMUX_IPSR_MSEL(IP8_30_28, TX3, SEL_SCIF3_0), 1262 PINMUX_IPSR_MSEL(IP8_30_28, SCIFA3_TXD, SEL_SCIFA3_0), 1263 PINMUX_IPSR_MSEL(IP8_30_28, CAN1_TX, SEL_CAN1_0), 1264 1265 /* IPSR9 */ 1266 PINMUX_IPSR_GPSR(IP9_2_0, DU1_DB6), 1267 PINMUX_IPSR_GPSR(IP9_2_0, LCDOUT22), 1268 PINMUX_IPSR_MSEL(IP9_2_0, I2C3_SCL_C, SEL_I2C3_2), 1269 PINMUX_IPSR_MSEL(IP9_2_0, RX3, SEL_SCIF3_0), 1270 PINMUX_IPSR_MSEL(IP9_2_0, SCIFA3_RXD, SEL_SCIFA3_0), 1271 PINMUX_IPSR_GPSR(IP9_5_3, DU1_DB7), 1272 PINMUX_IPSR_GPSR(IP9_5_3, LCDOUT23), 1273 PINMUX_IPSR_MSEL(IP9_5_3, I2C3_SDA_C, SEL_I2C3_2), 1274 PINMUX_IPSR_MSEL(IP9_5_3, SCIF3_SCK, SEL_SCIF3_0), 1275 PINMUX_IPSR_MSEL(IP9_5_3, SCIFA3_SCK, SEL_SCIFA3_0), 1276 PINMUX_IPSR_MSEL(IP9_6, DU1_DOTCLKIN, SEL_DIS_0), 1277 PINMUX_IPSR_GPSR(IP9_6, QSTVA_QVS), 1278 PINMUX_IPSR_GPSR(IP9_7, DU1_DOTCLKOUT0), 1279 PINMUX_IPSR_GPSR(IP9_7, QCLK), 1280 PINMUX_IPSR_GPSR(IP9_10_8, DU1_DOTCLKOUT1), 1281 PINMUX_IPSR_GPSR(IP9_10_8, QSTVB_QVE), 1282 PINMUX_IPSR_MSEL(IP9_10_8, CAN0_TX, SEL_CAN0_0), 1283 PINMUX_IPSR_MSEL(IP9_10_8, TX3_B, SEL_SCIF3_1), 1284 PINMUX_IPSR_MSEL(IP9_10_8, I2C2_SCL_B, SEL_I2C2_1), 1285 PINMUX_IPSR_GPSR(IP9_10_8, PWM4), 1286 PINMUX_IPSR_GPSR(IP9_11, DU1_EXHSYNC_DU1_HSYNC), 1287 PINMUX_IPSR_GPSR(IP9_11, QSTH_QHS), 1288 PINMUX_IPSR_GPSR(IP9_12, DU1_EXVSYNC_DU1_VSYNC), 1289 PINMUX_IPSR_GPSR(IP9_12, QSTB_QHE), 1290 PINMUX_IPSR_GPSR(IP9_15_13, DU1_EXODDF_DU1_ODDF_DISP_CDE), 1291 PINMUX_IPSR_GPSR(IP9_15_13, QCPV_QDE), 1292 PINMUX_IPSR_MSEL(IP9_15_13, CAN0_RX, SEL_CAN0_0), 1293 PINMUX_IPSR_MSEL(IP9_15_13, RX3_B, SEL_SCIF3_1), 1294 PINMUX_IPSR_MSEL(IP9_15_13, I2C2_SDA_B, SEL_I2C2_1), 1295 PINMUX_IPSR_GPSR(IP9_16, DU1_DISP), 1296 PINMUX_IPSR_GPSR(IP9_16, QPOLA), 1297 PINMUX_IPSR_GPSR(IP9_18_17, DU1_CDE), 1298 PINMUX_IPSR_GPSR(IP9_18_17, QPOLB), 1299 PINMUX_IPSR_GPSR(IP9_18_17, PWM4_B), 1300 PINMUX_IPSR_GPSR(IP9_20_19, VI0_CLKENB), 1301 PINMUX_IPSR_MSEL(IP9_20_19, TX4, SEL_SCIF4_0), 1302 PINMUX_IPSR_MSEL(IP9_20_19, SCIFA4_TXD, SEL_SCIFA4_0), 1303 PINMUX_IPSR_MSEL(IP9_20_19, TS_SDATA0_D, SEL_TSIF0_3), 1304 PINMUX_IPSR_GPSR(IP9_22_21, VI0_FIELD), 1305 PINMUX_IPSR_MSEL(IP9_22_21, RX4, SEL_SCIF4_0), 1306 PINMUX_IPSR_MSEL(IP9_22_21, SCIFA4_RXD, SEL_SCIFA4_0), 1307 PINMUX_IPSR_MSEL(IP9_22_21, TS_SCK0_D, SEL_TSIF0_3), 1308 PINMUX_IPSR_GPSR(IP9_24_23, VI0_HSYNC_N), 1309 PINMUX_IPSR_MSEL(IP9_24_23, TX5, SEL_SCIF5_0), 1310 PINMUX_IPSR_MSEL(IP9_24_23, SCIFA5_TXD, SEL_SCIFA5_0), 1311 PINMUX_IPSR_MSEL(IP9_24_23, TS_SDEN0_D, SEL_TSIF0_3), 1312 PINMUX_IPSR_GPSR(IP9_26_25, VI0_VSYNC_N), 1313 PINMUX_IPSR_MSEL(IP9_26_25, RX5, SEL_SCIF5_0), 1314 PINMUX_IPSR_MSEL(IP9_26_25, SCIFA5_RXD, SEL_SCIFA5_0), 1315 PINMUX_IPSR_MSEL(IP9_26_25, TS_SPSYNC0_D, SEL_TSIF0_3), 1316 PINMUX_IPSR_GPSR(IP9_28_27, VI0_DATA3_VI0_B3), 1317 PINMUX_IPSR_MSEL(IP9_28_27, SCIF3_SCK_B, SEL_SCIF3_1), 1318 PINMUX_IPSR_MSEL(IP9_28_27, SCIFA3_SCK_B, SEL_SCIFA3_1), 1319 PINMUX_IPSR_GPSR(IP9_31_29, VI0_G0), 1320 PINMUX_IPSR_MSEL(IP9_31_29, IIC1_SCL, SEL_IIC1_0), 1321 PINMUX_IPSR_MSEL(IP9_31_29, STP_IVCXO27_0_C, SEL_SSP_2), 1322 PINMUX_IPSR_MSEL(IP9_31_29, I2C4_SCL, SEL_I2C4_0), 1323 PINMUX_IPSR_MSEL(IP9_31_29, HCTS2_N, SEL_HSCIF2_0), 1324 PINMUX_IPSR_MSEL(IP9_31_29, SCIFB2_CTS_N, SEL_SCIFB2_0), 1325 PINMUX_IPSR_GPSR(IP9_31_29, ATAWR1_N), 1326 1327 /* IPSR10 */ 1328 PINMUX_IPSR_GPSR(IP10_2_0, VI0_G1), 1329 PINMUX_IPSR_MSEL(IP10_2_0, IIC1_SDA, SEL_IIC1_0), 1330 PINMUX_IPSR_MSEL(IP10_2_0, STP_ISCLK_0_C, SEL_SSP_2), 1331 PINMUX_IPSR_MSEL(IP10_2_0, I2C4_SDA, SEL_I2C4_0), 1332 PINMUX_IPSR_MSEL(IP10_2_0, HRTS2_N, SEL_HSCIF2_0), 1333 PINMUX_IPSR_MSEL(IP10_2_0, SCIFB2_RTS_N, SEL_SCIFB2_0), 1334 PINMUX_IPSR_GPSR(IP10_2_0, ATADIR1_N), 1335 PINMUX_IPSR_GPSR(IP10_5_3, VI0_G2), 1336 PINMUX_IPSR_GPSR(IP10_5_3, VI2_HSYNC_N), 1337 PINMUX_IPSR_MSEL(IP10_5_3, STP_ISD_0_C, SEL_SSP_2), 1338 PINMUX_IPSR_MSEL(IP10_5_3, I2C3_SCL_B, SEL_I2C3_1), 1339 PINMUX_IPSR_MSEL(IP10_5_3, HSCK2, SEL_HSCIF2_0), 1340 PINMUX_IPSR_MSEL(IP10_5_3, SCIFB2_SCK, SEL_SCIFB2_0), 1341 PINMUX_IPSR_GPSR(IP10_5_3, ATARD1_N), 1342 PINMUX_IPSR_GPSR(IP10_8_6, VI0_G3), 1343 PINMUX_IPSR_GPSR(IP10_8_6, VI2_VSYNC_N), 1344 PINMUX_IPSR_MSEL(IP10_8_6, STP_ISEN_0_C, SEL_SSP_2), 1345 PINMUX_IPSR_MSEL(IP10_8_6, I2C3_SDA_B, SEL_I2C3_1), 1346 PINMUX_IPSR_MSEL(IP10_8_6, HRX2, SEL_HSCIF2_0), 1347 PINMUX_IPSR_MSEL(IP10_8_6, SCIFB2_RXD, SEL_SCIFB2_0), 1348 PINMUX_IPSR_GPSR(IP10_8_6, ATACS01_N), 1349 PINMUX_IPSR_GPSR(IP10_11_9, VI0_G4), 1350 PINMUX_IPSR_GPSR(IP10_11_9, VI2_CLKENB), 1351 PINMUX_IPSR_MSEL(IP10_11_9, STP_ISSYNC_0_C, SEL_SSP_2), 1352 PINMUX_IPSR_MSEL(IP10_11_9, HTX2, SEL_HSCIF2_0), 1353 PINMUX_IPSR_MSEL(IP10_11_9, SCIFB2_TXD, SEL_SCIFB2_0), 1354 PINMUX_IPSR_MSEL(IP10_11_9, SCIFB0_SCK_D, SEL_SCIFB_3), 1355 PINMUX_IPSR_GPSR(IP10_14_12, VI0_G5), 1356 PINMUX_IPSR_GPSR(IP10_14_12, VI2_FIELD), 1357 PINMUX_IPSR_MSEL(IP10_14_12, STP_OPWM_0_C, SEL_SSP_2), 1358 PINMUX_IPSR_MSEL(IP10_14_12, FMCLK_D, SEL_FM_3), 1359 PINMUX_IPSR_MSEL(IP10_14_12, CAN0_TX_E, SEL_CAN0_4), 1360 PINMUX_IPSR_MSEL(IP10_14_12, HTX1_D, SEL_HSCIF1_3), 1361 PINMUX_IPSR_MSEL(IP10_14_12, SCIFB0_TXD_D, SEL_SCIFB_3), 1362 PINMUX_IPSR_GPSR(IP10_16_15, VI0_G6), 1363 PINMUX_IPSR_GPSR(IP10_16_15, VI2_CLK), 1364 PINMUX_IPSR_MSEL(IP10_16_15, BPFCLK_D, SEL_FM_3), 1365 PINMUX_IPSR_GPSR(IP10_18_17, VI0_G7), 1366 PINMUX_IPSR_GPSR(IP10_18_17, VI2_DATA0), 1367 PINMUX_IPSR_MSEL(IP10_18_17, FMIN_D, SEL_FM_3), 1368 PINMUX_IPSR_GPSR(IP10_21_19, VI0_R0), 1369 PINMUX_IPSR_GPSR(IP10_21_19, VI2_DATA1), 1370 PINMUX_IPSR_MSEL(IP10_21_19, GLO_I0_B, SEL_GPS_1), 1371 PINMUX_IPSR_MSEL(IP10_21_19, TS_SDATA0_C, SEL_TSIF0_2), 1372 PINMUX_IPSR_GPSR(IP10_21_19, ATACS11_N), 1373 PINMUX_IPSR_GPSR(IP10_24_22, VI0_R1), 1374 PINMUX_IPSR_GPSR(IP10_24_22, VI2_DATA2), 1375 PINMUX_IPSR_MSEL(IP10_24_22, GLO_I1_B, SEL_GPS_1), 1376 PINMUX_IPSR_MSEL(IP10_24_22, TS_SCK0_C, SEL_TSIF0_2), 1377 PINMUX_IPSR_GPSR(IP10_24_22, ATAG1_N), 1378 PINMUX_IPSR_GPSR(IP10_26_25, VI0_R2), 1379 PINMUX_IPSR_GPSR(IP10_26_25, VI2_DATA3), 1380 PINMUX_IPSR_MSEL(IP10_26_25, GLO_Q0_B, SEL_GPS_1), 1381 PINMUX_IPSR_MSEL(IP10_26_25, TS_SDEN0_C, SEL_TSIF0_2), 1382 PINMUX_IPSR_GPSR(IP10_28_27, VI0_R3), 1383 PINMUX_IPSR_GPSR(IP10_28_27, VI2_DATA4), 1384 PINMUX_IPSR_MSEL(IP10_28_27, GLO_Q1_B, SEL_GPS_1), 1385 PINMUX_IPSR_MSEL(IP10_28_27, TS_SPSYNC0_C, SEL_TSIF0_2), 1386 PINMUX_IPSR_GPSR(IP10_31_29, VI0_R4), 1387 PINMUX_IPSR_GPSR(IP10_31_29, VI2_DATA5), 1388 PINMUX_IPSR_MSEL(IP10_31_29, GLO_SCLK_B, SEL_GPS_1), 1389 PINMUX_IPSR_MSEL(IP10_31_29, TX0_C, SEL_SCIF0_2), 1390 PINMUX_IPSR_MSEL(IP10_31_29, I2C1_SCL_D, SEL_I2C1_3), 1391 1392 /* IPSR11 */ 1393 PINMUX_IPSR_GPSR(IP11_2_0, VI0_R5), 1394 PINMUX_IPSR_GPSR(IP11_2_0, VI2_DATA6), 1395 PINMUX_IPSR_MSEL(IP11_2_0, GLO_SDATA_B, SEL_GPS_1), 1396 PINMUX_IPSR_MSEL(IP11_2_0, RX0_C, SEL_SCIF0_2), 1397 PINMUX_IPSR_MSEL(IP11_2_0, I2C1_SDA_D, SEL_I2C1_3), 1398 PINMUX_IPSR_GPSR(IP11_5_3, VI0_R6), 1399 PINMUX_IPSR_GPSR(IP11_5_3, VI2_DATA7), 1400 PINMUX_IPSR_MSEL(IP11_5_3, GLO_SS_B, SEL_GPS_1), 1401 PINMUX_IPSR_MSEL(IP11_5_3, TX1_C, SEL_SCIF1_2), 1402 PINMUX_IPSR_MSEL(IP11_5_3, I2C4_SCL_B, SEL_I2C4_1), 1403 PINMUX_IPSR_GPSR(IP11_8_6, VI0_R7), 1404 PINMUX_IPSR_MSEL(IP11_8_6, GLO_RFON_B, SEL_GPS_1), 1405 PINMUX_IPSR_MSEL(IP11_8_6, RX1_C, SEL_SCIF1_2), 1406 PINMUX_IPSR_MSEL(IP11_8_6, CAN0_RX_E, SEL_CAN0_4), 1407 PINMUX_IPSR_MSEL(IP11_8_6, I2C4_SDA_B, SEL_I2C4_1), 1408 PINMUX_IPSR_MSEL(IP11_8_6, HRX1_D, SEL_HSCIF1_3), 1409 PINMUX_IPSR_MSEL(IP11_8_6, SCIFB0_RXD_D, SEL_SCIFB_3), 1410 PINMUX_IPSR_MSEL(IP11_11_9, VI1_HSYNC_N, SEL_VI1_0), 1411 PINMUX_IPSR_GPSR(IP11_11_9, AVB_RXD0), 1412 PINMUX_IPSR_MSEL(IP11_11_9, TS_SDATA0_B, SEL_TSIF0_1), 1413 PINMUX_IPSR_MSEL(IP11_11_9, TX4_B, SEL_SCIF4_1), 1414 PINMUX_IPSR_MSEL(IP11_11_9, SCIFA4_TXD_B, SEL_SCIFA4_1), 1415 PINMUX_IPSR_MSEL(IP11_14_12, VI1_VSYNC_N, SEL_VI1_0), 1416 PINMUX_IPSR_GPSR(IP11_14_12, AVB_RXD1), 1417 PINMUX_IPSR_MSEL(IP11_14_12, TS_SCK0_B, SEL_TSIF0_1), 1418 PINMUX_IPSR_MSEL(IP11_14_12, RX4_B, SEL_SCIF4_1), 1419 PINMUX_IPSR_MSEL(IP11_14_12, SCIFA4_RXD_B, SEL_SCIFA4_1), 1420 PINMUX_IPSR_MSEL(IP11_16_15, VI1_CLKENB, SEL_VI1_0), 1421 PINMUX_IPSR_GPSR(IP11_16_15, AVB_RXD2), 1422 PINMUX_IPSR_MSEL(IP11_16_15, TS_SDEN0_B, SEL_TSIF0_1), 1423 PINMUX_IPSR_MSEL(IP11_18_17, VI1_FIELD, SEL_VI1_0), 1424 PINMUX_IPSR_GPSR(IP11_18_17, AVB_RXD3), 1425 PINMUX_IPSR_MSEL(IP11_18_17, TS_SPSYNC0_B, SEL_TSIF0_1), 1426 PINMUX_IPSR_MSEL(IP11_19, VI1_CLK, SEL_VI1_0), 1427 PINMUX_IPSR_GPSR(IP11_19, AVB_RXD4), 1428 PINMUX_IPSR_MSEL(IP11_20, VI1_DATA0, SEL_VI1_0), 1429 PINMUX_IPSR_GPSR(IP11_20, AVB_RXD5), 1430 PINMUX_IPSR_MSEL(IP11_21, VI1_DATA1, SEL_VI1_0), 1431 PINMUX_IPSR_GPSR(IP11_21, AVB_RXD6), 1432 PINMUX_IPSR_MSEL(IP11_22, VI1_DATA2, SEL_VI1_0), 1433 PINMUX_IPSR_GPSR(IP11_22, AVB_RXD7), 1434 PINMUX_IPSR_MSEL(IP11_23, VI1_DATA3, SEL_VI1_0), 1435 PINMUX_IPSR_GPSR(IP11_23, AVB_RX_ER), 1436 PINMUX_IPSR_MSEL(IP11_24, VI1_DATA4, SEL_VI1_0), 1437 PINMUX_IPSR_GPSR(IP11_24, AVB_MDIO), 1438 PINMUX_IPSR_MSEL(IP11_25, VI1_DATA5, SEL_VI1_0), 1439 PINMUX_IPSR_GPSR(IP11_25, AVB_RX_DV), 1440 PINMUX_IPSR_MSEL(IP11_26, VI1_DATA6, SEL_VI1_0), 1441 PINMUX_IPSR_GPSR(IP11_26, AVB_MAGIC), 1442 PINMUX_IPSR_MSEL(IP11_27, VI1_DATA7, SEL_VI1_0), 1443 PINMUX_IPSR_GPSR(IP11_27, AVB_MDC), 1444 PINMUX_IPSR_GPSR(IP11_29_28, ETH_MDIO), 1445 PINMUX_IPSR_GPSR(IP11_29_28, AVB_RX_CLK), 1446 PINMUX_IPSR_MSEL(IP11_29_28, I2C2_SCL_C, SEL_I2C2_2), 1447 PINMUX_IPSR_GPSR(IP11_31_30, ETH_CRS_DV), 1448 PINMUX_IPSR_GPSR(IP11_31_30, AVB_LINK), 1449 PINMUX_IPSR_MSEL(IP11_31_30, I2C2_SDA_C, SEL_I2C2_2), 1450 1451 /* IPSR12 */ 1452 PINMUX_IPSR_GPSR(IP12_1_0, ETH_RX_ER), 1453 PINMUX_IPSR_GPSR(IP12_1_0, AVB_CRS), 1454 PINMUX_IPSR_MSEL(IP12_1_0, I2C3_SCL, SEL_I2C3_0), 1455 PINMUX_IPSR_MSEL(IP12_1_0, IIC0_SCL, SEL_IIC0_0), 1456 PINMUX_IPSR_GPSR(IP12_3_2, ETH_RXD0), 1457 PINMUX_IPSR_GPSR(IP12_3_2, AVB_PHY_INT), 1458 PINMUX_IPSR_MSEL(IP12_3_2, I2C3_SDA, SEL_I2C3_0), 1459 PINMUX_IPSR_MSEL(IP12_3_2, IIC0_SDA, SEL_IIC0_0), 1460 PINMUX_IPSR_GPSR(IP12_6_4, ETH_RXD1), 1461 PINMUX_IPSR_GPSR(IP12_6_4, AVB_GTXREFCLK), 1462 PINMUX_IPSR_MSEL(IP12_6_4, CAN0_TX_C, SEL_CAN0_2), 1463 PINMUX_IPSR_MSEL(IP12_6_4, I2C2_SCL_D, SEL_I2C2_3), 1464 PINMUX_IPSR_MSEL(IP12_6_4, MSIOF1_RXD_E, SEL_SOF1_4), 1465 PINMUX_IPSR_GPSR(IP12_9_7, ETH_LINK), 1466 PINMUX_IPSR_GPSR(IP12_9_7, AVB_TXD0), 1467 PINMUX_IPSR_MSEL(IP12_9_7, CAN0_RX_C, SEL_CAN0_2), 1468 PINMUX_IPSR_MSEL(IP12_9_7, I2C2_SDA_D, SEL_I2C2_3), 1469 PINMUX_IPSR_MSEL(IP12_9_7, MSIOF1_SCK_E, SEL_SOF1_4), 1470 PINMUX_IPSR_GPSR(IP12_12_10, ETH_REFCLK), 1471 PINMUX_IPSR_GPSR(IP12_12_10, AVB_TXD1), 1472 PINMUX_IPSR_MSEL(IP12_12_10, SCIFA3_RXD_B, SEL_SCIFA3_1), 1473 PINMUX_IPSR_MSEL(IP12_12_10, CAN1_RX_C, SEL_CAN1_2), 1474 PINMUX_IPSR_MSEL(IP12_12_10, MSIOF1_SYNC_E, SEL_SOF1_4), 1475 PINMUX_IPSR_GPSR(IP12_15_13, ETH_TXD1), 1476 PINMUX_IPSR_GPSR(IP12_15_13, AVB_TXD2), 1477 PINMUX_IPSR_MSEL(IP12_15_13, SCIFA3_TXD_B, SEL_SCIFA3_1), 1478 PINMUX_IPSR_MSEL(IP12_15_13, CAN1_TX_C, SEL_CAN1_2), 1479 PINMUX_IPSR_MSEL(IP12_15_13, MSIOF1_TXD_E, SEL_SOF1_4), 1480 PINMUX_IPSR_GPSR(IP12_17_16, ETH_TX_EN), 1481 PINMUX_IPSR_GPSR(IP12_17_16, AVB_TXD3), 1482 PINMUX_IPSR_MSEL(IP12_17_16, TCLK1_B, SEL_TMU1_0), 1483 PINMUX_IPSR_MSEL(IP12_17_16, CAN_CLK_B, SEL_CANCLK_1), 1484 PINMUX_IPSR_GPSR(IP12_19_18, ETH_MAGIC), 1485 PINMUX_IPSR_GPSR(IP12_19_18, AVB_TXD4), 1486 PINMUX_IPSR_MSEL(IP12_19_18, IETX_C, SEL_IEB_2), 1487 PINMUX_IPSR_GPSR(IP12_21_20, ETH_TXD0), 1488 PINMUX_IPSR_GPSR(IP12_21_20, AVB_TXD5), 1489 PINMUX_IPSR_MSEL(IP12_21_20, IECLK_C, SEL_IEB_2), 1490 PINMUX_IPSR_GPSR(IP12_23_22, ETH_MDC), 1491 PINMUX_IPSR_GPSR(IP12_23_22, AVB_TXD6), 1492 PINMUX_IPSR_MSEL(IP12_23_22, IERX_C, SEL_IEB_2), 1493 PINMUX_IPSR_MSEL(IP12_26_24, STP_IVCXO27_0, SEL_SSP_0), 1494 PINMUX_IPSR_GPSR(IP12_26_24, AVB_TXD7), 1495 PINMUX_IPSR_MSEL(IP12_26_24, SCIFB2_TXD_D, SEL_SCIFB2_3), 1496 PINMUX_IPSR_MSEL(IP12_26_24, ADIDATA_B, SEL_RAD_1), 1497 PINMUX_IPSR_MSEL(IP12_26_24, MSIOF0_SYNC_C, SEL_SOF0_2), 1498 PINMUX_IPSR_MSEL(IP12_29_27, STP_ISCLK_0, SEL_SSP_0), 1499 PINMUX_IPSR_GPSR(IP12_29_27, AVB_TX_EN), 1500 PINMUX_IPSR_MSEL(IP12_29_27, SCIFB2_RXD_D, SEL_SCIFB2_3), 1501 PINMUX_IPSR_MSEL(IP12_29_27, ADICS_SAMP_B, SEL_RAD_1), 1502 PINMUX_IPSR_MSEL(IP12_29_27, MSIOF0_SCK_C, SEL_SOF0_2), 1503 1504 /* IPSR13 */ 1505 PINMUX_IPSR_MSEL(IP13_2_0, STP_ISD_0, SEL_SSP_0), 1506 PINMUX_IPSR_GPSR(IP13_2_0, AVB_TX_ER), 1507 PINMUX_IPSR_MSEL(IP13_2_0, SCIFB2_SCK_C, SEL_SCIFB2_2), 1508 PINMUX_IPSR_MSEL(IP13_2_0, ADICLK_B, SEL_RAD_1), 1509 PINMUX_IPSR_MSEL(IP13_2_0, MSIOF0_SS1_C, SEL_SOF0_2), 1510 PINMUX_IPSR_MSEL(IP13_4_3, STP_ISEN_0, SEL_SSP_0), 1511 PINMUX_IPSR_GPSR(IP13_4_3, AVB_TX_CLK), 1512 PINMUX_IPSR_MSEL(IP13_4_3, ADICHS0_B, SEL_RAD_1), 1513 PINMUX_IPSR_MSEL(IP13_4_3, MSIOF0_SS2_C, SEL_SOF0_2), 1514 PINMUX_IPSR_MSEL(IP13_6_5, STP_ISSYNC_0, SEL_SSP_0), 1515 PINMUX_IPSR_GPSR(IP13_6_5, AVB_COL), 1516 PINMUX_IPSR_MSEL(IP13_6_5, ADICHS1_B, SEL_RAD_1), 1517 PINMUX_IPSR_MSEL(IP13_6_5, MSIOF0_RXD_C, SEL_SOF0_2), 1518 PINMUX_IPSR_MSEL(IP13_9_7, STP_OPWM_0, SEL_SSP_0), 1519 PINMUX_IPSR_GPSR(IP13_9_7, AVB_GTX_CLK), 1520 PINMUX_IPSR_GPSR(IP13_9_7, PWM0_B), 1521 PINMUX_IPSR_MSEL(IP13_9_7, ADICHS2_B, SEL_RAD_1), 1522 PINMUX_IPSR_MSEL(IP13_9_7, MSIOF0_TXD_C, SEL_SOF0_2), 1523 PINMUX_IPSR_GPSR(IP13_10, SD0_CLK), 1524 PINMUX_IPSR_MSEL(IP13_10, SPCLK_B, SEL_QSP_1), 1525 PINMUX_IPSR_GPSR(IP13_11, SD0_CMD), 1526 PINMUX_IPSR_MSEL(IP13_11, MOSI_IO0_B, SEL_QSP_1), 1527 PINMUX_IPSR_GPSR(IP13_12, SD0_DATA0), 1528 PINMUX_IPSR_MSEL(IP13_12, MISO_IO1_B, SEL_QSP_1), 1529 PINMUX_IPSR_GPSR(IP13_13, SD0_DATA1), 1530 PINMUX_IPSR_MSEL(IP13_13, IO2_B, SEL_QSP_1), 1531 PINMUX_IPSR_GPSR(IP13_14, SD0_DATA2), 1532 PINMUX_IPSR_MSEL(IP13_14, IO3_B, SEL_QSP_1), 1533 PINMUX_IPSR_GPSR(IP13_15, SD0_DATA3), 1534 PINMUX_IPSR_MSEL(IP13_15, SSL_B, SEL_QSP_1), 1535 PINMUX_IPSR_GPSR(IP13_18_16, SD0_CD), 1536 PINMUX_IPSR_MSEL(IP13_18_16, MMC_D6_B, SEL_MMC_1), 1537 PINMUX_IPSR_MSEL(IP13_18_16, SIM0_RST_B, SEL_SIM_1), 1538 PINMUX_IPSR_MSEL(IP13_18_16, CAN0_RX_F, SEL_CAN0_5), 1539 PINMUX_IPSR_MSEL(IP13_18_16, SCIFA5_TXD_B, SEL_SCIFA5_1), 1540 PINMUX_IPSR_MSEL(IP13_18_16, TX3_C, SEL_SCIF3_2), 1541 PINMUX_IPSR_GPSR(IP13_21_19, SD0_WP), 1542 PINMUX_IPSR_MSEL(IP13_21_19, MMC_D7_B, SEL_MMC_1), 1543 PINMUX_IPSR_MSEL(IP13_21_19, SIM0_D_B, SEL_SIM_1), 1544 PINMUX_IPSR_MSEL(IP13_21_19, CAN0_TX_F, SEL_CAN0_5), 1545 PINMUX_IPSR_MSEL(IP13_21_19, SCIFA5_RXD_B, SEL_SCIFA5_1), 1546 PINMUX_IPSR_MSEL(IP13_21_19, RX3_C, SEL_SCIF3_2), 1547 PINMUX_IPSR_GPSR(IP13_22, SD1_CMD), 1548 PINMUX_IPSR_MSEL(IP13_22, REMOCON_B, SEL_RCN_1), 1549 PINMUX_IPSR_GPSR(IP13_24_23, SD1_DATA0), 1550 PINMUX_IPSR_MSEL(IP13_24_23, SPEEDIN_B, SEL_RSP_1), 1551 PINMUX_IPSR_GPSR(IP13_25, SD1_DATA1), 1552 PINMUX_IPSR_MSEL(IP13_25, IETX_B, SEL_IEB_1), 1553 PINMUX_IPSR_GPSR(IP13_26, SD1_DATA2), 1554 PINMUX_IPSR_MSEL(IP13_26, IECLK_B, SEL_IEB_1), 1555 PINMUX_IPSR_GPSR(IP13_27, SD1_DATA3), 1556 PINMUX_IPSR_MSEL(IP13_27, IERX_B, SEL_IEB_1), 1557 PINMUX_IPSR_GPSR(IP13_30_28, SD1_CD), 1558 PINMUX_IPSR_GPSR(IP13_30_28, PWM0), 1559 PINMUX_IPSR_GPSR(IP13_30_28, TPU_TO0), 1560 PINMUX_IPSR_MSEL(IP13_30_28, I2C1_SCL_C, SEL_I2C1_2), 1561 1562 /* IPSR14 */ 1563 PINMUX_IPSR_GPSR(IP14_1_0, SD1_WP), 1564 PINMUX_IPSR_GPSR(IP14_1_0, PWM1_B), 1565 PINMUX_IPSR_MSEL(IP14_1_0, I2C1_SDA_C, SEL_I2C1_2), 1566 PINMUX_IPSR_GPSR(IP14_2, SD2_CLK), 1567 PINMUX_IPSR_GPSR(IP14_2, MMC_CLK), 1568 PINMUX_IPSR_GPSR(IP14_3, SD2_CMD), 1569 PINMUX_IPSR_GPSR(IP14_3, MMC_CMD), 1570 PINMUX_IPSR_GPSR(IP14_4, SD2_DATA0), 1571 PINMUX_IPSR_GPSR(IP14_4, MMC_D0), 1572 PINMUX_IPSR_GPSR(IP14_5, SD2_DATA1), 1573 PINMUX_IPSR_GPSR(IP14_5, MMC_D1), 1574 PINMUX_IPSR_GPSR(IP14_6, SD2_DATA2), 1575 PINMUX_IPSR_GPSR(IP14_6, MMC_D2), 1576 PINMUX_IPSR_GPSR(IP14_7, SD2_DATA3), 1577 PINMUX_IPSR_GPSR(IP14_7, MMC_D3), 1578 PINMUX_IPSR_GPSR(IP14_10_8, SD2_CD), 1579 PINMUX_IPSR_GPSR(IP14_10_8, MMC_D4), 1580 PINMUX_IPSR_MSEL(IP14_10_8, IIC1_SCL_C, SEL_IIC1_2), 1581 PINMUX_IPSR_MSEL(IP14_10_8, TX5_B, SEL_SCIF5_1), 1582 PINMUX_IPSR_MSEL(IP14_10_8, SCIFA5_TXD_C, SEL_SCIFA5_2), 1583 PINMUX_IPSR_GPSR(IP14_13_11, SD2_WP), 1584 PINMUX_IPSR_GPSR(IP14_13_11, MMC_D5), 1585 PINMUX_IPSR_MSEL(IP14_13_11, IIC1_SDA_C, SEL_IIC1_2), 1586 PINMUX_IPSR_MSEL(IP14_13_11, RX5_B, SEL_SCIF5_1), 1587 PINMUX_IPSR_MSEL(IP14_13_11, SCIFA5_RXD_C, SEL_SCIFA5_2), 1588 PINMUX_IPSR_MSEL(IP14_16_14, MSIOF0_SCK, SEL_SOF0_0), 1589 PINMUX_IPSR_MSEL(IP14_16_14, RX2_C, SEL_SCIF2_2), 1590 PINMUX_IPSR_MSEL(IP14_16_14, ADIDATA, SEL_RAD_0), 1591 PINMUX_IPSR_MSEL(IP14_16_14, VI1_CLK_C, SEL_VI1_2), 1592 PINMUX_IPSR_GPSR(IP14_16_14, VI1_G0_B), 1593 PINMUX_IPSR_MSEL(IP14_19_17, MSIOF0_SYNC, SEL_SOF0_0), 1594 PINMUX_IPSR_MSEL(IP14_19_17, TX2_C, SEL_SCIF2_2), 1595 PINMUX_IPSR_MSEL(IP14_19_17, ADICS_SAMP, SEL_RAD_0), 1596 PINMUX_IPSR_MSEL(IP14_19_17, VI1_CLKENB_C, SEL_VI1_2), 1597 PINMUX_IPSR_GPSR(IP14_19_17, VI1_G1_B), 1598 PINMUX_IPSR_MSEL(IP14_22_20, MSIOF0_TXD, SEL_SOF0_0), 1599 PINMUX_IPSR_MSEL(IP14_22_20, ADICLK, SEL_RAD_0), 1600 PINMUX_IPSR_MSEL(IP14_22_20, VI1_FIELD_C, SEL_VI1_2), 1601 PINMUX_IPSR_GPSR(IP14_22_20, VI1_G2_B), 1602 PINMUX_IPSR_MSEL(IP14_25_23, MSIOF0_RXD, SEL_SOF0_0), 1603 PINMUX_IPSR_MSEL(IP14_25_23, ADICHS0, SEL_RAD_0), 1604 PINMUX_IPSR_MSEL(IP14_25_23, VI1_DATA0_C, SEL_VI1_2), 1605 PINMUX_IPSR_GPSR(IP14_25_23, VI1_G3_B), 1606 PINMUX_IPSR_MSEL(IP14_28_26, MSIOF0_SS1, SEL_SOF0_0), 1607 PINMUX_IPSR_MSEL(IP14_28_26, MMC_D6, SEL_MMC_0), 1608 PINMUX_IPSR_MSEL(IP14_28_26, ADICHS1, SEL_RAD_0), 1609 PINMUX_IPSR_MSEL(IP14_28_26, TX0_E, SEL_SCIF0_4), 1610 PINMUX_IPSR_MSEL(IP14_28_26, VI1_HSYNC_N_C, SEL_VI1_2), 1611 PINMUX_IPSR_MSEL(IP14_28_26, IIC0_SCL_C, SEL_IIC0_2), 1612 PINMUX_IPSR_GPSR(IP14_28_26, VI1_G4_B), 1613 PINMUX_IPSR_MSEL(IP14_31_29, MSIOF0_SS2, SEL_SOF0_0), 1614 PINMUX_IPSR_MSEL(IP14_31_29, MMC_D7, SEL_MMC_0), 1615 PINMUX_IPSR_MSEL(IP14_31_29, ADICHS2, SEL_RAD_0), 1616 PINMUX_IPSR_MSEL(IP14_31_29, RX0_E, SEL_SCIF0_4), 1617 PINMUX_IPSR_MSEL(IP14_31_29, VI1_VSYNC_N_C, SEL_VI1_2), 1618 PINMUX_IPSR_MSEL(IP14_31_29, IIC0_SDA_C, SEL_IIC0_2), 1619 PINMUX_IPSR_GPSR(IP14_31_29, VI1_G5_B), 1620 1621 /* IPSR15 */ 1622 PINMUX_IPSR_MSEL(IP15_1_0, SIM0_RST, SEL_SIM_0), 1623 PINMUX_IPSR_MSEL(IP15_1_0, IETX, SEL_IEB_0), 1624 PINMUX_IPSR_MSEL(IP15_1_0, CAN1_TX_D, SEL_CAN1_3), 1625 PINMUX_IPSR_GPSR(IP15_3_2, SIM0_CLK), 1626 PINMUX_IPSR_MSEL(IP15_3_2, IECLK, SEL_IEB_0), 1627 PINMUX_IPSR_MSEL(IP15_3_2, CAN_CLK_C, SEL_CANCLK_2), 1628 PINMUX_IPSR_MSEL(IP15_5_4, SIM0_D, SEL_SIM_0), 1629 PINMUX_IPSR_MSEL(IP15_5_4, IERX, SEL_IEB_0), 1630 PINMUX_IPSR_MSEL(IP15_5_4, CAN1_RX_D, SEL_CAN1_3), 1631 PINMUX_IPSR_MSEL(IP15_8_6, GPS_CLK, SEL_GPS_0), 1632 PINMUX_IPSR_MSEL(IP15_8_6, DU1_DOTCLKIN_C, SEL_DIS_2), 1633 PINMUX_IPSR_MSEL(IP15_8_6, AUDIO_CLKB_B, SEL_ADG_1), 1634 PINMUX_IPSR_GPSR(IP15_8_6, PWM5_B), 1635 PINMUX_IPSR_MSEL(IP15_8_6, SCIFA3_TXD_C, SEL_SCIFA3_2), 1636 PINMUX_IPSR_MSEL(IP15_11_9, GPS_SIGN, SEL_GPS_0), 1637 PINMUX_IPSR_MSEL(IP15_11_9, TX4_C, SEL_SCIF4_2), 1638 PINMUX_IPSR_MSEL(IP15_11_9, SCIFA4_TXD_C, SEL_SCIFA4_2), 1639 PINMUX_IPSR_GPSR(IP15_11_9, PWM5), 1640 PINMUX_IPSR_GPSR(IP15_11_9, VI1_G6_B), 1641 PINMUX_IPSR_MSEL(IP15_11_9, SCIFA3_RXD_C, SEL_SCIFA3_2), 1642 PINMUX_IPSR_MSEL(IP15_14_12, GPS_MAG, SEL_GPS_0), 1643 PINMUX_IPSR_MSEL(IP15_14_12, RX4_C, SEL_SCIF4_2), 1644 PINMUX_IPSR_MSEL(IP15_14_12, SCIFA4_RXD_C, SEL_SCIFA4_2), 1645 PINMUX_IPSR_GPSR(IP15_14_12, PWM6), 1646 PINMUX_IPSR_GPSR(IP15_14_12, VI1_G7_B), 1647 PINMUX_IPSR_MSEL(IP15_14_12, SCIFA3_SCK_C, SEL_SCIFA3_2), 1648 PINMUX_IPSR_MSEL(IP15_17_15, HCTS0_N, SEL_HSCIF0_0), 1649 PINMUX_IPSR_MSEL(IP15_17_15, SCIFB0_CTS_N, SEL_SCIFB_0), 1650 PINMUX_IPSR_MSEL(IP15_17_15, GLO_I0_C, SEL_GPS_2), 1651 PINMUX_IPSR_MSEL(IP15_17_15, TCLK1, SEL_TMU1_0), 1652 PINMUX_IPSR_MSEL(IP15_17_15, VI1_DATA1_C, SEL_VI1_2), 1653 PINMUX_IPSR_MSEL(IP15_20_18, HRTS0_N, SEL_HSCIF0_0), 1654 PINMUX_IPSR_MSEL(IP15_20_18, SCIFB0_RTS_N, SEL_SCIFB_0), 1655 PINMUX_IPSR_MSEL(IP15_20_18, GLO_I1_C, SEL_GPS_2), 1656 PINMUX_IPSR_MSEL(IP15_20_18, VI1_DATA2_C, SEL_VI1_2), 1657 PINMUX_IPSR_MSEL(IP15_23_21, HSCK0, SEL_HSCIF0_0), 1658 PINMUX_IPSR_MSEL(IP15_23_21, SCIFB0_SCK, SEL_SCIFB_0), 1659 PINMUX_IPSR_MSEL(IP15_23_21, GLO_Q0_C, SEL_GPS_2), 1660 PINMUX_IPSR_MSEL(IP15_23_21, CAN_CLK, SEL_CANCLK_0), 1661 PINMUX_IPSR_GPSR(IP15_23_21, TCLK2), 1662 PINMUX_IPSR_MSEL(IP15_23_21, VI1_DATA3_C, SEL_VI1_2), 1663 PINMUX_IPSR_MSEL(IP15_26_24, HRX0, SEL_HSCIF0_0), 1664 PINMUX_IPSR_MSEL(IP15_26_24, SCIFB0_RXD, SEL_SCIFB_0), 1665 PINMUX_IPSR_MSEL(IP15_26_24, GLO_Q1_C, SEL_GPS_2), 1666 PINMUX_IPSR_MSEL(IP15_26_24, CAN0_RX_B, SEL_CAN0_1), 1667 PINMUX_IPSR_MSEL(IP15_26_24, VI1_DATA4_C, SEL_VI1_2), 1668 PINMUX_IPSR_MSEL(IP15_29_27, HTX0, SEL_HSCIF0_0), 1669 PINMUX_IPSR_MSEL(IP15_29_27, SCIFB0_TXD, SEL_SCIFB_0), 1670 PINMUX_IPSR_MSEL(IP15_29_27, GLO_SCLK_C, SEL_GPS_2), 1671 PINMUX_IPSR_MSEL(IP15_29_27, CAN0_TX_B, SEL_CAN0_1), 1672 PINMUX_IPSR_MSEL(IP15_29_27, VI1_DATA5_C, SEL_VI1_2), 1673 1674 /* IPSR16 */ 1675 PINMUX_IPSR_MSEL(IP16_2_0, HRX1, SEL_HSCIF1_0), 1676 PINMUX_IPSR_MSEL(IP16_2_0, SCIFB1_RXD, SEL_SCIFB1_0), 1677 PINMUX_IPSR_GPSR(IP16_2_0, VI1_R0_B), 1678 PINMUX_IPSR_MSEL(IP16_2_0, GLO_SDATA_C, SEL_GPS_2), 1679 PINMUX_IPSR_MSEL(IP16_2_0, VI1_DATA6_C, SEL_VI1_2), 1680 PINMUX_IPSR_MSEL(IP16_5_3, HTX1, SEL_HSCIF1_0), 1681 PINMUX_IPSR_MSEL(IP16_5_3, SCIFB1_TXD, SEL_SCIFB1_0), 1682 PINMUX_IPSR_GPSR(IP16_5_3, VI1_R1_B), 1683 PINMUX_IPSR_MSEL(IP16_5_3, GLO_SS_C, SEL_GPS_2), 1684 PINMUX_IPSR_MSEL(IP16_5_3, VI1_DATA7_C, SEL_VI1_2), 1685 PINMUX_IPSR_MSEL(IP16_7_6, HSCK1, SEL_HSCIF1_0), 1686 PINMUX_IPSR_MSEL(IP16_7_6, SCIFB1_SCK, SEL_SCIFB1_0), 1687 PINMUX_IPSR_GPSR(IP16_7_6, MLB_CLK), 1688 PINMUX_IPSR_MSEL(IP16_7_6, GLO_RFON_C, SEL_GPS_2), 1689 PINMUX_IPSR_MSEL(IP16_9_8, HCTS1_N, SEL_HSCIF1_0), 1690 PINMUX_IPSR_GPSR(IP16_9_8, SCIFB1_CTS_N), 1691 PINMUX_IPSR_GPSR(IP16_9_8, MLB_SIG), 1692 PINMUX_IPSR_MSEL(IP16_9_8, CAN1_TX_B, SEL_CAN1_1), 1693 PINMUX_IPSR_MSEL(IP16_11_10, HRTS1_N, SEL_HSCIF1_0), 1694 PINMUX_IPSR_GPSR(IP16_11_10, SCIFB1_RTS_N), 1695 PINMUX_IPSR_GPSR(IP16_11_10, MLB_DAT), 1696 PINMUX_IPSR_MSEL(IP16_11_10, CAN1_RX_B, SEL_CAN1_1), 1697 }; 1698 1699 static const struct sh_pfc_pin pinmux_pins[] = { 1700 PINMUX_GPIO_GP_ALL(), 1701 }; 1702 1703 /* - ADI -------------------------------------------------------------------- */ 1704 static const unsigned int adi_common_pins[] = { 1705 /* ADIDATA, ADICS/SAMP, ADICLK */ 1706 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26), 1707 }; 1708 static const unsigned int adi_common_mux[] = { 1709 /* ADIDATA, ADICS/SAMP, ADICLK */ 1710 ADIDATA_MARK, ADICS_SAMP_MARK, ADICLK_MARK, 1711 }; 1712 static const unsigned int adi_chsel0_pins[] = { 1713 /* ADICHS 0 */ 1714 RCAR_GP_PIN(6, 27), 1715 }; 1716 static const unsigned int adi_chsel0_mux[] = { 1717 /* ADICHS 0 */ 1718 ADICHS0_MARK, 1719 }; 1720 static const unsigned int adi_chsel1_pins[] = { 1721 /* ADICHS 1 */ 1722 RCAR_GP_PIN(6, 28), 1723 }; 1724 static const unsigned int adi_chsel1_mux[] = { 1725 /* ADICHS 1 */ 1726 ADICHS1_MARK, 1727 }; 1728 static const unsigned int adi_chsel2_pins[] = { 1729 /* ADICHS 2 */ 1730 RCAR_GP_PIN(6, 29), 1731 }; 1732 static const unsigned int adi_chsel2_mux[] = { 1733 /* ADICHS 2 */ 1734 ADICHS2_MARK, 1735 }; 1736 static const unsigned int adi_common_b_pins[] = { 1737 /* ADIDATA B, ADICS/SAMP B, ADICLK B */ 1738 RCAR_GP_PIN(5, 25), RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 27), 1739 }; 1740 static const unsigned int adi_common_b_mux[] = { 1741 /* ADIDATA B, ADICS/SAMP B, ADICLK B */ 1742 ADIDATA_B_MARK, ADICS_SAMP_B_MARK, ADICLK_B_MARK, 1743 }; 1744 static const unsigned int adi_chsel0_b_pins[] = { 1745 /* ADICHS B 0 */ 1746 RCAR_GP_PIN(5, 28), 1747 }; 1748 static const unsigned int adi_chsel0_b_mux[] = { 1749 /* ADICHS B 0 */ 1750 ADICHS0_B_MARK, 1751 }; 1752 static const unsigned int adi_chsel1_b_pins[] = { 1753 /* ADICHS B 1 */ 1754 RCAR_GP_PIN(5, 29), 1755 }; 1756 static const unsigned int adi_chsel1_b_mux[] = { 1757 /* ADICHS B 1 */ 1758 ADICHS1_B_MARK, 1759 }; 1760 static const unsigned int adi_chsel2_b_pins[] = { 1761 /* ADICHS B 2 */ 1762 RCAR_GP_PIN(5, 30), 1763 }; 1764 static const unsigned int adi_chsel2_b_mux[] = { 1765 /* ADICHS B 2 */ 1766 ADICHS2_B_MARK, 1767 }; 1768 1769 /* - Audio Clock ------------------------------------------------------------ */ 1770 static const unsigned int audio_clk_a_pins[] = { 1771 /* CLK */ 1772 RCAR_GP_PIN(2, 28), 1773 }; 1774 1775 static const unsigned int audio_clk_a_mux[] = { 1776 AUDIO_CLKA_MARK, 1777 }; 1778 1779 static const unsigned int audio_clk_b_pins[] = { 1780 /* CLK */ 1781 RCAR_GP_PIN(2, 29), 1782 }; 1783 1784 static const unsigned int audio_clk_b_mux[] = { 1785 AUDIO_CLKB_MARK, 1786 }; 1787 1788 static const unsigned int audio_clk_b_b_pins[] = { 1789 /* CLK */ 1790 RCAR_GP_PIN(7, 20), 1791 }; 1792 1793 static const unsigned int audio_clk_b_b_mux[] = { 1794 AUDIO_CLKB_B_MARK, 1795 }; 1796 1797 static const unsigned int audio_clk_c_pins[] = { 1798 /* CLK */ 1799 RCAR_GP_PIN(2, 30), 1800 }; 1801 1802 static const unsigned int audio_clk_c_mux[] = { 1803 AUDIO_CLKC_MARK, 1804 }; 1805 1806 static const unsigned int audio_clkout_pins[] = { 1807 /* CLK */ 1808 RCAR_GP_PIN(2, 31), 1809 }; 1810 1811 static const unsigned int audio_clkout_mux[] = { 1812 AUDIO_CLKOUT_MARK, 1813 }; 1814 1815 /* - AVB -------------------------------------------------------------------- */ 1816 static const unsigned int avb_link_pins[] = { 1817 RCAR_GP_PIN(5, 14), 1818 }; 1819 static const unsigned int avb_link_mux[] = { 1820 AVB_LINK_MARK, 1821 }; 1822 static const unsigned int avb_magic_pins[] = { 1823 RCAR_GP_PIN(5, 11), 1824 }; 1825 static const unsigned int avb_magic_mux[] = { 1826 AVB_MAGIC_MARK, 1827 }; 1828 static const unsigned int avb_phy_int_pins[] = { 1829 RCAR_GP_PIN(5, 16), 1830 }; 1831 static const unsigned int avb_phy_int_mux[] = { 1832 AVB_PHY_INT_MARK, 1833 }; 1834 static const unsigned int avb_mdio_pins[] = { 1835 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 9), 1836 }; 1837 static const unsigned int avb_mdio_mux[] = { 1838 AVB_MDC_MARK, AVB_MDIO_MARK, 1839 }; 1840 static const unsigned int avb_mii_pins[] = { 1841 RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 20), 1842 RCAR_GP_PIN(5, 21), 1843 1844 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), 1845 RCAR_GP_PIN(5, 3), 1846 1847 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 10), 1848 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 27), 1849 RCAR_GP_PIN(5, 28), RCAR_GP_PIN(5, 29), 1850 }; 1851 static const unsigned int avb_mii_mux[] = { 1852 AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK, 1853 AVB_TXD3_MARK, 1854 1855 AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK, 1856 AVB_RXD3_MARK, 1857 1858 AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK, 1859 AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_ER_MARK, 1860 AVB_TX_CLK_MARK, AVB_COL_MARK, 1861 }; 1862 static const unsigned int avb_gmii_pins[] = { 1863 RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 20), 1864 RCAR_GP_PIN(5, 21), RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23), 1865 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25), 1866 1867 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), 1868 RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5), 1869 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7), 1870 1871 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 10), 1872 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 30), RCAR_GP_PIN(5, 17), 1873 RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 27), RCAR_GP_PIN(5, 28), 1874 RCAR_GP_PIN(5, 29), 1875 }; 1876 static const unsigned int avb_gmii_mux[] = { 1877 AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK, 1878 AVB_TXD3_MARK, AVB_TXD4_MARK, AVB_TXD5_MARK, 1879 AVB_TXD6_MARK, AVB_TXD7_MARK, 1880 1881 AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK, 1882 AVB_RXD3_MARK, AVB_RXD4_MARK, AVB_RXD5_MARK, 1883 AVB_RXD6_MARK, AVB_RXD7_MARK, 1884 1885 AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK, 1886 AVB_CRS_MARK, AVB_GTX_CLK_MARK, AVB_GTXREFCLK_MARK, 1887 AVB_TX_EN_MARK, AVB_TX_ER_MARK, AVB_TX_CLK_MARK, 1888 AVB_COL_MARK, 1889 }; 1890 1891 /* - CAN -------------------------------------------------------------------- */ 1892 1893 static const unsigned int can0_data_pins[] = { 1894 /* TX, RX */ 1895 RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 29), 1896 }; 1897 1898 static const unsigned int can0_data_mux[] = { 1899 CAN0_TX_MARK, CAN0_RX_MARK, 1900 }; 1901 1902 static const unsigned int can0_data_b_pins[] = { 1903 /* TX, RX */ 1904 RCAR_GP_PIN(7, 4), RCAR_GP_PIN(7, 3), 1905 }; 1906 1907 static const unsigned int can0_data_b_mux[] = { 1908 CAN0_TX_B_MARK, CAN0_RX_B_MARK, 1909 }; 1910 1911 static const unsigned int can0_data_c_pins[] = { 1912 /* TX, RX */ 1913 RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18), 1914 }; 1915 1916 static const unsigned int can0_data_c_mux[] = { 1917 CAN0_TX_C_MARK, CAN0_RX_C_MARK, 1918 }; 1919 1920 static const unsigned int can0_data_d_pins[] = { 1921 /* TX, RX */ 1922 RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 27), 1923 }; 1924 1925 static const unsigned int can0_data_d_mux[] = { 1926 CAN0_TX_D_MARK, CAN0_RX_D_MARK, 1927 }; 1928 1929 static const unsigned int can0_data_e_pins[] = { 1930 /* TX, RX */ 1931 RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 28), 1932 }; 1933 1934 static const unsigned int can0_data_e_mux[] = { 1935 CAN0_TX_E_MARK, CAN0_RX_E_MARK, 1936 }; 1937 1938 static const unsigned int can0_data_f_pins[] = { 1939 /* TX, RX */ 1940 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6), 1941 }; 1942 1943 static const unsigned int can0_data_f_mux[] = { 1944 CAN0_TX_F_MARK, CAN0_RX_F_MARK, 1945 }; 1946 1947 static const unsigned int can1_data_pins[] = { 1948 /* TX, RX */ 1949 RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 20), 1950 }; 1951 1952 static const unsigned int can1_data_mux[] = { 1953 CAN1_TX_MARK, CAN1_RX_MARK, 1954 }; 1955 1956 static const unsigned int can1_data_b_pins[] = { 1957 /* TX, RX */ 1958 RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9), 1959 }; 1960 1961 static const unsigned int can1_data_b_mux[] = { 1962 CAN1_TX_B_MARK, CAN1_RX_B_MARK, 1963 }; 1964 1965 static const unsigned int can1_data_c_pins[] = { 1966 /* TX, RX */ 1967 RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 19), 1968 }; 1969 1970 static const unsigned int can1_data_c_mux[] = { 1971 CAN1_TX_C_MARK, CAN1_RX_C_MARK, 1972 }; 1973 1974 static const unsigned int can1_data_d_pins[] = { 1975 /* TX, RX */ 1976 RCAR_GP_PIN(4, 29), RCAR_GP_PIN(4, 31), 1977 }; 1978 1979 static const unsigned int can1_data_d_mux[] = { 1980 CAN1_TX_D_MARK, CAN1_RX_D_MARK, 1981 }; 1982 1983 static const unsigned int can_clk_pins[] = { 1984 /* CLK */ 1985 RCAR_GP_PIN(7, 2), 1986 }; 1987 1988 static const unsigned int can_clk_mux[] = { 1989 CAN_CLK_MARK, 1990 }; 1991 1992 static const unsigned int can_clk_b_pins[] = { 1993 /* CLK */ 1994 RCAR_GP_PIN(5, 21), 1995 }; 1996 1997 static const unsigned int can_clk_b_mux[] = { 1998 CAN_CLK_B_MARK, 1999 }; 2000 2001 static const unsigned int can_clk_c_pins[] = { 2002 /* CLK */ 2003 RCAR_GP_PIN(4, 30), 2004 }; 2005 2006 static const unsigned int can_clk_c_mux[] = { 2007 CAN_CLK_C_MARK, 2008 }; 2009 2010 static const unsigned int can_clk_d_pins[] = { 2011 /* CLK */ 2012 RCAR_GP_PIN(7, 19), 2013 }; 2014 2015 static const unsigned int can_clk_d_mux[] = { 2016 CAN_CLK_D_MARK, 2017 }; 2018 2019 /* - DU --------------------------------------------------------------------- */ 2020 static const unsigned int du_rgb666_pins[] = { 2021 /* R[7:2], G[7:2], B[7:2] */ 2022 RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 5), 2023 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 2), 2024 RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13), 2025 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 10), 2026 RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21), 2027 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 18), 2028 }; 2029 static const unsigned int du_rgb666_mux[] = { 2030 DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK, 2031 DU1_DR3_MARK, DU1_DR2_MARK, 2032 DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK, 2033 DU1_DG3_MARK, DU1_DG2_MARK, 2034 DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK, 2035 DU1_DB3_MARK, DU1_DB2_MARK, 2036 }; 2037 static const unsigned int du_rgb888_pins[] = { 2038 /* R[7:0], G[7:0], B[7:0] */ 2039 RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 5), 2040 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 2), 2041 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0), 2042 RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13), 2043 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 10), 2044 RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8), 2045 RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21), 2046 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 18), 2047 RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16), 2048 }; 2049 static const unsigned int du_rgb888_mux[] = { 2050 DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK, 2051 DU1_DR3_MARK, DU1_DR2_MARK, DU1_DR1_MARK, DU1_DR0_MARK, 2052 DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK, 2053 DU1_DG3_MARK, DU1_DG2_MARK, DU1_DG1_MARK, DU1_DG0_MARK, 2054 DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK, 2055 DU1_DB3_MARK, DU1_DB2_MARK, DU1_DB1_MARK, DU1_DB0_MARK, 2056 }; 2057 static const unsigned int du_clk_out_0_pins[] = { 2058 /* CLKOUT */ 2059 RCAR_GP_PIN(3, 25), 2060 }; 2061 static const unsigned int du_clk_out_0_mux[] = { 2062 DU1_DOTCLKOUT0_MARK 2063 }; 2064 static const unsigned int du_clk_out_1_pins[] = { 2065 /* CLKOUT */ 2066 RCAR_GP_PIN(3, 26), 2067 }; 2068 static const unsigned int du_clk_out_1_mux[] = { 2069 DU1_DOTCLKOUT1_MARK 2070 }; 2071 static const unsigned int du_sync_pins[] = { 2072 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */ 2073 RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 27), 2074 }; 2075 static const unsigned int du_sync_mux[] = { 2076 DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK 2077 }; 2078 static const unsigned int du_oddf_pins[] = { 2079 /* EXDISP/EXODDF/EXCDE */ 2080 RCAR_GP_PIN(3, 29), 2081 }; 2082 static const unsigned int du_oddf_mux[] = { 2083 DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK, 2084 }; 2085 static const unsigned int du_cde_pins[] = { 2086 /* CDE */ 2087 RCAR_GP_PIN(3, 31), 2088 }; 2089 static const unsigned int du_cde_mux[] = { 2090 DU1_CDE_MARK, 2091 }; 2092 static const unsigned int du_disp_pins[] = { 2093 /* DISP */ 2094 RCAR_GP_PIN(3, 30), 2095 }; 2096 static const unsigned int du_disp_mux[] = { 2097 DU1_DISP_MARK, 2098 }; 2099 static const unsigned int du0_clk_in_pins[] = { 2100 /* CLKIN */ 2101 RCAR_GP_PIN(6, 31), 2102 }; 2103 static const unsigned int du0_clk_in_mux[] = { 2104 DU0_DOTCLKIN_MARK 2105 }; 2106 static const unsigned int du1_clk_in_pins[] = { 2107 /* CLKIN */ 2108 RCAR_GP_PIN(3, 24), 2109 }; 2110 static const unsigned int du1_clk_in_mux[] = { 2111 DU1_DOTCLKIN_MARK 2112 }; 2113 static const unsigned int du1_clk_in_b_pins[] = { 2114 /* CLKIN */ 2115 RCAR_GP_PIN(7, 19), 2116 }; 2117 static const unsigned int du1_clk_in_b_mux[] = { 2118 DU1_DOTCLKIN_B_MARK, 2119 }; 2120 static const unsigned int du1_clk_in_c_pins[] = { 2121 /* CLKIN */ 2122 RCAR_GP_PIN(7, 20), 2123 }; 2124 static const unsigned int du1_clk_in_c_mux[] = { 2125 DU1_DOTCLKIN_C_MARK, 2126 }; 2127 /* - ETH -------------------------------------------------------------------- */ 2128 static const unsigned int eth_link_pins[] = { 2129 /* LINK */ 2130 RCAR_GP_PIN(5, 18), 2131 }; 2132 static const unsigned int eth_link_mux[] = { 2133 ETH_LINK_MARK, 2134 }; 2135 static const unsigned int eth_magic_pins[] = { 2136 /* MAGIC */ 2137 RCAR_GP_PIN(5, 22), 2138 }; 2139 static const unsigned int eth_magic_mux[] = { 2140 ETH_MAGIC_MARK, 2141 }; 2142 static const unsigned int eth_mdio_pins[] = { 2143 /* MDC, MDIO */ 2144 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 13), 2145 }; 2146 static const unsigned int eth_mdio_mux[] = { 2147 ETH_MDC_MARK, ETH_MDIO_MARK, 2148 }; 2149 static const unsigned int eth_rmii_pins[] = { 2150 /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */ 2151 RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 15), 2152 RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 23), RCAR_GP_PIN(5, 20), 2153 RCAR_GP_PIN(5, 21), RCAR_GP_PIN(5, 19), 2154 }; 2155 static const unsigned int eth_rmii_mux[] = { 2156 ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK, 2157 ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REFCLK_MARK, 2158 }; 2159 2160 /* - HSCIF0 ----------------------------------------------------------------- */ 2161 static const unsigned int hscif0_data_pins[] = { 2162 /* RX, TX */ 2163 RCAR_GP_PIN(7, 3), RCAR_GP_PIN(7, 4), 2164 }; 2165 static const unsigned int hscif0_data_mux[] = { 2166 HRX0_MARK, HTX0_MARK, 2167 }; 2168 static const unsigned int hscif0_clk_pins[] = { 2169 /* SCK */ 2170 RCAR_GP_PIN(7, 2), 2171 }; 2172 static const unsigned int hscif0_clk_mux[] = { 2173 HSCK0_MARK, 2174 }; 2175 static const unsigned int hscif0_ctrl_pins[] = { 2176 /* RTS, CTS */ 2177 RCAR_GP_PIN(7, 1), RCAR_GP_PIN(7, 0), 2178 }; 2179 static const unsigned int hscif0_ctrl_mux[] = { 2180 HRTS0_N_MARK, HCTS0_N_MARK, 2181 }; 2182 static const unsigned int hscif0_data_b_pins[] = { 2183 /* RX, TX */ 2184 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 15), 2185 }; 2186 static const unsigned int hscif0_data_b_mux[] = { 2187 HRX0_B_MARK, HTX0_B_MARK, 2188 }; 2189 static const unsigned int hscif0_ctrl_b_pins[] = { 2190 /* RTS, CTS */ 2191 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13), 2192 }; 2193 static const unsigned int hscif0_ctrl_b_mux[] = { 2194 HRTS0_N_B_MARK, HCTS0_N_B_MARK, 2195 }; 2196 static const unsigned int hscif0_data_c_pins[] = { 2197 /* RX, TX */ 2198 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), 2199 }; 2200 static const unsigned int hscif0_data_c_mux[] = { 2201 HRX0_C_MARK, HTX0_C_MARK, 2202 }; 2203 static const unsigned int hscif0_clk_c_pins[] = { 2204 /* SCK */ 2205 RCAR_GP_PIN(5, 31), 2206 }; 2207 static const unsigned int hscif0_clk_c_mux[] = { 2208 HSCK0_C_MARK, 2209 }; 2210 /* - HSCIF1 ----------------------------------------------------------------- */ 2211 static const unsigned int hscif1_data_pins[] = { 2212 /* RX, TX */ 2213 RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6), 2214 }; 2215 static const unsigned int hscif1_data_mux[] = { 2216 HRX1_MARK, HTX1_MARK, 2217 }; 2218 static const unsigned int hscif1_clk_pins[] = { 2219 /* SCK */ 2220 RCAR_GP_PIN(7, 7), 2221 }; 2222 static const unsigned int hscif1_clk_mux[] = { 2223 HSCK1_MARK, 2224 }; 2225 static const unsigned int hscif1_ctrl_pins[] = { 2226 /* RTS, CTS */ 2227 RCAR_GP_PIN(7, 9), RCAR_GP_PIN(7, 8), 2228 }; 2229 static const unsigned int hscif1_ctrl_mux[] = { 2230 HRTS1_N_MARK, HCTS1_N_MARK, 2231 }; 2232 static const unsigned int hscif1_data_b_pins[] = { 2233 /* RX, TX */ 2234 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18), 2235 }; 2236 static const unsigned int hscif1_data_b_mux[] = { 2237 HRX1_B_MARK, HTX1_B_MARK, 2238 }; 2239 static const unsigned int hscif1_data_c_pins[] = { 2240 /* RX, TX */ 2241 RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 15), 2242 }; 2243 static const unsigned int hscif1_data_c_mux[] = { 2244 HRX1_C_MARK, HTX1_C_MARK, 2245 }; 2246 static const unsigned int hscif1_clk_c_pins[] = { 2247 /* SCK */ 2248 RCAR_GP_PIN(7, 16), 2249 }; 2250 static const unsigned int hscif1_clk_c_mux[] = { 2251 HSCK1_C_MARK, 2252 }; 2253 static const unsigned int hscif1_ctrl_c_pins[] = { 2254 /* RTS, CTS */ 2255 RCAR_GP_PIN(7, 18), RCAR_GP_PIN(7, 17), 2256 }; 2257 static const unsigned int hscif1_ctrl_c_mux[] = { 2258 HRTS1_N_C_MARK, HCTS1_N_C_MARK, 2259 }; 2260 static const unsigned int hscif1_data_d_pins[] = { 2261 /* RX, TX */ 2262 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 18), 2263 }; 2264 static const unsigned int hscif1_data_d_mux[] = { 2265 HRX1_D_MARK, HTX1_D_MARK, 2266 }; 2267 static const unsigned int hscif1_data_e_pins[] = { 2268 /* RX, TX */ 2269 RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 15), 2270 }; 2271 static const unsigned int hscif1_data_e_mux[] = { 2272 HRX1_C_MARK, HTX1_C_MARK, 2273 }; 2274 static const unsigned int hscif1_clk_e_pins[] = { 2275 /* SCK */ 2276 RCAR_GP_PIN(2, 6), 2277 }; 2278 static const unsigned int hscif1_clk_e_mux[] = { 2279 HSCK1_E_MARK, 2280 }; 2281 static const unsigned int hscif1_ctrl_e_pins[] = { 2282 /* RTS, CTS */ 2283 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 7), 2284 }; 2285 static const unsigned int hscif1_ctrl_e_mux[] = { 2286 HRTS1_N_E_MARK, HCTS1_N_E_MARK, 2287 }; 2288 /* - HSCIF2 ----------------------------------------------------------------- */ 2289 static const unsigned int hscif2_data_pins[] = { 2290 /* RX, TX */ 2291 RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17), 2292 }; 2293 static const unsigned int hscif2_data_mux[] = { 2294 HRX2_MARK, HTX2_MARK, 2295 }; 2296 static const unsigned int hscif2_clk_pins[] = { 2297 /* SCK */ 2298 RCAR_GP_PIN(4, 15), 2299 }; 2300 static const unsigned int hscif2_clk_mux[] = { 2301 HSCK2_MARK, 2302 }; 2303 static const unsigned int hscif2_ctrl_pins[] = { 2304 /* RTS, CTS */ 2305 RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13), 2306 }; 2307 static const unsigned int hscif2_ctrl_mux[] = { 2308 HRTS2_N_MARK, HCTS2_N_MARK, 2309 }; 2310 static const unsigned int hscif2_data_b_pins[] = { 2311 /* RX, TX */ 2312 RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 22), 2313 }; 2314 static const unsigned int hscif2_data_b_mux[] = { 2315 HRX2_B_MARK, HTX2_B_MARK, 2316 }; 2317 static const unsigned int hscif2_ctrl_b_pins[] = { 2318 /* RTS, CTS */ 2319 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 21), 2320 }; 2321 static const unsigned int hscif2_ctrl_b_mux[] = { 2322 HRTS2_N_B_MARK, HCTS2_N_B_MARK, 2323 }; 2324 static const unsigned int hscif2_data_c_pins[] = { 2325 /* RX, TX */ 2326 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), 2327 }; 2328 static const unsigned int hscif2_data_c_mux[] = { 2329 HRX2_C_MARK, HTX2_C_MARK, 2330 }; 2331 static const unsigned int hscif2_clk_c_pins[] = { 2332 /* SCK */ 2333 RCAR_GP_PIN(5, 31), 2334 }; 2335 static const unsigned int hscif2_clk_c_mux[] = { 2336 HSCK2_C_MARK, 2337 }; 2338 static const unsigned int hscif2_data_d_pins[] = { 2339 /* RX, TX */ 2340 RCAR_GP_PIN(1, 20), RCAR_GP_PIN(5, 31), 2341 }; 2342 static const unsigned int hscif2_data_d_mux[] = { 2343 HRX2_B_MARK, HTX2_D_MARK, 2344 }; 2345 /* - I2C0 ------------------------------------------------------------------- */ 2346 static const unsigned int i2c0_pins[] = { 2347 /* SCL, SDA */ 2348 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25), 2349 }; 2350 static const unsigned int i2c0_mux[] = { 2351 I2C0_SCL_MARK, I2C0_SDA_MARK, 2352 }; 2353 static const unsigned int i2c0_b_pins[] = { 2354 /* SCL, SDA */ 2355 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), 2356 }; 2357 static const unsigned int i2c0_b_mux[] = { 2358 I2C0_SCL_B_MARK, I2C0_SDA_B_MARK, 2359 }; 2360 static const unsigned int i2c0_c_pins[] = { 2361 /* SCL, SDA */ 2362 RCAR_GP_PIN(0, 16), RCAR_GP_PIN(1, 1), 2363 }; 2364 static const unsigned int i2c0_c_mux[] = { 2365 I2C0_SCL_C_MARK, I2C0_SDA_C_MARK, 2366 }; 2367 /* - I2C1 ------------------------------------------------------------------- */ 2368 static const unsigned int i2c1_pins[] = { 2369 /* SCL, SDA */ 2370 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 11), 2371 }; 2372 static const unsigned int i2c1_mux[] = { 2373 I2C1_SCL_MARK, I2C1_SDA_MARK, 2374 }; 2375 static const unsigned int i2c1_b_pins[] = { 2376 /* SCL, SDA */ 2377 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), 2378 }; 2379 static const unsigned int i2c1_b_mux[] = { 2380 I2C1_SCL_B_MARK, I2C1_SDA_B_MARK, 2381 }; 2382 static const unsigned int i2c1_c_pins[] = { 2383 /* SCL, SDA */ 2384 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15), 2385 }; 2386 static const unsigned int i2c1_c_mux[] = { 2387 I2C1_SCL_C_MARK, I2C1_SDA_C_MARK, 2388 }; 2389 static const unsigned int i2c1_d_pins[] = { 2390 /* SCL, SDA */ 2391 RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26), 2392 }; 2393 static const unsigned int i2c1_d_mux[] = { 2394 I2C1_SCL_D_MARK, I2C1_SDA_D_MARK, 2395 }; 2396 static const unsigned int i2c1_e_pins[] = { 2397 /* SCL, SDA */ 2398 RCAR_GP_PIN(7, 15), RCAR_GP_PIN(7, 16), 2399 }; 2400 static const unsigned int i2c1_e_mux[] = { 2401 I2C1_SCL_E_MARK, I2C1_SDA_E_MARK, 2402 }; 2403 /* - I2C2 ------------------------------------------------------------------- */ 2404 static const unsigned int i2c2_pins[] = { 2405 /* SCL, SDA */ 2406 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), 2407 }; 2408 static const unsigned int i2c2_mux[] = { 2409 I2C2_SCL_MARK, I2C2_SDA_MARK, 2410 }; 2411 static const unsigned int i2c2_b_pins[] = { 2412 /* SCL, SDA */ 2413 RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 29), 2414 }; 2415 static const unsigned int i2c2_b_mux[] = { 2416 I2C2_SCL_B_MARK, I2C2_SDA_B_MARK, 2417 }; 2418 static const unsigned int i2c2_c_pins[] = { 2419 /* SCL, SDA */ 2420 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14), 2421 }; 2422 static const unsigned int i2c2_c_mux[] = { 2423 I2C2_SCL_C_MARK, I2C2_SDA_C_MARK, 2424 }; 2425 static const unsigned int i2c2_d_pins[] = { 2426 /* SCL, SDA */ 2427 RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18), 2428 }; 2429 static const unsigned int i2c2_d_mux[] = { 2430 I2C2_SCL_D_MARK, I2C2_SDA_D_MARK, 2431 }; 2432 /* - I2C3 ------------------------------------------------------------------- */ 2433 static const unsigned int i2c3_pins[] = { 2434 /* SCL, SDA */ 2435 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16), 2436 }; 2437 static const unsigned int i2c3_mux[] = { 2438 I2C3_SCL_MARK, I2C3_SDA_MARK, 2439 }; 2440 static const unsigned int i2c3_b_pins[] = { 2441 /* SCL, SDA */ 2442 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16), 2443 }; 2444 static const unsigned int i2c3_b_mux[] = { 2445 I2C3_SCL_B_MARK, I2C3_SDA_B_MARK, 2446 }; 2447 static const unsigned int i2c3_c_pins[] = { 2448 /* SCL, SDA */ 2449 RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23), 2450 }; 2451 static const unsigned int i2c3_c_mux[] = { 2452 I2C3_SCL_C_MARK, I2C3_SDA_C_MARK, 2453 }; 2454 static const unsigned int i2c3_d_pins[] = { 2455 /* SCL, SDA */ 2456 RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28), 2457 }; 2458 static const unsigned int i2c3_d_mux[] = { 2459 I2C3_SCL_D_MARK, I2C3_SDA_D_MARK, 2460 }; 2461 /* - I2C4 ------------------------------------------------------------------- */ 2462 static const unsigned int i2c4_pins[] = { 2463 /* SCL, SDA */ 2464 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14), 2465 }; 2466 static const unsigned int i2c4_mux[] = { 2467 I2C4_SCL_MARK, I2C4_SDA_MARK, 2468 }; 2469 static const unsigned int i2c4_b_pins[] = { 2470 /* SCL, SDA */ 2471 RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28), 2472 }; 2473 static const unsigned int i2c4_b_mux[] = { 2474 I2C4_SCL_B_MARK, I2C4_SDA_B_MARK, 2475 }; 2476 static const unsigned int i2c4_c_pins[] = { 2477 /* SCL, SDA */ 2478 RCAR_GP_PIN(7, 13), RCAR_GP_PIN(7, 14), 2479 }; 2480 static const unsigned int i2c4_c_mux[] = { 2481 I2C4_SCL_C_MARK, I2C4_SDA_C_MARK, 2482 }; 2483 /* - I2C7 ------------------------------------------------------------------- */ 2484 static const unsigned int i2c7_pins[] = { 2485 /* SCL, SDA */ 2486 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16), 2487 }; 2488 static const unsigned int i2c7_mux[] = { 2489 IIC0_SCL_MARK, IIC0_SDA_MARK, 2490 }; 2491 static const unsigned int i2c7_b_pins[] = { 2492 /* SCL, SDA */ 2493 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), 2494 }; 2495 static const unsigned int i2c7_b_mux[] = { 2496 IIC0_SCL_B_MARK, IIC0_SDA_B_MARK, 2497 }; 2498 static const unsigned int i2c7_c_pins[] = { 2499 /* SCL, SDA */ 2500 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29), 2501 }; 2502 static const unsigned int i2c7_c_mux[] = { 2503 IIC0_SCL_C_MARK, IIC0_SDA_C_MARK, 2504 }; 2505 /* - I2C8 ------------------------------------------------------------------- */ 2506 static const unsigned int i2c8_pins[] = { 2507 /* SCL, SDA */ 2508 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14), 2509 }; 2510 static const unsigned int i2c8_mux[] = { 2511 IIC1_SCL_MARK, IIC1_SDA_MARK, 2512 }; 2513 static const unsigned int i2c8_b_pins[] = { 2514 /* SCL, SDA */ 2515 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), 2516 }; 2517 static const unsigned int i2c8_b_mux[] = { 2518 IIC1_SCL_B_MARK, IIC1_SDA_B_MARK, 2519 }; 2520 static const unsigned int i2c8_c_pins[] = { 2521 /* SCL, SDA */ 2522 RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23), 2523 }; 2524 static const unsigned int i2c8_c_mux[] = { 2525 IIC1_SCL_C_MARK, IIC1_SDA_C_MARK, 2526 }; 2527 /* - INTC ------------------------------------------------------------------- */ 2528 static const unsigned int intc_irq0_pins[] = { 2529 /* IRQ */ 2530 RCAR_GP_PIN(7, 10), 2531 }; 2532 static const unsigned int intc_irq0_mux[] = { 2533 IRQ0_MARK, 2534 }; 2535 static const unsigned int intc_irq1_pins[] = { 2536 /* IRQ */ 2537 RCAR_GP_PIN(7, 11), 2538 }; 2539 static const unsigned int intc_irq1_mux[] = { 2540 IRQ1_MARK, 2541 }; 2542 static const unsigned int intc_irq2_pins[] = { 2543 /* IRQ */ 2544 RCAR_GP_PIN(7, 12), 2545 }; 2546 static const unsigned int intc_irq2_mux[] = { 2547 IRQ2_MARK, 2548 }; 2549 static const unsigned int intc_irq3_pins[] = { 2550 /* IRQ */ 2551 RCAR_GP_PIN(7, 13), 2552 }; 2553 static const unsigned int intc_irq3_mux[] = { 2554 IRQ3_MARK, 2555 }; 2556 /* - MLB+ ------------------------------------------------------------------- */ 2557 static const unsigned int mlb_3pin_pins[] = { 2558 RCAR_GP_PIN(7, 7), RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9), 2559 }; 2560 static const unsigned int mlb_3pin_mux[] = { 2561 MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK, 2562 }; 2563 /* - MMCIF ------------------------------------------------------------------ */ 2564 static const unsigned int mmc_data1_pins[] = { 2565 /* D[0] */ 2566 RCAR_GP_PIN(6, 18), 2567 }; 2568 static const unsigned int mmc_data1_mux[] = { 2569 MMC_D0_MARK, 2570 }; 2571 static const unsigned int mmc_data4_pins[] = { 2572 /* D[0:3] */ 2573 RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19), 2574 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21), 2575 }; 2576 static const unsigned int mmc_data4_mux[] = { 2577 MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK, 2578 }; 2579 static const unsigned int mmc_data8_pins[] = { 2580 /* D[0:7] */ 2581 RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19), 2582 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21), 2583 RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23), 2584 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29), 2585 }; 2586 static const unsigned int mmc_data8_mux[] = { 2587 MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK, 2588 MMC_D4_MARK, MMC_D5_MARK, MMC_D6_MARK, MMC_D7_MARK, 2589 }; 2590 static const unsigned int mmc_data8_b_pins[] = { 2591 /* D[0:7] */ 2592 RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19), 2593 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21), 2594 RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23), 2595 RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 7), 2596 }; 2597 static const unsigned int mmc_data8_b_mux[] = { 2598 MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK, 2599 MMC_D4_MARK, MMC_D5_MARK, MMC_D6_B_MARK, MMC_D7_B_MARK, 2600 }; 2601 static const unsigned int mmc_ctrl_pins[] = { 2602 /* CLK, CMD */ 2603 RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17), 2604 }; 2605 static const unsigned int mmc_ctrl_mux[] = { 2606 MMC_CLK_MARK, MMC_CMD_MARK, 2607 }; 2608 /* - MSIOF0 ----------------------------------------------------------------- */ 2609 static const unsigned int msiof0_clk_pins[] = { 2610 /* SCK */ 2611 RCAR_GP_PIN(6, 24), 2612 }; 2613 static const unsigned int msiof0_clk_mux[] = { 2614 MSIOF0_SCK_MARK, 2615 }; 2616 static const unsigned int msiof0_sync_pins[] = { 2617 /* SYNC */ 2618 RCAR_GP_PIN(6, 25), 2619 }; 2620 static const unsigned int msiof0_sync_mux[] = { 2621 MSIOF0_SYNC_MARK, 2622 }; 2623 static const unsigned int msiof0_ss1_pins[] = { 2624 /* SS1 */ 2625 RCAR_GP_PIN(6, 28), 2626 }; 2627 static const unsigned int msiof0_ss1_mux[] = { 2628 MSIOF0_SS1_MARK, 2629 }; 2630 static const unsigned int msiof0_ss2_pins[] = { 2631 /* SS2 */ 2632 RCAR_GP_PIN(6, 29), 2633 }; 2634 static const unsigned int msiof0_ss2_mux[] = { 2635 MSIOF0_SS2_MARK, 2636 }; 2637 static const unsigned int msiof0_rx_pins[] = { 2638 /* RXD */ 2639 RCAR_GP_PIN(6, 27), 2640 }; 2641 static const unsigned int msiof0_rx_mux[] = { 2642 MSIOF0_RXD_MARK, 2643 }; 2644 static const unsigned int msiof0_tx_pins[] = { 2645 /* TXD */ 2646 RCAR_GP_PIN(6, 26), 2647 }; 2648 static const unsigned int msiof0_tx_mux[] = { 2649 MSIOF0_TXD_MARK, 2650 }; 2651 2652 static const unsigned int msiof0_clk_b_pins[] = { 2653 /* SCK */ 2654 RCAR_GP_PIN(0, 16), 2655 }; 2656 static const unsigned int msiof0_clk_b_mux[] = { 2657 MSIOF0_SCK_B_MARK, 2658 }; 2659 static const unsigned int msiof0_sync_b_pins[] = { 2660 /* SYNC */ 2661 RCAR_GP_PIN(0, 17), 2662 }; 2663 static const unsigned int msiof0_sync_b_mux[] = { 2664 MSIOF0_SYNC_B_MARK, 2665 }; 2666 static const unsigned int msiof0_ss1_b_pins[] = { 2667 /* SS1 */ 2668 RCAR_GP_PIN(0, 18), 2669 }; 2670 static const unsigned int msiof0_ss1_b_mux[] = { 2671 MSIOF0_SS1_B_MARK, 2672 }; 2673 static const unsigned int msiof0_ss2_b_pins[] = { 2674 /* SS2 */ 2675 RCAR_GP_PIN(0, 19), 2676 }; 2677 static const unsigned int msiof0_ss2_b_mux[] = { 2678 MSIOF0_SS2_B_MARK, 2679 }; 2680 static const unsigned int msiof0_rx_b_pins[] = { 2681 /* RXD */ 2682 RCAR_GP_PIN(0, 21), 2683 }; 2684 static const unsigned int msiof0_rx_b_mux[] = { 2685 MSIOF0_RXD_B_MARK, 2686 }; 2687 static const unsigned int msiof0_tx_b_pins[] = { 2688 /* TXD */ 2689 RCAR_GP_PIN(0, 20), 2690 }; 2691 static const unsigned int msiof0_tx_b_mux[] = { 2692 MSIOF0_TXD_B_MARK, 2693 }; 2694 2695 static const unsigned int msiof0_clk_c_pins[] = { 2696 /* SCK */ 2697 RCAR_GP_PIN(5, 26), 2698 }; 2699 static const unsigned int msiof0_clk_c_mux[] = { 2700 MSIOF0_SCK_C_MARK, 2701 }; 2702 static const unsigned int msiof0_sync_c_pins[] = { 2703 /* SYNC */ 2704 RCAR_GP_PIN(5, 25), 2705 }; 2706 static const unsigned int msiof0_sync_c_mux[] = { 2707 MSIOF0_SYNC_C_MARK, 2708 }; 2709 static const unsigned int msiof0_ss1_c_pins[] = { 2710 /* SS1 */ 2711 RCAR_GP_PIN(5, 27), 2712 }; 2713 static const unsigned int msiof0_ss1_c_mux[] = { 2714 MSIOF0_SS1_C_MARK, 2715 }; 2716 static const unsigned int msiof0_ss2_c_pins[] = { 2717 /* SS2 */ 2718 RCAR_GP_PIN(5, 28), 2719 }; 2720 static const unsigned int msiof0_ss2_c_mux[] = { 2721 MSIOF0_SS2_C_MARK, 2722 }; 2723 static const unsigned int msiof0_rx_c_pins[] = { 2724 /* RXD */ 2725 RCAR_GP_PIN(5, 29), 2726 }; 2727 static const unsigned int msiof0_rx_c_mux[] = { 2728 MSIOF0_RXD_C_MARK, 2729 }; 2730 static const unsigned int msiof0_tx_c_pins[] = { 2731 /* TXD */ 2732 RCAR_GP_PIN(5, 30), 2733 }; 2734 static const unsigned int msiof0_tx_c_mux[] = { 2735 MSIOF0_TXD_C_MARK, 2736 }; 2737 /* - MSIOF1 ----------------------------------------------------------------- */ 2738 static const unsigned int msiof1_clk_pins[] = { 2739 /* SCK */ 2740 RCAR_GP_PIN(0, 22), 2741 }; 2742 static const unsigned int msiof1_clk_mux[] = { 2743 MSIOF1_SCK_MARK, 2744 }; 2745 static const unsigned int msiof1_sync_pins[] = { 2746 /* SYNC */ 2747 RCAR_GP_PIN(0, 23), 2748 }; 2749 static const unsigned int msiof1_sync_mux[] = { 2750 MSIOF1_SYNC_MARK, 2751 }; 2752 static const unsigned int msiof1_ss1_pins[] = { 2753 /* SS1 */ 2754 RCAR_GP_PIN(0, 24), 2755 }; 2756 static const unsigned int msiof1_ss1_mux[] = { 2757 MSIOF1_SS1_MARK, 2758 }; 2759 static const unsigned int msiof1_ss2_pins[] = { 2760 /* SS2 */ 2761 RCAR_GP_PIN(0, 25), 2762 }; 2763 static const unsigned int msiof1_ss2_mux[] = { 2764 MSIOF1_SS2_MARK, 2765 }; 2766 static const unsigned int msiof1_rx_pins[] = { 2767 /* RXD */ 2768 RCAR_GP_PIN(0, 27), 2769 }; 2770 static const unsigned int msiof1_rx_mux[] = { 2771 MSIOF1_RXD_MARK, 2772 }; 2773 static const unsigned int msiof1_tx_pins[] = { 2774 /* TXD */ 2775 RCAR_GP_PIN(0, 26), 2776 }; 2777 static const unsigned int msiof1_tx_mux[] = { 2778 MSIOF1_TXD_MARK, 2779 }; 2780 2781 static const unsigned int msiof1_clk_b_pins[] = { 2782 /* SCK */ 2783 RCAR_GP_PIN(2, 29), 2784 }; 2785 static const unsigned int msiof1_clk_b_mux[] = { 2786 MSIOF1_SCK_B_MARK, 2787 }; 2788 static const unsigned int msiof1_sync_b_pins[] = { 2789 /* SYNC */ 2790 RCAR_GP_PIN(2, 30), 2791 }; 2792 static const unsigned int msiof1_sync_b_mux[] = { 2793 MSIOF1_SYNC_B_MARK, 2794 }; 2795 static const unsigned int msiof1_ss1_b_pins[] = { 2796 /* SS1 */ 2797 RCAR_GP_PIN(2, 31), 2798 }; 2799 static const unsigned int msiof1_ss1_b_mux[] = { 2800 MSIOF1_SS1_B_MARK, 2801 }; 2802 static const unsigned int msiof1_ss2_b_pins[] = { 2803 /* SS2 */ 2804 RCAR_GP_PIN(7, 16), 2805 }; 2806 static const unsigned int msiof1_ss2_b_mux[] = { 2807 MSIOF1_SS2_B_MARK, 2808 }; 2809 static const unsigned int msiof1_rx_b_pins[] = { 2810 /* RXD */ 2811 RCAR_GP_PIN(7, 18), 2812 }; 2813 static const unsigned int msiof1_rx_b_mux[] = { 2814 MSIOF1_RXD_B_MARK, 2815 }; 2816 static const unsigned int msiof1_tx_b_pins[] = { 2817 /* TXD */ 2818 RCAR_GP_PIN(7, 17), 2819 }; 2820 static const unsigned int msiof1_tx_b_mux[] = { 2821 MSIOF1_TXD_B_MARK, 2822 }; 2823 2824 static const unsigned int msiof1_clk_c_pins[] = { 2825 /* SCK */ 2826 RCAR_GP_PIN(2, 15), 2827 }; 2828 static const unsigned int msiof1_clk_c_mux[] = { 2829 MSIOF1_SCK_C_MARK, 2830 }; 2831 static const unsigned int msiof1_sync_c_pins[] = { 2832 /* SYNC */ 2833 RCAR_GP_PIN(2, 16), 2834 }; 2835 static const unsigned int msiof1_sync_c_mux[] = { 2836 MSIOF1_SYNC_C_MARK, 2837 }; 2838 static const unsigned int msiof1_rx_c_pins[] = { 2839 /* RXD */ 2840 RCAR_GP_PIN(2, 18), 2841 }; 2842 static const unsigned int msiof1_rx_c_mux[] = { 2843 MSIOF1_RXD_C_MARK, 2844 }; 2845 static const unsigned int msiof1_tx_c_pins[] = { 2846 /* TXD */ 2847 RCAR_GP_PIN(2, 17), 2848 }; 2849 static const unsigned int msiof1_tx_c_mux[] = { 2850 MSIOF1_TXD_C_MARK, 2851 }; 2852 2853 static const unsigned int msiof1_clk_d_pins[] = { 2854 /* SCK */ 2855 RCAR_GP_PIN(0, 28), 2856 }; 2857 static const unsigned int msiof1_clk_d_mux[] = { 2858 MSIOF1_SCK_D_MARK, 2859 }; 2860 static const unsigned int msiof1_sync_d_pins[] = { 2861 /* SYNC */ 2862 RCAR_GP_PIN(0, 30), 2863 }; 2864 static const unsigned int msiof1_sync_d_mux[] = { 2865 MSIOF1_SYNC_D_MARK, 2866 }; 2867 static const unsigned int msiof1_ss1_d_pins[] = { 2868 /* SS1 */ 2869 RCAR_GP_PIN(0, 29), 2870 }; 2871 static const unsigned int msiof1_ss1_d_mux[] = { 2872 MSIOF1_SS1_D_MARK, 2873 }; 2874 static const unsigned int msiof1_rx_d_pins[] = { 2875 /* RXD */ 2876 RCAR_GP_PIN(0, 27), 2877 }; 2878 static const unsigned int msiof1_rx_d_mux[] = { 2879 MSIOF1_RXD_D_MARK, 2880 }; 2881 static const unsigned int msiof1_tx_d_pins[] = { 2882 /* TXD */ 2883 RCAR_GP_PIN(0, 26), 2884 }; 2885 static const unsigned int msiof1_tx_d_mux[] = { 2886 MSIOF1_TXD_D_MARK, 2887 }; 2888 2889 static const unsigned int msiof1_clk_e_pins[] = { 2890 /* SCK */ 2891 RCAR_GP_PIN(5, 18), 2892 }; 2893 static const unsigned int msiof1_clk_e_mux[] = { 2894 MSIOF1_SCK_E_MARK, 2895 }; 2896 static const unsigned int msiof1_sync_e_pins[] = { 2897 /* SYNC */ 2898 RCAR_GP_PIN(5, 19), 2899 }; 2900 static const unsigned int msiof1_sync_e_mux[] = { 2901 MSIOF1_SYNC_E_MARK, 2902 }; 2903 static const unsigned int msiof1_rx_e_pins[] = { 2904 /* RXD */ 2905 RCAR_GP_PIN(5, 17), 2906 }; 2907 static const unsigned int msiof1_rx_e_mux[] = { 2908 MSIOF1_RXD_E_MARK, 2909 }; 2910 static const unsigned int msiof1_tx_e_pins[] = { 2911 /* TXD */ 2912 RCAR_GP_PIN(5, 20), 2913 }; 2914 static const unsigned int msiof1_tx_e_mux[] = { 2915 MSIOF1_TXD_E_MARK, 2916 }; 2917 /* - MSIOF2 ----------------------------------------------------------------- */ 2918 static const unsigned int msiof2_clk_pins[] = { 2919 /* SCK */ 2920 RCAR_GP_PIN(1, 13), 2921 }; 2922 static const unsigned int msiof2_clk_mux[] = { 2923 MSIOF2_SCK_MARK, 2924 }; 2925 static const unsigned int msiof2_sync_pins[] = { 2926 /* SYNC */ 2927 RCAR_GP_PIN(1, 14), 2928 }; 2929 static const unsigned int msiof2_sync_mux[] = { 2930 MSIOF2_SYNC_MARK, 2931 }; 2932 static const unsigned int msiof2_ss1_pins[] = { 2933 /* SS1 */ 2934 RCAR_GP_PIN(1, 17), 2935 }; 2936 static const unsigned int msiof2_ss1_mux[] = { 2937 MSIOF2_SS1_MARK, 2938 }; 2939 static const unsigned int msiof2_ss2_pins[] = { 2940 /* SS2 */ 2941 RCAR_GP_PIN(1, 18), 2942 }; 2943 static const unsigned int msiof2_ss2_mux[] = { 2944 MSIOF2_SS2_MARK, 2945 }; 2946 static const unsigned int msiof2_rx_pins[] = { 2947 /* RXD */ 2948 RCAR_GP_PIN(1, 16), 2949 }; 2950 static const unsigned int msiof2_rx_mux[] = { 2951 MSIOF2_RXD_MARK, 2952 }; 2953 static const unsigned int msiof2_tx_pins[] = { 2954 /* TXD */ 2955 RCAR_GP_PIN(1, 15), 2956 }; 2957 static const unsigned int msiof2_tx_mux[] = { 2958 MSIOF2_TXD_MARK, 2959 }; 2960 2961 static const unsigned int msiof2_clk_b_pins[] = { 2962 /* SCK */ 2963 RCAR_GP_PIN(3, 0), 2964 }; 2965 static const unsigned int msiof2_clk_b_mux[] = { 2966 MSIOF2_SCK_B_MARK, 2967 }; 2968 static const unsigned int msiof2_sync_b_pins[] = { 2969 /* SYNC */ 2970 RCAR_GP_PIN(3, 1), 2971 }; 2972 static const unsigned int msiof2_sync_b_mux[] = { 2973 MSIOF2_SYNC_B_MARK, 2974 }; 2975 static const unsigned int msiof2_ss1_b_pins[] = { 2976 /* SS1 */ 2977 RCAR_GP_PIN(3, 8), 2978 }; 2979 static const unsigned int msiof2_ss1_b_mux[] = { 2980 MSIOF2_SS1_B_MARK, 2981 }; 2982 static const unsigned int msiof2_ss2_b_pins[] = { 2983 /* SS2 */ 2984 RCAR_GP_PIN(3, 9), 2985 }; 2986 static const unsigned int msiof2_ss2_b_mux[] = { 2987 MSIOF2_SS2_B_MARK, 2988 }; 2989 static const unsigned int msiof2_rx_b_pins[] = { 2990 /* RXD */ 2991 RCAR_GP_PIN(3, 17), 2992 }; 2993 static const unsigned int msiof2_rx_b_mux[] = { 2994 MSIOF2_RXD_B_MARK, 2995 }; 2996 static const unsigned int msiof2_tx_b_pins[] = { 2997 /* TXD */ 2998 RCAR_GP_PIN(3, 16), 2999 }; 3000 static const unsigned int msiof2_tx_b_mux[] = { 3001 MSIOF2_TXD_B_MARK, 3002 }; 3003 3004 static const unsigned int msiof2_clk_c_pins[] = { 3005 /* SCK */ 3006 RCAR_GP_PIN(2, 2), 3007 }; 3008 static const unsigned int msiof2_clk_c_mux[] = { 3009 MSIOF2_SCK_C_MARK, 3010 }; 3011 static const unsigned int msiof2_sync_c_pins[] = { 3012 /* SYNC */ 3013 RCAR_GP_PIN(2, 3), 3014 }; 3015 static const unsigned int msiof2_sync_c_mux[] = { 3016 MSIOF2_SYNC_C_MARK, 3017 }; 3018 static const unsigned int msiof2_rx_c_pins[] = { 3019 /* RXD */ 3020 RCAR_GP_PIN(2, 5), 3021 }; 3022 static const unsigned int msiof2_rx_c_mux[] = { 3023 MSIOF2_RXD_C_MARK, 3024 }; 3025 static const unsigned int msiof2_tx_c_pins[] = { 3026 /* TXD */ 3027 RCAR_GP_PIN(2, 4), 3028 }; 3029 static const unsigned int msiof2_tx_c_mux[] = { 3030 MSIOF2_TXD_C_MARK, 3031 }; 3032 3033 static const unsigned int msiof2_clk_d_pins[] = { 3034 /* SCK */ 3035 RCAR_GP_PIN(2, 14), 3036 }; 3037 static const unsigned int msiof2_clk_d_mux[] = { 3038 MSIOF2_SCK_D_MARK, 3039 }; 3040 static const unsigned int msiof2_sync_d_pins[] = { 3041 /* SYNC */ 3042 RCAR_GP_PIN(2, 15), 3043 }; 3044 static const unsigned int msiof2_sync_d_mux[] = { 3045 MSIOF2_SYNC_D_MARK, 3046 }; 3047 static const unsigned int msiof2_ss1_d_pins[] = { 3048 /* SS1 */ 3049 RCAR_GP_PIN(2, 17), 3050 }; 3051 static const unsigned int msiof2_ss1_d_mux[] = { 3052 MSIOF2_SS1_D_MARK, 3053 }; 3054 static const unsigned int msiof2_ss2_d_pins[] = { 3055 /* SS2 */ 3056 RCAR_GP_PIN(2, 19), 3057 }; 3058 static const unsigned int msiof2_ss2_d_mux[] = { 3059 MSIOF2_SS2_D_MARK, 3060 }; 3061 static const unsigned int msiof2_rx_d_pins[] = { 3062 /* RXD */ 3063 RCAR_GP_PIN(2, 18), 3064 }; 3065 static const unsigned int msiof2_rx_d_mux[] = { 3066 MSIOF2_RXD_D_MARK, 3067 }; 3068 static const unsigned int msiof2_tx_d_pins[] = { 3069 /* TXD */ 3070 RCAR_GP_PIN(2, 16), 3071 }; 3072 static const unsigned int msiof2_tx_d_mux[] = { 3073 MSIOF2_TXD_D_MARK, 3074 }; 3075 3076 static const unsigned int msiof2_clk_e_pins[] = { 3077 /* SCK */ 3078 RCAR_GP_PIN(7, 15), 3079 }; 3080 static const unsigned int msiof2_clk_e_mux[] = { 3081 MSIOF2_SCK_E_MARK, 3082 }; 3083 static const unsigned int msiof2_sync_e_pins[] = { 3084 /* SYNC */ 3085 RCAR_GP_PIN(7, 16), 3086 }; 3087 static const unsigned int msiof2_sync_e_mux[] = { 3088 MSIOF2_SYNC_E_MARK, 3089 }; 3090 static const unsigned int msiof2_rx_e_pins[] = { 3091 /* RXD */ 3092 RCAR_GP_PIN(7, 14), 3093 }; 3094 static const unsigned int msiof2_rx_e_mux[] = { 3095 MSIOF2_RXD_E_MARK, 3096 }; 3097 static const unsigned int msiof2_tx_e_pins[] = { 3098 /* TXD */ 3099 RCAR_GP_PIN(7, 13), 3100 }; 3101 static const unsigned int msiof2_tx_e_mux[] = { 3102 MSIOF2_TXD_E_MARK, 3103 }; 3104 /* - PWM -------------------------------------------------------------------- */ 3105 static const unsigned int pwm0_pins[] = { 3106 RCAR_GP_PIN(6, 14), 3107 }; 3108 static const unsigned int pwm0_mux[] = { 3109 PWM0_MARK, 3110 }; 3111 static const unsigned int pwm0_b_pins[] = { 3112 RCAR_GP_PIN(5, 30), 3113 }; 3114 static const unsigned int pwm0_b_mux[] = { 3115 PWM0_B_MARK, 3116 }; 3117 static const unsigned int pwm1_pins[] = { 3118 RCAR_GP_PIN(1, 17), 3119 }; 3120 static const unsigned int pwm1_mux[] = { 3121 PWM1_MARK, 3122 }; 3123 static const unsigned int pwm1_b_pins[] = { 3124 RCAR_GP_PIN(6, 15), 3125 }; 3126 static const unsigned int pwm1_b_mux[] = { 3127 PWM1_B_MARK, 3128 }; 3129 static const unsigned int pwm2_pins[] = { 3130 RCAR_GP_PIN(1, 18), 3131 }; 3132 static const unsigned int pwm2_mux[] = { 3133 PWM2_MARK, 3134 }; 3135 static const unsigned int pwm2_b_pins[] = { 3136 RCAR_GP_PIN(0, 16), 3137 }; 3138 static const unsigned int pwm2_b_mux[] = { 3139 PWM2_B_MARK, 3140 }; 3141 static const unsigned int pwm3_pins[] = { 3142 RCAR_GP_PIN(1, 24), 3143 }; 3144 static const unsigned int pwm3_mux[] = { 3145 PWM3_MARK, 3146 }; 3147 static const unsigned int pwm4_pins[] = { 3148 RCAR_GP_PIN(3, 26), 3149 }; 3150 static const unsigned int pwm4_mux[] = { 3151 PWM4_MARK, 3152 }; 3153 static const unsigned int pwm4_b_pins[] = { 3154 RCAR_GP_PIN(3, 31), 3155 }; 3156 static const unsigned int pwm4_b_mux[] = { 3157 PWM4_B_MARK, 3158 }; 3159 static const unsigned int pwm5_pins[] = { 3160 RCAR_GP_PIN(7, 21), 3161 }; 3162 static const unsigned int pwm5_mux[] = { 3163 PWM5_MARK, 3164 }; 3165 static const unsigned int pwm5_b_pins[] = { 3166 RCAR_GP_PIN(7, 20), 3167 }; 3168 static const unsigned int pwm5_b_mux[] = { 3169 PWM5_B_MARK, 3170 }; 3171 static const unsigned int pwm6_pins[] = { 3172 RCAR_GP_PIN(7, 22), 3173 }; 3174 static const unsigned int pwm6_mux[] = { 3175 PWM6_MARK, 3176 }; 3177 /* - QSPI ------------------------------------------------------------------- */ 3178 static const unsigned int qspi_ctrl_pins[] = { 3179 /* SPCLK, SSL */ 3180 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 9), 3181 }; 3182 static const unsigned int qspi_ctrl_mux[] = { 3183 SPCLK_MARK, SSL_MARK, 3184 }; 3185 static const unsigned int qspi_data2_pins[] = { 3186 /* MOSI_IO0, MISO_IO1 */ 3187 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), 3188 }; 3189 static const unsigned int qspi_data2_mux[] = { 3190 MOSI_IO0_MARK, MISO_IO1_MARK, 3191 }; 3192 static const unsigned int qspi_data4_pins[] = { 3193 /* MOSI_IO0, MISO_IO1, IO2, IO3 */ 3194 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 3195 RCAR_GP_PIN(1, 8), 3196 }; 3197 static const unsigned int qspi_data4_mux[] = { 3198 MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK, 3199 }; 3200 3201 static const unsigned int qspi_ctrl_b_pins[] = { 3202 /* SPCLK, SSL */ 3203 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 5), 3204 }; 3205 static const unsigned int qspi_ctrl_b_mux[] = { 3206 SPCLK_B_MARK, SSL_B_MARK, 3207 }; 3208 static const unsigned int qspi_data2_b_pins[] = { 3209 /* MOSI_IO0, MISO_IO1 */ 3210 RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 2), 3211 }; 3212 static const unsigned int qspi_data2_b_mux[] = { 3213 MOSI_IO0_B_MARK, MISO_IO1_B_MARK, 3214 }; 3215 static const unsigned int qspi_data4_b_pins[] = { 3216 /* MOSI_IO0, MISO_IO1, IO2, IO3 */ 3217 RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3), 3218 RCAR_GP_PIN(6, 4), 3219 }; 3220 static const unsigned int qspi_data4_b_mux[] = { 3221 MOSI_IO0_B_MARK, MISO_IO1_B_MARK, IO2_B_MARK, IO3_B_MARK, 3222 }; 3223 /* - SCIF0 ------------------------------------------------------------------ */ 3224 static const unsigned int scif0_data_pins[] = { 3225 /* RX, TX */ 3226 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), 3227 }; 3228 static const unsigned int scif0_data_mux[] = { 3229 RX0_MARK, TX0_MARK, 3230 }; 3231 static const unsigned int scif0_data_b_pins[] = { 3232 /* RX, TX */ 3233 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0), 3234 }; 3235 static const unsigned int scif0_data_b_mux[] = { 3236 RX0_B_MARK, TX0_B_MARK, 3237 }; 3238 static const unsigned int scif0_data_c_pins[] = { 3239 /* RX, TX */ 3240 RCAR_GP_PIN(4, 26), RCAR_GP_PIN(4, 25), 3241 }; 3242 static const unsigned int scif0_data_c_mux[] = { 3243 RX0_C_MARK, TX0_C_MARK, 3244 }; 3245 static const unsigned int scif0_data_d_pins[] = { 3246 /* RX, TX */ 3247 RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22), 3248 }; 3249 static const unsigned int scif0_data_d_mux[] = { 3250 RX0_D_MARK, TX0_D_MARK, 3251 }; 3252 static const unsigned int scif0_data_e_pins[] = { 3253 /* RX, TX */ 3254 RCAR_GP_PIN(6, 29), RCAR_GP_PIN(6, 28), 3255 }; 3256 static const unsigned int scif0_data_e_mux[] = { 3257 RX0_E_MARK, TX0_E_MARK, 3258 }; 3259 /* - SCIF1 ------------------------------------------------------------------ */ 3260 static const unsigned int scif1_data_pins[] = { 3261 /* RX, TX */ 3262 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8), 3263 }; 3264 static const unsigned int scif1_data_mux[] = { 3265 RX1_MARK, TX1_MARK, 3266 }; 3267 static const unsigned int scif1_data_b_pins[] = { 3268 /* RX, TX */ 3269 RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8), 3270 }; 3271 static const unsigned int scif1_data_b_mux[] = { 3272 RX1_B_MARK, TX1_B_MARK, 3273 }; 3274 static const unsigned int scif1_clk_b_pins[] = { 3275 /* SCK */ 3276 RCAR_GP_PIN(3, 10), 3277 }; 3278 static const unsigned int scif1_clk_b_mux[] = { 3279 SCIF1_SCK_B_MARK, 3280 }; 3281 static const unsigned int scif1_data_c_pins[] = { 3282 /* RX, TX */ 3283 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 27), 3284 }; 3285 static const unsigned int scif1_data_c_mux[] = { 3286 RX1_C_MARK, TX1_C_MARK, 3287 }; 3288 static const unsigned int scif1_data_d_pins[] = { 3289 /* RX, TX */ 3290 RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 24), 3291 }; 3292 static const unsigned int scif1_data_d_mux[] = { 3293 RX1_D_MARK, TX1_D_MARK, 3294 }; 3295 /* - SCIF2 ------------------------------------------------------------------ */ 3296 static const unsigned int scif2_data_pins[] = { 3297 /* RX, TX */ 3298 RCAR_GP_PIN(2, 30), RCAR_GP_PIN(2, 31), 3299 }; 3300 static const unsigned int scif2_data_mux[] = { 3301 RX2_MARK, TX2_MARK, 3302 }; 3303 static const unsigned int scif2_data_b_pins[] = { 3304 /* RX, TX */ 3305 RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16), 3306 }; 3307 static const unsigned int scif2_data_b_mux[] = { 3308 RX2_B_MARK, TX2_B_MARK, 3309 }; 3310 static const unsigned int scif2_clk_b_pins[] = { 3311 /* SCK */ 3312 RCAR_GP_PIN(3, 18), 3313 }; 3314 static const unsigned int scif2_clk_b_mux[] = { 3315 SCIF2_SCK_B_MARK, 3316 }; 3317 static const unsigned int scif2_data_c_pins[] = { 3318 /* RX, TX */ 3319 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25), 3320 }; 3321 static const unsigned int scif2_data_c_mux[] = { 3322 RX2_C_MARK, TX2_C_MARK, 3323 }; 3324 static const unsigned int scif2_data_e_pins[] = { 3325 /* RX, TX */ 3326 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), 3327 }; 3328 static const unsigned int scif2_data_e_mux[] = { 3329 RX2_E_MARK, TX2_E_MARK, 3330 }; 3331 /* - SCIF3 ------------------------------------------------------------------ */ 3332 static const unsigned int scif3_data_pins[] = { 3333 /* RX, TX */ 3334 RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21), 3335 }; 3336 static const unsigned int scif3_data_mux[] = { 3337 RX3_MARK, TX3_MARK, 3338 }; 3339 static const unsigned int scif3_clk_pins[] = { 3340 /* SCK */ 3341 RCAR_GP_PIN(3, 23), 3342 }; 3343 static const unsigned int scif3_clk_mux[] = { 3344 SCIF3_SCK_MARK, 3345 }; 3346 static const unsigned int scif3_data_b_pins[] = { 3347 /* RX, TX */ 3348 RCAR_GP_PIN(3, 29), RCAR_GP_PIN(3, 26), 3349 }; 3350 static const unsigned int scif3_data_b_mux[] = { 3351 RX3_B_MARK, TX3_B_MARK, 3352 }; 3353 static const unsigned int scif3_clk_b_pins[] = { 3354 /* SCK */ 3355 RCAR_GP_PIN(4, 8), 3356 }; 3357 static const unsigned int scif3_clk_b_mux[] = { 3358 SCIF3_SCK_B_MARK, 3359 }; 3360 static const unsigned int scif3_data_c_pins[] = { 3361 /* RX, TX */ 3362 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6), 3363 }; 3364 static const unsigned int scif3_data_c_mux[] = { 3365 RX3_C_MARK, TX3_C_MARK, 3366 }; 3367 static const unsigned int scif3_data_d_pins[] = { 3368 /* RX, TX */ 3369 RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 26), 3370 }; 3371 static const unsigned int scif3_data_d_mux[] = { 3372 RX3_D_MARK, TX3_D_MARK, 3373 }; 3374 /* - SCIF4 ------------------------------------------------------------------ */ 3375 static const unsigned int scif4_data_pins[] = { 3376 /* RX, TX */ 3377 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 1), 3378 }; 3379 static const unsigned int scif4_data_mux[] = { 3380 RX4_MARK, TX4_MARK, 3381 }; 3382 static const unsigned int scif4_data_b_pins[] = { 3383 /* RX, TX */ 3384 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 0), 3385 }; 3386 static const unsigned int scif4_data_b_mux[] = { 3387 RX4_B_MARK, TX4_B_MARK, 3388 }; 3389 static const unsigned int scif4_data_c_pins[] = { 3390 /* RX, TX */ 3391 RCAR_GP_PIN(7, 22), RCAR_GP_PIN(7, 21), 3392 }; 3393 static const unsigned int scif4_data_c_mux[] = { 3394 RX4_C_MARK, TX4_C_MARK, 3395 }; 3396 /* - SCIF5 ------------------------------------------------------------------ */ 3397 static const unsigned int scif5_data_pins[] = { 3398 /* RX, TX */ 3399 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 3), 3400 }; 3401 static const unsigned int scif5_data_mux[] = { 3402 RX5_MARK, TX5_MARK, 3403 }; 3404 static const unsigned int scif5_data_b_pins[] = { 3405 /* RX, TX */ 3406 RCAR_GP_PIN(6, 23), RCAR_GP_PIN(6, 22), 3407 }; 3408 static const unsigned int scif5_data_b_mux[] = { 3409 RX5_B_MARK, TX5_B_MARK, 3410 }; 3411 /* - SCIFA0 ----------------------------------------------------------------- */ 3412 static const unsigned int scifa0_data_pins[] = { 3413 /* RXD, TXD */ 3414 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), 3415 }; 3416 static const unsigned int scifa0_data_mux[] = { 3417 SCIFA0_RXD_MARK, SCIFA0_TXD_MARK, 3418 }; 3419 static const unsigned int scifa0_data_b_pins[] = { 3420 /* RXD, TXD */ 3421 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0), 3422 }; 3423 static const unsigned int scifa0_data_b_mux[] = { 3424 SCIFA0_RXD_B_MARK, SCIFA0_TXD_B_MARK 3425 }; 3426 /* - SCIFA1 ----------------------------------------------------------------- */ 3427 static const unsigned int scifa1_data_pins[] = { 3428 /* RXD, TXD */ 3429 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8), 3430 }; 3431 static const unsigned int scifa1_data_mux[] = { 3432 SCIFA1_RXD_MARK, SCIFA1_TXD_MARK, 3433 }; 3434 static const unsigned int scifa1_clk_pins[] = { 3435 /* SCK */ 3436 RCAR_GP_PIN(3, 10), 3437 }; 3438 static const unsigned int scifa1_clk_mux[] = { 3439 SCIFA1_SCK_MARK, 3440 }; 3441 static const unsigned int scifa1_data_b_pins[] = { 3442 /* RXD, TXD */ 3443 RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8), 3444 }; 3445 static const unsigned int scifa1_data_b_mux[] = { 3446 SCIFA1_RXD_B_MARK, SCIFA1_TXD_B_MARK, 3447 }; 3448 static const unsigned int scifa1_clk_b_pins[] = { 3449 /* SCK */ 3450 RCAR_GP_PIN(1, 0), 3451 }; 3452 static const unsigned int scifa1_clk_b_mux[] = { 3453 SCIFA1_SCK_B_MARK, 3454 }; 3455 static const unsigned int scifa1_data_c_pins[] = { 3456 /* RXD, TXD */ 3457 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), 3458 }; 3459 static const unsigned int scifa1_data_c_mux[] = { 3460 SCIFA1_RXD_C_MARK, SCIFA1_TXD_C_MARK, 3461 }; 3462 /* - SCIFA2 ----------------------------------------------------------------- */ 3463 static const unsigned int scifa2_data_pins[] = { 3464 /* RXD, TXD */ 3465 RCAR_GP_PIN(2, 30), RCAR_GP_PIN(2, 31), 3466 }; 3467 static const unsigned int scifa2_data_mux[] = { 3468 SCIFA2_RXD_MARK, SCIFA2_TXD_MARK, 3469 }; 3470 static const unsigned int scifa2_clk_pins[] = { 3471 /* SCK */ 3472 RCAR_GP_PIN(3, 18), 3473 }; 3474 static const unsigned int scifa2_clk_mux[] = { 3475 SCIFA2_SCK_MARK, 3476 }; 3477 static const unsigned int scifa2_data_b_pins[] = { 3478 /* RXD, TXD */ 3479 RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16), 3480 }; 3481 static const unsigned int scifa2_data_b_mux[] = { 3482 SCIFA2_RXD_B_MARK, SCIFA2_TXD_B_MARK, 3483 }; 3484 /* - SCIFA3 ----------------------------------------------------------------- */ 3485 static const unsigned int scifa3_data_pins[] = { 3486 /* RXD, TXD */ 3487 RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21), 3488 }; 3489 static const unsigned int scifa3_data_mux[] = { 3490 SCIFA3_RXD_MARK, SCIFA3_TXD_MARK, 3491 }; 3492 static const unsigned int scifa3_clk_pins[] = { 3493 /* SCK */ 3494 RCAR_GP_PIN(3, 23), 3495 }; 3496 static const unsigned int scifa3_clk_mux[] = { 3497 SCIFA3_SCK_MARK, 3498 }; 3499 static const unsigned int scifa3_data_b_pins[] = { 3500 /* RXD, TXD */ 3501 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 20), 3502 }; 3503 static const unsigned int scifa3_data_b_mux[] = { 3504 SCIFA3_RXD_B_MARK, SCIFA3_TXD_B_MARK, 3505 }; 3506 static const unsigned int scifa3_clk_b_pins[] = { 3507 /* SCK */ 3508 RCAR_GP_PIN(4, 8), 3509 }; 3510 static const unsigned int scifa3_clk_b_mux[] = { 3511 SCIFA3_SCK_B_MARK, 3512 }; 3513 static const unsigned int scifa3_data_c_pins[] = { 3514 /* RXD, TXD */ 3515 RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 20), 3516 }; 3517 static const unsigned int scifa3_data_c_mux[] = { 3518 SCIFA3_RXD_C_MARK, SCIFA3_TXD_C_MARK, 3519 }; 3520 static const unsigned int scifa3_clk_c_pins[] = { 3521 /* SCK */ 3522 RCAR_GP_PIN(7, 22), 3523 }; 3524 static const unsigned int scifa3_clk_c_mux[] = { 3525 SCIFA3_SCK_C_MARK, 3526 }; 3527 /* - SCIFA4 ----------------------------------------------------------------- */ 3528 static const unsigned int scifa4_data_pins[] = { 3529 /* RXD, TXD */ 3530 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 1), 3531 }; 3532 static const unsigned int scifa4_data_mux[] = { 3533 SCIFA4_RXD_MARK, SCIFA4_TXD_MARK, 3534 }; 3535 static const unsigned int scifa4_data_b_pins[] = { 3536 /* RXD, TXD */ 3537 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 0), 3538 }; 3539 static const unsigned int scifa4_data_b_mux[] = { 3540 SCIFA4_RXD_B_MARK, SCIFA4_TXD_B_MARK, 3541 }; 3542 static const unsigned int scifa4_data_c_pins[] = { 3543 /* RXD, TXD */ 3544 RCAR_GP_PIN(7, 22), RCAR_GP_PIN(7, 21), 3545 }; 3546 static const unsigned int scifa4_data_c_mux[] = { 3547 SCIFA4_RXD_C_MARK, SCIFA4_TXD_C_MARK, 3548 }; 3549 /* - SCIFA5 ----------------------------------------------------------------- */ 3550 static const unsigned int scifa5_data_pins[] = { 3551 /* RXD, TXD */ 3552 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 3), 3553 }; 3554 static const unsigned int scifa5_data_mux[] = { 3555 SCIFA5_RXD_MARK, SCIFA5_TXD_MARK, 3556 }; 3557 static const unsigned int scifa5_data_b_pins[] = { 3558 /* RXD, TXD */ 3559 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6), 3560 }; 3561 static const unsigned int scifa5_data_b_mux[] = { 3562 SCIFA5_RXD_B_MARK, SCIFA5_TXD_B_MARK, 3563 }; 3564 static const unsigned int scifa5_data_c_pins[] = { 3565 /* RXD, TXD */ 3566 RCAR_GP_PIN(6, 23), RCAR_GP_PIN(6, 22), 3567 }; 3568 static const unsigned int scifa5_data_c_mux[] = { 3569 SCIFA5_RXD_C_MARK, SCIFA5_TXD_C_MARK, 3570 }; 3571 /* - SCIFB0 ----------------------------------------------------------------- */ 3572 static const unsigned int scifb0_data_pins[] = { 3573 /* RXD, TXD */ 3574 RCAR_GP_PIN(7, 3), RCAR_GP_PIN(7, 4), 3575 }; 3576 static const unsigned int scifb0_data_mux[] = { 3577 SCIFB0_RXD_MARK, SCIFB0_TXD_MARK, 3578 }; 3579 static const unsigned int scifb0_clk_pins[] = { 3580 /* SCK */ 3581 RCAR_GP_PIN(7, 2), 3582 }; 3583 static const unsigned int scifb0_clk_mux[] = { 3584 SCIFB0_SCK_MARK, 3585 }; 3586 static const unsigned int scifb0_ctrl_pins[] = { 3587 /* RTS, CTS */ 3588 RCAR_GP_PIN(7, 1), RCAR_GP_PIN(7, 0), 3589 }; 3590 static const unsigned int scifb0_ctrl_mux[] = { 3591 SCIFB0_RTS_N_MARK, SCIFB0_CTS_N_MARK, 3592 }; 3593 static const unsigned int scifb0_data_b_pins[] = { 3594 /* RXD, TXD */ 3595 RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21), 3596 }; 3597 static const unsigned int scifb0_data_b_mux[] = { 3598 SCIFB0_RXD_B_MARK, SCIFB0_TXD_B_MARK, 3599 }; 3600 static const unsigned int scifb0_clk_b_pins[] = { 3601 /* SCK */ 3602 RCAR_GP_PIN(5, 31), 3603 }; 3604 static const unsigned int scifb0_clk_b_mux[] = { 3605 SCIFB0_SCK_B_MARK, 3606 }; 3607 static const unsigned int scifb0_ctrl_b_pins[] = { 3608 /* RTS, CTS */ 3609 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 23), 3610 }; 3611 static const unsigned int scifb0_ctrl_b_mux[] = { 3612 SCIFB0_RTS_N_B_MARK, SCIFB0_CTS_N_B_MARK, 3613 }; 3614 static const unsigned int scifb0_data_c_pins[] = { 3615 /* RXD, TXD */ 3616 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), 3617 }; 3618 static const unsigned int scifb0_data_c_mux[] = { 3619 SCIFB0_RXD_C_MARK, SCIFB0_TXD_C_MARK, 3620 }; 3621 static const unsigned int scifb0_clk_c_pins[] = { 3622 /* SCK */ 3623 RCAR_GP_PIN(2, 30), 3624 }; 3625 static const unsigned int scifb0_clk_c_mux[] = { 3626 SCIFB0_SCK_C_MARK, 3627 }; 3628 static const unsigned int scifb0_data_d_pins[] = { 3629 /* RXD, TXD */ 3630 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 18), 3631 }; 3632 static const unsigned int scifb0_data_d_mux[] = { 3633 SCIFB0_RXD_D_MARK, SCIFB0_TXD_D_MARK, 3634 }; 3635 static const unsigned int scifb0_clk_d_pins[] = { 3636 /* SCK */ 3637 RCAR_GP_PIN(4, 17), 3638 }; 3639 static const unsigned int scifb0_clk_d_mux[] = { 3640 SCIFB0_SCK_D_MARK, 3641 }; 3642 /* - SCIFB1 ----------------------------------------------------------------- */ 3643 static const unsigned int scifb1_data_pins[] = { 3644 /* RXD, TXD */ 3645 RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6), 3646 }; 3647 static const unsigned int scifb1_data_mux[] = { 3648 SCIFB1_RXD_MARK, SCIFB1_TXD_MARK, 3649 }; 3650 static const unsigned int scifb1_clk_pins[] = { 3651 /* SCK */ 3652 RCAR_GP_PIN(7, 7), 3653 }; 3654 static const unsigned int scifb1_clk_mux[] = { 3655 SCIFB1_SCK_MARK, 3656 }; 3657 static const unsigned int scifb1_ctrl_pins[] = { 3658 /* RTS, CTS */ 3659 RCAR_GP_PIN(7, 9), RCAR_GP_PIN(7, 8), 3660 }; 3661 static const unsigned int scifb1_ctrl_mux[] = { 3662 SCIFB1_RTS_N_MARK, SCIFB1_CTS_N_MARK, 3663 }; 3664 static const unsigned int scifb1_data_b_pins[] = { 3665 /* RXD, TXD */ 3666 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18), 3667 }; 3668 static const unsigned int scifb1_data_b_mux[] = { 3669 SCIFB1_RXD_B_MARK, SCIFB1_TXD_B_MARK, 3670 }; 3671 static const unsigned int scifb1_clk_b_pins[] = { 3672 /* SCK */ 3673 RCAR_GP_PIN(1, 3), 3674 }; 3675 static const unsigned int scifb1_clk_b_mux[] = { 3676 SCIFB1_SCK_B_MARK, 3677 }; 3678 static const unsigned int scifb1_data_c_pins[] = { 3679 /* RXD, TXD */ 3680 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), 3681 }; 3682 static const unsigned int scifb1_data_c_mux[] = { 3683 SCIFB1_RXD_C_MARK, SCIFB1_TXD_C_MARK, 3684 }; 3685 static const unsigned int scifb1_clk_c_pins[] = { 3686 /* SCK */ 3687 RCAR_GP_PIN(7, 11), 3688 }; 3689 static const unsigned int scifb1_clk_c_mux[] = { 3690 SCIFB1_SCK_C_MARK, 3691 }; 3692 static const unsigned int scifb1_data_d_pins[] = { 3693 /* RXD, TXD */ 3694 RCAR_GP_PIN(7, 10), RCAR_GP_PIN(7, 12), 3695 }; 3696 static const unsigned int scifb1_data_d_mux[] = { 3697 SCIFB1_RXD_D_MARK, SCIFB1_TXD_D_MARK, 3698 }; 3699 /* - SCIFB2 ----------------------------------------------------------------- */ 3700 static const unsigned int scifb2_data_pins[] = { 3701 /* RXD, TXD */ 3702 RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17), 3703 }; 3704 static const unsigned int scifb2_data_mux[] = { 3705 SCIFB2_RXD_MARK, SCIFB2_TXD_MARK, 3706 }; 3707 static const unsigned int scifb2_clk_pins[] = { 3708 /* SCK */ 3709 RCAR_GP_PIN(4, 15), 3710 }; 3711 static const unsigned int scifb2_clk_mux[] = { 3712 SCIFB2_SCK_MARK, 3713 }; 3714 static const unsigned int scifb2_ctrl_pins[] = { 3715 /* RTS, CTS */ 3716 RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13), 3717 }; 3718 static const unsigned int scifb2_ctrl_mux[] = { 3719 SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK, 3720 }; 3721 static const unsigned int scifb2_data_b_pins[] = { 3722 /* RXD, TXD */ 3723 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13), 3724 }; 3725 static const unsigned int scifb2_data_b_mux[] = { 3726 SCIFB2_RXD_B_MARK, SCIFB2_TXD_B_MARK, 3727 }; 3728 static const unsigned int scifb2_clk_b_pins[] = { 3729 /* SCK */ 3730 RCAR_GP_PIN(5, 31), 3731 }; 3732 static const unsigned int scifb2_clk_b_mux[] = { 3733 SCIFB2_SCK_B_MARK, 3734 }; 3735 static const unsigned int scifb2_ctrl_b_pins[] = { 3736 /* RTS, CTS */ 3737 RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14), 3738 }; 3739 static const unsigned int scifb2_ctrl_b_mux[] = { 3740 SCIFB2_RTS_N_B_MARK, SCIFB2_CTS_N_B_MARK, 3741 }; 3742 static const unsigned int scifb2_data_c_pins[] = { 3743 /* RXD, TXD */ 3744 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), 3745 }; 3746 static const unsigned int scifb2_data_c_mux[] = { 3747 SCIFB2_RXD_C_MARK, SCIFB2_TXD_C_MARK, 3748 }; 3749 static const unsigned int scifb2_clk_c_pins[] = { 3750 /* SCK */ 3751 RCAR_GP_PIN(5, 27), 3752 }; 3753 static const unsigned int scifb2_clk_c_mux[] = { 3754 SCIFB2_SCK_C_MARK, 3755 }; 3756 static const unsigned int scifb2_data_d_pins[] = { 3757 /* RXD, TXD */ 3758 RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 25), 3759 }; 3760 static const unsigned int scifb2_data_d_mux[] = { 3761 SCIFB2_RXD_D_MARK, SCIFB2_TXD_D_MARK, 3762 }; 3763 3764 /* - SCIF Clock ------------------------------------------------------------- */ 3765 static const unsigned int scif_clk_pins[] = { 3766 /* SCIF_CLK */ 3767 RCAR_GP_PIN(2, 29), 3768 }; 3769 static const unsigned int scif_clk_mux[] = { 3770 SCIF_CLK_MARK, 3771 }; 3772 static const unsigned int scif_clk_b_pins[] = { 3773 /* SCIF_CLK */ 3774 RCAR_GP_PIN(7, 19), 3775 }; 3776 static const unsigned int scif_clk_b_mux[] = { 3777 SCIF_CLK_B_MARK, 3778 }; 3779 3780 /* - SDHI0 ------------------------------------------------------------------ */ 3781 static const unsigned int sdhi0_data1_pins[] = { 3782 /* D0 */ 3783 RCAR_GP_PIN(6, 2), 3784 }; 3785 static const unsigned int sdhi0_data1_mux[] = { 3786 SD0_DATA0_MARK, 3787 }; 3788 static const unsigned int sdhi0_data4_pins[] = { 3789 /* D[0:3] */ 3790 RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3), 3791 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5), 3792 }; 3793 static const unsigned int sdhi0_data4_mux[] = { 3794 SD0_DATA0_MARK, SD0_DATA1_MARK, SD0_DATA2_MARK, SD0_DATA3_MARK, 3795 }; 3796 static const unsigned int sdhi0_ctrl_pins[] = { 3797 /* CLK, CMD */ 3798 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1), 3799 }; 3800 static const unsigned int sdhi0_ctrl_mux[] = { 3801 SD0_CLK_MARK, SD0_CMD_MARK, 3802 }; 3803 static const unsigned int sdhi0_cd_pins[] = { 3804 /* CD */ 3805 RCAR_GP_PIN(6, 6), 3806 }; 3807 static const unsigned int sdhi0_cd_mux[] = { 3808 SD0_CD_MARK, 3809 }; 3810 static const unsigned int sdhi0_wp_pins[] = { 3811 /* WP */ 3812 RCAR_GP_PIN(6, 7), 3813 }; 3814 static const unsigned int sdhi0_wp_mux[] = { 3815 SD0_WP_MARK, 3816 }; 3817 /* - SDHI1 ------------------------------------------------------------------ */ 3818 static const unsigned int sdhi1_data1_pins[] = { 3819 /* D0 */ 3820 RCAR_GP_PIN(6, 10), 3821 }; 3822 static const unsigned int sdhi1_data1_mux[] = { 3823 SD1_DATA0_MARK, 3824 }; 3825 static const unsigned int sdhi1_data4_pins[] = { 3826 /* D[0:3] */ 3827 RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11), 3828 RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13), 3829 }; 3830 static const unsigned int sdhi1_data4_mux[] = { 3831 SD1_DATA0_MARK, SD1_DATA1_MARK, SD1_DATA2_MARK, SD1_DATA3_MARK, 3832 }; 3833 static const unsigned int sdhi1_ctrl_pins[] = { 3834 /* CLK, CMD */ 3835 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), 3836 }; 3837 static const unsigned int sdhi1_ctrl_mux[] = { 3838 SD1_CLK_MARK, SD1_CMD_MARK, 3839 }; 3840 static const unsigned int sdhi1_cd_pins[] = { 3841 /* CD */ 3842 RCAR_GP_PIN(6, 14), 3843 }; 3844 static const unsigned int sdhi1_cd_mux[] = { 3845 SD1_CD_MARK, 3846 }; 3847 static const unsigned int sdhi1_wp_pins[] = { 3848 /* WP */ 3849 RCAR_GP_PIN(6, 15), 3850 }; 3851 static const unsigned int sdhi1_wp_mux[] = { 3852 SD1_WP_MARK, 3853 }; 3854 /* - SDHI2 ------------------------------------------------------------------ */ 3855 static const unsigned int sdhi2_data1_pins[] = { 3856 /* D0 */ 3857 RCAR_GP_PIN(6, 18), 3858 }; 3859 static const unsigned int sdhi2_data1_mux[] = { 3860 SD2_DATA0_MARK, 3861 }; 3862 static const unsigned int sdhi2_data4_pins[] = { 3863 /* D[0:3] */ 3864 RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19), 3865 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21), 3866 }; 3867 static const unsigned int sdhi2_data4_mux[] = { 3868 SD2_DATA0_MARK, SD2_DATA1_MARK, SD2_DATA2_MARK, SD2_DATA3_MARK, 3869 }; 3870 static const unsigned int sdhi2_ctrl_pins[] = { 3871 /* CLK, CMD */ 3872 RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17), 3873 }; 3874 static const unsigned int sdhi2_ctrl_mux[] = { 3875 SD2_CLK_MARK, SD2_CMD_MARK, 3876 }; 3877 static const unsigned int sdhi2_cd_pins[] = { 3878 /* CD */ 3879 RCAR_GP_PIN(6, 22), 3880 }; 3881 static const unsigned int sdhi2_cd_mux[] = { 3882 SD2_CD_MARK, 3883 }; 3884 static const unsigned int sdhi2_wp_pins[] = { 3885 /* WP */ 3886 RCAR_GP_PIN(6, 23), 3887 }; 3888 static const unsigned int sdhi2_wp_mux[] = { 3889 SD2_WP_MARK, 3890 }; 3891 3892 /* - SSI -------------------------------------------------------------------- */ 3893 static const unsigned int ssi0_data_pins[] = { 3894 /* SDATA */ 3895 RCAR_GP_PIN(2, 2), 3896 }; 3897 3898 static const unsigned int ssi0_data_mux[] = { 3899 SSI_SDATA0_MARK, 3900 }; 3901 3902 static const unsigned int ssi0_data_b_pins[] = { 3903 /* SDATA */ 3904 RCAR_GP_PIN(3, 4), 3905 }; 3906 3907 static const unsigned int ssi0_data_b_mux[] = { 3908 SSI_SDATA0_B_MARK, 3909 }; 3910 3911 static const unsigned int ssi0129_ctrl_pins[] = { 3912 /* SCK, WS */ 3913 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), 3914 }; 3915 3916 static const unsigned int ssi0129_ctrl_mux[] = { 3917 SSI_SCK0129_MARK, SSI_WS0129_MARK, 3918 }; 3919 3920 static const unsigned int ssi0129_ctrl_b_pins[] = { 3921 /* SCK, WS */ 3922 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), 3923 }; 3924 3925 static const unsigned int ssi0129_ctrl_b_mux[] = { 3926 SSI_SCK0129_B_MARK, SSI_WS0129_B_MARK, 3927 }; 3928 3929 static const unsigned int ssi1_data_pins[] = { 3930 /* SDATA */ 3931 RCAR_GP_PIN(2, 5), 3932 }; 3933 3934 static const unsigned int ssi1_data_mux[] = { 3935 SSI_SDATA1_MARK, 3936 }; 3937 3938 static const unsigned int ssi1_data_b_pins[] = { 3939 /* SDATA */ 3940 RCAR_GP_PIN(3, 7), 3941 }; 3942 3943 static const unsigned int ssi1_data_b_mux[] = { 3944 SSI_SDATA1_B_MARK, 3945 }; 3946 3947 static const unsigned int ssi1_ctrl_pins[] = { 3948 /* SCK, WS */ 3949 RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4), 3950 }; 3951 3952 static const unsigned int ssi1_ctrl_mux[] = { 3953 SSI_SCK1_MARK, SSI_WS1_MARK, 3954 }; 3955 3956 static const unsigned int ssi1_ctrl_b_pins[] = { 3957 /* SCK, WS */ 3958 RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6), 3959 }; 3960 3961 static const unsigned int ssi1_ctrl_b_mux[] = { 3962 SSI_SCK1_B_MARK, SSI_WS1_B_MARK, 3963 }; 3964 3965 static const unsigned int ssi2_data_pins[] = { 3966 /* SDATA */ 3967 RCAR_GP_PIN(2, 8), 3968 }; 3969 3970 static const unsigned int ssi2_data_mux[] = { 3971 SSI_SDATA2_MARK, 3972 }; 3973 3974 static const unsigned int ssi2_ctrl_pins[] = { 3975 /* SCK, WS */ 3976 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), 3977 }; 3978 3979 static const unsigned int ssi2_ctrl_mux[] = { 3980 SSI_SCK2_MARK, SSI_WS2_MARK, 3981 }; 3982 3983 static const unsigned int ssi3_data_pins[] = { 3984 /* SDATA */ 3985 RCAR_GP_PIN(2, 11), 3986 }; 3987 3988 static const unsigned int ssi3_data_mux[] = { 3989 SSI_SDATA3_MARK, 3990 }; 3991 3992 static const unsigned int ssi34_ctrl_pins[] = { 3993 /* SCK, WS */ 3994 RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10), 3995 }; 3996 3997 static const unsigned int ssi34_ctrl_mux[] = { 3998 SSI_SCK34_MARK, SSI_WS34_MARK, 3999 }; 4000 4001 static const unsigned int ssi4_data_pins[] = { 4002 /* SDATA */ 4003 RCAR_GP_PIN(2, 14), 4004 }; 4005 4006 static const unsigned int ssi4_data_mux[] = { 4007 SSI_SDATA4_MARK, 4008 }; 4009 4010 static const unsigned int ssi4_ctrl_pins[] = { 4011 /* SCK, WS */ 4012 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13), 4013 }; 4014 4015 static const unsigned int ssi4_ctrl_mux[] = { 4016 SSI_SCK4_MARK, SSI_WS4_MARK, 4017 }; 4018 4019 static const unsigned int ssi5_data_pins[] = { 4020 /* SDATA */ 4021 RCAR_GP_PIN(2, 17), 4022 }; 4023 4024 static const unsigned int ssi5_data_mux[] = { 4025 SSI_SDATA5_MARK, 4026 }; 4027 4028 static const unsigned int ssi5_ctrl_pins[] = { 4029 /* SCK, WS */ 4030 RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16), 4031 }; 4032 4033 static const unsigned int ssi5_ctrl_mux[] = { 4034 SSI_SCK5_MARK, SSI_WS5_MARK, 4035 }; 4036 4037 static const unsigned int ssi6_data_pins[] = { 4038 /* SDATA */ 4039 RCAR_GP_PIN(2, 20), 4040 }; 4041 4042 static const unsigned int ssi6_data_mux[] = { 4043 SSI_SDATA6_MARK, 4044 }; 4045 4046 static const unsigned int ssi6_ctrl_pins[] = { 4047 /* SCK, WS */ 4048 RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19), 4049 }; 4050 4051 static const unsigned int ssi6_ctrl_mux[] = { 4052 SSI_SCK6_MARK, SSI_WS6_MARK, 4053 }; 4054 4055 static const unsigned int ssi7_data_pins[] = { 4056 /* SDATA */ 4057 RCAR_GP_PIN(2, 23), 4058 }; 4059 4060 static const unsigned int ssi7_data_mux[] = { 4061 SSI_SDATA7_MARK, 4062 }; 4063 4064 static const unsigned int ssi7_data_b_pins[] = { 4065 /* SDATA */ 4066 RCAR_GP_PIN(3, 12), 4067 }; 4068 4069 static const unsigned int ssi7_data_b_mux[] = { 4070 SSI_SDATA7_B_MARK, 4071 }; 4072 4073 static const unsigned int ssi78_ctrl_pins[] = { 4074 /* SCK, WS */ 4075 RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22), 4076 }; 4077 4078 static const unsigned int ssi78_ctrl_mux[] = { 4079 SSI_SCK78_MARK, SSI_WS78_MARK, 4080 }; 4081 4082 static const unsigned int ssi78_ctrl_b_pins[] = { 4083 /* SCK, WS */ 4084 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), 4085 }; 4086 4087 static const unsigned int ssi78_ctrl_b_mux[] = { 4088 SSI_SCK78_B_MARK, SSI_WS78_B_MARK, 4089 }; 4090 4091 static const unsigned int ssi8_data_pins[] = { 4092 /* SDATA */ 4093 RCAR_GP_PIN(2, 24), 4094 }; 4095 4096 static const unsigned int ssi8_data_mux[] = { 4097 SSI_SDATA8_MARK, 4098 }; 4099 4100 static const unsigned int ssi8_data_b_pins[] = { 4101 /* SDATA */ 4102 RCAR_GP_PIN(3, 13), 4103 }; 4104 4105 static const unsigned int ssi8_data_b_mux[] = { 4106 SSI_SDATA8_B_MARK, 4107 }; 4108 4109 static const unsigned int ssi9_data_pins[] = { 4110 /* SDATA */ 4111 RCAR_GP_PIN(2, 27), 4112 }; 4113 4114 static const unsigned int ssi9_data_mux[] = { 4115 SSI_SDATA9_MARK, 4116 }; 4117 4118 static const unsigned int ssi9_data_b_pins[] = { 4119 /* SDATA */ 4120 RCAR_GP_PIN(3, 18), 4121 }; 4122 4123 static const unsigned int ssi9_data_b_mux[] = { 4124 SSI_SDATA9_B_MARK, 4125 }; 4126 4127 static const unsigned int ssi9_ctrl_pins[] = { 4128 /* SCK, WS */ 4129 RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 26), 4130 }; 4131 4132 static const unsigned int ssi9_ctrl_mux[] = { 4133 SSI_SCK9_MARK, SSI_WS9_MARK, 4134 }; 4135 4136 static const unsigned int ssi9_ctrl_b_pins[] = { 4137 /* SCK, WS */ 4138 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), 4139 }; 4140 4141 static const unsigned int ssi9_ctrl_b_mux[] = { 4142 SSI_SCK9_B_MARK, SSI_WS9_B_MARK, 4143 }; 4144 4145 /* - TPU -------------------------------------------------------------------- */ 4146 static const unsigned int tpu_to0_pins[] = { 4147 RCAR_GP_PIN(6, 14), 4148 }; 4149 static const unsigned int tpu_to0_mux[] = { 4150 TPU_TO0_MARK, 4151 }; 4152 static const unsigned int tpu_to1_pins[] = { 4153 RCAR_GP_PIN(1, 17), 4154 }; 4155 static const unsigned int tpu_to1_mux[] = { 4156 TPU_TO1_MARK, 4157 }; 4158 static const unsigned int tpu_to2_pins[] = { 4159 RCAR_GP_PIN(1, 18), 4160 }; 4161 static const unsigned int tpu_to2_mux[] = { 4162 TPU_TO2_MARK, 4163 }; 4164 static const unsigned int tpu_to3_pins[] = { 4165 RCAR_GP_PIN(1, 24), 4166 }; 4167 static const unsigned int tpu_to3_mux[] = { 4168 TPU_TO3_MARK, 4169 }; 4170 4171 /* - USB0 ------------------------------------------------------------------- */ 4172 static const unsigned int usb0_pins[] = { 4173 RCAR_GP_PIN(7, 23), /* PWEN */ 4174 RCAR_GP_PIN(7, 24), /* OVC */ 4175 }; 4176 static const unsigned int usb0_mux[] = { 4177 USB0_PWEN_MARK, 4178 USB0_OVC_MARK, 4179 }; 4180 /* - USB1 ------------------------------------------------------------------- */ 4181 static const unsigned int usb1_pins[] = { 4182 RCAR_GP_PIN(7, 25), /* PWEN */ 4183 RCAR_GP_PIN(6, 30), /* OVC */ 4184 }; 4185 static const unsigned int usb1_mux[] = { 4186 USB1_PWEN_MARK, 4187 USB1_OVC_MARK, 4188 }; 4189 /* - VIN0 ------------------------------------------------------------------- */ 4190 static const union vin_data vin0_data_pins = { 4191 .data24 = { 4192 /* B */ 4193 RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 6), 4194 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8), 4195 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10), 4196 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12), 4197 /* G */ 4198 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14), 4199 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16), 4200 RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18), 4201 RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 20), 4202 /* R */ 4203 RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 22), 4204 RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24), 4205 RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26), 4206 RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28), 4207 }, 4208 }; 4209 static const union vin_data vin0_data_mux = { 4210 .data24 = { 4211 /* B */ 4212 VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK, 4213 VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK, 4214 VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK, 4215 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK, 4216 /* G */ 4217 VI0_G0_MARK, VI0_G1_MARK, 4218 VI0_G2_MARK, VI0_G3_MARK, 4219 VI0_G4_MARK, VI0_G5_MARK, 4220 VI0_G6_MARK, VI0_G7_MARK, 4221 /* R */ 4222 VI0_R0_MARK, VI0_R1_MARK, 4223 VI0_R2_MARK, VI0_R3_MARK, 4224 VI0_R4_MARK, VI0_R5_MARK, 4225 VI0_R6_MARK, VI0_R7_MARK, 4226 }, 4227 }; 4228 static const unsigned int vin0_data18_pins[] = { 4229 /* B */ 4230 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8), 4231 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10), 4232 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12), 4233 /* G */ 4234 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16), 4235 RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18), 4236 RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 20), 4237 /* R */ 4238 RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24), 4239 RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26), 4240 RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28), 4241 }; 4242 static const unsigned int vin0_data18_mux[] = { 4243 /* B */ 4244 VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK, 4245 VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK, 4246 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK, 4247 /* G */ 4248 VI0_G2_MARK, VI0_G3_MARK, 4249 VI0_G4_MARK, VI0_G5_MARK, 4250 VI0_G6_MARK, VI0_G7_MARK, 4251 /* R */ 4252 VI0_R2_MARK, VI0_R3_MARK, 4253 VI0_R4_MARK, VI0_R5_MARK, 4254 VI0_R6_MARK, VI0_R7_MARK, 4255 }; 4256 static const unsigned int vin0_sync_pins[] = { 4257 RCAR_GP_PIN(4, 3), /* HSYNC */ 4258 RCAR_GP_PIN(4, 4), /* VSYNC */ 4259 }; 4260 static const unsigned int vin0_sync_mux[] = { 4261 VI0_HSYNC_N_MARK, 4262 VI0_VSYNC_N_MARK, 4263 }; 4264 static const unsigned int vin0_field_pins[] = { 4265 RCAR_GP_PIN(4, 2), 4266 }; 4267 static const unsigned int vin0_field_mux[] = { 4268 VI0_FIELD_MARK, 4269 }; 4270 static const unsigned int vin0_clkenb_pins[] = { 4271 RCAR_GP_PIN(4, 1), 4272 }; 4273 static const unsigned int vin0_clkenb_mux[] = { 4274 VI0_CLKENB_MARK, 4275 }; 4276 static const unsigned int vin0_clk_pins[] = { 4277 RCAR_GP_PIN(4, 0), 4278 }; 4279 static const unsigned int vin0_clk_mux[] = { 4280 VI0_CLK_MARK, 4281 }; 4282 /* - VIN1 ----------------------------------------------------------------- */ 4283 static const unsigned int vin1_data8_pins[] = { 4284 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6), 4285 RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8), 4286 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10), 4287 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 12), 4288 }; 4289 static const unsigned int vin1_data8_mux[] = { 4290 VI1_DATA0_MARK, VI1_DATA1_MARK, 4291 VI1_DATA2_MARK, VI1_DATA3_MARK, 4292 VI1_DATA4_MARK, VI1_DATA5_MARK, 4293 VI1_DATA6_MARK, VI1_DATA7_MARK, 4294 }; 4295 static const unsigned int vin1_sync_pins[] = { 4296 RCAR_GP_PIN(5, 0), /* HSYNC */ 4297 RCAR_GP_PIN(5, 1), /* VSYNC */ 4298 }; 4299 static const unsigned int vin1_sync_mux[] = { 4300 VI1_HSYNC_N_MARK, 4301 VI1_VSYNC_N_MARK, 4302 }; 4303 static const unsigned int vin1_field_pins[] = { 4304 RCAR_GP_PIN(5, 3), 4305 }; 4306 static const unsigned int vin1_field_mux[] = { 4307 VI1_FIELD_MARK, 4308 }; 4309 static const unsigned int vin1_clkenb_pins[] = { 4310 RCAR_GP_PIN(5, 2), 4311 }; 4312 static const unsigned int vin1_clkenb_mux[] = { 4313 VI1_CLKENB_MARK, 4314 }; 4315 static const unsigned int vin1_clk_pins[] = { 4316 RCAR_GP_PIN(5, 4), 4317 }; 4318 static const unsigned int vin1_clk_mux[] = { 4319 VI1_CLK_MARK, 4320 }; 4321 static const union vin_data vin1_data_b_pins = { 4322 .data24 = { 4323 /* B */ 4324 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1), 4325 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), 4326 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), 4327 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13), 4328 /* G */ 4329 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25), 4330 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27), 4331 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29), 4332 RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 22), 4333 /* R */ 4334 RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6), 4335 RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16), 4336 RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18), 4337 RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20), 4338 }, 4339 }; 4340 static const union vin_data vin1_data_b_mux = { 4341 .data24 = { 4342 /* B */ 4343 VI1_DATA0_B_MARK, VI1_DATA1_B_MARK, 4344 VI1_DATA2_B_MARK, VI1_DATA3_B_MARK, 4345 VI1_DATA4_B_MARK, VI1_DATA5_B_MARK, 4346 VI1_DATA6_B_MARK, VI1_DATA7_B_MARK, 4347 /* G */ 4348 VI1_G0_B_MARK, VI1_G1_B_MARK, 4349 VI1_G2_B_MARK, VI1_G3_B_MARK, 4350 VI1_G4_B_MARK, VI1_G5_B_MARK, 4351 VI1_G6_B_MARK, VI1_G7_B_MARK, 4352 /* R */ 4353 VI1_R0_B_MARK, VI1_R1_B_MARK, 4354 VI1_R2_B_MARK, VI1_R3_B_MARK, 4355 VI1_R4_B_MARK, VI1_R5_B_MARK, 4356 VI1_R6_B_MARK, VI1_R7_B_MARK, 4357 }, 4358 }; 4359 static const unsigned int vin1_data18_b_pins[] = { 4360 /* B */ 4361 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), 4362 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), 4363 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13), 4364 /* G */ 4365 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27), 4366 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29), 4367 RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 22), 4368 /* R */ 4369 RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16), 4370 RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18), 4371 RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20), 4372 }; 4373 static const unsigned int vin1_data18_b_mux[] = { 4374 /* B */ 4375 VI1_DATA2_B_MARK, VI1_DATA3_B_MARK, 4376 VI1_DATA4_B_MARK, VI1_DATA5_B_MARK, 4377 VI1_DATA6_B_MARK, VI1_DATA7_B_MARK, 4378 /* G */ 4379 VI1_G2_B_MARK, VI1_G3_B_MARK, 4380 VI1_G4_B_MARK, VI1_G5_B_MARK, 4381 VI1_G6_B_MARK, VI1_G7_B_MARK, 4382 /* R */ 4383 VI1_R2_B_MARK, VI1_R3_B_MARK, 4384 VI1_R4_B_MARK, VI1_R5_B_MARK, 4385 VI1_R6_B_MARK, VI1_R7_B_MARK, 4386 }; 4387 static const unsigned int vin1_sync_b_pins[] = { 4388 RCAR_GP_PIN(3, 17), /* HSYNC */ 4389 RCAR_GP_PIN(3, 18), /* VSYNC */ 4390 }; 4391 static const unsigned int vin1_sync_b_mux[] = { 4392 VI1_HSYNC_N_B_MARK, 4393 VI1_VSYNC_N_B_MARK, 4394 }; 4395 static const unsigned int vin1_field_b_pins[] = { 4396 RCAR_GP_PIN(3, 20), 4397 }; 4398 static const unsigned int vin1_field_b_mux[] = { 4399 VI1_FIELD_B_MARK, 4400 }; 4401 static const unsigned int vin1_clkenb_b_pins[] = { 4402 RCAR_GP_PIN(3, 19), 4403 }; 4404 static const unsigned int vin1_clkenb_b_mux[] = { 4405 VI1_CLKENB_B_MARK, 4406 }; 4407 static const unsigned int vin1_clk_b_pins[] = { 4408 RCAR_GP_PIN(3, 16), 4409 }; 4410 static const unsigned int vin1_clk_b_mux[] = { 4411 VI1_CLK_B_MARK, 4412 }; 4413 /* - VIN2 ----------------------------------------------------------------- */ 4414 static const unsigned int vin2_data8_pins[] = { 4415 RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21), 4416 RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23), 4417 RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 25), 4418 RCAR_GP_PIN(4, 26), RCAR_GP_PIN(4, 27), 4419 }; 4420 static const unsigned int vin2_data8_mux[] = { 4421 VI2_DATA0_MARK, VI2_DATA1_MARK, 4422 VI2_DATA2_MARK, VI2_DATA3_MARK, 4423 VI2_DATA4_MARK, VI2_DATA5_MARK, 4424 VI2_DATA6_MARK, VI2_DATA7_MARK, 4425 }; 4426 static const unsigned int vin2_sync_pins[] = { 4427 RCAR_GP_PIN(4, 15), /* HSYNC */ 4428 RCAR_GP_PIN(4, 16), /* VSYNC */ 4429 }; 4430 static const unsigned int vin2_sync_mux[] = { 4431 VI2_HSYNC_N_MARK, 4432 VI2_VSYNC_N_MARK, 4433 }; 4434 static const unsigned int vin2_field_pins[] = { 4435 RCAR_GP_PIN(4, 18), 4436 }; 4437 static const unsigned int vin2_field_mux[] = { 4438 VI2_FIELD_MARK, 4439 }; 4440 static const unsigned int vin2_clkenb_pins[] = { 4441 RCAR_GP_PIN(4, 17), 4442 }; 4443 static const unsigned int vin2_clkenb_mux[] = { 4444 VI2_CLKENB_MARK, 4445 }; 4446 static const unsigned int vin2_clk_pins[] = { 4447 RCAR_GP_PIN(4, 19), 4448 }; 4449 static const unsigned int vin2_clk_mux[] = { 4450 VI2_CLK_MARK, 4451 }; 4452 4453 static const struct { 4454 struct sh_pfc_pin_group common[346]; 4455 struct sh_pfc_pin_group automotive[9]; 4456 } pinmux_groups = { 4457 .common = { 4458 SH_PFC_PIN_GROUP(audio_clk_a), 4459 SH_PFC_PIN_GROUP(audio_clk_b), 4460 SH_PFC_PIN_GROUP(audio_clk_b_b), 4461 SH_PFC_PIN_GROUP(audio_clk_c), 4462 SH_PFC_PIN_GROUP(audio_clkout), 4463 SH_PFC_PIN_GROUP(avb_link), 4464 SH_PFC_PIN_GROUP(avb_magic), 4465 SH_PFC_PIN_GROUP(avb_phy_int), 4466 SH_PFC_PIN_GROUP(avb_mdio), 4467 SH_PFC_PIN_GROUP(avb_mii), 4468 SH_PFC_PIN_GROUP(avb_gmii), 4469 SH_PFC_PIN_GROUP(can0_data), 4470 SH_PFC_PIN_GROUP(can0_data_b), 4471 SH_PFC_PIN_GROUP(can0_data_c), 4472 SH_PFC_PIN_GROUP(can0_data_d), 4473 SH_PFC_PIN_GROUP(can0_data_e), 4474 SH_PFC_PIN_GROUP(can0_data_f), 4475 SH_PFC_PIN_GROUP(can1_data), 4476 SH_PFC_PIN_GROUP(can1_data_b), 4477 SH_PFC_PIN_GROUP(can1_data_c), 4478 SH_PFC_PIN_GROUP(can1_data_d), 4479 SH_PFC_PIN_GROUP(can_clk), 4480 SH_PFC_PIN_GROUP(can_clk_b), 4481 SH_PFC_PIN_GROUP(can_clk_c), 4482 SH_PFC_PIN_GROUP(can_clk_d), 4483 SH_PFC_PIN_GROUP(du_rgb666), 4484 SH_PFC_PIN_GROUP(du_rgb888), 4485 SH_PFC_PIN_GROUP(du_clk_out_0), 4486 SH_PFC_PIN_GROUP(du_clk_out_1), 4487 SH_PFC_PIN_GROUP(du_sync), 4488 SH_PFC_PIN_GROUP(du_oddf), 4489 SH_PFC_PIN_GROUP(du_cde), 4490 SH_PFC_PIN_GROUP(du_disp), 4491 SH_PFC_PIN_GROUP(du0_clk_in), 4492 SH_PFC_PIN_GROUP(du1_clk_in), 4493 SH_PFC_PIN_GROUP(du1_clk_in_b), 4494 SH_PFC_PIN_GROUP(du1_clk_in_c), 4495 SH_PFC_PIN_GROUP(eth_link), 4496 SH_PFC_PIN_GROUP(eth_magic), 4497 SH_PFC_PIN_GROUP(eth_mdio), 4498 SH_PFC_PIN_GROUP(eth_rmii), 4499 SH_PFC_PIN_GROUP(hscif0_data), 4500 SH_PFC_PIN_GROUP(hscif0_clk), 4501 SH_PFC_PIN_GROUP(hscif0_ctrl), 4502 SH_PFC_PIN_GROUP(hscif0_data_b), 4503 SH_PFC_PIN_GROUP(hscif0_ctrl_b), 4504 SH_PFC_PIN_GROUP(hscif0_data_c), 4505 SH_PFC_PIN_GROUP(hscif0_clk_c), 4506 SH_PFC_PIN_GROUP(hscif1_data), 4507 SH_PFC_PIN_GROUP(hscif1_clk), 4508 SH_PFC_PIN_GROUP(hscif1_ctrl), 4509 SH_PFC_PIN_GROUP(hscif1_data_b), 4510 SH_PFC_PIN_GROUP(hscif1_data_c), 4511 SH_PFC_PIN_GROUP(hscif1_clk_c), 4512 SH_PFC_PIN_GROUP(hscif1_ctrl_c), 4513 SH_PFC_PIN_GROUP(hscif1_data_d), 4514 SH_PFC_PIN_GROUP(hscif1_data_e), 4515 SH_PFC_PIN_GROUP(hscif1_clk_e), 4516 SH_PFC_PIN_GROUP(hscif1_ctrl_e), 4517 SH_PFC_PIN_GROUP(hscif2_data), 4518 SH_PFC_PIN_GROUP(hscif2_clk), 4519 SH_PFC_PIN_GROUP(hscif2_ctrl), 4520 SH_PFC_PIN_GROUP(hscif2_data_b), 4521 SH_PFC_PIN_GROUP(hscif2_ctrl_b), 4522 SH_PFC_PIN_GROUP(hscif2_data_c), 4523 SH_PFC_PIN_GROUP(hscif2_clk_c), 4524 SH_PFC_PIN_GROUP(hscif2_data_d), 4525 SH_PFC_PIN_GROUP(i2c0), 4526 SH_PFC_PIN_GROUP(i2c0_b), 4527 SH_PFC_PIN_GROUP(i2c0_c), 4528 SH_PFC_PIN_GROUP(i2c1), 4529 SH_PFC_PIN_GROUP(i2c1_b), 4530 SH_PFC_PIN_GROUP(i2c1_c), 4531 SH_PFC_PIN_GROUP(i2c1_d), 4532 SH_PFC_PIN_GROUP(i2c1_e), 4533 SH_PFC_PIN_GROUP(i2c2), 4534 SH_PFC_PIN_GROUP(i2c2_b), 4535 SH_PFC_PIN_GROUP(i2c2_c), 4536 SH_PFC_PIN_GROUP(i2c2_d), 4537 SH_PFC_PIN_GROUP(i2c3), 4538 SH_PFC_PIN_GROUP(i2c3_b), 4539 SH_PFC_PIN_GROUP(i2c3_c), 4540 SH_PFC_PIN_GROUP(i2c3_d), 4541 SH_PFC_PIN_GROUP(i2c4), 4542 SH_PFC_PIN_GROUP(i2c4_b), 4543 SH_PFC_PIN_GROUP(i2c4_c), 4544 SH_PFC_PIN_GROUP(i2c7), 4545 SH_PFC_PIN_GROUP(i2c7_b), 4546 SH_PFC_PIN_GROUP(i2c7_c), 4547 SH_PFC_PIN_GROUP(i2c8), 4548 SH_PFC_PIN_GROUP(i2c8_b), 4549 SH_PFC_PIN_GROUP(i2c8_c), 4550 SH_PFC_PIN_GROUP(intc_irq0), 4551 SH_PFC_PIN_GROUP(intc_irq1), 4552 SH_PFC_PIN_GROUP(intc_irq2), 4553 SH_PFC_PIN_GROUP(intc_irq3), 4554 SH_PFC_PIN_GROUP(mmc_data1), 4555 SH_PFC_PIN_GROUP(mmc_data4), 4556 SH_PFC_PIN_GROUP(mmc_data8), 4557 SH_PFC_PIN_GROUP(mmc_data8_b), 4558 SH_PFC_PIN_GROUP(mmc_ctrl), 4559 SH_PFC_PIN_GROUP(msiof0_clk), 4560 SH_PFC_PIN_GROUP(msiof0_sync), 4561 SH_PFC_PIN_GROUP(msiof0_ss1), 4562 SH_PFC_PIN_GROUP(msiof0_ss2), 4563 SH_PFC_PIN_GROUP(msiof0_rx), 4564 SH_PFC_PIN_GROUP(msiof0_tx), 4565 SH_PFC_PIN_GROUP(msiof0_clk_b), 4566 SH_PFC_PIN_GROUP(msiof0_sync_b), 4567 SH_PFC_PIN_GROUP(msiof0_ss1_b), 4568 SH_PFC_PIN_GROUP(msiof0_ss2_b), 4569 SH_PFC_PIN_GROUP(msiof0_rx_b), 4570 SH_PFC_PIN_GROUP(msiof0_tx_b), 4571 SH_PFC_PIN_GROUP(msiof0_clk_c), 4572 SH_PFC_PIN_GROUP(msiof0_sync_c), 4573 SH_PFC_PIN_GROUP(msiof0_ss1_c), 4574 SH_PFC_PIN_GROUP(msiof0_ss2_c), 4575 SH_PFC_PIN_GROUP(msiof0_rx_c), 4576 SH_PFC_PIN_GROUP(msiof0_tx_c), 4577 SH_PFC_PIN_GROUP(msiof1_clk), 4578 SH_PFC_PIN_GROUP(msiof1_sync), 4579 SH_PFC_PIN_GROUP(msiof1_ss1), 4580 SH_PFC_PIN_GROUP(msiof1_ss2), 4581 SH_PFC_PIN_GROUP(msiof1_rx), 4582 SH_PFC_PIN_GROUP(msiof1_tx), 4583 SH_PFC_PIN_GROUP(msiof1_clk_b), 4584 SH_PFC_PIN_GROUP(msiof1_sync_b), 4585 SH_PFC_PIN_GROUP(msiof1_ss1_b), 4586 SH_PFC_PIN_GROUP(msiof1_ss2_b), 4587 SH_PFC_PIN_GROUP(msiof1_rx_b), 4588 SH_PFC_PIN_GROUP(msiof1_tx_b), 4589 SH_PFC_PIN_GROUP(msiof1_clk_c), 4590 SH_PFC_PIN_GROUP(msiof1_sync_c), 4591 SH_PFC_PIN_GROUP(msiof1_rx_c), 4592 SH_PFC_PIN_GROUP(msiof1_tx_c), 4593 SH_PFC_PIN_GROUP(msiof1_clk_d), 4594 SH_PFC_PIN_GROUP(msiof1_sync_d), 4595 SH_PFC_PIN_GROUP(msiof1_ss1_d), 4596 SH_PFC_PIN_GROUP(msiof1_rx_d), 4597 SH_PFC_PIN_GROUP(msiof1_tx_d), 4598 SH_PFC_PIN_GROUP(msiof1_clk_e), 4599 SH_PFC_PIN_GROUP(msiof1_sync_e), 4600 SH_PFC_PIN_GROUP(msiof1_rx_e), 4601 SH_PFC_PIN_GROUP(msiof1_tx_e), 4602 SH_PFC_PIN_GROUP(msiof2_clk), 4603 SH_PFC_PIN_GROUP(msiof2_sync), 4604 SH_PFC_PIN_GROUP(msiof2_ss1), 4605 SH_PFC_PIN_GROUP(msiof2_ss2), 4606 SH_PFC_PIN_GROUP(msiof2_rx), 4607 SH_PFC_PIN_GROUP(msiof2_tx), 4608 SH_PFC_PIN_GROUP(msiof2_clk_b), 4609 SH_PFC_PIN_GROUP(msiof2_sync_b), 4610 SH_PFC_PIN_GROUP(msiof2_ss1_b), 4611 SH_PFC_PIN_GROUP(msiof2_ss2_b), 4612 SH_PFC_PIN_GROUP(msiof2_rx_b), 4613 SH_PFC_PIN_GROUP(msiof2_tx_b), 4614 SH_PFC_PIN_GROUP(msiof2_clk_c), 4615 SH_PFC_PIN_GROUP(msiof2_sync_c), 4616 SH_PFC_PIN_GROUP(msiof2_rx_c), 4617 SH_PFC_PIN_GROUP(msiof2_tx_c), 4618 SH_PFC_PIN_GROUP(msiof2_clk_d), 4619 SH_PFC_PIN_GROUP(msiof2_sync_d), 4620 SH_PFC_PIN_GROUP(msiof2_ss1_d), 4621 SH_PFC_PIN_GROUP(msiof2_ss2_d), 4622 SH_PFC_PIN_GROUP(msiof2_rx_d), 4623 SH_PFC_PIN_GROUP(msiof2_tx_d), 4624 SH_PFC_PIN_GROUP(msiof2_clk_e), 4625 SH_PFC_PIN_GROUP(msiof2_sync_e), 4626 SH_PFC_PIN_GROUP(msiof2_rx_e), 4627 SH_PFC_PIN_GROUP(msiof2_tx_e), 4628 SH_PFC_PIN_GROUP(pwm0), 4629 SH_PFC_PIN_GROUP(pwm0_b), 4630 SH_PFC_PIN_GROUP(pwm1), 4631 SH_PFC_PIN_GROUP(pwm1_b), 4632 SH_PFC_PIN_GROUP(pwm2), 4633 SH_PFC_PIN_GROUP(pwm2_b), 4634 SH_PFC_PIN_GROUP(pwm3), 4635 SH_PFC_PIN_GROUP(pwm4), 4636 SH_PFC_PIN_GROUP(pwm4_b), 4637 SH_PFC_PIN_GROUP(pwm5), 4638 SH_PFC_PIN_GROUP(pwm5_b), 4639 SH_PFC_PIN_GROUP(pwm6), 4640 SH_PFC_PIN_GROUP(qspi_ctrl), 4641 SH_PFC_PIN_GROUP(qspi_data2), 4642 SH_PFC_PIN_GROUP(qspi_data4), 4643 SH_PFC_PIN_GROUP(qspi_ctrl_b), 4644 SH_PFC_PIN_GROUP(qspi_data2_b), 4645 SH_PFC_PIN_GROUP(qspi_data4_b), 4646 SH_PFC_PIN_GROUP(scif0_data), 4647 SH_PFC_PIN_GROUP(scif0_data_b), 4648 SH_PFC_PIN_GROUP(scif0_data_c), 4649 SH_PFC_PIN_GROUP(scif0_data_d), 4650 SH_PFC_PIN_GROUP(scif0_data_e), 4651 SH_PFC_PIN_GROUP(scif1_data), 4652 SH_PFC_PIN_GROUP(scif1_data_b), 4653 SH_PFC_PIN_GROUP(scif1_clk_b), 4654 SH_PFC_PIN_GROUP(scif1_data_c), 4655 SH_PFC_PIN_GROUP(scif1_data_d), 4656 SH_PFC_PIN_GROUP(scif2_data), 4657 SH_PFC_PIN_GROUP(scif2_data_b), 4658 SH_PFC_PIN_GROUP(scif2_clk_b), 4659 SH_PFC_PIN_GROUP(scif2_data_c), 4660 SH_PFC_PIN_GROUP(scif2_data_e), 4661 SH_PFC_PIN_GROUP(scif3_data), 4662 SH_PFC_PIN_GROUP(scif3_clk), 4663 SH_PFC_PIN_GROUP(scif3_data_b), 4664 SH_PFC_PIN_GROUP(scif3_clk_b), 4665 SH_PFC_PIN_GROUP(scif3_data_c), 4666 SH_PFC_PIN_GROUP(scif3_data_d), 4667 SH_PFC_PIN_GROUP(scif4_data), 4668 SH_PFC_PIN_GROUP(scif4_data_b), 4669 SH_PFC_PIN_GROUP(scif4_data_c), 4670 SH_PFC_PIN_GROUP(scif5_data), 4671 SH_PFC_PIN_GROUP(scif5_data_b), 4672 SH_PFC_PIN_GROUP(scifa0_data), 4673 SH_PFC_PIN_GROUP(scifa0_data_b), 4674 SH_PFC_PIN_GROUP(scifa1_data), 4675 SH_PFC_PIN_GROUP(scifa1_clk), 4676 SH_PFC_PIN_GROUP(scifa1_data_b), 4677 SH_PFC_PIN_GROUP(scifa1_clk_b), 4678 SH_PFC_PIN_GROUP(scifa1_data_c), 4679 SH_PFC_PIN_GROUP(scifa2_data), 4680 SH_PFC_PIN_GROUP(scifa2_clk), 4681 SH_PFC_PIN_GROUP(scifa2_data_b), 4682 SH_PFC_PIN_GROUP(scifa3_data), 4683 SH_PFC_PIN_GROUP(scifa3_clk), 4684 SH_PFC_PIN_GROUP(scifa3_data_b), 4685 SH_PFC_PIN_GROUP(scifa3_clk_b), 4686 SH_PFC_PIN_GROUP(scifa3_data_c), 4687 SH_PFC_PIN_GROUP(scifa3_clk_c), 4688 SH_PFC_PIN_GROUP(scifa4_data), 4689 SH_PFC_PIN_GROUP(scifa4_data_b), 4690 SH_PFC_PIN_GROUP(scifa4_data_c), 4691 SH_PFC_PIN_GROUP(scifa5_data), 4692 SH_PFC_PIN_GROUP(scifa5_data_b), 4693 SH_PFC_PIN_GROUP(scifa5_data_c), 4694 SH_PFC_PIN_GROUP(scifb0_data), 4695 SH_PFC_PIN_GROUP(scifb0_clk), 4696 SH_PFC_PIN_GROUP(scifb0_ctrl), 4697 SH_PFC_PIN_GROUP(scifb0_data_b), 4698 SH_PFC_PIN_GROUP(scifb0_clk_b), 4699 SH_PFC_PIN_GROUP(scifb0_ctrl_b), 4700 SH_PFC_PIN_GROUP(scifb0_data_c), 4701 SH_PFC_PIN_GROUP(scifb0_clk_c), 4702 SH_PFC_PIN_GROUP(scifb0_data_d), 4703 SH_PFC_PIN_GROUP(scifb0_clk_d), 4704 SH_PFC_PIN_GROUP(scifb1_data), 4705 SH_PFC_PIN_GROUP(scifb1_clk), 4706 SH_PFC_PIN_GROUP(scifb1_ctrl), 4707 SH_PFC_PIN_GROUP(scifb1_data_b), 4708 SH_PFC_PIN_GROUP(scifb1_clk_b), 4709 SH_PFC_PIN_GROUP(scifb1_data_c), 4710 SH_PFC_PIN_GROUP(scifb1_clk_c), 4711 SH_PFC_PIN_GROUP(scifb1_data_d), 4712 SH_PFC_PIN_GROUP(scifb2_data), 4713 SH_PFC_PIN_GROUP(scifb2_clk), 4714 SH_PFC_PIN_GROUP(scifb2_ctrl), 4715 SH_PFC_PIN_GROUP(scifb2_data_b), 4716 SH_PFC_PIN_GROUP(scifb2_clk_b), 4717 SH_PFC_PIN_GROUP(scifb2_ctrl_b), 4718 SH_PFC_PIN_GROUP(scifb2_data_c), 4719 SH_PFC_PIN_GROUP(scifb2_clk_c), 4720 SH_PFC_PIN_GROUP(scifb2_data_d), 4721 SH_PFC_PIN_GROUP(scif_clk), 4722 SH_PFC_PIN_GROUP(scif_clk_b), 4723 SH_PFC_PIN_GROUP(sdhi0_data1), 4724 SH_PFC_PIN_GROUP(sdhi0_data4), 4725 SH_PFC_PIN_GROUP(sdhi0_ctrl), 4726 SH_PFC_PIN_GROUP(sdhi0_cd), 4727 SH_PFC_PIN_GROUP(sdhi0_wp), 4728 SH_PFC_PIN_GROUP(sdhi1_data1), 4729 SH_PFC_PIN_GROUP(sdhi1_data4), 4730 SH_PFC_PIN_GROUP(sdhi1_ctrl), 4731 SH_PFC_PIN_GROUP(sdhi1_cd), 4732 SH_PFC_PIN_GROUP(sdhi1_wp), 4733 SH_PFC_PIN_GROUP(sdhi2_data1), 4734 SH_PFC_PIN_GROUP(sdhi2_data4), 4735 SH_PFC_PIN_GROUP(sdhi2_ctrl), 4736 SH_PFC_PIN_GROUP(sdhi2_cd), 4737 SH_PFC_PIN_GROUP(sdhi2_wp), 4738 SH_PFC_PIN_GROUP(ssi0_data), 4739 SH_PFC_PIN_GROUP(ssi0_data_b), 4740 SH_PFC_PIN_GROUP(ssi0129_ctrl), 4741 SH_PFC_PIN_GROUP(ssi0129_ctrl_b), 4742 SH_PFC_PIN_GROUP(ssi1_data), 4743 SH_PFC_PIN_GROUP(ssi1_data_b), 4744 SH_PFC_PIN_GROUP(ssi1_ctrl), 4745 SH_PFC_PIN_GROUP(ssi1_ctrl_b), 4746 SH_PFC_PIN_GROUP(ssi2_data), 4747 SH_PFC_PIN_GROUP(ssi2_ctrl), 4748 SH_PFC_PIN_GROUP(ssi3_data), 4749 SH_PFC_PIN_GROUP(ssi34_ctrl), 4750 SH_PFC_PIN_GROUP(ssi4_data), 4751 SH_PFC_PIN_GROUP(ssi4_ctrl), 4752 SH_PFC_PIN_GROUP(ssi5_data), 4753 SH_PFC_PIN_GROUP(ssi5_ctrl), 4754 SH_PFC_PIN_GROUP(ssi6_data), 4755 SH_PFC_PIN_GROUP(ssi6_ctrl), 4756 SH_PFC_PIN_GROUP(ssi7_data), 4757 SH_PFC_PIN_GROUP(ssi7_data_b), 4758 SH_PFC_PIN_GROUP(ssi78_ctrl), 4759 SH_PFC_PIN_GROUP(ssi78_ctrl_b), 4760 SH_PFC_PIN_GROUP(ssi8_data), 4761 SH_PFC_PIN_GROUP(ssi8_data_b), 4762 SH_PFC_PIN_GROUP(ssi9_data), 4763 SH_PFC_PIN_GROUP(ssi9_data_b), 4764 SH_PFC_PIN_GROUP(ssi9_ctrl), 4765 SH_PFC_PIN_GROUP(ssi9_ctrl_b), 4766 SH_PFC_PIN_GROUP(tpu_to0), 4767 SH_PFC_PIN_GROUP(tpu_to1), 4768 SH_PFC_PIN_GROUP(tpu_to2), 4769 SH_PFC_PIN_GROUP(tpu_to3), 4770 SH_PFC_PIN_GROUP(usb0), 4771 SH_PFC_PIN_GROUP(usb1), 4772 VIN_DATA_PIN_GROUP(vin0_data, 24), 4773 VIN_DATA_PIN_GROUP(vin0_data, 20), 4774 SH_PFC_PIN_GROUP(vin0_data18), 4775 VIN_DATA_PIN_GROUP(vin0_data, 16), 4776 VIN_DATA_PIN_GROUP(vin0_data, 12), 4777 VIN_DATA_PIN_GROUP(vin0_data, 10), 4778 VIN_DATA_PIN_GROUP(vin0_data, 8), 4779 SH_PFC_PIN_GROUP(vin0_sync), 4780 SH_PFC_PIN_GROUP(vin0_field), 4781 SH_PFC_PIN_GROUP(vin0_clkenb), 4782 SH_PFC_PIN_GROUP(vin0_clk), 4783 SH_PFC_PIN_GROUP(vin1_data8), 4784 SH_PFC_PIN_GROUP(vin1_sync), 4785 SH_PFC_PIN_GROUP(vin1_field), 4786 SH_PFC_PIN_GROUP(vin1_clkenb), 4787 SH_PFC_PIN_GROUP(vin1_clk), 4788 VIN_DATA_PIN_GROUP(vin1_data, 24, _b), 4789 VIN_DATA_PIN_GROUP(vin1_data, 20, _b), 4790 SH_PFC_PIN_GROUP(vin1_data18_b), 4791 VIN_DATA_PIN_GROUP(vin1_data, 16, _b), 4792 VIN_DATA_PIN_GROUP(vin1_data, 12, _b), 4793 VIN_DATA_PIN_GROUP(vin1_data, 10, _b), 4794 VIN_DATA_PIN_GROUP(vin1_data, 8, _b), 4795 SH_PFC_PIN_GROUP(vin1_sync_b), 4796 SH_PFC_PIN_GROUP(vin1_field_b), 4797 SH_PFC_PIN_GROUP(vin1_clkenb_b), 4798 SH_PFC_PIN_GROUP(vin1_clk_b), 4799 SH_PFC_PIN_GROUP(vin2_data8), 4800 SH_PFC_PIN_GROUP(vin2_sync), 4801 SH_PFC_PIN_GROUP(vin2_field), 4802 SH_PFC_PIN_GROUP(vin2_clkenb), 4803 SH_PFC_PIN_GROUP(vin2_clk), 4804 }, 4805 .automotive = { 4806 SH_PFC_PIN_GROUP(adi_common), 4807 SH_PFC_PIN_GROUP(adi_chsel0), 4808 SH_PFC_PIN_GROUP(adi_chsel1), 4809 SH_PFC_PIN_GROUP(adi_chsel2), 4810 SH_PFC_PIN_GROUP(adi_common_b), 4811 SH_PFC_PIN_GROUP(adi_chsel0_b), 4812 SH_PFC_PIN_GROUP(adi_chsel1_b), 4813 SH_PFC_PIN_GROUP(adi_chsel2_b), 4814 SH_PFC_PIN_GROUP(mlb_3pin), 4815 } 4816 }; 4817 4818 static const char * const adi_groups[] = { 4819 "adi_common", 4820 "adi_chsel0", 4821 "adi_chsel1", 4822 "adi_chsel2", 4823 "adi_common_b", 4824 "adi_chsel0_b", 4825 "adi_chsel1_b", 4826 "adi_chsel2_b", 4827 }; 4828 4829 static const char * const audio_clk_groups[] = { 4830 "audio_clk_a", 4831 "audio_clk_b", 4832 "audio_clk_b_b", 4833 "audio_clk_c", 4834 "audio_clkout", 4835 }; 4836 4837 static const char * const avb_groups[] = { 4838 "avb_link", 4839 "avb_magic", 4840 "avb_phy_int", 4841 "avb_mdio", 4842 "avb_mii", 4843 "avb_gmii", 4844 }; 4845 4846 static const char * const can0_groups[] = { 4847 "can0_data", 4848 "can0_data_b", 4849 "can0_data_c", 4850 "can0_data_d", 4851 "can0_data_e", 4852 "can0_data_f", 4853 /* 4854 * Retained for backwards compatibility, use can_clk_groups in new 4855 * designs. 4856 */ 4857 "can_clk", 4858 "can_clk_b", 4859 "can_clk_c", 4860 "can_clk_d", 4861 }; 4862 4863 static const char * const can1_groups[] = { 4864 "can1_data", 4865 "can1_data_b", 4866 "can1_data_c", 4867 "can1_data_d", 4868 /* 4869 * Retained for backwards compatibility, use can_clk_groups in new 4870 * designs. 4871 */ 4872 "can_clk", 4873 "can_clk_b", 4874 "can_clk_c", 4875 "can_clk_d", 4876 }; 4877 4878 /* 4879 * can_clk_groups allows for independent configuration, use can_clk function 4880 * in new designs. 4881 */ 4882 static const char * const can_clk_groups[] = { 4883 "can_clk", 4884 "can_clk_b", 4885 "can_clk_c", 4886 "can_clk_d", 4887 }; 4888 4889 static const char * const du_groups[] = { 4890 "du_rgb666", 4891 "du_rgb888", 4892 "du_clk_out_0", 4893 "du_clk_out_1", 4894 "du_sync", 4895 "du_oddf", 4896 "du_cde", 4897 "du_disp", 4898 }; 4899 4900 static const char * const du0_groups[] = { 4901 "du0_clk_in", 4902 }; 4903 4904 static const char * const du1_groups[] = { 4905 "du1_clk_in", 4906 "du1_clk_in_b", 4907 "du1_clk_in_c", 4908 }; 4909 4910 static const char * const eth_groups[] = { 4911 "eth_link", 4912 "eth_magic", 4913 "eth_mdio", 4914 "eth_rmii", 4915 }; 4916 4917 static const char * const hscif0_groups[] = { 4918 "hscif0_data", 4919 "hscif0_clk", 4920 "hscif0_ctrl", 4921 "hscif0_data_b", 4922 "hscif0_ctrl_b", 4923 "hscif0_data_c", 4924 "hscif0_clk_c", 4925 }; 4926 4927 static const char * const hscif1_groups[] = { 4928 "hscif1_data", 4929 "hscif1_clk", 4930 "hscif1_ctrl", 4931 "hscif1_data_b", 4932 "hscif1_data_c", 4933 "hscif1_clk_c", 4934 "hscif1_ctrl_c", 4935 "hscif1_data_d", 4936 "hscif1_data_e", 4937 "hscif1_clk_e", 4938 "hscif1_ctrl_e", 4939 }; 4940 4941 static const char * const hscif2_groups[] = { 4942 "hscif2_data", 4943 "hscif2_clk", 4944 "hscif2_ctrl", 4945 "hscif2_data_b", 4946 "hscif2_ctrl_b", 4947 "hscif2_data_c", 4948 "hscif2_clk_c", 4949 "hscif2_data_d", 4950 }; 4951 4952 static const char * const i2c0_groups[] = { 4953 "i2c0", 4954 "i2c0_b", 4955 "i2c0_c", 4956 }; 4957 4958 static const char * const i2c1_groups[] = { 4959 "i2c1", 4960 "i2c1_b", 4961 "i2c1_c", 4962 "i2c1_d", 4963 "i2c1_e", 4964 }; 4965 4966 static const char * const i2c2_groups[] = { 4967 "i2c2", 4968 "i2c2_b", 4969 "i2c2_c", 4970 "i2c2_d", 4971 }; 4972 4973 static const char * const i2c3_groups[] = { 4974 "i2c3", 4975 "i2c3_b", 4976 "i2c3_c", 4977 "i2c3_d", 4978 }; 4979 4980 static const char * const i2c4_groups[] = { 4981 "i2c4", 4982 "i2c4_b", 4983 "i2c4_c", 4984 }; 4985 4986 static const char * const i2c7_groups[] = { 4987 "i2c7", 4988 "i2c7_b", 4989 "i2c7_c", 4990 }; 4991 4992 static const char * const i2c8_groups[] = { 4993 "i2c8", 4994 "i2c8_b", 4995 "i2c8_c", 4996 }; 4997 4998 static const char * const intc_groups[] = { 4999 "intc_irq0", 5000 "intc_irq1", 5001 "intc_irq2", 5002 "intc_irq3", 5003 }; 5004 5005 static const char * const mlb_groups[] = { 5006 "mlb_3pin", 5007 }; 5008 5009 static const char * const mmc_groups[] = { 5010 "mmc_data1", 5011 "mmc_data4", 5012 "mmc_data8", 5013 "mmc_data8_b", 5014 "mmc_ctrl", 5015 }; 5016 5017 static const char * const msiof0_groups[] = { 5018 "msiof0_clk", 5019 "msiof0_sync", 5020 "msiof0_ss1", 5021 "msiof0_ss2", 5022 "msiof0_rx", 5023 "msiof0_tx", 5024 "msiof0_clk_b", 5025 "msiof0_sync_b", 5026 "msiof0_ss1_b", 5027 "msiof0_ss2_b", 5028 "msiof0_rx_b", 5029 "msiof0_tx_b", 5030 "msiof0_clk_c", 5031 "msiof0_sync_c", 5032 "msiof0_ss1_c", 5033 "msiof0_ss2_c", 5034 "msiof0_rx_c", 5035 "msiof0_tx_c", 5036 }; 5037 5038 static const char * const msiof1_groups[] = { 5039 "msiof1_clk", 5040 "msiof1_sync", 5041 "msiof1_ss1", 5042 "msiof1_ss2", 5043 "msiof1_rx", 5044 "msiof1_tx", 5045 "msiof1_clk_b", 5046 "msiof1_sync_b", 5047 "msiof1_ss1_b", 5048 "msiof1_ss2_b", 5049 "msiof1_rx_b", 5050 "msiof1_tx_b", 5051 "msiof1_clk_c", 5052 "msiof1_sync_c", 5053 "msiof1_rx_c", 5054 "msiof1_tx_c", 5055 "msiof1_clk_d", 5056 "msiof1_sync_d", 5057 "msiof1_ss1_d", 5058 "msiof1_rx_d", 5059 "msiof1_tx_d", 5060 "msiof1_clk_e", 5061 "msiof1_sync_e", 5062 "msiof1_rx_e", 5063 "msiof1_tx_e", 5064 }; 5065 5066 static const char * const msiof2_groups[] = { 5067 "msiof2_clk", 5068 "msiof2_sync", 5069 "msiof2_ss1", 5070 "msiof2_ss2", 5071 "msiof2_rx", 5072 "msiof2_tx", 5073 "msiof2_clk_b", 5074 "msiof2_sync_b", 5075 "msiof2_ss1_b", 5076 "msiof2_ss2_b", 5077 "msiof2_rx_b", 5078 "msiof2_tx_b", 5079 "msiof2_clk_c", 5080 "msiof2_sync_c", 5081 "msiof2_rx_c", 5082 "msiof2_tx_c", 5083 "msiof2_clk_d", 5084 "msiof2_sync_d", 5085 "msiof2_ss1_d", 5086 "msiof2_ss2_d", 5087 "msiof2_rx_d", 5088 "msiof2_tx_d", 5089 "msiof2_clk_e", 5090 "msiof2_sync_e", 5091 "msiof2_rx_e", 5092 "msiof2_tx_e", 5093 }; 5094 5095 static const char * const pwm0_groups[] = { 5096 "pwm0", 5097 "pwm0_b", 5098 }; 5099 5100 static const char * const pwm1_groups[] = { 5101 "pwm1", 5102 "pwm1_b", 5103 }; 5104 5105 static const char * const pwm2_groups[] = { 5106 "pwm2", 5107 "pwm2_b", 5108 }; 5109 5110 static const char * const pwm3_groups[] = { 5111 "pwm3", 5112 }; 5113 5114 static const char * const pwm4_groups[] = { 5115 "pwm4", 5116 "pwm4_b", 5117 }; 5118 5119 static const char * const pwm5_groups[] = { 5120 "pwm5", 5121 "pwm5_b", 5122 }; 5123 5124 static const char * const pwm6_groups[] = { 5125 "pwm6", 5126 }; 5127 5128 static const char * const qspi_groups[] = { 5129 "qspi_ctrl", 5130 "qspi_data2", 5131 "qspi_data4", 5132 "qspi_ctrl_b", 5133 "qspi_data2_b", 5134 "qspi_data4_b", 5135 }; 5136 5137 static const char * const scif0_groups[] = { 5138 "scif0_data", 5139 "scif0_data_b", 5140 "scif0_data_c", 5141 "scif0_data_d", 5142 "scif0_data_e", 5143 }; 5144 5145 static const char * const scif1_groups[] = { 5146 "scif1_data", 5147 "scif1_data_b", 5148 "scif1_clk_b", 5149 "scif1_data_c", 5150 "scif1_data_d", 5151 }; 5152 5153 static const char * const scif2_groups[] = { 5154 "scif2_data", 5155 "scif2_data_b", 5156 "scif2_clk_b", 5157 "scif2_data_c", 5158 "scif2_data_e", 5159 }; 5160 static const char * const scif3_groups[] = { 5161 "scif3_data", 5162 "scif3_clk", 5163 "scif3_data_b", 5164 "scif3_clk_b", 5165 "scif3_data_c", 5166 "scif3_data_d", 5167 }; 5168 static const char * const scif4_groups[] = { 5169 "scif4_data", 5170 "scif4_data_b", 5171 "scif4_data_c", 5172 }; 5173 static const char * const scif5_groups[] = { 5174 "scif5_data", 5175 "scif5_data_b", 5176 }; 5177 static const char * const scifa0_groups[] = { 5178 "scifa0_data", 5179 "scifa0_data_b", 5180 }; 5181 static const char * const scifa1_groups[] = { 5182 "scifa1_data", 5183 "scifa1_clk", 5184 "scifa1_data_b", 5185 "scifa1_clk_b", 5186 "scifa1_data_c", 5187 }; 5188 static const char * const scifa2_groups[] = { 5189 "scifa2_data", 5190 "scifa2_clk", 5191 "scifa2_data_b", 5192 }; 5193 static const char * const scifa3_groups[] = { 5194 "scifa3_data", 5195 "scifa3_clk", 5196 "scifa3_data_b", 5197 "scifa3_clk_b", 5198 "scifa3_data_c", 5199 "scifa3_clk_c", 5200 }; 5201 static const char * const scifa4_groups[] = { 5202 "scifa4_data", 5203 "scifa4_data_b", 5204 "scifa4_data_c", 5205 }; 5206 static const char * const scifa5_groups[] = { 5207 "scifa5_data", 5208 "scifa5_data_b", 5209 "scifa5_data_c", 5210 }; 5211 static const char * const scifb0_groups[] = { 5212 "scifb0_data", 5213 "scifb0_clk", 5214 "scifb0_ctrl", 5215 "scifb0_data_b", 5216 "scifb0_clk_b", 5217 "scifb0_ctrl_b", 5218 "scifb0_data_c", 5219 "scifb0_clk_c", 5220 "scifb0_data_d", 5221 "scifb0_clk_d", 5222 }; 5223 static const char * const scifb1_groups[] = { 5224 "scifb1_data", 5225 "scifb1_clk", 5226 "scifb1_ctrl", 5227 "scifb1_data_b", 5228 "scifb1_clk_b", 5229 "scifb1_data_c", 5230 "scifb1_clk_c", 5231 "scifb1_data_d", 5232 }; 5233 static const char * const scifb2_groups[] = { 5234 "scifb2_data", 5235 "scifb2_clk", 5236 "scifb2_ctrl", 5237 "scifb2_data_b", 5238 "scifb2_clk_b", 5239 "scifb2_ctrl_b", 5240 "scifb2_data_c", 5241 "scifb2_clk_c", 5242 "scifb2_data_d", 5243 }; 5244 5245 static const char * const scif_clk_groups[] = { 5246 "scif_clk", 5247 "scif_clk_b", 5248 }; 5249 5250 static const char * const sdhi0_groups[] = { 5251 "sdhi0_data1", 5252 "sdhi0_data4", 5253 "sdhi0_ctrl", 5254 "sdhi0_cd", 5255 "sdhi0_wp", 5256 }; 5257 5258 static const char * const sdhi1_groups[] = { 5259 "sdhi1_data1", 5260 "sdhi1_data4", 5261 "sdhi1_ctrl", 5262 "sdhi1_cd", 5263 "sdhi1_wp", 5264 }; 5265 5266 static const char * const sdhi2_groups[] = { 5267 "sdhi2_data1", 5268 "sdhi2_data4", 5269 "sdhi2_ctrl", 5270 "sdhi2_cd", 5271 "sdhi2_wp", 5272 }; 5273 5274 static const char * const ssi_groups[] = { 5275 "ssi0_data", 5276 "ssi0_data_b", 5277 "ssi0129_ctrl", 5278 "ssi0129_ctrl_b", 5279 "ssi1_data", 5280 "ssi1_data_b", 5281 "ssi1_ctrl", 5282 "ssi1_ctrl_b", 5283 "ssi2_data", 5284 "ssi2_ctrl", 5285 "ssi3_data", 5286 "ssi34_ctrl", 5287 "ssi4_data", 5288 "ssi4_ctrl", 5289 "ssi5_data", 5290 "ssi5_ctrl", 5291 "ssi6_data", 5292 "ssi6_ctrl", 5293 "ssi7_data", 5294 "ssi7_data_b", 5295 "ssi78_ctrl", 5296 "ssi78_ctrl_b", 5297 "ssi8_data", 5298 "ssi8_data_b", 5299 "ssi9_data", 5300 "ssi9_data_b", 5301 "ssi9_ctrl", 5302 "ssi9_ctrl_b", 5303 }; 5304 5305 static const char * const tpu_groups[] = { 5306 "tpu_to0", 5307 "tpu_to1", 5308 "tpu_to2", 5309 "tpu_to3", 5310 }; 5311 5312 static const char * const usb0_groups[] = { 5313 "usb0", 5314 }; 5315 static const char * const usb1_groups[] = { 5316 "usb1", 5317 }; 5318 5319 static const char * const vin0_groups[] = { 5320 "vin0_data24", 5321 "vin0_data20", 5322 "vin0_data18", 5323 "vin0_data16", 5324 "vin0_data12", 5325 "vin0_data10", 5326 "vin0_data8", 5327 "vin0_sync", 5328 "vin0_field", 5329 "vin0_clkenb", 5330 "vin0_clk", 5331 }; 5332 5333 static const char * const vin1_groups[] = { 5334 "vin1_data8", 5335 "vin1_sync", 5336 "vin1_field", 5337 "vin1_clkenb", 5338 "vin1_clk", 5339 "vin1_data24_b", 5340 "vin1_data20_b", 5341 "vin1_data18_b", 5342 "vin1_data16_b", 5343 "vin1_data12_b", 5344 "vin1_data10_b", 5345 "vin1_data8_b", 5346 "vin1_sync_b", 5347 "vin1_field_b", 5348 "vin1_clkenb_b", 5349 "vin1_clk_b", 5350 }; 5351 5352 static const char * const vin2_groups[] = { 5353 "vin2_data8", 5354 "vin2_sync", 5355 "vin2_field", 5356 "vin2_clkenb", 5357 "vin2_clk", 5358 }; 5359 5360 static const struct { 5361 struct sh_pfc_function common[58]; 5362 struct sh_pfc_function automotive[2]; 5363 } pinmux_functions = { 5364 .common = { 5365 SH_PFC_FUNCTION(audio_clk), 5366 SH_PFC_FUNCTION(avb), 5367 SH_PFC_FUNCTION(can0), 5368 SH_PFC_FUNCTION(can1), 5369 SH_PFC_FUNCTION(can_clk), 5370 SH_PFC_FUNCTION(du), 5371 SH_PFC_FUNCTION(du0), 5372 SH_PFC_FUNCTION(du1), 5373 SH_PFC_FUNCTION(eth), 5374 SH_PFC_FUNCTION(hscif0), 5375 SH_PFC_FUNCTION(hscif1), 5376 SH_PFC_FUNCTION(hscif2), 5377 SH_PFC_FUNCTION(i2c0), 5378 SH_PFC_FUNCTION(i2c1), 5379 SH_PFC_FUNCTION(i2c2), 5380 SH_PFC_FUNCTION(i2c3), 5381 SH_PFC_FUNCTION(i2c4), 5382 SH_PFC_FUNCTION(i2c7), 5383 SH_PFC_FUNCTION(i2c8), 5384 SH_PFC_FUNCTION(intc), 5385 SH_PFC_FUNCTION(mmc), 5386 SH_PFC_FUNCTION(msiof0), 5387 SH_PFC_FUNCTION(msiof1), 5388 SH_PFC_FUNCTION(msiof2), 5389 SH_PFC_FUNCTION(pwm0), 5390 SH_PFC_FUNCTION(pwm1), 5391 SH_PFC_FUNCTION(pwm2), 5392 SH_PFC_FUNCTION(pwm3), 5393 SH_PFC_FUNCTION(pwm4), 5394 SH_PFC_FUNCTION(pwm5), 5395 SH_PFC_FUNCTION(pwm6), 5396 SH_PFC_FUNCTION(qspi), 5397 SH_PFC_FUNCTION(scif0), 5398 SH_PFC_FUNCTION(scif1), 5399 SH_PFC_FUNCTION(scif2), 5400 SH_PFC_FUNCTION(scif3), 5401 SH_PFC_FUNCTION(scif4), 5402 SH_PFC_FUNCTION(scif5), 5403 SH_PFC_FUNCTION(scifa0), 5404 SH_PFC_FUNCTION(scifa1), 5405 SH_PFC_FUNCTION(scifa2), 5406 SH_PFC_FUNCTION(scifa3), 5407 SH_PFC_FUNCTION(scifa4), 5408 SH_PFC_FUNCTION(scifa5), 5409 SH_PFC_FUNCTION(scifb0), 5410 SH_PFC_FUNCTION(scifb1), 5411 SH_PFC_FUNCTION(scifb2), 5412 SH_PFC_FUNCTION(scif_clk), 5413 SH_PFC_FUNCTION(sdhi0), 5414 SH_PFC_FUNCTION(sdhi1), 5415 SH_PFC_FUNCTION(sdhi2), 5416 SH_PFC_FUNCTION(ssi), 5417 SH_PFC_FUNCTION(tpu), 5418 SH_PFC_FUNCTION(usb0), 5419 SH_PFC_FUNCTION(usb1), 5420 SH_PFC_FUNCTION(vin0), 5421 SH_PFC_FUNCTION(vin1), 5422 SH_PFC_FUNCTION(vin2), 5423 }, 5424 .automotive = { 5425 SH_PFC_FUNCTION(adi), 5426 SH_PFC_FUNCTION(mlb), 5427 } 5428 }; 5429 5430 static const struct pinmux_cfg_reg pinmux_config_regs[] = { 5431 { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1, GROUP( 5432 GP_0_31_FN, FN_IP1_22_20, 5433 GP_0_30_FN, FN_IP1_19_17, 5434 GP_0_29_FN, FN_IP1_16_14, 5435 GP_0_28_FN, FN_IP1_13_11, 5436 GP_0_27_FN, FN_IP1_10_8, 5437 GP_0_26_FN, FN_IP1_7_6, 5438 GP_0_25_FN, FN_IP1_5_4, 5439 GP_0_24_FN, FN_IP1_3_2, 5440 GP_0_23_FN, FN_IP1_1_0, 5441 GP_0_22_FN, FN_IP0_30_29, 5442 GP_0_21_FN, FN_IP0_28_27, 5443 GP_0_20_FN, FN_IP0_26_25, 5444 GP_0_19_FN, FN_IP0_24_23, 5445 GP_0_18_FN, FN_IP0_22_21, 5446 GP_0_17_FN, FN_IP0_20_19, 5447 GP_0_16_FN, FN_IP0_18_16, 5448 GP_0_15_FN, FN_IP0_15, 5449 GP_0_14_FN, FN_IP0_14, 5450 GP_0_13_FN, FN_IP0_13, 5451 GP_0_12_FN, FN_IP0_12, 5452 GP_0_11_FN, FN_IP0_11, 5453 GP_0_10_FN, FN_IP0_10, 5454 GP_0_9_FN, FN_IP0_9, 5455 GP_0_8_FN, FN_IP0_8, 5456 GP_0_7_FN, FN_IP0_7, 5457 GP_0_6_FN, FN_IP0_6, 5458 GP_0_5_FN, FN_IP0_5, 5459 GP_0_4_FN, FN_IP0_4, 5460 GP_0_3_FN, FN_IP0_3, 5461 GP_0_2_FN, FN_IP0_2, 5462 GP_0_1_FN, FN_IP0_1, 5463 GP_0_0_FN, FN_IP0_0, )) 5464 }, 5465 { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1, GROUP( 5466 0, 0, 5467 0, 0, 5468 0, 0, 5469 0, 0, 5470 0, 0, 5471 0, 0, 5472 GP_1_25_FN, FN_IP3_21_20, 5473 GP_1_24_FN, FN_IP3_19_18, 5474 GP_1_23_FN, FN_IP3_17_16, 5475 GP_1_22_FN, FN_IP3_15_14, 5476 GP_1_21_FN, FN_IP3_13_12, 5477 GP_1_20_FN, FN_IP3_11_9, 5478 GP_1_19_FN, FN_RD_N, 5479 GP_1_18_FN, FN_IP3_8_6, 5480 GP_1_17_FN, FN_IP3_5_3, 5481 GP_1_16_FN, FN_IP3_2_0, 5482 GP_1_15_FN, FN_IP2_29_27, 5483 GP_1_14_FN, FN_IP2_26_25, 5484 GP_1_13_FN, FN_IP2_24_23, 5485 GP_1_12_FN, FN_EX_CS0_N, 5486 GP_1_11_FN, FN_IP2_22_21, 5487 GP_1_10_FN, FN_IP2_20_19, 5488 GP_1_9_FN, FN_IP2_18_16, 5489 GP_1_8_FN, FN_IP2_15_13, 5490 GP_1_7_FN, FN_IP2_12_10, 5491 GP_1_6_FN, FN_IP2_9_7, 5492 GP_1_5_FN, FN_IP2_6_5, 5493 GP_1_4_FN, FN_IP2_4_3, 5494 GP_1_3_FN, FN_IP2_2_0, 5495 GP_1_2_FN, FN_IP1_31_29, 5496 GP_1_1_FN, FN_IP1_28_26, 5497 GP_1_0_FN, FN_IP1_25_23, )) 5498 }, 5499 { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1, GROUP( 5500 GP_2_31_FN, FN_IP6_7_6, 5501 GP_2_30_FN, FN_IP6_5_3, 5502 GP_2_29_FN, FN_IP6_2_0, 5503 GP_2_28_FN, FN_AUDIO_CLKA, 5504 GP_2_27_FN, FN_IP5_31_29, 5505 GP_2_26_FN, FN_IP5_28_26, 5506 GP_2_25_FN, FN_IP5_25_24, 5507 GP_2_24_FN, FN_IP5_23_22, 5508 GP_2_23_FN, FN_IP5_21_20, 5509 GP_2_22_FN, FN_IP5_19_17, 5510 GP_2_21_FN, FN_IP5_16_15, 5511 GP_2_20_FN, FN_IP5_14_12, 5512 GP_2_19_FN, FN_IP5_11_9, 5513 GP_2_18_FN, FN_IP5_8_6, 5514 GP_2_17_FN, FN_IP5_5_3, 5515 GP_2_16_FN, FN_IP5_2_0, 5516 GP_2_15_FN, FN_IP4_30_28, 5517 GP_2_14_FN, FN_IP4_27_26, 5518 GP_2_13_FN, FN_IP4_25_24, 5519 GP_2_12_FN, FN_IP4_23_22, 5520 GP_2_11_FN, FN_IP4_21, 5521 GP_2_10_FN, FN_IP4_20, 5522 GP_2_9_FN, FN_IP4_19, 5523 GP_2_8_FN, FN_IP4_18_16, 5524 GP_2_7_FN, FN_IP4_15_13, 5525 GP_2_6_FN, FN_IP4_12_10, 5526 GP_2_5_FN, FN_IP4_9_8, 5527 GP_2_4_FN, FN_IP4_7_5, 5528 GP_2_3_FN, FN_IP4_4_2, 5529 GP_2_2_FN, FN_IP4_1_0, 5530 GP_2_1_FN, FN_IP3_30_28, 5531 GP_2_0_FN, FN_IP3_27_25 )) 5532 }, 5533 { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1, GROUP( 5534 GP_3_31_FN, FN_IP9_18_17, 5535 GP_3_30_FN, FN_IP9_16, 5536 GP_3_29_FN, FN_IP9_15_13, 5537 GP_3_28_FN, FN_IP9_12, 5538 GP_3_27_FN, FN_IP9_11, 5539 GP_3_26_FN, FN_IP9_10_8, 5540 GP_3_25_FN, FN_IP9_7, 5541 GP_3_24_FN, FN_IP9_6, 5542 GP_3_23_FN, FN_IP9_5_3, 5543 GP_3_22_FN, FN_IP9_2_0, 5544 GP_3_21_FN, FN_IP8_30_28, 5545 GP_3_20_FN, FN_IP8_27_26, 5546 GP_3_19_FN, FN_IP8_25_24, 5547 GP_3_18_FN, FN_IP8_23_21, 5548 GP_3_17_FN, FN_IP8_20_18, 5549 GP_3_16_FN, FN_IP8_17_15, 5550 GP_3_15_FN, FN_IP8_14_12, 5551 GP_3_14_FN, FN_IP8_11_9, 5552 GP_3_13_FN, FN_IP8_8_6, 5553 GP_3_12_FN, FN_IP8_5_3, 5554 GP_3_11_FN, FN_IP8_2_0, 5555 GP_3_10_FN, FN_IP7_29_27, 5556 GP_3_9_FN, FN_IP7_26_24, 5557 GP_3_8_FN, FN_IP7_23_21, 5558 GP_3_7_FN, FN_IP7_20_19, 5559 GP_3_6_FN, FN_IP7_18_17, 5560 GP_3_5_FN, FN_IP7_16_15, 5561 GP_3_4_FN, FN_IP7_14_13, 5562 GP_3_3_FN, FN_IP7_12_11, 5563 GP_3_2_FN, FN_IP7_10_9, 5564 GP_3_1_FN, FN_IP7_8_6, 5565 GP_3_0_FN, FN_IP7_5_3 )) 5566 }, 5567 { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1, GROUP( 5568 GP_4_31_FN, FN_IP15_5_4, 5569 GP_4_30_FN, FN_IP15_3_2, 5570 GP_4_29_FN, FN_IP15_1_0, 5571 GP_4_28_FN, FN_IP11_8_6, 5572 GP_4_27_FN, FN_IP11_5_3, 5573 GP_4_26_FN, FN_IP11_2_0, 5574 GP_4_25_FN, FN_IP10_31_29, 5575 GP_4_24_FN, FN_IP10_28_27, 5576 GP_4_23_FN, FN_IP10_26_25, 5577 GP_4_22_FN, FN_IP10_24_22, 5578 GP_4_21_FN, FN_IP10_21_19, 5579 GP_4_20_FN, FN_IP10_18_17, 5580 GP_4_19_FN, FN_IP10_16_15, 5581 GP_4_18_FN, FN_IP10_14_12, 5582 GP_4_17_FN, FN_IP10_11_9, 5583 GP_4_16_FN, FN_IP10_8_6, 5584 GP_4_15_FN, FN_IP10_5_3, 5585 GP_4_14_FN, FN_IP10_2_0, 5586 GP_4_13_FN, FN_IP9_31_29, 5587 GP_4_12_FN, FN_VI0_DATA7_VI0_B7, 5588 GP_4_11_FN, FN_VI0_DATA6_VI0_B6, 5589 GP_4_10_FN, FN_VI0_DATA5_VI0_B5, 5590 GP_4_9_FN, FN_VI0_DATA4_VI0_B4, 5591 GP_4_8_FN, FN_IP9_28_27, 5592 GP_4_7_FN, FN_VI0_DATA2_VI0_B2, 5593 GP_4_6_FN, FN_VI0_DATA1_VI0_B1, 5594 GP_4_5_FN, FN_VI0_DATA0_VI0_B0, 5595 GP_4_4_FN, FN_IP9_26_25, 5596 GP_4_3_FN, FN_IP9_24_23, 5597 GP_4_2_FN, FN_IP9_22_21, 5598 GP_4_1_FN, FN_IP9_20_19, 5599 GP_4_0_FN, FN_VI0_CLK )) 5600 }, 5601 { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1, GROUP( 5602 GP_5_31_FN, FN_IP3_24_22, 5603 GP_5_30_FN, FN_IP13_9_7, 5604 GP_5_29_FN, FN_IP13_6_5, 5605 GP_5_28_FN, FN_IP13_4_3, 5606 GP_5_27_FN, FN_IP13_2_0, 5607 GP_5_26_FN, FN_IP12_29_27, 5608 GP_5_25_FN, FN_IP12_26_24, 5609 GP_5_24_FN, FN_IP12_23_22, 5610 GP_5_23_FN, FN_IP12_21_20, 5611 GP_5_22_FN, FN_IP12_19_18, 5612 GP_5_21_FN, FN_IP12_17_16, 5613 GP_5_20_FN, FN_IP12_15_13, 5614 GP_5_19_FN, FN_IP12_12_10, 5615 GP_5_18_FN, FN_IP12_9_7, 5616 GP_5_17_FN, FN_IP12_6_4, 5617 GP_5_16_FN, FN_IP12_3_2, 5618 GP_5_15_FN, FN_IP12_1_0, 5619 GP_5_14_FN, FN_IP11_31_30, 5620 GP_5_13_FN, FN_IP11_29_28, 5621 GP_5_12_FN, FN_IP11_27, 5622 GP_5_11_FN, FN_IP11_26, 5623 GP_5_10_FN, FN_IP11_25, 5624 GP_5_9_FN, FN_IP11_24, 5625 GP_5_8_FN, FN_IP11_23, 5626 GP_5_7_FN, FN_IP11_22, 5627 GP_5_6_FN, FN_IP11_21, 5628 GP_5_5_FN, FN_IP11_20, 5629 GP_5_4_FN, FN_IP11_19, 5630 GP_5_3_FN, FN_IP11_18_17, 5631 GP_5_2_FN, FN_IP11_16_15, 5632 GP_5_1_FN, FN_IP11_14_12, 5633 GP_5_0_FN, FN_IP11_11_9 )) 5634 }, 5635 { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1, GROUP( 5636 GP_6_31_FN, FN_DU0_DOTCLKIN, 5637 GP_6_30_FN, FN_USB1_OVC, 5638 GP_6_29_FN, FN_IP14_31_29, 5639 GP_6_28_FN, FN_IP14_28_26, 5640 GP_6_27_FN, FN_IP14_25_23, 5641 GP_6_26_FN, FN_IP14_22_20, 5642 GP_6_25_FN, FN_IP14_19_17, 5643 GP_6_24_FN, FN_IP14_16_14, 5644 GP_6_23_FN, FN_IP14_13_11, 5645 GP_6_22_FN, FN_IP14_10_8, 5646 GP_6_21_FN, FN_IP14_7, 5647 GP_6_20_FN, FN_IP14_6, 5648 GP_6_19_FN, FN_IP14_5, 5649 GP_6_18_FN, FN_IP14_4, 5650 GP_6_17_FN, FN_IP14_3, 5651 GP_6_16_FN, FN_IP14_2, 5652 GP_6_15_FN, FN_IP14_1_0, 5653 GP_6_14_FN, FN_IP13_30_28, 5654 GP_6_13_FN, FN_IP13_27, 5655 GP_6_12_FN, FN_IP13_26, 5656 GP_6_11_FN, FN_IP13_25, 5657 GP_6_10_FN, FN_IP13_24_23, 5658 GP_6_9_FN, FN_IP13_22, 5659 GP_6_8_FN, FN_SD1_CLK, 5660 GP_6_7_FN, FN_IP13_21_19, 5661 GP_6_6_FN, FN_IP13_18_16, 5662 GP_6_5_FN, FN_IP13_15, 5663 GP_6_4_FN, FN_IP13_14, 5664 GP_6_3_FN, FN_IP13_13, 5665 GP_6_2_FN, FN_IP13_12, 5666 GP_6_1_FN, FN_IP13_11, 5667 GP_6_0_FN, FN_IP13_10 )) 5668 }, 5669 { PINMUX_CFG_REG("GPSR7", 0xE6060074, 32, 1, GROUP( 5670 0, 0, 5671 0, 0, 5672 0, 0, 5673 0, 0, 5674 0, 0, 5675 0, 0, 5676 GP_7_25_FN, FN_USB1_PWEN, 5677 GP_7_24_FN, FN_USB0_OVC, 5678 GP_7_23_FN, FN_USB0_PWEN, 5679 GP_7_22_FN, FN_IP15_14_12, 5680 GP_7_21_FN, FN_IP15_11_9, 5681 GP_7_20_FN, FN_IP15_8_6, 5682 GP_7_19_FN, FN_IP7_2_0, 5683 GP_7_18_FN, FN_IP6_29_27, 5684 GP_7_17_FN, FN_IP6_26_24, 5685 GP_7_16_FN, FN_IP6_23_21, 5686 GP_7_15_FN, FN_IP6_20_19, 5687 GP_7_14_FN, FN_IP6_18_16, 5688 GP_7_13_FN, FN_IP6_15_14, 5689 GP_7_12_FN, FN_IP6_13_12, 5690 GP_7_11_FN, FN_IP6_11_10, 5691 GP_7_10_FN, FN_IP6_9_8, 5692 GP_7_9_FN, FN_IP16_11_10, 5693 GP_7_8_FN, FN_IP16_9_8, 5694 GP_7_7_FN, FN_IP16_7_6, 5695 GP_7_6_FN, FN_IP16_5_3, 5696 GP_7_5_FN, FN_IP16_2_0, 5697 GP_7_4_FN, FN_IP15_29_27, 5698 GP_7_3_FN, FN_IP15_26_24, 5699 GP_7_2_FN, FN_IP15_23_21, 5700 GP_7_1_FN, FN_IP15_20_18, 5701 GP_7_0_FN, FN_IP15_17_15 )) 5702 }, 5703 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32, 5704 GROUP(1, 2, 2, 2, 2, 2, 2, 3, 1, 1, 1, 1, 5705 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), 5706 GROUP( 5707 /* IP0_31 [1] */ 5708 0, 0, 5709 /* IP0_30_29 [2] */ 5710 FN_A6, FN_MSIOF1_SCK, 5711 0, 0, 5712 /* IP0_28_27 [2] */ 5713 FN_A5, FN_MSIOF0_RXD_B, 5714 0, 0, 5715 /* IP0_26_25 [2] */ 5716 FN_A4, FN_MSIOF0_TXD_B, 5717 0, 0, 5718 /* IP0_24_23 [2] */ 5719 FN_A3, FN_MSIOF0_SS2_B, 5720 0, 0, 5721 /* IP0_22_21 [2] */ 5722 FN_A2, FN_MSIOF0_SS1_B, 5723 0, 0, 5724 /* IP0_20_19 [2] */ 5725 FN_A1, FN_MSIOF0_SYNC_B, 5726 0, 0, 5727 /* IP0_18_16 [3] */ 5728 FN_A0, FN_ATAWR0_N_C, FN_MSIOF0_SCK_B, FN_I2C0_SCL_C, FN_PWM2_B, 5729 0, 0, 0, 5730 /* IP0_15 [1] */ 5731 FN_D15, 0, 5732 /* IP0_14 [1] */ 5733 FN_D14, 0, 5734 /* IP0_13 [1] */ 5735 FN_D13, 0, 5736 /* IP0_12 [1] */ 5737 FN_D12, 0, 5738 /* IP0_11 [1] */ 5739 FN_D11, 0, 5740 /* IP0_10 [1] */ 5741 FN_D10, 0, 5742 /* IP0_9 [1] */ 5743 FN_D9, 0, 5744 /* IP0_8 [1] */ 5745 FN_D8, 0, 5746 /* IP0_7 [1] */ 5747 FN_D7, 0, 5748 /* IP0_6 [1] */ 5749 FN_D6, 0, 5750 /* IP0_5 [1] */ 5751 FN_D5, 0, 5752 /* IP0_4 [1] */ 5753 FN_D4, 0, 5754 /* IP0_3 [1] */ 5755 FN_D3, 0, 5756 /* IP0_2 [1] */ 5757 FN_D2, 0, 5758 /* IP0_1 [1] */ 5759 FN_D1, 0, 5760 /* IP0_0 [1] */ 5761 FN_D0, 0, )) 5762 }, 5763 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32, 5764 GROUP(3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2), 5765 GROUP( 5766 /* IP1_31_29 [3] */ 5767 FN_A18, FN_DREQ1, FN_SCIFA1_RXD_C, 0, FN_SCIFB1_RXD_C, 5768 0, 0, 0, 5769 /* IP1_28_26 [3] */ 5770 FN_A17, FN_DACK2_B, 0, FN_I2C0_SDA_C, 5771 0, 0, 0, 0, 5772 /* IP1_25_23 [3] */ 5773 FN_A16, FN_DREQ2_B, FN_FMCLK_C, 0, FN_SCIFA1_SCK_B, 5774 0, 0, 0, 5775 /* IP1_22_20 [3] */ 5776 FN_A15, FN_BPFCLK_C, 5777 0, 0, 0, 0, 0, 0, 5778 /* IP1_19_17 [3] */ 5779 FN_A14, FN_ATADIR0_N_C, FN_FMIN, FN_FMIN_C, FN_MSIOF1_SYNC_D, 5780 0, 0, 0, 5781 /* IP1_16_14 [3] */ 5782 FN_A13, FN_ATAG0_N_C, FN_BPFCLK, FN_MSIOF1_SS1_D, 5783 0, 0, 0, 0, 5784 /* IP1_13_11 [3] */ 5785 FN_A12, FN_FMCLK, FN_I2C3_SDA_D, FN_MSIOF1_SCK_D, 5786 0, 0, 0, 0, 5787 /* IP1_10_8 [3] */ 5788 FN_A11, FN_MSIOF1_RXD, FN_I2C3_SCL_D, FN_MSIOF1_RXD_D, 5789 0, 0, 0, 0, 5790 /* IP1_7_6 [2] */ 5791 FN_A10, FN_MSIOF1_TXD, 0, FN_MSIOF1_TXD_D, 5792 /* IP1_5_4 [2] */ 5793 FN_A9, FN_MSIOF1_SS2, FN_I2C0_SDA, 0, 5794 /* IP1_3_2 [2] */ 5795 FN_A8, FN_MSIOF1_SS1, FN_I2C0_SCL, 0, 5796 /* IP1_1_0 [2] */ 5797 FN_A7, FN_MSIOF1_SYNC, 5798 0, 0, )) 5799 }, 5800 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32, 5801 GROUP(2, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2, 3), 5802 GROUP( 5803 /* IP2_31_30 [2] */ 5804 0, 0, 0, 0, 5805 /* IP2_29_27 [3] */ 5806 FN_EX_CS3_N, FN_ATADIR0_N, FN_MSIOF2_TXD, 5807 FN_ATAG0_N, 0, FN_EX_WAIT1, 5808 0, 0, 5809 /* IP2_26_25 [2] */ 5810 FN_EX_CS2_N, FN_ATAWR0_N, FN_MSIOF2_SYNC, 0, 5811 /* IP2_24_23 [2] */ 5812 FN_EX_CS1_N, FN_MSIOF2_SCK, 0, 0, 5813 /* IP2_22_21 [2] */ 5814 FN_CS1_N_A26, FN_ATADIR0_N_B, FN_I2C1_SDA, 0, 5815 /* IP2_20_19 [2] */ 5816 FN_CS0_N, FN_ATAG0_N_B, FN_I2C1_SCL, 0, 5817 /* IP2_18_16 [3] */ 5818 FN_A25, FN_DACK2, FN_SSL, FN_DREQ1_C, FN_RX1, FN_SCIFA1_RXD, 5819 0, 0, 5820 /* IP2_15_13 [3] */ 5821 FN_A24, FN_DREQ2, FN_IO3, FN_TX1, FN_SCIFA1_TXD, 5822 0, 0, 0, 5823 /* IP2_12_10 [3] */ 5824 FN_A23, FN_IO2, FN_BPFCLK_B, FN_RX0, FN_SCIFA0_RXD, 5825 0, 0, 0, 5826 /* IP2_9_7 [3] */ 5827 FN_A22, FN_MISO_IO1, FN_FMCLK_B, FN_TX0, FN_SCIFA0_TXD, 5828 0, 0, 0, 5829 /* IP2_6_5 [2] */ 5830 FN_A21, FN_ATAWR0_N_B, FN_MOSI_IO0, 0, 5831 /* IP2_4_3 [2] */ 5832 FN_A20, FN_SPCLK, 0, 0, 5833 /* IP2_2_0 [3] */ 5834 FN_A19, FN_DACK1, FN_SCIFA1_TXD_C, 0, 5835 FN_SCIFB1_TXD_C, 0, FN_SCIFB1_SCK_B, 0, )) 5836 }, 5837 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32, 5838 GROUP(1, 3, 3, 3, 2, 2, 2, 2, 2, 3, 3, 3, 3), 5839 GROUP( 5840 /* IP3_31 [1] */ 5841 0, 0, 5842 /* IP3_30_28 [3] */ 5843 FN_SSI_WS0129, FN_HTX0_C, FN_HTX2_C, 5844 FN_SCIFB0_TXD_C, FN_SCIFB2_TXD_C, 5845 0, 0, 0, 5846 /* IP3_27_25 [3] */ 5847 FN_SSI_SCK0129, FN_HRX0_C, FN_HRX2_C, 5848 FN_SCIFB0_RXD_C, FN_SCIFB2_RXD_C, 5849 0, 0, 0, 5850 /* IP3_24_22 [3] */ 5851 FN_SPEEDIN, 0, FN_HSCK0_C, FN_HSCK2_C, FN_SCIFB0_SCK_B, 5852 FN_SCIFB2_SCK_B, FN_DREQ2_C, FN_HTX2_D, 5853 /* IP3_21_20 [2] */ 5854 FN_DACK0, FN_DRACK0, FN_REMOCON, 0, 5855 /* IP3_19_18 [2] */ 5856 FN_DREQ0, FN_PWM3, FN_TPU_TO3, 0, 5857 /* IP3_17_16 [2] */ 5858 FN_EX_WAIT0, FN_HRTS2_N_B, FN_SCIFB0_CTS_N_B, 0, 5859 /* IP3_15_14 [2] */ 5860 FN_WE1_N, FN_ATARD0_N_B, FN_HTX2_B, FN_SCIFB0_RTS_N_B, 5861 /* IP3_13_12 [2] */ 5862 FN_WE0_N, FN_HCTS2_N_B, FN_SCIFB0_TXD_B, 0, 5863 /* IP3_11_9 [3] */ 5864 FN_RD_WR_N, FN_HRX2_B, FN_FMIN_B, FN_SCIFB0_RXD_B, FN_DREQ1_D, 5865 0, 0, 0, 5866 /* IP3_8_6 [3] */ 5867 FN_BS_N, FN_ATACS10_N, FN_MSIOF2_SS2, FN_HTX1_B, 5868 FN_SCIFB1_TXD_B, FN_PWM2, FN_TPU_TO2, 0, 5869 /* IP3_5_3 [3] */ 5870 FN_EX_CS5_N, FN_ATACS00_N, FN_MSIOF2_SS1, FN_HRX1_B, 5871 FN_SCIFB1_RXD_B, FN_PWM1, FN_TPU_TO1, 0, 5872 /* IP3_2_0 [3] */ 5873 FN_EX_CS4_N, FN_ATARD0_N, FN_MSIOF2_RXD, 0, FN_EX_WAIT2, 5874 0, 0, 0, )) 5875 }, 5876 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32, 5877 GROUP(1, 3, 2, 2, 2, 1, 1, 1, 3, 3, 3, 2, 5878 3, 3, 2), 5879 GROUP( 5880 /* IP4_31 [1] */ 5881 0, 0, 5882 /* IP4_30_28 [3] */ 5883 FN_SSI_SCK5, FN_MSIOF1_SCK_C, FN_TS_SDATA0, FN_GLO_I0, 5884 FN_MSIOF2_SYNC_D, FN_VI1_R2_B, 5885 0, 0, 5886 /* IP4_27_26 [2] */ 5887 FN_SSI_SDATA4, FN_MSIOF2_SCK_D, 0, 0, 5888 /* IP4_25_24 [2] */ 5889 FN_SSI_WS4, FN_GLO_RFON_D, 0, 0, 5890 /* IP4_23_22 [2] */ 5891 FN_SSI_SCK4, FN_GLO_SS_D, 0, 0, 5892 /* IP4_21 [1] */ 5893 FN_SSI_SDATA3, 0, 5894 /* IP4_20 [1] */ 5895 FN_SSI_WS34, 0, 5896 /* IP4_19 [1] */ 5897 FN_SSI_SCK34, 0, 5898 /* IP4_18_16 [3] */ 5899 FN_SSI_SDATA2, FN_GPS_MAG_B, FN_TX2_E, FN_HRTS1_N_E, 5900 0, 0, 0, 0, 5901 /* IP4_15_13 [3] */ 5902 FN_SSI_WS2, FN_I2C2_SDA, FN_GPS_SIGN_B, FN_RX2_E, 5903 FN_GLO_Q1_D, FN_HCTS1_N_E, 5904 0, 0, 5905 /* IP4_12_10 [3] */ 5906 FN_SSI_SCK2, FN_I2C2_SCL, FN_GPS_CLK_B, FN_GLO_Q0_D, FN_HSCK1_E, 5907 0, 0, 0, 5908 /* IP4_9_8 [2] */ 5909 FN_SSI_SDATA1, FN_I2C1_SDA_B, FN_IIC1_SDA_B, FN_MSIOF2_RXD_C, 5910 /* IP4_7_5 [3] */ 5911 FN_SSI_WS1, FN_I2C1_SCL_B, FN_IIC1_SCL_B, FN_MSIOF2_TXD_C, 5912 FN_GLO_I1_D, 0, 0, 0, 5913 /* IP4_4_2 [3] */ 5914 FN_SSI_SCK1, FN_I2C0_SDA_B, FN_IIC0_SDA_B, 5915 FN_MSIOF2_SYNC_C, FN_GLO_I0_D, 5916 0, 0, 0, 5917 /* IP4_1_0 [2] */ 5918 FN_SSI_SDATA0, FN_I2C0_SCL_B, FN_IIC0_SCL_B, FN_MSIOF2_SCK_C, 5919 )) 5920 }, 5921 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32, 5922 GROUP(3, 3, 2, 2, 2, 3, 2, 3, 3, 3, 3, 3), 5923 GROUP( 5924 /* IP5_31_29 [3] */ 5925 FN_SSI_SDATA9, FN_RX3_D, FN_CAN0_RX_D, 5926 0, 0, 0, 0, 0, 5927 /* IP5_28_26 [3] */ 5928 FN_SSI_WS9, FN_TX3_D, FN_CAN0_TX_D, FN_GLO_SDATA_D, 5929 0, 0, 0, 0, 5930 /* IP5_25_24 [2] */ 5931 FN_SSI_SCK9, FN_RX1_D, FN_GLO_SCLK_D, 0, 5932 /* IP5_23_22 [2] */ 5933 FN_SSI_SDATA8, FN_TX1_D, FN_STP_ISSYNC_0_B, 0, 5934 /* IP5_21_20 [2] */ 5935 FN_SSI_SDATA7, FN_RX0_D, FN_STP_ISEN_0_B, 0, 5936 /* IP5_19_17 [3] */ 5937 FN_SSI_WS78, FN_TX0_D, FN_STP_ISD_0_B, FN_GLO_RFON, 5938 0, 0, 0, 0, 5939 /* IP5_16_15 [2] */ 5940 FN_SSI_SCK78, FN_STP_ISCLK_0_B, FN_GLO_SS, 0, 5941 /* IP5_14_12 [3] */ 5942 FN_SSI_SDATA6, FN_STP_IVCXO27_0_B, FN_GLO_SDATA, FN_VI1_R7_B, 5943 0, 0, 0, 0, 5944 /* IP5_11_9 [3] */ 5945 FN_SSI_WS6, FN_GLO_SCLK, FN_MSIOF2_SS2_D, FN_VI1_R6_B, 5946 0, 0, 0, 0, 5947 /* IP5_8_6 [3] */ 5948 FN_SSI_SCK6, FN_MSIOF1_RXD_C, FN_TS_SPSYNC0, FN_GLO_Q1, 5949 FN_MSIOF2_RXD_D, FN_VI1_R5_B, 5950 0, 0, 5951 /* IP5_5_3 [3] */ 5952 FN_SSI_SDATA5, FN_MSIOF1_TXD_C, FN_TS_SDEN0, FN_GLO_Q0, 5953 FN_MSIOF2_SS1_D, FN_VI1_R4_B, 5954 0, 0, 5955 /* IP5_2_0 [3] */ 5956 FN_SSI_WS5, FN_MSIOF1_SYNC_C, FN_TS_SCK0, FN_GLO_I1, 5957 FN_MSIOF2_TXD_D, FN_VI1_R3_B, 5958 0, 0, )) 5959 }, 5960 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32, 5961 GROUP(2, 3, 3, 3, 2, 3, 2, 2, 2, 2, 2, 3, 3), 5962 GROUP( 5963 /* IP6_31_30 [2] */ 5964 0, 0, 0, 0, 5965 /* IP6_29_27 [3] */ 5966 FN_IRQ8, FN_HRTS1_N_C, FN_MSIOF1_RXD_B, 5967 FN_GPS_SIGN_C, FN_GPS_SIGN_D, 5968 0, 0, 0, 5969 /* IP6_26_24 [3] */ 5970 FN_IRQ7, FN_HCTS1_N_C, FN_MSIOF1_TXD_B, 5971 FN_GPS_CLK_C, FN_GPS_CLK_D, 5972 0, 0, 0, 5973 /* IP6_23_21 [3] */ 5974 FN_IRQ6, FN_HSCK1_C, FN_MSIOF1_SS2_B, 5975 FN_I2C1_SDA_E, FN_MSIOF2_SYNC_E, 5976 0, 0, 0, 5977 /* IP6_20_19 [2] */ 5978 FN_IRQ5, FN_HTX1_C, FN_I2C1_SCL_E, FN_MSIOF2_SCK_E, 5979 /* IP6_18_16 [3] */ 5980 FN_IRQ4, FN_HRX1_C, FN_I2C4_SDA_C, FN_MSIOF2_RXD_E, 5981 FN_INTC_IRQ4_N, 0, 0, 0, 5982 /* IP6_15_14 [2] */ 5983 FN_IRQ3, FN_I2C4_SCL_C, FN_MSIOF2_TXD_E, FN_INTC_IRQ3_N, 5984 /* IP6_13_12 [2] */ 5985 FN_IRQ2, FN_SCIFB1_TXD_D, FN_INTC_IRQ2_N, 0, 5986 /* IP6_11_10 [2] */ 5987 FN_IRQ1, FN_SCIFB1_SCK_C, FN_INTC_IRQ1_N, 0, 5988 /* IP6_9_8 [2] */ 5989 FN_IRQ0, FN_SCIFB1_RXD_D, FN_INTC_IRQ0_N, 0, 5990 /* IP6_7_6 [2] */ 5991 FN_AUDIO_CLKOUT, FN_MSIOF1_SS1_B, FN_TX2, FN_SCIFA2_TXD, 5992 /* IP6_5_3 [3] */ 5993 FN_AUDIO_CLKC, FN_SCIFB0_SCK_C, FN_MSIOF1_SYNC_B, FN_RX2, 5994 FN_SCIFA2_RXD, FN_FMIN_E, 5995 0, 0, 5996 /* IP6_2_0 [3] */ 5997 FN_AUDIO_CLKB, FN_STP_OPWM_0_B, FN_MSIOF1_SCK_B, 5998 FN_SCIF_CLK, FN_DVC_MUTE, FN_BPFCLK_E, 5999 0, 0, )) 6000 }, 6001 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32, 6002 GROUP(2, 3, 3, 3, 2, 2, 2, 2, 2, 2, 3, 3, 3), 6003 GROUP( 6004 /* IP7_31_30 [2] */ 6005 0, 0, 0, 0, 6006 /* IP7_29_27 [3] */ 6007 FN_DU1_DG2, FN_LCDOUT10, FN_VI1_DATA4_B, FN_SCIF1_SCK_B, 6008 FN_SCIFA1_SCK, FN_SSI_SCK78_B, 6009 0, 0, 6010 /* IP7_26_24 [3] */ 6011 FN_DU1_DG1, FN_LCDOUT9, FN_VI1_DATA3_B, FN_RX1_B, 6012 FN_SCIFA1_RXD_B, FN_MSIOF2_SS2_B, 6013 0, 0, 6014 /* IP7_23_21 [3] */ 6015 FN_DU1_DG0, FN_LCDOUT8, FN_VI1_DATA2_B, FN_TX1_B, 6016 FN_SCIFA1_TXD_B, FN_MSIOF2_SS1_B, 6017 0, 0, 6018 /* IP7_20_19 [2] */ 6019 FN_DU1_DR7, FN_LCDOUT7, FN_SSI_SDATA1_B, 0, 6020 /* IP7_18_17 [2] */ 6021 FN_DU1_DR6, FN_LCDOUT6, FN_SSI_WS1_B, 0, 6022 /* IP7_16_15 [2] */ 6023 FN_DU1_DR5, FN_LCDOUT5, FN_SSI_SCK1_B, 0, 6024 /* IP7_14_13 [2] */ 6025 FN_DU1_DR4, FN_LCDOUT4, FN_SSI_SDATA0_B, 0, 6026 /* IP7_12_11 [2] */ 6027 FN_DU1_DR3, FN_LCDOUT3, FN_SSI_WS0129_B, 0, 6028 /* IP7_10_9 [2] */ 6029 FN_DU1_DR2, FN_LCDOUT2, FN_SSI_SCK0129_B, 0, 6030 /* IP7_8_6 [3] */ 6031 FN_DU1_DR1, FN_LCDOUT1, FN_VI1_DATA1_B, FN_RX0_B, 6032 FN_SCIFA0_RXD_B, FN_MSIOF2_SYNC_B, 6033 0, 0, 6034 /* IP7_5_3 [3] */ 6035 FN_DU1_DR0, FN_LCDOUT0, FN_VI1_DATA0_B, FN_TX0_B, 6036 FN_SCIFA0_TXD_B, FN_MSIOF2_SCK_B, 6037 0, 0, 6038 /* IP7_2_0 [3] */ 6039 FN_IRQ9, FN_DU1_DOTCLKIN_B, FN_CAN_CLK_D, FN_GPS_MAG_C, 6040 FN_SCIF_CLK_B, FN_GPS_MAG_D, 6041 0, 0, )) 6042 }, 6043 { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32, 6044 GROUP(1, 3, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3), 6045 GROUP( 6046 /* IP8_31 [1] */ 6047 0, 0, 6048 /* IP8_30_28 [3] */ 6049 FN_DU1_DB5, FN_LCDOUT21, FN_TX3, FN_SCIFA3_TXD, FN_CAN1_TX, 6050 0, 0, 0, 6051 /* IP8_27_26 [2] */ 6052 FN_DU1_DB4, FN_LCDOUT20, FN_VI1_FIELD_B, FN_CAN1_RX, 6053 /* IP8_25_24 [2] */ 6054 FN_DU1_DB3, FN_LCDOUT19, FN_VI1_CLKENB_B, 0, 6055 /* IP8_23_21 [3] */ 6056 FN_DU1_DB2, FN_LCDOUT18, FN_VI1_VSYNC_N_B, FN_SCIF2_SCK_B, 6057 FN_SCIFA2_SCK, FN_SSI_SDATA9_B, 6058 0, 0, 6059 /* IP8_20_18 [3] */ 6060 FN_DU1_DB1, FN_LCDOUT17, FN_VI1_HSYNC_N_B, FN_RX2_B, 6061 FN_SCIFA2_RXD_B, FN_MSIOF2_RXD_B, 6062 0, 0, 6063 /* IP8_17_15 [3] */ 6064 FN_DU1_DB0, FN_LCDOUT16, FN_VI1_CLK_B, FN_TX2_B, 6065 FN_SCIFA2_TXD_B, FN_MSIOF2_TXD_B, 6066 0, 0, 6067 /* IP8_14_12 [3] */ 6068 FN_DU1_DG7, FN_LCDOUT15, FN_HTX0_B, 6069 FN_SCIFB2_RTS_N_B, FN_SSI_WS9_B, 6070 0, 0, 0, 6071 /* IP8_11_9 [3] */ 6072 FN_DU1_DG6, FN_LCDOUT14, FN_HRTS0_N_B, 6073 FN_SCIFB2_CTS_N_B, FN_SSI_SCK9_B, 6074 0, 0, 0, 6075 /* IP8_8_6 [3] */ 6076 FN_DU1_DG5, FN_LCDOUT13, FN_VI1_DATA7_B, FN_HCTS0_N_B, 6077 FN_SCIFB2_TXD_B, FN_SSI_SDATA8_B, 6078 0, 0, 6079 /* IP8_5_3 [3] */ 6080 FN_DU1_DG4, FN_LCDOUT12, FN_VI1_DATA6_B, FN_HRX0_B, 6081 FN_SCIFB2_RXD_B, FN_SSI_SDATA7_B, 6082 0, 0, 6083 /* IP8_2_0 [3] */ 6084 FN_DU1_DG3, FN_LCDOUT11, FN_VI1_DATA5_B, 0, FN_SSI_WS78_B, 6085 0, 0, 0, )) 6086 }, 6087 { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32, 6088 GROUP(3, 2, 2, 2, 2, 2, 2, 1, 3, 1, 1, 3, 6089 1, 1, 3, 3), 6090 GROUP( 6091 /* IP9_31_29 [3] */ 6092 FN_VI0_G0, FN_IIC1_SCL, FN_STP_IVCXO27_0_C, FN_I2C4_SCL, 6093 FN_HCTS2_N, FN_SCIFB2_CTS_N, FN_ATAWR1_N, 0, 6094 /* IP9_28_27 [2] */ 6095 FN_VI0_DATA3_VI0_B3, FN_SCIF3_SCK_B, FN_SCIFA3_SCK_B, 0, 6096 /* IP9_26_25 [2] */ 6097 FN_VI0_VSYNC_N, FN_RX5, FN_SCIFA5_RXD, FN_TS_SPSYNC0_D, 6098 /* IP9_24_23 [2] */ 6099 FN_VI0_HSYNC_N, FN_TX5, FN_SCIFA5_TXD, FN_TS_SDEN0_D, 6100 /* IP9_22_21 [2] */ 6101 FN_VI0_FIELD, FN_RX4, FN_SCIFA4_RXD, FN_TS_SCK0_D, 6102 /* IP9_20_19 [2] */ 6103 FN_VI0_CLKENB, FN_TX4, FN_SCIFA4_TXD, FN_TS_SDATA0_D, 6104 /* IP9_18_17 [2] */ 6105 FN_DU1_CDE, FN_QPOLB, FN_PWM4_B, 0, 6106 /* IP9_16 [1] */ 6107 FN_DU1_DISP, FN_QPOLA, 6108 /* IP9_15_13 [3] */ 6109 FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_QCPV_QDE, 6110 FN_CAN0_RX, FN_RX3_B, FN_I2C2_SDA_B, 6111 0, 0, 0, 6112 /* IP9_12 [1] */ 6113 FN_DU1_EXVSYNC_DU1_VSYNC, FN_QSTB_QHE, 6114 /* IP9_11 [1] */ 6115 FN_DU1_EXHSYNC_DU1_HSYNC, FN_QSTH_QHS, 6116 /* IP9_10_8 [3] */ 6117 FN_DU1_DOTCLKOUT1, FN_QSTVB_QVE, FN_CAN0_TX, 6118 FN_TX3_B, FN_I2C2_SCL_B, FN_PWM4, 6119 0, 0, 6120 /* IP9_7 [1] */ 6121 FN_DU1_DOTCLKOUT0, FN_QCLK, 6122 /* IP9_6 [1] */ 6123 FN_DU1_DOTCLKIN, FN_QSTVA_QVS, 6124 /* IP9_5_3 [3] */ 6125 FN_DU1_DB7, FN_LCDOUT23, FN_I2C3_SDA_C, 6126 FN_SCIF3_SCK, FN_SCIFA3_SCK, 6127 0, 0, 0, 6128 /* IP9_2_0 [3] */ 6129 FN_DU1_DB6, FN_LCDOUT22, FN_I2C3_SCL_C, FN_RX3, FN_SCIFA3_RXD, 6130 0, 0, 0, )) 6131 }, 6132 { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32, 6133 GROUP(3, 2, 2, 3, 3, 2, 2, 3, 3, 3, 3, 3), 6134 GROUP( 6135 /* IP10_31_29 [3] */ 6136 FN_VI0_R4, FN_VI2_DATA5, FN_GLO_SCLK_B, FN_TX0_C, FN_I2C1_SCL_D, 6137 0, 0, 0, 6138 /* IP10_28_27 [2] */ 6139 FN_VI0_R3, FN_VI2_DATA4, FN_GLO_Q1_B, FN_TS_SPSYNC0_C, 6140 /* IP10_26_25 [2] */ 6141 FN_VI0_R2, FN_VI2_DATA3, FN_GLO_Q0_B, FN_TS_SDEN0_C, 6142 /* IP10_24_22 [3] */ 6143 FN_VI0_R1, FN_VI2_DATA2, FN_GLO_I1_B, FN_TS_SCK0_C, FN_ATAG1_N, 6144 0, 0, 0, 6145 /* IP10_21_19 [3] */ 6146 FN_VI0_R0, FN_VI2_DATA1, FN_GLO_I0_B, 6147 FN_TS_SDATA0_C, FN_ATACS11_N, 6148 0, 0, 0, 6149 /* IP10_18_17 [2] */ 6150 FN_VI0_G7, FN_VI2_DATA0, FN_FMIN_D, 0, 6151 /* IP10_16_15 [2] */ 6152 FN_VI0_G6, FN_VI2_CLK, FN_BPFCLK_D, 0, 6153 /* IP10_14_12 [3] */ 6154 FN_VI0_G5, FN_VI2_FIELD, FN_STP_OPWM_0_C, FN_FMCLK_D, 6155 FN_CAN0_TX_E, FN_HTX1_D, FN_SCIFB0_TXD_D, 0, 6156 /* IP10_11_9 [3] */ 6157 FN_VI0_G4, FN_VI2_CLKENB, FN_STP_ISSYNC_0_C, 6158 FN_HTX2, FN_SCIFB2_TXD, FN_SCIFB0_SCK_D, 6159 0, 0, 6160 /* IP10_8_6 [3] */ 6161 FN_VI0_G3, FN_VI2_VSYNC_N, FN_STP_ISEN_0_C, FN_I2C3_SDA_B, 6162 FN_HRX2, FN_SCIFB2_RXD, FN_ATACS01_N, 0, 6163 /* IP10_5_3 [3] */ 6164 FN_VI0_G2, FN_VI2_HSYNC_N, FN_STP_ISD_0_C, FN_I2C3_SCL_B, 6165 FN_HSCK2, FN_SCIFB2_SCK, FN_ATARD1_N, 0, 6166 /* IP10_2_0 [3] */ 6167 FN_VI0_G1, FN_IIC1_SDA, FN_STP_ISCLK_0_C, FN_I2C4_SDA, 6168 FN_HRTS2_N, FN_SCIFB2_RTS_N, FN_ATADIR1_N, 0, )) 6169 }, 6170 { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32, 6171 GROUP(2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 6172 2, 3, 3, 3, 3, 3), 6173 GROUP( 6174 /* IP11_31_30 [2] */ 6175 FN_ETH_CRS_DV, FN_AVB_LINK, FN_I2C2_SDA_C, 0, 6176 /* IP11_29_28 [2] */ 6177 FN_ETH_MDIO, FN_AVB_RX_CLK, FN_I2C2_SCL_C, 0, 6178 /* IP11_27 [1] */ 6179 FN_VI1_DATA7, FN_AVB_MDC, 6180 /* IP11_26 [1] */ 6181 FN_VI1_DATA6, FN_AVB_MAGIC, 6182 /* IP11_25 [1] */ 6183 FN_VI1_DATA5, FN_AVB_RX_DV, 6184 /* IP11_24 [1] */ 6185 FN_VI1_DATA4, FN_AVB_MDIO, 6186 /* IP11_23 [1] */ 6187 FN_VI1_DATA3, FN_AVB_RX_ER, 6188 /* IP11_22 [1] */ 6189 FN_VI1_DATA2, FN_AVB_RXD7, 6190 /* IP11_21 [1] */ 6191 FN_VI1_DATA1, FN_AVB_RXD6, 6192 /* IP11_20 [1] */ 6193 FN_VI1_DATA0, FN_AVB_RXD5, 6194 /* IP11_19 [1] */ 6195 FN_VI1_CLK, FN_AVB_RXD4, 6196 /* IP11_18_17 [2] */ 6197 FN_VI1_FIELD, FN_AVB_RXD3, FN_TS_SPSYNC0_B, 0, 6198 /* IP11_16_15 [2] */ 6199 FN_VI1_CLKENB, FN_AVB_RXD2, FN_TS_SDEN0_B, 0, 6200 /* IP11_14_12 [3] */ 6201 FN_VI1_VSYNC_N, FN_AVB_RXD1, FN_TS_SCK0_B, 6202 FN_RX4_B, FN_SCIFA4_RXD_B, 6203 0, 0, 0, 6204 /* IP11_11_9 [3] */ 6205 FN_VI1_HSYNC_N, FN_AVB_RXD0, FN_TS_SDATA0_B, 6206 FN_TX4_B, FN_SCIFA4_TXD_B, 6207 0, 0, 0, 6208 /* IP11_8_6 [3] */ 6209 FN_VI0_R7, FN_GLO_RFON_B, FN_RX1_C, FN_CAN0_RX_E, 6210 FN_I2C4_SDA_B, FN_HRX1_D, FN_SCIFB0_RXD_D, 0, 6211 /* IP11_5_3 [3] */ 6212 FN_VI0_R6, FN_VI2_DATA7, FN_GLO_SS_B, FN_TX1_C, FN_I2C4_SCL_B, 6213 0, 0, 0, 6214 /* IP11_2_0 [3] */ 6215 FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C, 6216 FN_I2C1_SDA_D, 0, 0, 0, )) 6217 }, 6218 { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32, 6219 GROUP(2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2), 6220 GROUP( 6221 /* IP12_31_30 [2] */ 6222 0, 0, 0, 0, 6223 /* IP12_29_27 [3] */ 6224 FN_STP_ISCLK_0, FN_AVB_TX_EN, FN_SCIFB2_RXD_D, 6225 FN_ADICS_SAMP_B, FN_MSIOF0_SCK_C, 6226 0, 0, 0, 6227 /* IP12_26_24 [3] */ 6228 FN_STP_IVCXO27_0, FN_AVB_TXD7, FN_SCIFB2_TXD_D, 6229 FN_ADIDATA_B, FN_MSIOF0_SYNC_C, 6230 0, 0, 0, 6231 /* IP12_23_22 [2] */ 6232 FN_ETH_MDC, FN_AVB_TXD6, FN_IERX_C, 0, 6233 /* IP12_21_20 [2] */ 6234 FN_ETH_TXD0, FN_AVB_TXD5, FN_IECLK_C, 0, 6235 /* IP12_19_18 [2] */ 6236 FN_ETH_MAGIC, FN_AVB_TXD4, FN_IETX_C, 0, 6237 /* IP12_17_16 [2] */ 6238 FN_ETH_TX_EN, FN_AVB_TXD3, FN_TCLK1_B, FN_CAN_CLK_B, 6239 /* IP12_15_13 [3] */ 6240 FN_ETH_TXD1, FN_AVB_TXD2, FN_SCIFA3_TXD_B, 6241 FN_CAN1_TX_C, FN_MSIOF1_TXD_E, 6242 0, 0, 0, 6243 /* IP12_12_10 [3] */ 6244 FN_ETH_REFCLK, FN_AVB_TXD1, FN_SCIFA3_RXD_B, 6245 FN_CAN1_RX_C, FN_MSIOF1_SYNC_E, 6246 0, 0, 0, 6247 /* IP12_9_7 [3] */ 6248 FN_ETH_LINK, FN_AVB_TXD0, FN_CAN0_RX_C, 6249 FN_I2C2_SDA_D, FN_MSIOF1_SCK_E, 6250 0, 0, 0, 6251 /* IP12_6_4 [3] */ 6252 FN_ETH_RXD1, FN_AVB_GTXREFCLK, FN_CAN0_TX_C, 6253 FN_I2C2_SCL_D, FN_MSIOF1_RXD_E, 6254 0, 0, 0, 6255 /* IP12_3_2 [2] */ 6256 FN_ETH_RXD0, FN_AVB_PHY_INT, FN_I2C3_SDA, FN_IIC0_SDA, 6257 /* IP12_1_0 [2] */ 6258 FN_ETH_RX_ER, FN_AVB_CRS, FN_I2C3_SCL, FN_IIC0_SCL, )) 6259 }, 6260 { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32, 6261 GROUP(1, 3, 1, 1, 1, 2, 1, 3, 3, 1, 1, 1, 6262 1, 1, 1, 3, 2, 2, 3), 6263 GROUP( 6264 /* IP13_31 [1] */ 6265 0, 0, 6266 /* IP13_30_28 [3] */ 6267 FN_SD1_CD, FN_PWM0, FN_TPU_TO0, FN_I2C1_SCL_C, 6268 0, 0, 0, 0, 6269 /* IP13_27 [1] */ 6270 FN_SD1_DATA3, FN_IERX_B, 6271 /* IP13_26 [1] */ 6272 FN_SD1_DATA2, FN_IECLK_B, 6273 /* IP13_25 [1] */ 6274 FN_SD1_DATA1, FN_IETX_B, 6275 /* IP13_24_23 [2] */ 6276 FN_SD1_DATA0, FN_SPEEDIN_B, 0, 0, 6277 /* IP13_22 [1] */ 6278 FN_SD1_CMD, FN_REMOCON_B, 6279 /* IP13_21_19 [3] */ 6280 FN_SD0_WP, FN_MMC_D7_B, FN_SIM0_D_B, FN_CAN0_TX_F, 6281 FN_SCIFA5_RXD_B, FN_RX3_C, 6282 0, 0, 6283 /* IP13_18_16 [3] */ 6284 FN_SD0_CD, FN_MMC_D6_B, FN_SIM0_RST_B, FN_CAN0_RX_F, 6285 FN_SCIFA5_TXD_B, FN_TX3_C, 6286 0, 0, 6287 /* IP13_15 [1] */ 6288 FN_SD0_DATA3, FN_SSL_B, 6289 /* IP13_14 [1] */ 6290 FN_SD0_DATA2, FN_IO3_B, 6291 /* IP13_13 [1] */ 6292 FN_SD0_DATA1, FN_IO2_B, 6293 /* IP13_12 [1] */ 6294 FN_SD0_DATA0, FN_MISO_IO1_B, 6295 /* IP13_11 [1] */ 6296 FN_SD0_CMD, FN_MOSI_IO0_B, 6297 /* IP13_10 [1] */ 6298 FN_SD0_CLK, FN_SPCLK_B, 6299 /* IP13_9_7 [3] */ 6300 FN_STP_OPWM_0, FN_AVB_GTX_CLK, FN_PWM0_B, 6301 FN_ADICHS2_B, FN_MSIOF0_TXD_C, 6302 0, 0, 0, 6303 /* IP13_6_5 [2] */ 6304 FN_STP_ISSYNC_0, FN_AVB_COL, FN_ADICHS1_B, FN_MSIOF0_RXD_C, 6305 /* IP13_4_3 [2] */ 6306 FN_STP_ISEN_0, FN_AVB_TX_CLK, FN_ADICHS0_B, FN_MSIOF0_SS2_C, 6307 /* IP13_2_0 [3] */ 6308 FN_STP_ISD_0, FN_AVB_TX_ER, FN_SCIFB2_SCK_C, 6309 FN_ADICLK_B, FN_MSIOF0_SS1_C, 6310 0, 0, 0, )) 6311 }, 6312 { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32, 6313 GROUP(3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 6314 1, 1, 2), 6315 GROUP( 6316 /* IP14_31_29 [3] */ 6317 FN_MSIOF0_SS2, FN_MMC_D7, FN_ADICHS2, FN_RX0_E, 6318 FN_VI1_VSYNC_N_C, FN_IIC0_SDA_C, FN_VI1_G5_B, 0, 6319 /* IP14_28_26 [3] */ 6320 FN_MSIOF0_SS1, FN_MMC_D6, FN_ADICHS1, FN_TX0_E, 6321 FN_VI1_HSYNC_N_C, FN_IIC0_SCL_C, FN_VI1_G4_B, 0, 6322 /* IP14_25_23 [3] */ 6323 FN_MSIOF0_RXD, FN_ADICHS0, 0, FN_VI1_DATA0_C, FN_VI1_G3_B, 6324 0, 0, 0, 6325 /* IP14_22_20 [3] */ 6326 FN_MSIOF0_TXD, FN_ADICLK, 0, FN_VI1_FIELD_C, FN_VI1_G2_B, 6327 0, 0, 0, 6328 /* IP14_19_17 [3] */ 6329 FN_MSIOF0_SYNC, FN_TX2_C, FN_ADICS_SAMP, 0, 6330 FN_VI1_CLKENB_C, FN_VI1_G1_B, 6331 0, 0, 6332 /* IP14_16_14 [3] */ 6333 FN_MSIOF0_SCK, FN_RX2_C, FN_ADIDATA, 0, 6334 FN_VI1_CLK_C, FN_VI1_G0_B, 6335 0, 0, 6336 /* IP14_13_11 [3] */ 6337 FN_SD2_WP, FN_MMC_D5, FN_IIC1_SDA_C, FN_RX5_B, FN_SCIFA5_RXD_C, 6338 0, 0, 0, 6339 /* IP14_10_8 [3] */ 6340 FN_SD2_CD, FN_MMC_D4, FN_IIC1_SCL_C, FN_TX5_B, FN_SCIFA5_TXD_C, 6341 0, 0, 0, 6342 /* IP14_7 [1] */ 6343 FN_SD2_DATA3, FN_MMC_D3, 6344 /* IP14_6 [1] */ 6345 FN_SD2_DATA2, FN_MMC_D2, 6346 /* IP14_5 [1] */ 6347 FN_SD2_DATA1, FN_MMC_D1, 6348 /* IP14_4 [1] */ 6349 FN_SD2_DATA0, FN_MMC_D0, 6350 /* IP14_3 [1] */ 6351 FN_SD2_CMD, FN_MMC_CMD, 6352 /* IP14_2 [1] */ 6353 FN_SD2_CLK, FN_MMC_CLK, 6354 /* IP14_1_0 [2] */ 6355 FN_SD1_WP, FN_PWM1_B, FN_I2C1_SDA_C, 0, )) 6356 }, 6357 { PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32, 6358 GROUP(2, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2), 6359 GROUP( 6360 /* IP15_31_30 [2] */ 6361 0, 0, 0, 0, 6362 /* IP15_29_27 [3] */ 6363 FN_HTX0, FN_SCIFB0_TXD, 0, FN_GLO_SCLK_C, 6364 FN_CAN0_TX_B, FN_VI1_DATA5_C, 6365 0, 0, 6366 /* IP15_26_24 [3] */ 6367 FN_HRX0, FN_SCIFB0_RXD, 0, FN_GLO_Q1_C, 6368 FN_CAN0_RX_B, FN_VI1_DATA4_C, 6369 0, 0, 6370 /* IP15_23_21 [3] */ 6371 FN_HSCK0, FN_SCIFB0_SCK, 0, FN_GLO_Q0_C, FN_CAN_CLK, 6372 FN_TCLK2, FN_VI1_DATA3_C, 0, 6373 /* IP15_20_18 [3] */ 6374 FN_HRTS0_N, FN_SCIFB0_RTS_N, 0, FN_GLO_I1_C, FN_VI1_DATA2_C, 6375 0, 0, 0, 6376 /* IP15_17_15 [3] */ 6377 FN_HCTS0_N, FN_SCIFB0_CTS_N, 0, FN_GLO_I0_C, 6378 FN_TCLK1, FN_VI1_DATA1_C, 6379 0, 0, 6380 /* IP15_14_12 [3] */ 6381 FN_GPS_MAG, FN_RX4_C, FN_SCIFA4_RXD_C, FN_PWM6, 6382 FN_VI1_G7_B, FN_SCIFA3_SCK_C, 6383 0, 0, 6384 /* IP15_11_9 [3] */ 6385 FN_GPS_SIGN, FN_TX4_C, FN_SCIFA4_TXD_C, FN_PWM5, 6386 FN_VI1_G6_B, FN_SCIFA3_RXD_C, 6387 0, 0, 6388 /* IP15_8_6 [3] */ 6389 FN_GPS_CLK, FN_DU1_DOTCLKIN_C, FN_AUDIO_CLKB_B, 6390 FN_PWM5_B, FN_SCIFA3_TXD_C, 6391 0, 0, 0, 6392 /* IP15_5_4 [2] */ 6393 FN_SIM0_D, FN_IERX, FN_CAN1_RX_D, 0, 6394 /* IP15_3_2 [2] */ 6395 FN_SIM0_CLK, FN_IECLK, FN_CAN_CLK_C, 0, 6396 /* IP15_1_0 [2] */ 6397 FN_SIM0_RST, FN_IETX, FN_CAN1_TX_D, 0, )) 6398 }, 6399 { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32, 6400 GROUP(4, 4, 4, 4, 4, 2, 2, 2, 3, 3), 6401 GROUP( 6402 /* IP16_31_28 [4] */ 6403 0, 0, 0, 0, 0, 0, 0, 0, 6404 0, 0, 0, 0, 0, 0, 0, 0, 6405 /* IP16_27_24 [4] */ 6406 0, 0, 0, 0, 0, 0, 0, 0, 6407 0, 0, 0, 0, 0, 0, 0, 0, 6408 /* IP16_23_20 [4] */ 6409 0, 0, 0, 0, 0, 0, 0, 0, 6410 0, 0, 0, 0, 0, 0, 0, 0, 6411 /* IP16_19_16 [4] */ 6412 0, 0, 0, 0, 0, 0, 0, 0, 6413 0, 0, 0, 0, 0, 0, 0, 0, 6414 /* IP16_15_12 [4] */ 6415 0, 0, 0, 0, 0, 0, 0, 0, 6416 0, 0, 0, 0, 0, 0, 0, 0, 6417 /* IP16_11_10 [2] */ 6418 FN_HRTS1_N, FN_SCIFB1_RTS_N, FN_MLB_DAT, FN_CAN1_RX_B, 6419 /* IP16_9_8 [2] */ 6420 FN_HCTS1_N, FN_SCIFB1_CTS_N, FN_MLB_SIG, FN_CAN1_TX_B, 6421 /* IP16_7_6 [2] */ 6422 FN_HSCK1, FN_SCIFB1_SCK, FN_MLB_CLK, FN_GLO_RFON_C, 6423 /* IP16_5_3 [3] */ 6424 FN_HTX1, FN_SCIFB1_TXD, FN_VI1_R1_B, 6425 FN_GLO_SS_C, FN_VI1_DATA7_C, 6426 0, 0, 0, 6427 /* IP16_2_0 [3] */ 6428 FN_HRX1, FN_SCIFB1_RXD, FN_VI1_R0_B, 6429 FN_GLO_SDATA_C, FN_VI1_DATA6_C, 6430 0, 0, 0, )) 6431 }, 6432 { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32, 6433 GROUP(1, 2, 2, 2, 3, 2, 1, 1, 1, 1, 3, 2, 6434 2, 2, 1, 2, 2, 2), 6435 GROUP( 6436 /* RESERVED [1] */ 6437 0, 0, 6438 /* SEL_SCIF1 [2] */ 6439 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3, 6440 /* SEL_SCIFB [2] */ 6441 FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, FN_SEL_SCIFB_3, 6442 /* SEL_SCIFB2 [2] */ 6443 FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, 6444 FN_SEL_SCIFB2_2, FN_SEL_SCIFB2_3, 6445 /* SEL_SCIFB1 [3] */ 6446 FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, 6447 FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3, 6448 0, 0, 0, 0, 6449 /* SEL_SCIFA1 [2] */ 6450 FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, 0, 6451 /* SEL_SSI9 [1] */ 6452 FN_SEL_SSI9_0, FN_SEL_SSI9_1, 6453 /* SEL_SCFA [1] */ 6454 FN_SEL_SCFA_0, FN_SEL_SCFA_1, 6455 /* SEL_QSP [1] */ 6456 FN_SEL_QSP_0, FN_SEL_QSP_1, 6457 /* SEL_SSI7 [1] */ 6458 FN_SEL_SSI7_0, FN_SEL_SSI7_1, 6459 /* SEL_HSCIF1 [3] */ 6460 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2, 6461 FN_SEL_HSCIF1_3, FN_SEL_HSCIF1_4, 6462 0, 0, 0, 6463 /* RESERVED [2] */ 6464 0, 0, 0, 0, 6465 /* SEL_VI1 [2] */ 6466 FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2, 0, 6467 /* RESERVED [2] */ 6468 0, 0, 0, 0, 6469 /* SEL_TMU [1] */ 6470 FN_SEL_TMU1_0, FN_SEL_TMU1_1, 6471 /* SEL_LBS [2] */ 6472 FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_LBS_2, FN_SEL_LBS_3, 6473 /* SEL_TSIF0 [2] */ 6474 FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, 6475 /* SEL_SOF0 [2] */ 6476 FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2, 0, )) 6477 }, 6478 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32, 6479 GROUP(3, 1, 1, 3, 2, 1, 1, 2, 2, 1, 3, 2, 6480 1, 2, 2, 2, 1, 1, 1), 6481 GROUP( 6482 /* SEL_SCIF0 [3] */ 6483 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, 6484 FN_SEL_SCIF0_3, FN_SEL_SCIF0_4, 6485 0, 0, 0, 6486 /* RESERVED [1] */ 6487 0, 0, 6488 /* SEL_SCIF [1] */ 6489 FN_SEL_SCIF_0, FN_SEL_SCIF_1, 6490 /* SEL_CAN0 [3] */ 6491 FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3, 6492 FN_SEL_CAN0_4, FN_SEL_CAN0_5, 6493 0, 0, 6494 /* SEL_CAN1 [2] */ 6495 FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3, 6496 /* RESERVED [1] */ 6497 0, 0, 6498 /* SEL_SCIFA2 [1] */ 6499 FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, 6500 /* SEL_SCIF4 [2] */ 6501 FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, 0, 6502 /* RESERVED [2] */ 6503 0, 0, 0, 0, 6504 /* SEL_ADG [1] */ 6505 FN_SEL_ADG_0, FN_SEL_ADG_1, 6506 /* SEL_FM [3] */ 6507 FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, 6508 FN_SEL_FM_3, FN_SEL_FM_4, 6509 0, 0, 0, 6510 /* SEL_SCIFA5 [2] */ 6511 FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, 0, 6512 /* RESERVED [1] */ 6513 0, 0, 6514 /* SEL_GPS [2] */ 6515 FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3, 6516 /* SEL_SCIFA4 [2] */ 6517 FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2, 0, 6518 /* SEL_SCIFA3 [2] */ 6519 FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2, 0, 6520 /* SEL_SIM [1] */ 6521 FN_SEL_SIM_0, FN_SEL_SIM_1, 6522 /* RESERVED [1] */ 6523 0, 0, 6524 /* SEL_SSI8 [1] */ 6525 FN_SEL_SSI8_0, FN_SEL_SSI8_1, )) 6526 }, 6527 { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32, 6528 GROUP(2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 2, 2, 6529 3, 2, 2, 2, 1), 6530 GROUP( 6531 /* SEL_HSCIF2 [2] */ 6532 FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1, 6533 FN_SEL_HSCIF2_2, FN_SEL_HSCIF2_3, 6534 /* SEL_CANCLK [2] */ 6535 FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, 6536 FN_SEL_CANCLK_2, FN_SEL_CANCLK_3, 6537 /* SEL_IIC1 [2] */ 6538 FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, 0, 6539 /* SEL_IIC0 [2] */ 6540 FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, 0, 6541 /* SEL_I2C4 [2] */ 6542 FN_SEL_I2C4_0, FN_SEL_I2C4_1, FN_SEL_I2C4_2, 0, 6543 /* SEL_I2C3 [2] */ 6544 FN_SEL_I2C3_0, FN_SEL_I2C3_1, FN_SEL_I2C3_2, FN_SEL_I2C3_3, 6545 /* SEL_SCIF3 [2] */ 6546 FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3, 6547 /* SEL_IEB [2] */ 6548 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0, 6549 /* SEL_MMC [1] */ 6550 FN_SEL_MMC_0, FN_SEL_MMC_1, 6551 /* SEL_SCIF5 [1] */ 6552 FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, 6553 /* RESERVED [2] */ 6554 0, 0, 0, 0, 6555 /* SEL_I2C2 [2] */ 6556 FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3, 6557 /* SEL_I2C1 [3] */ 6558 FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, FN_SEL_I2C1_3, 6559 FN_SEL_I2C1_4, 6560 0, 0, 0, 6561 /* SEL_I2C0 [2] */ 6562 FN_SEL_I2C0_0, FN_SEL_I2C0_1, FN_SEL_I2C0_2, 0, 6563 /* RESERVED [2] */ 6564 0, 0, 0, 0, 6565 /* RESERVED [2] */ 6566 0, 0, 0, 0, 6567 /* RESERVED [1] */ 6568 0, 0, )) 6569 }, 6570 { PINMUX_CFG_REG_VAR("MOD_SEL4", 0xE606009C, 32, 6571 GROUP(3, 2, 2, 1, 1, 1, 1, 3, 2, 2, 3, 1, 6572 1, 1, 2, 2, 2, 2), 6573 GROUP( 6574 /* SEL_SOF1 [3] */ 6575 FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3, 6576 FN_SEL_SOF1_4, 6577 0, 0, 0, 6578 /* SEL_HSCIF0 [2] */ 6579 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, 0, 6580 /* SEL_DIS [2] */ 6581 FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2, 0, 6582 /* RESERVED [1] */ 6583 0, 0, 6584 /* SEL_RAD [1] */ 6585 FN_SEL_RAD_0, FN_SEL_RAD_1, 6586 /* SEL_RCN [1] */ 6587 FN_SEL_RCN_0, FN_SEL_RCN_1, 6588 /* SEL_RSP [1] */ 6589 FN_SEL_RSP_0, FN_SEL_RSP_1, 6590 /* SEL_SCIF2 [3] */ 6591 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, 6592 FN_SEL_SCIF2_3, FN_SEL_SCIF2_4, 6593 0, 0, 0, 6594 /* RESERVED [2] */ 6595 0, 0, 0, 0, 6596 /* RESERVED [2] */ 6597 0, 0, 0, 0, 6598 /* SEL_SOF2 [3] */ 6599 FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2, 6600 FN_SEL_SOF2_3, FN_SEL_SOF2_4, 6601 0, 0, 0, 6602 /* RESERVED [1] */ 6603 0, 0, 6604 /* SEL_SSI1 [1] */ 6605 FN_SEL_SSI1_0, FN_SEL_SSI1_1, 6606 /* SEL_SSI0 [1] */ 6607 FN_SEL_SSI0_0, FN_SEL_SSI0_1, 6608 /* SEL_SSP [2] */ 6609 FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2, 0, 6610 /* RESERVED [2] */ 6611 0, 0, 0, 0, 6612 /* RESERVED [2] */ 6613 0, 0, 0, 0, 6614 /* RESERVED [2] */ 6615 0, 0, 0, 0, )) 6616 }, 6617 { }, 6618 }; 6619 6620 static int r8a7791_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl) 6621 { 6622 if (pin < RCAR_GP_PIN(6, 0) || pin > RCAR_GP_PIN(6, 23)) 6623 return -EINVAL; 6624 6625 *pocctrl = 0xe606008c; 6626 6627 return 31 - (pin & 0x1f); 6628 } 6629 6630 static const struct sh_pfc_soc_operations r8a7791_pinmux_ops = { 6631 .pin_to_pocctrl = r8a7791_pin_to_pocctrl, 6632 }; 6633 6634 #ifdef CONFIG_PINCTRL_PFC_R8A7743 6635 const struct sh_pfc_soc_info r8a7743_pinmux_info = { 6636 .name = "r8a77430_pfc", 6637 .ops = &r8a7791_pinmux_ops, 6638 .unlock_reg = 0xe6060000, /* PMMR */ 6639 6640 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 6641 6642 .pins = pinmux_pins, 6643 .nr_pins = ARRAY_SIZE(pinmux_pins), 6644 .groups = pinmux_groups.common, 6645 .nr_groups = ARRAY_SIZE(pinmux_groups.common), 6646 .functions = pinmux_functions.common, 6647 .nr_functions = ARRAY_SIZE(pinmux_functions.common), 6648 6649 .cfg_regs = pinmux_config_regs, 6650 6651 .pinmux_data = pinmux_data, 6652 .pinmux_data_size = ARRAY_SIZE(pinmux_data), 6653 }; 6654 #endif 6655 6656 #ifdef CONFIG_PINCTRL_PFC_R8A7744 6657 const struct sh_pfc_soc_info r8a7744_pinmux_info = { 6658 .name = "r8a77440_pfc", 6659 .ops = &r8a7791_pinmux_ops, 6660 .unlock_reg = 0xe6060000, /* PMMR */ 6661 6662 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 6663 6664 .pins = pinmux_pins, 6665 .nr_pins = ARRAY_SIZE(pinmux_pins), 6666 .groups = pinmux_groups.common, 6667 .nr_groups = ARRAY_SIZE(pinmux_groups.common), 6668 .functions = pinmux_functions.common, 6669 .nr_functions = ARRAY_SIZE(pinmux_functions.common), 6670 6671 .cfg_regs = pinmux_config_regs, 6672 6673 .pinmux_data = pinmux_data, 6674 .pinmux_data_size = ARRAY_SIZE(pinmux_data), 6675 }; 6676 #endif 6677 6678 #ifdef CONFIG_PINCTRL_PFC_R8A7791 6679 const struct sh_pfc_soc_info r8a7791_pinmux_info = { 6680 .name = "r8a77910_pfc", 6681 .ops = &r8a7791_pinmux_ops, 6682 .unlock_reg = 0xe6060000, /* PMMR */ 6683 6684 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 6685 6686 .pins = pinmux_pins, 6687 .nr_pins = ARRAY_SIZE(pinmux_pins), 6688 .groups = pinmux_groups.common, 6689 .nr_groups = ARRAY_SIZE(pinmux_groups.common) + 6690 ARRAY_SIZE(pinmux_groups.automotive), 6691 .functions = pinmux_functions.common, 6692 .nr_functions = ARRAY_SIZE(pinmux_functions.common) + 6693 ARRAY_SIZE(pinmux_functions.automotive), 6694 6695 .cfg_regs = pinmux_config_regs, 6696 6697 .pinmux_data = pinmux_data, 6698 .pinmux_data_size = ARRAY_SIZE(pinmux_data), 6699 }; 6700 #endif 6701 6702 #ifdef CONFIG_PINCTRL_PFC_R8A7793 6703 const struct sh_pfc_soc_info r8a7793_pinmux_info = { 6704 .name = "r8a77930_pfc", 6705 .ops = &r8a7791_pinmux_ops, 6706 .unlock_reg = 0xe6060000, /* PMMR */ 6707 6708 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 6709 6710 .pins = pinmux_pins, 6711 .nr_pins = ARRAY_SIZE(pinmux_pins), 6712 .groups = pinmux_groups.common, 6713 .nr_groups = ARRAY_SIZE(pinmux_groups.common) + 6714 ARRAY_SIZE(pinmux_groups.automotive), 6715 .functions = pinmux_functions.common, 6716 .nr_functions = ARRAY_SIZE(pinmux_functions.common) + 6717 ARRAY_SIZE(pinmux_functions.automotive), 6718 6719 .cfg_regs = pinmux_config_regs, 6720 6721 .pinmux_data = pinmux_data, 6722 .pinmux_data_size = ARRAY_SIZE(pinmux_data), 6723 }; 6724 #endif 6725