1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * R8A7790 processor support 4 * 5 * Copyright (C) 2013 Renesas Electronics Corporation 6 * Copyright (C) 2013 Magnus Damm 7 * Copyright (C) 2012 Renesas Solutions Corp. 8 * Copyright (C) 2012 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> 9 */ 10 11 #include <linux/errno.h> 12 #include <linux/io.h> 13 #include <linux/kernel.h> 14 #include <linux/sys_soc.h> 15 16 #include "core.h" 17 #include "sh_pfc.h" 18 19 /* 20 * All pins assigned to GPIO bank 3 can be used for SD interfaces in 21 * which case they support both 3.3V and 1.8V signalling. 22 */ 23 #define CPU_ALL_GP(fn, sfx) \ 24 PORT_GP_32(0, fn, sfx), \ 25 PORT_GP_30(1, fn, sfx), \ 26 PORT_GP_30(2, fn, sfx), \ 27 PORT_GP_CFG_32(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ 28 PORT_GP_32(4, fn, sfx), \ 29 PORT_GP_32(5, fn, sfx) 30 31 #define CPU_ALL_NOGP(fn) \ 32 PIN_NOGP(IIC0_SDA, "AF15", fn), \ 33 PIN_NOGP(IIC0_SCL, "AG15", fn), \ 34 PIN_NOGP(IIC3_SDA, "AH15", fn), \ 35 PIN_NOGP(IIC3_SCL, "AJ15", fn) 36 37 enum { 38 PINMUX_RESERVED = 0, 39 40 PINMUX_DATA_BEGIN, 41 GP_ALL(DATA), 42 PINMUX_DATA_END, 43 44 PINMUX_FUNCTION_BEGIN, 45 GP_ALL(FN), 46 47 /* GPSR0 */ 48 FN_IP0_2_0, FN_IP0_5_3, FN_IP0_8_6, FN_IP0_11_9, FN_IP0_15_12, 49 FN_IP0_19_16, FN_IP0_22_20, FN_IP0_26_23, FN_IP0_30_27, 50 FN_IP1_3_0, FN_IP1_7_4, FN_IP1_11_8, FN_IP1_14_12, 51 FN_IP1_17_15, FN_IP1_21_18, FN_IP1_25_22, FN_IP1_27_26, 52 FN_IP1_29_28, FN_IP2_2_0, FN_IP2_5_3, FN_IP2_8_6, FN_IP2_11_9, 53 FN_IP2_14_12, FN_IP2_17_15, FN_IP2_21_18, FN_IP2_25_22, 54 FN_IP2_28_26, FN_IP3_3_0, FN_IP3_7_4, FN_IP3_11_8, 55 FN_IP3_14_12, FN_IP3_17_15, 56 57 /* GPSR1 */ 58 FN_IP3_19_18, FN_IP3_22_20, FN_IP3_25_23, FN_IP3_28_26, 59 FN_IP3_31_29, FN_IP4_2_0, FN_IP4_5_3, FN_IP4_8_6, FN_IP4_11_9, 60 FN_IP4_14_12, FN_IP4_17_15, FN_IP4_20_18, FN_IP4_23_21, 61 FN_IP4_26_24, FN_IP4_29_27, FN_IP5_2_0, FN_IP5_5_3, FN_IP5_9_6, 62 FN_IP5_12_10, FN_IP5_14_13, FN_IP5_17_15, FN_IP5_20_18, 63 FN_IP5_23_21, FN_IP5_26_24, FN_IP5_29_27, FN_IP6_2_0, 64 FN_IP6_5_3, FN_IP6_8_6, FN_IP6_10_9, FN_IP6_13_11, 65 66 /* GPSR2 */ 67 FN_IP7_28_27, FN_IP7_30_29, FN_IP8_1_0, FN_IP8_3_2, FN_IP8_5_4, 68 FN_IP8_7_6, FN_IP8_9_8, FN_IP8_11_10, FN_IP8_13_12, FN_IP8_15_14, 69 FN_IP8_17_16, FN_IP8_19_18, FN_IP8_21_20, FN_IP8_23_22, 70 FN_IP8_25_24, FN_IP8_26, FN_IP8_27, FN_VI1_DATA7_VI1_B7, 71 FN_IP6_16_14, FN_IP6_19_17, FN_IP6_22_20, FN_IP6_25_23, 72 FN_IP6_28_26, FN_IP6_31_29, FN_IP7_2_0, FN_IP7_5_3, FN_IP7_7_6, 73 FN_IP7_9_8, FN_IP7_12_10, FN_IP7_15_13, 74 75 /* GPSR3 */ 76 FN_IP8_28, FN_IP8_30_29, FN_IP9_1_0, FN_IP9_3_2, FN_IP9_5_4, 77 FN_IP9_7_6, FN_IP9_11_8, FN_IP9_15_12, FN_IP9_17_16, FN_IP9_19_18, 78 FN_IP9_21_20, FN_IP9_23_22, FN_IP9_25_24, FN_IP9_27_26, 79 FN_IP9_31_28, FN_IP10_3_0, FN_IP10_6_4, FN_IP10_10_7, FN_IP10_14_11, 80 FN_IP10_18_15, FN_IP10_22_19, FN_IP10_25_23, FN_IP10_29_26, 81 FN_IP11_3_0, FN_IP11_4, FN_IP11_6_5, FN_IP11_8_7, FN_IP11_10_9, 82 FN_IP11_12_11, FN_IP11_14_13, FN_IP11_17_15, FN_IP11_21_18, 83 84 /* GPSR4 */ 85 FN_IP11_23_22, FN_IP11_26_24, FN_IP11_29_27, FN_IP11_31_30, 86 FN_IP12_1_0, FN_IP12_3_2, FN_IP12_5_4, FN_IP12_7_6, FN_IP12_10_8, 87 FN_IP12_13_11, FN_IP12_16_14, FN_IP12_19_17, FN_IP12_22_20, 88 FN_IP12_24_23, FN_IP12_27_25, FN_IP12_30_28, FN_IP13_2_0, 89 FN_IP13_6_3, FN_IP13_9_7, FN_IP13_12_10, FN_IP13_15_13, 90 FN_IP13_18_16, FN_IP13_22_19, FN_IP13_25_23, FN_IP13_28_26, 91 FN_IP13_30_29, FN_IP14_2_0, FN_IP14_5_3, FN_IP14_8_6, FN_IP14_11_9, 92 FN_IP14_15_12, FN_IP14_18_16, 93 94 /* GPSR5 */ 95 FN_IP14_21_19, FN_IP14_24_22, FN_IP14_27_25, FN_IP14_30_28, 96 FN_IP15_2_0, FN_IP15_5_3, FN_IP15_8_6, FN_IP15_11_9, FN_IP15_13_12, 97 FN_IP15_15_14, FN_IP15_17_16, FN_IP15_19_18, FN_IP15_22_20, 98 FN_IP15_25_23, FN_IP15_27_26, FN_IP15_29_28, FN_IP16_2_0, 99 FN_IP16_5_3, FN_USB0_PWEN, FN_USB0_OVC_VBUS, FN_IP16_6, FN_IP16_7, 100 FN_USB2_PWEN, FN_USB2_OVC, FN_AVS1, FN_AVS2, FN_DU_DOTCLKIN0, 101 FN_IP7_26_25, FN_DU_DOTCLKIN2, FN_IP7_18_16, FN_IP7_21_19, FN_IP7_24_22, 102 103 /* IPSR0 */ 104 FN_D0, FN_MSIOF3_SCK_B, FN_VI3_DATA0, FN_VI0_G4, FN_VI0_G4_B, 105 FN_D1, FN_MSIOF3_SYNC_B, FN_VI3_DATA1, FN_VI0_G5, 106 FN_VI0_G5_B, FN_D2, FN_MSIOF3_RXD_B, FN_VI3_DATA2, 107 FN_VI0_G6, FN_VI0_G6_B, FN_D3, FN_MSIOF3_TXD_B, 108 FN_VI3_DATA3, FN_VI0_G7, FN_VI0_G7_B, FN_D4, 109 FN_SCIFB1_RXD_F, FN_SCIFB0_RXD_C, FN_VI3_DATA4, 110 FN_VI0_R0, FN_VI0_R0_B, FN_RX0_B, FN_D5, 111 FN_SCIFB1_TXD_F, FN_SCIFB0_TXD_C, FN_VI3_DATA5, 112 FN_VI0_R1, FN_VI0_R1_B, FN_TX0_B, FN_D6, 113 FN_IIC2_SCL_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B, 114 FN_I2C2_SCL_C, FN_D7, FN_AD_DI_B, FN_IIC2_SDA_C, 115 FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_I2C2_SDA_C, FN_TCLK1, 116 FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0, 117 FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0, 118 119 /* IPSR1 */ 120 FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1, 121 FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1, FN_D10, 122 FN_SCIFA1_TXD_C, FN_AVB_TXD2, 123 FN_VI0_G2, FN_VI0_G2_B, FN_VI2_DATA2_VI2_B2, FN_D11, 124 FN_SCIFA1_CTS_N_C, FN_AVB_TXD3, 125 FN_VI0_G3, FN_VI0_G3_B, FN_VI2_DATA3_VI2_B3, 126 FN_D12, FN_SCIFA1_RTS_N_C, FN_AVB_TXD4, 127 FN_VI0_HSYNC_N, FN_VI0_HSYNC_N_B, FN_VI2_DATA4_VI2_B4, 128 FN_D13, FN_AVB_TXD5, FN_VI0_VSYNC_N, 129 FN_VI0_VSYNC_N_B, FN_VI2_DATA5_VI2_B5, FN_D14, 130 FN_SCIFB1_RXD_C, FN_AVB_TXD6, FN_RX1_B, 131 FN_VI0_CLKENB, FN_VI0_CLKENB_B, FN_VI2_DATA6_VI2_B6, 132 FN_D15, FN_SCIFB1_TXD_C, FN_AVB_TXD7, FN_TX1_B, 133 FN_VI0_FIELD, FN_VI0_FIELD_B, FN_VI2_DATA7_VI2_B7, 134 FN_A0, FN_PWM3, FN_A1, FN_PWM4, 135 136 /* IPSR2 */ 137 FN_A2, FN_PWM5, FN_MSIOF1_SS1_B, FN_A3, 138 FN_PWM6, FN_MSIOF1_SS2_B, FN_A4, FN_MSIOF1_TXD_B, 139 FN_TPU0TO0, FN_A5, FN_SCIFA1_TXD_B, FN_TPU0TO1, 140 FN_A6, FN_SCIFA1_RTS_N_B, FN_TPU0TO2, FN_A7, 141 FN_SCIFA1_SCK_B, FN_AUDIO_CLKOUT_B, FN_TPU0TO3, 142 FN_A8, FN_SCIFA1_RXD_B, FN_SSI_SCK5_B, FN_VI0_R4, 143 FN_VI0_R4_B, FN_SCIFB2_RXD_C, FN_RX2_B, FN_VI2_DATA0_VI2_B0_B, 144 FN_A9, FN_SCIFA1_CTS_N_B, FN_SSI_WS5_B, FN_VI0_R5, 145 FN_VI0_R5_B, FN_SCIFB2_TXD_C, FN_TX2_B, FN_VI2_DATA1_VI2_B1_B, 146 FN_A10, FN_SSI_SDATA5_B, FN_MSIOF2_SYNC, FN_VI0_R6, 147 FN_VI0_R6_B, FN_VI2_DATA2_VI2_B2_B, 148 149 /* IPSR3 */ 150 FN_A11, FN_SCIFB2_CTS_N_B, FN_MSIOF2_SCK, FN_VI1_R0, 151 FN_VI1_R0_B, FN_VI2_G0, FN_VI2_DATA3_VI2_B3_B, 152 FN_A12, FN_SCIFB2_RXD_B, FN_MSIOF2_TXD, FN_VI1_R1, 153 FN_VI1_R1_B, FN_VI2_G1, FN_VI2_DATA4_VI2_B4_B, 154 FN_A13, FN_SCIFB2_RTS_N_B, FN_EX_WAIT2, 155 FN_MSIOF2_RXD, FN_VI1_R2, FN_VI1_R2_B, FN_VI2_G2, 156 FN_VI2_DATA5_VI2_B5_B, FN_A14, FN_SCIFB2_TXD_B, 157 FN_ATACS11_N, FN_MSIOF2_SS1, FN_A15, FN_SCIFB2_SCK_B, 158 FN_ATARD1_N, FN_MSIOF2_SS2, FN_A16, FN_ATAWR1_N, 159 FN_A17, FN_AD_DO_B, FN_ATADIR1_N, FN_A18, 160 FN_AD_CLK_B, FN_ATAG1_N, FN_A19, FN_AD_NCS_N_B, 161 FN_ATACS01_N, FN_EX_WAIT0_B, FN_A20, FN_SPCLK, 162 FN_VI1_R3, FN_VI1_R3_B, FN_VI2_G4, 163 164 /* IPSR4 */ 165 FN_A21, FN_MOSI_IO0, FN_VI1_R4, FN_VI1_R4_B, FN_VI2_G5, 166 FN_A22, FN_MISO_IO1, FN_VI1_R5, FN_VI1_R5_B, 167 FN_VI2_G6, FN_A23, FN_IO2, FN_VI1_G7, 168 FN_VI1_G7_B, FN_VI2_G7, FN_A24, FN_IO3, 169 FN_VI1_R7, FN_VI1_R7_B, FN_VI2_CLKENB, 170 FN_VI2_CLKENB_B, FN_A25, FN_SSL, FN_VI1_G6, 171 FN_VI1_G6_B, FN_VI2_FIELD, FN_VI2_FIELD_B, FN_CS0_N, 172 FN_VI1_R6, FN_VI1_R6_B, FN_VI2_G3, FN_MSIOF0_SS2_B, 173 FN_CS1_N_A26, FN_SPEEDIN, FN_VI0_R7, FN_VI0_R7_B, 174 FN_VI2_CLK, FN_VI2_CLK_B, FN_EX_CS0_N, FN_HRX1_B, 175 FN_VI1_G5, FN_VI1_G5_B, FN_VI2_R0, FN_HTX0_B, 176 FN_MSIOF0_SS1_B, FN_EX_CS1_N, FN_GPS_CLK, 177 FN_HCTS1_N_B, FN_VI1_FIELD, FN_VI1_FIELD_B, 178 FN_VI2_R1, FN_EX_CS2_N, FN_GPS_SIGN, FN_HRTS1_N_B, 179 FN_VI3_CLKENB, FN_VI1_G0, FN_VI1_G0_B, FN_VI2_R2, 180 181 /* IPSR5 */ 182 FN_EX_CS3_N, FN_GPS_MAG, FN_VI3_FIELD, FN_VI1_G1, FN_VI1_G1_B, 183 FN_VI2_R3, FN_EX_CS4_N, FN_MSIOF1_SCK_B, FN_VI3_HSYNC_N, 184 FN_VI2_HSYNC_N, FN_IIC1_SCL, FN_VI2_HSYNC_N_B, 185 FN_INTC_EN0_N, FN_I2C1_SCL, FN_EX_CS5_N, FN_CAN0_RX, 186 FN_MSIOF1_RXD_B, FN_VI3_VSYNC_N, FN_VI1_G2, 187 FN_VI1_G2_B, FN_VI2_R4, FN_IIC1_SDA, FN_INTC_EN1_N, 188 FN_I2C1_SDA, FN_BS_N, FN_IETX, FN_HTX1_B, 189 FN_CAN1_TX, FN_DRACK0, FN_IETX_C, FN_RD_N, 190 FN_CAN0_TX, FN_SCIFA0_SCK_B, FN_RD_WR_N, FN_VI1_G3, 191 FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B, 192 FN_INTC_IRQ4_N, FN_WE0_N, FN_IECLK, FN_CAN_CLK, 193 FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B, 194 FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4, 195 FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B, 196 FN_IERX_C, FN_EX_WAIT0, FN_IRQ3, FN_INTC_IRQ3_N, 197 FN_VI3_CLK, FN_SCIFA0_RTS_N_B, FN_HRX0_B, 198 FN_MSIOF0_SCK_B, FN_DREQ0_N, FN_VI1_HSYNC_N, 199 FN_VI1_HSYNC_N_B, FN_VI2_R7, FN_SSI_SCK78_C, 200 FN_SSI_WS78_B, 201 202 /* IPSR6 */ 203 FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B, 204 FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, 205 FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B, 206 FN_SSI_SDATA7_C, FN_SSI_SCK78_B, FN_DACK1, FN_IRQ1, 207 FN_INTC_IRQ1_N, FN_SSI_WS6_B, FN_SSI_SDATA8_C, 208 FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B, 209 FN_MSIOF0_TXD_B, FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N, 210 FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B, 211 FN_ETH_CRS_DV, FN_STP_ISCLK_0_B, 212 FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_IIC2_SCL_E, 213 FN_I2C2_SCL_E, FN_ETH_RX_ER, 214 FN_STP_ISD_0_B, FN_TS_SPSYNC0_D, FN_GLO_Q1_C, 215 FN_IIC2_SDA_E, FN_I2C2_SDA_E, FN_ETH_RXD0, 216 FN_STP_ISEN_0_B, FN_TS_SDAT0_D, FN_GLO_I0_C, 217 FN_SCIFB1_SCK_G, FN_SCK1_E, FN_ETH_RXD1, 218 FN_HRX0_E, FN_STP_ISSYNC_0_B, 219 FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G, 220 FN_RX1_E, FN_ETH_LINK, FN_HTX0_E, 221 FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E, 222 FN_ETH_REF_CLK, FN_HCTS0_N_E, 223 FN_STP_IVCXO27_1_B, FN_HRX0_F, 224 225 /* IPSR7 */ 226 FN_ETH_MDIO, FN_HRTS0_N_E, 227 FN_SIM0_D_C, FN_HCTS0_N_F, FN_ETH_TXD1, 228 FN_HTX0_F, FN_BPFCLK_G, 229 FN_ETH_TX_EN, FN_SIM0_CLK_C, 230 FN_HRTS0_N_F, FN_ETH_MAGIC, 231 FN_SIM0_RST_C, FN_ETH_TXD0, 232 FN_STP_ISCLK_1_B, FN_TS_SDEN1_C, FN_GLO_SCLK_C, 233 FN_ETH_MDC, FN_STP_ISD_1_B, 234 FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, FN_PWM0, 235 FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C, 236 FN_GLO_SS_C, FN_PWM1, FN_SCIFA2_TXD_C, 237 FN_STP_ISSYNC_1_B, FN_TS_SCK1_C, FN_GLO_RFON_C, 238 FN_PCMOE_N, FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C, 239 FN_PCMWE_N, FN_IECLK_C, FN_DU_DOTCLKIN1, 240 FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, FN_VI0_CLK, 241 FN_ATACS00_N, FN_AVB_RXD1, 242 FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2, 243 244 /* IPSR8 */ 245 FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3, 246 FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N, 247 FN_AVB_RXD4, FN_VI0_DATA3_VI0_B3, FN_ATADIR0_N, 248 FN_AVB_RXD5, FN_VI0_DATA4_VI0_B4, FN_ATAG0_N, 249 FN_AVB_RXD6, FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1, 250 FN_AVB_RXD7, FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER, 251 FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK, 252 FN_VI1_CLK, FN_AVB_RX_DV, 253 FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D, 254 FN_AVB_CRS, FN_VI1_DATA1_VI1_B1, 255 FN_SCIFA1_RXD_D, FN_AVB_MDC, 256 FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO, 257 FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D, 258 FN_AVB_GTX_CLK, FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D, 259 FN_AVB_MAGIC, FN_VI1_DATA5_VI1_B5, 260 FN_AVB_PHY_INT, FN_VI1_DATA6_VI1_B6, FN_AVB_GTXREFCLK, 261 FN_SD0_CLK, FN_VI1_DATA0_VI1_B0_B, FN_SD0_CMD, 262 FN_SCIFB1_SCK_B, FN_VI1_DATA1_VI1_B1_B, 263 264 /* IPSR9 */ 265 FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B, 266 FN_SD0_DAT1, FN_SCIFB1_TXD_B, FN_VI1_DATA3_VI1_B3_B, 267 FN_SD0_DAT2, FN_SCIFB1_CTS_N_B, FN_VI1_DATA4_VI1_B4_B, 268 FN_SD0_DAT3, FN_SCIFB1_RTS_N_B, FN_VI1_DATA5_VI1_B5_B, 269 FN_SD0_CD, FN_MMC0_D6, FN_TS_SDEN0_B, FN_USB0_EXTP, 270 FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_IIC1_SCL_B, 271 FN_I2C1_SCL_B, FN_VI2_DATA6_VI2_B6_B, FN_SD0_WP, 272 FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN, 273 FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_IIC1_SDA_B, 274 FN_I2C1_SDA_B, FN_VI2_DATA7_VI2_B7_B, FN_SD1_CLK, 275 FN_AVB_TX_EN, FN_SD1_CMD, 276 FN_AVB_TX_ER, FN_SCIFB0_SCK_B, 277 FN_SD1_DAT0, FN_AVB_TX_CLK, 278 FN_SCIFB0_RXD_B, FN_SD1_DAT1, FN_AVB_LINK, 279 FN_SCIFB0_TXD_B, FN_SD1_DAT2, 280 FN_AVB_COL, FN_SCIFB0_CTS_N_B, 281 FN_SD1_DAT3, FN_AVB_RXD0, 282 FN_SCIFB0_RTS_N_B, FN_SD1_CD, FN_MMC1_D6, 283 FN_TS_SDEN1, FN_USB1_EXTP, FN_GLO_SS, FN_VI0_CLK_B, 284 FN_IIC2_SCL_D, FN_I2C2_SCL_D, FN_SIM0_CLK_B, 285 FN_VI3_CLK_B, 286 287 /* IPSR10 */ 288 FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN, 289 FN_GLO_RFON, FN_VI1_CLK_B, FN_IIC2_SDA_D, FN_I2C2_SDA_D, 290 FN_SIM0_D_B, FN_SD2_CLK, FN_MMC0_CLK, FN_SIM0_CLK, 291 FN_VI0_DATA0_VI0_B0_B, FN_TS_SDEN0_C, FN_GLO_SCLK_B, 292 FN_VI3_DATA0_B, FN_SD2_CMD, FN_MMC0_CMD, FN_SIM0_D, 293 FN_VI0_DATA1_VI0_B1_B, FN_SCIFB1_SCK_E, FN_SCK1_D, 294 FN_TS_SPSYNC0_C, FN_GLO_SDATA_B, FN_VI3_DATA1_B, 295 FN_SD2_DAT0, FN_MMC0_D0, FN_FMCLK_B, 296 FN_VI0_DATA2_VI0_B2_B, FN_SCIFB1_RXD_E, FN_RX1_D, 297 FN_TS_SDAT0_C, FN_GLO_SS_B, FN_VI3_DATA2_B, 298 FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B, 299 FN_VI0_DATA3_VI0_B3_B, FN_SCIFB1_TXD_E, FN_TX1_D, 300 FN_TS_SCK0_C, FN_GLO_RFON_B, FN_VI3_DATA3_B, 301 FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B, 302 FN_VI0_DATA4_VI0_B4_B, FN_HRX0_D, FN_TS_SDEN1_B, 303 FN_GLO_Q0_B, FN_VI3_DATA4_B, FN_SD2_DAT3, 304 FN_MMC0_D3, FN_SIM0_RST, FN_VI0_DATA5_VI0_B5_B, 305 FN_HTX0_D, FN_TS_SPSYNC1_B, FN_GLO_Q1_B, 306 FN_VI3_DATA5_B, FN_SD2_CD, FN_MMC0_D4, 307 FN_TS_SDAT0_B, FN_USB2_EXTP, FN_GLO_I0, 308 FN_VI0_DATA6_VI0_B6_B, FN_HCTS0_N_D, FN_TS_SDAT1_B, 309 FN_GLO_I0_B, FN_VI3_DATA6_B, 310 311 /* IPSR11 */ 312 FN_SD2_WP, FN_MMC0_D5, FN_TS_SCK0_B, FN_USB2_IDIN, 313 FN_GLO_I1, FN_VI0_DATA7_VI0_B7_B, FN_HRTS0_N_D, 314 FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B, 315 FN_SD3_CLK, FN_MMC1_CLK, FN_SD3_CMD, FN_MMC1_CMD, 316 FN_MTS_N, FN_SD3_DAT0, FN_MMC1_D0, FN_STM_N, 317 FN_SD3_DAT1, FN_MMC1_D1, FN_MDATA, FN_SD3_DAT2, 318 FN_MMC1_D2, FN_SDATA, FN_SD3_DAT3, FN_MMC1_D3, 319 FN_SCKZ, FN_SD3_CD, FN_MMC1_D4, FN_TS_SDAT1, 320 FN_VSP, FN_GLO_Q0, FN_SIM0_RST_B, FN_SD3_WP, 321 FN_MMC1_D5, FN_TS_SCK1, FN_GLO_Q1, FN_FMIN_C, 322 FN_FMIN_E, FN_FMIN_F, 323 FN_MLB_CLK, FN_IIC2_SCL_B, FN_I2C2_SCL_B, 324 FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_IIC2_SDA_B, 325 FN_I2C2_SDA_B, FN_MLB_DAT, 326 FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C, 327 FN_SSI_SCK0129, FN_CAN_CLK_B, 328 FN_MOUT0, 329 330 /* IPSR12 */ 331 FN_SSI_WS0129, FN_CAN0_TX_B, FN_MOUT1, 332 FN_SSI_SDATA0, FN_CAN0_RX_B, FN_MOUT2, 333 FN_SSI_SDATA1, FN_CAN1_TX_B, FN_MOUT5, 334 FN_SSI_SDATA2, FN_CAN1_RX_B, FN_SSI_SCK1, FN_MOUT6, 335 FN_SSI_SCK34, FN_STP_OPWM_0, FN_SCIFB0_SCK, 336 FN_MSIOF1_SCK, FN_CAN_DEBUG_HW_TRIGGER, FN_SSI_WS34, 337 FN_STP_IVCXO27_0, FN_SCIFB0_RXD, FN_MSIOF1_SYNC, 338 FN_CAN_STEP0, FN_SSI_SDATA3, FN_STP_ISCLK_0, 339 FN_SCIFB0_TXD, FN_MSIOF1_SS1, FN_CAN_TXCLK, 340 FN_SSI_SCK4, FN_STP_ISD_0, FN_SCIFB0_CTS_N, 341 FN_MSIOF1_SS2, FN_SSI_SCK5_C, FN_CAN_DEBUGOUT0, 342 FN_SSI_WS4, FN_STP_ISEN_0, FN_SCIFB0_RTS_N, 343 FN_MSIOF1_TXD, FN_SSI_WS5_C, FN_CAN_DEBUGOUT1, 344 FN_SSI_SDATA4, FN_STP_ISSYNC_0, FN_MSIOF1_RXD, 345 FN_CAN_DEBUGOUT2, FN_SSI_SCK5, FN_SCIFB1_SCK, 346 FN_IERX_B, FN_DU2_EXHSYNC_DU2_HSYNC, FN_QSTH_QHS, 347 FN_CAN_DEBUGOUT3, FN_SSI_WS5, FN_SCIFB1_RXD, 348 FN_IECLK_B, FN_DU2_EXVSYNC_DU2_VSYNC, FN_QSTB_QHE, 349 FN_CAN_DEBUGOUT4, 350 351 /* IPSR13 */ 352 FN_SSI_SDATA5, FN_SCIFB1_TXD, FN_IETX_B, FN_DU2_DR2, 353 FN_LCDOUT2, FN_CAN_DEBUGOUT5, FN_SSI_SCK6, 354 FN_SCIFB1_CTS_N, FN_BPFCLK_D, 355 FN_DU2_DR3, FN_LCDOUT3, FN_CAN_DEBUGOUT6, 356 FN_BPFCLK_F, FN_SSI_WS6, 357 FN_SCIFB1_RTS_N, FN_CAN0_TX_D, FN_DU2_DR4, 358 FN_LCDOUT4, FN_CAN_DEBUGOUT7, FN_SSI_SDATA6, 359 FN_FMIN_D, FN_DU2_DR5, FN_LCDOUT5, 360 FN_CAN_DEBUGOUT8, FN_SSI_SCK78, FN_STP_IVCXO27_1, 361 FN_SCK1, FN_SCIFA1_SCK, FN_DU2_DR6, FN_LCDOUT6, 362 FN_CAN_DEBUGOUT9, FN_SSI_WS78, FN_STP_ISCLK_1, 363 FN_SCIFB2_SCK, FN_SCIFA2_CTS_N, FN_DU2_DR7, 364 FN_LCDOUT7, FN_CAN_DEBUGOUT10, FN_SSI_SDATA7, 365 FN_STP_ISD_1, FN_SCIFB2_RXD, FN_SCIFA2_RTS_N, 366 FN_TCLK2, FN_QSTVA_QVS, FN_CAN_DEBUGOUT11, 367 FN_BPFCLK_E, FN_SSI_SDATA7_B, 368 FN_FMIN_G, FN_SSI_SDATA8, 369 FN_STP_ISEN_1, FN_SCIFB2_TXD, FN_CAN0_TX_C, 370 FN_CAN_DEBUGOUT12, FN_SSI_SDATA8_B, FN_SSI_SDATA9, 371 FN_STP_ISSYNC_1, FN_SCIFB2_CTS_N, FN_SSI_WS1, 372 FN_SSI_SDATA5_C, FN_CAN_DEBUGOUT13, FN_AUDIO_CLKA, 373 FN_SCIFB2_RTS_N, FN_CAN_DEBUGOUT14, 374 375 /* IPSR14 */ 376 FN_AUDIO_CLKB, FN_SCIF_CLK, FN_CAN0_RX_D, 377 FN_DVC_MUTE, FN_CAN0_RX_C, FN_CAN_DEBUGOUT15, 378 FN_REMOCON, FN_SCIFA0_SCK, FN_HSCK1, FN_SCK0, 379 FN_MSIOF3_SS2, FN_DU2_DG2, FN_LCDOUT10, FN_IIC1_SDA_C, 380 FN_I2C1_SDA_C, FN_SCIFA0_RXD, FN_HRX1, FN_RX0, 381 FN_DU2_DR0, FN_LCDOUT0, FN_SCIFA0_TXD, FN_HTX1, 382 FN_TX0, FN_DU2_DR1, FN_LCDOUT1, FN_SCIFA0_CTS_N, 383 FN_HCTS1_N, FN_CTS0_N, FN_MSIOF3_SYNC, FN_DU2_DG3, 384 FN_LCDOUT11, FN_PWM0_B, FN_IIC1_SCL_C, FN_I2C1_SCL_C, 385 FN_SCIFA0_RTS_N, FN_HRTS1_N, FN_RTS0_N, 386 FN_MSIOF3_SS1, FN_DU2_DG0, FN_LCDOUT8, FN_PWM1_B, 387 FN_SCIFA1_RXD, FN_AD_DI, FN_RX1, 388 FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, FN_QCPV_QDE, 389 FN_SCIFA1_TXD, FN_AD_DO, FN_TX1, FN_DU2_DG1, 390 FN_LCDOUT9, FN_SCIFA1_CTS_N, FN_AD_CLK, 391 FN_CTS1_N, FN_MSIOF3_RXD, FN_DU0_DOTCLKOUT, FN_QCLK, 392 FN_SCIFA1_RTS_N, FN_AD_NCS_N, FN_RTS1_N, 393 FN_MSIOF3_TXD, FN_DU1_DOTCLKOUT, FN_QSTVB_QVE, 394 FN_HRTS0_N_C, 395 396 /* IPSR15 */ 397 FN_SCIFA2_SCK, FN_FMCLK, FN_SCK2, FN_MSIOF3_SCK, FN_DU2_DG7, 398 FN_LCDOUT15, FN_SCIF_CLK_B, FN_SCIFA2_RXD, FN_FMIN, 399 FN_TX2, FN_DU2_DB0, FN_LCDOUT16, FN_IIC2_SCL, FN_I2C2_SCL, 400 FN_SCIFA2_TXD, FN_BPFCLK, FN_RX2, FN_DU2_DB1, FN_LCDOUT17, 401 FN_IIC2_SDA, FN_I2C2_SDA, FN_HSCK0, FN_TS_SDEN0, 402 FN_DU2_DG4, FN_LCDOUT12, FN_HCTS0_N_C, FN_HRX0, 403 FN_DU2_DB2, FN_LCDOUT18, FN_HTX0, FN_DU2_DB3, 404 FN_LCDOUT19, FN_HCTS0_N, FN_SSI_SCK9, FN_DU2_DB4, 405 FN_LCDOUT20, FN_HRTS0_N, FN_SSI_WS9, FN_DU2_DB5, 406 FN_LCDOUT21, FN_MSIOF0_SCK, FN_TS_SDAT0, FN_ADICLK, 407 FN_DU2_DB6, FN_LCDOUT22, FN_MSIOF0_SYNC, FN_TS_SCK0, 408 FN_SSI_SCK2, FN_ADIDATA, FN_DU2_DB7, FN_LCDOUT23, 409 FN_HRX0_C, FN_MSIOF0_SS1, FN_ADICHS0, 410 FN_DU2_DG5, FN_LCDOUT13, FN_MSIOF0_TXD, FN_ADICHS1, 411 FN_DU2_DG6, FN_LCDOUT14, 412 413 /* IPSR16 */ 414 FN_MSIOF0_SS2, FN_AUDIO_CLKOUT, FN_ADICHS2, 415 FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B, 416 FN_MSIOF0_RXD, FN_TS_SPSYNC0, FN_SSI_WS2, 417 FN_ADICS_SAMP, FN_DU2_CDE, FN_QPOLB, FN_SCIFA2_RXD_B, 418 FN_USB1_PWEN, FN_AUDIO_CLKOUT_D, FN_USB1_OVC, 419 FN_TCLK1_B, 420 421 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3, 422 FN_SEL_SCIF1_4, 423 FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, 424 FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, 425 FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3, 426 FN_SEL_SCIFB1_4, 427 FN_SEL_SCIFB1_5, FN_SEL_SCIFB1_6, 428 FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, FN_SEL_SCIFA1_3, 429 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, 430 FN_SEL_SCFA_0, FN_SEL_SCFA_1, 431 FN_SEL_SOF1_0, FN_SEL_SOF1_1, 432 FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2, 433 FN_SEL_SSI6_0, FN_SEL_SSI6_1, 434 FN_SEL_SSI5_0, FN_SEL_SSI5_1, FN_SEL_SSI5_2, 435 FN_SEL_VI3_0, FN_SEL_VI3_1, 436 FN_SEL_VI2_0, FN_SEL_VI2_1, 437 FN_SEL_VI1_0, FN_SEL_VI1_1, 438 FN_SEL_VI0_0, FN_SEL_VI0_1, 439 FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2, 440 FN_SEL_LBS_0, FN_SEL_LBS_1, 441 FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, 442 FN_SEL_SOF3_0, FN_SEL_SOF3_1, 443 FN_SEL_SOF0_0, FN_SEL_SOF0_1, 444 445 FN_SEL_TMU1_0, FN_SEL_TMU1_1, 446 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, 447 FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1, 448 FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3, 449 FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, 450 FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2, 451 FN_SEL_CAN1_0, FN_SEL_CAN1_1, 452 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, 453 FN_SEL_ADI_0, FN_SEL_ADI_1, 454 FN_SEL_SSP_0, FN_SEL_SSP_1, 455 FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3, 456 FN_SEL_FM_4, FN_SEL_FM_5, FN_SEL_FM_6, 457 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, FN_SEL_HSCIF0_3, 458 FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5, 459 FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, 460 FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2, 461 FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2, 462 463 FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1, 464 FN_SEL_IIC0_0, FN_SEL_IIC0_1, 465 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 466 FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3, 467 FN_SEL_IIC2_4, 468 FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, 469 FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3, 470 FN_SEL_I2C2_4, 471 FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, 472 PINMUX_FUNCTION_END, 473 474 PINMUX_MARK_BEGIN, 475 476 VI1_DATA7_VI1_B7_MARK, 477 478 USB0_PWEN_MARK, USB0_OVC_VBUS_MARK, 479 USB2_PWEN_MARK, USB2_OVC_MARK, AVS1_MARK, AVS2_MARK, 480 DU_DOTCLKIN0_MARK, DU_DOTCLKIN2_MARK, 481 482 D0_MARK, MSIOF3_SCK_B_MARK, VI3_DATA0_MARK, VI0_G4_MARK, VI0_G4_B_MARK, 483 D1_MARK, MSIOF3_SYNC_B_MARK, VI3_DATA1_MARK, VI0_G5_MARK, 484 VI0_G5_B_MARK, D2_MARK, MSIOF3_RXD_B_MARK, VI3_DATA2_MARK, 485 VI0_G6_MARK, VI0_G6_B_MARK, D3_MARK, MSIOF3_TXD_B_MARK, 486 VI3_DATA3_MARK, VI0_G7_MARK, VI0_G7_B_MARK, D4_MARK, 487 SCIFB1_RXD_F_MARK, SCIFB0_RXD_C_MARK, VI3_DATA4_MARK, 488 VI0_R0_MARK, VI0_R0_B_MARK, RX0_B_MARK, D5_MARK, 489 SCIFB1_TXD_F_MARK, SCIFB0_TXD_C_MARK, VI3_DATA5_MARK, 490 VI0_R1_MARK, VI0_R1_B_MARK, TX0_B_MARK, D6_MARK, 491 IIC2_SCL_C_MARK, VI3_DATA6_MARK, VI0_R2_MARK, VI0_R2_B_MARK, 492 I2C2_SCL_C_MARK, D7_MARK, AD_DI_B_MARK, IIC2_SDA_C_MARK, 493 VI3_DATA7_MARK, VI0_R3_MARK, VI0_R3_B_MARK, I2C2_SDA_C_MARK, TCLK1_MARK, 494 D8_MARK, SCIFA1_SCK_C_MARK, AVB_TXD0_MARK, 495 VI0_G0_MARK, VI0_G0_B_MARK, VI2_DATA0_VI2_B0_MARK, 496 497 D9_MARK, SCIFA1_RXD_C_MARK, AVB_TXD1_MARK, 498 VI0_G1_MARK, VI0_G1_B_MARK, VI2_DATA1_VI2_B1_MARK, D10_MARK, 499 SCIFA1_TXD_C_MARK, AVB_TXD2_MARK, 500 VI0_G2_MARK, VI0_G2_B_MARK, VI2_DATA2_VI2_B2_MARK, D11_MARK, 501 SCIFA1_CTS_N_C_MARK, AVB_TXD3_MARK, 502 VI0_G3_MARK, VI0_G3_B_MARK, VI2_DATA3_VI2_B3_MARK, 503 D12_MARK, SCIFA1_RTS_N_C_MARK, AVB_TXD4_MARK, 504 VI0_HSYNC_N_MARK, VI0_HSYNC_N_B_MARK, VI2_DATA4_VI2_B4_MARK, 505 D13_MARK, AVB_TXD5_MARK, VI0_VSYNC_N_MARK, 506 VI0_VSYNC_N_B_MARK, VI2_DATA5_VI2_B5_MARK, D14_MARK, 507 SCIFB1_RXD_C_MARK, AVB_TXD6_MARK, RX1_B_MARK, 508 VI0_CLKENB_MARK, VI0_CLKENB_B_MARK, VI2_DATA6_VI2_B6_MARK, 509 D15_MARK, SCIFB1_TXD_C_MARK, AVB_TXD7_MARK, TX1_B_MARK, 510 VI0_FIELD_MARK, VI0_FIELD_B_MARK, VI2_DATA7_VI2_B7_MARK, 511 A0_MARK, PWM3_MARK, A1_MARK, PWM4_MARK, 512 513 A2_MARK, PWM5_MARK, MSIOF1_SS1_B_MARK, A3_MARK, 514 PWM6_MARK, MSIOF1_SS2_B_MARK, A4_MARK, MSIOF1_TXD_B_MARK, 515 TPU0TO0_MARK, A5_MARK, SCIFA1_TXD_B_MARK, TPU0TO1_MARK, 516 A6_MARK, SCIFA1_RTS_N_B_MARK, TPU0TO2_MARK, A7_MARK, 517 SCIFA1_SCK_B_MARK, AUDIO_CLKOUT_B_MARK, TPU0TO3_MARK, 518 A8_MARK, SCIFA1_RXD_B_MARK, SSI_SCK5_B_MARK, VI0_R4_MARK, 519 VI0_R4_B_MARK, SCIFB2_RXD_C_MARK, RX2_B_MARK, VI2_DATA0_VI2_B0_B_MARK, 520 A9_MARK, SCIFA1_CTS_N_B_MARK, SSI_WS5_B_MARK, VI0_R5_MARK, 521 VI0_R5_B_MARK, SCIFB2_TXD_C_MARK, TX2_B_MARK, VI2_DATA1_VI2_B1_B_MARK, 522 A10_MARK, SSI_SDATA5_B_MARK, MSIOF2_SYNC_MARK, VI0_R6_MARK, 523 VI0_R6_B_MARK, VI2_DATA2_VI2_B2_B_MARK, 524 525 A11_MARK, SCIFB2_CTS_N_B_MARK, MSIOF2_SCK_MARK, VI1_R0_MARK, 526 VI1_R0_B_MARK, VI2_G0_MARK, VI2_DATA3_VI2_B3_B_MARK, 527 A12_MARK, SCIFB2_RXD_B_MARK, MSIOF2_TXD_MARK, VI1_R1_MARK, 528 VI1_R1_B_MARK, VI2_G1_MARK, VI2_DATA4_VI2_B4_B_MARK, 529 A13_MARK, SCIFB2_RTS_N_B_MARK, EX_WAIT2_MARK, 530 MSIOF2_RXD_MARK, VI1_R2_MARK, VI1_R2_B_MARK, VI2_G2_MARK, 531 VI2_DATA5_VI2_B5_B_MARK, A14_MARK, SCIFB2_TXD_B_MARK, 532 ATACS11_N_MARK, MSIOF2_SS1_MARK, A15_MARK, SCIFB2_SCK_B_MARK, 533 ATARD1_N_MARK, MSIOF2_SS2_MARK, A16_MARK, ATAWR1_N_MARK, 534 A17_MARK, AD_DO_B_MARK, ATADIR1_N_MARK, A18_MARK, 535 AD_CLK_B_MARK, ATAG1_N_MARK, A19_MARK, AD_NCS_N_B_MARK, 536 ATACS01_N_MARK, EX_WAIT0_B_MARK, A20_MARK, SPCLK_MARK, 537 VI1_R3_MARK, VI1_R3_B_MARK, VI2_G4_MARK, 538 539 A21_MARK, MOSI_IO0_MARK, VI1_R4_MARK, VI1_R4_B_MARK, VI2_G5_MARK, 540 A22_MARK, MISO_IO1_MARK, VI1_R5_MARK, VI1_R5_B_MARK, 541 VI2_G6_MARK, A23_MARK, IO2_MARK, VI1_G7_MARK, 542 VI1_G7_B_MARK, VI2_G7_MARK, A24_MARK, IO3_MARK, 543 VI1_R7_MARK, VI1_R7_B_MARK, VI2_CLKENB_MARK, 544 VI2_CLKENB_B_MARK, A25_MARK, SSL_MARK, VI1_G6_MARK, 545 VI1_G6_B_MARK, VI2_FIELD_MARK, VI2_FIELD_B_MARK, CS0_N_MARK, 546 VI1_R6_MARK, VI1_R6_B_MARK, VI2_G3_MARK, MSIOF0_SS2_B_MARK, 547 CS1_N_A26_MARK, SPEEDIN_MARK, VI0_R7_MARK, VI0_R7_B_MARK, 548 VI2_CLK_MARK, VI2_CLK_B_MARK, EX_CS0_N_MARK, HRX1_B_MARK, 549 VI1_G5_MARK, VI1_G5_B_MARK, VI2_R0_MARK, HTX0_B_MARK, 550 MSIOF0_SS1_B_MARK, EX_CS1_N_MARK, GPS_CLK_MARK, 551 HCTS1_N_B_MARK, VI1_FIELD_MARK, VI1_FIELD_B_MARK, 552 VI2_R1_MARK, EX_CS2_N_MARK, GPS_SIGN_MARK, HRTS1_N_B_MARK, 553 VI3_CLKENB_MARK, VI1_G0_MARK, VI1_G0_B_MARK, VI2_R2_MARK, 554 555 EX_CS3_N_MARK, GPS_MAG_MARK, VI3_FIELD_MARK, 556 VI1_G1_MARK, VI1_G1_B_MARK, VI2_R3_MARK, 557 EX_CS4_N_MARK, MSIOF1_SCK_B_MARK, VI3_HSYNC_N_MARK, 558 VI2_HSYNC_N_MARK, IIC1_SCL_MARK, VI2_HSYNC_N_B_MARK, 559 INTC_EN0_N_MARK, I2C1_SCL_MARK, EX_CS5_N_MARK, CAN0_RX_MARK, 560 MSIOF1_RXD_B_MARK, VI3_VSYNC_N_MARK, VI1_G2_MARK, 561 VI1_G2_B_MARK, VI2_R4_MARK, IIC1_SDA_MARK, INTC_EN1_N_MARK, 562 I2C1_SDA_MARK, BS_N_MARK, IETX_MARK, HTX1_B_MARK, 563 CAN1_TX_MARK, DRACK0_MARK, IETX_C_MARK, RD_N_MARK, 564 CAN0_TX_MARK, SCIFA0_SCK_B_MARK, RD_WR_N_MARK, VI1_G3_MARK, 565 VI1_G3_B_MARK, VI2_R5_MARK, SCIFA0_RXD_B_MARK, 566 INTC_IRQ4_N_MARK, WE0_N_MARK, IECLK_MARK, CAN_CLK_MARK, 567 VI2_VSYNC_N_MARK, SCIFA0_TXD_B_MARK, VI2_VSYNC_N_B_MARK, 568 WE1_N_MARK, IERX_MARK, CAN1_RX_MARK, VI1_G4_MARK, 569 VI1_G4_B_MARK, VI2_R6_MARK, SCIFA0_CTS_N_B_MARK, 570 IERX_C_MARK, EX_WAIT0_MARK, IRQ3_MARK, INTC_IRQ3_N_MARK, 571 VI3_CLK_MARK, SCIFA0_RTS_N_B_MARK, HRX0_B_MARK, 572 MSIOF0_SCK_B_MARK, DREQ0_N_MARK, VI1_HSYNC_N_MARK, 573 VI1_HSYNC_N_B_MARK, VI2_R7_MARK, SSI_SCK78_C_MARK, 574 SSI_WS78_B_MARK, 575 576 DACK0_MARK, IRQ0_MARK, INTC_IRQ0_N_MARK, SSI_SCK6_B_MARK, 577 VI1_VSYNC_N_MARK, VI1_VSYNC_N_B_MARK, SSI_WS78_C_MARK, 578 DREQ1_N_MARK, VI1_CLKENB_MARK, VI1_CLKENB_B_MARK, 579 SSI_SDATA7_C_MARK, SSI_SCK78_B_MARK, DACK1_MARK, IRQ1_MARK, 580 INTC_IRQ1_N_MARK, SSI_WS6_B_MARK, SSI_SDATA8_C_MARK, 581 DREQ2_N_MARK, HSCK1_B_MARK, HCTS0_N_B_MARK, 582 MSIOF0_TXD_B_MARK, DACK2_MARK, IRQ2_MARK, INTC_IRQ2_N_MARK, 583 SSI_SDATA6_B_MARK, HRTS0_N_B_MARK, MSIOF0_RXD_B_MARK, 584 ETH_CRS_DV_MARK, STP_ISCLK_0_B_MARK, 585 TS_SDEN0_D_MARK, GLO_Q0_C_MARK, IIC2_SCL_E_MARK, 586 I2C2_SCL_E_MARK, ETH_RX_ER_MARK, 587 STP_ISD_0_B_MARK, TS_SPSYNC0_D_MARK, GLO_Q1_C_MARK, 588 IIC2_SDA_E_MARK, I2C2_SDA_E_MARK, ETH_RXD0_MARK, 589 STP_ISEN_0_B_MARK, TS_SDAT0_D_MARK, GLO_I0_C_MARK, 590 SCIFB1_SCK_G_MARK, SCK1_E_MARK, ETH_RXD1_MARK, 591 HRX0_E_MARK, STP_ISSYNC_0_B_MARK, 592 TS_SCK0_D_MARK, GLO_I1_C_MARK, SCIFB1_RXD_G_MARK, 593 RX1_E_MARK, ETH_LINK_MARK, HTX0_E_MARK, 594 STP_IVCXO27_0_B_MARK, SCIFB1_TXD_G_MARK, TX1_E_MARK, 595 ETH_REF_CLK_MARK, HCTS0_N_E_MARK, 596 STP_IVCXO27_1_B_MARK, HRX0_F_MARK, 597 598 ETH_MDIO_MARK, HRTS0_N_E_MARK, 599 SIM0_D_C_MARK, HCTS0_N_F_MARK, ETH_TXD1_MARK, 600 HTX0_F_MARK, BPFCLK_G_MARK, 601 ETH_TX_EN_MARK, SIM0_CLK_C_MARK, 602 HRTS0_N_F_MARK, ETH_MAGIC_MARK, 603 SIM0_RST_C_MARK, ETH_TXD0_MARK, 604 STP_ISCLK_1_B_MARK, TS_SDEN1_C_MARK, GLO_SCLK_C_MARK, 605 ETH_MDC_MARK, STP_ISD_1_B_MARK, 606 TS_SPSYNC1_C_MARK, GLO_SDATA_C_MARK, PWM0_MARK, 607 SCIFA2_SCK_C_MARK, STP_ISEN_1_B_MARK, TS_SDAT1_C_MARK, 608 GLO_SS_C_MARK, PWM1_MARK, SCIFA2_TXD_C_MARK, 609 STP_ISSYNC_1_B_MARK, TS_SCK1_C_MARK, GLO_RFON_C_MARK, 610 PCMOE_N_MARK, PWM2_MARK, PWMFSW0_MARK, SCIFA2_RXD_C_MARK, 611 PCMWE_N_MARK, IECLK_C_MARK, DU_DOTCLKIN1_MARK, 612 AUDIO_CLKC_MARK, AUDIO_CLKOUT_C_MARK, VI0_CLK_MARK, 613 ATACS00_N_MARK, AVB_RXD1_MARK, 614 VI0_DATA0_VI0_B0_MARK, ATACS10_N_MARK, AVB_RXD2_MARK, 615 616 VI0_DATA1_VI0_B1_MARK, ATARD0_N_MARK, AVB_RXD3_MARK, 617 VI0_DATA2_VI0_B2_MARK, ATAWR0_N_MARK, 618 AVB_RXD4_MARK, VI0_DATA3_VI0_B3_MARK, ATADIR0_N_MARK, 619 AVB_RXD5_MARK, VI0_DATA4_VI0_B4_MARK, ATAG0_N_MARK, 620 AVB_RXD6_MARK, VI0_DATA5_VI0_B5_MARK, EX_WAIT1_MARK, 621 AVB_RXD7_MARK, VI0_DATA6_VI0_B6_MARK, AVB_RX_ER_MARK, 622 VI0_DATA7_VI0_B7_MARK, AVB_RX_CLK_MARK, 623 VI1_CLK_MARK, AVB_RX_DV_MARK, 624 VI1_DATA0_VI1_B0_MARK, SCIFA1_SCK_D_MARK, 625 AVB_CRS_MARK, VI1_DATA1_VI1_B1_MARK, 626 SCIFA1_RXD_D_MARK, AVB_MDC_MARK, 627 VI1_DATA2_VI1_B2_MARK, SCIFA1_TXD_D_MARK, AVB_MDIO_MARK, 628 VI1_DATA3_VI1_B3_MARK, SCIFA1_CTS_N_D_MARK, 629 AVB_GTX_CLK_MARK, VI1_DATA4_VI1_B4_MARK, SCIFA1_RTS_N_D_MARK, 630 AVB_MAGIC_MARK, VI1_DATA5_VI1_B5_MARK, 631 AVB_PHY_INT_MARK, VI1_DATA6_VI1_B6_MARK, AVB_GTXREFCLK_MARK, 632 SD0_CLK_MARK, VI1_DATA0_VI1_B0_B_MARK, SD0_CMD_MARK, 633 SCIFB1_SCK_B_MARK, VI1_DATA1_VI1_B1_B_MARK, 634 635 SD0_DAT0_MARK, SCIFB1_RXD_B_MARK, VI1_DATA2_VI1_B2_B_MARK, 636 SD0_DAT1_MARK, SCIFB1_TXD_B_MARK, VI1_DATA3_VI1_B3_B_MARK, 637 SD0_DAT2_MARK, SCIFB1_CTS_N_B_MARK, VI1_DATA4_VI1_B4_B_MARK, 638 SD0_DAT3_MARK, SCIFB1_RTS_N_B_MARK, VI1_DATA5_VI1_B5_B_MARK, 639 SD0_CD_MARK, MMC0_D6_MARK, TS_SDEN0_B_MARK, USB0_EXTP_MARK, 640 GLO_SCLK_MARK, VI1_DATA6_VI1_B6_B_MARK, IIC1_SCL_B_MARK, 641 I2C1_SCL_B_MARK, VI2_DATA6_VI2_B6_B_MARK, SD0_WP_MARK, 642 MMC0_D7_MARK, TS_SPSYNC0_B_MARK, USB0_IDIN_MARK, 643 GLO_SDATA_MARK, VI1_DATA7_VI1_B7_B_MARK, IIC1_SDA_B_MARK, 644 I2C1_SDA_B_MARK, VI2_DATA7_VI2_B7_B_MARK, SD1_CLK_MARK, 645 AVB_TX_EN_MARK, SD1_CMD_MARK, 646 AVB_TX_ER_MARK, SCIFB0_SCK_B_MARK, 647 SD1_DAT0_MARK, AVB_TX_CLK_MARK, 648 SCIFB0_RXD_B_MARK, SD1_DAT1_MARK, AVB_LINK_MARK, 649 SCIFB0_TXD_B_MARK, SD1_DAT2_MARK, 650 AVB_COL_MARK, SCIFB0_CTS_N_B_MARK, 651 SD1_DAT3_MARK, AVB_RXD0_MARK, 652 SCIFB0_RTS_N_B_MARK, SD1_CD_MARK, MMC1_D6_MARK, 653 TS_SDEN1_MARK, USB1_EXTP_MARK, GLO_SS_MARK, VI0_CLK_B_MARK, 654 IIC2_SCL_D_MARK, I2C2_SCL_D_MARK, SIM0_CLK_B_MARK, 655 VI3_CLK_B_MARK, 656 657 SD1_WP_MARK, MMC1_D7_MARK, TS_SPSYNC1_MARK, USB1_IDIN_MARK, 658 GLO_RFON_MARK, VI1_CLK_B_MARK, IIC2_SDA_D_MARK, I2C2_SDA_D_MARK, 659 SIM0_D_B_MARK, SD2_CLK_MARK, MMC0_CLK_MARK, SIM0_CLK_MARK, 660 VI0_DATA0_VI0_B0_B_MARK, TS_SDEN0_C_MARK, GLO_SCLK_B_MARK, 661 VI3_DATA0_B_MARK, SD2_CMD_MARK, MMC0_CMD_MARK, SIM0_D_MARK, 662 VI0_DATA1_VI0_B1_B_MARK, SCIFB1_SCK_E_MARK, SCK1_D_MARK, 663 TS_SPSYNC0_C_MARK, GLO_SDATA_B_MARK, VI3_DATA1_B_MARK, 664 SD2_DAT0_MARK, MMC0_D0_MARK, FMCLK_B_MARK, 665 VI0_DATA2_VI0_B2_B_MARK, SCIFB1_RXD_E_MARK, RX1_D_MARK, 666 TS_SDAT0_C_MARK, GLO_SS_B_MARK, VI3_DATA2_B_MARK, 667 SD2_DAT1_MARK, MMC0_D1_MARK, FMIN_B_MARK, 668 VI0_DATA3_VI0_B3_B_MARK, SCIFB1_TXD_E_MARK, TX1_D_MARK, 669 TS_SCK0_C_MARK, GLO_RFON_B_MARK, VI3_DATA3_B_MARK, 670 SD2_DAT2_MARK, MMC0_D2_MARK, BPFCLK_B_MARK, 671 VI0_DATA4_VI0_B4_B_MARK, HRX0_D_MARK, TS_SDEN1_B_MARK, 672 GLO_Q0_B_MARK, VI3_DATA4_B_MARK, SD2_DAT3_MARK, 673 MMC0_D3_MARK, SIM0_RST_MARK, VI0_DATA5_VI0_B5_B_MARK, 674 HTX0_D_MARK, TS_SPSYNC1_B_MARK, GLO_Q1_B_MARK, 675 VI3_DATA5_B_MARK, SD2_CD_MARK, MMC0_D4_MARK, 676 TS_SDAT0_B_MARK, USB2_EXTP_MARK, GLO_I0_MARK, 677 VI0_DATA6_VI0_B6_B_MARK, HCTS0_N_D_MARK, TS_SDAT1_B_MARK, 678 GLO_I0_B_MARK, VI3_DATA6_B_MARK, 679 680 SD2_WP_MARK, MMC0_D5_MARK, TS_SCK0_B_MARK, USB2_IDIN_MARK, 681 GLO_I1_MARK, VI0_DATA7_VI0_B7_B_MARK, HRTS0_N_D_MARK, 682 TS_SCK1_B_MARK, GLO_I1_B_MARK, VI3_DATA7_B_MARK, 683 SD3_CLK_MARK, MMC1_CLK_MARK, SD3_CMD_MARK, MMC1_CMD_MARK, 684 MTS_N_MARK, SD3_DAT0_MARK, MMC1_D0_MARK, STM_N_MARK, 685 SD3_DAT1_MARK, MMC1_D1_MARK, MDATA_MARK, SD3_DAT2_MARK, 686 MMC1_D2_MARK, SDATA_MARK, SD3_DAT3_MARK, MMC1_D3_MARK, 687 SCKZ_MARK, SD3_CD_MARK, MMC1_D4_MARK, TS_SDAT1_MARK, 688 VSP_MARK, GLO_Q0_MARK, SIM0_RST_B_MARK, SD3_WP_MARK, 689 MMC1_D5_MARK, TS_SCK1_MARK, GLO_Q1_MARK, FMIN_C_MARK, 690 FMIN_E_MARK, FMIN_F_MARK, 691 MLB_CLK_MARK, IIC2_SCL_B_MARK, I2C2_SCL_B_MARK, 692 MLB_SIG_MARK, SCIFB1_RXD_D_MARK, RX1_C_MARK, IIC2_SDA_B_MARK, 693 I2C2_SDA_B_MARK, MLB_DAT_MARK, 694 SCIFB1_TXD_D_MARK, TX1_C_MARK, BPFCLK_C_MARK, 695 SSI_SCK0129_MARK, CAN_CLK_B_MARK, 696 MOUT0_MARK, 697 698 SSI_WS0129_MARK, CAN0_TX_B_MARK, MOUT1_MARK, 699 SSI_SDATA0_MARK, CAN0_RX_B_MARK, MOUT2_MARK, 700 SSI_SDATA1_MARK, CAN1_TX_B_MARK, MOUT5_MARK, 701 SSI_SDATA2_MARK, CAN1_RX_B_MARK, SSI_SCK1_MARK, MOUT6_MARK, 702 SSI_SCK34_MARK, STP_OPWM_0_MARK, SCIFB0_SCK_MARK, 703 MSIOF1_SCK_MARK, CAN_DEBUG_HW_TRIGGER_MARK, SSI_WS34_MARK, 704 STP_IVCXO27_0_MARK, SCIFB0_RXD_MARK, MSIOF1_SYNC_MARK, 705 CAN_STEP0_MARK, SSI_SDATA3_MARK, STP_ISCLK_0_MARK, 706 SCIFB0_TXD_MARK, MSIOF1_SS1_MARK, CAN_TXCLK_MARK, 707 SSI_SCK4_MARK, STP_ISD_0_MARK, SCIFB0_CTS_N_MARK, 708 MSIOF1_SS2_MARK, SSI_SCK5_C_MARK, CAN_DEBUGOUT0_MARK, 709 SSI_WS4_MARK, STP_ISEN_0_MARK, SCIFB0_RTS_N_MARK, 710 MSIOF1_TXD_MARK, SSI_WS5_C_MARK, CAN_DEBUGOUT1_MARK, 711 SSI_SDATA4_MARK, STP_ISSYNC_0_MARK, MSIOF1_RXD_MARK, 712 CAN_DEBUGOUT2_MARK, SSI_SCK5_MARK, SCIFB1_SCK_MARK, 713 IERX_B_MARK, DU2_EXHSYNC_DU2_HSYNC_MARK, QSTH_QHS_MARK, 714 CAN_DEBUGOUT3_MARK, SSI_WS5_MARK, SCIFB1_RXD_MARK, 715 IECLK_B_MARK, DU2_EXVSYNC_DU2_VSYNC_MARK, QSTB_QHE_MARK, 716 CAN_DEBUGOUT4_MARK, 717 718 SSI_SDATA5_MARK, SCIFB1_TXD_MARK, IETX_B_MARK, DU2_DR2_MARK, 719 LCDOUT2_MARK, CAN_DEBUGOUT5_MARK, SSI_SCK6_MARK, 720 SCIFB1_CTS_N_MARK, BPFCLK_D_MARK, 721 DU2_DR3_MARK, LCDOUT3_MARK, CAN_DEBUGOUT6_MARK, 722 BPFCLK_F_MARK, SSI_WS6_MARK, 723 SCIFB1_RTS_N_MARK, CAN0_TX_D_MARK, DU2_DR4_MARK, 724 LCDOUT4_MARK, CAN_DEBUGOUT7_MARK, SSI_SDATA6_MARK, 725 FMIN_D_MARK, DU2_DR5_MARK, LCDOUT5_MARK, 726 CAN_DEBUGOUT8_MARK, SSI_SCK78_MARK, STP_IVCXO27_1_MARK, 727 SCK1_MARK, SCIFA1_SCK_MARK, DU2_DR6_MARK, LCDOUT6_MARK, 728 CAN_DEBUGOUT9_MARK, SSI_WS78_MARK, STP_ISCLK_1_MARK, 729 SCIFB2_SCK_MARK, SCIFA2_CTS_N_MARK, DU2_DR7_MARK, 730 LCDOUT7_MARK, CAN_DEBUGOUT10_MARK, SSI_SDATA7_MARK, 731 STP_ISD_1_MARK, SCIFB2_RXD_MARK, SCIFA2_RTS_N_MARK, 732 TCLK2_MARK, QSTVA_QVS_MARK, CAN_DEBUGOUT11_MARK, 733 BPFCLK_E_MARK, SSI_SDATA7_B_MARK, 734 FMIN_G_MARK, SSI_SDATA8_MARK, 735 STP_ISEN_1_MARK, SCIFB2_TXD_MARK, CAN0_TX_C_MARK, 736 CAN_DEBUGOUT12_MARK, SSI_SDATA8_B_MARK, SSI_SDATA9_MARK, 737 STP_ISSYNC_1_MARK, SCIFB2_CTS_N_MARK, SSI_WS1_MARK, 738 SSI_SDATA5_C_MARK, CAN_DEBUGOUT13_MARK, AUDIO_CLKA_MARK, 739 SCIFB2_RTS_N_MARK, CAN_DEBUGOUT14_MARK, 740 741 AUDIO_CLKB_MARK, SCIF_CLK_MARK, CAN0_RX_D_MARK, 742 DVC_MUTE_MARK, CAN0_RX_C_MARK, CAN_DEBUGOUT15_MARK, 743 REMOCON_MARK, SCIFA0_SCK_MARK, HSCK1_MARK, SCK0_MARK, 744 MSIOF3_SS2_MARK, DU2_DG2_MARK, LCDOUT10_MARK, IIC1_SDA_C_MARK, 745 I2C1_SDA_C_MARK, SCIFA0_RXD_MARK, HRX1_MARK, RX0_MARK, 746 DU2_DR0_MARK, LCDOUT0_MARK, SCIFA0_TXD_MARK, HTX1_MARK, 747 TX0_MARK, DU2_DR1_MARK, LCDOUT1_MARK, SCIFA0_CTS_N_MARK, 748 HCTS1_N_MARK, CTS0_N_MARK, MSIOF3_SYNC_MARK, DU2_DG3_MARK, 749 LCDOUT11_MARK, PWM0_B_MARK, IIC1_SCL_C_MARK, I2C1_SCL_C_MARK, 750 SCIFA0_RTS_N_MARK, HRTS1_N_MARK, RTS0_N_MARK, 751 MSIOF3_SS1_MARK, DU2_DG0_MARK, LCDOUT8_MARK, PWM1_B_MARK, 752 SCIFA1_RXD_MARK, AD_DI_MARK, RX1_MARK, 753 DU2_EXODDF_DU2_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK, 754 SCIFA1_TXD_MARK, AD_DO_MARK, TX1_MARK, DU2_DG1_MARK, 755 LCDOUT9_MARK, SCIFA1_CTS_N_MARK, AD_CLK_MARK, 756 CTS1_N_MARK, MSIOF3_RXD_MARK, DU0_DOTCLKOUT_MARK, QCLK_MARK, 757 SCIFA1_RTS_N_MARK, AD_NCS_N_MARK, RTS1_N_MARK, 758 MSIOF3_TXD_MARK, DU1_DOTCLKOUT_MARK, QSTVB_QVE_MARK, 759 HRTS0_N_C_MARK, 760 761 SCIFA2_SCK_MARK, FMCLK_MARK, SCK2_MARK, MSIOF3_SCK_MARK, DU2_DG7_MARK, 762 LCDOUT15_MARK, SCIF_CLK_B_MARK, SCIFA2_RXD_MARK, FMIN_MARK, 763 TX2_MARK, DU2_DB0_MARK, LCDOUT16_MARK, IIC2_SCL_MARK, I2C2_SCL_MARK, 764 SCIFA2_TXD_MARK, BPFCLK_MARK, RX2_MARK, DU2_DB1_MARK, LCDOUT17_MARK, 765 IIC2_SDA_MARK, I2C2_SDA_MARK, HSCK0_MARK, TS_SDEN0_MARK, 766 DU2_DG4_MARK, LCDOUT12_MARK, HCTS0_N_C_MARK, HRX0_MARK, 767 DU2_DB2_MARK, LCDOUT18_MARK, HTX0_MARK, DU2_DB3_MARK, 768 LCDOUT19_MARK, HCTS0_N_MARK, SSI_SCK9_MARK, DU2_DB4_MARK, 769 LCDOUT20_MARK, HRTS0_N_MARK, SSI_WS9_MARK, DU2_DB5_MARK, 770 LCDOUT21_MARK, MSIOF0_SCK_MARK, TS_SDAT0_MARK, ADICLK_MARK, 771 DU2_DB6_MARK, LCDOUT22_MARK, MSIOF0_SYNC_MARK, TS_SCK0_MARK, 772 SSI_SCK2_MARK, ADIDATA_MARK, DU2_DB7_MARK, LCDOUT23_MARK, 773 HRX0_C_MARK, MSIOF0_SS1_MARK, ADICHS0_MARK, 774 DU2_DG5_MARK, LCDOUT13_MARK, MSIOF0_TXD_MARK, ADICHS1_MARK, 775 DU2_DG6_MARK, LCDOUT14_MARK, 776 777 MSIOF0_SS2_MARK, AUDIO_CLKOUT_MARK, ADICHS2_MARK, 778 DU2_DISP_MARK, QPOLA_MARK, HTX0_C_MARK, SCIFA2_TXD_B_MARK, 779 MSIOF0_RXD_MARK, TS_SPSYNC0_MARK, SSI_WS2_MARK, 780 ADICS_SAMP_MARK, DU2_CDE_MARK, QPOLB_MARK, SCIFA2_RXD_B_MARK, 781 USB1_PWEN_MARK, AUDIO_CLKOUT_D_MARK, USB1_OVC_MARK, 782 TCLK1_B_MARK, 783 784 IIC0_SCL_MARK, IIC0_SDA_MARK, I2C0_SCL_MARK, I2C0_SDA_MARK, 785 IIC3_SCL_MARK, IIC3_SDA_MARK, I2C3_SCL_MARK, I2C3_SDA_MARK, 786 PINMUX_MARK_END, 787 }; 788 789 static const u16 pinmux_data[] = { 790 PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */ 791 792 PINMUX_SINGLE(VI1_DATA7_VI1_B7), 793 PINMUX_SINGLE(USB0_PWEN), 794 PINMUX_SINGLE(USB0_OVC_VBUS), 795 PINMUX_SINGLE(USB2_PWEN), 796 PINMUX_SINGLE(USB2_OVC), 797 PINMUX_SINGLE(AVS1), 798 PINMUX_SINGLE(AVS2), 799 PINMUX_SINGLE(DU_DOTCLKIN0), 800 PINMUX_SINGLE(DU_DOTCLKIN2), 801 802 PINMUX_IPSR_GPSR(IP0_2_0, D0), 803 PINMUX_IPSR_MSEL(IP0_2_0, MSIOF3_SCK_B, SEL_SOF3_1), 804 PINMUX_IPSR_MSEL(IP0_2_0, VI3_DATA0, SEL_VI3_0), 805 PINMUX_IPSR_MSEL(IP0_2_0, VI0_G4, SEL_VI0_0), 806 PINMUX_IPSR_MSEL(IP0_2_0, VI0_G4_B, SEL_VI0_1), 807 PINMUX_IPSR_GPSR(IP0_5_3, D1), 808 PINMUX_IPSR_MSEL(IP0_5_3, MSIOF3_SYNC_B, SEL_SOF3_1), 809 PINMUX_IPSR_MSEL(IP0_5_3, VI3_DATA1, SEL_VI3_0), 810 PINMUX_IPSR_MSEL(IP0_5_3, VI0_G5, SEL_VI0_0), 811 PINMUX_IPSR_MSEL(IP0_5_3, VI0_G5_B, SEL_VI0_1), 812 PINMUX_IPSR_GPSR(IP0_8_6, D2), 813 PINMUX_IPSR_MSEL(IP0_8_6, MSIOF3_RXD_B, SEL_SOF3_1), 814 PINMUX_IPSR_MSEL(IP0_8_6, VI3_DATA2, SEL_VI3_0), 815 PINMUX_IPSR_MSEL(IP0_8_6, VI0_G6, SEL_VI0_0), 816 PINMUX_IPSR_MSEL(IP0_8_6, VI0_G6_B, SEL_VI0_1), 817 PINMUX_IPSR_GPSR(IP0_11_9, D3), 818 PINMUX_IPSR_MSEL(IP0_11_9, MSIOF3_TXD_B, SEL_SOF3_1), 819 PINMUX_IPSR_MSEL(IP0_11_9, VI3_DATA3, SEL_VI3_0), 820 PINMUX_IPSR_MSEL(IP0_11_9, VI0_G7, SEL_VI0_0), 821 PINMUX_IPSR_MSEL(IP0_11_9, VI0_G7_B, SEL_VI0_1), 822 PINMUX_IPSR_GPSR(IP0_15_12, D4), 823 PINMUX_IPSR_MSEL(IP0_15_12, SCIFB1_RXD_F, SEL_SCIFB1_5), 824 PINMUX_IPSR_MSEL(IP0_15_12, SCIFB0_RXD_C, SEL_SCIFB_2), 825 PINMUX_IPSR_MSEL(IP0_15_12, VI3_DATA4, SEL_VI3_0), 826 PINMUX_IPSR_MSEL(IP0_15_12, VI0_R0, SEL_VI0_0), 827 PINMUX_IPSR_MSEL(IP0_15_12, VI0_R0_B, SEL_VI0_1), 828 PINMUX_IPSR_MSEL(IP0_15_12, RX0_B, SEL_SCIF0_1), 829 PINMUX_IPSR_GPSR(IP0_19_16, D5), 830 PINMUX_IPSR_MSEL(IP0_19_16, SCIFB1_TXD_F, SEL_SCIFB1_5), 831 PINMUX_IPSR_MSEL(IP0_19_16, SCIFB0_TXD_C, SEL_SCIFB_2), 832 PINMUX_IPSR_MSEL(IP0_19_16, VI3_DATA5, SEL_VI3_0), 833 PINMUX_IPSR_MSEL(IP0_19_16, VI0_R1, SEL_VI0_0), 834 PINMUX_IPSR_MSEL(IP0_19_16, VI0_R1_B, SEL_VI0_1), 835 PINMUX_IPSR_MSEL(IP0_19_16, TX0_B, SEL_SCIF0_1), 836 PINMUX_IPSR_GPSR(IP0_22_20, D6), 837 PINMUX_IPSR_MSEL(IP0_22_20, IIC2_SCL_C, SEL_IIC2_2), 838 PINMUX_IPSR_MSEL(IP0_22_20, VI3_DATA6, SEL_VI3_0), 839 PINMUX_IPSR_MSEL(IP0_22_20, VI0_R2, SEL_VI0_0), 840 PINMUX_IPSR_MSEL(IP0_22_20, VI0_R2_B, SEL_VI0_1), 841 PINMUX_IPSR_MSEL(IP0_22_20, I2C2_SCL_C, SEL_I2C2_2), 842 PINMUX_IPSR_GPSR(IP0_26_23, D7), 843 PINMUX_IPSR_MSEL(IP0_26_23, AD_DI_B, SEL_ADI_1), 844 PINMUX_IPSR_MSEL(IP0_26_23, IIC2_SDA_C, SEL_IIC2_2), 845 PINMUX_IPSR_MSEL(IP0_26_23, VI3_DATA7, SEL_VI3_0), 846 PINMUX_IPSR_MSEL(IP0_26_23, VI0_R3, SEL_VI0_0), 847 PINMUX_IPSR_MSEL(IP0_26_23, VI0_R3_B, SEL_VI0_1), 848 PINMUX_IPSR_MSEL(IP0_26_23, I2C2_SDA_C, SEL_I2C2_2), 849 PINMUX_IPSR_MSEL(IP0_26_23, TCLK1, SEL_TMU1_0), 850 PINMUX_IPSR_GPSR(IP0_30_27, D8), 851 PINMUX_IPSR_MSEL(IP0_30_27, SCIFA1_SCK_C, SEL_SCIFA1_2), 852 PINMUX_IPSR_GPSR(IP0_30_27, AVB_TXD0), 853 PINMUX_IPSR_MSEL(IP0_30_27, VI0_G0, SEL_VI0_0), 854 PINMUX_IPSR_MSEL(IP0_30_27, VI0_G0_B, SEL_VI0_1), 855 PINMUX_IPSR_MSEL(IP0_30_27, VI2_DATA0_VI2_B0, SEL_VI2_0), 856 857 PINMUX_IPSR_GPSR(IP1_3_0, D9), 858 PINMUX_IPSR_MSEL(IP1_3_0, SCIFA1_RXD_C, SEL_SCIFA1_2), 859 PINMUX_IPSR_GPSR(IP1_3_0, AVB_TXD1), 860 PINMUX_IPSR_MSEL(IP1_3_0, VI0_G1, SEL_VI0_0), 861 PINMUX_IPSR_MSEL(IP1_3_0, VI0_G1_B, SEL_VI0_1), 862 PINMUX_IPSR_MSEL(IP1_3_0, VI2_DATA1_VI2_B1, SEL_VI2_0), 863 PINMUX_IPSR_GPSR(IP1_7_4, D10), 864 PINMUX_IPSR_MSEL(IP1_7_4, SCIFA1_TXD_C, SEL_SCIFA1_2), 865 PINMUX_IPSR_GPSR(IP1_7_4, AVB_TXD2), 866 PINMUX_IPSR_MSEL(IP1_7_4, VI0_G2, SEL_VI0_0), 867 PINMUX_IPSR_MSEL(IP1_7_4, VI0_G2_B, SEL_VI0_1), 868 PINMUX_IPSR_MSEL(IP1_7_4, VI2_DATA2_VI2_B2, SEL_VI2_0), 869 PINMUX_IPSR_GPSR(IP1_11_8, D11), 870 PINMUX_IPSR_MSEL(IP1_11_8, SCIFA1_CTS_N_C, SEL_SCIFA1_2), 871 PINMUX_IPSR_GPSR(IP1_11_8, AVB_TXD3), 872 PINMUX_IPSR_MSEL(IP1_11_8, VI0_G3, SEL_VI0_0), 873 PINMUX_IPSR_MSEL(IP1_11_8, VI0_G3_B, SEL_VI0_1), 874 PINMUX_IPSR_MSEL(IP1_11_8, VI2_DATA3_VI2_B3, SEL_VI2_0), 875 PINMUX_IPSR_GPSR(IP1_14_12, D12), 876 PINMUX_IPSR_MSEL(IP1_14_12, SCIFA1_RTS_N_C, SEL_SCIFA1_2), 877 PINMUX_IPSR_GPSR(IP1_14_12, AVB_TXD4), 878 PINMUX_IPSR_MSEL(IP1_14_12, VI0_HSYNC_N, SEL_VI0_0), 879 PINMUX_IPSR_MSEL(IP1_14_12, VI0_HSYNC_N_B, SEL_VI0_1), 880 PINMUX_IPSR_MSEL(IP1_14_12, VI2_DATA4_VI2_B4, SEL_VI2_0), 881 PINMUX_IPSR_GPSR(IP1_17_15, D13), 882 PINMUX_IPSR_GPSR(IP1_17_15, AVB_TXD5), 883 PINMUX_IPSR_MSEL(IP1_17_15, VI0_VSYNC_N, SEL_VI0_0), 884 PINMUX_IPSR_MSEL(IP1_17_15, VI0_VSYNC_N_B, SEL_VI0_1), 885 PINMUX_IPSR_MSEL(IP1_17_15, VI2_DATA5_VI2_B5, SEL_VI2_0), 886 PINMUX_IPSR_GPSR(IP1_21_18, D14), 887 PINMUX_IPSR_MSEL(IP1_21_18, SCIFB1_RXD_C, SEL_SCIFB1_2), 888 PINMUX_IPSR_GPSR(IP1_21_18, AVB_TXD6), 889 PINMUX_IPSR_MSEL(IP1_21_18, RX1_B, SEL_SCIF1_1), 890 PINMUX_IPSR_MSEL(IP1_21_18, VI0_CLKENB, SEL_VI0_0), 891 PINMUX_IPSR_MSEL(IP1_21_18, VI0_CLKENB_B, SEL_VI0_1), 892 PINMUX_IPSR_MSEL(IP1_21_18, VI2_DATA6_VI2_B6, SEL_VI2_0), 893 PINMUX_IPSR_GPSR(IP1_25_22, D15), 894 PINMUX_IPSR_MSEL(IP1_25_22, SCIFB1_TXD_C, SEL_SCIFB1_2), 895 PINMUX_IPSR_GPSR(IP1_25_22, AVB_TXD7), 896 PINMUX_IPSR_MSEL(IP1_25_22, TX1_B, SEL_SCIF1_1), 897 PINMUX_IPSR_MSEL(IP1_25_22, VI0_FIELD, SEL_VI0_0), 898 PINMUX_IPSR_MSEL(IP1_25_22, VI0_FIELD_B, SEL_VI0_1), 899 PINMUX_IPSR_MSEL(IP1_25_22, VI2_DATA7_VI2_B7, SEL_VI2_0), 900 PINMUX_IPSR_GPSR(IP1_27_26, A0), 901 PINMUX_IPSR_GPSR(IP1_27_26, PWM3), 902 PINMUX_IPSR_GPSR(IP1_29_28, A1), 903 PINMUX_IPSR_GPSR(IP1_29_28, PWM4), 904 905 PINMUX_IPSR_GPSR(IP2_2_0, A2), 906 PINMUX_IPSR_GPSR(IP2_2_0, PWM5), 907 PINMUX_IPSR_MSEL(IP2_2_0, MSIOF1_SS1_B, SEL_SOF1_1), 908 PINMUX_IPSR_GPSR(IP2_5_3, A3), 909 PINMUX_IPSR_GPSR(IP2_5_3, PWM6), 910 PINMUX_IPSR_MSEL(IP2_5_3, MSIOF1_SS2_B, SEL_SOF1_1), 911 PINMUX_IPSR_GPSR(IP2_8_6, A4), 912 PINMUX_IPSR_MSEL(IP2_8_6, MSIOF1_TXD_B, SEL_SOF1_1), 913 PINMUX_IPSR_GPSR(IP2_8_6, TPU0TO0), 914 PINMUX_IPSR_GPSR(IP2_11_9, A5), 915 PINMUX_IPSR_MSEL(IP2_11_9, SCIFA1_TXD_B, SEL_SCIFA1_1), 916 PINMUX_IPSR_GPSR(IP2_11_9, TPU0TO1), 917 PINMUX_IPSR_GPSR(IP2_14_12, A6), 918 PINMUX_IPSR_MSEL(IP2_14_12, SCIFA1_RTS_N_B, SEL_SCIFA1_1), 919 PINMUX_IPSR_GPSR(IP2_14_12, TPU0TO2), 920 PINMUX_IPSR_GPSR(IP2_17_15, A7), 921 PINMUX_IPSR_MSEL(IP2_17_15, SCIFA1_SCK_B, SEL_SCIFA1_1), 922 PINMUX_IPSR_GPSR(IP2_17_15, AUDIO_CLKOUT_B), 923 PINMUX_IPSR_GPSR(IP2_17_15, TPU0TO3), 924 PINMUX_IPSR_GPSR(IP2_21_18, A8), 925 PINMUX_IPSR_MSEL(IP2_21_18, SCIFA1_RXD_B, SEL_SCIFA1_1), 926 PINMUX_IPSR_MSEL(IP2_21_18, SSI_SCK5_B, SEL_SSI5_1), 927 PINMUX_IPSR_MSEL(IP2_21_18, VI0_R4, SEL_VI0_0), 928 PINMUX_IPSR_MSEL(IP2_21_18, VI0_R4_B, SEL_VI0_1), 929 PINMUX_IPSR_MSEL(IP2_21_18, SCIFB2_RXD_C, SEL_SCIFB2_2), 930 PINMUX_IPSR_MSEL(IP2_21_18, RX2_B, SEL_SCIF2_1), 931 PINMUX_IPSR_MSEL(IP2_21_18, VI2_DATA0_VI2_B0_B, SEL_VI2_1), 932 PINMUX_IPSR_GPSR(IP2_25_22, A9), 933 PINMUX_IPSR_MSEL(IP2_25_22, SCIFA1_CTS_N_B, SEL_SCIFA1_1), 934 PINMUX_IPSR_MSEL(IP2_25_22, SSI_WS5_B, SEL_SSI5_1), 935 PINMUX_IPSR_MSEL(IP2_25_22, VI0_R5, SEL_VI0_0), 936 PINMUX_IPSR_MSEL(IP2_25_22, VI0_R5_B, SEL_VI0_1), 937 PINMUX_IPSR_MSEL(IP2_25_22, SCIFB2_TXD_C, SEL_SCIFB2_2), 938 PINMUX_IPSR_MSEL(IP2_25_22, TX2_B, SEL_SCIF2_1), 939 PINMUX_IPSR_MSEL(IP2_25_22, VI2_DATA1_VI2_B1_B, SEL_VI2_1), 940 PINMUX_IPSR_GPSR(IP2_28_26, A10), 941 PINMUX_IPSR_MSEL(IP2_28_26, SSI_SDATA5_B, SEL_SSI5_1), 942 PINMUX_IPSR_GPSR(IP2_28_26, MSIOF2_SYNC), 943 PINMUX_IPSR_MSEL(IP2_28_26, VI0_R6, SEL_VI0_0), 944 PINMUX_IPSR_MSEL(IP2_28_26, VI0_R6_B, SEL_VI0_1), 945 PINMUX_IPSR_MSEL(IP2_28_26, VI2_DATA2_VI2_B2_B, SEL_VI2_1), 946 947 PINMUX_IPSR_GPSR(IP3_3_0, A11), 948 PINMUX_IPSR_MSEL(IP3_3_0, SCIFB2_CTS_N_B, SEL_SCIFB2_1), 949 PINMUX_IPSR_GPSR(IP3_3_0, MSIOF2_SCK), 950 PINMUX_IPSR_MSEL(IP3_3_0, VI1_R0, SEL_VI1_0), 951 PINMUX_IPSR_MSEL(IP3_3_0, VI1_R0_B, SEL_VI1_1), 952 PINMUX_IPSR_GPSR(IP3_3_0, VI2_G0), 953 PINMUX_IPSR_MSEL(IP3_3_0, VI2_DATA3_VI2_B3_B, SEL_VI2_1), 954 PINMUX_IPSR_GPSR(IP3_7_4, A12), 955 PINMUX_IPSR_MSEL(IP3_7_4, SCIFB2_RXD_B, SEL_SCIFB2_1), 956 PINMUX_IPSR_GPSR(IP3_7_4, MSIOF2_TXD), 957 PINMUX_IPSR_MSEL(IP3_7_4, VI1_R1, SEL_VI1_0), 958 PINMUX_IPSR_MSEL(IP3_7_4, VI1_R1_B, SEL_VI1_1), 959 PINMUX_IPSR_GPSR(IP3_7_4, VI2_G1), 960 PINMUX_IPSR_MSEL(IP3_7_4, VI2_DATA4_VI2_B4_B, SEL_VI2_1), 961 PINMUX_IPSR_GPSR(IP3_11_8, A13), 962 PINMUX_IPSR_MSEL(IP3_11_8, SCIFB2_RTS_N_B, SEL_SCIFB2_1), 963 PINMUX_IPSR_GPSR(IP3_11_8, EX_WAIT2), 964 PINMUX_IPSR_GPSR(IP3_11_8, MSIOF2_RXD), 965 PINMUX_IPSR_MSEL(IP3_11_8, VI1_R2, SEL_VI1_0), 966 PINMUX_IPSR_MSEL(IP3_11_8, VI1_R2_B, SEL_VI1_1), 967 PINMUX_IPSR_GPSR(IP3_11_8, VI2_G2), 968 PINMUX_IPSR_MSEL(IP3_11_8, VI2_DATA5_VI2_B5_B, SEL_VI2_1), 969 PINMUX_IPSR_GPSR(IP3_14_12, A14), 970 PINMUX_IPSR_MSEL(IP3_14_12, SCIFB2_TXD_B, SEL_SCIFB2_1), 971 PINMUX_IPSR_GPSR(IP3_14_12, ATACS11_N), 972 PINMUX_IPSR_GPSR(IP3_14_12, MSIOF2_SS1), 973 PINMUX_IPSR_GPSR(IP3_17_15, A15), 974 PINMUX_IPSR_MSEL(IP3_17_15, SCIFB2_SCK_B, SEL_SCIFB2_1), 975 PINMUX_IPSR_GPSR(IP3_17_15, ATARD1_N), 976 PINMUX_IPSR_GPSR(IP3_17_15, MSIOF2_SS2), 977 PINMUX_IPSR_GPSR(IP3_19_18, A16), 978 PINMUX_IPSR_GPSR(IP3_19_18, ATAWR1_N), 979 PINMUX_IPSR_GPSR(IP3_22_20, A17), 980 PINMUX_IPSR_MSEL(IP3_22_20, AD_DO_B, SEL_ADI_1), 981 PINMUX_IPSR_GPSR(IP3_22_20, ATADIR1_N), 982 PINMUX_IPSR_GPSR(IP3_25_23, A18), 983 PINMUX_IPSR_MSEL(IP3_25_23, AD_CLK_B, SEL_ADI_1), 984 PINMUX_IPSR_GPSR(IP3_25_23, ATAG1_N), 985 PINMUX_IPSR_GPSR(IP3_28_26, A19), 986 PINMUX_IPSR_MSEL(IP3_28_26, AD_NCS_N_B, SEL_ADI_1), 987 PINMUX_IPSR_GPSR(IP3_28_26, ATACS01_N), 988 PINMUX_IPSR_MSEL(IP3_28_26, EX_WAIT0_B, SEL_LBS_1), 989 PINMUX_IPSR_GPSR(IP3_31_29, A20), 990 PINMUX_IPSR_GPSR(IP3_31_29, SPCLK), 991 PINMUX_IPSR_MSEL(IP3_31_29, VI1_R3, SEL_VI1_0), 992 PINMUX_IPSR_MSEL(IP3_31_29, VI1_R3_B, SEL_VI1_1), 993 PINMUX_IPSR_GPSR(IP3_31_29, VI2_G4), 994 995 PINMUX_IPSR_GPSR(IP4_2_0, A21), 996 PINMUX_IPSR_GPSR(IP4_2_0, MOSI_IO0), 997 PINMUX_IPSR_MSEL(IP4_2_0, VI1_R4, SEL_VI1_0), 998 PINMUX_IPSR_MSEL(IP4_2_0, VI1_R4_B, SEL_VI1_1), 999 PINMUX_IPSR_GPSR(IP4_2_0, VI2_G5), 1000 PINMUX_IPSR_GPSR(IP4_5_3, A22), 1001 PINMUX_IPSR_GPSR(IP4_5_3, MISO_IO1), 1002 PINMUX_IPSR_MSEL(IP4_5_3, VI1_R5, SEL_VI1_0), 1003 PINMUX_IPSR_MSEL(IP4_5_3, VI1_R5_B, SEL_VI1_1), 1004 PINMUX_IPSR_GPSR(IP4_5_3, VI2_G6), 1005 PINMUX_IPSR_GPSR(IP4_8_6, A23), 1006 PINMUX_IPSR_GPSR(IP4_8_6, IO2), 1007 PINMUX_IPSR_MSEL(IP4_8_6, VI1_G7, SEL_VI1_0), 1008 PINMUX_IPSR_MSEL(IP4_8_6, VI1_G7_B, SEL_VI1_1), 1009 PINMUX_IPSR_GPSR(IP4_8_6, VI2_G7), 1010 PINMUX_IPSR_GPSR(IP4_11_9, A24), 1011 PINMUX_IPSR_GPSR(IP4_11_9, IO3), 1012 PINMUX_IPSR_MSEL(IP4_11_9, VI1_R7, SEL_VI1_0), 1013 PINMUX_IPSR_MSEL(IP4_11_9, VI1_R7_B, SEL_VI1_1), 1014 PINMUX_IPSR_MSEL(IP4_11_9, VI2_CLKENB, SEL_VI2_0), 1015 PINMUX_IPSR_MSEL(IP4_11_9, VI2_CLKENB_B, SEL_VI2_1), 1016 PINMUX_IPSR_GPSR(IP4_14_12, A25), 1017 PINMUX_IPSR_GPSR(IP4_14_12, SSL), 1018 PINMUX_IPSR_MSEL(IP4_14_12, VI1_G6, SEL_VI1_0), 1019 PINMUX_IPSR_MSEL(IP4_14_12, VI1_G6_B, SEL_VI1_1), 1020 PINMUX_IPSR_MSEL(IP4_14_12, VI2_FIELD, SEL_VI2_0), 1021 PINMUX_IPSR_MSEL(IP4_14_12, VI2_FIELD_B, SEL_VI2_1), 1022 PINMUX_IPSR_GPSR(IP4_17_15, CS0_N), 1023 PINMUX_IPSR_MSEL(IP4_17_15, VI1_R6, SEL_VI1_0), 1024 PINMUX_IPSR_MSEL(IP4_17_15, VI1_R6_B, SEL_VI1_1), 1025 PINMUX_IPSR_GPSR(IP4_17_15, VI2_G3), 1026 PINMUX_IPSR_MSEL(IP4_17_15, MSIOF0_SS2_B, SEL_SOF0_1), 1027 PINMUX_IPSR_GPSR(IP4_20_18, CS1_N_A26), 1028 PINMUX_IPSR_GPSR(IP4_20_18, SPEEDIN), 1029 PINMUX_IPSR_MSEL(IP4_20_18, VI0_R7, SEL_VI0_0), 1030 PINMUX_IPSR_MSEL(IP4_20_18, VI0_R7_B, SEL_VI0_1), 1031 PINMUX_IPSR_MSEL(IP4_20_18, VI2_CLK, SEL_VI2_0), 1032 PINMUX_IPSR_MSEL(IP4_20_18, VI2_CLK_B, SEL_VI2_1), 1033 PINMUX_IPSR_GPSR(IP4_23_21, EX_CS0_N), 1034 PINMUX_IPSR_MSEL(IP4_23_21, HRX1_B, SEL_HSCIF1_1), 1035 PINMUX_IPSR_MSEL(IP4_23_21, VI1_G5, SEL_VI1_0), 1036 PINMUX_IPSR_MSEL(IP4_23_21, VI1_G5_B, SEL_VI1_1), 1037 PINMUX_IPSR_GPSR(IP4_23_21, VI2_R0), 1038 PINMUX_IPSR_MSEL(IP4_23_21, HTX0_B, SEL_HSCIF0_1), 1039 PINMUX_IPSR_MSEL(IP4_23_21, MSIOF0_SS1_B, SEL_SOF0_1), 1040 PINMUX_IPSR_GPSR(IP4_26_24, EX_CS1_N), 1041 PINMUX_IPSR_GPSR(IP4_26_24, GPS_CLK), 1042 PINMUX_IPSR_MSEL(IP4_26_24, HCTS1_N_B, SEL_HSCIF1_1), 1043 PINMUX_IPSR_MSEL(IP4_26_24, VI1_FIELD, SEL_VI1_0), 1044 PINMUX_IPSR_MSEL(IP4_26_24, VI1_FIELD_B, SEL_VI1_1), 1045 PINMUX_IPSR_GPSR(IP4_26_24, VI2_R1), 1046 PINMUX_IPSR_GPSR(IP4_29_27, EX_CS2_N), 1047 PINMUX_IPSR_GPSR(IP4_29_27, GPS_SIGN), 1048 PINMUX_IPSR_MSEL(IP4_29_27, HRTS1_N_B, SEL_HSCIF1_1), 1049 PINMUX_IPSR_GPSR(IP4_29_27, VI3_CLKENB), 1050 PINMUX_IPSR_MSEL(IP4_29_27, VI1_G0, SEL_VI1_0), 1051 PINMUX_IPSR_MSEL(IP4_29_27, VI1_G0_B, SEL_VI1_1), 1052 PINMUX_IPSR_GPSR(IP4_29_27, VI2_R2), 1053 1054 PINMUX_IPSR_GPSR(IP5_2_0, EX_CS3_N), 1055 PINMUX_IPSR_GPSR(IP5_2_0, GPS_MAG), 1056 PINMUX_IPSR_GPSR(IP5_2_0, VI3_FIELD), 1057 PINMUX_IPSR_MSEL(IP5_2_0, VI1_G1, SEL_VI1_0), 1058 PINMUX_IPSR_MSEL(IP5_2_0, VI1_G1_B, SEL_VI1_1), 1059 PINMUX_IPSR_GPSR(IP5_2_0, VI2_R3), 1060 PINMUX_IPSR_GPSR(IP5_5_3, EX_CS4_N), 1061 PINMUX_IPSR_MSEL(IP5_5_3, MSIOF1_SCK_B, SEL_SOF1_1), 1062 PINMUX_IPSR_GPSR(IP5_5_3, VI3_HSYNC_N), 1063 PINMUX_IPSR_MSEL(IP5_5_3, VI2_HSYNC_N, SEL_VI2_0), 1064 PINMUX_IPSR_MSEL(IP5_5_3, IIC1_SCL, SEL_IIC1_0), 1065 PINMUX_IPSR_MSEL(IP5_5_3, VI2_HSYNC_N_B, SEL_VI2_1), 1066 PINMUX_IPSR_GPSR(IP5_5_3, INTC_EN0_N), 1067 PINMUX_IPSR_MSEL(IP5_5_3, I2C1_SCL, SEL_I2C1_0), 1068 PINMUX_IPSR_GPSR(IP5_9_6, EX_CS5_N), 1069 PINMUX_IPSR_MSEL(IP5_9_6, CAN0_RX, SEL_CAN0_0), 1070 PINMUX_IPSR_MSEL(IP5_9_6, MSIOF1_RXD_B, SEL_SOF1_1), 1071 PINMUX_IPSR_GPSR(IP5_9_6, VI3_VSYNC_N), 1072 PINMUX_IPSR_MSEL(IP5_9_6, VI1_G2, SEL_VI1_0), 1073 PINMUX_IPSR_MSEL(IP5_9_6, VI1_G2_B, SEL_VI1_1), 1074 PINMUX_IPSR_GPSR(IP5_9_6, VI2_R4), 1075 PINMUX_IPSR_MSEL(IP5_9_6, IIC1_SDA, SEL_IIC1_0), 1076 PINMUX_IPSR_GPSR(IP5_9_6, INTC_EN1_N), 1077 PINMUX_IPSR_MSEL(IP5_9_6, I2C1_SDA, SEL_I2C1_0), 1078 PINMUX_IPSR_GPSR(IP5_12_10, BS_N), 1079 PINMUX_IPSR_MSEL(IP5_12_10, IETX, SEL_IEB_0), 1080 PINMUX_IPSR_MSEL(IP5_12_10, HTX1_B, SEL_HSCIF1_1), 1081 PINMUX_IPSR_MSEL(IP5_12_10, CAN1_TX, SEL_CAN1_0), 1082 PINMUX_IPSR_GPSR(IP5_12_10, DRACK0), 1083 PINMUX_IPSR_MSEL(IP5_12_10, IETX_C, SEL_IEB_2), 1084 PINMUX_IPSR_GPSR(IP5_14_13, RD_N), 1085 PINMUX_IPSR_MSEL(IP5_14_13, CAN0_TX, SEL_CAN0_0), 1086 PINMUX_IPSR_MSEL(IP5_14_13, SCIFA0_SCK_B, SEL_SCFA_1), 1087 PINMUX_IPSR_GPSR(IP5_17_15, RD_WR_N), 1088 PINMUX_IPSR_MSEL(IP5_17_15, VI1_G3, SEL_VI1_0), 1089 PINMUX_IPSR_MSEL(IP5_17_15, VI1_G3_B, SEL_VI1_1), 1090 PINMUX_IPSR_GPSR(IP5_17_15, VI2_R5), 1091 PINMUX_IPSR_MSEL(IP5_17_15, SCIFA0_RXD_B, SEL_SCFA_1), 1092 PINMUX_IPSR_GPSR(IP5_17_15, INTC_IRQ4_N), 1093 PINMUX_IPSR_GPSR(IP5_20_18, WE0_N), 1094 PINMUX_IPSR_MSEL(IP5_20_18, IECLK, SEL_IEB_0), 1095 PINMUX_IPSR_MSEL(IP5_20_18, CAN_CLK, SEL_CANCLK_0), 1096 PINMUX_IPSR_MSEL(IP5_20_18, VI2_VSYNC_N, SEL_VI2_0), 1097 PINMUX_IPSR_MSEL(IP5_20_18, SCIFA0_TXD_B, SEL_SCFA_1), 1098 PINMUX_IPSR_MSEL(IP5_20_18, VI2_VSYNC_N_B, SEL_VI2_1), 1099 PINMUX_IPSR_GPSR(IP5_23_21, WE1_N), 1100 PINMUX_IPSR_MSEL(IP5_23_21, IERX, SEL_IEB_0), 1101 PINMUX_IPSR_MSEL(IP5_23_21, CAN1_RX, SEL_CAN1_0), 1102 PINMUX_IPSR_MSEL(IP5_23_21, VI1_G4, SEL_VI1_0), 1103 PINMUX_IPSR_MSEL(IP5_23_21, VI1_G4_B, SEL_VI1_1), 1104 PINMUX_IPSR_GPSR(IP5_23_21, VI2_R6), 1105 PINMUX_IPSR_MSEL(IP5_23_21, SCIFA0_CTS_N_B, SEL_SCFA_1), 1106 PINMUX_IPSR_MSEL(IP5_23_21, IERX_C, SEL_IEB_2), 1107 PINMUX_IPSR_MSEL(IP5_26_24, EX_WAIT0, SEL_LBS_0), 1108 PINMUX_IPSR_GPSR(IP5_26_24, IRQ3), 1109 PINMUX_IPSR_GPSR(IP5_26_24, INTC_IRQ3_N), 1110 PINMUX_IPSR_MSEL(IP5_26_24, VI3_CLK, SEL_VI3_0), 1111 PINMUX_IPSR_MSEL(IP5_26_24, SCIFA0_RTS_N_B, SEL_SCFA_1), 1112 PINMUX_IPSR_MSEL(IP5_26_24, HRX0_B, SEL_HSCIF0_1), 1113 PINMUX_IPSR_MSEL(IP5_26_24, MSIOF0_SCK_B, SEL_SOF0_1), 1114 PINMUX_IPSR_GPSR(IP5_29_27, DREQ0_N), 1115 PINMUX_IPSR_MSEL(IP5_29_27, VI1_HSYNC_N, SEL_VI1_0), 1116 PINMUX_IPSR_MSEL(IP5_29_27, VI1_HSYNC_N_B, SEL_VI1_1), 1117 PINMUX_IPSR_GPSR(IP5_29_27, VI2_R7), 1118 PINMUX_IPSR_MSEL(IP5_29_27, SSI_SCK78_C, SEL_SSI7_2), 1119 PINMUX_IPSR_MSEL(IP5_29_27, SSI_WS78_B, SEL_SSI7_1), 1120 1121 PINMUX_IPSR_GPSR(IP6_2_0, DACK0), 1122 PINMUX_IPSR_GPSR(IP6_2_0, IRQ0), 1123 PINMUX_IPSR_GPSR(IP6_2_0, INTC_IRQ0_N), 1124 PINMUX_IPSR_MSEL(IP6_2_0, SSI_SCK6_B, SEL_SSI6_1), 1125 PINMUX_IPSR_MSEL(IP6_2_0, VI1_VSYNC_N, SEL_VI1_0), 1126 PINMUX_IPSR_MSEL(IP6_2_0, VI1_VSYNC_N_B, SEL_VI1_1), 1127 PINMUX_IPSR_MSEL(IP6_2_0, SSI_WS78_C, SEL_SSI7_2), 1128 PINMUX_IPSR_GPSR(IP6_5_3, DREQ1_N), 1129 PINMUX_IPSR_MSEL(IP6_5_3, VI1_CLKENB, SEL_VI1_0), 1130 PINMUX_IPSR_MSEL(IP6_5_3, VI1_CLKENB_B, SEL_VI1_1), 1131 PINMUX_IPSR_MSEL(IP6_5_3, SSI_SDATA7_C, SEL_SSI7_2), 1132 PINMUX_IPSR_MSEL(IP6_5_3, SSI_SCK78_B, SEL_SSI7_1), 1133 PINMUX_IPSR_GPSR(IP6_8_6, DACK1), 1134 PINMUX_IPSR_GPSR(IP6_8_6, IRQ1), 1135 PINMUX_IPSR_GPSR(IP6_8_6, INTC_IRQ1_N), 1136 PINMUX_IPSR_MSEL(IP6_8_6, SSI_WS6_B, SEL_SSI6_1), 1137 PINMUX_IPSR_MSEL(IP6_8_6, SSI_SDATA8_C, SEL_SSI8_2), 1138 PINMUX_IPSR_GPSR(IP6_10_9, DREQ2_N), 1139 PINMUX_IPSR_MSEL(IP6_10_9, HSCK1_B, SEL_HSCIF1_1), 1140 PINMUX_IPSR_MSEL(IP6_10_9, HCTS0_N_B, SEL_HSCIF0_1), 1141 PINMUX_IPSR_MSEL(IP6_10_9, MSIOF0_TXD_B, SEL_SOF0_1), 1142 PINMUX_IPSR_GPSR(IP6_13_11, DACK2), 1143 PINMUX_IPSR_GPSR(IP6_13_11, IRQ2), 1144 PINMUX_IPSR_GPSR(IP6_13_11, INTC_IRQ2_N), 1145 PINMUX_IPSR_MSEL(IP6_13_11, SSI_SDATA6_B, SEL_SSI6_1), 1146 PINMUX_IPSR_MSEL(IP6_13_11, HRTS0_N_B, SEL_HSCIF0_1), 1147 PINMUX_IPSR_MSEL(IP6_13_11, MSIOF0_RXD_B, SEL_SOF0_1), 1148 PINMUX_IPSR_GPSR(IP6_16_14, ETH_CRS_DV), 1149 PINMUX_IPSR_MSEL(IP6_16_14, STP_ISCLK_0_B, SEL_SSP_1), 1150 PINMUX_IPSR_MSEL(IP6_16_14, TS_SDEN0_D, SEL_TSIF0_3), 1151 PINMUX_IPSR_MSEL(IP6_16_14, GLO_Q0_C, SEL_GPS_2), 1152 PINMUX_IPSR_MSEL(IP6_16_14, IIC2_SCL_E, SEL_IIC2_4), 1153 PINMUX_IPSR_MSEL(IP6_16_14, I2C2_SCL_E, SEL_I2C2_4), 1154 PINMUX_IPSR_GPSR(IP6_19_17, ETH_RX_ER), 1155 PINMUX_IPSR_MSEL(IP6_19_17, STP_ISD_0_B, SEL_SSP_1), 1156 PINMUX_IPSR_MSEL(IP6_19_17, TS_SPSYNC0_D, SEL_TSIF0_3), 1157 PINMUX_IPSR_MSEL(IP6_19_17, GLO_Q1_C, SEL_GPS_2), 1158 PINMUX_IPSR_MSEL(IP6_19_17, IIC2_SDA_E, SEL_IIC2_4), 1159 PINMUX_IPSR_MSEL(IP6_19_17, I2C2_SDA_E, SEL_I2C2_4), 1160 PINMUX_IPSR_GPSR(IP6_22_20, ETH_RXD0), 1161 PINMUX_IPSR_MSEL(IP6_22_20, STP_ISEN_0_B, SEL_SSP_1), 1162 PINMUX_IPSR_MSEL(IP6_22_20, TS_SDAT0_D, SEL_TSIF0_3), 1163 PINMUX_IPSR_MSEL(IP6_22_20, GLO_I0_C, SEL_GPS_2), 1164 PINMUX_IPSR_MSEL(IP6_22_20, SCIFB1_SCK_G, SEL_SCIFB1_6), 1165 PINMUX_IPSR_MSEL(IP6_22_20, SCK1_E, SEL_SCIF1_4), 1166 PINMUX_IPSR_GPSR(IP6_25_23, ETH_RXD1), 1167 PINMUX_IPSR_MSEL(IP6_25_23, HRX0_E, SEL_HSCIF0_4), 1168 PINMUX_IPSR_MSEL(IP6_25_23, STP_ISSYNC_0_B, SEL_SSP_1), 1169 PINMUX_IPSR_MSEL(IP6_25_23, TS_SCK0_D, SEL_TSIF0_3), 1170 PINMUX_IPSR_MSEL(IP6_25_23, GLO_I1_C, SEL_GPS_2), 1171 PINMUX_IPSR_MSEL(IP6_25_23, SCIFB1_RXD_G, SEL_SCIFB1_6), 1172 PINMUX_IPSR_MSEL(IP6_25_23, RX1_E, SEL_SCIF1_4), 1173 PINMUX_IPSR_GPSR(IP6_28_26, ETH_LINK), 1174 PINMUX_IPSR_MSEL(IP6_28_26, HTX0_E, SEL_HSCIF0_4), 1175 PINMUX_IPSR_MSEL(IP6_28_26, STP_IVCXO27_0_B, SEL_SSP_1), 1176 PINMUX_IPSR_MSEL(IP6_28_26, SCIFB1_TXD_G, SEL_SCIFB1_6), 1177 PINMUX_IPSR_MSEL(IP6_28_26, TX1_E, SEL_SCIF1_4), 1178 PINMUX_IPSR_GPSR(IP6_31_29, ETH_REF_CLK), 1179 PINMUX_IPSR_MSEL(IP6_31_29, HCTS0_N_E, SEL_HSCIF0_4), 1180 PINMUX_IPSR_MSEL(IP6_31_29, STP_IVCXO27_1_B, SEL_SSP_1), 1181 PINMUX_IPSR_MSEL(IP6_31_29, HRX0_F, SEL_HSCIF0_5), 1182 1183 PINMUX_IPSR_GPSR(IP7_2_0, ETH_MDIO), 1184 PINMUX_IPSR_MSEL(IP7_2_0, HRTS0_N_E, SEL_HSCIF0_4), 1185 PINMUX_IPSR_MSEL(IP7_2_0, SIM0_D_C, SEL_SIM_2), 1186 PINMUX_IPSR_MSEL(IP7_2_0, HCTS0_N_F, SEL_HSCIF0_5), 1187 PINMUX_IPSR_GPSR(IP7_5_3, ETH_TXD1), 1188 PINMUX_IPSR_MSEL(IP7_5_3, HTX0_F, SEL_HSCIF0_5), 1189 PINMUX_IPSR_MSEL(IP7_5_3, BPFCLK_G, SEL_FM_6), 1190 PINMUX_IPSR_GPSR(IP7_7_6, ETH_TX_EN), 1191 PINMUX_IPSR_MSEL(IP7_7_6, SIM0_CLK_C, SEL_SIM_2), 1192 PINMUX_IPSR_MSEL(IP7_7_6, HRTS0_N_F, SEL_HSCIF0_5), 1193 PINMUX_IPSR_GPSR(IP7_9_8, ETH_MAGIC), 1194 PINMUX_IPSR_MSEL(IP7_9_8, SIM0_RST_C, SEL_SIM_2), 1195 PINMUX_IPSR_GPSR(IP7_12_10, ETH_TXD0), 1196 PINMUX_IPSR_MSEL(IP7_12_10, STP_ISCLK_1_B, SEL_SSP_1), 1197 PINMUX_IPSR_MSEL(IP7_12_10, TS_SDEN1_C, SEL_TSIF1_2), 1198 PINMUX_IPSR_MSEL(IP7_12_10, GLO_SCLK_C, SEL_GPS_2), 1199 PINMUX_IPSR_GPSR(IP7_15_13, ETH_MDC), 1200 PINMUX_IPSR_MSEL(IP7_15_13, STP_ISD_1_B, SEL_SSP_1), 1201 PINMUX_IPSR_MSEL(IP7_15_13, TS_SPSYNC1_C, SEL_TSIF1_2), 1202 PINMUX_IPSR_MSEL(IP7_15_13, GLO_SDATA_C, SEL_GPS_2), 1203 PINMUX_IPSR_GPSR(IP7_18_16, PWM0), 1204 PINMUX_IPSR_MSEL(IP7_18_16, SCIFA2_SCK_C, SEL_SCIFA2_2), 1205 PINMUX_IPSR_MSEL(IP7_18_16, STP_ISEN_1_B, SEL_SSP_1), 1206 PINMUX_IPSR_MSEL(IP7_18_16, TS_SDAT1_C, SEL_TSIF1_2), 1207 PINMUX_IPSR_MSEL(IP7_18_16, GLO_SS_C, SEL_GPS_2), 1208 PINMUX_IPSR_GPSR(IP7_21_19, PWM1), 1209 PINMUX_IPSR_MSEL(IP7_21_19, SCIFA2_TXD_C, SEL_SCIFA2_2), 1210 PINMUX_IPSR_MSEL(IP7_21_19, STP_ISSYNC_1_B, SEL_SSP_1), 1211 PINMUX_IPSR_MSEL(IP7_21_19, TS_SCK1_C, SEL_TSIF1_2), 1212 PINMUX_IPSR_MSEL(IP7_21_19, GLO_RFON_C, SEL_GPS_2), 1213 PINMUX_IPSR_GPSR(IP7_21_19, PCMOE_N), 1214 PINMUX_IPSR_GPSR(IP7_24_22, PWM2), 1215 PINMUX_IPSR_GPSR(IP7_24_22, PWMFSW0), 1216 PINMUX_IPSR_MSEL(IP7_24_22, SCIFA2_RXD_C, SEL_SCIFA2_2), 1217 PINMUX_IPSR_GPSR(IP7_24_22, PCMWE_N), 1218 PINMUX_IPSR_MSEL(IP7_24_22, IECLK_C, SEL_IEB_2), 1219 PINMUX_IPSR_GPSR(IP7_26_25, DU_DOTCLKIN1), 1220 PINMUX_IPSR_GPSR(IP7_26_25, AUDIO_CLKC), 1221 PINMUX_IPSR_GPSR(IP7_26_25, AUDIO_CLKOUT_C), 1222 PINMUX_IPSR_MSEL(IP7_28_27, VI0_CLK, SEL_VI0_0), 1223 PINMUX_IPSR_GPSR(IP7_28_27, ATACS00_N), 1224 PINMUX_IPSR_GPSR(IP7_28_27, AVB_RXD1), 1225 PINMUX_IPSR_MSEL(IP7_30_29, VI0_DATA0_VI0_B0, SEL_VI0_0), 1226 PINMUX_IPSR_GPSR(IP7_30_29, ATACS10_N), 1227 PINMUX_IPSR_GPSR(IP7_30_29, AVB_RXD2), 1228 1229 PINMUX_IPSR_MSEL(IP8_1_0, VI0_DATA1_VI0_B1, SEL_VI0_0), 1230 PINMUX_IPSR_GPSR(IP8_1_0, ATARD0_N), 1231 PINMUX_IPSR_GPSR(IP8_1_0, AVB_RXD3), 1232 PINMUX_IPSR_MSEL(IP8_3_2, VI0_DATA2_VI0_B2, SEL_VI0_0), 1233 PINMUX_IPSR_GPSR(IP8_3_2, ATAWR0_N), 1234 PINMUX_IPSR_GPSR(IP8_3_2, AVB_RXD4), 1235 PINMUX_IPSR_MSEL(IP8_5_4, VI0_DATA3_VI0_B3, SEL_VI0_0), 1236 PINMUX_IPSR_GPSR(IP8_5_4, ATADIR0_N), 1237 PINMUX_IPSR_GPSR(IP8_5_4, AVB_RXD5), 1238 PINMUX_IPSR_MSEL(IP8_7_6, VI0_DATA4_VI0_B4, SEL_VI0_0), 1239 PINMUX_IPSR_GPSR(IP8_7_6, ATAG0_N), 1240 PINMUX_IPSR_GPSR(IP8_7_6, AVB_RXD6), 1241 PINMUX_IPSR_MSEL(IP8_9_8, VI0_DATA5_VI0_B5, SEL_VI0_0), 1242 PINMUX_IPSR_GPSR(IP8_9_8, EX_WAIT1), 1243 PINMUX_IPSR_GPSR(IP8_9_8, AVB_RXD7), 1244 PINMUX_IPSR_MSEL(IP8_11_10, VI0_DATA6_VI0_B6, SEL_VI0_0), 1245 PINMUX_IPSR_GPSR(IP8_11_10, AVB_RX_ER), 1246 PINMUX_IPSR_MSEL(IP8_13_12, VI0_DATA7_VI0_B7, SEL_VI0_0), 1247 PINMUX_IPSR_GPSR(IP8_13_12, AVB_RX_CLK), 1248 PINMUX_IPSR_MSEL(IP8_15_14, VI1_CLK, SEL_VI1_0), 1249 PINMUX_IPSR_GPSR(IP8_15_14, AVB_RX_DV), 1250 PINMUX_IPSR_MSEL(IP8_17_16, VI1_DATA0_VI1_B0, SEL_VI1_0), 1251 PINMUX_IPSR_MSEL(IP8_17_16, SCIFA1_SCK_D, SEL_SCIFA1_3), 1252 PINMUX_IPSR_GPSR(IP8_17_16, AVB_CRS), 1253 PINMUX_IPSR_MSEL(IP8_19_18, VI1_DATA1_VI1_B1, SEL_VI1_0), 1254 PINMUX_IPSR_MSEL(IP8_19_18, SCIFA1_RXD_D, SEL_SCIFA1_3), 1255 PINMUX_IPSR_GPSR(IP8_19_18, AVB_MDC), 1256 PINMUX_IPSR_MSEL(IP8_21_20, VI1_DATA2_VI1_B2, SEL_VI1_0), 1257 PINMUX_IPSR_MSEL(IP8_21_20, SCIFA1_TXD_D, SEL_SCIFA1_3), 1258 PINMUX_IPSR_GPSR(IP8_21_20, AVB_MDIO), 1259 PINMUX_IPSR_MSEL(IP8_23_22, VI1_DATA3_VI1_B3, SEL_VI1_0), 1260 PINMUX_IPSR_MSEL(IP8_23_22, SCIFA1_CTS_N_D, SEL_SCIFA1_3), 1261 PINMUX_IPSR_GPSR(IP8_23_22, AVB_GTX_CLK), 1262 PINMUX_IPSR_MSEL(IP8_25_24, VI1_DATA4_VI1_B4, SEL_VI1_0), 1263 PINMUX_IPSR_MSEL(IP8_25_24, SCIFA1_RTS_N_D, SEL_SCIFA1_3), 1264 PINMUX_IPSR_GPSR(IP8_25_24, AVB_MAGIC), 1265 PINMUX_IPSR_MSEL(IP8_26, VI1_DATA5_VI1_B5, SEL_VI1_0), 1266 PINMUX_IPSR_GPSR(IP8_26, AVB_PHY_INT), 1267 PINMUX_IPSR_MSEL(IP8_27, VI1_DATA6_VI1_B6, SEL_VI1_0), 1268 PINMUX_IPSR_GPSR(IP8_27, AVB_GTXREFCLK), 1269 PINMUX_IPSR_GPSR(IP8_28, SD0_CLK), 1270 PINMUX_IPSR_MSEL(IP8_28, VI1_DATA0_VI1_B0_B, SEL_VI1_1), 1271 PINMUX_IPSR_GPSR(IP8_30_29, SD0_CMD), 1272 PINMUX_IPSR_MSEL(IP8_30_29, SCIFB1_SCK_B, SEL_SCIFB1_1), 1273 PINMUX_IPSR_MSEL(IP8_30_29, VI1_DATA1_VI1_B1_B, SEL_VI1_1), 1274 1275 PINMUX_IPSR_GPSR(IP9_1_0, SD0_DAT0), 1276 PINMUX_IPSR_MSEL(IP9_1_0, SCIFB1_RXD_B, SEL_SCIFB1_1), 1277 PINMUX_IPSR_MSEL(IP9_1_0, VI1_DATA2_VI1_B2_B, SEL_VI1_1), 1278 PINMUX_IPSR_GPSR(IP9_3_2, SD0_DAT1), 1279 PINMUX_IPSR_MSEL(IP9_3_2, SCIFB1_TXD_B, SEL_SCIFB1_1), 1280 PINMUX_IPSR_MSEL(IP9_3_2, VI1_DATA3_VI1_B3_B, SEL_VI1_1), 1281 PINMUX_IPSR_GPSR(IP9_5_4, SD0_DAT2), 1282 PINMUX_IPSR_MSEL(IP9_5_4, SCIFB1_CTS_N_B, SEL_SCIFB1_1), 1283 PINMUX_IPSR_MSEL(IP9_5_4, VI1_DATA4_VI1_B4_B, SEL_VI1_1), 1284 PINMUX_IPSR_GPSR(IP9_7_6, SD0_DAT3), 1285 PINMUX_IPSR_MSEL(IP9_7_6, SCIFB1_RTS_N_B, SEL_SCIFB1_1), 1286 PINMUX_IPSR_MSEL(IP9_7_6, VI1_DATA5_VI1_B5_B, SEL_VI1_1), 1287 PINMUX_IPSR_GPSR(IP9_11_8, SD0_CD), 1288 PINMUX_IPSR_GPSR(IP9_11_8, MMC0_D6), 1289 PINMUX_IPSR_MSEL(IP9_11_8, TS_SDEN0_B, SEL_TSIF0_1), 1290 PINMUX_IPSR_GPSR(IP9_11_8, USB0_EXTP), 1291 PINMUX_IPSR_MSEL(IP9_11_8, GLO_SCLK, SEL_GPS_0), 1292 PINMUX_IPSR_MSEL(IP9_11_8, VI1_DATA6_VI1_B6_B, SEL_VI1_1), 1293 PINMUX_IPSR_MSEL(IP9_11_8, IIC1_SCL_B, SEL_IIC1_1), 1294 PINMUX_IPSR_MSEL(IP9_11_8, I2C1_SCL_B, SEL_I2C1_1), 1295 PINMUX_IPSR_MSEL(IP9_11_8, VI2_DATA6_VI2_B6_B, SEL_VI2_1), 1296 PINMUX_IPSR_GPSR(IP9_15_12, SD0_WP), 1297 PINMUX_IPSR_GPSR(IP9_15_12, MMC0_D7), 1298 PINMUX_IPSR_MSEL(IP9_15_12, TS_SPSYNC0_B, SEL_TSIF0_1), 1299 PINMUX_IPSR_GPSR(IP9_15_12, USB0_IDIN), 1300 PINMUX_IPSR_MSEL(IP9_15_12, GLO_SDATA, SEL_GPS_0), 1301 PINMUX_IPSR_MSEL(IP9_15_12, VI1_DATA7_VI1_B7_B, SEL_VI1_1), 1302 PINMUX_IPSR_MSEL(IP9_15_12, IIC1_SDA_B, SEL_IIC1_1), 1303 PINMUX_IPSR_MSEL(IP9_15_12, I2C1_SDA_B, SEL_I2C1_1), 1304 PINMUX_IPSR_MSEL(IP9_15_12, VI2_DATA7_VI2_B7_B, SEL_VI2_1), 1305 PINMUX_IPSR_GPSR(IP9_17_16, SD1_CLK), 1306 PINMUX_IPSR_GPSR(IP9_17_16, AVB_TX_EN), 1307 PINMUX_IPSR_GPSR(IP9_19_18, SD1_CMD), 1308 PINMUX_IPSR_GPSR(IP9_19_18, AVB_TX_ER), 1309 PINMUX_IPSR_MSEL(IP9_19_18, SCIFB0_SCK_B, SEL_SCIFB_1), 1310 PINMUX_IPSR_GPSR(IP9_21_20, SD1_DAT0), 1311 PINMUX_IPSR_GPSR(IP9_21_20, AVB_TX_CLK), 1312 PINMUX_IPSR_MSEL(IP9_21_20, SCIFB0_RXD_B, SEL_SCIFB_1), 1313 PINMUX_IPSR_GPSR(IP9_23_22, SD1_DAT1), 1314 PINMUX_IPSR_GPSR(IP9_23_22, AVB_LINK), 1315 PINMUX_IPSR_MSEL(IP9_23_22, SCIFB0_TXD_B, SEL_SCIFB_1), 1316 PINMUX_IPSR_GPSR(IP9_25_24, SD1_DAT2), 1317 PINMUX_IPSR_GPSR(IP9_25_24, AVB_COL), 1318 PINMUX_IPSR_MSEL(IP9_25_24, SCIFB0_CTS_N_B, SEL_SCIFB_1), 1319 PINMUX_IPSR_GPSR(IP9_27_26, SD1_DAT3), 1320 PINMUX_IPSR_GPSR(IP9_27_26, AVB_RXD0), 1321 PINMUX_IPSR_MSEL(IP9_27_26, SCIFB0_RTS_N_B, SEL_SCIFB_1), 1322 PINMUX_IPSR_GPSR(IP9_31_28, SD1_CD), 1323 PINMUX_IPSR_GPSR(IP9_31_28, MMC1_D6), 1324 PINMUX_IPSR_MSEL(IP9_31_28, TS_SDEN1, SEL_TSIF1_0), 1325 PINMUX_IPSR_GPSR(IP9_31_28, USB1_EXTP), 1326 PINMUX_IPSR_MSEL(IP9_31_28, GLO_SS, SEL_GPS_0), 1327 PINMUX_IPSR_MSEL(IP9_31_28, VI0_CLK_B, SEL_VI0_1), 1328 PINMUX_IPSR_MSEL(IP9_31_28, IIC2_SCL_D, SEL_IIC2_3), 1329 PINMUX_IPSR_MSEL(IP9_31_28, I2C2_SCL_D, SEL_I2C2_3), 1330 PINMUX_IPSR_MSEL(IP9_31_28, SIM0_CLK_B, SEL_SIM_1), 1331 PINMUX_IPSR_MSEL(IP9_31_28, VI3_CLK_B, SEL_VI3_1), 1332 1333 PINMUX_IPSR_GPSR(IP10_3_0, SD1_WP), 1334 PINMUX_IPSR_GPSR(IP10_3_0, MMC1_D7), 1335 PINMUX_IPSR_MSEL(IP10_3_0, TS_SPSYNC1, SEL_TSIF1_0), 1336 PINMUX_IPSR_GPSR(IP10_3_0, USB1_IDIN), 1337 PINMUX_IPSR_MSEL(IP10_3_0, GLO_RFON, SEL_GPS_0), 1338 PINMUX_IPSR_MSEL(IP10_3_0, VI1_CLK_B, SEL_VI1_1), 1339 PINMUX_IPSR_MSEL(IP10_3_0, IIC2_SDA_D, SEL_IIC2_3), 1340 PINMUX_IPSR_MSEL(IP10_3_0, I2C2_SDA_D, SEL_I2C2_3), 1341 PINMUX_IPSR_MSEL(IP10_3_0, SIM0_D_B, SEL_SIM_1), 1342 PINMUX_IPSR_GPSR(IP10_6_4, SD2_CLK), 1343 PINMUX_IPSR_GPSR(IP10_6_4, MMC0_CLK), 1344 PINMUX_IPSR_MSEL(IP10_6_4, SIM0_CLK, SEL_SIM_0), 1345 PINMUX_IPSR_MSEL(IP10_6_4, VI0_DATA0_VI0_B0_B, SEL_VI0_1), 1346 PINMUX_IPSR_MSEL(IP10_6_4, TS_SDEN0_C, SEL_TSIF0_2), 1347 PINMUX_IPSR_MSEL(IP10_6_4, GLO_SCLK_B, SEL_GPS_1), 1348 PINMUX_IPSR_MSEL(IP10_6_4, VI3_DATA0_B, SEL_VI3_1), 1349 PINMUX_IPSR_GPSR(IP10_10_7, SD2_CMD), 1350 PINMUX_IPSR_GPSR(IP10_10_7, MMC0_CMD), 1351 PINMUX_IPSR_MSEL(IP10_10_7, SIM0_D, SEL_SIM_0), 1352 PINMUX_IPSR_MSEL(IP10_10_7, VI0_DATA1_VI0_B1_B, SEL_VI0_1), 1353 PINMUX_IPSR_MSEL(IP10_10_7, SCIFB1_SCK_E, SEL_SCIFB1_4), 1354 PINMUX_IPSR_MSEL(IP10_10_7, SCK1_D, SEL_SCIF1_3), 1355 PINMUX_IPSR_MSEL(IP10_10_7, TS_SPSYNC0_C, SEL_TSIF0_2), 1356 PINMUX_IPSR_MSEL(IP10_10_7, GLO_SDATA_B, SEL_GPS_1), 1357 PINMUX_IPSR_MSEL(IP10_10_7, VI3_DATA1_B, SEL_VI3_1), 1358 PINMUX_IPSR_GPSR(IP10_14_11, SD2_DAT0), 1359 PINMUX_IPSR_GPSR(IP10_14_11, MMC0_D0), 1360 PINMUX_IPSR_MSEL(IP10_14_11, FMCLK_B, SEL_FM_1), 1361 PINMUX_IPSR_MSEL(IP10_14_11, VI0_DATA2_VI0_B2_B, SEL_VI0_1), 1362 PINMUX_IPSR_MSEL(IP10_14_11, SCIFB1_RXD_E, SEL_SCIFB1_4), 1363 PINMUX_IPSR_MSEL(IP10_14_11, RX1_D, SEL_SCIF1_3), 1364 PINMUX_IPSR_MSEL(IP10_14_11, TS_SDAT0_C, SEL_TSIF0_2), 1365 PINMUX_IPSR_MSEL(IP10_14_11, GLO_SS_B, SEL_GPS_1), 1366 PINMUX_IPSR_MSEL(IP10_14_11, VI3_DATA2_B, SEL_VI3_1), 1367 PINMUX_IPSR_GPSR(IP10_18_15, SD2_DAT1), 1368 PINMUX_IPSR_GPSR(IP10_18_15, MMC0_D1), 1369 PINMUX_IPSR_MSEL(IP10_18_15, FMIN_B, SEL_FM_1), 1370 PINMUX_IPSR_MSEL(IP10_18_15, VI0_DATA3_VI0_B3_B, SEL_VI0_1), 1371 PINMUX_IPSR_MSEL(IP10_18_15, SCIFB1_TXD_E, SEL_SCIFB1_4), 1372 PINMUX_IPSR_MSEL(IP10_18_15, TX1_D, SEL_SCIF1_3), 1373 PINMUX_IPSR_MSEL(IP10_18_15, TS_SCK0_C, SEL_TSIF0_2), 1374 PINMUX_IPSR_MSEL(IP10_18_15, GLO_RFON_B, SEL_GPS_1), 1375 PINMUX_IPSR_MSEL(IP10_18_15, VI3_DATA3_B, SEL_VI3_1), 1376 PINMUX_IPSR_GPSR(IP10_22_19, SD2_DAT2), 1377 PINMUX_IPSR_GPSR(IP10_22_19, MMC0_D2), 1378 PINMUX_IPSR_MSEL(IP10_22_19, BPFCLK_B, SEL_FM_1), 1379 PINMUX_IPSR_MSEL(IP10_22_19, VI0_DATA4_VI0_B4_B, SEL_VI0_1), 1380 PINMUX_IPSR_MSEL(IP10_22_19, HRX0_D, SEL_HSCIF0_3), 1381 PINMUX_IPSR_MSEL(IP10_22_19, TS_SDEN1_B, SEL_TSIF1_1), 1382 PINMUX_IPSR_MSEL(IP10_22_19, GLO_Q0_B, SEL_GPS_1), 1383 PINMUX_IPSR_MSEL(IP10_22_19, VI3_DATA4_B, SEL_VI3_1), 1384 PINMUX_IPSR_GPSR(IP10_25_23, SD2_DAT3), 1385 PINMUX_IPSR_GPSR(IP10_25_23, MMC0_D3), 1386 PINMUX_IPSR_MSEL(IP10_25_23, SIM0_RST, SEL_SIM_0), 1387 PINMUX_IPSR_MSEL(IP10_25_23, VI0_DATA5_VI0_B5_B, SEL_VI0_1), 1388 PINMUX_IPSR_MSEL(IP10_25_23, HTX0_D, SEL_HSCIF0_3), 1389 PINMUX_IPSR_MSEL(IP10_25_23, TS_SPSYNC1_B, SEL_TSIF1_1), 1390 PINMUX_IPSR_MSEL(IP10_25_23, GLO_Q1_B, SEL_GPS_1), 1391 PINMUX_IPSR_MSEL(IP10_25_23, VI3_DATA5_B, SEL_VI3_1), 1392 PINMUX_IPSR_GPSR(IP10_29_26, SD2_CD), 1393 PINMUX_IPSR_GPSR(IP10_29_26, MMC0_D4), 1394 PINMUX_IPSR_MSEL(IP10_29_26, TS_SDAT0_B, SEL_TSIF0_1), 1395 PINMUX_IPSR_GPSR(IP10_29_26, USB2_EXTP), 1396 PINMUX_IPSR_MSEL(IP10_29_26, GLO_I0, SEL_GPS_0), 1397 PINMUX_IPSR_MSEL(IP10_29_26, VI0_DATA6_VI0_B6_B, SEL_VI0_1), 1398 PINMUX_IPSR_MSEL(IP10_29_26, HCTS0_N_D, SEL_HSCIF0_3), 1399 PINMUX_IPSR_MSEL(IP10_29_26, TS_SDAT1_B, SEL_TSIF1_1), 1400 PINMUX_IPSR_MSEL(IP10_29_26, GLO_I0_B, SEL_GPS_1), 1401 PINMUX_IPSR_MSEL(IP10_29_26, VI3_DATA6_B, SEL_VI3_1), 1402 1403 PINMUX_IPSR_GPSR(IP11_3_0, SD2_WP), 1404 PINMUX_IPSR_GPSR(IP11_3_0, MMC0_D5), 1405 PINMUX_IPSR_MSEL(IP11_3_0, TS_SCK0_B, SEL_TSIF0_1), 1406 PINMUX_IPSR_GPSR(IP11_3_0, USB2_IDIN), 1407 PINMUX_IPSR_MSEL(IP11_3_0, GLO_I1, SEL_GPS_0), 1408 PINMUX_IPSR_MSEL(IP11_3_0, VI0_DATA7_VI0_B7_B, SEL_VI0_1), 1409 PINMUX_IPSR_MSEL(IP11_3_0, HRTS0_N_D, SEL_HSCIF0_3), 1410 PINMUX_IPSR_MSEL(IP11_3_0, TS_SCK1_B, SEL_TSIF1_1), 1411 PINMUX_IPSR_MSEL(IP11_3_0, GLO_I1_B, SEL_GPS_1), 1412 PINMUX_IPSR_MSEL(IP11_3_0, VI3_DATA7_B, SEL_VI3_1), 1413 PINMUX_IPSR_GPSR(IP11_4, SD3_CLK), 1414 PINMUX_IPSR_GPSR(IP11_4, MMC1_CLK), 1415 PINMUX_IPSR_GPSR(IP11_6_5, SD3_CMD), 1416 PINMUX_IPSR_GPSR(IP11_6_5, MMC1_CMD), 1417 PINMUX_IPSR_GPSR(IP11_6_5, MTS_N), 1418 PINMUX_IPSR_GPSR(IP11_8_7, SD3_DAT0), 1419 PINMUX_IPSR_GPSR(IP11_8_7, MMC1_D0), 1420 PINMUX_IPSR_GPSR(IP11_8_7, STM_N), 1421 PINMUX_IPSR_GPSR(IP11_10_9, SD3_DAT1), 1422 PINMUX_IPSR_GPSR(IP11_10_9, MMC1_D1), 1423 PINMUX_IPSR_GPSR(IP11_10_9, MDATA), 1424 PINMUX_IPSR_GPSR(IP11_12_11, SD3_DAT2), 1425 PINMUX_IPSR_GPSR(IP11_12_11, MMC1_D2), 1426 PINMUX_IPSR_GPSR(IP11_12_11, SDATA), 1427 PINMUX_IPSR_GPSR(IP11_14_13, SD3_DAT3), 1428 PINMUX_IPSR_GPSR(IP11_14_13, MMC1_D3), 1429 PINMUX_IPSR_GPSR(IP11_14_13, SCKZ), 1430 PINMUX_IPSR_GPSR(IP11_17_15, SD3_CD), 1431 PINMUX_IPSR_GPSR(IP11_17_15, MMC1_D4), 1432 PINMUX_IPSR_MSEL(IP11_17_15, TS_SDAT1, SEL_TSIF1_0), 1433 PINMUX_IPSR_GPSR(IP11_17_15, VSP), 1434 PINMUX_IPSR_MSEL(IP11_17_15, GLO_Q0, SEL_GPS_0), 1435 PINMUX_IPSR_MSEL(IP11_17_15, SIM0_RST_B, SEL_SIM_1), 1436 PINMUX_IPSR_GPSR(IP11_21_18, SD3_WP), 1437 PINMUX_IPSR_GPSR(IP11_21_18, MMC1_D5), 1438 PINMUX_IPSR_MSEL(IP11_21_18, TS_SCK1, SEL_TSIF1_0), 1439 PINMUX_IPSR_MSEL(IP11_21_18, GLO_Q1, SEL_GPS_0), 1440 PINMUX_IPSR_MSEL(IP11_21_18, FMIN_C, SEL_FM_2), 1441 PINMUX_IPSR_MSEL(IP11_21_18, FMIN_E, SEL_FM_4), 1442 PINMUX_IPSR_MSEL(IP11_21_18, FMIN_F, SEL_FM_5), 1443 PINMUX_IPSR_GPSR(IP11_23_22, MLB_CLK), 1444 PINMUX_IPSR_MSEL(IP11_23_22, IIC2_SCL_B, SEL_IIC2_1), 1445 PINMUX_IPSR_MSEL(IP11_23_22, I2C2_SCL_B, SEL_I2C2_1), 1446 PINMUX_IPSR_GPSR(IP11_26_24, MLB_SIG), 1447 PINMUX_IPSR_MSEL(IP11_26_24, SCIFB1_RXD_D, SEL_SCIFB1_3), 1448 PINMUX_IPSR_MSEL(IP11_26_24, RX1_C, SEL_SCIF1_2), 1449 PINMUX_IPSR_MSEL(IP11_26_24, IIC2_SDA_B, SEL_IIC2_1), 1450 PINMUX_IPSR_MSEL(IP11_26_24, I2C2_SDA_B, SEL_I2C2_1), 1451 PINMUX_IPSR_GPSR(IP11_29_27, MLB_DAT), 1452 PINMUX_IPSR_MSEL(IP11_29_27, SCIFB1_TXD_D, SEL_SCIFB1_3), 1453 PINMUX_IPSR_MSEL(IP11_29_27, TX1_C, SEL_SCIF1_2), 1454 PINMUX_IPSR_MSEL(IP11_29_27, BPFCLK_C, SEL_FM_2), 1455 PINMUX_IPSR_GPSR(IP11_31_30, SSI_SCK0129), 1456 PINMUX_IPSR_MSEL(IP11_31_30, CAN_CLK_B, SEL_CANCLK_1), 1457 PINMUX_IPSR_GPSR(IP11_31_30, MOUT0), 1458 1459 PINMUX_IPSR_GPSR(IP12_1_0, SSI_WS0129), 1460 PINMUX_IPSR_MSEL(IP12_1_0, CAN0_TX_B, SEL_CAN0_1), 1461 PINMUX_IPSR_GPSR(IP12_1_0, MOUT1), 1462 PINMUX_IPSR_GPSR(IP12_3_2, SSI_SDATA0), 1463 PINMUX_IPSR_MSEL(IP12_3_2, CAN0_RX_B, SEL_CAN0_1), 1464 PINMUX_IPSR_GPSR(IP12_3_2, MOUT2), 1465 PINMUX_IPSR_GPSR(IP12_5_4, SSI_SDATA1), 1466 PINMUX_IPSR_MSEL(IP12_5_4, CAN1_TX_B, SEL_CAN1_1), 1467 PINMUX_IPSR_GPSR(IP12_5_4, MOUT5), 1468 PINMUX_IPSR_GPSR(IP12_7_6, SSI_SDATA2), 1469 PINMUX_IPSR_MSEL(IP12_7_6, CAN1_RX_B, SEL_CAN1_1), 1470 PINMUX_IPSR_GPSR(IP12_7_6, SSI_SCK1), 1471 PINMUX_IPSR_GPSR(IP12_7_6, MOUT6), 1472 PINMUX_IPSR_GPSR(IP12_10_8, SSI_SCK34), 1473 PINMUX_IPSR_GPSR(IP12_10_8, STP_OPWM_0), 1474 PINMUX_IPSR_MSEL(IP12_10_8, SCIFB0_SCK, SEL_SCIFB_0), 1475 PINMUX_IPSR_MSEL(IP12_10_8, MSIOF1_SCK, SEL_SOF1_0), 1476 PINMUX_IPSR_GPSR(IP12_10_8, CAN_DEBUG_HW_TRIGGER), 1477 PINMUX_IPSR_GPSR(IP12_13_11, SSI_WS34), 1478 PINMUX_IPSR_MSEL(IP12_13_11, STP_IVCXO27_0, SEL_SSP_0), 1479 PINMUX_IPSR_MSEL(IP12_13_11, SCIFB0_RXD, SEL_SCIFB_0), 1480 PINMUX_IPSR_GPSR(IP12_13_11, MSIOF1_SYNC), 1481 PINMUX_IPSR_GPSR(IP12_13_11, CAN_STEP0), 1482 PINMUX_IPSR_GPSR(IP12_16_14, SSI_SDATA3), 1483 PINMUX_IPSR_MSEL(IP12_16_14, STP_ISCLK_0, SEL_SSP_0), 1484 PINMUX_IPSR_MSEL(IP12_16_14, SCIFB0_TXD, SEL_SCIFB_0), 1485 PINMUX_IPSR_MSEL(IP12_16_14, MSIOF1_SS1, SEL_SOF1_0), 1486 PINMUX_IPSR_GPSR(IP12_16_14, CAN_TXCLK), 1487 PINMUX_IPSR_GPSR(IP12_19_17, SSI_SCK4), 1488 PINMUX_IPSR_MSEL(IP12_19_17, STP_ISD_0, SEL_SSP_0), 1489 PINMUX_IPSR_MSEL(IP12_19_17, SCIFB0_CTS_N, SEL_SCIFB_0), 1490 PINMUX_IPSR_MSEL(IP12_19_17, MSIOF1_SS2, SEL_SOF1_0), 1491 PINMUX_IPSR_MSEL(IP12_19_17, SSI_SCK5_C, SEL_SSI5_2), 1492 PINMUX_IPSR_GPSR(IP12_19_17, CAN_DEBUGOUT0), 1493 PINMUX_IPSR_GPSR(IP12_22_20, SSI_WS4), 1494 PINMUX_IPSR_MSEL(IP12_22_20, STP_ISEN_0, SEL_SSP_0), 1495 PINMUX_IPSR_MSEL(IP12_22_20, SCIFB0_RTS_N, SEL_SCIFB_0), 1496 PINMUX_IPSR_MSEL(IP12_22_20, MSIOF1_TXD, SEL_SOF1_0), 1497 PINMUX_IPSR_MSEL(IP12_22_20, SSI_WS5_C, SEL_SSI5_2), 1498 PINMUX_IPSR_GPSR(IP12_22_20, CAN_DEBUGOUT1), 1499 PINMUX_IPSR_GPSR(IP12_24_23, SSI_SDATA4), 1500 PINMUX_IPSR_MSEL(IP12_24_23, STP_ISSYNC_0, SEL_SSP_0), 1501 PINMUX_IPSR_MSEL(IP12_24_23, MSIOF1_RXD, SEL_SOF1_0), 1502 PINMUX_IPSR_GPSR(IP12_24_23, CAN_DEBUGOUT2), 1503 PINMUX_IPSR_MSEL(IP12_27_25, SSI_SCK5, SEL_SSI5_0), 1504 PINMUX_IPSR_MSEL(IP12_27_25, SCIFB1_SCK, SEL_SCIFB1_0), 1505 PINMUX_IPSR_MSEL(IP12_27_25, IERX_B, SEL_IEB_1), 1506 PINMUX_IPSR_GPSR(IP12_27_25, DU2_EXHSYNC_DU2_HSYNC), 1507 PINMUX_IPSR_GPSR(IP12_27_25, QSTH_QHS), 1508 PINMUX_IPSR_GPSR(IP12_27_25, CAN_DEBUGOUT3), 1509 PINMUX_IPSR_MSEL(IP12_30_28, SSI_WS5, SEL_SSI5_0), 1510 PINMUX_IPSR_MSEL(IP12_30_28, SCIFB1_RXD, SEL_SCIFB1_0), 1511 PINMUX_IPSR_MSEL(IP12_30_28, IECLK_B, SEL_IEB_1), 1512 PINMUX_IPSR_GPSR(IP12_30_28, DU2_EXVSYNC_DU2_VSYNC), 1513 PINMUX_IPSR_GPSR(IP12_30_28, QSTB_QHE), 1514 PINMUX_IPSR_GPSR(IP12_30_28, CAN_DEBUGOUT4), 1515 1516 PINMUX_IPSR_MSEL(IP13_2_0, SSI_SDATA5, SEL_SSI5_0), 1517 PINMUX_IPSR_MSEL(IP13_2_0, SCIFB1_TXD, SEL_SCIFB1_0), 1518 PINMUX_IPSR_MSEL(IP13_2_0, IETX_B, SEL_IEB_1), 1519 PINMUX_IPSR_GPSR(IP13_2_0, DU2_DR2), 1520 PINMUX_IPSR_GPSR(IP13_2_0, LCDOUT2), 1521 PINMUX_IPSR_GPSR(IP13_2_0, CAN_DEBUGOUT5), 1522 PINMUX_IPSR_MSEL(IP13_6_3, SSI_SCK6, SEL_SSI6_0), 1523 PINMUX_IPSR_MSEL(IP13_6_3, SCIFB1_CTS_N, SEL_SCIFB1_0), 1524 PINMUX_IPSR_MSEL(IP13_6_3, BPFCLK_D, SEL_FM_3), 1525 PINMUX_IPSR_GPSR(IP13_6_3, DU2_DR3), 1526 PINMUX_IPSR_GPSR(IP13_6_3, LCDOUT3), 1527 PINMUX_IPSR_GPSR(IP13_6_3, CAN_DEBUGOUT6), 1528 PINMUX_IPSR_MSEL(IP13_6_3, BPFCLK_F, SEL_FM_5), 1529 PINMUX_IPSR_MSEL(IP13_9_7, SSI_WS6, SEL_SSI6_0), 1530 PINMUX_IPSR_MSEL(IP13_9_7, SCIFB1_RTS_N, SEL_SCIFB1_0), 1531 PINMUX_IPSR_MSEL(IP13_9_7, CAN0_TX_D, SEL_CAN0_3), 1532 PINMUX_IPSR_GPSR(IP13_9_7, DU2_DR4), 1533 PINMUX_IPSR_GPSR(IP13_9_7, LCDOUT4), 1534 PINMUX_IPSR_GPSR(IP13_9_7, CAN_DEBUGOUT7), 1535 PINMUX_IPSR_MSEL(IP13_12_10, SSI_SDATA6, SEL_SSI6_0), 1536 PINMUX_IPSR_MSEL(IP13_12_10, FMIN_D, SEL_FM_3), 1537 PINMUX_IPSR_GPSR(IP13_12_10, DU2_DR5), 1538 PINMUX_IPSR_GPSR(IP13_12_10, LCDOUT5), 1539 PINMUX_IPSR_GPSR(IP13_12_10, CAN_DEBUGOUT8), 1540 PINMUX_IPSR_MSEL(IP13_15_13, SSI_SCK78, SEL_SSI7_0), 1541 PINMUX_IPSR_MSEL(IP13_15_13, STP_IVCXO27_1, SEL_SSP_0), 1542 PINMUX_IPSR_MSEL(IP13_15_13, SCK1, SEL_SCIF1_0), 1543 PINMUX_IPSR_MSEL(IP13_15_13, SCIFA1_SCK, SEL_SCIFA1_0), 1544 PINMUX_IPSR_GPSR(IP13_15_13, DU2_DR6), 1545 PINMUX_IPSR_GPSR(IP13_15_13, LCDOUT6), 1546 PINMUX_IPSR_GPSR(IP13_15_13, CAN_DEBUGOUT9), 1547 PINMUX_IPSR_MSEL(IP13_18_16, SSI_WS78, SEL_SSI7_0), 1548 PINMUX_IPSR_MSEL(IP13_18_16, STP_ISCLK_1, SEL_SSP_0), 1549 PINMUX_IPSR_MSEL(IP13_18_16, SCIFB2_SCK, SEL_SCIFB2_0), 1550 PINMUX_IPSR_GPSR(IP13_18_16, SCIFA2_CTS_N), 1551 PINMUX_IPSR_GPSR(IP13_18_16, DU2_DR7), 1552 PINMUX_IPSR_GPSR(IP13_18_16, LCDOUT7), 1553 PINMUX_IPSR_GPSR(IP13_18_16, CAN_DEBUGOUT10), 1554 PINMUX_IPSR_MSEL(IP13_22_19, SSI_SDATA7, SEL_SSI7_0), 1555 PINMUX_IPSR_MSEL(IP13_22_19, STP_ISD_1, SEL_SSP_0), 1556 PINMUX_IPSR_MSEL(IP13_22_19, SCIFB2_RXD, SEL_SCIFB2_0), 1557 PINMUX_IPSR_GPSR(IP13_22_19, SCIFA2_RTS_N), 1558 PINMUX_IPSR_GPSR(IP13_22_19, TCLK2), 1559 PINMUX_IPSR_GPSR(IP13_22_19, QSTVA_QVS), 1560 PINMUX_IPSR_GPSR(IP13_22_19, CAN_DEBUGOUT11), 1561 PINMUX_IPSR_MSEL(IP13_22_19, BPFCLK_E, SEL_FM_4), 1562 PINMUX_IPSR_MSEL(IP13_22_19, SSI_SDATA7_B, SEL_SSI7_1), 1563 PINMUX_IPSR_MSEL(IP13_22_19, FMIN_G, SEL_FM_6), 1564 PINMUX_IPSR_MSEL(IP13_25_23, SSI_SDATA8, SEL_SSI8_0), 1565 PINMUX_IPSR_MSEL(IP13_25_23, STP_ISEN_1, SEL_SSP_0), 1566 PINMUX_IPSR_MSEL(IP13_25_23, SCIFB2_TXD, SEL_SCIFB2_0), 1567 PINMUX_IPSR_MSEL(IP13_25_23, CAN0_TX_C, SEL_CAN0_2), 1568 PINMUX_IPSR_GPSR(IP13_25_23, CAN_DEBUGOUT12), 1569 PINMUX_IPSR_MSEL(IP13_25_23, SSI_SDATA8_B, SEL_SSI8_1), 1570 PINMUX_IPSR_GPSR(IP13_28_26, SSI_SDATA9), 1571 PINMUX_IPSR_MSEL(IP13_28_26, STP_ISSYNC_1, SEL_SSP_0), 1572 PINMUX_IPSR_MSEL(IP13_28_26, SCIFB2_CTS_N, SEL_SCIFB2_0), 1573 PINMUX_IPSR_GPSR(IP13_28_26, SSI_WS1), 1574 PINMUX_IPSR_MSEL(IP13_28_26, SSI_SDATA5_C, SEL_SSI5_2), 1575 PINMUX_IPSR_GPSR(IP13_28_26, CAN_DEBUGOUT13), 1576 PINMUX_IPSR_GPSR(IP13_30_29, AUDIO_CLKA), 1577 PINMUX_IPSR_MSEL(IP13_30_29, SCIFB2_RTS_N, SEL_SCIFB2_0), 1578 PINMUX_IPSR_GPSR(IP13_30_29, CAN_DEBUGOUT14), 1579 1580 PINMUX_IPSR_GPSR(IP14_2_0, AUDIO_CLKB), 1581 PINMUX_IPSR_MSEL(IP14_2_0, SCIF_CLK, SEL_SCIFCLK_0), 1582 PINMUX_IPSR_MSEL(IP14_2_0, CAN0_RX_D, SEL_CAN0_3), 1583 PINMUX_IPSR_GPSR(IP14_2_0, DVC_MUTE), 1584 PINMUX_IPSR_MSEL(IP14_2_0, CAN0_RX_C, SEL_CAN0_2), 1585 PINMUX_IPSR_GPSR(IP14_2_0, CAN_DEBUGOUT15), 1586 PINMUX_IPSR_GPSR(IP14_2_0, REMOCON), 1587 PINMUX_IPSR_MSEL(IP14_5_3, SCIFA0_SCK, SEL_SCFA_0), 1588 PINMUX_IPSR_MSEL(IP14_5_3, HSCK1, SEL_HSCIF1_0), 1589 PINMUX_IPSR_GPSR(IP14_5_3, SCK0), 1590 PINMUX_IPSR_GPSR(IP14_5_3, MSIOF3_SS2), 1591 PINMUX_IPSR_GPSR(IP14_5_3, DU2_DG2), 1592 PINMUX_IPSR_GPSR(IP14_5_3, LCDOUT10), 1593 PINMUX_IPSR_MSEL(IP14_5_3, IIC1_SDA_C, SEL_IIC1_2), 1594 PINMUX_IPSR_MSEL(IP14_5_3, I2C1_SDA_C, SEL_I2C1_2), 1595 PINMUX_IPSR_MSEL(IP14_8_6, SCIFA0_RXD, SEL_SCFA_0), 1596 PINMUX_IPSR_MSEL(IP14_8_6, HRX1, SEL_HSCIF1_0), 1597 PINMUX_IPSR_MSEL(IP14_8_6, RX0, SEL_SCIF0_0), 1598 PINMUX_IPSR_GPSR(IP14_8_6, DU2_DR0), 1599 PINMUX_IPSR_GPSR(IP14_8_6, LCDOUT0), 1600 PINMUX_IPSR_MSEL(IP14_11_9, SCIFA0_TXD, SEL_SCFA_0), 1601 PINMUX_IPSR_MSEL(IP14_11_9, HTX1, SEL_HSCIF1_0), 1602 PINMUX_IPSR_MSEL(IP14_11_9, TX0, SEL_SCIF0_0), 1603 PINMUX_IPSR_GPSR(IP14_11_9, DU2_DR1), 1604 PINMUX_IPSR_GPSR(IP14_11_9, LCDOUT1), 1605 PINMUX_IPSR_MSEL(IP14_15_12, SCIFA0_CTS_N, SEL_SCFA_0), 1606 PINMUX_IPSR_MSEL(IP14_15_12, HCTS1_N, SEL_HSCIF1_0), 1607 PINMUX_IPSR_GPSR(IP14_15_12, CTS0_N), 1608 PINMUX_IPSR_MSEL(IP14_15_12, MSIOF3_SYNC, SEL_SOF3_0), 1609 PINMUX_IPSR_GPSR(IP14_15_12, DU2_DG3), 1610 PINMUX_IPSR_GPSR(IP14_15_12, LCDOUT11), 1611 PINMUX_IPSR_GPSR(IP14_15_12, PWM0_B), 1612 PINMUX_IPSR_MSEL(IP14_15_12, IIC1_SCL_C, SEL_IIC1_2), 1613 PINMUX_IPSR_MSEL(IP14_15_12, I2C1_SCL_C, SEL_I2C1_2), 1614 PINMUX_IPSR_MSEL(IP14_18_16, SCIFA0_RTS_N, SEL_SCFA_0), 1615 PINMUX_IPSR_MSEL(IP14_18_16, HRTS1_N, SEL_HSCIF1_0), 1616 PINMUX_IPSR_GPSR(IP14_18_16, RTS0_N), 1617 PINMUX_IPSR_GPSR(IP14_18_16, MSIOF3_SS1), 1618 PINMUX_IPSR_GPSR(IP14_18_16, DU2_DG0), 1619 PINMUX_IPSR_GPSR(IP14_18_16, LCDOUT8), 1620 PINMUX_IPSR_GPSR(IP14_18_16, PWM1_B), 1621 PINMUX_IPSR_MSEL(IP14_21_19, SCIFA1_RXD, SEL_SCIFA1_0), 1622 PINMUX_IPSR_MSEL(IP14_21_19, AD_DI, SEL_ADI_0), 1623 PINMUX_IPSR_MSEL(IP14_21_19, RX1, SEL_SCIF1_0), 1624 PINMUX_IPSR_GPSR(IP14_21_19, DU2_EXODDF_DU2_ODDF_DISP_CDE), 1625 PINMUX_IPSR_GPSR(IP14_21_19, QCPV_QDE), 1626 PINMUX_IPSR_MSEL(IP14_24_22, SCIFA1_TXD, SEL_SCIFA1_0), 1627 PINMUX_IPSR_MSEL(IP14_24_22, AD_DO, SEL_ADI_0), 1628 PINMUX_IPSR_MSEL(IP14_24_22, TX1, SEL_SCIF1_0), 1629 PINMUX_IPSR_GPSR(IP14_24_22, DU2_DG1), 1630 PINMUX_IPSR_GPSR(IP14_24_22, LCDOUT9), 1631 PINMUX_IPSR_MSEL(IP14_27_25, SCIFA1_CTS_N, SEL_SCIFA1_0), 1632 PINMUX_IPSR_MSEL(IP14_27_25, AD_CLK, SEL_ADI_0), 1633 PINMUX_IPSR_GPSR(IP14_27_25, CTS1_N), 1634 PINMUX_IPSR_MSEL(IP14_27_25, MSIOF3_RXD, SEL_SOF3_0), 1635 PINMUX_IPSR_GPSR(IP14_27_25, DU0_DOTCLKOUT), 1636 PINMUX_IPSR_GPSR(IP14_27_25, QCLK), 1637 PINMUX_IPSR_MSEL(IP14_30_28, SCIFA1_RTS_N, SEL_SCIFA1_0), 1638 PINMUX_IPSR_MSEL(IP14_30_28, AD_NCS_N, SEL_ADI_0), 1639 PINMUX_IPSR_GPSR(IP14_30_28, RTS1_N), 1640 PINMUX_IPSR_MSEL(IP14_30_28, MSIOF3_TXD, SEL_SOF3_0), 1641 PINMUX_IPSR_GPSR(IP14_30_28, DU1_DOTCLKOUT), 1642 PINMUX_IPSR_GPSR(IP14_30_28, QSTVB_QVE), 1643 PINMUX_IPSR_MSEL(IP14_30_28, HRTS0_N_C, SEL_HSCIF0_2), 1644 1645 PINMUX_IPSR_MSEL(IP15_2_0, SCIFA2_SCK, SEL_SCIFA2_0), 1646 PINMUX_IPSR_MSEL(IP15_2_0, FMCLK, SEL_FM_0), 1647 PINMUX_IPSR_GPSR(IP15_2_0, SCK2), 1648 PINMUX_IPSR_MSEL(IP15_2_0, MSIOF3_SCK, SEL_SOF3_0), 1649 PINMUX_IPSR_GPSR(IP15_2_0, DU2_DG7), 1650 PINMUX_IPSR_GPSR(IP15_2_0, LCDOUT15), 1651 PINMUX_IPSR_MSEL(IP15_2_0, SCIF_CLK_B, SEL_SCIFCLK_1), 1652 PINMUX_IPSR_MSEL(IP15_5_3, SCIFA2_RXD, SEL_SCIFA2_0), 1653 PINMUX_IPSR_MSEL(IP15_5_3, FMIN, SEL_FM_0), 1654 PINMUX_IPSR_MSEL(IP15_5_3, TX2, SEL_SCIF2_0), 1655 PINMUX_IPSR_GPSR(IP15_5_3, DU2_DB0), 1656 PINMUX_IPSR_GPSR(IP15_5_3, LCDOUT16), 1657 PINMUX_IPSR_MSEL(IP15_5_3, IIC2_SCL, SEL_IIC2_0), 1658 PINMUX_IPSR_MSEL(IP15_5_3, I2C2_SCL, SEL_I2C2_0), 1659 PINMUX_IPSR_MSEL(IP15_8_6, SCIFA2_TXD, SEL_SCIFA2_0), 1660 PINMUX_IPSR_MSEL(IP15_8_6, BPFCLK, SEL_FM_0), 1661 PINMUX_IPSR_MSEL(IP15_8_6, RX2, SEL_SCIF2_0), 1662 PINMUX_IPSR_GPSR(IP15_8_6, DU2_DB1), 1663 PINMUX_IPSR_GPSR(IP15_8_6, LCDOUT17), 1664 PINMUX_IPSR_MSEL(IP15_8_6, IIC2_SDA, SEL_IIC2_0), 1665 PINMUX_IPSR_MSEL(IP15_8_6, I2C2_SDA, SEL_I2C2_0), 1666 PINMUX_IPSR_GPSR(IP15_11_9, HSCK0), 1667 PINMUX_IPSR_MSEL(IP15_11_9, TS_SDEN0, SEL_TSIF0_0), 1668 PINMUX_IPSR_GPSR(IP15_11_9, DU2_DG4), 1669 PINMUX_IPSR_GPSR(IP15_11_9, LCDOUT12), 1670 PINMUX_IPSR_MSEL(IP15_11_9, HCTS0_N_C, SEL_HSCIF0_2), 1671 PINMUX_IPSR_MSEL(IP15_13_12, HRX0, SEL_HSCIF0_0), 1672 PINMUX_IPSR_GPSR(IP15_13_12, DU2_DB2), 1673 PINMUX_IPSR_GPSR(IP15_13_12, LCDOUT18), 1674 PINMUX_IPSR_MSEL(IP15_15_14, HTX0, SEL_HSCIF0_0), 1675 PINMUX_IPSR_GPSR(IP15_15_14, DU2_DB3), 1676 PINMUX_IPSR_GPSR(IP15_15_14, LCDOUT19), 1677 PINMUX_IPSR_MSEL(IP15_17_16, HCTS0_N, SEL_HSCIF0_0), 1678 PINMUX_IPSR_GPSR(IP15_17_16, SSI_SCK9), 1679 PINMUX_IPSR_GPSR(IP15_17_16, DU2_DB4), 1680 PINMUX_IPSR_GPSR(IP15_17_16, LCDOUT20), 1681 PINMUX_IPSR_MSEL(IP15_19_18, HRTS0_N, SEL_HSCIF0_0), 1682 PINMUX_IPSR_GPSR(IP15_19_18, SSI_WS9), 1683 PINMUX_IPSR_GPSR(IP15_19_18, DU2_DB5), 1684 PINMUX_IPSR_GPSR(IP15_19_18, LCDOUT21), 1685 PINMUX_IPSR_MSEL(IP15_22_20, MSIOF0_SCK, SEL_SOF0_0), 1686 PINMUX_IPSR_MSEL(IP15_22_20, TS_SDAT0, SEL_TSIF0_0), 1687 PINMUX_IPSR_GPSR(IP15_22_20, ADICLK), 1688 PINMUX_IPSR_GPSR(IP15_22_20, DU2_DB6), 1689 PINMUX_IPSR_GPSR(IP15_22_20, LCDOUT22), 1690 PINMUX_IPSR_GPSR(IP15_25_23, MSIOF0_SYNC), 1691 PINMUX_IPSR_MSEL(IP15_25_23, TS_SCK0, SEL_TSIF0_0), 1692 PINMUX_IPSR_GPSR(IP15_25_23, SSI_SCK2), 1693 PINMUX_IPSR_GPSR(IP15_25_23, ADIDATA), 1694 PINMUX_IPSR_GPSR(IP15_25_23, DU2_DB7), 1695 PINMUX_IPSR_GPSR(IP15_25_23, LCDOUT23), 1696 PINMUX_IPSR_MSEL(IP15_25_23, HRX0_C, SEL_SCIFA2_1), 1697 PINMUX_IPSR_MSEL(IP15_27_26, MSIOF0_SS1, SEL_SOF0_0), 1698 PINMUX_IPSR_GPSR(IP15_27_26, ADICHS0), 1699 PINMUX_IPSR_GPSR(IP15_27_26, DU2_DG5), 1700 PINMUX_IPSR_GPSR(IP15_27_26, LCDOUT13), 1701 PINMUX_IPSR_MSEL(IP15_29_28, MSIOF0_TXD, SEL_SOF0_0), 1702 PINMUX_IPSR_GPSR(IP15_29_28, ADICHS1), 1703 PINMUX_IPSR_GPSR(IP15_29_28, DU2_DG6), 1704 PINMUX_IPSR_GPSR(IP15_29_28, LCDOUT14), 1705 1706 PINMUX_IPSR_MSEL(IP16_2_0, MSIOF0_SS2, SEL_SOF0_0), 1707 PINMUX_IPSR_GPSR(IP16_2_0, AUDIO_CLKOUT), 1708 PINMUX_IPSR_GPSR(IP16_2_0, ADICHS2), 1709 PINMUX_IPSR_GPSR(IP16_2_0, DU2_DISP), 1710 PINMUX_IPSR_GPSR(IP16_2_0, QPOLA), 1711 PINMUX_IPSR_MSEL(IP16_2_0, HTX0_C, SEL_HSCIF0_2), 1712 PINMUX_IPSR_MSEL(IP16_2_0, SCIFA2_TXD_B, SEL_SCIFA2_1), 1713 PINMUX_IPSR_MSEL(IP16_5_3, MSIOF0_RXD, SEL_SOF0_0), 1714 PINMUX_IPSR_MSEL(IP16_5_3, TS_SPSYNC0, SEL_TSIF0_0), 1715 PINMUX_IPSR_GPSR(IP16_5_3, SSI_WS2), 1716 PINMUX_IPSR_GPSR(IP16_5_3, ADICS_SAMP), 1717 PINMUX_IPSR_GPSR(IP16_5_3, DU2_CDE), 1718 PINMUX_IPSR_GPSR(IP16_5_3, QPOLB), 1719 PINMUX_IPSR_MSEL(IP16_5_3, SCIFA2_RXD_B, SEL_HSCIF0_2), 1720 PINMUX_IPSR_GPSR(IP16_6, USB1_PWEN), 1721 PINMUX_IPSR_GPSR(IP16_6, AUDIO_CLKOUT_D), 1722 PINMUX_IPSR_GPSR(IP16_7, USB1_OVC), 1723 PINMUX_IPSR_MSEL(IP16_7, TCLK1_B, SEL_TMU1_1), 1724 1725 PINMUX_DATA(IIC0_SCL_MARK, FN_SEL_IIC0_0), 1726 PINMUX_DATA(IIC0_SDA_MARK, FN_SEL_IIC0_0), 1727 PINMUX_DATA(I2C0_SCL_MARK, FN_SEL_IIC0_1), 1728 PINMUX_DATA(I2C0_SDA_MARK, FN_SEL_IIC0_1), 1729 1730 PINMUX_DATA(IIC3_SCL_MARK, FN_SEL_IICDVFS_0), 1731 PINMUX_DATA(IIC3_SDA_MARK, FN_SEL_IICDVFS_0), 1732 PINMUX_DATA(I2C3_SCL_MARK, FN_SEL_IICDVFS_1), 1733 PINMUX_DATA(I2C3_SDA_MARK, FN_SEL_IICDVFS_1), 1734 }; 1735 1736 /* 1737 * Pins not associated with a GPIO port. 1738 */ 1739 enum { 1740 GP_ASSIGN_LAST(), 1741 NOGP_ALL(), 1742 }; 1743 1744 static const struct sh_pfc_pin pinmux_pins[] = { 1745 PINMUX_GPIO_GP_ALL(), 1746 PINMUX_NOGP_ALL(), 1747 }; 1748 1749 /* - AUDIO CLOCK ------------------------------------------------------------ */ 1750 static const unsigned int audio_clk_a_pins[] = { 1751 /* CLK A */ 1752 RCAR_GP_PIN(4, 25), 1753 }; 1754 static const unsigned int audio_clk_a_mux[] = { 1755 AUDIO_CLKA_MARK, 1756 }; 1757 static const unsigned int audio_clk_b_pins[] = { 1758 /* CLK B */ 1759 RCAR_GP_PIN(4, 26), 1760 }; 1761 static const unsigned int audio_clk_b_mux[] = { 1762 AUDIO_CLKB_MARK, 1763 }; 1764 static const unsigned int audio_clk_c_pins[] = { 1765 /* CLK C */ 1766 RCAR_GP_PIN(5, 27), 1767 }; 1768 static const unsigned int audio_clk_c_mux[] = { 1769 AUDIO_CLKC_MARK, 1770 }; 1771 static const unsigned int audio_clkout_pins[] = { 1772 /* CLK OUT */ 1773 RCAR_GP_PIN(5, 16), 1774 }; 1775 static const unsigned int audio_clkout_mux[] = { 1776 AUDIO_CLKOUT_MARK, 1777 }; 1778 static const unsigned int audio_clkout_b_pins[] = { 1779 /* CLK OUT B */ 1780 RCAR_GP_PIN(0, 23), 1781 }; 1782 static const unsigned int audio_clkout_b_mux[] = { 1783 AUDIO_CLKOUT_B_MARK, 1784 }; 1785 static const unsigned int audio_clkout_c_pins[] = { 1786 /* CLK OUT C */ 1787 RCAR_GP_PIN(5, 27), 1788 }; 1789 static const unsigned int audio_clkout_c_mux[] = { 1790 AUDIO_CLKOUT_C_MARK, 1791 }; 1792 static const unsigned int audio_clkout_d_pins[] = { 1793 /* CLK OUT D */ 1794 RCAR_GP_PIN(5, 20), 1795 }; 1796 static const unsigned int audio_clkout_d_mux[] = { 1797 AUDIO_CLKOUT_D_MARK, 1798 }; 1799 /* - AVB -------------------------------------------------------------------- */ 1800 static const unsigned int avb_link_pins[] = { 1801 RCAR_GP_PIN(3, 11), 1802 }; 1803 static const unsigned int avb_link_mux[] = { 1804 AVB_LINK_MARK, 1805 }; 1806 static const unsigned int avb_magic_pins[] = { 1807 RCAR_GP_PIN(2, 14), 1808 }; 1809 static const unsigned int avb_magic_mux[] = { 1810 AVB_MAGIC_MARK, 1811 }; 1812 static const unsigned int avb_phy_int_pins[] = { 1813 RCAR_GP_PIN(2, 15), 1814 }; 1815 static const unsigned int avb_phy_int_mux[] = { 1816 AVB_PHY_INT_MARK, 1817 }; 1818 static const unsigned int avb_mdio_pins[] = { 1819 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12), 1820 }; 1821 static const unsigned int avb_mdio_mux[] = { 1822 AVB_MDC_MARK, AVB_MDIO_MARK, 1823 }; 1824 static const unsigned int avb_mii_pins[] = { 1825 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10), 1826 RCAR_GP_PIN(0, 11), 1827 1828 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), 1829 RCAR_GP_PIN(2, 2), 1830 1831 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), 1832 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), 1833 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 12), 1834 }; 1835 static const unsigned int avb_mii_mux[] = { 1836 AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK, 1837 AVB_TXD3_MARK, 1838 1839 AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK, 1840 AVB_RXD3_MARK, 1841 1842 AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK, 1843 AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_ER_MARK, 1844 AVB_TX_CLK_MARK, AVB_COL_MARK, 1845 }; 1846 static const unsigned int avb_gmii_pins[] = { 1847 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10), 1848 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), 1849 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), 1850 1851 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), 1852 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4), 1853 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6), 1854 1855 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), 1856 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 16), 1857 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10), 1858 RCAR_GP_PIN(3, 12), 1859 }; 1860 static const unsigned int avb_gmii_mux[] = { 1861 AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK, 1862 AVB_TXD3_MARK, AVB_TXD4_MARK, AVB_TXD5_MARK, 1863 AVB_TXD6_MARK, AVB_TXD7_MARK, 1864 1865 AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK, 1866 AVB_RXD3_MARK, AVB_RXD4_MARK, AVB_RXD5_MARK, 1867 AVB_RXD6_MARK, AVB_RXD7_MARK, 1868 1869 AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK, 1870 AVB_CRS_MARK, AVB_GTX_CLK_MARK, AVB_GTXREFCLK_MARK, 1871 AVB_TX_EN_MARK, AVB_TX_ER_MARK, AVB_TX_CLK_MARK, 1872 AVB_COL_MARK, 1873 }; 1874 /* - CAN0 ----------------------------------------------------------------- */ 1875 static const unsigned int can0_data_pins[] = { 1876 /* CAN0 RX */ 1877 RCAR_GP_PIN(1, 17), 1878 /* CAN0 TX */ 1879 RCAR_GP_PIN(1, 19), 1880 }; 1881 static const unsigned int can0_data_mux[] = { 1882 CAN0_RX_MARK, 1883 CAN0_TX_MARK, 1884 }; 1885 static const unsigned int can0_data_b_pins[] = { 1886 /* CAN0 RXB */ 1887 RCAR_GP_PIN(4, 5), 1888 /* CAN0 TXB */ 1889 RCAR_GP_PIN(4, 4), 1890 }; 1891 static const unsigned int can0_data_b_mux[] = { 1892 CAN0_RX_B_MARK, 1893 CAN0_TX_B_MARK, 1894 }; 1895 static const unsigned int can0_data_c_pins[] = { 1896 /* CAN0 RXC */ 1897 RCAR_GP_PIN(4, 26), 1898 /* CAN0 TXC */ 1899 RCAR_GP_PIN(4, 23), 1900 }; 1901 static const unsigned int can0_data_c_mux[] = { 1902 CAN0_RX_C_MARK, 1903 CAN0_TX_C_MARK, 1904 }; 1905 static const unsigned int can0_data_d_pins[] = { 1906 /* CAN0 RXD */ 1907 RCAR_GP_PIN(4, 26), 1908 /* CAN0 TXD */ 1909 RCAR_GP_PIN(4, 18), 1910 }; 1911 static const unsigned int can0_data_d_mux[] = { 1912 CAN0_RX_D_MARK, 1913 CAN0_TX_D_MARK, 1914 }; 1915 /* - CAN1 ----------------------------------------------------------------- */ 1916 static const unsigned int can1_data_pins[] = { 1917 /* CAN1 RX */ 1918 RCAR_GP_PIN(1, 22), 1919 /* CAN1 TX */ 1920 RCAR_GP_PIN(1, 18), 1921 }; 1922 static const unsigned int can1_data_mux[] = { 1923 CAN1_RX_MARK, 1924 CAN1_TX_MARK, 1925 }; 1926 static const unsigned int can1_data_b_pins[] = { 1927 /* CAN1 RXB */ 1928 RCAR_GP_PIN(4, 7), 1929 /* CAN1 TXB */ 1930 RCAR_GP_PIN(4, 6), 1931 }; 1932 static const unsigned int can1_data_b_mux[] = { 1933 CAN1_RX_B_MARK, 1934 CAN1_TX_B_MARK, 1935 }; 1936 /* - CAN Clock -------------------------------------------------------------- */ 1937 static const unsigned int can_clk_pins[] = { 1938 /* CLK */ 1939 RCAR_GP_PIN(1, 21), 1940 }; 1941 1942 static const unsigned int can_clk_mux[] = { 1943 CAN_CLK_MARK, 1944 }; 1945 1946 static const unsigned int can_clk_b_pins[] = { 1947 /* CLK */ 1948 RCAR_GP_PIN(4, 3), 1949 }; 1950 1951 static const unsigned int can_clk_b_mux[] = { 1952 CAN_CLK_B_MARK, 1953 }; 1954 /* - DU RGB ----------------------------------------------------------------- */ 1955 static const unsigned int du_rgb666_pins[] = { 1956 /* R[7:2], G[7:2], B[7:2] */ 1957 RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 19), 1958 RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16), 1959 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 14), 1960 RCAR_GP_PIN(5, 7), RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27), 1961 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 11), 1962 RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 8), 1963 }; 1964 static const unsigned int du_rgb666_mux[] = { 1965 DU2_DR7_MARK, DU2_DR6_MARK, DU2_DR5_MARK, DU2_DR4_MARK, 1966 DU2_DR3_MARK, DU2_DR2_MARK, 1967 DU2_DG7_MARK, DU2_DG6_MARK, DU2_DG5_MARK, DU2_DG4_MARK, 1968 DU2_DG3_MARK, DU2_DG2_MARK, 1969 DU2_DB7_MARK, DU2_DB6_MARK, DU2_DB5_MARK, DU2_DB4_MARK, 1970 DU2_DB3_MARK, DU2_DB2_MARK, 1971 }; 1972 static const unsigned int du_rgb888_pins[] = { 1973 /* R[7:0], G[7:0], B[7:0] */ 1974 RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 19), 1975 RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16), 1976 RCAR_GP_PIN(4, 29), RCAR_GP_PIN(4, 28), RCAR_GP_PIN(5, 4), 1977 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 7), 1978 RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27), RCAR_GP_PIN(5, 1), 1979 RCAR_GP_PIN(4, 31), RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 12), 1980 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 9), 1981 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 5), 1982 }; 1983 static const unsigned int du_rgb888_mux[] = { 1984 DU2_DR7_MARK, DU2_DR6_MARK, DU2_DR5_MARK, DU2_DR4_MARK, 1985 DU2_DR3_MARK, DU2_DR2_MARK, DU2_DR1_MARK, DU2_DR0_MARK, 1986 DU2_DG7_MARK, DU2_DG6_MARK, DU2_DG5_MARK, DU2_DG4_MARK, 1987 DU2_DG3_MARK, DU2_DG2_MARK, DU2_DG1_MARK, DU2_DG0_MARK, 1988 DU2_DB7_MARK, DU2_DB6_MARK, DU2_DB5_MARK, DU2_DB4_MARK, 1989 DU2_DB3_MARK, DU2_DB2_MARK, DU2_DB1_MARK, DU2_DB0_MARK, 1990 }; 1991 static const unsigned int du_clk_out_0_pins[] = { 1992 /* CLKOUT */ 1993 RCAR_GP_PIN(5, 2), 1994 }; 1995 static const unsigned int du_clk_out_0_mux[] = { 1996 DU0_DOTCLKOUT_MARK 1997 }; 1998 static const unsigned int du_clk_out_1_pins[] = { 1999 /* CLKOUT */ 2000 RCAR_GP_PIN(5, 3), 2001 }; 2002 static const unsigned int du_clk_out_1_mux[] = { 2003 DU1_DOTCLKOUT_MARK 2004 }; 2005 static const unsigned int du_sync_0_pins[] = { 2006 /* VSYNC, HSYNC, DISP */ 2007 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(5, 0), 2008 }; 2009 static const unsigned int du_sync_0_mux[] = { 2010 DU2_EXVSYNC_DU2_VSYNC_MARK, DU2_EXHSYNC_DU2_HSYNC_MARK, 2011 DU2_EXODDF_DU2_ODDF_DISP_CDE_MARK 2012 }; 2013 static const unsigned int du_sync_1_pins[] = { 2014 /* VSYNC, HSYNC, DISP */ 2015 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(5, 16), 2016 }; 2017 static const unsigned int du_sync_1_mux[] = { 2018 DU2_EXVSYNC_DU2_VSYNC_MARK, DU2_EXHSYNC_DU2_HSYNC_MARK, 2019 DU2_DISP_MARK 2020 }; 2021 static const unsigned int du_cde_pins[] = { 2022 /* CDE */ 2023 RCAR_GP_PIN(5, 17), 2024 }; 2025 static const unsigned int du_cde_mux[] = { 2026 DU2_CDE_MARK, 2027 }; 2028 /* - DU0 -------------------------------------------------------------------- */ 2029 static const unsigned int du0_clk_in_pins[] = { 2030 /* CLKIN */ 2031 RCAR_GP_PIN(5, 26), 2032 }; 2033 static const unsigned int du0_clk_in_mux[] = { 2034 DU_DOTCLKIN0_MARK 2035 }; 2036 /* - DU1 -------------------------------------------------------------------- */ 2037 static const unsigned int du1_clk_in_pins[] = { 2038 /* CLKIN */ 2039 RCAR_GP_PIN(5, 27), 2040 }; 2041 static const unsigned int du1_clk_in_mux[] = { 2042 DU_DOTCLKIN1_MARK, 2043 }; 2044 /* - DU2 -------------------------------------------------------------------- */ 2045 static const unsigned int du2_clk_in_pins[] = { 2046 /* CLKIN */ 2047 RCAR_GP_PIN(5, 28), 2048 }; 2049 static const unsigned int du2_clk_in_mux[] = { 2050 DU_DOTCLKIN2_MARK, 2051 }; 2052 /* - ETH -------------------------------------------------------------------- */ 2053 static const unsigned int eth_link_pins[] = { 2054 /* LINK */ 2055 RCAR_GP_PIN(2, 22), 2056 }; 2057 static const unsigned int eth_link_mux[] = { 2058 ETH_LINK_MARK, 2059 }; 2060 static const unsigned int eth_magic_pins[] = { 2061 /* MAGIC */ 2062 RCAR_GP_PIN(2, 27), 2063 }; 2064 static const unsigned int eth_magic_mux[] = { 2065 ETH_MAGIC_MARK, 2066 }; 2067 static const unsigned int eth_mdio_pins[] = { 2068 /* MDC, MDIO */ 2069 RCAR_GP_PIN(2, 29), RCAR_GP_PIN(2, 24), 2070 }; 2071 static const unsigned int eth_mdio_mux[] = { 2072 ETH_MDC_MARK, ETH_MDIO_MARK, 2073 }; 2074 static const unsigned int eth_rmii_pins[] = { 2075 /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */ 2076 RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 19), 2077 RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 28), RCAR_GP_PIN(2, 25), 2078 RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 23), 2079 }; 2080 static const unsigned int eth_rmii_mux[] = { 2081 ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK, 2082 ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REF_CLK_MARK, 2083 }; 2084 /* - HSCIF0 ----------------------------------------------------------------- */ 2085 static const unsigned int hscif0_data_pins[] = { 2086 /* RX, TX */ 2087 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9), 2088 }; 2089 static const unsigned int hscif0_data_mux[] = { 2090 HRX0_MARK, HTX0_MARK, 2091 }; 2092 static const unsigned int hscif0_clk_pins[] = { 2093 /* SCK */ 2094 RCAR_GP_PIN(5, 7), 2095 }; 2096 static const unsigned int hscif0_clk_mux[] = { 2097 HSCK0_MARK, 2098 }; 2099 static const unsigned int hscif0_ctrl_pins[] = { 2100 /* RTS, CTS */ 2101 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10), 2102 }; 2103 static const unsigned int hscif0_ctrl_mux[] = { 2104 HRTS0_N_MARK, HCTS0_N_MARK, 2105 }; 2106 static const unsigned int hscif0_data_b_pins[] = { 2107 /* RX, TX */ 2108 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 12), 2109 }; 2110 static const unsigned int hscif0_data_b_mux[] = { 2111 HRX0_B_MARK, HTX0_B_MARK, 2112 }; 2113 static const unsigned int hscif0_ctrl_b_pins[] = { 2114 /* RTS, CTS */ 2115 RCAR_GP_PIN(1, 29), RCAR_GP_PIN(1, 28), 2116 }; 2117 static const unsigned int hscif0_ctrl_b_mux[] = { 2118 HRTS0_N_B_MARK, HCTS0_N_B_MARK, 2119 }; 2120 static const unsigned int hscif0_data_c_pins[] = { 2121 /* RX, TX */ 2122 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 16), 2123 }; 2124 static const unsigned int hscif0_data_c_mux[] = { 2125 HRX0_C_MARK, HTX0_C_MARK, 2126 }; 2127 static const unsigned int hscif0_ctrl_c_pins[] = { 2128 /* RTS, CTS */ 2129 RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 7), 2130 }; 2131 static const unsigned int hscif0_ctrl_c_mux[] = { 2132 HRTS0_N_C_MARK, HCTS0_N_C_MARK, 2133 }; 2134 static const unsigned int hscif0_data_d_pins[] = { 2135 /* RX, TX */ 2136 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21), 2137 }; 2138 static const unsigned int hscif0_data_d_mux[] = { 2139 HRX0_D_MARK, HTX0_D_MARK, 2140 }; 2141 static const unsigned int hscif0_ctrl_d_pins[] = { 2142 /* RTS, CTS */ 2143 RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 22), 2144 }; 2145 static const unsigned int hscif0_ctrl_d_mux[] = { 2146 HRTS0_N_D_MARK, HCTS0_N_D_MARK, 2147 }; 2148 static const unsigned int hscif0_data_e_pins[] = { 2149 /* RX, TX */ 2150 RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22), 2151 }; 2152 static const unsigned int hscif0_data_e_mux[] = { 2153 HRX0_E_MARK, HTX0_E_MARK, 2154 }; 2155 static const unsigned int hscif0_ctrl_e_pins[] = { 2156 /* RTS, CTS */ 2157 RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 23), 2158 }; 2159 static const unsigned int hscif0_ctrl_e_mux[] = { 2160 HRTS0_N_E_MARK, HCTS0_N_E_MARK, 2161 }; 2162 static const unsigned int hscif0_data_f_pins[] = { 2163 /* RX, TX */ 2164 RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 25), 2165 }; 2166 static const unsigned int hscif0_data_f_mux[] = { 2167 HRX0_F_MARK, HTX0_F_MARK, 2168 }; 2169 static const unsigned int hscif0_ctrl_f_pins[] = { 2170 /* RTS, CTS */ 2171 RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 24), 2172 }; 2173 static const unsigned int hscif0_ctrl_f_mux[] = { 2174 HRTS0_N_F_MARK, HCTS0_N_F_MARK, 2175 }; 2176 /* - HSCIF1 ----------------------------------------------------------------- */ 2177 static const unsigned int hscif1_data_pins[] = { 2178 /* RX, TX */ 2179 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29), 2180 }; 2181 static const unsigned int hscif1_data_mux[] = { 2182 HRX1_MARK, HTX1_MARK, 2183 }; 2184 static const unsigned int hscif1_clk_pins[] = { 2185 /* SCK */ 2186 RCAR_GP_PIN(4, 27), 2187 }; 2188 static const unsigned int hscif1_clk_mux[] = { 2189 HSCK1_MARK, 2190 }; 2191 static const unsigned int hscif1_ctrl_pins[] = { 2192 /* RTS, CTS */ 2193 RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30), 2194 }; 2195 static const unsigned int hscif1_ctrl_mux[] = { 2196 HRTS1_N_MARK, HCTS1_N_MARK, 2197 }; 2198 static const unsigned int hscif1_data_b_pins[] = { 2199 /* RX, TX */ 2200 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 18), 2201 }; 2202 static const unsigned int hscif1_data_b_mux[] = { 2203 HRX1_B_MARK, HTX1_B_MARK, 2204 }; 2205 static const unsigned int hscif1_clk_b_pins[] = { 2206 /* SCK */ 2207 RCAR_GP_PIN(1, 28), 2208 }; 2209 static const unsigned int hscif1_clk_b_mux[] = { 2210 HSCK1_B_MARK, 2211 }; 2212 static const unsigned int hscif1_ctrl_b_pins[] = { 2213 /* RTS, CTS */ 2214 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), 2215 }; 2216 static const unsigned int hscif1_ctrl_b_mux[] = { 2217 HRTS1_N_B_MARK, HCTS1_N_B_MARK, 2218 }; 2219 /* - I2C0 ------------------------------------------------------------------- */ 2220 static const unsigned int i2c0_pins[] = { 2221 /* SCL, SDA */ 2222 PIN_IIC0_SCL, PIN_IIC0_SDA, 2223 }; 2224 static const unsigned int i2c0_mux[] = { 2225 I2C0_SCL_MARK, I2C0_SDA_MARK, 2226 }; 2227 /* - I2C1 ------------------------------------------------------------------- */ 2228 static const unsigned int i2c1_pins[] = { 2229 /* SCL, SDA */ 2230 RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17), 2231 }; 2232 static const unsigned int i2c1_mux[] = { 2233 I2C1_SCL_MARK, I2C1_SDA_MARK, 2234 }; 2235 static const unsigned int i2c1_b_pins[] = { 2236 /* SCL, SDA */ 2237 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), 2238 }; 2239 static const unsigned int i2c1_b_mux[] = { 2240 I2C1_SCL_B_MARK, I2C1_SDA_B_MARK, 2241 }; 2242 static const unsigned int i2c1_c_pins[] = { 2243 /* SCL, SDA */ 2244 RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27), 2245 }; 2246 static const unsigned int i2c1_c_mux[] = { 2247 I2C1_SCL_C_MARK, I2C1_SDA_C_MARK, 2248 }; 2249 /* - I2C2 ------------------------------------------------------------------- */ 2250 static const unsigned int i2c2_pins[] = { 2251 /* SCL, SDA */ 2252 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6), 2253 }; 2254 static const unsigned int i2c2_mux[] = { 2255 I2C2_SCL_MARK, I2C2_SDA_MARK, 2256 }; 2257 static const unsigned int i2c2_b_pins[] = { 2258 /* SCL, SDA */ 2259 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1), 2260 }; 2261 static const unsigned int i2c2_b_mux[] = { 2262 I2C2_SCL_B_MARK, I2C2_SDA_B_MARK, 2263 }; 2264 static const unsigned int i2c2_c_pins[] = { 2265 /* SCL, SDA */ 2266 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), 2267 }; 2268 static const unsigned int i2c2_c_mux[] = { 2269 I2C2_SCL_C_MARK, I2C2_SDA_C_MARK, 2270 }; 2271 static const unsigned int i2c2_d_pins[] = { 2272 /* SCL, SDA */ 2273 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), 2274 }; 2275 static const unsigned int i2c2_d_mux[] = { 2276 I2C2_SCL_D_MARK, I2C2_SDA_D_MARK, 2277 }; 2278 static const unsigned int i2c2_e_pins[] = { 2279 /* SCL, SDA */ 2280 RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19), 2281 }; 2282 static const unsigned int i2c2_e_mux[] = { 2283 I2C2_SCL_E_MARK, I2C2_SDA_E_MARK, 2284 }; 2285 /* - I2C3 ------------------------------------------------------------------- */ 2286 static const unsigned int i2c3_pins[] = { 2287 /* SCL, SDA */ 2288 PIN_IIC3_SCL, PIN_IIC3_SDA, 2289 }; 2290 static const unsigned int i2c3_mux[] = { 2291 I2C3_SCL_MARK, I2C3_SDA_MARK, 2292 }; 2293 /* - IIC0 (I2C4) ------------------------------------------------------------ */ 2294 static const unsigned int iic0_pins[] = { 2295 /* SCL, SDA */ 2296 PIN_IIC0_SCL, PIN_IIC0_SDA, 2297 }; 2298 static const unsigned int iic0_mux[] = { 2299 IIC0_SCL_MARK, IIC0_SDA_MARK, 2300 }; 2301 /* - IIC1 (I2C5) ------------------------------------------------------------ */ 2302 static const unsigned int iic1_pins[] = { 2303 /* SCL, SDA */ 2304 RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17), 2305 }; 2306 static const unsigned int iic1_mux[] = { 2307 IIC1_SCL_MARK, IIC1_SDA_MARK, 2308 }; 2309 static const unsigned int iic1_b_pins[] = { 2310 /* SCL, SDA */ 2311 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), 2312 }; 2313 static const unsigned int iic1_b_mux[] = { 2314 IIC1_SCL_B_MARK, IIC1_SDA_B_MARK, 2315 }; 2316 static const unsigned int iic1_c_pins[] = { 2317 /* SCL, SDA */ 2318 RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27), 2319 }; 2320 static const unsigned int iic1_c_mux[] = { 2321 IIC1_SCL_C_MARK, IIC1_SDA_C_MARK, 2322 }; 2323 /* - IIC2 (I2C6) ------------------------------------------------------------ */ 2324 static const unsigned int iic2_pins[] = { 2325 /* SCL, SDA */ 2326 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6), 2327 }; 2328 static const unsigned int iic2_mux[] = { 2329 IIC2_SCL_MARK, IIC2_SDA_MARK, 2330 }; 2331 static const unsigned int iic2_b_pins[] = { 2332 /* SCL, SDA */ 2333 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1), 2334 }; 2335 static const unsigned int iic2_b_mux[] = { 2336 IIC2_SCL_B_MARK, IIC2_SDA_B_MARK, 2337 }; 2338 static const unsigned int iic2_c_pins[] = { 2339 /* SCL, SDA */ 2340 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), 2341 }; 2342 static const unsigned int iic2_c_mux[] = { 2343 IIC2_SCL_C_MARK, IIC2_SDA_C_MARK, 2344 }; 2345 static const unsigned int iic2_d_pins[] = { 2346 /* SCL, SDA */ 2347 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), 2348 }; 2349 static const unsigned int iic2_d_mux[] = { 2350 IIC2_SCL_D_MARK, IIC2_SDA_D_MARK, 2351 }; 2352 static const unsigned int iic2_e_pins[] = { 2353 /* SCL, SDA */ 2354 RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19), 2355 }; 2356 static const unsigned int iic2_e_mux[] = { 2357 IIC2_SCL_E_MARK, IIC2_SDA_E_MARK, 2358 }; 2359 /* - IIC3 (I2C7) ------------------------------------------------------------ */ 2360 static const unsigned int iic3_pins[] = { 2361 /* SCL, SDA */ 2362 PIN_IIC3_SCL, PIN_IIC3_SDA, 2363 }; 2364 static const unsigned int iic3_mux[] = { 2365 IIC3_SCL_MARK, IIC3_SDA_MARK, 2366 }; 2367 /* - INTC ------------------------------------------------------------------- */ 2368 static const unsigned int intc_irq0_pins[] = { 2369 /* IRQ */ 2370 RCAR_GP_PIN(1, 25), 2371 }; 2372 static const unsigned int intc_irq0_mux[] = { 2373 IRQ0_MARK, 2374 }; 2375 static const unsigned int intc_irq1_pins[] = { 2376 /* IRQ */ 2377 RCAR_GP_PIN(1, 27), 2378 }; 2379 static const unsigned int intc_irq1_mux[] = { 2380 IRQ1_MARK, 2381 }; 2382 static const unsigned int intc_irq2_pins[] = { 2383 /* IRQ */ 2384 RCAR_GP_PIN(1, 29), 2385 }; 2386 static const unsigned int intc_irq2_mux[] = { 2387 IRQ2_MARK, 2388 }; 2389 static const unsigned int intc_irq3_pins[] = { 2390 /* IRQ */ 2391 RCAR_GP_PIN(1, 23), 2392 }; 2393 static const unsigned int intc_irq3_mux[] = { 2394 IRQ3_MARK, 2395 }; 2396 /* - MLB+ ------------------------------------------------------------------- */ 2397 static const unsigned int mlb_3pin_pins[] = { 2398 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2), 2399 }; 2400 static const unsigned int mlb_3pin_mux[] = { 2401 MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK, 2402 }; 2403 /* - MMCIF0 ----------------------------------------------------------------- */ 2404 static const unsigned int mmc0_data1_pins[] = { 2405 /* D[0] */ 2406 RCAR_GP_PIN(3, 18), 2407 }; 2408 static const unsigned int mmc0_data1_mux[] = { 2409 MMC0_D0_MARK, 2410 }; 2411 static const unsigned int mmc0_data4_pins[] = { 2412 /* D[0:3] */ 2413 RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), 2414 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21), 2415 }; 2416 static const unsigned int mmc0_data4_mux[] = { 2417 MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK, 2418 }; 2419 static const unsigned int mmc0_data8_pins[] = { 2420 /* D[0:7] */ 2421 RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), 2422 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21), 2423 RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23), 2424 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), 2425 }; 2426 static const unsigned int mmc0_data8_mux[] = { 2427 MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK, 2428 MMC0_D4_MARK, MMC0_D5_MARK, MMC0_D6_MARK, MMC0_D7_MARK, 2429 }; 2430 static const unsigned int mmc0_ctrl_pins[] = { 2431 /* CLK, CMD */ 2432 RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17), 2433 }; 2434 static const unsigned int mmc0_ctrl_mux[] = { 2435 MMC0_CLK_MARK, MMC0_CMD_MARK, 2436 }; 2437 /* - MMCIF1 ----------------------------------------------------------------- */ 2438 static const unsigned int mmc1_data1_pins[] = { 2439 /* D[0] */ 2440 RCAR_GP_PIN(3, 26), 2441 }; 2442 static const unsigned int mmc1_data1_mux[] = { 2443 MMC1_D0_MARK, 2444 }; 2445 static const unsigned int mmc1_data4_pins[] = { 2446 /* D[0:3] */ 2447 RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27), 2448 RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29), 2449 }; 2450 static const unsigned int mmc1_data4_mux[] = { 2451 MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK, 2452 }; 2453 static const unsigned int mmc1_data8_pins[] = { 2454 /* D[0:7] */ 2455 RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27), 2456 RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29), 2457 RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31), 2458 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), 2459 }; 2460 static const unsigned int mmc1_data8_mux[] = { 2461 MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK, 2462 MMC1_D4_MARK, MMC1_D5_MARK, MMC1_D6_MARK, MMC1_D7_MARK, 2463 }; 2464 static const unsigned int mmc1_ctrl_pins[] = { 2465 /* CLK, CMD */ 2466 RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25), 2467 }; 2468 static const unsigned int mmc1_ctrl_mux[] = { 2469 MMC1_CLK_MARK, MMC1_CMD_MARK, 2470 }; 2471 /* - MSIOF0 ----------------------------------------------------------------- */ 2472 static const unsigned int msiof0_clk_pins[] = { 2473 /* SCK */ 2474 RCAR_GP_PIN(5, 12), 2475 }; 2476 static const unsigned int msiof0_clk_mux[] = { 2477 MSIOF0_SCK_MARK, 2478 }; 2479 static const unsigned int msiof0_sync_pins[] = { 2480 /* SYNC */ 2481 RCAR_GP_PIN(5, 13), 2482 }; 2483 static const unsigned int msiof0_sync_mux[] = { 2484 MSIOF0_SYNC_MARK, 2485 }; 2486 static const unsigned int msiof0_ss1_pins[] = { 2487 /* SS1 */ 2488 RCAR_GP_PIN(5, 14), 2489 }; 2490 static const unsigned int msiof0_ss1_mux[] = { 2491 MSIOF0_SS1_MARK, 2492 }; 2493 static const unsigned int msiof0_ss2_pins[] = { 2494 /* SS2 */ 2495 RCAR_GP_PIN(5, 16), 2496 }; 2497 static const unsigned int msiof0_ss2_mux[] = { 2498 MSIOF0_SS2_MARK, 2499 }; 2500 static const unsigned int msiof0_rx_pins[] = { 2501 /* RXD */ 2502 RCAR_GP_PIN(5, 17), 2503 }; 2504 static const unsigned int msiof0_rx_mux[] = { 2505 MSIOF0_RXD_MARK, 2506 }; 2507 static const unsigned int msiof0_tx_pins[] = { 2508 /* TXD */ 2509 RCAR_GP_PIN(5, 15), 2510 }; 2511 static const unsigned int msiof0_tx_mux[] = { 2512 MSIOF0_TXD_MARK, 2513 }; 2514 2515 static const unsigned int msiof0_clk_b_pins[] = { 2516 /* SCK */ 2517 RCAR_GP_PIN(1, 23), 2518 }; 2519 static const unsigned int msiof0_clk_b_mux[] = { 2520 MSIOF0_SCK_B_MARK, 2521 }; 2522 static const unsigned int msiof0_ss1_b_pins[] = { 2523 /* SS1 */ 2524 RCAR_GP_PIN(1, 12), 2525 }; 2526 static const unsigned int msiof0_ss1_b_mux[] = { 2527 MSIOF0_SS1_B_MARK, 2528 }; 2529 static const unsigned int msiof0_ss2_b_pins[] = { 2530 /* SS2 */ 2531 RCAR_GP_PIN(1, 10), 2532 }; 2533 static const unsigned int msiof0_ss2_b_mux[] = { 2534 MSIOF0_SS2_B_MARK, 2535 }; 2536 static const unsigned int msiof0_rx_b_pins[] = { 2537 /* RXD */ 2538 RCAR_GP_PIN(1, 29), 2539 }; 2540 static const unsigned int msiof0_rx_b_mux[] = { 2541 MSIOF0_RXD_B_MARK, 2542 }; 2543 static const unsigned int msiof0_tx_b_pins[] = { 2544 /* TXD */ 2545 RCAR_GP_PIN(1, 28), 2546 }; 2547 static const unsigned int msiof0_tx_b_mux[] = { 2548 MSIOF0_TXD_B_MARK, 2549 }; 2550 /* - MSIOF1 ----------------------------------------------------------------- */ 2551 static const unsigned int msiof1_clk_pins[] = { 2552 /* SCK */ 2553 RCAR_GP_PIN(4, 8), 2554 }; 2555 static const unsigned int msiof1_clk_mux[] = { 2556 MSIOF1_SCK_MARK, 2557 }; 2558 static const unsigned int msiof1_sync_pins[] = { 2559 /* SYNC */ 2560 RCAR_GP_PIN(4, 9), 2561 }; 2562 static const unsigned int msiof1_sync_mux[] = { 2563 MSIOF1_SYNC_MARK, 2564 }; 2565 static const unsigned int msiof1_ss1_pins[] = { 2566 /* SS1 */ 2567 RCAR_GP_PIN(4, 10), 2568 }; 2569 static const unsigned int msiof1_ss1_mux[] = { 2570 MSIOF1_SS1_MARK, 2571 }; 2572 static const unsigned int msiof1_ss2_pins[] = { 2573 /* SS2 */ 2574 RCAR_GP_PIN(4, 11), 2575 }; 2576 static const unsigned int msiof1_ss2_mux[] = { 2577 MSIOF1_SS2_MARK, 2578 }; 2579 static const unsigned int msiof1_rx_pins[] = { 2580 /* RXD */ 2581 RCAR_GP_PIN(4, 13), 2582 }; 2583 static const unsigned int msiof1_rx_mux[] = { 2584 MSIOF1_RXD_MARK, 2585 }; 2586 static const unsigned int msiof1_tx_pins[] = { 2587 /* TXD */ 2588 RCAR_GP_PIN(4, 12), 2589 }; 2590 static const unsigned int msiof1_tx_mux[] = { 2591 MSIOF1_TXD_MARK, 2592 }; 2593 2594 static const unsigned int msiof1_clk_b_pins[] = { 2595 /* SCK */ 2596 RCAR_GP_PIN(1, 16), 2597 }; 2598 static const unsigned int msiof1_clk_b_mux[] = { 2599 MSIOF1_SCK_B_MARK, 2600 }; 2601 static const unsigned int msiof1_ss1_b_pins[] = { 2602 /* SS1 */ 2603 RCAR_GP_PIN(0, 18), 2604 }; 2605 static const unsigned int msiof1_ss1_b_mux[] = { 2606 MSIOF1_SS1_B_MARK, 2607 }; 2608 static const unsigned int msiof1_ss2_b_pins[] = { 2609 /* SS2 */ 2610 RCAR_GP_PIN(0, 19), 2611 }; 2612 static const unsigned int msiof1_ss2_b_mux[] = { 2613 MSIOF1_SS2_B_MARK, 2614 }; 2615 static const unsigned int msiof1_rx_b_pins[] = { 2616 /* RXD */ 2617 RCAR_GP_PIN(1, 17), 2618 }; 2619 static const unsigned int msiof1_rx_b_mux[] = { 2620 MSIOF1_RXD_B_MARK, 2621 }; 2622 static const unsigned int msiof1_tx_b_pins[] = { 2623 /* TXD */ 2624 RCAR_GP_PIN(0, 20), 2625 }; 2626 static const unsigned int msiof1_tx_b_mux[] = { 2627 MSIOF1_TXD_B_MARK, 2628 }; 2629 /* - MSIOF2 ----------------------------------------------------------------- */ 2630 static const unsigned int msiof2_clk_pins[] = { 2631 /* SCK */ 2632 RCAR_GP_PIN(0, 27), 2633 }; 2634 static const unsigned int msiof2_clk_mux[] = { 2635 MSIOF2_SCK_MARK, 2636 }; 2637 static const unsigned int msiof2_sync_pins[] = { 2638 /* SYNC */ 2639 RCAR_GP_PIN(0, 26), 2640 }; 2641 static const unsigned int msiof2_sync_mux[] = { 2642 MSIOF2_SYNC_MARK, 2643 }; 2644 static const unsigned int msiof2_ss1_pins[] = { 2645 /* SS1 */ 2646 RCAR_GP_PIN(0, 30), 2647 }; 2648 static const unsigned int msiof2_ss1_mux[] = { 2649 MSIOF2_SS1_MARK, 2650 }; 2651 static const unsigned int msiof2_ss2_pins[] = { 2652 /* SS2 */ 2653 RCAR_GP_PIN(0, 31), 2654 }; 2655 static const unsigned int msiof2_ss2_mux[] = { 2656 MSIOF2_SS2_MARK, 2657 }; 2658 static const unsigned int msiof2_rx_pins[] = { 2659 /* RXD */ 2660 RCAR_GP_PIN(0, 29), 2661 }; 2662 static const unsigned int msiof2_rx_mux[] = { 2663 MSIOF2_RXD_MARK, 2664 }; 2665 static const unsigned int msiof2_tx_pins[] = { 2666 /* TXD */ 2667 RCAR_GP_PIN(0, 28), 2668 }; 2669 static const unsigned int msiof2_tx_mux[] = { 2670 MSIOF2_TXD_MARK, 2671 }; 2672 /* - MSIOF3 ----------------------------------------------------------------- */ 2673 static const unsigned int msiof3_clk_pins[] = { 2674 /* SCK */ 2675 RCAR_GP_PIN(5, 4), 2676 }; 2677 static const unsigned int msiof3_clk_mux[] = { 2678 MSIOF3_SCK_MARK, 2679 }; 2680 static const unsigned int msiof3_sync_pins[] = { 2681 /* SYNC */ 2682 RCAR_GP_PIN(4, 30), 2683 }; 2684 static const unsigned int msiof3_sync_mux[] = { 2685 MSIOF3_SYNC_MARK, 2686 }; 2687 static const unsigned int msiof3_ss1_pins[] = { 2688 /* SS1 */ 2689 RCAR_GP_PIN(4, 31), 2690 }; 2691 static const unsigned int msiof3_ss1_mux[] = { 2692 MSIOF3_SS1_MARK, 2693 }; 2694 static const unsigned int msiof3_ss2_pins[] = { 2695 /* SS2 */ 2696 RCAR_GP_PIN(4, 27), 2697 }; 2698 static const unsigned int msiof3_ss2_mux[] = { 2699 MSIOF3_SS2_MARK, 2700 }; 2701 static const unsigned int msiof3_rx_pins[] = { 2702 /* RXD */ 2703 RCAR_GP_PIN(5, 2), 2704 }; 2705 static const unsigned int msiof3_rx_mux[] = { 2706 MSIOF3_RXD_MARK, 2707 }; 2708 static const unsigned int msiof3_tx_pins[] = { 2709 /* TXD */ 2710 RCAR_GP_PIN(5, 3), 2711 }; 2712 static const unsigned int msiof3_tx_mux[] = { 2713 MSIOF3_TXD_MARK, 2714 }; 2715 2716 static const unsigned int msiof3_clk_b_pins[] = { 2717 /* SCK */ 2718 RCAR_GP_PIN(0, 0), 2719 }; 2720 static const unsigned int msiof3_clk_b_mux[] = { 2721 MSIOF3_SCK_B_MARK, 2722 }; 2723 static const unsigned int msiof3_sync_b_pins[] = { 2724 /* SYNC */ 2725 RCAR_GP_PIN(0, 1), 2726 }; 2727 static const unsigned int msiof3_sync_b_mux[] = { 2728 MSIOF3_SYNC_B_MARK, 2729 }; 2730 static const unsigned int msiof3_rx_b_pins[] = { 2731 /* RXD */ 2732 RCAR_GP_PIN(0, 2), 2733 }; 2734 static const unsigned int msiof3_rx_b_mux[] = { 2735 MSIOF3_RXD_B_MARK, 2736 }; 2737 static const unsigned int msiof3_tx_b_pins[] = { 2738 /* TXD */ 2739 RCAR_GP_PIN(0, 3), 2740 }; 2741 static const unsigned int msiof3_tx_b_mux[] = { 2742 MSIOF3_TXD_B_MARK, 2743 }; 2744 /* - PWM -------------------------------------------------------------------- */ 2745 static const unsigned int pwm0_pins[] = { 2746 RCAR_GP_PIN(5, 29), 2747 }; 2748 static const unsigned int pwm0_mux[] = { 2749 PWM0_MARK, 2750 }; 2751 static const unsigned int pwm0_b_pins[] = { 2752 RCAR_GP_PIN(4, 30), 2753 }; 2754 static const unsigned int pwm0_b_mux[] = { 2755 PWM0_B_MARK, 2756 }; 2757 static const unsigned int pwm1_pins[] = { 2758 RCAR_GP_PIN(5, 30), 2759 }; 2760 static const unsigned int pwm1_mux[] = { 2761 PWM1_MARK, 2762 }; 2763 static const unsigned int pwm1_b_pins[] = { 2764 RCAR_GP_PIN(4, 31), 2765 }; 2766 static const unsigned int pwm1_b_mux[] = { 2767 PWM1_B_MARK, 2768 }; 2769 static const unsigned int pwm2_pins[] = { 2770 RCAR_GP_PIN(5, 31), 2771 }; 2772 static const unsigned int pwm2_mux[] = { 2773 PWM2_MARK, 2774 }; 2775 static const unsigned int pwm3_pins[] = { 2776 RCAR_GP_PIN(0, 16), 2777 }; 2778 static const unsigned int pwm3_mux[] = { 2779 PWM3_MARK, 2780 }; 2781 static const unsigned int pwm4_pins[] = { 2782 RCAR_GP_PIN(0, 17), 2783 }; 2784 static const unsigned int pwm4_mux[] = { 2785 PWM4_MARK, 2786 }; 2787 static const unsigned int pwm5_pins[] = { 2788 RCAR_GP_PIN(0, 18), 2789 }; 2790 static const unsigned int pwm5_mux[] = { 2791 PWM5_MARK, 2792 }; 2793 static const unsigned int pwm6_pins[] = { 2794 RCAR_GP_PIN(0, 19), 2795 }; 2796 static const unsigned int pwm6_mux[] = { 2797 PWM6_MARK, 2798 }; 2799 /* - QSPI ------------------------------------------------------------------- */ 2800 static const unsigned int qspi_ctrl_pins[] = { 2801 /* SPCLK, SSL */ 2802 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 9), 2803 }; 2804 static const unsigned int qspi_ctrl_mux[] = { 2805 SPCLK_MARK, SSL_MARK, 2806 }; 2807 static const unsigned int qspi_data2_pins[] = { 2808 /* MOSI_IO0, MISO_IO1 */ 2809 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), 2810 }; 2811 static const unsigned int qspi_data2_mux[] = { 2812 MOSI_IO0_MARK, MISO_IO1_MARK, 2813 }; 2814 static const unsigned int qspi_data4_pins[] = { 2815 /* MOSI_IO0, MISO_IO1, IO2, IO3 */ 2816 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 2817 RCAR_GP_PIN(1, 8), 2818 }; 2819 static const unsigned int qspi_data4_mux[] = { 2820 MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK, 2821 }; 2822 /* - SCIF0 ------------------------------------------------------------------ */ 2823 static const unsigned int scif0_data_pins[] = { 2824 /* RX, TX */ 2825 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29), 2826 }; 2827 static const unsigned int scif0_data_mux[] = { 2828 RX0_MARK, TX0_MARK, 2829 }; 2830 static const unsigned int scif0_clk_pins[] = { 2831 /* SCK */ 2832 RCAR_GP_PIN(4, 27), 2833 }; 2834 static const unsigned int scif0_clk_mux[] = { 2835 SCK0_MARK, 2836 }; 2837 static const unsigned int scif0_ctrl_pins[] = { 2838 /* RTS, CTS */ 2839 RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30), 2840 }; 2841 static const unsigned int scif0_ctrl_mux[] = { 2842 RTS0_N_MARK, CTS0_N_MARK, 2843 }; 2844 static const unsigned int scif0_data_b_pins[] = { 2845 /* RX, TX */ 2846 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), 2847 }; 2848 static const unsigned int scif0_data_b_mux[] = { 2849 RX0_B_MARK, TX0_B_MARK, 2850 }; 2851 /* - SCIF1 ------------------------------------------------------------------ */ 2852 static const unsigned int scif1_data_pins[] = { 2853 /* RX, TX */ 2854 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1), 2855 }; 2856 static const unsigned int scif1_data_mux[] = { 2857 RX1_MARK, TX1_MARK, 2858 }; 2859 static const unsigned int scif1_clk_pins[] = { 2860 /* SCK */ 2861 RCAR_GP_PIN(4, 20), 2862 }; 2863 static const unsigned int scif1_clk_mux[] = { 2864 SCK1_MARK, 2865 }; 2866 static const unsigned int scif1_ctrl_pins[] = { 2867 /* RTS, CTS */ 2868 RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 2), 2869 }; 2870 static const unsigned int scif1_ctrl_mux[] = { 2871 RTS1_N_MARK, CTS1_N_MARK, 2872 }; 2873 static const unsigned int scif1_data_b_pins[] = { 2874 /* RX, TX */ 2875 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), 2876 }; 2877 static const unsigned int scif1_data_b_mux[] = { 2878 RX1_B_MARK, TX1_B_MARK, 2879 }; 2880 static const unsigned int scif1_data_c_pins[] = { 2881 /* RX, TX */ 2882 RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2), 2883 }; 2884 static const unsigned int scif1_data_c_mux[] = { 2885 RX1_C_MARK, TX1_C_MARK, 2886 }; 2887 static const unsigned int scif1_data_d_pins[] = { 2888 /* RX, TX */ 2889 RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), 2890 }; 2891 static const unsigned int scif1_data_d_mux[] = { 2892 RX1_D_MARK, TX1_D_MARK, 2893 }; 2894 static const unsigned int scif1_clk_d_pins[] = { 2895 /* SCK */ 2896 RCAR_GP_PIN(3, 17), 2897 }; 2898 static const unsigned int scif1_clk_d_mux[] = { 2899 SCK1_D_MARK, 2900 }; 2901 static const unsigned int scif1_data_e_pins[] = { 2902 /* RX, TX */ 2903 RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22), 2904 }; 2905 static const unsigned int scif1_data_e_mux[] = { 2906 RX1_E_MARK, TX1_E_MARK, 2907 }; 2908 static const unsigned int scif1_clk_e_pins[] = { 2909 /* SCK */ 2910 RCAR_GP_PIN(2, 20), 2911 }; 2912 static const unsigned int scif1_clk_e_mux[] = { 2913 SCK1_E_MARK, 2914 }; 2915 /* - SCIF2 ------------------------------------------------------------------ */ 2916 static const unsigned int scif2_data_pins[] = { 2917 /* RX, TX */ 2918 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 5), 2919 }; 2920 static const unsigned int scif2_data_mux[] = { 2921 RX2_MARK, TX2_MARK, 2922 }; 2923 static const unsigned int scif2_clk_pins[] = { 2924 /* SCK */ 2925 RCAR_GP_PIN(5, 4), 2926 }; 2927 static const unsigned int scif2_clk_mux[] = { 2928 SCK2_MARK, 2929 }; 2930 static const unsigned int scif2_data_b_pins[] = { 2931 /* RX, TX */ 2932 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25), 2933 }; 2934 static const unsigned int scif2_data_b_mux[] = { 2935 RX2_B_MARK, TX2_B_MARK, 2936 }; 2937 /* - SCIFA0 ----------------------------------------------------------------- */ 2938 static const unsigned int scifa0_data_pins[] = { 2939 /* RXD, TXD */ 2940 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29), 2941 }; 2942 static const unsigned int scifa0_data_mux[] = { 2943 SCIFA0_RXD_MARK, SCIFA0_TXD_MARK, 2944 }; 2945 static const unsigned int scifa0_clk_pins[] = { 2946 /* SCK */ 2947 RCAR_GP_PIN(4, 27), 2948 }; 2949 static const unsigned int scifa0_clk_mux[] = { 2950 SCIFA0_SCK_MARK, 2951 }; 2952 static const unsigned int scifa0_ctrl_pins[] = { 2953 /* RTS, CTS */ 2954 RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30), 2955 }; 2956 static const unsigned int scifa0_ctrl_mux[] = { 2957 SCIFA0_RTS_N_MARK, SCIFA0_CTS_N_MARK, 2958 }; 2959 static const unsigned int scifa0_data_b_pins[] = { 2960 /* RXD, TXD */ 2961 RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21), 2962 }; 2963 static const unsigned int scifa0_data_b_mux[] = { 2964 SCIFA0_RXD_B_MARK, SCIFA0_TXD_B_MARK 2965 }; 2966 static const unsigned int scifa0_clk_b_pins[] = { 2967 /* SCK */ 2968 RCAR_GP_PIN(1, 19), 2969 }; 2970 static const unsigned int scifa0_clk_b_mux[] = { 2971 SCIFA0_SCK_B_MARK, 2972 }; 2973 static const unsigned int scifa0_ctrl_b_pins[] = { 2974 /* RTS, CTS */ 2975 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22), 2976 }; 2977 static const unsigned int scifa0_ctrl_b_mux[] = { 2978 SCIFA0_RTS_N_B_MARK, SCIFA0_CTS_N_B_MARK, 2979 }; 2980 /* - SCIFA1 ----------------------------------------------------------------- */ 2981 static const unsigned int scifa1_data_pins[] = { 2982 /* RXD, TXD */ 2983 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1), 2984 }; 2985 static const unsigned int scifa1_data_mux[] = { 2986 SCIFA1_RXD_MARK, SCIFA1_TXD_MARK, 2987 }; 2988 static const unsigned int scifa1_clk_pins[] = { 2989 /* SCK */ 2990 RCAR_GP_PIN(4, 20), 2991 }; 2992 static const unsigned int scifa1_clk_mux[] = { 2993 SCIFA1_SCK_MARK, 2994 }; 2995 static const unsigned int scifa1_ctrl_pins[] = { 2996 /* RTS, CTS */ 2997 RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 2), 2998 }; 2999 static const unsigned int scifa1_ctrl_mux[] = { 3000 SCIFA1_RTS_N_MARK, SCIFA1_CTS_N_MARK, 3001 }; 3002 static const unsigned int scifa1_data_b_pins[] = { 3003 /* RXD, TXD */ 3004 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 21), 3005 }; 3006 static const unsigned int scifa1_data_b_mux[] = { 3007 SCIFA1_RXD_B_MARK, SCIFA1_TXD_B_MARK, 3008 }; 3009 static const unsigned int scifa1_clk_b_pins[] = { 3010 /* SCK */ 3011 RCAR_GP_PIN(0, 23), 3012 }; 3013 static const unsigned int scifa1_clk_b_mux[] = { 3014 SCIFA1_SCK_B_MARK, 3015 }; 3016 static const unsigned int scifa1_ctrl_b_pins[] = { 3017 /* RTS, CTS */ 3018 RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 25), 3019 }; 3020 static const unsigned int scifa1_ctrl_b_mux[] = { 3021 SCIFA1_RTS_N_B_MARK, SCIFA1_CTS_N_B_MARK, 3022 }; 3023 static const unsigned int scifa1_data_c_pins[] = { 3024 /* RXD, TXD */ 3025 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10), 3026 }; 3027 static const unsigned int scifa1_data_c_mux[] = { 3028 SCIFA1_RXD_C_MARK, SCIFA1_TXD_C_MARK, 3029 }; 3030 static const unsigned int scifa1_clk_c_pins[] = { 3031 /* SCK */ 3032 RCAR_GP_PIN(0, 8), 3033 }; 3034 static const unsigned int scifa1_clk_c_mux[] = { 3035 SCIFA1_SCK_C_MARK, 3036 }; 3037 static const unsigned int scifa1_ctrl_c_pins[] = { 3038 /* RTS, CTS */ 3039 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), 3040 }; 3041 static const unsigned int scifa1_ctrl_c_mux[] = { 3042 SCIFA1_RTS_N_C_MARK, SCIFA1_CTS_N_C_MARK, 3043 }; 3044 static const unsigned int scifa1_data_d_pins[] = { 3045 /* RXD, TXD */ 3046 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12), 3047 }; 3048 static const unsigned int scifa1_data_d_mux[] = { 3049 SCIFA1_RXD_D_MARK, SCIFA1_TXD_D_MARK, 3050 }; 3051 static const unsigned int scifa1_clk_d_pins[] = { 3052 /* SCK */ 3053 RCAR_GP_PIN(2, 10), 3054 }; 3055 static const unsigned int scifa1_clk_d_mux[] = { 3056 SCIFA1_SCK_D_MARK, 3057 }; 3058 static const unsigned int scifa1_ctrl_d_pins[] = { 3059 /* RTS, CTS */ 3060 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13), 3061 }; 3062 static const unsigned int scifa1_ctrl_d_mux[] = { 3063 SCIFA1_RTS_N_D_MARK, SCIFA1_CTS_N_D_MARK, 3064 }; 3065 /* - SCIFA2 ----------------------------------------------------------------- */ 3066 static const unsigned int scifa2_data_pins[] = { 3067 /* RXD, TXD */ 3068 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6), 3069 }; 3070 static const unsigned int scifa2_data_mux[] = { 3071 SCIFA2_RXD_MARK, SCIFA2_TXD_MARK, 3072 }; 3073 static const unsigned int scifa2_clk_pins[] = { 3074 /* SCK */ 3075 RCAR_GP_PIN(5, 4), 3076 }; 3077 static const unsigned int scifa2_clk_mux[] = { 3078 SCIFA2_SCK_MARK, 3079 }; 3080 static const unsigned int scifa2_ctrl_pins[] = { 3081 /* RTS, CTS */ 3082 RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 21), 3083 }; 3084 static const unsigned int scifa2_ctrl_mux[] = { 3085 SCIFA2_RTS_N_MARK, SCIFA2_CTS_N_MARK, 3086 }; 3087 static const unsigned int scifa2_data_b_pins[] = { 3088 /* RXD, TXD */ 3089 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 16), 3090 }; 3091 static const unsigned int scifa2_data_b_mux[] = { 3092 SCIFA2_RXD_B_MARK, SCIFA2_TXD_B_MARK, 3093 }; 3094 static const unsigned int scifa2_data_c_pins[] = { 3095 /* RXD, TXD */ 3096 RCAR_GP_PIN(5, 31), RCAR_GP_PIN(5, 30), 3097 }; 3098 static const unsigned int scifa2_data_c_mux[] = { 3099 SCIFA2_RXD_C_MARK, SCIFA2_TXD_C_MARK, 3100 }; 3101 static const unsigned int scifa2_clk_c_pins[] = { 3102 /* SCK */ 3103 RCAR_GP_PIN(5, 29), 3104 }; 3105 static const unsigned int scifa2_clk_c_mux[] = { 3106 SCIFA2_SCK_C_MARK, 3107 }; 3108 /* - SCIFB0 ----------------------------------------------------------------- */ 3109 static const unsigned int scifb0_data_pins[] = { 3110 /* RXD, TXD */ 3111 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10), 3112 }; 3113 static const unsigned int scifb0_data_mux[] = { 3114 SCIFB0_RXD_MARK, SCIFB0_TXD_MARK, 3115 }; 3116 static const unsigned int scifb0_clk_pins[] = { 3117 /* SCK */ 3118 RCAR_GP_PIN(4, 8), 3119 }; 3120 static const unsigned int scifb0_clk_mux[] = { 3121 SCIFB0_SCK_MARK, 3122 }; 3123 static const unsigned int scifb0_ctrl_pins[] = { 3124 /* RTS, CTS */ 3125 RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 11), 3126 }; 3127 static const unsigned int scifb0_ctrl_mux[] = { 3128 SCIFB0_RTS_N_MARK, SCIFB0_CTS_N_MARK, 3129 }; 3130 static const unsigned int scifb0_data_b_pins[] = { 3131 /* RXD, TXD */ 3132 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), 3133 }; 3134 static const unsigned int scifb0_data_b_mux[] = { 3135 SCIFB0_RXD_B_MARK, SCIFB0_TXD_B_MARK, 3136 }; 3137 static const unsigned int scifb0_clk_b_pins[] = { 3138 /* SCK */ 3139 RCAR_GP_PIN(3, 9), 3140 }; 3141 static const unsigned int scifb0_clk_b_mux[] = { 3142 SCIFB0_SCK_B_MARK, 3143 }; 3144 static const unsigned int scifb0_ctrl_b_pins[] = { 3145 /* RTS, CTS */ 3146 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12), 3147 }; 3148 static const unsigned int scifb0_ctrl_b_mux[] = { 3149 SCIFB0_RTS_N_B_MARK, SCIFB0_CTS_N_B_MARK, 3150 }; 3151 static const unsigned int scifb0_data_c_pins[] = { 3152 /* RXD, TXD */ 3153 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), 3154 }; 3155 static const unsigned int scifb0_data_c_mux[] = { 3156 SCIFB0_RXD_C_MARK, SCIFB0_TXD_C_MARK, 3157 }; 3158 /* - SCIFB1 ----------------------------------------------------------------- */ 3159 static const unsigned int scifb1_data_pins[] = { 3160 /* RXD, TXD */ 3161 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16), 3162 }; 3163 static const unsigned int scifb1_data_mux[] = { 3164 SCIFB1_RXD_MARK, SCIFB1_TXD_MARK, 3165 }; 3166 static const unsigned int scifb1_clk_pins[] = { 3167 /* SCK */ 3168 RCAR_GP_PIN(4, 14), 3169 }; 3170 static const unsigned int scifb1_clk_mux[] = { 3171 SCIFB1_SCK_MARK, 3172 }; 3173 static const unsigned int scifb1_ctrl_pins[] = { 3174 /* RTS, CTS */ 3175 RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17), 3176 }; 3177 static const unsigned int scifb1_ctrl_mux[] = { 3178 SCIFB1_RTS_N_MARK, SCIFB1_CTS_N_MARK, 3179 }; 3180 static const unsigned int scifb1_data_b_pins[] = { 3181 /* RXD, TXD */ 3182 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), 3183 }; 3184 static const unsigned int scifb1_data_b_mux[] = { 3185 SCIFB1_RXD_B_MARK, SCIFB1_TXD_B_MARK, 3186 }; 3187 static const unsigned int scifb1_clk_b_pins[] = { 3188 /* SCK */ 3189 RCAR_GP_PIN(3, 1), 3190 }; 3191 static const unsigned int scifb1_clk_b_mux[] = { 3192 SCIFB1_SCK_B_MARK, 3193 }; 3194 static const unsigned int scifb1_ctrl_b_pins[] = { 3195 /* RTS, CTS */ 3196 RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 4), 3197 }; 3198 static const unsigned int scifb1_ctrl_b_mux[] = { 3199 SCIFB1_RTS_N_B_MARK, SCIFB1_CTS_N_B_MARK, 3200 }; 3201 static const unsigned int scifb1_data_c_pins[] = { 3202 /* RXD, TXD */ 3203 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), 3204 }; 3205 static const unsigned int scifb1_data_c_mux[] = { 3206 SCIFB1_RXD_C_MARK, SCIFB1_TXD_C_MARK, 3207 }; 3208 static const unsigned int scifb1_data_d_pins[] = { 3209 /* RXD, TXD */ 3210 RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2), 3211 }; 3212 static const unsigned int scifb1_data_d_mux[] = { 3213 SCIFB1_RXD_D_MARK, SCIFB1_TXD_D_MARK, 3214 }; 3215 static const unsigned int scifb1_data_e_pins[] = { 3216 /* RXD, TXD */ 3217 RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), 3218 }; 3219 static const unsigned int scifb1_data_e_mux[] = { 3220 SCIFB1_RXD_E_MARK, SCIFB1_TXD_E_MARK, 3221 }; 3222 static const unsigned int scifb1_clk_e_pins[] = { 3223 /* SCK */ 3224 RCAR_GP_PIN(3, 17), 3225 }; 3226 static const unsigned int scifb1_clk_e_mux[] = { 3227 SCIFB1_SCK_E_MARK, 3228 }; 3229 static const unsigned int scifb1_data_f_pins[] = { 3230 /* RXD, TXD */ 3231 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), 3232 }; 3233 static const unsigned int scifb1_data_f_mux[] = { 3234 SCIFB1_RXD_F_MARK, SCIFB1_TXD_F_MARK, 3235 }; 3236 static const unsigned int scifb1_data_g_pins[] = { 3237 /* RXD, TXD */ 3238 RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22), 3239 }; 3240 static const unsigned int scifb1_data_g_mux[] = { 3241 SCIFB1_RXD_G_MARK, SCIFB1_TXD_G_MARK, 3242 }; 3243 static const unsigned int scifb1_clk_g_pins[] = { 3244 /* SCK */ 3245 RCAR_GP_PIN(2, 20), 3246 }; 3247 static const unsigned int scifb1_clk_g_mux[] = { 3248 SCIFB1_SCK_G_MARK, 3249 }; 3250 /* - SCIFB2 ----------------------------------------------------------------- */ 3251 static const unsigned int scifb2_data_pins[] = { 3252 /* RXD, TXD */ 3253 RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23), 3254 }; 3255 static const unsigned int scifb2_data_mux[] = { 3256 SCIFB2_RXD_MARK, SCIFB2_TXD_MARK, 3257 }; 3258 static const unsigned int scifb2_clk_pins[] = { 3259 /* SCK */ 3260 RCAR_GP_PIN(4, 21), 3261 }; 3262 static const unsigned int scifb2_clk_mux[] = { 3263 SCIFB2_SCK_MARK, 3264 }; 3265 static const unsigned int scifb2_ctrl_pins[] = { 3266 /* RTS, CTS */ 3267 RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 24), 3268 }; 3269 static const unsigned int scifb2_ctrl_mux[] = { 3270 SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK, 3271 }; 3272 static const unsigned int scifb2_data_b_pins[] = { 3273 /* RXD, TXD */ 3274 RCAR_GP_PIN(0, 28), RCAR_GP_PIN(0, 30), 3275 }; 3276 static const unsigned int scifb2_data_b_mux[] = { 3277 SCIFB2_RXD_B_MARK, SCIFB2_TXD_B_MARK, 3278 }; 3279 static const unsigned int scifb2_clk_b_pins[] = { 3280 /* SCK */ 3281 RCAR_GP_PIN(0, 31), 3282 }; 3283 static const unsigned int scifb2_clk_b_mux[] = { 3284 SCIFB2_SCK_B_MARK, 3285 }; 3286 static const unsigned int scifb2_ctrl_b_pins[] = { 3287 /* RTS, CTS */ 3288 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(0, 27), 3289 }; 3290 static const unsigned int scifb2_ctrl_b_mux[] = { 3291 SCIFB2_RTS_N_B_MARK, SCIFB2_CTS_N_B_MARK, 3292 }; 3293 static const unsigned int scifb2_data_c_pins[] = { 3294 /* RXD, TXD */ 3295 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25), 3296 }; 3297 static const unsigned int scifb2_data_c_mux[] = { 3298 SCIFB2_RXD_C_MARK, SCIFB2_TXD_C_MARK, 3299 }; 3300 /* - SCIF Clock ------------------------------------------------------------- */ 3301 static const unsigned int scif_clk_pins[] = { 3302 /* SCIF_CLK */ 3303 RCAR_GP_PIN(4, 26), 3304 }; 3305 static const unsigned int scif_clk_mux[] = { 3306 SCIF_CLK_MARK, 3307 }; 3308 static const unsigned int scif_clk_b_pins[] = { 3309 /* SCIF_CLK */ 3310 RCAR_GP_PIN(5, 4), 3311 }; 3312 static const unsigned int scif_clk_b_mux[] = { 3313 SCIF_CLK_B_MARK, 3314 }; 3315 /* - SDHI0 ------------------------------------------------------------------ */ 3316 static const unsigned int sdhi0_data1_pins[] = { 3317 /* D0 */ 3318 RCAR_GP_PIN(3, 2), 3319 }; 3320 static const unsigned int sdhi0_data1_mux[] = { 3321 SD0_DAT0_MARK, 3322 }; 3323 static const unsigned int sdhi0_data4_pins[] = { 3324 /* D[0:3] */ 3325 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), 3326 }; 3327 static const unsigned int sdhi0_data4_mux[] = { 3328 SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK, 3329 }; 3330 static const unsigned int sdhi0_ctrl_pins[] = { 3331 /* CLK, CMD */ 3332 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1), 3333 }; 3334 static const unsigned int sdhi0_ctrl_mux[] = { 3335 SD0_CLK_MARK, SD0_CMD_MARK, 3336 }; 3337 static const unsigned int sdhi0_cd_pins[] = { 3338 /* CD */ 3339 RCAR_GP_PIN(3, 6), 3340 }; 3341 static const unsigned int sdhi0_cd_mux[] = { 3342 SD0_CD_MARK, 3343 }; 3344 static const unsigned int sdhi0_wp_pins[] = { 3345 /* WP */ 3346 RCAR_GP_PIN(3, 7), 3347 }; 3348 static const unsigned int sdhi0_wp_mux[] = { 3349 SD0_WP_MARK, 3350 }; 3351 /* - SDHI1 ------------------------------------------------------------------ */ 3352 static const unsigned int sdhi1_data1_pins[] = { 3353 /* D0 */ 3354 RCAR_GP_PIN(3, 10), 3355 }; 3356 static const unsigned int sdhi1_data1_mux[] = { 3357 SD1_DAT0_MARK, 3358 }; 3359 static const unsigned int sdhi1_data4_pins[] = { 3360 /* D[0:3] */ 3361 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13), 3362 }; 3363 static const unsigned int sdhi1_data4_mux[] = { 3364 SD1_DAT0_MARK, SD1_DAT1_MARK, SD1_DAT2_MARK, SD1_DAT3_MARK, 3365 }; 3366 static const unsigned int sdhi1_ctrl_pins[] = { 3367 /* CLK, CMD */ 3368 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), 3369 }; 3370 static const unsigned int sdhi1_ctrl_mux[] = { 3371 SD1_CLK_MARK, SD1_CMD_MARK, 3372 }; 3373 static const unsigned int sdhi1_cd_pins[] = { 3374 /* CD */ 3375 RCAR_GP_PIN(3, 14), 3376 }; 3377 static const unsigned int sdhi1_cd_mux[] = { 3378 SD1_CD_MARK, 3379 }; 3380 static const unsigned int sdhi1_wp_pins[] = { 3381 /* WP */ 3382 RCAR_GP_PIN(3, 15), 3383 }; 3384 static const unsigned int sdhi1_wp_mux[] = { 3385 SD1_WP_MARK, 3386 }; 3387 /* - SDHI2 ------------------------------------------------------------------ */ 3388 static const unsigned int sdhi2_data1_pins[] = { 3389 /* D0 */ 3390 RCAR_GP_PIN(3, 18), 3391 }; 3392 static const unsigned int sdhi2_data1_mux[] = { 3393 SD2_DAT0_MARK, 3394 }; 3395 static const unsigned int sdhi2_data4_pins[] = { 3396 /* D[0:3] */ 3397 RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21), 3398 }; 3399 static const unsigned int sdhi2_data4_mux[] = { 3400 SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK, 3401 }; 3402 static const unsigned int sdhi2_ctrl_pins[] = { 3403 /* CLK, CMD */ 3404 RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17), 3405 }; 3406 static const unsigned int sdhi2_ctrl_mux[] = { 3407 SD2_CLK_MARK, SD2_CMD_MARK, 3408 }; 3409 static const unsigned int sdhi2_cd_pins[] = { 3410 /* CD */ 3411 RCAR_GP_PIN(3, 22), 3412 }; 3413 static const unsigned int sdhi2_cd_mux[] = { 3414 SD2_CD_MARK, 3415 }; 3416 static const unsigned int sdhi2_wp_pins[] = { 3417 /* WP */ 3418 RCAR_GP_PIN(3, 23), 3419 }; 3420 static const unsigned int sdhi2_wp_mux[] = { 3421 SD2_WP_MARK, 3422 }; 3423 /* - SDHI3 ------------------------------------------------------------------ */ 3424 static const unsigned int sdhi3_data1_pins[] = { 3425 /* D0 */ 3426 RCAR_GP_PIN(3, 26), 3427 }; 3428 static const unsigned int sdhi3_data1_mux[] = { 3429 SD3_DAT0_MARK, 3430 }; 3431 static const unsigned int sdhi3_data4_pins[] = { 3432 /* D[0:3] */ 3433 RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29), 3434 }; 3435 static const unsigned int sdhi3_data4_mux[] = { 3436 SD3_DAT0_MARK, SD3_DAT1_MARK, SD3_DAT2_MARK, SD3_DAT3_MARK, 3437 }; 3438 static const unsigned int sdhi3_ctrl_pins[] = { 3439 /* CLK, CMD */ 3440 RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25), 3441 }; 3442 static const unsigned int sdhi3_ctrl_mux[] = { 3443 SD3_CLK_MARK, SD3_CMD_MARK, 3444 }; 3445 static const unsigned int sdhi3_cd_pins[] = { 3446 /* CD */ 3447 RCAR_GP_PIN(3, 30), 3448 }; 3449 static const unsigned int sdhi3_cd_mux[] = { 3450 SD3_CD_MARK, 3451 }; 3452 static const unsigned int sdhi3_wp_pins[] = { 3453 /* WP */ 3454 RCAR_GP_PIN(3, 31), 3455 }; 3456 static const unsigned int sdhi3_wp_mux[] = { 3457 SD3_WP_MARK, 3458 }; 3459 /* - SSI -------------------------------------------------------------------- */ 3460 static const unsigned int ssi0_data_pins[] = { 3461 /* SDATA0 */ 3462 RCAR_GP_PIN(4, 5), 3463 }; 3464 static const unsigned int ssi0_data_mux[] = { 3465 SSI_SDATA0_MARK, 3466 }; 3467 static const unsigned int ssi0129_ctrl_pins[] = { 3468 /* SCK, WS */ 3469 RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 4), 3470 }; 3471 static const unsigned int ssi0129_ctrl_mux[] = { 3472 SSI_SCK0129_MARK, SSI_WS0129_MARK, 3473 }; 3474 static const unsigned int ssi1_data_pins[] = { 3475 /* SDATA1 */ 3476 RCAR_GP_PIN(4, 6), 3477 }; 3478 static const unsigned int ssi1_data_mux[] = { 3479 SSI_SDATA1_MARK, 3480 }; 3481 static const unsigned int ssi1_ctrl_pins[] = { 3482 /* SCK, WS */ 3483 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 24), 3484 }; 3485 static const unsigned int ssi1_ctrl_mux[] = { 3486 SSI_SCK1_MARK, SSI_WS1_MARK, 3487 }; 3488 static const unsigned int ssi2_data_pins[] = { 3489 /* SDATA2 */ 3490 RCAR_GP_PIN(4, 7), 3491 }; 3492 static const unsigned int ssi2_data_mux[] = { 3493 SSI_SDATA2_MARK, 3494 }; 3495 static const unsigned int ssi2_ctrl_pins[] = { 3496 /* SCK, WS */ 3497 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 17), 3498 }; 3499 static const unsigned int ssi2_ctrl_mux[] = { 3500 SSI_SCK2_MARK, SSI_WS2_MARK, 3501 }; 3502 static const unsigned int ssi3_data_pins[] = { 3503 /* SDATA3 */ 3504 RCAR_GP_PIN(4, 10), 3505 }; 3506 static const unsigned int ssi3_data_mux[] = { 3507 SSI_SDATA3_MARK 3508 }; 3509 static const unsigned int ssi34_ctrl_pins[] = { 3510 /* SCK, WS */ 3511 RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9), 3512 }; 3513 static const unsigned int ssi34_ctrl_mux[] = { 3514 SSI_SCK34_MARK, SSI_WS34_MARK, 3515 }; 3516 static const unsigned int ssi4_data_pins[] = { 3517 /* SDATA4 */ 3518 RCAR_GP_PIN(4, 13), 3519 }; 3520 static const unsigned int ssi4_data_mux[] = { 3521 SSI_SDATA4_MARK, 3522 }; 3523 static const unsigned int ssi4_ctrl_pins[] = { 3524 /* SCK, WS */ 3525 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12), 3526 }; 3527 static const unsigned int ssi4_ctrl_mux[] = { 3528 SSI_SCK4_MARK, SSI_WS4_MARK, 3529 }; 3530 static const unsigned int ssi5_pins[] = { 3531 /* SDATA5, SCK, WS */ 3532 RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15), 3533 }; 3534 static const unsigned int ssi5_mux[] = { 3535 SSI_SDATA5_MARK, SSI_SCK5_MARK, SSI_WS5_MARK, 3536 }; 3537 static const unsigned int ssi5_b_pins[] = { 3538 /* SDATA5, SCK, WS */ 3539 RCAR_GP_PIN(0, 26), RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25), 3540 }; 3541 static const unsigned int ssi5_b_mux[] = { 3542 SSI_SDATA5_B_MARK, SSI_SCK5_B_MARK, SSI_WS5_B_MARK 3543 }; 3544 static const unsigned int ssi5_c_pins[] = { 3545 /* SDATA5, SCK, WS */ 3546 RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12), 3547 }; 3548 static const unsigned int ssi5_c_mux[] = { 3549 SSI_SDATA5_C_MARK, SSI_SCK5_C_MARK, SSI_WS5_C_MARK, 3550 }; 3551 static const unsigned int ssi6_pins[] = { 3552 /* SDATA6, SCK, WS */ 3553 RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18), 3554 }; 3555 static const unsigned int ssi6_mux[] = { 3556 SSI_SDATA6_MARK, SSI_SCK6_MARK, SSI_WS6_MARK, 3557 }; 3558 static const unsigned int ssi6_b_pins[] = { 3559 /* SDATA6, SCK, WS */ 3560 RCAR_GP_PIN(1, 29), RCAR_GP_PIN(1, 25), RCAR_GP_PIN(1, 27), 3561 }; 3562 static const unsigned int ssi6_b_mux[] = { 3563 SSI_SDATA6_B_MARK, SSI_SCK6_B_MARK, SSI_WS6_B_MARK, 3564 }; 3565 static const unsigned int ssi7_data_pins[] = { 3566 /* SDATA7 */ 3567 RCAR_GP_PIN(4, 22), 3568 }; 3569 static const unsigned int ssi7_data_mux[] = { 3570 SSI_SDATA7_MARK, 3571 }; 3572 static const unsigned int ssi7_b_data_pins[] = { 3573 /* SDATA7 */ 3574 RCAR_GP_PIN(4, 22), 3575 }; 3576 static const unsigned int ssi7_b_data_mux[] = { 3577 SSI_SDATA7_B_MARK, 3578 }; 3579 static const unsigned int ssi7_c_data_pins[] = { 3580 /* SDATA7 */ 3581 RCAR_GP_PIN(1, 26), 3582 }; 3583 static const unsigned int ssi7_c_data_mux[] = { 3584 SSI_SDATA7_C_MARK, 3585 }; 3586 static const unsigned int ssi78_ctrl_pins[] = { 3587 /* SCK, WS */ 3588 RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21), 3589 }; 3590 static const unsigned int ssi78_ctrl_mux[] = { 3591 SSI_SCK78_MARK, SSI_WS78_MARK, 3592 }; 3593 static const unsigned int ssi78_b_ctrl_pins[] = { 3594 /* SCK, WS */ 3595 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 24), 3596 }; 3597 static const unsigned int ssi78_b_ctrl_mux[] = { 3598 SSI_SCK78_B_MARK, SSI_WS78_B_MARK, 3599 }; 3600 static const unsigned int ssi78_c_ctrl_pins[] = { 3601 /* SCK, WS */ 3602 RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 25), 3603 }; 3604 static const unsigned int ssi78_c_ctrl_mux[] = { 3605 SSI_SCK78_C_MARK, SSI_WS78_C_MARK, 3606 }; 3607 static const unsigned int ssi8_data_pins[] = { 3608 /* SDATA8 */ 3609 RCAR_GP_PIN(4, 23), 3610 }; 3611 static const unsigned int ssi8_data_mux[] = { 3612 SSI_SDATA8_MARK, 3613 }; 3614 static const unsigned int ssi8_b_data_pins[] = { 3615 /* SDATA8 */ 3616 RCAR_GP_PIN(4, 23), 3617 }; 3618 static const unsigned int ssi8_b_data_mux[] = { 3619 SSI_SDATA8_B_MARK, 3620 }; 3621 static const unsigned int ssi8_c_data_pins[] = { 3622 /* SDATA8 */ 3623 RCAR_GP_PIN(1, 27), 3624 }; 3625 static const unsigned int ssi8_c_data_mux[] = { 3626 SSI_SDATA8_C_MARK, 3627 }; 3628 static const unsigned int ssi9_data_pins[] = { 3629 /* SDATA9 */ 3630 RCAR_GP_PIN(4, 24), 3631 }; 3632 static const unsigned int ssi9_data_mux[] = { 3633 SSI_SDATA9_MARK, 3634 }; 3635 static const unsigned int ssi9_ctrl_pins[] = { 3636 /* SCK, WS */ 3637 RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11), 3638 }; 3639 static const unsigned int ssi9_ctrl_mux[] = { 3640 SSI_SCK9_MARK, SSI_WS9_MARK, 3641 }; 3642 /* - TPU0 ------------------------------------------------------------------- */ 3643 static const unsigned int tpu0_to0_pins[] = { 3644 /* TO */ 3645 RCAR_GP_PIN(0, 20), 3646 }; 3647 static const unsigned int tpu0_to0_mux[] = { 3648 TPU0TO0_MARK, 3649 }; 3650 static const unsigned int tpu0_to1_pins[] = { 3651 /* TO */ 3652 RCAR_GP_PIN(0, 21), 3653 }; 3654 static const unsigned int tpu0_to1_mux[] = { 3655 TPU0TO1_MARK, 3656 }; 3657 static const unsigned int tpu0_to2_pins[] = { 3658 /* TO */ 3659 RCAR_GP_PIN(0, 22), 3660 }; 3661 static const unsigned int tpu0_to2_mux[] = { 3662 TPU0TO2_MARK, 3663 }; 3664 static const unsigned int tpu0_to3_pins[] = { 3665 /* TO */ 3666 RCAR_GP_PIN(0, 23), 3667 }; 3668 static const unsigned int tpu0_to3_mux[] = { 3669 TPU0TO3_MARK, 3670 }; 3671 /* - USB0 ------------------------------------------------------------------- */ 3672 static const unsigned int usb0_pins[] = { 3673 /* PWEN, OVC/VBUS */ 3674 RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19), 3675 }; 3676 static const unsigned int usb0_mux[] = { 3677 USB0_PWEN_MARK, USB0_OVC_VBUS_MARK, 3678 }; 3679 static const unsigned int usb0_ovc_vbus_pins[] = { 3680 /* OVC/VBUS */ 3681 RCAR_GP_PIN(5, 19), 3682 }; 3683 static const unsigned int usb0_ovc_vbus_mux[] = { 3684 USB0_OVC_VBUS_MARK, 3685 }; 3686 /* - USB1 ------------------------------------------------------------------- */ 3687 static const unsigned int usb1_pins[] = { 3688 /* PWEN, OVC */ 3689 RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21), 3690 }; 3691 static const unsigned int usb1_mux[] = { 3692 USB1_PWEN_MARK, USB1_OVC_MARK, 3693 }; 3694 static const unsigned int usb1_pwen_pins[] = { 3695 /* PWEN */ 3696 RCAR_GP_PIN(5, 20), 3697 }; 3698 static const unsigned int usb1_pwen_mux[] = { 3699 USB1_PWEN_MARK, 3700 }; 3701 /* - USB2 ------------------------------------------------------------------- */ 3702 static const unsigned int usb2_pins[] = { 3703 /* PWEN, OVC */ 3704 RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23), 3705 }; 3706 static const unsigned int usb2_mux[] = { 3707 USB2_PWEN_MARK, USB2_OVC_MARK, 3708 }; 3709 /* - VIN0 ------------------------------------------------------------------- */ 3710 static const union vin_data vin0_data_pins = { 3711 .data24 = { 3712 /* B */ 3713 RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2), 3714 RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4), 3715 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6), 3716 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), 3717 /* G */ 3718 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), 3719 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), 3720 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), 3721 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), 3722 /* R */ 3723 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), 3724 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), 3725 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25), 3726 RCAR_GP_PIN(0, 26), RCAR_GP_PIN(1, 11), 3727 }, 3728 }; 3729 static const union vin_data vin0_data_mux = { 3730 .data24 = { 3731 /* B */ 3732 VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK, 3733 VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK, 3734 VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK, 3735 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK, 3736 /* G */ 3737 VI0_G0_MARK, VI0_G1_MARK, 3738 VI0_G2_MARK, VI0_G3_MARK, 3739 VI0_G4_MARK, VI0_G5_MARK, 3740 VI0_G6_MARK, VI0_G7_MARK, 3741 /* R */ 3742 VI0_R0_MARK, VI0_R1_MARK, 3743 VI0_R2_MARK, VI0_R3_MARK, 3744 VI0_R4_MARK, VI0_R5_MARK, 3745 VI0_R6_MARK, VI0_R7_MARK, 3746 }, 3747 }; 3748 static const unsigned int vin0_data18_pins[] = { 3749 /* B */ 3750 RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4), 3751 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6), 3752 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), 3753 /* G */ 3754 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), 3755 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), 3756 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), 3757 /* R */ 3758 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), 3759 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25), 3760 RCAR_GP_PIN(0, 26), RCAR_GP_PIN(1, 11), 3761 }; 3762 static const unsigned int vin0_data18_mux[] = { 3763 /* B */ 3764 VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK, 3765 VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK, 3766 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK, 3767 /* G */ 3768 VI0_G2_MARK, VI0_G3_MARK, 3769 VI0_G4_MARK, VI0_G5_MARK, 3770 VI0_G6_MARK, VI0_G7_MARK, 3771 /* R */ 3772 VI0_R2_MARK, VI0_R3_MARK, 3773 VI0_R4_MARK, VI0_R5_MARK, 3774 VI0_R6_MARK, VI0_R7_MARK, 3775 }; 3776 static const unsigned int vin0_sync_pins[] = { 3777 RCAR_GP_PIN(0, 12), /* HSYNC */ 3778 RCAR_GP_PIN(0, 13), /* VSYNC */ 3779 }; 3780 static const unsigned int vin0_sync_mux[] = { 3781 VI0_HSYNC_N_MARK, 3782 VI0_VSYNC_N_MARK, 3783 }; 3784 static const unsigned int vin0_field_pins[] = { 3785 RCAR_GP_PIN(0, 15), 3786 }; 3787 static const unsigned int vin0_field_mux[] = { 3788 VI0_FIELD_MARK, 3789 }; 3790 static const unsigned int vin0_clkenb_pins[] = { 3791 RCAR_GP_PIN(0, 14), 3792 }; 3793 static const unsigned int vin0_clkenb_mux[] = { 3794 VI0_CLKENB_MARK, 3795 }; 3796 static const unsigned int vin0_clk_pins[] = { 3797 RCAR_GP_PIN(2, 0), 3798 }; 3799 static const unsigned int vin0_clk_mux[] = { 3800 VI0_CLK_MARK, 3801 }; 3802 /* - VIN1 ------------------------------------------------------------------- */ 3803 static const union vin_data vin1_data_pins = { 3804 .data24 = { 3805 /* B */ 3806 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11), 3807 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13), 3808 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15), 3809 RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17), 3810 /* G */ 3811 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), 3812 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20), 3813 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12), 3814 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7), 3815 /* R */ 3816 RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28), 3817 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4), 3818 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), 3819 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8), 3820 }, 3821 }; 3822 static const union vin_data vin1_data_mux = { 3823 .data24 = { 3824 /* B */ 3825 VI1_DATA0_VI1_B0_MARK, VI1_DATA1_VI1_B1_MARK, 3826 VI1_DATA2_VI1_B2_MARK, VI1_DATA3_VI1_B3_MARK, 3827 VI1_DATA4_VI1_B4_MARK, VI1_DATA5_VI1_B5_MARK, 3828 VI1_DATA6_VI1_B6_MARK, VI1_DATA7_VI1_B7_MARK, 3829 /* G */ 3830 VI1_G0_MARK, VI1_G1_MARK, 3831 VI1_G2_MARK, VI1_G3_MARK, 3832 VI1_G4_MARK, VI1_G5_MARK, 3833 VI1_G6_MARK, VI1_G7_MARK, 3834 /* R */ 3835 VI1_R0_MARK, VI1_R1_MARK, 3836 VI1_R2_MARK, VI1_R3_MARK, 3837 VI1_R4_MARK, VI1_R5_MARK, 3838 VI1_R6_MARK, VI1_R7_MARK, 3839 }, 3840 }; 3841 static const unsigned int vin1_data18_pins[] = { 3842 /* B */ 3843 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13), 3844 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15), 3845 RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17), 3846 /* G */ 3847 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20), 3848 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12), 3849 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7), 3850 /* R */ 3851 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4), 3852 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), 3853 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8), 3854 }; 3855 static const unsigned int vin1_data18_mux[] = { 3856 /* B */ 3857 VI1_DATA2_VI1_B2_MARK, VI1_DATA3_VI1_B3_MARK, 3858 VI1_DATA4_VI1_B4_MARK, VI1_DATA5_VI1_B5_MARK, 3859 VI1_DATA6_VI1_B6_MARK, VI1_DATA7_VI1_B7_MARK, 3860 /* G */ 3861 VI1_G2_MARK, VI1_G3_MARK, 3862 VI1_G4_MARK, VI1_G5_MARK, 3863 VI1_G6_MARK, VI1_G7_MARK, 3864 /* R */ 3865 VI1_R2_MARK, VI1_R3_MARK, 3866 VI1_R4_MARK, VI1_R5_MARK, 3867 VI1_R6_MARK, VI1_R7_MARK, 3868 }; 3869 static const unsigned int vin1_sync_pins[] = { 3870 RCAR_GP_PIN(1, 24), /* HSYNC */ 3871 RCAR_GP_PIN(1, 25), /* VSYNC */ 3872 }; 3873 static const unsigned int vin1_sync_mux[] = { 3874 VI1_HSYNC_N_MARK, 3875 VI1_VSYNC_N_MARK, 3876 }; 3877 static const unsigned int vin1_field_pins[] = { 3878 RCAR_GP_PIN(1, 13), 3879 }; 3880 static const unsigned int vin1_field_mux[] = { 3881 VI1_FIELD_MARK, 3882 }; 3883 static const unsigned int vin1_clkenb_pins[] = { 3884 RCAR_GP_PIN(1, 26), 3885 }; 3886 static const unsigned int vin1_clkenb_mux[] = { 3887 VI1_CLKENB_MARK, 3888 }; 3889 static const unsigned int vin1_clk_pins[] = { 3890 RCAR_GP_PIN(2, 9), 3891 }; 3892 static const unsigned int vin1_clk_mux[] = { 3893 VI1_CLK_MARK, 3894 }; 3895 /* - VIN2 ----------------------------------------------------------------- */ 3896 static const union vin_data vin2_data_pins = { 3897 .data24 = { 3898 /* B */ 3899 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), 3900 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), 3901 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), 3902 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), 3903 /* G */ 3904 RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28), 3905 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 10), 3906 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), 3907 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 3908 /* R */ 3909 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), 3910 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), 3911 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20), 3912 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 24), 3913 }, 3914 }; 3915 static const union vin_data vin2_data_mux = { 3916 .data24 = { 3917 /* B */ 3918 VI2_DATA0_VI2_B0_MARK, VI2_DATA1_VI2_B1_MARK, 3919 VI2_DATA2_VI2_B2_MARK, VI2_DATA3_VI2_B3_MARK, 3920 VI2_DATA4_VI2_B4_MARK, VI2_DATA5_VI2_B5_MARK, 3921 VI2_DATA6_VI2_B6_MARK, VI2_DATA7_VI2_B7_MARK, 3922 /* G */ 3923 VI2_G0_MARK, VI2_G1_MARK, 3924 VI2_G2_MARK, VI2_G3_MARK, 3925 VI2_G4_MARK, VI2_G5_MARK, 3926 VI2_G6_MARK, VI2_G7_MARK, 3927 /* R */ 3928 VI2_R0_MARK, VI2_R1_MARK, 3929 VI2_R2_MARK, VI2_R3_MARK, 3930 VI2_R4_MARK, VI2_R5_MARK, 3931 VI2_R6_MARK, VI2_R7_MARK, 3932 }, 3933 }; 3934 static const unsigned int vin2_data18_pins[] = { 3935 /* B */ 3936 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), 3937 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), 3938 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), 3939 /* G */ 3940 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 10), 3941 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), 3942 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 3943 /* R */ 3944 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), 3945 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20), 3946 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 24), 3947 }; 3948 static const unsigned int vin2_data18_mux[] = { 3949 /* B */ 3950 VI2_DATA2_VI2_B2_MARK, VI2_DATA3_VI2_B3_MARK, 3951 VI2_DATA4_VI2_B4_MARK, VI2_DATA5_VI2_B5_MARK, 3952 VI2_DATA6_VI2_B6_MARK, VI2_DATA7_VI2_B7_MARK, 3953 /* G */ 3954 VI2_G2_MARK, VI2_G3_MARK, 3955 VI2_G4_MARK, VI2_G5_MARK, 3956 VI2_G6_MARK, VI2_G7_MARK, 3957 /* R */ 3958 VI2_R2_MARK, VI2_R3_MARK, 3959 VI2_R4_MARK, VI2_R5_MARK, 3960 VI2_R6_MARK, VI2_R7_MARK, 3961 }; 3962 static const unsigned int vin2_sync_pins[] = { 3963 RCAR_GP_PIN(1, 16), /* HSYNC */ 3964 RCAR_GP_PIN(1, 21), /* VSYNC */ 3965 }; 3966 static const unsigned int vin2_sync_mux[] = { 3967 VI2_HSYNC_N_MARK, 3968 VI2_VSYNC_N_MARK, 3969 }; 3970 static const unsigned int vin2_field_pins[] = { 3971 RCAR_GP_PIN(1, 9), 3972 }; 3973 static const unsigned int vin2_field_mux[] = { 3974 VI2_FIELD_MARK, 3975 }; 3976 static const unsigned int vin2_clkenb_pins[] = { 3977 RCAR_GP_PIN(1, 8), 3978 }; 3979 static const unsigned int vin2_clkenb_mux[] = { 3980 VI2_CLKENB_MARK, 3981 }; 3982 static const unsigned int vin2_clk_pins[] = { 3983 RCAR_GP_PIN(1, 11), 3984 }; 3985 static const unsigned int vin2_clk_mux[] = { 3986 VI2_CLK_MARK, 3987 }; 3988 /* - VIN3 ----------------------------------------------------------------- */ 3989 static const unsigned int vin3_data8_pins[] = { 3990 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), 3991 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), 3992 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), 3993 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), 3994 }; 3995 static const unsigned int vin3_data8_mux[] = { 3996 VI3_DATA0_MARK, VI3_DATA1_MARK, 3997 VI3_DATA2_MARK, VI3_DATA3_MARK, 3998 VI3_DATA4_MARK, VI3_DATA5_MARK, 3999 VI3_DATA6_MARK, VI3_DATA7_MARK, 4000 }; 4001 static const unsigned int vin3_sync_pins[] = { 4002 RCAR_GP_PIN(1, 16), /* HSYNC */ 4003 RCAR_GP_PIN(1, 17), /* VSYNC */ 4004 }; 4005 static const unsigned int vin3_sync_mux[] = { 4006 VI3_HSYNC_N_MARK, 4007 VI3_VSYNC_N_MARK, 4008 }; 4009 static const unsigned int vin3_field_pins[] = { 4010 RCAR_GP_PIN(1, 15), 4011 }; 4012 static const unsigned int vin3_field_mux[] = { 4013 VI3_FIELD_MARK, 4014 }; 4015 static const unsigned int vin3_clkenb_pins[] = { 4016 RCAR_GP_PIN(1, 14), 4017 }; 4018 static const unsigned int vin3_clkenb_mux[] = { 4019 VI3_CLKENB_MARK, 4020 }; 4021 static const unsigned int vin3_clk_pins[] = { 4022 RCAR_GP_PIN(1, 23), 4023 }; 4024 static const unsigned int vin3_clk_mux[] = { 4025 VI3_CLK_MARK, 4026 }; 4027 4028 static const struct { 4029 struct sh_pfc_pin_group common[298]; 4030 struct sh_pfc_pin_group automotive[1]; 4031 } pinmux_groups = { 4032 .common = { 4033 SH_PFC_PIN_GROUP(audio_clk_a), 4034 SH_PFC_PIN_GROUP(audio_clk_b), 4035 SH_PFC_PIN_GROUP(audio_clk_c), 4036 SH_PFC_PIN_GROUP(audio_clkout), 4037 SH_PFC_PIN_GROUP(audio_clkout_b), 4038 SH_PFC_PIN_GROUP(audio_clkout_c), 4039 SH_PFC_PIN_GROUP(audio_clkout_d), 4040 SH_PFC_PIN_GROUP(avb_link), 4041 SH_PFC_PIN_GROUP(avb_magic), 4042 SH_PFC_PIN_GROUP(avb_phy_int), 4043 SH_PFC_PIN_GROUP(avb_mdio), 4044 SH_PFC_PIN_GROUP(avb_mii), 4045 SH_PFC_PIN_GROUP(avb_gmii), 4046 SH_PFC_PIN_GROUP(can0_data), 4047 SH_PFC_PIN_GROUP(can0_data_b), 4048 SH_PFC_PIN_GROUP(can0_data_c), 4049 SH_PFC_PIN_GROUP(can0_data_d), 4050 SH_PFC_PIN_GROUP(can1_data), 4051 SH_PFC_PIN_GROUP(can1_data_b), 4052 SH_PFC_PIN_GROUP(can_clk), 4053 SH_PFC_PIN_GROUP(can_clk_b), 4054 SH_PFC_PIN_GROUP(du_rgb666), 4055 SH_PFC_PIN_GROUP(du_rgb888), 4056 SH_PFC_PIN_GROUP(du_clk_out_0), 4057 SH_PFC_PIN_GROUP(du_clk_out_1), 4058 SH_PFC_PIN_GROUP(du_sync_0), 4059 SH_PFC_PIN_GROUP(du_sync_1), 4060 SH_PFC_PIN_GROUP(du_cde), 4061 SH_PFC_PIN_GROUP(du0_clk_in), 4062 SH_PFC_PIN_GROUP(du1_clk_in), 4063 SH_PFC_PIN_GROUP(du2_clk_in), 4064 SH_PFC_PIN_GROUP(eth_link), 4065 SH_PFC_PIN_GROUP(eth_magic), 4066 SH_PFC_PIN_GROUP(eth_mdio), 4067 SH_PFC_PIN_GROUP(eth_rmii), 4068 SH_PFC_PIN_GROUP(hscif0_data), 4069 SH_PFC_PIN_GROUP(hscif0_clk), 4070 SH_PFC_PIN_GROUP(hscif0_ctrl), 4071 SH_PFC_PIN_GROUP(hscif0_data_b), 4072 SH_PFC_PIN_GROUP(hscif0_ctrl_b), 4073 SH_PFC_PIN_GROUP(hscif0_data_c), 4074 SH_PFC_PIN_GROUP(hscif0_ctrl_c), 4075 SH_PFC_PIN_GROUP(hscif0_data_d), 4076 SH_PFC_PIN_GROUP(hscif0_ctrl_d), 4077 SH_PFC_PIN_GROUP(hscif0_data_e), 4078 SH_PFC_PIN_GROUP(hscif0_ctrl_e), 4079 SH_PFC_PIN_GROUP(hscif0_data_f), 4080 SH_PFC_PIN_GROUP(hscif0_ctrl_f), 4081 SH_PFC_PIN_GROUP(hscif1_data), 4082 SH_PFC_PIN_GROUP(hscif1_clk), 4083 SH_PFC_PIN_GROUP(hscif1_ctrl), 4084 SH_PFC_PIN_GROUP(hscif1_data_b), 4085 SH_PFC_PIN_GROUP(hscif1_clk_b), 4086 SH_PFC_PIN_GROUP(hscif1_ctrl_b), 4087 SH_PFC_PIN_GROUP(i2c0), 4088 SH_PFC_PIN_GROUP(i2c1), 4089 SH_PFC_PIN_GROUP(i2c1_b), 4090 SH_PFC_PIN_GROUP(i2c1_c), 4091 SH_PFC_PIN_GROUP(i2c2), 4092 SH_PFC_PIN_GROUP(i2c2_b), 4093 SH_PFC_PIN_GROUP(i2c2_c), 4094 SH_PFC_PIN_GROUP(i2c2_d), 4095 SH_PFC_PIN_GROUP(i2c2_e), 4096 SH_PFC_PIN_GROUP(i2c3), 4097 SH_PFC_PIN_GROUP(iic0), 4098 SH_PFC_PIN_GROUP(iic1), 4099 SH_PFC_PIN_GROUP(iic1_b), 4100 SH_PFC_PIN_GROUP(iic1_c), 4101 SH_PFC_PIN_GROUP(iic2), 4102 SH_PFC_PIN_GROUP(iic2_b), 4103 SH_PFC_PIN_GROUP(iic2_c), 4104 SH_PFC_PIN_GROUP(iic2_d), 4105 SH_PFC_PIN_GROUP(iic2_e), 4106 SH_PFC_PIN_GROUP(iic3), 4107 SH_PFC_PIN_GROUP(intc_irq0), 4108 SH_PFC_PIN_GROUP(intc_irq1), 4109 SH_PFC_PIN_GROUP(intc_irq2), 4110 SH_PFC_PIN_GROUP(intc_irq3), 4111 SH_PFC_PIN_GROUP(mmc0_data1), 4112 SH_PFC_PIN_GROUP(mmc0_data4), 4113 SH_PFC_PIN_GROUP(mmc0_data8), 4114 SH_PFC_PIN_GROUP(mmc0_ctrl), 4115 SH_PFC_PIN_GROUP(mmc1_data1), 4116 SH_PFC_PIN_GROUP(mmc1_data4), 4117 SH_PFC_PIN_GROUP(mmc1_data8), 4118 SH_PFC_PIN_GROUP(mmc1_ctrl), 4119 SH_PFC_PIN_GROUP(msiof0_clk), 4120 SH_PFC_PIN_GROUP(msiof0_sync), 4121 SH_PFC_PIN_GROUP(msiof0_ss1), 4122 SH_PFC_PIN_GROUP(msiof0_ss2), 4123 SH_PFC_PIN_GROUP(msiof0_rx), 4124 SH_PFC_PIN_GROUP(msiof0_tx), 4125 SH_PFC_PIN_GROUP(msiof0_clk_b), 4126 SH_PFC_PIN_GROUP(msiof0_ss1_b), 4127 SH_PFC_PIN_GROUP(msiof0_ss2_b), 4128 SH_PFC_PIN_GROUP(msiof0_rx_b), 4129 SH_PFC_PIN_GROUP(msiof0_tx_b), 4130 SH_PFC_PIN_GROUP(msiof1_clk), 4131 SH_PFC_PIN_GROUP(msiof1_sync), 4132 SH_PFC_PIN_GROUP(msiof1_ss1), 4133 SH_PFC_PIN_GROUP(msiof1_ss2), 4134 SH_PFC_PIN_GROUP(msiof1_rx), 4135 SH_PFC_PIN_GROUP(msiof1_tx), 4136 SH_PFC_PIN_GROUP(msiof1_clk_b), 4137 SH_PFC_PIN_GROUP(msiof1_ss1_b), 4138 SH_PFC_PIN_GROUP(msiof1_ss2_b), 4139 SH_PFC_PIN_GROUP(msiof1_rx_b), 4140 SH_PFC_PIN_GROUP(msiof1_tx_b), 4141 SH_PFC_PIN_GROUP(msiof2_clk), 4142 SH_PFC_PIN_GROUP(msiof2_sync), 4143 SH_PFC_PIN_GROUP(msiof2_ss1), 4144 SH_PFC_PIN_GROUP(msiof2_ss2), 4145 SH_PFC_PIN_GROUP(msiof2_rx), 4146 SH_PFC_PIN_GROUP(msiof2_tx), 4147 SH_PFC_PIN_GROUP(msiof3_clk), 4148 SH_PFC_PIN_GROUP(msiof3_sync), 4149 SH_PFC_PIN_GROUP(msiof3_ss1), 4150 SH_PFC_PIN_GROUP(msiof3_ss2), 4151 SH_PFC_PIN_GROUP(msiof3_rx), 4152 SH_PFC_PIN_GROUP(msiof3_tx), 4153 SH_PFC_PIN_GROUP(msiof3_clk_b), 4154 SH_PFC_PIN_GROUP(msiof3_sync_b), 4155 SH_PFC_PIN_GROUP(msiof3_rx_b), 4156 SH_PFC_PIN_GROUP(msiof3_tx_b), 4157 SH_PFC_PIN_GROUP(pwm0), 4158 SH_PFC_PIN_GROUP(pwm0_b), 4159 SH_PFC_PIN_GROUP(pwm1), 4160 SH_PFC_PIN_GROUP(pwm1_b), 4161 SH_PFC_PIN_GROUP(pwm2), 4162 SH_PFC_PIN_GROUP(pwm3), 4163 SH_PFC_PIN_GROUP(pwm4), 4164 SH_PFC_PIN_GROUP(pwm5), 4165 SH_PFC_PIN_GROUP(pwm6), 4166 SH_PFC_PIN_GROUP(qspi_ctrl), 4167 SH_PFC_PIN_GROUP(qspi_data2), 4168 SH_PFC_PIN_GROUP(qspi_data4), 4169 SH_PFC_PIN_GROUP(scif0_data), 4170 SH_PFC_PIN_GROUP(scif0_clk), 4171 SH_PFC_PIN_GROUP(scif0_ctrl), 4172 SH_PFC_PIN_GROUP(scif0_data_b), 4173 SH_PFC_PIN_GROUP(scif1_data), 4174 SH_PFC_PIN_GROUP(scif1_clk), 4175 SH_PFC_PIN_GROUP(scif1_ctrl), 4176 SH_PFC_PIN_GROUP(scif1_data_b), 4177 SH_PFC_PIN_GROUP(scif1_data_c), 4178 SH_PFC_PIN_GROUP(scif1_data_d), 4179 SH_PFC_PIN_GROUP(scif1_clk_d), 4180 SH_PFC_PIN_GROUP(scif1_data_e), 4181 SH_PFC_PIN_GROUP(scif1_clk_e), 4182 SH_PFC_PIN_GROUP(scif2_data), 4183 SH_PFC_PIN_GROUP(scif2_clk), 4184 SH_PFC_PIN_GROUP(scif2_data_b), 4185 SH_PFC_PIN_GROUP(scifa0_data), 4186 SH_PFC_PIN_GROUP(scifa0_clk), 4187 SH_PFC_PIN_GROUP(scifa0_ctrl), 4188 SH_PFC_PIN_GROUP(scifa0_data_b), 4189 SH_PFC_PIN_GROUP(scifa0_clk_b), 4190 SH_PFC_PIN_GROUP(scifa0_ctrl_b), 4191 SH_PFC_PIN_GROUP(scifa1_data), 4192 SH_PFC_PIN_GROUP(scifa1_clk), 4193 SH_PFC_PIN_GROUP(scifa1_ctrl), 4194 SH_PFC_PIN_GROUP(scifa1_data_b), 4195 SH_PFC_PIN_GROUP(scifa1_clk_b), 4196 SH_PFC_PIN_GROUP(scifa1_ctrl_b), 4197 SH_PFC_PIN_GROUP(scifa1_data_c), 4198 SH_PFC_PIN_GROUP(scifa1_clk_c), 4199 SH_PFC_PIN_GROUP(scifa1_ctrl_c), 4200 SH_PFC_PIN_GROUP(scifa1_data_d), 4201 SH_PFC_PIN_GROUP(scifa1_clk_d), 4202 SH_PFC_PIN_GROUP(scifa1_ctrl_d), 4203 SH_PFC_PIN_GROUP(scifa2_data), 4204 SH_PFC_PIN_GROUP(scifa2_clk), 4205 SH_PFC_PIN_GROUP(scifa2_ctrl), 4206 SH_PFC_PIN_GROUP(scifa2_data_b), 4207 SH_PFC_PIN_GROUP(scifa2_data_c), 4208 SH_PFC_PIN_GROUP(scifa2_clk_c), 4209 SH_PFC_PIN_GROUP(scifb0_data), 4210 SH_PFC_PIN_GROUP(scifb0_clk), 4211 SH_PFC_PIN_GROUP(scifb0_ctrl), 4212 SH_PFC_PIN_GROUP(scifb0_data_b), 4213 SH_PFC_PIN_GROUP(scifb0_clk_b), 4214 SH_PFC_PIN_GROUP(scifb0_ctrl_b), 4215 SH_PFC_PIN_GROUP(scifb0_data_c), 4216 SH_PFC_PIN_GROUP(scifb1_data), 4217 SH_PFC_PIN_GROUP(scifb1_clk), 4218 SH_PFC_PIN_GROUP(scifb1_ctrl), 4219 SH_PFC_PIN_GROUP(scifb1_data_b), 4220 SH_PFC_PIN_GROUP(scifb1_clk_b), 4221 SH_PFC_PIN_GROUP(scifb1_ctrl_b), 4222 SH_PFC_PIN_GROUP(scifb1_data_c), 4223 SH_PFC_PIN_GROUP(scifb1_data_d), 4224 SH_PFC_PIN_GROUP(scifb1_data_e), 4225 SH_PFC_PIN_GROUP(scifb1_clk_e), 4226 SH_PFC_PIN_GROUP(scifb1_data_f), 4227 SH_PFC_PIN_GROUP(scifb1_data_g), 4228 SH_PFC_PIN_GROUP(scifb1_clk_g), 4229 SH_PFC_PIN_GROUP(scifb2_data), 4230 SH_PFC_PIN_GROUP(scifb2_clk), 4231 SH_PFC_PIN_GROUP(scifb2_ctrl), 4232 SH_PFC_PIN_GROUP(scifb2_data_b), 4233 SH_PFC_PIN_GROUP(scifb2_clk_b), 4234 SH_PFC_PIN_GROUP(scifb2_ctrl_b), 4235 SH_PFC_PIN_GROUP(scifb2_data_c), 4236 SH_PFC_PIN_GROUP(scif_clk), 4237 SH_PFC_PIN_GROUP(scif_clk_b), 4238 SH_PFC_PIN_GROUP(sdhi0_data1), 4239 SH_PFC_PIN_GROUP(sdhi0_data4), 4240 SH_PFC_PIN_GROUP(sdhi0_ctrl), 4241 SH_PFC_PIN_GROUP(sdhi0_cd), 4242 SH_PFC_PIN_GROUP(sdhi0_wp), 4243 SH_PFC_PIN_GROUP(sdhi1_data1), 4244 SH_PFC_PIN_GROUP(sdhi1_data4), 4245 SH_PFC_PIN_GROUP(sdhi1_ctrl), 4246 SH_PFC_PIN_GROUP(sdhi1_cd), 4247 SH_PFC_PIN_GROUP(sdhi1_wp), 4248 SH_PFC_PIN_GROUP(sdhi2_data1), 4249 SH_PFC_PIN_GROUP(sdhi2_data4), 4250 SH_PFC_PIN_GROUP(sdhi2_ctrl), 4251 SH_PFC_PIN_GROUP(sdhi2_cd), 4252 SH_PFC_PIN_GROUP(sdhi2_wp), 4253 SH_PFC_PIN_GROUP(sdhi3_data1), 4254 SH_PFC_PIN_GROUP(sdhi3_data4), 4255 SH_PFC_PIN_GROUP(sdhi3_ctrl), 4256 SH_PFC_PIN_GROUP(sdhi3_cd), 4257 SH_PFC_PIN_GROUP(sdhi3_wp), 4258 SH_PFC_PIN_GROUP(ssi0_data), 4259 SH_PFC_PIN_GROUP(ssi0129_ctrl), 4260 SH_PFC_PIN_GROUP(ssi1_data), 4261 SH_PFC_PIN_GROUP(ssi1_ctrl), 4262 SH_PFC_PIN_GROUP(ssi2_data), 4263 SH_PFC_PIN_GROUP(ssi2_ctrl), 4264 SH_PFC_PIN_GROUP(ssi3_data), 4265 SH_PFC_PIN_GROUP(ssi34_ctrl), 4266 SH_PFC_PIN_GROUP(ssi4_data), 4267 SH_PFC_PIN_GROUP(ssi4_ctrl), 4268 SH_PFC_PIN_GROUP(ssi5), 4269 SH_PFC_PIN_GROUP(ssi5_b), 4270 SH_PFC_PIN_GROUP(ssi5_c), 4271 SH_PFC_PIN_GROUP(ssi6), 4272 SH_PFC_PIN_GROUP(ssi6_b), 4273 SH_PFC_PIN_GROUP(ssi7_data), 4274 SH_PFC_PIN_GROUP(ssi7_b_data), 4275 SH_PFC_PIN_GROUP(ssi7_c_data), 4276 SH_PFC_PIN_GROUP(ssi78_ctrl), 4277 SH_PFC_PIN_GROUP(ssi78_b_ctrl), 4278 SH_PFC_PIN_GROUP(ssi78_c_ctrl), 4279 SH_PFC_PIN_GROUP(ssi8_data), 4280 SH_PFC_PIN_GROUP(ssi8_b_data), 4281 SH_PFC_PIN_GROUP(ssi8_c_data), 4282 SH_PFC_PIN_GROUP(ssi9_data), 4283 SH_PFC_PIN_GROUP(ssi9_ctrl), 4284 SH_PFC_PIN_GROUP(tpu0_to0), 4285 SH_PFC_PIN_GROUP(tpu0_to1), 4286 SH_PFC_PIN_GROUP(tpu0_to2), 4287 SH_PFC_PIN_GROUP(tpu0_to3), 4288 SH_PFC_PIN_GROUP(usb0), 4289 SH_PFC_PIN_GROUP(usb0_ovc_vbus), 4290 SH_PFC_PIN_GROUP(usb1), 4291 SH_PFC_PIN_GROUP(usb1_pwen), 4292 SH_PFC_PIN_GROUP(usb2), 4293 VIN_DATA_PIN_GROUP(vin0_data, 24), 4294 VIN_DATA_PIN_GROUP(vin0_data, 20), 4295 SH_PFC_PIN_GROUP(vin0_data18), 4296 VIN_DATA_PIN_GROUP(vin0_data, 16), 4297 VIN_DATA_PIN_GROUP(vin0_data, 12), 4298 VIN_DATA_PIN_GROUP(vin0_data, 10), 4299 VIN_DATA_PIN_GROUP(vin0_data, 8), 4300 VIN_DATA_PIN_GROUP(vin0_data, 4), 4301 SH_PFC_PIN_GROUP(vin0_sync), 4302 SH_PFC_PIN_GROUP(vin0_field), 4303 SH_PFC_PIN_GROUP(vin0_clkenb), 4304 SH_PFC_PIN_GROUP(vin0_clk), 4305 VIN_DATA_PIN_GROUP(vin1_data, 24), 4306 VIN_DATA_PIN_GROUP(vin1_data, 20), 4307 SH_PFC_PIN_GROUP(vin1_data18), 4308 VIN_DATA_PIN_GROUP(vin1_data, 16), 4309 VIN_DATA_PIN_GROUP(vin1_data, 12), 4310 VIN_DATA_PIN_GROUP(vin1_data, 10), 4311 VIN_DATA_PIN_GROUP(vin1_data, 8), 4312 VIN_DATA_PIN_GROUP(vin1_data, 4), 4313 SH_PFC_PIN_GROUP(vin1_sync), 4314 SH_PFC_PIN_GROUP(vin1_field), 4315 SH_PFC_PIN_GROUP(vin1_clkenb), 4316 SH_PFC_PIN_GROUP(vin1_clk), 4317 VIN_DATA_PIN_GROUP(vin2_data, 24), 4318 SH_PFC_PIN_GROUP(vin2_data18), 4319 VIN_DATA_PIN_GROUP(vin2_data, 16), 4320 VIN_DATA_PIN_GROUP(vin2_data, 8), 4321 VIN_DATA_PIN_GROUP(vin2_data, 4), 4322 SH_PFC_PIN_GROUP(vin2_sync), 4323 SH_PFC_PIN_GROUP(vin2_field), 4324 SH_PFC_PIN_GROUP(vin2_clkenb), 4325 SH_PFC_PIN_GROUP(vin2_clk), 4326 SH_PFC_PIN_GROUP(vin3_data8), 4327 SH_PFC_PIN_GROUP(vin3_sync), 4328 SH_PFC_PIN_GROUP(vin3_field), 4329 SH_PFC_PIN_GROUP(vin3_clkenb), 4330 SH_PFC_PIN_GROUP(vin3_clk), 4331 }, 4332 .automotive = { 4333 SH_PFC_PIN_GROUP(mlb_3pin), 4334 } 4335 }; 4336 4337 static const char * const audio_clk_groups[] = { 4338 "audio_clk_a", 4339 "audio_clk_b", 4340 "audio_clk_c", 4341 "audio_clkout", 4342 "audio_clkout_b", 4343 "audio_clkout_c", 4344 "audio_clkout_d", 4345 }; 4346 4347 static const char * const avb_groups[] = { 4348 "avb_link", 4349 "avb_magic", 4350 "avb_phy_int", 4351 "avb_mdio", 4352 "avb_mii", 4353 "avb_gmii", 4354 }; 4355 4356 static const char * const can0_groups[] = { 4357 "can0_data", 4358 "can0_data_b", 4359 "can0_data_c", 4360 "can0_data_d", 4361 }; 4362 4363 static const char * const can1_groups[] = { 4364 "can1_data", 4365 "can1_data_b", 4366 }; 4367 4368 static const char * const can_clk_groups[] = { 4369 "can_clk", 4370 "can_clk_b", 4371 }; 4372 4373 static const char * const du_groups[] = { 4374 "du_rgb666", 4375 "du_rgb888", 4376 "du_clk_out_0", 4377 "du_clk_out_1", 4378 "du_sync_0", 4379 "du_sync_1", 4380 "du_cde", 4381 }; 4382 4383 static const char * const du0_groups[] = { 4384 "du0_clk_in", 4385 }; 4386 4387 static const char * const du1_groups[] = { 4388 "du1_clk_in", 4389 }; 4390 4391 static const char * const du2_groups[] = { 4392 "du2_clk_in", 4393 }; 4394 4395 static const char * const eth_groups[] = { 4396 "eth_link", 4397 "eth_magic", 4398 "eth_mdio", 4399 "eth_rmii", 4400 }; 4401 4402 static const char * const hscif0_groups[] = { 4403 "hscif0_data", 4404 "hscif0_clk", 4405 "hscif0_ctrl", 4406 "hscif0_data_b", 4407 "hscif0_ctrl_b", 4408 "hscif0_data_c", 4409 "hscif0_ctrl_c", 4410 "hscif0_data_d", 4411 "hscif0_ctrl_d", 4412 "hscif0_data_e", 4413 "hscif0_ctrl_e", 4414 "hscif0_data_f", 4415 "hscif0_ctrl_f", 4416 }; 4417 4418 static const char * const hscif1_groups[] = { 4419 "hscif1_data", 4420 "hscif1_clk", 4421 "hscif1_ctrl", 4422 "hscif1_data_b", 4423 "hscif1_clk_b", 4424 "hscif1_ctrl_b", 4425 }; 4426 4427 static const char * const i2c0_groups[] = { 4428 "i2c0", 4429 }; 4430 4431 static const char * const i2c1_groups[] = { 4432 "i2c1", 4433 "i2c1_b", 4434 "i2c1_c", 4435 }; 4436 4437 static const char * const i2c2_groups[] = { 4438 "i2c2", 4439 "i2c2_b", 4440 "i2c2_c", 4441 "i2c2_d", 4442 "i2c2_e", 4443 }; 4444 4445 static const char * const i2c3_groups[] = { 4446 "i2c3", 4447 }; 4448 4449 static const char * const iic0_groups[] = { 4450 "iic0", 4451 }; 4452 4453 static const char * const iic1_groups[] = { 4454 "iic1", 4455 "iic1_b", 4456 "iic1_c", 4457 }; 4458 4459 static const char * const iic2_groups[] = { 4460 "iic2", 4461 "iic2_b", 4462 "iic2_c", 4463 "iic2_d", 4464 "iic2_e", 4465 }; 4466 4467 static const char * const iic3_groups[] = { 4468 "iic3", 4469 }; 4470 4471 static const char * const intc_groups[] = { 4472 "intc_irq0", 4473 "intc_irq1", 4474 "intc_irq2", 4475 "intc_irq3", 4476 }; 4477 4478 static const char * const mlb_groups[] = { 4479 "mlb_3pin", 4480 }; 4481 4482 static const char * const mmc0_groups[] = { 4483 "mmc0_data1", 4484 "mmc0_data4", 4485 "mmc0_data8", 4486 "mmc0_ctrl", 4487 }; 4488 4489 static const char * const mmc1_groups[] = { 4490 "mmc1_data1", 4491 "mmc1_data4", 4492 "mmc1_data8", 4493 "mmc1_ctrl", 4494 }; 4495 4496 static const char * const msiof0_groups[] = { 4497 "msiof0_clk", 4498 "msiof0_sync", 4499 "msiof0_ss1", 4500 "msiof0_ss2", 4501 "msiof0_rx", 4502 "msiof0_tx", 4503 "msiof0_clk_b", 4504 "msiof0_ss1_b", 4505 "msiof0_ss2_b", 4506 "msiof0_rx_b", 4507 "msiof0_tx_b", 4508 }; 4509 4510 static const char * const msiof1_groups[] = { 4511 "msiof1_clk", 4512 "msiof1_sync", 4513 "msiof1_ss1", 4514 "msiof1_ss2", 4515 "msiof1_rx", 4516 "msiof1_tx", 4517 "msiof1_clk_b", 4518 "msiof1_ss1_b", 4519 "msiof1_ss2_b", 4520 "msiof1_rx_b", 4521 "msiof1_tx_b", 4522 }; 4523 4524 static const char * const msiof2_groups[] = { 4525 "msiof2_clk", 4526 "msiof2_sync", 4527 "msiof2_ss1", 4528 "msiof2_ss2", 4529 "msiof2_rx", 4530 "msiof2_tx", 4531 }; 4532 4533 static const char * const msiof3_groups[] = { 4534 "msiof3_clk", 4535 "msiof3_sync", 4536 "msiof3_ss1", 4537 "msiof3_ss2", 4538 "msiof3_rx", 4539 "msiof3_tx", 4540 "msiof3_clk_b", 4541 "msiof3_sync_b", 4542 "msiof3_rx_b", 4543 "msiof3_tx_b", 4544 }; 4545 4546 static const char * const pwm0_groups[] = { 4547 "pwm0", 4548 "pwm0_b", 4549 }; 4550 4551 static const char * const pwm1_groups[] = { 4552 "pwm1", 4553 "pwm1_b", 4554 }; 4555 4556 static const char * const pwm2_groups[] = { 4557 "pwm2", 4558 }; 4559 4560 static const char * const pwm3_groups[] = { 4561 "pwm3", 4562 }; 4563 4564 static const char * const pwm4_groups[] = { 4565 "pwm4", 4566 }; 4567 4568 static const char * const pwm5_groups[] = { 4569 "pwm5", 4570 }; 4571 4572 static const char * const pwm6_groups[] = { 4573 "pwm6", 4574 }; 4575 4576 static const char * const qspi_groups[] = { 4577 "qspi_ctrl", 4578 "qspi_data2", 4579 "qspi_data4", 4580 }; 4581 4582 static const char * const scif0_groups[] = { 4583 "scif0_data", 4584 "scif0_clk", 4585 "scif0_ctrl", 4586 "scif0_data_b", 4587 }; 4588 4589 static const char * const scif1_groups[] = { 4590 "scif1_data", 4591 "scif1_clk", 4592 "scif1_ctrl", 4593 "scif1_data_b", 4594 "scif1_data_c", 4595 "scif1_data_d", 4596 "scif1_clk_d", 4597 "scif1_data_e", 4598 "scif1_clk_e", 4599 }; 4600 4601 static const char * const scif2_groups[] = { 4602 "scif2_data", 4603 "scif2_clk", 4604 "scif2_data_b", 4605 }; 4606 4607 static const char * const scifa0_groups[] = { 4608 "scifa0_data", 4609 "scifa0_clk", 4610 "scifa0_ctrl", 4611 "scifa0_data_b", 4612 "scifa0_clk_b", 4613 "scifa0_ctrl_b", 4614 }; 4615 4616 static const char * const scifa1_groups[] = { 4617 "scifa1_data", 4618 "scifa1_clk", 4619 "scifa1_ctrl", 4620 "scifa1_data_b", 4621 "scifa1_clk_b", 4622 "scifa1_ctrl_b", 4623 "scifa1_data_c", 4624 "scifa1_clk_c", 4625 "scifa1_ctrl_c", 4626 "scifa1_data_d", 4627 "scifa1_clk_d", 4628 "scifa1_ctrl_d", 4629 }; 4630 4631 static const char * const scifa2_groups[] = { 4632 "scifa2_data", 4633 "scifa2_clk", 4634 "scifa2_ctrl", 4635 "scifa2_data_b", 4636 "scifa2_data_c", 4637 "scifa2_clk_c", 4638 }; 4639 4640 static const char * const scifb0_groups[] = { 4641 "scifb0_data", 4642 "scifb0_clk", 4643 "scifb0_ctrl", 4644 "scifb0_data_b", 4645 "scifb0_clk_b", 4646 "scifb0_ctrl_b", 4647 "scifb0_data_c", 4648 }; 4649 4650 static const char * const scifb1_groups[] = { 4651 "scifb1_data", 4652 "scifb1_clk", 4653 "scifb1_ctrl", 4654 "scifb1_data_b", 4655 "scifb1_clk_b", 4656 "scifb1_ctrl_b", 4657 "scifb1_data_c", 4658 "scifb1_data_d", 4659 "scifb1_data_e", 4660 "scifb1_clk_e", 4661 "scifb1_data_f", 4662 "scifb1_data_g", 4663 "scifb1_clk_g", 4664 }; 4665 4666 static const char * const scifb2_groups[] = { 4667 "scifb2_data", 4668 "scifb2_clk", 4669 "scifb2_ctrl", 4670 "scifb2_data_b", 4671 "scifb2_clk_b", 4672 "scifb2_ctrl_b", 4673 "scifb2_data_c", 4674 }; 4675 4676 static const char * const scif_clk_groups[] = { 4677 "scif_clk", 4678 "scif_clk_b", 4679 }; 4680 4681 static const char * const sdhi0_groups[] = { 4682 "sdhi0_data1", 4683 "sdhi0_data4", 4684 "sdhi0_ctrl", 4685 "sdhi0_cd", 4686 "sdhi0_wp", 4687 }; 4688 4689 static const char * const sdhi1_groups[] = { 4690 "sdhi1_data1", 4691 "sdhi1_data4", 4692 "sdhi1_ctrl", 4693 "sdhi1_cd", 4694 "sdhi1_wp", 4695 }; 4696 4697 static const char * const sdhi2_groups[] = { 4698 "sdhi2_data1", 4699 "sdhi2_data4", 4700 "sdhi2_ctrl", 4701 "sdhi2_cd", 4702 "sdhi2_wp", 4703 }; 4704 4705 static const char * const sdhi3_groups[] = { 4706 "sdhi3_data1", 4707 "sdhi3_data4", 4708 "sdhi3_ctrl", 4709 "sdhi3_cd", 4710 "sdhi3_wp", 4711 }; 4712 4713 static const char * const ssi_groups[] = { 4714 "ssi0_data", 4715 "ssi0129_ctrl", 4716 "ssi1_data", 4717 "ssi1_ctrl", 4718 "ssi2_data", 4719 "ssi2_ctrl", 4720 "ssi3_data", 4721 "ssi34_ctrl", 4722 "ssi4_data", 4723 "ssi4_ctrl", 4724 "ssi5", 4725 "ssi5_b", 4726 "ssi5_c", 4727 "ssi6", 4728 "ssi6_b", 4729 "ssi7_data", 4730 "ssi7_b_data", 4731 "ssi7_c_data", 4732 "ssi78_ctrl", 4733 "ssi78_b_ctrl", 4734 "ssi78_c_ctrl", 4735 "ssi8_data", 4736 "ssi8_b_data", 4737 "ssi8_c_data", 4738 "ssi9_data", 4739 "ssi9_ctrl", 4740 }; 4741 4742 static const char * const tpu0_groups[] = { 4743 "tpu0_to0", 4744 "tpu0_to1", 4745 "tpu0_to2", 4746 "tpu0_to3", 4747 }; 4748 4749 static const char * const usb0_groups[] = { 4750 "usb0", 4751 "usb0_ovc_vbus", 4752 }; 4753 4754 static const char * const usb1_groups[] = { 4755 "usb1", 4756 "usb1_pwen", 4757 }; 4758 4759 static const char * const usb2_groups[] = { 4760 "usb2", 4761 }; 4762 4763 static const char * const vin0_groups[] = { 4764 "vin0_data24", 4765 "vin0_data20", 4766 "vin0_data18", 4767 "vin0_data16", 4768 "vin0_data12", 4769 "vin0_data10", 4770 "vin0_data8", 4771 "vin0_data4", 4772 "vin0_sync", 4773 "vin0_field", 4774 "vin0_clkenb", 4775 "vin0_clk", 4776 }; 4777 4778 static const char * const vin1_groups[] = { 4779 "vin1_data24", 4780 "vin1_data20", 4781 "vin1_data18", 4782 "vin1_data16", 4783 "vin1_data12", 4784 "vin1_data10", 4785 "vin1_data8", 4786 "vin1_data4", 4787 "vin1_sync", 4788 "vin1_field", 4789 "vin1_clkenb", 4790 "vin1_clk", 4791 }; 4792 4793 static const char * const vin2_groups[] = { 4794 "vin2_data24", 4795 "vin2_data18", 4796 "vin2_data16", 4797 "vin2_data8", 4798 "vin2_data4", 4799 "vin2_sync", 4800 "vin2_field", 4801 "vin2_clkenb", 4802 "vin2_clk", 4803 }; 4804 4805 static const char * const vin3_groups[] = { 4806 "vin3_data8", 4807 "vin3_sync", 4808 "vin3_field", 4809 "vin3_clkenb", 4810 "vin3_clk", 4811 }; 4812 4813 static const struct { 4814 struct sh_pfc_function common[58]; 4815 struct sh_pfc_function automotive[1]; 4816 } pinmux_functions = { 4817 .common = { 4818 SH_PFC_FUNCTION(audio_clk), 4819 SH_PFC_FUNCTION(avb), 4820 SH_PFC_FUNCTION(du), 4821 SH_PFC_FUNCTION(can0), 4822 SH_PFC_FUNCTION(can1), 4823 SH_PFC_FUNCTION(can_clk), 4824 SH_PFC_FUNCTION(du0), 4825 SH_PFC_FUNCTION(du1), 4826 SH_PFC_FUNCTION(du2), 4827 SH_PFC_FUNCTION(eth), 4828 SH_PFC_FUNCTION(hscif0), 4829 SH_PFC_FUNCTION(hscif1), 4830 SH_PFC_FUNCTION(i2c0), 4831 SH_PFC_FUNCTION(i2c1), 4832 SH_PFC_FUNCTION(i2c2), 4833 SH_PFC_FUNCTION(i2c3), 4834 SH_PFC_FUNCTION(iic0), 4835 SH_PFC_FUNCTION(iic1), 4836 SH_PFC_FUNCTION(iic2), 4837 SH_PFC_FUNCTION(iic3), 4838 SH_PFC_FUNCTION(intc), 4839 SH_PFC_FUNCTION(mmc0), 4840 SH_PFC_FUNCTION(mmc1), 4841 SH_PFC_FUNCTION(msiof0), 4842 SH_PFC_FUNCTION(msiof1), 4843 SH_PFC_FUNCTION(msiof2), 4844 SH_PFC_FUNCTION(msiof3), 4845 SH_PFC_FUNCTION(pwm0), 4846 SH_PFC_FUNCTION(pwm1), 4847 SH_PFC_FUNCTION(pwm2), 4848 SH_PFC_FUNCTION(pwm3), 4849 SH_PFC_FUNCTION(pwm4), 4850 SH_PFC_FUNCTION(pwm5), 4851 SH_PFC_FUNCTION(pwm6), 4852 SH_PFC_FUNCTION(qspi), 4853 SH_PFC_FUNCTION(scif0), 4854 SH_PFC_FUNCTION(scif1), 4855 SH_PFC_FUNCTION(scif2), 4856 SH_PFC_FUNCTION(scifa0), 4857 SH_PFC_FUNCTION(scifa1), 4858 SH_PFC_FUNCTION(scifa2), 4859 SH_PFC_FUNCTION(scifb0), 4860 SH_PFC_FUNCTION(scifb1), 4861 SH_PFC_FUNCTION(scifb2), 4862 SH_PFC_FUNCTION(scif_clk), 4863 SH_PFC_FUNCTION(sdhi0), 4864 SH_PFC_FUNCTION(sdhi1), 4865 SH_PFC_FUNCTION(sdhi2), 4866 SH_PFC_FUNCTION(sdhi3), 4867 SH_PFC_FUNCTION(ssi), 4868 SH_PFC_FUNCTION(tpu0), 4869 SH_PFC_FUNCTION(usb0), 4870 SH_PFC_FUNCTION(usb1), 4871 SH_PFC_FUNCTION(usb2), 4872 SH_PFC_FUNCTION(vin0), 4873 SH_PFC_FUNCTION(vin1), 4874 SH_PFC_FUNCTION(vin2), 4875 SH_PFC_FUNCTION(vin3), 4876 }, 4877 .automotive = { 4878 SH_PFC_FUNCTION(mlb), 4879 } 4880 }; 4881 4882 static const struct pinmux_cfg_reg pinmux_config_regs[] = { 4883 { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1, GROUP( 4884 GP_0_31_FN, FN_IP3_17_15, 4885 GP_0_30_FN, FN_IP3_14_12, 4886 GP_0_29_FN, FN_IP3_11_8, 4887 GP_0_28_FN, FN_IP3_7_4, 4888 GP_0_27_FN, FN_IP3_3_0, 4889 GP_0_26_FN, FN_IP2_28_26, 4890 GP_0_25_FN, FN_IP2_25_22, 4891 GP_0_24_FN, FN_IP2_21_18, 4892 GP_0_23_FN, FN_IP2_17_15, 4893 GP_0_22_FN, FN_IP2_14_12, 4894 GP_0_21_FN, FN_IP2_11_9, 4895 GP_0_20_FN, FN_IP2_8_6, 4896 GP_0_19_FN, FN_IP2_5_3, 4897 GP_0_18_FN, FN_IP2_2_0, 4898 GP_0_17_FN, FN_IP1_29_28, 4899 GP_0_16_FN, FN_IP1_27_26, 4900 GP_0_15_FN, FN_IP1_25_22, 4901 GP_0_14_FN, FN_IP1_21_18, 4902 GP_0_13_FN, FN_IP1_17_15, 4903 GP_0_12_FN, FN_IP1_14_12, 4904 GP_0_11_FN, FN_IP1_11_8, 4905 GP_0_10_FN, FN_IP1_7_4, 4906 GP_0_9_FN, FN_IP1_3_0, 4907 GP_0_8_FN, FN_IP0_30_27, 4908 GP_0_7_FN, FN_IP0_26_23, 4909 GP_0_6_FN, FN_IP0_22_20, 4910 GP_0_5_FN, FN_IP0_19_16, 4911 GP_0_4_FN, FN_IP0_15_12, 4912 GP_0_3_FN, FN_IP0_11_9, 4913 GP_0_2_FN, FN_IP0_8_6, 4914 GP_0_1_FN, FN_IP0_5_3, 4915 GP_0_0_FN, FN_IP0_2_0 )) 4916 }, 4917 { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1, GROUP( 4918 0, 0, 4919 0, 0, 4920 GP_1_29_FN, FN_IP6_13_11, 4921 GP_1_28_FN, FN_IP6_10_9, 4922 GP_1_27_FN, FN_IP6_8_6, 4923 GP_1_26_FN, FN_IP6_5_3, 4924 GP_1_25_FN, FN_IP6_2_0, 4925 GP_1_24_FN, FN_IP5_29_27, 4926 GP_1_23_FN, FN_IP5_26_24, 4927 GP_1_22_FN, FN_IP5_23_21, 4928 GP_1_21_FN, FN_IP5_20_18, 4929 GP_1_20_FN, FN_IP5_17_15, 4930 GP_1_19_FN, FN_IP5_14_13, 4931 GP_1_18_FN, FN_IP5_12_10, 4932 GP_1_17_FN, FN_IP5_9_6, 4933 GP_1_16_FN, FN_IP5_5_3, 4934 GP_1_15_FN, FN_IP5_2_0, 4935 GP_1_14_FN, FN_IP4_29_27, 4936 GP_1_13_FN, FN_IP4_26_24, 4937 GP_1_12_FN, FN_IP4_23_21, 4938 GP_1_11_FN, FN_IP4_20_18, 4939 GP_1_10_FN, FN_IP4_17_15, 4940 GP_1_9_FN, FN_IP4_14_12, 4941 GP_1_8_FN, FN_IP4_11_9, 4942 GP_1_7_FN, FN_IP4_8_6, 4943 GP_1_6_FN, FN_IP4_5_3, 4944 GP_1_5_FN, FN_IP4_2_0, 4945 GP_1_4_FN, FN_IP3_31_29, 4946 GP_1_3_FN, FN_IP3_28_26, 4947 GP_1_2_FN, FN_IP3_25_23, 4948 GP_1_1_FN, FN_IP3_22_20, 4949 GP_1_0_FN, FN_IP3_19_18, )) 4950 }, 4951 { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1, GROUP( 4952 0, 0, 4953 0, 0, 4954 GP_2_29_FN, FN_IP7_15_13, 4955 GP_2_28_FN, FN_IP7_12_10, 4956 GP_2_27_FN, FN_IP7_9_8, 4957 GP_2_26_FN, FN_IP7_7_6, 4958 GP_2_25_FN, FN_IP7_5_3, 4959 GP_2_24_FN, FN_IP7_2_0, 4960 GP_2_23_FN, FN_IP6_31_29, 4961 GP_2_22_FN, FN_IP6_28_26, 4962 GP_2_21_FN, FN_IP6_25_23, 4963 GP_2_20_FN, FN_IP6_22_20, 4964 GP_2_19_FN, FN_IP6_19_17, 4965 GP_2_18_FN, FN_IP6_16_14, 4966 GP_2_17_FN, FN_VI1_DATA7_VI1_B7, 4967 GP_2_16_FN, FN_IP8_27, 4968 GP_2_15_FN, FN_IP8_26, 4969 GP_2_14_FN, FN_IP8_25_24, 4970 GP_2_13_FN, FN_IP8_23_22, 4971 GP_2_12_FN, FN_IP8_21_20, 4972 GP_2_11_FN, FN_IP8_19_18, 4973 GP_2_10_FN, FN_IP8_17_16, 4974 GP_2_9_FN, FN_IP8_15_14, 4975 GP_2_8_FN, FN_IP8_13_12, 4976 GP_2_7_FN, FN_IP8_11_10, 4977 GP_2_6_FN, FN_IP8_9_8, 4978 GP_2_5_FN, FN_IP8_7_6, 4979 GP_2_4_FN, FN_IP8_5_4, 4980 GP_2_3_FN, FN_IP8_3_2, 4981 GP_2_2_FN, FN_IP8_1_0, 4982 GP_2_1_FN, FN_IP7_30_29, 4983 GP_2_0_FN, FN_IP7_28_27 )) 4984 }, 4985 { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1, GROUP( 4986 GP_3_31_FN, FN_IP11_21_18, 4987 GP_3_30_FN, FN_IP11_17_15, 4988 GP_3_29_FN, FN_IP11_14_13, 4989 GP_3_28_FN, FN_IP11_12_11, 4990 GP_3_27_FN, FN_IP11_10_9, 4991 GP_3_26_FN, FN_IP11_8_7, 4992 GP_3_25_FN, FN_IP11_6_5, 4993 GP_3_24_FN, FN_IP11_4, 4994 GP_3_23_FN, FN_IP11_3_0, 4995 GP_3_22_FN, FN_IP10_29_26, 4996 GP_3_21_FN, FN_IP10_25_23, 4997 GP_3_20_FN, FN_IP10_22_19, 4998 GP_3_19_FN, FN_IP10_18_15, 4999 GP_3_18_FN, FN_IP10_14_11, 5000 GP_3_17_FN, FN_IP10_10_7, 5001 GP_3_16_FN, FN_IP10_6_4, 5002 GP_3_15_FN, FN_IP10_3_0, 5003 GP_3_14_FN, FN_IP9_31_28, 5004 GP_3_13_FN, FN_IP9_27_26, 5005 GP_3_12_FN, FN_IP9_25_24, 5006 GP_3_11_FN, FN_IP9_23_22, 5007 GP_3_10_FN, FN_IP9_21_20, 5008 GP_3_9_FN, FN_IP9_19_18, 5009 GP_3_8_FN, FN_IP9_17_16, 5010 GP_3_7_FN, FN_IP9_15_12, 5011 GP_3_6_FN, FN_IP9_11_8, 5012 GP_3_5_FN, FN_IP9_7_6, 5013 GP_3_4_FN, FN_IP9_5_4, 5014 GP_3_3_FN, FN_IP9_3_2, 5015 GP_3_2_FN, FN_IP9_1_0, 5016 GP_3_1_FN, FN_IP8_30_29, 5017 GP_3_0_FN, FN_IP8_28 )) 5018 }, 5019 { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1, GROUP( 5020 GP_4_31_FN, FN_IP14_18_16, 5021 GP_4_30_FN, FN_IP14_15_12, 5022 GP_4_29_FN, FN_IP14_11_9, 5023 GP_4_28_FN, FN_IP14_8_6, 5024 GP_4_27_FN, FN_IP14_5_3, 5025 GP_4_26_FN, FN_IP14_2_0, 5026 GP_4_25_FN, FN_IP13_30_29, 5027 GP_4_24_FN, FN_IP13_28_26, 5028 GP_4_23_FN, FN_IP13_25_23, 5029 GP_4_22_FN, FN_IP13_22_19, 5030 GP_4_21_FN, FN_IP13_18_16, 5031 GP_4_20_FN, FN_IP13_15_13, 5032 GP_4_19_FN, FN_IP13_12_10, 5033 GP_4_18_FN, FN_IP13_9_7, 5034 GP_4_17_FN, FN_IP13_6_3, 5035 GP_4_16_FN, FN_IP13_2_0, 5036 GP_4_15_FN, FN_IP12_30_28, 5037 GP_4_14_FN, FN_IP12_27_25, 5038 GP_4_13_FN, FN_IP12_24_23, 5039 GP_4_12_FN, FN_IP12_22_20, 5040 GP_4_11_FN, FN_IP12_19_17, 5041 GP_4_10_FN, FN_IP12_16_14, 5042 GP_4_9_FN, FN_IP12_13_11, 5043 GP_4_8_FN, FN_IP12_10_8, 5044 GP_4_7_FN, FN_IP12_7_6, 5045 GP_4_6_FN, FN_IP12_5_4, 5046 GP_4_5_FN, FN_IP12_3_2, 5047 GP_4_4_FN, FN_IP12_1_0, 5048 GP_4_3_FN, FN_IP11_31_30, 5049 GP_4_2_FN, FN_IP11_29_27, 5050 GP_4_1_FN, FN_IP11_26_24, 5051 GP_4_0_FN, FN_IP11_23_22 )) 5052 }, 5053 { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1, GROUP( 5054 GP_5_31_FN, FN_IP7_24_22, 5055 GP_5_30_FN, FN_IP7_21_19, 5056 GP_5_29_FN, FN_IP7_18_16, 5057 GP_5_28_FN, FN_DU_DOTCLKIN2, 5058 GP_5_27_FN, FN_IP7_26_25, 5059 GP_5_26_FN, FN_DU_DOTCLKIN0, 5060 GP_5_25_FN, FN_AVS2, 5061 GP_5_24_FN, FN_AVS1, 5062 GP_5_23_FN, FN_USB2_OVC, 5063 GP_5_22_FN, FN_USB2_PWEN, 5064 GP_5_21_FN, FN_IP16_7, 5065 GP_5_20_FN, FN_IP16_6, 5066 GP_5_19_FN, FN_USB0_OVC_VBUS, 5067 GP_5_18_FN, FN_USB0_PWEN, 5068 GP_5_17_FN, FN_IP16_5_3, 5069 GP_5_16_FN, FN_IP16_2_0, 5070 GP_5_15_FN, FN_IP15_29_28, 5071 GP_5_14_FN, FN_IP15_27_26, 5072 GP_5_13_FN, FN_IP15_25_23, 5073 GP_5_12_FN, FN_IP15_22_20, 5074 GP_5_11_FN, FN_IP15_19_18, 5075 GP_5_10_FN, FN_IP15_17_16, 5076 GP_5_9_FN, FN_IP15_15_14, 5077 GP_5_8_FN, FN_IP15_13_12, 5078 GP_5_7_FN, FN_IP15_11_9, 5079 GP_5_6_FN, FN_IP15_8_6, 5080 GP_5_5_FN, FN_IP15_5_3, 5081 GP_5_4_FN, FN_IP15_2_0, 5082 GP_5_3_FN, FN_IP14_30_28, 5083 GP_5_2_FN, FN_IP14_27_25, 5084 GP_5_1_FN, FN_IP14_24_22, 5085 GP_5_0_FN, FN_IP14_21_19 )) 5086 }, 5087 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32, 5088 GROUP(1, 4, 4, 3, 4, 4, 3, 3, 3, 3), 5089 GROUP( 5090 /* IP0_31 [1] */ 5091 0, 0, 5092 /* IP0_30_27 [4] */ 5093 FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0, 0, 5094 FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0, 5095 0, 0, 0, 0, 0, 0, 0, 0, 0, 5096 /* IP0_26_23 [4] */ 5097 FN_D7, FN_AD_DI_B, FN_IIC2_SDA_C, 5098 FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_I2C2_SDA_C, 5099 FN_TCLK1, 0, 0, 0, 0, 0, 0, 0, 0, 5100 /* IP0_22_20 [3] */ 5101 FN_D6, FN_IIC2_SCL_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B, 5102 FN_I2C2_SCL_C, 0, 0, 5103 /* IP0_19_16 [4] */ 5104 FN_D5, FN_SCIFB1_TXD_F, FN_SCIFB0_TXD_C, FN_VI3_DATA5, 5105 FN_VI0_R1, FN_VI0_R1_B, FN_TX0_B, 5106 0, 0, 0, 0, 0, 0, 0, 0, 0, 5107 /* IP0_15_12 [4] */ 5108 FN_D4, FN_SCIFB1_RXD_F, FN_SCIFB0_RXD_C, FN_VI3_DATA4, 5109 FN_VI0_R0, FN_VI0_R0_B, FN_RX0_B, 5110 0, 0, 0, 0, 0, 0, 0, 0, 0, 5111 /* IP0_11_9 [3] */ 5112 FN_D3, FN_MSIOF3_TXD_B, FN_VI3_DATA3, FN_VI0_G7, FN_VI0_G7_B, 5113 0, 0, 0, 5114 /* IP0_8_6 [3] */ 5115 FN_D2, FN_MSIOF3_RXD_B, FN_VI3_DATA2, FN_VI0_G6, FN_VI0_G6_B, 5116 0, 0, 0, 5117 /* IP0_5_3 [3] */ 5118 FN_D1, FN_MSIOF3_SYNC_B, FN_VI3_DATA1, FN_VI0_G5, FN_VI0_G5_B, 5119 0, 0, 0, 5120 /* IP0_2_0 [3] */ 5121 FN_D0, FN_MSIOF3_SCK_B, FN_VI3_DATA0, FN_VI0_G4, FN_VI0_G4_B, 5122 0, 0, 0, )) 5123 }, 5124 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32, 5125 GROUP(2, 2, 2, 4, 4, 3, 3, 4, 4, 4), 5126 GROUP( 5127 /* IP1_31_30 [2] */ 5128 0, 0, 0, 0, 5129 /* IP1_29_28 [2] */ 5130 FN_A1, FN_PWM4, 0, 0, 5131 /* IP1_27_26 [2] */ 5132 FN_A0, FN_PWM3, 0, 0, 5133 /* IP1_25_22 [4] */ 5134 FN_D15, FN_SCIFB1_TXD_C, FN_AVB_TXD7, FN_TX1_B, 5135 FN_VI0_FIELD, FN_VI0_FIELD_B, FN_VI2_DATA7_VI2_B7, 5136 0, 0, 0, 0, 0, 0, 0, 0, 0, 5137 /* IP1_21_18 [4] */ 5138 FN_D14, FN_SCIFB1_RXD_C, FN_AVB_TXD6, FN_RX1_B, 5139 FN_VI0_CLKENB, FN_VI0_CLKENB_B, FN_VI2_DATA6_VI2_B6, 5140 0, 0, 0, 0, 0, 0, 0, 0, 0, 5141 /* IP1_17_15 [3] */ 5142 FN_D13, FN_AVB_TXD5, FN_VI0_VSYNC_N, 5143 FN_VI0_VSYNC_N_B, FN_VI2_DATA5_VI2_B5, 5144 0, 0, 0, 5145 /* IP1_14_12 [3] */ 5146 FN_D12, FN_SCIFA1_RTS_N_C, FN_AVB_TXD4, 5147 FN_VI0_HSYNC_N, FN_VI0_HSYNC_N_B, FN_VI2_DATA4_VI2_B4, 5148 0, 0, 5149 /* IP1_11_8 [4] */ 5150 FN_D11, FN_SCIFA1_CTS_N_C, FN_AVB_TXD3, 0, 5151 FN_VI0_G3, FN_VI0_G3_B, FN_VI2_DATA3_VI2_B3, 5152 0, 0, 0, 0, 0, 0, 0, 0, 0, 5153 /* IP1_7_4 [4] */ 5154 FN_D10, FN_SCIFA1_TXD_C, FN_AVB_TXD2, 0, 5155 FN_VI0_G2, FN_VI0_G2_B, FN_VI2_DATA2_VI2_B2, 5156 0, 0, 0, 0, 0, 0, 0, 0, 0, 5157 /* IP1_3_0 [4] */ 5158 FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1, 0, 5159 FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1, 5160 0, 0, 0, 0, 0, 0, 0, 0, 0, )) 5161 }, 5162 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32, 5163 GROUP(3, 3, 4, 4, 3, 3, 3, 3, 3, 3), 5164 GROUP( 5165 /* IP2_31_29 [3] */ 5166 0, 0, 0, 0, 0, 0, 0, 0, 5167 /* IP2_28_26 [3] */ 5168 FN_A10, FN_SSI_SDATA5_B, FN_MSIOF2_SYNC, FN_VI0_R6, 5169 FN_VI0_R6_B, FN_VI2_DATA2_VI2_B2_B, 0, 0, 5170 /* IP2_25_22 [4] */ 5171 FN_A9, FN_SCIFA1_CTS_N_B, FN_SSI_WS5_B, FN_VI0_R5, 5172 FN_VI0_R5_B, FN_SCIFB2_TXD_C, FN_TX2_B, FN_VI2_DATA1_VI2_B1_B, 5173 0, 0, 0, 0, 0, 0, 0, 0, 5174 /* IP2_21_18 [4] */ 5175 FN_A8, FN_SCIFA1_RXD_B, FN_SSI_SCK5_B, FN_VI0_R4, 5176 FN_VI0_R4_B, FN_SCIFB2_RXD_C, FN_RX2_B, FN_VI2_DATA0_VI2_B0_B, 5177 0, 0, 0, 0, 0, 0, 0, 0, 5178 /* IP2_17_15 [3] */ 5179 FN_A7, FN_SCIFA1_SCK_B, FN_AUDIO_CLKOUT_B, FN_TPU0TO3, 5180 0, 0, 0, 0, 5181 /* IP2_14_12 [3] */ 5182 FN_A6, FN_SCIFA1_RTS_N_B, FN_TPU0TO2, 0, 0, 0, 0, 0, 5183 /* IP2_11_9 [3] */ 5184 FN_A5, FN_SCIFA1_TXD_B, FN_TPU0TO1, 0, 0, 0, 0, 0, 5185 /* IP2_8_6 [3] */ 5186 FN_A4, FN_MSIOF1_TXD_B, FN_TPU0TO0, 0, 0, 0, 0, 0, 5187 /* IP2_5_3 [3] */ 5188 FN_A3, FN_PWM6, FN_MSIOF1_SS2_B, 0, 0, 0, 0, 0, 5189 /* IP2_2_0 [3] */ 5190 FN_A2, FN_PWM5, FN_MSIOF1_SS1_B, 0, 0, 0, 0, 0, )) 5191 }, 5192 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32, 5193 GROUP(3, 3, 3, 3, 2, 3, 3, 4, 4, 4), 5194 GROUP( 5195 /* IP3_31_29 [3] */ 5196 FN_A20, FN_SPCLK, FN_VI1_R3, FN_VI1_R3_B, FN_VI2_G4, 5197 0, 0, 0, 5198 /* IP3_28_26 [3] */ 5199 FN_A19, FN_AD_NCS_N_B, FN_ATACS01_N, FN_EX_WAIT0_B, 5200 0, 0, 0, 0, 5201 /* IP3_25_23 [3] */ 5202 FN_A18, FN_AD_CLK_B, FN_ATAG1_N, 0, 0, 0, 0, 0, 5203 /* IP3_22_20 [3] */ 5204 FN_A17, FN_AD_DO_B, FN_ATADIR1_N, 0, 0, 0, 0, 0, 5205 /* IP3_19_18 [2] */ 5206 FN_A16, FN_ATAWR1_N, 0, 0, 5207 /* IP3_17_15 [3] */ 5208 FN_A15, FN_SCIFB2_SCK_B, FN_ATARD1_N, FN_MSIOF2_SS2, 5209 0, 0, 0, 0, 5210 /* IP3_14_12 [3] */ 5211 FN_A14, FN_SCIFB2_TXD_B, FN_ATACS11_N, FN_MSIOF2_SS1, 5212 0, 0, 0, 0, 5213 /* IP3_11_8 [4] */ 5214 FN_A13, FN_SCIFB2_RTS_N_B, FN_EX_WAIT2, 5215 FN_MSIOF2_RXD, FN_VI1_R2, FN_VI1_R2_B, FN_VI2_G2, 5216 FN_VI2_DATA5_VI2_B5_B, 0, 0, 0, 0, 0, 0, 0, 0, 5217 /* IP3_7_4 [4] */ 5218 FN_A12, FN_SCIFB2_RXD_B, FN_MSIOF2_TXD, FN_VI1_R1, 5219 FN_VI1_R1_B, FN_VI2_G1, FN_VI2_DATA4_VI2_B4_B, 5220 0, 0, 0, 0, 0, 0, 0, 0, 0, 5221 /* IP3_3_0 [4] */ 5222 FN_A11, FN_SCIFB2_CTS_N_B, FN_MSIOF2_SCK, FN_VI1_R0, 5223 FN_VI1_R0_B, FN_VI2_G0, FN_VI2_DATA3_VI2_B3_B, 0, 5224 0, 0, 0, 0, 0, 0, 0, 0, )) 5225 }, 5226 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32, 5227 GROUP(2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3), 5228 GROUP( 5229 /* IP4_31_30 [2] */ 5230 0, 0, 0, 0, 5231 /* IP4_29_27 [3] */ 5232 FN_EX_CS2_N, FN_GPS_SIGN, FN_HRTS1_N_B, 5233 FN_VI3_CLKENB, FN_VI1_G0, FN_VI1_G0_B, FN_VI2_R2, 0, 5234 /* IP4_26_24 [3] */ 5235 FN_EX_CS1_N, FN_GPS_CLK, FN_HCTS1_N_B, FN_VI1_FIELD, 5236 FN_VI1_FIELD_B, FN_VI2_R1, 0, 0, 5237 /* IP4_23_21 [3] */ 5238 FN_EX_CS0_N, FN_HRX1_B, FN_VI1_G5, FN_VI1_G5_B, FN_VI2_R0, 5239 FN_HTX0_B, FN_MSIOF0_SS1_B, 0, 5240 /* IP4_20_18 [3] */ 5241 FN_CS1_N_A26, FN_SPEEDIN, FN_VI0_R7, FN_VI0_R7_B, 5242 FN_VI2_CLK, FN_VI2_CLK_B, 0, 0, 5243 /* IP4_17_15 [3] */ 5244 FN_CS0_N, FN_VI1_R6, FN_VI1_R6_B, FN_VI2_G3, FN_MSIOF0_SS2_B, 5245 0, 0, 0, 5246 /* IP4_14_12 [3] */ 5247 FN_A25, FN_SSL, FN_VI1_G6, FN_VI1_G6_B, FN_VI2_FIELD, 5248 FN_VI2_FIELD_B, 0, 0, 5249 /* IP4_11_9 [3] */ 5250 FN_A24, FN_IO3, FN_VI1_R7, FN_VI1_R7_B, FN_VI2_CLKENB, 5251 FN_VI2_CLKENB_B, 0, 0, 5252 /* IP4_8_6 [3] */ 5253 FN_A23, FN_IO2, FN_VI1_G7, FN_VI1_G7_B, FN_VI2_G7, 0, 0, 0, 5254 /* IP4_5_3 [3] */ 5255 FN_A22, FN_MISO_IO1, FN_VI1_R5, FN_VI1_R5_B, FN_VI2_G6, 0, 0, 0, 5256 /* IP4_2_0 [3] */ 5257 FN_A21, FN_MOSI_IO0, FN_VI1_R4, FN_VI1_R4_B, FN_VI2_G5, 0, 0, 0, 5258 )) 5259 }, 5260 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32, 5261 GROUP(2, 3, 3, 3, 3, 3, 2, 3, 4, 3, 3), 5262 GROUP( 5263 /* IP5_31_30 [2] */ 5264 0, 0, 0, 0, 5265 /* IP5_29_27 [3] */ 5266 FN_DREQ0_N, FN_VI1_HSYNC_N, FN_VI1_HSYNC_N_B, FN_VI2_R7, 5267 FN_SSI_SCK78_C, FN_SSI_WS78_B, 0, 0, 5268 /* IP5_26_24 [3] */ 5269 FN_EX_WAIT0, FN_IRQ3, FN_INTC_IRQ3_N, 5270 FN_VI3_CLK, FN_SCIFA0_RTS_N_B, FN_HRX0_B, 5271 FN_MSIOF0_SCK_B, 0, 5272 /* IP5_23_21 [3] */ 5273 FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4, 5274 FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B, FN_IERX_C, 5275 /* IP5_20_18 [3] */ 5276 FN_WE0_N, FN_IECLK, FN_CAN_CLK, 5277 FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B, 0, 0, 5278 /* IP5_17_15 [3] */ 5279 FN_RD_WR_N, FN_VI1_G3, FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B, 5280 FN_INTC_IRQ4_N, 0, 0, 5281 /* IP5_14_13 [2] */ 5282 FN_RD_N, FN_CAN0_TX, FN_SCIFA0_SCK_B, 0, 5283 /* IP5_12_10 [3] */ 5284 FN_BS_N, FN_IETX, FN_HTX1_B, FN_CAN1_TX, FN_DRACK0, FN_IETX_C, 5285 0, 0, 5286 /* IP5_9_6 [4] */ 5287 FN_EX_CS5_N, FN_CAN0_RX, FN_MSIOF1_RXD_B, FN_VI3_VSYNC_N, 5288 FN_VI1_G2, FN_VI1_G2_B, FN_VI2_R4, FN_IIC1_SDA, FN_INTC_EN1_N, 5289 FN_I2C1_SDA, 0, 0, 0, 0, 0, 0, 5290 /* IP5_5_3 [3] */ 5291 FN_EX_CS4_N, FN_MSIOF1_SCK_B, FN_VI3_HSYNC_N, 5292 FN_VI2_HSYNC_N, FN_IIC1_SCL, FN_VI2_HSYNC_N_B, 5293 FN_INTC_EN0_N, FN_I2C1_SCL, 5294 /* IP5_2_0 [3] */ 5295 FN_EX_CS3_N, FN_GPS_MAG, FN_VI3_FIELD, FN_VI1_G1, FN_VI1_G1_B, 5296 FN_VI2_R3, 0, 0, )) 5297 }, 5298 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32, 5299 GROUP(3, 3, 3, 3, 3, 3, 3, 2, 3, 3, 3), 5300 GROUP( 5301 /* IP6_31_29 [3] */ 5302 FN_ETH_REF_CLK, 0, FN_HCTS0_N_E, 5303 FN_STP_IVCXO27_1_B, FN_HRX0_F, 0, 0, 0, 5304 /* IP6_28_26 [3] */ 5305 FN_ETH_LINK, 0, FN_HTX0_E, 5306 FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E, 0, 0, 5307 /* IP6_25_23 [3] */ 5308 FN_ETH_RXD1, 0, FN_HRX0_E, FN_STP_ISSYNC_0_B, 5309 FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G, FN_RX1_E, 5310 /* IP6_22_20 [3] */ 5311 FN_ETH_RXD0, 0, FN_STP_ISEN_0_B, FN_TS_SDAT0_D, 5312 FN_GLO_I0_C, FN_SCIFB1_SCK_G, FN_SCK1_E, 0, 5313 /* IP6_19_17 [3] */ 5314 FN_ETH_RX_ER, 0, FN_STP_ISD_0_B, 5315 FN_TS_SPSYNC0_D, FN_GLO_Q1_C, FN_IIC2_SDA_E, FN_I2C2_SDA_E, 0, 5316 /* IP6_16_14 [3] */ 5317 FN_ETH_CRS_DV, 0, FN_STP_ISCLK_0_B, 5318 FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_IIC2_SCL_E, 5319 FN_I2C2_SCL_E, 0, 5320 /* IP6_13_11 [3] */ 5321 FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N, 5322 FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B, 0, 0, 5323 /* IP6_10_9 [2] */ 5324 FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B, FN_MSIOF0_TXD_B, 5325 /* IP6_8_6 [3] */ 5326 FN_DACK1, FN_IRQ1, FN_INTC_IRQ1_N, FN_SSI_WS6_B, 5327 FN_SSI_SDATA8_C, 0, 0, 0, 5328 /* IP6_5_3 [3] */ 5329 FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B, 5330 FN_SSI_SDATA7_C, FN_SSI_SCK78_B, 0, 0, 0, 5331 /* IP6_2_0 [3] */ 5332 FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B, 5333 FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, 0, )) 5334 }, 5335 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32, 5336 GROUP(1, 2, 2, 2, 3, 3, 3, 3, 3, 2, 2, 3, 3), 5337 GROUP( 5338 /* IP7_31 [1] */ 5339 0, 0, 5340 /* IP7_30_29 [2] */ 5341 FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2, 0, 5342 /* IP7_28_27 [2] */ 5343 FN_VI0_CLK, FN_ATACS00_N, FN_AVB_RXD1, 0, 5344 /* IP7_26_25 [2] */ 5345 FN_DU_DOTCLKIN1, FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, 0, 5346 /* IP7_24_22 [3] */ 5347 FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C, FN_PCMWE_N, FN_IECLK_C, 5348 0, 0, 0, 5349 /* IP7_21_19 [3] */ 5350 FN_PWM1, FN_SCIFA2_TXD_C, FN_STP_ISSYNC_1_B, FN_TS_SCK1_C, 5351 FN_GLO_RFON_C, FN_PCMOE_N, 0, 0, 5352 /* IP7_18_16 [3] */ 5353 FN_PWM0, FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C, 5354 FN_GLO_SS_C, 0, 0, 0, 5355 /* IP7_15_13 [3] */ 5356 FN_ETH_MDC, 0, FN_STP_ISD_1_B, 5357 FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, 0, 0, 0, 5358 /* IP7_12_10 [3] */ 5359 FN_ETH_TXD0, 0, FN_STP_ISCLK_1_B, FN_TS_SDEN1_C, 5360 FN_GLO_SCLK_C, 0, 0, 0, 5361 /* IP7_9_8 [2] */ 5362 FN_ETH_MAGIC, 0, FN_SIM0_RST_C, 0, 5363 /* IP7_7_6 [2] */ 5364 FN_ETH_TX_EN, 0, FN_SIM0_CLK_C, FN_HRTS0_N_F, 5365 /* IP7_5_3 [3] */ 5366 FN_ETH_TXD1, 0, FN_HTX0_F, FN_BPFCLK_G, 0, 0, 0, 0, 5367 /* IP7_2_0 [3] */ 5368 FN_ETH_MDIO, 0, FN_HRTS0_N_E, 5369 FN_SIM0_D_C, FN_HCTS0_N_F, 0, 0, 0, )) 5370 }, 5371 { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32, 5372 GROUP(1, 2, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 5373 2, 2, 2, 2, 2, 2), 5374 GROUP( 5375 /* IP8_31 [1] */ 5376 0, 0, 5377 /* IP8_30_29 [2] */ 5378 FN_SD0_CMD, FN_SCIFB1_SCK_B, FN_VI1_DATA1_VI1_B1_B, 0, 5379 /* IP8_28 [1] */ 5380 FN_SD0_CLK, FN_VI1_DATA0_VI1_B0_B, 5381 /* IP8_27 [1] */ 5382 FN_VI1_DATA6_VI1_B6, FN_AVB_GTXREFCLK, 5383 /* IP8_26 [1] */ 5384 FN_VI1_DATA5_VI1_B5, FN_AVB_PHY_INT, 5385 /* IP8_25_24 [2] */ 5386 FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D, 5387 FN_AVB_MAGIC, 0, 5388 /* IP8_23_22 [2] */ 5389 FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D, FN_AVB_GTX_CLK, 0, 5390 /* IP8_21_20 [2] */ 5391 FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO, 0, 5392 /* IP8_19_18 [2] */ 5393 FN_VI1_DATA1_VI1_B1, FN_SCIFA1_RXD_D, FN_AVB_MDC, 0, 5394 /* IP8_17_16 [2] */ 5395 FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D, FN_AVB_CRS, 0, 5396 /* IP8_15_14 [2] */ 5397 FN_VI1_CLK, FN_AVB_RX_DV, 0, 0, 5398 /* IP8_13_12 [2] */ 5399 FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK, 0, 0, 5400 /* IP8_11_10 [2] */ 5401 FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER, 0, 0, 5402 /* IP8_9_8 [2] */ 5403 FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1, FN_AVB_RXD7, 0, 5404 /* IP8_7_6 [2] */ 5405 FN_VI0_DATA4_VI0_B4, FN_ATAG0_N, FN_AVB_RXD6, 0, 5406 /* IP8_5_4 [2] */ 5407 FN_VI0_DATA3_VI0_B3, FN_ATADIR0_N, FN_AVB_RXD5, 0, 5408 /* IP8_3_2 [2] */ 5409 FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N, FN_AVB_RXD4, 0, 5410 /* IP8_1_0 [2] */ 5411 FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3, 0, )) 5412 }, 5413 { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32, 5414 GROUP(4, 2, 2, 2, 2, 2, 2, 4, 4, 2, 2, 2, 2), 5415 GROUP( 5416 /* IP9_31_28 [4] */ 5417 FN_SD1_CD, FN_MMC1_D6, FN_TS_SDEN1, FN_USB1_EXTP, 5418 FN_GLO_SS, FN_VI0_CLK_B, FN_IIC2_SCL_D, FN_I2C2_SCL_D, 5419 FN_SIM0_CLK_B, FN_VI3_CLK_B, 0, 0, 0, 0, 0, 0, 5420 /* IP9_27_26 [2] */ 5421 FN_SD1_DAT3, FN_AVB_RXD0, 0, FN_SCIFB0_RTS_N_B, 5422 /* IP9_25_24 [2] */ 5423 FN_SD1_DAT2, FN_AVB_COL, 0, FN_SCIFB0_CTS_N_B, 5424 /* IP9_23_22 [2] */ 5425 FN_SD1_DAT1, FN_AVB_LINK, 0, FN_SCIFB0_TXD_B, 5426 /* IP9_21_20 [2] */ 5427 FN_SD1_DAT0, FN_AVB_TX_CLK, 0, FN_SCIFB0_RXD_B, 5428 /* IP9_19_18 [2] */ 5429 FN_SD1_CMD, FN_AVB_TX_ER, 0, FN_SCIFB0_SCK_B, 5430 /* IP9_17_16 [2] */ 5431 FN_SD1_CLK, FN_AVB_TX_EN, 0, 0, 5432 /* IP9_15_12 [4] */ 5433 FN_SD0_WP, FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN, 5434 FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_IIC1_SDA_B, 5435 FN_I2C1_SDA_B, FN_VI2_DATA7_VI2_B7_B, 0, 0, 0, 0, 0, 0, 0, 5436 /* IP9_11_8 [4] */ 5437 FN_SD0_CD, FN_MMC0_D6, FN_TS_SDEN0_B, FN_USB0_EXTP, 5438 FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_IIC1_SCL_B, 5439 FN_I2C1_SCL_B, FN_VI2_DATA6_VI2_B6_B, 0, 0, 0, 0, 0, 0, 0, 5440 /* IP9_7_6 [2] */ 5441 FN_SD0_DAT3, FN_SCIFB1_RTS_N_B, FN_VI1_DATA5_VI1_B5_B, 0, 5442 /* IP9_5_4 [2] */ 5443 FN_SD0_DAT2, FN_SCIFB1_CTS_N_B, FN_VI1_DATA4_VI1_B4_B, 0, 5444 /* IP9_3_2 [2] */ 5445 FN_SD0_DAT1, FN_SCIFB1_TXD_B, FN_VI1_DATA3_VI1_B3_B, 0, 5446 /* IP9_1_0 [2] */ 5447 FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B, 0, )) 5448 }, 5449 { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32, 5450 GROUP(2, 4, 3, 4, 4, 4, 4, 3, 4), 5451 GROUP( 5452 /* IP10_31_30 [2] */ 5453 0, 0, 0, 0, 5454 /* IP10_29_26 [4] */ 5455 FN_SD2_CD, FN_MMC0_D4, FN_TS_SDAT0_B, FN_USB2_EXTP, FN_GLO_I0, 5456 FN_VI0_DATA6_VI0_B6_B, FN_HCTS0_N_D, FN_TS_SDAT1_B, 5457 FN_GLO_I0_B, FN_VI3_DATA6_B, 0, 0, 0, 0, 0, 0, 5458 /* IP10_25_23 [3] */ 5459 FN_SD2_DAT3, FN_MMC0_D3, FN_SIM0_RST, FN_VI0_DATA5_VI0_B5_B, 5460 FN_HTX0_D, FN_TS_SPSYNC1_B, FN_GLO_Q1_B, FN_VI3_DATA5_B, 5461 /* IP10_22_19 [4] */ 5462 FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B, 0, 5463 FN_VI0_DATA4_VI0_B4_B, FN_HRX0_D, FN_TS_SDEN1_B, 5464 FN_GLO_Q0_B, FN_VI3_DATA4_B, 0, 0, 0, 0, 0, 0, 0, 5465 /* IP10_18_15 [4] */ 5466 FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B, 0, 5467 FN_VI0_DATA3_VI0_B3_B, FN_SCIFB1_TXD_E, FN_TX1_D, 5468 FN_TS_SCK0_C, FN_GLO_RFON_B, FN_VI3_DATA3_B, 5469 0, 0, 0, 0, 0, 0, 5470 /* IP10_14_11 [4] */ 5471 FN_SD2_DAT0, FN_MMC0_D0, FN_FMCLK_B, 5472 FN_VI0_DATA2_VI0_B2_B, FN_SCIFB1_RXD_E, FN_RX1_D, 5473 FN_TS_SDAT0_C, FN_GLO_SS_B, FN_VI3_DATA2_B, 5474 0, 0, 0, 0, 0, 0, 0, 5475 /* IP10_10_7 [4] */ 5476 FN_SD2_CMD, FN_MMC0_CMD, FN_SIM0_D, 5477 FN_VI0_DATA1_VI0_B1_B, FN_SCIFB1_SCK_E, FN_SCK1_D, 5478 FN_TS_SPSYNC0_C, FN_GLO_SDATA_B, FN_VI3_DATA1_B, 5479 0, 0, 0, 0, 0, 0, 0, 5480 /* IP10_6_4 [3] */ 5481 FN_SD2_CLK, FN_MMC0_CLK, FN_SIM0_CLK, 5482 FN_VI0_DATA0_VI0_B0_B, FN_TS_SDEN0_C, FN_GLO_SCLK_B, 5483 FN_VI3_DATA0_B, 0, 5484 /* IP10_3_0 [4] */ 5485 FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN, 5486 FN_GLO_RFON, FN_VI1_CLK_B, FN_IIC2_SDA_D, FN_I2C2_SDA_D, 5487 FN_SIM0_D_B, 0, 0, 0, 0, 0, 0, 0, )) 5488 }, 5489 { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32, 5490 GROUP(2, 3, 3, 2, 4, 3, 2, 2, 2, 2, 2, 1, 4), 5491 GROUP( 5492 /* IP11_31_30 [2] */ 5493 FN_SSI_SCK0129, FN_CAN_CLK_B, FN_MOUT0, 0, 5494 /* IP11_29_27 [3] */ 5495 FN_MLB_DAT, 0, FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C, 5496 0, 0, 0, 5497 /* IP11_26_24 [3] */ 5498 FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_IIC2_SDA_B, FN_I2C2_SDA_B, 5499 0, 0, 0, 5500 /* IP11_23_22 [2] */ 5501 FN_MLB_CLK, FN_IIC2_SCL_B, FN_I2C2_SCL_B, 0, 5502 /* IP11_21_18 [4] */ 5503 FN_SD3_WP, FN_MMC1_D5, FN_TS_SCK1, FN_GLO_Q1, FN_FMIN_C, 5504 0, FN_FMIN_E, 0, FN_FMIN_F, 0, 0, 0, 0, 0, 0, 0, 5505 /* IP11_17_15 [3] */ 5506 FN_SD3_CD, FN_MMC1_D4, FN_TS_SDAT1, 5507 FN_VSP, FN_GLO_Q0, FN_SIM0_RST_B, 0, 0, 5508 /* IP11_14_13 [2] */ 5509 FN_SD3_DAT3, FN_MMC1_D3, FN_SCKZ, 0, 5510 /* IP11_12_11 [2] */ 5511 FN_SD3_DAT2, FN_MMC1_D2, FN_SDATA, 0, 5512 /* IP11_10_9 [2] */ 5513 FN_SD3_DAT1, FN_MMC1_D1, FN_MDATA, 0, 5514 /* IP11_8_7 [2] */ 5515 FN_SD3_DAT0, FN_MMC1_D0, FN_STM_N, 0, 5516 /* IP11_6_5 [2] */ 5517 FN_SD3_CMD, FN_MMC1_CMD, FN_MTS_N, 0, 5518 /* IP11_4 [1] */ 5519 FN_SD3_CLK, FN_MMC1_CLK, 5520 /* IP11_3_0 [4] */ 5521 FN_SD2_WP, FN_MMC0_D5, FN_TS_SCK0_B, FN_USB2_IDIN, 5522 FN_GLO_I1, FN_VI0_DATA7_VI0_B7_B, FN_HRTS0_N_D, 5523 FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B, 0, 0, 0, 0, 0, 0, )) 5524 }, 5525 { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32, 5526 GROUP(1, 3, 3, 2, 3, 3, 3, 3, 3, 2, 2, 2, 2), 5527 GROUP( 5528 /* IP12_31 [1] */ 5529 0, 0, 5530 /* IP12_30_28 [3] */ 5531 FN_SSI_WS5, FN_SCIFB1_RXD, FN_IECLK_B, 5532 FN_DU2_EXVSYNC_DU2_VSYNC, FN_QSTB_QHE, 5533 FN_CAN_DEBUGOUT4, 0, 0, 5534 /* IP12_27_25 [3] */ 5535 FN_SSI_SCK5, FN_SCIFB1_SCK, 5536 FN_IERX_B, FN_DU2_EXHSYNC_DU2_HSYNC, FN_QSTH_QHS, 5537 FN_CAN_DEBUGOUT3, 0, 0, 5538 /* IP12_24_23 [2] */ 5539 FN_SSI_SDATA4, FN_STP_ISSYNC_0, FN_MSIOF1_RXD, 5540 FN_CAN_DEBUGOUT2, 5541 /* IP12_22_20 [3] */ 5542 FN_SSI_WS4, FN_STP_ISEN_0, FN_SCIFB0_RTS_N, 5543 FN_MSIOF1_TXD, FN_SSI_WS5_C, FN_CAN_DEBUGOUT1, 0, 0, 5544 /* IP12_19_17 [3] */ 5545 FN_SSI_SCK4, FN_STP_ISD_0, FN_SCIFB0_CTS_N, 5546 FN_MSIOF1_SS2, FN_SSI_SCK5_C, FN_CAN_DEBUGOUT0, 0, 0, 5547 /* IP12_16_14 [3] */ 5548 FN_SSI_SDATA3, FN_STP_ISCLK_0, 5549 FN_SCIFB0_TXD, FN_MSIOF1_SS1, FN_CAN_TXCLK, 0, 0, 0, 5550 /* IP12_13_11 [3] */ 5551 FN_SSI_WS34, FN_STP_IVCXO27_0, FN_SCIFB0_RXD, FN_MSIOF1_SYNC, 5552 FN_CAN_STEP0, 0, 0, 0, 5553 /* IP12_10_8 [3] */ 5554 FN_SSI_SCK34, FN_STP_OPWM_0, FN_SCIFB0_SCK, 5555 FN_MSIOF1_SCK, FN_CAN_DEBUG_HW_TRIGGER, 0, 0, 0, 5556 /* IP12_7_6 [2] */ 5557 FN_SSI_SDATA2, FN_CAN1_RX_B, FN_SSI_SCK1, FN_MOUT6, 5558 /* IP12_5_4 [2] */ 5559 FN_SSI_SDATA1, FN_CAN1_TX_B, FN_MOUT5, 0, 5560 /* IP12_3_2 [2] */ 5561 FN_SSI_SDATA0, FN_CAN0_RX_B, FN_MOUT2, 0, 5562 /* IP12_1_0 [2] */ 5563 FN_SSI_WS0129, FN_CAN0_TX_B, FN_MOUT1, 0, )) 5564 }, 5565 { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32, 5566 GROUP(1, 2, 3, 3, 4, 3, 3, 3, 3, 4, 3), 5567 GROUP( 5568 /* IP13_31 [1] */ 5569 0, 0, 5570 /* IP13_30_29 [2] */ 5571 FN_AUDIO_CLKA, FN_SCIFB2_RTS_N, FN_CAN_DEBUGOUT14, 0, 5572 /* IP13_28_26 [3] */ 5573 FN_SSI_SDATA9, FN_STP_ISSYNC_1, FN_SCIFB2_CTS_N, FN_SSI_WS1, 5574 FN_SSI_SDATA5_C, FN_CAN_DEBUGOUT13, 0, 0, 5575 /* IP13_25_23 [3] */ 5576 FN_SSI_SDATA8, FN_STP_ISEN_1, FN_SCIFB2_TXD, FN_CAN0_TX_C, 5577 FN_CAN_DEBUGOUT12, FN_SSI_SDATA8_B, 0, 0, 5578 /* IP13_22_19 [4] */ 5579 FN_SSI_SDATA7, FN_STP_ISD_1, FN_SCIFB2_RXD, FN_SCIFA2_RTS_N, 5580 FN_TCLK2, FN_QSTVA_QVS, FN_CAN_DEBUGOUT11, FN_BPFCLK_E, 5581 0, FN_SSI_SDATA7_B, FN_FMIN_G, 0, 0, 0, 0, 0, 5582 /* IP13_18_16 [3] */ 5583 FN_SSI_WS78, FN_STP_ISCLK_1, FN_SCIFB2_SCK, FN_SCIFA2_CTS_N, 5584 FN_DU2_DR7, FN_LCDOUT7, FN_CAN_DEBUGOUT10, 0, 5585 /* IP13_15_13 [3] */ 5586 FN_SSI_SCK78, FN_STP_IVCXO27_1, FN_SCK1, FN_SCIFA1_SCK, 5587 FN_DU2_DR6, FN_LCDOUT6, FN_CAN_DEBUGOUT9, 0, 5588 /* IP13_12_10 [3] */ 5589 FN_SSI_SDATA6, FN_FMIN_D, 0, FN_DU2_DR5, FN_LCDOUT5, 5590 FN_CAN_DEBUGOUT8, 0, 0, 5591 /* IP13_9_7 [3] */ 5592 FN_SSI_WS6, FN_SCIFB1_RTS_N, FN_CAN0_TX_D, FN_DU2_DR4, 5593 FN_LCDOUT4, FN_CAN_DEBUGOUT7, 0, 0, 5594 /* IP13_6_3 [4] */ 5595 FN_SSI_SCK6, FN_SCIFB1_CTS_N, FN_BPFCLK_D, 0, 5596 FN_DU2_DR3, FN_LCDOUT3, FN_CAN_DEBUGOUT6, 5597 FN_BPFCLK_F, 0, 0, 0, 0, 0, 0, 0, 0, 5598 /* IP13_2_0 [3] */ 5599 FN_SSI_SDATA5, FN_SCIFB1_TXD, FN_IETX_B, FN_DU2_DR2, 5600 FN_LCDOUT2, FN_CAN_DEBUGOUT5, 0, 0, )) 5601 }, 5602 { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32, 5603 GROUP(1, 3, 3, 3, 3, 3, 4, 3, 3, 3, 3), 5604 GROUP( 5605 /* IP14_30 [1] */ 5606 0, 0, 5607 /* IP14_30_28 [3] */ 5608 FN_SCIFA1_RTS_N, FN_AD_NCS_N, FN_RTS1_N, 5609 FN_MSIOF3_TXD, FN_DU1_DOTCLKOUT, FN_QSTVB_QVE, 5610 FN_HRTS0_N_C, 0, 5611 /* IP14_27_25 [3] */ 5612 FN_SCIFA1_CTS_N, FN_AD_CLK, FN_CTS1_N, FN_MSIOF3_RXD, 5613 FN_DU0_DOTCLKOUT, FN_QCLK, 0, 0, 5614 /* IP14_24_22 [3] */ 5615 FN_SCIFA1_TXD, FN_AD_DO, FN_TX1, FN_DU2_DG1, 5616 FN_LCDOUT9, 0, 0, 0, 5617 /* IP14_21_19 [3] */ 5618 FN_SCIFA1_RXD, FN_AD_DI, FN_RX1, 5619 FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, FN_QCPV_QDE, 0, 0, 0, 5620 /* IP14_18_16 [3] */ 5621 FN_SCIFA0_RTS_N, FN_HRTS1_N, FN_RTS0_N, 5622 FN_MSIOF3_SS1, FN_DU2_DG0, FN_LCDOUT8, FN_PWM1_B, 0, 5623 /* IP14_15_12 [4] */ 5624 FN_SCIFA0_CTS_N, FN_HCTS1_N, FN_CTS0_N, FN_MSIOF3_SYNC, 5625 FN_DU2_DG3, FN_LCDOUT11, FN_PWM0_B, FN_IIC1_SCL_C, FN_I2C1_SCL_C, 5626 0, 0, 0, 0, 0, 0, 0, 5627 /* IP14_11_9 [3] */ 5628 FN_SCIFA0_TXD, FN_HTX1, FN_TX0, FN_DU2_DR1, FN_LCDOUT1, 5629 0, 0, 0, 5630 /* IP14_8_6 [3] */ 5631 FN_SCIFA0_RXD, FN_HRX1, FN_RX0, FN_DU2_DR0, FN_LCDOUT0, 5632 0, 0, 0, 5633 /* IP14_5_3 [3] */ 5634 FN_SCIFA0_SCK, FN_HSCK1, FN_SCK0, FN_MSIOF3_SS2, FN_DU2_DG2, 5635 FN_LCDOUT10, FN_IIC1_SDA_C, FN_I2C1_SDA_C, 5636 /* IP14_2_0 [3] */ 5637 FN_AUDIO_CLKB, FN_SCIF_CLK, FN_CAN0_RX_D, 5638 FN_DVC_MUTE, FN_CAN0_RX_C, FN_CAN_DEBUGOUT15, 5639 FN_REMOCON, 0, )) 5640 }, 5641 { PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32, 5642 GROUP(2, 2, 2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3), 5643 GROUP( 5644 /* IP15_31_30 [2] */ 5645 0, 0, 0, 0, 5646 /* IP15_29_28 [2] */ 5647 FN_MSIOF0_TXD, FN_ADICHS1, FN_DU2_DG6, FN_LCDOUT14, 5648 /* IP15_27_26 [2] */ 5649 FN_MSIOF0_SS1, FN_ADICHS0, FN_DU2_DG5, FN_LCDOUT13, 5650 /* IP15_25_23 [3] */ 5651 FN_MSIOF0_SYNC, FN_TS_SCK0, FN_SSI_SCK2, FN_ADIDATA, 5652 FN_DU2_DB7, FN_LCDOUT23, FN_HRX0_C, 0, 5653 /* IP15_22_20 [3] */ 5654 FN_MSIOF0_SCK, FN_TS_SDAT0, FN_ADICLK, 5655 FN_DU2_DB6, FN_LCDOUT22, 0, 0, 0, 5656 /* IP15_19_18 [2] */ 5657 FN_HRTS0_N, FN_SSI_WS9, FN_DU2_DB5, FN_LCDOUT21, 5658 /* IP15_17_16 [2] */ 5659 FN_HCTS0_N, FN_SSI_SCK9, FN_DU2_DB4, FN_LCDOUT20, 5660 /* IP15_15_14 [2] */ 5661 FN_HTX0, FN_DU2_DB3, FN_LCDOUT19, 0, 5662 /* IP15_13_12 [2] */ 5663 FN_HRX0, FN_DU2_DB2, FN_LCDOUT18, 0, 5664 /* IP15_11_9 [3] */ 5665 FN_HSCK0, FN_TS_SDEN0, FN_DU2_DG4, FN_LCDOUT12, FN_HCTS0_N_C, 5666 0, 0, 0, 5667 /* IP15_8_6 [3] */ 5668 FN_SCIFA2_TXD, FN_BPFCLK, FN_RX2, FN_DU2_DB1, FN_LCDOUT17, 5669 FN_IIC2_SDA, FN_I2C2_SDA, 0, 5670 /* IP15_5_3 [3] */ 5671 FN_SCIFA2_RXD, FN_FMIN, FN_TX2, FN_DU2_DB0, FN_LCDOUT16, 5672 FN_IIC2_SCL, FN_I2C2_SCL, 0, 5673 /* IP15_2_0 [3] */ 5674 FN_SCIFA2_SCK, FN_FMCLK, FN_SCK2, FN_MSIOF3_SCK, FN_DU2_DG7, 5675 FN_LCDOUT15, FN_SCIF_CLK_B, 0, )) 5676 }, 5677 { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32, 5678 GROUP(4, 4, 4, 4, 4, 4, 1, 1, 3, 3), 5679 GROUP( 5680 /* IP16_31_28 [4] */ 5681 0, 0, 0, 0, 0, 0, 0, 0, 5682 0, 0, 0, 0, 0, 0, 0, 0, 5683 /* IP16_27_24 [4] */ 5684 0, 0, 0, 0, 0, 0, 0, 0, 5685 0, 0, 0, 0, 0, 0, 0, 0, 5686 /* IP16_23_20 [4] */ 5687 0, 0, 0, 0, 0, 0, 0, 0, 5688 0, 0, 0, 0, 0, 0, 0, 0, 5689 /* IP16_19_16 [4] */ 5690 0, 0, 0, 0, 0, 0, 0, 0, 5691 0, 0, 0, 0, 0, 0, 0, 0, 5692 /* IP16_15_12 [4] */ 5693 0, 0, 0, 0, 0, 0, 0, 0, 5694 0, 0, 0, 0, 0, 0, 0, 0, 5695 /* IP16_11_8 [4] */ 5696 0, 0, 0, 0, 0, 0, 0, 0, 5697 0, 0, 0, 0, 0, 0, 0, 0, 5698 /* IP16_7 [1] */ 5699 FN_USB1_OVC, FN_TCLK1_B, 5700 /* IP16_6 [1] */ 5701 FN_USB1_PWEN, FN_AUDIO_CLKOUT_D, 5702 /* IP16_5_3 [3] */ 5703 FN_MSIOF0_RXD, FN_TS_SPSYNC0, FN_SSI_WS2, 5704 FN_ADICS_SAMP, FN_DU2_CDE, FN_QPOLB, FN_SCIFA2_RXD_B, 0, 5705 /* IP16_2_0 [3] */ 5706 FN_MSIOF0_SS2, FN_AUDIO_CLKOUT, FN_ADICHS2, 5707 FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B, 0, )) 5708 }, 5709 { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32, 5710 GROUP(3, 2, 2, 3, 2, 1, 1, 1, 2, 1, 2, 1, 5711 1, 1, 1, 2, 1, 1, 2, 1, 1), 5712 GROUP( 5713 /* SEL_SCIF1 [3] */ 5714 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3, 5715 FN_SEL_SCIF1_4, 0, 0, 0, 5716 /* SEL_SCIFB [2] */ 5717 FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, 0, 5718 /* SEL_SCIFB2 [2] */ 5719 FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, 0, 5720 /* SEL_SCIFB1 [3] */ 5721 FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, 5722 FN_SEL_SCIFB1_3, FN_SEL_SCIFB1_4, FN_SEL_SCIFB1_5, 5723 FN_SEL_SCIFB1_6, 0, 5724 /* SEL_SCIFA1 [2] */ 5725 FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, 5726 FN_SEL_SCIFA1_3, 5727 /* SEL_SCIF0 [1] */ 5728 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, 5729 /* SEL_SCIFA [1] */ 5730 FN_SEL_SCFA_0, FN_SEL_SCFA_1, 5731 /* SEL_SOF1 [1] */ 5732 FN_SEL_SOF1_0, FN_SEL_SOF1_1, 5733 /* SEL_SSI7 [2] */ 5734 FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2, 0, 5735 /* SEL_SSI6 [1] */ 5736 FN_SEL_SSI6_0, FN_SEL_SSI6_1, 5737 /* SEL_SSI5 [2] */ 5738 FN_SEL_SSI5_0, FN_SEL_SSI5_1, FN_SEL_SSI5_2, 0, 5739 /* SEL_VI3 [1] */ 5740 FN_SEL_VI3_0, FN_SEL_VI3_1, 5741 /* SEL_VI2 [1] */ 5742 FN_SEL_VI2_0, FN_SEL_VI2_1, 5743 /* SEL_VI1 [1] */ 5744 FN_SEL_VI1_0, FN_SEL_VI1_1, 5745 /* SEL_VI0 [1] */ 5746 FN_SEL_VI0_0, FN_SEL_VI0_1, 5747 /* SEL_TSIF1 [2] */ 5748 FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2, 0, 5749 /* RESERVED [1] */ 5750 0, 0, 5751 /* SEL_LBS [1] */ 5752 FN_SEL_LBS_0, FN_SEL_LBS_1, 5753 /* SEL_TSIF0 [2] */ 5754 FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, 5755 /* SEL_SOF3 [1] */ 5756 FN_SEL_SOF3_0, FN_SEL_SOF3_1, 5757 /* SEL_SOF0 [1] */ 5758 FN_SEL_SOF0_0, FN_SEL_SOF0_1, )) 5759 }, 5760 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32, 5761 GROUP(3, 1, 1, 1, 2, 1, 2, 1, 2, 1, 1, 1, 5762 3, 3, 2, 3, 2, 2), 5763 GROUP( 5764 /* RESERVED [3] */ 5765 0, 0, 0, 0, 0, 0, 0, 0, 5766 /* SEL_TMU1 [1] */ 5767 FN_SEL_TMU1_0, FN_SEL_TMU1_1, 5768 /* SEL_HSCIF1 [1] */ 5769 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, 5770 /* SEL_SCIFCLK [1] */ 5771 FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1, 5772 /* SEL_CAN0 [2] */ 5773 FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3, 5774 /* SEL_CANCLK [1] */ 5775 FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, 5776 /* SEL_SCIFA2 [2] */ 5777 FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2, 0, 5778 /* SEL_CAN1 [1] */ 5779 FN_SEL_CAN1_0, FN_SEL_CAN1_1, 5780 /* RESERVED [2] */ 5781 0, 0, 0, 0, 5782 /* SEL_SCIF2 [1] */ 5783 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, 5784 /* SEL_ADI [1] */ 5785 FN_SEL_ADI_0, FN_SEL_ADI_1, 5786 /* SEL_SSP [1] */ 5787 FN_SEL_SSP_0, FN_SEL_SSP_1, 5788 /* SEL_FM [3] */ 5789 FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3, 5790 FN_SEL_FM_4, FN_SEL_FM_5, FN_SEL_FM_6, 0, 5791 /* SEL_HSCIF0 [3] */ 5792 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, 5793 FN_SEL_HSCIF0_3, FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5, 0, 0, 5794 /* SEL_GPS [2] */ 5795 FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, 0, 5796 /* RESERVED [3] */ 5797 0, 0, 0, 0, 0, 0, 0, 0, 5798 /* SEL_SIM [2] */ 5799 FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2, 0, 5800 /* SEL_SSI8 [2] */ 5801 FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2, 0, )) 5802 }, 5803 { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32, 5804 GROUP(1, 1, 2, 4, 4, 2, 2, 4, 2, 3, 2, 3, 2), 5805 GROUP( 5806 /* SEL_IICDVFS [1] */ 5807 FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1, 5808 /* SEL_IIC0 [1] */ 5809 FN_SEL_IIC0_0, FN_SEL_IIC0_1, 5810 /* RESERVED [2] */ 5811 0, 0, 0, 0, 5812 /* RESERVED [4] */ 5813 0, 0, 0, 0, 0, 0, 0, 0, 5814 0, 0, 0, 0, 0, 0, 0, 0, 5815 /* RESERVED [4] */ 5816 0, 0, 0, 0, 0, 0, 0, 0, 5817 0, 0, 0, 0, 0, 0, 0, 0, 5818 /* RESERVED [2] */ 5819 0, 0, 0, 0, 5820 /* SEL_IEB [2] */ 5821 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0, 5822 /* RESERVED [4] */ 5823 0, 0, 0, 0, 0, 0, 0, 0, 5824 0, 0, 0, 0, 0, 0, 0, 0, 5825 /* RESERVED [2] */ 5826 0, 0, 0, 0, 5827 /* SEL_IIC2 [3] */ 5828 FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3, 5829 FN_SEL_IIC2_4, 0, 0, 0, 5830 /* SEL_IIC1 [2] */ 5831 FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, 0, 5832 /* SEL_I2C2 [3] */ 5833 FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3, 5834 FN_SEL_I2C2_4, 0, 0, 0, 5835 /* SEL_I2C1 [2] */ 5836 FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, 0, )) 5837 }, 5838 { }, 5839 }; 5840 5841 static int r8a7790_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl) 5842 { 5843 if (pin < RCAR_GP_PIN(3, 0) || pin > RCAR_GP_PIN(3, 31)) 5844 return -EINVAL; 5845 5846 *pocctrl = 0xe606008c; 5847 5848 return 31 - (pin & 0x1f); 5849 } 5850 5851 static const struct soc_device_attribute r8a7790_tdsel[] = { 5852 { .soc_id = "r8a7790", .revision = "ES1.0" }, 5853 { /* sentinel */ } 5854 }; 5855 5856 static int r8a7790_pinmux_soc_init(struct sh_pfc *pfc) 5857 { 5858 /* Initialize TDSEL on old revisions */ 5859 if (soc_device_match(r8a7790_tdsel)) 5860 sh_pfc_write(pfc, 0xe6060088, 0x00155554); 5861 5862 return 0; 5863 } 5864 5865 static const struct sh_pfc_soc_operations r8a7790_pinmux_ops = { 5866 .init = r8a7790_pinmux_soc_init, 5867 .pin_to_pocctrl = r8a7790_pin_to_pocctrl, 5868 }; 5869 5870 #ifdef CONFIG_PINCTRL_PFC_R8A7742 5871 const struct sh_pfc_soc_info r8a7742_pinmux_info = { 5872 .name = "r8a77420_pfc", 5873 .ops = &r8a7790_pinmux_ops, 5874 .unlock_reg = 0xe6060000, /* PMMR */ 5875 5876 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 5877 5878 .pins = pinmux_pins, 5879 .nr_pins = ARRAY_SIZE(pinmux_pins), 5880 .groups = pinmux_groups.common, 5881 .nr_groups = ARRAY_SIZE(pinmux_groups.common), 5882 .functions = pinmux_functions.common, 5883 .nr_functions = ARRAY_SIZE(pinmux_functions.common), 5884 5885 .cfg_regs = pinmux_config_regs, 5886 5887 .pinmux_data = pinmux_data, 5888 .pinmux_data_size = ARRAY_SIZE(pinmux_data), 5889 }; 5890 #endif 5891 5892 #ifdef CONFIG_PINCTRL_PFC_R8A7790 5893 const struct sh_pfc_soc_info r8a7790_pinmux_info = { 5894 .name = "r8a77900_pfc", 5895 .ops = &r8a7790_pinmux_ops, 5896 .unlock_reg = 0xe6060000, /* PMMR */ 5897 5898 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 5899 5900 .pins = pinmux_pins, 5901 .nr_pins = ARRAY_SIZE(pinmux_pins), 5902 .groups = pinmux_groups.common, 5903 .nr_groups = ARRAY_SIZE(pinmux_groups.common) + 5904 ARRAY_SIZE(pinmux_groups.automotive), 5905 .functions = pinmux_functions.common, 5906 .nr_functions = ARRAY_SIZE(pinmux_functions.common) + 5907 ARRAY_SIZE(pinmux_functions.automotive), 5908 5909 .cfg_regs = pinmux_config_regs, 5910 5911 .pinmux_data = pinmux_data, 5912 .pinmux_data_size = ARRAY_SIZE(pinmux_data), 5913 }; 5914 #endif 5915