1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * R8A7790 processor support 4 * 5 * Copyright (C) 2013 Renesas Electronics Corporation 6 * Copyright (C) 2013 Magnus Damm 7 * Copyright (C) 2012 Renesas Solutions Corp. 8 * Copyright (C) 2012 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> 9 */ 10 11 #include <linux/errno.h> 12 #include <linux/io.h> 13 #include <linux/kernel.h> 14 #include <linux/sys_soc.h> 15 16 #include "core.h" 17 #include "sh_pfc.h" 18 19 /* 20 * All pins assigned to GPIO bank 3 can be used for SD interfaces in 21 * which case they support both 3.3V and 1.8V signalling. 22 */ 23 #define CPU_ALL_GP(fn, sfx) \ 24 PORT_GP_CFG_32(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ 25 PORT_GP_CFG_30(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ 26 PORT_GP_CFG_30(2, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ 27 PORT_GP_CFG_32(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ 28 PORT_GP_CFG_32(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ 29 PORT_GP_CFG_32(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP) 30 31 #define CPU_ALL_NOGP(fn) \ 32 PIN_NOGP_CFG(ASEBRK_N_ACK, "ASEBRK#/ACK", fn, SH_PFC_PIN_CFG_PULL_DOWN), \ 33 PIN_NOGP(IIC0_SDA, "AF15", fn), \ 34 PIN_NOGP(IIC0_SCL, "AG15", fn), \ 35 PIN_NOGP(IIC3_SDA, "AH15", fn), \ 36 PIN_NOGP(IIC3_SCL, "AJ15", fn), \ 37 PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP), \ 38 PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP), \ 39 PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP), \ 40 PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP) 41 42 enum { 43 PINMUX_RESERVED = 0, 44 45 PINMUX_DATA_BEGIN, 46 GP_ALL(DATA), 47 PINMUX_DATA_END, 48 49 PINMUX_FUNCTION_BEGIN, 50 GP_ALL(FN), 51 52 /* GPSR0 */ 53 FN_IP0_2_0, FN_IP0_5_3, FN_IP0_8_6, FN_IP0_11_9, FN_IP0_15_12, 54 FN_IP0_19_16, FN_IP0_22_20, FN_IP0_26_23, FN_IP0_30_27, 55 FN_IP1_3_0, FN_IP1_7_4, FN_IP1_11_8, FN_IP1_14_12, 56 FN_IP1_17_15, FN_IP1_21_18, FN_IP1_25_22, FN_IP1_27_26, 57 FN_IP1_29_28, FN_IP2_2_0, FN_IP2_5_3, FN_IP2_8_6, FN_IP2_11_9, 58 FN_IP2_14_12, FN_IP2_17_15, FN_IP2_21_18, FN_IP2_25_22, 59 FN_IP2_28_26, FN_IP3_3_0, FN_IP3_7_4, FN_IP3_11_8, 60 FN_IP3_14_12, FN_IP3_17_15, 61 62 /* GPSR1 */ 63 FN_IP3_19_18, FN_IP3_22_20, FN_IP3_25_23, FN_IP3_28_26, 64 FN_IP3_31_29, FN_IP4_2_0, FN_IP4_5_3, FN_IP4_8_6, FN_IP4_11_9, 65 FN_IP4_14_12, FN_IP4_17_15, FN_IP4_20_18, FN_IP4_23_21, 66 FN_IP4_26_24, FN_IP4_29_27, FN_IP5_2_0, FN_IP5_5_3, FN_IP5_9_6, 67 FN_IP5_12_10, FN_IP5_14_13, FN_IP5_17_15, FN_IP5_20_18, 68 FN_IP5_23_21, FN_IP5_26_24, FN_IP5_29_27, FN_IP6_2_0, 69 FN_IP6_5_3, FN_IP6_8_6, FN_IP6_10_9, FN_IP6_13_11, 70 71 /* GPSR2 */ 72 FN_IP7_28_27, FN_IP7_30_29, FN_IP8_1_0, FN_IP8_3_2, FN_IP8_5_4, 73 FN_IP8_7_6, FN_IP8_9_8, FN_IP8_11_10, FN_IP8_13_12, FN_IP8_15_14, 74 FN_IP8_17_16, FN_IP8_19_18, FN_IP8_21_20, FN_IP8_23_22, 75 FN_IP8_25_24, FN_IP8_26, FN_IP8_27, FN_VI1_DATA7_VI1_B7, 76 FN_IP6_16_14, FN_IP6_19_17, FN_IP6_22_20, FN_IP6_25_23, 77 FN_IP6_28_26, FN_IP6_31_29, FN_IP7_2_0, FN_IP7_5_3, FN_IP7_7_6, 78 FN_IP7_9_8, FN_IP7_12_10, FN_IP7_15_13, 79 80 /* GPSR3 */ 81 FN_IP8_28, FN_IP8_30_29, FN_IP9_1_0, FN_IP9_3_2, FN_IP9_5_4, 82 FN_IP9_7_6, FN_IP9_11_8, FN_IP9_15_12, FN_IP9_17_16, FN_IP9_19_18, 83 FN_IP9_21_20, FN_IP9_23_22, FN_IP9_25_24, FN_IP9_27_26, 84 FN_IP9_31_28, FN_IP10_3_0, FN_IP10_6_4, FN_IP10_10_7, FN_IP10_14_11, 85 FN_IP10_18_15, FN_IP10_22_19, FN_IP10_25_23, FN_IP10_29_26, 86 FN_IP11_3_0, FN_IP11_4, FN_IP11_6_5, FN_IP11_8_7, FN_IP11_10_9, 87 FN_IP11_12_11, FN_IP11_14_13, FN_IP11_17_15, FN_IP11_21_18, 88 89 /* GPSR4 */ 90 FN_IP11_23_22, FN_IP11_26_24, FN_IP11_29_27, FN_IP11_31_30, 91 FN_IP12_1_0, FN_IP12_3_2, FN_IP12_5_4, FN_IP12_7_6, FN_IP12_10_8, 92 FN_IP12_13_11, FN_IP12_16_14, FN_IP12_19_17, FN_IP12_22_20, 93 FN_IP12_24_23, FN_IP12_27_25, FN_IP12_30_28, FN_IP13_2_0, 94 FN_IP13_6_3, FN_IP13_9_7, FN_IP13_12_10, FN_IP13_15_13, 95 FN_IP13_18_16, FN_IP13_22_19, FN_IP13_25_23, FN_IP13_28_26, 96 FN_IP13_30_29, FN_IP14_2_0, FN_IP14_5_3, FN_IP14_8_6, FN_IP14_11_9, 97 FN_IP14_15_12, FN_IP14_18_16, 98 99 /* GPSR5 */ 100 FN_IP14_21_19, FN_IP14_24_22, FN_IP14_27_25, FN_IP14_30_28, 101 FN_IP15_2_0, FN_IP15_5_3, FN_IP15_8_6, FN_IP15_11_9, FN_IP15_13_12, 102 FN_IP15_15_14, FN_IP15_17_16, FN_IP15_19_18, FN_IP15_22_20, 103 FN_IP15_25_23, FN_IP15_27_26, FN_IP15_29_28, FN_IP16_2_0, 104 FN_IP16_5_3, FN_USB0_PWEN, FN_USB0_OVC_VBUS, FN_IP16_6, FN_IP16_7, 105 FN_USB2_PWEN, FN_USB2_OVC, FN_AVS1, FN_AVS2, FN_DU_DOTCLKIN0, 106 FN_IP7_26_25, FN_DU_DOTCLKIN2, FN_IP7_18_16, FN_IP7_21_19, FN_IP7_24_22, 107 108 /* IPSR0 */ 109 FN_D0, FN_MSIOF3_SCK_B, FN_VI3_DATA0, FN_VI0_G4, FN_VI0_G4_B, 110 FN_D1, FN_MSIOF3_SYNC_B, FN_VI3_DATA1, FN_VI0_G5, 111 FN_VI0_G5_B, FN_D2, FN_MSIOF3_RXD_B, FN_VI3_DATA2, 112 FN_VI0_G6, FN_VI0_G6_B, FN_D3, FN_MSIOF3_TXD_B, 113 FN_VI3_DATA3, FN_VI0_G7, FN_VI0_G7_B, FN_D4, 114 FN_SCIFB1_RXD_F, FN_SCIFB0_RXD_C, FN_VI3_DATA4, 115 FN_VI0_R0, FN_VI0_R0_B, FN_RX0_B, FN_D5, 116 FN_SCIFB1_TXD_F, FN_SCIFB0_TXD_C, FN_VI3_DATA5, 117 FN_VI0_R1, FN_VI0_R1_B, FN_TX0_B, FN_D6, 118 FN_IIC2_SCL_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B, 119 FN_I2C2_SCL_C, FN_D7, FN_AD_DI_B, FN_IIC2_SDA_C, 120 FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_I2C2_SDA_C, FN_TCLK1, 121 FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0, 122 FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0, 123 124 /* IPSR1 */ 125 FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1, 126 FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1, FN_D10, 127 FN_SCIFA1_TXD_C, FN_AVB_TXD2, 128 FN_VI0_G2, FN_VI0_G2_B, FN_VI2_DATA2_VI2_B2, FN_D11, 129 FN_SCIFA1_CTS_N_C, FN_AVB_TXD3, 130 FN_VI0_G3, FN_VI0_G3_B, FN_VI2_DATA3_VI2_B3, 131 FN_D12, FN_SCIFA1_RTS_N_C, FN_AVB_TXD4, 132 FN_VI0_HSYNC_N, FN_VI0_HSYNC_N_B, FN_VI2_DATA4_VI2_B4, 133 FN_D13, FN_AVB_TXD5, FN_VI0_VSYNC_N, 134 FN_VI0_VSYNC_N_B, FN_VI2_DATA5_VI2_B5, FN_D14, 135 FN_SCIFB1_RXD_C, FN_AVB_TXD6, FN_RX1_B, 136 FN_VI0_CLKENB, FN_VI0_CLKENB_B, FN_VI2_DATA6_VI2_B6, 137 FN_D15, FN_SCIFB1_TXD_C, FN_AVB_TXD7, FN_TX1_B, 138 FN_VI0_FIELD, FN_VI0_FIELD_B, FN_VI2_DATA7_VI2_B7, 139 FN_A0, FN_PWM3, FN_A1, FN_PWM4, 140 141 /* IPSR2 */ 142 FN_A2, FN_PWM5, FN_MSIOF1_SS1_B, FN_A3, 143 FN_PWM6, FN_MSIOF1_SS2_B, FN_A4, FN_MSIOF1_TXD_B, 144 FN_TPU0TO0, FN_A5, FN_SCIFA1_TXD_B, FN_TPU0TO1, 145 FN_A6, FN_SCIFA1_RTS_N_B, FN_TPU0TO2, FN_A7, 146 FN_SCIFA1_SCK_B, FN_AUDIO_CLKOUT_B, FN_TPU0TO3, 147 FN_A8, FN_SCIFA1_RXD_B, FN_SSI_SCK5_B, FN_VI0_R4, 148 FN_VI0_R4_B, FN_SCIFB2_RXD_C, FN_RX2_B, FN_VI2_DATA0_VI2_B0_B, 149 FN_A9, FN_SCIFA1_CTS_N_B, FN_SSI_WS5_B, FN_VI0_R5, 150 FN_VI0_R5_B, FN_SCIFB2_TXD_C, FN_TX2_B, FN_VI2_DATA1_VI2_B1_B, 151 FN_A10, FN_SSI_SDATA5_B, FN_MSIOF2_SYNC, FN_VI0_R6, 152 FN_VI0_R6_B, FN_VI2_DATA2_VI2_B2_B, 153 154 /* IPSR3 */ 155 FN_A11, FN_SCIFB2_CTS_N_B, FN_MSIOF2_SCK, FN_VI1_R0, 156 FN_VI1_R0_B, FN_VI2_G0, FN_VI2_DATA3_VI2_B3_B, 157 FN_A12, FN_SCIFB2_RXD_B, FN_MSIOF2_TXD, FN_VI1_R1, 158 FN_VI1_R1_B, FN_VI2_G1, FN_VI2_DATA4_VI2_B4_B, 159 FN_A13, FN_SCIFB2_RTS_N_B, FN_EX_WAIT2, 160 FN_MSIOF2_RXD, FN_VI1_R2, FN_VI1_R2_B, FN_VI2_G2, 161 FN_VI2_DATA5_VI2_B5_B, FN_A14, FN_SCIFB2_TXD_B, 162 FN_ATACS11_N, FN_MSIOF2_SS1, FN_A15, FN_SCIFB2_SCK_B, 163 FN_ATARD1_N, FN_MSIOF2_SS2, FN_A16, FN_ATAWR1_N, 164 FN_A17, FN_AD_DO_B, FN_ATADIR1_N, FN_A18, 165 FN_AD_CLK_B, FN_ATAG1_N, FN_A19, FN_AD_NCS_N_B, 166 FN_ATACS01_N, FN_EX_WAIT0_B, FN_A20, FN_SPCLK, 167 FN_VI1_R3, FN_VI1_R3_B, FN_VI2_G4, 168 169 /* IPSR4 */ 170 FN_A21, FN_MOSI_IO0, FN_VI1_R4, FN_VI1_R4_B, FN_VI2_G5, 171 FN_A22, FN_MISO_IO1, FN_VI1_R5, FN_VI1_R5_B, 172 FN_VI2_G6, FN_A23, FN_IO2, FN_VI1_G7, 173 FN_VI1_G7_B, FN_VI2_G7, FN_A24, FN_IO3, 174 FN_VI1_R7, FN_VI1_R7_B, FN_VI2_CLKENB, 175 FN_VI2_CLKENB_B, FN_A25, FN_SSL, FN_VI1_G6, 176 FN_VI1_G6_B, FN_VI2_FIELD, FN_VI2_FIELD_B, FN_CS0_N, 177 FN_VI1_R6, FN_VI1_R6_B, FN_VI2_G3, FN_MSIOF0_SS2_B, 178 FN_CS1_N_A26, FN_SPEEDIN, FN_VI0_R7, FN_VI0_R7_B, 179 FN_VI2_CLK, FN_VI2_CLK_B, FN_EX_CS0_N, FN_HRX1_B, 180 FN_VI1_G5, FN_VI1_G5_B, FN_VI2_R0, FN_HTX0_B, 181 FN_MSIOF0_SS1_B, FN_EX_CS1_N, FN_GPS_CLK, 182 FN_HCTS1_N_B, FN_VI1_FIELD, FN_VI1_FIELD_B, 183 FN_VI2_R1, FN_EX_CS2_N, FN_GPS_SIGN, FN_HRTS1_N_B, 184 FN_VI3_CLKENB, FN_VI1_G0, FN_VI1_G0_B, FN_VI2_R2, 185 186 /* IPSR5 */ 187 FN_EX_CS3_N, FN_GPS_MAG, FN_VI3_FIELD, FN_VI1_G1, FN_VI1_G1_B, 188 FN_VI2_R3, FN_EX_CS4_N, FN_MSIOF1_SCK_B, FN_VI3_HSYNC_N, 189 FN_VI2_HSYNC_N, FN_IIC1_SCL, FN_VI2_HSYNC_N_B, 190 FN_INTC_EN0_N, FN_I2C1_SCL, FN_EX_CS5_N, FN_CAN0_RX, 191 FN_MSIOF1_RXD_B, FN_VI3_VSYNC_N, FN_VI1_G2, 192 FN_VI1_G2_B, FN_VI2_R4, FN_IIC1_SDA, FN_INTC_EN1_N, 193 FN_I2C1_SDA, FN_BS_N, FN_IETX, FN_HTX1_B, 194 FN_CAN1_TX, FN_DRACK0, FN_IETX_C, FN_RD_N, 195 FN_CAN0_TX, FN_SCIFA0_SCK_B, FN_RD_WR_N, FN_VI1_G3, 196 FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B, 197 FN_INTC_IRQ4_N, FN_WE0_N, FN_IECLK, FN_CAN_CLK, 198 FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B, 199 FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4, 200 FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B, 201 FN_IERX_C, FN_EX_WAIT0, FN_IRQ3, FN_INTC_IRQ3_N, 202 FN_VI3_CLK, FN_SCIFA0_RTS_N_B, FN_HRX0_B, 203 FN_MSIOF0_SCK_B, FN_DREQ0_N, FN_VI1_HSYNC_N, 204 FN_VI1_HSYNC_N_B, FN_VI2_R7, FN_SSI_SCK78_C, 205 FN_SSI_WS78_B, 206 207 /* IPSR6 */ 208 FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B, 209 FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, 210 FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B, 211 FN_SSI_SDATA7_C, FN_SSI_SCK78_B, FN_DACK1, FN_IRQ1, 212 FN_INTC_IRQ1_N, FN_SSI_WS6_B, FN_SSI_SDATA8_C, 213 FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B, 214 FN_MSIOF0_TXD_B, FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N, 215 FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B, 216 FN_ETH_CRS_DV, FN_STP_ISCLK_0_B, 217 FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_IIC2_SCL_E, 218 FN_I2C2_SCL_E, FN_ETH_RX_ER, 219 FN_STP_ISD_0_B, FN_TS_SPSYNC0_D, FN_GLO_Q1_C, 220 FN_IIC2_SDA_E, FN_I2C2_SDA_E, FN_ETH_RXD0, 221 FN_STP_ISEN_0_B, FN_TS_SDAT0_D, FN_GLO_I0_C, 222 FN_SCIFB1_SCK_G, FN_SCK1_E, FN_ETH_RXD1, 223 FN_HRX0_E, FN_STP_ISSYNC_0_B, 224 FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G, 225 FN_RX1_E, FN_ETH_LINK, FN_HTX0_E, 226 FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E, 227 FN_ETH_REF_CLK, FN_HCTS0_N_E, 228 FN_STP_IVCXO27_1_B, FN_HRX0_F, 229 230 /* IPSR7 */ 231 FN_ETH_MDIO, FN_HRTS0_N_E, 232 FN_SIM0_D_C, FN_HCTS0_N_F, FN_ETH_TXD1, 233 FN_HTX0_F, FN_BPFCLK_G, 234 FN_ETH_TX_EN, FN_SIM0_CLK_C, 235 FN_HRTS0_N_F, FN_ETH_MAGIC, 236 FN_SIM0_RST_C, FN_ETH_TXD0, 237 FN_STP_ISCLK_1_B, FN_TS_SDEN1_C, FN_GLO_SCLK_C, 238 FN_ETH_MDC, FN_STP_ISD_1_B, 239 FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, FN_PWM0, 240 FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C, 241 FN_GLO_SS_C, FN_PWM1, FN_SCIFA2_TXD_C, 242 FN_STP_ISSYNC_1_B, FN_TS_SCK1_C, FN_GLO_RFON_C, 243 FN_PCMOE_N, FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C, 244 FN_PCMWE_N, FN_IECLK_C, FN_DU_DOTCLKIN1, 245 FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, FN_VI0_CLK, 246 FN_ATACS00_N, FN_AVB_RXD1, 247 FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2, 248 249 /* IPSR8 */ 250 FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3, 251 FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N, 252 FN_AVB_RXD4, FN_VI0_DATA3_VI0_B3, FN_ATADIR0_N, 253 FN_AVB_RXD5, FN_VI0_DATA4_VI0_B4, FN_ATAG0_N, 254 FN_AVB_RXD6, FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1, 255 FN_AVB_RXD7, FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER, 256 FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK, 257 FN_VI1_CLK, FN_AVB_RX_DV, 258 FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D, 259 FN_AVB_CRS, FN_VI1_DATA1_VI1_B1, 260 FN_SCIFA1_RXD_D, FN_AVB_MDC, 261 FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO, 262 FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D, 263 FN_AVB_GTX_CLK, FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D, 264 FN_AVB_MAGIC, FN_VI1_DATA5_VI1_B5, 265 FN_AVB_PHY_INT, FN_VI1_DATA6_VI1_B6, FN_AVB_GTXREFCLK, 266 FN_SD0_CLK, FN_VI1_DATA0_VI1_B0_B, FN_SD0_CMD, 267 FN_SCIFB1_SCK_B, FN_VI1_DATA1_VI1_B1_B, 268 269 /* IPSR9 */ 270 FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B, 271 FN_SD0_DAT1, FN_SCIFB1_TXD_B, FN_VI1_DATA3_VI1_B3_B, 272 FN_SD0_DAT2, FN_SCIFB1_CTS_N_B, FN_VI1_DATA4_VI1_B4_B, 273 FN_SD0_DAT3, FN_SCIFB1_RTS_N_B, FN_VI1_DATA5_VI1_B5_B, 274 FN_SD0_CD, FN_MMC0_D6, FN_TS_SDEN0_B, FN_USB0_EXTP, 275 FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_IIC1_SCL_B, 276 FN_I2C1_SCL_B, FN_VI2_DATA6_VI2_B6_B, FN_SD0_WP, 277 FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN, 278 FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_IIC1_SDA_B, 279 FN_I2C1_SDA_B, FN_VI2_DATA7_VI2_B7_B, FN_SD1_CLK, 280 FN_AVB_TX_EN, FN_SD1_CMD, 281 FN_AVB_TX_ER, FN_SCIFB0_SCK_B, 282 FN_SD1_DAT0, FN_AVB_TX_CLK, 283 FN_SCIFB0_RXD_B, FN_SD1_DAT1, FN_AVB_LINK, 284 FN_SCIFB0_TXD_B, FN_SD1_DAT2, 285 FN_AVB_COL, FN_SCIFB0_CTS_N_B, 286 FN_SD1_DAT3, FN_AVB_RXD0, 287 FN_SCIFB0_RTS_N_B, FN_SD1_CD, FN_MMC1_D6, 288 FN_TS_SDEN1, FN_USB1_EXTP, FN_GLO_SS, FN_VI0_CLK_B, 289 FN_IIC2_SCL_D, FN_I2C2_SCL_D, FN_SIM0_CLK_B, 290 FN_VI3_CLK_B, 291 292 /* IPSR10 */ 293 FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN, 294 FN_GLO_RFON, FN_VI1_CLK_B, FN_IIC2_SDA_D, FN_I2C2_SDA_D, 295 FN_SIM0_D_B, FN_SD2_CLK, FN_MMC0_CLK, FN_SIM0_CLK, 296 FN_VI0_DATA0_VI0_B0_B, FN_TS_SDEN0_C, FN_GLO_SCLK_B, 297 FN_VI3_DATA0_B, FN_SD2_CMD, FN_MMC0_CMD, FN_SIM0_D, 298 FN_VI0_DATA1_VI0_B1_B, FN_SCIFB1_SCK_E, FN_SCK1_D, 299 FN_TS_SPSYNC0_C, FN_GLO_SDATA_B, FN_VI3_DATA1_B, 300 FN_SD2_DAT0, FN_MMC0_D0, FN_FMCLK_B, 301 FN_VI0_DATA2_VI0_B2_B, FN_SCIFB1_RXD_E, FN_RX1_D, 302 FN_TS_SDAT0_C, FN_GLO_SS_B, FN_VI3_DATA2_B, 303 FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B, 304 FN_VI0_DATA3_VI0_B3_B, FN_SCIFB1_TXD_E, FN_TX1_D, 305 FN_TS_SCK0_C, FN_GLO_RFON_B, FN_VI3_DATA3_B, 306 FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B, 307 FN_VI0_DATA4_VI0_B4_B, FN_HRX0_D, FN_TS_SDEN1_B, 308 FN_GLO_Q0_B, FN_VI3_DATA4_B, FN_SD2_DAT3, 309 FN_MMC0_D3, FN_SIM0_RST, FN_VI0_DATA5_VI0_B5_B, 310 FN_HTX0_D, FN_TS_SPSYNC1_B, FN_GLO_Q1_B, 311 FN_VI3_DATA5_B, FN_SD2_CD, FN_MMC0_D4, 312 FN_TS_SDAT0_B, FN_USB2_EXTP, FN_GLO_I0, 313 FN_VI0_DATA6_VI0_B6_B, FN_HCTS0_N_D, FN_TS_SDAT1_B, 314 FN_GLO_I0_B, FN_VI3_DATA6_B, 315 316 /* IPSR11 */ 317 FN_SD2_WP, FN_MMC0_D5, FN_TS_SCK0_B, FN_USB2_IDIN, 318 FN_GLO_I1, FN_VI0_DATA7_VI0_B7_B, FN_HRTS0_N_D, 319 FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B, 320 FN_SD3_CLK, FN_MMC1_CLK, FN_SD3_CMD, FN_MMC1_CMD, 321 FN_MTS_N, FN_SD3_DAT0, FN_MMC1_D0, FN_STM_N, 322 FN_SD3_DAT1, FN_MMC1_D1, FN_MDATA, FN_SD3_DAT2, 323 FN_MMC1_D2, FN_SDATA, FN_SD3_DAT3, FN_MMC1_D3, 324 FN_SCKZ, FN_SD3_CD, FN_MMC1_D4, FN_TS_SDAT1, 325 FN_VSP, FN_GLO_Q0, FN_SIM0_RST_B, FN_SD3_WP, 326 FN_MMC1_D5, FN_TS_SCK1, FN_GLO_Q1, FN_FMIN_C, 327 FN_FMIN_E, FN_FMIN_F, 328 FN_MLB_CLK, FN_IIC2_SCL_B, FN_I2C2_SCL_B, 329 FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_IIC2_SDA_B, 330 FN_I2C2_SDA_B, FN_MLB_DAT, 331 FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C, 332 FN_SSI_SCK0129, FN_CAN_CLK_B, 333 FN_MOUT0, 334 335 /* IPSR12 */ 336 FN_SSI_WS0129, FN_CAN0_TX_B, FN_MOUT1, 337 FN_SSI_SDATA0, FN_CAN0_RX_B, FN_MOUT2, 338 FN_SSI_SDATA1, FN_CAN1_TX_B, FN_MOUT5, 339 FN_SSI_SDATA2, FN_CAN1_RX_B, FN_SSI_SCK1, FN_MOUT6, 340 FN_SSI_SCK34, FN_STP_OPWM_0, FN_SCIFB0_SCK, 341 FN_MSIOF1_SCK, FN_CAN_DEBUG_HW_TRIGGER, FN_SSI_WS34, 342 FN_STP_IVCXO27_0, FN_SCIFB0_RXD, FN_MSIOF1_SYNC, 343 FN_CAN_STEP0, FN_SSI_SDATA3, FN_STP_ISCLK_0, 344 FN_SCIFB0_TXD, FN_MSIOF1_SS1, FN_CAN_TXCLK, 345 FN_SSI_SCK4, FN_STP_ISD_0, FN_SCIFB0_CTS_N, 346 FN_MSIOF1_SS2, FN_SSI_SCK5_C, FN_CAN_DEBUGOUT0, 347 FN_SSI_WS4, FN_STP_ISEN_0, FN_SCIFB0_RTS_N, 348 FN_MSIOF1_TXD, FN_SSI_WS5_C, FN_CAN_DEBUGOUT1, 349 FN_SSI_SDATA4, FN_STP_ISSYNC_0, FN_MSIOF1_RXD, 350 FN_CAN_DEBUGOUT2, FN_SSI_SCK5, FN_SCIFB1_SCK, 351 FN_IERX_B, FN_DU2_EXHSYNC_DU2_HSYNC, FN_QSTH_QHS, 352 FN_CAN_DEBUGOUT3, FN_SSI_WS5, FN_SCIFB1_RXD, 353 FN_IECLK_B, FN_DU2_EXVSYNC_DU2_VSYNC, FN_QSTB_QHE, 354 FN_CAN_DEBUGOUT4, 355 356 /* IPSR13 */ 357 FN_SSI_SDATA5, FN_SCIFB1_TXD, FN_IETX_B, FN_DU2_DR2, 358 FN_LCDOUT2, FN_CAN_DEBUGOUT5, FN_SSI_SCK6, 359 FN_SCIFB1_CTS_N, FN_BPFCLK_D, 360 FN_DU2_DR3, FN_LCDOUT3, FN_CAN_DEBUGOUT6, 361 FN_BPFCLK_F, FN_SSI_WS6, 362 FN_SCIFB1_RTS_N, FN_CAN0_TX_D, FN_DU2_DR4, 363 FN_LCDOUT4, FN_CAN_DEBUGOUT7, FN_SSI_SDATA6, 364 FN_FMIN_D, FN_DU2_DR5, FN_LCDOUT5, 365 FN_CAN_DEBUGOUT8, FN_SSI_SCK78, FN_STP_IVCXO27_1, 366 FN_SCK1, FN_SCIFA1_SCK, FN_DU2_DR6, FN_LCDOUT6, 367 FN_CAN_DEBUGOUT9, FN_SSI_WS78, FN_STP_ISCLK_1, 368 FN_SCIFB2_SCK, FN_SCIFA2_CTS_N, FN_DU2_DR7, 369 FN_LCDOUT7, FN_CAN_DEBUGOUT10, FN_SSI_SDATA7, 370 FN_STP_ISD_1, FN_SCIFB2_RXD, FN_SCIFA2_RTS_N, 371 FN_TCLK2, FN_QSTVA_QVS, FN_CAN_DEBUGOUT11, 372 FN_BPFCLK_E, FN_SSI_SDATA7_B, 373 FN_FMIN_G, FN_SSI_SDATA8, 374 FN_STP_ISEN_1, FN_SCIFB2_TXD, FN_CAN0_TX_C, 375 FN_CAN_DEBUGOUT12, FN_SSI_SDATA8_B, FN_SSI_SDATA9, 376 FN_STP_ISSYNC_1, FN_SCIFB2_CTS_N, FN_SSI_WS1, 377 FN_SSI_SDATA5_C, FN_CAN_DEBUGOUT13, FN_AUDIO_CLKA, 378 FN_SCIFB2_RTS_N, FN_CAN_DEBUGOUT14, 379 380 /* IPSR14 */ 381 FN_AUDIO_CLKB, FN_SCIF_CLK, FN_CAN0_RX_D, 382 FN_DVC_MUTE, FN_CAN0_RX_C, FN_CAN_DEBUGOUT15, 383 FN_REMOCON, FN_SCIFA0_SCK, FN_HSCK1, FN_SCK0, 384 FN_MSIOF3_SS2, FN_DU2_DG2, FN_LCDOUT10, FN_IIC1_SDA_C, 385 FN_I2C1_SDA_C, FN_SCIFA0_RXD, FN_HRX1, FN_RX0, 386 FN_DU2_DR0, FN_LCDOUT0, FN_SCIFA0_TXD, FN_HTX1, 387 FN_TX0, FN_DU2_DR1, FN_LCDOUT1, FN_SCIFA0_CTS_N, 388 FN_HCTS1_N, FN_CTS0_N, FN_MSIOF3_SYNC, FN_DU2_DG3, 389 FN_LCDOUT11, FN_PWM0_B, FN_IIC1_SCL_C, FN_I2C1_SCL_C, 390 FN_SCIFA0_RTS_N, FN_HRTS1_N, FN_RTS0_N, 391 FN_MSIOF3_SS1, FN_DU2_DG0, FN_LCDOUT8, FN_PWM1_B, 392 FN_SCIFA1_RXD, FN_AD_DI, FN_RX1, 393 FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, FN_QCPV_QDE, 394 FN_SCIFA1_TXD, FN_AD_DO, FN_TX1, FN_DU2_DG1, 395 FN_LCDOUT9, FN_SCIFA1_CTS_N, FN_AD_CLK, 396 FN_CTS1_N, FN_MSIOF3_RXD, FN_DU0_DOTCLKOUT, FN_QCLK, 397 FN_SCIFA1_RTS_N, FN_AD_NCS_N, FN_RTS1_N, 398 FN_MSIOF3_TXD, FN_DU1_DOTCLKOUT, FN_QSTVB_QVE, 399 FN_HRTS0_N_C, 400 401 /* IPSR15 */ 402 FN_SCIFA2_SCK, FN_FMCLK, FN_SCK2, FN_MSIOF3_SCK, FN_DU2_DG7, 403 FN_LCDOUT15, FN_SCIF_CLK_B, FN_SCIFA2_RXD, FN_FMIN, 404 FN_TX2, FN_DU2_DB0, FN_LCDOUT16, FN_IIC2_SCL, FN_I2C2_SCL, 405 FN_SCIFA2_TXD, FN_BPFCLK, FN_RX2, FN_DU2_DB1, FN_LCDOUT17, 406 FN_IIC2_SDA, FN_I2C2_SDA, FN_HSCK0, FN_TS_SDEN0, 407 FN_DU2_DG4, FN_LCDOUT12, FN_HCTS0_N_C, FN_HRX0, 408 FN_DU2_DB2, FN_LCDOUT18, FN_HTX0, FN_DU2_DB3, 409 FN_LCDOUT19, FN_HCTS0_N, FN_SSI_SCK9, FN_DU2_DB4, 410 FN_LCDOUT20, FN_HRTS0_N, FN_SSI_WS9, FN_DU2_DB5, 411 FN_LCDOUT21, FN_MSIOF0_SCK, FN_TS_SDAT0, FN_ADICLK, 412 FN_DU2_DB6, FN_LCDOUT22, FN_MSIOF0_SYNC, FN_TS_SCK0, 413 FN_SSI_SCK2, FN_ADIDATA, FN_DU2_DB7, FN_LCDOUT23, 414 FN_HRX0_C, FN_MSIOF0_SS1, FN_ADICHS0, 415 FN_DU2_DG5, FN_LCDOUT13, FN_MSIOF0_TXD, FN_ADICHS1, 416 FN_DU2_DG6, FN_LCDOUT14, 417 418 /* IPSR16 */ 419 FN_MSIOF0_SS2, FN_AUDIO_CLKOUT, FN_ADICHS2, 420 FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B, 421 FN_MSIOF0_RXD, FN_TS_SPSYNC0, FN_SSI_WS2, 422 FN_ADICS_SAMP, FN_DU2_CDE, FN_QPOLB, FN_SCIFA2_RXD_B, 423 FN_USB1_PWEN, FN_AUDIO_CLKOUT_D, FN_USB1_OVC, 424 FN_TCLK1_B, 425 426 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3, 427 FN_SEL_SCIF1_4, 428 FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, 429 FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, 430 FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3, 431 FN_SEL_SCIFB1_4, 432 FN_SEL_SCIFB1_5, FN_SEL_SCIFB1_6, 433 FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, FN_SEL_SCIFA1_3, 434 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, 435 FN_SEL_SCFA_0, FN_SEL_SCFA_1, 436 FN_SEL_SOF1_0, FN_SEL_SOF1_1, 437 FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2, 438 FN_SEL_SSI6_0, FN_SEL_SSI6_1, 439 FN_SEL_SSI5_0, FN_SEL_SSI5_1, FN_SEL_SSI5_2, 440 FN_SEL_VI3_0, FN_SEL_VI3_1, 441 FN_SEL_VI2_0, FN_SEL_VI2_1, 442 FN_SEL_VI1_0, FN_SEL_VI1_1, 443 FN_SEL_VI0_0, FN_SEL_VI0_1, 444 FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2, 445 FN_SEL_LBS_0, FN_SEL_LBS_1, 446 FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, 447 FN_SEL_SOF3_0, FN_SEL_SOF3_1, 448 FN_SEL_SOF0_0, FN_SEL_SOF0_1, 449 450 FN_SEL_TMU1_0, FN_SEL_TMU1_1, 451 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, 452 FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1, 453 FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3, 454 FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, 455 FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2, 456 FN_SEL_CAN1_0, FN_SEL_CAN1_1, 457 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, 458 FN_SEL_ADI_0, FN_SEL_ADI_1, 459 FN_SEL_SSP_0, FN_SEL_SSP_1, 460 FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3, 461 FN_SEL_FM_4, FN_SEL_FM_5, FN_SEL_FM_6, 462 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, FN_SEL_HSCIF0_3, 463 FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5, 464 FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, 465 FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2, 466 FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2, 467 468 FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1, 469 FN_SEL_IIC0_0, FN_SEL_IIC0_1, 470 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 471 FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3, 472 FN_SEL_IIC2_4, 473 FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, 474 FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3, 475 FN_SEL_I2C2_4, 476 FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, 477 PINMUX_FUNCTION_END, 478 479 PINMUX_MARK_BEGIN, 480 481 VI1_DATA7_VI1_B7_MARK, 482 483 USB0_PWEN_MARK, USB0_OVC_VBUS_MARK, 484 USB2_PWEN_MARK, USB2_OVC_MARK, AVS1_MARK, AVS2_MARK, 485 DU_DOTCLKIN0_MARK, DU_DOTCLKIN2_MARK, 486 487 D0_MARK, MSIOF3_SCK_B_MARK, VI3_DATA0_MARK, VI0_G4_MARK, VI0_G4_B_MARK, 488 D1_MARK, MSIOF3_SYNC_B_MARK, VI3_DATA1_MARK, VI0_G5_MARK, 489 VI0_G5_B_MARK, D2_MARK, MSIOF3_RXD_B_MARK, VI3_DATA2_MARK, 490 VI0_G6_MARK, VI0_G6_B_MARK, D3_MARK, MSIOF3_TXD_B_MARK, 491 VI3_DATA3_MARK, VI0_G7_MARK, VI0_G7_B_MARK, D4_MARK, 492 SCIFB1_RXD_F_MARK, SCIFB0_RXD_C_MARK, VI3_DATA4_MARK, 493 VI0_R0_MARK, VI0_R0_B_MARK, RX0_B_MARK, D5_MARK, 494 SCIFB1_TXD_F_MARK, SCIFB0_TXD_C_MARK, VI3_DATA5_MARK, 495 VI0_R1_MARK, VI0_R1_B_MARK, TX0_B_MARK, D6_MARK, 496 IIC2_SCL_C_MARK, VI3_DATA6_MARK, VI0_R2_MARK, VI0_R2_B_MARK, 497 I2C2_SCL_C_MARK, D7_MARK, AD_DI_B_MARK, IIC2_SDA_C_MARK, 498 VI3_DATA7_MARK, VI0_R3_MARK, VI0_R3_B_MARK, I2C2_SDA_C_MARK, TCLK1_MARK, 499 D8_MARK, SCIFA1_SCK_C_MARK, AVB_TXD0_MARK, 500 VI0_G0_MARK, VI0_G0_B_MARK, VI2_DATA0_VI2_B0_MARK, 501 502 D9_MARK, SCIFA1_RXD_C_MARK, AVB_TXD1_MARK, 503 VI0_G1_MARK, VI0_G1_B_MARK, VI2_DATA1_VI2_B1_MARK, D10_MARK, 504 SCIFA1_TXD_C_MARK, AVB_TXD2_MARK, 505 VI0_G2_MARK, VI0_G2_B_MARK, VI2_DATA2_VI2_B2_MARK, D11_MARK, 506 SCIFA1_CTS_N_C_MARK, AVB_TXD3_MARK, 507 VI0_G3_MARK, VI0_G3_B_MARK, VI2_DATA3_VI2_B3_MARK, 508 D12_MARK, SCIFA1_RTS_N_C_MARK, AVB_TXD4_MARK, 509 VI0_HSYNC_N_MARK, VI0_HSYNC_N_B_MARK, VI2_DATA4_VI2_B4_MARK, 510 D13_MARK, AVB_TXD5_MARK, VI0_VSYNC_N_MARK, 511 VI0_VSYNC_N_B_MARK, VI2_DATA5_VI2_B5_MARK, D14_MARK, 512 SCIFB1_RXD_C_MARK, AVB_TXD6_MARK, RX1_B_MARK, 513 VI0_CLKENB_MARK, VI0_CLKENB_B_MARK, VI2_DATA6_VI2_B6_MARK, 514 D15_MARK, SCIFB1_TXD_C_MARK, AVB_TXD7_MARK, TX1_B_MARK, 515 VI0_FIELD_MARK, VI0_FIELD_B_MARK, VI2_DATA7_VI2_B7_MARK, 516 A0_MARK, PWM3_MARK, A1_MARK, PWM4_MARK, 517 518 A2_MARK, PWM5_MARK, MSIOF1_SS1_B_MARK, A3_MARK, 519 PWM6_MARK, MSIOF1_SS2_B_MARK, A4_MARK, MSIOF1_TXD_B_MARK, 520 TPU0TO0_MARK, A5_MARK, SCIFA1_TXD_B_MARK, TPU0TO1_MARK, 521 A6_MARK, SCIFA1_RTS_N_B_MARK, TPU0TO2_MARK, A7_MARK, 522 SCIFA1_SCK_B_MARK, AUDIO_CLKOUT_B_MARK, TPU0TO3_MARK, 523 A8_MARK, SCIFA1_RXD_B_MARK, SSI_SCK5_B_MARK, VI0_R4_MARK, 524 VI0_R4_B_MARK, SCIFB2_RXD_C_MARK, RX2_B_MARK, VI2_DATA0_VI2_B0_B_MARK, 525 A9_MARK, SCIFA1_CTS_N_B_MARK, SSI_WS5_B_MARK, VI0_R5_MARK, 526 VI0_R5_B_MARK, SCIFB2_TXD_C_MARK, TX2_B_MARK, VI2_DATA1_VI2_B1_B_MARK, 527 A10_MARK, SSI_SDATA5_B_MARK, MSIOF2_SYNC_MARK, VI0_R6_MARK, 528 VI0_R6_B_MARK, VI2_DATA2_VI2_B2_B_MARK, 529 530 A11_MARK, SCIFB2_CTS_N_B_MARK, MSIOF2_SCK_MARK, VI1_R0_MARK, 531 VI1_R0_B_MARK, VI2_G0_MARK, VI2_DATA3_VI2_B3_B_MARK, 532 A12_MARK, SCIFB2_RXD_B_MARK, MSIOF2_TXD_MARK, VI1_R1_MARK, 533 VI1_R1_B_MARK, VI2_G1_MARK, VI2_DATA4_VI2_B4_B_MARK, 534 A13_MARK, SCIFB2_RTS_N_B_MARK, EX_WAIT2_MARK, 535 MSIOF2_RXD_MARK, VI1_R2_MARK, VI1_R2_B_MARK, VI2_G2_MARK, 536 VI2_DATA5_VI2_B5_B_MARK, A14_MARK, SCIFB2_TXD_B_MARK, 537 ATACS11_N_MARK, MSIOF2_SS1_MARK, A15_MARK, SCIFB2_SCK_B_MARK, 538 ATARD1_N_MARK, MSIOF2_SS2_MARK, A16_MARK, ATAWR1_N_MARK, 539 A17_MARK, AD_DO_B_MARK, ATADIR1_N_MARK, A18_MARK, 540 AD_CLK_B_MARK, ATAG1_N_MARK, A19_MARK, AD_NCS_N_B_MARK, 541 ATACS01_N_MARK, EX_WAIT0_B_MARK, A20_MARK, SPCLK_MARK, 542 VI1_R3_MARK, VI1_R3_B_MARK, VI2_G4_MARK, 543 544 A21_MARK, MOSI_IO0_MARK, VI1_R4_MARK, VI1_R4_B_MARK, VI2_G5_MARK, 545 A22_MARK, MISO_IO1_MARK, VI1_R5_MARK, VI1_R5_B_MARK, 546 VI2_G6_MARK, A23_MARK, IO2_MARK, VI1_G7_MARK, 547 VI1_G7_B_MARK, VI2_G7_MARK, A24_MARK, IO3_MARK, 548 VI1_R7_MARK, VI1_R7_B_MARK, VI2_CLKENB_MARK, 549 VI2_CLKENB_B_MARK, A25_MARK, SSL_MARK, VI1_G6_MARK, 550 VI1_G6_B_MARK, VI2_FIELD_MARK, VI2_FIELD_B_MARK, CS0_N_MARK, 551 VI1_R6_MARK, VI1_R6_B_MARK, VI2_G3_MARK, MSIOF0_SS2_B_MARK, 552 CS1_N_A26_MARK, SPEEDIN_MARK, VI0_R7_MARK, VI0_R7_B_MARK, 553 VI2_CLK_MARK, VI2_CLK_B_MARK, EX_CS0_N_MARK, HRX1_B_MARK, 554 VI1_G5_MARK, VI1_G5_B_MARK, VI2_R0_MARK, HTX0_B_MARK, 555 MSIOF0_SS1_B_MARK, EX_CS1_N_MARK, GPS_CLK_MARK, 556 HCTS1_N_B_MARK, VI1_FIELD_MARK, VI1_FIELD_B_MARK, 557 VI2_R1_MARK, EX_CS2_N_MARK, GPS_SIGN_MARK, HRTS1_N_B_MARK, 558 VI3_CLKENB_MARK, VI1_G0_MARK, VI1_G0_B_MARK, VI2_R2_MARK, 559 560 EX_CS3_N_MARK, GPS_MAG_MARK, VI3_FIELD_MARK, 561 VI1_G1_MARK, VI1_G1_B_MARK, VI2_R3_MARK, 562 EX_CS4_N_MARK, MSIOF1_SCK_B_MARK, VI3_HSYNC_N_MARK, 563 VI2_HSYNC_N_MARK, IIC1_SCL_MARK, VI2_HSYNC_N_B_MARK, 564 INTC_EN0_N_MARK, I2C1_SCL_MARK, EX_CS5_N_MARK, CAN0_RX_MARK, 565 MSIOF1_RXD_B_MARK, VI3_VSYNC_N_MARK, VI1_G2_MARK, 566 VI1_G2_B_MARK, VI2_R4_MARK, IIC1_SDA_MARK, INTC_EN1_N_MARK, 567 I2C1_SDA_MARK, BS_N_MARK, IETX_MARK, HTX1_B_MARK, 568 CAN1_TX_MARK, DRACK0_MARK, IETX_C_MARK, RD_N_MARK, 569 CAN0_TX_MARK, SCIFA0_SCK_B_MARK, RD_WR_N_MARK, VI1_G3_MARK, 570 VI1_G3_B_MARK, VI2_R5_MARK, SCIFA0_RXD_B_MARK, 571 INTC_IRQ4_N_MARK, WE0_N_MARK, IECLK_MARK, CAN_CLK_MARK, 572 VI2_VSYNC_N_MARK, SCIFA0_TXD_B_MARK, VI2_VSYNC_N_B_MARK, 573 WE1_N_MARK, IERX_MARK, CAN1_RX_MARK, VI1_G4_MARK, 574 VI1_G4_B_MARK, VI2_R6_MARK, SCIFA0_CTS_N_B_MARK, 575 IERX_C_MARK, EX_WAIT0_MARK, IRQ3_MARK, INTC_IRQ3_N_MARK, 576 VI3_CLK_MARK, SCIFA0_RTS_N_B_MARK, HRX0_B_MARK, 577 MSIOF0_SCK_B_MARK, DREQ0_N_MARK, VI1_HSYNC_N_MARK, 578 VI1_HSYNC_N_B_MARK, VI2_R7_MARK, SSI_SCK78_C_MARK, 579 SSI_WS78_B_MARK, 580 581 DACK0_MARK, IRQ0_MARK, INTC_IRQ0_N_MARK, SSI_SCK6_B_MARK, 582 VI1_VSYNC_N_MARK, VI1_VSYNC_N_B_MARK, SSI_WS78_C_MARK, 583 DREQ1_N_MARK, VI1_CLKENB_MARK, VI1_CLKENB_B_MARK, 584 SSI_SDATA7_C_MARK, SSI_SCK78_B_MARK, DACK1_MARK, IRQ1_MARK, 585 INTC_IRQ1_N_MARK, SSI_WS6_B_MARK, SSI_SDATA8_C_MARK, 586 DREQ2_N_MARK, HSCK1_B_MARK, HCTS0_N_B_MARK, 587 MSIOF0_TXD_B_MARK, DACK2_MARK, IRQ2_MARK, INTC_IRQ2_N_MARK, 588 SSI_SDATA6_B_MARK, HRTS0_N_B_MARK, MSIOF0_RXD_B_MARK, 589 ETH_CRS_DV_MARK, STP_ISCLK_0_B_MARK, 590 TS_SDEN0_D_MARK, GLO_Q0_C_MARK, IIC2_SCL_E_MARK, 591 I2C2_SCL_E_MARK, ETH_RX_ER_MARK, 592 STP_ISD_0_B_MARK, TS_SPSYNC0_D_MARK, GLO_Q1_C_MARK, 593 IIC2_SDA_E_MARK, I2C2_SDA_E_MARK, ETH_RXD0_MARK, 594 STP_ISEN_0_B_MARK, TS_SDAT0_D_MARK, GLO_I0_C_MARK, 595 SCIFB1_SCK_G_MARK, SCK1_E_MARK, ETH_RXD1_MARK, 596 HRX0_E_MARK, STP_ISSYNC_0_B_MARK, 597 TS_SCK0_D_MARK, GLO_I1_C_MARK, SCIFB1_RXD_G_MARK, 598 RX1_E_MARK, ETH_LINK_MARK, HTX0_E_MARK, 599 STP_IVCXO27_0_B_MARK, SCIFB1_TXD_G_MARK, TX1_E_MARK, 600 ETH_REF_CLK_MARK, HCTS0_N_E_MARK, 601 STP_IVCXO27_1_B_MARK, HRX0_F_MARK, 602 603 ETH_MDIO_MARK, HRTS0_N_E_MARK, 604 SIM0_D_C_MARK, HCTS0_N_F_MARK, ETH_TXD1_MARK, 605 HTX0_F_MARK, BPFCLK_G_MARK, 606 ETH_TX_EN_MARK, SIM0_CLK_C_MARK, 607 HRTS0_N_F_MARK, ETH_MAGIC_MARK, 608 SIM0_RST_C_MARK, ETH_TXD0_MARK, 609 STP_ISCLK_1_B_MARK, TS_SDEN1_C_MARK, GLO_SCLK_C_MARK, 610 ETH_MDC_MARK, STP_ISD_1_B_MARK, 611 TS_SPSYNC1_C_MARK, GLO_SDATA_C_MARK, PWM0_MARK, 612 SCIFA2_SCK_C_MARK, STP_ISEN_1_B_MARK, TS_SDAT1_C_MARK, 613 GLO_SS_C_MARK, PWM1_MARK, SCIFA2_TXD_C_MARK, 614 STP_ISSYNC_1_B_MARK, TS_SCK1_C_MARK, GLO_RFON_C_MARK, 615 PCMOE_N_MARK, PWM2_MARK, PWMFSW0_MARK, SCIFA2_RXD_C_MARK, 616 PCMWE_N_MARK, IECLK_C_MARK, DU_DOTCLKIN1_MARK, 617 AUDIO_CLKC_MARK, AUDIO_CLKOUT_C_MARK, VI0_CLK_MARK, 618 ATACS00_N_MARK, AVB_RXD1_MARK, 619 VI0_DATA0_VI0_B0_MARK, ATACS10_N_MARK, AVB_RXD2_MARK, 620 621 VI0_DATA1_VI0_B1_MARK, ATARD0_N_MARK, AVB_RXD3_MARK, 622 VI0_DATA2_VI0_B2_MARK, ATAWR0_N_MARK, 623 AVB_RXD4_MARK, VI0_DATA3_VI0_B3_MARK, ATADIR0_N_MARK, 624 AVB_RXD5_MARK, VI0_DATA4_VI0_B4_MARK, ATAG0_N_MARK, 625 AVB_RXD6_MARK, VI0_DATA5_VI0_B5_MARK, EX_WAIT1_MARK, 626 AVB_RXD7_MARK, VI0_DATA6_VI0_B6_MARK, AVB_RX_ER_MARK, 627 VI0_DATA7_VI0_B7_MARK, AVB_RX_CLK_MARK, 628 VI1_CLK_MARK, AVB_RX_DV_MARK, 629 VI1_DATA0_VI1_B0_MARK, SCIFA1_SCK_D_MARK, 630 AVB_CRS_MARK, VI1_DATA1_VI1_B1_MARK, 631 SCIFA1_RXD_D_MARK, AVB_MDC_MARK, 632 VI1_DATA2_VI1_B2_MARK, SCIFA1_TXD_D_MARK, AVB_MDIO_MARK, 633 VI1_DATA3_VI1_B3_MARK, SCIFA1_CTS_N_D_MARK, 634 AVB_GTX_CLK_MARK, VI1_DATA4_VI1_B4_MARK, SCIFA1_RTS_N_D_MARK, 635 AVB_MAGIC_MARK, VI1_DATA5_VI1_B5_MARK, 636 AVB_PHY_INT_MARK, VI1_DATA6_VI1_B6_MARK, AVB_GTXREFCLK_MARK, 637 SD0_CLK_MARK, VI1_DATA0_VI1_B0_B_MARK, SD0_CMD_MARK, 638 SCIFB1_SCK_B_MARK, VI1_DATA1_VI1_B1_B_MARK, 639 640 SD0_DAT0_MARK, SCIFB1_RXD_B_MARK, VI1_DATA2_VI1_B2_B_MARK, 641 SD0_DAT1_MARK, SCIFB1_TXD_B_MARK, VI1_DATA3_VI1_B3_B_MARK, 642 SD0_DAT2_MARK, SCIFB1_CTS_N_B_MARK, VI1_DATA4_VI1_B4_B_MARK, 643 SD0_DAT3_MARK, SCIFB1_RTS_N_B_MARK, VI1_DATA5_VI1_B5_B_MARK, 644 SD0_CD_MARK, MMC0_D6_MARK, TS_SDEN0_B_MARK, USB0_EXTP_MARK, 645 GLO_SCLK_MARK, VI1_DATA6_VI1_B6_B_MARK, IIC1_SCL_B_MARK, 646 I2C1_SCL_B_MARK, VI2_DATA6_VI2_B6_B_MARK, SD0_WP_MARK, 647 MMC0_D7_MARK, TS_SPSYNC0_B_MARK, USB0_IDIN_MARK, 648 GLO_SDATA_MARK, VI1_DATA7_VI1_B7_B_MARK, IIC1_SDA_B_MARK, 649 I2C1_SDA_B_MARK, VI2_DATA7_VI2_B7_B_MARK, SD1_CLK_MARK, 650 AVB_TX_EN_MARK, SD1_CMD_MARK, 651 AVB_TX_ER_MARK, SCIFB0_SCK_B_MARK, 652 SD1_DAT0_MARK, AVB_TX_CLK_MARK, 653 SCIFB0_RXD_B_MARK, SD1_DAT1_MARK, AVB_LINK_MARK, 654 SCIFB0_TXD_B_MARK, SD1_DAT2_MARK, 655 AVB_COL_MARK, SCIFB0_CTS_N_B_MARK, 656 SD1_DAT3_MARK, AVB_RXD0_MARK, 657 SCIFB0_RTS_N_B_MARK, SD1_CD_MARK, MMC1_D6_MARK, 658 TS_SDEN1_MARK, USB1_EXTP_MARK, GLO_SS_MARK, VI0_CLK_B_MARK, 659 IIC2_SCL_D_MARK, I2C2_SCL_D_MARK, SIM0_CLK_B_MARK, 660 VI3_CLK_B_MARK, 661 662 SD1_WP_MARK, MMC1_D7_MARK, TS_SPSYNC1_MARK, USB1_IDIN_MARK, 663 GLO_RFON_MARK, VI1_CLK_B_MARK, IIC2_SDA_D_MARK, I2C2_SDA_D_MARK, 664 SIM0_D_B_MARK, SD2_CLK_MARK, MMC0_CLK_MARK, SIM0_CLK_MARK, 665 VI0_DATA0_VI0_B0_B_MARK, TS_SDEN0_C_MARK, GLO_SCLK_B_MARK, 666 VI3_DATA0_B_MARK, SD2_CMD_MARK, MMC0_CMD_MARK, SIM0_D_MARK, 667 VI0_DATA1_VI0_B1_B_MARK, SCIFB1_SCK_E_MARK, SCK1_D_MARK, 668 TS_SPSYNC0_C_MARK, GLO_SDATA_B_MARK, VI3_DATA1_B_MARK, 669 SD2_DAT0_MARK, MMC0_D0_MARK, FMCLK_B_MARK, 670 VI0_DATA2_VI0_B2_B_MARK, SCIFB1_RXD_E_MARK, RX1_D_MARK, 671 TS_SDAT0_C_MARK, GLO_SS_B_MARK, VI3_DATA2_B_MARK, 672 SD2_DAT1_MARK, MMC0_D1_MARK, FMIN_B_MARK, 673 VI0_DATA3_VI0_B3_B_MARK, SCIFB1_TXD_E_MARK, TX1_D_MARK, 674 TS_SCK0_C_MARK, GLO_RFON_B_MARK, VI3_DATA3_B_MARK, 675 SD2_DAT2_MARK, MMC0_D2_MARK, BPFCLK_B_MARK, 676 VI0_DATA4_VI0_B4_B_MARK, HRX0_D_MARK, TS_SDEN1_B_MARK, 677 GLO_Q0_B_MARK, VI3_DATA4_B_MARK, SD2_DAT3_MARK, 678 MMC0_D3_MARK, SIM0_RST_MARK, VI0_DATA5_VI0_B5_B_MARK, 679 HTX0_D_MARK, TS_SPSYNC1_B_MARK, GLO_Q1_B_MARK, 680 VI3_DATA5_B_MARK, SD2_CD_MARK, MMC0_D4_MARK, 681 TS_SDAT0_B_MARK, USB2_EXTP_MARK, GLO_I0_MARK, 682 VI0_DATA6_VI0_B6_B_MARK, HCTS0_N_D_MARK, TS_SDAT1_B_MARK, 683 GLO_I0_B_MARK, VI3_DATA6_B_MARK, 684 685 SD2_WP_MARK, MMC0_D5_MARK, TS_SCK0_B_MARK, USB2_IDIN_MARK, 686 GLO_I1_MARK, VI0_DATA7_VI0_B7_B_MARK, HRTS0_N_D_MARK, 687 TS_SCK1_B_MARK, GLO_I1_B_MARK, VI3_DATA7_B_MARK, 688 SD3_CLK_MARK, MMC1_CLK_MARK, SD3_CMD_MARK, MMC1_CMD_MARK, 689 MTS_N_MARK, SD3_DAT0_MARK, MMC1_D0_MARK, STM_N_MARK, 690 SD3_DAT1_MARK, MMC1_D1_MARK, MDATA_MARK, SD3_DAT2_MARK, 691 MMC1_D2_MARK, SDATA_MARK, SD3_DAT3_MARK, MMC1_D3_MARK, 692 SCKZ_MARK, SD3_CD_MARK, MMC1_D4_MARK, TS_SDAT1_MARK, 693 VSP_MARK, GLO_Q0_MARK, SIM0_RST_B_MARK, SD3_WP_MARK, 694 MMC1_D5_MARK, TS_SCK1_MARK, GLO_Q1_MARK, FMIN_C_MARK, 695 FMIN_E_MARK, FMIN_F_MARK, 696 MLB_CLK_MARK, IIC2_SCL_B_MARK, I2C2_SCL_B_MARK, 697 MLB_SIG_MARK, SCIFB1_RXD_D_MARK, RX1_C_MARK, IIC2_SDA_B_MARK, 698 I2C2_SDA_B_MARK, MLB_DAT_MARK, 699 SCIFB1_TXD_D_MARK, TX1_C_MARK, BPFCLK_C_MARK, 700 SSI_SCK0129_MARK, CAN_CLK_B_MARK, 701 MOUT0_MARK, 702 703 SSI_WS0129_MARK, CAN0_TX_B_MARK, MOUT1_MARK, 704 SSI_SDATA0_MARK, CAN0_RX_B_MARK, MOUT2_MARK, 705 SSI_SDATA1_MARK, CAN1_TX_B_MARK, MOUT5_MARK, 706 SSI_SDATA2_MARK, CAN1_RX_B_MARK, SSI_SCK1_MARK, MOUT6_MARK, 707 SSI_SCK34_MARK, STP_OPWM_0_MARK, SCIFB0_SCK_MARK, 708 MSIOF1_SCK_MARK, CAN_DEBUG_HW_TRIGGER_MARK, SSI_WS34_MARK, 709 STP_IVCXO27_0_MARK, SCIFB0_RXD_MARK, MSIOF1_SYNC_MARK, 710 CAN_STEP0_MARK, SSI_SDATA3_MARK, STP_ISCLK_0_MARK, 711 SCIFB0_TXD_MARK, MSIOF1_SS1_MARK, CAN_TXCLK_MARK, 712 SSI_SCK4_MARK, STP_ISD_0_MARK, SCIFB0_CTS_N_MARK, 713 MSIOF1_SS2_MARK, SSI_SCK5_C_MARK, CAN_DEBUGOUT0_MARK, 714 SSI_WS4_MARK, STP_ISEN_0_MARK, SCIFB0_RTS_N_MARK, 715 MSIOF1_TXD_MARK, SSI_WS5_C_MARK, CAN_DEBUGOUT1_MARK, 716 SSI_SDATA4_MARK, STP_ISSYNC_0_MARK, MSIOF1_RXD_MARK, 717 CAN_DEBUGOUT2_MARK, SSI_SCK5_MARK, SCIFB1_SCK_MARK, 718 IERX_B_MARK, DU2_EXHSYNC_DU2_HSYNC_MARK, QSTH_QHS_MARK, 719 CAN_DEBUGOUT3_MARK, SSI_WS5_MARK, SCIFB1_RXD_MARK, 720 IECLK_B_MARK, DU2_EXVSYNC_DU2_VSYNC_MARK, QSTB_QHE_MARK, 721 CAN_DEBUGOUT4_MARK, 722 723 SSI_SDATA5_MARK, SCIFB1_TXD_MARK, IETX_B_MARK, DU2_DR2_MARK, 724 LCDOUT2_MARK, CAN_DEBUGOUT5_MARK, SSI_SCK6_MARK, 725 SCIFB1_CTS_N_MARK, BPFCLK_D_MARK, 726 DU2_DR3_MARK, LCDOUT3_MARK, CAN_DEBUGOUT6_MARK, 727 BPFCLK_F_MARK, SSI_WS6_MARK, 728 SCIFB1_RTS_N_MARK, CAN0_TX_D_MARK, DU2_DR4_MARK, 729 LCDOUT4_MARK, CAN_DEBUGOUT7_MARK, SSI_SDATA6_MARK, 730 FMIN_D_MARK, DU2_DR5_MARK, LCDOUT5_MARK, 731 CAN_DEBUGOUT8_MARK, SSI_SCK78_MARK, STP_IVCXO27_1_MARK, 732 SCK1_MARK, SCIFA1_SCK_MARK, DU2_DR6_MARK, LCDOUT6_MARK, 733 CAN_DEBUGOUT9_MARK, SSI_WS78_MARK, STP_ISCLK_1_MARK, 734 SCIFB2_SCK_MARK, SCIFA2_CTS_N_MARK, DU2_DR7_MARK, 735 LCDOUT7_MARK, CAN_DEBUGOUT10_MARK, SSI_SDATA7_MARK, 736 STP_ISD_1_MARK, SCIFB2_RXD_MARK, SCIFA2_RTS_N_MARK, 737 TCLK2_MARK, QSTVA_QVS_MARK, CAN_DEBUGOUT11_MARK, 738 BPFCLK_E_MARK, SSI_SDATA7_B_MARK, 739 FMIN_G_MARK, SSI_SDATA8_MARK, 740 STP_ISEN_1_MARK, SCIFB2_TXD_MARK, CAN0_TX_C_MARK, 741 CAN_DEBUGOUT12_MARK, SSI_SDATA8_B_MARK, SSI_SDATA9_MARK, 742 STP_ISSYNC_1_MARK, SCIFB2_CTS_N_MARK, SSI_WS1_MARK, 743 SSI_SDATA5_C_MARK, CAN_DEBUGOUT13_MARK, AUDIO_CLKA_MARK, 744 SCIFB2_RTS_N_MARK, CAN_DEBUGOUT14_MARK, 745 746 AUDIO_CLKB_MARK, SCIF_CLK_MARK, CAN0_RX_D_MARK, 747 DVC_MUTE_MARK, CAN0_RX_C_MARK, CAN_DEBUGOUT15_MARK, 748 REMOCON_MARK, SCIFA0_SCK_MARK, HSCK1_MARK, SCK0_MARK, 749 MSIOF3_SS2_MARK, DU2_DG2_MARK, LCDOUT10_MARK, IIC1_SDA_C_MARK, 750 I2C1_SDA_C_MARK, SCIFA0_RXD_MARK, HRX1_MARK, RX0_MARK, 751 DU2_DR0_MARK, LCDOUT0_MARK, SCIFA0_TXD_MARK, HTX1_MARK, 752 TX0_MARK, DU2_DR1_MARK, LCDOUT1_MARK, SCIFA0_CTS_N_MARK, 753 HCTS1_N_MARK, CTS0_N_MARK, MSIOF3_SYNC_MARK, DU2_DG3_MARK, 754 LCDOUT11_MARK, PWM0_B_MARK, IIC1_SCL_C_MARK, I2C1_SCL_C_MARK, 755 SCIFA0_RTS_N_MARK, HRTS1_N_MARK, RTS0_N_MARK, 756 MSIOF3_SS1_MARK, DU2_DG0_MARK, LCDOUT8_MARK, PWM1_B_MARK, 757 SCIFA1_RXD_MARK, AD_DI_MARK, RX1_MARK, 758 DU2_EXODDF_DU2_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK, 759 SCIFA1_TXD_MARK, AD_DO_MARK, TX1_MARK, DU2_DG1_MARK, 760 LCDOUT9_MARK, SCIFA1_CTS_N_MARK, AD_CLK_MARK, 761 CTS1_N_MARK, MSIOF3_RXD_MARK, DU0_DOTCLKOUT_MARK, QCLK_MARK, 762 SCIFA1_RTS_N_MARK, AD_NCS_N_MARK, RTS1_N_MARK, 763 MSIOF3_TXD_MARK, DU1_DOTCLKOUT_MARK, QSTVB_QVE_MARK, 764 HRTS0_N_C_MARK, 765 766 SCIFA2_SCK_MARK, FMCLK_MARK, SCK2_MARK, MSIOF3_SCK_MARK, DU2_DG7_MARK, 767 LCDOUT15_MARK, SCIF_CLK_B_MARK, SCIFA2_RXD_MARK, FMIN_MARK, 768 TX2_MARK, DU2_DB0_MARK, LCDOUT16_MARK, IIC2_SCL_MARK, I2C2_SCL_MARK, 769 SCIFA2_TXD_MARK, BPFCLK_MARK, RX2_MARK, DU2_DB1_MARK, LCDOUT17_MARK, 770 IIC2_SDA_MARK, I2C2_SDA_MARK, HSCK0_MARK, TS_SDEN0_MARK, 771 DU2_DG4_MARK, LCDOUT12_MARK, HCTS0_N_C_MARK, HRX0_MARK, 772 DU2_DB2_MARK, LCDOUT18_MARK, HTX0_MARK, DU2_DB3_MARK, 773 LCDOUT19_MARK, HCTS0_N_MARK, SSI_SCK9_MARK, DU2_DB4_MARK, 774 LCDOUT20_MARK, HRTS0_N_MARK, SSI_WS9_MARK, DU2_DB5_MARK, 775 LCDOUT21_MARK, MSIOF0_SCK_MARK, TS_SDAT0_MARK, ADICLK_MARK, 776 DU2_DB6_MARK, LCDOUT22_MARK, MSIOF0_SYNC_MARK, TS_SCK0_MARK, 777 SSI_SCK2_MARK, ADIDATA_MARK, DU2_DB7_MARK, LCDOUT23_MARK, 778 HRX0_C_MARK, MSIOF0_SS1_MARK, ADICHS0_MARK, 779 DU2_DG5_MARK, LCDOUT13_MARK, MSIOF0_TXD_MARK, ADICHS1_MARK, 780 DU2_DG6_MARK, LCDOUT14_MARK, 781 782 MSIOF0_SS2_MARK, AUDIO_CLKOUT_MARK, ADICHS2_MARK, 783 DU2_DISP_MARK, QPOLA_MARK, HTX0_C_MARK, SCIFA2_TXD_B_MARK, 784 MSIOF0_RXD_MARK, TS_SPSYNC0_MARK, SSI_WS2_MARK, 785 ADICS_SAMP_MARK, DU2_CDE_MARK, QPOLB_MARK, SCIFA2_RXD_B_MARK, 786 USB1_PWEN_MARK, AUDIO_CLKOUT_D_MARK, USB1_OVC_MARK, 787 TCLK1_B_MARK, 788 789 IIC0_SCL_MARK, IIC0_SDA_MARK, I2C0_SCL_MARK, I2C0_SDA_MARK, 790 IIC3_SCL_MARK, IIC3_SDA_MARK, I2C3_SCL_MARK, I2C3_SDA_MARK, 791 PINMUX_MARK_END, 792 }; 793 794 static const u16 pinmux_data[] = { 795 PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */ 796 797 PINMUX_SINGLE(VI1_DATA7_VI1_B7), 798 PINMUX_SINGLE(USB0_PWEN), 799 PINMUX_SINGLE(USB0_OVC_VBUS), 800 PINMUX_SINGLE(USB2_PWEN), 801 PINMUX_SINGLE(USB2_OVC), 802 PINMUX_SINGLE(AVS1), 803 PINMUX_SINGLE(AVS2), 804 PINMUX_SINGLE(DU_DOTCLKIN0), 805 PINMUX_SINGLE(DU_DOTCLKIN2), 806 807 PINMUX_IPSR_GPSR(IP0_2_0, D0), 808 PINMUX_IPSR_MSEL(IP0_2_0, MSIOF3_SCK_B, SEL_SOF3_1), 809 PINMUX_IPSR_MSEL(IP0_2_0, VI3_DATA0, SEL_VI3_0), 810 PINMUX_IPSR_MSEL(IP0_2_0, VI0_G4, SEL_VI0_0), 811 PINMUX_IPSR_MSEL(IP0_2_0, VI0_G4_B, SEL_VI0_1), 812 PINMUX_IPSR_GPSR(IP0_5_3, D1), 813 PINMUX_IPSR_MSEL(IP0_5_3, MSIOF3_SYNC_B, SEL_SOF3_1), 814 PINMUX_IPSR_MSEL(IP0_5_3, VI3_DATA1, SEL_VI3_0), 815 PINMUX_IPSR_MSEL(IP0_5_3, VI0_G5, SEL_VI0_0), 816 PINMUX_IPSR_MSEL(IP0_5_3, VI0_G5_B, SEL_VI0_1), 817 PINMUX_IPSR_GPSR(IP0_8_6, D2), 818 PINMUX_IPSR_MSEL(IP0_8_6, MSIOF3_RXD_B, SEL_SOF3_1), 819 PINMUX_IPSR_MSEL(IP0_8_6, VI3_DATA2, SEL_VI3_0), 820 PINMUX_IPSR_MSEL(IP0_8_6, VI0_G6, SEL_VI0_0), 821 PINMUX_IPSR_MSEL(IP0_8_6, VI0_G6_B, SEL_VI0_1), 822 PINMUX_IPSR_GPSR(IP0_11_9, D3), 823 PINMUX_IPSR_MSEL(IP0_11_9, MSIOF3_TXD_B, SEL_SOF3_1), 824 PINMUX_IPSR_MSEL(IP0_11_9, VI3_DATA3, SEL_VI3_0), 825 PINMUX_IPSR_MSEL(IP0_11_9, VI0_G7, SEL_VI0_0), 826 PINMUX_IPSR_MSEL(IP0_11_9, VI0_G7_B, SEL_VI0_1), 827 PINMUX_IPSR_GPSR(IP0_15_12, D4), 828 PINMUX_IPSR_MSEL(IP0_15_12, SCIFB1_RXD_F, SEL_SCIFB1_5), 829 PINMUX_IPSR_MSEL(IP0_15_12, SCIFB0_RXD_C, SEL_SCIFB_2), 830 PINMUX_IPSR_MSEL(IP0_15_12, VI3_DATA4, SEL_VI3_0), 831 PINMUX_IPSR_MSEL(IP0_15_12, VI0_R0, SEL_VI0_0), 832 PINMUX_IPSR_MSEL(IP0_15_12, VI0_R0_B, SEL_VI0_1), 833 PINMUX_IPSR_MSEL(IP0_15_12, RX0_B, SEL_SCIF0_1), 834 PINMUX_IPSR_GPSR(IP0_19_16, D5), 835 PINMUX_IPSR_MSEL(IP0_19_16, SCIFB1_TXD_F, SEL_SCIFB1_5), 836 PINMUX_IPSR_MSEL(IP0_19_16, SCIFB0_TXD_C, SEL_SCIFB_2), 837 PINMUX_IPSR_MSEL(IP0_19_16, VI3_DATA5, SEL_VI3_0), 838 PINMUX_IPSR_MSEL(IP0_19_16, VI0_R1, SEL_VI0_0), 839 PINMUX_IPSR_MSEL(IP0_19_16, VI0_R1_B, SEL_VI0_1), 840 PINMUX_IPSR_MSEL(IP0_19_16, TX0_B, SEL_SCIF0_1), 841 PINMUX_IPSR_GPSR(IP0_22_20, D6), 842 PINMUX_IPSR_MSEL(IP0_22_20, IIC2_SCL_C, SEL_IIC2_2), 843 PINMUX_IPSR_MSEL(IP0_22_20, VI3_DATA6, SEL_VI3_0), 844 PINMUX_IPSR_MSEL(IP0_22_20, VI0_R2, SEL_VI0_0), 845 PINMUX_IPSR_MSEL(IP0_22_20, VI0_R2_B, SEL_VI0_1), 846 PINMUX_IPSR_MSEL(IP0_22_20, I2C2_SCL_C, SEL_I2C2_2), 847 PINMUX_IPSR_GPSR(IP0_26_23, D7), 848 PINMUX_IPSR_MSEL(IP0_26_23, AD_DI_B, SEL_ADI_1), 849 PINMUX_IPSR_MSEL(IP0_26_23, IIC2_SDA_C, SEL_IIC2_2), 850 PINMUX_IPSR_MSEL(IP0_26_23, VI3_DATA7, SEL_VI3_0), 851 PINMUX_IPSR_MSEL(IP0_26_23, VI0_R3, SEL_VI0_0), 852 PINMUX_IPSR_MSEL(IP0_26_23, VI0_R3_B, SEL_VI0_1), 853 PINMUX_IPSR_MSEL(IP0_26_23, I2C2_SDA_C, SEL_I2C2_2), 854 PINMUX_IPSR_MSEL(IP0_26_23, TCLK1, SEL_TMU1_0), 855 PINMUX_IPSR_GPSR(IP0_30_27, D8), 856 PINMUX_IPSR_MSEL(IP0_30_27, SCIFA1_SCK_C, SEL_SCIFA1_2), 857 PINMUX_IPSR_GPSR(IP0_30_27, AVB_TXD0), 858 PINMUX_IPSR_MSEL(IP0_30_27, VI0_G0, SEL_VI0_0), 859 PINMUX_IPSR_MSEL(IP0_30_27, VI0_G0_B, SEL_VI0_1), 860 PINMUX_IPSR_MSEL(IP0_30_27, VI2_DATA0_VI2_B0, SEL_VI2_0), 861 862 PINMUX_IPSR_GPSR(IP1_3_0, D9), 863 PINMUX_IPSR_MSEL(IP1_3_0, SCIFA1_RXD_C, SEL_SCIFA1_2), 864 PINMUX_IPSR_GPSR(IP1_3_0, AVB_TXD1), 865 PINMUX_IPSR_MSEL(IP1_3_0, VI0_G1, SEL_VI0_0), 866 PINMUX_IPSR_MSEL(IP1_3_0, VI0_G1_B, SEL_VI0_1), 867 PINMUX_IPSR_MSEL(IP1_3_0, VI2_DATA1_VI2_B1, SEL_VI2_0), 868 PINMUX_IPSR_GPSR(IP1_7_4, D10), 869 PINMUX_IPSR_MSEL(IP1_7_4, SCIFA1_TXD_C, SEL_SCIFA1_2), 870 PINMUX_IPSR_GPSR(IP1_7_4, AVB_TXD2), 871 PINMUX_IPSR_MSEL(IP1_7_4, VI0_G2, SEL_VI0_0), 872 PINMUX_IPSR_MSEL(IP1_7_4, VI0_G2_B, SEL_VI0_1), 873 PINMUX_IPSR_MSEL(IP1_7_4, VI2_DATA2_VI2_B2, SEL_VI2_0), 874 PINMUX_IPSR_GPSR(IP1_11_8, D11), 875 PINMUX_IPSR_MSEL(IP1_11_8, SCIFA1_CTS_N_C, SEL_SCIFA1_2), 876 PINMUX_IPSR_GPSR(IP1_11_8, AVB_TXD3), 877 PINMUX_IPSR_MSEL(IP1_11_8, VI0_G3, SEL_VI0_0), 878 PINMUX_IPSR_MSEL(IP1_11_8, VI0_G3_B, SEL_VI0_1), 879 PINMUX_IPSR_MSEL(IP1_11_8, VI2_DATA3_VI2_B3, SEL_VI2_0), 880 PINMUX_IPSR_GPSR(IP1_14_12, D12), 881 PINMUX_IPSR_MSEL(IP1_14_12, SCIFA1_RTS_N_C, SEL_SCIFA1_2), 882 PINMUX_IPSR_GPSR(IP1_14_12, AVB_TXD4), 883 PINMUX_IPSR_MSEL(IP1_14_12, VI0_HSYNC_N, SEL_VI0_0), 884 PINMUX_IPSR_MSEL(IP1_14_12, VI0_HSYNC_N_B, SEL_VI0_1), 885 PINMUX_IPSR_MSEL(IP1_14_12, VI2_DATA4_VI2_B4, SEL_VI2_0), 886 PINMUX_IPSR_GPSR(IP1_17_15, D13), 887 PINMUX_IPSR_GPSR(IP1_17_15, AVB_TXD5), 888 PINMUX_IPSR_MSEL(IP1_17_15, VI0_VSYNC_N, SEL_VI0_0), 889 PINMUX_IPSR_MSEL(IP1_17_15, VI0_VSYNC_N_B, SEL_VI0_1), 890 PINMUX_IPSR_MSEL(IP1_17_15, VI2_DATA5_VI2_B5, SEL_VI2_0), 891 PINMUX_IPSR_GPSR(IP1_21_18, D14), 892 PINMUX_IPSR_MSEL(IP1_21_18, SCIFB1_RXD_C, SEL_SCIFB1_2), 893 PINMUX_IPSR_GPSR(IP1_21_18, AVB_TXD6), 894 PINMUX_IPSR_MSEL(IP1_21_18, RX1_B, SEL_SCIF1_1), 895 PINMUX_IPSR_MSEL(IP1_21_18, VI0_CLKENB, SEL_VI0_0), 896 PINMUX_IPSR_MSEL(IP1_21_18, VI0_CLKENB_B, SEL_VI0_1), 897 PINMUX_IPSR_MSEL(IP1_21_18, VI2_DATA6_VI2_B6, SEL_VI2_0), 898 PINMUX_IPSR_GPSR(IP1_25_22, D15), 899 PINMUX_IPSR_MSEL(IP1_25_22, SCIFB1_TXD_C, SEL_SCIFB1_2), 900 PINMUX_IPSR_GPSR(IP1_25_22, AVB_TXD7), 901 PINMUX_IPSR_MSEL(IP1_25_22, TX1_B, SEL_SCIF1_1), 902 PINMUX_IPSR_MSEL(IP1_25_22, VI0_FIELD, SEL_VI0_0), 903 PINMUX_IPSR_MSEL(IP1_25_22, VI0_FIELD_B, SEL_VI0_1), 904 PINMUX_IPSR_MSEL(IP1_25_22, VI2_DATA7_VI2_B7, SEL_VI2_0), 905 PINMUX_IPSR_GPSR(IP1_27_26, A0), 906 PINMUX_IPSR_GPSR(IP1_27_26, PWM3), 907 PINMUX_IPSR_GPSR(IP1_29_28, A1), 908 PINMUX_IPSR_GPSR(IP1_29_28, PWM4), 909 910 PINMUX_IPSR_GPSR(IP2_2_0, A2), 911 PINMUX_IPSR_GPSR(IP2_2_0, PWM5), 912 PINMUX_IPSR_MSEL(IP2_2_0, MSIOF1_SS1_B, SEL_SOF1_1), 913 PINMUX_IPSR_GPSR(IP2_5_3, A3), 914 PINMUX_IPSR_GPSR(IP2_5_3, PWM6), 915 PINMUX_IPSR_MSEL(IP2_5_3, MSIOF1_SS2_B, SEL_SOF1_1), 916 PINMUX_IPSR_GPSR(IP2_8_6, A4), 917 PINMUX_IPSR_MSEL(IP2_8_6, MSIOF1_TXD_B, SEL_SOF1_1), 918 PINMUX_IPSR_GPSR(IP2_8_6, TPU0TO0), 919 PINMUX_IPSR_GPSR(IP2_11_9, A5), 920 PINMUX_IPSR_MSEL(IP2_11_9, SCIFA1_TXD_B, SEL_SCIFA1_1), 921 PINMUX_IPSR_GPSR(IP2_11_9, TPU0TO1), 922 PINMUX_IPSR_GPSR(IP2_14_12, A6), 923 PINMUX_IPSR_MSEL(IP2_14_12, SCIFA1_RTS_N_B, SEL_SCIFA1_1), 924 PINMUX_IPSR_GPSR(IP2_14_12, TPU0TO2), 925 PINMUX_IPSR_GPSR(IP2_17_15, A7), 926 PINMUX_IPSR_MSEL(IP2_17_15, SCIFA1_SCK_B, SEL_SCIFA1_1), 927 PINMUX_IPSR_GPSR(IP2_17_15, AUDIO_CLKOUT_B), 928 PINMUX_IPSR_GPSR(IP2_17_15, TPU0TO3), 929 PINMUX_IPSR_GPSR(IP2_21_18, A8), 930 PINMUX_IPSR_MSEL(IP2_21_18, SCIFA1_RXD_B, SEL_SCIFA1_1), 931 PINMUX_IPSR_MSEL(IP2_21_18, SSI_SCK5_B, SEL_SSI5_1), 932 PINMUX_IPSR_MSEL(IP2_21_18, VI0_R4, SEL_VI0_0), 933 PINMUX_IPSR_MSEL(IP2_21_18, VI0_R4_B, SEL_VI0_1), 934 PINMUX_IPSR_MSEL(IP2_21_18, SCIFB2_RXD_C, SEL_SCIFB2_2), 935 PINMUX_IPSR_MSEL(IP2_21_18, RX2_B, SEL_SCIF2_1), 936 PINMUX_IPSR_MSEL(IP2_21_18, VI2_DATA0_VI2_B0_B, SEL_VI2_1), 937 PINMUX_IPSR_GPSR(IP2_25_22, A9), 938 PINMUX_IPSR_MSEL(IP2_25_22, SCIFA1_CTS_N_B, SEL_SCIFA1_1), 939 PINMUX_IPSR_MSEL(IP2_25_22, SSI_WS5_B, SEL_SSI5_1), 940 PINMUX_IPSR_MSEL(IP2_25_22, VI0_R5, SEL_VI0_0), 941 PINMUX_IPSR_MSEL(IP2_25_22, VI0_R5_B, SEL_VI0_1), 942 PINMUX_IPSR_MSEL(IP2_25_22, SCIFB2_TXD_C, SEL_SCIFB2_2), 943 PINMUX_IPSR_MSEL(IP2_25_22, TX2_B, SEL_SCIF2_1), 944 PINMUX_IPSR_MSEL(IP2_25_22, VI2_DATA1_VI2_B1_B, SEL_VI2_1), 945 PINMUX_IPSR_GPSR(IP2_28_26, A10), 946 PINMUX_IPSR_MSEL(IP2_28_26, SSI_SDATA5_B, SEL_SSI5_1), 947 PINMUX_IPSR_GPSR(IP2_28_26, MSIOF2_SYNC), 948 PINMUX_IPSR_MSEL(IP2_28_26, VI0_R6, SEL_VI0_0), 949 PINMUX_IPSR_MSEL(IP2_28_26, VI0_R6_B, SEL_VI0_1), 950 PINMUX_IPSR_MSEL(IP2_28_26, VI2_DATA2_VI2_B2_B, SEL_VI2_1), 951 952 PINMUX_IPSR_GPSR(IP3_3_0, A11), 953 PINMUX_IPSR_MSEL(IP3_3_0, SCIFB2_CTS_N_B, SEL_SCIFB2_1), 954 PINMUX_IPSR_GPSR(IP3_3_0, MSIOF2_SCK), 955 PINMUX_IPSR_MSEL(IP3_3_0, VI1_R0, SEL_VI1_0), 956 PINMUX_IPSR_MSEL(IP3_3_0, VI1_R0_B, SEL_VI1_1), 957 PINMUX_IPSR_GPSR(IP3_3_0, VI2_G0), 958 PINMUX_IPSR_MSEL(IP3_3_0, VI2_DATA3_VI2_B3_B, SEL_VI2_1), 959 PINMUX_IPSR_GPSR(IP3_7_4, A12), 960 PINMUX_IPSR_MSEL(IP3_7_4, SCIFB2_RXD_B, SEL_SCIFB2_1), 961 PINMUX_IPSR_GPSR(IP3_7_4, MSIOF2_TXD), 962 PINMUX_IPSR_MSEL(IP3_7_4, VI1_R1, SEL_VI1_0), 963 PINMUX_IPSR_MSEL(IP3_7_4, VI1_R1_B, SEL_VI1_1), 964 PINMUX_IPSR_GPSR(IP3_7_4, VI2_G1), 965 PINMUX_IPSR_MSEL(IP3_7_4, VI2_DATA4_VI2_B4_B, SEL_VI2_1), 966 PINMUX_IPSR_GPSR(IP3_11_8, A13), 967 PINMUX_IPSR_MSEL(IP3_11_8, SCIFB2_RTS_N_B, SEL_SCIFB2_1), 968 PINMUX_IPSR_GPSR(IP3_11_8, EX_WAIT2), 969 PINMUX_IPSR_GPSR(IP3_11_8, MSIOF2_RXD), 970 PINMUX_IPSR_MSEL(IP3_11_8, VI1_R2, SEL_VI1_0), 971 PINMUX_IPSR_MSEL(IP3_11_8, VI1_R2_B, SEL_VI1_1), 972 PINMUX_IPSR_GPSR(IP3_11_8, VI2_G2), 973 PINMUX_IPSR_MSEL(IP3_11_8, VI2_DATA5_VI2_B5_B, SEL_VI2_1), 974 PINMUX_IPSR_GPSR(IP3_14_12, A14), 975 PINMUX_IPSR_MSEL(IP3_14_12, SCIFB2_TXD_B, SEL_SCIFB2_1), 976 PINMUX_IPSR_GPSR(IP3_14_12, ATACS11_N), 977 PINMUX_IPSR_GPSR(IP3_14_12, MSIOF2_SS1), 978 PINMUX_IPSR_GPSR(IP3_17_15, A15), 979 PINMUX_IPSR_MSEL(IP3_17_15, SCIFB2_SCK_B, SEL_SCIFB2_1), 980 PINMUX_IPSR_GPSR(IP3_17_15, ATARD1_N), 981 PINMUX_IPSR_GPSR(IP3_17_15, MSIOF2_SS2), 982 PINMUX_IPSR_GPSR(IP3_19_18, A16), 983 PINMUX_IPSR_GPSR(IP3_19_18, ATAWR1_N), 984 PINMUX_IPSR_GPSR(IP3_22_20, A17), 985 PINMUX_IPSR_MSEL(IP3_22_20, AD_DO_B, SEL_ADI_1), 986 PINMUX_IPSR_GPSR(IP3_22_20, ATADIR1_N), 987 PINMUX_IPSR_GPSR(IP3_25_23, A18), 988 PINMUX_IPSR_MSEL(IP3_25_23, AD_CLK_B, SEL_ADI_1), 989 PINMUX_IPSR_GPSR(IP3_25_23, ATAG1_N), 990 PINMUX_IPSR_GPSR(IP3_28_26, A19), 991 PINMUX_IPSR_MSEL(IP3_28_26, AD_NCS_N_B, SEL_ADI_1), 992 PINMUX_IPSR_GPSR(IP3_28_26, ATACS01_N), 993 PINMUX_IPSR_MSEL(IP3_28_26, EX_WAIT0_B, SEL_LBS_1), 994 PINMUX_IPSR_GPSR(IP3_31_29, A20), 995 PINMUX_IPSR_GPSR(IP3_31_29, SPCLK), 996 PINMUX_IPSR_MSEL(IP3_31_29, VI1_R3, SEL_VI1_0), 997 PINMUX_IPSR_MSEL(IP3_31_29, VI1_R3_B, SEL_VI1_1), 998 PINMUX_IPSR_GPSR(IP3_31_29, VI2_G4), 999 1000 PINMUX_IPSR_GPSR(IP4_2_0, A21), 1001 PINMUX_IPSR_GPSR(IP4_2_0, MOSI_IO0), 1002 PINMUX_IPSR_MSEL(IP4_2_0, VI1_R4, SEL_VI1_0), 1003 PINMUX_IPSR_MSEL(IP4_2_0, VI1_R4_B, SEL_VI1_1), 1004 PINMUX_IPSR_GPSR(IP4_2_0, VI2_G5), 1005 PINMUX_IPSR_GPSR(IP4_5_3, A22), 1006 PINMUX_IPSR_GPSR(IP4_5_3, MISO_IO1), 1007 PINMUX_IPSR_MSEL(IP4_5_3, VI1_R5, SEL_VI1_0), 1008 PINMUX_IPSR_MSEL(IP4_5_3, VI1_R5_B, SEL_VI1_1), 1009 PINMUX_IPSR_GPSR(IP4_5_3, VI2_G6), 1010 PINMUX_IPSR_GPSR(IP4_8_6, A23), 1011 PINMUX_IPSR_GPSR(IP4_8_6, IO2), 1012 PINMUX_IPSR_MSEL(IP4_8_6, VI1_G7, SEL_VI1_0), 1013 PINMUX_IPSR_MSEL(IP4_8_6, VI1_G7_B, SEL_VI1_1), 1014 PINMUX_IPSR_GPSR(IP4_8_6, VI2_G7), 1015 PINMUX_IPSR_GPSR(IP4_11_9, A24), 1016 PINMUX_IPSR_GPSR(IP4_11_9, IO3), 1017 PINMUX_IPSR_MSEL(IP4_11_9, VI1_R7, SEL_VI1_0), 1018 PINMUX_IPSR_MSEL(IP4_11_9, VI1_R7_B, SEL_VI1_1), 1019 PINMUX_IPSR_MSEL(IP4_11_9, VI2_CLKENB, SEL_VI2_0), 1020 PINMUX_IPSR_MSEL(IP4_11_9, VI2_CLKENB_B, SEL_VI2_1), 1021 PINMUX_IPSR_GPSR(IP4_14_12, A25), 1022 PINMUX_IPSR_GPSR(IP4_14_12, SSL), 1023 PINMUX_IPSR_MSEL(IP4_14_12, VI1_G6, SEL_VI1_0), 1024 PINMUX_IPSR_MSEL(IP4_14_12, VI1_G6_B, SEL_VI1_1), 1025 PINMUX_IPSR_MSEL(IP4_14_12, VI2_FIELD, SEL_VI2_0), 1026 PINMUX_IPSR_MSEL(IP4_14_12, VI2_FIELD_B, SEL_VI2_1), 1027 PINMUX_IPSR_GPSR(IP4_17_15, CS0_N), 1028 PINMUX_IPSR_MSEL(IP4_17_15, VI1_R6, SEL_VI1_0), 1029 PINMUX_IPSR_MSEL(IP4_17_15, VI1_R6_B, SEL_VI1_1), 1030 PINMUX_IPSR_GPSR(IP4_17_15, VI2_G3), 1031 PINMUX_IPSR_MSEL(IP4_17_15, MSIOF0_SS2_B, SEL_SOF0_1), 1032 PINMUX_IPSR_GPSR(IP4_20_18, CS1_N_A26), 1033 PINMUX_IPSR_GPSR(IP4_20_18, SPEEDIN), 1034 PINMUX_IPSR_MSEL(IP4_20_18, VI0_R7, SEL_VI0_0), 1035 PINMUX_IPSR_MSEL(IP4_20_18, VI0_R7_B, SEL_VI0_1), 1036 PINMUX_IPSR_MSEL(IP4_20_18, VI2_CLK, SEL_VI2_0), 1037 PINMUX_IPSR_MSEL(IP4_20_18, VI2_CLK_B, SEL_VI2_1), 1038 PINMUX_IPSR_GPSR(IP4_23_21, EX_CS0_N), 1039 PINMUX_IPSR_MSEL(IP4_23_21, HRX1_B, SEL_HSCIF1_1), 1040 PINMUX_IPSR_MSEL(IP4_23_21, VI1_G5, SEL_VI1_0), 1041 PINMUX_IPSR_MSEL(IP4_23_21, VI1_G5_B, SEL_VI1_1), 1042 PINMUX_IPSR_GPSR(IP4_23_21, VI2_R0), 1043 PINMUX_IPSR_MSEL(IP4_23_21, HTX0_B, SEL_HSCIF0_1), 1044 PINMUX_IPSR_MSEL(IP4_23_21, MSIOF0_SS1_B, SEL_SOF0_1), 1045 PINMUX_IPSR_GPSR(IP4_26_24, EX_CS1_N), 1046 PINMUX_IPSR_GPSR(IP4_26_24, GPS_CLK), 1047 PINMUX_IPSR_MSEL(IP4_26_24, HCTS1_N_B, SEL_HSCIF1_1), 1048 PINMUX_IPSR_MSEL(IP4_26_24, VI1_FIELD, SEL_VI1_0), 1049 PINMUX_IPSR_MSEL(IP4_26_24, VI1_FIELD_B, SEL_VI1_1), 1050 PINMUX_IPSR_GPSR(IP4_26_24, VI2_R1), 1051 PINMUX_IPSR_GPSR(IP4_29_27, EX_CS2_N), 1052 PINMUX_IPSR_GPSR(IP4_29_27, GPS_SIGN), 1053 PINMUX_IPSR_MSEL(IP4_29_27, HRTS1_N_B, SEL_HSCIF1_1), 1054 PINMUX_IPSR_GPSR(IP4_29_27, VI3_CLKENB), 1055 PINMUX_IPSR_MSEL(IP4_29_27, VI1_G0, SEL_VI1_0), 1056 PINMUX_IPSR_MSEL(IP4_29_27, VI1_G0_B, SEL_VI1_1), 1057 PINMUX_IPSR_GPSR(IP4_29_27, VI2_R2), 1058 1059 PINMUX_IPSR_GPSR(IP5_2_0, EX_CS3_N), 1060 PINMUX_IPSR_GPSR(IP5_2_0, GPS_MAG), 1061 PINMUX_IPSR_GPSR(IP5_2_0, VI3_FIELD), 1062 PINMUX_IPSR_MSEL(IP5_2_0, VI1_G1, SEL_VI1_0), 1063 PINMUX_IPSR_MSEL(IP5_2_0, VI1_G1_B, SEL_VI1_1), 1064 PINMUX_IPSR_GPSR(IP5_2_0, VI2_R3), 1065 PINMUX_IPSR_GPSR(IP5_5_3, EX_CS4_N), 1066 PINMUX_IPSR_MSEL(IP5_5_3, MSIOF1_SCK_B, SEL_SOF1_1), 1067 PINMUX_IPSR_GPSR(IP5_5_3, VI3_HSYNC_N), 1068 PINMUX_IPSR_MSEL(IP5_5_3, VI2_HSYNC_N, SEL_VI2_0), 1069 PINMUX_IPSR_MSEL(IP5_5_3, IIC1_SCL, SEL_IIC1_0), 1070 PINMUX_IPSR_MSEL(IP5_5_3, VI2_HSYNC_N_B, SEL_VI2_1), 1071 PINMUX_IPSR_GPSR(IP5_5_3, INTC_EN0_N), 1072 PINMUX_IPSR_MSEL(IP5_5_3, I2C1_SCL, SEL_I2C1_0), 1073 PINMUX_IPSR_GPSR(IP5_9_6, EX_CS5_N), 1074 PINMUX_IPSR_MSEL(IP5_9_6, CAN0_RX, SEL_CAN0_0), 1075 PINMUX_IPSR_MSEL(IP5_9_6, MSIOF1_RXD_B, SEL_SOF1_1), 1076 PINMUX_IPSR_GPSR(IP5_9_6, VI3_VSYNC_N), 1077 PINMUX_IPSR_MSEL(IP5_9_6, VI1_G2, SEL_VI1_0), 1078 PINMUX_IPSR_MSEL(IP5_9_6, VI1_G2_B, SEL_VI1_1), 1079 PINMUX_IPSR_GPSR(IP5_9_6, VI2_R4), 1080 PINMUX_IPSR_MSEL(IP5_9_6, IIC1_SDA, SEL_IIC1_0), 1081 PINMUX_IPSR_GPSR(IP5_9_6, INTC_EN1_N), 1082 PINMUX_IPSR_MSEL(IP5_9_6, I2C1_SDA, SEL_I2C1_0), 1083 PINMUX_IPSR_GPSR(IP5_12_10, BS_N), 1084 PINMUX_IPSR_MSEL(IP5_12_10, IETX, SEL_IEB_0), 1085 PINMUX_IPSR_MSEL(IP5_12_10, HTX1_B, SEL_HSCIF1_1), 1086 PINMUX_IPSR_MSEL(IP5_12_10, CAN1_TX, SEL_CAN1_0), 1087 PINMUX_IPSR_GPSR(IP5_12_10, DRACK0), 1088 PINMUX_IPSR_MSEL(IP5_12_10, IETX_C, SEL_IEB_2), 1089 PINMUX_IPSR_GPSR(IP5_14_13, RD_N), 1090 PINMUX_IPSR_MSEL(IP5_14_13, CAN0_TX, SEL_CAN0_0), 1091 PINMUX_IPSR_MSEL(IP5_14_13, SCIFA0_SCK_B, SEL_SCFA_1), 1092 PINMUX_IPSR_GPSR(IP5_17_15, RD_WR_N), 1093 PINMUX_IPSR_MSEL(IP5_17_15, VI1_G3, SEL_VI1_0), 1094 PINMUX_IPSR_MSEL(IP5_17_15, VI1_G3_B, SEL_VI1_1), 1095 PINMUX_IPSR_GPSR(IP5_17_15, VI2_R5), 1096 PINMUX_IPSR_MSEL(IP5_17_15, SCIFA0_RXD_B, SEL_SCFA_1), 1097 PINMUX_IPSR_GPSR(IP5_17_15, INTC_IRQ4_N), 1098 PINMUX_IPSR_GPSR(IP5_20_18, WE0_N), 1099 PINMUX_IPSR_MSEL(IP5_20_18, IECLK, SEL_IEB_0), 1100 PINMUX_IPSR_MSEL(IP5_20_18, CAN_CLK, SEL_CANCLK_0), 1101 PINMUX_IPSR_MSEL(IP5_20_18, VI2_VSYNC_N, SEL_VI2_0), 1102 PINMUX_IPSR_MSEL(IP5_20_18, SCIFA0_TXD_B, SEL_SCFA_1), 1103 PINMUX_IPSR_MSEL(IP5_20_18, VI2_VSYNC_N_B, SEL_VI2_1), 1104 PINMUX_IPSR_GPSR(IP5_23_21, WE1_N), 1105 PINMUX_IPSR_MSEL(IP5_23_21, IERX, SEL_IEB_0), 1106 PINMUX_IPSR_MSEL(IP5_23_21, CAN1_RX, SEL_CAN1_0), 1107 PINMUX_IPSR_MSEL(IP5_23_21, VI1_G4, SEL_VI1_0), 1108 PINMUX_IPSR_MSEL(IP5_23_21, VI1_G4_B, SEL_VI1_1), 1109 PINMUX_IPSR_GPSR(IP5_23_21, VI2_R6), 1110 PINMUX_IPSR_MSEL(IP5_23_21, SCIFA0_CTS_N_B, SEL_SCFA_1), 1111 PINMUX_IPSR_MSEL(IP5_23_21, IERX_C, SEL_IEB_2), 1112 PINMUX_IPSR_MSEL(IP5_26_24, EX_WAIT0, SEL_LBS_0), 1113 PINMUX_IPSR_GPSR(IP5_26_24, IRQ3), 1114 PINMUX_IPSR_GPSR(IP5_26_24, INTC_IRQ3_N), 1115 PINMUX_IPSR_MSEL(IP5_26_24, VI3_CLK, SEL_VI3_0), 1116 PINMUX_IPSR_MSEL(IP5_26_24, SCIFA0_RTS_N_B, SEL_SCFA_1), 1117 PINMUX_IPSR_MSEL(IP5_26_24, HRX0_B, SEL_HSCIF0_1), 1118 PINMUX_IPSR_MSEL(IP5_26_24, MSIOF0_SCK_B, SEL_SOF0_1), 1119 PINMUX_IPSR_GPSR(IP5_29_27, DREQ0_N), 1120 PINMUX_IPSR_MSEL(IP5_29_27, VI1_HSYNC_N, SEL_VI1_0), 1121 PINMUX_IPSR_MSEL(IP5_29_27, VI1_HSYNC_N_B, SEL_VI1_1), 1122 PINMUX_IPSR_GPSR(IP5_29_27, VI2_R7), 1123 PINMUX_IPSR_MSEL(IP5_29_27, SSI_SCK78_C, SEL_SSI7_2), 1124 PINMUX_IPSR_MSEL(IP5_29_27, SSI_WS78_B, SEL_SSI7_1), 1125 1126 PINMUX_IPSR_GPSR(IP6_2_0, DACK0), 1127 PINMUX_IPSR_GPSR(IP6_2_0, IRQ0), 1128 PINMUX_IPSR_GPSR(IP6_2_0, INTC_IRQ0_N), 1129 PINMUX_IPSR_MSEL(IP6_2_0, SSI_SCK6_B, SEL_SSI6_1), 1130 PINMUX_IPSR_MSEL(IP6_2_0, VI1_VSYNC_N, SEL_VI1_0), 1131 PINMUX_IPSR_MSEL(IP6_2_0, VI1_VSYNC_N_B, SEL_VI1_1), 1132 PINMUX_IPSR_MSEL(IP6_2_0, SSI_WS78_C, SEL_SSI7_2), 1133 PINMUX_IPSR_GPSR(IP6_5_3, DREQ1_N), 1134 PINMUX_IPSR_MSEL(IP6_5_3, VI1_CLKENB, SEL_VI1_0), 1135 PINMUX_IPSR_MSEL(IP6_5_3, VI1_CLKENB_B, SEL_VI1_1), 1136 PINMUX_IPSR_MSEL(IP6_5_3, SSI_SDATA7_C, SEL_SSI7_2), 1137 PINMUX_IPSR_MSEL(IP6_5_3, SSI_SCK78_B, SEL_SSI7_1), 1138 PINMUX_IPSR_GPSR(IP6_8_6, DACK1), 1139 PINMUX_IPSR_GPSR(IP6_8_6, IRQ1), 1140 PINMUX_IPSR_GPSR(IP6_8_6, INTC_IRQ1_N), 1141 PINMUX_IPSR_MSEL(IP6_8_6, SSI_WS6_B, SEL_SSI6_1), 1142 PINMUX_IPSR_MSEL(IP6_8_6, SSI_SDATA8_C, SEL_SSI8_2), 1143 PINMUX_IPSR_GPSR(IP6_10_9, DREQ2_N), 1144 PINMUX_IPSR_MSEL(IP6_10_9, HSCK1_B, SEL_HSCIF1_1), 1145 PINMUX_IPSR_MSEL(IP6_10_9, HCTS0_N_B, SEL_HSCIF0_1), 1146 PINMUX_IPSR_MSEL(IP6_10_9, MSIOF0_TXD_B, SEL_SOF0_1), 1147 PINMUX_IPSR_GPSR(IP6_13_11, DACK2), 1148 PINMUX_IPSR_GPSR(IP6_13_11, IRQ2), 1149 PINMUX_IPSR_GPSR(IP6_13_11, INTC_IRQ2_N), 1150 PINMUX_IPSR_MSEL(IP6_13_11, SSI_SDATA6_B, SEL_SSI6_1), 1151 PINMUX_IPSR_MSEL(IP6_13_11, HRTS0_N_B, SEL_HSCIF0_1), 1152 PINMUX_IPSR_MSEL(IP6_13_11, MSIOF0_RXD_B, SEL_SOF0_1), 1153 PINMUX_IPSR_GPSR(IP6_16_14, ETH_CRS_DV), 1154 PINMUX_IPSR_MSEL(IP6_16_14, STP_ISCLK_0_B, SEL_SSP_1), 1155 PINMUX_IPSR_MSEL(IP6_16_14, TS_SDEN0_D, SEL_TSIF0_3), 1156 PINMUX_IPSR_MSEL(IP6_16_14, GLO_Q0_C, SEL_GPS_2), 1157 PINMUX_IPSR_MSEL(IP6_16_14, IIC2_SCL_E, SEL_IIC2_4), 1158 PINMUX_IPSR_MSEL(IP6_16_14, I2C2_SCL_E, SEL_I2C2_4), 1159 PINMUX_IPSR_GPSR(IP6_19_17, ETH_RX_ER), 1160 PINMUX_IPSR_MSEL(IP6_19_17, STP_ISD_0_B, SEL_SSP_1), 1161 PINMUX_IPSR_MSEL(IP6_19_17, TS_SPSYNC0_D, SEL_TSIF0_3), 1162 PINMUX_IPSR_MSEL(IP6_19_17, GLO_Q1_C, SEL_GPS_2), 1163 PINMUX_IPSR_MSEL(IP6_19_17, IIC2_SDA_E, SEL_IIC2_4), 1164 PINMUX_IPSR_MSEL(IP6_19_17, I2C2_SDA_E, SEL_I2C2_4), 1165 PINMUX_IPSR_GPSR(IP6_22_20, ETH_RXD0), 1166 PINMUX_IPSR_MSEL(IP6_22_20, STP_ISEN_0_B, SEL_SSP_1), 1167 PINMUX_IPSR_MSEL(IP6_22_20, TS_SDAT0_D, SEL_TSIF0_3), 1168 PINMUX_IPSR_MSEL(IP6_22_20, GLO_I0_C, SEL_GPS_2), 1169 PINMUX_IPSR_MSEL(IP6_22_20, SCIFB1_SCK_G, SEL_SCIFB1_6), 1170 PINMUX_IPSR_MSEL(IP6_22_20, SCK1_E, SEL_SCIF1_4), 1171 PINMUX_IPSR_GPSR(IP6_25_23, ETH_RXD1), 1172 PINMUX_IPSR_MSEL(IP6_25_23, HRX0_E, SEL_HSCIF0_4), 1173 PINMUX_IPSR_MSEL(IP6_25_23, STP_ISSYNC_0_B, SEL_SSP_1), 1174 PINMUX_IPSR_MSEL(IP6_25_23, TS_SCK0_D, SEL_TSIF0_3), 1175 PINMUX_IPSR_MSEL(IP6_25_23, GLO_I1_C, SEL_GPS_2), 1176 PINMUX_IPSR_MSEL(IP6_25_23, SCIFB1_RXD_G, SEL_SCIFB1_6), 1177 PINMUX_IPSR_MSEL(IP6_25_23, RX1_E, SEL_SCIF1_4), 1178 PINMUX_IPSR_GPSR(IP6_28_26, ETH_LINK), 1179 PINMUX_IPSR_MSEL(IP6_28_26, HTX0_E, SEL_HSCIF0_4), 1180 PINMUX_IPSR_MSEL(IP6_28_26, STP_IVCXO27_0_B, SEL_SSP_1), 1181 PINMUX_IPSR_MSEL(IP6_28_26, SCIFB1_TXD_G, SEL_SCIFB1_6), 1182 PINMUX_IPSR_MSEL(IP6_28_26, TX1_E, SEL_SCIF1_4), 1183 PINMUX_IPSR_GPSR(IP6_31_29, ETH_REF_CLK), 1184 PINMUX_IPSR_MSEL(IP6_31_29, HCTS0_N_E, SEL_HSCIF0_4), 1185 PINMUX_IPSR_MSEL(IP6_31_29, STP_IVCXO27_1_B, SEL_SSP_1), 1186 PINMUX_IPSR_MSEL(IP6_31_29, HRX0_F, SEL_HSCIF0_5), 1187 1188 PINMUX_IPSR_GPSR(IP7_2_0, ETH_MDIO), 1189 PINMUX_IPSR_MSEL(IP7_2_0, HRTS0_N_E, SEL_HSCIF0_4), 1190 PINMUX_IPSR_MSEL(IP7_2_0, SIM0_D_C, SEL_SIM_2), 1191 PINMUX_IPSR_MSEL(IP7_2_0, HCTS0_N_F, SEL_HSCIF0_5), 1192 PINMUX_IPSR_GPSR(IP7_5_3, ETH_TXD1), 1193 PINMUX_IPSR_MSEL(IP7_5_3, HTX0_F, SEL_HSCIF0_5), 1194 PINMUX_IPSR_MSEL(IP7_5_3, BPFCLK_G, SEL_FM_6), 1195 PINMUX_IPSR_GPSR(IP7_7_6, ETH_TX_EN), 1196 PINMUX_IPSR_MSEL(IP7_7_6, SIM0_CLK_C, SEL_SIM_2), 1197 PINMUX_IPSR_MSEL(IP7_7_6, HRTS0_N_F, SEL_HSCIF0_5), 1198 PINMUX_IPSR_GPSR(IP7_9_8, ETH_MAGIC), 1199 PINMUX_IPSR_MSEL(IP7_9_8, SIM0_RST_C, SEL_SIM_2), 1200 PINMUX_IPSR_GPSR(IP7_12_10, ETH_TXD0), 1201 PINMUX_IPSR_MSEL(IP7_12_10, STP_ISCLK_1_B, SEL_SSP_1), 1202 PINMUX_IPSR_MSEL(IP7_12_10, TS_SDEN1_C, SEL_TSIF1_2), 1203 PINMUX_IPSR_MSEL(IP7_12_10, GLO_SCLK_C, SEL_GPS_2), 1204 PINMUX_IPSR_GPSR(IP7_15_13, ETH_MDC), 1205 PINMUX_IPSR_MSEL(IP7_15_13, STP_ISD_1_B, SEL_SSP_1), 1206 PINMUX_IPSR_MSEL(IP7_15_13, TS_SPSYNC1_C, SEL_TSIF1_2), 1207 PINMUX_IPSR_MSEL(IP7_15_13, GLO_SDATA_C, SEL_GPS_2), 1208 PINMUX_IPSR_GPSR(IP7_18_16, PWM0), 1209 PINMUX_IPSR_MSEL(IP7_18_16, SCIFA2_SCK_C, SEL_SCIFA2_2), 1210 PINMUX_IPSR_MSEL(IP7_18_16, STP_ISEN_1_B, SEL_SSP_1), 1211 PINMUX_IPSR_MSEL(IP7_18_16, TS_SDAT1_C, SEL_TSIF1_2), 1212 PINMUX_IPSR_MSEL(IP7_18_16, GLO_SS_C, SEL_GPS_2), 1213 PINMUX_IPSR_GPSR(IP7_21_19, PWM1), 1214 PINMUX_IPSR_MSEL(IP7_21_19, SCIFA2_TXD_C, SEL_SCIFA2_2), 1215 PINMUX_IPSR_MSEL(IP7_21_19, STP_ISSYNC_1_B, SEL_SSP_1), 1216 PINMUX_IPSR_MSEL(IP7_21_19, TS_SCK1_C, SEL_TSIF1_2), 1217 PINMUX_IPSR_MSEL(IP7_21_19, GLO_RFON_C, SEL_GPS_2), 1218 PINMUX_IPSR_GPSR(IP7_21_19, PCMOE_N), 1219 PINMUX_IPSR_GPSR(IP7_24_22, PWM2), 1220 PINMUX_IPSR_GPSR(IP7_24_22, PWMFSW0), 1221 PINMUX_IPSR_MSEL(IP7_24_22, SCIFA2_RXD_C, SEL_SCIFA2_2), 1222 PINMUX_IPSR_GPSR(IP7_24_22, PCMWE_N), 1223 PINMUX_IPSR_MSEL(IP7_24_22, IECLK_C, SEL_IEB_2), 1224 PINMUX_IPSR_GPSR(IP7_26_25, DU_DOTCLKIN1), 1225 PINMUX_IPSR_GPSR(IP7_26_25, AUDIO_CLKC), 1226 PINMUX_IPSR_GPSR(IP7_26_25, AUDIO_CLKOUT_C), 1227 PINMUX_IPSR_MSEL(IP7_28_27, VI0_CLK, SEL_VI0_0), 1228 PINMUX_IPSR_GPSR(IP7_28_27, ATACS00_N), 1229 PINMUX_IPSR_GPSR(IP7_28_27, AVB_RXD1), 1230 PINMUX_IPSR_MSEL(IP7_30_29, VI0_DATA0_VI0_B0, SEL_VI0_0), 1231 PINMUX_IPSR_GPSR(IP7_30_29, ATACS10_N), 1232 PINMUX_IPSR_GPSR(IP7_30_29, AVB_RXD2), 1233 1234 PINMUX_IPSR_MSEL(IP8_1_0, VI0_DATA1_VI0_B1, SEL_VI0_0), 1235 PINMUX_IPSR_GPSR(IP8_1_0, ATARD0_N), 1236 PINMUX_IPSR_GPSR(IP8_1_0, AVB_RXD3), 1237 PINMUX_IPSR_MSEL(IP8_3_2, VI0_DATA2_VI0_B2, SEL_VI0_0), 1238 PINMUX_IPSR_GPSR(IP8_3_2, ATAWR0_N), 1239 PINMUX_IPSR_GPSR(IP8_3_2, AVB_RXD4), 1240 PINMUX_IPSR_MSEL(IP8_5_4, VI0_DATA3_VI0_B3, SEL_VI0_0), 1241 PINMUX_IPSR_GPSR(IP8_5_4, ATADIR0_N), 1242 PINMUX_IPSR_GPSR(IP8_5_4, AVB_RXD5), 1243 PINMUX_IPSR_MSEL(IP8_7_6, VI0_DATA4_VI0_B4, SEL_VI0_0), 1244 PINMUX_IPSR_GPSR(IP8_7_6, ATAG0_N), 1245 PINMUX_IPSR_GPSR(IP8_7_6, AVB_RXD6), 1246 PINMUX_IPSR_MSEL(IP8_9_8, VI0_DATA5_VI0_B5, SEL_VI0_0), 1247 PINMUX_IPSR_GPSR(IP8_9_8, EX_WAIT1), 1248 PINMUX_IPSR_GPSR(IP8_9_8, AVB_RXD7), 1249 PINMUX_IPSR_MSEL(IP8_11_10, VI0_DATA6_VI0_B6, SEL_VI0_0), 1250 PINMUX_IPSR_GPSR(IP8_11_10, AVB_RX_ER), 1251 PINMUX_IPSR_MSEL(IP8_13_12, VI0_DATA7_VI0_B7, SEL_VI0_0), 1252 PINMUX_IPSR_GPSR(IP8_13_12, AVB_RX_CLK), 1253 PINMUX_IPSR_MSEL(IP8_15_14, VI1_CLK, SEL_VI1_0), 1254 PINMUX_IPSR_GPSR(IP8_15_14, AVB_RX_DV), 1255 PINMUX_IPSR_MSEL(IP8_17_16, VI1_DATA0_VI1_B0, SEL_VI1_0), 1256 PINMUX_IPSR_MSEL(IP8_17_16, SCIFA1_SCK_D, SEL_SCIFA1_3), 1257 PINMUX_IPSR_GPSR(IP8_17_16, AVB_CRS), 1258 PINMUX_IPSR_MSEL(IP8_19_18, VI1_DATA1_VI1_B1, SEL_VI1_0), 1259 PINMUX_IPSR_MSEL(IP8_19_18, SCIFA1_RXD_D, SEL_SCIFA1_3), 1260 PINMUX_IPSR_GPSR(IP8_19_18, AVB_MDC), 1261 PINMUX_IPSR_MSEL(IP8_21_20, VI1_DATA2_VI1_B2, SEL_VI1_0), 1262 PINMUX_IPSR_MSEL(IP8_21_20, SCIFA1_TXD_D, SEL_SCIFA1_3), 1263 PINMUX_IPSR_GPSR(IP8_21_20, AVB_MDIO), 1264 PINMUX_IPSR_MSEL(IP8_23_22, VI1_DATA3_VI1_B3, SEL_VI1_0), 1265 PINMUX_IPSR_MSEL(IP8_23_22, SCIFA1_CTS_N_D, SEL_SCIFA1_3), 1266 PINMUX_IPSR_GPSR(IP8_23_22, AVB_GTX_CLK), 1267 PINMUX_IPSR_MSEL(IP8_25_24, VI1_DATA4_VI1_B4, SEL_VI1_0), 1268 PINMUX_IPSR_MSEL(IP8_25_24, SCIFA1_RTS_N_D, SEL_SCIFA1_3), 1269 PINMUX_IPSR_GPSR(IP8_25_24, AVB_MAGIC), 1270 PINMUX_IPSR_MSEL(IP8_26, VI1_DATA5_VI1_B5, SEL_VI1_0), 1271 PINMUX_IPSR_GPSR(IP8_26, AVB_PHY_INT), 1272 PINMUX_IPSR_MSEL(IP8_27, VI1_DATA6_VI1_B6, SEL_VI1_0), 1273 PINMUX_IPSR_GPSR(IP8_27, AVB_GTXREFCLK), 1274 PINMUX_IPSR_GPSR(IP8_28, SD0_CLK), 1275 PINMUX_IPSR_MSEL(IP8_28, VI1_DATA0_VI1_B0_B, SEL_VI1_1), 1276 PINMUX_IPSR_GPSR(IP8_30_29, SD0_CMD), 1277 PINMUX_IPSR_MSEL(IP8_30_29, SCIFB1_SCK_B, SEL_SCIFB1_1), 1278 PINMUX_IPSR_MSEL(IP8_30_29, VI1_DATA1_VI1_B1_B, SEL_VI1_1), 1279 1280 PINMUX_IPSR_GPSR(IP9_1_0, SD0_DAT0), 1281 PINMUX_IPSR_MSEL(IP9_1_0, SCIFB1_RXD_B, SEL_SCIFB1_1), 1282 PINMUX_IPSR_MSEL(IP9_1_0, VI1_DATA2_VI1_B2_B, SEL_VI1_1), 1283 PINMUX_IPSR_GPSR(IP9_3_2, SD0_DAT1), 1284 PINMUX_IPSR_MSEL(IP9_3_2, SCIFB1_TXD_B, SEL_SCIFB1_1), 1285 PINMUX_IPSR_MSEL(IP9_3_2, VI1_DATA3_VI1_B3_B, SEL_VI1_1), 1286 PINMUX_IPSR_GPSR(IP9_5_4, SD0_DAT2), 1287 PINMUX_IPSR_MSEL(IP9_5_4, SCIFB1_CTS_N_B, SEL_SCIFB1_1), 1288 PINMUX_IPSR_MSEL(IP9_5_4, VI1_DATA4_VI1_B4_B, SEL_VI1_1), 1289 PINMUX_IPSR_GPSR(IP9_7_6, SD0_DAT3), 1290 PINMUX_IPSR_MSEL(IP9_7_6, SCIFB1_RTS_N_B, SEL_SCIFB1_1), 1291 PINMUX_IPSR_MSEL(IP9_7_6, VI1_DATA5_VI1_B5_B, SEL_VI1_1), 1292 PINMUX_IPSR_GPSR(IP9_11_8, SD0_CD), 1293 PINMUX_IPSR_GPSR(IP9_11_8, MMC0_D6), 1294 PINMUX_IPSR_MSEL(IP9_11_8, TS_SDEN0_B, SEL_TSIF0_1), 1295 PINMUX_IPSR_GPSR(IP9_11_8, USB0_EXTP), 1296 PINMUX_IPSR_MSEL(IP9_11_8, GLO_SCLK, SEL_GPS_0), 1297 PINMUX_IPSR_MSEL(IP9_11_8, VI1_DATA6_VI1_B6_B, SEL_VI1_1), 1298 PINMUX_IPSR_MSEL(IP9_11_8, IIC1_SCL_B, SEL_IIC1_1), 1299 PINMUX_IPSR_MSEL(IP9_11_8, I2C1_SCL_B, SEL_I2C1_1), 1300 PINMUX_IPSR_MSEL(IP9_11_8, VI2_DATA6_VI2_B6_B, SEL_VI2_1), 1301 PINMUX_IPSR_GPSR(IP9_15_12, SD0_WP), 1302 PINMUX_IPSR_GPSR(IP9_15_12, MMC0_D7), 1303 PINMUX_IPSR_MSEL(IP9_15_12, TS_SPSYNC0_B, SEL_TSIF0_1), 1304 PINMUX_IPSR_GPSR(IP9_15_12, USB0_IDIN), 1305 PINMUX_IPSR_MSEL(IP9_15_12, GLO_SDATA, SEL_GPS_0), 1306 PINMUX_IPSR_MSEL(IP9_15_12, VI1_DATA7_VI1_B7_B, SEL_VI1_1), 1307 PINMUX_IPSR_MSEL(IP9_15_12, IIC1_SDA_B, SEL_IIC1_1), 1308 PINMUX_IPSR_MSEL(IP9_15_12, I2C1_SDA_B, SEL_I2C1_1), 1309 PINMUX_IPSR_MSEL(IP9_15_12, VI2_DATA7_VI2_B7_B, SEL_VI2_1), 1310 PINMUX_IPSR_GPSR(IP9_17_16, SD1_CLK), 1311 PINMUX_IPSR_GPSR(IP9_17_16, AVB_TX_EN), 1312 PINMUX_IPSR_GPSR(IP9_19_18, SD1_CMD), 1313 PINMUX_IPSR_GPSR(IP9_19_18, AVB_TX_ER), 1314 PINMUX_IPSR_MSEL(IP9_19_18, SCIFB0_SCK_B, SEL_SCIFB_1), 1315 PINMUX_IPSR_GPSR(IP9_21_20, SD1_DAT0), 1316 PINMUX_IPSR_GPSR(IP9_21_20, AVB_TX_CLK), 1317 PINMUX_IPSR_MSEL(IP9_21_20, SCIFB0_RXD_B, SEL_SCIFB_1), 1318 PINMUX_IPSR_GPSR(IP9_23_22, SD1_DAT1), 1319 PINMUX_IPSR_GPSR(IP9_23_22, AVB_LINK), 1320 PINMUX_IPSR_MSEL(IP9_23_22, SCIFB0_TXD_B, SEL_SCIFB_1), 1321 PINMUX_IPSR_GPSR(IP9_25_24, SD1_DAT2), 1322 PINMUX_IPSR_GPSR(IP9_25_24, AVB_COL), 1323 PINMUX_IPSR_MSEL(IP9_25_24, SCIFB0_CTS_N_B, SEL_SCIFB_1), 1324 PINMUX_IPSR_GPSR(IP9_27_26, SD1_DAT3), 1325 PINMUX_IPSR_GPSR(IP9_27_26, AVB_RXD0), 1326 PINMUX_IPSR_MSEL(IP9_27_26, SCIFB0_RTS_N_B, SEL_SCIFB_1), 1327 PINMUX_IPSR_GPSR(IP9_31_28, SD1_CD), 1328 PINMUX_IPSR_GPSR(IP9_31_28, MMC1_D6), 1329 PINMUX_IPSR_MSEL(IP9_31_28, TS_SDEN1, SEL_TSIF1_0), 1330 PINMUX_IPSR_GPSR(IP9_31_28, USB1_EXTP), 1331 PINMUX_IPSR_MSEL(IP9_31_28, GLO_SS, SEL_GPS_0), 1332 PINMUX_IPSR_MSEL(IP9_31_28, VI0_CLK_B, SEL_VI0_1), 1333 PINMUX_IPSR_MSEL(IP9_31_28, IIC2_SCL_D, SEL_IIC2_3), 1334 PINMUX_IPSR_MSEL(IP9_31_28, I2C2_SCL_D, SEL_I2C2_3), 1335 PINMUX_IPSR_MSEL(IP9_31_28, SIM0_CLK_B, SEL_SIM_1), 1336 PINMUX_IPSR_MSEL(IP9_31_28, VI3_CLK_B, SEL_VI3_1), 1337 1338 PINMUX_IPSR_GPSR(IP10_3_0, SD1_WP), 1339 PINMUX_IPSR_GPSR(IP10_3_0, MMC1_D7), 1340 PINMUX_IPSR_MSEL(IP10_3_0, TS_SPSYNC1, SEL_TSIF1_0), 1341 PINMUX_IPSR_GPSR(IP10_3_0, USB1_IDIN), 1342 PINMUX_IPSR_MSEL(IP10_3_0, GLO_RFON, SEL_GPS_0), 1343 PINMUX_IPSR_MSEL(IP10_3_0, VI1_CLK_B, SEL_VI1_1), 1344 PINMUX_IPSR_MSEL(IP10_3_0, IIC2_SDA_D, SEL_IIC2_3), 1345 PINMUX_IPSR_MSEL(IP10_3_0, I2C2_SDA_D, SEL_I2C2_3), 1346 PINMUX_IPSR_MSEL(IP10_3_0, SIM0_D_B, SEL_SIM_1), 1347 PINMUX_IPSR_GPSR(IP10_6_4, SD2_CLK), 1348 PINMUX_IPSR_GPSR(IP10_6_4, MMC0_CLK), 1349 PINMUX_IPSR_MSEL(IP10_6_4, SIM0_CLK, SEL_SIM_0), 1350 PINMUX_IPSR_MSEL(IP10_6_4, VI0_DATA0_VI0_B0_B, SEL_VI0_1), 1351 PINMUX_IPSR_MSEL(IP10_6_4, TS_SDEN0_C, SEL_TSIF0_2), 1352 PINMUX_IPSR_MSEL(IP10_6_4, GLO_SCLK_B, SEL_GPS_1), 1353 PINMUX_IPSR_MSEL(IP10_6_4, VI3_DATA0_B, SEL_VI3_1), 1354 PINMUX_IPSR_GPSR(IP10_10_7, SD2_CMD), 1355 PINMUX_IPSR_GPSR(IP10_10_7, MMC0_CMD), 1356 PINMUX_IPSR_MSEL(IP10_10_7, SIM0_D, SEL_SIM_0), 1357 PINMUX_IPSR_MSEL(IP10_10_7, VI0_DATA1_VI0_B1_B, SEL_VI0_1), 1358 PINMUX_IPSR_MSEL(IP10_10_7, SCIFB1_SCK_E, SEL_SCIFB1_4), 1359 PINMUX_IPSR_MSEL(IP10_10_7, SCK1_D, SEL_SCIF1_3), 1360 PINMUX_IPSR_MSEL(IP10_10_7, TS_SPSYNC0_C, SEL_TSIF0_2), 1361 PINMUX_IPSR_MSEL(IP10_10_7, GLO_SDATA_B, SEL_GPS_1), 1362 PINMUX_IPSR_MSEL(IP10_10_7, VI3_DATA1_B, SEL_VI3_1), 1363 PINMUX_IPSR_GPSR(IP10_14_11, SD2_DAT0), 1364 PINMUX_IPSR_GPSR(IP10_14_11, MMC0_D0), 1365 PINMUX_IPSR_MSEL(IP10_14_11, FMCLK_B, SEL_FM_1), 1366 PINMUX_IPSR_MSEL(IP10_14_11, VI0_DATA2_VI0_B2_B, SEL_VI0_1), 1367 PINMUX_IPSR_MSEL(IP10_14_11, SCIFB1_RXD_E, SEL_SCIFB1_4), 1368 PINMUX_IPSR_MSEL(IP10_14_11, RX1_D, SEL_SCIF1_3), 1369 PINMUX_IPSR_MSEL(IP10_14_11, TS_SDAT0_C, SEL_TSIF0_2), 1370 PINMUX_IPSR_MSEL(IP10_14_11, GLO_SS_B, SEL_GPS_1), 1371 PINMUX_IPSR_MSEL(IP10_14_11, VI3_DATA2_B, SEL_VI3_1), 1372 PINMUX_IPSR_GPSR(IP10_18_15, SD2_DAT1), 1373 PINMUX_IPSR_GPSR(IP10_18_15, MMC0_D1), 1374 PINMUX_IPSR_MSEL(IP10_18_15, FMIN_B, SEL_FM_1), 1375 PINMUX_IPSR_MSEL(IP10_18_15, VI0_DATA3_VI0_B3_B, SEL_VI0_1), 1376 PINMUX_IPSR_MSEL(IP10_18_15, SCIFB1_TXD_E, SEL_SCIFB1_4), 1377 PINMUX_IPSR_MSEL(IP10_18_15, TX1_D, SEL_SCIF1_3), 1378 PINMUX_IPSR_MSEL(IP10_18_15, TS_SCK0_C, SEL_TSIF0_2), 1379 PINMUX_IPSR_MSEL(IP10_18_15, GLO_RFON_B, SEL_GPS_1), 1380 PINMUX_IPSR_MSEL(IP10_18_15, VI3_DATA3_B, SEL_VI3_1), 1381 PINMUX_IPSR_GPSR(IP10_22_19, SD2_DAT2), 1382 PINMUX_IPSR_GPSR(IP10_22_19, MMC0_D2), 1383 PINMUX_IPSR_MSEL(IP10_22_19, BPFCLK_B, SEL_FM_1), 1384 PINMUX_IPSR_MSEL(IP10_22_19, VI0_DATA4_VI0_B4_B, SEL_VI0_1), 1385 PINMUX_IPSR_MSEL(IP10_22_19, HRX0_D, SEL_HSCIF0_3), 1386 PINMUX_IPSR_MSEL(IP10_22_19, TS_SDEN1_B, SEL_TSIF1_1), 1387 PINMUX_IPSR_MSEL(IP10_22_19, GLO_Q0_B, SEL_GPS_1), 1388 PINMUX_IPSR_MSEL(IP10_22_19, VI3_DATA4_B, SEL_VI3_1), 1389 PINMUX_IPSR_GPSR(IP10_25_23, SD2_DAT3), 1390 PINMUX_IPSR_GPSR(IP10_25_23, MMC0_D3), 1391 PINMUX_IPSR_MSEL(IP10_25_23, SIM0_RST, SEL_SIM_0), 1392 PINMUX_IPSR_MSEL(IP10_25_23, VI0_DATA5_VI0_B5_B, SEL_VI0_1), 1393 PINMUX_IPSR_MSEL(IP10_25_23, HTX0_D, SEL_HSCIF0_3), 1394 PINMUX_IPSR_MSEL(IP10_25_23, TS_SPSYNC1_B, SEL_TSIF1_1), 1395 PINMUX_IPSR_MSEL(IP10_25_23, GLO_Q1_B, SEL_GPS_1), 1396 PINMUX_IPSR_MSEL(IP10_25_23, VI3_DATA5_B, SEL_VI3_1), 1397 PINMUX_IPSR_GPSR(IP10_29_26, SD2_CD), 1398 PINMUX_IPSR_GPSR(IP10_29_26, MMC0_D4), 1399 PINMUX_IPSR_MSEL(IP10_29_26, TS_SDAT0_B, SEL_TSIF0_1), 1400 PINMUX_IPSR_GPSR(IP10_29_26, USB2_EXTP), 1401 PINMUX_IPSR_MSEL(IP10_29_26, GLO_I0, SEL_GPS_0), 1402 PINMUX_IPSR_MSEL(IP10_29_26, VI0_DATA6_VI0_B6_B, SEL_VI0_1), 1403 PINMUX_IPSR_MSEL(IP10_29_26, HCTS0_N_D, SEL_HSCIF0_3), 1404 PINMUX_IPSR_MSEL(IP10_29_26, TS_SDAT1_B, SEL_TSIF1_1), 1405 PINMUX_IPSR_MSEL(IP10_29_26, GLO_I0_B, SEL_GPS_1), 1406 PINMUX_IPSR_MSEL(IP10_29_26, VI3_DATA6_B, SEL_VI3_1), 1407 1408 PINMUX_IPSR_GPSR(IP11_3_0, SD2_WP), 1409 PINMUX_IPSR_GPSR(IP11_3_0, MMC0_D5), 1410 PINMUX_IPSR_MSEL(IP11_3_0, TS_SCK0_B, SEL_TSIF0_1), 1411 PINMUX_IPSR_GPSR(IP11_3_0, USB2_IDIN), 1412 PINMUX_IPSR_MSEL(IP11_3_0, GLO_I1, SEL_GPS_0), 1413 PINMUX_IPSR_MSEL(IP11_3_0, VI0_DATA7_VI0_B7_B, SEL_VI0_1), 1414 PINMUX_IPSR_MSEL(IP11_3_0, HRTS0_N_D, SEL_HSCIF0_3), 1415 PINMUX_IPSR_MSEL(IP11_3_0, TS_SCK1_B, SEL_TSIF1_1), 1416 PINMUX_IPSR_MSEL(IP11_3_0, GLO_I1_B, SEL_GPS_1), 1417 PINMUX_IPSR_MSEL(IP11_3_0, VI3_DATA7_B, SEL_VI3_1), 1418 PINMUX_IPSR_GPSR(IP11_4, SD3_CLK), 1419 PINMUX_IPSR_GPSR(IP11_4, MMC1_CLK), 1420 PINMUX_IPSR_GPSR(IP11_6_5, SD3_CMD), 1421 PINMUX_IPSR_GPSR(IP11_6_5, MMC1_CMD), 1422 PINMUX_IPSR_GPSR(IP11_6_5, MTS_N), 1423 PINMUX_IPSR_GPSR(IP11_8_7, SD3_DAT0), 1424 PINMUX_IPSR_GPSR(IP11_8_7, MMC1_D0), 1425 PINMUX_IPSR_GPSR(IP11_8_7, STM_N), 1426 PINMUX_IPSR_GPSR(IP11_10_9, SD3_DAT1), 1427 PINMUX_IPSR_GPSR(IP11_10_9, MMC1_D1), 1428 PINMUX_IPSR_GPSR(IP11_10_9, MDATA), 1429 PINMUX_IPSR_GPSR(IP11_12_11, SD3_DAT2), 1430 PINMUX_IPSR_GPSR(IP11_12_11, MMC1_D2), 1431 PINMUX_IPSR_GPSR(IP11_12_11, SDATA), 1432 PINMUX_IPSR_GPSR(IP11_14_13, SD3_DAT3), 1433 PINMUX_IPSR_GPSR(IP11_14_13, MMC1_D3), 1434 PINMUX_IPSR_GPSR(IP11_14_13, SCKZ), 1435 PINMUX_IPSR_GPSR(IP11_17_15, SD3_CD), 1436 PINMUX_IPSR_GPSR(IP11_17_15, MMC1_D4), 1437 PINMUX_IPSR_MSEL(IP11_17_15, TS_SDAT1, SEL_TSIF1_0), 1438 PINMUX_IPSR_GPSR(IP11_17_15, VSP), 1439 PINMUX_IPSR_MSEL(IP11_17_15, GLO_Q0, SEL_GPS_0), 1440 PINMUX_IPSR_MSEL(IP11_17_15, SIM0_RST_B, SEL_SIM_1), 1441 PINMUX_IPSR_GPSR(IP11_21_18, SD3_WP), 1442 PINMUX_IPSR_GPSR(IP11_21_18, MMC1_D5), 1443 PINMUX_IPSR_MSEL(IP11_21_18, TS_SCK1, SEL_TSIF1_0), 1444 PINMUX_IPSR_MSEL(IP11_21_18, GLO_Q1, SEL_GPS_0), 1445 PINMUX_IPSR_MSEL(IP11_21_18, FMIN_C, SEL_FM_2), 1446 PINMUX_IPSR_MSEL(IP11_21_18, FMIN_E, SEL_FM_4), 1447 PINMUX_IPSR_MSEL(IP11_21_18, FMIN_F, SEL_FM_5), 1448 PINMUX_IPSR_GPSR(IP11_23_22, MLB_CLK), 1449 PINMUX_IPSR_MSEL(IP11_23_22, IIC2_SCL_B, SEL_IIC2_1), 1450 PINMUX_IPSR_MSEL(IP11_23_22, I2C2_SCL_B, SEL_I2C2_1), 1451 PINMUX_IPSR_GPSR(IP11_26_24, MLB_SIG), 1452 PINMUX_IPSR_MSEL(IP11_26_24, SCIFB1_RXD_D, SEL_SCIFB1_3), 1453 PINMUX_IPSR_MSEL(IP11_26_24, RX1_C, SEL_SCIF1_2), 1454 PINMUX_IPSR_MSEL(IP11_26_24, IIC2_SDA_B, SEL_IIC2_1), 1455 PINMUX_IPSR_MSEL(IP11_26_24, I2C2_SDA_B, SEL_I2C2_1), 1456 PINMUX_IPSR_GPSR(IP11_29_27, MLB_DAT), 1457 PINMUX_IPSR_MSEL(IP11_29_27, SCIFB1_TXD_D, SEL_SCIFB1_3), 1458 PINMUX_IPSR_MSEL(IP11_29_27, TX1_C, SEL_SCIF1_2), 1459 PINMUX_IPSR_MSEL(IP11_29_27, BPFCLK_C, SEL_FM_2), 1460 PINMUX_IPSR_GPSR(IP11_31_30, SSI_SCK0129), 1461 PINMUX_IPSR_MSEL(IP11_31_30, CAN_CLK_B, SEL_CANCLK_1), 1462 PINMUX_IPSR_GPSR(IP11_31_30, MOUT0), 1463 1464 PINMUX_IPSR_GPSR(IP12_1_0, SSI_WS0129), 1465 PINMUX_IPSR_MSEL(IP12_1_0, CAN0_TX_B, SEL_CAN0_1), 1466 PINMUX_IPSR_GPSR(IP12_1_0, MOUT1), 1467 PINMUX_IPSR_GPSR(IP12_3_2, SSI_SDATA0), 1468 PINMUX_IPSR_MSEL(IP12_3_2, CAN0_RX_B, SEL_CAN0_1), 1469 PINMUX_IPSR_GPSR(IP12_3_2, MOUT2), 1470 PINMUX_IPSR_GPSR(IP12_5_4, SSI_SDATA1), 1471 PINMUX_IPSR_MSEL(IP12_5_4, CAN1_TX_B, SEL_CAN1_1), 1472 PINMUX_IPSR_GPSR(IP12_5_4, MOUT5), 1473 PINMUX_IPSR_GPSR(IP12_7_6, SSI_SDATA2), 1474 PINMUX_IPSR_MSEL(IP12_7_6, CAN1_RX_B, SEL_CAN1_1), 1475 PINMUX_IPSR_GPSR(IP12_7_6, SSI_SCK1), 1476 PINMUX_IPSR_GPSR(IP12_7_6, MOUT6), 1477 PINMUX_IPSR_GPSR(IP12_10_8, SSI_SCK34), 1478 PINMUX_IPSR_GPSR(IP12_10_8, STP_OPWM_0), 1479 PINMUX_IPSR_MSEL(IP12_10_8, SCIFB0_SCK, SEL_SCIFB_0), 1480 PINMUX_IPSR_MSEL(IP12_10_8, MSIOF1_SCK, SEL_SOF1_0), 1481 PINMUX_IPSR_GPSR(IP12_10_8, CAN_DEBUG_HW_TRIGGER), 1482 PINMUX_IPSR_GPSR(IP12_13_11, SSI_WS34), 1483 PINMUX_IPSR_MSEL(IP12_13_11, STP_IVCXO27_0, SEL_SSP_0), 1484 PINMUX_IPSR_MSEL(IP12_13_11, SCIFB0_RXD, SEL_SCIFB_0), 1485 PINMUX_IPSR_GPSR(IP12_13_11, MSIOF1_SYNC), 1486 PINMUX_IPSR_GPSR(IP12_13_11, CAN_STEP0), 1487 PINMUX_IPSR_GPSR(IP12_16_14, SSI_SDATA3), 1488 PINMUX_IPSR_MSEL(IP12_16_14, STP_ISCLK_0, SEL_SSP_0), 1489 PINMUX_IPSR_MSEL(IP12_16_14, SCIFB0_TXD, SEL_SCIFB_0), 1490 PINMUX_IPSR_MSEL(IP12_16_14, MSIOF1_SS1, SEL_SOF1_0), 1491 PINMUX_IPSR_GPSR(IP12_16_14, CAN_TXCLK), 1492 PINMUX_IPSR_GPSR(IP12_19_17, SSI_SCK4), 1493 PINMUX_IPSR_MSEL(IP12_19_17, STP_ISD_0, SEL_SSP_0), 1494 PINMUX_IPSR_MSEL(IP12_19_17, SCIFB0_CTS_N, SEL_SCIFB_0), 1495 PINMUX_IPSR_MSEL(IP12_19_17, MSIOF1_SS2, SEL_SOF1_0), 1496 PINMUX_IPSR_MSEL(IP12_19_17, SSI_SCK5_C, SEL_SSI5_2), 1497 PINMUX_IPSR_GPSR(IP12_19_17, CAN_DEBUGOUT0), 1498 PINMUX_IPSR_GPSR(IP12_22_20, SSI_WS4), 1499 PINMUX_IPSR_MSEL(IP12_22_20, STP_ISEN_0, SEL_SSP_0), 1500 PINMUX_IPSR_MSEL(IP12_22_20, SCIFB0_RTS_N, SEL_SCIFB_0), 1501 PINMUX_IPSR_MSEL(IP12_22_20, MSIOF1_TXD, SEL_SOF1_0), 1502 PINMUX_IPSR_MSEL(IP12_22_20, SSI_WS5_C, SEL_SSI5_2), 1503 PINMUX_IPSR_GPSR(IP12_22_20, CAN_DEBUGOUT1), 1504 PINMUX_IPSR_GPSR(IP12_24_23, SSI_SDATA4), 1505 PINMUX_IPSR_MSEL(IP12_24_23, STP_ISSYNC_0, SEL_SSP_0), 1506 PINMUX_IPSR_MSEL(IP12_24_23, MSIOF1_RXD, SEL_SOF1_0), 1507 PINMUX_IPSR_GPSR(IP12_24_23, CAN_DEBUGOUT2), 1508 PINMUX_IPSR_MSEL(IP12_27_25, SSI_SCK5, SEL_SSI5_0), 1509 PINMUX_IPSR_MSEL(IP12_27_25, SCIFB1_SCK, SEL_SCIFB1_0), 1510 PINMUX_IPSR_MSEL(IP12_27_25, IERX_B, SEL_IEB_1), 1511 PINMUX_IPSR_GPSR(IP12_27_25, DU2_EXHSYNC_DU2_HSYNC), 1512 PINMUX_IPSR_GPSR(IP12_27_25, QSTH_QHS), 1513 PINMUX_IPSR_GPSR(IP12_27_25, CAN_DEBUGOUT3), 1514 PINMUX_IPSR_MSEL(IP12_30_28, SSI_WS5, SEL_SSI5_0), 1515 PINMUX_IPSR_MSEL(IP12_30_28, SCIFB1_RXD, SEL_SCIFB1_0), 1516 PINMUX_IPSR_MSEL(IP12_30_28, IECLK_B, SEL_IEB_1), 1517 PINMUX_IPSR_GPSR(IP12_30_28, DU2_EXVSYNC_DU2_VSYNC), 1518 PINMUX_IPSR_GPSR(IP12_30_28, QSTB_QHE), 1519 PINMUX_IPSR_GPSR(IP12_30_28, CAN_DEBUGOUT4), 1520 1521 PINMUX_IPSR_MSEL(IP13_2_0, SSI_SDATA5, SEL_SSI5_0), 1522 PINMUX_IPSR_MSEL(IP13_2_0, SCIFB1_TXD, SEL_SCIFB1_0), 1523 PINMUX_IPSR_MSEL(IP13_2_0, IETX_B, SEL_IEB_1), 1524 PINMUX_IPSR_GPSR(IP13_2_0, DU2_DR2), 1525 PINMUX_IPSR_GPSR(IP13_2_0, LCDOUT2), 1526 PINMUX_IPSR_GPSR(IP13_2_0, CAN_DEBUGOUT5), 1527 PINMUX_IPSR_MSEL(IP13_6_3, SSI_SCK6, SEL_SSI6_0), 1528 PINMUX_IPSR_MSEL(IP13_6_3, SCIFB1_CTS_N, SEL_SCIFB1_0), 1529 PINMUX_IPSR_MSEL(IP13_6_3, BPFCLK_D, SEL_FM_3), 1530 PINMUX_IPSR_GPSR(IP13_6_3, DU2_DR3), 1531 PINMUX_IPSR_GPSR(IP13_6_3, LCDOUT3), 1532 PINMUX_IPSR_GPSR(IP13_6_3, CAN_DEBUGOUT6), 1533 PINMUX_IPSR_MSEL(IP13_6_3, BPFCLK_F, SEL_FM_5), 1534 PINMUX_IPSR_MSEL(IP13_9_7, SSI_WS6, SEL_SSI6_0), 1535 PINMUX_IPSR_MSEL(IP13_9_7, SCIFB1_RTS_N, SEL_SCIFB1_0), 1536 PINMUX_IPSR_MSEL(IP13_9_7, CAN0_TX_D, SEL_CAN0_3), 1537 PINMUX_IPSR_GPSR(IP13_9_7, DU2_DR4), 1538 PINMUX_IPSR_GPSR(IP13_9_7, LCDOUT4), 1539 PINMUX_IPSR_GPSR(IP13_9_7, CAN_DEBUGOUT7), 1540 PINMUX_IPSR_MSEL(IP13_12_10, SSI_SDATA6, SEL_SSI6_0), 1541 PINMUX_IPSR_MSEL(IP13_12_10, FMIN_D, SEL_FM_3), 1542 PINMUX_IPSR_GPSR(IP13_12_10, DU2_DR5), 1543 PINMUX_IPSR_GPSR(IP13_12_10, LCDOUT5), 1544 PINMUX_IPSR_GPSR(IP13_12_10, CAN_DEBUGOUT8), 1545 PINMUX_IPSR_MSEL(IP13_15_13, SSI_SCK78, SEL_SSI7_0), 1546 PINMUX_IPSR_MSEL(IP13_15_13, STP_IVCXO27_1, SEL_SSP_0), 1547 PINMUX_IPSR_MSEL(IP13_15_13, SCK1, SEL_SCIF1_0), 1548 PINMUX_IPSR_MSEL(IP13_15_13, SCIFA1_SCK, SEL_SCIFA1_0), 1549 PINMUX_IPSR_GPSR(IP13_15_13, DU2_DR6), 1550 PINMUX_IPSR_GPSR(IP13_15_13, LCDOUT6), 1551 PINMUX_IPSR_GPSR(IP13_15_13, CAN_DEBUGOUT9), 1552 PINMUX_IPSR_MSEL(IP13_18_16, SSI_WS78, SEL_SSI7_0), 1553 PINMUX_IPSR_MSEL(IP13_18_16, STP_ISCLK_1, SEL_SSP_0), 1554 PINMUX_IPSR_MSEL(IP13_18_16, SCIFB2_SCK, SEL_SCIFB2_0), 1555 PINMUX_IPSR_GPSR(IP13_18_16, SCIFA2_CTS_N), 1556 PINMUX_IPSR_GPSR(IP13_18_16, DU2_DR7), 1557 PINMUX_IPSR_GPSR(IP13_18_16, LCDOUT7), 1558 PINMUX_IPSR_GPSR(IP13_18_16, CAN_DEBUGOUT10), 1559 PINMUX_IPSR_MSEL(IP13_22_19, SSI_SDATA7, SEL_SSI7_0), 1560 PINMUX_IPSR_MSEL(IP13_22_19, STP_ISD_1, SEL_SSP_0), 1561 PINMUX_IPSR_MSEL(IP13_22_19, SCIFB2_RXD, SEL_SCIFB2_0), 1562 PINMUX_IPSR_GPSR(IP13_22_19, SCIFA2_RTS_N), 1563 PINMUX_IPSR_GPSR(IP13_22_19, TCLK2), 1564 PINMUX_IPSR_GPSR(IP13_22_19, QSTVA_QVS), 1565 PINMUX_IPSR_GPSR(IP13_22_19, CAN_DEBUGOUT11), 1566 PINMUX_IPSR_MSEL(IP13_22_19, BPFCLK_E, SEL_FM_4), 1567 PINMUX_IPSR_MSEL(IP13_22_19, SSI_SDATA7_B, SEL_SSI7_1), 1568 PINMUX_IPSR_MSEL(IP13_22_19, FMIN_G, SEL_FM_6), 1569 PINMUX_IPSR_MSEL(IP13_25_23, SSI_SDATA8, SEL_SSI8_0), 1570 PINMUX_IPSR_MSEL(IP13_25_23, STP_ISEN_1, SEL_SSP_0), 1571 PINMUX_IPSR_MSEL(IP13_25_23, SCIFB2_TXD, SEL_SCIFB2_0), 1572 PINMUX_IPSR_MSEL(IP13_25_23, CAN0_TX_C, SEL_CAN0_2), 1573 PINMUX_IPSR_GPSR(IP13_25_23, CAN_DEBUGOUT12), 1574 PINMUX_IPSR_MSEL(IP13_25_23, SSI_SDATA8_B, SEL_SSI8_1), 1575 PINMUX_IPSR_GPSR(IP13_28_26, SSI_SDATA9), 1576 PINMUX_IPSR_MSEL(IP13_28_26, STP_ISSYNC_1, SEL_SSP_0), 1577 PINMUX_IPSR_MSEL(IP13_28_26, SCIFB2_CTS_N, SEL_SCIFB2_0), 1578 PINMUX_IPSR_GPSR(IP13_28_26, SSI_WS1), 1579 PINMUX_IPSR_MSEL(IP13_28_26, SSI_SDATA5_C, SEL_SSI5_2), 1580 PINMUX_IPSR_GPSR(IP13_28_26, CAN_DEBUGOUT13), 1581 PINMUX_IPSR_GPSR(IP13_30_29, AUDIO_CLKA), 1582 PINMUX_IPSR_MSEL(IP13_30_29, SCIFB2_RTS_N, SEL_SCIFB2_0), 1583 PINMUX_IPSR_GPSR(IP13_30_29, CAN_DEBUGOUT14), 1584 1585 PINMUX_IPSR_GPSR(IP14_2_0, AUDIO_CLKB), 1586 PINMUX_IPSR_MSEL(IP14_2_0, SCIF_CLK, SEL_SCIFCLK_0), 1587 PINMUX_IPSR_MSEL(IP14_2_0, CAN0_RX_D, SEL_CAN0_3), 1588 PINMUX_IPSR_GPSR(IP14_2_0, DVC_MUTE), 1589 PINMUX_IPSR_MSEL(IP14_2_0, CAN0_RX_C, SEL_CAN0_2), 1590 PINMUX_IPSR_GPSR(IP14_2_0, CAN_DEBUGOUT15), 1591 PINMUX_IPSR_GPSR(IP14_2_0, REMOCON), 1592 PINMUX_IPSR_MSEL(IP14_5_3, SCIFA0_SCK, SEL_SCFA_0), 1593 PINMUX_IPSR_MSEL(IP14_5_3, HSCK1, SEL_HSCIF1_0), 1594 PINMUX_IPSR_GPSR(IP14_5_3, SCK0), 1595 PINMUX_IPSR_GPSR(IP14_5_3, MSIOF3_SS2), 1596 PINMUX_IPSR_GPSR(IP14_5_3, DU2_DG2), 1597 PINMUX_IPSR_GPSR(IP14_5_3, LCDOUT10), 1598 PINMUX_IPSR_MSEL(IP14_5_3, IIC1_SDA_C, SEL_IIC1_2), 1599 PINMUX_IPSR_MSEL(IP14_5_3, I2C1_SDA_C, SEL_I2C1_2), 1600 PINMUX_IPSR_MSEL(IP14_8_6, SCIFA0_RXD, SEL_SCFA_0), 1601 PINMUX_IPSR_MSEL(IP14_8_6, HRX1, SEL_HSCIF1_0), 1602 PINMUX_IPSR_MSEL(IP14_8_6, RX0, SEL_SCIF0_0), 1603 PINMUX_IPSR_GPSR(IP14_8_6, DU2_DR0), 1604 PINMUX_IPSR_GPSR(IP14_8_6, LCDOUT0), 1605 PINMUX_IPSR_MSEL(IP14_11_9, SCIFA0_TXD, SEL_SCFA_0), 1606 PINMUX_IPSR_MSEL(IP14_11_9, HTX1, SEL_HSCIF1_0), 1607 PINMUX_IPSR_MSEL(IP14_11_9, TX0, SEL_SCIF0_0), 1608 PINMUX_IPSR_GPSR(IP14_11_9, DU2_DR1), 1609 PINMUX_IPSR_GPSR(IP14_11_9, LCDOUT1), 1610 PINMUX_IPSR_MSEL(IP14_15_12, SCIFA0_CTS_N, SEL_SCFA_0), 1611 PINMUX_IPSR_MSEL(IP14_15_12, HCTS1_N, SEL_HSCIF1_0), 1612 PINMUX_IPSR_GPSR(IP14_15_12, CTS0_N), 1613 PINMUX_IPSR_MSEL(IP14_15_12, MSIOF3_SYNC, SEL_SOF3_0), 1614 PINMUX_IPSR_GPSR(IP14_15_12, DU2_DG3), 1615 PINMUX_IPSR_GPSR(IP14_15_12, LCDOUT11), 1616 PINMUX_IPSR_GPSR(IP14_15_12, PWM0_B), 1617 PINMUX_IPSR_MSEL(IP14_15_12, IIC1_SCL_C, SEL_IIC1_2), 1618 PINMUX_IPSR_MSEL(IP14_15_12, I2C1_SCL_C, SEL_I2C1_2), 1619 PINMUX_IPSR_MSEL(IP14_18_16, SCIFA0_RTS_N, SEL_SCFA_0), 1620 PINMUX_IPSR_MSEL(IP14_18_16, HRTS1_N, SEL_HSCIF1_0), 1621 PINMUX_IPSR_GPSR(IP14_18_16, RTS0_N), 1622 PINMUX_IPSR_GPSR(IP14_18_16, MSIOF3_SS1), 1623 PINMUX_IPSR_GPSR(IP14_18_16, DU2_DG0), 1624 PINMUX_IPSR_GPSR(IP14_18_16, LCDOUT8), 1625 PINMUX_IPSR_GPSR(IP14_18_16, PWM1_B), 1626 PINMUX_IPSR_MSEL(IP14_21_19, SCIFA1_RXD, SEL_SCIFA1_0), 1627 PINMUX_IPSR_MSEL(IP14_21_19, AD_DI, SEL_ADI_0), 1628 PINMUX_IPSR_MSEL(IP14_21_19, RX1, SEL_SCIF1_0), 1629 PINMUX_IPSR_GPSR(IP14_21_19, DU2_EXODDF_DU2_ODDF_DISP_CDE), 1630 PINMUX_IPSR_GPSR(IP14_21_19, QCPV_QDE), 1631 PINMUX_IPSR_MSEL(IP14_24_22, SCIFA1_TXD, SEL_SCIFA1_0), 1632 PINMUX_IPSR_MSEL(IP14_24_22, AD_DO, SEL_ADI_0), 1633 PINMUX_IPSR_MSEL(IP14_24_22, TX1, SEL_SCIF1_0), 1634 PINMUX_IPSR_GPSR(IP14_24_22, DU2_DG1), 1635 PINMUX_IPSR_GPSR(IP14_24_22, LCDOUT9), 1636 PINMUX_IPSR_MSEL(IP14_27_25, SCIFA1_CTS_N, SEL_SCIFA1_0), 1637 PINMUX_IPSR_MSEL(IP14_27_25, AD_CLK, SEL_ADI_0), 1638 PINMUX_IPSR_GPSR(IP14_27_25, CTS1_N), 1639 PINMUX_IPSR_MSEL(IP14_27_25, MSIOF3_RXD, SEL_SOF3_0), 1640 PINMUX_IPSR_GPSR(IP14_27_25, DU0_DOTCLKOUT), 1641 PINMUX_IPSR_GPSR(IP14_27_25, QCLK), 1642 PINMUX_IPSR_MSEL(IP14_30_28, SCIFA1_RTS_N, SEL_SCIFA1_0), 1643 PINMUX_IPSR_MSEL(IP14_30_28, AD_NCS_N, SEL_ADI_0), 1644 PINMUX_IPSR_GPSR(IP14_30_28, RTS1_N), 1645 PINMUX_IPSR_MSEL(IP14_30_28, MSIOF3_TXD, SEL_SOF3_0), 1646 PINMUX_IPSR_GPSR(IP14_30_28, DU1_DOTCLKOUT), 1647 PINMUX_IPSR_GPSR(IP14_30_28, QSTVB_QVE), 1648 PINMUX_IPSR_MSEL(IP14_30_28, HRTS0_N_C, SEL_HSCIF0_2), 1649 1650 PINMUX_IPSR_MSEL(IP15_2_0, SCIFA2_SCK, SEL_SCIFA2_0), 1651 PINMUX_IPSR_MSEL(IP15_2_0, FMCLK, SEL_FM_0), 1652 PINMUX_IPSR_GPSR(IP15_2_0, SCK2), 1653 PINMUX_IPSR_MSEL(IP15_2_0, MSIOF3_SCK, SEL_SOF3_0), 1654 PINMUX_IPSR_GPSR(IP15_2_0, DU2_DG7), 1655 PINMUX_IPSR_GPSR(IP15_2_0, LCDOUT15), 1656 PINMUX_IPSR_MSEL(IP15_2_0, SCIF_CLK_B, SEL_SCIFCLK_1), 1657 PINMUX_IPSR_MSEL(IP15_5_3, SCIFA2_RXD, SEL_SCIFA2_0), 1658 PINMUX_IPSR_MSEL(IP15_5_3, FMIN, SEL_FM_0), 1659 PINMUX_IPSR_MSEL(IP15_5_3, TX2, SEL_SCIF2_0), 1660 PINMUX_IPSR_GPSR(IP15_5_3, DU2_DB0), 1661 PINMUX_IPSR_GPSR(IP15_5_3, LCDOUT16), 1662 PINMUX_IPSR_MSEL(IP15_5_3, IIC2_SCL, SEL_IIC2_0), 1663 PINMUX_IPSR_MSEL(IP15_5_3, I2C2_SCL, SEL_I2C2_0), 1664 PINMUX_IPSR_MSEL(IP15_8_6, SCIFA2_TXD, SEL_SCIFA2_0), 1665 PINMUX_IPSR_MSEL(IP15_8_6, BPFCLK, SEL_FM_0), 1666 PINMUX_IPSR_MSEL(IP15_8_6, RX2, SEL_SCIF2_0), 1667 PINMUX_IPSR_GPSR(IP15_8_6, DU2_DB1), 1668 PINMUX_IPSR_GPSR(IP15_8_6, LCDOUT17), 1669 PINMUX_IPSR_MSEL(IP15_8_6, IIC2_SDA, SEL_IIC2_0), 1670 PINMUX_IPSR_MSEL(IP15_8_6, I2C2_SDA, SEL_I2C2_0), 1671 PINMUX_IPSR_GPSR(IP15_11_9, HSCK0), 1672 PINMUX_IPSR_MSEL(IP15_11_9, TS_SDEN0, SEL_TSIF0_0), 1673 PINMUX_IPSR_GPSR(IP15_11_9, DU2_DG4), 1674 PINMUX_IPSR_GPSR(IP15_11_9, LCDOUT12), 1675 PINMUX_IPSR_MSEL(IP15_11_9, HCTS0_N_C, SEL_HSCIF0_2), 1676 PINMUX_IPSR_MSEL(IP15_13_12, HRX0, SEL_HSCIF0_0), 1677 PINMUX_IPSR_GPSR(IP15_13_12, DU2_DB2), 1678 PINMUX_IPSR_GPSR(IP15_13_12, LCDOUT18), 1679 PINMUX_IPSR_MSEL(IP15_15_14, HTX0, SEL_HSCIF0_0), 1680 PINMUX_IPSR_GPSR(IP15_15_14, DU2_DB3), 1681 PINMUX_IPSR_GPSR(IP15_15_14, LCDOUT19), 1682 PINMUX_IPSR_MSEL(IP15_17_16, HCTS0_N, SEL_HSCIF0_0), 1683 PINMUX_IPSR_GPSR(IP15_17_16, SSI_SCK9), 1684 PINMUX_IPSR_GPSR(IP15_17_16, DU2_DB4), 1685 PINMUX_IPSR_GPSR(IP15_17_16, LCDOUT20), 1686 PINMUX_IPSR_MSEL(IP15_19_18, HRTS0_N, SEL_HSCIF0_0), 1687 PINMUX_IPSR_GPSR(IP15_19_18, SSI_WS9), 1688 PINMUX_IPSR_GPSR(IP15_19_18, DU2_DB5), 1689 PINMUX_IPSR_GPSR(IP15_19_18, LCDOUT21), 1690 PINMUX_IPSR_MSEL(IP15_22_20, MSIOF0_SCK, SEL_SOF0_0), 1691 PINMUX_IPSR_MSEL(IP15_22_20, TS_SDAT0, SEL_TSIF0_0), 1692 PINMUX_IPSR_GPSR(IP15_22_20, ADICLK), 1693 PINMUX_IPSR_GPSR(IP15_22_20, DU2_DB6), 1694 PINMUX_IPSR_GPSR(IP15_22_20, LCDOUT22), 1695 PINMUX_IPSR_GPSR(IP15_25_23, MSIOF0_SYNC), 1696 PINMUX_IPSR_MSEL(IP15_25_23, TS_SCK0, SEL_TSIF0_0), 1697 PINMUX_IPSR_GPSR(IP15_25_23, SSI_SCK2), 1698 PINMUX_IPSR_GPSR(IP15_25_23, ADIDATA), 1699 PINMUX_IPSR_GPSR(IP15_25_23, DU2_DB7), 1700 PINMUX_IPSR_GPSR(IP15_25_23, LCDOUT23), 1701 PINMUX_IPSR_MSEL(IP15_25_23, HRX0_C, SEL_SCIFA2_1), 1702 PINMUX_IPSR_MSEL(IP15_27_26, MSIOF0_SS1, SEL_SOF0_0), 1703 PINMUX_IPSR_GPSR(IP15_27_26, ADICHS0), 1704 PINMUX_IPSR_GPSR(IP15_27_26, DU2_DG5), 1705 PINMUX_IPSR_GPSR(IP15_27_26, LCDOUT13), 1706 PINMUX_IPSR_MSEL(IP15_29_28, MSIOF0_TXD, SEL_SOF0_0), 1707 PINMUX_IPSR_GPSR(IP15_29_28, ADICHS1), 1708 PINMUX_IPSR_GPSR(IP15_29_28, DU2_DG6), 1709 PINMUX_IPSR_GPSR(IP15_29_28, LCDOUT14), 1710 1711 PINMUX_IPSR_MSEL(IP16_2_0, MSIOF0_SS2, SEL_SOF0_0), 1712 PINMUX_IPSR_GPSR(IP16_2_0, AUDIO_CLKOUT), 1713 PINMUX_IPSR_GPSR(IP16_2_0, ADICHS2), 1714 PINMUX_IPSR_GPSR(IP16_2_0, DU2_DISP), 1715 PINMUX_IPSR_GPSR(IP16_2_0, QPOLA), 1716 PINMUX_IPSR_MSEL(IP16_2_0, HTX0_C, SEL_HSCIF0_2), 1717 PINMUX_IPSR_MSEL(IP16_2_0, SCIFA2_TXD_B, SEL_SCIFA2_1), 1718 PINMUX_IPSR_MSEL(IP16_5_3, MSIOF0_RXD, SEL_SOF0_0), 1719 PINMUX_IPSR_MSEL(IP16_5_3, TS_SPSYNC0, SEL_TSIF0_0), 1720 PINMUX_IPSR_GPSR(IP16_5_3, SSI_WS2), 1721 PINMUX_IPSR_GPSR(IP16_5_3, ADICS_SAMP), 1722 PINMUX_IPSR_GPSR(IP16_5_3, DU2_CDE), 1723 PINMUX_IPSR_GPSR(IP16_5_3, QPOLB), 1724 PINMUX_IPSR_MSEL(IP16_5_3, SCIFA2_RXD_B, SEL_HSCIF0_2), 1725 PINMUX_IPSR_GPSR(IP16_6, USB1_PWEN), 1726 PINMUX_IPSR_GPSR(IP16_6, AUDIO_CLKOUT_D), 1727 PINMUX_IPSR_GPSR(IP16_7, USB1_OVC), 1728 PINMUX_IPSR_MSEL(IP16_7, TCLK1_B, SEL_TMU1_1), 1729 1730 PINMUX_DATA(IIC0_SCL_MARK, FN_SEL_IIC0_0), 1731 PINMUX_DATA(IIC0_SDA_MARK, FN_SEL_IIC0_0), 1732 PINMUX_DATA(I2C0_SCL_MARK, FN_SEL_IIC0_1), 1733 PINMUX_DATA(I2C0_SDA_MARK, FN_SEL_IIC0_1), 1734 1735 PINMUX_DATA(IIC3_SCL_MARK, FN_SEL_IICDVFS_0), 1736 PINMUX_DATA(IIC3_SDA_MARK, FN_SEL_IICDVFS_0), 1737 PINMUX_DATA(I2C3_SCL_MARK, FN_SEL_IICDVFS_1), 1738 PINMUX_DATA(I2C3_SDA_MARK, FN_SEL_IICDVFS_1), 1739 }; 1740 1741 /* 1742 * Pins not associated with a GPIO port. 1743 */ 1744 enum { 1745 GP_ASSIGN_LAST(), 1746 NOGP_ALL(), 1747 }; 1748 1749 static const struct sh_pfc_pin pinmux_pins[] = { 1750 PINMUX_GPIO_GP_ALL(), 1751 PINMUX_NOGP_ALL(), 1752 }; 1753 1754 /* - AUDIO CLOCK ------------------------------------------------------------ */ 1755 static const unsigned int audio_clk_a_pins[] = { 1756 /* CLK A */ 1757 RCAR_GP_PIN(4, 25), 1758 }; 1759 static const unsigned int audio_clk_a_mux[] = { 1760 AUDIO_CLKA_MARK, 1761 }; 1762 static const unsigned int audio_clk_b_pins[] = { 1763 /* CLK B */ 1764 RCAR_GP_PIN(4, 26), 1765 }; 1766 static const unsigned int audio_clk_b_mux[] = { 1767 AUDIO_CLKB_MARK, 1768 }; 1769 static const unsigned int audio_clk_c_pins[] = { 1770 /* CLK C */ 1771 RCAR_GP_PIN(5, 27), 1772 }; 1773 static const unsigned int audio_clk_c_mux[] = { 1774 AUDIO_CLKC_MARK, 1775 }; 1776 static const unsigned int audio_clkout_pins[] = { 1777 /* CLK OUT */ 1778 RCAR_GP_PIN(5, 16), 1779 }; 1780 static const unsigned int audio_clkout_mux[] = { 1781 AUDIO_CLKOUT_MARK, 1782 }; 1783 static const unsigned int audio_clkout_b_pins[] = { 1784 /* CLK OUT B */ 1785 RCAR_GP_PIN(0, 23), 1786 }; 1787 static const unsigned int audio_clkout_b_mux[] = { 1788 AUDIO_CLKOUT_B_MARK, 1789 }; 1790 static const unsigned int audio_clkout_c_pins[] = { 1791 /* CLK OUT C */ 1792 RCAR_GP_PIN(5, 27), 1793 }; 1794 static const unsigned int audio_clkout_c_mux[] = { 1795 AUDIO_CLKOUT_C_MARK, 1796 }; 1797 static const unsigned int audio_clkout_d_pins[] = { 1798 /* CLK OUT D */ 1799 RCAR_GP_PIN(5, 20), 1800 }; 1801 static const unsigned int audio_clkout_d_mux[] = { 1802 AUDIO_CLKOUT_D_MARK, 1803 }; 1804 /* - AVB -------------------------------------------------------------------- */ 1805 static const unsigned int avb_link_pins[] = { 1806 RCAR_GP_PIN(3, 11), 1807 }; 1808 static const unsigned int avb_link_mux[] = { 1809 AVB_LINK_MARK, 1810 }; 1811 static const unsigned int avb_magic_pins[] = { 1812 RCAR_GP_PIN(2, 14), 1813 }; 1814 static const unsigned int avb_magic_mux[] = { 1815 AVB_MAGIC_MARK, 1816 }; 1817 static const unsigned int avb_phy_int_pins[] = { 1818 RCAR_GP_PIN(2, 15), 1819 }; 1820 static const unsigned int avb_phy_int_mux[] = { 1821 AVB_PHY_INT_MARK, 1822 }; 1823 static const unsigned int avb_mdio_pins[] = { 1824 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12), 1825 }; 1826 static const unsigned int avb_mdio_mux[] = { 1827 AVB_MDC_MARK, AVB_MDIO_MARK, 1828 }; 1829 static const unsigned int avb_mii_pins[] = { 1830 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10), 1831 RCAR_GP_PIN(0, 11), 1832 1833 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), 1834 RCAR_GP_PIN(2, 2), 1835 1836 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), 1837 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), 1838 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 12), 1839 }; 1840 static const unsigned int avb_mii_mux[] = { 1841 AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK, 1842 AVB_TXD3_MARK, 1843 1844 AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK, 1845 AVB_RXD3_MARK, 1846 1847 AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK, 1848 AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_ER_MARK, 1849 AVB_TX_CLK_MARK, AVB_COL_MARK, 1850 }; 1851 static const unsigned int avb_gmii_pins[] = { 1852 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10), 1853 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), 1854 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), 1855 1856 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), 1857 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4), 1858 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6), 1859 1860 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), 1861 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 16), 1862 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10), 1863 RCAR_GP_PIN(3, 12), 1864 }; 1865 static const unsigned int avb_gmii_mux[] = { 1866 AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK, 1867 AVB_TXD3_MARK, AVB_TXD4_MARK, AVB_TXD5_MARK, 1868 AVB_TXD6_MARK, AVB_TXD7_MARK, 1869 1870 AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK, 1871 AVB_RXD3_MARK, AVB_RXD4_MARK, AVB_RXD5_MARK, 1872 AVB_RXD6_MARK, AVB_RXD7_MARK, 1873 1874 AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK, 1875 AVB_CRS_MARK, AVB_GTX_CLK_MARK, AVB_GTXREFCLK_MARK, 1876 AVB_TX_EN_MARK, AVB_TX_ER_MARK, AVB_TX_CLK_MARK, 1877 AVB_COL_MARK, 1878 }; 1879 /* - CAN0 ----------------------------------------------------------------- */ 1880 static const unsigned int can0_data_pins[] = { 1881 /* CAN0 RX */ 1882 RCAR_GP_PIN(1, 17), 1883 /* CAN0 TX */ 1884 RCAR_GP_PIN(1, 19), 1885 }; 1886 static const unsigned int can0_data_mux[] = { 1887 CAN0_RX_MARK, 1888 CAN0_TX_MARK, 1889 }; 1890 static const unsigned int can0_data_b_pins[] = { 1891 /* CAN0 RXB */ 1892 RCAR_GP_PIN(4, 5), 1893 /* CAN0 TXB */ 1894 RCAR_GP_PIN(4, 4), 1895 }; 1896 static const unsigned int can0_data_b_mux[] = { 1897 CAN0_RX_B_MARK, 1898 CAN0_TX_B_MARK, 1899 }; 1900 static const unsigned int can0_data_c_pins[] = { 1901 /* CAN0 RXC */ 1902 RCAR_GP_PIN(4, 26), 1903 /* CAN0 TXC */ 1904 RCAR_GP_PIN(4, 23), 1905 }; 1906 static const unsigned int can0_data_c_mux[] = { 1907 CAN0_RX_C_MARK, 1908 CAN0_TX_C_MARK, 1909 }; 1910 static const unsigned int can0_data_d_pins[] = { 1911 /* CAN0 RXD */ 1912 RCAR_GP_PIN(4, 26), 1913 /* CAN0 TXD */ 1914 RCAR_GP_PIN(4, 18), 1915 }; 1916 static const unsigned int can0_data_d_mux[] = { 1917 CAN0_RX_D_MARK, 1918 CAN0_TX_D_MARK, 1919 }; 1920 /* - CAN1 ----------------------------------------------------------------- */ 1921 static const unsigned int can1_data_pins[] = { 1922 /* CAN1 RX */ 1923 RCAR_GP_PIN(1, 22), 1924 /* CAN1 TX */ 1925 RCAR_GP_PIN(1, 18), 1926 }; 1927 static const unsigned int can1_data_mux[] = { 1928 CAN1_RX_MARK, 1929 CAN1_TX_MARK, 1930 }; 1931 static const unsigned int can1_data_b_pins[] = { 1932 /* CAN1 RXB */ 1933 RCAR_GP_PIN(4, 7), 1934 /* CAN1 TXB */ 1935 RCAR_GP_PIN(4, 6), 1936 }; 1937 static const unsigned int can1_data_b_mux[] = { 1938 CAN1_RX_B_MARK, 1939 CAN1_TX_B_MARK, 1940 }; 1941 /* - CAN Clock -------------------------------------------------------------- */ 1942 static const unsigned int can_clk_pins[] = { 1943 /* CLK */ 1944 RCAR_GP_PIN(1, 21), 1945 }; 1946 1947 static const unsigned int can_clk_mux[] = { 1948 CAN_CLK_MARK, 1949 }; 1950 1951 static const unsigned int can_clk_b_pins[] = { 1952 /* CLK */ 1953 RCAR_GP_PIN(4, 3), 1954 }; 1955 1956 static const unsigned int can_clk_b_mux[] = { 1957 CAN_CLK_B_MARK, 1958 }; 1959 /* - DU RGB ----------------------------------------------------------------- */ 1960 static const unsigned int du_rgb666_pins[] = { 1961 /* R[7:2], G[7:2], B[7:2] */ 1962 RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 19), 1963 RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16), 1964 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 14), 1965 RCAR_GP_PIN(5, 7), RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27), 1966 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 11), 1967 RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 8), 1968 }; 1969 static const unsigned int du_rgb666_mux[] = { 1970 DU2_DR7_MARK, DU2_DR6_MARK, DU2_DR5_MARK, DU2_DR4_MARK, 1971 DU2_DR3_MARK, DU2_DR2_MARK, 1972 DU2_DG7_MARK, DU2_DG6_MARK, DU2_DG5_MARK, DU2_DG4_MARK, 1973 DU2_DG3_MARK, DU2_DG2_MARK, 1974 DU2_DB7_MARK, DU2_DB6_MARK, DU2_DB5_MARK, DU2_DB4_MARK, 1975 DU2_DB3_MARK, DU2_DB2_MARK, 1976 }; 1977 static const unsigned int du_rgb888_pins[] = { 1978 /* R[7:0], G[7:0], B[7:0] */ 1979 RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 19), 1980 RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16), 1981 RCAR_GP_PIN(4, 29), RCAR_GP_PIN(4, 28), RCAR_GP_PIN(5, 4), 1982 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 7), 1983 RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27), RCAR_GP_PIN(5, 1), 1984 RCAR_GP_PIN(4, 31), RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 12), 1985 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 9), 1986 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 5), 1987 }; 1988 static const unsigned int du_rgb888_mux[] = { 1989 DU2_DR7_MARK, DU2_DR6_MARK, DU2_DR5_MARK, DU2_DR4_MARK, 1990 DU2_DR3_MARK, DU2_DR2_MARK, DU2_DR1_MARK, DU2_DR0_MARK, 1991 DU2_DG7_MARK, DU2_DG6_MARK, DU2_DG5_MARK, DU2_DG4_MARK, 1992 DU2_DG3_MARK, DU2_DG2_MARK, DU2_DG1_MARK, DU2_DG0_MARK, 1993 DU2_DB7_MARK, DU2_DB6_MARK, DU2_DB5_MARK, DU2_DB4_MARK, 1994 DU2_DB3_MARK, DU2_DB2_MARK, DU2_DB1_MARK, DU2_DB0_MARK, 1995 }; 1996 static const unsigned int du_clk_out_0_pins[] = { 1997 /* CLKOUT */ 1998 RCAR_GP_PIN(5, 2), 1999 }; 2000 static const unsigned int du_clk_out_0_mux[] = { 2001 DU0_DOTCLKOUT_MARK 2002 }; 2003 static const unsigned int du_clk_out_1_pins[] = { 2004 /* CLKOUT */ 2005 RCAR_GP_PIN(5, 3), 2006 }; 2007 static const unsigned int du_clk_out_1_mux[] = { 2008 DU1_DOTCLKOUT_MARK 2009 }; 2010 static const unsigned int du_sync_0_pins[] = { 2011 /* VSYNC, HSYNC, DISP */ 2012 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(5, 0), 2013 }; 2014 static const unsigned int du_sync_0_mux[] = { 2015 DU2_EXVSYNC_DU2_VSYNC_MARK, DU2_EXHSYNC_DU2_HSYNC_MARK, 2016 DU2_EXODDF_DU2_ODDF_DISP_CDE_MARK 2017 }; 2018 static const unsigned int du_sync_1_pins[] = { 2019 /* VSYNC, HSYNC, DISP */ 2020 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(5, 16), 2021 }; 2022 static const unsigned int du_sync_1_mux[] = { 2023 DU2_EXVSYNC_DU2_VSYNC_MARK, DU2_EXHSYNC_DU2_HSYNC_MARK, 2024 DU2_DISP_MARK 2025 }; 2026 static const unsigned int du_cde_pins[] = { 2027 /* CDE */ 2028 RCAR_GP_PIN(5, 17), 2029 }; 2030 static const unsigned int du_cde_mux[] = { 2031 DU2_CDE_MARK, 2032 }; 2033 /* - DU0 -------------------------------------------------------------------- */ 2034 static const unsigned int du0_clk_in_pins[] = { 2035 /* CLKIN */ 2036 RCAR_GP_PIN(5, 26), 2037 }; 2038 static const unsigned int du0_clk_in_mux[] = { 2039 DU_DOTCLKIN0_MARK 2040 }; 2041 /* - DU1 -------------------------------------------------------------------- */ 2042 static const unsigned int du1_clk_in_pins[] = { 2043 /* CLKIN */ 2044 RCAR_GP_PIN(5, 27), 2045 }; 2046 static const unsigned int du1_clk_in_mux[] = { 2047 DU_DOTCLKIN1_MARK, 2048 }; 2049 /* - DU2 -------------------------------------------------------------------- */ 2050 static const unsigned int du2_clk_in_pins[] = { 2051 /* CLKIN */ 2052 RCAR_GP_PIN(5, 28), 2053 }; 2054 static const unsigned int du2_clk_in_mux[] = { 2055 DU_DOTCLKIN2_MARK, 2056 }; 2057 /* - ETH -------------------------------------------------------------------- */ 2058 static const unsigned int eth_link_pins[] = { 2059 /* LINK */ 2060 RCAR_GP_PIN(2, 22), 2061 }; 2062 static const unsigned int eth_link_mux[] = { 2063 ETH_LINK_MARK, 2064 }; 2065 static const unsigned int eth_magic_pins[] = { 2066 /* MAGIC */ 2067 RCAR_GP_PIN(2, 27), 2068 }; 2069 static const unsigned int eth_magic_mux[] = { 2070 ETH_MAGIC_MARK, 2071 }; 2072 static const unsigned int eth_mdio_pins[] = { 2073 /* MDC, MDIO */ 2074 RCAR_GP_PIN(2, 29), RCAR_GP_PIN(2, 24), 2075 }; 2076 static const unsigned int eth_mdio_mux[] = { 2077 ETH_MDC_MARK, ETH_MDIO_MARK, 2078 }; 2079 static const unsigned int eth_rmii_pins[] = { 2080 /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */ 2081 RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 19), 2082 RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 28), RCAR_GP_PIN(2, 25), 2083 RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 23), 2084 }; 2085 static const unsigned int eth_rmii_mux[] = { 2086 ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK, 2087 ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REF_CLK_MARK, 2088 }; 2089 /* - HSCIF0 ----------------------------------------------------------------- */ 2090 static const unsigned int hscif0_data_pins[] = { 2091 /* RX, TX */ 2092 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9), 2093 }; 2094 static const unsigned int hscif0_data_mux[] = { 2095 HRX0_MARK, HTX0_MARK, 2096 }; 2097 static const unsigned int hscif0_clk_pins[] = { 2098 /* SCK */ 2099 RCAR_GP_PIN(5, 7), 2100 }; 2101 static const unsigned int hscif0_clk_mux[] = { 2102 HSCK0_MARK, 2103 }; 2104 static const unsigned int hscif0_ctrl_pins[] = { 2105 /* RTS, CTS */ 2106 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10), 2107 }; 2108 static const unsigned int hscif0_ctrl_mux[] = { 2109 HRTS0_N_MARK, HCTS0_N_MARK, 2110 }; 2111 static const unsigned int hscif0_data_b_pins[] = { 2112 /* RX, TX */ 2113 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 12), 2114 }; 2115 static const unsigned int hscif0_data_b_mux[] = { 2116 HRX0_B_MARK, HTX0_B_MARK, 2117 }; 2118 static const unsigned int hscif0_ctrl_b_pins[] = { 2119 /* RTS, CTS */ 2120 RCAR_GP_PIN(1, 29), RCAR_GP_PIN(1, 28), 2121 }; 2122 static const unsigned int hscif0_ctrl_b_mux[] = { 2123 HRTS0_N_B_MARK, HCTS0_N_B_MARK, 2124 }; 2125 static const unsigned int hscif0_data_c_pins[] = { 2126 /* RX, TX */ 2127 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 16), 2128 }; 2129 static const unsigned int hscif0_data_c_mux[] = { 2130 HRX0_C_MARK, HTX0_C_MARK, 2131 }; 2132 static const unsigned int hscif0_ctrl_c_pins[] = { 2133 /* RTS, CTS */ 2134 RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 7), 2135 }; 2136 static const unsigned int hscif0_ctrl_c_mux[] = { 2137 HRTS0_N_C_MARK, HCTS0_N_C_MARK, 2138 }; 2139 static const unsigned int hscif0_data_d_pins[] = { 2140 /* RX, TX */ 2141 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21), 2142 }; 2143 static const unsigned int hscif0_data_d_mux[] = { 2144 HRX0_D_MARK, HTX0_D_MARK, 2145 }; 2146 static const unsigned int hscif0_ctrl_d_pins[] = { 2147 /* RTS, CTS */ 2148 RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 22), 2149 }; 2150 static const unsigned int hscif0_ctrl_d_mux[] = { 2151 HRTS0_N_D_MARK, HCTS0_N_D_MARK, 2152 }; 2153 static const unsigned int hscif0_data_e_pins[] = { 2154 /* RX, TX */ 2155 RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22), 2156 }; 2157 static const unsigned int hscif0_data_e_mux[] = { 2158 HRX0_E_MARK, HTX0_E_MARK, 2159 }; 2160 static const unsigned int hscif0_ctrl_e_pins[] = { 2161 /* RTS, CTS */ 2162 RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 23), 2163 }; 2164 static const unsigned int hscif0_ctrl_e_mux[] = { 2165 HRTS0_N_E_MARK, HCTS0_N_E_MARK, 2166 }; 2167 static const unsigned int hscif0_data_f_pins[] = { 2168 /* RX, TX */ 2169 RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 25), 2170 }; 2171 static const unsigned int hscif0_data_f_mux[] = { 2172 HRX0_F_MARK, HTX0_F_MARK, 2173 }; 2174 static const unsigned int hscif0_ctrl_f_pins[] = { 2175 /* RTS, CTS */ 2176 RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 24), 2177 }; 2178 static const unsigned int hscif0_ctrl_f_mux[] = { 2179 HRTS0_N_F_MARK, HCTS0_N_F_MARK, 2180 }; 2181 /* - HSCIF1 ----------------------------------------------------------------- */ 2182 static const unsigned int hscif1_data_pins[] = { 2183 /* RX, TX */ 2184 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29), 2185 }; 2186 static const unsigned int hscif1_data_mux[] = { 2187 HRX1_MARK, HTX1_MARK, 2188 }; 2189 static const unsigned int hscif1_clk_pins[] = { 2190 /* SCK */ 2191 RCAR_GP_PIN(4, 27), 2192 }; 2193 static const unsigned int hscif1_clk_mux[] = { 2194 HSCK1_MARK, 2195 }; 2196 static const unsigned int hscif1_ctrl_pins[] = { 2197 /* RTS, CTS */ 2198 RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30), 2199 }; 2200 static const unsigned int hscif1_ctrl_mux[] = { 2201 HRTS1_N_MARK, HCTS1_N_MARK, 2202 }; 2203 static const unsigned int hscif1_data_b_pins[] = { 2204 /* RX, TX */ 2205 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 18), 2206 }; 2207 static const unsigned int hscif1_data_b_mux[] = { 2208 HRX1_B_MARK, HTX1_B_MARK, 2209 }; 2210 static const unsigned int hscif1_clk_b_pins[] = { 2211 /* SCK */ 2212 RCAR_GP_PIN(1, 28), 2213 }; 2214 static const unsigned int hscif1_clk_b_mux[] = { 2215 HSCK1_B_MARK, 2216 }; 2217 static const unsigned int hscif1_ctrl_b_pins[] = { 2218 /* RTS, CTS */ 2219 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), 2220 }; 2221 static const unsigned int hscif1_ctrl_b_mux[] = { 2222 HRTS1_N_B_MARK, HCTS1_N_B_MARK, 2223 }; 2224 /* - I2C0 ------------------------------------------------------------------- */ 2225 static const unsigned int i2c0_pins[] = { 2226 /* SCL, SDA */ 2227 PIN_IIC0_SCL, PIN_IIC0_SDA, 2228 }; 2229 static const unsigned int i2c0_mux[] = { 2230 I2C0_SCL_MARK, I2C0_SDA_MARK, 2231 }; 2232 /* - I2C1 ------------------------------------------------------------------- */ 2233 static const unsigned int i2c1_pins[] = { 2234 /* SCL, SDA */ 2235 RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17), 2236 }; 2237 static const unsigned int i2c1_mux[] = { 2238 I2C1_SCL_MARK, I2C1_SDA_MARK, 2239 }; 2240 static const unsigned int i2c1_b_pins[] = { 2241 /* SCL, SDA */ 2242 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), 2243 }; 2244 static const unsigned int i2c1_b_mux[] = { 2245 I2C1_SCL_B_MARK, I2C1_SDA_B_MARK, 2246 }; 2247 static const unsigned int i2c1_c_pins[] = { 2248 /* SCL, SDA */ 2249 RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27), 2250 }; 2251 static const unsigned int i2c1_c_mux[] = { 2252 I2C1_SCL_C_MARK, I2C1_SDA_C_MARK, 2253 }; 2254 /* - I2C2 ------------------------------------------------------------------- */ 2255 static const unsigned int i2c2_pins[] = { 2256 /* SCL, SDA */ 2257 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6), 2258 }; 2259 static const unsigned int i2c2_mux[] = { 2260 I2C2_SCL_MARK, I2C2_SDA_MARK, 2261 }; 2262 static const unsigned int i2c2_b_pins[] = { 2263 /* SCL, SDA */ 2264 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1), 2265 }; 2266 static const unsigned int i2c2_b_mux[] = { 2267 I2C2_SCL_B_MARK, I2C2_SDA_B_MARK, 2268 }; 2269 static const unsigned int i2c2_c_pins[] = { 2270 /* SCL, SDA */ 2271 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), 2272 }; 2273 static const unsigned int i2c2_c_mux[] = { 2274 I2C2_SCL_C_MARK, I2C2_SDA_C_MARK, 2275 }; 2276 static const unsigned int i2c2_d_pins[] = { 2277 /* SCL, SDA */ 2278 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), 2279 }; 2280 static const unsigned int i2c2_d_mux[] = { 2281 I2C2_SCL_D_MARK, I2C2_SDA_D_MARK, 2282 }; 2283 static const unsigned int i2c2_e_pins[] = { 2284 /* SCL, SDA */ 2285 RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19), 2286 }; 2287 static const unsigned int i2c2_e_mux[] = { 2288 I2C2_SCL_E_MARK, I2C2_SDA_E_MARK, 2289 }; 2290 /* - I2C3 ------------------------------------------------------------------- */ 2291 static const unsigned int i2c3_pins[] = { 2292 /* SCL, SDA */ 2293 PIN_IIC3_SCL, PIN_IIC3_SDA, 2294 }; 2295 static const unsigned int i2c3_mux[] = { 2296 I2C3_SCL_MARK, I2C3_SDA_MARK, 2297 }; 2298 /* - IIC0 (I2C4) ------------------------------------------------------------ */ 2299 static const unsigned int iic0_pins[] = { 2300 /* SCL, SDA */ 2301 PIN_IIC0_SCL, PIN_IIC0_SDA, 2302 }; 2303 static const unsigned int iic0_mux[] = { 2304 IIC0_SCL_MARK, IIC0_SDA_MARK, 2305 }; 2306 /* - IIC1 (I2C5) ------------------------------------------------------------ */ 2307 static const unsigned int iic1_pins[] = { 2308 /* SCL, SDA */ 2309 RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17), 2310 }; 2311 static const unsigned int iic1_mux[] = { 2312 IIC1_SCL_MARK, IIC1_SDA_MARK, 2313 }; 2314 static const unsigned int iic1_b_pins[] = { 2315 /* SCL, SDA */ 2316 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), 2317 }; 2318 static const unsigned int iic1_b_mux[] = { 2319 IIC1_SCL_B_MARK, IIC1_SDA_B_MARK, 2320 }; 2321 static const unsigned int iic1_c_pins[] = { 2322 /* SCL, SDA */ 2323 RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27), 2324 }; 2325 static const unsigned int iic1_c_mux[] = { 2326 IIC1_SCL_C_MARK, IIC1_SDA_C_MARK, 2327 }; 2328 /* - IIC2 (I2C6) ------------------------------------------------------------ */ 2329 static const unsigned int iic2_pins[] = { 2330 /* SCL, SDA */ 2331 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6), 2332 }; 2333 static const unsigned int iic2_mux[] = { 2334 IIC2_SCL_MARK, IIC2_SDA_MARK, 2335 }; 2336 static const unsigned int iic2_b_pins[] = { 2337 /* SCL, SDA */ 2338 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1), 2339 }; 2340 static const unsigned int iic2_b_mux[] = { 2341 IIC2_SCL_B_MARK, IIC2_SDA_B_MARK, 2342 }; 2343 static const unsigned int iic2_c_pins[] = { 2344 /* SCL, SDA */ 2345 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), 2346 }; 2347 static const unsigned int iic2_c_mux[] = { 2348 IIC2_SCL_C_MARK, IIC2_SDA_C_MARK, 2349 }; 2350 static const unsigned int iic2_d_pins[] = { 2351 /* SCL, SDA */ 2352 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), 2353 }; 2354 static const unsigned int iic2_d_mux[] = { 2355 IIC2_SCL_D_MARK, IIC2_SDA_D_MARK, 2356 }; 2357 static const unsigned int iic2_e_pins[] = { 2358 /* SCL, SDA */ 2359 RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19), 2360 }; 2361 static const unsigned int iic2_e_mux[] = { 2362 IIC2_SCL_E_MARK, IIC2_SDA_E_MARK, 2363 }; 2364 /* - IIC3 (I2C7) ------------------------------------------------------------ */ 2365 static const unsigned int iic3_pins[] = { 2366 /* SCL, SDA */ 2367 PIN_IIC3_SCL, PIN_IIC3_SDA, 2368 }; 2369 static const unsigned int iic3_mux[] = { 2370 IIC3_SCL_MARK, IIC3_SDA_MARK, 2371 }; 2372 /* - INTC ------------------------------------------------------------------- */ 2373 static const unsigned int intc_irq0_pins[] = { 2374 /* IRQ */ 2375 RCAR_GP_PIN(1, 25), 2376 }; 2377 static const unsigned int intc_irq0_mux[] = { 2378 IRQ0_MARK, 2379 }; 2380 static const unsigned int intc_irq1_pins[] = { 2381 /* IRQ */ 2382 RCAR_GP_PIN(1, 27), 2383 }; 2384 static const unsigned int intc_irq1_mux[] = { 2385 IRQ1_MARK, 2386 }; 2387 static const unsigned int intc_irq2_pins[] = { 2388 /* IRQ */ 2389 RCAR_GP_PIN(1, 29), 2390 }; 2391 static const unsigned int intc_irq2_mux[] = { 2392 IRQ2_MARK, 2393 }; 2394 static const unsigned int intc_irq3_pins[] = { 2395 /* IRQ */ 2396 RCAR_GP_PIN(1, 23), 2397 }; 2398 static const unsigned int intc_irq3_mux[] = { 2399 IRQ3_MARK, 2400 }; 2401 2402 #ifdef CONFIG_PINCTRL_PFC_R8A7790 2403 /* - MLB+ ------------------------------------------------------------------- */ 2404 static const unsigned int mlb_3pin_pins[] = { 2405 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2), 2406 }; 2407 static const unsigned int mlb_3pin_mux[] = { 2408 MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK, 2409 }; 2410 #endif /* CONFIG_PINCTRL_PFC_R8A7790 */ 2411 2412 /* - MMCIF0 ----------------------------------------------------------------- */ 2413 static const unsigned int mmc0_data1_pins[] = { 2414 /* D[0] */ 2415 RCAR_GP_PIN(3, 18), 2416 }; 2417 static const unsigned int mmc0_data1_mux[] = { 2418 MMC0_D0_MARK, 2419 }; 2420 static const unsigned int mmc0_data4_pins[] = { 2421 /* D[0:3] */ 2422 RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), 2423 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21), 2424 }; 2425 static const unsigned int mmc0_data4_mux[] = { 2426 MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK, 2427 }; 2428 static const unsigned int mmc0_data8_pins[] = { 2429 /* D[0:7] */ 2430 RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), 2431 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21), 2432 RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23), 2433 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), 2434 }; 2435 static const unsigned int mmc0_data8_mux[] = { 2436 MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK, 2437 MMC0_D4_MARK, MMC0_D5_MARK, MMC0_D6_MARK, MMC0_D7_MARK, 2438 }; 2439 static const unsigned int mmc0_ctrl_pins[] = { 2440 /* CLK, CMD */ 2441 RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17), 2442 }; 2443 static const unsigned int mmc0_ctrl_mux[] = { 2444 MMC0_CLK_MARK, MMC0_CMD_MARK, 2445 }; 2446 /* - MMCIF1 ----------------------------------------------------------------- */ 2447 static const unsigned int mmc1_data1_pins[] = { 2448 /* D[0] */ 2449 RCAR_GP_PIN(3, 26), 2450 }; 2451 static const unsigned int mmc1_data1_mux[] = { 2452 MMC1_D0_MARK, 2453 }; 2454 static const unsigned int mmc1_data4_pins[] = { 2455 /* D[0:3] */ 2456 RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27), 2457 RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29), 2458 }; 2459 static const unsigned int mmc1_data4_mux[] = { 2460 MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK, 2461 }; 2462 static const unsigned int mmc1_data8_pins[] = { 2463 /* D[0:7] */ 2464 RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27), 2465 RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29), 2466 RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31), 2467 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), 2468 }; 2469 static const unsigned int mmc1_data8_mux[] = { 2470 MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK, 2471 MMC1_D4_MARK, MMC1_D5_MARK, MMC1_D6_MARK, MMC1_D7_MARK, 2472 }; 2473 static const unsigned int mmc1_ctrl_pins[] = { 2474 /* CLK, CMD */ 2475 RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25), 2476 }; 2477 static const unsigned int mmc1_ctrl_mux[] = { 2478 MMC1_CLK_MARK, MMC1_CMD_MARK, 2479 }; 2480 /* - MSIOF0 ----------------------------------------------------------------- */ 2481 static const unsigned int msiof0_clk_pins[] = { 2482 /* SCK */ 2483 RCAR_GP_PIN(5, 12), 2484 }; 2485 static const unsigned int msiof0_clk_mux[] = { 2486 MSIOF0_SCK_MARK, 2487 }; 2488 static const unsigned int msiof0_sync_pins[] = { 2489 /* SYNC */ 2490 RCAR_GP_PIN(5, 13), 2491 }; 2492 static const unsigned int msiof0_sync_mux[] = { 2493 MSIOF0_SYNC_MARK, 2494 }; 2495 static const unsigned int msiof0_ss1_pins[] = { 2496 /* SS1 */ 2497 RCAR_GP_PIN(5, 14), 2498 }; 2499 static const unsigned int msiof0_ss1_mux[] = { 2500 MSIOF0_SS1_MARK, 2501 }; 2502 static const unsigned int msiof0_ss2_pins[] = { 2503 /* SS2 */ 2504 RCAR_GP_PIN(5, 16), 2505 }; 2506 static const unsigned int msiof0_ss2_mux[] = { 2507 MSIOF0_SS2_MARK, 2508 }; 2509 static const unsigned int msiof0_rx_pins[] = { 2510 /* RXD */ 2511 RCAR_GP_PIN(5, 17), 2512 }; 2513 static const unsigned int msiof0_rx_mux[] = { 2514 MSIOF0_RXD_MARK, 2515 }; 2516 static const unsigned int msiof0_tx_pins[] = { 2517 /* TXD */ 2518 RCAR_GP_PIN(5, 15), 2519 }; 2520 static const unsigned int msiof0_tx_mux[] = { 2521 MSIOF0_TXD_MARK, 2522 }; 2523 2524 static const unsigned int msiof0_clk_b_pins[] = { 2525 /* SCK */ 2526 RCAR_GP_PIN(1, 23), 2527 }; 2528 static const unsigned int msiof0_clk_b_mux[] = { 2529 MSIOF0_SCK_B_MARK, 2530 }; 2531 static const unsigned int msiof0_ss1_b_pins[] = { 2532 /* SS1 */ 2533 RCAR_GP_PIN(1, 12), 2534 }; 2535 static const unsigned int msiof0_ss1_b_mux[] = { 2536 MSIOF0_SS1_B_MARK, 2537 }; 2538 static const unsigned int msiof0_ss2_b_pins[] = { 2539 /* SS2 */ 2540 RCAR_GP_PIN(1, 10), 2541 }; 2542 static const unsigned int msiof0_ss2_b_mux[] = { 2543 MSIOF0_SS2_B_MARK, 2544 }; 2545 static const unsigned int msiof0_rx_b_pins[] = { 2546 /* RXD */ 2547 RCAR_GP_PIN(1, 29), 2548 }; 2549 static const unsigned int msiof0_rx_b_mux[] = { 2550 MSIOF0_RXD_B_MARK, 2551 }; 2552 static const unsigned int msiof0_tx_b_pins[] = { 2553 /* TXD */ 2554 RCAR_GP_PIN(1, 28), 2555 }; 2556 static const unsigned int msiof0_tx_b_mux[] = { 2557 MSIOF0_TXD_B_MARK, 2558 }; 2559 /* - MSIOF1 ----------------------------------------------------------------- */ 2560 static const unsigned int msiof1_clk_pins[] = { 2561 /* SCK */ 2562 RCAR_GP_PIN(4, 8), 2563 }; 2564 static const unsigned int msiof1_clk_mux[] = { 2565 MSIOF1_SCK_MARK, 2566 }; 2567 static const unsigned int msiof1_sync_pins[] = { 2568 /* SYNC */ 2569 RCAR_GP_PIN(4, 9), 2570 }; 2571 static const unsigned int msiof1_sync_mux[] = { 2572 MSIOF1_SYNC_MARK, 2573 }; 2574 static const unsigned int msiof1_ss1_pins[] = { 2575 /* SS1 */ 2576 RCAR_GP_PIN(4, 10), 2577 }; 2578 static const unsigned int msiof1_ss1_mux[] = { 2579 MSIOF1_SS1_MARK, 2580 }; 2581 static const unsigned int msiof1_ss2_pins[] = { 2582 /* SS2 */ 2583 RCAR_GP_PIN(4, 11), 2584 }; 2585 static const unsigned int msiof1_ss2_mux[] = { 2586 MSIOF1_SS2_MARK, 2587 }; 2588 static const unsigned int msiof1_rx_pins[] = { 2589 /* RXD */ 2590 RCAR_GP_PIN(4, 13), 2591 }; 2592 static const unsigned int msiof1_rx_mux[] = { 2593 MSIOF1_RXD_MARK, 2594 }; 2595 static const unsigned int msiof1_tx_pins[] = { 2596 /* TXD */ 2597 RCAR_GP_PIN(4, 12), 2598 }; 2599 static const unsigned int msiof1_tx_mux[] = { 2600 MSIOF1_TXD_MARK, 2601 }; 2602 2603 static const unsigned int msiof1_clk_b_pins[] = { 2604 /* SCK */ 2605 RCAR_GP_PIN(1, 16), 2606 }; 2607 static const unsigned int msiof1_clk_b_mux[] = { 2608 MSIOF1_SCK_B_MARK, 2609 }; 2610 static const unsigned int msiof1_ss1_b_pins[] = { 2611 /* SS1 */ 2612 RCAR_GP_PIN(0, 18), 2613 }; 2614 static const unsigned int msiof1_ss1_b_mux[] = { 2615 MSIOF1_SS1_B_MARK, 2616 }; 2617 static const unsigned int msiof1_ss2_b_pins[] = { 2618 /* SS2 */ 2619 RCAR_GP_PIN(0, 19), 2620 }; 2621 static const unsigned int msiof1_ss2_b_mux[] = { 2622 MSIOF1_SS2_B_MARK, 2623 }; 2624 static const unsigned int msiof1_rx_b_pins[] = { 2625 /* RXD */ 2626 RCAR_GP_PIN(1, 17), 2627 }; 2628 static const unsigned int msiof1_rx_b_mux[] = { 2629 MSIOF1_RXD_B_MARK, 2630 }; 2631 static const unsigned int msiof1_tx_b_pins[] = { 2632 /* TXD */ 2633 RCAR_GP_PIN(0, 20), 2634 }; 2635 static const unsigned int msiof1_tx_b_mux[] = { 2636 MSIOF1_TXD_B_MARK, 2637 }; 2638 /* - MSIOF2 ----------------------------------------------------------------- */ 2639 static const unsigned int msiof2_clk_pins[] = { 2640 /* SCK */ 2641 RCAR_GP_PIN(0, 27), 2642 }; 2643 static const unsigned int msiof2_clk_mux[] = { 2644 MSIOF2_SCK_MARK, 2645 }; 2646 static const unsigned int msiof2_sync_pins[] = { 2647 /* SYNC */ 2648 RCAR_GP_PIN(0, 26), 2649 }; 2650 static const unsigned int msiof2_sync_mux[] = { 2651 MSIOF2_SYNC_MARK, 2652 }; 2653 static const unsigned int msiof2_ss1_pins[] = { 2654 /* SS1 */ 2655 RCAR_GP_PIN(0, 30), 2656 }; 2657 static const unsigned int msiof2_ss1_mux[] = { 2658 MSIOF2_SS1_MARK, 2659 }; 2660 static const unsigned int msiof2_ss2_pins[] = { 2661 /* SS2 */ 2662 RCAR_GP_PIN(0, 31), 2663 }; 2664 static const unsigned int msiof2_ss2_mux[] = { 2665 MSIOF2_SS2_MARK, 2666 }; 2667 static const unsigned int msiof2_rx_pins[] = { 2668 /* RXD */ 2669 RCAR_GP_PIN(0, 29), 2670 }; 2671 static const unsigned int msiof2_rx_mux[] = { 2672 MSIOF2_RXD_MARK, 2673 }; 2674 static const unsigned int msiof2_tx_pins[] = { 2675 /* TXD */ 2676 RCAR_GP_PIN(0, 28), 2677 }; 2678 static const unsigned int msiof2_tx_mux[] = { 2679 MSIOF2_TXD_MARK, 2680 }; 2681 /* - MSIOF3 ----------------------------------------------------------------- */ 2682 static const unsigned int msiof3_clk_pins[] = { 2683 /* SCK */ 2684 RCAR_GP_PIN(5, 4), 2685 }; 2686 static const unsigned int msiof3_clk_mux[] = { 2687 MSIOF3_SCK_MARK, 2688 }; 2689 static const unsigned int msiof3_sync_pins[] = { 2690 /* SYNC */ 2691 RCAR_GP_PIN(4, 30), 2692 }; 2693 static const unsigned int msiof3_sync_mux[] = { 2694 MSIOF3_SYNC_MARK, 2695 }; 2696 static const unsigned int msiof3_ss1_pins[] = { 2697 /* SS1 */ 2698 RCAR_GP_PIN(4, 31), 2699 }; 2700 static const unsigned int msiof3_ss1_mux[] = { 2701 MSIOF3_SS1_MARK, 2702 }; 2703 static const unsigned int msiof3_ss2_pins[] = { 2704 /* SS2 */ 2705 RCAR_GP_PIN(4, 27), 2706 }; 2707 static const unsigned int msiof3_ss2_mux[] = { 2708 MSIOF3_SS2_MARK, 2709 }; 2710 static const unsigned int msiof3_rx_pins[] = { 2711 /* RXD */ 2712 RCAR_GP_PIN(5, 2), 2713 }; 2714 static const unsigned int msiof3_rx_mux[] = { 2715 MSIOF3_RXD_MARK, 2716 }; 2717 static const unsigned int msiof3_tx_pins[] = { 2718 /* TXD */ 2719 RCAR_GP_PIN(5, 3), 2720 }; 2721 static const unsigned int msiof3_tx_mux[] = { 2722 MSIOF3_TXD_MARK, 2723 }; 2724 2725 static const unsigned int msiof3_clk_b_pins[] = { 2726 /* SCK */ 2727 RCAR_GP_PIN(0, 0), 2728 }; 2729 static const unsigned int msiof3_clk_b_mux[] = { 2730 MSIOF3_SCK_B_MARK, 2731 }; 2732 static const unsigned int msiof3_sync_b_pins[] = { 2733 /* SYNC */ 2734 RCAR_GP_PIN(0, 1), 2735 }; 2736 static const unsigned int msiof3_sync_b_mux[] = { 2737 MSIOF3_SYNC_B_MARK, 2738 }; 2739 static const unsigned int msiof3_rx_b_pins[] = { 2740 /* RXD */ 2741 RCAR_GP_PIN(0, 2), 2742 }; 2743 static const unsigned int msiof3_rx_b_mux[] = { 2744 MSIOF3_RXD_B_MARK, 2745 }; 2746 static const unsigned int msiof3_tx_b_pins[] = { 2747 /* TXD */ 2748 RCAR_GP_PIN(0, 3), 2749 }; 2750 static const unsigned int msiof3_tx_b_mux[] = { 2751 MSIOF3_TXD_B_MARK, 2752 }; 2753 /* - PWM -------------------------------------------------------------------- */ 2754 static const unsigned int pwm0_pins[] = { 2755 RCAR_GP_PIN(5, 29), 2756 }; 2757 static const unsigned int pwm0_mux[] = { 2758 PWM0_MARK, 2759 }; 2760 static const unsigned int pwm0_b_pins[] = { 2761 RCAR_GP_PIN(4, 30), 2762 }; 2763 static const unsigned int pwm0_b_mux[] = { 2764 PWM0_B_MARK, 2765 }; 2766 static const unsigned int pwm1_pins[] = { 2767 RCAR_GP_PIN(5, 30), 2768 }; 2769 static const unsigned int pwm1_mux[] = { 2770 PWM1_MARK, 2771 }; 2772 static const unsigned int pwm1_b_pins[] = { 2773 RCAR_GP_PIN(4, 31), 2774 }; 2775 static const unsigned int pwm1_b_mux[] = { 2776 PWM1_B_MARK, 2777 }; 2778 static const unsigned int pwm2_pins[] = { 2779 RCAR_GP_PIN(5, 31), 2780 }; 2781 static const unsigned int pwm2_mux[] = { 2782 PWM2_MARK, 2783 }; 2784 static const unsigned int pwm3_pins[] = { 2785 RCAR_GP_PIN(0, 16), 2786 }; 2787 static const unsigned int pwm3_mux[] = { 2788 PWM3_MARK, 2789 }; 2790 static const unsigned int pwm4_pins[] = { 2791 RCAR_GP_PIN(0, 17), 2792 }; 2793 static const unsigned int pwm4_mux[] = { 2794 PWM4_MARK, 2795 }; 2796 static const unsigned int pwm5_pins[] = { 2797 RCAR_GP_PIN(0, 18), 2798 }; 2799 static const unsigned int pwm5_mux[] = { 2800 PWM5_MARK, 2801 }; 2802 static const unsigned int pwm6_pins[] = { 2803 RCAR_GP_PIN(0, 19), 2804 }; 2805 static const unsigned int pwm6_mux[] = { 2806 PWM6_MARK, 2807 }; 2808 /* - QSPI ------------------------------------------------------------------- */ 2809 static const unsigned int qspi_ctrl_pins[] = { 2810 /* SPCLK, SSL */ 2811 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 9), 2812 }; 2813 static const unsigned int qspi_ctrl_mux[] = { 2814 SPCLK_MARK, SSL_MARK, 2815 }; 2816 static const unsigned int qspi_data2_pins[] = { 2817 /* MOSI_IO0, MISO_IO1 */ 2818 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), 2819 }; 2820 static const unsigned int qspi_data2_mux[] = { 2821 MOSI_IO0_MARK, MISO_IO1_MARK, 2822 }; 2823 static const unsigned int qspi_data4_pins[] = { 2824 /* MOSI_IO0, MISO_IO1, IO2, IO3 */ 2825 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 2826 RCAR_GP_PIN(1, 8), 2827 }; 2828 static const unsigned int qspi_data4_mux[] = { 2829 MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK, 2830 }; 2831 /* - SCIF0 ------------------------------------------------------------------ */ 2832 static const unsigned int scif0_data_pins[] = { 2833 /* RX, TX */ 2834 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29), 2835 }; 2836 static const unsigned int scif0_data_mux[] = { 2837 RX0_MARK, TX0_MARK, 2838 }; 2839 static const unsigned int scif0_clk_pins[] = { 2840 /* SCK */ 2841 RCAR_GP_PIN(4, 27), 2842 }; 2843 static const unsigned int scif0_clk_mux[] = { 2844 SCK0_MARK, 2845 }; 2846 static const unsigned int scif0_ctrl_pins[] = { 2847 /* RTS, CTS */ 2848 RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30), 2849 }; 2850 static const unsigned int scif0_ctrl_mux[] = { 2851 RTS0_N_MARK, CTS0_N_MARK, 2852 }; 2853 static const unsigned int scif0_data_b_pins[] = { 2854 /* RX, TX */ 2855 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), 2856 }; 2857 static const unsigned int scif0_data_b_mux[] = { 2858 RX0_B_MARK, TX0_B_MARK, 2859 }; 2860 /* - SCIF1 ------------------------------------------------------------------ */ 2861 static const unsigned int scif1_data_pins[] = { 2862 /* RX, TX */ 2863 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1), 2864 }; 2865 static const unsigned int scif1_data_mux[] = { 2866 RX1_MARK, TX1_MARK, 2867 }; 2868 static const unsigned int scif1_clk_pins[] = { 2869 /* SCK */ 2870 RCAR_GP_PIN(4, 20), 2871 }; 2872 static const unsigned int scif1_clk_mux[] = { 2873 SCK1_MARK, 2874 }; 2875 static const unsigned int scif1_ctrl_pins[] = { 2876 /* RTS, CTS */ 2877 RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 2), 2878 }; 2879 static const unsigned int scif1_ctrl_mux[] = { 2880 RTS1_N_MARK, CTS1_N_MARK, 2881 }; 2882 static const unsigned int scif1_data_b_pins[] = { 2883 /* RX, TX */ 2884 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), 2885 }; 2886 static const unsigned int scif1_data_b_mux[] = { 2887 RX1_B_MARK, TX1_B_MARK, 2888 }; 2889 static const unsigned int scif1_data_c_pins[] = { 2890 /* RX, TX */ 2891 RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2), 2892 }; 2893 static const unsigned int scif1_data_c_mux[] = { 2894 RX1_C_MARK, TX1_C_MARK, 2895 }; 2896 static const unsigned int scif1_data_d_pins[] = { 2897 /* RX, TX */ 2898 RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), 2899 }; 2900 static const unsigned int scif1_data_d_mux[] = { 2901 RX1_D_MARK, TX1_D_MARK, 2902 }; 2903 static const unsigned int scif1_clk_d_pins[] = { 2904 /* SCK */ 2905 RCAR_GP_PIN(3, 17), 2906 }; 2907 static const unsigned int scif1_clk_d_mux[] = { 2908 SCK1_D_MARK, 2909 }; 2910 static const unsigned int scif1_data_e_pins[] = { 2911 /* RX, TX */ 2912 RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22), 2913 }; 2914 static const unsigned int scif1_data_e_mux[] = { 2915 RX1_E_MARK, TX1_E_MARK, 2916 }; 2917 static const unsigned int scif1_clk_e_pins[] = { 2918 /* SCK */ 2919 RCAR_GP_PIN(2, 20), 2920 }; 2921 static const unsigned int scif1_clk_e_mux[] = { 2922 SCK1_E_MARK, 2923 }; 2924 /* - SCIF2 ------------------------------------------------------------------ */ 2925 static const unsigned int scif2_data_pins[] = { 2926 /* RX, TX */ 2927 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 5), 2928 }; 2929 static const unsigned int scif2_data_mux[] = { 2930 RX2_MARK, TX2_MARK, 2931 }; 2932 static const unsigned int scif2_clk_pins[] = { 2933 /* SCK */ 2934 RCAR_GP_PIN(5, 4), 2935 }; 2936 static const unsigned int scif2_clk_mux[] = { 2937 SCK2_MARK, 2938 }; 2939 static const unsigned int scif2_data_b_pins[] = { 2940 /* RX, TX */ 2941 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25), 2942 }; 2943 static const unsigned int scif2_data_b_mux[] = { 2944 RX2_B_MARK, TX2_B_MARK, 2945 }; 2946 /* - SCIFA0 ----------------------------------------------------------------- */ 2947 static const unsigned int scifa0_data_pins[] = { 2948 /* RXD, TXD */ 2949 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29), 2950 }; 2951 static const unsigned int scifa0_data_mux[] = { 2952 SCIFA0_RXD_MARK, SCIFA0_TXD_MARK, 2953 }; 2954 static const unsigned int scifa0_clk_pins[] = { 2955 /* SCK */ 2956 RCAR_GP_PIN(4, 27), 2957 }; 2958 static const unsigned int scifa0_clk_mux[] = { 2959 SCIFA0_SCK_MARK, 2960 }; 2961 static const unsigned int scifa0_ctrl_pins[] = { 2962 /* RTS, CTS */ 2963 RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30), 2964 }; 2965 static const unsigned int scifa0_ctrl_mux[] = { 2966 SCIFA0_RTS_N_MARK, SCIFA0_CTS_N_MARK, 2967 }; 2968 static const unsigned int scifa0_data_b_pins[] = { 2969 /* RXD, TXD */ 2970 RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21), 2971 }; 2972 static const unsigned int scifa0_data_b_mux[] = { 2973 SCIFA0_RXD_B_MARK, SCIFA0_TXD_B_MARK 2974 }; 2975 static const unsigned int scifa0_clk_b_pins[] = { 2976 /* SCK */ 2977 RCAR_GP_PIN(1, 19), 2978 }; 2979 static const unsigned int scifa0_clk_b_mux[] = { 2980 SCIFA0_SCK_B_MARK, 2981 }; 2982 static const unsigned int scifa0_ctrl_b_pins[] = { 2983 /* RTS, CTS */ 2984 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22), 2985 }; 2986 static const unsigned int scifa0_ctrl_b_mux[] = { 2987 SCIFA0_RTS_N_B_MARK, SCIFA0_CTS_N_B_MARK, 2988 }; 2989 /* - SCIFA1 ----------------------------------------------------------------- */ 2990 static const unsigned int scifa1_data_pins[] = { 2991 /* RXD, TXD */ 2992 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1), 2993 }; 2994 static const unsigned int scifa1_data_mux[] = { 2995 SCIFA1_RXD_MARK, SCIFA1_TXD_MARK, 2996 }; 2997 static const unsigned int scifa1_clk_pins[] = { 2998 /* SCK */ 2999 RCAR_GP_PIN(4, 20), 3000 }; 3001 static const unsigned int scifa1_clk_mux[] = { 3002 SCIFA1_SCK_MARK, 3003 }; 3004 static const unsigned int scifa1_ctrl_pins[] = { 3005 /* RTS, CTS */ 3006 RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 2), 3007 }; 3008 static const unsigned int scifa1_ctrl_mux[] = { 3009 SCIFA1_RTS_N_MARK, SCIFA1_CTS_N_MARK, 3010 }; 3011 static const unsigned int scifa1_data_b_pins[] = { 3012 /* RXD, TXD */ 3013 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 21), 3014 }; 3015 static const unsigned int scifa1_data_b_mux[] = { 3016 SCIFA1_RXD_B_MARK, SCIFA1_TXD_B_MARK, 3017 }; 3018 static const unsigned int scifa1_clk_b_pins[] = { 3019 /* SCK */ 3020 RCAR_GP_PIN(0, 23), 3021 }; 3022 static const unsigned int scifa1_clk_b_mux[] = { 3023 SCIFA1_SCK_B_MARK, 3024 }; 3025 static const unsigned int scifa1_ctrl_b_pins[] = { 3026 /* RTS, CTS */ 3027 RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 25), 3028 }; 3029 static const unsigned int scifa1_ctrl_b_mux[] = { 3030 SCIFA1_RTS_N_B_MARK, SCIFA1_CTS_N_B_MARK, 3031 }; 3032 static const unsigned int scifa1_data_c_pins[] = { 3033 /* RXD, TXD */ 3034 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10), 3035 }; 3036 static const unsigned int scifa1_data_c_mux[] = { 3037 SCIFA1_RXD_C_MARK, SCIFA1_TXD_C_MARK, 3038 }; 3039 static const unsigned int scifa1_clk_c_pins[] = { 3040 /* SCK */ 3041 RCAR_GP_PIN(0, 8), 3042 }; 3043 static const unsigned int scifa1_clk_c_mux[] = { 3044 SCIFA1_SCK_C_MARK, 3045 }; 3046 static const unsigned int scifa1_ctrl_c_pins[] = { 3047 /* RTS, CTS */ 3048 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), 3049 }; 3050 static const unsigned int scifa1_ctrl_c_mux[] = { 3051 SCIFA1_RTS_N_C_MARK, SCIFA1_CTS_N_C_MARK, 3052 }; 3053 static const unsigned int scifa1_data_d_pins[] = { 3054 /* RXD, TXD */ 3055 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12), 3056 }; 3057 static const unsigned int scifa1_data_d_mux[] = { 3058 SCIFA1_RXD_D_MARK, SCIFA1_TXD_D_MARK, 3059 }; 3060 static const unsigned int scifa1_clk_d_pins[] = { 3061 /* SCK */ 3062 RCAR_GP_PIN(2, 10), 3063 }; 3064 static const unsigned int scifa1_clk_d_mux[] = { 3065 SCIFA1_SCK_D_MARK, 3066 }; 3067 static const unsigned int scifa1_ctrl_d_pins[] = { 3068 /* RTS, CTS */ 3069 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13), 3070 }; 3071 static const unsigned int scifa1_ctrl_d_mux[] = { 3072 SCIFA1_RTS_N_D_MARK, SCIFA1_CTS_N_D_MARK, 3073 }; 3074 /* - SCIFA2 ----------------------------------------------------------------- */ 3075 static const unsigned int scifa2_data_pins[] = { 3076 /* RXD, TXD */ 3077 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6), 3078 }; 3079 static const unsigned int scifa2_data_mux[] = { 3080 SCIFA2_RXD_MARK, SCIFA2_TXD_MARK, 3081 }; 3082 static const unsigned int scifa2_clk_pins[] = { 3083 /* SCK */ 3084 RCAR_GP_PIN(5, 4), 3085 }; 3086 static const unsigned int scifa2_clk_mux[] = { 3087 SCIFA2_SCK_MARK, 3088 }; 3089 static const unsigned int scifa2_ctrl_pins[] = { 3090 /* RTS, CTS */ 3091 RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 21), 3092 }; 3093 static const unsigned int scifa2_ctrl_mux[] = { 3094 SCIFA2_RTS_N_MARK, SCIFA2_CTS_N_MARK, 3095 }; 3096 static const unsigned int scifa2_data_b_pins[] = { 3097 /* RXD, TXD */ 3098 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 16), 3099 }; 3100 static const unsigned int scifa2_data_b_mux[] = { 3101 SCIFA2_RXD_B_MARK, SCIFA2_TXD_B_MARK, 3102 }; 3103 static const unsigned int scifa2_data_c_pins[] = { 3104 /* RXD, TXD */ 3105 RCAR_GP_PIN(5, 31), RCAR_GP_PIN(5, 30), 3106 }; 3107 static const unsigned int scifa2_data_c_mux[] = { 3108 SCIFA2_RXD_C_MARK, SCIFA2_TXD_C_MARK, 3109 }; 3110 static const unsigned int scifa2_clk_c_pins[] = { 3111 /* SCK */ 3112 RCAR_GP_PIN(5, 29), 3113 }; 3114 static const unsigned int scifa2_clk_c_mux[] = { 3115 SCIFA2_SCK_C_MARK, 3116 }; 3117 /* - SCIFB0 ----------------------------------------------------------------- */ 3118 static const unsigned int scifb0_data_pins[] = { 3119 /* RXD, TXD */ 3120 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10), 3121 }; 3122 static const unsigned int scifb0_data_mux[] = { 3123 SCIFB0_RXD_MARK, SCIFB0_TXD_MARK, 3124 }; 3125 static const unsigned int scifb0_clk_pins[] = { 3126 /* SCK */ 3127 RCAR_GP_PIN(4, 8), 3128 }; 3129 static const unsigned int scifb0_clk_mux[] = { 3130 SCIFB0_SCK_MARK, 3131 }; 3132 static const unsigned int scifb0_ctrl_pins[] = { 3133 /* RTS, CTS */ 3134 RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 11), 3135 }; 3136 static const unsigned int scifb0_ctrl_mux[] = { 3137 SCIFB0_RTS_N_MARK, SCIFB0_CTS_N_MARK, 3138 }; 3139 static const unsigned int scifb0_data_b_pins[] = { 3140 /* RXD, TXD */ 3141 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), 3142 }; 3143 static const unsigned int scifb0_data_b_mux[] = { 3144 SCIFB0_RXD_B_MARK, SCIFB0_TXD_B_MARK, 3145 }; 3146 static const unsigned int scifb0_clk_b_pins[] = { 3147 /* SCK */ 3148 RCAR_GP_PIN(3, 9), 3149 }; 3150 static const unsigned int scifb0_clk_b_mux[] = { 3151 SCIFB0_SCK_B_MARK, 3152 }; 3153 static const unsigned int scifb0_ctrl_b_pins[] = { 3154 /* RTS, CTS */ 3155 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12), 3156 }; 3157 static const unsigned int scifb0_ctrl_b_mux[] = { 3158 SCIFB0_RTS_N_B_MARK, SCIFB0_CTS_N_B_MARK, 3159 }; 3160 static const unsigned int scifb0_data_c_pins[] = { 3161 /* RXD, TXD */ 3162 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), 3163 }; 3164 static const unsigned int scifb0_data_c_mux[] = { 3165 SCIFB0_RXD_C_MARK, SCIFB0_TXD_C_MARK, 3166 }; 3167 /* - SCIFB1 ----------------------------------------------------------------- */ 3168 static const unsigned int scifb1_data_pins[] = { 3169 /* RXD, TXD */ 3170 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16), 3171 }; 3172 static const unsigned int scifb1_data_mux[] = { 3173 SCIFB1_RXD_MARK, SCIFB1_TXD_MARK, 3174 }; 3175 static const unsigned int scifb1_clk_pins[] = { 3176 /* SCK */ 3177 RCAR_GP_PIN(4, 14), 3178 }; 3179 static const unsigned int scifb1_clk_mux[] = { 3180 SCIFB1_SCK_MARK, 3181 }; 3182 static const unsigned int scifb1_ctrl_pins[] = { 3183 /* RTS, CTS */ 3184 RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17), 3185 }; 3186 static const unsigned int scifb1_ctrl_mux[] = { 3187 SCIFB1_RTS_N_MARK, SCIFB1_CTS_N_MARK, 3188 }; 3189 static const unsigned int scifb1_data_b_pins[] = { 3190 /* RXD, TXD */ 3191 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), 3192 }; 3193 static const unsigned int scifb1_data_b_mux[] = { 3194 SCIFB1_RXD_B_MARK, SCIFB1_TXD_B_MARK, 3195 }; 3196 static const unsigned int scifb1_clk_b_pins[] = { 3197 /* SCK */ 3198 RCAR_GP_PIN(3, 1), 3199 }; 3200 static const unsigned int scifb1_clk_b_mux[] = { 3201 SCIFB1_SCK_B_MARK, 3202 }; 3203 static const unsigned int scifb1_ctrl_b_pins[] = { 3204 /* RTS, CTS */ 3205 RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 4), 3206 }; 3207 static const unsigned int scifb1_ctrl_b_mux[] = { 3208 SCIFB1_RTS_N_B_MARK, SCIFB1_CTS_N_B_MARK, 3209 }; 3210 static const unsigned int scifb1_data_c_pins[] = { 3211 /* RXD, TXD */ 3212 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), 3213 }; 3214 static const unsigned int scifb1_data_c_mux[] = { 3215 SCIFB1_RXD_C_MARK, SCIFB1_TXD_C_MARK, 3216 }; 3217 static const unsigned int scifb1_data_d_pins[] = { 3218 /* RXD, TXD */ 3219 RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2), 3220 }; 3221 static const unsigned int scifb1_data_d_mux[] = { 3222 SCIFB1_RXD_D_MARK, SCIFB1_TXD_D_MARK, 3223 }; 3224 static const unsigned int scifb1_data_e_pins[] = { 3225 /* RXD, TXD */ 3226 RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), 3227 }; 3228 static const unsigned int scifb1_data_e_mux[] = { 3229 SCIFB1_RXD_E_MARK, SCIFB1_TXD_E_MARK, 3230 }; 3231 static const unsigned int scifb1_clk_e_pins[] = { 3232 /* SCK */ 3233 RCAR_GP_PIN(3, 17), 3234 }; 3235 static const unsigned int scifb1_clk_e_mux[] = { 3236 SCIFB1_SCK_E_MARK, 3237 }; 3238 static const unsigned int scifb1_data_f_pins[] = { 3239 /* RXD, TXD */ 3240 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), 3241 }; 3242 static const unsigned int scifb1_data_f_mux[] = { 3243 SCIFB1_RXD_F_MARK, SCIFB1_TXD_F_MARK, 3244 }; 3245 static const unsigned int scifb1_data_g_pins[] = { 3246 /* RXD, TXD */ 3247 RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22), 3248 }; 3249 static const unsigned int scifb1_data_g_mux[] = { 3250 SCIFB1_RXD_G_MARK, SCIFB1_TXD_G_MARK, 3251 }; 3252 static const unsigned int scifb1_clk_g_pins[] = { 3253 /* SCK */ 3254 RCAR_GP_PIN(2, 20), 3255 }; 3256 static const unsigned int scifb1_clk_g_mux[] = { 3257 SCIFB1_SCK_G_MARK, 3258 }; 3259 /* - SCIFB2 ----------------------------------------------------------------- */ 3260 static const unsigned int scifb2_data_pins[] = { 3261 /* RXD, TXD */ 3262 RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23), 3263 }; 3264 static const unsigned int scifb2_data_mux[] = { 3265 SCIFB2_RXD_MARK, SCIFB2_TXD_MARK, 3266 }; 3267 static const unsigned int scifb2_clk_pins[] = { 3268 /* SCK */ 3269 RCAR_GP_PIN(4, 21), 3270 }; 3271 static const unsigned int scifb2_clk_mux[] = { 3272 SCIFB2_SCK_MARK, 3273 }; 3274 static const unsigned int scifb2_ctrl_pins[] = { 3275 /* RTS, CTS */ 3276 RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 24), 3277 }; 3278 static const unsigned int scifb2_ctrl_mux[] = { 3279 SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK, 3280 }; 3281 static const unsigned int scifb2_data_b_pins[] = { 3282 /* RXD, TXD */ 3283 RCAR_GP_PIN(0, 28), RCAR_GP_PIN(0, 30), 3284 }; 3285 static const unsigned int scifb2_data_b_mux[] = { 3286 SCIFB2_RXD_B_MARK, SCIFB2_TXD_B_MARK, 3287 }; 3288 static const unsigned int scifb2_clk_b_pins[] = { 3289 /* SCK */ 3290 RCAR_GP_PIN(0, 31), 3291 }; 3292 static const unsigned int scifb2_clk_b_mux[] = { 3293 SCIFB2_SCK_B_MARK, 3294 }; 3295 static const unsigned int scifb2_ctrl_b_pins[] = { 3296 /* RTS, CTS */ 3297 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(0, 27), 3298 }; 3299 static const unsigned int scifb2_ctrl_b_mux[] = { 3300 SCIFB2_RTS_N_B_MARK, SCIFB2_CTS_N_B_MARK, 3301 }; 3302 static const unsigned int scifb2_data_c_pins[] = { 3303 /* RXD, TXD */ 3304 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25), 3305 }; 3306 static const unsigned int scifb2_data_c_mux[] = { 3307 SCIFB2_RXD_C_MARK, SCIFB2_TXD_C_MARK, 3308 }; 3309 /* - SCIF Clock ------------------------------------------------------------- */ 3310 static const unsigned int scif_clk_pins[] = { 3311 /* SCIF_CLK */ 3312 RCAR_GP_PIN(4, 26), 3313 }; 3314 static const unsigned int scif_clk_mux[] = { 3315 SCIF_CLK_MARK, 3316 }; 3317 static const unsigned int scif_clk_b_pins[] = { 3318 /* SCIF_CLK */ 3319 RCAR_GP_PIN(5, 4), 3320 }; 3321 static const unsigned int scif_clk_b_mux[] = { 3322 SCIF_CLK_B_MARK, 3323 }; 3324 /* - SDHI0 ------------------------------------------------------------------ */ 3325 static const unsigned int sdhi0_data1_pins[] = { 3326 /* D0 */ 3327 RCAR_GP_PIN(3, 2), 3328 }; 3329 static const unsigned int sdhi0_data1_mux[] = { 3330 SD0_DAT0_MARK, 3331 }; 3332 static const unsigned int sdhi0_data4_pins[] = { 3333 /* D[0:3] */ 3334 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), 3335 }; 3336 static const unsigned int sdhi0_data4_mux[] = { 3337 SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK, 3338 }; 3339 static const unsigned int sdhi0_ctrl_pins[] = { 3340 /* CLK, CMD */ 3341 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1), 3342 }; 3343 static const unsigned int sdhi0_ctrl_mux[] = { 3344 SD0_CLK_MARK, SD0_CMD_MARK, 3345 }; 3346 static const unsigned int sdhi0_cd_pins[] = { 3347 /* CD */ 3348 RCAR_GP_PIN(3, 6), 3349 }; 3350 static const unsigned int sdhi0_cd_mux[] = { 3351 SD0_CD_MARK, 3352 }; 3353 static const unsigned int sdhi0_wp_pins[] = { 3354 /* WP */ 3355 RCAR_GP_PIN(3, 7), 3356 }; 3357 static const unsigned int sdhi0_wp_mux[] = { 3358 SD0_WP_MARK, 3359 }; 3360 /* - SDHI1 ------------------------------------------------------------------ */ 3361 static const unsigned int sdhi1_data1_pins[] = { 3362 /* D0 */ 3363 RCAR_GP_PIN(3, 10), 3364 }; 3365 static const unsigned int sdhi1_data1_mux[] = { 3366 SD1_DAT0_MARK, 3367 }; 3368 static const unsigned int sdhi1_data4_pins[] = { 3369 /* D[0:3] */ 3370 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13), 3371 }; 3372 static const unsigned int sdhi1_data4_mux[] = { 3373 SD1_DAT0_MARK, SD1_DAT1_MARK, SD1_DAT2_MARK, SD1_DAT3_MARK, 3374 }; 3375 static const unsigned int sdhi1_ctrl_pins[] = { 3376 /* CLK, CMD */ 3377 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), 3378 }; 3379 static const unsigned int sdhi1_ctrl_mux[] = { 3380 SD1_CLK_MARK, SD1_CMD_MARK, 3381 }; 3382 static const unsigned int sdhi1_cd_pins[] = { 3383 /* CD */ 3384 RCAR_GP_PIN(3, 14), 3385 }; 3386 static const unsigned int sdhi1_cd_mux[] = { 3387 SD1_CD_MARK, 3388 }; 3389 static const unsigned int sdhi1_wp_pins[] = { 3390 /* WP */ 3391 RCAR_GP_PIN(3, 15), 3392 }; 3393 static const unsigned int sdhi1_wp_mux[] = { 3394 SD1_WP_MARK, 3395 }; 3396 /* - SDHI2 ------------------------------------------------------------------ */ 3397 static const unsigned int sdhi2_data1_pins[] = { 3398 /* D0 */ 3399 RCAR_GP_PIN(3, 18), 3400 }; 3401 static const unsigned int sdhi2_data1_mux[] = { 3402 SD2_DAT0_MARK, 3403 }; 3404 static const unsigned int sdhi2_data4_pins[] = { 3405 /* D[0:3] */ 3406 RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21), 3407 }; 3408 static const unsigned int sdhi2_data4_mux[] = { 3409 SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK, 3410 }; 3411 static const unsigned int sdhi2_ctrl_pins[] = { 3412 /* CLK, CMD */ 3413 RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17), 3414 }; 3415 static const unsigned int sdhi2_ctrl_mux[] = { 3416 SD2_CLK_MARK, SD2_CMD_MARK, 3417 }; 3418 static const unsigned int sdhi2_cd_pins[] = { 3419 /* CD */ 3420 RCAR_GP_PIN(3, 22), 3421 }; 3422 static const unsigned int sdhi2_cd_mux[] = { 3423 SD2_CD_MARK, 3424 }; 3425 static const unsigned int sdhi2_wp_pins[] = { 3426 /* WP */ 3427 RCAR_GP_PIN(3, 23), 3428 }; 3429 static const unsigned int sdhi2_wp_mux[] = { 3430 SD2_WP_MARK, 3431 }; 3432 /* - SDHI3 ------------------------------------------------------------------ */ 3433 static const unsigned int sdhi3_data1_pins[] = { 3434 /* D0 */ 3435 RCAR_GP_PIN(3, 26), 3436 }; 3437 static const unsigned int sdhi3_data1_mux[] = { 3438 SD3_DAT0_MARK, 3439 }; 3440 static const unsigned int sdhi3_data4_pins[] = { 3441 /* D[0:3] */ 3442 RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29), 3443 }; 3444 static const unsigned int sdhi3_data4_mux[] = { 3445 SD3_DAT0_MARK, SD3_DAT1_MARK, SD3_DAT2_MARK, SD3_DAT3_MARK, 3446 }; 3447 static const unsigned int sdhi3_ctrl_pins[] = { 3448 /* CLK, CMD */ 3449 RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25), 3450 }; 3451 static const unsigned int sdhi3_ctrl_mux[] = { 3452 SD3_CLK_MARK, SD3_CMD_MARK, 3453 }; 3454 static const unsigned int sdhi3_cd_pins[] = { 3455 /* CD */ 3456 RCAR_GP_PIN(3, 30), 3457 }; 3458 static const unsigned int sdhi3_cd_mux[] = { 3459 SD3_CD_MARK, 3460 }; 3461 static const unsigned int sdhi3_wp_pins[] = { 3462 /* WP */ 3463 RCAR_GP_PIN(3, 31), 3464 }; 3465 static const unsigned int sdhi3_wp_mux[] = { 3466 SD3_WP_MARK, 3467 }; 3468 /* - SSI -------------------------------------------------------------------- */ 3469 static const unsigned int ssi0_data_pins[] = { 3470 /* SDATA0 */ 3471 RCAR_GP_PIN(4, 5), 3472 }; 3473 static const unsigned int ssi0_data_mux[] = { 3474 SSI_SDATA0_MARK, 3475 }; 3476 static const unsigned int ssi0129_ctrl_pins[] = { 3477 /* SCK, WS */ 3478 RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 4), 3479 }; 3480 static const unsigned int ssi0129_ctrl_mux[] = { 3481 SSI_SCK0129_MARK, SSI_WS0129_MARK, 3482 }; 3483 static const unsigned int ssi1_data_pins[] = { 3484 /* SDATA1 */ 3485 RCAR_GP_PIN(4, 6), 3486 }; 3487 static const unsigned int ssi1_data_mux[] = { 3488 SSI_SDATA1_MARK, 3489 }; 3490 static const unsigned int ssi1_ctrl_pins[] = { 3491 /* SCK, WS */ 3492 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 24), 3493 }; 3494 static const unsigned int ssi1_ctrl_mux[] = { 3495 SSI_SCK1_MARK, SSI_WS1_MARK, 3496 }; 3497 static const unsigned int ssi2_data_pins[] = { 3498 /* SDATA2 */ 3499 RCAR_GP_PIN(4, 7), 3500 }; 3501 static const unsigned int ssi2_data_mux[] = { 3502 SSI_SDATA2_MARK, 3503 }; 3504 static const unsigned int ssi2_ctrl_pins[] = { 3505 /* SCK, WS */ 3506 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 17), 3507 }; 3508 static const unsigned int ssi2_ctrl_mux[] = { 3509 SSI_SCK2_MARK, SSI_WS2_MARK, 3510 }; 3511 static const unsigned int ssi3_data_pins[] = { 3512 /* SDATA3 */ 3513 RCAR_GP_PIN(4, 10), 3514 }; 3515 static const unsigned int ssi3_data_mux[] = { 3516 SSI_SDATA3_MARK 3517 }; 3518 static const unsigned int ssi34_ctrl_pins[] = { 3519 /* SCK, WS */ 3520 RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9), 3521 }; 3522 static const unsigned int ssi34_ctrl_mux[] = { 3523 SSI_SCK34_MARK, SSI_WS34_MARK, 3524 }; 3525 static const unsigned int ssi4_data_pins[] = { 3526 /* SDATA4 */ 3527 RCAR_GP_PIN(4, 13), 3528 }; 3529 static const unsigned int ssi4_data_mux[] = { 3530 SSI_SDATA4_MARK, 3531 }; 3532 static const unsigned int ssi4_ctrl_pins[] = { 3533 /* SCK, WS */ 3534 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12), 3535 }; 3536 static const unsigned int ssi4_ctrl_mux[] = { 3537 SSI_SCK4_MARK, SSI_WS4_MARK, 3538 }; 3539 static const unsigned int ssi5_pins[] = { 3540 /* SDATA5, SCK, WS */ 3541 RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15), 3542 }; 3543 static const unsigned int ssi5_mux[] = { 3544 SSI_SDATA5_MARK, SSI_SCK5_MARK, SSI_WS5_MARK, 3545 }; 3546 static const unsigned int ssi5_b_pins[] = { 3547 /* SDATA5, SCK, WS */ 3548 RCAR_GP_PIN(0, 26), RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25), 3549 }; 3550 static const unsigned int ssi5_b_mux[] = { 3551 SSI_SDATA5_B_MARK, SSI_SCK5_B_MARK, SSI_WS5_B_MARK 3552 }; 3553 static const unsigned int ssi5_c_pins[] = { 3554 /* SDATA5, SCK, WS */ 3555 RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12), 3556 }; 3557 static const unsigned int ssi5_c_mux[] = { 3558 SSI_SDATA5_C_MARK, SSI_SCK5_C_MARK, SSI_WS5_C_MARK, 3559 }; 3560 static const unsigned int ssi6_pins[] = { 3561 /* SDATA6, SCK, WS */ 3562 RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18), 3563 }; 3564 static const unsigned int ssi6_mux[] = { 3565 SSI_SDATA6_MARK, SSI_SCK6_MARK, SSI_WS6_MARK, 3566 }; 3567 static const unsigned int ssi6_b_pins[] = { 3568 /* SDATA6, SCK, WS */ 3569 RCAR_GP_PIN(1, 29), RCAR_GP_PIN(1, 25), RCAR_GP_PIN(1, 27), 3570 }; 3571 static const unsigned int ssi6_b_mux[] = { 3572 SSI_SDATA6_B_MARK, SSI_SCK6_B_MARK, SSI_WS6_B_MARK, 3573 }; 3574 static const unsigned int ssi7_data_pins[] = { 3575 /* SDATA7 */ 3576 RCAR_GP_PIN(4, 22), 3577 }; 3578 static const unsigned int ssi7_data_mux[] = { 3579 SSI_SDATA7_MARK, 3580 }; 3581 static const unsigned int ssi7_b_data_pins[] = { 3582 /* SDATA7 */ 3583 RCAR_GP_PIN(4, 22), 3584 }; 3585 static const unsigned int ssi7_b_data_mux[] = { 3586 SSI_SDATA7_B_MARK, 3587 }; 3588 static const unsigned int ssi7_c_data_pins[] = { 3589 /* SDATA7 */ 3590 RCAR_GP_PIN(1, 26), 3591 }; 3592 static const unsigned int ssi7_c_data_mux[] = { 3593 SSI_SDATA7_C_MARK, 3594 }; 3595 static const unsigned int ssi78_ctrl_pins[] = { 3596 /* SCK, WS */ 3597 RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21), 3598 }; 3599 static const unsigned int ssi78_ctrl_mux[] = { 3600 SSI_SCK78_MARK, SSI_WS78_MARK, 3601 }; 3602 static const unsigned int ssi78_b_ctrl_pins[] = { 3603 /* SCK, WS */ 3604 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 24), 3605 }; 3606 static const unsigned int ssi78_b_ctrl_mux[] = { 3607 SSI_SCK78_B_MARK, SSI_WS78_B_MARK, 3608 }; 3609 static const unsigned int ssi78_c_ctrl_pins[] = { 3610 /* SCK, WS */ 3611 RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 25), 3612 }; 3613 static const unsigned int ssi78_c_ctrl_mux[] = { 3614 SSI_SCK78_C_MARK, SSI_WS78_C_MARK, 3615 }; 3616 static const unsigned int ssi8_data_pins[] = { 3617 /* SDATA8 */ 3618 RCAR_GP_PIN(4, 23), 3619 }; 3620 static const unsigned int ssi8_data_mux[] = { 3621 SSI_SDATA8_MARK, 3622 }; 3623 static const unsigned int ssi8_b_data_pins[] = { 3624 /* SDATA8 */ 3625 RCAR_GP_PIN(4, 23), 3626 }; 3627 static const unsigned int ssi8_b_data_mux[] = { 3628 SSI_SDATA8_B_MARK, 3629 }; 3630 static const unsigned int ssi8_c_data_pins[] = { 3631 /* SDATA8 */ 3632 RCAR_GP_PIN(1, 27), 3633 }; 3634 static const unsigned int ssi8_c_data_mux[] = { 3635 SSI_SDATA8_C_MARK, 3636 }; 3637 static const unsigned int ssi9_data_pins[] = { 3638 /* SDATA9 */ 3639 RCAR_GP_PIN(4, 24), 3640 }; 3641 static const unsigned int ssi9_data_mux[] = { 3642 SSI_SDATA9_MARK, 3643 }; 3644 static const unsigned int ssi9_ctrl_pins[] = { 3645 /* SCK, WS */ 3646 RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11), 3647 }; 3648 static const unsigned int ssi9_ctrl_mux[] = { 3649 SSI_SCK9_MARK, SSI_WS9_MARK, 3650 }; 3651 /* - TPU0 ------------------------------------------------------------------- */ 3652 static const unsigned int tpu0_to0_pins[] = { 3653 /* TO */ 3654 RCAR_GP_PIN(0, 20), 3655 }; 3656 static const unsigned int tpu0_to0_mux[] = { 3657 TPU0TO0_MARK, 3658 }; 3659 static const unsigned int tpu0_to1_pins[] = { 3660 /* TO */ 3661 RCAR_GP_PIN(0, 21), 3662 }; 3663 static const unsigned int tpu0_to1_mux[] = { 3664 TPU0TO1_MARK, 3665 }; 3666 static const unsigned int tpu0_to2_pins[] = { 3667 /* TO */ 3668 RCAR_GP_PIN(0, 22), 3669 }; 3670 static const unsigned int tpu0_to2_mux[] = { 3671 TPU0TO2_MARK, 3672 }; 3673 static const unsigned int tpu0_to3_pins[] = { 3674 /* TO */ 3675 RCAR_GP_PIN(0, 23), 3676 }; 3677 static const unsigned int tpu0_to3_mux[] = { 3678 TPU0TO3_MARK, 3679 }; 3680 /* - USB0 ------------------------------------------------------------------- */ 3681 static const unsigned int usb0_pins[] = { 3682 /* PWEN, OVC/VBUS */ 3683 RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19), 3684 }; 3685 static const unsigned int usb0_mux[] = { 3686 USB0_PWEN_MARK, USB0_OVC_VBUS_MARK, 3687 }; 3688 static const unsigned int usb0_ovc_vbus_pins[] = { 3689 /* OVC/VBUS */ 3690 RCAR_GP_PIN(5, 19), 3691 }; 3692 static const unsigned int usb0_ovc_vbus_mux[] = { 3693 USB0_OVC_VBUS_MARK, 3694 }; 3695 /* - USB1 ------------------------------------------------------------------- */ 3696 static const unsigned int usb1_pins[] = { 3697 /* PWEN, OVC */ 3698 RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21), 3699 }; 3700 static const unsigned int usb1_mux[] = { 3701 USB1_PWEN_MARK, USB1_OVC_MARK, 3702 }; 3703 static const unsigned int usb1_pwen_pins[] = { 3704 /* PWEN */ 3705 RCAR_GP_PIN(5, 20), 3706 }; 3707 static const unsigned int usb1_pwen_mux[] = { 3708 USB1_PWEN_MARK, 3709 }; 3710 /* - USB2 ------------------------------------------------------------------- */ 3711 static const unsigned int usb2_pins[] = { 3712 /* PWEN, OVC */ 3713 RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23), 3714 }; 3715 static const unsigned int usb2_mux[] = { 3716 USB2_PWEN_MARK, USB2_OVC_MARK, 3717 }; 3718 /* - VIN0 ------------------------------------------------------------------- */ 3719 static const union vin_data vin0_data_pins = { 3720 .data24 = { 3721 /* B */ 3722 RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2), 3723 RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4), 3724 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6), 3725 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), 3726 /* G */ 3727 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), 3728 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), 3729 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), 3730 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), 3731 /* R */ 3732 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), 3733 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), 3734 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25), 3735 RCAR_GP_PIN(0, 26), RCAR_GP_PIN(1, 11), 3736 }, 3737 }; 3738 static const union vin_data vin0_data_mux = { 3739 .data24 = { 3740 /* B */ 3741 VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK, 3742 VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK, 3743 VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK, 3744 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK, 3745 /* G */ 3746 VI0_G0_MARK, VI0_G1_MARK, 3747 VI0_G2_MARK, VI0_G3_MARK, 3748 VI0_G4_MARK, VI0_G5_MARK, 3749 VI0_G6_MARK, VI0_G7_MARK, 3750 /* R */ 3751 VI0_R0_MARK, VI0_R1_MARK, 3752 VI0_R2_MARK, VI0_R3_MARK, 3753 VI0_R4_MARK, VI0_R5_MARK, 3754 VI0_R6_MARK, VI0_R7_MARK, 3755 }, 3756 }; 3757 static const unsigned int vin0_data18_pins[] = { 3758 /* B */ 3759 RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4), 3760 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6), 3761 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), 3762 /* G */ 3763 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), 3764 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), 3765 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), 3766 /* R */ 3767 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), 3768 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25), 3769 RCAR_GP_PIN(0, 26), RCAR_GP_PIN(1, 11), 3770 }; 3771 static const unsigned int vin0_data18_mux[] = { 3772 /* B */ 3773 VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK, 3774 VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK, 3775 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK, 3776 /* G */ 3777 VI0_G2_MARK, VI0_G3_MARK, 3778 VI0_G4_MARK, VI0_G5_MARK, 3779 VI0_G6_MARK, VI0_G7_MARK, 3780 /* R */ 3781 VI0_R2_MARK, VI0_R3_MARK, 3782 VI0_R4_MARK, VI0_R5_MARK, 3783 VI0_R6_MARK, VI0_R7_MARK, 3784 }; 3785 static const unsigned int vin0_sync_pins[] = { 3786 RCAR_GP_PIN(0, 12), /* HSYNC */ 3787 RCAR_GP_PIN(0, 13), /* VSYNC */ 3788 }; 3789 static const unsigned int vin0_sync_mux[] = { 3790 VI0_HSYNC_N_MARK, 3791 VI0_VSYNC_N_MARK, 3792 }; 3793 static const unsigned int vin0_field_pins[] = { 3794 RCAR_GP_PIN(0, 15), 3795 }; 3796 static const unsigned int vin0_field_mux[] = { 3797 VI0_FIELD_MARK, 3798 }; 3799 static const unsigned int vin0_clkenb_pins[] = { 3800 RCAR_GP_PIN(0, 14), 3801 }; 3802 static const unsigned int vin0_clkenb_mux[] = { 3803 VI0_CLKENB_MARK, 3804 }; 3805 static const unsigned int vin0_clk_pins[] = { 3806 RCAR_GP_PIN(2, 0), 3807 }; 3808 static const unsigned int vin0_clk_mux[] = { 3809 VI0_CLK_MARK, 3810 }; 3811 /* - VIN1 ------------------------------------------------------------------- */ 3812 static const union vin_data vin1_data_pins = { 3813 .data24 = { 3814 /* B */ 3815 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11), 3816 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13), 3817 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15), 3818 RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17), 3819 /* G */ 3820 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), 3821 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20), 3822 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12), 3823 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7), 3824 /* R */ 3825 RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28), 3826 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4), 3827 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), 3828 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8), 3829 }, 3830 }; 3831 static const union vin_data vin1_data_mux = { 3832 .data24 = { 3833 /* B */ 3834 VI1_DATA0_VI1_B0_MARK, VI1_DATA1_VI1_B1_MARK, 3835 VI1_DATA2_VI1_B2_MARK, VI1_DATA3_VI1_B3_MARK, 3836 VI1_DATA4_VI1_B4_MARK, VI1_DATA5_VI1_B5_MARK, 3837 VI1_DATA6_VI1_B6_MARK, VI1_DATA7_VI1_B7_MARK, 3838 /* G */ 3839 VI1_G0_MARK, VI1_G1_MARK, 3840 VI1_G2_MARK, VI1_G3_MARK, 3841 VI1_G4_MARK, VI1_G5_MARK, 3842 VI1_G6_MARK, VI1_G7_MARK, 3843 /* R */ 3844 VI1_R0_MARK, VI1_R1_MARK, 3845 VI1_R2_MARK, VI1_R3_MARK, 3846 VI1_R4_MARK, VI1_R5_MARK, 3847 VI1_R6_MARK, VI1_R7_MARK, 3848 }, 3849 }; 3850 static const unsigned int vin1_data18_pins[] = { 3851 /* B */ 3852 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13), 3853 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15), 3854 RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17), 3855 /* G */ 3856 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20), 3857 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12), 3858 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7), 3859 /* R */ 3860 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4), 3861 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), 3862 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8), 3863 }; 3864 static const unsigned int vin1_data18_mux[] = { 3865 /* B */ 3866 VI1_DATA2_VI1_B2_MARK, VI1_DATA3_VI1_B3_MARK, 3867 VI1_DATA4_VI1_B4_MARK, VI1_DATA5_VI1_B5_MARK, 3868 VI1_DATA6_VI1_B6_MARK, VI1_DATA7_VI1_B7_MARK, 3869 /* G */ 3870 VI1_G2_MARK, VI1_G3_MARK, 3871 VI1_G4_MARK, VI1_G5_MARK, 3872 VI1_G6_MARK, VI1_G7_MARK, 3873 /* R */ 3874 VI1_R2_MARK, VI1_R3_MARK, 3875 VI1_R4_MARK, VI1_R5_MARK, 3876 VI1_R6_MARK, VI1_R7_MARK, 3877 }; 3878 static const union vin_data vin1_data_b_pins = { 3879 .data24 = { 3880 /* B */ 3881 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1), 3882 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), 3883 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), 3884 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), 3885 /* G */ 3886 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), 3887 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20), 3888 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12), 3889 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7), 3890 /* R */ 3891 RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28), 3892 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4), 3893 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), 3894 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8), 3895 }, 3896 }; 3897 static const union vin_data vin1_data_b_mux = { 3898 .data24 = { 3899 /* B */ 3900 VI1_DATA0_VI1_B0_B_MARK, VI1_DATA1_VI1_B1_B_MARK, 3901 VI1_DATA2_VI1_B2_B_MARK, VI1_DATA3_VI1_B3_B_MARK, 3902 VI1_DATA4_VI1_B4_B_MARK, VI1_DATA5_VI1_B5_B_MARK, 3903 VI1_DATA6_VI1_B6_B_MARK, VI1_DATA7_VI1_B7_B_MARK, 3904 /* G */ 3905 VI1_G0_B_MARK, VI1_G1_B_MARK, 3906 VI1_G2_B_MARK, VI1_G3_B_MARK, 3907 VI1_G4_B_MARK, VI1_G5_B_MARK, 3908 VI1_G6_B_MARK, VI1_G7_B_MARK, 3909 /* R */ 3910 VI1_R0_B_MARK, VI1_R1_B_MARK, 3911 VI1_R2_B_MARK, VI1_R3_B_MARK, 3912 VI1_R4_B_MARK, VI1_R5_B_MARK, 3913 VI1_R6_B_MARK, VI1_R7_B_MARK, 3914 }, 3915 }; 3916 static const unsigned int vin1_data18_b_pins[] = { 3917 /* B */ 3918 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), 3919 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), 3920 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), 3921 /* G */ 3922 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20), 3923 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12), 3924 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7), 3925 /* R */ 3926 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4), 3927 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), 3928 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8), 3929 }; 3930 static const unsigned int vin1_data18_b_mux[] = { 3931 /* B */ 3932 VI1_DATA2_VI1_B2_B_MARK, VI1_DATA3_VI1_B3_B_MARK, 3933 VI1_DATA4_VI1_B4_B_MARK, VI1_DATA5_VI1_B5_B_MARK, 3934 VI1_DATA6_VI1_B6_B_MARK, VI1_DATA7_VI1_B7_B_MARK, 3935 /* G */ 3936 VI1_G2_B_MARK, VI1_G3_B_MARK, 3937 VI1_G4_B_MARK, VI1_G5_B_MARK, 3938 VI1_G6_B_MARK, VI1_G7_B_MARK, 3939 /* R */ 3940 VI1_R2_B_MARK, VI1_R3_B_MARK, 3941 VI1_R4_B_MARK, VI1_R5_B_MARK, 3942 VI1_R6_B_MARK, VI1_R7_B_MARK, 3943 }; 3944 static const unsigned int vin1_sync_pins[] = { 3945 RCAR_GP_PIN(1, 24), /* HSYNC */ 3946 RCAR_GP_PIN(1, 25), /* VSYNC */ 3947 }; 3948 static const unsigned int vin1_sync_mux[] = { 3949 VI1_HSYNC_N_MARK, 3950 VI1_VSYNC_N_MARK, 3951 }; 3952 static const unsigned int vin1_sync_b_pins[] = { 3953 RCAR_GP_PIN(1, 24), /* HSYNC */ 3954 RCAR_GP_PIN(1, 25), /* VSYNC */ 3955 }; 3956 static const unsigned int vin1_sync_b_mux[] = { 3957 VI1_HSYNC_N_B_MARK, 3958 VI1_VSYNC_N_B_MARK, 3959 }; 3960 static const unsigned int vin1_field_pins[] = { 3961 RCAR_GP_PIN(1, 13), 3962 }; 3963 static const unsigned int vin1_field_mux[] = { 3964 VI1_FIELD_MARK, 3965 }; 3966 static const unsigned int vin1_field_b_pins[] = { 3967 RCAR_GP_PIN(1, 13), 3968 }; 3969 static const unsigned int vin1_field_b_mux[] = { 3970 VI1_FIELD_B_MARK, 3971 }; 3972 static const unsigned int vin1_clkenb_pins[] = { 3973 RCAR_GP_PIN(1, 26), 3974 }; 3975 static const unsigned int vin1_clkenb_mux[] = { 3976 VI1_CLKENB_MARK, 3977 }; 3978 static const unsigned int vin1_clkenb_b_pins[] = { 3979 RCAR_GP_PIN(1, 26), 3980 }; 3981 static const unsigned int vin1_clkenb_b_mux[] = { 3982 VI1_CLKENB_B_MARK, 3983 }; 3984 static const unsigned int vin1_clk_pins[] = { 3985 RCAR_GP_PIN(2, 9), 3986 }; 3987 static const unsigned int vin1_clk_mux[] = { 3988 VI1_CLK_MARK, 3989 }; 3990 static const unsigned int vin1_clk_b_pins[] = { 3991 RCAR_GP_PIN(3, 15), 3992 }; 3993 static const unsigned int vin1_clk_b_mux[] = { 3994 VI1_CLK_B_MARK, 3995 }; 3996 /* - VIN2 ----------------------------------------------------------------- */ 3997 static const union vin_data vin2_data_pins = { 3998 .data24 = { 3999 /* B */ 4000 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), 4001 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), 4002 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), 4003 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), 4004 /* G */ 4005 RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28), 4006 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 10), 4007 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), 4008 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 4009 /* R */ 4010 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), 4011 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), 4012 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20), 4013 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 24), 4014 }, 4015 }; 4016 static const union vin_data vin2_data_mux = { 4017 .data24 = { 4018 /* B */ 4019 VI2_DATA0_VI2_B0_MARK, VI2_DATA1_VI2_B1_MARK, 4020 VI2_DATA2_VI2_B2_MARK, VI2_DATA3_VI2_B3_MARK, 4021 VI2_DATA4_VI2_B4_MARK, VI2_DATA5_VI2_B5_MARK, 4022 VI2_DATA6_VI2_B6_MARK, VI2_DATA7_VI2_B7_MARK, 4023 /* G */ 4024 VI2_G0_MARK, VI2_G1_MARK, 4025 VI2_G2_MARK, VI2_G3_MARK, 4026 VI2_G4_MARK, VI2_G5_MARK, 4027 VI2_G6_MARK, VI2_G7_MARK, 4028 /* R */ 4029 VI2_R0_MARK, VI2_R1_MARK, 4030 VI2_R2_MARK, VI2_R3_MARK, 4031 VI2_R4_MARK, VI2_R5_MARK, 4032 VI2_R6_MARK, VI2_R7_MARK, 4033 }, 4034 }; 4035 static const unsigned int vin2_data18_pins[] = { 4036 /* B */ 4037 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), 4038 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), 4039 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), 4040 /* G */ 4041 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 10), 4042 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), 4043 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 4044 /* R */ 4045 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), 4046 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20), 4047 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 24), 4048 }; 4049 static const unsigned int vin2_data18_mux[] = { 4050 /* B */ 4051 VI2_DATA2_VI2_B2_MARK, VI2_DATA3_VI2_B3_MARK, 4052 VI2_DATA4_VI2_B4_MARK, VI2_DATA5_VI2_B5_MARK, 4053 VI2_DATA6_VI2_B6_MARK, VI2_DATA7_VI2_B7_MARK, 4054 /* G */ 4055 VI2_G2_MARK, VI2_G3_MARK, 4056 VI2_G4_MARK, VI2_G5_MARK, 4057 VI2_G6_MARK, VI2_G7_MARK, 4058 /* R */ 4059 VI2_R2_MARK, VI2_R3_MARK, 4060 VI2_R4_MARK, VI2_R5_MARK, 4061 VI2_R6_MARK, VI2_R7_MARK, 4062 }; 4063 static const unsigned int vin2_g8_pins[] = { 4064 RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28), 4065 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 10), 4066 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), 4067 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 4068 }; 4069 static const unsigned int vin2_g8_mux[] = { 4070 VI2_G0_MARK, VI2_G1_MARK, 4071 VI2_G2_MARK, VI2_G3_MARK, 4072 VI2_G4_MARK, VI2_G5_MARK, 4073 VI2_G6_MARK, VI2_G7_MARK, 4074 }; 4075 static const unsigned int vin2_sync_pins[] = { 4076 RCAR_GP_PIN(1, 16), /* HSYNC */ 4077 RCAR_GP_PIN(1, 21), /* VSYNC */ 4078 }; 4079 static const unsigned int vin2_sync_mux[] = { 4080 VI2_HSYNC_N_MARK, 4081 VI2_VSYNC_N_MARK, 4082 }; 4083 static const unsigned int vin2_field_pins[] = { 4084 RCAR_GP_PIN(1, 9), 4085 }; 4086 static const unsigned int vin2_field_mux[] = { 4087 VI2_FIELD_MARK, 4088 }; 4089 static const unsigned int vin2_clkenb_pins[] = { 4090 RCAR_GP_PIN(1, 8), 4091 }; 4092 static const unsigned int vin2_clkenb_mux[] = { 4093 VI2_CLKENB_MARK, 4094 }; 4095 static const unsigned int vin2_clk_pins[] = { 4096 RCAR_GP_PIN(1, 11), 4097 }; 4098 static const unsigned int vin2_clk_mux[] = { 4099 VI2_CLK_MARK, 4100 }; 4101 /* - VIN3 ----------------------------------------------------------------- */ 4102 static const unsigned int vin3_data8_pins[] = { 4103 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), 4104 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), 4105 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), 4106 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), 4107 }; 4108 static const unsigned int vin3_data8_mux[] = { 4109 VI3_DATA0_MARK, VI3_DATA1_MARK, 4110 VI3_DATA2_MARK, VI3_DATA3_MARK, 4111 VI3_DATA4_MARK, VI3_DATA5_MARK, 4112 VI3_DATA6_MARK, VI3_DATA7_MARK, 4113 }; 4114 static const unsigned int vin3_sync_pins[] = { 4115 RCAR_GP_PIN(1, 16), /* HSYNC */ 4116 RCAR_GP_PIN(1, 17), /* VSYNC */ 4117 }; 4118 static const unsigned int vin3_sync_mux[] = { 4119 VI3_HSYNC_N_MARK, 4120 VI3_VSYNC_N_MARK, 4121 }; 4122 static const unsigned int vin3_field_pins[] = { 4123 RCAR_GP_PIN(1, 15), 4124 }; 4125 static const unsigned int vin3_field_mux[] = { 4126 VI3_FIELD_MARK, 4127 }; 4128 static const unsigned int vin3_clkenb_pins[] = { 4129 RCAR_GP_PIN(1, 14), 4130 }; 4131 static const unsigned int vin3_clkenb_mux[] = { 4132 VI3_CLKENB_MARK, 4133 }; 4134 static const unsigned int vin3_clk_pins[] = { 4135 RCAR_GP_PIN(1, 23), 4136 }; 4137 static const unsigned int vin3_clk_mux[] = { 4138 VI3_CLK_MARK, 4139 }; 4140 4141 static const struct { 4142 struct sh_pfc_pin_group common[311]; 4143 #ifdef CONFIG_PINCTRL_PFC_R8A7790 4144 struct sh_pfc_pin_group automotive[1]; 4145 #endif 4146 } pinmux_groups = { 4147 .common = { 4148 SH_PFC_PIN_GROUP(audio_clk_a), 4149 SH_PFC_PIN_GROUP(audio_clk_b), 4150 SH_PFC_PIN_GROUP(audio_clk_c), 4151 SH_PFC_PIN_GROUP(audio_clkout), 4152 SH_PFC_PIN_GROUP(audio_clkout_b), 4153 SH_PFC_PIN_GROUP(audio_clkout_c), 4154 SH_PFC_PIN_GROUP(audio_clkout_d), 4155 SH_PFC_PIN_GROUP(avb_link), 4156 SH_PFC_PIN_GROUP(avb_magic), 4157 SH_PFC_PIN_GROUP(avb_phy_int), 4158 SH_PFC_PIN_GROUP(avb_mdio), 4159 SH_PFC_PIN_GROUP(avb_mii), 4160 SH_PFC_PIN_GROUP(avb_gmii), 4161 SH_PFC_PIN_GROUP(can0_data), 4162 SH_PFC_PIN_GROUP(can0_data_b), 4163 SH_PFC_PIN_GROUP(can0_data_c), 4164 SH_PFC_PIN_GROUP(can0_data_d), 4165 SH_PFC_PIN_GROUP(can1_data), 4166 SH_PFC_PIN_GROUP(can1_data_b), 4167 SH_PFC_PIN_GROUP(can_clk), 4168 SH_PFC_PIN_GROUP(can_clk_b), 4169 SH_PFC_PIN_GROUP(du_rgb666), 4170 SH_PFC_PIN_GROUP(du_rgb888), 4171 SH_PFC_PIN_GROUP(du_clk_out_0), 4172 SH_PFC_PIN_GROUP(du_clk_out_1), 4173 SH_PFC_PIN_GROUP(du_sync_0), 4174 SH_PFC_PIN_GROUP(du_sync_1), 4175 SH_PFC_PIN_GROUP(du_cde), 4176 SH_PFC_PIN_GROUP(du0_clk_in), 4177 SH_PFC_PIN_GROUP(du1_clk_in), 4178 SH_PFC_PIN_GROUP(du2_clk_in), 4179 SH_PFC_PIN_GROUP(eth_link), 4180 SH_PFC_PIN_GROUP(eth_magic), 4181 SH_PFC_PIN_GROUP(eth_mdio), 4182 SH_PFC_PIN_GROUP(eth_rmii), 4183 SH_PFC_PIN_GROUP(hscif0_data), 4184 SH_PFC_PIN_GROUP(hscif0_clk), 4185 SH_PFC_PIN_GROUP(hscif0_ctrl), 4186 SH_PFC_PIN_GROUP(hscif0_data_b), 4187 SH_PFC_PIN_GROUP(hscif0_ctrl_b), 4188 SH_PFC_PIN_GROUP(hscif0_data_c), 4189 SH_PFC_PIN_GROUP(hscif0_ctrl_c), 4190 SH_PFC_PIN_GROUP(hscif0_data_d), 4191 SH_PFC_PIN_GROUP(hscif0_ctrl_d), 4192 SH_PFC_PIN_GROUP(hscif0_data_e), 4193 SH_PFC_PIN_GROUP(hscif0_ctrl_e), 4194 SH_PFC_PIN_GROUP(hscif0_data_f), 4195 SH_PFC_PIN_GROUP(hscif0_ctrl_f), 4196 SH_PFC_PIN_GROUP(hscif1_data), 4197 SH_PFC_PIN_GROUP(hscif1_clk), 4198 SH_PFC_PIN_GROUP(hscif1_ctrl), 4199 SH_PFC_PIN_GROUP(hscif1_data_b), 4200 SH_PFC_PIN_GROUP(hscif1_clk_b), 4201 SH_PFC_PIN_GROUP(hscif1_ctrl_b), 4202 SH_PFC_PIN_GROUP(i2c0), 4203 SH_PFC_PIN_GROUP(i2c1), 4204 SH_PFC_PIN_GROUP(i2c1_b), 4205 SH_PFC_PIN_GROUP(i2c1_c), 4206 SH_PFC_PIN_GROUP(i2c2), 4207 SH_PFC_PIN_GROUP(i2c2_b), 4208 SH_PFC_PIN_GROUP(i2c2_c), 4209 SH_PFC_PIN_GROUP(i2c2_d), 4210 SH_PFC_PIN_GROUP(i2c2_e), 4211 SH_PFC_PIN_GROUP(i2c3), 4212 SH_PFC_PIN_GROUP(iic0), 4213 SH_PFC_PIN_GROUP(iic1), 4214 SH_PFC_PIN_GROUP(iic1_b), 4215 SH_PFC_PIN_GROUP(iic1_c), 4216 SH_PFC_PIN_GROUP(iic2), 4217 SH_PFC_PIN_GROUP(iic2_b), 4218 SH_PFC_PIN_GROUP(iic2_c), 4219 SH_PFC_PIN_GROUP(iic2_d), 4220 SH_PFC_PIN_GROUP(iic2_e), 4221 SH_PFC_PIN_GROUP(iic3), 4222 SH_PFC_PIN_GROUP(intc_irq0), 4223 SH_PFC_PIN_GROUP(intc_irq1), 4224 SH_PFC_PIN_GROUP(intc_irq2), 4225 SH_PFC_PIN_GROUP(intc_irq3), 4226 SH_PFC_PIN_GROUP(mmc0_data1), 4227 SH_PFC_PIN_GROUP(mmc0_data4), 4228 SH_PFC_PIN_GROUP(mmc0_data8), 4229 SH_PFC_PIN_GROUP(mmc0_ctrl), 4230 SH_PFC_PIN_GROUP(mmc1_data1), 4231 SH_PFC_PIN_GROUP(mmc1_data4), 4232 SH_PFC_PIN_GROUP(mmc1_data8), 4233 SH_PFC_PIN_GROUP(mmc1_ctrl), 4234 SH_PFC_PIN_GROUP(msiof0_clk), 4235 SH_PFC_PIN_GROUP(msiof0_sync), 4236 SH_PFC_PIN_GROUP(msiof0_ss1), 4237 SH_PFC_PIN_GROUP(msiof0_ss2), 4238 SH_PFC_PIN_GROUP(msiof0_rx), 4239 SH_PFC_PIN_GROUP(msiof0_tx), 4240 SH_PFC_PIN_GROUP(msiof0_clk_b), 4241 SH_PFC_PIN_GROUP(msiof0_ss1_b), 4242 SH_PFC_PIN_GROUP(msiof0_ss2_b), 4243 SH_PFC_PIN_GROUP(msiof0_rx_b), 4244 SH_PFC_PIN_GROUP(msiof0_tx_b), 4245 SH_PFC_PIN_GROUP(msiof1_clk), 4246 SH_PFC_PIN_GROUP(msiof1_sync), 4247 SH_PFC_PIN_GROUP(msiof1_ss1), 4248 SH_PFC_PIN_GROUP(msiof1_ss2), 4249 SH_PFC_PIN_GROUP(msiof1_rx), 4250 SH_PFC_PIN_GROUP(msiof1_tx), 4251 SH_PFC_PIN_GROUP(msiof1_clk_b), 4252 SH_PFC_PIN_GROUP(msiof1_ss1_b), 4253 SH_PFC_PIN_GROUP(msiof1_ss2_b), 4254 SH_PFC_PIN_GROUP(msiof1_rx_b), 4255 SH_PFC_PIN_GROUP(msiof1_tx_b), 4256 SH_PFC_PIN_GROUP(msiof2_clk), 4257 SH_PFC_PIN_GROUP(msiof2_sync), 4258 SH_PFC_PIN_GROUP(msiof2_ss1), 4259 SH_PFC_PIN_GROUP(msiof2_ss2), 4260 SH_PFC_PIN_GROUP(msiof2_rx), 4261 SH_PFC_PIN_GROUP(msiof2_tx), 4262 SH_PFC_PIN_GROUP(msiof3_clk), 4263 SH_PFC_PIN_GROUP(msiof3_sync), 4264 SH_PFC_PIN_GROUP(msiof3_ss1), 4265 SH_PFC_PIN_GROUP(msiof3_ss2), 4266 SH_PFC_PIN_GROUP(msiof3_rx), 4267 SH_PFC_PIN_GROUP(msiof3_tx), 4268 SH_PFC_PIN_GROUP(msiof3_clk_b), 4269 SH_PFC_PIN_GROUP(msiof3_sync_b), 4270 SH_PFC_PIN_GROUP(msiof3_rx_b), 4271 SH_PFC_PIN_GROUP(msiof3_tx_b), 4272 SH_PFC_PIN_GROUP(pwm0), 4273 SH_PFC_PIN_GROUP(pwm0_b), 4274 SH_PFC_PIN_GROUP(pwm1), 4275 SH_PFC_PIN_GROUP(pwm1_b), 4276 SH_PFC_PIN_GROUP(pwm2), 4277 SH_PFC_PIN_GROUP(pwm3), 4278 SH_PFC_PIN_GROUP(pwm4), 4279 SH_PFC_PIN_GROUP(pwm5), 4280 SH_PFC_PIN_GROUP(pwm6), 4281 SH_PFC_PIN_GROUP(qspi_ctrl), 4282 SH_PFC_PIN_GROUP(qspi_data2), 4283 SH_PFC_PIN_GROUP(qspi_data4), 4284 SH_PFC_PIN_GROUP(scif0_data), 4285 SH_PFC_PIN_GROUP(scif0_clk), 4286 SH_PFC_PIN_GROUP(scif0_ctrl), 4287 SH_PFC_PIN_GROUP(scif0_data_b), 4288 SH_PFC_PIN_GROUP(scif1_data), 4289 SH_PFC_PIN_GROUP(scif1_clk), 4290 SH_PFC_PIN_GROUP(scif1_ctrl), 4291 SH_PFC_PIN_GROUP(scif1_data_b), 4292 SH_PFC_PIN_GROUP(scif1_data_c), 4293 SH_PFC_PIN_GROUP(scif1_data_d), 4294 SH_PFC_PIN_GROUP(scif1_clk_d), 4295 SH_PFC_PIN_GROUP(scif1_data_e), 4296 SH_PFC_PIN_GROUP(scif1_clk_e), 4297 SH_PFC_PIN_GROUP(scif2_data), 4298 SH_PFC_PIN_GROUP(scif2_clk), 4299 SH_PFC_PIN_GROUP(scif2_data_b), 4300 SH_PFC_PIN_GROUP(scifa0_data), 4301 SH_PFC_PIN_GROUP(scifa0_clk), 4302 SH_PFC_PIN_GROUP(scifa0_ctrl), 4303 SH_PFC_PIN_GROUP(scifa0_data_b), 4304 SH_PFC_PIN_GROUP(scifa0_clk_b), 4305 SH_PFC_PIN_GROUP(scifa0_ctrl_b), 4306 SH_PFC_PIN_GROUP(scifa1_data), 4307 SH_PFC_PIN_GROUP(scifa1_clk), 4308 SH_PFC_PIN_GROUP(scifa1_ctrl), 4309 SH_PFC_PIN_GROUP(scifa1_data_b), 4310 SH_PFC_PIN_GROUP(scifa1_clk_b), 4311 SH_PFC_PIN_GROUP(scifa1_ctrl_b), 4312 SH_PFC_PIN_GROUP(scifa1_data_c), 4313 SH_PFC_PIN_GROUP(scifa1_clk_c), 4314 SH_PFC_PIN_GROUP(scifa1_ctrl_c), 4315 SH_PFC_PIN_GROUP(scifa1_data_d), 4316 SH_PFC_PIN_GROUP(scifa1_clk_d), 4317 SH_PFC_PIN_GROUP(scifa1_ctrl_d), 4318 SH_PFC_PIN_GROUP(scifa2_data), 4319 SH_PFC_PIN_GROUP(scifa2_clk), 4320 SH_PFC_PIN_GROUP(scifa2_ctrl), 4321 SH_PFC_PIN_GROUP(scifa2_data_b), 4322 SH_PFC_PIN_GROUP(scifa2_data_c), 4323 SH_PFC_PIN_GROUP(scifa2_clk_c), 4324 SH_PFC_PIN_GROUP(scifb0_data), 4325 SH_PFC_PIN_GROUP(scifb0_clk), 4326 SH_PFC_PIN_GROUP(scifb0_ctrl), 4327 SH_PFC_PIN_GROUP(scifb0_data_b), 4328 SH_PFC_PIN_GROUP(scifb0_clk_b), 4329 SH_PFC_PIN_GROUP(scifb0_ctrl_b), 4330 SH_PFC_PIN_GROUP(scifb0_data_c), 4331 SH_PFC_PIN_GROUP(scifb1_data), 4332 SH_PFC_PIN_GROUP(scifb1_clk), 4333 SH_PFC_PIN_GROUP(scifb1_ctrl), 4334 SH_PFC_PIN_GROUP(scifb1_data_b), 4335 SH_PFC_PIN_GROUP(scifb1_clk_b), 4336 SH_PFC_PIN_GROUP(scifb1_ctrl_b), 4337 SH_PFC_PIN_GROUP(scifb1_data_c), 4338 SH_PFC_PIN_GROUP(scifb1_data_d), 4339 SH_PFC_PIN_GROUP(scifb1_data_e), 4340 SH_PFC_PIN_GROUP(scifb1_clk_e), 4341 SH_PFC_PIN_GROUP(scifb1_data_f), 4342 SH_PFC_PIN_GROUP(scifb1_data_g), 4343 SH_PFC_PIN_GROUP(scifb1_clk_g), 4344 SH_PFC_PIN_GROUP(scifb2_data), 4345 SH_PFC_PIN_GROUP(scifb2_clk), 4346 SH_PFC_PIN_GROUP(scifb2_ctrl), 4347 SH_PFC_PIN_GROUP(scifb2_data_b), 4348 SH_PFC_PIN_GROUP(scifb2_clk_b), 4349 SH_PFC_PIN_GROUP(scifb2_ctrl_b), 4350 SH_PFC_PIN_GROUP(scifb2_data_c), 4351 SH_PFC_PIN_GROUP(scif_clk), 4352 SH_PFC_PIN_GROUP(scif_clk_b), 4353 SH_PFC_PIN_GROUP(sdhi0_data1), 4354 SH_PFC_PIN_GROUP(sdhi0_data4), 4355 SH_PFC_PIN_GROUP(sdhi0_ctrl), 4356 SH_PFC_PIN_GROUP(sdhi0_cd), 4357 SH_PFC_PIN_GROUP(sdhi0_wp), 4358 SH_PFC_PIN_GROUP(sdhi1_data1), 4359 SH_PFC_PIN_GROUP(sdhi1_data4), 4360 SH_PFC_PIN_GROUP(sdhi1_ctrl), 4361 SH_PFC_PIN_GROUP(sdhi1_cd), 4362 SH_PFC_PIN_GROUP(sdhi1_wp), 4363 SH_PFC_PIN_GROUP(sdhi2_data1), 4364 SH_PFC_PIN_GROUP(sdhi2_data4), 4365 SH_PFC_PIN_GROUP(sdhi2_ctrl), 4366 SH_PFC_PIN_GROUP(sdhi2_cd), 4367 SH_PFC_PIN_GROUP(sdhi2_wp), 4368 SH_PFC_PIN_GROUP(sdhi3_data1), 4369 SH_PFC_PIN_GROUP(sdhi3_data4), 4370 SH_PFC_PIN_GROUP(sdhi3_ctrl), 4371 SH_PFC_PIN_GROUP(sdhi3_cd), 4372 SH_PFC_PIN_GROUP(sdhi3_wp), 4373 SH_PFC_PIN_GROUP(ssi0_data), 4374 SH_PFC_PIN_GROUP(ssi0129_ctrl), 4375 SH_PFC_PIN_GROUP(ssi1_data), 4376 SH_PFC_PIN_GROUP(ssi1_ctrl), 4377 SH_PFC_PIN_GROUP(ssi2_data), 4378 SH_PFC_PIN_GROUP(ssi2_ctrl), 4379 SH_PFC_PIN_GROUP(ssi3_data), 4380 SH_PFC_PIN_GROUP(ssi34_ctrl), 4381 SH_PFC_PIN_GROUP(ssi4_data), 4382 SH_PFC_PIN_GROUP(ssi4_ctrl), 4383 SH_PFC_PIN_GROUP(ssi5), 4384 SH_PFC_PIN_GROUP(ssi5_b), 4385 SH_PFC_PIN_GROUP(ssi5_c), 4386 SH_PFC_PIN_GROUP(ssi6), 4387 SH_PFC_PIN_GROUP(ssi6_b), 4388 SH_PFC_PIN_GROUP(ssi7_data), 4389 SH_PFC_PIN_GROUP(ssi7_b_data), 4390 SH_PFC_PIN_GROUP(ssi7_c_data), 4391 SH_PFC_PIN_GROUP(ssi78_ctrl), 4392 SH_PFC_PIN_GROUP(ssi78_b_ctrl), 4393 SH_PFC_PIN_GROUP(ssi78_c_ctrl), 4394 SH_PFC_PIN_GROUP(ssi8_data), 4395 SH_PFC_PIN_GROUP(ssi8_b_data), 4396 SH_PFC_PIN_GROUP(ssi8_c_data), 4397 SH_PFC_PIN_GROUP(ssi9_data), 4398 SH_PFC_PIN_GROUP(ssi9_ctrl), 4399 SH_PFC_PIN_GROUP(tpu0_to0), 4400 SH_PFC_PIN_GROUP(tpu0_to1), 4401 SH_PFC_PIN_GROUP(tpu0_to2), 4402 SH_PFC_PIN_GROUP(tpu0_to3), 4403 SH_PFC_PIN_GROUP(usb0), 4404 SH_PFC_PIN_GROUP(usb0_ovc_vbus), 4405 SH_PFC_PIN_GROUP(usb1), 4406 SH_PFC_PIN_GROUP(usb1_pwen), 4407 SH_PFC_PIN_GROUP(usb2), 4408 VIN_DATA_PIN_GROUP(vin0_data, 24), 4409 VIN_DATA_PIN_GROUP(vin0_data, 20), 4410 SH_PFC_PIN_GROUP(vin0_data18), 4411 VIN_DATA_PIN_GROUP(vin0_data, 16), 4412 VIN_DATA_PIN_GROUP(vin0_data, 12), 4413 VIN_DATA_PIN_GROUP(vin0_data, 10), 4414 VIN_DATA_PIN_GROUP(vin0_data, 8), 4415 VIN_DATA_PIN_GROUP(vin0_data, 4), 4416 SH_PFC_PIN_GROUP(vin0_sync), 4417 SH_PFC_PIN_GROUP(vin0_field), 4418 SH_PFC_PIN_GROUP(vin0_clkenb), 4419 SH_PFC_PIN_GROUP(vin0_clk), 4420 VIN_DATA_PIN_GROUP(vin1_data, 24), 4421 VIN_DATA_PIN_GROUP(vin1_data, 20), 4422 SH_PFC_PIN_GROUP(vin1_data18), 4423 VIN_DATA_PIN_GROUP(vin1_data, 16), 4424 VIN_DATA_PIN_GROUP(vin1_data, 12), 4425 VIN_DATA_PIN_GROUP(vin1_data, 10), 4426 VIN_DATA_PIN_GROUP(vin1_data, 8), 4427 VIN_DATA_PIN_GROUP(vin1_data, 4), 4428 VIN_DATA_PIN_GROUP(vin1_data, 24, _b), 4429 VIN_DATA_PIN_GROUP(vin1_data, 20, _b), 4430 SH_PFC_PIN_GROUP(vin1_data18_b), 4431 VIN_DATA_PIN_GROUP(vin1_data, 16, _b), 4432 VIN_DATA_PIN_GROUP(vin1_data, 12, _b), 4433 VIN_DATA_PIN_GROUP(vin1_data, 10, _b), 4434 VIN_DATA_PIN_GROUP(vin1_data, 8, _b), 4435 VIN_DATA_PIN_GROUP(vin1_data, 4, _b), 4436 SH_PFC_PIN_GROUP(vin1_sync), 4437 SH_PFC_PIN_GROUP(vin1_sync_b), 4438 SH_PFC_PIN_GROUP(vin1_field), 4439 SH_PFC_PIN_GROUP(vin1_field_b), 4440 SH_PFC_PIN_GROUP(vin1_clkenb), 4441 SH_PFC_PIN_GROUP(vin1_clkenb_b), 4442 SH_PFC_PIN_GROUP(vin1_clk), 4443 SH_PFC_PIN_GROUP(vin1_clk_b), 4444 VIN_DATA_PIN_GROUP(vin2_data, 24), 4445 SH_PFC_PIN_GROUP(vin2_data18), 4446 VIN_DATA_PIN_GROUP(vin2_data, 16), 4447 VIN_DATA_PIN_GROUP(vin2_data, 8), 4448 VIN_DATA_PIN_GROUP(vin2_data, 4), 4449 SH_PFC_PIN_GROUP(vin2_g8), 4450 SH_PFC_PIN_GROUP(vin2_sync), 4451 SH_PFC_PIN_GROUP(vin2_field), 4452 SH_PFC_PIN_GROUP(vin2_clkenb), 4453 SH_PFC_PIN_GROUP(vin2_clk), 4454 SH_PFC_PIN_GROUP(vin3_data8), 4455 SH_PFC_PIN_GROUP(vin3_sync), 4456 SH_PFC_PIN_GROUP(vin3_field), 4457 SH_PFC_PIN_GROUP(vin3_clkenb), 4458 SH_PFC_PIN_GROUP(vin3_clk), 4459 }, 4460 #ifdef CONFIG_PINCTRL_PFC_R8A7790 4461 .automotive = { 4462 SH_PFC_PIN_GROUP(mlb_3pin), 4463 } 4464 #endif /* CONFIG_PINCTRL_PFC_R8A7790 */ 4465 }; 4466 4467 static const char * const audio_clk_groups[] = { 4468 "audio_clk_a", 4469 "audio_clk_b", 4470 "audio_clk_c", 4471 "audio_clkout", 4472 "audio_clkout_b", 4473 "audio_clkout_c", 4474 "audio_clkout_d", 4475 }; 4476 4477 static const char * const avb_groups[] = { 4478 "avb_link", 4479 "avb_magic", 4480 "avb_phy_int", 4481 "avb_mdio", 4482 "avb_mii", 4483 "avb_gmii", 4484 }; 4485 4486 static const char * const can0_groups[] = { 4487 "can0_data", 4488 "can0_data_b", 4489 "can0_data_c", 4490 "can0_data_d", 4491 }; 4492 4493 static const char * const can1_groups[] = { 4494 "can1_data", 4495 "can1_data_b", 4496 }; 4497 4498 static const char * const can_clk_groups[] = { 4499 "can_clk", 4500 "can_clk_b", 4501 }; 4502 4503 static const char * const du_groups[] = { 4504 "du_rgb666", 4505 "du_rgb888", 4506 "du_clk_out_0", 4507 "du_clk_out_1", 4508 "du_sync_0", 4509 "du_sync_1", 4510 "du_cde", 4511 }; 4512 4513 static const char * const du0_groups[] = { 4514 "du0_clk_in", 4515 }; 4516 4517 static const char * const du1_groups[] = { 4518 "du1_clk_in", 4519 }; 4520 4521 static const char * const du2_groups[] = { 4522 "du2_clk_in", 4523 }; 4524 4525 static const char * const eth_groups[] = { 4526 "eth_link", 4527 "eth_magic", 4528 "eth_mdio", 4529 "eth_rmii", 4530 }; 4531 4532 static const char * const hscif0_groups[] = { 4533 "hscif0_data", 4534 "hscif0_clk", 4535 "hscif0_ctrl", 4536 "hscif0_data_b", 4537 "hscif0_ctrl_b", 4538 "hscif0_data_c", 4539 "hscif0_ctrl_c", 4540 "hscif0_data_d", 4541 "hscif0_ctrl_d", 4542 "hscif0_data_e", 4543 "hscif0_ctrl_e", 4544 "hscif0_data_f", 4545 "hscif0_ctrl_f", 4546 }; 4547 4548 static const char * const hscif1_groups[] = { 4549 "hscif1_data", 4550 "hscif1_clk", 4551 "hscif1_ctrl", 4552 "hscif1_data_b", 4553 "hscif1_clk_b", 4554 "hscif1_ctrl_b", 4555 }; 4556 4557 static const char * const i2c0_groups[] = { 4558 "i2c0", 4559 }; 4560 4561 static const char * const i2c1_groups[] = { 4562 "i2c1", 4563 "i2c1_b", 4564 "i2c1_c", 4565 }; 4566 4567 static const char * const i2c2_groups[] = { 4568 "i2c2", 4569 "i2c2_b", 4570 "i2c2_c", 4571 "i2c2_d", 4572 "i2c2_e", 4573 }; 4574 4575 static const char * const i2c3_groups[] = { 4576 "i2c3", 4577 }; 4578 4579 static const char * const iic0_groups[] = { 4580 "iic0", 4581 }; 4582 4583 static const char * const iic1_groups[] = { 4584 "iic1", 4585 "iic1_b", 4586 "iic1_c", 4587 }; 4588 4589 static const char * const iic2_groups[] = { 4590 "iic2", 4591 "iic2_b", 4592 "iic2_c", 4593 "iic2_d", 4594 "iic2_e", 4595 }; 4596 4597 static const char * const iic3_groups[] = { 4598 "iic3", 4599 }; 4600 4601 static const char * const intc_groups[] = { 4602 "intc_irq0", 4603 "intc_irq1", 4604 "intc_irq2", 4605 "intc_irq3", 4606 }; 4607 4608 #ifdef CONFIG_PINCTRL_PFC_R8A7790 4609 static const char * const mlb_groups[] = { 4610 "mlb_3pin", 4611 }; 4612 #endif /* CONFIG_PINCTRL_PFC_R8A7790 */ 4613 4614 static const char * const mmc0_groups[] = { 4615 "mmc0_data1", 4616 "mmc0_data4", 4617 "mmc0_data8", 4618 "mmc0_ctrl", 4619 }; 4620 4621 static const char * const mmc1_groups[] = { 4622 "mmc1_data1", 4623 "mmc1_data4", 4624 "mmc1_data8", 4625 "mmc1_ctrl", 4626 }; 4627 4628 static const char * const msiof0_groups[] = { 4629 "msiof0_clk", 4630 "msiof0_sync", 4631 "msiof0_ss1", 4632 "msiof0_ss2", 4633 "msiof0_rx", 4634 "msiof0_tx", 4635 "msiof0_clk_b", 4636 "msiof0_ss1_b", 4637 "msiof0_ss2_b", 4638 "msiof0_rx_b", 4639 "msiof0_tx_b", 4640 }; 4641 4642 static const char * const msiof1_groups[] = { 4643 "msiof1_clk", 4644 "msiof1_sync", 4645 "msiof1_ss1", 4646 "msiof1_ss2", 4647 "msiof1_rx", 4648 "msiof1_tx", 4649 "msiof1_clk_b", 4650 "msiof1_ss1_b", 4651 "msiof1_ss2_b", 4652 "msiof1_rx_b", 4653 "msiof1_tx_b", 4654 }; 4655 4656 static const char * const msiof2_groups[] = { 4657 "msiof2_clk", 4658 "msiof2_sync", 4659 "msiof2_ss1", 4660 "msiof2_ss2", 4661 "msiof2_rx", 4662 "msiof2_tx", 4663 }; 4664 4665 static const char * const msiof3_groups[] = { 4666 "msiof3_clk", 4667 "msiof3_sync", 4668 "msiof3_ss1", 4669 "msiof3_ss2", 4670 "msiof3_rx", 4671 "msiof3_tx", 4672 "msiof3_clk_b", 4673 "msiof3_sync_b", 4674 "msiof3_rx_b", 4675 "msiof3_tx_b", 4676 }; 4677 4678 static const char * const pwm0_groups[] = { 4679 "pwm0", 4680 "pwm0_b", 4681 }; 4682 4683 static const char * const pwm1_groups[] = { 4684 "pwm1", 4685 "pwm1_b", 4686 }; 4687 4688 static const char * const pwm2_groups[] = { 4689 "pwm2", 4690 }; 4691 4692 static const char * const pwm3_groups[] = { 4693 "pwm3", 4694 }; 4695 4696 static const char * const pwm4_groups[] = { 4697 "pwm4", 4698 }; 4699 4700 static const char * const pwm5_groups[] = { 4701 "pwm5", 4702 }; 4703 4704 static const char * const pwm6_groups[] = { 4705 "pwm6", 4706 }; 4707 4708 static const char * const qspi_groups[] = { 4709 "qspi_ctrl", 4710 "qspi_data2", 4711 "qspi_data4", 4712 }; 4713 4714 static const char * const scif0_groups[] = { 4715 "scif0_data", 4716 "scif0_clk", 4717 "scif0_ctrl", 4718 "scif0_data_b", 4719 }; 4720 4721 static const char * const scif1_groups[] = { 4722 "scif1_data", 4723 "scif1_clk", 4724 "scif1_ctrl", 4725 "scif1_data_b", 4726 "scif1_data_c", 4727 "scif1_data_d", 4728 "scif1_clk_d", 4729 "scif1_data_e", 4730 "scif1_clk_e", 4731 }; 4732 4733 static const char * const scif2_groups[] = { 4734 "scif2_data", 4735 "scif2_clk", 4736 "scif2_data_b", 4737 }; 4738 4739 static const char * const scifa0_groups[] = { 4740 "scifa0_data", 4741 "scifa0_clk", 4742 "scifa0_ctrl", 4743 "scifa0_data_b", 4744 "scifa0_clk_b", 4745 "scifa0_ctrl_b", 4746 }; 4747 4748 static const char * const scifa1_groups[] = { 4749 "scifa1_data", 4750 "scifa1_clk", 4751 "scifa1_ctrl", 4752 "scifa1_data_b", 4753 "scifa1_clk_b", 4754 "scifa1_ctrl_b", 4755 "scifa1_data_c", 4756 "scifa1_clk_c", 4757 "scifa1_ctrl_c", 4758 "scifa1_data_d", 4759 "scifa1_clk_d", 4760 "scifa1_ctrl_d", 4761 }; 4762 4763 static const char * const scifa2_groups[] = { 4764 "scifa2_data", 4765 "scifa2_clk", 4766 "scifa2_ctrl", 4767 "scifa2_data_b", 4768 "scifa2_data_c", 4769 "scifa2_clk_c", 4770 }; 4771 4772 static const char * const scifb0_groups[] = { 4773 "scifb0_data", 4774 "scifb0_clk", 4775 "scifb0_ctrl", 4776 "scifb0_data_b", 4777 "scifb0_clk_b", 4778 "scifb0_ctrl_b", 4779 "scifb0_data_c", 4780 }; 4781 4782 static const char * const scifb1_groups[] = { 4783 "scifb1_data", 4784 "scifb1_clk", 4785 "scifb1_ctrl", 4786 "scifb1_data_b", 4787 "scifb1_clk_b", 4788 "scifb1_ctrl_b", 4789 "scifb1_data_c", 4790 "scifb1_data_d", 4791 "scifb1_data_e", 4792 "scifb1_clk_e", 4793 "scifb1_data_f", 4794 "scifb1_data_g", 4795 "scifb1_clk_g", 4796 }; 4797 4798 static const char * const scifb2_groups[] = { 4799 "scifb2_data", 4800 "scifb2_clk", 4801 "scifb2_ctrl", 4802 "scifb2_data_b", 4803 "scifb2_clk_b", 4804 "scifb2_ctrl_b", 4805 "scifb2_data_c", 4806 }; 4807 4808 static const char * const scif_clk_groups[] = { 4809 "scif_clk", 4810 "scif_clk_b", 4811 }; 4812 4813 static const char * const sdhi0_groups[] = { 4814 "sdhi0_data1", 4815 "sdhi0_data4", 4816 "sdhi0_ctrl", 4817 "sdhi0_cd", 4818 "sdhi0_wp", 4819 }; 4820 4821 static const char * const sdhi1_groups[] = { 4822 "sdhi1_data1", 4823 "sdhi1_data4", 4824 "sdhi1_ctrl", 4825 "sdhi1_cd", 4826 "sdhi1_wp", 4827 }; 4828 4829 static const char * const sdhi2_groups[] = { 4830 "sdhi2_data1", 4831 "sdhi2_data4", 4832 "sdhi2_ctrl", 4833 "sdhi2_cd", 4834 "sdhi2_wp", 4835 }; 4836 4837 static const char * const sdhi3_groups[] = { 4838 "sdhi3_data1", 4839 "sdhi3_data4", 4840 "sdhi3_ctrl", 4841 "sdhi3_cd", 4842 "sdhi3_wp", 4843 }; 4844 4845 static const char * const ssi_groups[] = { 4846 "ssi0_data", 4847 "ssi0129_ctrl", 4848 "ssi1_data", 4849 "ssi1_ctrl", 4850 "ssi2_data", 4851 "ssi2_ctrl", 4852 "ssi3_data", 4853 "ssi34_ctrl", 4854 "ssi4_data", 4855 "ssi4_ctrl", 4856 "ssi5", 4857 "ssi5_b", 4858 "ssi5_c", 4859 "ssi6", 4860 "ssi6_b", 4861 "ssi7_data", 4862 "ssi7_b_data", 4863 "ssi7_c_data", 4864 "ssi78_ctrl", 4865 "ssi78_b_ctrl", 4866 "ssi78_c_ctrl", 4867 "ssi8_data", 4868 "ssi8_b_data", 4869 "ssi8_c_data", 4870 "ssi9_data", 4871 "ssi9_ctrl", 4872 }; 4873 4874 static const char * const tpu0_groups[] = { 4875 "tpu0_to0", 4876 "tpu0_to1", 4877 "tpu0_to2", 4878 "tpu0_to3", 4879 }; 4880 4881 static const char * const usb0_groups[] = { 4882 "usb0", 4883 "usb0_ovc_vbus", 4884 }; 4885 4886 static const char * const usb1_groups[] = { 4887 "usb1", 4888 "usb1_pwen", 4889 }; 4890 4891 static const char * const usb2_groups[] = { 4892 "usb2", 4893 }; 4894 4895 static const char * const vin0_groups[] = { 4896 "vin0_data24", 4897 "vin0_data20", 4898 "vin0_data18", 4899 "vin0_data16", 4900 "vin0_data12", 4901 "vin0_data10", 4902 "vin0_data8", 4903 "vin0_data4", 4904 "vin0_sync", 4905 "vin0_field", 4906 "vin0_clkenb", 4907 "vin0_clk", 4908 }; 4909 4910 static const char * const vin1_groups[] = { 4911 "vin1_data24", 4912 "vin1_data20", 4913 "vin1_data18", 4914 "vin1_data16", 4915 "vin1_data12", 4916 "vin1_data10", 4917 "vin1_data8", 4918 "vin1_data4", 4919 "vin1_data24_b", 4920 "vin1_data20_b", 4921 "vin1_data18_b", 4922 "vin1_data16_b", 4923 "vin1_data12_b", 4924 "vin1_data10_b", 4925 "vin1_data8_b", 4926 "vin1_data4_b", 4927 "vin1_sync", 4928 "vin1_sync_b", 4929 "vin1_field", 4930 "vin1_field_b", 4931 "vin1_clkenb", 4932 "vin1_clkenb_b", 4933 "vin1_clk", 4934 "vin1_clk_b", 4935 }; 4936 4937 static const char * const vin2_groups[] = { 4938 "vin2_data24", 4939 "vin2_data18", 4940 "vin2_data16", 4941 "vin2_data8", 4942 "vin2_data4", 4943 "vin2_g8", 4944 "vin2_sync", 4945 "vin2_field", 4946 "vin2_clkenb", 4947 "vin2_clk", 4948 }; 4949 4950 static const char * const vin3_groups[] = { 4951 "vin3_data8", 4952 "vin3_sync", 4953 "vin3_field", 4954 "vin3_clkenb", 4955 "vin3_clk", 4956 }; 4957 4958 static const struct { 4959 struct sh_pfc_function common[58]; 4960 #ifdef CONFIG_PINCTRL_PFC_R8A7790 4961 struct sh_pfc_function automotive[1]; 4962 #endif 4963 } pinmux_functions = { 4964 .common = { 4965 SH_PFC_FUNCTION(audio_clk), 4966 SH_PFC_FUNCTION(avb), 4967 SH_PFC_FUNCTION(du), 4968 SH_PFC_FUNCTION(can0), 4969 SH_PFC_FUNCTION(can1), 4970 SH_PFC_FUNCTION(can_clk), 4971 SH_PFC_FUNCTION(du0), 4972 SH_PFC_FUNCTION(du1), 4973 SH_PFC_FUNCTION(du2), 4974 SH_PFC_FUNCTION(eth), 4975 SH_PFC_FUNCTION(hscif0), 4976 SH_PFC_FUNCTION(hscif1), 4977 SH_PFC_FUNCTION(i2c0), 4978 SH_PFC_FUNCTION(i2c1), 4979 SH_PFC_FUNCTION(i2c2), 4980 SH_PFC_FUNCTION(i2c3), 4981 SH_PFC_FUNCTION(iic0), 4982 SH_PFC_FUNCTION(iic1), 4983 SH_PFC_FUNCTION(iic2), 4984 SH_PFC_FUNCTION(iic3), 4985 SH_PFC_FUNCTION(intc), 4986 SH_PFC_FUNCTION(mmc0), 4987 SH_PFC_FUNCTION(mmc1), 4988 SH_PFC_FUNCTION(msiof0), 4989 SH_PFC_FUNCTION(msiof1), 4990 SH_PFC_FUNCTION(msiof2), 4991 SH_PFC_FUNCTION(msiof3), 4992 SH_PFC_FUNCTION(pwm0), 4993 SH_PFC_FUNCTION(pwm1), 4994 SH_PFC_FUNCTION(pwm2), 4995 SH_PFC_FUNCTION(pwm3), 4996 SH_PFC_FUNCTION(pwm4), 4997 SH_PFC_FUNCTION(pwm5), 4998 SH_PFC_FUNCTION(pwm6), 4999 SH_PFC_FUNCTION(qspi), 5000 SH_PFC_FUNCTION(scif0), 5001 SH_PFC_FUNCTION(scif1), 5002 SH_PFC_FUNCTION(scif2), 5003 SH_PFC_FUNCTION(scifa0), 5004 SH_PFC_FUNCTION(scifa1), 5005 SH_PFC_FUNCTION(scifa2), 5006 SH_PFC_FUNCTION(scifb0), 5007 SH_PFC_FUNCTION(scifb1), 5008 SH_PFC_FUNCTION(scifb2), 5009 SH_PFC_FUNCTION(scif_clk), 5010 SH_PFC_FUNCTION(sdhi0), 5011 SH_PFC_FUNCTION(sdhi1), 5012 SH_PFC_FUNCTION(sdhi2), 5013 SH_PFC_FUNCTION(sdhi3), 5014 SH_PFC_FUNCTION(ssi), 5015 SH_PFC_FUNCTION(tpu0), 5016 SH_PFC_FUNCTION(usb0), 5017 SH_PFC_FUNCTION(usb1), 5018 SH_PFC_FUNCTION(usb2), 5019 SH_PFC_FUNCTION(vin0), 5020 SH_PFC_FUNCTION(vin1), 5021 SH_PFC_FUNCTION(vin2), 5022 SH_PFC_FUNCTION(vin3), 5023 }, 5024 #ifdef CONFIG_PINCTRL_PFC_R8A7790 5025 .automotive = { 5026 SH_PFC_FUNCTION(mlb), 5027 } 5028 #endif /* CONFIG_PINCTRL_PFC_R8A7790 */ 5029 }; 5030 5031 static const struct pinmux_cfg_reg pinmux_config_regs[] = { 5032 { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1, GROUP( 5033 GP_0_31_FN, FN_IP3_17_15, 5034 GP_0_30_FN, FN_IP3_14_12, 5035 GP_0_29_FN, FN_IP3_11_8, 5036 GP_0_28_FN, FN_IP3_7_4, 5037 GP_0_27_FN, FN_IP3_3_0, 5038 GP_0_26_FN, FN_IP2_28_26, 5039 GP_0_25_FN, FN_IP2_25_22, 5040 GP_0_24_FN, FN_IP2_21_18, 5041 GP_0_23_FN, FN_IP2_17_15, 5042 GP_0_22_FN, FN_IP2_14_12, 5043 GP_0_21_FN, FN_IP2_11_9, 5044 GP_0_20_FN, FN_IP2_8_6, 5045 GP_0_19_FN, FN_IP2_5_3, 5046 GP_0_18_FN, FN_IP2_2_0, 5047 GP_0_17_FN, FN_IP1_29_28, 5048 GP_0_16_FN, FN_IP1_27_26, 5049 GP_0_15_FN, FN_IP1_25_22, 5050 GP_0_14_FN, FN_IP1_21_18, 5051 GP_0_13_FN, FN_IP1_17_15, 5052 GP_0_12_FN, FN_IP1_14_12, 5053 GP_0_11_FN, FN_IP1_11_8, 5054 GP_0_10_FN, FN_IP1_7_4, 5055 GP_0_9_FN, FN_IP1_3_0, 5056 GP_0_8_FN, FN_IP0_30_27, 5057 GP_0_7_FN, FN_IP0_26_23, 5058 GP_0_6_FN, FN_IP0_22_20, 5059 GP_0_5_FN, FN_IP0_19_16, 5060 GP_0_4_FN, FN_IP0_15_12, 5061 GP_0_3_FN, FN_IP0_11_9, 5062 GP_0_2_FN, FN_IP0_8_6, 5063 GP_0_1_FN, FN_IP0_5_3, 5064 GP_0_0_FN, FN_IP0_2_0 )) 5065 }, 5066 { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1, GROUP( 5067 0, 0, 5068 0, 0, 5069 GP_1_29_FN, FN_IP6_13_11, 5070 GP_1_28_FN, FN_IP6_10_9, 5071 GP_1_27_FN, FN_IP6_8_6, 5072 GP_1_26_FN, FN_IP6_5_3, 5073 GP_1_25_FN, FN_IP6_2_0, 5074 GP_1_24_FN, FN_IP5_29_27, 5075 GP_1_23_FN, FN_IP5_26_24, 5076 GP_1_22_FN, FN_IP5_23_21, 5077 GP_1_21_FN, FN_IP5_20_18, 5078 GP_1_20_FN, FN_IP5_17_15, 5079 GP_1_19_FN, FN_IP5_14_13, 5080 GP_1_18_FN, FN_IP5_12_10, 5081 GP_1_17_FN, FN_IP5_9_6, 5082 GP_1_16_FN, FN_IP5_5_3, 5083 GP_1_15_FN, FN_IP5_2_0, 5084 GP_1_14_FN, FN_IP4_29_27, 5085 GP_1_13_FN, FN_IP4_26_24, 5086 GP_1_12_FN, FN_IP4_23_21, 5087 GP_1_11_FN, FN_IP4_20_18, 5088 GP_1_10_FN, FN_IP4_17_15, 5089 GP_1_9_FN, FN_IP4_14_12, 5090 GP_1_8_FN, FN_IP4_11_9, 5091 GP_1_7_FN, FN_IP4_8_6, 5092 GP_1_6_FN, FN_IP4_5_3, 5093 GP_1_5_FN, FN_IP4_2_0, 5094 GP_1_4_FN, FN_IP3_31_29, 5095 GP_1_3_FN, FN_IP3_28_26, 5096 GP_1_2_FN, FN_IP3_25_23, 5097 GP_1_1_FN, FN_IP3_22_20, 5098 GP_1_0_FN, FN_IP3_19_18, )) 5099 }, 5100 { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1, GROUP( 5101 0, 0, 5102 0, 0, 5103 GP_2_29_FN, FN_IP7_15_13, 5104 GP_2_28_FN, FN_IP7_12_10, 5105 GP_2_27_FN, FN_IP7_9_8, 5106 GP_2_26_FN, FN_IP7_7_6, 5107 GP_2_25_FN, FN_IP7_5_3, 5108 GP_2_24_FN, FN_IP7_2_0, 5109 GP_2_23_FN, FN_IP6_31_29, 5110 GP_2_22_FN, FN_IP6_28_26, 5111 GP_2_21_FN, FN_IP6_25_23, 5112 GP_2_20_FN, FN_IP6_22_20, 5113 GP_2_19_FN, FN_IP6_19_17, 5114 GP_2_18_FN, FN_IP6_16_14, 5115 GP_2_17_FN, FN_VI1_DATA7_VI1_B7, 5116 GP_2_16_FN, FN_IP8_27, 5117 GP_2_15_FN, FN_IP8_26, 5118 GP_2_14_FN, FN_IP8_25_24, 5119 GP_2_13_FN, FN_IP8_23_22, 5120 GP_2_12_FN, FN_IP8_21_20, 5121 GP_2_11_FN, FN_IP8_19_18, 5122 GP_2_10_FN, FN_IP8_17_16, 5123 GP_2_9_FN, FN_IP8_15_14, 5124 GP_2_8_FN, FN_IP8_13_12, 5125 GP_2_7_FN, FN_IP8_11_10, 5126 GP_2_6_FN, FN_IP8_9_8, 5127 GP_2_5_FN, FN_IP8_7_6, 5128 GP_2_4_FN, FN_IP8_5_4, 5129 GP_2_3_FN, FN_IP8_3_2, 5130 GP_2_2_FN, FN_IP8_1_0, 5131 GP_2_1_FN, FN_IP7_30_29, 5132 GP_2_0_FN, FN_IP7_28_27 )) 5133 }, 5134 { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1, GROUP( 5135 GP_3_31_FN, FN_IP11_21_18, 5136 GP_3_30_FN, FN_IP11_17_15, 5137 GP_3_29_FN, FN_IP11_14_13, 5138 GP_3_28_FN, FN_IP11_12_11, 5139 GP_3_27_FN, FN_IP11_10_9, 5140 GP_3_26_FN, FN_IP11_8_7, 5141 GP_3_25_FN, FN_IP11_6_5, 5142 GP_3_24_FN, FN_IP11_4, 5143 GP_3_23_FN, FN_IP11_3_0, 5144 GP_3_22_FN, FN_IP10_29_26, 5145 GP_3_21_FN, FN_IP10_25_23, 5146 GP_3_20_FN, FN_IP10_22_19, 5147 GP_3_19_FN, FN_IP10_18_15, 5148 GP_3_18_FN, FN_IP10_14_11, 5149 GP_3_17_FN, FN_IP10_10_7, 5150 GP_3_16_FN, FN_IP10_6_4, 5151 GP_3_15_FN, FN_IP10_3_0, 5152 GP_3_14_FN, FN_IP9_31_28, 5153 GP_3_13_FN, FN_IP9_27_26, 5154 GP_3_12_FN, FN_IP9_25_24, 5155 GP_3_11_FN, FN_IP9_23_22, 5156 GP_3_10_FN, FN_IP9_21_20, 5157 GP_3_9_FN, FN_IP9_19_18, 5158 GP_3_8_FN, FN_IP9_17_16, 5159 GP_3_7_FN, FN_IP9_15_12, 5160 GP_3_6_FN, FN_IP9_11_8, 5161 GP_3_5_FN, FN_IP9_7_6, 5162 GP_3_4_FN, FN_IP9_5_4, 5163 GP_3_3_FN, FN_IP9_3_2, 5164 GP_3_2_FN, FN_IP9_1_0, 5165 GP_3_1_FN, FN_IP8_30_29, 5166 GP_3_0_FN, FN_IP8_28 )) 5167 }, 5168 { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1, GROUP( 5169 GP_4_31_FN, FN_IP14_18_16, 5170 GP_4_30_FN, FN_IP14_15_12, 5171 GP_4_29_FN, FN_IP14_11_9, 5172 GP_4_28_FN, FN_IP14_8_6, 5173 GP_4_27_FN, FN_IP14_5_3, 5174 GP_4_26_FN, FN_IP14_2_0, 5175 GP_4_25_FN, FN_IP13_30_29, 5176 GP_4_24_FN, FN_IP13_28_26, 5177 GP_4_23_FN, FN_IP13_25_23, 5178 GP_4_22_FN, FN_IP13_22_19, 5179 GP_4_21_FN, FN_IP13_18_16, 5180 GP_4_20_FN, FN_IP13_15_13, 5181 GP_4_19_FN, FN_IP13_12_10, 5182 GP_4_18_FN, FN_IP13_9_7, 5183 GP_4_17_FN, FN_IP13_6_3, 5184 GP_4_16_FN, FN_IP13_2_0, 5185 GP_4_15_FN, FN_IP12_30_28, 5186 GP_4_14_FN, FN_IP12_27_25, 5187 GP_4_13_FN, FN_IP12_24_23, 5188 GP_4_12_FN, FN_IP12_22_20, 5189 GP_4_11_FN, FN_IP12_19_17, 5190 GP_4_10_FN, FN_IP12_16_14, 5191 GP_4_9_FN, FN_IP12_13_11, 5192 GP_4_8_FN, FN_IP12_10_8, 5193 GP_4_7_FN, FN_IP12_7_6, 5194 GP_4_6_FN, FN_IP12_5_4, 5195 GP_4_5_FN, FN_IP12_3_2, 5196 GP_4_4_FN, FN_IP12_1_0, 5197 GP_4_3_FN, FN_IP11_31_30, 5198 GP_4_2_FN, FN_IP11_29_27, 5199 GP_4_1_FN, FN_IP11_26_24, 5200 GP_4_0_FN, FN_IP11_23_22 )) 5201 }, 5202 { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1, GROUP( 5203 GP_5_31_FN, FN_IP7_24_22, 5204 GP_5_30_FN, FN_IP7_21_19, 5205 GP_5_29_FN, FN_IP7_18_16, 5206 GP_5_28_FN, FN_DU_DOTCLKIN2, 5207 GP_5_27_FN, FN_IP7_26_25, 5208 GP_5_26_FN, FN_DU_DOTCLKIN0, 5209 GP_5_25_FN, FN_AVS2, 5210 GP_5_24_FN, FN_AVS1, 5211 GP_5_23_FN, FN_USB2_OVC, 5212 GP_5_22_FN, FN_USB2_PWEN, 5213 GP_5_21_FN, FN_IP16_7, 5214 GP_5_20_FN, FN_IP16_6, 5215 GP_5_19_FN, FN_USB0_OVC_VBUS, 5216 GP_5_18_FN, FN_USB0_PWEN, 5217 GP_5_17_FN, FN_IP16_5_3, 5218 GP_5_16_FN, FN_IP16_2_0, 5219 GP_5_15_FN, FN_IP15_29_28, 5220 GP_5_14_FN, FN_IP15_27_26, 5221 GP_5_13_FN, FN_IP15_25_23, 5222 GP_5_12_FN, FN_IP15_22_20, 5223 GP_5_11_FN, FN_IP15_19_18, 5224 GP_5_10_FN, FN_IP15_17_16, 5225 GP_5_9_FN, FN_IP15_15_14, 5226 GP_5_8_FN, FN_IP15_13_12, 5227 GP_5_7_FN, FN_IP15_11_9, 5228 GP_5_6_FN, FN_IP15_8_6, 5229 GP_5_5_FN, FN_IP15_5_3, 5230 GP_5_4_FN, FN_IP15_2_0, 5231 GP_5_3_FN, FN_IP14_30_28, 5232 GP_5_2_FN, FN_IP14_27_25, 5233 GP_5_1_FN, FN_IP14_24_22, 5234 GP_5_0_FN, FN_IP14_21_19 )) 5235 }, 5236 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32, 5237 GROUP(1, 4, 4, 3, 4, 4, 3, 3, 3, 3), 5238 GROUP( 5239 /* IP0_31 [1] */ 5240 0, 0, 5241 /* IP0_30_27 [4] */ 5242 FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0, 0, 5243 FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0, 5244 0, 0, 0, 0, 0, 0, 0, 0, 0, 5245 /* IP0_26_23 [4] */ 5246 FN_D7, FN_AD_DI_B, FN_IIC2_SDA_C, 5247 FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_I2C2_SDA_C, 5248 FN_TCLK1, 0, 0, 0, 0, 0, 0, 0, 0, 5249 /* IP0_22_20 [3] */ 5250 FN_D6, FN_IIC2_SCL_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B, 5251 FN_I2C2_SCL_C, 0, 0, 5252 /* IP0_19_16 [4] */ 5253 FN_D5, FN_SCIFB1_TXD_F, FN_SCIFB0_TXD_C, FN_VI3_DATA5, 5254 FN_VI0_R1, FN_VI0_R1_B, FN_TX0_B, 5255 0, 0, 0, 0, 0, 0, 0, 0, 0, 5256 /* IP0_15_12 [4] */ 5257 FN_D4, FN_SCIFB1_RXD_F, FN_SCIFB0_RXD_C, FN_VI3_DATA4, 5258 FN_VI0_R0, FN_VI0_R0_B, FN_RX0_B, 5259 0, 0, 0, 0, 0, 0, 0, 0, 0, 5260 /* IP0_11_9 [3] */ 5261 FN_D3, FN_MSIOF3_TXD_B, FN_VI3_DATA3, FN_VI0_G7, FN_VI0_G7_B, 5262 0, 0, 0, 5263 /* IP0_8_6 [3] */ 5264 FN_D2, FN_MSIOF3_RXD_B, FN_VI3_DATA2, FN_VI0_G6, FN_VI0_G6_B, 5265 0, 0, 0, 5266 /* IP0_5_3 [3] */ 5267 FN_D1, FN_MSIOF3_SYNC_B, FN_VI3_DATA1, FN_VI0_G5, FN_VI0_G5_B, 5268 0, 0, 0, 5269 /* IP0_2_0 [3] */ 5270 FN_D0, FN_MSIOF3_SCK_B, FN_VI3_DATA0, FN_VI0_G4, FN_VI0_G4_B, 5271 0, 0, 0, )) 5272 }, 5273 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32, 5274 GROUP(2, 2, 2, 4, 4, 3, 3, 4, 4, 4), 5275 GROUP( 5276 /* IP1_31_30 [2] */ 5277 0, 0, 0, 0, 5278 /* IP1_29_28 [2] */ 5279 FN_A1, FN_PWM4, 0, 0, 5280 /* IP1_27_26 [2] */ 5281 FN_A0, FN_PWM3, 0, 0, 5282 /* IP1_25_22 [4] */ 5283 FN_D15, FN_SCIFB1_TXD_C, FN_AVB_TXD7, FN_TX1_B, 5284 FN_VI0_FIELD, FN_VI0_FIELD_B, FN_VI2_DATA7_VI2_B7, 5285 0, 0, 0, 0, 0, 0, 0, 0, 0, 5286 /* IP1_21_18 [4] */ 5287 FN_D14, FN_SCIFB1_RXD_C, FN_AVB_TXD6, FN_RX1_B, 5288 FN_VI0_CLKENB, FN_VI0_CLKENB_B, FN_VI2_DATA6_VI2_B6, 5289 0, 0, 0, 0, 0, 0, 0, 0, 0, 5290 /* IP1_17_15 [3] */ 5291 FN_D13, FN_AVB_TXD5, FN_VI0_VSYNC_N, 5292 FN_VI0_VSYNC_N_B, FN_VI2_DATA5_VI2_B5, 5293 0, 0, 0, 5294 /* IP1_14_12 [3] */ 5295 FN_D12, FN_SCIFA1_RTS_N_C, FN_AVB_TXD4, 5296 FN_VI0_HSYNC_N, FN_VI0_HSYNC_N_B, FN_VI2_DATA4_VI2_B4, 5297 0, 0, 5298 /* IP1_11_8 [4] */ 5299 FN_D11, FN_SCIFA1_CTS_N_C, FN_AVB_TXD3, 0, 5300 FN_VI0_G3, FN_VI0_G3_B, FN_VI2_DATA3_VI2_B3, 5301 0, 0, 0, 0, 0, 0, 0, 0, 0, 5302 /* IP1_7_4 [4] */ 5303 FN_D10, FN_SCIFA1_TXD_C, FN_AVB_TXD2, 0, 5304 FN_VI0_G2, FN_VI0_G2_B, FN_VI2_DATA2_VI2_B2, 5305 0, 0, 0, 0, 0, 0, 0, 0, 0, 5306 /* IP1_3_0 [4] */ 5307 FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1, 0, 5308 FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1, 5309 0, 0, 0, 0, 0, 0, 0, 0, 0, )) 5310 }, 5311 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32, 5312 GROUP(3, 3, 4, 4, 3, 3, 3, 3, 3, 3), 5313 GROUP( 5314 /* IP2_31_29 [3] */ 5315 0, 0, 0, 0, 0, 0, 0, 0, 5316 /* IP2_28_26 [3] */ 5317 FN_A10, FN_SSI_SDATA5_B, FN_MSIOF2_SYNC, FN_VI0_R6, 5318 FN_VI0_R6_B, FN_VI2_DATA2_VI2_B2_B, 0, 0, 5319 /* IP2_25_22 [4] */ 5320 FN_A9, FN_SCIFA1_CTS_N_B, FN_SSI_WS5_B, FN_VI0_R5, 5321 FN_VI0_R5_B, FN_SCIFB2_TXD_C, FN_TX2_B, FN_VI2_DATA1_VI2_B1_B, 5322 0, 0, 0, 0, 0, 0, 0, 0, 5323 /* IP2_21_18 [4] */ 5324 FN_A8, FN_SCIFA1_RXD_B, FN_SSI_SCK5_B, FN_VI0_R4, 5325 FN_VI0_R4_B, FN_SCIFB2_RXD_C, FN_RX2_B, FN_VI2_DATA0_VI2_B0_B, 5326 0, 0, 0, 0, 0, 0, 0, 0, 5327 /* IP2_17_15 [3] */ 5328 FN_A7, FN_SCIFA1_SCK_B, FN_AUDIO_CLKOUT_B, FN_TPU0TO3, 5329 0, 0, 0, 0, 5330 /* IP2_14_12 [3] */ 5331 FN_A6, FN_SCIFA1_RTS_N_B, FN_TPU0TO2, 0, 0, 0, 0, 0, 5332 /* IP2_11_9 [3] */ 5333 FN_A5, FN_SCIFA1_TXD_B, FN_TPU0TO1, 0, 0, 0, 0, 0, 5334 /* IP2_8_6 [3] */ 5335 FN_A4, FN_MSIOF1_TXD_B, FN_TPU0TO0, 0, 0, 0, 0, 0, 5336 /* IP2_5_3 [3] */ 5337 FN_A3, FN_PWM6, FN_MSIOF1_SS2_B, 0, 0, 0, 0, 0, 5338 /* IP2_2_0 [3] */ 5339 FN_A2, FN_PWM5, FN_MSIOF1_SS1_B, 0, 0, 0, 0, 0, )) 5340 }, 5341 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32, 5342 GROUP(3, 3, 3, 3, 2, 3, 3, 4, 4, 4), 5343 GROUP( 5344 /* IP3_31_29 [3] */ 5345 FN_A20, FN_SPCLK, FN_VI1_R3, FN_VI1_R3_B, FN_VI2_G4, 5346 0, 0, 0, 5347 /* IP3_28_26 [3] */ 5348 FN_A19, FN_AD_NCS_N_B, FN_ATACS01_N, FN_EX_WAIT0_B, 5349 0, 0, 0, 0, 5350 /* IP3_25_23 [3] */ 5351 FN_A18, FN_AD_CLK_B, FN_ATAG1_N, 0, 0, 0, 0, 0, 5352 /* IP3_22_20 [3] */ 5353 FN_A17, FN_AD_DO_B, FN_ATADIR1_N, 0, 0, 0, 0, 0, 5354 /* IP3_19_18 [2] */ 5355 FN_A16, FN_ATAWR1_N, 0, 0, 5356 /* IP3_17_15 [3] */ 5357 FN_A15, FN_SCIFB2_SCK_B, FN_ATARD1_N, FN_MSIOF2_SS2, 5358 0, 0, 0, 0, 5359 /* IP3_14_12 [3] */ 5360 FN_A14, FN_SCIFB2_TXD_B, FN_ATACS11_N, FN_MSIOF2_SS1, 5361 0, 0, 0, 0, 5362 /* IP3_11_8 [4] */ 5363 FN_A13, FN_SCIFB2_RTS_N_B, FN_EX_WAIT2, 5364 FN_MSIOF2_RXD, FN_VI1_R2, FN_VI1_R2_B, FN_VI2_G2, 5365 FN_VI2_DATA5_VI2_B5_B, 0, 0, 0, 0, 0, 0, 0, 0, 5366 /* IP3_7_4 [4] */ 5367 FN_A12, FN_SCIFB2_RXD_B, FN_MSIOF2_TXD, FN_VI1_R1, 5368 FN_VI1_R1_B, FN_VI2_G1, FN_VI2_DATA4_VI2_B4_B, 5369 0, 0, 0, 0, 0, 0, 0, 0, 0, 5370 /* IP3_3_0 [4] */ 5371 FN_A11, FN_SCIFB2_CTS_N_B, FN_MSIOF2_SCK, FN_VI1_R0, 5372 FN_VI1_R0_B, FN_VI2_G0, FN_VI2_DATA3_VI2_B3_B, 0, 5373 0, 0, 0, 0, 0, 0, 0, 0, )) 5374 }, 5375 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32, 5376 GROUP(2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3), 5377 GROUP( 5378 /* IP4_31_30 [2] */ 5379 0, 0, 0, 0, 5380 /* IP4_29_27 [3] */ 5381 FN_EX_CS2_N, FN_GPS_SIGN, FN_HRTS1_N_B, 5382 FN_VI3_CLKENB, FN_VI1_G0, FN_VI1_G0_B, FN_VI2_R2, 0, 5383 /* IP4_26_24 [3] */ 5384 FN_EX_CS1_N, FN_GPS_CLK, FN_HCTS1_N_B, FN_VI1_FIELD, 5385 FN_VI1_FIELD_B, FN_VI2_R1, 0, 0, 5386 /* IP4_23_21 [3] */ 5387 FN_EX_CS0_N, FN_HRX1_B, FN_VI1_G5, FN_VI1_G5_B, FN_VI2_R0, 5388 FN_HTX0_B, FN_MSIOF0_SS1_B, 0, 5389 /* IP4_20_18 [3] */ 5390 FN_CS1_N_A26, FN_SPEEDIN, FN_VI0_R7, FN_VI0_R7_B, 5391 FN_VI2_CLK, FN_VI2_CLK_B, 0, 0, 5392 /* IP4_17_15 [3] */ 5393 FN_CS0_N, FN_VI1_R6, FN_VI1_R6_B, FN_VI2_G3, FN_MSIOF0_SS2_B, 5394 0, 0, 0, 5395 /* IP4_14_12 [3] */ 5396 FN_A25, FN_SSL, FN_VI1_G6, FN_VI1_G6_B, FN_VI2_FIELD, 5397 FN_VI2_FIELD_B, 0, 0, 5398 /* IP4_11_9 [3] */ 5399 FN_A24, FN_IO3, FN_VI1_R7, FN_VI1_R7_B, FN_VI2_CLKENB, 5400 FN_VI2_CLKENB_B, 0, 0, 5401 /* IP4_8_6 [3] */ 5402 FN_A23, FN_IO2, FN_VI1_G7, FN_VI1_G7_B, FN_VI2_G7, 0, 0, 0, 5403 /* IP4_5_3 [3] */ 5404 FN_A22, FN_MISO_IO1, FN_VI1_R5, FN_VI1_R5_B, FN_VI2_G6, 0, 0, 0, 5405 /* IP4_2_0 [3] */ 5406 FN_A21, FN_MOSI_IO0, FN_VI1_R4, FN_VI1_R4_B, FN_VI2_G5, 0, 0, 0, 5407 )) 5408 }, 5409 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32, 5410 GROUP(2, 3, 3, 3, 3, 3, 2, 3, 4, 3, 3), 5411 GROUP( 5412 /* IP5_31_30 [2] */ 5413 0, 0, 0, 0, 5414 /* IP5_29_27 [3] */ 5415 FN_DREQ0_N, FN_VI1_HSYNC_N, FN_VI1_HSYNC_N_B, FN_VI2_R7, 5416 FN_SSI_SCK78_C, FN_SSI_WS78_B, 0, 0, 5417 /* IP5_26_24 [3] */ 5418 FN_EX_WAIT0, FN_IRQ3, FN_INTC_IRQ3_N, 5419 FN_VI3_CLK, FN_SCIFA0_RTS_N_B, FN_HRX0_B, 5420 FN_MSIOF0_SCK_B, 0, 5421 /* IP5_23_21 [3] */ 5422 FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4, 5423 FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B, FN_IERX_C, 5424 /* IP5_20_18 [3] */ 5425 FN_WE0_N, FN_IECLK, FN_CAN_CLK, 5426 FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B, 0, 0, 5427 /* IP5_17_15 [3] */ 5428 FN_RD_WR_N, FN_VI1_G3, FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B, 5429 FN_INTC_IRQ4_N, 0, 0, 5430 /* IP5_14_13 [2] */ 5431 FN_RD_N, FN_CAN0_TX, FN_SCIFA0_SCK_B, 0, 5432 /* IP5_12_10 [3] */ 5433 FN_BS_N, FN_IETX, FN_HTX1_B, FN_CAN1_TX, FN_DRACK0, FN_IETX_C, 5434 0, 0, 5435 /* IP5_9_6 [4] */ 5436 FN_EX_CS5_N, FN_CAN0_RX, FN_MSIOF1_RXD_B, FN_VI3_VSYNC_N, 5437 FN_VI1_G2, FN_VI1_G2_B, FN_VI2_R4, FN_IIC1_SDA, FN_INTC_EN1_N, 5438 FN_I2C1_SDA, 0, 0, 0, 0, 0, 0, 5439 /* IP5_5_3 [3] */ 5440 FN_EX_CS4_N, FN_MSIOF1_SCK_B, FN_VI3_HSYNC_N, 5441 FN_VI2_HSYNC_N, FN_IIC1_SCL, FN_VI2_HSYNC_N_B, 5442 FN_INTC_EN0_N, FN_I2C1_SCL, 5443 /* IP5_2_0 [3] */ 5444 FN_EX_CS3_N, FN_GPS_MAG, FN_VI3_FIELD, FN_VI1_G1, FN_VI1_G1_B, 5445 FN_VI2_R3, 0, 0, )) 5446 }, 5447 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32, 5448 GROUP(3, 3, 3, 3, 3, 3, 3, 2, 3, 3, 3), 5449 GROUP( 5450 /* IP6_31_29 [3] */ 5451 FN_ETH_REF_CLK, 0, FN_HCTS0_N_E, 5452 FN_STP_IVCXO27_1_B, FN_HRX0_F, 0, 0, 0, 5453 /* IP6_28_26 [3] */ 5454 FN_ETH_LINK, 0, FN_HTX0_E, 5455 FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E, 0, 0, 5456 /* IP6_25_23 [3] */ 5457 FN_ETH_RXD1, 0, FN_HRX0_E, FN_STP_ISSYNC_0_B, 5458 FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G, FN_RX1_E, 5459 /* IP6_22_20 [3] */ 5460 FN_ETH_RXD0, 0, FN_STP_ISEN_0_B, FN_TS_SDAT0_D, 5461 FN_GLO_I0_C, FN_SCIFB1_SCK_G, FN_SCK1_E, 0, 5462 /* IP6_19_17 [3] */ 5463 FN_ETH_RX_ER, 0, FN_STP_ISD_0_B, 5464 FN_TS_SPSYNC0_D, FN_GLO_Q1_C, FN_IIC2_SDA_E, FN_I2C2_SDA_E, 0, 5465 /* IP6_16_14 [3] */ 5466 FN_ETH_CRS_DV, 0, FN_STP_ISCLK_0_B, 5467 FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_IIC2_SCL_E, 5468 FN_I2C2_SCL_E, 0, 5469 /* IP6_13_11 [3] */ 5470 FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N, 5471 FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B, 0, 0, 5472 /* IP6_10_9 [2] */ 5473 FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B, FN_MSIOF0_TXD_B, 5474 /* IP6_8_6 [3] */ 5475 FN_DACK1, FN_IRQ1, FN_INTC_IRQ1_N, FN_SSI_WS6_B, 5476 FN_SSI_SDATA8_C, 0, 0, 0, 5477 /* IP6_5_3 [3] */ 5478 FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B, 5479 FN_SSI_SDATA7_C, FN_SSI_SCK78_B, 0, 0, 0, 5480 /* IP6_2_0 [3] */ 5481 FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B, 5482 FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, 0, )) 5483 }, 5484 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32, 5485 GROUP(1, 2, 2, 2, 3, 3, 3, 3, 3, 2, 2, 3, 3), 5486 GROUP( 5487 /* IP7_31 [1] */ 5488 0, 0, 5489 /* IP7_30_29 [2] */ 5490 FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2, 0, 5491 /* IP7_28_27 [2] */ 5492 FN_VI0_CLK, FN_ATACS00_N, FN_AVB_RXD1, 0, 5493 /* IP7_26_25 [2] */ 5494 FN_DU_DOTCLKIN1, FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, 0, 5495 /* IP7_24_22 [3] */ 5496 FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C, FN_PCMWE_N, FN_IECLK_C, 5497 0, 0, 0, 5498 /* IP7_21_19 [3] */ 5499 FN_PWM1, FN_SCIFA2_TXD_C, FN_STP_ISSYNC_1_B, FN_TS_SCK1_C, 5500 FN_GLO_RFON_C, FN_PCMOE_N, 0, 0, 5501 /* IP7_18_16 [3] */ 5502 FN_PWM0, FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C, 5503 FN_GLO_SS_C, 0, 0, 0, 5504 /* IP7_15_13 [3] */ 5505 FN_ETH_MDC, 0, FN_STP_ISD_1_B, 5506 FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, 0, 0, 0, 5507 /* IP7_12_10 [3] */ 5508 FN_ETH_TXD0, 0, FN_STP_ISCLK_1_B, FN_TS_SDEN1_C, 5509 FN_GLO_SCLK_C, 0, 0, 0, 5510 /* IP7_9_8 [2] */ 5511 FN_ETH_MAGIC, 0, FN_SIM0_RST_C, 0, 5512 /* IP7_7_6 [2] */ 5513 FN_ETH_TX_EN, 0, FN_SIM0_CLK_C, FN_HRTS0_N_F, 5514 /* IP7_5_3 [3] */ 5515 FN_ETH_TXD1, 0, FN_HTX0_F, FN_BPFCLK_G, 0, 0, 0, 0, 5516 /* IP7_2_0 [3] */ 5517 FN_ETH_MDIO, 0, FN_HRTS0_N_E, 5518 FN_SIM0_D_C, FN_HCTS0_N_F, 0, 0, 0, )) 5519 }, 5520 { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32, 5521 GROUP(1, 2, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 5522 2, 2, 2, 2, 2, 2), 5523 GROUP( 5524 /* IP8_31 [1] */ 5525 0, 0, 5526 /* IP8_30_29 [2] */ 5527 FN_SD0_CMD, FN_SCIFB1_SCK_B, FN_VI1_DATA1_VI1_B1_B, 0, 5528 /* IP8_28 [1] */ 5529 FN_SD0_CLK, FN_VI1_DATA0_VI1_B0_B, 5530 /* IP8_27 [1] */ 5531 FN_VI1_DATA6_VI1_B6, FN_AVB_GTXREFCLK, 5532 /* IP8_26 [1] */ 5533 FN_VI1_DATA5_VI1_B5, FN_AVB_PHY_INT, 5534 /* IP8_25_24 [2] */ 5535 FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D, 5536 FN_AVB_MAGIC, 0, 5537 /* IP8_23_22 [2] */ 5538 FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D, FN_AVB_GTX_CLK, 0, 5539 /* IP8_21_20 [2] */ 5540 FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO, 0, 5541 /* IP8_19_18 [2] */ 5542 FN_VI1_DATA1_VI1_B1, FN_SCIFA1_RXD_D, FN_AVB_MDC, 0, 5543 /* IP8_17_16 [2] */ 5544 FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D, FN_AVB_CRS, 0, 5545 /* IP8_15_14 [2] */ 5546 FN_VI1_CLK, FN_AVB_RX_DV, 0, 0, 5547 /* IP8_13_12 [2] */ 5548 FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK, 0, 0, 5549 /* IP8_11_10 [2] */ 5550 FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER, 0, 0, 5551 /* IP8_9_8 [2] */ 5552 FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1, FN_AVB_RXD7, 0, 5553 /* IP8_7_6 [2] */ 5554 FN_VI0_DATA4_VI0_B4, FN_ATAG0_N, FN_AVB_RXD6, 0, 5555 /* IP8_5_4 [2] */ 5556 FN_VI0_DATA3_VI0_B3, FN_ATADIR0_N, FN_AVB_RXD5, 0, 5557 /* IP8_3_2 [2] */ 5558 FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N, FN_AVB_RXD4, 0, 5559 /* IP8_1_0 [2] */ 5560 FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3, 0, )) 5561 }, 5562 { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32, 5563 GROUP(4, 2, 2, 2, 2, 2, 2, 4, 4, 2, 2, 2, 2), 5564 GROUP( 5565 /* IP9_31_28 [4] */ 5566 FN_SD1_CD, FN_MMC1_D6, FN_TS_SDEN1, FN_USB1_EXTP, 5567 FN_GLO_SS, FN_VI0_CLK_B, FN_IIC2_SCL_D, FN_I2C2_SCL_D, 5568 FN_SIM0_CLK_B, FN_VI3_CLK_B, 0, 0, 0, 0, 0, 0, 5569 /* IP9_27_26 [2] */ 5570 FN_SD1_DAT3, FN_AVB_RXD0, 0, FN_SCIFB0_RTS_N_B, 5571 /* IP9_25_24 [2] */ 5572 FN_SD1_DAT2, FN_AVB_COL, 0, FN_SCIFB0_CTS_N_B, 5573 /* IP9_23_22 [2] */ 5574 FN_SD1_DAT1, FN_AVB_LINK, 0, FN_SCIFB0_TXD_B, 5575 /* IP9_21_20 [2] */ 5576 FN_SD1_DAT0, FN_AVB_TX_CLK, 0, FN_SCIFB0_RXD_B, 5577 /* IP9_19_18 [2] */ 5578 FN_SD1_CMD, FN_AVB_TX_ER, 0, FN_SCIFB0_SCK_B, 5579 /* IP9_17_16 [2] */ 5580 FN_SD1_CLK, FN_AVB_TX_EN, 0, 0, 5581 /* IP9_15_12 [4] */ 5582 FN_SD0_WP, FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN, 5583 FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_IIC1_SDA_B, 5584 FN_I2C1_SDA_B, FN_VI2_DATA7_VI2_B7_B, 0, 0, 0, 0, 0, 0, 0, 5585 /* IP9_11_8 [4] */ 5586 FN_SD0_CD, FN_MMC0_D6, FN_TS_SDEN0_B, FN_USB0_EXTP, 5587 FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_IIC1_SCL_B, 5588 FN_I2C1_SCL_B, FN_VI2_DATA6_VI2_B6_B, 0, 0, 0, 0, 0, 0, 0, 5589 /* IP9_7_6 [2] */ 5590 FN_SD0_DAT3, FN_SCIFB1_RTS_N_B, FN_VI1_DATA5_VI1_B5_B, 0, 5591 /* IP9_5_4 [2] */ 5592 FN_SD0_DAT2, FN_SCIFB1_CTS_N_B, FN_VI1_DATA4_VI1_B4_B, 0, 5593 /* IP9_3_2 [2] */ 5594 FN_SD0_DAT1, FN_SCIFB1_TXD_B, FN_VI1_DATA3_VI1_B3_B, 0, 5595 /* IP9_1_0 [2] */ 5596 FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B, 0, )) 5597 }, 5598 { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32, 5599 GROUP(2, 4, 3, 4, 4, 4, 4, 3, 4), 5600 GROUP( 5601 /* IP10_31_30 [2] */ 5602 0, 0, 0, 0, 5603 /* IP10_29_26 [4] */ 5604 FN_SD2_CD, FN_MMC0_D4, FN_TS_SDAT0_B, FN_USB2_EXTP, FN_GLO_I0, 5605 FN_VI0_DATA6_VI0_B6_B, FN_HCTS0_N_D, FN_TS_SDAT1_B, 5606 FN_GLO_I0_B, FN_VI3_DATA6_B, 0, 0, 0, 0, 0, 0, 5607 /* IP10_25_23 [3] */ 5608 FN_SD2_DAT3, FN_MMC0_D3, FN_SIM0_RST, FN_VI0_DATA5_VI0_B5_B, 5609 FN_HTX0_D, FN_TS_SPSYNC1_B, FN_GLO_Q1_B, FN_VI3_DATA5_B, 5610 /* IP10_22_19 [4] */ 5611 FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B, 0, 5612 FN_VI0_DATA4_VI0_B4_B, FN_HRX0_D, FN_TS_SDEN1_B, 5613 FN_GLO_Q0_B, FN_VI3_DATA4_B, 0, 0, 0, 0, 0, 0, 0, 5614 /* IP10_18_15 [4] */ 5615 FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B, 0, 5616 FN_VI0_DATA3_VI0_B3_B, FN_SCIFB1_TXD_E, FN_TX1_D, 5617 FN_TS_SCK0_C, FN_GLO_RFON_B, FN_VI3_DATA3_B, 5618 0, 0, 0, 0, 0, 0, 5619 /* IP10_14_11 [4] */ 5620 FN_SD2_DAT0, FN_MMC0_D0, FN_FMCLK_B, 5621 FN_VI0_DATA2_VI0_B2_B, FN_SCIFB1_RXD_E, FN_RX1_D, 5622 FN_TS_SDAT0_C, FN_GLO_SS_B, FN_VI3_DATA2_B, 5623 0, 0, 0, 0, 0, 0, 0, 5624 /* IP10_10_7 [4] */ 5625 FN_SD2_CMD, FN_MMC0_CMD, FN_SIM0_D, 5626 FN_VI0_DATA1_VI0_B1_B, FN_SCIFB1_SCK_E, FN_SCK1_D, 5627 FN_TS_SPSYNC0_C, FN_GLO_SDATA_B, FN_VI3_DATA1_B, 5628 0, 0, 0, 0, 0, 0, 0, 5629 /* IP10_6_4 [3] */ 5630 FN_SD2_CLK, FN_MMC0_CLK, FN_SIM0_CLK, 5631 FN_VI0_DATA0_VI0_B0_B, FN_TS_SDEN0_C, FN_GLO_SCLK_B, 5632 FN_VI3_DATA0_B, 0, 5633 /* IP10_3_0 [4] */ 5634 FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN, 5635 FN_GLO_RFON, FN_VI1_CLK_B, FN_IIC2_SDA_D, FN_I2C2_SDA_D, 5636 FN_SIM0_D_B, 0, 0, 0, 0, 0, 0, 0, )) 5637 }, 5638 { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32, 5639 GROUP(2, 3, 3, 2, 4, 3, 2, 2, 2, 2, 2, 1, 4), 5640 GROUP( 5641 /* IP11_31_30 [2] */ 5642 FN_SSI_SCK0129, FN_CAN_CLK_B, FN_MOUT0, 0, 5643 /* IP11_29_27 [3] */ 5644 FN_MLB_DAT, 0, FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C, 5645 0, 0, 0, 5646 /* IP11_26_24 [3] */ 5647 FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_IIC2_SDA_B, FN_I2C2_SDA_B, 5648 0, 0, 0, 5649 /* IP11_23_22 [2] */ 5650 FN_MLB_CLK, FN_IIC2_SCL_B, FN_I2C2_SCL_B, 0, 5651 /* IP11_21_18 [4] */ 5652 FN_SD3_WP, FN_MMC1_D5, FN_TS_SCK1, FN_GLO_Q1, FN_FMIN_C, 5653 0, FN_FMIN_E, 0, FN_FMIN_F, 0, 0, 0, 0, 0, 0, 0, 5654 /* IP11_17_15 [3] */ 5655 FN_SD3_CD, FN_MMC1_D4, FN_TS_SDAT1, 5656 FN_VSP, FN_GLO_Q0, FN_SIM0_RST_B, 0, 0, 5657 /* IP11_14_13 [2] */ 5658 FN_SD3_DAT3, FN_MMC1_D3, FN_SCKZ, 0, 5659 /* IP11_12_11 [2] */ 5660 FN_SD3_DAT2, FN_MMC1_D2, FN_SDATA, 0, 5661 /* IP11_10_9 [2] */ 5662 FN_SD3_DAT1, FN_MMC1_D1, FN_MDATA, 0, 5663 /* IP11_8_7 [2] */ 5664 FN_SD3_DAT0, FN_MMC1_D0, FN_STM_N, 0, 5665 /* IP11_6_5 [2] */ 5666 FN_SD3_CMD, FN_MMC1_CMD, FN_MTS_N, 0, 5667 /* IP11_4 [1] */ 5668 FN_SD3_CLK, FN_MMC1_CLK, 5669 /* IP11_3_0 [4] */ 5670 FN_SD2_WP, FN_MMC0_D5, FN_TS_SCK0_B, FN_USB2_IDIN, 5671 FN_GLO_I1, FN_VI0_DATA7_VI0_B7_B, FN_HRTS0_N_D, 5672 FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B, 0, 0, 0, 0, 0, 0, )) 5673 }, 5674 { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32, 5675 GROUP(1, 3, 3, 2, 3, 3, 3, 3, 3, 2, 2, 2, 2), 5676 GROUP( 5677 /* IP12_31 [1] */ 5678 0, 0, 5679 /* IP12_30_28 [3] */ 5680 FN_SSI_WS5, FN_SCIFB1_RXD, FN_IECLK_B, 5681 FN_DU2_EXVSYNC_DU2_VSYNC, FN_QSTB_QHE, 5682 FN_CAN_DEBUGOUT4, 0, 0, 5683 /* IP12_27_25 [3] */ 5684 FN_SSI_SCK5, FN_SCIFB1_SCK, 5685 FN_IERX_B, FN_DU2_EXHSYNC_DU2_HSYNC, FN_QSTH_QHS, 5686 FN_CAN_DEBUGOUT3, 0, 0, 5687 /* IP12_24_23 [2] */ 5688 FN_SSI_SDATA4, FN_STP_ISSYNC_0, FN_MSIOF1_RXD, 5689 FN_CAN_DEBUGOUT2, 5690 /* IP12_22_20 [3] */ 5691 FN_SSI_WS4, FN_STP_ISEN_0, FN_SCIFB0_RTS_N, 5692 FN_MSIOF1_TXD, FN_SSI_WS5_C, FN_CAN_DEBUGOUT1, 0, 0, 5693 /* IP12_19_17 [3] */ 5694 FN_SSI_SCK4, FN_STP_ISD_0, FN_SCIFB0_CTS_N, 5695 FN_MSIOF1_SS2, FN_SSI_SCK5_C, FN_CAN_DEBUGOUT0, 0, 0, 5696 /* IP12_16_14 [3] */ 5697 FN_SSI_SDATA3, FN_STP_ISCLK_0, 5698 FN_SCIFB0_TXD, FN_MSIOF1_SS1, FN_CAN_TXCLK, 0, 0, 0, 5699 /* IP12_13_11 [3] */ 5700 FN_SSI_WS34, FN_STP_IVCXO27_0, FN_SCIFB0_RXD, FN_MSIOF1_SYNC, 5701 FN_CAN_STEP0, 0, 0, 0, 5702 /* IP12_10_8 [3] */ 5703 FN_SSI_SCK34, FN_STP_OPWM_0, FN_SCIFB0_SCK, 5704 FN_MSIOF1_SCK, FN_CAN_DEBUG_HW_TRIGGER, 0, 0, 0, 5705 /* IP12_7_6 [2] */ 5706 FN_SSI_SDATA2, FN_CAN1_RX_B, FN_SSI_SCK1, FN_MOUT6, 5707 /* IP12_5_4 [2] */ 5708 FN_SSI_SDATA1, FN_CAN1_TX_B, FN_MOUT5, 0, 5709 /* IP12_3_2 [2] */ 5710 FN_SSI_SDATA0, FN_CAN0_RX_B, FN_MOUT2, 0, 5711 /* IP12_1_0 [2] */ 5712 FN_SSI_WS0129, FN_CAN0_TX_B, FN_MOUT1, 0, )) 5713 }, 5714 { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32, 5715 GROUP(1, 2, 3, 3, 4, 3, 3, 3, 3, 4, 3), 5716 GROUP( 5717 /* IP13_31 [1] */ 5718 0, 0, 5719 /* IP13_30_29 [2] */ 5720 FN_AUDIO_CLKA, FN_SCIFB2_RTS_N, FN_CAN_DEBUGOUT14, 0, 5721 /* IP13_28_26 [3] */ 5722 FN_SSI_SDATA9, FN_STP_ISSYNC_1, FN_SCIFB2_CTS_N, FN_SSI_WS1, 5723 FN_SSI_SDATA5_C, FN_CAN_DEBUGOUT13, 0, 0, 5724 /* IP13_25_23 [3] */ 5725 FN_SSI_SDATA8, FN_STP_ISEN_1, FN_SCIFB2_TXD, FN_CAN0_TX_C, 5726 FN_CAN_DEBUGOUT12, FN_SSI_SDATA8_B, 0, 0, 5727 /* IP13_22_19 [4] */ 5728 FN_SSI_SDATA7, FN_STP_ISD_1, FN_SCIFB2_RXD, FN_SCIFA2_RTS_N, 5729 FN_TCLK2, FN_QSTVA_QVS, FN_CAN_DEBUGOUT11, FN_BPFCLK_E, 5730 0, FN_SSI_SDATA7_B, FN_FMIN_G, 0, 0, 0, 0, 0, 5731 /* IP13_18_16 [3] */ 5732 FN_SSI_WS78, FN_STP_ISCLK_1, FN_SCIFB2_SCK, FN_SCIFA2_CTS_N, 5733 FN_DU2_DR7, FN_LCDOUT7, FN_CAN_DEBUGOUT10, 0, 5734 /* IP13_15_13 [3] */ 5735 FN_SSI_SCK78, FN_STP_IVCXO27_1, FN_SCK1, FN_SCIFA1_SCK, 5736 FN_DU2_DR6, FN_LCDOUT6, FN_CAN_DEBUGOUT9, 0, 5737 /* IP13_12_10 [3] */ 5738 FN_SSI_SDATA6, FN_FMIN_D, 0, FN_DU2_DR5, FN_LCDOUT5, 5739 FN_CAN_DEBUGOUT8, 0, 0, 5740 /* IP13_9_7 [3] */ 5741 FN_SSI_WS6, FN_SCIFB1_RTS_N, FN_CAN0_TX_D, FN_DU2_DR4, 5742 FN_LCDOUT4, FN_CAN_DEBUGOUT7, 0, 0, 5743 /* IP13_6_3 [4] */ 5744 FN_SSI_SCK6, FN_SCIFB1_CTS_N, FN_BPFCLK_D, 0, 5745 FN_DU2_DR3, FN_LCDOUT3, FN_CAN_DEBUGOUT6, 5746 FN_BPFCLK_F, 0, 0, 0, 0, 0, 0, 0, 0, 5747 /* IP13_2_0 [3] */ 5748 FN_SSI_SDATA5, FN_SCIFB1_TXD, FN_IETX_B, FN_DU2_DR2, 5749 FN_LCDOUT2, FN_CAN_DEBUGOUT5, 0, 0, )) 5750 }, 5751 { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32, 5752 GROUP(1, 3, 3, 3, 3, 3, 4, 3, 3, 3, 3), 5753 GROUP( 5754 /* IP14_30 [1] */ 5755 0, 0, 5756 /* IP14_30_28 [3] */ 5757 FN_SCIFA1_RTS_N, FN_AD_NCS_N, FN_RTS1_N, 5758 FN_MSIOF3_TXD, FN_DU1_DOTCLKOUT, FN_QSTVB_QVE, 5759 FN_HRTS0_N_C, 0, 5760 /* IP14_27_25 [3] */ 5761 FN_SCIFA1_CTS_N, FN_AD_CLK, FN_CTS1_N, FN_MSIOF3_RXD, 5762 FN_DU0_DOTCLKOUT, FN_QCLK, 0, 0, 5763 /* IP14_24_22 [3] */ 5764 FN_SCIFA1_TXD, FN_AD_DO, FN_TX1, FN_DU2_DG1, 5765 FN_LCDOUT9, 0, 0, 0, 5766 /* IP14_21_19 [3] */ 5767 FN_SCIFA1_RXD, FN_AD_DI, FN_RX1, 5768 FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, FN_QCPV_QDE, 0, 0, 0, 5769 /* IP14_18_16 [3] */ 5770 FN_SCIFA0_RTS_N, FN_HRTS1_N, FN_RTS0_N, 5771 FN_MSIOF3_SS1, FN_DU2_DG0, FN_LCDOUT8, FN_PWM1_B, 0, 5772 /* IP14_15_12 [4] */ 5773 FN_SCIFA0_CTS_N, FN_HCTS1_N, FN_CTS0_N, FN_MSIOF3_SYNC, 5774 FN_DU2_DG3, FN_LCDOUT11, FN_PWM0_B, FN_IIC1_SCL_C, FN_I2C1_SCL_C, 5775 0, 0, 0, 0, 0, 0, 0, 5776 /* IP14_11_9 [3] */ 5777 FN_SCIFA0_TXD, FN_HTX1, FN_TX0, FN_DU2_DR1, FN_LCDOUT1, 5778 0, 0, 0, 5779 /* IP14_8_6 [3] */ 5780 FN_SCIFA0_RXD, FN_HRX1, FN_RX0, FN_DU2_DR0, FN_LCDOUT0, 5781 0, 0, 0, 5782 /* IP14_5_3 [3] */ 5783 FN_SCIFA0_SCK, FN_HSCK1, FN_SCK0, FN_MSIOF3_SS2, FN_DU2_DG2, 5784 FN_LCDOUT10, FN_IIC1_SDA_C, FN_I2C1_SDA_C, 5785 /* IP14_2_0 [3] */ 5786 FN_AUDIO_CLKB, FN_SCIF_CLK, FN_CAN0_RX_D, 5787 FN_DVC_MUTE, FN_CAN0_RX_C, FN_CAN_DEBUGOUT15, 5788 FN_REMOCON, 0, )) 5789 }, 5790 { PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32, 5791 GROUP(2, 2, 2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3), 5792 GROUP( 5793 /* IP15_31_30 [2] */ 5794 0, 0, 0, 0, 5795 /* IP15_29_28 [2] */ 5796 FN_MSIOF0_TXD, FN_ADICHS1, FN_DU2_DG6, FN_LCDOUT14, 5797 /* IP15_27_26 [2] */ 5798 FN_MSIOF0_SS1, FN_ADICHS0, FN_DU2_DG5, FN_LCDOUT13, 5799 /* IP15_25_23 [3] */ 5800 FN_MSIOF0_SYNC, FN_TS_SCK0, FN_SSI_SCK2, FN_ADIDATA, 5801 FN_DU2_DB7, FN_LCDOUT23, FN_HRX0_C, 0, 5802 /* IP15_22_20 [3] */ 5803 FN_MSIOF0_SCK, FN_TS_SDAT0, FN_ADICLK, 5804 FN_DU2_DB6, FN_LCDOUT22, 0, 0, 0, 5805 /* IP15_19_18 [2] */ 5806 FN_HRTS0_N, FN_SSI_WS9, FN_DU2_DB5, FN_LCDOUT21, 5807 /* IP15_17_16 [2] */ 5808 FN_HCTS0_N, FN_SSI_SCK9, FN_DU2_DB4, FN_LCDOUT20, 5809 /* IP15_15_14 [2] */ 5810 FN_HTX0, FN_DU2_DB3, FN_LCDOUT19, 0, 5811 /* IP15_13_12 [2] */ 5812 FN_HRX0, FN_DU2_DB2, FN_LCDOUT18, 0, 5813 /* IP15_11_9 [3] */ 5814 FN_HSCK0, FN_TS_SDEN0, FN_DU2_DG4, FN_LCDOUT12, FN_HCTS0_N_C, 5815 0, 0, 0, 5816 /* IP15_8_6 [3] */ 5817 FN_SCIFA2_TXD, FN_BPFCLK, FN_RX2, FN_DU2_DB1, FN_LCDOUT17, 5818 FN_IIC2_SDA, FN_I2C2_SDA, 0, 5819 /* IP15_5_3 [3] */ 5820 FN_SCIFA2_RXD, FN_FMIN, FN_TX2, FN_DU2_DB0, FN_LCDOUT16, 5821 FN_IIC2_SCL, FN_I2C2_SCL, 0, 5822 /* IP15_2_0 [3] */ 5823 FN_SCIFA2_SCK, FN_FMCLK, FN_SCK2, FN_MSIOF3_SCK, FN_DU2_DG7, 5824 FN_LCDOUT15, FN_SCIF_CLK_B, 0, )) 5825 }, 5826 { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32, 5827 GROUP(4, 4, 4, 4, 4, 4, 1, 1, 3, 3), 5828 GROUP( 5829 /* IP16_31_28 [4] */ 5830 0, 0, 0, 0, 0, 0, 0, 0, 5831 0, 0, 0, 0, 0, 0, 0, 0, 5832 /* IP16_27_24 [4] */ 5833 0, 0, 0, 0, 0, 0, 0, 0, 5834 0, 0, 0, 0, 0, 0, 0, 0, 5835 /* IP16_23_20 [4] */ 5836 0, 0, 0, 0, 0, 0, 0, 0, 5837 0, 0, 0, 0, 0, 0, 0, 0, 5838 /* IP16_19_16 [4] */ 5839 0, 0, 0, 0, 0, 0, 0, 0, 5840 0, 0, 0, 0, 0, 0, 0, 0, 5841 /* IP16_15_12 [4] */ 5842 0, 0, 0, 0, 0, 0, 0, 0, 5843 0, 0, 0, 0, 0, 0, 0, 0, 5844 /* IP16_11_8 [4] */ 5845 0, 0, 0, 0, 0, 0, 0, 0, 5846 0, 0, 0, 0, 0, 0, 0, 0, 5847 /* IP16_7 [1] */ 5848 FN_USB1_OVC, FN_TCLK1_B, 5849 /* IP16_6 [1] */ 5850 FN_USB1_PWEN, FN_AUDIO_CLKOUT_D, 5851 /* IP16_5_3 [3] */ 5852 FN_MSIOF0_RXD, FN_TS_SPSYNC0, FN_SSI_WS2, 5853 FN_ADICS_SAMP, FN_DU2_CDE, FN_QPOLB, FN_SCIFA2_RXD_B, 0, 5854 /* IP16_2_0 [3] */ 5855 FN_MSIOF0_SS2, FN_AUDIO_CLKOUT, FN_ADICHS2, 5856 FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B, 0, )) 5857 }, 5858 { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32, 5859 GROUP(3, 2, 2, 3, 2, 1, 1, 1, 2, 1, 2, 1, 5860 1, 1, 1, 2, 1, 1, 2, 1, 1), 5861 GROUP( 5862 /* SEL_SCIF1 [3] */ 5863 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3, 5864 FN_SEL_SCIF1_4, 0, 0, 0, 5865 /* SEL_SCIFB [2] */ 5866 FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, 0, 5867 /* SEL_SCIFB2 [2] */ 5868 FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, 0, 5869 /* SEL_SCIFB1 [3] */ 5870 FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, 5871 FN_SEL_SCIFB1_3, FN_SEL_SCIFB1_4, FN_SEL_SCIFB1_5, 5872 FN_SEL_SCIFB1_6, 0, 5873 /* SEL_SCIFA1 [2] */ 5874 FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, 5875 FN_SEL_SCIFA1_3, 5876 /* SEL_SCIF0 [1] */ 5877 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, 5878 /* SEL_SCIFA [1] */ 5879 FN_SEL_SCFA_0, FN_SEL_SCFA_1, 5880 /* SEL_SOF1 [1] */ 5881 FN_SEL_SOF1_0, FN_SEL_SOF1_1, 5882 /* SEL_SSI7 [2] */ 5883 FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2, 0, 5884 /* SEL_SSI6 [1] */ 5885 FN_SEL_SSI6_0, FN_SEL_SSI6_1, 5886 /* SEL_SSI5 [2] */ 5887 FN_SEL_SSI5_0, FN_SEL_SSI5_1, FN_SEL_SSI5_2, 0, 5888 /* SEL_VI3 [1] */ 5889 FN_SEL_VI3_0, FN_SEL_VI3_1, 5890 /* SEL_VI2 [1] */ 5891 FN_SEL_VI2_0, FN_SEL_VI2_1, 5892 /* SEL_VI1 [1] */ 5893 FN_SEL_VI1_0, FN_SEL_VI1_1, 5894 /* SEL_VI0 [1] */ 5895 FN_SEL_VI0_0, FN_SEL_VI0_1, 5896 /* SEL_TSIF1 [2] */ 5897 FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2, 0, 5898 /* RESERVED [1] */ 5899 0, 0, 5900 /* SEL_LBS [1] */ 5901 FN_SEL_LBS_0, FN_SEL_LBS_1, 5902 /* SEL_TSIF0 [2] */ 5903 FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, 5904 /* SEL_SOF3 [1] */ 5905 FN_SEL_SOF3_0, FN_SEL_SOF3_1, 5906 /* SEL_SOF0 [1] */ 5907 FN_SEL_SOF0_0, FN_SEL_SOF0_1, )) 5908 }, 5909 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32, 5910 GROUP(3, 1, 1, 1, 2, 1, 2, 1, 2, 1, 1, 1, 5911 3, 3, 2, 3, 2, 2), 5912 GROUP( 5913 /* RESERVED [3] */ 5914 0, 0, 0, 0, 0, 0, 0, 0, 5915 /* SEL_TMU1 [1] */ 5916 FN_SEL_TMU1_0, FN_SEL_TMU1_1, 5917 /* SEL_HSCIF1 [1] */ 5918 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, 5919 /* SEL_SCIFCLK [1] */ 5920 FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1, 5921 /* SEL_CAN0 [2] */ 5922 FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3, 5923 /* SEL_CANCLK [1] */ 5924 FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, 5925 /* SEL_SCIFA2 [2] */ 5926 FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2, 0, 5927 /* SEL_CAN1 [1] */ 5928 FN_SEL_CAN1_0, FN_SEL_CAN1_1, 5929 /* RESERVED [2] */ 5930 0, 0, 0, 0, 5931 /* SEL_SCIF2 [1] */ 5932 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, 5933 /* SEL_ADI [1] */ 5934 FN_SEL_ADI_0, FN_SEL_ADI_1, 5935 /* SEL_SSP [1] */ 5936 FN_SEL_SSP_0, FN_SEL_SSP_1, 5937 /* SEL_FM [3] */ 5938 FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3, 5939 FN_SEL_FM_4, FN_SEL_FM_5, FN_SEL_FM_6, 0, 5940 /* SEL_HSCIF0 [3] */ 5941 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, 5942 FN_SEL_HSCIF0_3, FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5, 0, 0, 5943 /* SEL_GPS [2] */ 5944 FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, 0, 5945 /* RESERVED [3] */ 5946 0, 0, 0, 0, 0, 0, 0, 0, 5947 /* SEL_SIM [2] */ 5948 FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2, 0, 5949 /* SEL_SSI8 [2] */ 5950 FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2, 0, )) 5951 }, 5952 { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32, 5953 GROUP(1, 1, 2, 4, 4, 2, 2, 4, 2, 3, 2, 3, 2), 5954 GROUP( 5955 /* SEL_IICDVFS [1] */ 5956 FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1, 5957 /* SEL_IIC0 [1] */ 5958 FN_SEL_IIC0_0, FN_SEL_IIC0_1, 5959 /* RESERVED [2] */ 5960 0, 0, 0, 0, 5961 /* RESERVED [4] */ 5962 0, 0, 0, 0, 0, 0, 0, 0, 5963 0, 0, 0, 0, 0, 0, 0, 0, 5964 /* RESERVED [4] */ 5965 0, 0, 0, 0, 0, 0, 0, 0, 5966 0, 0, 0, 0, 0, 0, 0, 0, 5967 /* RESERVED [2] */ 5968 0, 0, 0, 0, 5969 /* SEL_IEB [2] */ 5970 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0, 5971 /* RESERVED [4] */ 5972 0, 0, 0, 0, 0, 0, 0, 0, 5973 0, 0, 0, 0, 0, 0, 0, 0, 5974 /* RESERVED [2] */ 5975 0, 0, 0, 0, 5976 /* SEL_IIC2 [3] */ 5977 FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3, 5978 FN_SEL_IIC2_4, 0, 0, 0, 5979 /* SEL_IIC1 [2] */ 5980 FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, 0, 5981 /* SEL_I2C2 [3] */ 5982 FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3, 5983 FN_SEL_I2C2_4, 0, 0, 0, 5984 /* SEL_I2C1 [2] */ 5985 FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, 0, )) 5986 }, 5987 { }, 5988 }; 5989 5990 static int r8a7790_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl) 5991 { 5992 if (pin < RCAR_GP_PIN(3, 0) || pin > RCAR_GP_PIN(3, 31)) 5993 return -EINVAL; 5994 5995 *pocctrl = 0xe606008c; 5996 5997 return 31 - (pin & 0x1f); 5998 } 5999 6000 static const struct pinmux_bias_reg pinmux_bias_regs[] = { 6001 { PINMUX_BIAS_REG("PUPR0", 0xe6060100, "N/A", 0) { 6002 [ 0] = RCAR_GP_PIN(0, 16), /* A0 */ 6003 [ 1] = RCAR_GP_PIN(0, 17), /* A1 */ 6004 [ 2] = RCAR_GP_PIN(0, 18), /* A2 */ 6005 [ 3] = RCAR_GP_PIN(0, 19), /* A3 */ 6006 [ 4] = RCAR_GP_PIN(0, 20), /* A4 */ 6007 [ 5] = RCAR_GP_PIN(0, 21), /* A5 */ 6008 [ 6] = RCAR_GP_PIN(0, 22), /* A6 */ 6009 [ 7] = RCAR_GP_PIN(0, 23), /* A7 */ 6010 [ 8] = RCAR_GP_PIN(0, 24), /* A8 */ 6011 [ 9] = RCAR_GP_PIN(0, 25), /* A9 */ 6012 [10] = RCAR_GP_PIN(0, 26), /* A10 */ 6013 [11] = RCAR_GP_PIN(0, 27), /* A11 */ 6014 [12] = RCAR_GP_PIN(0, 28), /* A12 */ 6015 [13] = RCAR_GP_PIN(0, 29), /* A13 */ 6016 [14] = RCAR_GP_PIN(0, 30), /* A14 */ 6017 [15] = RCAR_GP_PIN(0, 31), /* A15 */ 6018 [16] = RCAR_GP_PIN(1, 0), /* A16 */ 6019 [17] = RCAR_GP_PIN(1, 1), /* A17 */ 6020 [18] = RCAR_GP_PIN(1, 2), /* A18 */ 6021 [19] = RCAR_GP_PIN(1, 3), /* A19 */ 6022 [20] = RCAR_GP_PIN(1, 4), /* A20 */ 6023 [21] = RCAR_GP_PIN(1, 5), /* A21 */ 6024 [22] = RCAR_GP_PIN(1, 6), /* A22 */ 6025 [23] = RCAR_GP_PIN(1, 7), /* A23 */ 6026 [24] = RCAR_GP_PIN(1, 8), /* A24 */ 6027 [25] = RCAR_GP_PIN(1, 9), /* A25 */ 6028 [26] = RCAR_GP_PIN(1, 12), /* EX_CS0# */ 6029 [27] = RCAR_GP_PIN(1, 13), /* EX_CS1# */ 6030 [28] = RCAR_GP_PIN(1, 14), /* EX_CS2# */ 6031 [29] = RCAR_GP_PIN(1, 15), /* EX_CS3# */ 6032 [30] = RCAR_GP_PIN(1, 16), /* EX_CS4# */ 6033 [31] = RCAR_GP_PIN(1, 17), /* EX_CS5# */ 6034 } }, 6035 { PINMUX_BIAS_REG("PUPR1", 0xe6060104, "N/A", 0) { 6036 /* PUPR1 pull-up pins */ 6037 [ 0] = RCAR_GP_PIN(1, 18), /* BS# */ 6038 [ 1] = RCAR_GP_PIN(1, 19), /* RD# */ 6039 [ 2] = RCAR_GP_PIN(1, 20), /* RD/WR# */ 6040 [ 3] = RCAR_GP_PIN(1, 21), /* WE0# */ 6041 [ 4] = RCAR_GP_PIN(1, 22), /* WE1# */ 6042 [ 5] = RCAR_GP_PIN(1, 23), /* EX_WAIT0 */ 6043 [ 6] = RCAR_GP_PIN(5, 24), /* AVS1 */ 6044 [ 7] = RCAR_GP_PIN(5, 25), /* AVS2 */ 6045 [ 8] = RCAR_GP_PIN(1, 10), /* CS0# */ 6046 [ 9] = RCAR_GP_PIN(1, 11), /* CS1#/A26 */ 6047 [10] = PIN_TRST_N, /* TRST# */ 6048 [11] = PIN_TCK, /* TCK */ 6049 [12] = PIN_TMS, /* TMS */ 6050 [13] = PIN_TDI, /* TDI */ 6051 [14] = SH_PFC_PIN_NONE, 6052 [15] = SH_PFC_PIN_NONE, 6053 [16] = RCAR_GP_PIN(0, 0), /* D0 */ 6054 [17] = RCAR_GP_PIN(0, 1), /* D1 */ 6055 [18] = RCAR_GP_PIN(0, 2), /* D2 */ 6056 [19] = RCAR_GP_PIN(0, 3), /* D3 */ 6057 [20] = RCAR_GP_PIN(0, 4), /* D4 */ 6058 [21] = RCAR_GP_PIN(0, 5), /* D5 */ 6059 [22] = RCAR_GP_PIN(0, 6), /* D6 */ 6060 [23] = RCAR_GP_PIN(0, 7), /* D7 */ 6061 [24] = RCAR_GP_PIN(0, 8), /* D8 */ 6062 [25] = RCAR_GP_PIN(0, 9), /* D9 */ 6063 [26] = RCAR_GP_PIN(0, 10), /* D10 */ 6064 [27] = RCAR_GP_PIN(0, 11), /* D11 */ 6065 [28] = RCAR_GP_PIN(0, 12), /* D12 */ 6066 [29] = RCAR_GP_PIN(0, 13), /* D13 */ 6067 [30] = RCAR_GP_PIN(0, 14), /* D14 */ 6068 [31] = RCAR_GP_PIN(0, 15), /* D15 */ 6069 } }, 6070 { PINMUX_BIAS_REG("N/A", 0, "PUPR1", 0xe6060104) { 6071 /* PUPR1 pull-down pins */ 6072 [ 0] = SH_PFC_PIN_NONE, 6073 [ 1] = SH_PFC_PIN_NONE, 6074 [ 2] = SH_PFC_PIN_NONE, 6075 [ 3] = SH_PFC_PIN_NONE, 6076 [ 4] = SH_PFC_PIN_NONE, 6077 [ 5] = SH_PFC_PIN_NONE, 6078 [ 6] = SH_PFC_PIN_NONE, 6079 [ 7] = SH_PFC_PIN_NONE, 6080 [ 8] = SH_PFC_PIN_NONE, 6081 [ 9] = SH_PFC_PIN_NONE, 6082 [10] = SH_PFC_PIN_NONE, 6083 [11] = SH_PFC_PIN_NONE, 6084 [12] = SH_PFC_PIN_NONE, 6085 [13] = SH_PFC_PIN_NONE, 6086 [14] = SH_PFC_PIN_NONE, 6087 [15] = PIN_ASEBRK_N_ACK, /* ASEBRK#/ACK */ 6088 [16] = SH_PFC_PIN_NONE, 6089 [17] = SH_PFC_PIN_NONE, 6090 [18] = SH_PFC_PIN_NONE, 6091 [19] = SH_PFC_PIN_NONE, 6092 [20] = SH_PFC_PIN_NONE, 6093 [21] = SH_PFC_PIN_NONE, 6094 [22] = SH_PFC_PIN_NONE, 6095 [23] = SH_PFC_PIN_NONE, 6096 [24] = SH_PFC_PIN_NONE, 6097 [25] = SH_PFC_PIN_NONE, 6098 [26] = SH_PFC_PIN_NONE, 6099 [27] = SH_PFC_PIN_NONE, 6100 [28] = SH_PFC_PIN_NONE, 6101 [29] = SH_PFC_PIN_NONE, 6102 [30] = SH_PFC_PIN_NONE, 6103 [31] = SH_PFC_PIN_NONE, 6104 } }, 6105 { PINMUX_BIAS_REG("PUPR2", 0xe6060108, "N/A", 0) { 6106 [ 0] = RCAR_GP_PIN(5, 28), /* DU_DOTCLKIN2 */ 6107 [ 1] = SH_PFC_PIN_NONE, 6108 [ 2] = SH_PFC_PIN_NONE, 6109 [ 3] = SH_PFC_PIN_NONE, 6110 [ 4] = SH_PFC_PIN_NONE, 6111 [ 5] = RCAR_GP_PIN(2, 0), /* VI0_CLK */ 6112 [ 6] = RCAR_GP_PIN(2, 1), /* VI0_DATA0_VI0_B0 */ 6113 [ 7] = RCAR_GP_PIN(2, 2), /* VI0_DATA1_VI0_B1 */ 6114 [ 8] = RCAR_GP_PIN(2, 3), /* VI0_DATA2_VI0_B2 */ 6115 [ 9] = RCAR_GP_PIN(2, 4), /* VI0_DATA3_VI0_B3 */ 6116 [10] = RCAR_GP_PIN(2, 5), /* VI0_DATA4_VI0_B4 */ 6117 [11] = RCAR_GP_PIN(2, 6), /* VI0_DATA5_VI0_B5 */ 6118 [12] = RCAR_GP_PIN(2, 7), /* VI0_DATA6_VI0_B6 */ 6119 [13] = RCAR_GP_PIN(2, 8), /* VI0_DATA7_VI0_B7 */ 6120 [14] = RCAR_GP_PIN(2, 9), /* VI1_CLK */ 6121 [15] = RCAR_GP_PIN(2, 10), /* VI1_DATA0_VI1_B0 */ 6122 [16] = RCAR_GP_PIN(2, 11), /* VI1_DATA1_VI1_B1 */ 6123 [17] = RCAR_GP_PIN(2, 12), /* VI1_DATA2_VI1_B2 */ 6124 [18] = RCAR_GP_PIN(2, 13), /* VI1_DATA3_VI1_B3 */ 6125 [19] = RCAR_GP_PIN(2, 14), /* VI1_DATA4_VI1_B4 */ 6126 [20] = RCAR_GP_PIN(2, 15), /* VI1_DATA5_VI1_B5 */ 6127 [21] = RCAR_GP_PIN(2, 16), /* VI1_DATA6_VI1_B6 */ 6128 [22] = RCAR_GP_PIN(2, 17), /* VI1_DATA7_VI1_B7 */ 6129 [23] = RCAR_GP_PIN(5, 27), /* DU_DOTCLKIN1 */ 6130 [24] = SH_PFC_PIN_NONE, 6131 [25] = SH_PFC_PIN_NONE, 6132 [26] = SH_PFC_PIN_NONE, 6133 [27] = RCAR_GP_PIN(4, 0), /* MLB_CLK */ 6134 [28] = RCAR_GP_PIN(4, 1), /* MLB_SIG */ 6135 [29] = RCAR_GP_PIN(4, 2), /* MLB_DAT */ 6136 [30] = SH_PFC_PIN_NONE, 6137 [31] = RCAR_GP_PIN(5, 26), /* DU_DOTCLKIN0 */ 6138 } }, 6139 { PINMUX_BIAS_REG("PUPR3", 0xe606010c, "N/A", 0) { 6140 [ 0] = RCAR_GP_PIN(3, 0), /* SD0_CLK */ 6141 [ 1] = RCAR_GP_PIN(3, 1), /* SD0_CMD */ 6142 [ 2] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */ 6143 [ 3] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */ 6144 [ 4] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */ 6145 [ 5] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */ 6146 [ 6] = RCAR_GP_PIN(3, 6), /* SD0_CD */ 6147 [ 7] = RCAR_GP_PIN(3, 7), /* SD0_WP */ 6148 [ 8] = RCAR_GP_PIN(3, 8), /* SD1_CLK */ 6149 [ 9] = RCAR_GP_PIN(3, 9), /* SD1_CMD */ 6150 [10] = RCAR_GP_PIN(3, 10), /* SD1_DAT0 */ 6151 [11] = RCAR_GP_PIN(3, 11), /* SD1_DAT1 */ 6152 [12] = RCAR_GP_PIN(3, 12), /* SD1_DAT2 */ 6153 [13] = RCAR_GP_PIN(3, 13), /* SD1_DAT3 */ 6154 [14] = RCAR_GP_PIN(3, 14), /* SD1_CD */ 6155 [15] = RCAR_GP_PIN(3, 15), /* SD1_WP */ 6156 [16] = RCAR_GP_PIN(3, 16), /* SD2_CLK */ 6157 [17] = RCAR_GP_PIN(3, 17), /* SD2_CMD */ 6158 [18] = RCAR_GP_PIN(3, 18), /* SD2_DAT0 */ 6159 [19] = RCAR_GP_PIN(3, 19), /* SD2_DAT1 */ 6160 [20] = RCAR_GP_PIN(3, 20), /* SD2_DAT2 */ 6161 [21] = RCAR_GP_PIN(3, 21), /* SD2_DAT3 */ 6162 [22] = RCAR_GP_PIN(3, 22), /* SD2_CD */ 6163 [23] = RCAR_GP_PIN(3, 23), /* SD2_WP */ 6164 [24] = RCAR_GP_PIN(3, 24), /* SD3_CLK */ 6165 [25] = RCAR_GP_PIN(3, 25), /* SD3_CMD */ 6166 [26] = RCAR_GP_PIN(3, 26), /* SD3_DAT0 */ 6167 [27] = RCAR_GP_PIN(3, 27), /* SD3_DAT1 */ 6168 [28] = RCAR_GP_PIN(3, 28), /* SD3_DAT2 */ 6169 [29] = RCAR_GP_PIN(3, 29), /* SD3_DAT3 */ 6170 [30] = RCAR_GP_PIN(3, 30), /* SD3_CD */ 6171 [31] = RCAR_GP_PIN(3, 31), /* SD3_WP */ 6172 } }, 6173 { PINMUX_BIAS_REG("PUPR4", 0xe6060110, "N/A", 0) { 6174 [ 0] = RCAR_GP_PIN(4, 3), /* SSI_SCK0129 */ 6175 [ 1] = RCAR_GP_PIN(4, 4), /* SSI_WS0129 */ 6176 [ 2] = RCAR_GP_PIN(4, 5), /* SSI_SDATA0 */ 6177 [ 3] = RCAR_GP_PIN(4, 6), /* SSI_SDATA1 */ 6178 [ 4] = RCAR_GP_PIN(4, 7), /* SSI_SDATA2 */ 6179 [ 5] = RCAR_GP_PIN(4, 8), /* SSI_SCK34 */ 6180 [ 6] = RCAR_GP_PIN(4, 9), /* SSI_WS34 */ 6181 [ 7] = RCAR_GP_PIN(4, 10), /* SSI_SDATA3 */ 6182 [ 8] = RCAR_GP_PIN(4, 11), /* SSI_SCK4 */ 6183 [ 9] = RCAR_GP_PIN(4, 12), /* SSI_WS4 */ 6184 [10] = RCAR_GP_PIN(4, 13), /* SSI_SDATA4 */ 6185 [11] = RCAR_GP_PIN(4, 14), /* SSI_SCK5 */ 6186 [12] = RCAR_GP_PIN(4, 15), /* SSI_WS5 */ 6187 [13] = RCAR_GP_PIN(4, 16), /* SSI_SDATA5 */ 6188 [14] = RCAR_GP_PIN(4, 17), /* SSI_SCK6 */ 6189 [15] = RCAR_GP_PIN(4, 18), /* SSI_WS6 */ 6190 [16] = RCAR_GP_PIN(4, 19), /* SSI_SDATA6 */ 6191 [17] = RCAR_GP_PIN(4, 20), /* SSI_SCK78 */ 6192 [18] = RCAR_GP_PIN(4, 21), /* SSI_WS78 */ 6193 [19] = RCAR_GP_PIN(4, 22), /* SSI_SDATA7 */ 6194 [20] = RCAR_GP_PIN(4, 23), /* SSI_SDATA8 */ 6195 [21] = RCAR_GP_PIN(4, 24), /* SSI_SDATA9 */ 6196 [22] = RCAR_GP_PIN(4, 25), /* AUDIO_CLKA */ 6197 [23] = RCAR_GP_PIN(4, 26), /* AUDIO_CLKB */ 6198 [24] = RCAR_GP_PIN(1, 24), /* DREQ0 */ 6199 [25] = RCAR_GP_PIN(1, 25), /* DACK0 */ 6200 [26] = RCAR_GP_PIN(1, 26), /* DREQ1 */ 6201 [27] = RCAR_GP_PIN(1, 27), /* DACK1 */ 6202 [28] = RCAR_GP_PIN(1, 28), /* DREQ2 */ 6203 [29] = RCAR_GP_PIN(1, 29), /* DACK2 */ 6204 [30] = RCAR_GP_PIN(2, 18), /* ETH_CRS_DV */ 6205 [31] = RCAR_GP_PIN(2, 19), /* ETH_RX_ER */ 6206 } }, 6207 { PINMUX_BIAS_REG("PUPR5", 0xe6060114, "N/A", 0) { 6208 [ 0] = RCAR_GP_PIN(4, 27), /* SCIFA0_SCK */ 6209 [ 1] = RCAR_GP_PIN(4, 28), /* SCIFA0_RXD */ 6210 [ 2] = RCAR_GP_PIN(4, 29), /* SCIFA0_TXD */ 6211 [ 3] = RCAR_GP_PIN(4, 30), /* SCIFA0_CTS# */ 6212 [ 4] = RCAR_GP_PIN(4, 31), /* SCIFA0_RTS# */ 6213 [ 5] = RCAR_GP_PIN(5, 0), /* SCIFA1_RXD */ 6214 [ 6] = RCAR_GP_PIN(5, 1), /* SCIFA1_TXD */ 6215 [ 7] = RCAR_GP_PIN(5, 2), /* SCIFA1_CTS# */ 6216 [ 8] = RCAR_GP_PIN(5, 3), /* SCIFA1_RTS# */ 6217 [ 9] = RCAR_GP_PIN(5, 4), /* SCIFA2_SCK */ 6218 [10] = RCAR_GP_PIN(5, 5), /* SCIFA2_RXD */ 6219 [11] = RCAR_GP_PIN(5, 6), /* SCIFA2_TXD */ 6220 [12] = RCAR_GP_PIN(5, 7), /* HSCK0 */ 6221 [13] = RCAR_GP_PIN(5, 8), /* HRX0 */ 6222 [14] = RCAR_GP_PIN(5, 9), /* HTX0 */ 6223 [15] = RCAR_GP_PIN(5, 10), /* HCTS0# */ 6224 [16] = RCAR_GP_PIN(5, 11), /* HRTS0# */ 6225 [17] = RCAR_GP_PIN(5, 12), /* MSIOF0_SCK */ 6226 [18] = RCAR_GP_PIN(5, 13), /* MSIOF0_SYNC */ 6227 [19] = RCAR_GP_PIN(5, 14), /* MSIOF0_SS1 */ 6228 [20] = RCAR_GP_PIN(5, 15), /* MSIOF0_TXD */ 6229 [21] = RCAR_GP_PIN(5, 16), /* MSIOF0_SS2 */ 6230 [22] = RCAR_GP_PIN(5, 17), /* MSIOF0_RXD */ 6231 [23] = RCAR_GP_PIN(5, 18), /* USB0_PWEN */ 6232 [24] = RCAR_GP_PIN(5, 19), /* USB0_OVC_VBUS */ 6233 [25] = RCAR_GP_PIN(5, 20), /* USB1_PWEN */ 6234 [26] = RCAR_GP_PIN(5, 21), /* USB1_OVC */ 6235 [27] = RCAR_GP_PIN(5, 22), /* USB2_PWEN */ 6236 [28] = RCAR_GP_PIN(5, 23), /* USB2_OVC */ 6237 [29] = RCAR_GP_PIN(2, 20), /* ETH_RXD0 */ 6238 [30] = RCAR_GP_PIN(2, 21), /* ETH_RXD1 */ 6239 [31] = RCAR_GP_PIN(2, 22), /* ETH_LINK */ 6240 } }, 6241 { PINMUX_BIAS_REG("PUPR6", 0xe6060118, "N/A", 0) { 6242 [ 0] = RCAR_GP_PIN(2, 23), /* ETH_REF_CLK */ 6243 [ 1] = RCAR_GP_PIN(2, 24), /* ETH_MDIO */ 6244 [ 2] = RCAR_GP_PIN(2, 25), /* ETH_TXD1 */ 6245 [ 3] = RCAR_GP_PIN(2, 26), /* ETH_TX_EN */ 6246 [ 4] = RCAR_GP_PIN(2, 27), /* ETH_MAGIC */ 6247 [ 5] = RCAR_GP_PIN(2, 28), /* ETH_TXD0 */ 6248 [ 6] = RCAR_GP_PIN(2, 29), /* ETH_MDC */ 6249 [ 7] = RCAR_GP_PIN(5, 29), /* PWM0 */ 6250 [ 8] = RCAR_GP_PIN(5, 30), /* PWM1 */ 6251 [ 9] = RCAR_GP_PIN(5, 31), /* PWM2 */ 6252 [10] = SH_PFC_PIN_NONE, 6253 [11] = SH_PFC_PIN_NONE, 6254 [12] = SH_PFC_PIN_NONE, 6255 [13] = SH_PFC_PIN_NONE, 6256 [14] = SH_PFC_PIN_NONE, 6257 [15] = SH_PFC_PIN_NONE, 6258 [16] = SH_PFC_PIN_NONE, 6259 [17] = SH_PFC_PIN_NONE, 6260 [18] = SH_PFC_PIN_NONE, 6261 [19] = SH_PFC_PIN_NONE, 6262 [20] = SH_PFC_PIN_NONE, 6263 [21] = SH_PFC_PIN_NONE, 6264 [22] = SH_PFC_PIN_NONE, 6265 [23] = SH_PFC_PIN_NONE, 6266 [24] = SH_PFC_PIN_NONE, 6267 [25] = SH_PFC_PIN_NONE, 6268 [26] = SH_PFC_PIN_NONE, 6269 [27] = SH_PFC_PIN_NONE, 6270 [28] = SH_PFC_PIN_NONE, 6271 [29] = SH_PFC_PIN_NONE, 6272 [30] = SH_PFC_PIN_NONE, 6273 [31] = SH_PFC_PIN_NONE, 6274 } }, 6275 { /* sentinel */ } 6276 }; 6277 6278 static const struct soc_device_attribute r8a7790_tdsel[] = { 6279 { .soc_id = "r8a7790", .revision = "ES1.0" }, 6280 { /* sentinel */ } 6281 }; 6282 6283 static int r8a7790_pinmux_soc_init(struct sh_pfc *pfc) 6284 { 6285 /* Initialize TDSEL on old revisions */ 6286 if (soc_device_match(r8a7790_tdsel)) 6287 sh_pfc_write(pfc, 0xe6060088, 0x00155554); 6288 6289 return 0; 6290 } 6291 6292 static const struct sh_pfc_soc_operations r8a7790_pinmux_ops = { 6293 .init = r8a7790_pinmux_soc_init, 6294 .pin_to_pocctrl = r8a7790_pin_to_pocctrl, 6295 .get_bias = rcar_pinmux_get_bias, 6296 .set_bias = rcar_pinmux_set_bias, 6297 }; 6298 6299 #ifdef CONFIG_PINCTRL_PFC_R8A7742 6300 const struct sh_pfc_soc_info r8a7742_pinmux_info = { 6301 .name = "r8a77420_pfc", 6302 .ops = &r8a7790_pinmux_ops, 6303 .unlock_reg = 0xe6060000, /* PMMR */ 6304 6305 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 6306 6307 .pins = pinmux_pins, 6308 .nr_pins = ARRAY_SIZE(pinmux_pins), 6309 .groups = pinmux_groups.common, 6310 .nr_groups = ARRAY_SIZE(pinmux_groups.common), 6311 .functions = pinmux_functions.common, 6312 .nr_functions = ARRAY_SIZE(pinmux_functions.common), 6313 6314 .cfg_regs = pinmux_config_regs, 6315 .bias_regs = pinmux_bias_regs, 6316 6317 .pinmux_data = pinmux_data, 6318 .pinmux_data_size = ARRAY_SIZE(pinmux_data), 6319 }; 6320 #endif 6321 6322 #ifdef CONFIG_PINCTRL_PFC_R8A7790 6323 const struct sh_pfc_soc_info r8a7790_pinmux_info = { 6324 .name = "r8a77900_pfc", 6325 .ops = &r8a7790_pinmux_ops, 6326 .unlock_reg = 0xe6060000, /* PMMR */ 6327 6328 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 6329 6330 .pins = pinmux_pins, 6331 .nr_pins = ARRAY_SIZE(pinmux_pins), 6332 .groups = pinmux_groups.common, 6333 .nr_groups = ARRAY_SIZE(pinmux_groups.common) + 6334 ARRAY_SIZE(pinmux_groups.automotive), 6335 .functions = pinmux_functions.common, 6336 .nr_functions = ARRAY_SIZE(pinmux_functions.common) + 6337 ARRAY_SIZE(pinmux_functions.automotive), 6338 6339 .cfg_regs = pinmux_config_regs, 6340 .bias_regs = pinmux_bias_regs, 6341 6342 .pinmux_data = pinmux_data, 6343 .pinmux_data_size = ARRAY_SIZE(pinmux_data), 6344 }; 6345 #endif 6346