1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * r8a7779 processor support - PFC hardware block 4 * 5 * Copyright (C) 2011, 2013 Renesas Solutions Corp. 6 * Copyright (C) 2011 Magnus Damm 7 * Copyright (C) 2013 Cogent Embedded, Inc. 8 */ 9 10 #include <linux/kernel.h> 11 12 #include "sh_pfc.h" 13 14 #define CPU_ALL_GP(fn, sfx) \ 15 PORT_GP_32(0, fn, sfx), \ 16 PORT_GP_32(1, fn, sfx), \ 17 PORT_GP_32(2, fn, sfx), \ 18 PORT_GP_32(3, fn, sfx), \ 19 PORT_GP_32(4, fn, sfx), \ 20 PORT_GP_32(5, fn, sfx), \ 21 PORT_GP_9(6, fn, sfx) 22 23 enum { 24 PINMUX_RESERVED = 0, 25 26 PINMUX_DATA_BEGIN, 27 GP_ALL(DATA), /* GP_0_0_DATA -> GP_6_8_DATA */ 28 PINMUX_DATA_END, 29 30 PINMUX_FUNCTION_BEGIN, 31 GP_ALL(FN), /* GP_0_0_FN -> GP_6_8_FN */ 32 33 /* GPSR0 */ 34 FN_AVS1, FN_AVS2, FN_IP0_7_6, FN_A17, 35 FN_A18, FN_A19, FN_IP0_9_8, FN_IP0_11_10, 36 FN_IP0_13_12, FN_IP0_15_14, FN_IP0_18_16, FN_IP0_22_19, 37 FN_IP0_24_23, FN_IP0_25, FN_IP0_27_26, FN_IP1_1_0, 38 FN_IP1_3_2, FN_IP1_6_4, FN_IP1_10_7, FN_IP1_14_11, 39 FN_IP1_18_15, FN_IP0_5_3, FN_IP0_30_28, FN_IP2_18_16, 40 FN_IP2_21_19, FN_IP2_30_28, FN_IP3_2_0, FN_IP3_11_9, 41 FN_IP3_14_12, FN_IP3_22_21, FN_IP3_26_24, FN_IP3_31_29, 42 43 /* GPSR1 */ 44 FN_IP4_1_0, FN_IP4_4_2, FN_IP4_7_5, FN_IP4_10_8, 45 FN_IP4_11, FN_IP4_12, FN_IP4_13, FN_IP4_14, 46 FN_IP4_15, FN_IP4_16, FN_IP4_19_17, FN_IP4_22_20, 47 FN_IP4_23, FN_IP4_24, FN_IP4_25, FN_IP4_26, 48 FN_IP4_27, FN_IP4_28, FN_IP4_31_29, FN_IP5_2_0, 49 FN_IP5_3, FN_IP5_4, FN_IP5_5, FN_IP5_6, 50 FN_IP5_7, FN_IP5_8, FN_IP5_10_9, FN_IP5_12_11, 51 FN_IP5_14_13, FN_IP5_16_15, FN_IP5_20_17, FN_IP5_23_21, 52 53 /* GPSR2 */ 54 FN_IP5_27_24, FN_IP8_20, FN_IP8_22_21, FN_IP8_24_23, 55 FN_IP8_27_25, FN_IP8_30_28, FN_IP9_1_0, FN_IP9_3_2, 56 FN_IP9_4, FN_IP9_5, FN_IP9_6, FN_IP9_7, 57 FN_IP9_9_8, FN_IP9_11_10, FN_IP9_13_12, FN_IP9_15_14, 58 FN_IP9_18_16, FN_IP9_21_19, FN_IP9_23_22, FN_IP9_25_24, 59 FN_IP9_27_26, FN_IP9_29_28, FN_IP10_2_0, FN_IP10_5_3, 60 FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_17_15, 61 FN_IP10_20_18, FN_IP10_23_21, FN_IP10_25_24, FN_IP10_28_26, 62 63 /* GPSR3 */ 64 FN_IP10_31_29, FN_IP11_2_0, FN_IP11_5_3, FN_IP11_8_6, 65 FN_IP11_11_9, FN_IP11_14_12, FN_IP11_17_15, FN_IP11_20_18, 66 FN_IP11_23_21, FN_IP11_26_24, FN_IP11_29_27, FN_IP12_2_0, 67 FN_IP12_5_3, FN_IP12_8_6, FN_IP12_11_9, FN_IP12_14_12, 68 FN_IP12_17_15, FN_IP7_16_15, FN_IP7_18_17, FN_IP7_28_27, 69 FN_IP7_30_29, FN_IP7_20_19, FN_IP7_22_21, FN_IP7_24_23, 70 FN_IP7_26_25, FN_IP1_20_19, FN_IP1_22_21, FN_IP1_24_23, 71 FN_IP5_28, FN_IP5_30_29, FN_IP6_1_0, FN_IP6_3_2, 72 73 /* GPSR4 */ 74 FN_IP6_5_4, FN_IP6_7_6, FN_IP6_8, FN_IP6_11_9, 75 FN_IP6_14_12, FN_IP6_17_15, FN_IP6_19_18, FN_IP6_22_20, 76 FN_IP6_24_23, FN_IP6_26_25, FN_IP6_30_29, FN_IP7_1_0, 77 FN_IP7_3_2, FN_IP7_6_4, FN_IP7_9_7, FN_IP7_12_10, 78 FN_IP7_14_13, FN_IP2_7_4, FN_IP2_11_8, FN_IP2_15_12, 79 FN_IP1_28_25, FN_IP2_3_0, FN_IP8_3_0, FN_IP8_7_4, 80 FN_IP8_11_8, FN_IP8_15_12, FN_USB_PENC0, FN_USB_PENC1, 81 FN_IP0_2_0, FN_IP8_17_16, FN_IP8_18, FN_IP8_19, 82 83 /* GPSR5 */ 84 FN_A1, FN_A2, FN_A3, FN_A4, 85 FN_A5, FN_A6, FN_A7, FN_A8, 86 FN_A9, FN_A10, FN_A11, FN_A12, 87 FN_A13, FN_A14, FN_A15, FN_A16, 88 FN_RD, FN_WE0, FN_WE1, FN_EX_WAIT0, 89 FN_IP3_23, FN_IP3_27, FN_IP3_28, FN_IP2_22, 90 FN_IP2_23, FN_IP2_24, FN_IP2_25, FN_IP2_26, 91 FN_IP2_27, FN_IP3_3, FN_IP3_4, FN_IP3_5, 92 93 /* GPSR6 */ 94 FN_IP3_6, FN_IP3_7, FN_IP3_8, FN_IP3_15, 95 FN_IP3_16, FN_IP3_17, FN_IP3_18, FN_IP3_19, 96 FN_IP3_20, 97 98 /* IPSR0 */ 99 FN_RD_WR, FN_FWE, FN_ATAG0, FN_VI1_R7, 100 FN_HRTS1, FN_RX4_C, 101 FN_CS1_A26, FN_HSPI_TX2, FN_SDSELF_B, 102 FN_CS0, FN_HSPI_CS2_B, 103 FN_CLKOUT, FN_TX3C_IRDA_TX_C, FN_PWM0_B, 104 FN_A25, FN_SD1_WP, FN_MMC0_D5, FN_FD5, 105 FN_HSPI_RX2, FN_VI1_R3, FN_TX5_B, FN_SSI_SDATA7_B, 106 FN_CTS0_B, 107 FN_A24, FN_SD1_CD, FN_MMC0_D4, FN_FD4, 108 FN_HSPI_CS2, FN_VI1_R2, FN_SSI_WS78_B, 109 FN_A23, FN_FCLE, FN_HSPI_CLK2, FN_VI1_R1, 110 FN_A22, FN_RX5_D, FN_HSPI_RX2_B, FN_VI1_R0, 111 FN_A21, FN_SCK5_D, FN_HSPI_CLK2_B, 112 FN_A20, FN_TX5_D, FN_HSPI_TX2_B, 113 FN_A0, FN_SD1_DAT3, FN_MMC0_D3, FN_FD3, 114 FN_BS, FN_SD1_DAT2, FN_MMC0_D2, FN_FD2, 115 FN_ATADIR0, FN_SDSELF, FN_HCTS1, FN_TX4_C, 116 FN_USB_PENC2, FN_SCK0, FN_PWM1, FN_PWMFSW0, 117 FN_SCIF_CLK, FN_TCLK0_C, 118 119 /* IPSR1 */ 120 FN_EX_CS0, FN_RX3_C_IRDA_RX_C, FN_MMC0_D6, 121 FN_FD6, FN_EX_CS1, FN_MMC0_D7, FN_FD7, 122 FN_EX_CS2, FN_SD1_CLK, FN_MMC0_CLK, FN_FALE, 123 FN_ATACS00, FN_EX_CS3, FN_SD1_CMD, FN_MMC0_CMD, 124 FN_FRE, FN_ATACS10, FN_VI1_R4, FN_RX5_B, 125 FN_HSCK1, FN_SSI_SDATA8_B, FN_RTS0_B_TANS_B, FN_SSI_SDATA9, 126 FN_EX_CS4, FN_SD1_DAT0, FN_MMC0_D0, FN_FD0, 127 FN_ATARD0, FN_VI1_R5, FN_SCK5_B, FN_HTX1, 128 FN_TX2_E, FN_TX0_B, FN_SSI_SCK9, FN_EX_CS5, 129 FN_SD1_DAT1, FN_MMC0_D1, FN_FD1, FN_ATAWR0, 130 FN_VI1_R6, FN_HRX1, FN_RX2_E, FN_RX0_B, 131 FN_SSI_WS9, FN_MLB_CLK, FN_PWM2, FN_SCK4, 132 FN_MLB_SIG, FN_PWM3, FN_TX4, FN_MLB_DAT, 133 FN_PWM4, FN_RX4, FN_HTX0, FN_TX1, 134 FN_SDATA, FN_CTS0_C, FN_SUB_TCK, FN_CC5_STATE2, 135 FN_CC5_STATE10, FN_CC5_STATE18, FN_CC5_STATE26, FN_CC5_STATE34, 136 137 /* IPSR2 */ 138 FN_HRX0, FN_RX1, FN_SCKZ, FN_RTS0_C_TANS_C, 139 FN_SUB_TDI, FN_CC5_STATE3, FN_CC5_STATE11, FN_CC5_STATE19, 140 FN_CC5_STATE27, FN_CC5_STATE35, FN_HSCK0, FN_SCK1, 141 FN_MTS, FN_PWM5, FN_SCK0_C, FN_SSI_SDATA9_B, 142 FN_SUB_TDO, FN_CC5_STATE0, FN_CC5_STATE8, FN_CC5_STATE16, 143 FN_CC5_STATE24, FN_CC5_STATE32, FN_HCTS0, FN_CTS1, 144 FN_STM, FN_PWM0_D, FN_RX0_C, FN_SCIF_CLK_C, 145 FN_SUB_TRST, FN_TCLK1_B, FN_CC5_OSCOUT, FN_HRTS0, 146 FN_RTS1_TANS, FN_MDATA, FN_TX0_C, FN_SUB_TMS, 147 FN_CC5_STATE1, FN_CC5_STATE9, FN_CC5_STATE17, FN_CC5_STATE25, 148 FN_CC5_STATE33, FN_DU0_DR0, FN_LCDOUT0, FN_DREQ0, 149 FN_GPS_CLK_B, FN_AUDATA0, FN_TX5_C, FN_DU0_DR1, 150 FN_LCDOUT1, FN_DACK0, FN_DRACK0, FN_GPS_SIGN_B, 151 FN_AUDATA1, FN_RX5_C, FN_DU0_DR2, FN_LCDOUT2, 152 FN_DU0_DR3, FN_LCDOUT3, FN_DU0_DR4, FN_LCDOUT4, 153 FN_DU0_DR5, FN_LCDOUT5, FN_DU0_DR6, FN_LCDOUT6, 154 FN_DU0_DR7, FN_LCDOUT7, FN_DU0_DG0, FN_LCDOUT8, 155 FN_DREQ1, FN_SCL2, FN_AUDATA2, 156 157 /* IPSR3 */ 158 FN_DU0_DG1, FN_LCDOUT9, FN_DACK1, FN_SDA2, 159 FN_AUDATA3, FN_DU0_DG2, FN_LCDOUT10, FN_DU0_DG3, 160 FN_LCDOUT11, FN_DU0_DG4, FN_LCDOUT12, FN_DU0_DG5, 161 FN_LCDOUT13, FN_DU0_DG6, FN_LCDOUT14, FN_DU0_DG7, 162 FN_LCDOUT15, FN_DU0_DB0, FN_LCDOUT16, FN_EX_WAIT1, 163 FN_SCL1, FN_TCLK1, FN_AUDATA4, FN_DU0_DB1, 164 FN_LCDOUT17, FN_EX_WAIT2, FN_SDA1, FN_GPS_MAG_B, 165 FN_AUDATA5, FN_SCK5_C, FN_DU0_DB2, FN_LCDOUT18, 166 FN_DU0_DB3, FN_LCDOUT19, FN_DU0_DB4, FN_LCDOUT20, 167 FN_DU0_DB5, FN_LCDOUT21, FN_DU0_DB6, FN_LCDOUT22, 168 FN_DU0_DB7, FN_LCDOUT23, FN_DU0_DOTCLKIN, FN_QSTVA_QVS, 169 FN_TX3_D_IRDA_TX_D, FN_SCL3_B, FN_DU0_DOTCLKOUT0, FN_QCLK, 170 FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE, FN_RX3_D_IRDA_RX_D, FN_SDA3_B, 171 FN_SDA2_C, FN_DACK0_B, FN_DRACK0_B, FN_DU0_EXHSYNC_DU0_HSYNC, 172 FN_QSTH_QHS, FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, 173 FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, FN_CAN1_TX, 174 FN_TX2_C, FN_SCL2_C, FN_REMOCON, 175 176 /* IPSR4 */ 177 FN_DU0_DISP, FN_QPOLA, FN_CAN_CLK_C, FN_SCK2_C, 178 FN_DU0_CDE, FN_QPOLB, FN_CAN1_RX, FN_RX2_C, 179 FN_DREQ0_B, FN_SSI_SCK78_B, FN_SCK0_B, FN_DU1_DR0, 180 FN_VI2_DATA0_VI2_B0, FN_PWM6, FN_SD3_CLK, FN_TX3_E_IRDA_TX_E, 181 FN_AUDCK, FN_PWMFSW0_B, FN_DU1_DR1, FN_VI2_DATA1_VI2_B1, 182 FN_PWM0, FN_SD3_CMD, FN_RX3_E_IRDA_RX_E, FN_AUDSYNC, 183 FN_CTS0_D, FN_DU1_DR2, FN_VI2_G0, FN_DU1_DR3, 184 FN_VI2_G1, FN_DU1_DR4, FN_VI2_G2, FN_DU1_DR5, 185 FN_VI2_G3, FN_DU1_DR6, FN_VI2_G4, FN_DU1_DR7, 186 FN_VI2_G5, FN_DU1_DG0, FN_VI2_DATA2_VI2_B2, FN_SCL1_B, 187 FN_SD3_DAT2, FN_SCK3_E, FN_AUDATA6, FN_TX0_D, 188 FN_DU1_DG1, FN_VI2_DATA3_VI2_B3, FN_SDA1_B, FN_SD3_DAT3, 189 FN_SCK5, FN_AUDATA7, FN_RX0_D, FN_DU1_DG2, 190 FN_VI2_G6, FN_DU1_DG3, FN_VI2_G7, FN_DU1_DG4, 191 FN_VI2_R0, FN_DU1_DG5, FN_VI2_R1, FN_DU1_DG6, 192 FN_VI2_R2, FN_DU1_DG7, FN_VI2_R3, FN_DU1_DB0, 193 FN_VI2_DATA4_VI2_B4, FN_SCL2_B, FN_SD3_DAT0, FN_TX5, 194 FN_SCK0_D, 195 196 /* IPSR5 */ 197 FN_DU1_DB1, FN_VI2_DATA5_VI2_B5, FN_SDA2_B, FN_SD3_DAT1, 198 FN_RX5, FN_RTS0_D_TANS_D, FN_DU1_DB2, FN_VI2_R4, 199 FN_DU1_DB3, FN_VI2_R5, FN_DU1_DB4, FN_VI2_R6, 200 FN_DU1_DB5, FN_VI2_R7, FN_DU1_DB6, FN_SCL2_D, 201 FN_DU1_DB7, FN_SDA2_D, FN_DU1_DOTCLKIN, FN_VI2_CLKENB, 202 FN_HSPI_CS1, FN_SCL1_D, FN_DU1_DOTCLKOUT, FN_VI2_FIELD, 203 FN_SDA1_D, FN_DU1_EXHSYNC_DU1_HSYNC, FN_VI2_HSYNC, 204 FN_VI3_HSYNC, FN_DU1_EXVSYNC_DU1_VSYNC, FN_VI2_VSYNC, FN_VI3_VSYNC, 205 FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_VI2_CLK, FN_TX3_B_IRDA_TX_B, 206 FN_SD3_CD, FN_HSPI_TX1, FN_VI1_CLKENB, FN_VI3_CLKENB, 207 FN_AUDIO_CLKC, FN_TX2_D, FN_SPEEDIN, FN_GPS_SIGN_D, 208 FN_DU1_DISP, FN_VI2_DATA6_VI2_B6, FN_TCLK0, FN_QSTVA_B_QVS_B, 209 FN_HSPI_CLK1, FN_SCK2_D, FN_AUDIO_CLKOUT_B, FN_GPS_MAG_D, 210 FN_DU1_CDE, FN_VI2_DATA7_VI2_B7, FN_RX3_B_IRDA_RX_B, 211 FN_SD3_WP, FN_HSPI_RX1, FN_VI1_FIELD, FN_VI3_FIELD, 212 FN_AUDIO_CLKOUT, FN_RX2_D, FN_GPS_CLK_C, FN_GPS_CLK_D, 213 FN_AUDIO_CLKA, FN_CAN_TXCLK, FN_AUDIO_CLKB, FN_USB_OVC2, 214 FN_CAN_DEBUGOUT0, FN_MOUT0, 215 216 /* IPSR6 */ 217 FN_SSI_SCK0129, FN_CAN_DEBUGOUT1, FN_MOUT1, FN_SSI_WS0129, 218 FN_CAN_DEBUGOUT2, FN_MOUT2, FN_SSI_SDATA0, FN_CAN_DEBUGOUT3, 219 FN_MOUT5, FN_SSI_SDATA1, FN_CAN_DEBUGOUT4, FN_MOUT6, 220 FN_SSI_SDATA2, FN_CAN_DEBUGOUT5, FN_SSI_SCK34, FN_CAN_DEBUGOUT6, 221 FN_CAN0_TX_B, FN_IERX, FN_SSI_SCK9_C, FN_SSI_WS34, 222 FN_CAN_DEBUGOUT7, FN_CAN0_RX_B, FN_IETX, FN_SSI_WS9_C, 223 FN_SSI_SDATA3, FN_PWM0_C, FN_CAN_DEBUGOUT8, FN_CAN_CLK_B, 224 FN_IECLK, FN_SCIF_CLK_B, FN_TCLK0_B, FN_SSI_SDATA4, 225 FN_CAN_DEBUGOUT9, FN_SSI_SDATA9_C, FN_SSI_SCK5, FN_ADICLK, 226 FN_CAN_DEBUGOUT10, FN_SCK3, FN_TCLK0_D, FN_SSI_WS5, 227 FN_ADICS_SAMP, FN_CAN_DEBUGOUT11, FN_TX3_IRDA_TX, FN_SSI_SDATA5, 228 FN_ADIDATA, FN_CAN_DEBUGOUT12, FN_RX3_IRDA_RX, FN_SSI_SCK6, 229 FN_ADICHS0, FN_CAN0_TX, FN_IERX_B, 230 231 /* IPSR7 */ 232 FN_SSI_WS6, FN_ADICHS1, FN_CAN0_RX, FN_IETX_B, 233 FN_SSI_SDATA6, FN_ADICHS2, FN_CAN_CLK, FN_IECLK_B, 234 FN_SSI_SCK78, FN_CAN_DEBUGOUT13, FN_IRQ0_B, FN_SSI_SCK9_B, 235 FN_HSPI_CLK1_C, FN_SSI_WS78, FN_CAN_DEBUGOUT14, FN_IRQ1_B, 236 FN_SSI_WS9_B, FN_HSPI_CS1_C, FN_SSI_SDATA7, FN_CAN_DEBUGOUT15, 237 FN_IRQ2_B, FN_TCLK1_C, FN_HSPI_TX1_C, FN_SSI_SDATA8, 238 FN_VSP, FN_IRQ3_B, FN_HSPI_RX1_C, FN_SD0_CLK, 239 FN_ATACS01, FN_SCK1_B, FN_SD0_CMD, FN_ATACS11, 240 FN_TX1_B, FN_CC5_TDO, FN_SD0_DAT0, FN_ATADIR1, 241 FN_RX1_B, FN_CC5_TRST, FN_SD0_DAT1, FN_ATAG1, 242 FN_SCK2_B, FN_CC5_TMS, FN_SD0_DAT2, FN_ATARD1, 243 FN_TX2_B, FN_CC5_TCK, FN_SD0_DAT3, FN_ATAWR1, 244 FN_RX2_B, FN_CC5_TDI, FN_SD0_CD, FN_DREQ2, 245 FN_RTS1_B_TANS_B, FN_SD0_WP, FN_DACK2, FN_CTS1_B, 246 247 /* IPSR8 */ 248 FN_HSPI_CLK0, FN_CTS0, FN_USB_OVC0, FN_AD_CLK, 249 FN_CC5_STATE4, FN_CC5_STATE12, FN_CC5_STATE20, FN_CC5_STATE28, 250 FN_CC5_STATE36, FN_HSPI_CS0, FN_RTS0_TANS, FN_USB_OVC1, 251 FN_AD_DI, FN_CC5_STATE5, FN_CC5_STATE13, FN_CC5_STATE21, 252 FN_CC5_STATE29, FN_CC5_STATE37, FN_HSPI_TX0, FN_TX0, 253 FN_CAN_DEBUG_HW_TRIGGER, FN_AD_DO, FN_CC5_STATE6, FN_CC5_STATE14, 254 FN_CC5_STATE22, FN_CC5_STATE30, FN_CC5_STATE38, FN_HSPI_RX0, 255 FN_RX0, FN_CAN_STEP0, FN_AD_NCS, FN_CC5_STATE7, 256 FN_CC5_STATE15, FN_CC5_STATE23, FN_CC5_STATE31, FN_CC5_STATE39, 257 FN_FMCLK, FN_RDS_CLK, FN_PCMOE, FN_BPFCLK, 258 FN_PCMWE, FN_FMIN, FN_RDS_DATA, FN_VI0_CLK, 259 FN_MMC1_CLK, FN_VI0_CLKENB, FN_TX1_C, FN_HTX1_B, 260 FN_MT1_SYNC, FN_VI0_FIELD, FN_RX1_C, FN_HRX1_B, 261 FN_VI0_HSYNC, FN_VI0_DATA0_B_VI0_B0_B, FN_CTS1_C, FN_TX4_D, 262 FN_MMC1_CMD, FN_HSCK1_B, FN_VI0_VSYNC, FN_VI0_DATA1_B_VI0_B1_B, 263 FN_RTS1_C_TANS_C, FN_RX4_D, FN_PWMFSW0_C, 264 265 /* IPSR9 */ 266 FN_VI0_DATA0_VI0_B0, FN_HRTS1_B, FN_MT1_VCXO, FN_VI0_DATA1_VI0_B1, 267 FN_HCTS1_B, FN_MT1_PWM, FN_VI0_DATA2_VI0_B2, FN_MMC1_D0, 268 FN_VI0_DATA3_VI0_B3, FN_MMC1_D1, FN_VI0_DATA4_VI0_B4, FN_MMC1_D2, 269 FN_VI0_DATA5_VI0_B5, FN_MMC1_D3, FN_VI0_DATA6_VI0_B6, FN_MMC1_D4, 270 FN_ARM_TRACEDATA_0, FN_VI0_DATA7_VI0_B7, FN_MMC1_D5, 271 FN_ARM_TRACEDATA_1, FN_VI0_G0, FN_SSI_SCK78_C, FN_IRQ0, 272 FN_ARM_TRACEDATA_2, FN_VI0_G1, FN_SSI_WS78_C, FN_IRQ1, 273 FN_ARM_TRACEDATA_3, FN_VI0_G2, FN_ETH_TXD1, FN_MMC1_D6, 274 FN_ARM_TRACEDATA_4, FN_TS_SPSYNC0, FN_VI0_G3, FN_ETH_CRS_DV, 275 FN_MMC1_D7, FN_ARM_TRACEDATA_5, FN_TS_SDAT0, FN_VI0_G4, 276 FN_ETH_TX_EN, FN_SD2_DAT0_B, FN_ARM_TRACEDATA_6, FN_VI0_G5, 277 FN_ETH_RX_ER, FN_SD2_DAT1_B, FN_ARM_TRACEDATA_7, FN_VI0_G6, 278 FN_ETH_RXD0, FN_SD2_DAT2_B, FN_ARM_TRACEDATA_8, FN_VI0_G7, 279 FN_ETH_RXD1, FN_SD2_DAT3_B, FN_ARM_TRACEDATA_9, 280 281 /* IPSR10 */ 282 FN_VI0_R0, FN_SSI_SDATA7_C, FN_SCK1_C, FN_DREQ1_B, 283 FN_ARM_TRACEDATA_10, FN_DREQ0_C, FN_VI0_R1, FN_SSI_SDATA8_C, 284 FN_DACK1_B, FN_ARM_TRACEDATA_11, FN_DACK0_C, FN_DRACK0_C, 285 FN_VI0_R2, FN_ETH_LINK, FN_SD2_CLK_B, FN_IRQ2, 286 FN_ARM_TRACEDATA_12, FN_VI0_R3, FN_ETH_MAGIC, FN_SD2_CMD_B, 287 FN_IRQ3, FN_ARM_TRACEDATA_13, FN_VI0_R4, FN_ETH_REFCLK, 288 FN_SD2_CD_B, FN_HSPI_CLK1_B, FN_ARM_TRACEDATA_14, FN_MT1_CLK, 289 FN_TS_SCK0, FN_VI0_R5, FN_ETH_TXD0, FN_SD2_WP_B, FN_HSPI_CS1_B, 290 FN_ARM_TRACEDATA_15, FN_MT1_D, FN_TS_SDEN0, FN_VI0_R6, 291 FN_ETH_MDC, FN_DREQ2_C, FN_HSPI_TX1_B, FN_TRACECLK, 292 FN_MT1_BEN, FN_PWMFSW0_D, FN_VI0_R7, FN_ETH_MDIO, 293 FN_DACK2_C, FN_HSPI_RX1_B, FN_SCIF_CLK_D, FN_TRACECTL, 294 FN_MT1_PEN, FN_VI1_CLK, FN_SIM_D, FN_SDA3, 295 FN_VI1_HSYNC, FN_VI3_CLK, FN_SSI_SCK4, FN_GPS_SIGN_C, 296 FN_PWMFSW0_E, FN_VI1_VSYNC, FN_AUDIO_CLKOUT_C, FN_SSI_WS4, 297 FN_SIM_CLK, FN_GPS_MAG_C, FN_SPV_TRST, FN_SCL3, 298 299 /* IPSR11 */ 300 FN_VI1_DATA0_VI1_B0, FN_SD2_DAT0, FN_SIM_RST, FN_SPV_TCK, 301 FN_ADICLK_B, FN_VI1_DATA1_VI1_B1, FN_SD2_DAT1, FN_MT0_CLK, 302 FN_SPV_TMS, FN_ADICS_B_SAMP_B, FN_VI1_DATA2_VI1_B2, FN_SD2_DAT2, 303 FN_MT0_D, FN_SPVTDI, FN_ADIDATA_B, FN_VI1_DATA3_VI1_B3, 304 FN_SD2_DAT3, FN_MT0_BEN, FN_SPV_TDO, FN_ADICHS0_B, 305 FN_VI1_DATA4_VI1_B4, FN_SD2_CLK, FN_MT0_PEN, FN_SPA_TRST, 306 FN_HSPI_CLK1_D, FN_ADICHS1_B, FN_VI1_DATA5_VI1_B5, FN_SD2_CMD, 307 FN_MT0_SYNC, FN_SPA_TCK, FN_HSPI_CS1_D, FN_ADICHS2_B, 308 FN_VI1_DATA6_VI1_B6, FN_SD2_CD, FN_MT0_VCXO, FN_SPA_TMS, 309 FN_HSPI_TX1_D, FN_VI1_DATA7_VI1_B7, FN_SD2_WP, FN_MT0_PWM, 310 FN_SPA_TDI, FN_HSPI_RX1_D, FN_VI1_G0, FN_VI3_DATA0, 311 FN_TS_SCK1, FN_DREQ2_B, FN_TX2, 312 FN_SPA_TDO, FN_HCTS0_B, FN_VI1_G1, FN_VI3_DATA1, 313 FN_SSI_SCK1, FN_TS_SDEN1, FN_DACK2_B, FN_RX2, FN_HRTS0_B, 314 315 /* IPSR12 */ 316 FN_VI1_G2, FN_VI3_DATA2, FN_SSI_WS1, FN_TS_SPSYNC1, 317 FN_SCK2, FN_HSCK0_B, FN_VI1_G3, FN_VI3_DATA3, 318 FN_SSI_SCK2, FN_TS_SDAT1, FN_SCL1_C, FN_HTX0_B, 319 FN_VI1_G4, FN_VI3_DATA4, FN_SSI_WS2, FN_SDA1_C, 320 FN_SIM_RST_B, FN_HRX0_B, FN_VI1_G5, FN_VI3_DATA5, 321 FN_GPS_CLK, FN_FSE, FN_TX4_B, FN_SIM_D_B, 322 FN_VI1_G6, FN_VI3_DATA6, FN_GPS_SIGN, FN_FRB, 323 FN_RX4_B, FN_SIM_CLK_B, FN_VI1_G7, FN_VI3_DATA7, 324 FN_GPS_MAG, FN_FCE, FN_SCK4_B, 325 326 FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3, 327 FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3, 328 FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, 329 FN_SEL_SCIF3_3, FN_SEL_SCIF3_4, 330 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, 331 FN_SEL_SCIF2_3, FN_SEL_SCIF2_4, 332 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, 333 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3, 334 FN_SEL_SSI9_0, FN_SEL_SSI9_1, FN_SEL_SSI9_2, 335 FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2, 336 FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2, 337 FN_SEL_VI0_0, FN_SEL_VI0_1, 338 FN_SEL_SD2_0, FN_SEL_SD2_1, 339 FN_SEL_INT3_0, FN_SEL_INT3_1, 340 FN_SEL_INT2_0, FN_SEL_INT2_1, 341 FN_SEL_INT1_0, FN_SEL_INT1_1, 342 FN_SEL_INT0_0, FN_SEL_INT0_1, 343 FN_SEL_IE_0, FN_SEL_IE_1, 344 FN_SEL_EXBUS2_0, FN_SEL_EXBUS2_1, FN_SEL_EXBUS2_2, 345 FN_SEL_EXBUS1_0, FN_SEL_EXBUS1_1, 346 FN_SEL_EXBUS0_0, FN_SEL_EXBUS0_1, FN_SEL_EXBUS0_2, 347 348 FN_SEL_TMU1_0, FN_SEL_TMU1_1, FN_SEL_TMU1_2, 349 FN_SEL_TMU0_0, FN_SEL_TMU0_1, FN_SEL_TMU0_2, FN_SEL_TMU0_3, 350 FN_SEL_SCIF_0, FN_SEL_SCIF_1, FN_SEL_SCIF_2, FN_SEL_SCIF_3, 351 FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2, 352 FN_SEL_CAN0_0, FN_SEL_CAN0_1, 353 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, 354 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, 355 FN_SEL_PWMFSW_0, FN_SEL_PWMFSW_1, FN_SEL_PWMFSW_2, 356 FN_SEL_PWMFSW_3, FN_SEL_PWMFSW_4, 357 FN_SEL_ADI_0, FN_SEL_ADI_1, 358 FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3, 359 FN_SEL_SIM_0, FN_SEL_SIM_1, 360 FN_SEL_HSPI2_0, FN_SEL_HSPI2_1, 361 FN_SEL_HSPI1_0, FN_SEL_HSPI1_1, FN_SEL_HSPI1_2, FN_SEL_HSPI1_3, 362 FN_SEL_I2C3_0, FN_SEL_I2C3_1, 363 FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3, 364 FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, FN_SEL_I2C1_3, 365 PINMUX_FUNCTION_END, 366 367 PINMUX_MARK_BEGIN, 368 AVS1_MARK, AVS2_MARK, A17_MARK, A18_MARK, 369 A19_MARK, 370 371 RD_WR_MARK, FWE_MARK, ATAG0_MARK, VI1_R7_MARK, 372 HRTS1_MARK, RX4_C_MARK, 373 CS1_A26_MARK, HSPI_TX2_MARK, SDSELF_B_MARK, 374 CS0_MARK, HSPI_CS2_B_MARK, 375 CLKOUT_MARK, TX3C_IRDA_TX_C_MARK, PWM0_B_MARK, 376 A25_MARK, SD1_WP_MARK, MMC0_D5_MARK, FD5_MARK, 377 HSPI_RX2_MARK, VI1_R3_MARK, TX5_B_MARK, SSI_SDATA7_B_MARK, CTS0_B_MARK, 378 A24_MARK, SD1_CD_MARK, MMC0_D4_MARK, FD4_MARK, 379 HSPI_CS2_MARK, VI1_R2_MARK, SSI_WS78_B_MARK, 380 A23_MARK, FCLE_MARK, HSPI_CLK2_MARK, VI1_R1_MARK, 381 A22_MARK, RX5_D_MARK, HSPI_RX2_B_MARK, VI1_R0_MARK, 382 A21_MARK, SCK5_D_MARK, HSPI_CLK2_B_MARK, 383 A20_MARK, TX5_D_MARK, HSPI_TX2_B_MARK, 384 A0_MARK, SD1_DAT3_MARK, MMC0_D3_MARK, FD3_MARK, 385 BS_MARK, SD1_DAT2_MARK, MMC0_D2_MARK, FD2_MARK, 386 ATADIR0_MARK, SDSELF_MARK, HCTS1_MARK, TX4_C_MARK, 387 USB_PENC0_MARK, USB_PENC1_MARK, USB_PENC2_MARK, 388 SCK0_MARK, PWM1_MARK, PWMFSW0_MARK, 389 SCIF_CLK_MARK, TCLK0_C_MARK, 390 391 EX_CS0_MARK, RX3_C_IRDA_RX_C_MARK, MMC0_D6_MARK, 392 FD6_MARK, EX_CS1_MARK, MMC0_D7_MARK, FD7_MARK, 393 EX_CS2_MARK, SD1_CLK_MARK, MMC0_CLK_MARK, FALE_MARK, 394 ATACS00_MARK, EX_CS3_MARK, SD1_CMD_MARK, MMC0_CMD_MARK, 395 FRE_MARK, ATACS10_MARK, VI1_R4_MARK, RX5_B_MARK, 396 HSCK1_MARK, SSI_SDATA8_B_MARK, RTS0_B_TANS_B_MARK, SSI_SDATA9_MARK, 397 EX_CS4_MARK, SD1_DAT0_MARK, MMC0_D0_MARK, FD0_MARK, 398 ATARD0_MARK, VI1_R5_MARK, SCK5_B_MARK, HTX1_MARK, 399 TX2_E_MARK, TX0_B_MARK, SSI_SCK9_MARK, EX_CS5_MARK, 400 SD1_DAT1_MARK, MMC0_D1_MARK, FD1_MARK, ATAWR0_MARK, 401 VI1_R6_MARK, HRX1_MARK, RX2_E_MARK, RX0_B_MARK, 402 SSI_WS9_MARK, MLB_CLK_MARK, PWM2_MARK, SCK4_MARK, 403 MLB_SIG_MARK, PWM3_MARK, TX4_MARK, MLB_DAT_MARK, 404 PWM4_MARK, RX4_MARK, HTX0_MARK, TX1_MARK, 405 SDATA_MARK, CTS0_C_MARK, SUB_TCK_MARK, CC5_STATE2_MARK, 406 CC5_STATE10_MARK, CC5_STATE18_MARK, CC5_STATE26_MARK, CC5_STATE34_MARK, 407 408 HRX0_MARK, RX1_MARK, SCKZ_MARK, RTS0_C_TANS_C_MARK, 409 SUB_TDI_MARK, CC5_STATE3_MARK, CC5_STATE11_MARK, CC5_STATE19_MARK, 410 CC5_STATE27_MARK, CC5_STATE35_MARK, HSCK0_MARK, SCK1_MARK, 411 MTS_MARK, PWM5_MARK, SCK0_C_MARK, SSI_SDATA9_B_MARK, 412 SUB_TDO_MARK, CC5_STATE0_MARK, CC5_STATE8_MARK, CC5_STATE16_MARK, 413 CC5_STATE24_MARK, CC5_STATE32_MARK, HCTS0_MARK, CTS1_MARK, 414 STM_MARK, PWM0_D_MARK, RX0_C_MARK, SCIF_CLK_C_MARK, 415 SUB_TRST_MARK, TCLK1_B_MARK, CC5_OSCOUT_MARK, HRTS0_MARK, 416 RTS1_TANS_MARK, MDATA_MARK, TX0_C_MARK, SUB_TMS_MARK, 417 CC5_STATE1_MARK, CC5_STATE9_MARK, CC5_STATE17_MARK, CC5_STATE25_MARK, 418 CC5_STATE33_MARK, DU0_DR0_MARK, LCDOUT0_MARK, DREQ0_MARK, 419 GPS_CLK_B_MARK, AUDATA0_MARK, TX5_C_MARK, DU0_DR1_MARK, 420 LCDOUT1_MARK, DACK0_MARK, DRACK0_MARK, GPS_SIGN_B_MARK, 421 AUDATA1_MARK, RX5_C_MARK, DU0_DR2_MARK, LCDOUT2_MARK, 422 DU0_DR3_MARK, LCDOUT3_MARK, DU0_DR4_MARK, LCDOUT4_MARK, 423 DU0_DR5_MARK, LCDOUT5_MARK, DU0_DR6_MARK, LCDOUT6_MARK, 424 DU0_DR7_MARK, LCDOUT7_MARK, DU0_DG0_MARK, LCDOUT8_MARK, 425 DREQ1_MARK, SCL2_MARK, AUDATA2_MARK, 426 427 DU0_DG1_MARK, LCDOUT9_MARK, DACK1_MARK, SDA2_MARK, 428 AUDATA3_MARK, DU0_DG2_MARK, LCDOUT10_MARK, DU0_DG3_MARK, 429 LCDOUT11_MARK, DU0_DG4_MARK, LCDOUT12_MARK, DU0_DG5_MARK, 430 LCDOUT13_MARK, DU0_DG6_MARK, LCDOUT14_MARK, DU0_DG7_MARK, 431 LCDOUT15_MARK, DU0_DB0_MARK, LCDOUT16_MARK, EX_WAIT1_MARK, 432 SCL1_MARK, TCLK1_MARK, AUDATA4_MARK, DU0_DB1_MARK, 433 LCDOUT17_MARK, EX_WAIT2_MARK, SDA1_MARK, GPS_MAG_B_MARK, 434 AUDATA5_MARK, SCK5_C_MARK, DU0_DB2_MARK, LCDOUT18_MARK, 435 DU0_DB3_MARK, LCDOUT19_MARK, DU0_DB4_MARK, LCDOUT20_MARK, 436 DU0_DB5_MARK, LCDOUT21_MARK, DU0_DB6_MARK, LCDOUT22_MARK, 437 DU0_DB7_MARK, LCDOUT23_MARK, DU0_DOTCLKIN_MARK, QSTVA_QVS_MARK, 438 TX3_D_IRDA_TX_D_MARK, SCL3_B_MARK, DU0_DOTCLKOUT0_MARK, QCLK_MARK, 439 DU0_DOTCLKOUT1_MARK, QSTVB_QVE_MARK, RX3_D_IRDA_RX_D_MARK, SDA3_B_MARK, 440 SDA2_C_MARK, DACK0_B_MARK, DRACK0_B_MARK, DU0_EXHSYNC_DU0_HSYNC_MARK, 441 QSTH_QHS_MARK, DU0_EXVSYNC_DU0_VSYNC_MARK, QSTB_QHE_MARK, 442 DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK, CAN1_TX_MARK, 443 TX2_C_MARK, SCL2_C_MARK, REMOCON_MARK, 444 445 DU0_DISP_MARK, QPOLA_MARK, CAN_CLK_C_MARK, SCK2_C_MARK, 446 DU0_CDE_MARK, QPOLB_MARK, CAN1_RX_MARK, RX2_C_MARK, 447 DREQ0_B_MARK, SSI_SCK78_B_MARK, SCK0_B_MARK, DU1_DR0_MARK, 448 VI2_DATA0_VI2_B0_MARK, PWM6_MARK, SD3_CLK_MARK, TX3_E_IRDA_TX_E_MARK, 449 AUDCK_MARK, PWMFSW0_B_MARK, DU1_DR1_MARK, VI2_DATA1_VI2_B1_MARK, 450 PWM0_MARK, SD3_CMD_MARK, RX3_E_IRDA_RX_E_MARK, AUDSYNC_MARK, 451 CTS0_D_MARK, DU1_DR2_MARK, VI2_G0_MARK, DU1_DR3_MARK, 452 VI2_G1_MARK, DU1_DR4_MARK, VI2_G2_MARK, DU1_DR5_MARK, 453 VI2_G3_MARK, DU1_DR6_MARK, VI2_G4_MARK, DU1_DR7_MARK, 454 VI2_G5_MARK, DU1_DG0_MARK, VI2_DATA2_VI2_B2_MARK, SCL1_B_MARK, 455 SD3_DAT2_MARK, SCK3_E_MARK, AUDATA6_MARK, TX0_D_MARK, 456 DU1_DG1_MARK, VI2_DATA3_VI2_B3_MARK, SDA1_B_MARK, SD3_DAT3_MARK, 457 SCK5_MARK, AUDATA7_MARK, RX0_D_MARK, DU1_DG2_MARK, 458 VI2_G6_MARK, DU1_DG3_MARK, VI2_G7_MARK, DU1_DG4_MARK, 459 VI2_R0_MARK, DU1_DG5_MARK, VI2_R1_MARK, DU1_DG6_MARK, 460 VI2_R2_MARK, DU1_DG7_MARK, VI2_R3_MARK, DU1_DB0_MARK, 461 VI2_DATA4_VI2_B4_MARK, SCL2_B_MARK, SD3_DAT0_MARK, TX5_MARK, 462 SCK0_D_MARK, 463 464 DU1_DB1_MARK, VI2_DATA5_VI2_B5_MARK, SDA2_B_MARK, SD3_DAT1_MARK, 465 RX5_MARK, RTS0_D_TANS_D_MARK, DU1_DB2_MARK, VI2_R4_MARK, 466 DU1_DB3_MARK, VI2_R5_MARK, DU1_DB4_MARK, VI2_R6_MARK, 467 DU1_DB5_MARK, VI2_R7_MARK, DU1_DB6_MARK, SCL2_D_MARK, 468 DU1_DB7_MARK, SDA2_D_MARK, DU1_DOTCLKIN_MARK, VI2_CLKENB_MARK, 469 HSPI_CS1_MARK, SCL1_D_MARK, DU1_DOTCLKOUT_MARK, VI2_FIELD_MARK, 470 SDA1_D_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK, VI2_HSYNC_MARK, 471 VI3_HSYNC_MARK, DU1_EXVSYNC_DU1_VSYNC_MARK, VI2_VSYNC_MARK, 472 VI3_VSYNC_MARK, DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK, VI2_CLK_MARK, 473 TX3_B_IRDA_TX_B_MARK, SD3_CD_MARK, HSPI_TX1_MARK, VI1_CLKENB_MARK, 474 VI3_CLKENB_MARK, AUDIO_CLKC_MARK, TX2_D_MARK, SPEEDIN_MARK, 475 GPS_SIGN_D_MARK, DU1_DISP_MARK, VI2_DATA6_VI2_B6_MARK, TCLK0_MARK, 476 QSTVA_B_QVS_B_MARK, HSPI_CLK1_MARK, SCK2_D_MARK, AUDIO_CLKOUT_B_MARK, 477 GPS_MAG_D_MARK, DU1_CDE_MARK, VI2_DATA7_VI2_B7_MARK, 478 RX3_B_IRDA_RX_B_MARK, SD3_WP_MARK, HSPI_RX1_MARK, VI1_FIELD_MARK, 479 VI3_FIELD_MARK, AUDIO_CLKOUT_MARK, RX2_D_MARK, GPS_CLK_C_MARK, 480 GPS_CLK_D_MARK, AUDIO_CLKA_MARK, CAN_TXCLK_MARK, AUDIO_CLKB_MARK, 481 USB_OVC2_MARK, CAN_DEBUGOUT0_MARK, MOUT0_MARK, 482 483 SSI_SCK0129_MARK, CAN_DEBUGOUT1_MARK, MOUT1_MARK, SSI_WS0129_MARK, 484 CAN_DEBUGOUT2_MARK, MOUT2_MARK, SSI_SDATA0_MARK, CAN_DEBUGOUT3_MARK, 485 MOUT5_MARK, SSI_SDATA1_MARK, CAN_DEBUGOUT4_MARK, MOUT6_MARK, 486 SSI_SDATA2_MARK, CAN_DEBUGOUT5_MARK, SSI_SCK34_MARK, 487 CAN_DEBUGOUT6_MARK, CAN0_TX_B_MARK, IERX_MARK, SSI_SCK9_C_MARK, 488 SSI_WS34_MARK, CAN_DEBUGOUT7_MARK, CAN0_RX_B_MARK, IETX_MARK, 489 SSI_WS9_C_MARK, SSI_SDATA3_MARK, PWM0_C_MARK, CAN_DEBUGOUT8_MARK, 490 CAN_CLK_B_MARK, IECLK_MARK, SCIF_CLK_B_MARK, TCLK0_B_MARK, 491 SSI_SDATA4_MARK, CAN_DEBUGOUT9_MARK, SSI_SDATA9_C_MARK, SSI_SCK5_MARK, 492 ADICLK_MARK, CAN_DEBUGOUT10_MARK, SCK3_MARK, TCLK0_D_MARK, 493 SSI_WS5_MARK, ADICS_SAMP_MARK, CAN_DEBUGOUT11_MARK, TX3_IRDA_TX_MARK, 494 SSI_SDATA5_MARK, ADIDATA_MARK, CAN_DEBUGOUT12_MARK, RX3_IRDA_RX_MARK, 495 SSI_SCK6_MARK, ADICHS0_MARK, CAN0_TX_MARK, IERX_B_MARK, 496 497 SSI_WS6_MARK, ADICHS1_MARK, CAN0_RX_MARK, IETX_B_MARK, 498 SSI_SDATA6_MARK, ADICHS2_MARK, CAN_CLK_MARK, IECLK_B_MARK, 499 SSI_SCK78_MARK, CAN_DEBUGOUT13_MARK, IRQ0_B_MARK, SSI_SCK9_B_MARK, 500 HSPI_CLK1_C_MARK, SSI_WS78_MARK, CAN_DEBUGOUT14_MARK, IRQ1_B_MARK, 501 SSI_WS9_B_MARK, HSPI_CS1_C_MARK, SSI_SDATA7_MARK, CAN_DEBUGOUT15_MARK, 502 IRQ2_B_MARK, TCLK1_C_MARK, HSPI_TX1_C_MARK, SSI_SDATA8_MARK, 503 VSP_MARK, IRQ3_B_MARK, HSPI_RX1_C_MARK, SD0_CLK_MARK, 504 ATACS01_MARK, SCK1_B_MARK, SD0_CMD_MARK, ATACS11_MARK, 505 TX1_B_MARK, CC5_TDO_MARK, SD0_DAT0_MARK, ATADIR1_MARK, 506 RX1_B_MARK, CC5_TRST_MARK, SD0_DAT1_MARK, ATAG1_MARK, 507 SCK2_B_MARK, CC5_TMS_MARK, SD0_DAT2_MARK, ATARD1_MARK, 508 TX2_B_MARK, CC5_TCK_MARK, SD0_DAT3_MARK, ATAWR1_MARK, 509 RX2_B_MARK, CC5_TDI_MARK, SD0_CD_MARK, DREQ2_MARK, 510 RTS1_B_TANS_B_MARK, SD0_WP_MARK, DACK2_MARK, CTS1_B_MARK, 511 512 HSPI_CLK0_MARK, CTS0_MARK, USB_OVC0_MARK, AD_CLK_MARK, 513 CC5_STATE4_MARK, CC5_STATE12_MARK, CC5_STATE20_MARK, CC5_STATE28_MARK, 514 CC5_STATE36_MARK, HSPI_CS0_MARK, RTS0_TANS_MARK, USB_OVC1_MARK, 515 AD_DI_MARK, CC5_STATE5_MARK, CC5_STATE13_MARK, CC5_STATE21_MARK, 516 CC5_STATE29_MARK, CC5_STATE37_MARK, HSPI_TX0_MARK, TX0_MARK, 517 CAN_DEBUG_HW_TRIGGER_MARK, AD_DO_MARK, CC5_STATE6_MARK, 518 CC5_STATE14_MARK, CC5_STATE22_MARK, CC5_STATE30_MARK, 519 CC5_STATE38_MARK, HSPI_RX0_MARK, RX0_MARK, CAN_STEP0_MARK, 520 AD_NCS_MARK, CC5_STATE7_MARK, CC5_STATE15_MARK, CC5_STATE23_MARK, 521 CC5_STATE31_MARK, CC5_STATE39_MARK, FMCLK_MARK, RDS_CLK_MARK, 522 PCMOE_MARK, BPFCLK_MARK, PCMWE_MARK, FMIN_MARK, RDS_DATA_MARK, 523 VI0_CLK_MARK, MMC1_CLK_MARK, VI0_CLKENB_MARK, TX1_C_MARK, HTX1_B_MARK, 524 MT1_SYNC_MARK, VI0_FIELD_MARK, RX1_C_MARK, HRX1_B_MARK, 525 VI0_HSYNC_MARK, VI0_DATA0_B_VI0_B0_B_MARK, CTS1_C_MARK, TX4_D_MARK, 526 MMC1_CMD_MARK, HSCK1_B_MARK, VI0_VSYNC_MARK, VI0_DATA1_B_VI0_B1_B_MARK, 527 RTS1_C_TANS_C_MARK, RX4_D_MARK, PWMFSW0_C_MARK, 528 529 VI0_DATA0_VI0_B0_MARK, HRTS1_B_MARK, MT1_VCXO_MARK, 530 VI0_DATA1_VI0_B1_MARK, HCTS1_B_MARK, MT1_PWM_MARK, 531 VI0_DATA2_VI0_B2_MARK, MMC1_D0_MARK, VI0_DATA3_VI0_B3_MARK, 532 MMC1_D1_MARK, VI0_DATA4_VI0_B4_MARK, MMC1_D2_MARK, 533 VI0_DATA5_VI0_B5_MARK, MMC1_D3_MARK, VI0_DATA6_VI0_B6_MARK, 534 MMC1_D4_MARK, ARM_TRACEDATA_0_MARK, VI0_DATA7_VI0_B7_MARK, 535 MMC1_D5_MARK, ARM_TRACEDATA_1_MARK, VI0_G0_MARK, SSI_SCK78_C_MARK, 536 IRQ0_MARK, ARM_TRACEDATA_2_MARK, VI0_G1_MARK, SSI_WS78_C_MARK, 537 IRQ1_MARK, ARM_TRACEDATA_3_MARK, VI0_G2_MARK, ETH_TXD1_MARK, 538 MMC1_D6_MARK, ARM_TRACEDATA_4_MARK, TS_SPSYNC0_MARK, VI0_G3_MARK, 539 ETH_CRS_DV_MARK, MMC1_D7_MARK, ARM_TRACEDATA_5_MARK, TS_SDAT0_MARK, 540 VI0_G4_MARK, ETH_TX_EN_MARK, SD2_DAT0_B_MARK, ARM_TRACEDATA_6_MARK, 541 VI0_G5_MARK, ETH_RX_ER_MARK, SD2_DAT1_B_MARK, ARM_TRACEDATA_7_MARK, 542 VI0_G6_MARK, ETH_RXD0_MARK, SD2_DAT2_B_MARK, ARM_TRACEDATA_8_MARK, 543 VI0_G7_MARK, ETH_RXD1_MARK, SD2_DAT3_B_MARK, ARM_TRACEDATA_9_MARK, 544 545 VI0_R0_MARK, SSI_SDATA7_C_MARK, SCK1_C_MARK, DREQ1_B_MARK, 546 ARM_TRACEDATA_10_MARK, DREQ0_C_MARK, VI0_R1_MARK, SSI_SDATA8_C_MARK, 547 DACK1_B_MARK, ARM_TRACEDATA_11_MARK, DACK0_C_MARK, DRACK0_C_MARK, 548 VI0_R2_MARK, ETH_LINK_MARK, SD2_CLK_B_MARK, IRQ2_MARK, 549 ARM_TRACEDATA_12_MARK, VI0_R3_MARK, ETH_MAGIC_MARK, SD2_CMD_B_MARK, 550 IRQ3_MARK, ARM_TRACEDATA_13_MARK, VI0_R4_MARK, ETH_REFCLK_MARK, 551 SD2_CD_B_MARK, HSPI_CLK1_B_MARK, ARM_TRACEDATA_14_MARK, MT1_CLK_MARK, 552 TS_SCK0_MARK, VI0_R5_MARK, ETH_TXD0_MARK, SD2_WP_B_MARK, 553 HSPI_CS1_B_MARK, ARM_TRACEDATA_15_MARK, MT1_D_MARK, TS_SDEN0_MARK, 554 VI0_R6_MARK, ETH_MDC_MARK, DREQ2_C_MARK, HSPI_TX1_B_MARK, 555 TRACECLK_MARK, MT1_BEN_MARK, PWMFSW0_D_MARK, VI0_R7_MARK, 556 ETH_MDIO_MARK, DACK2_C_MARK, HSPI_RX1_B_MARK, SCIF_CLK_D_MARK, 557 TRACECTL_MARK, MT1_PEN_MARK, VI1_CLK_MARK, SIM_D_MARK, SDA3_MARK, 558 VI1_HSYNC_MARK, VI3_CLK_MARK, SSI_SCK4_MARK, GPS_SIGN_C_MARK, 559 PWMFSW0_E_MARK, VI1_VSYNC_MARK, AUDIO_CLKOUT_C_MARK, SSI_WS4_MARK, 560 SIM_CLK_MARK, GPS_MAG_C_MARK, SPV_TRST_MARK, SCL3_MARK, 561 562 VI1_DATA0_VI1_B0_MARK, SD2_DAT0_MARK, SIM_RST_MARK, SPV_TCK_MARK, 563 ADICLK_B_MARK, VI1_DATA1_VI1_B1_MARK, SD2_DAT1_MARK, MT0_CLK_MARK, 564 SPV_TMS_MARK, ADICS_B_SAMP_B_MARK, VI1_DATA2_VI1_B2_MARK, 565 SD2_DAT2_MARK, MT0_D_MARK, SPVTDI_MARK, ADIDATA_B_MARK, 566 VI1_DATA3_VI1_B3_MARK, SD2_DAT3_MARK, MT0_BEN_MARK, SPV_TDO_MARK, 567 ADICHS0_B_MARK, VI1_DATA4_VI1_B4_MARK, SD2_CLK_MARK, MT0_PEN_MARK, 568 SPA_TRST_MARK, HSPI_CLK1_D_MARK, ADICHS1_B_MARK, 569 VI1_DATA5_VI1_B5_MARK, SD2_CMD_MARK, MT0_SYNC_MARK, SPA_TCK_MARK, 570 HSPI_CS1_D_MARK, ADICHS2_B_MARK, VI1_DATA6_VI1_B6_MARK, SD2_CD_MARK, 571 MT0_VCXO_MARK, SPA_TMS_MARK, HSPI_TX1_D_MARK, VI1_DATA7_VI1_B7_MARK, 572 SD2_WP_MARK, MT0_PWM_MARK, SPA_TDI_MARK, HSPI_RX1_D_MARK, 573 VI1_G0_MARK, VI3_DATA0_MARK, TS_SCK1_MARK, 574 DREQ2_B_MARK, TX2_MARK, SPA_TDO_MARK, HCTS0_B_MARK, 575 VI1_G1_MARK, VI3_DATA1_MARK, SSI_SCK1_MARK, TS_SDEN1_MARK, 576 DACK2_B_MARK, RX2_MARK, HRTS0_B_MARK, 577 578 VI1_G2_MARK, VI3_DATA2_MARK, SSI_WS1_MARK, TS_SPSYNC1_MARK, 579 SCK2_MARK, HSCK0_B_MARK, VI1_G3_MARK, VI3_DATA3_MARK, 580 SSI_SCK2_MARK, TS_SDAT1_MARK, SCL1_C_MARK, HTX0_B_MARK, 581 VI1_G4_MARK, VI3_DATA4_MARK, SSI_WS2_MARK, SDA1_C_MARK, 582 SIM_RST_B_MARK, HRX0_B_MARK, VI1_G5_MARK, VI3_DATA5_MARK, 583 GPS_CLK_MARK, FSE_MARK, TX4_B_MARK, SIM_D_B_MARK, 584 VI1_G6_MARK, VI3_DATA6_MARK, GPS_SIGN_MARK, FRB_MARK, 585 RX4_B_MARK, SIM_CLK_B_MARK, VI1_G7_MARK, VI3_DATA7_MARK, 586 GPS_MAG_MARK, FCE_MARK, SCK4_B_MARK, 587 PINMUX_MARK_END, 588 }; 589 590 static const u16 pinmux_data[] = { 591 PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */ 592 593 PINMUX_SINGLE(AVS1), 594 PINMUX_SINGLE(AVS1), 595 PINMUX_SINGLE(A17), 596 PINMUX_SINGLE(A18), 597 PINMUX_SINGLE(A19), 598 599 PINMUX_SINGLE(USB_PENC0), 600 PINMUX_SINGLE(USB_PENC1), 601 602 PINMUX_IPSR_GPSR(IP0_2_0, USB_PENC2), 603 PINMUX_IPSR_MSEL(IP0_2_0, SCK0, SEL_SCIF0_0), 604 PINMUX_IPSR_GPSR(IP0_2_0, PWM1), 605 PINMUX_IPSR_MSEL(IP0_2_0, PWMFSW0, SEL_PWMFSW_0), 606 PINMUX_IPSR_MSEL(IP0_2_0, SCIF_CLK, SEL_SCIF_0), 607 PINMUX_IPSR_MSEL(IP0_2_0, TCLK0_C, SEL_TMU0_2), 608 PINMUX_IPSR_GPSR(IP0_5_3, BS), 609 PINMUX_IPSR_GPSR(IP0_5_3, SD1_DAT2), 610 PINMUX_IPSR_GPSR(IP0_5_3, MMC0_D2), 611 PINMUX_IPSR_GPSR(IP0_5_3, FD2), 612 PINMUX_IPSR_GPSR(IP0_5_3, ATADIR0), 613 PINMUX_IPSR_GPSR(IP0_5_3, SDSELF), 614 PINMUX_IPSR_MSEL(IP0_5_3, HCTS1, SEL_HSCIF1_0), 615 PINMUX_IPSR_GPSR(IP0_5_3, TX4_C), 616 PINMUX_IPSR_GPSR(IP0_7_6, A0), 617 PINMUX_IPSR_GPSR(IP0_7_6, SD1_DAT3), 618 PINMUX_IPSR_GPSR(IP0_7_6, MMC0_D3), 619 PINMUX_IPSR_GPSR(IP0_7_6, FD3), 620 PINMUX_IPSR_GPSR(IP0_9_8, A20), 621 PINMUX_IPSR_GPSR(IP0_9_8, TX5_D), 622 PINMUX_IPSR_GPSR(IP0_9_8, HSPI_TX2_B), 623 PINMUX_IPSR_GPSR(IP0_11_10, A21), 624 PINMUX_IPSR_MSEL(IP0_11_10, SCK5_D, SEL_SCIF5_3), 625 PINMUX_IPSR_MSEL(IP0_11_10, HSPI_CLK2_B, SEL_HSPI2_1), 626 PINMUX_IPSR_GPSR(IP0_13_12, A22), 627 PINMUX_IPSR_MSEL(IP0_13_12, RX5_D, SEL_SCIF5_3), 628 PINMUX_IPSR_MSEL(IP0_13_12, HSPI_RX2_B, SEL_HSPI2_1), 629 PINMUX_IPSR_GPSR(IP0_13_12, VI1_R0), 630 PINMUX_IPSR_GPSR(IP0_15_14, A23), 631 PINMUX_IPSR_GPSR(IP0_15_14, FCLE), 632 PINMUX_IPSR_MSEL(IP0_15_14, HSPI_CLK2, SEL_HSPI2_0), 633 PINMUX_IPSR_GPSR(IP0_15_14, VI1_R1), 634 PINMUX_IPSR_GPSR(IP0_18_16, A24), 635 PINMUX_IPSR_GPSR(IP0_18_16, SD1_CD), 636 PINMUX_IPSR_GPSR(IP0_18_16, MMC0_D4), 637 PINMUX_IPSR_GPSR(IP0_18_16, FD4), 638 PINMUX_IPSR_MSEL(IP0_18_16, HSPI_CS2, SEL_HSPI2_0), 639 PINMUX_IPSR_GPSR(IP0_18_16, VI1_R2), 640 PINMUX_IPSR_MSEL(IP0_18_16, SSI_WS78_B, SEL_SSI7_1), 641 PINMUX_IPSR_GPSR(IP0_22_19, A25), 642 PINMUX_IPSR_GPSR(IP0_22_19, SD1_WP), 643 PINMUX_IPSR_GPSR(IP0_22_19, MMC0_D5), 644 PINMUX_IPSR_GPSR(IP0_22_19, FD5), 645 PINMUX_IPSR_MSEL(IP0_22_19, HSPI_RX2, SEL_HSPI2_0), 646 PINMUX_IPSR_GPSR(IP0_22_19, VI1_R3), 647 PINMUX_IPSR_GPSR(IP0_22_19, TX5_B), 648 PINMUX_IPSR_MSEL(IP0_22_19, SSI_SDATA7_B, SEL_SSI7_1), 649 PINMUX_IPSR_MSEL(IP0_22_19, CTS0_B, SEL_SCIF0_1), 650 PINMUX_IPSR_GPSR(IP0_24_23, CLKOUT), 651 PINMUX_IPSR_GPSR(IP0_24_23, TX3C_IRDA_TX_C), 652 PINMUX_IPSR_GPSR(IP0_24_23, PWM0_B), 653 PINMUX_IPSR_GPSR(IP0_25, CS0), 654 PINMUX_IPSR_MSEL(IP0_25, HSPI_CS2_B, SEL_HSPI2_1), 655 PINMUX_IPSR_GPSR(IP0_27_26, CS1_A26), 656 PINMUX_IPSR_GPSR(IP0_27_26, HSPI_TX2), 657 PINMUX_IPSR_GPSR(IP0_27_26, SDSELF_B), 658 PINMUX_IPSR_GPSR(IP0_30_28, RD_WR), 659 PINMUX_IPSR_GPSR(IP0_30_28, FWE), 660 PINMUX_IPSR_GPSR(IP0_30_28, ATAG0), 661 PINMUX_IPSR_GPSR(IP0_30_28, VI1_R7), 662 PINMUX_IPSR_MSEL(IP0_30_28, HRTS1, SEL_HSCIF1_0), 663 PINMUX_IPSR_MSEL(IP0_30_28, RX4_C, SEL_SCIF4_2), 664 665 PINMUX_IPSR_GPSR(IP1_1_0, EX_CS0), 666 PINMUX_IPSR_MSEL(IP1_1_0, RX3_C_IRDA_RX_C, SEL_SCIF3_2), 667 PINMUX_IPSR_GPSR(IP1_1_0, MMC0_D6), 668 PINMUX_IPSR_GPSR(IP1_1_0, FD6), 669 PINMUX_IPSR_GPSR(IP1_3_2, EX_CS1), 670 PINMUX_IPSR_GPSR(IP1_3_2, MMC0_D7), 671 PINMUX_IPSR_GPSR(IP1_3_2, FD7), 672 PINMUX_IPSR_GPSR(IP1_6_4, EX_CS2), 673 PINMUX_IPSR_GPSR(IP1_6_4, SD1_CLK), 674 PINMUX_IPSR_GPSR(IP1_6_4, MMC0_CLK), 675 PINMUX_IPSR_GPSR(IP1_6_4, FALE), 676 PINMUX_IPSR_GPSR(IP1_6_4, ATACS00), 677 PINMUX_IPSR_GPSR(IP1_10_7, EX_CS3), 678 PINMUX_IPSR_GPSR(IP1_10_7, SD1_CMD), 679 PINMUX_IPSR_GPSR(IP1_10_7, MMC0_CMD), 680 PINMUX_IPSR_GPSR(IP1_10_7, FRE), 681 PINMUX_IPSR_GPSR(IP1_10_7, ATACS10), 682 PINMUX_IPSR_GPSR(IP1_10_7, VI1_R4), 683 PINMUX_IPSR_MSEL(IP1_10_7, RX5_B, SEL_SCIF5_1), 684 PINMUX_IPSR_MSEL(IP1_10_7, HSCK1, SEL_HSCIF1_0), 685 PINMUX_IPSR_MSEL(IP1_10_7, SSI_SDATA8_B, SEL_SSI8_1), 686 PINMUX_IPSR_MSEL(IP1_10_7, RTS0_B_TANS_B, SEL_SCIF0_1), 687 PINMUX_IPSR_MSEL(IP1_10_7, SSI_SDATA9, SEL_SSI9_0), 688 PINMUX_IPSR_GPSR(IP1_14_11, EX_CS4), 689 PINMUX_IPSR_GPSR(IP1_14_11, SD1_DAT0), 690 PINMUX_IPSR_GPSR(IP1_14_11, MMC0_D0), 691 PINMUX_IPSR_GPSR(IP1_14_11, FD0), 692 PINMUX_IPSR_GPSR(IP1_14_11, ATARD0), 693 PINMUX_IPSR_GPSR(IP1_14_11, VI1_R5), 694 PINMUX_IPSR_MSEL(IP1_14_11, SCK5_B, SEL_SCIF5_1), 695 PINMUX_IPSR_GPSR(IP1_14_11, HTX1), 696 PINMUX_IPSR_GPSR(IP1_14_11, TX2_E), 697 PINMUX_IPSR_GPSR(IP1_14_11, TX0_B), 698 PINMUX_IPSR_MSEL(IP1_14_11, SSI_SCK9, SEL_SSI9_0), 699 PINMUX_IPSR_GPSR(IP1_18_15, EX_CS5), 700 PINMUX_IPSR_GPSR(IP1_18_15, SD1_DAT1), 701 PINMUX_IPSR_GPSR(IP1_18_15, MMC0_D1), 702 PINMUX_IPSR_GPSR(IP1_18_15, FD1), 703 PINMUX_IPSR_GPSR(IP1_18_15, ATAWR0), 704 PINMUX_IPSR_GPSR(IP1_18_15, VI1_R6), 705 PINMUX_IPSR_MSEL(IP1_18_15, HRX1, SEL_HSCIF1_0), 706 PINMUX_IPSR_MSEL(IP1_18_15, RX2_E, SEL_SCIF2_4), 707 PINMUX_IPSR_MSEL(IP1_18_15, RX0_B, SEL_SCIF0_1), 708 PINMUX_IPSR_MSEL(IP1_18_15, SSI_WS9, SEL_SSI9_0), 709 PINMUX_IPSR_GPSR(IP1_20_19, MLB_CLK), 710 PINMUX_IPSR_GPSR(IP1_20_19, PWM2), 711 PINMUX_IPSR_MSEL(IP1_20_19, SCK4, SEL_SCIF4_0), 712 PINMUX_IPSR_GPSR(IP1_22_21, MLB_SIG), 713 PINMUX_IPSR_GPSR(IP1_22_21, PWM3), 714 PINMUX_IPSR_GPSR(IP1_22_21, TX4), 715 PINMUX_IPSR_GPSR(IP1_24_23, MLB_DAT), 716 PINMUX_IPSR_GPSR(IP1_24_23, PWM4), 717 PINMUX_IPSR_MSEL(IP1_24_23, RX4, SEL_SCIF4_0), 718 PINMUX_IPSR_GPSR(IP1_28_25, HTX0), 719 PINMUX_IPSR_GPSR(IP1_28_25, TX1), 720 PINMUX_IPSR_GPSR(IP1_28_25, SDATA), 721 PINMUX_IPSR_MSEL(IP1_28_25, CTS0_C, SEL_SCIF0_2), 722 PINMUX_IPSR_GPSR(IP1_28_25, SUB_TCK), 723 PINMUX_IPSR_GPSR(IP1_28_25, CC5_STATE2), 724 PINMUX_IPSR_GPSR(IP1_28_25, CC5_STATE10), 725 PINMUX_IPSR_GPSR(IP1_28_25, CC5_STATE18), 726 PINMUX_IPSR_GPSR(IP1_28_25, CC5_STATE26), 727 PINMUX_IPSR_GPSR(IP1_28_25, CC5_STATE34), 728 729 PINMUX_IPSR_MSEL(IP2_3_0, HRX0, SEL_HSCIF0_0), 730 PINMUX_IPSR_MSEL(IP2_3_0, RX1, SEL_SCIF1_0), 731 PINMUX_IPSR_GPSR(IP2_3_0, SCKZ), 732 PINMUX_IPSR_MSEL(IP2_3_0, RTS0_C_TANS_C, SEL_SCIF0_2), 733 PINMUX_IPSR_GPSR(IP2_3_0, SUB_TDI), 734 PINMUX_IPSR_GPSR(IP2_3_0, CC5_STATE3), 735 PINMUX_IPSR_GPSR(IP2_3_0, CC5_STATE11), 736 PINMUX_IPSR_GPSR(IP2_3_0, CC5_STATE19), 737 PINMUX_IPSR_GPSR(IP2_3_0, CC5_STATE27), 738 PINMUX_IPSR_GPSR(IP2_3_0, CC5_STATE35), 739 PINMUX_IPSR_MSEL(IP2_7_4, HSCK0, SEL_HSCIF0_0), 740 PINMUX_IPSR_MSEL(IP2_7_4, SCK1, SEL_SCIF1_0), 741 PINMUX_IPSR_GPSR(IP2_7_4, MTS), 742 PINMUX_IPSR_GPSR(IP2_7_4, PWM5), 743 PINMUX_IPSR_MSEL(IP2_7_4, SCK0_C, SEL_SCIF0_2), 744 PINMUX_IPSR_MSEL(IP2_7_4, SSI_SDATA9_B, SEL_SSI9_1), 745 PINMUX_IPSR_GPSR(IP2_7_4, SUB_TDO), 746 PINMUX_IPSR_GPSR(IP2_7_4, CC5_STATE0), 747 PINMUX_IPSR_GPSR(IP2_7_4, CC5_STATE8), 748 PINMUX_IPSR_GPSR(IP2_7_4, CC5_STATE16), 749 PINMUX_IPSR_GPSR(IP2_7_4, CC5_STATE24), 750 PINMUX_IPSR_GPSR(IP2_7_4, CC5_STATE32), 751 PINMUX_IPSR_MSEL(IP2_11_8, HCTS0, SEL_HSCIF0_0), 752 PINMUX_IPSR_MSEL(IP2_11_8, CTS1, SEL_SCIF1_0), 753 PINMUX_IPSR_GPSR(IP2_11_8, STM), 754 PINMUX_IPSR_GPSR(IP2_11_8, PWM0_D), 755 PINMUX_IPSR_MSEL(IP2_11_8, RX0_C, SEL_SCIF0_2), 756 PINMUX_IPSR_MSEL(IP2_11_8, SCIF_CLK_C, SEL_SCIF_2), 757 PINMUX_IPSR_GPSR(IP2_11_8, SUB_TRST), 758 PINMUX_IPSR_MSEL(IP2_11_8, TCLK1_B, SEL_TMU1_1), 759 PINMUX_IPSR_GPSR(IP2_11_8, CC5_OSCOUT), 760 PINMUX_IPSR_MSEL(IP2_15_12, HRTS0, SEL_HSCIF0_0), 761 PINMUX_IPSR_MSEL(IP2_15_12, RTS1_TANS, SEL_SCIF1_0), 762 PINMUX_IPSR_GPSR(IP2_15_12, MDATA), 763 PINMUX_IPSR_GPSR(IP2_15_12, TX0_C), 764 PINMUX_IPSR_GPSR(IP2_15_12, SUB_TMS), 765 PINMUX_IPSR_GPSR(IP2_15_12, CC5_STATE1), 766 PINMUX_IPSR_GPSR(IP2_15_12, CC5_STATE9), 767 PINMUX_IPSR_GPSR(IP2_15_12, CC5_STATE17), 768 PINMUX_IPSR_GPSR(IP2_15_12, CC5_STATE25), 769 PINMUX_IPSR_GPSR(IP2_15_12, CC5_STATE33), 770 PINMUX_IPSR_GPSR(IP2_18_16, DU0_DR0), 771 PINMUX_IPSR_GPSR(IP2_18_16, LCDOUT0), 772 PINMUX_IPSR_MSEL(IP2_18_16, DREQ0, SEL_EXBUS0_0), 773 PINMUX_IPSR_MSEL(IP2_18_16, GPS_CLK_B, SEL_GPS_1), 774 PINMUX_IPSR_GPSR(IP2_18_16, AUDATA0), 775 PINMUX_IPSR_GPSR(IP2_18_16, TX5_C), 776 PINMUX_IPSR_GPSR(IP2_21_19, DU0_DR1), 777 PINMUX_IPSR_GPSR(IP2_21_19, LCDOUT1), 778 PINMUX_IPSR_GPSR(IP2_21_19, DACK0), 779 PINMUX_IPSR_GPSR(IP2_21_19, DRACK0), 780 PINMUX_IPSR_MSEL(IP2_21_19, GPS_SIGN_B, SEL_GPS_1), 781 PINMUX_IPSR_GPSR(IP2_21_19, AUDATA1), 782 PINMUX_IPSR_MSEL(IP2_21_19, RX5_C, SEL_SCIF5_2), 783 PINMUX_IPSR_GPSR(IP2_22, DU0_DR2), 784 PINMUX_IPSR_GPSR(IP2_22, LCDOUT2), 785 PINMUX_IPSR_GPSR(IP2_23, DU0_DR3), 786 PINMUX_IPSR_GPSR(IP2_23, LCDOUT3), 787 PINMUX_IPSR_GPSR(IP2_24, DU0_DR4), 788 PINMUX_IPSR_GPSR(IP2_24, LCDOUT4), 789 PINMUX_IPSR_GPSR(IP2_25, DU0_DR5), 790 PINMUX_IPSR_GPSR(IP2_25, LCDOUT5), 791 PINMUX_IPSR_GPSR(IP2_26, DU0_DR6), 792 PINMUX_IPSR_GPSR(IP2_26, LCDOUT6), 793 PINMUX_IPSR_GPSR(IP2_27, DU0_DR7), 794 PINMUX_IPSR_GPSR(IP2_27, LCDOUT7), 795 PINMUX_IPSR_GPSR(IP2_30_28, DU0_DG0), 796 PINMUX_IPSR_GPSR(IP2_30_28, LCDOUT8), 797 PINMUX_IPSR_MSEL(IP2_30_28, DREQ1, SEL_EXBUS1_0), 798 PINMUX_IPSR_MSEL(IP2_30_28, SCL2, SEL_I2C2_0), 799 PINMUX_IPSR_GPSR(IP2_30_28, AUDATA2), 800 801 PINMUX_IPSR_GPSR(IP3_2_0, DU0_DG1), 802 PINMUX_IPSR_GPSR(IP3_2_0, LCDOUT9), 803 PINMUX_IPSR_GPSR(IP3_2_0, DACK1), 804 PINMUX_IPSR_MSEL(IP3_2_0, SDA2, SEL_I2C2_0), 805 PINMUX_IPSR_GPSR(IP3_2_0, AUDATA3), 806 PINMUX_IPSR_GPSR(IP3_3, DU0_DG2), 807 PINMUX_IPSR_GPSR(IP3_3, LCDOUT10), 808 PINMUX_IPSR_GPSR(IP3_4, DU0_DG3), 809 PINMUX_IPSR_GPSR(IP3_4, LCDOUT11), 810 PINMUX_IPSR_GPSR(IP3_5, DU0_DG4), 811 PINMUX_IPSR_GPSR(IP3_5, LCDOUT12), 812 PINMUX_IPSR_GPSR(IP3_6, DU0_DG5), 813 PINMUX_IPSR_GPSR(IP3_6, LCDOUT13), 814 PINMUX_IPSR_GPSR(IP3_7, DU0_DG6), 815 PINMUX_IPSR_GPSR(IP3_7, LCDOUT14), 816 PINMUX_IPSR_GPSR(IP3_8, DU0_DG7), 817 PINMUX_IPSR_GPSR(IP3_8, LCDOUT15), 818 PINMUX_IPSR_GPSR(IP3_11_9, DU0_DB0), 819 PINMUX_IPSR_GPSR(IP3_11_9, LCDOUT16), 820 PINMUX_IPSR_GPSR(IP3_11_9, EX_WAIT1), 821 PINMUX_IPSR_MSEL(IP3_11_9, SCL1, SEL_I2C1_0), 822 PINMUX_IPSR_MSEL(IP3_11_9, TCLK1, SEL_TMU1_0), 823 PINMUX_IPSR_GPSR(IP3_11_9, AUDATA4), 824 PINMUX_IPSR_GPSR(IP3_14_12, DU0_DB1), 825 PINMUX_IPSR_GPSR(IP3_14_12, LCDOUT17), 826 PINMUX_IPSR_GPSR(IP3_14_12, EX_WAIT2), 827 PINMUX_IPSR_MSEL(IP3_14_12, SDA1, SEL_I2C1_0), 828 PINMUX_IPSR_MSEL(IP3_14_12, GPS_MAG_B, SEL_GPS_1), 829 PINMUX_IPSR_GPSR(IP3_14_12, AUDATA5), 830 PINMUX_IPSR_MSEL(IP3_14_12, SCK5_C, SEL_SCIF5_2), 831 PINMUX_IPSR_GPSR(IP3_15, DU0_DB2), 832 PINMUX_IPSR_GPSR(IP3_15, LCDOUT18), 833 PINMUX_IPSR_GPSR(IP3_16, DU0_DB3), 834 PINMUX_IPSR_GPSR(IP3_16, LCDOUT19), 835 PINMUX_IPSR_GPSR(IP3_17, DU0_DB4), 836 PINMUX_IPSR_GPSR(IP3_17, LCDOUT20), 837 PINMUX_IPSR_GPSR(IP3_18, DU0_DB5), 838 PINMUX_IPSR_GPSR(IP3_18, LCDOUT21), 839 PINMUX_IPSR_GPSR(IP3_19, DU0_DB6), 840 PINMUX_IPSR_GPSR(IP3_19, LCDOUT22), 841 PINMUX_IPSR_GPSR(IP3_20, DU0_DB7), 842 PINMUX_IPSR_GPSR(IP3_20, LCDOUT23), 843 PINMUX_IPSR_GPSR(IP3_22_21, DU0_DOTCLKIN), 844 PINMUX_IPSR_GPSR(IP3_22_21, QSTVA_QVS), 845 PINMUX_IPSR_GPSR(IP3_22_21, TX3_D_IRDA_TX_D), 846 PINMUX_IPSR_MSEL(IP3_22_21, SCL3_B, SEL_I2C3_1), 847 PINMUX_IPSR_GPSR(IP3_23, DU0_DOTCLKOUT0), 848 PINMUX_IPSR_GPSR(IP3_23, QCLK), 849 PINMUX_IPSR_GPSR(IP3_26_24, DU0_DOTCLKOUT1), 850 PINMUX_IPSR_GPSR(IP3_26_24, QSTVB_QVE), 851 PINMUX_IPSR_MSEL(IP3_26_24, RX3_D_IRDA_RX_D, SEL_SCIF3_3), 852 PINMUX_IPSR_MSEL(IP3_26_24, SDA3_B, SEL_I2C3_1), 853 PINMUX_IPSR_MSEL(IP3_26_24, SDA2_C, SEL_I2C2_2), 854 PINMUX_IPSR_GPSR(IP3_26_24, DACK0_B), 855 PINMUX_IPSR_GPSR(IP3_26_24, DRACK0_B), 856 PINMUX_IPSR_GPSR(IP3_27, DU0_EXHSYNC_DU0_HSYNC), 857 PINMUX_IPSR_GPSR(IP3_27, QSTH_QHS), 858 PINMUX_IPSR_GPSR(IP3_28, DU0_EXVSYNC_DU0_VSYNC), 859 PINMUX_IPSR_GPSR(IP3_28, QSTB_QHE), 860 PINMUX_IPSR_GPSR(IP3_31_29, DU0_EXODDF_DU0_ODDF_DISP_CDE), 861 PINMUX_IPSR_GPSR(IP3_31_29, QCPV_QDE), 862 PINMUX_IPSR_GPSR(IP3_31_29, CAN1_TX), 863 PINMUX_IPSR_GPSR(IP3_31_29, TX2_C), 864 PINMUX_IPSR_MSEL(IP3_31_29, SCL2_C, SEL_I2C2_2), 865 PINMUX_IPSR_GPSR(IP3_31_29, REMOCON), 866 867 PINMUX_IPSR_GPSR(IP4_1_0, DU0_DISP), 868 PINMUX_IPSR_GPSR(IP4_1_0, QPOLA), 869 PINMUX_IPSR_MSEL(IP4_1_0, CAN_CLK_C, SEL_CANCLK_2), 870 PINMUX_IPSR_MSEL(IP4_1_0, SCK2_C, SEL_SCIF2_2), 871 PINMUX_IPSR_GPSR(IP4_4_2, DU0_CDE), 872 PINMUX_IPSR_GPSR(IP4_4_2, QPOLB), 873 PINMUX_IPSR_GPSR(IP4_4_2, CAN1_RX), 874 PINMUX_IPSR_MSEL(IP4_4_2, RX2_C, SEL_SCIF2_2), 875 PINMUX_IPSR_MSEL(IP4_4_2, DREQ0_B, SEL_EXBUS0_1), 876 PINMUX_IPSR_MSEL(IP4_4_2, SSI_SCK78_B, SEL_SSI7_1), 877 PINMUX_IPSR_MSEL(IP4_4_2, SCK0_B, SEL_SCIF0_1), 878 PINMUX_IPSR_GPSR(IP4_7_5, DU1_DR0), 879 PINMUX_IPSR_GPSR(IP4_7_5, VI2_DATA0_VI2_B0), 880 PINMUX_IPSR_GPSR(IP4_7_5, PWM6), 881 PINMUX_IPSR_GPSR(IP4_7_5, SD3_CLK), 882 PINMUX_IPSR_GPSR(IP4_7_5, TX3_E_IRDA_TX_E), 883 PINMUX_IPSR_GPSR(IP4_7_5, AUDCK), 884 PINMUX_IPSR_MSEL(IP4_7_5, PWMFSW0_B, SEL_PWMFSW_1), 885 PINMUX_IPSR_GPSR(IP4_10_8, DU1_DR1), 886 PINMUX_IPSR_GPSR(IP4_10_8, VI2_DATA1_VI2_B1), 887 PINMUX_IPSR_GPSR(IP4_10_8, PWM0), 888 PINMUX_IPSR_GPSR(IP4_10_8, SD3_CMD), 889 PINMUX_IPSR_MSEL(IP4_10_8, RX3_E_IRDA_RX_E, SEL_SCIF3_4), 890 PINMUX_IPSR_GPSR(IP4_10_8, AUDSYNC), 891 PINMUX_IPSR_MSEL(IP4_10_8, CTS0_D, SEL_SCIF0_3), 892 PINMUX_IPSR_GPSR(IP4_11, DU1_DR2), 893 PINMUX_IPSR_GPSR(IP4_11, VI2_G0), 894 PINMUX_IPSR_GPSR(IP4_12, DU1_DR3), 895 PINMUX_IPSR_GPSR(IP4_12, VI2_G1), 896 PINMUX_IPSR_GPSR(IP4_13, DU1_DR4), 897 PINMUX_IPSR_GPSR(IP4_13, VI2_G2), 898 PINMUX_IPSR_GPSR(IP4_14, DU1_DR5), 899 PINMUX_IPSR_GPSR(IP4_14, VI2_G3), 900 PINMUX_IPSR_GPSR(IP4_15, DU1_DR6), 901 PINMUX_IPSR_GPSR(IP4_15, VI2_G4), 902 PINMUX_IPSR_GPSR(IP4_16, DU1_DR7), 903 PINMUX_IPSR_GPSR(IP4_16, VI2_G5), 904 PINMUX_IPSR_GPSR(IP4_19_17, DU1_DG0), 905 PINMUX_IPSR_GPSR(IP4_19_17, VI2_DATA2_VI2_B2), 906 PINMUX_IPSR_MSEL(IP4_19_17, SCL1_B, SEL_I2C1_1), 907 PINMUX_IPSR_GPSR(IP4_19_17, SD3_DAT2), 908 PINMUX_IPSR_MSEL(IP4_19_17, SCK3_E, SEL_SCIF3_4), 909 PINMUX_IPSR_GPSR(IP4_19_17, AUDATA6), 910 PINMUX_IPSR_GPSR(IP4_19_17, TX0_D), 911 PINMUX_IPSR_GPSR(IP4_22_20, DU1_DG1), 912 PINMUX_IPSR_GPSR(IP4_22_20, VI2_DATA3_VI2_B3), 913 PINMUX_IPSR_MSEL(IP4_22_20, SDA1_B, SEL_I2C1_1), 914 PINMUX_IPSR_GPSR(IP4_22_20, SD3_DAT3), 915 PINMUX_IPSR_MSEL(IP4_22_20, SCK5, SEL_SCIF5_0), 916 PINMUX_IPSR_GPSR(IP4_22_20, AUDATA7), 917 PINMUX_IPSR_MSEL(IP4_22_20, RX0_D, SEL_SCIF0_3), 918 PINMUX_IPSR_GPSR(IP4_23, DU1_DG2), 919 PINMUX_IPSR_GPSR(IP4_23, VI2_G6), 920 PINMUX_IPSR_GPSR(IP4_24, DU1_DG3), 921 PINMUX_IPSR_GPSR(IP4_24, VI2_G7), 922 PINMUX_IPSR_GPSR(IP4_25, DU1_DG4), 923 PINMUX_IPSR_GPSR(IP4_25, VI2_R0), 924 PINMUX_IPSR_GPSR(IP4_26, DU1_DG5), 925 PINMUX_IPSR_GPSR(IP4_26, VI2_R1), 926 PINMUX_IPSR_GPSR(IP4_27, DU1_DG6), 927 PINMUX_IPSR_GPSR(IP4_27, VI2_R2), 928 PINMUX_IPSR_GPSR(IP4_28, DU1_DG7), 929 PINMUX_IPSR_GPSR(IP4_28, VI2_R3), 930 PINMUX_IPSR_GPSR(IP4_31_29, DU1_DB0), 931 PINMUX_IPSR_GPSR(IP4_31_29, VI2_DATA4_VI2_B4), 932 PINMUX_IPSR_MSEL(IP4_31_29, SCL2_B, SEL_I2C2_1), 933 PINMUX_IPSR_GPSR(IP4_31_29, SD3_DAT0), 934 PINMUX_IPSR_GPSR(IP4_31_29, TX5), 935 PINMUX_IPSR_MSEL(IP4_31_29, SCK0_D, SEL_SCIF0_3), 936 937 PINMUX_IPSR_GPSR(IP5_2_0, DU1_DB1), 938 PINMUX_IPSR_GPSR(IP5_2_0, VI2_DATA5_VI2_B5), 939 PINMUX_IPSR_MSEL(IP5_2_0, SDA2_B, SEL_I2C2_1), 940 PINMUX_IPSR_GPSR(IP5_2_0, SD3_DAT1), 941 PINMUX_IPSR_MSEL(IP5_2_0, RX5, SEL_SCIF5_0), 942 PINMUX_IPSR_MSEL(IP5_2_0, RTS0_D_TANS_D, SEL_SCIF0_3), 943 PINMUX_IPSR_GPSR(IP5_3, DU1_DB2), 944 PINMUX_IPSR_GPSR(IP5_3, VI2_R4), 945 PINMUX_IPSR_GPSR(IP5_4, DU1_DB3), 946 PINMUX_IPSR_GPSR(IP5_4, VI2_R5), 947 PINMUX_IPSR_GPSR(IP5_5, DU1_DB4), 948 PINMUX_IPSR_GPSR(IP5_5, VI2_R6), 949 PINMUX_IPSR_GPSR(IP5_6, DU1_DB5), 950 PINMUX_IPSR_GPSR(IP5_6, VI2_R7), 951 PINMUX_IPSR_GPSR(IP5_7, DU1_DB6), 952 PINMUX_IPSR_MSEL(IP5_7, SCL2_D, SEL_I2C2_3), 953 PINMUX_IPSR_GPSR(IP5_8, DU1_DB7), 954 PINMUX_IPSR_MSEL(IP5_8, SDA2_D, SEL_I2C2_3), 955 PINMUX_IPSR_GPSR(IP5_10_9, DU1_DOTCLKIN), 956 PINMUX_IPSR_GPSR(IP5_10_9, VI2_CLKENB), 957 PINMUX_IPSR_MSEL(IP5_10_9, HSPI_CS1, SEL_HSPI1_0), 958 PINMUX_IPSR_MSEL(IP5_10_9, SCL1_D, SEL_I2C1_3), 959 PINMUX_IPSR_GPSR(IP5_12_11, DU1_DOTCLKOUT), 960 PINMUX_IPSR_GPSR(IP5_12_11, VI2_FIELD), 961 PINMUX_IPSR_MSEL(IP5_12_11, SDA1_D, SEL_I2C1_3), 962 PINMUX_IPSR_GPSR(IP5_14_13, DU1_EXHSYNC_DU1_HSYNC), 963 PINMUX_IPSR_GPSR(IP5_14_13, VI2_HSYNC), 964 PINMUX_IPSR_GPSR(IP5_14_13, VI3_HSYNC), 965 PINMUX_IPSR_GPSR(IP5_16_15, DU1_EXVSYNC_DU1_VSYNC), 966 PINMUX_IPSR_GPSR(IP5_16_15, VI2_VSYNC), 967 PINMUX_IPSR_GPSR(IP5_16_15, VI3_VSYNC), 968 PINMUX_IPSR_GPSR(IP5_20_17, DU1_EXODDF_DU1_ODDF_DISP_CDE), 969 PINMUX_IPSR_GPSR(IP5_20_17, VI2_CLK), 970 PINMUX_IPSR_GPSR(IP5_20_17, TX3_B_IRDA_TX_B), 971 PINMUX_IPSR_GPSR(IP5_20_17, SD3_CD), 972 PINMUX_IPSR_GPSR(IP5_20_17, HSPI_TX1), 973 PINMUX_IPSR_GPSR(IP5_20_17, VI1_CLKENB), 974 PINMUX_IPSR_GPSR(IP5_20_17, VI3_CLKENB), 975 PINMUX_IPSR_GPSR(IP5_20_17, AUDIO_CLKC), 976 PINMUX_IPSR_GPSR(IP5_20_17, TX2_D), 977 PINMUX_IPSR_GPSR(IP5_20_17, SPEEDIN), 978 PINMUX_IPSR_MSEL(IP5_20_17, GPS_SIGN_D, SEL_GPS_3), 979 PINMUX_IPSR_GPSR(IP5_23_21, DU1_DISP), 980 PINMUX_IPSR_GPSR(IP5_23_21, VI2_DATA6_VI2_B6), 981 PINMUX_IPSR_MSEL(IP5_23_21, TCLK0, SEL_TMU0_0), 982 PINMUX_IPSR_GPSR(IP5_23_21, QSTVA_B_QVS_B), 983 PINMUX_IPSR_MSEL(IP5_23_21, HSPI_CLK1, SEL_HSPI1_0), 984 PINMUX_IPSR_MSEL(IP5_23_21, SCK2_D, SEL_SCIF2_3), 985 PINMUX_IPSR_GPSR(IP5_23_21, AUDIO_CLKOUT_B), 986 PINMUX_IPSR_MSEL(IP5_23_21, GPS_MAG_D, SEL_GPS_3), 987 PINMUX_IPSR_GPSR(IP5_27_24, DU1_CDE), 988 PINMUX_IPSR_GPSR(IP5_27_24, VI2_DATA7_VI2_B7), 989 PINMUX_IPSR_MSEL(IP5_27_24, RX3_B_IRDA_RX_B, SEL_SCIF3_1), 990 PINMUX_IPSR_GPSR(IP5_27_24, SD3_WP), 991 PINMUX_IPSR_MSEL(IP5_27_24, HSPI_RX1, SEL_HSPI1_0), 992 PINMUX_IPSR_GPSR(IP5_27_24, VI1_FIELD), 993 PINMUX_IPSR_GPSR(IP5_27_24, VI3_FIELD), 994 PINMUX_IPSR_GPSR(IP5_27_24, AUDIO_CLKOUT), 995 PINMUX_IPSR_MSEL(IP5_27_24, RX2_D, SEL_SCIF2_3), 996 PINMUX_IPSR_MSEL(IP5_27_24, GPS_CLK_C, SEL_GPS_2), 997 PINMUX_IPSR_MSEL(IP5_27_24, GPS_CLK_D, SEL_GPS_3), 998 PINMUX_IPSR_GPSR(IP5_28, AUDIO_CLKA), 999 PINMUX_IPSR_GPSR(IP5_28, CAN_TXCLK), 1000 PINMUX_IPSR_GPSR(IP5_30_29, AUDIO_CLKB), 1001 PINMUX_IPSR_GPSR(IP5_30_29, USB_OVC2), 1002 PINMUX_IPSR_GPSR(IP5_30_29, CAN_DEBUGOUT0), 1003 PINMUX_IPSR_GPSR(IP5_30_29, MOUT0), 1004 1005 PINMUX_IPSR_GPSR(IP6_1_0, SSI_SCK0129), 1006 PINMUX_IPSR_GPSR(IP6_1_0, CAN_DEBUGOUT1), 1007 PINMUX_IPSR_GPSR(IP6_1_0, MOUT1), 1008 PINMUX_IPSR_GPSR(IP6_3_2, SSI_WS0129), 1009 PINMUX_IPSR_GPSR(IP6_3_2, CAN_DEBUGOUT2), 1010 PINMUX_IPSR_GPSR(IP6_3_2, MOUT2), 1011 PINMUX_IPSR_GPSR(IP6_5_4, SSI_SDATA0), 1012 PINMUX_IPSR_GPSR(IP6_5_4, CAN_DEBUGOUT3), 1013 PINMUX_IPSR_GPSR(IP6_5_4, MOUT5), 1014 PINMUX_IPSR_GPSR(IP6_7_6, SSI_SDATA1), 1015 PINMUX_IPSR_GPSR(IP6_7_6, CAN_DEBUGOUT4), 1016 PINMUX_IPSR_GPSR(IP6_7_6, MOUT6), 1017 PINMUX_IPSR_GPSR(IP6_8, SSI_SDATA2), 1018 PINMUX_IPSR_GPSR(IP6_8, CAN_DEBUGOUT5), 1019 PINMUX_IPSR_GPSR(IP6_11_9, SSI_SCK34), 1020 PINMUX_IPSR_GPSR(IP6_11_9, CAN_DEBUGOUT6), 1021 PINMUX_IPSR_GPSR(IP6_11_9, CAN0_TX_B), 1022 PINMUX_IPSR_MSEL(IP6_11_9, IERX, SEL_IE_0), 1023 PINMUX_IPSR_MSEL(IP6_11_9, SSI_SCK9_C, SEL_SSI9_2), 1024 PINMUX_IPSR_GPSR(IP6_14_12, SSI_WS34), 1025 PINMUX_IPSR_GPSR(IP6_14_12, CAN_DEBUGOUT7), 1026 PINMUX_IPSR_MSEL(IP6_14_12, CAN0_RX_B, SEL_CAN0_1), 1027 PINMUX_IPSR_GPSR(IP6_14_12, IETX), 1028 PINMUX_IPSR_MSEL(IP6_14_12, SSI_WS9_C, SEL_SSI9_2), 1029 PINMUX_IPSR_GPSR(IP6_17_15, SSI_SDATA3), 1030 PINMUX_IPSR_GPSR(IP6_17_15, PWM0_C), 1031 PINMUX_IPSR_GPSR(IP6_17_15, CAN_DEBUGOUT8), 1032 PINMUX_IPSR_MSEL(IP6_17_15, CAN_CLK_B, SEL_CANCLK_1), 1033 PINMUX_IPSR_MSEL(IP6_17_15, IECLK, SEL_IE_0), 1034 PINMUX_IPSR_MSEL(IP6_17_15, SCIF_CLK_B, SEL_SCIF_1), 1035 PINMUX_IPSR_MSEL(IP6_17_15, TCLK0_B, SEL_TMU0_1), 1036 PINMUX_IPSR_GPSR(IP6_19_18, SSI_SDATA4), 1037 PINMUX_IPSR_GPSR(IP6_19_18, CAN_DEBUGOUT9), 1038 PINMUX_IPSR_MSEL(IP6_19_18, SSI_SDATA9_C, SEL_SSI9_2), 1039 PINMUX_IPSR_GPSR(IP6_22_20, SSI_SCK5), 1040 PINMUX_IPSR_GPSR(IP6_22_20, ADICLK), 1041 PINMUX_IPSR_GPSR(IP6_22_20, CAN_DEBUGOUT10), 1042 PINMUX_IPSR_MSEL(IP6_22_20, SCK3, SEL_SCIF3_0), 1043 PINMUX_IPSR_MSEL(IP6_22_20, TCLK0_D, SEL_TMU0_3), 1044 PINMUX_IPSR_GPSR(IP6_24_23, SSI_WS5), 1045 PINMUX_IPSR_MSEL(IP6_24_23, ADICS_SAMP, SEL_ADI_0), 1046 PINMUX_IPSR_GPSR(IP6_24_23, CAN_DEBUGOUT11), 1047 PINMUX_IPSR_GPSR(IP6_24_23, TX3_IRDA_TX), 1048 PINMUX_IPSR_GPSR(IP6_26_25, SSI_SDATA5), 1049 PINMUX_IPSR_MSEL(IP6_26_25, ADIDATA, SEL_ADI_0), 1050 PINMUX_IPSR_GPSR(IP6_26_25, CAN_DEBUGOUT12), 1051 PINMUX_IPSR_MSEL(IP6_26_25, RX3_IRDA_RX, SEL_SCIF3_0), 1052 PINMUX_IPSR_GPSR(IP6_30_29, SSI_SCK6), 1053 PINMUX_IPSR_GPSR(IP6_30_29, ADICHS0), 1054 PINMUX_IPSR_GPSR(IP6_30_29, CAN0_TX), 1055 PINMUX_IPSR_MSEL(IP6_30_29, IERX_B, SEL_IE_1), 1056 1057 PINMUX_IPSR_GPSR(IP7_1_0, SSI_WS6), 1058 PINMUX_IPSR_GPSR(IP7_1_0, ADICHS1), 1059 PINMUX_IPSR_MSEL(IP7_1_0, CAN0_RX, SEL_CAN0_0), 1060 PINMUX_IPSR_GPSR(IP7_1_0, IETX_B), 1061 PINMUX_IPSR_GPSR(IP7_3_2, SSI_SDATA6), 1062 PINMUX_IPSR_GPSR(IP7_3_2, ADICHS2), 1063 PINMUX_IPSR_MSEL(IP7_3_2, CAN_CLK, SEL_CANCLK_0), 1064 PINMUX_IPSR_MSEL(IP7_3_2, IECLK_B, SEL_IE_1), 1065 PINMUX_IPSR_MSEL(IP7_6_4, SSI_SCK78, SEL_SSI7_0), 1066 PINMUX_IPSR_GPSR(IP7_6_4, CAN_DEBUGOUT13), 1067 PINMUX_IPSR_MSEL(IP7_6_4, IRQ0_B, SEL_INT0_1), 1068 PINMUX_IPSR_MSEL(IP7_6_4, SSI_SCK9_B, SEL_SSI9_1), 1069 PINMUX_IPSR_MSEL(IP7_6_4, HSPI_CLK1_C, SEL_HSPI1_2), 1070 PINMUX_IPSR_MSEL(IP7_9_7, SSI_WS78, SEL_SSI7_0), 1071 PINMUX_IPSR_GPSR(IP7_9_7, CAN_DEBUGOUT14), 1072 PINMUX_IPSR_MSEL(IP7_9_7, IRQ1_B, SEL_INT1_1), 1073 PINMUX_IPSR_MSEL(IP7_9_7, SSI_WS9_B, SEL_SSI9_1), 1074 PINMUX_IPSR_MSEL(IP7_9_7, HSPI_CS1_C, SEL_HSPI1_2), 1075 PINMUX_IPSR_MSEL(IP7_12_10, SSI_SDATA7, SEL_SSI7_0), 1076 PINMUX_IPSR_GPSR(IP7_12_10, CAN_DEBUGOUT15), 1077 PINMUX_IPSR_MSEL(IP7_12_10, IRQ2_B, SEL_INT2_1), 1078 PINMUX_IPSR_MSEL(IP7_12_10, TCLK1_C, SEL_TMU1_2), 1079 PINMUX_IPSR_GPSR(IP7_12_10, HSPI_TX1_C), 1080 PINMUX_IPSR_MSEL(IP7_14_13, SSI_SDATA8, SEL_SSI8_0), 1081 PINMUX_IPSR_GPSR(IP7_14_13, VSP), 1082 PINMUX_IPSR_MSEL(IP7_14_13, IRQ3_B, SEL_INT3_1), 1083 PINMUX_IPSR_MSEL(IP7_14_13, HSPI_RX1_C, SEL_HSPI1_2), 1084 PINMUX_IPSR_GPSR(IP7_16_15, SD0_CLK), 1085 PINMUX_IPSR_GPSR(IP7_16_15, ATACS01), 1086 PINMUX_IPSR_MSEL(IP7_16_15, SCK1_B, SEL_SCIF1_1), 1087 PINMUX_IPSR_GPSR(IP7_18_17, SD0_CMD), 1088 PINMUX_IPSR_GPSR(IP7_18_17, ATACS11), 1089 PINMUX_IPSR_GPSR(IP7_18_17, TX1_B), 1090 PINMUX_IPSR_GPSR(IP7_18_17, CC5_TDO), 1091 PINMUX_IPSR_GPSR(IP7_20_19, SD0_DAT0), 1092 PINMUX_IPSR_GPSR(IP7_20_19, ATADIR1), 1093 PINMUX_IPSR_MSEL(IP7_20_19, RX1_B, SEL_SCIF1_1), 1094 PINMUX_IPSR_GPSR(IP7_20_19, CC5_TRST), 1095 PINMUX_IPSR_GPSR(IP7_22_21, SD0_DAT1), 1096 PINMUX_IPSR_GPSR(IP7_22_21, ATAG1), 1097 PINMUX_IPSR_MSEL(IP7_22_21, SCK2_B, SEL_SCIF2_1), 1098 PINMUX_IPSR_GPSR(IP7_22_21, CC5_TMS), 1099 PINMUX_IPSR_GPSR(IP7_24_23, SD0_DAT2), 1100 PINMUX_IPSR_GPSR(IP7_24_23, ATARD1), 1101 PINMUX_IPSR_GPSR(IP7_24_23, TX2_B), 1102 PINMUX_IPSR_GPSR(IP7_24_23, CC5_TCK), 1103 PINMUX_IPSR_GPSR(IP7_26_25, SD0_DAT3), 1104 PINMUX_IPSR_GPSR(IP7_26_25, ATAWR1), 1105 PINMUX_IPSR_MSEL(IP7_26_25, RX2_B, SEL_SCIF2_1), 1106 PINMUX_IPSR_GPSR(IP7_26_25, CC5_TDI), 1107 PINMUX_IPSR_GPSR(IP7_28_27, SD0_CD), 1108 PINMUX_IPSR_MSEL(IP7_28_27, DREQ2, SEL_EXBUS2_0), 1109 PINMUX_IPSR_MSEL(IP7_28_27, RTS1_B_TANS_B, SEL_SCIF1_1), 1110 PINMUX_IPSR_GPSR(IP7_30_29, SD0_WP), 1111 PINMUX_IPSR_GPSR(IP7_30_29, DACK2), 1112 PINMUX_IPSR_MSEL(IP7_30_29, CTS1_B, SEL_SCIF1_1), 1113 1114 PINMUX_IPSR_GPSR(IP8_3_0, HSPI_CLK0), 1115 PINMUX_IPSR_MSEL(IP8_3_0, CTS0, SEL_SCIF0_0), 1116 PINMUX_IPSR_GPSR(IP8_3_0, USB_OVC0), 1117 PINMUX_IPSR_GPSR(IP8_3_0, AD_CLK), 1118 PINMUX_IPSR_GPSR(IP8_3_0, CC5_STATE4), 1119 PINMUX_IPSR_GPSR(IP8_3_0, CC5_STATE12), 1120 PINMUX_IPSR_GPSR(IP8_3_0, CC5_STATE20), 1121 PINMUX_IPSR_GPSR(IP8_3_0, CC5_STATE28), 1122 PINMUX_IPSR_GPSR(IP8_3_0, CC5_STATE36), 1123 PINMUX_IPSR_GPSR(IP8_7_4, HSPI_CS0), 1124 PINMUX_IPSR_MSEL(IP8_7_4, RTS0_TANS, SEL_SCIF0_0), 1125 PINMUX_IPSR_GPSR(IP8_7_4, USB_OVC1), 1126 PINMUX_IPSR_GPSR(IP8_7_4, AD_DI), 1127 PINMUX_IPSR_GPSR(IP8_7_4, CC5_STATE5), 1128 PINMUX_IPSR_GPSR(IP8_7_4, CC5_STATE13), 1129 PINMUX_IPSR_GPSR(IP8_7_4, CC5_STATE21), 1130 PINMUX_IPSR_GPSR(IP8_7_4, CC5_STATE29), 1131 PINMUX_IPSR_GPSR(IP8_7_4, CC5_STATE37), 1132 PINMUX_IPSR_GPSR(IP8_11_8, HSPI_TX0), 1133 PINMUX_IPSR_GPSR(IP8_11_8, TX0), 1134 PINMUX_IPSR_GPSR(IP8_11_8, CAN_DEBUG_HW_TRIGGER), 1135 PINMUX_IPSR_GPSR(IP8_11_8, AD_DO), 1136 PINMUX_IPSR_GPSR(IP8_11_8, CC5_STATE6), 1137 PINMUX_IPSR_GPSR(IP8_11_8, CC5_STATE14), 1138 PINMUX_IPSR_GPSR(IP8_11_8, CC5_STATE22), 1139 PINMUX_IPSR_GPSR(IP8_11_8, CC5_STATE30), 1140 PINMUX_IPSR_GPSR(IP8_11_8, CC5_STATE38), 1141 PINMUX_IPSR_GPSR(IP8_15_12, HSPI_RX0), 1142 PINMUX_IPSR_MSEL(IP8_15_12, RX0, SEL_SCIF0_0), 1143 PINMUX_IPSR_GPSR(IP8_15_12, CAN_STEP0), 1144 PINMUX_IPSR_GPSR(IP8_15_12, AD_NCS), 1145 PINMUX_IPSR_GPSR(IP8_15_12, CC5_STATE7), 1146 PINMUX_IPSR_GPSR(IP8_15_12, CC5_STATE15), 1147 PINMUX_IPSR_GPSR(IP8_15_12, CC5_STATE23), 1148 PINMUX_IPSR_GPSR(IP8_15_12, CC5_STATE31), 1149 PINMUX_IPSR_GPSR(IP8_15_12, CC5_STATE39), 1150 PINMUX_IPSR_GPSR(IP8_17_16, FMCLK), 1151 PINMUX_IPSR_GPSR(IP8_17_16, RDS_CLK), 1152 PINMUX_IPSR_GPSR(IP8_17_16, PCMOE), 1153 PINMUX_IPSR_GPSR(IP8_18, BPFCLK), 1154 PINMUX_IPSR_GPSR(IP8_18, PCMWE), 1155 PINMUX_IPSR_GPSR(IP8_19, FMIN), 1156 PINMUX_IPSR_GPSR(IP8_19, RDS_DATA), 1157 PINMUX_IPSR_GPSR(IP8_20, VI0_CLK), 1158 PINMUX_IPSR_GPSR(IP8_20, MMC1_CLK), 1159 PINMUX_IPSR_GPSR(IP8_22_21, VI0_CLKENB), 1160 PINMUX_IPSR_GPSR(IP8_22_21, TX1_C), 1161 PINMUX_IPSR_GPSR(IP8_22_21, HTX1_B), 1162 PINMUX_IPSR_GPSR(IP8_22_21, MT1_SYNC), 1163 PINMUX_IPSR_GPSR(IP8_24_23, VI0_FIELD), 1164 PINMUX_IPSR_MSEL(IP8_24_23, RX1_C, SEL_SCIF1_2), 1165 PINMUX_IPSR_MSEL(IP8_24_23, HRX1_B, SEL_HSCIF1_1), 1166 PINMUX_IPSR_GPSR(IP8_27_25, VI0_HSYNC), 1167 PINMUX_IPSR_MSEL(IP8_27_25, VI0_DATA0_B_VI0_B0_B, SEL_VI0_1), 1168 PINMUX_IPSR_MSEL(IP8_27_25, CTS1_C, SEL_SCIF1_2), 1169 PINMUX_IPSR_GPSR(IP8_27_25, TX4_D), 1170 PINMUX_IPSR_GPSR(IP8_27_25, MMC1_CMD), 1171 PINMUX_IPSR_MSEL(IP8_27_25, HSCK1_B, SEL_HSCIF1_1), 1172 PINMUX_IPSR_GPSR(IP8_30_28, VI0_VSYNC), 1173 PINMUX_IPSR_MSEL(IP8_30_28, VI0_DATA1_B_VI0_B1_B, SEL_VI0_1), 1174 PINMUX_IPSR_MSEL(IP8_30_28, RTS1_C_TANS_C, SEL_SCIF1_2), 1175 PINMUX_IPSR_MSEL(IP8_30_28, RX4_D, SEL_SCIF4_3), 1176 PINMUX_IPSR_MSEL(IP8_30_28, PWMFSW0_C, SEL_PWMFSW_2), 1177 1178 PINMUX_IPSR_MSEL(IP9_1_0, VI0_DATA0_VI0_B0, SEL_VI0_0), 1179 PINMUX_IPSR_MSEL(IP9_1_0, HRTS1_B, SEL_HSCIF1_1), 1180 PINMUX_IPSR_GPSR(IP9_1_0, MT1_VCXO), 1181 PINMUX_IPSR_MSEL(IP9_3_2, VI0_DATA1_VI0_B1, SEL_VI0_0), 1182 PINMUX_IPSR_MSEL(IP9_3_2, HCTS1_B, SEL_HSCIF1_1), 1183 PINMUX_IPSR_GPSR(IP9_3_2, MT1_PWM), 1184 PINMUX_IPSR_GPSR(IP9_4, VI0_DATA2_VI0_B2), 1185 PINMUX_IPSR_GPSR(IP9_4, MMC1_D0), 1186 PINMUX_IPSR_GPSR(IP9_5, VI0_DATA3_VI0_B3), 1187 PINMUX_IPSR_GPSR(IP9_5, MMC1_D1), 1188 PINMUX_IPSR_GPSR(IP9_6, VI0_DATA4_VI0_B4), 1189 PINMUX_IPSR_GPSR(IP9_6, MMC1_D2), 1190 PINMUX_IPSR_GPSR(IP9_7, VI0_DATA5_VI0_B5), 1191 PINMUX_IPSR_GPSR(IP9_7, MMC1_D3), 1192 PINMUX_IPSR_GPSR(IP9_9_8, VI0_DATA6_VI0_B6), 1193 PINMUX_IPSR_GPSR(IP9_9_8, MMC1_D4), 1194 PINMUX_IPSR_GPSR(IP9_9_8, ARM_TRACEDATA_0), 1195 PINMUX_IPSR_GPSR(IP9_11_10, VI0_DATA7_VI0_B7), 1196 PINMUX_IPSR_GPSR(IP9_11_10, MMC1_D5), 1197 PINMUX_IPSR_GPSR(IP9_11_10, ARM_TRACEDATA_1), 1198 PINMUX_IPSR_GPSR(IP9_13_12, VI0_G0), 1199 PINMUX_IPSR_MSEL(IP9_13_12, SSI_SCK78_C, SEL_SSI7_2), 1200 PINMUX_IPSR_MSEL(IP9_13_12, IRQ0, SEL_INT0_0), 1201 PINMUX_IPSR_GPSR(IP9_13_12, ARM_TRACEDATA_2), 1202 PINMUX_IPSR_GPSR(IP9_15_14, VI0_G1), 1203 PINMUX_IPSR_MSEL(IP9_15_14, SSI_WS78_C, SEL_SSI7_2), 1204 PINMUX_IPSR_MSEL(IP9_15_14, IRQ1, SEL_INT1_0), 1205 PINMUX_IPSR_GPSR(IP9_15_14, ARM_TRACEDATA_3), 1206 PINMUX_IPSR_GPSR(IP9_18_16, VI0_G2), 1207 PINMUX_IPSR_GPSR(IP9_18_16, ETH_TXD1), 1208 PINMUX_IPSR_GPSR(IP9_18_16, MMC1_D6), 1209 PINMUX_IPSR_GPSR(IP9_18_16, ARM_TRACEDATA_4), 1210 PINMUX_IPSR_GPSR(IP9_18_16, TS_SPSYNC0), 1211 PINMUX_IPSR_GPSR(IP9_21_19, VI0_G3), 1212 PINMUX_IPSR_GPSR(IP9_21_19, ETH_CRS_DV), 1213 PINMUX_IPSR_GPSR(IP9_21_19, MMC1_D7), 1214 PINMUX_IPSR_GPSR(IP9_21_19, ARM_TRACEDATA_5), 1215 PINMUX_IPSR_GPSR(IP9_21_19, TS_SDAT0), 1216 PINMUX_IPSR_GPSR(IP9_23_22, VI0_G4), 1217 PINMUX_IPSR_GPSR(IP9_23_22, ETH_TX_EN), 1218 PINMUX_IPSR_MSEL(IP9_23_22, SD2_DAT0_B, SEL_SD2_1), 1219 PINMUX_IPSR_GPSR(IP9_23_22, ARM_TRACEDATA_6), 1220 PINMUX_IPSR_GPSR(IP9_25_24, VI0_G5), 1221 PINMUX_IPSR_GPSR(IP9_25_24, ETH_RX_ER), 1222 PINMUX_IPSR_MSEL(IP9_25_24, SD2_DAT1_B, SEL_SD2_1), 1223 PINMUX_IPSR_GPSR(IP9_25_24, ARM_TRACEDATA_7), 1224 PINMUX_IPSR_GPSR(IP9_27_26, VI0_G6), 1225 PINMUX_IPSR_GPSR(IP9_27_26, ETH_RXD0), 1226 PINMUX_IPSR_MSEL(IP9_27_26, SD2_DAT2_B, SEL_SD2_1), 1227 PINMUX_IPSR_GPSR(IP9_27_26, ARM_TRACEDATA_8), 1228 PINMUX_IPSR_GPSR(IP9_29_28, VI0_G7), 1229 PINMUX_IPSR_GPSR(IP9_29_28, ETH_RXD1), 1230 PINMUX_IPSR_MSEL(IP9_29_28, SD2_DAT3_B, SEL_SD2_1), 1231 PINMUX_IPSR_GPSR(IP9_29_28, ARM_TRACEDATA_9), 1232 1233 PINMUX_IPSR_GPSR(IP10_2_0, VI0_R0), 1234 PINMUX_IPSR_MSEL(IP10_2_0, SSI_SDATA7_C, SEL_SSI7_2), 1235 PINMUX_IPSR_MSEL(IP10_2_0, SCK1_C, SEL_SCIF1_2), 1236 PINMUX_IPSR_MSEL(IP10_2_0, DREQ1_B, SEL_EXBUS1_0), 1237 PINMUX_IPSR_GPSR(IP10_2_0, ARM_TRACEDATA_10), 1238 PINMUX_IPSR_MSEL(IP10_2_0, DREQ0_C, SEL_EXBUS0_2), 1239 PINMUX_IPSR_GPSR(IP10_5_3, VI0_R1), 1240 PINMUX_IPSR_MSEL(IP10_5_3, SSI_SDATA8_C, SEL_SSI8_2), 1241 PINMUX_IPSR_GPSR(IP10_5_3, DACK1_B), 1242 PINMUX_IPSR_GPSR(IP10_5_3, ARM_TRACEDATA_11), 1243 PINMUX_IPSR_GPSR(IP10_5_3, DACK0_C), 1244 PINMUX_IPSR_GPSR(IP10_5_3, DRACK0_C), 1245 PINMUX_IPSR_GPSR(IP10_8_6, VI0_R2), 1246 PINMUX_IPSR_GPSR(IP10_8_6, ETH_LINK), 1247 PINMUX_IPSR_GPSR(IP10_8_6, SD2_CLK_B), 1248 PINMUX_IPSR_MSEL(IP10_8_6, IRQ2, SEL_INT2_0), 1249 PINMUX_IPSR_GPSR(IP10_8_6, ARM_TRACEDATA_12), 1250 PINMUX_IPSR_GPSR(IP10_11_9, VI0_R3), 1251 PINMUX_IPSR_GPSR(IP10_11_9, ETH_MAGIC), 1252 PINMUX_IPSR_MSEL(IP10_11_9, SD2_CMD_B, SEL_SD2_1), 1253 PINMUX_IPSR_MSEL(IP10_11_9, IRQ3, SEL_INT3_0), 1254 PINMUX_IPSR_GPSR(IP10_11_9, ARM_TRACEDATA_13), 1255 PINMUX_IPSR_GPSR(IP10_14_12, VI0_R4), 1256 PINMUX_IPSR_GPSR(IP10_14_12, ETH_REFCLK), 1257 PINMUX_IPSR_MSEL(IP10_14_12, SD2_CD_B, SEL_SD2_1), 1258 PINMUX_IPSR_MSEL(IP10_14_12, HSPI_CLK1_B, SEL_HSPI1_1), 1259 PINMUX_IPSR_GPSR(IP10_14_12, ARM_TRACEDATA_14), 1260 PINMUX_IPSR_GPSR(IP10_14_12, MT1_CLK), 1261 PINMUX_IPSR_GPSR(IP10_14_12, TS_SCK0), 1262 PINMUX_IPSR_GPSR(IP10_17_15, VI0_R5), 1263 PINMUX_IPSR_GPSR(IP10_17_15, ETH_TXD0), 1264 PINMUX_IPSR_MSEL(IP10_17_15, SD2_WP_B, SEL_SD2_1), 1265 PINMUX_IPSR_MSEL(IP10_17_15, HSPI_CS1_B, SEL_HSPI1_1), 1266 PINMUX_IPSR_GPSR(IP10_17_15, ARM_TRACEDATA_15), 1267 PINMUX_IPSR_GPSR(IP10_17_15, MT1_D), 1268 PINMUX_IPSR_GPSR(IP10_17_15, TS_SDEN0), 1269 PINMUX_IPSR_GPSR(IP10_20_18, VI0_R6), 1270 PINMUX_IPSR_GPSR(IP10_20_18, ETH_MDC), 1271 PINMUX_IPSR_MSEL(IP10_20_18, DREQ2_C, SEL_EXBUS2_2), 1272 PINMUX_IPSR_GPSR(IP10_20_18, HSPI_TX1_B), 1273 PINMUX_IPSR_GPSR(IP10_20_18, TRACECLK), 1274 PINMUX_IPSR_GPSR(IP10_20_18, MT1_BEN), 1275 PINMUX_IPSR_MSEL(IP10_20_18, PWMFSW0_D, SEL_PWMFSW_3), 1276 PINMUX_IPSR_GPSR(IP10_23_21, VI0_R7), 1277 PINMUX_IPSR_GPSR(IP10_23_21, ETH_MDIO), 1278 PINMUX_IPSR_GPSR(IP10_23_21, DACK2_C), 1279 PINMUX_IPSR_MSEL(IP10_23_21, HSPI_RX1_B, SEL_HSPI1_1), 1280 PINMUX_IPSR_MSEL(IP10_23_21, SCIF_CLK_D, SEL_SCIF_3), 1281 PINMUX_IPSR_GPSR(IP10_23_21, TRACECTL), 1282 PINMUX_IPSR_GPSR(IP10_23_21, MT1_PEN), 1283 PINMUX_IPSR_GPSR(IP10_25_24, VI1_CLK), 1284 PINMUX_IPSR_MSEL(IP10_25_24, SIM_D, SEL_SIM_0), 1285 PINMUX_IPSR_MSEL(IP10_25_24, SDA3, SEL_I2C3_0), 1286 PINMUX_IPSR_GPSR(IP10_28_26, VI1_HSYNC), 1287 PINMUX_IPSR_GPSR(IP10_28_26, VI3_CLK), 1288 PINMUX_IPSR_GPSR(IP10_28_26, SSI_SCK4), 1289 PINMUX_IPSR_MSEL(IP10_28_26, GPS_SIGN_C, SEL_GPS_2), 1290 PINMUX_IPSR_MSEL(IP10_28_26, PWMFSW0_E, SEL_PWMFSW_4), 1291 PINMUX_IPSR_GPSR(IP10_31_29, VI1_VSYNC), 1292 PINMUX_IPSR_GPSR(IP10_31_29, AUDIO_CLKOUT_C), 1293 PINMUX_IPSR_GPSR(IP10_31_29, SSI_WS4), 1294 PINMUX_IPSR_GPSR(IP10_31_29, SIM_CLK), 1295 PINMUX_IPSR_MSEL(IP10_31_29, GPS_MAG_C, SEL_GPS_2), 1296 PINMUX_IPSR_GPSR(IP10_31_29, SPV_TRST), 1297 PINMUX_IPSR_MSEL(IP10_31_29, SCL3, SEL_I2C3_0), 1298 1299 PINMUX_IPSR_GPSR(IP11_2_0, VI1_DATA0_VI1_B0), 1300 PINMUX_IPSR_MSEL(IP11_2_0, SD2_DAT0, SEL_SD2_0), 1301 PINMUX_IPSR_GPSR(IP11_2_0, SIM_RST), 1302 PINMUX_IPSR_GPSR(IP11_2_0, SPV_TCK), 1303 PINMUX_IPSR_GPSR(IP11_2_0, ADICLK_B), 1304 PINMUX_IPSR_GPSR(IP11_5_3, VI1_DATA1_VI1_B1), 1305 PINMUX_IPSR_MSEL(IP11_5_3, SD2_DAT1, SEL_SD2_0), 1306 PINMUX_IPSR_GPSR(IP11_5_3, MT0_CLK), 1307 PINMUX_IPSR_GPSR(IP11_5_3, SPV_TMS), 1308 PINMUX_IPSR_MSEL(IP11_5_3, ADICS_B_SAMP_B, SEL_ADI_1), 1309 PINMUX_IPSR_GPSR(IP11_8_6, VI1_DATA2_VI1_B2), 1310 PINMUX_IPSR_MSEL(IP11_8_6, SD2_DAT2, SEL_SD2_0), 1311 PINMUX_IPSR_GPSR(IP11_8_6, MT0_D), 1312 PINMUX_IPSR_GPSR(IP11_8_6, SPVTDI), 1313 PINMUX_IPSR_MSEL(IP11_8_6, ADIDATA_B, SEL_ADI_1), 1314 PINMUX_IPSR_GPSR(IP11_11_9, VI1_DATA3_VI1_B3), 1315 PINMUX_IPSR_MSEL(IP11_11_9, SD2_DAT3, SEL_SD2_0), 1316 PINMUX_IPSR_GPSR(IP11_11_9, MT0_BEN), 1317 PINMUX_IPSR_GPSR(IP11_11_9, SPV_TDO), 1318 PINMUX_IPSR_GPSR(IP11_11_9, ADICHS0_B), 1319 PINMUX_IPSR_GPSR(IP11_14_12, VI1_DATA4_VI1_B4), 1320 PINMUX_IPSR_GPSR(IP11_14_12, SD2_CLK), 1321 PINMUX_IPSR_GPSR(IP11_14_12, MT0_PEN), 1322 PINMUX_IPSR_GPSR(IP11_14_12, SPA_TRST), 1323 PINMUX_IPSR_MSEL(IP11_14_12, HSPI_CLK1_D, SEL_HSPI1_3), 1324 PINMUX_IPSR_GPSR(IP11_14_12, ADICHS1_B), 1325 PINMUX_IPSR_GPSR(IP11_17_15, VI1_DATA5_VI1_B5), 1326 PINMUX_IPSR_MSEL(IP11_17_15, SD2_CMD, SEL_SD2_0), 1327 PINMUX_IPSR_GPSR(IP11_17_15, MT0_SYNC), 1328 PINMUX_IPSR_GPSR(IP11_17_15, SPA_TCK), 1329 PINMUX_IPSR_MSEL(IP11_17_15, HSPI_CS1_D, SEL_HSPI1_3), 1330 PINMUX_IPSR_GPSR(IP11_17_15, ADICHS2_B), 1331 PINMUX_IPSR_GPSR(IP11_20_18, VI1_DATA6_VI1_B6), 1332 PINMUX_IPSR_MSEL(IP11_20_18, SD2_CD, SEL_SD2_0), 1333 PINMUX_IPSR_GPSR(IP11_20_18, MT0_VCXO), 1334 PINMUX_IPSR_GPSR(IP11_20_18, SPA_TMS), 1335 PINMUX_IPSR_GPSR(IP11_20_18, HSPI_TX1_D), 1336 PINMUX_IPSR_GPSR(IP11_23_21, VI1_DATA7_VI1_B7), 1337 PINMUX_IPSR_MSEL(IP11_23_21, SD2_WP, SEL_SD2_0), 1338 PINMUX_IPSR_GPSR(IP11_23_21, MT0_PWM), 1339 PINMUX_IPSR_GPSR(IP11_23_21, SPA_TDI), 1340 PINMUX_IPSR_MSEL(IP11_23_21, HSPI_RX1_D, SEL_HSPI1_3), 1341 PINMUX_IPSR_GPSR(IP11_26_24, VI1_G0), 1342 PINMUX_IPSR_GPSR(IP11_26_24, VI3_DATA0), 1343 PINMUX_IPSR_GPSR(IP11_26_24, TS_SCK1), 1344 PINMUX_IPSR_MSEL(IP11_26_24, DREQ2_B, SEL_EXBUS2_1), 1345 PINMUX_IPSR_GPSR(IP11_26_24, TX2), 1346 PINMUX_IPSR_GPSR(IP11_26_24, SPA_TDO), 1347 PINMUX_IPSR_MSEL(IP11_26_24, HCTS0_B, SEL_HSCIF0_1), 1348 PINMUX_IPSR_GPSR(IP11_29_27, VI1_G1), 1349 PINMUX_IPSR_GPSR(IP11_29_27, VI3_DATA1), 1350 PINMUX_IPSR_GPSR(IP11_29_27, SSI_SCK1), 1351 PINMUX_IPSR_GPSR(IP11_29_27, TS_SDEN1), 1352 PINMUX_IPSR_GPSR(IP11_29_27, DACK2_B), 1353 PINMUX_IPSR_MSEL(IP11_29_27, RX2, SEL_SCIF2_0), 1354 PINMUX_IPSR_MSEL(IP11_29_27, HRTS0_B, SEL_HSCIF0_1), 1355 1356 PINMUX_IPSR_GPSR(IP12_2_0, VI1_G2), 1357 PINMUX_IPSR_GPSR(IP12_2_0, VI3_DATA2), 1358 PINMUX_IPSR_GPSR(IP12_2_0, SSI_WS1), 1359 PINMUX_IPSR_GPSR(IP12_2_0, TS_SPSYNC1), 1360 PINMUX_IPSR_MSEL(IP12_2_0, SCK2, SEL_SCIF2_0), 1361 PINMUX_IPSR_MSEL(IP12_2_0, HSCK0_B, SEL_HSCIF0_1), 1362 PINMUX_IPSR_GPSR(IP12_5_3, VI1_G3), 1363 PINMUX_IPSR_GPSR(IP12_5_3, VI3_DATA3), 1364 PINMUX_IPSR_GPSR(IP12_5_3, SSI_SCK2), 1365 PINMUX_IPSR_GPSR(IP12_5_3, TS_SDAT1), 1366 PINMUX_IPSR_MSEL(IP12_5_3, SCL1_C, SEL_I2C1_2), 1367 PINMUX_IPSR_GPSR(IP12_5_3, HTX0_B), 1368 PINMUX_IPSR_GPSR(IP12_8_6, VI1_G4), 1369 PINMUX_IPSR_GPSR(IP12_8_6, VI3_DATA4), 1370 PINMUX_IPSR_GPSR(IP12_8_6, SSI_WS2), 1371 PINMUX_IPSR_MSEL(IP12_8_6, SDA1_C, SEL_I2C1_2), 1372 PINMUX_IPSR_GPSR(IP12_8_6, SIM_RST_B), 1373 PINMUX_IPSR_MSEL(IP12_8_6, HRX0_B, SEL_HSCIF0_1), 1374 PINMUX_IPSR_GPSR(IP12_11_9, VI1_G5), 1375 PINMUX_IPSR_GPSR(IP12_11_9, VI3_DATA5), 1376 PINMUX_IPSR_MSEL(IP12_11_9, GPS_CLK, SEL_GPS_0), 1377 PINMUX_IPSR_GPSR(IP12_11_9, FSE), 1378 PINMUX_IPSR_GPSR(IP12_11_9, TX4_B), 1379 PINMUX_IPSR_MSEL(IP12_11_9, SIM_D_B, SEL_SIM_1), 1380 PINMUX_IPSR_GPSR(IP12_14_12, VI1_G6), 1381 PINMUX_IPSR_GPSR(IP12_14_12, VI3_DATA6), 1382 PINMUX_IPSR_MSEL(IP12_14_12, GPS_SIGN, SEL_GPS_0), 1383 PINMUX_IPSR_GPSR(IP12_14_12, FRB), 1384 PINMUX_IPSR_MSEL(IP12_14_12, RX4_B, SEL_SCIF4_1), 1385 PINMUX_IPSR_GPSR(IP12_14_12, SIM_CLK_B), 1386 PINMUX_IPSR_GPSR(IP12_17_15, VI1_G7), 1387 PINMUX_IPSR_GPSR(IP12_17_15, VI3_DATA7), 1388 PINMUX_IPSR_MSEL(IP12_17_15, GPS_MAG, SEL_GPS_0), 1389 PINMUX_IPSR_GPSR(IP12_17_15, FCE), 1390 PINMUX_IPSR_MSEL(IP12_17_15, SCK4_B, SEL_SCIF4_1), 1391 }; 1392 1393 static const struct sh_pfc_pin pinmux_pins[] = { 1394 PINMUX_GPIO_GP_ALL(), 1395 }; 1396 1397 /* - DU0 -------------------------------------------------------------------- */ 1398 static const unsigned int du0_rgb666_pins[] = { 1399 /* R[7:2], G[7:2], B[7:2] */ 1400 RCAR_GP_PIN(5, 28), RCAR_GP_PIN(5, 27), RCAR_GP_PIN(5, 26), 1401 RCAR_GP_PIN(5, 25), RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23), 1402 RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 0), 1403 RCAR_GP_PIN(5, 31), RCAR_GP_PIN(5, 30), RCAR_GP_PIN(5, 29), 1404 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6), 1405 RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 3), 1406 }; 1407 static const unsigned int du0_rgb666_mux[] = { 1408 DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK, 1409 DU0_DR3_MARK, DU0_DR2_MARK, 1410 DU0_DG7_MARK, DU0_DG6_MARK, DU0_DG5_MARK, DU0_DG4_MARK, 1411 DU0_DG3_MARK, DU0_DG2_MARK, 1412 DU0_DB7_MARK, DU0_DB6_MARK, DU0_DB5_MARK, DU0_DB4_MARK, 1413 DU0_DB3_MARK, DU0_DB2_MARK, 1414 }; 1415 static const unsigned int du0_rgb888_pins[] = { 1416 /* R[7:0], G[7:0], B[7:0] */ 1417 RCAR_GP_PIN(5, 28), RCAR_GP_PIN(5, 27), RCAR_GP_PIN(5, 26), 1418 RCAR_GP_PIN(5, 25), RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23), 1419 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 23), RCAR_GP_PIN(6, 2), 1420 RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 0), RCAR_GP_PIN(5, 31), 1421 RCAR_GP_PIN(5, 30), RCAR_GP_PIN(5, 29), RCAR_GP_PIN(0, 26), 1422 RCAR_GP_PIN(0, 25), RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 7), 1423 RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 4), 1424 RCAR_GP_PIN(6, 3), RCAR_GP_PIN(0, 28), RCAR_GP_PIN(0, 27), 1425 }; 1426 static const unsigned int du0_rgb888_mux[] = { 1427 DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK, 1428 DU0_DR3_MARK, DU0_DR2_MARK, DU0_DR1_MARK, DU0_DR0_MARK, 1429 DU0_DG7_MARK, DU0_DG6_MARK, DU0_DG5_MARK, DU0_DG4_MARK, 1430 DU0_DG3_MARK, DU0_DG2_MARK, DU0_DG1_MARK, DU0_DG0_MARK, 1431 DU0_DB7_MARK, DU0_DB6_MARK, DU0_DB5_MARK, DU0_DB4_MARK, 1432 DU0_DB3_MARK, DU0_DB2_MARK, DU0_DB1_MARK, DU0_DB0_MARK, 1433 }; 1434 static const unsigned int du0_clk_in_pins[] = { 1435 /* CLKIN */ 1436 RCAR_GP_PIN(0, 29), 1437 }; 1438 static const unsigned int du0_clk_in_mux[] = { 1439 DU0_DOTCLKIN_MARK, 1440 }; 1441 static const unsigned int du0_clk_out_0_pins[] = { 1442 /* CLKOUT */ 1443 RCAR_GP_PIN(5, 20), 1444 }; 1445 static const unsigned int du0_clk_out_0_mux[] = { 1446 DU0_DOTCLKOUT0_MARK, 1447 }; 1448 static const unsigned int du0_clk_out_1_pins[] = { 1449 /* CLKOUT */ 1450 RCAR_GP_PIN(0, 30), 1451 }; 1452 static const unsigned int du0_clk_out_1_mux[] = { 1453 DU0_DOTCLKOUT1_MARK, 1454 }; 1455 static const unsigned int du0_sync_0_pins[] = { 1456 /* VSYNC, HSYNC, DISP */ 1457 RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 21), RCAR_GP_PIN(0, 31), 1458 }; 1459 static const unsigned int du0_sync_0_mux[] = { 1460 DU0_EXHSYNC_DU0_HSYNC_MARK, DU0_EXVSYNC_DU0_VSYNC_MARK, 1461 DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK 1462 }; 1463 static const unsigned int du0_sync_1_pins[] = { 1464 /* VSYNC, HSYNC, DISP */ 1465 RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 21), RCAR_GP_PIN(1, 0), 1466 }; 1467 static const unsigned int du0_sync_1_mux[] = { 1468 DU0_EXHSYNC_DU0_HSYNC_MARK, DU0_EXVSYNC_DU0_VSYNC_MARK, 1469 DU0_DISP_MARK 1470 }; 1471 static const unsigned int du0_oddf_pins[] = { 1472 /* ODDF */ 1473 RCAR_GP_PIN(0, 31), 1474 }; 1475 static const unsigned int du0_oddf_mux[] = { 1476 DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK 1477 }; 1478 static const unsigned int du0_cde_pins[] = { 1479 /* CDE */ 1480 RCAR_GP_PIN(1, 1), 1481 }; 1482 static const unsigned int du0_cde_mux[] = { 1483 DU0_CDE_MARK 1484 }; 1485 /* - DU1 -------------------------------------------------------------------- */ 1486 static const unsigned int du1_rgb666_pins[] = { 1487 /* R[7:2], G[7:2], B[7:2] */ 1488 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 7), 1489 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 4), 1490 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 15), 1491 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 12), 1492 RCAR_GP_PIN(1, 25), RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 23), 1493 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 20), 1494 }; 1495 static const unsigned int du1_rgb666_mux[] = { 1496 DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK, 1497 DU1_DR3_MARK, DU1_DR2_MARK, 1498 DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK, 1499 DU1_DG3_MARK, DU1_DG2_MARK, 1500 DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK, 1501 DU1_DB3_MARK, DU1_DB2_MARK, 1502 }; 1503 static const unsigned int du1_rgb888_pins[] = { 1504 /* R[7:0], G[7:0], B[7:0] */ 1505 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 7), 1506 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 4), 1507 RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 17), 1508 RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), 1509 RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 11), 1510 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 25), RCAR_GP_PIN(1, 24), 1511 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21), 1512 RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18), 1513 }; 1514 static const unsigned int du1_rgb888_mux[] = { 1515 DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK, 1516 DU1_DR3_MARK, DU1_DR2_MARK, DU1_DR1_MARK, DU1_DR0_MARK, 1517 DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK, 1518 DU1_DG3_MARK, DU1_DG2_MARK, DU1_DG1_MARK, DU1_DG0_MARK, 1519 DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK, 1520 DU1_DB3_MARK, DU1_DB2_MARK, DU1_DB1_MARK, DU1_DB0_MARK, 1521 }; 1522 static const unsigned int du1_clk_in_pins[] = { 1523 /* CLKIN */ 1524 RCAR_GP_PIN(1, 26), 1525 }; 1526 static const unsigned int du1_clk_in_mux[] = { 1527 DU1_DOTCLKIN_MARK, 1528 }; 1529 static const unsigned int du1_clk_out_pins[] = { 1530 /* CLKOUT */ 1531 RCAR_GP_PIN(1, 27), 1532 }; 1533 static const unsigned int du1_clk_out_mux[] = { 1534 DU1_DOTCLKOUT_MARK, 1535 }; 1536 static const unsigned int du1_sync_0_pins[] = { 1537 /* VSYNC, HSYNC, DISP */ 1538 RCAR_GP_PIN(1, 29), RCAR_GP_PIN(1, 28), RCAR_GP_PIN(1, 30), 1539 }; 1540 static const unsigned int du1_sync_0_mux[] = { 1541 DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK, 1542 DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK 1543 }; 1544 static const unsigned int du1_sync_1_pins[] = { 1545 /* VSYNC, HSYNC, DISP */ 1546 RCAR_GP_PIN(1, 29), RCAR_GP_PIN(1, 28), RCAR_GP_PIN(1, 31), 1547 }; 1548 static const unsigned int du1_sync_1_mux[] = { 1549 DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK, 1550 DU1_DISP_MARK 1551 }; 1552 static const unsigned int du1_oddf_pins[] = { 1553 /* ODDF */ 1554 RCAR_GP_PIN(1, 30), 1555 }; 1556 static const unsigned int du1_oddf_mux[] = { 1557 DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK 1558 }; 1559 static const unsigned int du1_cde_pins[] = { 1560 /* CDE */ 1561 RCAR_GP_PIN(2, 0), 1562 }; 1563 static const unsigned int du1_cde_mux[] = { 1564 DU1_CDE_MARK 1565 }; 1566 /* - Ether ------------------------------------------------------------------ */ 1567 static const unsigned int ether_rmii_pins[] = { 1568 /* 1569 * ETH_TXD0, ETH_TXD1, ETH_TX_EN, ETH_REFCLK, 1570 * ETH_RXD0, ETH_RXD1, ETH_CRS_DV, ETH_RX_ER, 1571 * ETH_MDIO, ETH_MDC 1572 */ 1573 RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 18), 1574 RCAR_GP_PIN(2, 26), 1575 RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 17), 1576 RCAR_GP_PIN(2, 19), 1577 RCAR_GP_PIN(2, 29), RCAR_GP_PIN(2, 28), 1578 }; 1579 static const unsigned int ether_rmii_mux[] = { 1580 ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REFCLK_MARK, 1581 ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_CRS_DV_MARK, ETH_RX_ER_MARK, 1582 ETH_MDIO_MARK, ETH_MDC_MARK, 1583 }; 1584 static const unsigned int ether_link_pins[] = { 1585 /* ETH_LINK */ 1586 RCAR_GP_PIN(2, 24), 1587 }; 1588 static const unsigned int ether_link_mux[] = { 1589 ETH_LINK_MARK, 1590 }; 1591 static const unsigned int ether_magic_pins[] = { 1592 /* ETH_MAGIC */ 1593 RCAR_GP_PIN(2, 25), 1594 }; 1595 static const unsigned int ether_magic_mux[] = { 1596 ETH_MAGIC_MARK, 1597 }; 1598 /* - HSCIF0 ----------------------------------------------------------------- */ 1599 static const unsigned int hscif0_data_pins[] = { 1600 /* TX, RX */ 1601 RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21) 1602 }; 1603 static const unsigned int hscif0_data_mux[] = { 1604 HTX0_MARK, HRX0_MARK 1605 }; 1606 static const unsigned int hscif0_data_b_pins[] = { 1607 /* TX, RX */ 1608 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13) 1609 }; 1610 static const unsigned int hscif0_data_b_mux[] = { 1611 HTX0_B_MARK, HRX0_B_MARK 1612 }; 1613 static const unsigned int hscif0_ctrl_pins[] = { 1614 /* CTS, RTS */ 1615 RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 19) 1616 }; 1617 static const unsigned int hscif0_ctrl_mux[] = { 1618 HCTS0_MARK, HRTS0_MARK 1619 }; 1620 static const unsigned int hscif0_ctrl_b_pins[] = { 1621 /* CTS, RTS */ 1622 RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10) 1623 }; 1624 static const unsigned int hscif0_ctrl_b_mux[] = { 1625 HCTS0_B_MARK, HRTS0_B_MARK 1626 }; 1627 static const unsigned int hscif0_clk_pins[] = { 1628 /* SCK */ 1629 RCAR_GP_PIN(4, 17) 1630 }; 1631 static const unsigned int hscif0_clk_mux[] = { 1632 HSCK0_MARK 1633 }; 1634 static const unsigned int hscif0_clk_b_pins[] = { 1635 /* SCK */ 1636 RCAR_GP_PIN(3, 11) 1637 }; 1638 static const unsigned int hscif0_clk_b_mux[] = { 1639 HSCK0_B_MARK 1640 }; 1641 /* - HSCIF1 ----------------------------------------------------------------- */ 1642 static const unsigned int hscif1_data_pins[] = { 1643 /* TX, RX */ 1644 RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20) 1645 }; 1646 static const unsigned int hscif1_data_mux[] = { 1647 HTX1_MARK, HRX1_MARK 1648 }; 1649 static const unsigned int hscif1_data_b_pins[] = { 1650 /* TX, RX */ 1651 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3) 1652 }; 1653 static const unsigned int hscif1_data_b_mux[] = { 1654 HTX1_B_MARK, HRX1_B_MARK 1655 }; 1656 static const unsigned int hscif1_ctrl_pins[] = { 1657 /* CTS, RTS */ 1658 RCAR_GP_PIN(0, 21), RCAR_GP_PIN(0, 22) 1659 }; 1660 static const unsigned int hscif1_ctrl_mux[] = { 1661 HCTS1_MARK, HRTS1_MARK 1662 }; 1663 static const unsigned int hscif1_ctrl_b_pins[] = { 1664 /* CTS, RTS */ 1665 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 6) 1666 }; 1667 static const unsigned int hscif1_ctrl_b_mux[] = { 1668 HCTS1_B_MARK, HRTS1_B_MARK 1669 }; 1670 static const unsigned int hscif1_clk_pins[] = { 1671 /* SCK */ 1672 RCAR_GP_PIN(0, 18) 1673 }; 1674 static const unsigned int hscif1_clk_mux[] = { 1675 HSCK1_MARK 1676 }; 1677 static const unsigned int hscif1_clk_b_pins[] = { 1678 /* SCK */ 1679 RCAR_GP_PIN(2, 4) 1680 }; 1681 static const unsigned int hscif1_clk_b_mux[] = { 1682 HSCK1_B_MARK 1683 }; 1684 /* - HSPI0 ------------------------------------------------------------------ */ 1685 static const unsigned int hspi0_pins[] = { 1686 /* CLK, CS, RX, TX */ 1687 RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 25), 1688 RCAR_GP_PIN(4, 24), 1689 }; 1690 static const unsigned int hspi0_mux[] = { 1691 HSPI_CLK0_MARK, HSPI_CS0_MARK, HSPI_RX0_MARK, HSPI_TX0_MARK, 1692 }; 1693 /* - HSPI1 ------------------------------------------------------------------ */ 1694 static const unsigned int hspi1_pins[] = { 1695 /* CLK, CS, RX, TX */ 1696 RCAR_GP_PIN(1, 31), RCAR_GP_PIN(1, 26), RCAR_GP_PIN(2, 0), 1697 RCAR_GP_PIN(1, 30), 1698 }; 1699 static const unsigned int hspi1_mux[] = { 1700 HSPI_CLK1_MARK, HSPI_CS1_MARK, HSPI_RX1_MARK, HSPI_TX1_MARK, 1701 }; 1702 static const unsigned int hspi1_b_pins[] = { 1703 /* CLK, CS, RX, TX */ 1704 RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 29), 1705 RCAR_GP_PIN(2, 28), 1706 }; 1707 static const unsigned int hspi1_b_mux[] = { 1708 HSPI_CLK1_B_MARK, HSPI_CS1_B_MARK, HSPI_RX1_B_MARK, HSPI_TX1_B_MARK, 1709 }; 1710 static const unsigned int hspi1_c_pins[] = { 1711 /* CLK, CS, RX, TX */ 1712 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 16), 1713 RCAR_GP_PIN(4, 15), 1714 }; 1715 static const unsigned int hspi1_c_mux[] = { 1716 HSPI_CLK1_C_MARK, HSPI_CS1_C_MARK, HSPI_RX1_C_MARK, HSPI_TX1_C_MARK, 1717 }; 1718 static const unsigned int hspi1_d_pins[] = { 1719 /* CLK, CS, RX, TX */ 1720 RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 8), 1721 RCAR_GP_PIN(3, 7), 1722 }; 1723 static const unsigned int hspi1_d_mux[] = { 1724 HSPI_CLK1_D_MARK, HSPI_CS1_D_MARK, HSPI_RX1_D_MARK, HSPI_TX1_D_MARK, 1725 }; 1726 /* - HSPI2 ------------------------------------------------------------------ */ 1727 static const unsigned int hspi2_pins[] = { 1728 /* CLK, CS, RX, TX */ 1729 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), 1730 RCAR_GP_PIN(0, 14), 1731 }; 1732 static const unsigned int hspi2_mux[] = { 1733 HSPI_CLK2_MARK, HSPI_CS2_MARK, HSPI_RX2_MARK, HSPI_TX2_MARK, 1734 }; 1735 static const unsigned int hspi2_b_pins[] = { 1736 /* CLK, CS, RX, TX */ 1737 RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 8), 1738 RCAR_GP_PIN(0, 6), 1739 }; 1740 static const unsigned int hspi2_b_mux[] = { 1741 HSPI_CLK2_B_MARK, HSPI_CS2_B_MARK, HSPI_RX2_B_MARK, HSPI_TX2_B_MARK, 1742 }; 1743 /* - I2C1 ------------------------------------------------------------------ */ 1744 static const unsigned int i2c1_pins[] = { 1745 /* SCL, SDA, */ 1746 RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28), 1747 }; 1748 static const unsigned int i2c1_mux[] = { 1749 SCL1_MARK, SDA1_MARK, 1750 }; 1751 static const unsigned int i2c1_b_pins[] = { 1752 /* SCL, SDA, */ 1753 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 11), 1754 }; 1755 static const unsigned int i2c1_b_mux[] = { 1756 SCL1_B_MARK, SDA1_B_MARK, 1757 }; 1758 static const unsigned int i2c1_c_pins[] = { 1759 /* SCL, SDA, */ 1760 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13), 1761 }; 1762 static const unsigned int i2c1_c_mux[] = { 1763 SCL1_C_MARK, SDA1_C_MARK, 1764 }; 1765 static const unsigned int i2c1_d_pins[] = { 1766 /* SCL, SDA, */ 1767 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 27), 1768 }; 1769 static const unsigned int i2c1_d_mux[] = { 1770 SCL1_D_MARK, SDA1_D_MARK, 1771 }; 1772 /* - I2C2 ------------------------------------------------------------------ */ 1773 static const unsigned int i2c2_pins[] = { 1774 /* SCL, SDA, */ 1775 RCAR_GP_PIN(0, 25), RCAR_GP_PIN(0, 26), 1776 }; 1777 static const unsigned int i2c2_mux[] = { 1778 SCL2_MARK, SDA2_MARK, 1779 }; 1780 static const unsigned int i2c2_b_pins[] = { 1781 /* SCL, SDA, */ 1782 RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19), 1783 }; 1784 static const unsigned int i2c2_b_mux[] = { 1785 SCL2_B_MARK, SDA2_B_MARK, 1786 }; 1787 static const unsigned int i2c2_c_pins[] = { 1788 /* SCL, SDA */ 1789 RCAR_GP_PIN(0, 31), RCAR_GP_PIN(0, 30), 1790 }; 1791 static const unsigned int i2c2_c_mux[] = { 1792 SCL2_C_MARK, SDA2_C_MARK, 1793 }; 1794 static const unsigned int i2c2_d_pins[] = { 1795 /* SCL, SDA */ 1796 RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 25), 1797 }; 1798 static const unsigned int i2c2_d_mux[] = { 1799 SCL2_D_MARK, SDA2_D_MARK, 1800 }; 1801 /* - I2C3 ------------------------------------------------------------------ */ 1802 static const unsigned int i2c3_pins[] = { 1803 /* SCL, SDA, */ 1804 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(2, 30), 1805 }; 1806 static const unsigned int i2c3_mux[] = { 1807 SCL3_MARK, SDA3_MARK, 1808 }; 1809 static const unsigned int i2c3_b_pins[] = { 1810 /* SCL, SDA, */ 1811 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(0, 30), 1812 }; 1813 static const unsigned int i2c3_b_mux[] = { 1814 SCL3_B_MARK, SDA3_B_MARK, 1815 }; 1816 /* - INTC ------------------------------------------------------------------- */ 1817 static const unsigned int intc_irq0_pins[] = { 1818 /* IRQ */ 1819 RCAR_GP_PIN(2, 14), 1820 }; 1821 static const unsigned int intc_irq0_mux[] = { 1822 IRQ0_MARK, 1823 }; 1824 static const unsigned int intc_irq0_b_pins[] = { 1825 /* IRQ */ 1826 RCAR_GP_PIN(4, 13), 1827 }; 1828 static const unsigned int intc_irq0_b_mux[] = { 1829 IRQ0_B_MARK, 1830 }; 1831 static const unsigned int intc_irq1_pins[] = { 1832 /* IRQ */ 1833 RCAR_GP_PIN(2, 15), 1834 }; 1835 static const unsigned int intc_irq1_mux[] = { 1836 IRQ1_MARK, 1837 }; 1838 static const unsigned int intc_irq1_b_pins[] = { 1839 /* IRQ */ 1840 RCAR_GP_PIN(4, 14), 1841 }; 1842 static const unsigned int intc_irq1_b_mux[] = { 1843 IRQ1_B_MARK, 1844 }; 1845 static const unsigned int intc_irq2_pins[] = { 1846 /* IRQ */ 1847 RCAR_GP_PIN(2, 24), 1848 }; 1849 static const unsigned int intc_irq2_mux[] = { 1850 IRQ2_MARK, 1851 }; 1852 static const unsigned int intc_irq2_b_pins[] = { 1853 /* IRQ */ 1854 RCAR_GP_PIN(4, 15), 1855 }; 1856 static const unsigned int intc_irq2_b_mux[] = { 1857 IRQ2_B_MARK, 1858 }; 1859 static const unsigned int intc_irq3_pins[] = { 1860 /* IRQ */ 1861 RCAR_GP_PIN(2, 25), 1862 }; 1863 static const unsigned int intc_irq3_mux[] = { 1864 IRQ3_MARK, 1865 }; 1866 static const unsigned int intc_irq3_b_pins[] = { 1867 /* IRQ */ 1868 RCAR_GP_PIN(4, 16), 1869 }; 1870 static const unsigned int intc_irq3_b_mux[] = { 1871 IRQ3_B_MARK, 1872 }; 1873 /* - LSBC ------------------------------------------------------------------- */ 1874 static const unsigned int lbsc_cs0_pins[] = { 1875 /* CS */ 1876 RCAR_GP_PIN(0, 13), 1877 }; 1878 static const unsigned int lbsc_cs0_mux[] = { 1879 CS0_MARK, 1880 }; 1881 static const unsigned int lbsc_cs1_pins[] = { 1882 /* CS */ 1883 RCAR_GP_PIN(0, 14), 1884 }; 1885 static const unsigned int lbsc_cs1_mux[] = { 1886 CS1_A26_MARK, 1887 }; 1888 static const unsigned int lbsc_ex_cs0_pins[] = { 1889 /* CS */ 1890 RCAR_GP_PIN(0, 15), 1891 }; 1892 static const unsigned int lbsc_ex_cs0_mux[] = { 1893 EX_CS0_MARK, 1894 }; 1895 static const unsigned int lbsc_ex_cs1_pins[] = { 1896 /* CS */ 1897 RCAR_GP_PIN(0, 16), 1898 }; 1899 static const unsigned int lbsc_ex_cs1_mux[] = { 1900 EX_CS1_MARK, 1901 }; 1902 static const unsigned int lbsc_ex_cs2_pins[] = { 1903 /* CS */ 1904 RCAR_GP_PIN(0, 17), 1905 }; 1906 static const unsigned int lbsc_ex_cs2_mux[] = { 1907 EX_CS2_MARK, 1908 }; 1909 static const unsigned int lbsc_ex_cs3_pins[] = { 1910 /* CS */ 1911 RCAR_GP_PIN(0, 18), 1912 }; 1913 static const unsigned int lbsc_ex_cs3_mux[] = { 1914 EX_CS3_MARK, 1915 }; 1916 static const unsigned int lbsc_ex_cs4_pins[] = { 1917 /* CS */ 1918 RCAR_GP_PIN(0, 19), 1919 }; 1920 static const unsigned int lbsc_ex_cs4_mux[] = { 1921 EX_CS4_MARK, 1922 }; 1923 static const unsigned int lbsc_ex_cs5_pins[] = { 1924 /* CS */ 1925 RCAR_GP_PIN(0, 20), 1926 }; 1927 static const unsigned int lbsc_ex_cs5_mux[] = { 1928 EX_CS5_MARK, 1929 }; 1930 /* - MMCIF ------------------------------------------------------------------ */ 1931 static const unsigned int mmc0_data1_pins[] = { 1932 /* D[0] */ 1933 RCAR_GP_PIN(0, 19), 1934 }; 1935 static const unsigned int mmc0_data1_mux[] = { 1936 MMC0_D0_MARK, 1937 }; 1938 static const unsigned int mmc0_data4_pins[] = { 1939 /* D[0:3] */ 1940 RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 21), 1941 RCAR_GP_PIN(0, 2), 1942 }; 1943 static const unsigned int mmc0_data4_mux[] = { 1944 MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK, 1945 }; 1946 static const unsigned int mmc0_data8_pins[] = { 1947 /* D[0:7] */ 1948 RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 21), 1949 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), 1950 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 16), 1951 }; 1952 static const unsigned int mmc0_data8_mux[] = { 1953 MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK, 1954 MMC0_D4_MARK, MMC0_D5_MARK, MMC0_D6_MARK, MMC0_D7_MARK, 1955 }; 1956 static const unsigned int mmc0_ctrl_pins[] = { 1957 /* CMD, CLK */ 1958 RCAR_GP_PIN(0, 18), RCAR_GP_PIN(0, 17), 1959 }; 1960 static const unsigned int mmc0_ctrl_mux[] = { 1961 MMC0_CMD_MARK, MMC0_CLK_MARK, 1962 }; 1963 static const unsigned int mmc1_data1_pins[] = { 1964 /* D[0] */ 1965 RCAR_GP_PIN(2, 8), 1966 }; 1967 static const unsigned int mmc1_data1_mux[] = { 1968 MMC1_D0_MARK, 1969 }; 1970 static const unsigned int mmc1_data4_pins[] = { 1971 /* D[0:3] */ 1972 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10), 1973 RCAR_GP_PIN(2, 11), 1974 }; 1975 static const unsigned int mmc1_data4_mux[] = { 1976 MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK, 1977 }; 1978 static const unsigned int mmc1_data8_pins[] = { 1979 /* D[0:7] */ 1980 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10), 1981 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13), 1982 RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17), 1983 }; 1984 static const unsigned int mmc1_data8_mux[] = { 1985 MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK, 1986 MMC1_D4_MARK, MMC1_D5_MARK, MMC1_D6_MARK, MMC1_D7_MARK, 1987 }; 1988 static const unsigned int mmc1_ctrl_pins[] = { 1989 /* CMD, CLK */ 1990 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 1), 1991 }; 1992 static const unsigned int mmc1_ctrl_mux[] = { 1993 MMC1_CMD_MARK, MMC1_CLK_MARK, 1994 }; 1995 /* - SCIF0 ------------------------------------------------------------------ */ 1996 static const unsigned int scif0_data_pins[] = { 1997 /* RXD, TXD */ 1998 RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 24), 1999 }; 2000 static const unsigned int scif0_data_mux[] = { 2001 RX0_MARK, TX0_MARK, 2002 }; 2003 static const unsigned int scif0_clk_pins[] = { 2004 /* SCK */ 2005 RCAR_GP_PIN(4, 28), 2006 }; 2007 static const unsigned int scif0_clk_mux[] = { 2008 SCK0_MARK, 2009 }; 2010 static const unsigned int scif0_ctrl_pins[] = { 2011 /* RTS, CTS */ 2012 RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 22), 2013 }; 2014 static const unsigned int scif0_ctrl_mux[] = { 2015 RTS0_TANS_MARK, CTS0_MARK, 2016 }; 2017 static const unsigned int scif0_data_b_pins[] = { 2018 /* RXD, TXD */ 2019 RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19), 2020 }; 2021 static const unsigned int scif0_data_b_mux[] = { 2022 RX0_B_MARK, TX0_B_MARK, 2023 }; 2024 static const unsigned int scif0_clk_b_pins[] = { 2025 /* SCK */ 2026 RCAR_GP_PIN(1, 1), 2027 }; 2028 static const unsigned int scif0_clk_b_mux[] = { 2029 SCK0_B_MARK, 2030 }; 2031 static const unsigned int scif0_ctrl_b_pins[] = { 2032 /* RTS, CTS */ 2033 RCAR_GP_PIN(0, 18), RCAR_GP_PIN(0, 11), 2034 }; 2035 static const unsigned int scif0_ctrl_b_mux[] = { 2036 RTS0_B_TANS_B_MARK, CTS0_B_MARK, 2037 }; 2038 static const unsigned int scif0_data_c_pins[] = { 2039 /* RXD, TXD */ 2040 RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 19), 2041 }; 2042 static const unsigned int scif0_data_c_mux[] = { 2043 RX0_C_MARK, TX0_C_MARK, 2044 }; 2045 static const unsigned int scif0_clk_c_pins[] = { 2046 /* SCK */ 2047 RCAR_GP_PIN(4, 17), 2048 }; 2049 static const unsigned int scif0_clk_c_mux[] = { 2050 SCK0_C_MARK, 2051 }; 2052 static const unsigned int scif0_ctrl_c_pins[] = { 2053 /* RTS, CTS */ 2054 RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20), 2055 }; 2056 static const unsigned int scif0_ctrl_c_mux[] = { 2057 RTS0_C_TANS_C_MARK, CTS0_C_MARK, 2058 }; 2059 static const unsigned int scif0_data_d_pins[] = { 2060 /* RXD, TXD */ 2061 RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 10), 2062 }; 2063 static const unsigned int scif0_data_d_mux[] = { 2064 RX0_D_MARK, TX0_D_MARK, 2065 }; 2066 static const unsigned int scif0_clk_d_pins[] = { 2067 /* SCK */ 2068 RCAR_GP_PIN(1, 18), 2069 }; 2070 static const unsigned int scif0_clk_d_mux[] = { 2071 SCK0_D_MARK, 2072 }; 2073 static const unsigned int scif0_ctrl_d_pins[] = { 2074 /* RTS, CTS */ 2075 RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 3), 2076 }; 2077 static const unsigned int scif0_ctrl_d_mux[] = { 2078 RTS0_D_TANS_D_MARK, CTS0_D_MARK, 2079 }; 2080 /* - SCIF1 ------------------------------------------------------------------ */ 2081 static const unsigned int scif1_data_pins[] = { 2082 /* RXD, TXD */ 2083 RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20), 2084 }; 2085 static const unsigned int scif1_data_mux[] = { 2086 RX1_MARK, TX1_MARK, 2087 }; 2088 static const unsigned int scif1_clk_pins[] = { 2089 /* SCK */ 2090 RCAR_GP_PIN(4, 17), 2091 }; 2092 static const unsigned int scif1_clk_mux[] = { 2093 SCK1_MARK, 2094 }; 2095 static const unsigned int scif1_ctrl_pins[] = { 2096 /* RTS, CTS */ 2097 RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 18), 2098 }; 2099 static const unsigned int scif1_ctrl_mux[] = { 2100 RTS1_TANS_MARK, CTS1_MARK, 2101 }; 2102 static const unsigned int scif1_data_b_pins[] = { 2103 /* RXD, TXD */ 2104 RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 18), 2105 }; 2106 static const unsigned int scif1_data_b_mux[] = { 2107 RX1_B_MARK, TX1_B_MARK, 2108 }; 2109 static const unsigned int scif1_clk_b_pins[] = { 2110 /* SCK */ 2111 RCAR_GP_PIN(3, 17), 2112 }; 2113 static const unsigned int scif1_clk_b_mux[] = { 2114 SCK1_B_MARK, 2115 }; 2116 static const unsigned int scif1_ctrl_b_pins[] = { 2117 /* RTS, CTS */ 2118 RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20), 2119 }; 2120 static const unsigned int scif1_ctrl_b_mux[] = { 2121 RTS1_B_TANS_B_MARK, CTS1_B_MARK, 2122 }; 2123 static const unsigned int scif1_data_c_pins[] = { 2124 /* RXD, TXD */ 2125 RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2), 2126 }; 2127 static const unsigned int scif1_data_c_mux[] = { 2128 RX1_C_MARK, TX1_C_MARK, 2129 }; 2130 static const unsigned int scif1_clk_c_pins[] = { 2131 /* SCK */ 2132 RCAR_GP_PIN(2, 22), 2133 }; 2134 static const unsigned int scif1_clk_c_mux[] = { 2135 SCK1_C_MARK, 2136 }; 2137 static const unsigned int scif1_ctrl_c_pins[] = { 2138 /* RTS, CTS */ 2139 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4), 2140 }; 2141 static const unsigned int scif1_ctrl_c_mux[] = { 2142 RTS1_C_TANS_C_MARK, CTS1_C_MARK, 2143 }; 2144 /* - SCIF2 ------------------------------------------------------------------ */ 2145 static const unsigned int scif2_data_pins[] = { 2146 /* RXD, TXD */ 2147 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 9), 2148 }; 2149 static const unsigned int scif2_data_mux[] = { 2150 RX2_MARK, TX2_MARK, 2151 }; 2152 static const unsigned int scif2_clk_pins[] = { 2153 /* SCK */ 2154 RCAR_GP_PIN(3, 11), 2155 }; 2156 static const unsigned int scif2_clk_mux[] = { 2157 SCK2_MARK, 2158 }; 2159 static const unsigned int scif2_data_b_pins[] = { 2160 /* RXD, TXD */ 2161 RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 23), 2162 }; 2163 static const unsigned int scif2_data_b_mux[] = { 2164 RX2_B_MARK, TX2_B_MARK, 2165 }; 2166 static const unsigned int scif2_clk_b_pins[] = { 2167 /* SCK */ 2168 RCAR_GP_PIN(3, 22), 2169 }; 2170 static const unsigned int scif2_clk_b_mux[] = { 2171 SCK2_B_MARK, 2172 }; 2173 static const unsigned int scif2_data_c_pins[] = { 2174 /* RXD, TXD */ 2175 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(0, 31), 2176 }; 2177 static const unsigned int scif2_data_c_mux[] = { 2178 RX2_C_MARK, TX2_C_MARK, 2179 }; 2180 static const unsigned int scif2_clk_c_pins[] = { 2181 /* SCK */ 2182 RCAR_GP_PIN(1, 0), 2183 }; 2184 static const unsigned int scif2_clk_c_mux[] = { 2185 SCK2_C_MARK, 2186 }; 2187 static const unsigned int scif2_data_d_pins[] = { 2188 /* RXD, TXD */ 2189 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(1, 30), 2190 }; 2191 static const unsigned int scif2_data_d_mux[] = { 2192 RX2_D_MARK, TX2_D_MARK, 2193 }; 2194 static const unsigned int scif2_clk_d_pins[] = { 2195 /* SCK */ 2196 RCAR_GP_PIN(1, 31), 2197 }; 2198 static const unsigned int scif2_clk_d_mux[] = { 2199 SCK2_D_MARK, 2200 }; 2201 static const unsigned int scif2_data_e_pins[] = { 2202 /* RXD, TXD */ 2203 RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19), 2204 }; 2205 static const unsigned int scif2_data_e_mux[] = { 2206 RX2_E_MARK, TX2_E_MARK, 2207 }; 2208 /* - SCIF3 ------------------------------------------------------------------ */ 2209 static const unsigned int scif3_data_pins[] = { 2210 /* RXD, TXD */ 2211 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 8), 2212 }; 2213 static const unsigned int scif3_data_mux[] = { 2214 RX3_IRDA_RX_MARK, TX3_IRDA_TX_MARK, 2215 }; 2216 static const unsigned int scif3_clk_pins[] = { 2217 /* SCK */ 2218 RCAR_GP_PIN(4, 7), 2219 }; 2220 static const unsigned int scif3_clk_mux[] = { 2221 SCK3_MARK, 2222 }; 2223 2224 static const unsigned int scif3_data_b_pins[] = { 2225 /* RXD, TXD */ 2226 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(1, 30), 2227 }; 2228 static const unsigned int scif3_data_b_mux[] = { 2229 RX3_B_IRDA_RX_B_MARK, TX3_B_IRDA_TX_B_MARK, 2230 }; 2231 static const unsigned int scif3_data_c_pins[] = { 2232 /* RXD, TXD */ 2233 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 12), 2234 }; 2235 static const unsigned int scif3_data_c_mux[] = { 2236 RX3_C_IRDA_RX_C_MARK, TX3C_IRDA_TX_C_MARK, 2237 }; 2238 static const unsigned int scif3_data_d_pins[] = { 2239 /* RXD, TXD */ 2240 RCAR_GP_PIN(0, 30), RCAR_GP_PIN(0, 29), 2241 }; 2242 static const unsigned int scif3_data_d_mux[] = { 2243 RX3_D_IRDA_RX_D_MARK, TX3_D_IRDA_TX_D_MARK, 2244 }; 2245 static const unsigned int scif3_data_e_pins[] = { 2246 /* RXD, TXD */ 2247 RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2), 2248 }; 2249 static const unsigned int scif3_data_e_mux[] = { 2250 RX3_E_IRDA_RX_E_MARK, TX3_E_IRDA_TX_E_MARK, 2251 }; 2252 static const unsigned int scif3_clk_e_pins[] = { 2253 /* SCK */ 2254 RCAR_GP_PIN(1, 10), 2255 }; 2256 static const unsigned int scif3_clk_e_mux[] = { 2257 SCK3_E_MARK, 2258 }; 2259 /* - SCIF4 ------------------------------------------------------------------ */ 2260 static const unsigned int scif4_data_pins[] = { 2261 /* RXD, TXD */ 2262 RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 26), 2263 }; 2264 static const unsigned int scif4_data_mux[] = { 2265 RX4_MARK, TX4_MARK, 2266 }; 2267 static const unsigned int scif4_clk_pins[] = { 2268 /* SCK */ 2269 RCAR_GP_PIN(3, 25), 2270 }; 2271 static const unsigned int scif4_clk_mux[] = { 2272 SCK4_MARK, 2273 }; 2274 static const unsigned int scif4_data_b_pins[] = { 2275 /* RXD, TXD */ 2276 RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14), 2277 }; 2278 static const unsigned int scif4_data_b_mux[] = { 2279 RX4_B_MARK, TX4_B_MARK, 2280 }; 2281 static const unsigned int scif4_clk_b_pins[] = { 2282 /* SCK */ 2283 RCAR_GP_PIN(3, 16), 2284 }; 2285 static const unsigned int scif4_clk_b_mux[] = { 2286 SCK4_B_MARK, 2287 }; 2288 static const unsigned int scif4_data_c_pins[] = { 2289 /* RXD, TXD */ 2290 RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 21), 2291 }; 2292 static const unsigned int scif4_data_c_mux[] = { 2293 RX4_C_MARK, TX4_C_MARK, 2294 }; 2295 static const unsigned int scif4_data_d_pins[] = { 2296 /* RXD, TXD */ 2297 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4), 2298 }; 2299 static const unsigned int scif4_data_d_mux[] = { 2300 RX4_D_MARK, TX4_D_MARK, 2301 }; 2302 /* - SCIF5 ------------------------------------------------------------------ */ 2303 static const unsigned int scif5_data_pins[] = { 2304 /* RXD, TXD */ 2305 RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18), 2306 }; 2307 static const unsigned int scif5_data_mux[] = { 2308 RX5_MARK, TX5_MARK, 2309 }; 2310 static const unsigned int scif5_clk_pins[] = { 2311 /* SCK */ 2312 RCAR_GP_PIN(1, 11), 2313 }; 2314 static const unsigned int scif5_clk_mux[] = { 2315 SCK5_MARK, 2316 }; 2317 static const unsigned int scif5_data_b_pins[] = { 2318 /* RXD, TXD */ 2319 RCAR_GP_PIN(0, 18), RCAR_GP_PIN(0, 11), 2320 }; 2321 static const unsigned int scif5_data_b_mux[] = { 2322 RX5_B_MARK, TX5_B_MARK, 2323 }; 2324 static const unsigned int scif5_clk_b_pins[] = { 2325 /* SCK */ 2326 RCAR_GP_PIN(0, 19), 2327 }; 2328 static const unsigned int scif5_clk_b_mux[] = { 2329 SCK5_B_MARK, 2330 }; 2331 static const unsigned int scif5_data_c_pins[] = { 2332 /* RXD, TXD */ 2333 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 23), 2334 }; 2335 static const unsigned int scif5_data_c_mux[] = { 2336 RX5_C_MARK, TX5_C_MARK, 2337 }; 2338 static const unsigned int scif5_clk_c_pins[] = { 2339 /* SCK */ 2340 RCAR_GP_PIN(0, 28), 2341 }; 2342 static const unsigned int scif5_clk_c_mux[] = { 2343 SCK5_C_MARK, 2344 }; 2345 static const unsigned int scif5_data_d_pins[] = { 2346 /* RXD, TXD */ 2347 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 6), 2348 }; 2349 static const unsigned int scif5_data_d_mux[] = { 2350 RX5_D_MARK, TX5_D_MARK, 2351 }; 2352 static const unsigned int scif5_clk_d_pins[] = { 2353 /* SCK */ 2354 RCAR_GP_PIN(0, 7), 2355 }; 2356 static const unsigned int scif5_clk_d_mux[] = { 2357 SCK5_D_MARK, 2358 }; 2359 /* - SCIF Clock ------------------------------------------------------------- */ 2360 static const unsigned int scif_clk_pins[] = { 2361 /* SCIF_CLK */ 2362 RCAR_GP_PIN(4, 28), 2363 }; 2364 static const unsigned int scif_clk_mux[] = { 2365 SCIF_CLK_MARK, 2366 }; 2367 static const unsigned int scif_clk_b_pins[] = { 2368 /* SCIF_CLK */ 2369 RCAR_GP_PIN(4, 5), 2370 }; 2371 static const unsigned int scif_clk_b_mux[] = { 2372 SCIF_CLK_B_MARK, 2373 }; 2374 static const unsigned int scif_clk_c_pins[] = { 2375 /* SCIF_CLK */ 2376 RCAR_GP_PIN(4, 18), 2377 }; 2378 static const unsigned int scif_clk_c_mux[] = { 2379 SCIF_CLK_C_MARK, 2380 }; 2381 static const unsigned int scif_clk_d_pins[] = { 2382 /* SCIF_CLK */ 2383 RCAR_GP_PIN(2, 29), 2384 }; 2385 static const unsigned int scif_clk_d_mux[] = { 2386 SCIF_CLK_D_MARK, 2387 }; 2388 /* - SDHI0 ------------------------------------------------------------------ */ 2389 static const unsigned int sdhi0_data1_pins[] = { 2390 /* D0 */ 2391 RCAR_GP_PIN(3, 21), 2392 }; 2393 static const unsigned int sdhi0_data1_mux[] = { 2394 SD0_DAT0_MARK, 2395 }; 2396 static const unsigned int sdhi0_data4_pins[] = { 2397 /* D[0:3] */ 2398 RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23), 2399 RCAR_GP_PIN(3, 24), 2400 }; 2401 static const unsigned int sdhi0_data4_mux[] = { 2402 SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK, 2403 }; 2404 static const unsigned int sdhi0_ctrl_pins[] = { 2405 /* CMD, CLK */ 2406 RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 17), 2407 }; 2408 static const unsigned int sdhi0_ctrl_mux[] = { 2409 SD0_CMD_MARK, SD0_CLK_MARK, 2410 }; 2411 static const unsigned int sdhi0_cd_pins[] = { 2412 /* CD */ 2413 RCAR_GP_PIN(3, 19), 2414 }; 2415 static const unsigned int sdhi0_cd_mux[] = { 2416 SD0_CD_MARK, 2417 }; 2418 static const unsigned int sdhi0_wp_pins[] = { 2419 /* WP */ 2420 RCAR_GP_PIN(3, 20), 2421 }; 2422 static const unsigned int sdhi0_wp_mux[] = { 2423 SD0_WP_MARK, 2424 }; 2425 /* - SDHI1 ------------------------------------------------------------------ */ 2426 static const unsigned int sdhi1_data1_pins[] = { 2427 /* D0 */ 2428 RCAR_GP_PIN(0, 19), 2429 }; 2430 static const unsigned int sdhi1_data1_mux[] = { 2431 SD1_DAT0_MARK, 2432 }; 2433 static const unsigned int sdhi1_data4_pins[] = { 2434 /* D[0:3] */ 2435 RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 21), 2436 RCAR_GP_PIN(0, 2), 2437 }; 2438 static const unsigned int sdhi1_data4_mux[] = { 2439 SD1_DAT0_MARK, SD1_DAT1_MARK, SD1_DAT2_MARK, SD1_DAT3_MARK, 2440 }; 2441 static const unsigned int sdhi1_ctrl_pins[] = { 2442 /* CMD, CLK */ 2443 RCAR_GP_PIN(0, 18), RCAR_GP_PIN(0, 17), 2444 }; 2445 static const unsigned int sdhi1_ctrl_mux[] = { 2446 SD1_CMD_MARK, SD1_CLK_MARK, 2447 }; 2448 static const unsigned int sdhi1_cd_pins[] = { 2449 /* CD */ 2450 RCAR_GP_PIN(0, 10), 2451 }; 2452 static const unsigned int sdhi1_cd_mux[] = { 2453 SD1_CD_MARK, 2454 }; 2455 static const unsigned int sdhi1_wp_pins[] = { 2456 /* WP */ 2457 RCAR_GP_PIN(0, 11), 2458 }; 2459 static const unsigned int sdhi1_wp_mux[] = { 2460 SD1_WP_MARK, 2461 }; 2462 /* - SDHI2 ------------------------------------------------------------------ */ 2463 static const unsigned int sdhi2_data1_pins[] = { 2464 /* D0 */ 2465 RCAR_GP_PIN(3, 1), 2466 }; 2467 static const unsigned int sdhi2_data1_mux[] = { 2468 SD2_DAT0_MARK, 2469 }; 2470 static const unsigned int sdhi2_data4_pins[] = { 2471 /* D[0:3] */ 2472 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), 2473 RCAR_GP_PIN(3, 4), 2474 }; 2475 static const unsigned int sdhi2_data4_mux[] = { 2476 SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK, 2477 }; 2478 static const unsigned int sdhi2_ctrl_pins[] = { 2479 /* CMD, CLK */ 2480 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 5), 2481 }; 2482 static const unsigned int sdhi2_ctrl_mux[] = { 2483 SD2_CMD_MARK, SD2_CLK_MARK, 2484 }; 2485 static const unsigned int sdhi2_cd_pins[] = { 2486 /* CD */ 2487 RCAR_GP_PIN(3, 7), 2488 }; 2489 static const unsigned int sdhi2_cd_mux[] = { 2490 SD2_CD_MARK, 2491 }; 2492 static const unsigned int sdhi2_wp_pins[] = { 2493 /* WP */ 2494 RCAR_GP_PIN(3, 8), 2495 }; 2496 static const unsigned int sdhi2_wp_mux[] = { 2497 SD2_WP_MARK, 2498 }; 2499 /* - SDHI3 ------------------------------------------------------------------ */ 2500 static const unsigned int sdhi3_data1_pins[] = { 2501 /* D0 */ 2502 RCAR_GP_PIN(1, 18), 2503 }; 2504 static const unsigned int sdhi3_data1_mux[] = { 2505 SD3_DAT0_MARK, 2506 }; 2507 static const unsigned int sdhi3_data4_pins[] = { 2508 /* D[0:3] */ 2509 RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 20), 2510 RCAR_GP_PIN(1, 21), 2511 }; 2512 static const unsigned int sdhi3_data4_mux[] = { 2513 SD3_DAT0_MARK, SD3_DAT1_MARK, SD3_DAT2_MARK, SD3_DAT3_MARK, 2514 }; 2515 static const unsigned int sdhi3_ctrl_pins[] = { 2516 /* CMD, CLK */ 2517 RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2), 2518 }; 2519 static const unsigned int sdhi3_ctrl_mux[] = { 2520 SD3_CMD_MARK, SD3_CLK_MARK, 2521 }; 2522 static const unsigned int sdhi3_cd_pins[] = { 2523 /* CD */ 2524 RCAR_GP_PIN(1, 30), 2525 }; 2526 static const unsigned int sdhi3_cd_mux[] = { 2527 SD3_CD_MARK, 2528 }; 2529 static const unsigned int sdhi3_wp_pins[] = { 2530 /* WP */ 2531 RCAR_GP_PIN(2, 0), 2532 }; 2533 static const unsigned int sdhi3_wp_mux[] = { 2534 SD3_WP_MARK, 2535 }; 2536 /* - USB0 ------------------------------------------------------------------- */ 2537 static const unsigned int usb0_pins[] = { 2538 /* PENC */ 2539 RCAR_GP_PIN(4, 26), 2540 }; 2541 static const unsigned int usb0_mux[] = { 2542 USB_PENC0_MARK, 2543 }; 2544 static const unsigned int usb0_ovc_pins[] = { 2545 /* USB_OVC */ 2546 RCAR_GP_PIN(4, 22), 2547 }; 2548 static const unsigned int usb0_ovc_mux[] = { 2549 USB_OVC0_MARK, 2550 }; 2551 /* - USB1 ------------------------------------------------------------------- */ 2552 static const unsigned int usb1_pins[] = { 2553 /* PENC */ 2554 RCAR_GP_PIN(4, 27), 2555 }; 2556 static const unsigned int usb1_mux[] = { 2557 USB_PENC1_MARK, 2558 }; 2559 static const unsigned int usb1_ovc_pins[] = { 2560 /* USB_OVC */ 2561 RCAR_GP_PIN(4, 24), 2562 }; 2563 static const unsigned int usb1_ovc_mux[] = { 2564 USB_OVC1_MARK, 2565 }; 2566 /* - USB2 ------------------------------------------------------------------- */ 2567 static const unsigned int usb2_pins[] = { 2568 /* PENC */ 2569 RCAR_GP_PIN(4, 28), 2570 }; 2571 static const unsigned int usb2_mux[] = { 2572 USB_PENC2_MARK, 2573 }; 2574 static const unsigned int usb2_ovc_pins[] = { 2575 /* USB_OVC */ 2576 RCAR_GP_PIN(3, 29), 2577 }; 2578 static const unsigned int usb2_ovc_mux[] = { 2579 USB_OVC2_MARK, 2580 }; 2581 /* - VIN0 ------------------------------------------------------------------- */ 2582 static const unsigned int vin0_data8_pins[] = { 2583 /* D[0:7] */ 2584 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), 2585 RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11), 2586 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13), 2587 }; 2588 static const unsigned int vin0_data8_mux[] = { 2589 VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK, VI0_DATA2_VI0_B2_MARK, 2590 VI0_DATA3_VI0_B3_MARK, VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK, 2591 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK, 2592 }; 2593 static const unsigned int vin0_clk_pins[] = { 2594 /* CLK */ 2595 RCAR_GP_PIN(2, 1), 2596 }; 2597 static const unsigned int vin0_clk_mux[] = { 2598 VI0_CLK_MARK, 2599 }; 2600 static const unsigned int vin0_sync_pins[] = { 2601 /* HSYNC, VSYNC */ 2602 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), 2603 }; 2604 static const unsigned int vin0_sync_mux[] = { 2605 VI0_HSYNC_MARK, VI0_VSYNC_MARK, 2606 }; 2607 /* - VIN1 ------------------------------------------------------------------- */ 2608 static const unsigned int vin1_data8_pins[] = { 2609 /* D[0:7] */ 2610 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), 2611 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6), 2612 RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8), 2613 }; 2614 static const unsigned int vin1_data8_mux[] = { 2615 VI1_DATA0_VI1_B0_MARK, VI1_DATA1_VI1_B1_MARK, VI1_DATA2_VI1_B2_MARK, 2616 VI1_DATA3_VI1_B3_MARK, VI1_DATA4_VI1_B4_MARK, VI1_DATA5_VI1_B5_MARK, 2617 VI1_DATA6_VI1_B6_MARK, VI1_DATA7_VI1_B7_MARK, 2618 }; 2619 static const unsigned int vin1_clk_pins[] = { 2620 /* CLK */ 2621 RCAR_GP_PIN(2, 30), 2622 }; 2623 static const unsigned int vin1_clk_mux[] = { 2624 VI1_CLK_MARK, 2625 }; 2626 static const unsigned int vin1_sync_pins[] = { 2627 /* HSYNC, VSYNC */ 2628 RCAR_GP_PIN(2, 31), RCAR_GP_PIN(3, 0), 2629 }; 2630 static const unsigned int vin1_sync_mux[] = { 2631 VI1_HSYNC_MARK, VI1_VSYNC_MARK, 2632 }; 2633 /* - VIN2 ------------------------------------------------------------------- */ 2634 static const unsigned int vin2_data8_pins[] = { 2635 /* D[0:7] */ 2636 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10), 2637 RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19), 2638 RCAR_GP_PIN(1, 31), RCAR_GP_PIN(2, 0), 2639 }; 2640 static const unsigned int vin2_data8_mux[] = { 2641 VI2_DATA0_VI2_B0_MARK, VI2_DATA1_VI2_B1_MARK, VI2_DATA2_VI2_B2_MARK, 2642 VI2_DATA3_VI2_B3_MARK, VI2_DATA4_VI2_B4_MARK, VI2_DATA5_VI2_B5_MARK, 2643 VI2_DATA6_VI2_B6_MARK, VI2_DATA7_VI2_B7_MARK, 2644 }; 2645 static const unsigned int vin2_clk_pins[] = { 2646 /* CLK */ 2647 RCAR_GP_PIN(1, 30), 2648 }; 2649 static const unsigned int vin2_clk_mux[] = { 2650 VI2_CLK_MARK, 2651 }; 2652 static const unsigned int vin2_sync_pins[] = { 2653 /* HSYNC, VSYNC */ 2654 RCAR_GP_PIN(1, 28), RCAR_GP_PIN(1, 29), 2655 }; 2656 static const unsigned int vin2_sync_mux[] = { 2657 VI2_HSYNC_MARK, VI2_VSYNC_MARK, 2658 }; 2659 /* - VIN3 ------------------------------------------------------------------- */ 2660 static const unsigned int vin3_data8_pins[] = { 2661 /* D[0:7] */ 2662 RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), 2663 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14), 2664 RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16), 2665 }; 2666 static const unsigned int vin3_data8_mux[] = { 2667 VI3_DATA0_MARK, VI3_DATA1_MARK, VI3_DATA2_MARK, 2668 VI3_DATA3_MARK, VI3_DATA4_MARK, VI3_DATA5_MARK, 2669 VI3_DATA6_MARK, VI3_DATA7_MARK, 2670 }; 2671 static const unsigned int vin3_clk_pins[] = { 2672 /* CLK */ 2673 RCAR_GP_PIN(2, 31), 2674 }; 2675 static const unsigned int vin3_clk_mux[] = { 2676 VI3_CLK_MARK, 2677 }; 2678 static const unsigned int vin3_sync_pins[] = { 2679 /* HSYNC, VSYNC */ 2680 RCAR_GP_PIN(1, 28), RCAR_GP_PIN(1, 29), 2681 }; 2682 static const unsigned int vin3_sync_mux[] = { 2683 VI3_HSYNC_MARK, VI3_VSYNC_MARK, 2684 }; 2685 2686 static const struct sh_pfc_pin_group pinmux_groups[] = { 2687 SH_PFC_PIN_GROUP(du0_rgb666), 2688 SH_PFC_PIN_GROUP(du0_rgb888), 2689 SH_PFC_PIN_GROUP(du0_clk_in), 2690 SH_PFC_PIN_GROUP(du0_clk_out_0), 2691 SH_PFC_PIN_GROUP(du0_clk_out_1), 2692 SH_PFC_PIN_GROUP(du0_sync_0), 2693 SH_PFC_PIN_GROUP(du0_sync_1), 2694 SH_PFC_PIN_GROUP(du0_oddf), 2695 SH_PFC_PIN_GROUP(du0_cde), 2696 SH_PFC_PIN_GROUP(du1_rgb666), 2697 SH_PFC_PIN_GROUP(du1_rgb888), 2698 SH_PFC_PIN_GROUP(du1_clk_in), 2699 SH_PFC_PIN_GROUP(du1_clk_out), 2700 SH_PFC_PIN_GROUP(du1_sync_0), 2701 SH_PFC_PIN_GROUP(du1_sync_1), 2702 SH_PFC_PIN_GROUP(du1_oddf), 2703 SH_PFC_PIN_GROUP(du1_cde), 2704 SH_PFC_PIN_GROUP(ether_rmii), 2705 SH_PFC_PIN_GROUP(ether_link), 2706 SH_PFC_PIN_GROUP(ether_magic), 2707 SH_PFC_PIN_GROUP(hscif0_data), 2708 SH_PFC_PIN_GROUP(hscif0_data_b), 2709 SH_PFC_PIN_GROUP(hscif0_ctrl), 2710 SH_PFC_PIN_GROUP(hscif0_ctrl_b), 2711 SH_PFC_PIN_GROUP(hscif0_clk), 2712 SH_PFC_PIN_GROUP(hscif0_clk_b), 2713 SH_PFC_PIN_GROUP(hscif1_data), 2714 SH_PFC_PIN_GROUP(hscif1_data_b), 2715 SH_PFC_PIN_GROUP(hscif1_ctrl), 2716 SH_PFC_PIN_GROUP(hscif1_ctrl_b), 2717 SH_PFC_PIN_GROUP(hscif1_clk), 2718 SH_PFC_PIN_GROUP(hscif1_clk_b), 2719 SH_PFC_PIN_GROUP(hspi0), 2720 SH_PFC_PIN_GROUP(hspi1), 2721 SH_PFC_PIN_GROUP(hspi1_b), 2722 SH_PFC_PIN_GROUP(hspi1_c), 2723 SH_PFC_PIN_GROUP(hspi1_d), 2724 SH_PFC_PIN_GROUP(hspi2), 2725 SH_PFC_PIN_GROUP(hspi2_b), 2726 SH_PFC_PIN_GROUP(i2c1), 2727 SH_PFC_PIN_GROUP(i2c1_b), 2728 SH_PFC_PIN_GROUP(i2c1_c), 2729 SH_PFC_PIN_GROUP(i2c1_d), 2730 SH_PFC_PIN_GROUP(i2c2), 2731 SH_PFC_PIN_GROUP(i2c2_b), 2732 SH_PFC_PIN_GROUP(i2c2_c), 2733 SH_PFC_PIN_GROUP(i2c2_d), 2734 SH_PFC_PIN_GROUP(i2c3), 2735 SH_PFC_PIN_GROUP(i2c3_b), 2736 SH_PFC_PIN_GROUP(intc_irq0), 2737 SH_PFC_PIN_GROUP(intc_irq0_b), 2738 SH_PFC_PIN_GROUP(intc_irq1), 2739 SH_PFC_PIN_GROUP(intc_irq1_b), 2740 SH_PFC_PIN_GROUP(intc_irq2), 2741 SH_PFC_PIN_GROUP(intc_irq2_b), 2742 SH_PFC_PIN_GROUP(intc_irq3), 2743 SH_PFC_PIN_GROUP(intc_irq3_b), 2744 SH_PFC_PIN_GROUP(lbsc_cs0), 2745 SH_PFC_PIN_GROUP(lbsc_cs1), 2746 SH_PFC_PIN_GROUP(lbsc_ex_cs0), 2747 SH_PFC_PIN_GROUP(lbsc_ex_cs1), 2748 SH_PFC_PIN_GROUP(lbsc_ex_cs2), 2749 SH_PFC_PIN_GROUP(lbsc_ex_cs3), 2750 SH_PFC_PIN_GROUP(lbsc_ex_cs4), 2751 SH_PFC_PIN_GROUP(lbsc_ex_cs5), 2752 SH_PFC_PIN_GROUP(mmc0_data1), 2753 SH_PFC_PIN_GROUP(mmc0_data4), 2754 SH_PFC_PIN_GROUP(mmc0_data8), 2755 SH_PFC_PIN_GROUP(mmc0_ctrl), 2756 SH_PFC_PIN_GROUP(mmc1_data1), 2757 SH_PFC_PIN_GROUP(mmc1_data4), 2758 SH_PFC_PIN_GROUP(mmc1_data8), 2759 SH_PFC_PIN_GROUP(mmc1_ctrl), 2760 SH_PFC_PIN_GROUP(scif0_data), 2761 SH_PFC_PIN_GROUP(scif0_clk), 2762 SH_PFC_PIN_GROUP(scif0_ctrl), 2763 SH_PFC_PIN_GROUP(scif0_data_b), 2764 SH_PFC_PIN_GROUP(scif0_clk_b), 2765 SH_PFC_PIN_GROUP(scif0_ctrl_b), 2766 SH_PFC_PIN_GROUP(scif0_data_c), 2767 SH_PFC_PIN_GROUP(scif0_clk_c), 2768 SH_PFC_PIN_GROUP(scif0_ctrl_c), 2769 SH_PFC_PIN_GROUP(scif0_data_d), 2770 SH_PFC_PIN_GROUP(scif0_clk_d), 2771 SH_PFC_PIN_GROUP(scif0_ctrl_d), 2772 SH_PFC_PIN_GROUP(scif1_data), 2773 SH_PFC_PIN_GROUP(scif1_clk), 2774 SH_PFC_PIN_GROUP(scif1_ctrl), 2775 SH_PFC_PIN_GROUP(scif1_data_b), 2776 SH_PFC_PIN_GROUP(scif1_clk_b), 2777 SH_PFC_PIN_GROUP(scif1_ctrl_b), 2778 SH_PFC_PIN_GROUP(scif1_data_c), 2779 SH_PFC_PIN_GROUP(scif1_clk_c), 2780 SH_PFC_PIN_GROUP(scif1_ctrl_c), 2781 SH_PFC_PIN_GROUP(scif2_data), 2782 SH_PFC_PIN_GROUP(scif2_clk), 2783 SH_PFC_PIN_GROUP(scif2_data_b), 2784 SH_PFC_PIN_GROUP(scif2_clk_b), 2785 SH_PFC_PIN_GROUP(scif2_data_c), 2786 SH_PFC_PIN_GROUP(scif2_clk_c), 2787 SH_PFC_PIN_GROUP(scif2_data_d), 2788 SH_PFC_PIN_GROUP(scif2_clk_d), 2789 SH_PFC_PIN_GROUP(scif2_data_e), 2790 SH_PFC_PIN_GROUP(scif3_data), 2791 SH_PFC_PIN_GROUP(scif3_clk), 2792 SH_PFC_PIN_GROUP(scif3_data_b), 2793 SH_PFC_PIN_GROUP(scif3_data_c), 2794 SH_PFC_PIN_GROUP(scif3_data_d), 2795 SH_PFC_PIN_GROUP(scif3_data_e), 2796 SH_PFC_PIN_GROUP(scif3_clk_e), 2797 SH_PFC_PIN_GROUP(scif4_data), 2798 SH_PFC_PIN_GROUP(scif4_clk), 2799 SH_PFC_PIN_GROUP(scif4_data_b), 2800 SH_PFC_PIN_GROUP(scif4_clk_b), 2801 SH_PFC_PIN_GROUP(scif4_data_c), 2802 SH_PFC_PIN_GROUP(scif4_data_d), 2803 SH_PFC_PIN_GROUP(scif5_data), 2804 SH_PFC_PIN_GROUP(scif5_clk), 2805 SH_PFC_PIN_GROUP(scif5_data_b), 2806 SH_PFC_PIN_GROUP(scif5_clk_b), 2807 SH_PFC_PIN_GROUP(scif5_data_c), 2808 SH_PFC_PIN_GROUP(scif5_clk_c), 2809 SH_PFC_PIN_GROUP(scif5_data_d), 2810 SH_PFC_PIN_GROUP(scif5_clk_d), 2811 SH_PFC_PIN_GROUP(scif_clk), 2812 SH_PFC_PIN_GROUP(scif_clk_b), 2813 SH_PFC_PIN_GROUP(scif_clk_c), 2814 SH_PFC_PIN_GROUP(scif_clk_d), 2815 SH_PFC_PIN_GROUP(sdhi0_data1), 2816 SH_PFC_PIN_GROUP(sdhi0_data4), 2817 SH_PFC_PIN_GROUP(sdhi0_ctrl), 2818 SH_PFC_PIN_GROUP(sdhi0_cd), 2819 SH_PFC_PIN_GROUP(sdhi0_wp), 2820 SH_PFC_PIN_GROUP(sdhi1_data1), 2821 SH_PFC_PIN_GROUP(sdhi1_data4), 2822 SH_PFC_PIN_GROUP(sdhi1_ctrl), 2823 SH_PFC_PIN_GROUP(sdhi1_cd), 2824 SH_PFC_PIN_GROUP(sdhi1_wp), 2825 SH_PFC_PIN_GROUP(sdhi2_data1), 2826 SH_PFC_PIN_GROUP(sdhi2_data4), 2827 SH_PFC_PIN_GROUP(sdhi2_ctrl), 2828 SH_PFC_PIN_GROUP(sdhi2_cd), 2829 SH_PFC_PIN_GROUP(sdhi2_wp), 2830 SH_PFC_PIN_GROUP(sdhi3_data1), 2831 SH_PFC_PIN_GROUP(sdhi3_data4), 2832 SH_PFC_PIN_GROUP(sdhi3_ctrl), 2833 SH_PFC_PIN_GROUP(sdhi3_cd), 2834 SH_PFC_PIN_GROUP(sdhi3_wp), 2835 SH_PFC_PIN_GROUP(usb0), 2836 SH_PFC_PIN_GROUP(usb0_ovc), 2837 SH_PFC_PIN_GROUP(usb1), 2838 SH_PFC_PIN_GROUP(usb1_ovc), 2839 SH_PFC_PIN_GROUP(usb2), 2840 SH_PFC_PIN_GROUP(usb2_ovc), 2841 SH_PFC_PIN_GROUP(vin0_data8), 2842 SH_PFC_PIN_GROUP(vin0_clk), 2843 SH_PFC_PIN_GROUP(vin0_sync), 2844 SH_PFC_PIN_GROUP(vin1_data8), 2845 SH_PFC_PIN_GROUP(vin1_clk), 2846 SH_PFC_PIN_GROUP(vin1_sync), 2847 SH_PFC_PIN_GROUP(vin2_data8), 2848 SH_PFC_PIN_GROUP(vin2_clk), 2849 SH_PFC_PIN_GROUP(vin2_sync), 2850 SH_PFC_PIN_GROUP(vin3_data8), 2851 SH_PFC_PIN_GROUP(vin3_clk), 2852 SH_PFC_PIN_GROUP(vin3_sync), 2853 }; 2854 2855 static const char * const du0_groups[] = { 2856 "du0_rgb666", 2857 "du0_rgb888", 2858 "du0_clk_in", 2859 "du0_clk_out_0", 2860 "du0_clk_out_1", 2861 "du0_sync_0", 2862 "du0_sync_1", 2863 "du0_oddf", 2864 "du0_cde", 2865 }; 2866 2867 static const char * const du1_groups[] = { 2868 "du1_rgb666", 2869 "du1_rgb888", 2870 "du1_clk_in", 2871 "du1_clk_out", 2872 "du1_sync_0", 2873 "du1_sync_1", 2874 "du1_oddf", 2875 "du1_cde", 2876 }; 2877 2878 static const char * const ether_groups[] = { 2879 "ether_rmii", 2880 "ether_link", 2881 "ether_magic", 2882 }; 2883 2884 static const char * const hscif0_groups[] = { 2885 "hscif0_data", 2886 "hscif0_data_b", 2887 "hscif0_ctrl", 2888 "hscif0_ctrl_b", 2889 "hscif0_clk", 2890 "hscif0_clk_b", 2891 }; 2892 2893 static const char * const hscif1_groups[] = { 2894 "hscif1_data", 2895 "hscif1_data_b", 2896 "hscif1_ctrl", 2897 "hscif1_ctrl_b", 2898 "hscif1_clk", 2899 "hscif1_clk_b", 2900 }; 2901 2902 static const char * const hspi0_groups[] = { 2903 "hspi0", 2904 }; 2905 2906 static const char * const hspi1_groups[] = { 2907 "hspi1", 2908 "hspi1_b", 2909 "hspi1_c", 2910 "hspi1_d", 2911 }; 2912 2913 static const char * const hspi2_groups[] = { 2914 "hspi2", 2915 "hspi2_b", 2916 }; 2917 2918 static const char * const i2c1_groups[] = { 2919 "i2c1", 2920 "i2c1_b", 2921 "i2c1_c", 2922 "i2c1_d", 2923 }; 2924 2925 static const char * const i2c2_groups[] = { 2926 "i2c2", 2927 "i2c2_b", 2928 "i2c2_c", 2929 "i2c2_d", 2930 }; 2931 2932 static const char * const i2c3_groups[] = { 2933 "i2c3", 2934 "i2c3_b", 2935 }; 2936 2937 static const char * const intc_groups[] = { 2938 "intc_irq0", 2939 "intc_irq0_b", 2940 "intc_irq1", 2941 "intc_irq1_b", 2942 "intc_irq2", 2943 "intc_irq2_b", 2944 "intc_irq3", 2945 "intc_irq3_b", 2946 }; 2947 2948 static const char * const lbsc_groups[] = { 2949 "lbsc_cs0", 2950 "lbsc_cs1", 2951 "lbsc_ex_cs0", 2952 "lbsc_ex_cs1", 2953 "lbsc_ex_cs2", 2954 "lbsc_ex_cs3", 2955 "lbsc_ex_cs4", 2956 "lbsc_ex_cs5", 2957 }; 2958 2959 static const char * const mmc0_groups[] = { 2960 "mmc0_data1", 2961 "mmc0_data4", 2962 "mmc0_data8", 2963 "mmc0_ctrl", 2964 }; 2965 2966 static const char * const mmc1_groups[] = { 2967 "mmc1_data1", 2968 "mmc1_data4", 2969 "mmc1_data8", 2970 "mmc1_ctrl", 2971 }; 2972 2973 static const char * const scif0_groups[] = { 2974 "scif0_data", 2975 "scif0_clk", 2976 "scif0_ctrl", 2977 "scif0_data_b", 2978 "scif0_clk_b", 2979 "scif0_ctrl_b", 2980 "scif0_data_c", 2981 "scif0_clk_c", 2982 "scif0_ctrl_c", 2983 "scif0_data_d", 2984 "scif0_clk_d", 2985 "scif0_ctrl_d", 2986 }; 2987 2988 static const char * const scif1_groups[] = { 2989 "scif1_data", 2990 "scif1_clk", 2991 "scif1_ctrl", 2992 "scif1_data_b", 2993 "scif1_clk_b", 2994 "scif1_ctrl_b", 2995 "scif1_data_c", 2996 "scif1_clk_c", 2997 "scif1_ctrl_c", 2998 }; 2999 3000 static const char * const scif2_groups[] = { 3001 "scif2_data", 3002 "scif2_clk", 3003 "scif2_data_b", 3004 "scif2_clk_b", 3005 "scif2_data_c", 3006 "scif2_clk_c", 3007 "scif2_data_d", 3008 "scif2_clk_d", 3009 "scif2_data_e", 3010 }; 3011 3012 static const char * const scif3_groups[] = { 3013 "scif3_data", 3014 "scif3_clk", 3015 "scif3_data_b", 3016 "scif3_data_c", 3017 "scif3_data_d", 3018 "scif3_data_e", 3019 "scif3_clk_e", 3020 }; 3021 3022 static const char * const scif4_groups[] = { 3023 "scif4_data", 3024 "scif4_clk", 3025 "scif4_data_b", 3026 "scif4_clk_b", 3027 "scif4_data_c", 3028 "scif4_data_d", 3029 }; 3030 3031 static const char * const scif5_groups[] = { 3032 "scif5_data", 3033 "scif5_clk", 3034 "scif5_data_b", 3035 "scif5_clk_b", 3036 "scif5_data_c", 3037 "scif5_clk_c", 3038 "scif5_data_d", 3039 "scif5_clk_d", 3040 }; 3041 3042 static const char * const scif_clk_groups[] = { 3043 "scif_clk", 3044 "scif_clk_b", 3045 "scif_clk_c", 3046 "scif_clk_d", 3047 }; 3048 3049 static const char * const sdhi0_groups[] = { 3050 "sdhi0_data1", 3051 "sdhi0_data4", 3052 "sdhi0_ctrl", 3053 "sdhi0_cd", 3054 "sdhi0_wp", 3055 }; 3056 3057 static const char * const sdhi1_groups[] = { 3058 "sdhi1_data1", 3059 "sdhi1_data4", 3060 "sdhi1_ctrl", 3061 "sdhi1_cd", 3062 "sdhi1_wp", 3063 }; 3064 3065 static const char * const sdhi2_groups[] = { 3066 "sdhi2_data1", 3067 "sdhi2_data4", 3068 "sdhi2_ctrl", 3069 "sdhi2_cd", 3070 "sdhi2_wp", 3071 }; 3072 3073 static const char * const sdhi3_groups[] = { 3074 "sdhi3_data1", 3075 "sdhi3_data4", 3076 "sdhi3_ctrl", 3077 "sdhi3_cd", 3078 "sdhi3_wp", 3079 }; 3080 3081 static const char * const usb0_groups[] = { 3082 "usb0", 3083 "usb0_ovc", 3084 }; 3085 3086 static const char * const usb1_groups[] = { 3087 "usb1", 3088 "usb1_ovc", 3089 }; 3090 3091 static const char * const usb2_groups[] = { 3092 "usb2", 3093 "usb2_ovc", 3094 }; 3095 3096 static const char * const vin0_groups[] = { 3097 "vin0_data8", 3098 "vin0_clk", 3099 "vin0_sync", 3100 }; 3101 3102 static const char * const vin1_groups[] = { 3103 "vin1_data8", 3104 "vin1_clk", 3105 "vin1_sync", 3106 }; 3107 3108 static const char * const vin2_groups[] = { 3109 "vin2_data8", 3110 "vin2_clk", 3111 "vin2_sync", 3112 }; 3113 3114 static const char * const vin3_groups[] = { 3115 "vin3_data8", 3116 "vin3_clk", 3117 "vin3_sync", 3118 }; 3119 3120 static const struct sh_pfc_function pinmux_functions[] = { 3121 SH_PFC_FUNCTION(du0), 3122 SH_PFC_FUNCTION(du1), 3123 SH_PFC_FUNCTION(ether), 3124 SH_PFC_FUNCTION(hscif0), 3125 SH_PFC_FUNCTION(hscif1), 3126 SH_PFC_FUNCTION(hspi0), 3127 SH_PFC_FUNCTION(hspi1), 3128 SH_PFC_FUNCTION(hspi2), 3129 SH_PFC_FUNCTION(i2c1), 3130 SH_PFC_FUNCTION(i2c2), 3131 SH_PFC_FUNCTION(i2c3), 3132 SH_PFC_FUNCTION(intc), 3133 SH_PFC_FUNCTION(lbsc), 3134 SH_PFC_FUNCTION(mmc0), 3135 SH_PFC_FUNCTION(mmc1), 3136 SH_PFC_FUNCTION(sdhi0), 3137 SH_PFC_FUNCTION(sdhi1), 3138 SH_PFC_FUNCTION(sdhi2), 3139 SH_PFC_FUNCTION(sdhi3), 3140 SH_PFC_FUNCTION(scif0), 3141 SH_PFC_FUNCTION(scif1), 3142 SH_PFC_FUNCTION(scif2), 3143 SH_PFC_FUNCTION(scif3), 3144 SH_PFC_FUNCTION(scif4), 3145 SH_PFC_FUNCTION(scif5), 3146 SH_PFC_FUNCTION(scif_clk), 3147 SH_PFC_FUNCTION(usb0), 3148 SH_PFC_FUNCTION(usb1), 3149 SH_PFC_FUNCTION(usb2), 3150 SH_PFC_FUNCTION(vin0), 3151 SH_PFC_FUNCTION(vin1), 3152 SH_PFC_FUNCTION(vin2), 3153 SH_PFC_FUNCTION(vin3), 3154 }; 3155 3156 static const struct pinmux_cfg_reg pinmux_config_regs[] = { 3157 { PINMUX_CFG_REG("GPSR0", 0xfffc0004, 32, 1, GROUP( 3158 GP_0_31_FN, FN_IP3_31_29, 3159 GP_0_30_FN, FN_IP3_26_24, 3160 GP_0_29_FN, FN_IP3_22_21, 3161 GP_0_28_FN, FN_IP3_14_12, 3162 GP_0_27_FN, FN_IP3_11_9, 3163 GP_0_26_FN, FN_IP3_2_0, 3164 GP_0_25_FN, FN_IP2_30_28, 3165 GP_0_24_FN, FN_IP2_21_19, 3166 GP_0_23_FN, FN_IP2_18_16, 3167 GP_0_22_FN, FN_IP0_30_28, 3168 GP_0_21_FN, FN_IP0_5_3, 3169 GP_0_20_FN, FN_IP1_18_15, 3170 GP_0_19_FN, FN_IP1_14_11, 3171 GP_0_18_FN, FN_IP1_10_7, 3172 GP_0_17_FN, FN_IP1_6_4, 3173 GP_0_16_FN, FN_IP1_3_2, 3174 GP_0_15_FN, FN_IP1_1_0, 3175 GP_0_14_FN, FN_IP0_27_26, 3176 GP_0_13_FN, FN_IP0_25, 3177 GP_0_12_FN, FN_IP0_24_23, 3178 GP_0_11_FN, FN_IP0_22_19, 3179 GP_0_10_FN, FN_IP0_18_16, 3180 GP_0_9_FN, FN_IP0_15_14, 3181 GP_0_8_FN, FN_IP0_13_12, 3182 GP_0_7_FN, FN_IP0_11_10, 3183 GP_0_6_FN, FN_IP0_9_8, 3184 GP_0_5_FN, FN_A19, 3185 GP_0_4_FN, FN_A18, 3186 GP_0_3_FN, FN_A17, 3187 GP_0_2_FN, FN_IP0_7_6, 3188 GP_0_1_FN, FN_AVS2, 3189 GP_0_0_FN, FN_AVS1 )) 3190 }, 3191 { PINMUX_CFG_REG("GPSR1", 0xfffc0008, 32, 1, GROUP( 3192 GP_1_31_FN, FN_IP5_23_21, 3193 GP_1_30_FN, FN_IP5_20_17, 3194 GP_1_29_FN, FN_IP5_16_15, 3195 GP_1_28_FN, FN_IP5_14_13, 3196 GP_1_27_FN, FN_IP5_12_11, 3197 GP_1_26_FN, FN_IP5_10_9, 3198 GP_1_25_FN, FN_IP5_8, 3199 GP_1_24_FN, FN_IP5_7, 3200 GP_1_23_FN, FN_IP5_6, 3201 GP_1_22_FN, FN_IP5_5, 3202 GP_1_21_FN, FN_IP5_4, 3203 GP_1_20_FN, FN_IP5_3, 3204 GP_1_19_FN, FN_IP5_2_0, 3205 GP_1_18_FN, FN_IP4_31_29, 3206 GP_1_17_FN, FN_IP4_28, 3207 GP_1_16_FN, FN_IP4_27, 3208 GP_1_15_FN, FN_IP4_26, 3209 GP_1_14_FN, FN_IP4_25, 3210 GP_1_13_FN, FN_IP4_24, 3211 GP_1_12_FN, FN_IP4_23, 3212 GP_1_11_FN, FN_IP4_22_20, 3213 GP_1_10_FN, FN_IP4_19_17, 3214 GP_1_9_FN, FN_IP4_16, 3215 GP_1_8_FN, FN_IP4_15, 3216 GP_1_7_FN, FN_IP4_14, 3217 GP_1_6_FN, FN_IP4_13, 3218 GP_1_5_FN, FN_IP4_12, 3219 GP_1_4_FN, FN_IP4_11, 3220 GP_1_3_FN, FN_IP4_10_8, 3221 GP_1_2_FN, FN_IP4_7_5, 3222 GP_1_1_FN, FN_IP4_4_2, 3223 GP_1_0_FN, FN_IP4_1_0 )) 3224 }, 3225 { PINMUX_CFG_REG("GPSR2", 0xfffc000c, 32, 1, GROUP( 3226 GP_2_31_FN, FN_IP10_28_26, 3227 GP_2_30_FN, FN_IP10_25_24, 3228 GP_2_29_FN, FN_IP10_23_21, 3229 GP_2_28_FN, FN_IP10_20_18, 3230 GP_2_27_FN, FN_IP10_17_15, 3231 GP_2_26_FN, FN_IP10_14_12, 3232 GP_2_25_FN, FN_IP10_11_9, 3233 GP_2_24_FN, FN_IP10_8_6, 3234 GP_2_23_FN, FN_IP10_5_3, 3235 GP_2_22_FN, FN_IP10_2_0, 3236 GP_2_21_FN, FN_IP9_29_28, 3237 GP_2_20_FN, FN_IP9_27_26, 3238 GP_2_19_FN, FN_IP9_25_24, 3239 GP_2_18_FN, FN_IP9_23_22, 3240 GP_2_17_FN, FN_IP9_21_19, 3241 GP_2_16_FN, FN_IP9_18_16, 3242 GP_2_15_FN, FN_IP9_15_14, 3243 GP_2_14_FN, FN_IP9_13_12, 3244 GP_2_13_FN, FN_IP9_11_10, 3245 GP_2_12_FN, FN_IP9_9_8, 3246 GP_2_11_FN, FN_IP9_7, 3247 GP_2_10_FN, FN_IP9_6, 3248 GP_2_9_FN, FN_IP9_5, 3249 GP_2_8_FN, FN_IP9_4, 3250 GP_2_7_FN, FN_IP9_3_2, 3251 GP_2_6_FN, FN_IP9_1_0, 3252 GP_2_5_FN, FN_IP8_30_28, 3253 GP_2_4_FN, FN_IP8_27_25, 3254 GP_2_3_FN, FN_IP8_24_23, 3255 GP_2_2_FN, FN_IP8_22_21, 3256 GP_2_1_FN, FN_IP8_20, 3257 GP_2_0_FN, FN_IP5_27_24 )) 3258 }, 3259 { PINMUX_CFG_REG("GPSR3", 0xfffc0010, 32, 1, GROUP( 3260 GP_3_31_FN, FN_IP6_3_2, 3261 GP_3_30_FN, FN_IP6_1_0, 3262 GP_3_29_FN, FN_IP5_30_29, 3263 GP_3_28_FN, FN_IP5_28, 3264 GP_3_27_FN, FN_IP1_24_23, 3265 GP_3_26_FN, FN_IP1_22_21, 3266 GP_3_25_FN, FN_IP1_20_19, 3267 GP_3_24_FN, FN_IP7_26_25, 3268 GP_3_23_FN, FN_IP7_24_23, 3269 GP_3_22_FN, FN_IP7_22_21, 3270 GP_3_21_FN, FN_IP7_20_19, 3271 GP_3_20_FN, FN_IP7_30_29, 3272 GP_3_19_FN, FN_IP7_28_27, 3273 GP_3_18_FN, FN_IP7_18_17, 3274 GP_3_17_FN, FN_IP7_16_15, 3275 GP_3_16_FN, FN_IP12_17_15, 3276 GP_3_15_FN, FN_IP12_14_12, 3277 GP_3_14_FN, FN_IP12_11_9, 3278 GP_3_13_FN, FN_IP12_8_6, 3279 GP_3_12_FN, FN_IP12_5_3, 3280 GP_3_11_FN, FN_IP12_2_0, 3281 GP_3_10_FN, FN_IP11_29_27, 3282 GP_3_9_FN, FN_IP11_26_24, 3283 GP_3_8_FN, FN_IP11_23_21, 3284 GP_3_7_FN, FN_IP11_20_18, 3285 GP_3_6_FN, FN_IP11_17_15, 3286 GP_3_5_FN, FN_IP11_14_12, 3287 GP_3_4_FN, FN_IP11_11_9, 3288 GP_3_3_FN, FN_IP11_8_6, 3289 GP_3_2_FN, FN_IP11_5_3, 3290 GP_3_1_FN, FN_IP11_2_0, 3291 GP_3_0_FN, FN_IP10_31_29 )) 3292 }, 3293 { PINMUX_CFG_REG("GPSR4", 0xfffc0014, 32, 1, GROUP( 3294 GP_4_31_FN, FN_IP8_19, 3295 GP_4_30_FN, FN_IP8_18, 3296 GP_4_29_FN, FN_IP8_17_16, 3297 GP_4_28_FN, FN_IP0_2_0, 3298 GP_4_27_FN, FN_USB_PENC1, 3299 GP_4_26_FN, FN_USB_PENC0, 3300 GP_4_25_FN, FN_IP8_15_12, 3301 GP_4_24_FN, FN_IP8_11_8, 3302 GP_4_23_FN, FN_IP8_7_4, 3303 GP_4_22_FN, FN_IP8_3_0, 3304 GP_4_21_FN, FN_IP2_3_0, 3305 GP_4_20_FN, FN_IP1_28_25, 3306 GP_4_19_FN, FN_IP2_15_12, 3307 GP_4_18_FN, FN_IP2_11_8, 3308 GP_4_17_FN, FN_IP2_7_4, 3309 GP_4_16_FN, FN_IP7_14_13, 3310 GP_4_15_FN, FN_IP7_12_10, 3311 GP_4_14_FN, FN_IP7_9_7, 3312 GP_4_13_FN, FN_IP7_6_4, 3313 GP_4_12_FN, FN_IP7_3_2, 3314 GP_4_11_FN, FN_IP7_1_0, 3315 GP_4_10_FN, FN_IP6_30_29, 3316 GP_4_9_FN, FN_IP6_26_25, 3317 GP_4_8_FN, FN_IP6_24_23, 3318 GP_4_7_FN, FN_IP6_22_20, 3319 GP_4_6_FN, FN_IP6_19_18, 3320 GP_4_5_FN, FN_IP6_17_15, 3321 GP_4_4_FN, FN_IP6_14_12, 3322 GP_4_3_FN, FN_IP6_11_9, 3323 GP_4_2_FN, FN_IP6_8, 3324 GP_4_1_FN, FN_IP6_7_6, 3325 GP_4_0_FN, FN_IP6_5_4 )) 3326 }, 3327 { PINMUX_CFG_REG("GPSR5", 0xfffc0018, 32, 1, GROUP( 3328 GP_5_31_FN, FN_IP3_5, 3329 GP_5_30_FN, FN_IP3_4, 3330 GP_5_29_FN, FN_IP3_3, 3331 GP_5_28_FN, FN_IP2_27, 3332 GP_5_27_FN, FN_IP2_26, 3333 GP_5_26_FN, FN_IP2_25, 3334 GP_5_25_FN, FN_IP2_24, 3335 GP_5_24_FN, FN_IP2_23, 3336 GP_5_23_FN, FN_IP2_22, 3337 GP_5_22_FN, FN_IP3_28, 3338 GP_5_21_FN, FN_IP3_27, 3339 GP_5_20_FN, FN_IP3_23, 3340 GP_5_19_FN, FN_EX_WAIT0, 3341 GP_5_18_FN, FN_WE1, 3342 GP_5_17_FN, FN_WE0, 3343 GP_5_16_FN, FN_RD, 3344 GP_5_15_FN, FN_A16, 3345 GP_5_14_FN, FN_A15, 3346 GP_5_13_FN, FN_A14, 3347 GP_5_12_FN, FN_A13, 3348 GP_5_11_FN, FN_A12, 3349 GP_5_10_FN, FN_A11, 3350 GP_5_9_FN, FN_A10, 3351 GP_5_8_FN, FN_A9, 3352 GP_5_7_FN, FN_A8, 3353 GP_5_6_FN, FN_A7, 3354 GP_5_5_FN, FN_A6, 3355 GP_5_4_FN, FN_A5, 3356 GP_5_3_FN, FN_A4, 3357 GP_5_2_FN, FN_A3, 3358 GP_5_1_FN, FN_A2, 3359 GP_5_0_FN, FN_A1 )) 3360 }, 3361 { PINMUX_CFG_REG("GPSR6", 0xfffc001c, 32, 1, GROUP( 3362 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3363 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3364 0, 0, 0, 0, 0, 0, 0, 0, 3365 0, 0, 3366 0, 0, 3367 0, 0, 3368 GP_6_8_FN, FN_IP3_20, 3369 GP_6_7_FN, FN_IP3_19, 3370 GP_6_6_FN, FN_IP3_18, 3371 GP_6_5_FN, FN_IP3_17, 3372 GP_6_4_FN, FN_IP3_16, 3373 GP_6_3_FN, FN_IP3_15, 3374 GP_6_2_FN, FN_IP3_8, 3375 GP_6_1_FN, FN_IP3_7, 3376 GP_6_0_FN, FN_IP3_6 )) 3377 }, 3378 3379 { PINMUX_CFG_REG_VAR("IPSR0", 0xfffc0020, 32, 3380 GROUP(1, 3, 2, 1, 2, 4, 3, 2, 2, 2, 2, 2, 3, 3), 3381 GROUP( 3382 /* IP0_31 [1] */ 3383 0, 0, 3384 /* IP0_30_28 [3] */ 3385 FN_RD_WR, FN_FWE, FN_ATAG0, FN_VI1_R7, 3386 FN_HRTS1, FN_RX4_C, 0, 0, 3387 /* IP0_27_26 [2] */ 3388 FN_CS1_A26, FN_HSPI_TX2, FN_SDSELF_B, 0, 3389 /* IP0_25 [1] */ 3390 FN_CS0, FN_HSPI_CS2_B, 3391 /* IP0_24_23 [2] */ 3392 FN_CLKOUT, FN_TX3C_IRDA_TX_C, FN_PWM0_B, 0, 3393 /* IP0_22_19 [4] */ 3394 FN_A25, FN_SD1_WP, FN_MMC0_D5, FN_FD5, 3395 FN_HSPI_RX2, FN_VI1_R3, FN_TX5_B, FN_SSI_SDATA7_B, 3396 FN_CTS0_B, 0, 0, 0, 3397 0, 0, 0, 0, 3398 /* IP0_18_16 [3] */ 3399 FN_A24, FN_SD1_CD, FN_MMC0_D4, FN_FD4, 3400 FN_HSPI_CS2, FN_VI1_R2, FN_SSI_WS78_B, 0, 3401 /* IP0_15_14 [2] */ 3402 FN_A23, FN_FCLE, FN_HSPI_CLK2, FN_VI1_R1, 3403 /* IP0_13_12 [2] */ 3404 FN_A22, FN_RX5_D, FN_HSPI_RX2_B, FN_VI1_R0, 3405 /* IP0_11_10 [2] */ 3406 FN_A21, FN_SCK5_D, FN_HSPI_CLK2_B, 0, 3407 /* IP0_9_8 [2] */ 3408 FN_A20, FN_TX5_D, FN_HSPI_TX2_B, 0, 3409 /* IP0_7_6 [2] */ 3410 FN_A0, FN_SD1_DAT3, FN_MMC0_D3, FN_FD3, 3411 /* IP0_5_3 [3] */ 3412 FN_BS, FN_SD1_DAT2, FN_MMC0_D2, FN_FD2, 3413 FN_ATADIR0, FN_SDSELF, FN_HCTS1, FN_TX4_C, 3414 /* IP0_2_0 [3] */ 3415 FN_USB_PENC2, FN_SCK0, FN_PWM1, FN_PWMFSW0, 3416 FN_SCIF_CLK, FN_TCLK0_C, 0, 0 )) 3417 }, 3418 { PINMUX_CFG_REG_VAR("IPSR1", 0xfffc0024, 32, 3419 GROUP(3, 4, 2, 2, 2, 4, 4, 4, 3, 2, 2), 3420 GROUP( 3421 /* IP1_31_29 [3] */ 3422 0, 0, 0, 0, 0, 0, 0, 0, 3423 /* IP1_28_25 [4] */ 3424 FN_HTX0, FN_TX1, FN_SDATA, FN_CTS0_C, 3425 FN_SUB_TCK, FN_CC5_STATE2, FN_CC5_STATE10, FN_CC5_STATE18, 3426 FN_CC5_STATE26, FN_CC5_STATE34, 0, 0, 3427 0, 0, 0, 0, 3428 /* IP1_24_23 [2] */ 3429 FN_MLB_DAT, FN_PWM4, FN_RX4, 0, 3430 /* IP1_22_21 [2] */ 3431 FN_MLB_SIG, FN_PWM3, FN_TX4, 0, 3432 /* IP1_20_19 [2] */ 3433 FN_MLB_CLK, FN_PWM2, FN_SCK4, 0, 3434 /* IP1_18_15 [4] */ 3435 FN_EX_CS5, FN_SD1_DAT1, FN_MMC0_D1, FN_FD1, 3436 FN_ATAWR0, FN_VI1_R6, FN_HRX1, FN_RX2_E, 3437 FN_RX0_B, FN_SSI_WS9, 0, 0, 3438 0, 0, 0, 0, 3439 /* IP1_14_11 [4] */ 3440 FN_EX_CS4, FN_SD1_DAT0, FN_MMC0_D0, FN_FD0, 3441 FN_ATARD0, FN_VI1_R5, FN_SCK5_B, FN_HTX1, 3442 FN_TX2_E, FN_TX0_B, FN_SSI_SCK9, 0, 3443 0, 0, 0, 0, 3444 /* IP1_10_7 [4] */ 3445 FN_EX_CS3, FN_SD1_CMD, FN_MMC0_CMD, FN_FRE, 3446 FN_ATACS10, FN_VI1_R4, FN_RX5_B, FN_HSCK1, 3447 FN_SSI_SDATA8_B, FN_RTS0_B_TANS_B, FN_SSI_SDATA9, 0, 3448 0, 0, 0, 0, 3449 /* IP1_6_4 [3] */ 3450 FN_EX_CS2, FN_SD1_CLK, FN_MMC0_CLK, FN_FALE, 3451 FN_ATACS00, 0, 0, 0, 3452 /* IP1_3_2 [2] */ 3453 FN_EX_CS1, FN_MMC0_D7, FN_FD7, 0, 3454 /* IP1_1_0 [2] */ 3455 FN_EX_CS0, FN_RX3_C_IRDA_RX_C, FN_MMC0_D6, FN_FD6 )) 3456 }, 3457 { PINMUX_CFG_REG_VAR("IPSR2", 0xfffc0028, 32, 3458 GROUP(1, 3, 1, 1, 1, 1, 1, 1, 3, 3, 4, 4, 4, 4), 3459 GROUP( 3460 /* IP2_31 [1] */ 3461 0, 0, 3462 /* IP2_30_28 [3] */ 3463 FN_DU0_DG0, FN_LCDOUT8, FN_DREQ1, FN_SCL2, 3464 FN_AUDATA2, 0, 0, 0, 3465 /* IP2_27 [1] */ 3466 FN_DU0_DR7, FN_LCDOUT7, 3467 /* IP2_26 [1] */ 3468 FN_DU0_DR6, FN_LCDOUT6, 3469 /* IP2_25 [1] */ 3470 FN_DU0_DR5, FN_LCDOUT5, 3471 /* IP2_24 [1] */ 3472 FN_DU0_DR4, FN_LCDOUT4, 3473 /* IP2_23 [1] */ 3474 FN_DU0_DR3, FN_LCDOUT3, 3475 /* IP2_22 [1] */ 3476 FN_DU0_DR2, FN_LCDOUT2, 3477 /* IP2_21_19 [3] */ 3478 FN_DU0_DR1, FN_LCDOUT1, FN_DACK0, FN_DRACK0, 3479 FN_GPS_SIGN_B, FN_AUDATA1, FN_RX5_C, 0, 3480 /* IP2_18_16 [3] */ 3481 FN_DU0_DR0, FN_LCDOUT0, FN_DREQ0, FN_GPS_CLK_B, 3482 FN_AUDATA0, FN_TX5_C, 0, 0, 3483 /* IP2_15_12 [4] */ 3484 FN_HRTS0, FN_RTS1_TANS, FN_MDATA, FN_TX0_C, 3485 FN_SUB_TMS, FN_CC5_STATE1, FN_CC5_STATE9, FN_CC5_STATE17, 3486 FN_CC5_STATE25, FN_CC5_STATE33, 0, 0, 3487 0, 0, 0, 0, 3488 /* IP2_11_8 [4] */ 3489 FN_HCTS0, FN_CTS1, FN_STM, FN_PWM0_D, 3490 FN_RX0_C, FN_SCIF_CLK_C, FN_SUB_TRST, FN_TCLK1_B, 3491 FN_CC5_OSCOUT, 0, 0, 0, 3492 0, 0, 0, 0, 3493 /* IP2_7_4 [4] */ 3494 FN_HSCK0, FN_SCK1, FN_MTS, FN_PWM5, 3495 FN_SCK0_C, FN_SSI_SDATA9_B, FN_SUB_TDO, FN_CC5_STATE0, 3496 FN_CC5_STATE8, FN_CC5_STATE16, FN_CC5_STATE24, FN_CC5_STATE32, 3497 0, 0, 0, 0, 3498 /* IP2_3_0 [4] */ 3499 FN_HRX0, FN_RX1, FN_SCKZ, FN_RTS0_C_TANS_C, 3500 FN_SUB_TDI, FN_CC5_STATE3, FN_CC5_STATE11, FN_CC5_STATE19, 3501 FN_CC5_STATE27, FN_CC5_STATE35, 0, 0, 3502 0, 0, 0, 0 )) 3503 }, 3504 { PINMUX_CFG_REG_VAR("IPSR3", 0xfffc002c, 32, 3505 GROUP(3, 1, 1, 3, 1, 2, 1, 1, 1, 1, 1, 1, 3506 3, 3, 1, 1, 1, 1, 1, 1, 3), 3507 GROUP( 3508 /* IP3_31_29 [3] */ 3509 FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, FN_CAN1_TX, FN_TX2_C, 3510 FN_SCL2_C, FN_REMOCON, 0, 0, 3511 /* IP3_28 [1] */ 3512 FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, 3513 /* IP3_27 [1] */ 3514 FN_DU0_EXHSYNC_DU0_HSYNC, FN_QSTH_QHS, 3515 /* IP3_26_24 [3] */ 3516 FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE, FN_RX3_D_IRDA_RX_D, FN_SDA3_B, 3517 FN_SDA2_C, FN_DACK0_B, FN_DRACK0_B, 0, 3518 /* IP3_23 [1] */ 3519 FN_DU0_DOTCLKOUT0, FN_QCLK, 3520 /* IP3_22_21 [2] */ 3521 FN_DU0_DOTCLKIN, FN_QSTVA_QVS, FN_TX3_D_IRDA_TX_D, FN_SCL3_B, 3522 /* IP3_20 [1] */ 3523 FN_DU0_DB7, FN_LCDOUT23, 3524 /* IP3_19 [1] */ 3525 FN_DU0_DB6, FN_LCDOUT22, 3526 /* IP3_18 [1] */ 3527 FN_DU0_DB5, FN_LCDOUT21, 3528 /* IP3_17 [1] */ 3529 FN_DU0_DB4, FN_LCDOUT20, 3530 /* IP3_16 [1] */ 3531 FN_DU0_DB3, FN_LCDOUT19, 3532 /* IP3_15 [1] */ 3533 FN_DU0_DB2, FN_LCDOUT18, 3534 /* IP3_14_12 [3] */ 3535 FN_DU0_DB1, FN_LCDOUT17, FN_EX_WAIT2, FN_SDA1, 3536 FN_GPS_MAG_B, FN_AUDATA5, FN_SCK5_C, 0, 3537 /* IP3_11_9 [3] */ 3538 FN_DU0_DB0, FN_LCDOUT16, FN_EX_WAIT1, FN_SCL1, 3539 FN_TCLK1, FN_AUDATA4, 0, 0, 3540 /* IP3_8 [1] */ 3541 FN_DU0_DG7, FN_LCDOUT15, 3542 /* IP3_7 [1] */ 3543 FN_DU0_DG6, FN_LCDOUT14, 3544 /* IP3_6 [1] */ 3545 FN_DU0_DG5, FN_LCDOUT13, 3546 /* IP3_5 [1] */ 3547 FN_DU0_DG4, FN_LCDOUT12, 3548 /* IP3_4 [1] */ 3549 FN_DU0_DG3, FN_LCDOUT11, 3550 /* IP3_3 [1] */ 3551 FN_DU0_DG2, FN_LCDOUT10, 3552 /* IP3_2_0 [3] */ 3553 FN_DU0_DG1, FN_LCDOUT9, FN_DACK1, FN_SDA2, 3554 FN_AUDATA3, 0, 0, 0 )) 3555 }, 3556 { PINMUX_CFG_REG_VAR("IPSR4", 0xfffc0030, 32, 3557 GROUP(3, 1, 1, 1, 1, 1, 1, 3, 3, 1, 1, 1, 3558 1, 1, 1, 3, 3, 3, 2), 3559 GROUP( 3560 /* IP4_31_29 [3] */ 3561 FN_DU1_DB0, FN_VI2_DATA4_VI2_B4, FN_SCL2_B, FN_SD3_DAT0, 3562 FN_TX5, FN_SCK0_D, 0, 0, 3563 /* IP4_28 [1] */ 3564 FN_DU1_DG7, FN_VI2_R3, 3565 /* IP4_27 [1] */ 3566 FN_DU1_DG6, FN_VI2_R2, 3567 /* IP4_26 [1] */ 3568 FN_DU1_DG5, FN_VI2_R1, 3569 /* IP4_25 [1] */ 3570 FN_DU1_DG4, FN_VI2_R0, 3571 /* IP4_24 [1] */ 3572 FN_DU1_DG3, FN_VI2_G7, 3573 /* IP4_23 [1] */ 3574 FN_DU1_DG2, FN_VI2_G6, 3575 /* IP4_22_20 [3] */ 3576 FN_DU1_DG1, FN_VI2_DATA3_VI2_B3, FN_SDA1_B, FN_SD3_DAT3, 3577 FN_SCK5, FN_AUDATA7, FN_RX0_D, 0, 3578 /* IP4_19_17 [3] */ 3579 FN_DU1_DG0, FN_VI2_DATA2_VI2_B2, FN_SCL1_B, FN_SD3_DAT2, 3580 FN_SCK3_E, FN_AUDATA6, FN_TX0_D, 0, 3581 /* IP4_16 [1] */ 3582 FN_DU1_DR7, FN_VI2_G5, 3583 /* IP4_15 [1] */ 3584 FN_DU1_DR6, FN_VI2_G4, 3585 /* IP4_14 [1] */ 3586 FN_DU1_DR5, FN_VI2_G3, 3587 /* IP4_13 [1] */ 3588 FN_DU1_DR4, FN_VI2_G2, 3589 /* IP4_12 [1] */ 3590 FN_DU1_DR3, FN_VI2_G1, 3591 /* IP4_11 [1] */ 3592 FN_DU1_DR2, FN_VI2_G0, 3593 /* IP4_10_8 [3] */ 3594 FN_DU1_DR1, FN_VI2_DATA1_VI2_B1, FN_PWM0, FN_SD3_CMD, 3595 FN_RX3_E_IRDA_RX_E, FN_AUDSYNC, FN_CTS0_D, 0, 3596 /* IP4_7_5 [3] */ 3597 FN_DU1_DR0, FN_VI2_DATA0_VI2_B0, FN_PWM6, FN_SD3_CLK, 3598 FN_TX3_E_IRDA_TX_E, FN_AUDCK, FN_PWMFSW0_B, 0, 3599 /* IP4_4_2 [3] */ 3600 FN_DU0_CDE, FN_QPOLB, FN_CAN1_RX, FN_RX2_C, 3601 FN_DREQ0_B, FN_SSI_SCK78_B, FN_SCK0_B, 0, 3602 /* IP4_1_0 [2] */ 3603 FN_DU0_DISP, FN_QPOLA, FN_CAN_CLK_C, FN_SCK2_C )) 3604 }, 3605 { PINMUX_CFG_REG_VAR("IPSR5", 0xfffc0034, 32, 3606 GROUP(1, 2, 1, 4, 3, 4, 2, 2, 2, 2, 1, 1, 3607 1, 1, 1, 1, 3), 3608 GROUP( 3609 /* IP5_31 [1] */ 3610 0, 0, 3611 /* IP5_30_29 [2] */ 3612 FN_AUDIO_CLKB, FN_USB_OVC2, FN_CAN_DEBUGOUT0, FN_MOUT0, 3613 /* IP5_28 [1] */ 3614 FN_AUDIO_CLKA, FN_CAN_TXCLK, 3615 /* IP5_27_24 [4] */ 3616 FN_DU1_CDE, FN_VI2_DATA7_VI2_B7, FN_RX3_B_IRDA_RX_B, FN_SD3_WP, 3617 FN_HSPI_RX1, FN_VI1_FIELD, FN_VI3_FIELD, FN_AUDIO_CLKOUT, 3618 FN_RX2_D, FN_GPS_CLK_C, FN_GPS_CLK_D, 0, 3619 0, 0, 0, 0, 3620 /* IP5_23_21 [3] */ 3621 FN_DU1_DISP, FN_VI2_DATA6_VI2_B6, FN_TCLK0, FN_QSTVA_B_QVS_B, 3622 FN_HSPI_CLK1, FN_SCK2_D, FN_AUDIO_CLKOUT_B, FN_GPS_MAG_D, 3623 /* IP5_20_17 [4] */ 3624 FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_VI2_CLK, FN_TX3_B_IRDA_TX_B, 3625 FN_SD3_CD, FN_HSPI_TX1, FN_VI1_CLKENB, FN_VI3_CLKENB, 3626 FN_AUDIO_CLKC, FN_TX2_D, FN_SPEEDIN, FN_GPS_SIGN_D, 0, 3627 0, 0, 0, 0, 3628 /* IP5_16_15 [2] */ 3629 FN_DU1_EXVSYNC_DU1_VSYNC, FN_VI2_VSYNC, FN_VI3_VSYNC, 0, 3630 /* IP5_14_13 [2] */ 3631 FN_DU1_EXHSYNC_DU1_HSYNC, FN_VI2_HSYNC, FN_VI3_HSYNC, 0, 3632 /* IP5_12_11 [2] */ 3633 FN_DU1_DOTCLKOUT, FN_VI2_FIELD, FN_SDA1_D, 0, 3634 /* IP5_10_9 [2] */ 3635 FN_DU1_DOTCLKIN, FN_VI2_CLKENB, FN_HSPI_CS1, FN_SCL1_D, 3636 /* IP5_8 [1] */ 3637 FN_DU1_DB7, FN_SDA2_D, 3638 /* IP5_7 [1] */ 3639 FN_DU1_DB6, FN_SCL2_D, 3640 /* IP5_6 [1] */ 3641 FN_DU1_DB5, FN_VI2_R7, 3642 /* IP5_5 [1] */ 3643 FN_DU1_DB4, FN_VI2_R6, 3644 /* IP5_4 [1] */ 3645 FN_DU1_DB3, FN_VI2_R5, 3646 /* IP5_3 [1] */ 3647 FN_DU1_DB2, FN_VI2_R4, 3648 /* IP5_2_0 [3] */ 3649 FN_DU1_DB1, FN_VI2_DATA5_VI2_B5, FN_SDA2_B, FN_SD3_DAT1, 3650 FN_RX5, FN_RTS0_D_TANS_D, 0, 0 )) 3651 }, 3652 { PINMUX_CFG_REG_VAR("IPSR6", 0xfffc0038, 32, 3653 GROUP(1, 2, 2, 2, 2, 3, 2, 3, 3, 3, 1, 2, 3654 2, 2, 2), 3655 GROUP( 3656 /* IP6_31 [1] */ 3657 0, 0, 3658 /* IP6_30_29 [2] */ 3659 FN_SSI_SCK6, FN_ADICHS0, FN_CAN0_TX, FN_IERX_B, 3660 /* IP_28_27 [2] */ 3661 0, 0, 0, 0, 3662 /* IP6_26_25 [2] */ 3663 FN_SSI_SDATA5, FN_ADIDATA, FN_CAN_DEBUGOUT12, FN_RX3_IRDA_RX, 3664 /* IP6_24_23 [2] */ 3665 FN_SSI_WS5, FN_ADICS_SAMP, FN_CAN_DEBUGOUT11, FN_TX3_IRDA_TX, 3666 /* IP6_22_20 [3] */ 3667 FN_SSI_SCK5, FN_ADICLK, FN_CAN_DEBUGOUT10, FN_SCK3, 3668 FN_TCLK0_D, 0, 0, 0, 3669 /* IP6_19_18 [2] */ 3670 FN_SSI_SDATA4, FN_CAN_DEBUGOUT9, FN_SSI_SDATA9_C, 0, 3671 /* IP6_17_15 [3] */ 3672 FN_SSI_SDATA3, FN_PWM0_C, FN_CAN_DEBUGOUT8, FN_CAN_CLK_B, 3673 FN_IECLK, FN_SCIF_CLK_B, FN_TCLK0_B, 0, 3674 /* IP6_14_12 [3] */ 3675 FN_SSI_WS34, FN_CAN_DEBUGOUT7, FN_CAN0_RX_B, FN_IETX, 3676 FN_SSI_WS9_C, 0, 0, 0, 3677 /* IP6_11_9 [3] */ 3678 FN_SSI_SCK34, FN_CAN_DEBUGOUT6, FN_CAN0_TX_B, FN_IERX, 3679 FN_SSI_SCK9_C, 0, 0, 0, 3680 /* IP6_8 [1] */ 3681 FN_SSI_SDATA2, FN_CAN_DEBUGOUT5, 3682 /* IP6_7_6 [2] */ 3683 FN_SSI_SDATA1, FN_CAN_DEBUGOUT4, FN_MOUT6, 0, 3684 /* IP6_5_4 [2] */ 3685 FN_SSI_SDATA0, FN_CAN_DEBUGOUT3, FN_MOUT5, 0, 3686 /* IP6_3_2 [2] */ 3687 FN_SSI_WS0129, FN_CAN_DEBUGOUT2, FN_MOUT2, 0, 3688 /* IP6_1_0 [2] */ 3689 FN_SSI_SCK0129, FN_CAN_DEBUGOUT1, FN_MOUT1, 0 )) 3690 }, 3691 { PINMUX_CFG_REG_VAR("IPSR7", 0xfffc003c, 32, 3692 GROUP(1, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 3693 3, 2, 2), 3694 GROUP( 3695 /* IP7_31 [1] */ 3696 0, 0, 3697 /* IP7_30_29 [2] */ 3698 FN_SD0_WP, FN_DACK2, FN_CTS1_B, 0, 3699 /* IP7_28_27 [2] */ 3700 FN_SD0_CD, FN_DREQ2, FN_RTS1_B_TANS_B, 0, 3701 /* IP7_26_25 [2] */ 3702 FN_SD0_DAT3, FN_ATAWR1, FN_RX2_B, FN_CC5_TDI, 3703 /* IP7_24_23 [2] */ 3704 FN_SD0_DAT2, FN_ATARD1, FN_TX2_B, FN_CC5_TCK, 3705 /* IP7_22_21 [2] */ 3706 FN_SD0_DAT1, FN_ATAG1, FN_SCK2_B, FN_CC5_TMS, 3707 /* IP7_20_19 [2] */ 3708 FN_SD0_DAT0, FN_ATADIR1, FN_RX1_B, FN_CC5_TRST, 3709 /* IP7_18_17 [2] */ 3710 FN_SD0_CMD, FN_ATACS11, FN_TX1_B, FN_CC5_TDO, 3711 /* IP7_16_15 [2] */ 3712 FN_SD0_CLK, FN_ATACS01, FN_SCK1_B, 0, 3713 /* IP7_14_13 [2] */ 3714 FN_SSI_SDATA8, FN_VSP, FN_IRQ3_B, FN_HSPI_RX1_C, 3715 /* IP7_12_10 [3] */ 3716 FN_SSI_SDATA7, FN_CAN_DEBUGOUT15, FN_IRQ2_B, FN_TCLK1_C, 3717 FN_HSPI_TX1_C, 0, 0, 0, 3718 /* IP7_9_7 [3] */ 3719 FN_SSI_WS78, FN_CAN_DEBUGOUT14, FN_IRQ1_B, FN_SSI_WS9_B, 3720 FN_HSPI_CS1_C, 0, 0, 0, 3721 /* IP7_6_4 [3] */ 3722 FN_SSI_SCK78, FN_CAN_DEBUGOUT13, FN_IRQ0_B, FN_SSI_SCK9_B, 3723 FN_HSPI_CLK1_C, 0, 0, 0, 3724 /* IP7_3_2 [2] */ 3725 FN_SSI_SDATA6, FN_ADICHS2, FN_CAN_CLK, FN_IECLK_B, 3726 /* IP7_1_0 [2] */ 3727 FN_SSI_WS6, FN_ADICHS1, FN_CAN0_RX, FN_IETX_B )) 3728 }, 3729 { PINMUX_CFG_REG_VAR("IPSR8", 0xfffc0040, 32, 3730 GROUP(1, 3, 3, 2, 2, 1, 1, 1, 2, 4, 4, 4, 4), 3731 GROUP( 3732 /* IP8_31 [1] */ 3733 0, 0, 3734 /* IP8_30_28 [3] */ 3735 FN_VI0_VSYNC, FN_VI0_DATA1_B_VI0_B1_B, FN_RTS1_C_TANS_C, FN_RX4_D, 3736 FN_PWMFSW0_C, 0, 0, 0, 3737 /* IP8_27_25 [3] */ 3738 FN_VI0_HSYNC, FN_VI0_DATA0_B_VI0_B0_B, FN_CTS1_C, FN_TX4_D, 3739 FN_MMC1_CMD, FN_HSCK1_B, 0, 0, 3740 /* IP8_24_23 [2] */ 3741 FN_VI0_FIELD, FN_RX1_C, FN_HRX1_B, 0, 3742 /* IP8_22_21 [2] */ 3743 FN_VI0_CLKENB, FN_TX1_C, FN_HTX1_B, FN_MT1_SYNC, 3744 /* IP8_20 [1] */ 3745 FN_VI0_CLK, FN_MMC1_CLK, 3746 /* IP8_19 [1] */ 3747 FN_FMIN, FN_RDS_DATA, 3748 /* IP8_18 [1] */ 3749 FN_BPFCLK, FN_PCMWE, 3750 /* IP8_17_16 [2] */ 3751 FN_FMCLK, FN_RDS_CLK, FN_PCMOE, 0, 3752 /* IP8_15_12 [4] */ 3753 FN_HSPI_RX0, FN_RX0, FN_CAN_STEP0, FN_AD_NCS, 3754 FN_CC5_STATE7, FN_CC5_STATE15, FN_CC5_STATE23, FN_CC5_STATE31, 3755 FN_CC5_STATE39, 0, 0, 0, 3756 0, 0, 0, 0, 3757 /* IP8_11_8 [4] */ 3758 FN_HSPI_TX0, FN_TX0, FN_CAN_DEBUG_HW_TRIGGER, FN_AD_DO, 3759 FN_CC5_STATE6, FN_CC5_STATE14, FN_CC5_STATE22, FN_CC5_STATE30, 3760 FN_CC5_STATE38, 0, 0, 0, 3761 0, 0, 0, 0, 3762 /* IP8_7_4 [4] */ 3763 FN_HSPI_CS0, FN_RTS0_TANS, FN_USB_OVC1, FN_AD_DI, 3764 FN_CC5_STATE5, FN_CC5_STATE13, FN_CC5_STATE21, FN_CC5_STATE29, 3765 FN_CC5_STATE37, 0, 0, 0, 3766 0, 0, 0, 0, 3767 /* IP8_3_0 [4] */ 3768 FN_HSPI_CLK0, FN_CTS0, FN_USB_OVC0, FN_AD_CLK, 3769 FN_CC5_STATE4, FN_CC5_STATE12, FN_CC5_STATE20, FN_CC5_STATE28, 3770 FN_CC5_STATE36, 0, 0, 0, 3771 0, 0, 0, 0 )) 3772 }, 3773 { PINMUX_CFG_REG_VAR("IPSR9", 0xfffc0044, 32, 3774 GROUP(2, 2, 2, 2, 2, 3, 3, 2, 2, 2, 2, 1, 3775 1, 1, 1, 2, 2), 3776 GROUP( 3777 /* IP9_31_30 [2] */ 3778 0, 0, 0, 0, 3779 /* IP9_29_28 [2] */ 3780 FN_VI0_G7, FN_ETH_RXD1, FN_SD2_DAT3_B, FN_ARM_TRACEDATA_9, 3781 /* IP9_27_26 [2] */ 3782 FN_VI0_G6, FN_ETH_RXD0, FN_SD2_DAT2_B, FN_ARM_TRACEDATA_8, 3783 /* IP9_25_24 [2] */ 3784 FN_VI0_G5, FN_ETH_RX_ER, FN_SD2_DAT1_B, FN_ARM_TRACEDATA_7, 3785 /* IP9_23_22 [2] */ 3786 FN_VI0_G4, FN_ETH_TX_EN, FN_SD2_DAT0_B, FN_ARM_TRACEDATA_6, 3787 /* IP9_21_19 [3] */ 3788 FN_VI0_G3, FN_ETH_CRS_DV, FN_MMC1_D7, FN_ARM_TRACEDATA_5, 3789 FN_TS_SDAT0, 0, 0, 0, 3790 /* IP9_18_16 [3] */ 3791 FN_VI0_G2, FN_ETH_TXD1, FN_MMC1_D6, FN_ARM_TRACEDATA_4, 3792 FN_TS_SPSYNC0, 0, 0, 0, 3793 /* IP9_15_14 [2] */ 3794 FN_VI0_G1, FN_SSI_WS78_C, FN_IRQ1, FN_ARM_TRACEDATA_3, 3795 /* IP9_13_12 [2] */ 3796 FN_VI0_G0, FN_SSI_SCK78_C, FN_IRQ0, FN_ARM_TRACEDATA_2, 3797 /* IP9_11_10 [2] */ 3798 FN_VI0_DATA7_VI0_B7, FN_MMC1_D5, FN_ARM_TRACEDATA_1, 0, 3799 /* IP9_9_8 [2] */ 3800 FN_VI0_DATA6_VI0_B6, FN_MMC1_D4, FN_ARM_TRACEDATA_0, 0, 3801 /* IP9_7 [1] */ 3802 FN_VI0_DATA5_VI0_B5, FN_MMC1_D3, 3803 /* IP9_6 [1] */ 3804 FN_VI0_DATA4_VI0_B4, FN_MMC1_D2, 3805 /* IP9_5 [1] */ 3806 FN_VI0_DATA3_VI0_B3, FN_MMC1_D1, 3807 /* IP9_4 [1] */ 3808 FN_VI0_DATA2_VI0_B2, FN_MMC1_D0, 3809 /* IP9_3_2 [2] */ 3810 FN_VI0_DATA1_VI0_B1, FN_HCTS1_B, FN_MT1_PWM, 0, 3811 /* IP9_1_0 [2] */ 3812 FN_VI0_DATA0_VI0_B0, FN_HRTS1_B, FN_MT1_VCXO, 0 )) 3813 }, 3814 { PINMUX_CFG_REG_VAR("IPSR10", 0xfffc0048, 32, 3815 GROUP(3, 3, 2, 3, 3, 3, 3, 3, 3, 3, 3), 3816 GROUP( 3817 /* IP10_31_29 [3] */ 3818 FN_VI1_VSYNC, FN_AUDIO_CLKOUT_C, FN_SSI_WS4, FN_SIM_CLK, 3819 FN_GPS_MAG_C, FN_SPV_TRST, FN_SCL3, 0, 3820 /* IP10_28_26 [3] */ 3821 FN_VI1_HSYNC, FN_VI3_CLK, FN_SSI_SCK4, FN_GPS_SIGN_C, 3822 FN_PWMFSW0_E, 0, 0, 0, 3823 /* IP10_25_24 [2] */ 3824 FN_VI1_CLK, FN_SIM_D, FN_SDA3, 0, 3825 /* IP10_23_21 [3] */ 3826 FN_VI0_R7, FN_ETH_MDIO, FN_DACK2_C, FN_HSPI_RX1_B, 3827 FN_SCIF_CLK_D, FN_TRACECTL, FN_MT1_PEN, 0, 3828 /* IP10_20_18 [3] */ 3829 FN_VI0_R6, FN_ETH_MDC, FN_DREQ2_C, FN_HSPI_TX1_B, 3830 FN_TRACECLK, FN_MT1_BEN, FN_PWMFSW0_D, 0, 3831 /* IP10_17_15 [3] */ 3832 FN_VI0_R5, FN_ETH_TXD0, FN_SD2_WP_B, FN_HSPI_CS1_B, 3833 FN_ARM_TRACEDATA_15, FN_MT1_D, FN_TS_SDEN0, 0, 3834 /* IP10_14_12 [3] */ 3835 FN_VI0_R4, FN_ETH_REFCLK, FN_SD2_CD_B, FN_HSPI_CLK1_B, 3836 FN_ARM_TRACEDATA_14, FN_MT1_CLK, FN_TS_SCK0, 0, 3837 /* IP10_11_9 [3] */ 3838 FN_VI0_R3, FN_ETH_MAGIC, FN_SD2_CMD_B, FN_IRQ3, 3839 FN_ARM_TRACEDATA_13, 0, 0, 0, 3840 /* IP10_8_6 [3] */ 3841 FN_VI0_R2, FN_ETH_LINK, FN_SD2_CLK_B, FN_IRQ2, 3842 FN_ARM_TRACEDATA_12, 0, 0, 0, 3843 /* IP10_5_3 [3] */ 3844 FN_VI0_R1, FN_SSI_SDATA8_C, FN_DACK1_B, FN_ARM_TRACEDATA_11, 3845 FN_DACK0_C, FN_DRACK0_C, 0, 0, 3846 /* IP10_2_0 [3] */ 3847 FN_VI0_R0, FN_SSI_SDATA7_C, FN_SCK1_C, FN_DREQ1_B, 3848 FN_ARM_TRACEDATA_10, FN_DREQ0_C, 0, 0 )) 3849 }, 3850 { PINMUX_CFG_REG_VAR("IPSR11", 0xfffc004c, 32, 3851 GROUP(2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3), 3852 GROUP( 3853 /* IP11_31_30 [2] */ 3854 0, 0, 0, 0, 3855 /* IP11_29_27 [3] */ 3856 FN_VI1_G1, FN_VI3_DATA1, FN_SSI_SCK1, FN_TS_SDEN1, 3857 FN_DACK2_B, FN_RX2, FN_HRTS0_B, 0, 3858 /* IP11_26_24 [3] */ 3859 FN_VI1_G0, FN_VI3_DATA0, 0, FN_TS_SCK1, 3860 FN_DREQ2_B, FN_TX2, FN_SPA_TDO, FN_HCTS0_B, 3861 /* IP11_23_21 [3] */ 3862 FN_VI1_DATA7_VI1_B7, FN_SD2_WP, FN_MT0_PWM, FN_SPA_TDI, 3863 FN_HSPI_RX1_D, 0, 0, 0, 3864 /* IP11_20_18 [3] */ 3865 FN_VI1_DATA6_VI1_B6, FN_SD2_CD, FN_MT0_VCXO, FN_SPA_TMS, 3866 FN_HSPI_TX1_D, 0, 0, 0, 3867 /* IP11_17_15 [3] */ 3868 FN_VI1_DATA5_VI1_B5, FN_SD2_CMD, FN_MT0_SYNC, FN_SPA_TCK, 3869 FN_HSPI_CS1_D, FN_ADICHS2_B, 0, 0, 3870 /* IP11_14_12 [3] */ 3871 FN_VI1_DATA4_VI1_B4, FN_SD2_CLK, FN_MT0_PEN, FN_SPA_TRST, 3872 FN_HSPI_CLK1_D, FN_ADICHS1_B, 0, 0, 3873 /* IP11_11_9 [3] */ 3874 FN_VI1_DATA3_VI1_B3, FN_SD2_DAT3, FN_MT0_BEN, FN_SPV_TDO, 3875 FN_ADICHS0_B, 0, 0, 0, 3876 /* IP11_8_6 [3] */ 3877 FN_VI1_DATA2_VI1_B2, FN_SD2_DAT2, FN_MT0_D, FN_SPVTDI, 3878 FN_ADIDATA_B, 0, 0, 0, 3879 /* IP11_5_3 [3] */ 3880 FN_VI1_DATA1_VI1_B1, FN_SD2_DAT1, FN_MT0_CLK, FN_SPV_TMS, 3881 FN_ADICS_B_SAMP_B, 0, 0, 0, 3882 /* IP11_2_0 [3] */ 3883 FN_VI1_DATA0_VI1_B0, FN_SD2_DAT0, FN_SIM_RST, FN_SPV_TCK, 3884 FN_ADICLK_B, 0, 0, 0 )) 3885 }, 3886 { PINMUX_CFG_REG_VAR("IPSR12", 0xfffc0050, 32, 3887 GROUP(4, 4, 4, 2, 3, 3, 3, 3, 3, 3), 3888 GROUP( 3889 /* IP12_31_28 [4] */ 3890 0, 0, 0, 0, 0, 0, 0, 0, 3891 0, 0, 0, 0, 0, 0, 0, 0, 3892 /* IP12_27_24 [4] */ 3893 0, 0, 0, 0, 0, 0, 0, 0, 3894 0, 0, 0, 0, 0, 0, 0, 0, 3895 /* IP12_23_20 [4] */ 3896 0, 0, 0, 0, 0, 0, 0, 0, 3897 0, 0, 0, 0, 0, 0, 0, 0, 3898 /* IP12_19_18 [2] */ 3899 0, 0, 0, 0, 3900 /* IP12_17_15 [3] */ 3901 FN_VI1_G7, FN_VI3_DATA7, FN_GPS_MAG, FN_FCE, 3902 FN_SCK4_B, 0, 0, 0, 3903 /* IP12_14_12 [3] */ 3904 FN_VI1_G6, FN_VI3_DATA6, FN_GPS_SIGN, FN_FRB, 3905 FN_RX4_B, FN_SIM_CLK_B, 0, 0, 3906 /* IP12_11_9 [3] */ 3907 FN_VI1_G5, FN_VI3_DATA5, FN_GPS_CLK, FN_FSE, 3908 FN_TX4_B, FN_SIM_D_B, 0, 0, 3909 /* IP12_8_6 [3] */ 3910 FN_VI1_G4, FN_VI3_DATA4, FN_SSI_WS2, FN_SDA1_C, 3911 FN_SIM_RST_B, FN_HRX0_B, 0, 0, 3912 /* IP12_5_3 [3] */ 3913 FN_VI1_G3, FN_VI3_DATA3, FN_SSI_SCK2, FN_TS_SDAT1, 3914 FN_SCL1_C, FN_HTX0_B, 0, 0, 3915 /* IP12_2_0 [3] */ 3916 FN_VI1_G2, FN_VI3_DATA2, FN_SSI_WS1, FN_TS_SPSYNC1, 3917 FN_SCK2, FN_HSCK0_B, 0, 0 )) 3918 }, 3919 { PINMUX_CFG_REG_VAR("MOD_SEL", 0xfffc0090, 32, 3920 GROUP(2, 2, 3, 3, 2, 2, 2, 2, 2, 1, 1, 1, 3921 1, 1, 1, 1, 2, 1, 2), 3922 GROUP( 3923 /* SEL_SCIF5 [2] */ 3924 FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3, 3925 /* SEL_SCIF4 [2] */ 3926 FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3, 3927 /* SEL_SCIF3 [3] */ 3928 FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3, 3929 FN_SEL_SCIF3_4, 0, 0, 0, 3930 /* SEL_SCIF2 [3] */ 3931 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF2_3, 3932 FN_SEL_SCIF2_4, 0, 0, 0, 3933 /* SEL_SCIF1 [2] */ 3934 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, 0, 3935 /* SEL_SCIF0 [2] */ 3936 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3, 3937 /* SEL_SSI9 [2] */ 3938 FN_SEL_SSI9_0, FN_SEL_SSI9_1, FN_SEL_SSI9_2, 0, 3939 /* SEL_SSI8 [2] */ 3940 FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2, 0, 3941 /* SEL_SSI7 [2] */ 3942 FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2, 0, 3943 /* SEL_VI0 [1] */ 3944 FN_SEL_VI0_0, FN_SEL_VI0_1, 3945 /* SEL_SD2 [1] */ 3946 FN_SEL_SD2_0, FN_SEL_SD2_1, 3947 /* SEL_INT3 [1] */ 3948 FN_SEL_INT3_0, FN_SEL_INT3_1, 3949 /* SEL_INT2 [1] */ 3950 FN_SEL_INT2_0, FN_SEL_INT2_1, 3951 /* SEL_INT1 [1] */ 3952 FN_SEL_INT1_0, FN_SEL_INT1_1, 3953 /* SEL_INT0 [1] */ 3954 FN_SEL_INT0_0, FN_SEL_INT0_1, 3955 /* SEL_IE [1] */ 3956 FN_SEL_IE_0, FN_SEL_IE_1, 3957 /* SEL_EXBUS2 [2] */ 3958 FN_SEL_EXBUS2_0, FN_SEL_EXBUS2_1, FN_SEL_EXBUS2_2, 0, 3959 /* SEL_EXBUS1 [1] */ 3960 FN_SEL_EXBUS1_0, FN_SEL_EXBUS1_1, 3961 /* SEL_EXBUS0 [2] */ 3962 FN_SEL_EXBUS0_0, FN_SEL_EXBUS0_1, FN_SEL_EXBUS0_2, 0 )) 3963 }, 3964 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xfffc0094, 32, 3965 GROUP(2, 2, 2, 2, 1, 1, 1, 3, 1, 2, 2, 2, 3966 2, 1, 1, 2, 1, 2, 2), 3967 GROUP( 3968 /* SEL_TMU1 [2] */ 3969 FN_SEL_TMU1_0, FN_SEL_TMU1_1, FN_SEL_TMU1_2, 0, 3970 /* SEL_TMU0 [2] */ 3971 FN_SEL_TMU0_0, FN_SEL_TMU0_1, FN_SEL_TMU0_2, FN_SEL_TMU0_3, 3972 /* SEL_SCIF [2] */ 3973 FN_SEL_SCIF_0, FN_SEL_SCIF_1, FN_SEL_SCIF_2, FN_SEL_SCIF_3, 3974 /* SEL_CANCLK [2] */ 3975 FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2, 0, 3976 /* SEL_CAN0 [1] */ 3977 FN_SEL_CAN0_0, FN_SEL_CAN0_1, 3978 /* SEL_HSCIF1 [1] */ 3979 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, 3980 /* SEL_HSCIF0 [1] */ 3981 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, 3982 /* SEL_PWMFSW [3] */ 3983 FN_SEL_PWMFSW_0, FN_SEL_PWMFSW_1, FN_SEL_PWMFSW_2, 3984 FN_SEL_PWMFSW_3, FN_SEL_PWMFSW_4, 0, 0, 0, 3985 /* SEL_ADI [1] */ 3986 FN_SEL_ADI_0, FN_SEL_ADI_1, 3987 /* [2] */ 3988 0, 0, 0, 0, 3989 /* [2] */ 3990 0, 0, 0, 0, 3991 /* [2] */ 3992 0, 0, 0, 0, 3993 /* SEL_GPS [2] */ 3994 FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3, 3995 /* SEL_SIM [1] */ 3996 FN_SEL_SIM_0, FN_SEL_SIM_1, 3997 /* SEL_HSPI2 [1] */ 3998 FN_SEL_HSPI2_0, FN_SEL_HSPI2_1, 3999 /* SEL_HSPI1 [2] */ 4000 FN_SEL_HSPI1_0, FN_SEL_HSPI1_1, FN_SEL_HSPI1_2, FN_SEL_HSPI1_3, 4001 /* SEL_I2C3 [1] */ 4002 FN_SEL_I2C3_0, FN_SEL_I2C3_1, 4003 /* SEL_I2C2 [2] */ 4004 FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3, 4005 /* SEL_I2C1 [2] */ 4006 FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, FN_SEL_I2C1_3 )) 4007 }, 4008 { }, 4009 }; 4010 4011 const struct sh_pfc_soc_info r8a7779_pinmux_info = { 4012 .name = "r8a7779_pfc", 4013 4014 .unlock_reg = 0xfffc0000, /* PMMR */ 4015 4016 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 4017 4018 .pins = pinmux_pins, 4019 .nr_pins = ARRAY_SIZE(pinmux_pins), 4020 .groups = pinmux_groups, 4021 .nr_groups = ARRAY_SIZE(pinmux_groups), 4022 .functions = pinmux_functions, 4023 .nr_functions = ARRAY_SIZE(pinmux_functions), 4024 4025 .cfg_regs = pinmux_config_regs, 4026 4027 .pinmux_data = pinmux_data, 4028 .pinmux_data_size = ARRAY_SIZE(pinmux_data), 4029 }; 4030