1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * R8A77470 processor support - PFC hardware block.
4  *
5  * Copyright (C) 2018 Renesas Electronics Corp.
6  */
7 
8 #include <linux/errno.h>
9 #include <linux/kernel.h>
10 
11 #include "sh_pfc.h"
12 
13 #define CPU_ALL_GP(fn, sfx)						\
14 	PORT_GP_CFG_4(0,  fn, sfx, SH_PFC_PIN_CFG_PULL_UP),		\
15 	PORT_GP_CFG_1(0,  4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),		\
16 	PORT_GP_CFG_1(0,  5, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP),	\
17 	PORT_GP_CFG_1(0,  6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP),	\
18 	PORT_GP_CFG_1(0,  7, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP),	\
19 	PORT_GP_CFG_1(0,  8, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP),	\
20 	PORT_GP_CFG_1(0,  9, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP),	\
21 	PORT_GP_CFG_1(0, 10, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP),	\
22 	PORT_GP_CFG_1(0, 11, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),		\
23 	PORT_GP_CFG_1(0, 12, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),		\
24 	PORT_GP_CFG_1(0, 13, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP),	\
25 	PORT_GP_CFG_1(0, 14, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP),	\
26 	PORT_GP_CFG_1(0, 15, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP),	\
27 	PORT_GP_CFG_1(0, 16, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP),	\
28 	PORT_GP_CFG_1(0, 17, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP),	\
29 	PORT_GP_CFG_1(0, 18, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP),	\
30 	PORT_GP_CFG_1(0, 19, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP),	\
31 	PORT_GP_CFG_1(0, 20, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP),	\
32 	PORT_GP_CFG_1(0, 21, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP),	\
33 	PORT_GP_CFG_1(0, 22, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP),	\
34 	PORT_GP_CFG_23(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),		\
35 	PORT_GP_CFG_32(2, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),		\
36 	PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),		\
37 	PORT_GP_CFG_1(3, 27, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),		\
38 	PORT_GP_CFG_1(3, 28, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),		\
39 	PORT_GP_CFG_1(3, 29, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),		\
40 	PORT_GP_CFG_14(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),		\
41 	PORT_GP_CFG_1(4, 14, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP),	\
42 	PORT_GP_CFG_1(4, 15, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP),	\
43 	PORT_GP_CFG_1(4, 16, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP),	\
44 	PORT_GP_CFG_1(4, 17, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP),	\
45 	PORT_GP_CFG_1(4, 18, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP),	\
46 	PORT_GP_CFG_1(4, 19, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP),	\
47 	PORT_GP_CFG_1(4, 20, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),		\
48 	PORT_GP_CFG_1(4, 21, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),		\
49 	PORT_GP_CFG_1(4, 22, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),		\
50 	PORT_GP_CFG_1(4, 23, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),		\
51 	PORT_GP_CFG_1(4, 24, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),		\
52 	PORT_GP_CFG_1(4, 25, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),		\
53 	PORT_GP_CFG_32(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP)
54 
55 #define CPU_ALL_NOGP(fn)						\
56 	PIN_NOGP_CFG(ASEBRK_N_ACK, "ASEBRK#/ACK", fn, SH_PFC_PIN_CFG_PULL_DOWN),	\
57 	PIN_NOGP_CFG(NMI, "NMI", fn, SH_PFC_PIN_CFG_PULL_UP),		\
58 	PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, SH_PFC_PIN_CFG_PULL_UP),	\
59 	PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP),		\
60 	PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP),		\
61 	PIN_NOGP_CFG(TDO, "TDO", fn, SH_PFC_PIN_CFG_PULL_UP),		\
62 	PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP),		\
63 	PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP)
64 
65 enum {
66 	PINMUX_RESERVED = 0,
67 
68 	PINMUX_DATA_BEGIN,
69 	GP_ALL(DATA),
70 	PINMUX_DATA_END,
71 
72 	PINMUX_FUNCTION_BEGIN,
73 	GP_ALL(FN),
74 
75 	/* GPSR0 */
76 	FN_USB0_PWEN, FN_USB0_OVC, FN_USB1_PWEN, FN_USB1_OVC, FN_CLKOUT,
77 	FN_IP0_3_0, FN_IP0_7_4, FN_IP0_11_8, FN_IP0_15_12, FN_IP0_19_16,
78 	FN_IP0_23_20, FN_IP0_27_24, FN_IP0_31_28, FN_MMC0_CLK_SDHI1_CLK,
79 	FN_MMC0_CMD_SDHI1_CMD, FN_MMC0_D0_SDHI1_D0, FN_MMC0_D1_SDHI1_D1,
80 	FN_MMC0_D2_SDHI1_D2, FN_MMC0_D3_SDHI1_D3, FN_IP1_3_0,
81 	FN_IP1_7_4, FN_MMC0_D6, FN_MMC0_D7,
82 
83 	/* GPSR1 */
84 	FN_IP1_11_8, FN_IP1_15_12, FN_IP1_19_16, FN_IP1_23_20, FN_IP1_27_24,
85 	FN_IP1_31_28, FN_IP2_3_0, FN_IP2_7_4, FN_IP2_11_8, FN_IP2_15_12,
86 	FN_IP2_19_16, FN_IP2_23_20, FN_IP2_27_24, FN_IP2_31_28, FN_IP3_3_0,
87 	FN_IP3_7_4, FN_IP3_11_8, FN_IP3_15_12, FN_IP3_19_16, FN_IP3_23_20,
88 	FN_IP3_27_24, FN_IP3_31_28, FN_IP4_3_0,
89 
90 	/* GPSR2 */
91 	FN_IP4_7_4, FN_IP4_11_8, FN_IP4_15_12, FN_IP4_19_16, FN_IP4_23_20,
92 	FN_IP4_27_24, FN_IP4_31_28, FN_IP5_3_0, FN_IP5_7_4, FN_IP5_11_8,
93 	FN_IP5_15_12, FN_IP5_19_16, FN_IP5_23_20, FN_IP5_27_24, FN_IP5_31_28,
94 	FN_IP6_3_0, FN_IP6_7_4, FN_IP6_11_8, FN_IP6_15_12, FN_IP6_19_16,
95 	FN_IP6_23_20, FN_IP6_27_24, FN_IP6_31_28, FN_IP7_3_0, FN_IP7_7_4,
96 	FN_IP7_11_8, FN_IP7_15_12, FN_IP7_19_16, FN_IP7_23_20, FN_IP7_27_24,
97 	FN_IP7_31_28, FN_IP8_3_0,
98 
99 	/* GPSR3 */
100 	FN_IP8_7_4, FN_IP8_11_8, FN_IP8_15_12, FN_IP8_19_16, FN_IP8_23_20,
101 	FN_IP8_27_24, FN_IP8_31_28, FN_IP9_3_0, FN_IP9_7_4, FN_IP9_11_8,
102 	FN_IP9_15_12, FN_IP9_19_16, FN_IP9_23_20, FN_IP9_27_24, FN_IP9_31_28,
103 	FN_IP10_3_0, FN_IP10_7_4, FN_IP10_11_8, FN_IP10_15_12, FN_IP10_19_16,
104 
105 	/* GPSR4 */
106 	FN_IP10_23_20, FN_IP10_27_24, FN_IP10_31_28, FN_IP11_3_0, FN_IP11_7_4,
107 	FN_IP11_11_8, FN_IP11_15_12, FN_IP11_19_16, FN_IP11_23_20,
108 	FN_IP11_27_24, FN_IP11_31_28, FN_IP12_3_0, FN_IP12_7_4, FN_IP12_11_8,
109 	FN_IP12_15_12, FN_IP12_19_16, FN_IP12_23_20, FN_IP12_27_24,
110 	FN_IP12_31_28, FN_IP13_3_0, FN_IP13_7_4, FN_IP13_11_8, FN_IP13_15_12,
111 	FN_IP13_19_16, FN_IP13_23_20, FN_IP13_27_24,
112 
113 	/* GPSR5 */
114 	FN_IP13_31_28, FN_IP14_3_0, FN_IP14_7_4, FN_IP14_11_8, FN_IP14_15_12,
115 	FN_IP14_19_16, FN_IP14_23_20, FN_IP14_27_24, FN_IP14_31_28,
116 	FN_IP15_3_0, FN_IP15_7_4, FN_IP15_11_8, FN_IP15_15_12, FN_IP15_19_16,
117 	FN_IP15_23_20, FN_IP15_27_24, FN_IP15_31_28, FN_IP16_3_0, FN_IP16_7_4,
118 	FN_IP16_11_8, FN_IP16_15_12, FN_IP16_19_16, FN_IP16_23_20,
119 	FN_IP16_27_24, FN_IP16_31_28, FN_IP17_3_0, FN_IP17_7_4, FN_IP17_11_8,
120 	FN_IP17_15_12, FN_IP17_19_16, FN_IP17_23_20, FN_IP17_27_24,
121 
122 	/* IPSR0 */
123 	FN_SD0_CLK, FN_SSI_SCK1_C, FN_RX3_C,
124 	FN_SD0_CMD, FN_SSI_WS1_C, FN_TX3_C,
125 	FN_SD0_DAT0, FN_SSI_SDATA1_C, FN_RX4_E,
126 	FN_SD0_DAT1, FN_SSI_SCK0129_B, FN_TX4_E,
127 	FN_SD0_DAT2, FN_SSI_WS0129_B, FN_RX5_E,
128 	FN_SD0_DAT3, FN_SSI_SDATA0_B, FN_TX5_E,
129 	FN_SD0_CD, FN_CAN0_RX_A,
130 	FN_SD0_WP, FN_IRQ7, FN_CAN0_TX_A,
131 
132 	/* IPSR1 */
133 	FN_MMC0_D4, FN_SD1_CD,
134 	FN_MMC0_D5, FN_SD1_WP,
135 	FN_D0, FN_SCL3_B, FN_RX5_B, FN_IRQ4, FN_MSIOF2_RXD_C, FN_SSI_SDATA5_B,
136 	FN_D1, FN_SDA3_B, FN_TX5_B, FN_MSIOF2_TXD_C, FN_SSI_WS5_B,
137 	FN_D2, FN_RX4_B, FN_SCL0_D, FN_PWM1_C, FN_MSIOF2_SCK_C, FN_SSI_SCK5_B,
138 	FN_D3, FN_TX4_B, FN_SDA0_D, FN_PWM0_A, FN_MSIOF2_SYNC_C,
139 	FN_D4, FN_IRQ3, FN_TCLK1_A, FN_PWM6_C,
140 	FN_D5, FN_HRX2, FN_SCL1_B, FN_PWM2_C, FN_TCLK2_B,
141 
142 	/* IPSR2 */
143 	FN_D6, FN_HTX2, FN_SDA1_B, FN_PWM4_C,
144 	FN_D7, FN_HSCK2, FN_SCIF1_SCK_C, FN_IRQ6, FN_PWM5_C,
145 	FN_D8, FN_HCTS2_N, FN_RX1_C, FN_SCL1_D, FN_PWM3_C,
146 	FN_D9, FN_HRTS2_N, FN_TX1_C, FN_SDA1_D,
147 	FN_D10, FN_MSIOF2_RXD_A, FN_HRX0_B,
148 	FN_D11, FN_MSIOF2_TXD_A, FN_HTX0_B,
149 	FN_D12, FN_MSIOF2_SCK_A, FN_HSCK0, FN_CAN_CLK_C,
150 	FN_D13,	FN_MSIOF2_SYNC_A, FN_RX4_C,
151 
152 	/* IPSR3 */
153 	FN_D14, FN_MSIOF2_SS1, FN_TX4_C, FN_CAN1_RX_B, FN_AVB_AVTP_CAPTURE_A,
154 	FN_D15, FN_MSIOF2_SS2, FN_PWM4_A, FN_CAN1_TX_B, FN_IRQ2, FN_AVB_AVTP_MATCH_A,
155 	FN_QSPI0_SPCLK, FN_WE0_N,
156 	FN_QSPI0_MOSI_QSPI0_IO0, FN_BS_N,
157 	FN_QSPI0_MISO_QSPI0_IO1, FN_RD_WR_N,
158 	FN_QSPI0_IO2, FN_CS0_N,
159 	FN_QSPI0_IO3, FN_RD_N,
160 	FN_QSPI0_SSL, FN_WE1_N,
161 
162 	/* IPSR4 */
163 	FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK_A,
164 	FN_DU0_DR0, FN_RX5_C, FN_SCL2_D, FN_A0,
165 	FN_DU0_DR1, FN_TX5_C, FN_SDA2_D, FN_A1,
166 	FN_DU0_DR2, FN_RX0_D, FN_SCL0_E, FN_A2,
167 	FN_DU0_DR3, FN_TX0_D, FN_SDA0_E, FN_PWM0_B, FN_A3,
168 	FN_DU0_DR4, FN_RX1_D, FN_A4,
169 	FN_DU0_DR5, FN_TX1_D, FN_PWM1_B, FN_A5,
170 	FN_DU0_DR6, FN_RX2_C, FN_A6,
171 
172 	/* IPSR5 */
173 	FN_DU0_DR7, FN_TX2_C, FN_PWM2_B, FN_A7,
174 	FN_DU0_DG0, FN_RX3_B, FN_SCL3_D, FN_A8,
175 	FN_DU0_DG1, FN_TX3_B, FN_SDA3_D, FN_PWM3_B, FN_A9,
176 	FN_DU0_DG2, FN_RX4_D, FN_A10,
177 	FN_DU0_DG3, FN_TX4_D, FN_PWM4_B, FN_A11,
178 	FN_DU0_DG4, FN_HRX0_A, FN_A12,
179 	FN_DU0_DG5, FN_HTX0_A, FN_PWM5_B, FN_A13,
180 	FN_DU0_DG6, FN_HRX1_C, FN_A14,
181 
182 	/* IPSR6 */
183 	FN_DU0_DG7, FN_HTX1_C, FN_PWM6_B, FN_A15,
184 	FN_DU0_DB0, FN_SCL4_D, FN_CAN0_RX_C, FN_A16,
185 	FN_DU0_DB1, FN_SDA4_D, FN_CAN0_TX_C, FN_A17,
186 	FN_DU0_DB2, FN_HCTS0_N, FN_A18,
187 	FN_DU0_DB3, FN_HRTS0_N, FN_A19,
188 	FN_DU0_DB4, FN_HCTS1_N_C, FN_A20,
189 	FN_DU0_DB5, FN_HRTS1_N_C, FN_A21,
190 	FN_DU0_DB6, FN_A22,
191 
192 	/* IPSR7 */
193 	FN_DU0_DB7, FN_A23,
194 	FN_DU0_DOTCLKIN, FN_A24,
195 	FN_DU0_DOTCLKOUT0, FN_A25,
196 	FN_DU0_DOTCLKOUT1, FN_MSIOF2_RXD_B, FN_CS1_N_A26,
197 	FN_DU0_EXHSYNC_DU0_HSYNC, FN_MSIOF2_TXD_B, FN_DREQ0_N,
198 	FN_DU0_EXVSYNC_DU0_VSYNC, FN_MSIOF2_SYNC_B, FN_DACK0,
199 	FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_MSIOF2_SCK_B, FN_DRACK0,
200 	FN_DU0_DISP, FN_CAN1_RX_C,
201 
202 	/* IPSR8 */
203 	FN_DU0_CDE, FN_CAN1_TX_C,
204 	FN_VI1_CLK, FN_AVB_RX_CLK, FN_ETH_REF_CLK,
205 	FN_VI1_DATA0, FN_AVB_RX_DV, FN_ETH_CRS_DV,
206 	FN_VI1_DATA1, FN_AVB_RXD0, FN_ETH_RXD0,
207 	FN_VI1_DATA2, FN_AVB_RXD1, FN_ETH_RXD1,
208 	FN_VI1_DATA3, FN_AVB_RXD2, FN_ETH_MDIO,
209 	FN_VI1_DATA4, FN_AVB_RXD3, FN_ETH_RX_ER,
210 	FN_VI1_DATA5, FN_AVB_RXD4, FN_ETH_LINK,
211 
212 	/* IPSR9 */
213 	FN_VI1_DATA6, FN_AVB_RXD5, FN_ETH_TXD1,
214 	FN_VI1_DATA7, FN_AVB_RXD6, FN_ETH_TX_EN,
215 	FN_VI1_CLKENB, FN_SCL3_A, FN_AVB_RXD7, FN_ETH_MAGIC,
216 	FN_VI1_FIELD, FN_SDA3_A, FN_AVB_RX_ER, FN_ETH_TXD0,
217 	FN_VI1_HSYNC_N,	FN_RX0_B, FN_SCL0_C, FN_AVB_GTXREFCLK, FN_ETH_MDC,
218 	FN_VI1_VSYNC_N,	FN_TX0_B, FN_SDA0_C, FN_AUDIO_CLKOUT_B, FN_AVB_TX_CLK,
219 	FN_VI1_DATA8, FN_SCL2_B, FN_AVB_TX_EN,
220 	FN_VI1_DATA9, FN_SDA2_B, FN_AVB_TXD0,
221 
222 	/* IPSR10 */
223 	FN_VI1_DATA10, FN_CAN0_RX_B, FN_AVB_TXD1,
224 	FN_VI1_DATA11, FN_CAN0_TX_B, FN_AVB_TXD2,
225 	FN_AVB_TXD3, FN_AUDIO_CLKA_B, FN_SSI_SCK1_D, FN_RX5_F, FN_MSIOF0_RXD_B,
226 	FN_AVB_TXD4, FN_AUDIO_CLKB_B, FN_SSI_WS1_D, FN_TX5_F, FN_MSIOF0_TXD_B,
227 	FN_AVB_TXD5, FN_SCIF_CLK_B, FN_AUDIO_CLKC_B, FN_SSI_SDATA1_D, FN_MSIOF0_SCK_B,
228 	FN_SCL0_A, FN_RX0_C, FN_PWM5_A,	FN_TCLK1_B, FN_AVB_TXD6, FN_CAN1_RX_D, FN_MSIOF0_SYNC_B,
229 	FN_SDA0_A, FN_TX0_C, FN_IRQ5, FN_CAN_CLK_A, FN_AVB_GTX_CLK, FN_CAN1_TX_D, FN_DVC_MUTE,
230 	FN_SCL1_A, FN_RX4_A, FN_PWM5_D, FN_DU1_DR0, FN_SSI_SCK6_B, FN_VI0_G0,
231 
232 	/* IPSR11 */
233 	FN_SDA1_A, FN_TX4_A, FN_DU1_DR1, FN_SSI_WS6_B, FN_VI0_G1,
234 	FN_MSIOF0_RXD_A, FN_RX5_A, FN_SCL2_C, FN_DU1_DR2, FN_QSPI1_MOSI_QSPI1_IO0, FN_SSI_SDATA6_B, FN_VI0_G2,
235 	FN_MSIOF0_TXD_A, FN_TX5_A, FN_SDA2_C, FN_DU1_DR3, FN_QSPI1_MISO_QSPI1_IO1, FN_SSI_WS78_B, FN_VI0_G3,
236 	FN_MSIOF0_SCK_A, FN_IRQ0, FN_DU1_DR4, FN_QSPI1_SPCLK, FN_SSI_SCK78_B, FN_VI0_G4,
237 	FN_MSIOF0_SYNC_A, FN_PWM1_A, FN_DU1_DR5, FN_QSPI1_IO2, FN_SSI_SDATA7_B,
238 	FN_MSIOF0_SS1_A, FN_DU1_DR6, FN_QSPI1_IO3, FN_SSI_SDATA8_B,
239 	FN_MSIOF0_SS2_A, FN_DU1_DR7, FN_QSPI1_SSL,
240 	FN_HRX1_A, FN_SCL4_A, FN_PWM6_A, FN_DU1_DG0, FN_RX0_A,
241 
242 	/* IPSR12 */
243 	FN_HTX1_A, FN_SDA4_A, FN_DU1_DG1, FN_TX0_A,
244 	FN_HCTS1_N_A, FN_PWM2_A, FN_DU1_DG2, FN_REMOCON_B,
245 	FN_HRTS1_N_A, FN_DU1_DG3, FN_SSI_WS1_B, FN_IRQ1,
246 	FN_SD2_CLK, FN_HSCK1, FN_DU1_DG4, FN_SSI_SCK1_B,
247 	FN_SD2_CMD, FN_SCIF1_SCK_A, FN_TCLK2_A, FN_DU1_DG5, FN_SSI_SCK2_B, FN_PWM3_A,
248 	FN_SD2_DAT0, FN_RX1_A, FN_SCL1_E, FN_DU1_DG6, FN_SSI_SDATA1_B,
249 	FN_SD2_DAT1, FN_TX1_A, FN_SDA1_E, FN_DU1_DG7, FN_SSI_WS2_B,
250 	FN_SD2_DAT2, FN_RX2_A, FN_DU1_DB0, FN_SSI_SDATA2_B,
251 
252 	/* IPSR13 */
253 	FN_SD2_DAT3, FN_TX2_A, FN_DU1_DB1, FN_SSI_WS9_B,
254 	FN_SD2_CD, FN_SCIF2_SCK_A, FN_DU1_DB2, FN_SSI_SCK9_B,
255 	FN_SD2_WP, FN_SCIF3_SCK, FN_DU1_DB3, FN_SSI_SDATA9_B,
256 	FN_RX3_A, FN_SCL1_C, FN_MSIOF1_RXD_B, FN_DU1_DB4, FN_AUDIO_CLKA_C, FN_SSI_SDATA4_B,
257 	FN_TX3_A, FN_SDA1_C, FN_MSIOF1_TXD_B, FN_DU1_DB5, FN_AUDIO_CLKB_C, FN_SSI_WS4_B,
258 	FN_SCL2_A, FN_MSIOF1_SCK_B, FN_DU1_DB6, FN_AUDIO_CLKC_C, FN_SSI_SCK4_B,
259 	FN_SDA2_A, FN_MSIOF1_SYNC_B, FN_DU1_DB7, FN_AUDIO_CLKOUT_C,
260 	FN_SSI_SCK5_A, FN_DU1_DOTCLKOUT1,
261 
262 	/* IPSR14 */
263 	FN_SSI_WS5_A, FN_SCL3_C, FN_DU1_DOTCLKIN,
264 	FN_SSI_SDATA5_A, FN_SDA3_C, FN_DU1_DOTCLKOUT0,
265 	FN_SSI_SCK6_A, FN_DU1_EXODDF_DU1_ODDF_DISP_CDE,
266 	FN_SSI_WS6_A, FN_SCL4_C, FN_DU1_EXHSYNC_DU1_HSYNC,
267 	FN_SSI_SDATA6_A, FN_SDA4_C, FN_DU1_EXVSYNC_DU1_VSYNC,
268 	FN_SSI_SCK78_A, FN_SDA4_E, FN_DU1_DISP,
269 	FN_SSI_WS78_A, FN_SCL4_E, FN_DU1_CDE,
270 	FN_SSI_SDATA7_A, FN_IRQ8, FN_AUDIO_CLKA_D, FN_CAN_CLK_D, FN_VI0_G5,
271 
272 	/* IPSR15 */
273 	FN_SSI_SCK0129_A, FN_MSIOF1_RXD_A, FN_RX5_D, FN_VI0_G6,
274 	FN_SSI_WS0129_A, FN_MSIOF1_TXD_A, FN_TX5_D, FN_VI0_G7,
275 	FN_SSI_SDATA0_A, FN_MSIOF1_SYNC_A, FN_PWM0_C, FN_VI0_R0,
276 	FN_SSI_SCK34, FN_MSIOF1_SCK_A, FN_AVB_MDC, FN_DACK1, FN_VI0_R1,
277 	FN_SSI_WS34, FN_MSIOF1_SS1_A, FN_AVB_MDIO, FN_CAN1_RX_A, FN_DREQ1_N, FN_VI0_R2,
278 	FN_SSI_SDATA3, FN_MSIOF1_SS2_A, FN_AVB_LINK, FN_CAN1_TX_A, FN_DREQ2_N, FN_VI0_R3,
279 	FN_SSI_SCK4_A, FN_AVB_MAGIC, FN_VI0_R4,
280 	FN_SSI_WS4_A, FN_AVB_PHY_INT, FN_VI0_R5,
281 
282 	/* IPSR16 */
283 	FN_SSI_SDATA4_A, FN_AVB_CRS, FN_VI0_R6,
284 	FN_SSI_SCK1_A, FN_SCIF1_SCK_B, FN_PWM1_D, FN_IRQ9, FN_REMOCON_A, FN_DACK2, FN_VI0_CLK, FN_AVB_COL,
285 	FN_SSI_SDATA8_A, FN_RX1_B, FN_CAN0_RX_D, FN_AVB_AVTP_CAPTURE_B,	FN_VI0_R7,
286 	FN_SSI_WS1_A, FN_TX1_B, FN_CAN0_TX_D, FN_AVB_AVTP_MATCH_B, FN_VI0_DATA0_VI0_B0,
287 	FN_SSI_SDATA1_A, FN_HRX1_B, FN_VI0_DATA1_VI0_B1,
288 	FN_SSI_SCK2_A, FN_HTX1_B, FN_AVB_TXD7, FN_VI0_DATA2_VI0_B2,
289 	FN_SSI_WS2_A, FN_HCTS1_N_B, FN_AVB_TX_ER, FN_VI0_DATA3_VI0_B3,
290 	FN_SSI_SDATA2_A, FN_HRTS1_N_B, FN_VI0_DATA4_VI0_B4,
291 
292 	/* IPSR17 */
293 	FN_SSI_SCK9_A, FN_RX2_B, FN_SCL3_E, FN_EX_WAIT1, FN_VI0_DATA5_VI0_B5,
294 	FN_SSI_WS9_A, FN_TX2_B, FN_SDA3_E, FN_VI0_DATA6_VI0_B6,
295 	FN_SSI_SDATA9_A, FN_SCIF2_SCK_B, FN_PWM2_D, FN_VI0_DATA7_VI0_B7,
296 	FN_AUDIO_CLKA_A, FN_SCL0_B, FN_VI0_CLKENB,
297 	FN_AUDIO_CLKB_A, FN_SDA0_B, FN_VI0_FIELD,
298 	FN_AUDIO_CLKC_A, FN_SCL4_B, FN_VI0_HSYNC_N,
299 	FN_AUDIO_CLKOUT_A, FN_SDA4_B, FN_VI0_VSYNC_N,
300 
301 	/* MOD_SEL0 */
302 	FN_SEL_ADGA_0, FN_SEL_ADGA_1, FN_SEL_ADGA_2, FN_SEL_ADGA_3,
303 	FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2, FN_SEL_CANCLK_3,
304 	FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
305 	FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
306 	FN_SEL_I2C04_0, FN_SEL_I2C04_1,	FN_SEL_I2C04_2, FN_SEL_I2C04_3, FN_SEL_I2C04_4,
307 	FN_SEL_I2C03_0,	FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3, FN_SEL_I2C03_4,
308 	FN_SEL_I2C02_0, FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3,
309 	FN_SEL_I2C01_0, FN_SEL_I2C01_1, FN_SEL_I2C01_2, FN_SEL_I2C01_3, FN_SEL_I2C01_4,
310 	FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2, FN_SEL_I2C00_3, FN_SEL_I2C00_4,
311 	FN_SEL_AVB_0, FN_SEL_AVB_1,
312 
313 	/* MOD_SEL1 */
314 	FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1,
315 	FN_SEL_SCIF5_0, FN_SEL_SCIF5_1,	FN_SEL_SCIF5_2, FN_SEL_SCIF5_3, FN_SEL_SCIF5_4, FN_SEL_SCIF5_5,
316 	FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,	FN_SEL_SCIF4_4,
317 	FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2,
318 	FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2,
319 	FN_SEL_SCIF2_CLK_0, FN_SEL_SCIF2_CLK_1,
320 	FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2,	FN_SEL_SCIF1_3,
321 	FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2,	FN_SEL_SCIF0_3,
322 	FN_SEL_MSIOF2_0, FN_SEL_MSIOF2_1, FN_SEL_MSIOF2_2,
323 	FN_SEL_MSIOF1_0, FN_SEL_MSIOF1_1,
324 	FN_SEL_MSIOF0_0, FN_SEL_MSIOF0_1,
325 	FN_SEL_RCN_0, FN_SEL_RCN_1,
326 	FN_SEL_TMU2_0, FN_SEL_TMU2_1,
327 	FN_SEL_TMU1_0, FN_SEL_TMU1_1,
328 	FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2,
329 	FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1,
330 
331 	/* MOD_SEL2 */
332 	FN_SEL_ADGB_0, FN_SEL_ADGB_1, FN_SEL_ADGB_2,
333 	FN_SEL_ADGC_0, FN_SEL_ADGC_1, FN_SEL_ADGC_2,
334 	FN_SEL_SSI9_0, FN_SEL_SSI9_1,
335 	FN_SEL_SSI8_0, FN_SEL_SSI8_1,
336 	FN_SEL_SSI7_0, FN_SEL_SSI7_1,
337 	FN_SEL_SSI6_0, FN_SEL_SSI6_1,
338 	FN_SEL_SSI5_0, FN_SEL_SSI5_1,
339 	FN_SEL_SSI4_0, FN_SEL_SSI4_1,
340 	FN_SEL_SSI2_0, FN_SEL_SSI2_1,
341 	FN_SEL_SSI1_0, FN_SEL_SSI1_1, FN_SEL_SSI1_2, FN_SEL_SSI1_3,
342 	FN_SEL_SSI0_0, FN_SEL_SSI0_1,
343 	PINMUX_FUNCTION_END,
344 
345 	PINMUX_MARK_BEGIN,
346 
347 	USB0_PWEN_MARK, USB0_OVC_MARK, USB1_PWEN_MARK, USB1_OVC_MARK,
348 	CLKOUT_MARK, MMC0_CLK_SDHI1_CLK_MARK, MMC0_CMD_SDHI1_CMD_MARK,
349 	MMC0_D0_SDHI1_D0_MARK, MMC0_D1_SDHI1_D1_MARK,
350 	MMC0_D2_SDHI1_D2_MARK, MMC0_D3_SDHI1_D3_MARK, MMC0_D6_MARK,
351 	MMC0_D7_MARK,
352 
353 	/* IPSR0 */
354 	SD0_CLK_MARK, SSI_SCK1_C_MARK, RX3_C_MARK,
355 	SD0_CMD_MARK, SSI_WS1_C_MARK, TX3_C_MARK,
356 	SD0_DAT0_MARK, SSI_SDATA1_C_MARK, RX4_E_MARK,
357 	SD0_DAT1_MARK, SSI_SCK0129_B_MARK, TX4_E_MARK,
358 	SD0_DAT2_MARK, SSI_WS0129_B_MARK, RX5_E_MARK,
359 	SD0_DAT3_MARK, SSI_SDATA0_B_MARK, TX5_E_MARK,
360 	SD0_CD_MARK, CAN0_RX_A_MARK,
361 	SD0_WP_MARK, IRQ7_MARK,	CAN0_TX_A_MARK,
362 
363 	/* IPSR1 */
364 	MMC0_D4_MARK, SD1_CD_MARK,
365 	MMC0_D5_MARK, SD1_WP_MARK,
366 	D0_MARK, SCL3_B_MARK, RX5_B_MARK, IRQ4_MARK, MSIOF2_RXD_C_MARK,	SSI_SDATA5_B_MARK,
367 	D1_MARK, SDA3_B_MARK, TX5_B_MARK, MSIOF2_TXD_C_MARK, SSI_WS5_B_MARK,
368 	D2_MARK, RX4_B_MARK, SCL0_D_MARK, PWM1_C_MARK, MSIOF2_SCK_C_MARK, SSI_SCK5_B_MARK,
369 	D3_MARK, TX4_B_MARK, SDA0_D_MARK, PWM0_A_MARK, MSIOF2_SYNC_C_MARK,
370 	D4_MARK, IRQ3_MARK, TCLK1_A_MARK, PWM6_C_MARK,
371 	D5_MARK, HRX2_MARK, SCL1_B_MARK, PWM2_C_MARK, TCLK2_B_MARK,
372 
373 	/* IPSR2 */
374 	D6_MARK, HTX2_MARK, SDA1_B_MARK, PWM4_C_MARK,
375 	D7_MARK, HSCK2_MARK, SCIF1_SCK_C_MARK, IRQ6_MARK, PWM5_C_MARK,
376 	D8_MARK, HCTS2_N_MARK, RX1_C_MARK, SCL1_D_MARK,	PWM3_C_MARK,
377 	D9_MARK, HRTS2_N_MARK, TX1_C_MARK, SDA1_D_MARK,
378 	D10_MARK, MSIOF2_RXD_A_MARK, HRX0_B_MARK,
379 	D11_MARK, MSIOF2_TXD_A_MARK, HTX0_B_MARK,
380 	D12_MARK, MSIOF2_SCK_A_MARK, HSCK0_MARK, CAN_CLK_C_MARK,
381 	D13_MARK, MSIOF2_SYNC_A_MARK, RX4_C_MARK,
382 
383 	/* IPSR3 */
384 	D14_MARK, MSIOF2_SS1_MARK, TX4_C_MARK, CAN1_RX_B_MARK, AVB_AVTP_CAPTURE_A_MARK,
385 	D15_MARK, MSIOF2_SS2_MARK, PWM4_A_MARK, CAN1_TX_B_MARK, IRQ2_MARK, AVB_AVTP_MATCH_A_MARK,
386 	QSPI0_SPCLK_MARK, WE0_N_MARK,
387 	QSPI0_MOSI_QSPI0_IO0_MARK, BS_N_MARK,
388 	QSPI0_MISO_QSPI0_IO1_MARK, RD_WR_N_MARK,
389 	QSPI0_IO2_MARK, CS0_N_MARK,
390 	QSPI0_IO3_MARK, RD_N_MARK,
391 	QSPI0_SSL_MARK, WE1_N_MARK,
392 
393 	/* IPSR4 */
394 	EX_WAIT0_MARK, CAN_CLK_B_MARK, SCIF_CLK_A_MARK,
395 	DU0_DR0_MARK, RX5_C_MARK, SCL2_D_MARK, A0_MARK,
396 	DU0_DR1_MARK, TX5_C_MARK, SDA2_D_MARK, A1_MARK,
397 	DU0_DR2_MARK, RX0_D_MARK, SCL0_E_MARK, A2_MARK,
398 	DU0_DR3_MARK, TX0_D_MARK, SDA0_E_MARK, PWM0_B_MARK, A3_MARK,
399 	DU0_DR4_MARK, RX1_D_MARK, A4_MARK,
400 	DU0_DR5_MARK, TX1_D_MARK, PWM1_B_MARK, A5_MARK,
401 	DU0_DR6_MARK, RX2_C_MARK, A6_MARK,
402 
403 	/* IPSR5 */
404 	DU0_DR7_MARK, TX2_C_MARK, PWM2_B_MARK, A7_MARK,
405 	DU0_DG0_MARK, RX3_B_MARK, SCL3_D_MARK, A8_MARK,
406 	DU0_DG1_MARK, TX3_B_MARK, SDA3_D_MARK, PWM3_B_MARK, A9_MARK,
407 	DU0_DG2_MARK, RX4_D_MARK, A10_MARK,
408 	DU0_DG3_MARK, TX4_D_MARK, PWM4_B_MARK, A11_MARK,
409 	DU0_DG4_MARK, HRX0_A_MARK, A12_MARK,
410 	DU0_DG5_MARK, HTX0_A_MARK, PWM5_B_MARK, A13_MARK,
411 	DU0_DG6_MARK, HRX1_C_MARK, A14_MARK,
412 
413 	/* IPSR6 */
414 	DU0_DG7_MARK, HTX1_C_MARK, PWM6_B_MARK, A15_MARK,
415 	DU0_DB0_MARK, SCL4_D_MARK, CAN0_RX_C_MARK, A16_MARK,
416 	DU0_DB1_MARK, SDA4_D_MARK, CAN0_TX_C_MARK, A17_MARK,
417 	DU0_DB2_MARK, HCTS0_N_MARK, A18_MARK,
418 	DU0_DB3_MARK, HRTS0_N_MARK, A19_MARK,
419 	DU0_DB4_MARK, HCTS1_N_C_MARK, A20_MARK,
420 	DU0_DB5_MARK, HRTS1_N_C_MARK, A21_MARK,
421 	DU0_DB6_MARK, A22_MARK,
422 
423 	/* IPSR7 */
424 	DU0_DB7_MARK, A23_MARK,
425 	DU0_DOTCLKIN_MARK, A24_MARK,
426 	DU0_DOTCLKOUT0_MARK, A25_MARK,
427 	DU0_DOTCLKOUT1_MARK, MSIOF2_RXD_B_MARK, CS1_N_A26_MARK,
428 	DU0_EXHSYNC_DU0_HSYNC_MARK, MSIOF2_TXD_B_MARK, DREQ0_N_MARK,
429 	DU0_EXVSYNC_DU0_VSYNC_MARK, MSIOF2_SYNC_B_MARK, DACK0_MARK,
430 	DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, MSIOF2_SCK_B_MARK, DRACK0_MARK,
431 	DU0_DISP_MARK, CAN1_RX_C_MARK,
432 
433 	/* IPSR8 */
434 	DU0_CDE_MARK, CAN1_TX_C_MARK,
435 	VI1_CLK_MARK, AVB_RX_CLK_MARK, ETH_REF_CLK_MARK,
436 	VI1_DATA0_MARK, AVB_RX_DV_MARK, ETH_CRS_DV_MARK,
437 	VI1_DATA1_MARK, AVB_RXD0_MARK, ETH_RXD0_MARK,
438 	VI1_DATA2_MARK, AVB_RXD1_MARK, ETH_RXD1_MARK,
439 	VI1_DATA3_MARK, AVB_RXD2_MARK, ETH_MDIO_MARK,
440 	VI1_DATA4_MARK, AVB_RXD3_MARK, ETH_RX_ER_MARK,
441 	VI1_DATA5_MARK, AVB_RXD4_MARK, ETH_LINK_MARK,
442 
443 	/* IPSR9 */
444 	VI1_DATA6_MARK, AVB_RXD5_MARK, ETH_TXD1_MARK,
445 	VI1_DATA7_MARK,	AVB_RXD6_MARK, ETH_TX_EN_MARK,
446 	VI1_CLKENB_MARK, SCL3_A_MARK, AVB_RXD7_MARK, ETH_MAGIC_MARK,
447 	VI1_FIELD_MARK, SDA3_A_MARK, AVB_RX_ER_MARK, ETH_TXD0_MARK,
448 	VI1_HSYNC_N_MARK, RX0_B_MARK, SCL0_C_MARK, AVB_GTXREFCLK_MARK, ETH_MDC_MARK,
449 	VI1_VSYNC_N_MARK, TX0_B_MARK, SDA0_C_MARK, AUDIO_CLKOUT_B_MARK, AVB_TX_CLK_MARK,
450 	VI1_DATA8_MARK, SCL2_B_MARK, AVB_TX_EN_MARK,
451 	VI1_DATA9_MARK, SDA2_B_MARK, AVB_TXD0_MARK,
452 
453 	/* IPSR10 */
454 	VI1_DATA10_MARK, CAN0_RX_B_MARK, AVB_TXD1_MARK,
455 	VI1_DATA11_MARK, CAN0_TX_B_MARK, AVB_TXD2_MARK,
456 	AVB_TXD3_MARK, AUDIO_CLKA_B_MARK, SSI_SCK1_D_MARK, RX5_F_MARK, MSIOF0_RXD_B_MARK,
457 	AVB_TXD4_MARK, AUDIO_CLKB_B_MARK, SSI_WS1_D_MARK, TX5_F_MARK, MSIOF0_TXD_B_MARK,
458 	AVB_TXD5_MARK, SCIF_CLK_B_MARK, AUDIO_CLKC_B_MARK, SSI_SDATA1_D_MARK, MSIOF0_SCK_B_MARK,
459 	SCL0_A_MARK, RX0_C_MARK, PWM5_A_MARK, TCLK1_B_MARK, AVB_TXD6_MARK, CAN1_RX_D_MARK, MSIOF0_SYNC_B_MARK,
460 	SDA0_A_MARK, TX0_C_MARK, IRQ5_MARK, CAN_CLK_A_MARK, AVB_GTX_CLK_MARK, CAN1_TX_D_MARK, DVC_MUTE_MARK,
461 	SCL1_A_MARK, RX4_A_MARK, PWM5_D_MARK, DU1_DR0_MARK, SSI_SCK6_B_MARK, VI0_G0_MARK,
462 
463 	/* IPSR11 */
464 	SDA1_A_MARK, TX4_A_MARK, DU1_DR1_MARK, SSI_WS6_B_MARK, VI0_G1_MARK,
465 	MSIOF0_RXD_A_MARK, RX5_A_MARK, SCL2_C_MARK, DU1_DR2_MARK, QSPI1_MOSI_QSPI1_IO0_MARK, SSI_SDATA6_B_MARK, VI0_G2_MARK,
466 	MSIOF0_TXD_A_MARK, TX5_A_MARK, SDA2_C_MARK, DU1_DR3_MARK, QSPI1_MISO_QSPI1_IO1_MARK, SSI_WS78_B_MARK, VI0_G3_MARK,
467 	MSIOF0_SCK_A_MARK, IRQ0_MARK, DU1_DR4_MARK, QSPI1_SPCLK_MARK, SSI_SCK78_B_MARK, VI0_G4_MARK,
468 	MSIOF0_SYNC_A_MARK, PWM1_A_MARK, DU1_DR5_MARK, QSPI1_IO2_MARK, SSI_SDATA7_B_MARK,
469 	MSIOF0_SS1_A_MARK, DU1_DR6_MARK, QSPI1_IO3_MARK, SSI_SDATA8_B_MARK,
470 	MSIOF0_SS2_A_MARK, DU1_DR7_MARK, QSPI1_SSL_MARK,
471 	HRX1_A_MARK, SCL4_A_MARK, PWM6_A_MARK, DU1_DG0_MARK, RX0_A_MARK,
472 
473 	/* IPSR12 */
474 	HTX1_A_MARK, SDA4_A_MARK, DU1_DG1_MARK, TX0_A_MARK,
475 	HCTS1_N_A_MARK, PWM2_A_MARK, DU1_DG2_MARK, REMOCON_B_MARK,
476 	HRTS1_N_A_MARK, DU1_DG3_MARK, SSI_WS1_B_MARK, IRQ1_MARK,
477 	SD2_CLK_MARK, HSCK1_MARK, DU1_DG4_MARK, SSI_SCK1_B_MARK,
478 	SD2_CMD_MARK, SCIF1_SCK_A_MARK, TCLK2_A_MARK, DU1_DG5_MARK, SSI_SCK2_B_MARK, PWM3_A_MARK,
479 	SD2_DAT0_MARK, RX1_A_MARK, SCL1_E_MARK, DU1_DG6_MARK, SSI_SDATA1_B_MARK,
480 	SD2_DAT1_MARK, TX1_A_MARK, SDA1_E_MARK, DU1_DG7_MARK, SSI_WS2_B_MARK,
481 	SD2_DAT2_MARK, RX2_A_MARK, DU1_DB0_MARK, SSI_SDATA2_B_MARK,
482 
483 	/* IPSR13 */
484 	SD2_DAT3_MARK, TX2_A_MARK, DU1_DB1_MARK, SSI_WS9_B_MARK,
485 	SD2_CD_MARK, SCIF2_SCK_A_MARK, DU1_DB2_MARK, SSI_SCK9_B_MARK,
486 	SD2_WP_MARK, SCIF3_SCK_MARK, DU1_DB3_MARK, SSI_SDATA9_B_MARK,
487 	RX3_A_MARK, SCL1_C_MARK, MSIOF1_RXD_B_MARK, DU1_DB4_MARK, AUDIO_CLKA_C_MARK, SSI_SDATA4_B_MARK,
488 	TX3_A_MARK, SDA1_C_MARK, MSIOF1_TXD_B_MARK, DU1_DB5_MARK, AUDIO_CLKB_C_MARK, SSI_WS4_B_MARK,
489 	SCL2_A_MARK, MSIOF1_SCK_B_MARK, DU1_DB6_MARK, AUDIO_CLKC_C_MARK, SSI_SCK4_B_MARK,
490 	SDA2_A_MARK, MSIOF1_SYNC_B_MARK, DU1_DB7_MARK, AUDIO_CLKOUT_C_MARK,
491 	SSI_SCK5_A_MARK, DU1_DOTCLKOUT1_MARK,
492 
493 	/* IPSR14 */
494 	SSI_WS5_A_MARK, SCL3_C_MARK, DU1_DOTCLKIN_MARK,
495 	SSI_SDATA5_A_MARK, SDA3_C_MARK, DU1_DOTCLKOUT0_MARK,
496 	SSI_SCK6_A_MARK, DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
497 	SSI_WS6_A_MARK, SCL4_C_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK,
498 	SSI_SDATA6_A_MARK, SDA4_C_MARK, DU1_EXVSYNC_DU1_VSYNC_MARK,
499 	SSI_SCK78_A_MARK, SDA4_E_MARK, DU1_DISP_MARK,
500 	SSI_WS78_A_MARK, SCL4_E_MARK, DU1_CDE_MARK,
501 	SSI_SDATA7_A_MARK, IRQ8_MARK, AUDIO_CLKA_D_MARK, CAN_CLK_D_MARK, VI0_G5_MARK,
502 
503 	/* IPSR15 */
504 	SSI_SCK0129_A_MARK, MSIOF1_RXD_A_MARK, RX5_D_MARK, VI0_G6_MARK,
505 	SSI_WS0129_A_MARK, MSIOF1_TXD_A_MARK, TX5_D_MARK, VI0_G7_MARK,
506 	SSI_SDATA0_A_MARK, MSIOF1_SYNC_A_MARK, PWM0_C_MARK, VI0_R0_MARK,
507 	SSI_SCK34_MARK, MSIOF1_SCK_A_MARK, AVB_MDC_MARK, DACK1_MARK, VI0_R1_MARK,
508 	SSI_WS34_MARK, MSIOF1_SS1_A_MARK, AVB_MDIO_MARK, CAN1_RX_A_MARK, DREQ1_N_MARK, VI0_R2_MARK,
509 	SSI_SDATA3_MARK, MSIOF1_SS2_A_MARK, AVB_LINK_MARK, CAN1_TX_A_MARK, DREQ2_N_MARK, VI0_R3_MARK,
510 	SSI_SCK4_A_MARK, AVB_MAGIC_MARK, VI0_R4_MARK,
511 	SSI_WS4_A_MARK, AVB_PHY_INT_MARK, VI0_R5_MARK,
512 
513 	/* IPSR16 */
514 	SSI_SDATA4_A_MARK, AVB_CRS_MARK, VI0_R6_MARK,
515 	SSI_SCK1_A_MARK, SCIF1_SCK_B_MARK, PWM1_D_MARK, IRQ9_MARK, REMOCON_A_MARK, DACK2_MARK, VI0_CLK_MARK, AVB_COL_MARK,
516 	SSI_SDATA8_A_MARK, RX1_B_MARK, CAN0_RX_D_MARK, AVB_AVTP_CAPTURE_B_MARK, VI0_R7_MARK,
517 	SSI_WS1_A_MARK,	TX1_B_MARK, CAN0_TX_D_MARK, AVB_AVTP_MATCH_B_MARK, VI0_DATA0_VI0_B0_MARK,
518 	SSI_SDATA1_A_MARK, HRX1_B_MARK, VI0_DATA1_VI0_B1_MARK,
519 	SSI_SCK2_A_MARK, HTX1_B_MARK, AVB_TXD7_MARK, VI0_DATA2_VI0_B2_MARK,
520 	SSI_WS2_A_MARK, HCTS1_N_B_MARK, AVB_TX_ER_MARK, VI0_DATA3_VI0_B3_MARK,
521 	SSI_SDATA2_A_MARK, HRTS1_N_B_MARK, VI0_DATA4_VI0_B4_MARK,
522 
523 	/* IPSR17 */
524 	SSI_SCK9_A_MARK, RX2_B_MARK, SCL3_E_MARK, EX_WAIT1_MARK, VI0_DATA5_VI0_B5_MARK,
525 	SSI_WS9_A_MARK, TX2_B_MARK, SDA3_E_MARK, VI0_DATA6_VI0_B6_MARK,
526 	SSI_SDATA9_A_MARK, SCIF2_SCK_B_MARK, PWM2_D_MARK, VI0_DATA7_VI0_B7_MARK,
527 	AUDIO_CLKA_A_MARK, SCL0_B_MARK, VI0_CLKENB_MARK,
528 	AUDIO_CLKB_A_MARK, SDA0_B_MARK,	VI0_FIELD_MARK,
529 	AUDIO_CLKC_A_MARK, SCL4_B_MARK, VI0_HSYNC_N_MARK,
530 	AUDIO_CLKOUT_A_MARK, SDA4_B_MARK, VI0_VSYNC_N_MARK,
531 
532 	PINMUX_MARK_END,
533 };
534 
535 static const u16 pinmux_data[] = {
536 	PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
537 
538 	PINMUX_SINGLE(USB0_PWEN),
539 	PINMUX_SINGLE(USB0_OVC),
540 	PINMUX_SINGLE(USB1_PWEN),
541 	PINMUX_SINGLE(USB1_OVC),
542 	PINMUX_SINGLE(CLKOUT),
543 	PINMUX_SINGLE(MMC0_CLK_SDHI1_CLK),
544 	PINMUX_SINGLE(MMC0_CMD_SDHI1_CMD),
545 	PINMUX_SINGLE(MMC0_D0_SDHI1_D0),
546 	PINMUX_SINGLE(MMC0_D1_SDHI1_D1),
547 	PINMUX_SINGLE(MMC0_D2_SDHI1_D2),
548 	PINMUX_SINGLE(MMC0_D3_SDHI1_D3),
549 	PINMUX_SINGLE(MMC0_D6),
550 	PINMUX_SINGLE(MMC0_D7),
551 
552 	/* IPSR0 */
553 	PINMUX_IPSR_GPSR(IP0_3_0, SD0_CLK),
554 	PINMUX_IPSR_MSEL(IP0_3_0, SSI_SCK1_C, SEL_SSI1_2),
555 	PINMUX_IPSR_MSEL(IP0_3_0, RX3_C, SEL_SCIF3_2),
556 	PINMUX_IPSR_GPSR(IP0_7_4, SD0_CMD),
557 	PINMUX_IPSR_MSEL(IP0_7_4, SSI_WS1_C, SEL_SSI1_2),
558 	PINMUX_IPSR_MSEL(IP0_7_4, TX3_C, SEL_SCIF3_2),
559 	PINMUX_IPSR_GPSR(IP0_11_8, SD0_DAT0),
560 	PINMUX_IPSR_MSEL(IP0_11_8, SSI_SDATA1_C, SEL_SSI1_2),
561 	PINMUX_IPSR_MSEL(IP0_11_8, RX4_E, SEL_SCIF4_4),
562 	PINMUX_IPSR_GPSR(IP0_15_12, SD0_DAT1),
563 	PINMUX_IPSR_MSEL(IP0_15_12, SSI_SCK0129_B, SEL_SSI0_1),
564 	PINMUX_IPSR_MSEL(IP0_15_12, TX4_E, SEL_SCIF4_4),
565 	PINMUX_IPSR_GPSR(IP0_19_16, SD0_DAT2),
566 	PINMUX_IPSR_MSEL(IP0_19_16, SSI_WS0129_B, SEL_SSI0_1),
567 	PINMUX_IPSR_MSEL(IP0_19_16, RX5_E, SEL_SCIF5_4),
568 	PINMUX_IPSR_GPSR(IP0_23_20, SD0_DAT3),
569 	PINMUX_IPSR_MSEL(IP0_23_20, SSI_SDATA0_B, SEL_SSI0_1),
570 	PINMUX_IPSR_MSEL(IP0_23_20, TX5_E, SEL_SCIF5_4),
571 	PINMUX_IPSR_GPSR(IP0_27_24, SD0_CD),
572 	PINMUX_IPSR_MSEL(IP0_27_24, CAN0_RX_A, SEL_CAN0_0),
573 	PINMUX_IPSR_GPSR(IP0_31_28, SD0_WP),
574 	PINMUX_IPSR_GPSR(IP0_31_28, IRQ7),
575 	PINMUX_IPSR_MSEL(IP0_31_28, CAN0_TX_A, SEL_CAN0_0),
576 
577 	/* IPSR1 */
578 	PINMUX_IPSR_GPSR(IP1_3_0, MMC0_D4),
579 	PINMUX_IPSR_GPSR(IP1_3_0, SD1_CD),
580 	PINMUX_IPSR_GPSR(IP1_7_4, MMC0_D5),
581 	PINMUX_IPSR_GPSR(IP1_7_4, SD1_WP),
582 	PINMUX_IPSR_GPSR(IP1_11_8, D0),
583 	PINMUX_IPSR_MSEL(IP1_11_8, SCL3_B, SEL_I2C03_1),
584 	PINMUX_IPSR_MSEL(IP1_11_8, RX5_B, SEL_SCIF5_1),
585 	PINMUX_IPSR_GPSR(IP1_11_8, IRQ4),
586 	PINMUX_IPSR_MSEL(IP1_11_8, MSIOF2_RXD_C, SEL_MSIOF2_2),
587 	PINMUX_IPSR_MSEL(IP1_11_8, SSI_SDATA5_B, SEL_SSI5_1),
588 	PINMUX_IPSR_GPSR(IP1_15_12, D1),
589 	PINMUX_IPSR_MSEL(IP1_15_12, SDA3_B, SEL_I2C03_1),
590 	PINMUX_IPSR_MSEL(IP1_15_12, TX5_B, SEL_SCIF5_1),
591 	PINMUX_IPSR_MSEL(IP1_15_12, MSIOF2_TXD_C, SEL_MSIOF2_2),
592 	PINMUX_IPSR_MSEL(IP1_15_12, SSI_WS5_B, SEL_SSI5_1),
593 	PINMUX_IPSR_GPSR(IP1_19_16, D2),
594 	PINMUX_IPSR_MSEL(IP1_19_16, RX4_B, SEL_SCIF4_1),
595 	PINMUX_IPSR_MSEL(IP1_19_16, SCL0_D, SEL_I2C00_3),
596 	PINMUX_IPSR_GPSR(IP1_19_16, PWM1_C),
597 	PINMUX_IPSR_MSEL(IP1_19_16, MSIOF2_SCK_C, SEL_MSIOF2_2),
598 	PINMUX_IPSR_MSEL(IP1_19_16, SSI_SCK5_B, SEL_SSI5_1),
599 	PINMUX_IPSR_GPSR(IP1_23_20, D3),
600 	PINMUX_IPSR_MSEL(IP1_23_20, TX4_B, SEL_SCIF4_1),
601 	PINMUX_IPSR_MSEL(IP1_23_20, SDA0_D, SEL_I2C00_3),
602 	PINMUX_IPSR_GPSR(IP1_23_20, PWM0_A),
603 	PINMUX_IPSR_MSEL(IP1_23_20, MSIOF2_SYNC_C, SEL_MSIOF2_2),
604 	PINMUX_IPSR_GPSR(IP1_27_24, D4),
605 	PINMUX_IPSR_GPSR(IP1_27_24, IRQ3),
606 	PINMUX_IPSR_MSEL(IP1_27_24, TCLK1_A, SEL_TMU1_0),
607 	PINMUX_IPSR_GPSR(IP1_27_24, PWM6_C),
608 	PINMUX_IPSR_GPSR(IP1_31_28, D5),
609 	PINMUX_IPSR_GPSR(IP1_31_28, HRX2),
610 	PINMUX_IPSR_MSEL(IP1_31_28, SCL1_B, SEL_I2C01_1),
611 	PINMUX_IPSR_GPSR(IP1_31_28, PWM2_C),
612 	PINMUX_IPSR_MSEL(IP1_31_28, TCLK2_B, SEL_TMU2_1),
613 
614 	/* IPSR2 */
615 	PINMUX_IPSR_GPSR(IP2_3_0, D6),
616 	PINMUX_IPSR_GPSR(IP2_3_0, HTX2),
617 	PINMUX_IPSR_MSEL(IP2_3_0, SDA1_B, SEL_I2C01_1),
618 	PINMUX_IPSR_GPSR(IP2_3_0, PWM4_C),
619 	PINMUX_IPSR_GPSR(IP2_7_4, D7),
620 	PINMUX_IPSR_GPSR(IP2_7_4, HSCK2),
621 	PINMUX_IPSR_MSEL(IP2_7_4, SCIF1_SCK_C, SEL_SCIF1_2),
622 	PINMUX_IPSR_GPSR(IP2_7_4, IRQ6),
623 	PINMUX_IPSR_GPSR(IP2_7_4, PWM5_C),
624 	PINMUX_IPSR_GPSR(IP2_11_8, D8),
625 	PINMUX_IPSR_GPSR(IP2_11_8, HCTS2_N),
626 	PINMUX_IPSR_MSEL(IP2_11_8, RX1_C, SEL_SCIF1_2),
627 	PINMUX_IPSR_MSEL(IP2_11_8, SCL1_D, SEL_I2C01_3),
628 	PINMUX_IPSR_GPSR(IP2_11_8, PWM3_C),
629 	PINMUX_IPSR_GPSR(IP2_15_12, D9),
630 	PINMUX_IPSR_GPSR(IP2_15_12, HRTS2_N),
631 	PINMUX_IPSR_MSEL(IP2_15_12, TX1_C, SEL_SCIF1_2),
632 	PINMUX_IPSR_MSEL(IP2_15_12, SDA1_D, SEL_I2C01_3),
633 	PINMUX_IPSR_GPSR(IP2_19_16, D10),
634 	PINMUX_IPSR_MSEL(IP2_19_16, MSIOF2_RXD_A, SEL_MSIOF2_0),
635 	PINMUX_IPSR_MSEL(IP2_19_16, HRX0_B, SEL_HSCIF0_1),
636 	PINMUX_IPSR_GPSR(IP2_23_20, D11),
637 	PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_TXD_A, SEL_MSIOF2_0),
638 	PINMUX_IPSR_MSEL(IP2_23_20, HTX0_B, SEL_HSCIF0_1),
639 	PINMUX_IPSR_GPSR(IP2_27_24, D12),
640 	PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SCK_A, SEL_MSIOF2_0),
641 	PINMUX_IPSR_GPSR(IP2_27_24, HSCK0),
642 	PINMUX_IPSR_MSEL(IP2_27_24, CAN_CLK_C, SEL_CANCLK_2),
643 	PINMUX_IPSR_GPSR(IP2_31_28, D13),
644 	PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0),
645 	PINMUX_IPSR_MSEL(IP2_31_28, RX4_C, SEL_SCIF4_2),
646 
647 	/* IPSR3 */
648 	PINMUX_IPSR_GPSR(IP3_3_0, D14),
649 	PINMUX_IPSR_GPSR(IP3_3_0, MSIOF2_SS1),
650 	PINMUX_IPSR_MSEL(IP3_3_0, TX4_C, SEL_SCIF4_2),
651 	PINMUX_IPSR_MSEL(IP3_3_0, CAN1_RX_B, SEL_CAN1_1),
652 	PINMUX_IPSR_MSEL(IP3_3_0, AVB_AVTP_CAPTURE_A, SEL_AVB_0),
653 	PINMUX_IPSR_GPSR(IP3_7_4, D15),
654 	PINMUX_IPSR_GPSR(IP3_7_4, MSIOF2_SS2),
655 	PINMUX_IPSR_GPSR(IP3_7_4, PWM4_A),
656 	PINMUX_IPSR_MSEL(IP3_7_4, CAN1_TX_B, SEL_CAN1_1),
657 	PINMUX_IPSR_GPSR(IP3_7_4, IRQ2),
658 	PINMUX_IPSR_MSEL(IP3_7_4, AVB_AVTP_MATCH_A, SEL_AVB_0),
659 	PINMUX_IPSR_GPSR(IP3_11_8, QSPI0_SPCLK),
660 	PINMUX_IPSR_GPSR(IP3_11_8, WE0_N),
661 	PINMUX_IPSR_GPSR(IP3_15_12, QSPI0_MOSI_QSPI0_IO0),
662 	PINMUX_IPSR_GPSR(IP3_15_12, BS_N),
663 	PINMUX_IPSR_GPSR(IP3_19_16, QSPI0_MISO_QSPI0_IO1),
664 	PINMUX_IPSR_GPSR(IP3_19_16, RD_WR_N),
665 	PINMUX_IPSR_GPSR(IP3_23_20, QSPI0_IO2),
666 	PINMUX_IPSR_GPSR(IP3_23_20, CS0_N),
667 	PINMUX_IPSR_GPSR(IP3_27_24, QSPI0_IO3),
668 	PINMUX_IPSR_GPSR(IP3_27_24, RD_N),
669 	PINMUX_IPSR_GPSR(IP3_31_28, QSPI0_SSL),
670 	PINMUX_IPSR_GPSR(IP3_31_28, WE1_N),
671 
672 	/* IPSR4 */
673 	PINMUX_IPSR_GPSR(IP4_3_0, EX_WAIT0),
674 	PINMUX_IPSR_MSEL(IP4_3_0, CAN_CLK_B, SEL_CANCLK_1),
675 	PINMUX_IPSR_MSEL(IP4_3_0, SCIF_CLK_A, SEL_SCIFCLK_0),
676 	PINMUX_IPSR_GPSR(IP4_7_4, DU0_DR0),
677 	PINMUX_IPSR_MSEL(IP4_7_4, RX5_C, SEL_SCIF5_2),
678 	PINMUX_IPSR_MSEL(IP4_7_4, SCL2_D, SEL_I2C02_3),
679 	PINMUX_IPSR_GPSR(IP4_7_4, A0),
680 	PINMUX_IPSR_GPSR(IP4_11_8, DU0_DR1),
681 	PINMUX_IPSR_MSEL(IP4_11_8, TX5_C, SEL_SCIF5_2),
682 	PINMUX_IPSR_MSEL(IP4_11_8, SDA2_D, SEL_I2C02_3),
683 	PINMUX_IPSR_GPSR(IP4_11_8, A1),
684 	PINMUX_IPSR_GPSR(IP4_15_12, DU0_DR2),
685 	PINMUX_IPSR_MSEL(IP4_15_12, RX0_D, SEL_SCIF0_3),
686 	PINMUX_IPSR_MSEL(IP4_15_12, SCL0_E, SEL_I2C00_4),
687 	PINMUX_IPSR_GPSR(IP4_15_12, A2),
688 	PINMUX_IPSR_GPSR(IP4_19_16, DU0_DR3),
689 	PINMUX_IPSR_MSEL(IP4_19_16, TX0_D, SEL_SCIF0_3),
690 	PINMUX_IPSR_MSEL(IP4_19_16, SDA0_E, SEL_I2C00_4),
691 	PINMUX_IPSR_GPSR(IP4_19_16, PWM0_B),
692 	PINMUX_IPSR_GPSR(IP4_19_16, A3),
693 	PINMUX_IPSR_GPSR(IP4_23_20, DU0_DR4),
694 	PINMUX_IPSR_MSEL(IP4_23_20, RX1_D, SEL_SCIF1_3),
695 	PINMUX_IPSR_GPSR(IP4_23_20, A4),
696 	PINMUX_IPSR_GPSR(IP4_27_24, DU0_DR5),
697 	PINMUX_IPSR_MSEL(IP4_27_24, TX1_D, SEL_SCIF1_3),
698 	PINMUX_IPSR_GPSR(IP4_27_24, PWM1_B),
699 	PINMUX_IPSR_GPSR(IP4_27_24, A5),
700 	PINMUX_IPSR_GPSR(IP4_31_28, DU0_DR6),
701 	PINMUX_IPSR_MSEL(IP4_31_28, RX2_C, SEL_SCIF2_2),
702 	PINMUX_IPSR_GPSR(IP4_31_28, A6),
703 
704 	/* IPSR5 */
705 	PINMUX_IPSR_GPSR(IP5_3_0, DU0_DR7),
706 	PINMUX_IPSR_MSEL(IP5_3_0, TX2_C, SEL_SCIF2_2),
707 	PINMUX_IPSR_GPSR(IP5_3_0, PWM2_B),
708 	PINMUX_IPSR_GPSR(IP5_3_0, A7),
709 	PINMUX_IPSR_GPSR(IP5_7_4, DU0_DG0),
710 	PINMUX_IPSR_MSEL(IP5_7_4, RX3_B, SEL_SCIF3_1),
711 	PINMUX_IPSR_MSEL(IP5_7_4, SCL3_D, SEL_I2C03_3),
712 	PINMUX_IPSR_GPSR(IP5_7_4, A8),
713 	PINMUX_IPSR_GPSR(IP5_11_8, DU0_DG1),
714 	PINMUX_IPSR_MSEL(IP5_11_8, TX3_B, SEL_SCIF3_1),
715 	PINMUX_IPSR_MSEL(IP5_11_8, SDA3_D, SEL_I2C03_3),
716 	PINMUX_IPSR_GPSR(IP5_11_8, PWM3_B),
717 	PINMUX_IPSR_GPSR(IP5_11_8, A9),
718 	PINMUX_IPSR_GPSR(IP5_15_12, DU0_DG2),
719 	PINMUX_IPSR_MSEL(IP5_15_12, RX4_D, SEL_SCIF4_3),
720 	PINMUX_IPSR_GPSR(IP5_15_12, A10),
721 	PINMUX_IPSR_GPSR(IP5_19_16, DU0_DG3),
722 	PINMUX_IPSR_MSEL(IP5_19_16, TX4_D, SEL_SCIF4_3),
723 	PINMUX_IPSR_GPSR(IP5_19_16, PWM4_B),
724 	PINMUX_IPSR_GPSR(IP5_19_16, A11),
725 	PINMUX_IPSR_GPSR(IP5_23_20, DU0_DG4),
726 	PINMUX_IPSR_MSEL(IP5_23_20, HRX0_A, SEL_HSCIF0_0),
727 	PINMUX_IPSR_GPSR(IP5_23_20, A12),
728 	PINMUX_IPSR_GPSR(IP5_27_24, DU0_DG5),
729 	PINMUX_IPSR_MSEL(IP5_27_24, HTX0_A, SEL_HSCIF0_0),
730 	PINMUX_IPSR_GPSR(IP5_27_24, PWM5_B),
731 	PINMUX_IPSR_GPSR(IP5_27_24, A13),
732 	PINMUX_IPSR_GPSR(IP5_31_28, DU0_DG6),
733 	PINMUX_IPSR_MSEL(IP5_31_28, HRX1_C, SEL_HSCIF1_2),
734 	PINMUX_IPSR_GPSR(IP5_31_28, A14),
735 
736 	/* IPSR6 */
737 	PINMUX_IPSR_GPSR(IP6_3_0, DU0_DG7),
738 	PINMUX_IPSR_MSEL(IP6_3_0, HTX1_C, SEL_HSCIF1_2),
739 	PINMUX_IPSR_GPSR(IP6_3_0, PWM6_B),
740 	PINMUX_IPSR_GPSR(IP6_3_0, A15),
741 	PINMUX_IPSR_GPSR(IP6_7_4, DU0_DB0),
742 	PINMUX_IPSR_MSEL(IP6_7_4, SCL4_D, SEL_I2C04_3),
743 	PINMUX_IPSR_MSEL(IP6_7_4, CAN0_RX_C, SEL_CAN0_2),
744 	PINMUX_IPSR_GPSR(IP6_7_4, A16),
745 	PINMUX_IPSR_GPSR(IP6_11_8, DU0_DB1),
746 	PINMUX_IPSR_MSEL(IP6_11_8, SDA4_D, SEL_I2C04_3),
747 	PINMUX_IPSR_MSEL(IP6_11_8, CAN0_TX_C, SEL_CAN0_2),
748 	PINMUX_IPSR_GPSR(IP6_11_8, A17),
749 	PINMUX_IPSR_GPSR(IP6_15_12, DU0_DB2),
750 	PINMUX_IPSR_GPSR(IP6_15_12, HCTS0_N),
751 	PINMUX_IPSR_GPSR(IP6_15_12, A18),
752 	PINMUX_IPSR_GPSR(IP6_19_16, DU0_DB3),
753 	PINMUX_IPSR_GPSR(IP6_19_16, HRTS0_N),
754 	PINMUX_IPSR_GPSR(IP6_19_16, A19),
755 	PINMUX_IPSR_GPSR(IP6_23_20, DU0_DB4),
756 	PINMUX_IPSR_MSEL(IP6_23_20, HCTS1_N_C, SEL_HSCIF1_2),
757 	PINMUX_IPSR_GPSR(IP6_23_20, A20),
758 	PINMUX_IPSR_GPSR(IP6_27_24, DU0_DB5),
759 	PINMUX_IPSR_MSEL(IP6_27_24, HRTS1_N_C, SEL_HSCIF1_2),
760 	PINMUX_IPSR_GPSR(IP6_27_24, A21),
761 	PINMUX_IPSR_GPSR(IP6_31_28, DU0_DB6),
762 	PINMUX_IPSR_GPSR(IP6_31_28, A22),
763 
764 	/* IPSR7 */
765 	PINMUX_IPSR_GPSR(IP7_3_0, DU0_DB7),
766 	PINMUX_IPSR_GPSR(IP7_3_0, A23),
767 	PINMUX_IPSR_GPSR(IP7_7_4, DU0_DOTCLKIN),
768 	PINMUX_IPSR_GPSR(IP7_7_4, A24),
769 	PINMUX_IPSR_GPSR(IP7_11_8, DU0_DOTCLKOUT0),
770 	PINMUX_IPSR_GPSR(IP7_11_8, A25),
771 	PINMUX_IPSR_GPSR(IP7_15_12, DU0_DOTCLKOUT1),
772 	PINMUX_IPSR_MSEL(IP7_15_12, MSIOF2_RXD_B, SEL_MSIOF2_1),
773 	PINMUX_IPSR_GPSR(IP7_15_12, CS1_N_A26),
774 	PINMUX_IPSR_GPSR(IP7_19_16, DU0_EXHSYNC_DU0_HSYNC),
775 	PINMUX_IPSR_MSEL(IP7_19_16, MSIOF2_TXD_B, SEL_MSIOF2_1),
776 	PINMUX_IPSR_GPSR(IP7_19_16, DREQ0_N),
777 	PINMUX_IPSR_GPSR(IP7_23_20, DU0_EXVSYNC_DU0_VSYNC),
778 	PINMUX_IPSR_MSEL(IP7_23_20, MSIOF2_SYNC_B, SEL_MSIOF2_1),
779 	PINMUX_IPSR_GPSR(IP7_23_20, DACK0),
780 	PINMUX_IPSR_GPSR(IP7_27_24, DU0_EXODDF_DU0_ODDF_DISP_CDE),
781 	PINMUX_IPSR_MSEL(IP7_27_24, MSIOF2_SCK_B, SEL_MSIOF2_1),
782 	PINMUX_IPSR_GPSR(IP7_27_24, DRACK0),
783 	PINMUX_IPSR_GPSR(IP7_31_28, DU0_DISP),
784 	PINMUX_IPSR_MSEL(IP7_31_28, CAN1_RX_C, SEL_CAN1_2),
785 
786 	/* IPSR8 */
787 	PINMUX_IPSR_GPSR(IP8_3_0, DU0_CDE),
788 	PINMUX_IPSR_MSEL(IP8_3_0, CAN1_TX_C, SEL_CAN1_2),
789 	PINMUX_IPSR_GPSR(IP8_7_4, VI1_CLK),
790 	PINMUX_IPSR_GPSR(IP8_7_4, AVB_RX_CLK),
791 	PINMUX_IPSR_GPSR(IP8_7_4, ETH_REF_CLK),
792 	PINMUX_IPSR_GPSR(IP8_11_8, VI1_DATA0),
793 	PINMUX_IPSR_GPSR(IP8_11_8, AVB_RX_DV),
794 	PINMUX_IPSR_GPSR(IP8_11_8, ETH_CRS_DV),
795 	PINMUX_IPSR_GPSR(IP8_15_12, VI1_DATA1),
796 	PINMUX_IPSR_GPSR(IP8_15_12, AVB_RXD0),
797 	PINMUX_IPSR_GPSR(IP8_15_12, ETH_RXD0),
798 	PINMUX_IPSR_GPSR(IP8_19_16, VI1_DATA2),
799 	PINMUX_IPSR_GPSR(IP8_19_16, AVB_RXD1),
800 	PINMUX_IPSR_GPSR(IP8_19_16, ETH_RXD1),
801 	PINMUX_IPSR_GPSR(IP8_23_20, VI1_DATA3),
802 	PINMUX_IPSR_GPSR(IP8_23_20, AVB_RXD2),
803 	PINMUX_IPSR_GPSR(IP8_23_20, ETH_MDIO),
804 	PINMUX_IPSR_GPSR(IP8_27_24, VI1_DATA4),
805 	PINMUX_IPSR_GPSR(IP8_27_24, AVB_RXD3),
806 	PINMUX_IPSR_GPSR(IP8_27_24, ETH_RX_ER),
807 	PINMUX_IPSR_GPSR(IP8_31_28, VI1_DATA5),
808 	PINMUX_IPSR_GPSR(IP8_31_28, AVB_RXD4),
809 	PINMUX_IPSR_GPSR(IP8_31_28, ETH_LINK),
810 
811 	/* IPSR9 */
812 	PINMUX_IPSR_GPSR(IP9_3_0, VI1_DATA6),
813 	PINMUX_IPSR_GPSR(IP9_3_0, AVB_RXD5),
814 	PINMUX_IPSR_GPSR(IP9_3_0, ETH_TXD1),
815 	PINMUX_IPSR_GPSR(IP9_7_4, VI1_DATA7),
816 	PINMUX_IPSR_GPSR(IP9_7_4, AVB_RXD6),
817 	PINMUX_IPSR_GPSR(IP9_7_4, ETH_TX_EN),
818 	PINMUX_IPSR_GPSR(IP9_11_8, VI1_CLKENB),
819 	PINMUX_IPSR_MSEL(IP9_11_8, SCL3_A, SEL_I2C03_0),
820 	PINMUX_IPSR_GPSR(IP9_11_8, AVB_RXD7),
821 	PINMUX_IPSR_GPSR(IP9_11_8, ETH_MAGIC),
822 	PINMUX_IPSR_GPSR(IP9_15_12, VI1_FIELD),
823 	PINMUX_IPSR_MSEL(IP9_15_12, SDA3_A, SEL_I2C03_0),
824 	PINMUX_IPSR_GPSR(IP9_15_12, AVB_RX_ER),
825 	PINMUX_IPSR_GPSR(IP9_15_12, ETH_TXD0),
826 	PINMUX_IPSR_GPSR(IP9_19_16, VI1_HSYNC_N),
827 	PINMUX_IPSR_MSEL(IP9_19_16, RX0_B, SEL_SCIF0_1),
828 	PINMUX_IPSR_MSEL(IP9_19_16, SCL0_C, SEL_I2C00_2),
829 	PINMUX_IPSR_GPSR(IP9_19_16, AVB_GTXREFCLK),
830 	PINMUX_IPSR_GPSR(IP9_19_16, ETH_MDC),
831 	PINMUX_IPSR_GPSR(IP9_23_20, VI1_VSYNC_N),
832 	PINMUX_IPSR_MSEL(IP9_23_20, TX0_B, SEL_SCIF0_1),
833 	PINMUX_IPSR_MSEL(IP9_23_20, SDA0_C, SEL_I2C00_2),
834 	PINMUX_IPSR_GPSR(IP9_23_20, AUDIO_CLKOUT_B),
835 	PINMUX_IPSR_GPSR(IP9_23_20, AVB_TX_CLK),
836 	PINMUX_IPSR_GPSR(IP9_27_24, VI1_DATA8),
837 	PINMUX_IPSR_MSEL(IP9_27_24, SCL2_B, SEL_I2C02_1),
838 	PINMUX_IPSR_GPSR(IP9_27_24, AVB_TX_EN),
839 	PINMUX_IPSR_GPSR(IP9_31_28, VI1_DATA9),
840 	PINMUX_IPSR_MSEL(IP9_31_28, SDA2_B, SEL_I2C02_1),
841 	PINMUX_IPSR_GPSR(IP9_31_28, AVB_TXD0),
842 
843 	/* IPSR10 */
844 	PINMUX_IPSR_GPSR(IP10_3_0, VI1_DATA10),
845 	PINMUX_IPSR_MSEL(IP10_3_0, CAN0_RX_B, SEL_CAN0_1),
846 	PINMUX_IPSR_GPSR(IP10_3_0, AVB_TXD1),
847 	PINMUX_IPSR_GPSR(IP10_7_4, VI1_DATA11),
848 	PINMUX_IPSR_MSEL(IP10_7_4, CAN0_TX_B, SEL_CAN0_1),
849 	PINMUX_IPSR_GPSR(IP10_7_4, AVB_TXD2),
850 	PINMUX_IPSR_GPSR(IP10_11_8, AVB_TXD3),
851 	PINMUX_IPSR_MSEL(IP10_11_8, AUDIO_CLKA_B, SEL_ADGA_1),
852 	PINMUX_IPSR_MSEL(IP10_11_8, SSI_SCK1_D, SEL_SSI1_3),
853 	PINMUX_IPSR_MSEL(IP10_11_8, RX5_F, SEL_SCIF5_5),
854 	PINMUX_IPSR_MSEL(IP10_11_8, MSIOF0_RXD_B, SEL_MSIOF0_1),
855 	PINMUX_IPSR_GPSR(IP10_15_12, AVB_TXD4),
856 	PINMUX_IPSR_MSEL(IP10_15_12, AUDIO_CLKB_B, SEL_ADGB_1),
857 	PINMUX_IPSR_MSEL(IP10_15_12, SSI_WS1_D, SEL_SSI1_3),
858 	PINMUX_IPSR_MSEL(IP10_15_12, TX5_F, SEL_SCIF5_5),
859 	PINMUX_IPSR_MSEL(IP10_15_12, MSIOF0_TXD_B, SEL_MSIOF0_1),
860 	PINMUX_IPSR_GPSR(IP10_19_16, AVB_TXD5),
861 	PINMUX_IPSR_MSEL(IP10_19_16, SCIF_CLK_B, SEL_SCIFCLK_1),
862 	PINMUX_IPSR_MSEL(IP10_19_16, AUDIO_CLKC_B, SEL_ADGC_1),
863 	PINMUX_IPSR_MSEL(IP10_19_16, SSI_SDATA1_D, SEL_SSI1_3),
864 	PINMUX_IPSR_MSEL(IP10_19_16, MSIOF0_SCK_B, SEL_MSIOF0_1),
865 	PINMUX_IPSR_MSEL(IP10_23_20, SCL0_A, SEL_I2C00_0),
866 	PINMUX_IPSR_MSEL(IP10_23_20, RX0_C, SEL_SCIF0_2),
867 	PINMUX_IPSR_GPSR(IP10_23_20, PWM5_A),
868 	PINMUX_IPSR_MSEL(IP10_23_20, TCLK1_B, SEL_TMU1_1),
869 	PINMUX_IPSR_GPSR(IP10_23_20, AVB_TXD6),
870 	PINMUX_IPSR_MSEL(IP10_23_20, CAN1_RX_D, SEL_CAN1_3),
871 	PINMUX_IPSR_MSEL(IP10_23_20, MSIOF0_SYNC_B, SEL_MSIOF0_1),
872 	PINMUX_IPSR_MSEL(IP10_27_24, SDA0_A, SEL_I2C00_0),
873 	PINMUX_IPSR_MSEL(IP10_27_24, TX0_C, SEL_SCIF0_2),
874 	PINMUX_IPSR_GPSR(IP10_27_24, IRQ5),
875 	PINMUX_IPSR_MSEL(IP10_27_24, CAN_CLK_A, SEL_CANCLK_0),
876 	PINMUX_IPSR_GPSR(IP10_27_24, AVB_GTX_CLK),
877 	PINMUX_IPSR_MSEL(IP10_27_24, CAN1_TX_D, SEL_CAN1_3),
878 	PINMUX_IPSR_GPSR(IP10_27_24, DVC_MUTE),
879 	PINMUX_IPSR_MSEL(IP10_31_28, SCL1_A, SEL_I2C01_0),
880 	PINMUX_IPSR_MSEL(IP10_31_28, RX4_A, SEL_SCIF4_0),
881 	PINMUX_IPSR_GPSR(IP10_31_28, PWM5_D),
882 	PINMUX_IPSR_GPSR(IP10_31_28, DU1_DR0),
883 	PINMUX_IPSR_MSEL(IP10_31_28, SSI_SCK6_B, SEL_SSI6_1),
884 	PINMUX_IPSR_GPSR(IP10_31_28, VI0_G0),
885 
886 	/* IPSR11 */
887 	PINMUX_IPSR_MSEL(IP11_3_0, SDA1_A, SEL_I2C01_0),
888 	PINMUX_IPSR_MSEL(IP11_3_0, TX4_A, SEL_SCIF4_0),
889 	PINMUX_IPSR_GPSR(IP11_3_0, DU1_DR1),
890 	PINMUX_IPSR_MSEL(IP11_3_0, SSI_WS6_B, SEL_SSI6_1),
891 	PINMUX_IPSR_GPSR(IP11_3_0, VI0_G1),
892 	PINMUX_IPSR_MSEL(IP11_7_4, MSIOF0_RXD_A, SEL_MSIOF0_0),
893 	PINMUX_IPSR_MSEL(IP11_7_4, RX5_A, SEL_SCIF5_0),
894 	PINMUX_IPSR_MSEL(IP11_7_4, SCL2_C, SEL_I2C02_2),
895 	PINMUX_IPSR_GPSR(IP11_7_4, DU1_DR2),
896 	PINMUX_IPSR_GPSR(IP11_7_4, QSPI1_MOSI_QSPI1_IO0),
897 	PINMUX_IPSR_MSEL(IP11_7_4, SSI_SDATA6_B, SEL_SSI6_1),
898 	PINMUX_IPSR_GPSR(IP11_7_4, VI0_G2),
899 	PINMUX_IPSR_MSEL(IP11_11_8, MSIOF0_TXD_A, SEL_MSIOF0_0),
900 	PINMUX_IPSR_MSEL(IP11_11_8, TX5_A, SEL_SCIF5_0),
901 	PINMUX_IPSR_MSEL(IP11_11_8, SDA2_C, SEL_I2C02_2),
902 	PINMUX_IPSR_GPSR(IP11_11_8, DU1_DR3),
903 	PINMUX_IPSR_GPSR(IP11_11_8, QSPI1_MISO_QSPI1_IO1),
904 	PINMUX_IPSR_MSEL(IP11_11_8, SSI_WS78_B, SEL_SSI7_1),
905 	PINMUX_IPSR_GPSR(IP11_11_8, VI0_G3),
906 	PINMUX_IPSR_MSEL(IP11_15_12, MSIOF0_SCK_A, SEL_MSIOF0_0),
907 	PINMUX_IPSR_GPSR(IP11_15_12, IRQ0),
908 	PINMUX_IPSR_GPSR(IP11_15_12, DU1_DR4),
909 	PINMUX_IPSR_GPSR(IP11_15_12, QSPI1_SPCLK),
910 	PINMUX_IPSR_MSEL(IP11_15_12, SSI_SCK78_B, SEL_SSI7_1),
911 	PINMUX_IPSR_GPSR(IP11_15_12, VI0_G4),
912 	PINMUX_IPSR_MSEL(IP11_19_16, MSIOF0_SYNC_A, SEL_MSIOF0_0),
913 	PINMUX_IPSR_GPSR(IP11_19_16, PWM1_A),
914 	PINMUX_IPSR_GPSR(IP11_19_16, DU1_DR5),
915 	PINMUX_IPSR_GPSR(IP11_19_16, QSPI1_IO2),
916 	PINMUX_IPSR_MSEL(IP11_19_16, SSI_SDATA7_B, SEL_SSI7_1),
917 	PINMUX_IPSR_MSEL(IP11_23_20, MSIOF0_SS1_A, SEL_MSIOF0_0),
918 	PINMUX_IPSR_GPSR(IP11_23_20, DU1_DR6),
919 	PINMUX_IPSR_GPSR(IP11_23_20, QSPI1_IO3),
920 	PINMUX_IPSR_MSEL(IP11_23_20, SSI_SDATA8_B, SEL_SSI8_1),
921 	PINMUX_IPSR_MSEL(IP11_27_24, MSIOF0_SS2_A, SEL_MSIOF0_0),
922 	PINMUX_IPSR_GPSR(IP11_27_24, DU1_DR7),
923 	PINMUX_IPSR_GPSR(IP11_27_24, QSPI1_SSL),
924 	PINMUX_IPSR_MSEL(IP11_31_28, HRX1_A, SEL_HSCIF1_0),
925 	PINMUX_IPSR_MSEL(IP11_31_28, SCL4_A, SEL_I2C04_0),
926 	PINMUX_IPSR_GPSR(IP11_31_28, PWM6_A),
927 	PINMUX_IPSR_GPSR(IP11_31_28, DU1_DG0),
928 	PINMUX_IPSR_MSEL(IP11_31_28, RX0_A, SEL_SCIF0_0),
929 
930 	/* IPSR12 */
931 	PINMUX_IPSR_MSEL(IP12_3_0, HTX1_A, SEL_HSCIF1_0),
932 	PINMUX_IPSR_MSEL(IP12_3_0, SDA4_A, SEL_I2C04_0),
933 	PINMUX_IPSR_GPSR(IP12_3_0, DU1_DG1),
934 	PINMUX_IPSR_MSEL(IP12_3_0, TX0_A, SEL_SCIF0_0),
935 	PINMUX_IPSR_MSEL(IP12_7_4, HCTS1_N_A, SEL_HSCIF1_0),
936 	PINMUX_IPSR_GPSR(IP12_7_4, PWM2_A),
937 	PINMUX_IPSR_GPSR(IP12_7_4, DU1_DG2),
938 	PINMUX_IPSR_MSEL(IP12_7_4, REMOCON_B, SEL_RCN_1),
939 	PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_A, SEL_HSCIF1_0),
940 	PINMUX_IPSR_GPSR(IP12_11_8, DU1_DG3),
941 	PINMUX_IPSR_MSEL(IP12_11_8, SSI_WS1_B, SEL_SSI1_1),
942 	PINMUX_IPSR_GPSR(IP12_11_8, IRQ1),
943 	PINMUX_IPSR_GPSR(IP12_15_12, SD2_CLK),
944 	PINMUX_IPSR_GPSR(IP12_15_12, HSCK1),
945 	PINMUX_IPSR_GPSR(IP12_15_12, DU1_DG4),
946 	PINMUX_IPSR_MSEL(IP12_15_12, SSI_SCK1_B, SEL_SSI1_1),
947 	PINMUX_IPSR_GPSR(IP12_19_16, SD2_CMD),
948 	PINMUX_IPSR_MSEL(IP12_19_16, SCIF1_SCK_A, SEL_SCIF1_0),
949 	PINMUX_IPSR_MSEL(IP12_19_16, TCLK2_A, SEL_TMU2_0),
950 	PINMUX_IPSR_GPSR(IP12_19_16, DU1_DG5),
951 	PINMUX_IPSR_MSEL(IP12_19_16, SSI_SCK2_B, SEL_SSI2_1),
952 	PINMUX_IPSR_GPSR(IP12_19_16, PWM3_A),
953 	PINMUX_IPSR_GPSR(IP12_23_20, SD2_DAT0),
954 	PINMUX_IPSR_MSEL(IP12_23_20, RX1_A, SEL_SCIF1_0),
955 	PINMUX_IPSR_MSEL(IP12_23_20, SCL1_E, SEL_I2C01_4),
956 	PINMUX_IPSR_GPSR(IP12_23_20, DU1_DG6),
957 	PINMUX_IPSR_MSEL(IP12_23_20, SSI_SDATA1_B, SEL_SSI1_1),
958 	PINMUX_IPSR_GPSR(IP12_27_24, SD2_DAT1),
959 	PINMUX_IPSR_MSEL(IP12_27_24, TX1_A, SEL_SCIF1_0),
960 	PINMUX_IPSR_MSEL(IP12_27_24, SDA1_E, SEL_I2C01_4),
961 	PINMUX_IPSR_GPSR(IP12_27_24, DU1_DG7),
962 	PINMUX_IPSR_MSEL(IP12_27_24, SSI_WS2_B, SEL_SSI2_1),
963 	PINMUX_IPSR_GPSR(IP12_31_28, SD2_DAT2),
964 	PINMUX_IPSR_MSEL(IP12_31_28, RX2_A, SEL_SCIF2_0),
965 	PINMUX_IPSR_GPSR(IP12_31_28, DU1_DB0),
966 	PINMUX_IPSR_MSEL(IP12_31_28, SSI_SDATA2_B, SEL_SSI2_1),
967 
968 	/* IPSR13 */
969 	PINMUX_IPSR_GPSR(IP13_3_0, SD2_DAT3),
970 	PINMUX_IPSR_MSEL(IP13_3_0, TX2_A, SEL_SCIF2_0),
971 	PINMUX_IPSR_GPSR(IP13_3_0, DU1_DB1),
972 	PINMUX_IPSR_MSEL(IP13_3_0, SSI_WS9_B, SEL_SSI9_1),
973 	PINMUX_IPSR_GPSR(IP13_7_4, SD2_CD),
974 	PINMUX_IPSR_MSEL(IP13_7_4, SCIF2_SCK_A, SEL_SCIF2_CLK_0),
975 	PINMUX_IPSR_GPSR(IP13_7_4, DU1_DB2),
976 	PINMUX_IPSR_MSEL(IP13_7_4, SSI_SCK9_B, SEL_SSI9_1),
977 	PINMUX_IPSR_GPSR(IP13_11_8, SD2_WP),
978 	PINMUX_IPSR_GPSR(IP13_11_8, SCIF3_SCK),
979 	PINMUX_IPSR_GPSR(IP13_11_8, DU1_DB3),
980 	PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA9_B, SEL_SSI9_1),
981 	PINMUX_IPSR_MSEL(IP13_15_12, RX3_A, SEL_SCIF3_0),
982 	PINMUX_IPSR_MSEL(IP13_15_12, SCL1_C, SEL_I2C01_2),
983 	PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_RXD_B, SEL_MSIOF1_1),
984 	PINMUX_IPSR_GPSR(IP13_15_12, DU1_DB4),
985 	PINMUX_IPSR_MSEL(IP13_15_12, AUDIO_CLKA_C, SEL_ADGA_2),
986 	PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA4_B, SEL_SSI4_1),
987 	PINMUX_IPSR_MSEL(IP13_19_16, TX3_A, SEL_SCIF3_0),
988 	PINMUX_IPSR_MSEL(IP13_19_16, SDA1_C, SEL_I2C01_2),
989 	PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_TXD_B, SEL_MSIOF1_1),
990 	PINMUX_IPSR_GPSR(IP13_19_16, DU1_DB5),
991 	PINMUX_IPSR_MSEL(IP13_19_16, AUDIO_CLKB_C, SEL_ADGB_2),
992 	PINMUX_IPSR_MSEL(IP13_19_16, SSI_WS4_B, SEL_SSI4_1),
993 	PINMUX_IPSR_MSEL(IP13_23_20, SCL2_A, SEL_I2C02_0),
994 	PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_SCK_B, SEL_MSIOF1_1),
995 	PINMUX_IPSR_GPSR(IP13_23_20, DU1_DB6),
996 	PINMUX_IPSR_MSEL(IP13_23_20, AUDIO_CLKC_C, SEL_ADGC_2),
997 	PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK4_B, SEL_SSI4_1),
998 	PINMUX_IPSR_MSEL(IP13_27_24, SDA2_A, SEL_I2C02_0),
999 	PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SYNC_B, SEL_MSIOF1_1),
1000 	PINMUX_IPSR_GPSR(IP13_27_24, DU1_DB7),
1001 	PINMUX_IPSR_GPSR(IP13_27_24, AUDIO_CLKOUT_C),
1002 	PINMUX_IPSR_MSEL(IP13_31_28, SSI_SCK5_A, SEL_SSI5_0),
1003 	PINMUX_IPSR_GPSR(IP13_31_28, DU1_DOTCLKOUT1),
1004 
1005 	/* IPSR14 */
1006 	PINMUX_IPSR_MSEL(IP14_3_0, SSI_WS5_A, SEL_SSI5_0),
1007 	PINMUX_IPSR_MSEL(IP14_3_0, SCL3_C, SEL_I2C03_2),
1008 	PINMUX_IPSR_GPSR(IP14_3_0, DU1_DOTCLKIN),
1009 	PINMUX_IPSR_MSEL(IP14_7_4, SSI_SDATA5_A, SEL_SSI5_0),
1010 	PINMUX_IPSR_MSEL(IP14_7_4, SDA3_C, SEL_I2C03_2),
1011 	PINMUX_IPSR_GPSR(IP14_7_4, DU1_DOTCLKOUT0),
1012 	PINMUX_IPSR_MSEL(IP14_11_8, SSI_SCK6_A, SEL_SSI6_0),
1013 	PINMUX_IPSR_GPSR(IP14_11_8, DU1_EXODDF_DU1_ODDF_DISP_CDE),
1014 	PINMUX_IPSR_MSEL(IP14_15_12, SSI_WS6_A, SEL_SSI6_0),
1015 	PINMUX_IPSR_MSEL(IP14_15_12, SCL4_C, SEL_I2C04_2),
1016 	PINMUX_IPSR_GPSR(IP14_15_12, DU1_EXHSYNC_DU1_HSYNC),
1017 	PINMUX_IPSR_MSEL(IP14_19_16, SSI_SDATA6_A, SEL_SSI6_0),
1018 	PINMUX_IPSR_MSEL(IP14_19_16, SDA4_C, SEL_I2C04_2),
1019 	PINMUX_IPSR_GPSR(IP14_19_16, DU1_EXVSYNC_DU1_VSYNC),
1020 	PINMUX_IPSR_MSEL(IP14_23_20, SSI_SCK78_A, SEL_SSI7_0),
1021 	PINMUX_IPSR_MSEL(IP14_23_20, SDA4_E, SEL_I2C04_4),
1022 	PINMUX_IPSR_GPSR(IP14_23_20, DU1_DISP),
1023 	PINMUX_IPSR_MSEL(IP14_27_24, SSI_WS78_A, SEL_SSI7_0),
1024 	PINMUX_IPSR_MSEL(IP14_27_24, SCL4_E, SEL_I2C04_4),
1025 	PINMUX_IPSR_GPSR(IP14_27_24, DU1_CDE),
1026 	PINMUX_IPSR_MSEL(IP14_31_28, SSI_SDATA7_A, SEL_SSI7_0),
1027 	PINMUX_IPSR_GPSR(IP14_31_28, IRQ8),
1028 	PINMUX_IPSR_MSEL(IP14_31_28, AUDIO_CLKA_D, SEL_ADGA_3),
1029 	PINMUX_IPSR_MSEL(IP14_31_28, CAN_CLK_D, SEL_CANCLK_3),
1030 	PINMUX_IPSR_GPSR(IP14_31_28, VI0_G5),
1031 
1032 	/* IPSR15 */
1033 	PINMUX_IPSR_MSEL(IP15_3_0, SSI_SCK0129_A, SEL_SSI0_0),
1034 	PINMUX_IPSR_MSEL(IP15_3_0, MSIOF1_RXD_A, SEL_MSIOF1_0),
1035 	PINMUX_IPSR_MSEL(IP15_3_0, RX5_D, SEL_SCIF5_3),
1036 	PINMUX_IPSR_GPSR(IP15_3_0, VI0_G6),
1037 	PINMUX_IPSR_MSEL(IP15_7_4, SSI_WS0129_A, SEL_SSI0_0),
1038 	PINMUX_IPSR_MSEL(IP15_7_4, MSIOF1_TXD_A, SEL_MSIOF1_0),
1039 	PINMUX_IPSR_MSEL(IP15_7_4, TX5_D, SEL_SCIF5_3),
1040 	PINMUX_IPSR_GPSR(IP15_7_4, VI0_G7),
1041 	PINMUX_IPSR_MSEL(IP15_11_8, SSI_SDATA0_A, SEL_SSI0_0),
1042 	PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SYNC_A, SEL_MSIOF1_0),
1043 	PINMUX_IPSR_GPSR(IP15_11_8, PWM0_C),
1044 	PINMUX_IPSR_GPSR(IP15_11_8, VI0_R0),
1045 	PINMUX_IPSR_GPSR(IP15_15_12, SSI_SCK34),
1046 	PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SCK_A, SEL_MSIOF1_0),
1047 	PINMUX_IPSR_GPSR(IP15_15_12, AVB_MDC),
1048 	PINMUX_IPSR_GPSR(IP15_15_12, DACK1),
1049 	PINMUX_IPSR_GPSR(IP15_15_12, VI0_R1),
1050 	PINMUX_IPSR_GPSR(IP15_19_16, SSI_WS34),
1051 	PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_SS1_A, SEL_MSIOF1_0),
1052 	PINMUX_IPSR_GPSR(IP15_19_16, AVB_MDIO),
1053 	PINMUX_IPSR_MSEL(IP15_19_16, CAN1_RX_A, SEL_CAN1_0),
1054 	PINMUX_IPSR_GPSR(IP15_19_16, DREQ1_N),
1055 	PINMUX_IPSR_GPSR(IP15_19_16, VI0_R2),
1056 	PINMUX_IPSR_GPSR(IP15_23_20, SSI_SDATA3),
1057 	PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_SS2_A, SEL_MSIOF1_0),
1058 	PINMUX_IPSR_GPSR(IP15_23_20, AVB_LINK),
1059 	PINMUX_IPSR_MSEL(IP15_23_20, CAN1_TX_A, SEL_CAN1_0),
1060 	PINMUX_IPSR_GPSR(IP15_23_20, DREQ2_N),
1061 	PINMUX_IPSR_GPSR(IP15_23_20, VI0_R3),
1062 	PINMUX_IPSR_MSEL(IP15_27_24, SSI_SCK4_A, SEL_SSI4_0),
1063 	PINMUX_IPSR_GPSR(IP15_27_24, AVB_MAGIC),
1064 	PINMUX_IPSR_GPSR(IP15_27_24, VI0_R4),
1065 	PINMUX_IPSR_MSEL(IP15_31_28, SSI_WS4_A, SEL_SSI4_0),
1066 	PINMUX_IPSR_GPSR(IP15_31_28, AVB_PHY_INT),
1067 	PINMUX_IPSR_GPSR(IP15_31_28, VI0_R5),
1068 
1069 	/* IPSR16 */
1070 	PINMUX_IPSR_MSEL(IP16_3_0, SSI_SDATA4_A, SEL_SSI4_0),
1071 	PINMUX_IPSR_GPSR(IP16_3_0, AVB_CRS),
1072 	PINMUX_IPSR_GPSR(IP16_3_0, VI0_R6),
1073 	PINMUX_IPSR_MSEL(IP16_7_4, SSI_SCK1_A, SEL_SSI1_0),
1074 	PINMUX_IPSR_MSEL(IP16_7_4, SCIF1_SCK_B, SEL_SCIF1_1),
1075 	PINMUX_IPSR_GPSR(IP16_7_4, PWM1_D),
1076 	PINMUX_IPSR_GPSR(IP16_7_4, IRQ9),
1077 	PINMUX_IPSR_MSEL(IP16_7_4, REMOCON_A, SEL_RCN_0),
1078 	PINMUX_IPSR_GPSR(IP16_7_4, DACK2),
1079 	PINMUX_IPSR_GPSR(IP16_7_4, VI0_CLK),
1080 	PINMUX_IPSR_GPSR(IP16_7_4, AVB_COL),
1081 	PINMUX_IPSR_MSEL(IP16_11_8, SSI_SDATA8_A, SEL_SSI8_0),
1082 	PINMUX_IPSR_MSEL(IP16_11_8, RX1_B, SEL_SCIF1_1),
1083 	PINMUX_IPSR_MSEL(IP16_11_8, CAN0_RX_D, SEL_CAN0_3),
1084 	PINMUX_IPSR_MSEL(IP16_11_8, AVB_AVTP_CAPTURE_B, SEL_AVB_1),
1085 	PINMUX_IPSR_GPSR(IP16_11_8, VI0_R7),
1086 	PINMUX_IPSR_MSEL(IP16_15_12, SSI_WS1_A, SEL_SSI1_0),
1087 	PINMUX_IPSR_MSEL(IP16_15_12, TX1_B, SEL_SCIF1_1),
1088 	PINMUX_IPSR_MSEL(IP16_15_12, CAN0_TX_D, SEL_CAN0_3),
1089 	PINMUX_IPSR_MSEL(IP16_15_12, AVB_AVTP_MATCH_B, SEL_AVB_1),
1090 	PINMUX_IPSR_GPSR(IP16_15_12, VI0_DATA0_VI0_B0),
1091 	PINMUX_IPSR_MSEL(IP16_19_16, SSI_SDATA1_A, SEL_SSI1_0),
1092 	PINMUX_IPSR_MSEL(IP16_19_16, HRX1_B, SEL_HSCIF1_1),
1093 	PINMUX_IPSR_GPSR(IP16_19_16, VI0_DATA1_VI0_B1),
1094 	PINMUX_IPSR_MSEL(IP16_23_20, SSI_SCK2_A, SEL_SSI2_0),
1095 	PINMUX_IPSR_MSEL(IP16_23_20, HTX1_B, SEL_HSCIF1_1),
1096 	PINMUX_IPSR_GPSR(IP16_23_20, AVB_TXD7),
1097 	PINMUX_IPSR_GPSR(IP16_23_20, VI0_DATA2_VI0_B2),
1098 	PINMUX_IPSR_MSEL(IP16_27_24, SSI_WS2_A, SEL_SSI2_0),
1099 	PINMUX_IPSR_MSEL(IP16_27_24, HCTS1_N_B, SEL_HSCIF1_1),
1100 	PINMUX_IPSR_GPSR(IP16_27_24, AVB_TX_ER),
1101 	PINMUX_IPSR_GPSR(IP16_27_24, VI0_DATA3_VI0_B3),
1102 	PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA2_A, SEL_SSI2_0),
1103 	PINMUX_IPSR_MSEL(IP16_31_28, HRTS1_N_B, SEL_HSCIF1_1),
1104 	PINMUX_IPSR_GPSR(IP16_31_28, VI0_DATA4_VI0_B4),
1105 
1106 	/* IPSR17 */
1107 	PINMUX_IPSR_MSEL(IP17_3_0, SSI_SCK9_A, SEL_SSI9_0),
1108 	PINMUX_IPSR_MSEL(IP17_3_0, RX2_B, SEL_SCIF2_1),
1109 	PINMUX_IPSR_MSEL(IP17_3_0, SCL3_E, SEL_I2C03_4),
1110 	PINMUX_IPSR_GPSR(IP17_3_0, EX_WAIT1),
1111 	PINMUX_IPSR_GPSR(IP17_3_0, VI0_DATA5_VI0_B5),
1112 	PINMUX_IPSR_MSEL(IP17_7_4, SSI_WS9_A, SEL_SSI9_0),
1113 	PINMUX_IPSR_MSEL(IP17_7_4, TX2_B, SEL_SCIF2_1),
1114 	PINMUX_IPSR_MSEL(IP17_7_4, SDA3_E, SEL_I2C03_4),
1115 	PINMUX_IPSR_GPSR(IP17_7_4, VI0_DATA6_VI0_B6),
1116 	PINMUX_IPSR_MSEL(IP17_11_8, SSI_SDATA9_A, SEL_SSI9_0),
1117 	PINMUX_IPSR_GPSR(IP17_11_8, SCIF2_SCK_B),
1118 	PINMUX_IPSR_GPSR(IP17_11_8, PWM2_D),
1119 	PINMUX_IPSR_GPSR(IP17_11_8, VI0_DATA7_VI0_B7),
1120 	PINMUX_IPSR_MSEL(IP17_15_12, AUDIO_CLKA_A, SEL_ADGA_0),
1121 	PINMUX_IPSR_MSEL(IP17_15_12, SCL0_B, SEL_I2C00_1),
1122 	PINMUX_IPSR_GPSR(IP17_15_12, VI0_CLKENB),
1123 	PINMUX_IPSR_MSEL(IP17_19_16, AUDIO_CLKB_A, SEL_ADGB_0),
1124 	PINMUX_IPSR_MSEL(IP17_19_16, SDA0_B, SEL_I2C00_1),
1125 	PINMUX_IPSR_GPSR(IP17_19_16, VI0_FIELD),
1126 	PINMUX_IPSR_MSEL(IP17_23_20, AUDIO_CLKC_A, SEL_ADGC_0),
1127 	PINMUX_IPSR_MSEL(IP17_23_20, SCL4_B, SEL_I2C04_1),
1128 	PINMUX_IPSR_GPSR(IP17_23_20, VI0_HSYNC_N),
1129 	PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_A),
1130 	PINMUX_IPSR_MSEL(IP17_27_24, SDA4_B, SEL_I2C04_1),
1131 	PINMUX_IPSR_GPSR(IP17_27_24, VI0_VSYNC_N),
1132 };
1133 
1134 /*
1135  * Pins not associated with a GPIO port.
1136  */
1137 enum {
1138 	GP_ASSIGN_LAST(),
1139 	NOGP_ALL(),
1140 };
1141 
1142 static const struct sh_pfc_pin pinmux_pins[] = {
1143 	PINMUX_GPIO_GP_ALL(),
1144 	PINMUX_NOGP_ALL(),
1145 };
1146 
1147 /* - AVB -------------------------------------------------------------------- */
1148 static const unsigned int avb_col_pins[] = {
1149 	RCAR_GP_PIN(5, 18),
1150 };
1151 static const unsigned int avb_col_mux[] = {
1152 	AVB_COL_MARK,
1153 };
1154 static const unsigned int avb_crs_pins[] = {
1155 	RCAR_GP_PIN(5, 17),
1156 };
1157 static const unsigned int avb_crs_mux[] = {
1158 	AVB_CRS_MARK,
1159 };
1160 static const unsigned int avb_link_pins[] = {
1161 	RCAR_GP_PIN(5, 14),
1162 };
1163 static const unsigned int avb_link_mux[] = {
1164 	AVB_LINK_MARK,
1165 };
1166 static const unsigned int avb_magic_pins[] = {
1167 	RCAR_GP_PIN(5, 15),
1168 };
1169 static const unsigned int avb_magic_mux[] = {
1170 	AVB_MAGIC_MARK,
1171 };
1172 static const unsigned int avb_phy_int_pins[] = {
1173 	RCAR_GP_PIN(5, 16),
1174 };
1175 static const unsigned int avb_phy_int_mux[] = {
1176 	AVB_PHY_INT_MARK,
1177 };
1178 static const unsigned int avb_mdio_pins[] = {
1179 	RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13),
1180 };
1181 static const unsigned int avb_mdio_mux[] = {
1182 	AVB_MDC_MARK, AVB_MDIO_MARK,
1183 };
1184 static const unsigned int avb_mii_tx_rx_pins[] = {
1185 	RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
1186 	RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 13),
1187 
1188 	RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
1189 	RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 1),
1190 	RCAR_GP_PIN(3, 10),
1191 };
1192 static const unsigned int avb_mii_tx_rx_mux[] = {
1193 	AVB_TX_CLK_MARK, AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
1194 	AVB_TXD3_MARK, AVB_TX_EN_MARK,
1195 
1196 	AVB_RX_CLK_MARK, AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
1197 	AVB_RXD3_MARK, AVB_RX_DV_MARK, AVB_RX_ER_MARK,
1198 };
1199 static const unsigned int avb_mii_tx_er_pins[] = {
1200 	RCAR_GP_PIN(5, 23),
1201 };
1202 static const unsigned int avb_mii_tx_er_mux[] = {
1203 	AVB_TX_ER_MARK,
1204 };
1205 static const unsigned int avb_gmii_tx_rx_pins[] = {
1206 	RCAR_GP_PIN(4, 1), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12),
1207 	RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
1208 	RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
1209 	RCAR_GP_PIN(4, 0), RCAR_GP_PIN(5, 22), RCAR_GP_PIN(3, 13),
1210 	RCAR_GP_PIN(5, 23),
1211 
1212 	RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
1213 	RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
1214 	RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1215 	RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 10),
1216 };
1217 static const unsigned int avb_gmii_tx_rx_mux[] = {
1218 	AVB_GTX_CLK_MARK, AVB_GTXREFCLK_MARK, AVB_TX_CLK_MARK, AVB_TXD0_MARK,
1219 	AVB_TXD1_MARK, AVB_TXD2_MARK, AVB_TXD3_MARK, AVB_TXD4_MARK,
1220 	AVB_TXD5_MARK, AVB_TXD6_MARK, AVB_TXD7_MARK, AVB_TX_EN_MARK,
1221 	AVB_TX_ER_MARK,
1222 
1223 	AVB_RX_CLK_MARK, AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
1224 	AVB_RXD3_MARK, AVB_RXD4_MARK, AVB_RXD5_MARK, AVB_RXD6_MARK,
1225 	AVB_RXD7_MARK, AVB_RX_DV_MARK, AVB_RX_ER_MARK,
1226 };
1227 static const unsigned int avb_avtp_match_a_pins[] = {
1228 	RCAR_GP_PIN(1, 15),
1229 };
1230 static const unsigned int avb_avtp_match_a_mux[] = {
1231 	AVB_AVTP_MATCH_A_MARK,
1232 };
1233 static const unsigned int avb_avtp_capture_a_pins[] = {
1234 	RCAR_GP_PIN(1, 14),
1235 };
1236 static const unsigned int avb_avtp_capture_a_mux[] = {
1237 	AVB_AVTP_CAPTURE_A_MARK,
1238 };
1239 static const unsigned int avb_avtp_match_b_pins[] = {
1240 	RCAR_GP_PIN(5, 20),
1241 };
1242 static const unsigned int avb_avtp_match_b_mux[] = {
1243 	AVB_AVTP_MATCH_B_MARK,
1244 };
1245 static const unsigned int avb_avtp_capture_b_pins[] = {
1246 	RCAR_GP_PIN(5, 19),
1247 };
1248 static const unsigned int avb_avtp_capture_b_mux[] = {
1249 	AVB_AVTP_CAPTURE_B_MARK,
1250 };
1251 /* - DU --------------------------------------------------------------------- */
1252 static const unsigned int du0_rgb666_pins[] = {
1253 	/* R[7:2], G[7:2], B[7:2] */
1254 	RCAR_GP_PIN(2, 7),  RCAR_GP_PIN(2, 6),  RCAR_GP_PIN(2, 5),
1255 	RCAR_GP_PIN(2, 4),  RCAR_GP_PIN(2, 3),  RCAR_GP_PIN(2, 2),
1256 	RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
1257 	RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
1258 	RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22), RCAR_GP_PIN(2, 21),
1259 	RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 18),
1260 };
1261 static const unsigned int du0_rgb666_mux[] = {
1262 	DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK,
1263 	DU0_DR3_MARK, DU0_DR2_MARK,
1264 	DU0_DG7_MARK, DU0_DG6_MARK, DU0_DG5_MARK, DU0_DG4_MARK,
1265 	DU0_DG3_MARK, DU0_DG2_MARK,
1266 	DU0_DB7_MARK, DU0_DB6_MARK, DU0_DB5_MARK, DU0_DB4_MARK,
1267 	DU0_DB3_MARK, DU0_DB2_MARK,
1268 };
1269 static const unsigned int du0_rgb888_pins[] = {
1270 	/* R[7:0], G[7:0], B[7:0] */
1271 	RCAR_GP_PIN(2, 7),  RCAR_GP_PIN(2, 6),  RCAR_GP_PIN(2, 5),
1272 	RCAR_GP_PIN(2, 4),  RCAR_GP_PIN(2, 3),  RCAR_GP_PIN(2, 2),
1273 	RCAR_GP_PIN(2, 1),  RCAR_GP_PIN(2, 0),
1274 	RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
1275 	RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
1276 	RCAR_GP_PIN(2, 9),  RCAR_GP_PIN(2, 8),
1277 	RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22), RCAR_GP_PIN(2, 21),
1278 	RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 18),
1279 	RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 16),
1280 };
1281 static const unsigned int du0_rgb888_mux[] = {
1282 	DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK,
1283 	DU0_DR3_MARK, DU0_DR2_MARK, DU0_DR1_MARK, DU0_DR0_MARK,
1284 	DU0_DG7_MARK, DU0_DG6_MARK, DU0_DG5_MARK, DU0_DG4_MARK,
1285 	DU0_DG3_MARK, DU0_DG2_MARK, DU0_DG1_MARK, DU0_DG0_MARK,
1286 	DU0_DB7_MARK, DU0_DB6_MARK, DU0_DB5_MARK, DU0_DB4_MARK,
1287 	DU0_DB3_MARK, DU0_DB2_MARK, DU0_DB1_MARK, DU0_DB0_MARK,
1288 };
1289 static const unsigned int du0_clk0_out_pins[] = {
1290 	/* DOTCLKOUT0 */
1291 	RCAR_GP_PIN(2, 25),
1292 };
1293 static const unsigned int du0_clk0_out_mux[] = {
1294 	DU0_DOTCLKOUT0_MARK
1295 };
1296 static const unsigned int du0_clk1_out_pins[] = {
1297 	/* DOTCLKOUT1 */
1298 	RCAR_GP_PIN(2, 26),
1299 };
1300 static const unsigned int du0_clk1_out_mux[] = {
1301 	DU0_DOTCLKOUT1_MARK
1302 };
1303 static const unsigned int du0_clk_in_pins[] = {
1304 	/* CLKIN */
1305 	RCAR_GP_PIN(2, 24),
1306 };
1307 static const unsigned int du0_clk_in_mux[] = {
1308 	DU0_DOTCLKIN_MARK
1309 };
1310 static const unsigned int du0_sync_pins[] = {
1311 	/* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
1312 	RCAR_GP_PIN(2, 28), RCAR_GP_PIN(2, 27),
1313 };
1314 static const unsigned int du0_sync_mux[] = {
1315 	DU0_EXVSYNC_DU0_VSYNC_MARK, DU0_EXHSYNC_DU0_HSYNC_MARK
1316 };
1317 static const unsigned int du0_oddf_pins[] = {
1318 	/* EXODDF/ODDF/DISP/CDE */
1319 	RCAR_GP_PIN(2, 29),
1320 };
1321 static const unsigned int du0_oddf_mux[] = {
1322 	DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK,
1323 };
1324 static const unsigned int du0_cde_pins[] = {
1325 	/* CDE */
1326 	RCAR_GP_PIN(2, 31),
1327 };
1328 static const unsigned int du0_cde_mux[] = {
1329 	DU0_CDE_MARK,
1330 };
1331 static const unsigned int du0_disp_pins[] = {
1332 	/* DISP */
1333 	RCAR_GP_PIN(2, 30),
1334 };
1335 static const unsigned int du0_disp_mux[] = {
1336 	DU0_DISP_MARK
1337 };
1338 static const unsigned int du1_rgb666_pins[] = {
1339 	/* R[7:2], G[7:2], B[7:2] */
1340 	RCAR_GP_PIN(4, 9),  RCAR_GP_PIN(4, 8),  RCAR_GP_PIN(4, 7),
1341 	RCAR_GP_PIN(4, 6),  RCAR_GP_PIN(4, 5),  RCAR_GP_PIN(4, 4),
1342 	RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 15),
1343 	RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 12),
1344 	RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 23),
1345 	RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20),
1346 };
1347 static const unsigned int du1_rgb666_mux[] = {
1348 	DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
1349 	DU1_DR3_MARK, DU1_DR2_MARK,
1350 	DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
1351 	DU1_DG3_MARK, DU1_DG2_MARK,
1352 	DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
1353 	DU1_DB3_MARK, DU1_DB2_MARK,
1354 };
1355 static const unsigned int du1_rgb888_pins[] = {
1356 	/* R[7:0], G[7:0], B[7:0] */
1357 	RCAR_GP_PIN(4, 9),  RCAR_GP_PIN(4, 8),  RCAR_GP_PIN(4, 7),
1358 	RCAR_GP_PIN(4, 6),  RCAR_GP_PIN(4, 5),  RCAR_GP_PIN(4, 4),
1359 	RCAR_GP_PIN(4, 3),  RCAR_GP_PIN(4, 2),
1360 	RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 15),
1361 	RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 12),
1362 	RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 10),
1363 	RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 23),
1364 	RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20),
1365 	RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 18),
1366 };
1367 static const unsigned int du1_rgb888_mux[] = {
1368 	DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
1369 	DU1_DR3_MARK, DU1_DR2_MARK, DU1_DR1_MARK, DU1_DR0_MARK,
1370 	DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
1371 	DU1_DG3_MARK, DU1_DG2_MARK, DU1_DG1_MARK, DU1_DG0_MARK,
1372 	DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
1373 	DU1_DB3_MARK, DU1_DB2_MARK, DU1_DB1_MARK, DU1_DB0_MARK,
1374 };
1375 static const unsigned int du1_clk0_out_pins[] = {
1376 	/* DOTCLKOUT0 */
1377 	RCAR_GP_PIN(5, 2),
1378 };
1379 static const unsigned int du1_clk0_out_mux[] = {
1380 	DU1_DOTCLKOUT0_MARK
1381 };
1382 static const unsigned int du1_clk1_out_pins[] = {
1383 	/* DOTCLKOUT1 */
1384 	RCAR_GP_PIN(5, 0),
1385 };
1386 static const unsigned int du1_clk1_out_mux[] = {
1387 	DU1_DOTCLKOUT1_MARK
1388 };
1389 static const unsigned int du1_clk_in_pins[] = {
1390 	/* DOTCLKIN */
1391 	RCAR_GP_PIN(5, 1),
1392 };
1393 static const unsigned int du1_clk_in_mux[] = {
1394 	DU1_DOTCLKIN_MARK
1395 };
1396 static const unsigned int du1_sync_pins[] = {
1397 	/* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
1398 	RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 4),
1399 };
1400 static const unsigned int du1_sync_mux[] = {
1401 	DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK
1402 };
1403 static const unsigned int du1_oddf_pins[] = {
1404 	/* EXODDF/ODDF/DISP/CDE */
1405 	RCAR_GP_PIN(5, 3),
1406 };
1407 static const unsigned int du1_oddf_mux[] = {
1408 	DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
1409 };
1410 static const unsigned int du1_cde_pins[] = {
1411 	/* CDE */
1412 	RCAR_GP_PIN(5, 7),
1413 };
1414 static const unsigned int du1_cde_mux[] = {
1415 	DU1_CDE_MARK
1416 };
1417 static const unsigned int du1_disp_pins[] = {
1418 	/* DISP */
1419 	RCAR_GP_PIN(5, 6),
1420 };
1421 static const unsigned int du1_disp_mux[] = {
1422 	DU1_DISP_MARK
1423 };
1424 /* - I2C0 ------------------------------------------------------------------- */
1425 static const unsigned int i2c0_a_pins[] = {
1426 	/* SCL, SDA */
1427 	RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
1428 };
1429 static const unsigned int i2c0_a_mux[] = {
1430 	SCL0_A_MARK, SDA0_A_MARK,
1431 };
1432 static const unsigned int i2c0_b_pins[] = {
1433 	/* SCL, SDA */
1434 	RCAR_GP_PIN(5, 28), RCAR_GP_PIN(5, 29),
1435 };
1436 static const unsigned int i2c0_b_mux[] = {
1437 	SCL0_B_MARK, SDA0_B_MARK,
1438 };
1439 static const unsigned int i2c0_c_pins[] = {
1440 	/* SCL, SDA */
1441 	RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12),
1442 };
1443 static const unsigned int i2c0_c_mux[] = {
1444 	SCL0_C_MARK, SDA0_C_MARK,
1445 };
1446 static const unsigned int i2c0_d_pins[] = {
1447 	/* SCL, SDA */
1448 	RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
1449 };
1450 static const unsigned int i2c0_d_mux[] = {
1451 	SCL0_D_MARK, SDA0_D_MARK,
1452 };
1453 static const unsigned int i2c0_e_pins[] = {
1454 	/* SCL, SDA */
1455 	RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
1456 };
1457 static const unsigned int i2c0_e_mux[] = {
1458 	SCL0_E_MARK, SDA0_E_MARK,
1459 };
1460 /* - I2C1 ------------------------------------------------------------------- */
1461 static const unsigned int i2c1_a_pins[] = {
1462 	/* SCL, SDA */
1463 	RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
1464 };
1465 static const unsigned int i2c1_a_mux[] = {
1466 	SCL1_A_MARK, SDA1_A_MARK,
1467 };
1468 static const unsigned int i2c1_b_pins[] = {
1469 	/* SCL, SDA */
1470 	RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
1471 };
1472 static const unsigned int i2c1_b_mux[] = {
1473 	SCL1_B_MARK, SDA1_B_MARK,
1474 };
1475 static const unsigned int i2c1_c_pins[] = {
1476 	/* SCL, SDA */
1477 	RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
1478 };
1479 static const unsigned int i2c1_c_mux[] = {
1480 	SCL1_C_MARK, SDA1_C_MARK,
1481 };
1482 static const unsigned int i2c1_d_pins[] = {
1483 	/* SCL, SDA */
1484 	RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 9),
1485 };
1486 static const unsigned int i2c1_d_mux[] = {
1487 	SCL1_D_MARK, SDA1_D_MARK,
1488 };
1489 static const unsigned int i2c1_e_pins[] = {
1490 	/* SCL, SDA */
1491 	RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
1492 };
1493 static const unsigned int i2c1_e_mux[] = {
1494 	SCL1_E_MARK, SDA1_E_MARK,
1495 };
1496 /* - I2C2 ------------------------------------------------------------------- */
1497 static const unsigned int i2c2_a_pins[] = {
1498 	/* SCL, SDA */
1499 	RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 25),
1500 };
1501 static const unsigned int i2c2_a_mux[] = {
1502 	SCL2_A_MARK, SDA2_A_MARK,
1503 };
1504 static const unsigned int i2c2_b_pins[] = {
1505 	/* SCL, SDA */
1506 	RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
1507 };
1508 static const unsigned int i2c2_b_mux[] = {
1509 	SCL2_B_MARK, SDA2_B_MARK,
1510 };
1511 static const unsigned int i2c2_c_pins[] = {
1512 	/* SCL, SDA */
1513 	RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
1514 };
1515 static const unsigned int i2c2_c_mux[] = {
1516 	SCL2_C_MARK, SDA2_C_MARK,
1517 };
1518 static const unsigned int i2c2_d_pins[] = {
1519 	/* SCL, SDA */
1520 	RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1521 };
1522 static const unsigned int i2c2_d_mux[] = {
1523 	SCL2_D_MARK, SDA2_D_MARK,
1524 };
1525 /* - I2C3 ------------------------------------------------------------------- */
1526 static const unsigned int i2c3_a_pins[] = {
1527 	/* SCL, SDA */
1528 	RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10),
1529 };
1530 static const unsigned int i2c3_a_mux[] = {
1531 	SCL3_A_MARK, SDA3_A_MARK,
1532 };
1533 static const unsigned int i2c3_b_pins[] = {
1534 	/* SCL, SDA */
1535 	RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
1536 };
1537 static const unsigned int i2c3_b_mux[] = {
1538 	SCL3_B_MARK, SDA3_B_MARK,
1539 };
1540 static const unsigned int i2c3_c_pins[] = {
1541 	/* SCL, SDA */
1542 	RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
1543 };
1544 static const unsigned int i2c3_c_mux[] = {
1545 	SCL3_C_MARK, SDA3_C_MARK,
1546 };
1547 static const unsigned int i2c3_d_pins[] = {
1548 	/* SCL, SDA */
1549 	RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1550 };
1551 static const unsigned int i2c3_d_mux[] = {
1552 	SCL3_D_MARK, SDA3_D_MARK,
1553 };
1554 static const unsigned int i2c3_e_pins[] = {
1555 	/* SCL, SDA */
1556 	RCAR_GP_PIN(5, 25), RCAR_GP_PIN(5, 26),
1557 };
1558 static const unsigned int i2c3_e_mux[] = {
1559 	SCL3_E_MARK, SDA3_E_MARK,
1560 };
1561 /* - I2C4 ------------------------------------------------------------------- */
1562 static const unsigned int i2c4_a_pins[] = {
1563 	/* SCL, SDA */
1564 	RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
1565 };
1566 static const unsigned int i2c4_a_mux[] = {
1567 	SCL4_A_MARK, SDA4_A_MARK,
1568 };
1569 static const unsigned int i2c4_b_pins[] = {
1570 	/* SCL, SDA */
1571 	RCAR_GP_PIN(5, 30), RCAR_GP_PIN(5, 31),
1572 };
1573 static const unsigned int i2c4_b_mux[] = {
1574 	SCL4_B_MARK, SDA4_B_MARK,
1575 };
1576 static const unsigned int i2c4_c_pins[] = {
1577 	/* SCL, SDA */
1578 	RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
1579 };
1580 static const unsigned int i2c4_c_mux[] = {
1581 	SCL4_C_MARK, SDA4_C_MARK,
1582 };
1583 static const unsigned int i2c4_d_pins[] = {
1584 	/* SCL, SDA */
1585 	RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
1586 };
1587 static const unsigned int i2c4_d_mux[] = {
1588 	SCL4_D_MARK, SDA4_D_MARK,
1589 };
1590 static const unsigned int i2c4_e_pins[] = {
1591 	/* SCL, SDA */
1592 	RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 6),
1593 };
1594 static const unsigned int i2c4_e_mux[] = {
1595 	SCL4_E_MARK, SDA4_E_MARK,
1596 };
1597 /* - MMC -------------------------------------------------------------------- */
1598 static const unsigned int mmc_data_pins[] = {
1599 	/* D[0:3] */
1600 	RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 16),
1601 	RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 18),
1602 	RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20),
1603 	RCAR_GP_PIN(0, 21), RCAR_GP_PIN(0, 22),
1604 };
1605 static const unsigned int mmc_data_mux[] = {
1606 	MMC0_D0_SDHI1_D0_MARK, MMC0_D1_SDHI1_D1_MARK,
1607 	MMC0_D2_SDHI1_D2_MARK, MMC0_D3_SDHI1_D3_MARK,
1608 	MMC0_D4_MARK, MMC0_D5_MARK,
1609 	MMC0_D6_MARK, MMC0_D7_MARK,
1610 };
1611 static const unsigned int mmc_ctrl_pins[] = {
1612 	/* CLK, CMD */
1613 	RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 14),
1614 };
1615 static const unsigned int mmc_ctrl_mux[] = {
1616 	MMC0_CLK_SDHI1_CLK_MARK, MMC0_CMD_SDHI1_CMD_MARK,
1617 };
1618 /* - QSPI ------------------------------------------------------------------- */
1619 static const unsigned int qspi0_ctrl_pins[] = {
1620 	/* SPCLK, SSL */
1621 	RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 21),
1622 };
1623 static const unsigned int qspi0_ctrl_mux[] = {
1624 	QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
1625 };
1626 static const unsigned int qspi0_data_pins[] = {
1627 	/* MOSI_IO0, MISO_IO1, IO2, IO3 */
1628 	RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19),
1629 	RCAR_GP_PIN(1, 20),
1630 };
1631 static const unsigned int qspi0_data_mux[] = {
1632 	QSPI0_MOSI_QSPI0_IO0_MARK, QSPI0_MISO_QSPI0_IO1_MARK,
1633 	QSPI0_IO2_MARK, QSPI0_IO3_MARK,
1634 };
1635 static const unsigned int qspi1_ctrl_pins[] = {
1636 	/* SPCLK, SSL */
1637 	RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 9),
1638 };
1639 static const unsigned int qspi1_ctrl_mux[] = {
1640 	QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
1641 };
1642 static const unsigned int qspi1_data_pins[] = {
1643 	/* MOSI_IO0, MISO_IO1, IO2, IO3 */
1644 	RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 7),
1645 	RCAR_GP_PIN(4, 8),
1646 };
1647 static const unsigned int qspi1_data_mux[] = {
1648 	QSPI1_MOSI_QSPI1_IO0_MARK, QSPI1_MISO_QSPI1_IO1_MARK,
1649 	QSPI1_IO2_MARK, QSPI1_IO3_MARK,
1650 };
1651 /* - SCIF0 ------------------------------------------------------------------ */
1652 static const unsigned int scif0_data_a_pins[] = {
1653 	/* RX, TX */
1654 	RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
1655 };
1656 static const unsigned int scif0_data_a_mux[] = {
1657 	RX0_A_MARK, TX0_A_MARK,
1658 };
1659 static const unsigned int scif0_data_b_pins[] = {
1660 	/* RX, TX */
1661 	RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12),
1662 };
1663 static const unsigned int scif0_data_b_mux[] = {
1664 	RX0_B_MARK, TX0_B_MARK,
1665 };
1666 static const unsigned int scif0_data_c_pins[] = {
1667 	/* RX, TX */
1668 	RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
1669 };
1670 static const unsigned int scif0_data_c_mux[] = {
1671 	RX0_C_MARK, TX0_C_MARK,
1672 };
1673 static const unsigned int scif0_data_d_pins[] = {
1674 	/* RX, TX */
1675 	RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
1676 };
1677 static const unsigned int scif0_data_d_mux[] = {
1678 	RX0_D_MARK, TX0_D_MARK,
1679 };
1680 /* - SCIF1 ------------------------------------------------------------------ */
1681 static const unsigned int scif1_data_a_pins[] = {
1682 	/* RX, TX */
1683 	RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
1684 };
1685 static const unsigned int scif1_data_a_mux[] = {
1686 	RX1_A_MARK, TX1_A_MARK,
1687 };
1688 static const unsigned int scif1_clk_a_pins[] = {
1689 	/* SCK */
1690 	RCAR_GP_PIN(4, 15),
1691 };
1692 static const unsigned int scif1_clk_a_mux[] = {
1693 	SCIF1_SCK_A_MARK,
1694 };
1695 static const unsigned int scif1_data_b_pins[] = {
1696 	/* RX, TX */
1697 	RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 20),
1698 };
1699 static const unsigned int scif1_data_b_mux[] = {
1700 	RX1_B_MARK, TX1_B_MARK,
1701 };
1702 static const unsigned int scif1_clk_b_pins[] = {
1703 	/* SCK */
1704 	RCAR_GP_PIN(5, 18),
1705 };
1706 static const unsigned int scif1_clk_b_mux[] = {
1707 	SCIF1_SCK_B_MARK,
1708 };
1709 static const unsigned int scif1_data_c_pins[] = {
1710 	/* RX, TX */
1711 	RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 9),
1712 };
1713 static const unsigned int scif1_data_c_mux[] = {
1714 	RX1_C_MARK, TX1_C_MARK,
1715 };
1716 static const unsigned int scif1_clk_c_pins[] = {
1717 	/* SCK */
1718 	RCAR_GP_PIN(1, 7),
1719 };
1720 static const unsigned int scif1_clk_c_mux[] = {
1721 	SCIF1_SCK_C_MARK,
1722 };
1723 static const unsigned int scif1_data_d_pins[] = {
1724 	/* RX, TX */
1725 	RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
1726 };
1727 static const unsigned int scif1_data_d_mux[] = {
1728 	RX1_D_MARK, TX1_D_MARK,
1729 };
1730 /* - SCIF2 ------------------------------------------------------------------ */
1731 static const unsigned int scif2_data_a_pins[] = {
1732 	/* RX, TX */
1733 	RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 19),
1734 };
1735 static const unsigned int scif2_data_a_mux[] = {
1736 	RX2_A_MARK, TX2_A_MARK,
1737 };
1738 static const unsigned int scif2_clk_a_pins[] = {
1739 	/* SCK */
1740 	RCAR_GP_PIN(4, 20),
1741 };
1742 static const unsigned int scif2_clk_a_mux[] = {
1743 	SCIF2_SCK_A_MARK,
1744 };
1745 static const unsigned int scif2_data_b_pins[] = {
1746 	/* RX, TX */
1747 	RCAR_GP_PIN(5, 25), RCAR_GP_PIN(5, 26),
1748 };
1749 static const unsigned int scif2_data_b_mux[] = {
1750 	RX2_B_MARK, TX2_B_MARK,
1751 };
1752 static const unsigned int scif2_clk_b_pins[] = {
1753 	/* SCK */
1754 	RCAR_GP_PIN(5, 27),
1755 };
1756 static const unsigned int scif2_clk_b_mux[] = {
1757 	SCIF2_SCK_B_MARK,
1758 };
1759 static const unsigned int scif2_data_c_pins[] = {
1760 	/* RX, TX */
1761 	RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
1762 };
1763 static const unsigned int scif2_data_c_mux[] = {
1764 	RX2_C_MARK, TX2_C_MARK,
1765 };
1766 /* - SCIF3 ------------------------------------------------------------------ */
1767 static const unsigned int scif3_data_a_pins[] = {
1768 	/* RX, TX */
1769 	RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
1770 };
1771 static const unsigned int scif3_data_a_mux[] = {
1772 	RX3_A_MARK, TX3_A_MARK,
1773 };
1774 static const unsigned int scif3_clk_pins[] = {
1775 	/* SCK */
1776 	RCAR_GP_PIN(4, 21),
1777 };
1778 static const unsigned int scif3_clk_mux[] = {
1779 	SCIF3_SCK_MARK,
1780 };
1781 static const unsigned int scif3_data_b_pins[] = {
1782 	/* RX, TX */
1783 	RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1784 };
1785 static const unsigned int scif3_data_b_mux[] = {
1786 	RX3_B_MARK, TX3_B_MARK,
1787 };
1788 static const unsigned int scif3_data_c_pins[] = {
1789 	/* RX, TX */
1790 	RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
1791 };
1792 static const unsigned int scif3_data_c_mux[] = {
1793 	RX3_C_MARK, TX3_C_MARK,
1794 };
1795 /* - SCIF4 ------------------------------------------------------------------ */
1796 static const unsigned int scif4_data_a_pins[] = {
1797 	/* RX, TX */
1798 	RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
1799 };
1800 static const unsigned int scif4_data_a_mux[] = {
1801 	RX4_A_MARK, TX4_A_MARK,
1802 };
1803 static const unsigned int scif4_data_b_pins[] = {
1804 	/* RX, TX */
1805 	RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
1806 };
1807 static const unsigned int scif4_data_b_mux[] = {
1808 	RX4_B_MARK, TX4_B_MARK,
1809 };
1810 static const unsigned int scif4_data_c_pins[] = {
1811 	/* RX, TX */
1812 	RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
1813 };
1814 static const unsigned int scif4_data_c_mux[] = {
1815 	RX4_C_MARK, TX4_C_MARK,
1816 };
1817 static const unsigned int scif4_data_d_pins[] = {
1818 	/* RX, TX */
1819 	RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
1820 };
1821 static const unsigned int scif4_data_d_mux[] = {
1822 	RX4_D_MARK, TX4_D_MARK,
1823 };
1824 static const unsigned int scif4_data_e_pins[] = {
1825 	/* RX, TX */
1826 	RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8),
1827 };
1828 static const unsigned int scif4_data_e_mux[] = {
1829 	RX4_E_MARK, TX4_E_MARK,
1830 };
1831 /* - SCIF5 ------------------------------------------------------------------ */
1832 static const unsigned int scif5_data_a_pins[] = {
1833 	/* RX, TX */
1834 	RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
1835 };
1836 static const unsigned int scif5_data_a_mux[] = {
1837 	RX5_A_MARK, TX5_A_MARK,
1838 };
1839 static const unsigned int scif5_data_b_pins[] = {
1840 	/* RX, TX */
1841 	RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
1842 };
1843 static const unsigned int scif5_data_b_mux[] = {
1844 	RX5_B_MARK, TX5_B_MARK,
1845 };
1846 static const unsigned int scif5_data_c_pins[] = {
1847 	/* RX, TX */
1848 	RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1849 };
1850 static const unsigned int scif5_data_c_mux[] = {
1851 	RX5_C_MARK, TX5_C_MARK,
1852 };
1853 static const unsigned int scif5_data_d_pins[] = {
1854 	/* RX, TX */
1855 	RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
1856 };
1857 static const unsigned int scif5_data_d_mux[] = {
1858 	RX5_D_MARK, TX5_D_MARK,
1859 };
1860 static const unsigned int scif5_data_e_pins[] = {
1861 	/* RX, TX */
1862 	RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
1863 };
1864 static const unsigned int scif5_data_e_mux[] = {
1865 	RX5_E_MARK, TX5_E_MARK,
1866 };
1867 static const unsigned int scif5_data_f_pins[] = {
1868 	/* RX, TX */
1869 	RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28),
1870 };
1871 static const unsigned int scif5_data_f_mux[] = {
1872 	RX5_F_MARK, TX5_F_MARK,
1873 };
1874 /* - SCIF Clock ------------------------------------------------------------- */
1875 static const unsigned int scif_clk_a_pins[] = {
1876 	/* SCIF_CLK */
1877 	RCAR_GP_PIN(1, 22),
1878 };
1879 static const unsigned int scif_clk_a_mux[] = {
1880 	SCIF_CLK_A_MARK,
1881 };
1882 static const unsigned int scif_clk_b_pins[] = {
1883 	/* SCIF_CLK */
1884 	RCAR_GP_PIN(3, 29),
1885 };
1886 static const unsigned int scif_clk_b_mux[] = {
1887 	SCIF_CLK_B_MARK,
1888 };
1889 /* - SDHI0 ------------------------------------------------------------------ */
1890 static const unsigned int sdhi0_data_pins[] = {
1891 	/* D[0:3] */
1892 	RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8),
1893 	RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
1894 };
1895 static const unsigned int sdhi0_data_mux[] = {
1896 	SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK,
1897 };
1898 static const unsigned int sdhi0_ctrl_pins[] = {
1899 	/* CLK, CMD */
1900 	RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
1901 };
1902 static const unsigned int sdhi0_ctrl_mux[] = {
1903 	SD0_CLK_MARK, SD0_CMD_MARK,
1904 };
1905 static const unsigned int sdhi0_cd_pins[] = {
1906 	/* CD */
1907 	RCAR_GP_PIN(0, 11),
1908 };
1909 static const unsigned int sdhi0_cd_mux[] = {
1910 	SD0_CD_MARK,
1911 };
1912 static const unsigned int sdhi0_wp_pins[] = {
1913 	/* WP */
1914 	RCAR_GP_PIN(0, 12),
1915 };
1916 static const unsigned int sdhi0_wp_mux[] = {
1917 	SD0_WP_MARK,
1918 };
1919 /* - SDHI1 ------------------------------------------------------------------ */
1920 static const unsigned int sdhi1_cd_pins[] = {
1921 	/* CD */
1922 	RCAR_GP_PIN(0, 19),
1923 };
1924 static const unsigned int sdhi1_cd_mux[] = {
1925 	SD1_CD_MARK,
1926 };
1927 static const unsigned int sdhi1_wp_pins[] = {
1928 	/* WP */
1929 	RCAR_GP_PIN(0, 20),
1930 };
1931 static const unsigned int sdhi1_wp_mux[] = {
1932 	SD1_WP_MARK,
1933 };
1934 /* - SDHI2 ------------------------------------------------------------------ */
1935 static const unsigned int sdhi2_data_pins[] = {
1936 	/* D[0:3] */
1937 	RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
1938 	RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 19),
1939 };
1940 static const unsigned int sdhi2_data_mux[] = {
1941 	SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK,
1942 };
1943 static const unsigned int sdhi2_ctrl_pins[] = {
1944 	/* CLK, CMD */
1945 	RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
1946 };
1947 static const unsigned int sdhi2_ctrl_mux[] = {
1948 	SD2_CLK_MARK, SD2_CMD_MARK,
1949 };
1950 static const unsigned int sdhi2_cd_pins[] = {
1951 	/* CD */
1952 	RCAR_GP_PIN(4, 20),
1953 };
1954 static const unsigned int sdhi2_cd_mux[] = {
1955 	SD2_CD_MARK,
1956 };
1957 static const unsigned int sdhi2_wp_pins[] = {
1958 	/* WP */
1959 	RCAR_GP_PIN(4, 21),
1960 };
1961 static const unsigned int sdhi2_wp_mux[] = {
1962 	SD2_WP_MARK,
1963 };
1964 /* - USB0 ------------------------------------------------------------------- */
1965 static const unsigned int usb0_pins[] = {
1966 	RCAR_GP_PIN(0, 0), /* PWEN */
1967 	RCAR_GP_PIN(0, 1), /* OVC */
1968 };
1969 static const unsigned int usb0_mux[] = {
1970 	USB0_PWEN_MARK,
1971 	USB0_OVC_MARK,
1972 };
1973 /* - USB1 ------------------------------------------------------------------- */
1974 static const unsigned int usb1_pins[] = {
1975 	RCAR_GP_PIN(0, 2), /* PWEN */
1976 	RCAR_GP_PIN(0, 3), /* OVC */
1977 };
1978 static const unsigned int usb1_mux[] = {
1979 	USB1_PWEN_MARK,
1980 	USB1_OVC_MARK,
1981 };
1982 /* - VIN0 ------------------------------------------------------------------- */
1983 static const unsigned int vin0_data_pins[] = {
1984 	/* B */
1985 	RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21),
1986 	RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
1987 	RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
1988 	RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 27),
1989 	/* G */
1990 	RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
1991 	RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
1992 	RCAR_GP_PIN(4, 6), RCAR_GP_PIN(5, 8),
1993 	RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
1994 	/* R */
1995 	RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 12),
1996 	RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
1997 	RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
1998 	RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 19),
1999 };
2000 static const unsigned int vin0_data_mux[] = {
2001 	/* B */
2002 	VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
2003 	VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
2004 	VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
2005 	VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
2006 	/* G */
2007 	VI0_G0_MARK, VI0_G1_MARK,
2008 	VI0_G2_MARK, VI0_G3_MARK,
2009 	VI0_G4_MARK, VI0_G5_MARK,
2010 	VI0_G6_MARK, VI0_G7_MARK,
2011 	/* R */
2012 	VI0_R0_MARK, VI0_R1_MARK,
2013 	VI0_R2_MARK, VI0_R3_MARK,
2014 	VI0_R4_MARK, VI0_R5_MARK,
2015 	VI0_R6_MARK, VI0_R7_MARK,
2016 };
2017 static const unsigned int vin0_data18_pins[] = {
2018 	/* B */
2019 	RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
2020 	RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
2021 	RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 27),
2022 	/* G */
2023 	RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
2024 	RCAR_GP_PIN(4, 6), RCAR_GP_PIN(5, 8),
2025 	RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
2026 	/* R */
2027 	RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
2028 	RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
2029 	RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 19),
2030 };
2031 static const unsigned int vin0_data18_mux[] = {
2032 	/* B */
2033 	VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
2034 	VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
2035 	VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
2036 	/* G */
2037 	VI0_G2_MARK, VI0_G3_MARK,
2038 	VI0_G4_MARK, VI0_G5_MARK,
2039 	VI0_G6_MARK, VI0_G7_MARK,
2040 	/* R */
2041 	VI0_R2_MARK, VI0_R3_MARK,
2042 	VI0_R4_MARK, VI0_R5_MARK,
2043 	VI0_R6_MARK, VI0_R7_MARK,
2044 };
2045 static const unsigned int vin0_sync_pins[] = {
2046 	RCAR_GP_PIN(5, 30), /* HSYNC */
2047 	RCAR_GP_PIN(5, 31), /* VSYNC */
2048 };
2049 static const unsigned int vin0_sync_mux[] = {
2050 	VI0_HSYNC_N_MARK,
2051 	VI0_VSYNC_N_MARK,
2052 };
2053 static const unsigned int vin0_field_pins[] = {
2054 	RCAR_GP_PIN(5, 29),
2055 };
2056 static const unsigned int vin0_field_mux[] = {
2057 	VI0_FIELD_MARK,
2058 };
2059 static const unsigned int vin0_clkenb_pins[] = {
2060 	RCAR_GP_PIN(5, 28),
2061 };
2062 static const unsigned int vin0_clkenb_mux[] = {
2063 	VI0_CLKENB_MARK,
2064 };
2065 static const unsigned int vin0_clk_pins[] = {
2066 	RCAR_GP_PIN(5, 18),
2067 };
2068 static const unsigned int vin0_clk_mux[] = {
2069 	VI0_CLK_MARK,
2070 };
2071 /* - VIN1 ------------------------------------------------------------------- */
2072 static const unsigned int vin1_data_pins[] = {
2073 	RCAR_GP_PIN(3,  1), RCAR_GP_PIN(3, 2),
2074 	RCAR_GP_PIN(3,  3), RCAR_GP_PIN(3, 4),
2075 	RCAR_GP_PIN(3,  5), RCAR_GP_PIN(3, 6),
2076 	RCAR_GP_PIN(3,  7), RCAR_GP_PIN(3, 8),
2077 	RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
2078 	RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
2079 };
2080 static const unsigned int vin1_data_mux[] = {
2081 	VI1_DATA0_MARK, VI1_DATA1_MARK,
2082 	VI1_DATA2_MARK, VI1_DATA3_MARK,
2083 	VI1_DATA4_MARK, VI1_DATA5_MARK,
2084 	VI1_DATA6_MARK, VI1_DATA7_MARK,
2085 	VI1_DATA8_MARK, VI1_DATA9_MARK,
2086 	VI1_DATA10_MARK, VI1_DATA11_MARK,
2087 };
2088 static const unsigned int vin1_sync_pins[] = {
2089 	RCAR_GP_PIN(3, 11), /* HSYNC */
2090 	RCAR_GP_PIN(3, 12), /* VSYNC */
2091 };
2092 static const unsigned int vin1_sync_mux[] = {
2093 	VI1_HSYNC_N_MARK,
2094 	VI1_VSYNC_N_MARK,
2095 };
2096 static const unsigned int vin1_field_pins[] = {
2097 	RCAR_GP_PIN(3, 10),
2098 };
2099 static const unsigned int vin1_field_mux[] = {
2100 	VI1_FIELD_MARK,
2101 };
2102 static const unsigned int vin1_clkenb_pins[] = {
2103 	RCAR_GP_PIN(3, 9),
2104 };
2105 static const unsigned int vin1_clkenb_mux[] = {
2106 	VI1_CLKENB_MARK,
2107 };
2108 static const unsigned int vin1_clk_pins[] = {
2109 	RCAR_GP_PIN(3, 0),
2110 };
2111 static const unsigned int vin1_clk_mux[] = {
2112 	VI1_CLK_MARK,
2113 };
2114 
2115 static const struct sh_pfc_pin_group pinmux_groups[] = {
2116 	SH_PFC_PIN_GROUP(avb_col),
2117 	SH_PFC_PIN_GROUP(avb_crs),
2118 	SH_PFC_PIN_GROUP(avb_link),
2119 	SH_PFC_PIN_GROUP(avb_magic),
2120 	SH_PFC_PIN_GROUP(avb_phy_int),
2121 	SH_PFC_PIN_GROUP(avb_mdio),
2122 	SH_PFC_PIN_GROUP(avb_mii_tx_rx),
2123 	SH_PFC_PIN_GROUP(avb_mii_tx_er),
2124 	SH_PFC_PIN_GROUP(avb_gmii_tx_rx),
2125 	SH_PFC_PIN_GROUP(avb_avtp_match_a),
2126 	SH_PFC_PIN_GROUP(avb_avtp_capture_a),
2127 	SH_PFC_PIN_GROUP(avb_avtp_match_b),
2128 	SH_PFC_PIN_GROUP(avb_avtp_capture_b),
2129 	SH_PFC_PIN_GROUP(du0_rgb666),
2130 	SH_PFC_PIN_GROUP(du0_rgb888),
2131 	SH_PFC_PIN_GROUP(du0_clk0_out),
2132 	SH_PFC_PIN_GROUP(du0_clk1_out),
2133 	SH_PFC_PIN_GROUP(du0_clk_in),
2134 	SH_PFC_PIN_GROUP(du0_sync),
2135 	SH_PFC_PIN_GROUP(du0_oddf),
2136 	SH_PFC_PIN_GROUP(du0_cde),
2137 	SH_PFC_PIN_GROUP(du0_disp),
2138 	SH_PFC_PIN_GROUP(du1_rgb666),
2139 	SH_PFC_PIN_GROUP(du1_rgb888),
2140 	SH_PFC_PIN_GROUP(du1_clk0_out),
2141 	SH_PFC_PIN_GROUP(du1_clk1_out),
2142 	SH_PFC_PIN_GROUP(du1_clk_in),
2143 	SH_PFC_PIN_GROUP(du1_sync),
2144 	SH_PFC_PIN_GROUP(du1_oddf),
2145 	SH_PFC_PIN_GROUP(du1_cde),
2146 	SH_PFC_PIN_GROUP(du1_disp),
2147 	SH_PFC_PIN_GROUP(i2c0_a),
2148 	SH_PFC_PIN_GROUP(i2c0_b),
2149 	SH_PFC_PIN_GROUP(i2c0_c),
2150 	SH_PFC_PIN_GROUP(i2c0_d),
2151 	SH_PFC_PIN_GROUP(i2c0_e),
2152 	SH_PFC_PIN_GROUP(i2c1_a),
2153 	SH_PFC_PIN_GROUP(i2c1_b),
2154 	SH_PFC_PIN_GROUP(i2c1_c),
2155 	SH_PFC_PIN_GROUP(i2c1_d),
2156 	SH_PFC_PIN_GROUP(i2c1_e),
2157 	SH_PFC_PIN_GROUP(i2c2_a),
2158 	SH_PFC_PIN_GROUP(i2c2_b),
2159 	SH_PFC_PIN_GROUP(i2c2_c),
2160 	SH_PFC_PIN_GROUP(i2c2_d),
2161 	SH_PFC_PIN_GROUP(i2c3_a),
2162 	SH_PFC_PIN_GROUP(i2c3_b),
2163 	SH_PFC_PIN_GROUP(i2c3_c),
2164 	SH_PFC_PIN_GROUP(i2c3_d),
2165 	SH_PFC_PIN_GROUP(i2c3_e),
2166 	SH_PFC_PIN_GROUP(i2c4_a),
2167 	SH_PFC_PIN_GROUP(i2c4_b),
2168 	SH_PFC_PIN_GROUP(i2c4_c),
2169 	SH_PFC_PIN_GROUP(i2c4_d),
2170 	SH_PFC_PIN_GROUP(i2c4_e),
2171 	BUS_DATA_PIN_GROUP(mmc_data, 1),
2172 	BUS_DATA_PIN_GROUP(mmc_data, 4),
2173 	BUS_DATA_PIN_GROUP(mmc_data, 8),
2174 	SH_PFC_PIN_GROUP(mmc_ctrl),
2175 	SH_PFC_PIN_GROUP(qspi0_ctrl),
2176 	BUS_DATA_PIN_GROUP(qspi0_data, 2),
2177 	BUS_DATA_PIN_GROUP(qspi0_data, 4),
2178 	SH_PFC_PIN_GROUP(qspi1_ctrl),
2179 	BUS_DATA_PIN_GROUP(qspi1_data, 2),
2180 	BUS_DATA_PIN_GROUP(qspi1_data, 4),
2181 	SH_PFC_PIN_GROUP(scif0_data_a),
2182 	SH_PFC_PIN_GROUP(scif0_data_b),
2183 	SH_PFC_PIN_GROUP(scif0_data_c),
2184 	SH_PFC_PIN_GROUP(scif0_data_d),
2185 	SH_PFC_PIN_GROUP(scif1_data_a),
2186 	SH_PFC_PIN_GROUP(scif1_clk_a),
2187 	SH_PFC_PIN_GROUP(scif1_data_b),
2188 	SH_PFC_PIN_GROUP(scif1_clk_b),
2189 	SH_PFC_PIN_GROUP(scif1_data_c),
2190 	SH_PFC_PIN_GROUP(scif1_clk_c),
2191 	SH_PFC_PIN_GROUP(scif1_data_d),
2192 	SH_PFC_PIN_GROUP(scif2_data_a),
2193 	SH_PFC_PIN_GROUP(scif2_clk_a),
2194 	SH_PFC_PIN_GROUP(scif2_data_b),
2195 	SH_PFC_PIN_GROUP(scif2_clk_b),
2196 	SH_PFC_PIN_GROUP(scif2_data_c),
2197 	SH_PFC_PIN_GROUP(scif3_data_a),
2198 	SH_PFC_PIN_GROUP(scif3_clk),
2199 	SH_PFC_PIN_GROUP(scif3_data_b),
2200 	SH_PFC_PIN_GROUP(scif3_data_c),
2201 	SH_PFC_PIN_GROUP(scif4_data_a),
2202 	SH_PFC_PIN_GROUP(scif4_data_b),
2203 	SH_PFC_PIN_GROUP(scif4_data_c),
2204 	SH_PFC_PIN_GROUP(scif4_data_d),
2205 	SH_PFC_PIN_GROUP(scif4_data_e),
2206 	SH_PFC_PIN_GROUP(scif5_data_a),
2207 	SH_PFC_PIN_GROUP(scif5_data_b),
2208 	SH_PFC_PIN_GROUP(scif5_data_c),
2209 	SH_PFC_PIN_GROUP(scif5_data_d),
2210 	SH_PFC_PIN_GROUP(scif5_data_e),
2211 	SH_PFC_PIN_GROUP(scif5_data_f),
2212 	SH_PFC_PIN_GROUP(scif_clk_a),
2213 	SH_PFC_PIN_GROUP(scif_clk_b),
2214 	BUS_DATA_PIN_GROUP(sdhi0_data, 1),
2215 	BUS_DATA_PIN_GROUP(sdhi0_data, 4),
2216 	SH_PFC_PIN_GROUP(sdhi0_ctrl),
2217 	SH_PFC_PIN_GROUP(sdhi0_cd),
2218 	SH_PFC_PIN_GROUP(sdhi0_wp),
2219 	SH_PFC_PIN_GROUP_SUBSET(sdhi1_data1, mmc_data, 0, 1),
2220 	SH_PFC_PIN_GROUP_SUBSET(sdhi1_data4, mmc_data, 0, 4),
2221 	SH_PFC_PIN_GROUP_ALIAS(sdhi1_ctrl, mmc_ctrl),
2222 	SH_PFC_PIN_GROUP(sdhi1_cd),
2223 	SH_PFC_PIN_GROUP(sdhi1_wp),
2224 	BUS_DATA_PIN_GROUP(sdhi2_data, 1),
2225 	BUS_DATA_PIN_GROUP(sdhi2_data, 4),
2226 	SH_PFC_PIN_GROUP(sdhi2_ctrl),
2227 	SH_PFC_PIN_GROUP(sdhi2_cd),
2228 	SH_PFC_PIN_GROUP(sdhi2_wp),
2229 	SH_PFC_PIN_GROUP(usb0),
2230 	SH_PFC_PIN_GROUP(usb1),
2231 	BUS_DATA_PIN_GROUP(vin0_data, 24),
2232 	BUS_DATA_PIN_GROUP(vin0_data, 20),
2233 	SH_PFC_PIN_GROUP(vin0_data18),
2234 	BUS_DATA_PIN_GROUP(vin0_data, 16),
2235 	BUS_DATA_PIN_GROUP(vin0_data, 12),
2236 	BUS_DATA_PIN_GROUP(vin0_data, 10),
2237 	BUS_DATA_PIN_GROUP(vin0_data, 8),
2238 	SH_PFC_PIN_GROUP(vin0_sync),
2239 	SH_PFC_PIN_GROUP(vin0_field),
2240 	SH_PFC_PIN_GROUP(vin0_clkenb),
2241 	SH_PFC_PIN_GROUP(vin0_clk),
2242 	BUS_DATA_PIN_GROUP(vin1_data, 12),
2243 	BUS_DATA_PIN_GROUP(vin1_data, 10),
2244 	BUS_DATA_PIN_GROUP(vin1_data, 8),
2245 	SH_PFC_PIN_GROUP(vin1_sync),
2246 	SH_PFC_PIN_GROUP(vin1_field),
2247 	SH_PFC_PIN_GROUP(vin1_clkenb),
2248 	SH_PFC_PIN_GROUP(vin1_clk),
2249 };
2250 
2251 static const char * const avb_groups[] = {
2252 	"avb_col",
2253 	"avb_crs",
2254 	"avb_link",
2255 	"avb_magic",
2256 	"avb_phy_int",
2257 	"avb_mdio",
2258 	"avb_mii_tx_rx",
2259 	"avb_mii_tx_er",
2260 	"avb_gmii_tx_rx",
2261 	"avb_avtp_match_a",
2262 	"avb_avtp_capture_a",
2263 	"avb_avtp_match_b",
2264 	"avb_avtp_capture_b",
2265 };
2266 
2267 static const char * const du0_groups[] = {
2268 	"du0_rgb666",
2269 	"du0_rgb888",
2270 	"du0_clk0_out",
2271 	"du0_clk1_out",
2272 	"du0_clk_in",
2273 	"du0_sync",
2274 	"du0_oddf",
2275 	"du0_cde",
2276 	"du0_disp",
2277 };
2278 
2279 static const char * const du1_groups[] = {
2280 	"du1_rgb666",
2281 	"du1_rgb888",
2282 	"du1_clk0_out",
2283 	"du1_clk1_out",
2284 	"du1_clk_in",
2285 	"du1_sync",
2286 	"du1_oddf",
2287 	"du1_cde",
2288 	"du1_disp",
2289 };
2290 
2291 static const char * const i2c0_groups[] = {
2292 	"i2c0_a",
2293 	"i2c0_b",
2294 	"i2c0_c",
2295 	"i2c0_d",
2296 	"i2c0_e",
2297 };
2298 
2299 static const char * const i2c1_groups[] = {
2300 	"i2c1_a",
2301 	"i2c1_b",
2302 	"i2c1_c",
2303 	"i2c1_d",
2304 	"i2c1_e",
2305 };
2306 
2307 static const char * const i2c2_groups[] = {
2308 	"i2c2_a",
2309 	"i2c2_b",
2310 	"i2c2_c",
2311 	"i2c2_d",
2312 };
2313 
2314 static const char * const i2c3_groups[] = {
2315 	"i2c3_a",
2316 	"i2c3_b",
2317 	"i2c3_c",
2318 	"i2c3_d",
2319 	"i2c3_e",
2320 };
2321 
2322 static const char * const i2c4_groups[] = {
2323 	"i2c4_a",
2324 	"i2c4_b",
2325 	"i2c4_c",
2326 	"i2c4_d",
2327 	"i2c4_e",
2328 };
2329 
2330 static const char * const mmc_groups[] = {
2331 	"mmc_data1",
2332 	"mmc_data4",
2333 	"mmc_data8",
2334 	"mmc_ctrl",
2335 };
2336 
2337 static const char * const qspi0_groups[] = {
2338 	"qspi0_ctrl",
2339 	"qspi0_data2",
2340 	"qspi0_data4",
2341 };
2342 
2343 static const char * const qspi1_groups[] = {
2344 	"qspi1_ctrl",
2345 	"qspi1_data2",
2346 	"qspi1_data4",
2347 };
2348 
2349 static const char * const scif0_groups[] = {
2350 	"scif0_data_a",
2351 	"scif0_data_b",
2352 	"scif0_data_c",
2353 	"scif0_data_d",
2354 };
2355 
2356 static const char * const scif1_groups[] = {
2357 	"scif1_data_a",
2358 	"scif1_clk_a",
2359 	"scif1_data_b",
2360 	"scif1_clk_b",
2361 	"scif1_data_c",
2362 	"scif1_clk_c",
2363 	"scif1_data_d",
2364 };
2365 
2366 static const char * const scif2_groups[] = {
2367 	"scif2_data_a",
2368 	"scif2_clk_a",
2369 	"scif2_data_b",
2370 	"scif2_clk_b",
2371 	"scif2_data_c",
2372 };
2373 
2374 static const char * const scif3_groups[] = {
2375 	"scif3_data_a",
2376 	"scif3_clk",
2377 	"scif3_data_b",
2378 	"scif3_data_c",
2379 };
2380 
2381 static const char * const scif4_groups[] = {
2382 	"scif4_data_a",
2383 	"scif4_data_b",
2384 	"scif4_data_c",
2385 	"scif4_data_d",
2386 	"scif4_data_e",
2387 };
2388 
2389 static const char * const scif5_groups[] = {
2390 	"scif5_data_a",
2391 	"scif5_data_b",
2392 	"scif5_data_c",
2393 	"scif5_data_d",
2394 	"scif5_data_e",
2395 	"scif5_data_f",
2396 };
2397 
2398 static const char * const scif_clk_groups[] = {
2399 	"scif_clk_a",
2400 	"scif_clk_b",
2401 };
2402 
2403 static const char * const sdhi0_groups[] = {
2404 	"sdhi0_data1",
2405 	"sdhi0_data4",
2406 	"sdhi0_ctrl",
2407 	"sdhi0_cd",
2408 	"sdhi0_wp",
2409 };
2410 
2411 static const char * const sdhi1_groups[] = {
2412 	"sdhi1_data1",
2413 	"sdhi1_data4",
2414 	"sdhi1_ctrl",
2415 	"sdhi1_cd",
2416 	"sdhi1_wp",
2417 };
2418 
2419 static const char * const sdhi2_groups[] = {
2420 	"sdhi2_data1",
2421 	"sdhi2_data4",
2422 	"sdhi2_ctrl",
2423 	"sdhi2_cd",
2424 	"sdhi2_wp",
2425 };
2426 
2427 static const char * const usb0_groups[] = {
2428 	"usb0",
2429 };
2430 
2431 static const char * const usb1_groups[] = {
2432 	"usb1",
2433 };
2434 
2435 static const char * const vin0_groups[] = {
2436 	"vin0_data24",
2437 	"vin0_data20",
2438 	"vin0_data18",
2439 	"vin0_data16",
2440 	"vin0_data12",
2441 	"vin0_data10",
2442 	"vin0_data8",
2443 	"vin0_sync",
2444 	"vin0_field",
2445 	"vin0_clkenb",
2446 	"vin0_clk",
2447 };
2448 
2449 static const char * const vin1_groups[] = {
2450 	"vin1_data12",
2451 	"vin1_data10",
2452 	"vin1_data8",
2453 	"vin1_sync",
2454 	"vin1_field",
2455 	"vin1_clkenb",
2456 	"vin1_clk",
2457 };
2458 
2459 static const struct sh_pfc_function pinmux_functions[] = {
2460 	SH_PFC_FUNCTION(avb),
2461 	SH_PFC_FUNCTION(du0),
2462 	SH_PFC_FUNCTION(du1),
2463 	SH_PFC_FUNCTION(i2c0),
2464 	SH_PFC_FUNCTION(i2c1),
2465 	SH_PFC_FUNCTION(i2c2),
2466 	SH_PFC_FUNCTION(i2c3),
2467 	SH_PFC_FUNCTION(i2c4),
2468 	SH_PFC_FUNCTION(mmc),
2469 	SH_PFC_FUNCTION(qspi0),
2470 	SH_PFC_FUNCTION(qspi1),
2471 	SH_PFC_FUNCTION(scif0),
2472 	SH_PFC_FUNCTION(scif1),
2473 	SH_PFC_FUNCTION(scif2),
2474 	SH_PFC_FUNCTION(scif3),
2475 	SH_PFC_FUNCTION(scif4),
2476 	SH_PFC_FUNCTION(scif5),
2477 	SH_PFC_FUNCTION(scif_clk),
2478 	SH_PFC_FUNCTION(sdhi0),
2479 	SH_PFC_FUNCTION(sdhi1),
2480 	SH_PFC_FUNCTION(sdhi2),
2481 	SH_PFC_FUNCTION(usb0),
2482 	SH_PFC_FUNCTION(usb1),
2483 	SH_PFC_FUNCTION(vin0),
2484 	SH_PFC_FUNCTION(vin1),
2485 };
2486 
2487 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2488 	{ PINMUX_CFG_REG_VAR("GPSR0", 0xE6060004, 32,
2489 			     GROUP(-9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
2490 				   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
2491 			     GROUP(
2492 		/* GP0_31_23 RESERVED */
2493 		GP_0_22_FN, FN_MMC0_D7,
2494 		GP_0_21_FN, FN_MMC0_D6,
2495 		GP_0_20_FN, FN_IP1_7_4,
2496 		GP_0_19_FN, FN_IP1_3_0,
2497 		GP_0_18_FN, FN_MMC0_D3_SDHI1_D3,
2498 		GP_0_17_FN, FN_MMC0_D2_SDHI1_D2,
2499 		GP_0_16_FN, FN_MMC0_D1_SDHI1_D1,
2500 		GP_0_15_FN, FN_MMC0_D0_SDHI1_D0,
2501 		GP_0_14_FN, FN_MMC0_CMD_SDHI1_CMD,
2502 		GP_0_13_FN, FN_MMC0_CLK_SDHI1_CLK,
2503 		GP_0_12_FN, FN_IP0_31_28,
2504 		GP_0_11_FN, FN_IP0_27_24,
2505 		GP_0_10_FN, FN_IP0_23_20,
2506 		GP_0_9_FN, FN_IP0_19_16,
2507 		GP_0_8_FN, FN_IP0_15_12,
2508 		GP_0_7_FN, FN_IP0_11_8,
2509 		GP_0_6_FN, FN_IP0_7_4,
2510 		GP_0_5_FN, FN_IP0_3_0,
2511 		GP_0_4_FN, FN_CLKOUT,
2512 		GP_0_3_FN, FN_USB1_OVC,
2513 		GP_0_2_FN, FN_USB1_PWEN,
2514 		GP_0_1_FN, FN_USB0_OVC,
2515 		GP_0_0_FN, FN_USB0_PWEN, ))
2516 	},
2517 	{ PINMUX_CFG_REG_VAR("GPSR1", 0xE6060008, 32,
2518 			     GROUP(-9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
2519 				   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
2520 			     GROUP(
2521 		/* GP1_31_23 RESERVED */
2522 		GP_1_22_FN, FN_IP4_3_0,
2523 		GP_1_21_FN, FN_IP3_31_28,
2524 		GP_1_20_FN, FN_IP3_27_24,
2525 		GP_1_19_FN, FN_IP3_23_20,
2526 		GP_1_18_FN, FN_IP3_19_16,
2527 		GP_1_17_FN, FN_IP3_15_12,
2528 		GP_1_16_FN, FN_IP3_11_8,
2529 		GP_1_15_FN, FN_IP3_7_4,
2530 		GP_1_14_FN, FN_IP3_3_0,
2531 		GP_1_13_FN, FN_IP2_31_28,
2532 		GP_1_12_FN, FN_IP2_27_24,
2533 		GP_1_11_FN, FN_IP2_23_20,
2534 		GP_1_10_FN, FN_IP2_19_16,
2535 		GP_1_9_FN, FN_IP2_15_12,
2536 		GP_1_8_FN, FN_IP2_11_8,
2537 		GP_1_7_FN, FN_IP2_7_4,
2538 		GP_1_6_FN, FN_IP2_3_0,
2539 		GP_1_5_FN, FN_IP1_31_28,
2540 		GP_1_4_FN, FN_IP1_27_24,
2541 		GP_1_3_FN, FN_IP1_23_20,
2542 		GP_1_2_FN, FN_IP1_19_16,
2543 		GP_1_1_FN, FN_IP1_15_12,
2544 		GP_1_0_FN, FN_IP1_11_8, ))
2545 	},
2546 	{ PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1, GROUP(
2547 		GP_2_31_FN, FN_IP8_3_0,
2548 		GP_2_30_FN, FN_IP7_31_28,
2549 		GP_2_29_FN, FN_IP7_27_24,
2550 		GP_2_28_FN, FN_IP7_23_20,
2551 		GP_2_27_FN, FN_IP7_19_16,
2552 		GP_2_26_FN, FN_IP7_15_12,
2553 		GP_2_25_FN, FN_IP7_11_8,
2554 		GP_2_24_FN, FN_IP7_7_4,
2555 		GP_2_23_FN, FN_IP7_3_0,
2556 		GP_2_22_FN, FN_IP6_31_28,
2557 		GP_2_21_FN, FN_IP6_27_24,
2558 		GP_2_20_FN, FN_IP6_23_20,
2559 		GP_2_19_FN, FN_IP6_19_16,
2560 		GP_2_18_FN, FN_IP6_15_12,
2561 		GP_2_17_FN, FN_IP6_11_8,
2562 		GP_2_16_FN, FN_IP6_7_4,
2563 		GP_2_15_FN, FN_IP6_3_0,
2564 		GP_2_14_FN, FN_IP5_31_28,
2565 		GP_2_13_FN, FN_IP5_27_24,
2566 		GP_2_12_FN, FN_IP5_23_20,
2567 		GP_2_11_FN, FN_IP5_19_16,
2568 		GP_2_10_FN, FN_IP5_15_12,
2569 		GP_2_9_FN, FN_IP5_11_8,
2570 		GP_2_8_FN, FN_IP5_7_4,
2571 		GP_2_7_FN, FN_IP5_3_0,
2572 		GP_2_6_FN, FN_IP4_31_28,
2573 		GP_2_5_FN, FN_IP4_27_24,
2574 		GP_2_4_FN, FN_IP4_23_20,
2575 		GP_2_3_FN, FN_IP4_19_16,
2576 		GP_2_2_FN, FN_IP4_15_12,
2577 		GP_2_1_FN, FN_IP4_11_8,
2578 		GP_2_0_FN, FN_IP4_7_4, ))
2579 	},
2580 	{ PINMUX_CFG_REG_VAR("GPSR3", 0xE6060010, 32,
2581 			     GROUP(-2, 1, 1, -10, 1, 1, 1, 1, 1, 1, 1, 1,
2582 				   1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
2583 			     GROUP(
2584 		/* GP3_31_30 RESERVED */
2585 		GP_3_29_FN, FN_IP10_19_16,
2586 		GP_3_28_FN, FN_IP10_15_12,
2587 		GP_3_27_FN, FN_IP10_11_8,
2588 		/* GP3_26_17 RESERVED */
2589 		GP_3_16_FN, FN_IP10_7_4,
2590 		GP_3_15_FN, FN_IP10_3_0,
2591 		GP_3_14_FN, FN_IP9_31_28,
2592 		GP_3_13_FN, FN_IP9_27_24,
2593 		GP_3_12_FN, FN_IP9_23_20,
2594 		GP_3_11_FN, FN_IP9_19_16,
2595 		GP_3_10_FN, FN_IP9_15_12,
2596 		GP_3_9_FN, FN_IP9_11_8,
2597 		GP_3_8_FN, FN_IP9_7_4,
2598 		GP_3_7_FN, FN_IP9_3_0,
2599 		GP_3_6_FN, FN_IP8_31_28,
2600 		GP_3_5_FN, FN_IP8_27_24,
2601 		GP_3_4_FN, FN_IP8_23_20,
2602 		GP_3_3_FN, FN_IP8_19_16,
2603 		GP_3_2_FN, FN_IP8_15_12,
2604 		GP_3_1_FN, FN_IP8_11_8,
2605 		GP_3_0_FN, FN_IP8_7_4, ))
2606 	},
2607 	{ PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1, GROUP(
2608 		0, 0,
2609 		0, 0,
2610 		0, 0,
2611 		0, 0,
2612 		0, 0,
2613 		0, 0,
2614 		GP_4_25_FN, FN_IP13_27_24,
2615 		GP_4_24_FN, FN_IP13_23_20,
2616 		GP_4_23_FN, FN_IP13_19_16,
2617 		GP_4_22_FN, FN_IP13_15_12,
2618 		GP_4_21_FN, FN_IP13_11_8,
2619 		GP_4_20_FN, FN_IP13_7_4,
2620 		GP_4_19_FN, FN_IP13_3_0,
2621 		GP_4_18_FN, FN_IP12_31_28,
2622 		GP_4_17_FN, FN_IP12_27_24,
2623 		GP_4_16_FN, FN_IP12_23_20,
2624 		GP_4_15_FN, FN_IP12_19_16,
2625 		GP_4_14_FN, FN_IP12_15_12,
2626 		GP_4_13_FN, FN_IP12_11_8,
2627 		GP_4_12_FN, FN_IP12_7_4,
2628 		GP_4_11_FN, FN_IP12_3_0,
2629 		GP_4_10_FN, FN_IP11_31_28,
2630 		GP_4_9_FN, FN_IP11_27_24,
2631 		GP_4_8_FN, FN_IP11_23_20,
2632 		GP_4_7_FN, FN_IP11_19_16,
2633 		GP_4_6_FN, FN_IP11_15_12,
2634 		GP_4_5_FN, FN_IP11_11_8,
2635 		GP_4_4_FN, FN_IP11_7_4,
2636 		GP_4_3_FN, FN_IP11_3_0,
2637 		GP_4_2_FN, FN_IP10_31_28,
2638 		GP_4_1_FN, FN_IP10_27_24,
2639 		GP_4_0_FN, FN_IP10_23_20, ))
2640 	},
2641 	{ PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1, GROUP(
2642 		GP_5_31_FN, FN_IP17_27_24,
2643 		GP_5_30_FN, FN_IP17_23_20,
2644 		GP_5_29_FN, FN_IP17_19_16,
2645 		GP_5_28_FN, FN_IP17_15_12,
2646 		GP_5_27_FN, FN_IP17_11_8,
2647 		GP_5_26_FN, FN_IP17_7_4,
2648 		GP_5_25_FN, FN_IP17_3_0,
2649 		GP_5_24_FN, FN_IP16_31_28,
2650 		GP_5_23_FN, FN_IP16_27_24,
2651 		GP_5_22_FN, FN_IP16_23_20,
2652 		GP_5_21_FN, FN_IP16_19_16,
2653 		GP_5_20_FN, FN_IP16_15_12,
2654 		GP_5_19_FN, FN_IP16_11_8,
2655 		GP_5_18_FN, FN_IP16_7_4,
2656 		GP_5_17_FN, FN_IP16_3_0,
2657 		GP_5_16_FN, FN_IP15_31_28,
2658 		GP_5_15_FN, FN_IP15_27_24,
2659 		GP_5_14_FN, FN_IP15_23_20,
2660 		GP_5_13_FN, FN_IP15_19_16,
2661 		GP_5_12_FN, FN_IP15_15_12,
2662 		GP_5_11_FN, FN_IP15_11_8,
2663 		GP_5_10_FN, FN_IP15_7_4,
2664 		GP_5_9_FN, FN_IP15_3_0,
2665 		GP_5_8_FN, FN_IP14_31_28,
2666 		GP_5_7_FN, FN_IP14_27_24,
2667 		GP_5_6_FN, FN_IP14_23_20,
2668 		GP_5_5_FN, FN_IP14_19_16,
2669 		GP_5_4_FN, FN_IP14_15_12,
2670 		GP_5_3_FN, FN_IP14_11_8,
2671 		GP_5_2_FN, FN_IP14_7_4,
2672 		GP_5_1_FN, FN_IP14_3_0,
2673 		GP_5_0_FN, FN_IP13_31_28, ))
2674 	},
2675 	{ PINMUX_CFG_REG("IPSR0", 0xE6060040, 32, 4, GROUP(
2676 		/* IP0_31_28 [4] */
2677 		FN_SD0_WP, FN_IRQ7, FN_CAN0_TX_A, 0, 0, 0, 0, 0,
2678 		0, 0, 0, 0, 0, 0, 0, 0,
2679 		/* IP0_27_24 [4] */
2680 		FN_SD0_CD, 0, FN_CAN0_RX_A, 0, 0, 0, 0, 0,
2681 		0, 0, 0, 0, 0, 0, 0, 0,
2682 		/* IP0_23_20 [4] */
2683 		FN_SD0_DAT3, 0, 0, FN_SSI_SDATA0_B, FN_TX5_E, 0, 0, 0,
2684 		0, 0, 0, 0, 0, 0, 0, 0,
2685 		/* IP0_19_16 [4] */
2686 		FN_SD0_DAT2, 0, 0, FN_SSI_WS0129_B, FN_RX5_E, 0, 0, 0,
2687 		0, 0, 0, 0, 0, 0, 0, 0,
2688 		/* IP0_15_12 [4] */
2689 		FN_SD0_DAT1, 0, 0, FN_SSI_SCK0129_B, FN_TX4_E, 0, 0, 0,
2690 		0, 0, 0, 0, 0, 0, 0, 0,
2691 		/* IP0_11_8 [4] */
2692 		FN_SD0_DAT0, 0, 0, FN_SSI_SDATA1_C, FN_RX4_E, 0, 0, 0,
2693 		0, 0, 0, 0, 0, 0, 0, 0,
2694 		/* IP0_7_4 [4] */
2695 		FN_SD0_CMD, 0, 0, FN_SSI_WS1_C, FN_TX3_C, 0, 0, 0,
2696 		0, 0, 0, 0, 0, 0, 0, 0,
2697 		/* IP0_3_0 [4] */
2698 		FN_SD0_CLK, 0, 0, FN_SSI_SCK1_C, FN_RX3_C, 0, 0, 0,
2699 		0, 0, 0, 0, 0, 0, 0, 0, ))
2700 	},
2701 	{ PINMUX_CFG_REG("IPSR1", 0xE6060044, 32, 4, GROUP(
2702 		/* IP1_31_28 [4] */
2703 		FN_D5, FN_HRX2, FN_SCL1_B, FN_PWM2_C, FN_TCLK2_B, 0, 0, 0,
2704 		0, 0, 0, 0, 0, 0, 0, 0,
2705 		/* IP1_27_24 [4] */
2706 		FN_D4, 0, FN_IRQ3, FN_TCLK1_A, FN_PWM6_C, 0, 0, 0,
2707 		0, 0, 0, 0, 0, 0, 0, 0,
2708 		/* IP1_23_20 [4] */
2709 		FN_D3, 0, FN_TX4_B, FN_SDA0_D, FN_PWM0_A,
2710 		FN_MSIOF2_SYNC_C, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2711 		/* IP1_19_16 [4] */
2712 		FN_D2, 0, FN_RX4_B, FN_SCL0_D, FN_PWM1_C,
2713 		FN_MSIOF2_SCK_C, FN_SSI_SCK5_B, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2714 		/* IP1_15_12 [4] */
2715 		FN_D1, 0, FN_SDA3_B, FN_TX5_B, 0, FN_MSIOF2_TXD_C,
2716 		FN_SSI_WS5_B, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2717 		/* IP1_11_8 [4] */
2718 		FN_D0, 0, FN_SCL3_B, FN_RX5_B, FN_IRQ4,
2719 		FN_MSIOF2_RXD_C, FN_SSI_SDATA5_B, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2720 		/* IP1_7_4 [4] */
2721 		FN_MMC0_D5, FN_SD1_WP, 0, 0, 0, 0, 0, 0,
2722 		0, 0, 0, 0, 0, 0, 0, 0,
2723 		/* IP1_3_0 [4] */
2724 		FN_MMC0_D4, FN_SD1_CD, 0, 0, 0, 0, 0, 0,
2725 		0, 0, 0, 0, 0, 0, 0, 0, ))
2726 	},
2727 	{ PINMUX_CFG_REG("IPSR2", 0xE6060048, 32, 4, GROUP(
2728 		/* IP2_31_28 [4] */
2729 		FN_D13, FN_MSIOF2_SYNC_A, 0, FN_RX4_C, 0, 0, 0, 0, 0,
2730 		0, 0, 0, 0, 0, 0, 0,
2731 		/* IP2_27_24 [4] */
2732 		FN_D12, FN_MSIOF2_SCK_A, FN_HSCK0, 0, FN_CAN_CLK_C,
2733 		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2734 		/* IP2_23_20 [4] */
2735 		FN_D11, FN_MSIOF2_TXD_A, FN_HTX0_B, 0, 0, 0, 0, 0, 0,
2736 		0, 0, 0, 0, 0, 0, 0,
2737 		/* IP2_19_16 [4] */
2738 		FN_D10, FN_MSIOF2_RXD_A, FN_HRX0_B, 0, 0, 0, 0, 0, 0,
2739 		0, 0, 0, 0, 0, 0, 0,
2740 		/* IP2_15_12 [4] */
2741 		FN_D9, FN_HRTS2_N, FN_TX1_C, FN_SDA1_D, 0, 0, 0,
2742 		0, 0, 0, 0, 0, 0, 0, 0, 0,
2743 		/* IP2_11_8 [4] */
2744 		FN_D8, FN_HCTS2_N, FN_RX1_C, FN_SCL1_D, FN_PWM3_C, 0,
2745 		0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2746 		/* IP2_7_4 [4] */
2747 		FN_D7, FN_HSCK2, FN_SCIF1_SCK_C, FN_IRQ6, FN_PWM5_C,
2748 		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2749 		/* IP2_3_0 [4] */
2750 		FN_D6, FN_HTX2, FN_SDA1_B, FN_PWM4_C, 0, 0, 0, 0,
2751 		0, 0, 0, 0, 0, 0, 0, 0, ))
2752 	},
2753 	{ PINMUX_CFG_REG("IPSR3", 0xE606004C, 32, 4, GROUP(
2754 		/* IP3_31_28 [4] */
2755 		FN_QSPI0_SSL, FN_WE1_N, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2756 		0, 0,
2757 		/* IP3_27_24 [4] */
2758 		FN_QSPI0_IO3, FN_RD_N, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2759 		0, 0,
2760 		/* IP3_23_20 [4] */
2761 		FN_QSPI0_IO2, FN_CS0_N, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2762 		0, 0,
2763 		/* IP3_19_16 [4] */
2764 		FN_QSPI0_MISO_QSPI0_IO1, FN_RD_WR_N, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2765 		0, 0, 0, 0,
2766 		/* IP3_15_12 [4] */
2767 		FN_QSPI0_MOSI_QSPI0_IO0, FN_BS_N, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2768 		0, 0, 0,
2769 		/* IP3_11_8 [4] */
2770 		FN_QSPI0_SPCLK, FN_WE0_N, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2771 		0, 0,
2772 		/* IP3_7_4 [4] */
2773 		FN_D15, FN_MSIOF2_SS2, FN_PWM4_A, 0, FN_CAN1_TX_B, FN_IRQ2,
2774 		FN_AVB_AVTP_MATCH_A, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2775 		/* IP3_3_0 [4] */
2776 		FN_D14, FN_MSIOF2_SS1, 0, FN_TX4_C, FN_CAN1_RX_B,
2777 		0, FN_AVB_AVTP_CAPTURE_A,
2778 		0, 0, 0, 0, 0, 0, 0, 0, 0, ))
2779 	},
2780 	{ PINMUX_CFG_REG("IPSR4", 0xE6060050, 32, 4, GROUP(
2781 		/* IP4_31_28 [4] */
2782 		FN_DU0_DR6, 0, FN_RX2_C, 0, 0, 0, FN_A6, 0,
2783 		0, 0, 0, 0, 0, 0, 0, 0,
2784 		/* IP4_27_24 [4] */
2785 		FN_DU0_DR5, 0, FN_TX1_D, 0, FN_PWM1_B, 0, FN_A5, 0,
2786 		0, 0, 0, 0, 0, 0, 0, 0,
2787 		/* IP4_23_20 [4] */
2788 		FN_DU0_DR4, 0, FN_RX1_D, 0, 0, 0, FN_A4, 0, 0, 0, 0,
2789 		0, 0, 0, 0, 0,
2790 		/* IP4_19_16 [4] */
2791 		FN_DU0_DR3, 0, FN_TX0_D, FN_SDA0_E, FN_PWM0_B, 0,
2792 		FN_A3, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2793 		/* IP4_15_12 [4] */
2794 		FN_DU0_DR2, 0, FN_RX0_D, FN_SCL0_E, 0, 0, FN_A2, 0,
2795 		0, 0, 0, 0, 0, 0, 0, 0,
2796 		/* IP4_11_8 [4] */
2797 		FN_DU0_DR1, 0, FN_TX5_C, FN_SDA2_D, 0, 0, FN_A1, 0,
2798 		0, 0, 0, 0, 0, 0, 0, 0,
2799 		/* IP4_7_4 [4] */
2800 		FN_DU0_DR0, 0, FN_RX5_C, FN_SCL2_D, 0, 0, FN_A0, 0,
2801 		0, 0, 0, 0, 0, 0, 0, 0,
2802 		/* IP4_3_0 [4] */
2803 		FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK_A, 0, 0, 0, 0,
2804 		0, 0, 0, 0, 0, 0, 0, 0, 0, ))
2805 	},
2806 	{ PINMUX_CFG_REG("IPSR5", 0xE6060054, 32, 4, GROUP(
2807 		/* IP5_31_28 [4] */
2808 		FN_DU0_DG6, 0, FN_HRX1_C, 0, 0, 0, FN_A14,  0, 0, 0,
2809 		0, 0, 0, 0, 0, 0,
2810 		/* IP5_27_24 [4] */
2811 		FN_DU0_DG5, 0, FN_HTX0_A, 0, FN_PWM5_B, 0, FN_A13,
2812 		0, 0, 0, 0, 0, 0, 0, 0, 0,
2813 		/* IP5_23_20 [4] */
2814 		FN_DU0_DG4, 0, FN_HRX0_A, 0, 0, 0, FN_A12, 0, 0, 0,
2815 		0, 0, 0, 0, 0, 0,
2816 		/* IP5_19_16 [4] */
2817 		FN_DU0_DG3, 0, FN_TX4_D, 0, FN_PWM4_B, 0, FN_A11, 0,
2818 		0, 0, 0, 0, 0, 0, 0, 0,
2819 		/* IP5_15_12 [4] */
2820 		FN_DU0_DG2, 0, FN_RX4_D, 0, 0, 0, FN_A10, 0, 0, 0,
2821 		0, 0, 0, 0, 0, 0,
2822 		/* IP5_11_8 [4] */
2823 		FN_DU0_DG1, 0, FN_TX3_B, FN_SDA3_D, FN_PWM3_B, 0,
2824 		FN_A9, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2825 		/* IP5_7_4 [4] */
2826 		FN_DU0_DG0, 0, FN_RX3_B, FN_SCL3_D, 0, 0, FN_A8, 0,
2827 		0, 0, 0, 0, 0, 0, 0, 0,
2828 		/* IP5_3_0 [4] */
2829 		FN_DU0_DR7, 0, FN_TX2_C, 0, FN_PWM2_B, 0, FN_A7, 0,
2830 		0, 0, 0, 0, 0, 0, 0, 0, ))
2831 	},
2832 	{ PINMUX_CFG_REG("IPSR6", 0xE6060058, 32, 4, GROUP(
2833 		/* IP6_31_28 [4] */
2834 		FN_DU0_DB6, 0, 0, 0, 0, 0, FN_A22, 0, 0,
2835 		0, 0, 0, 0, 0, 0, 0,
2836 		/* IP6_27_24 [4] */
2837 		FN_DU0_DB5, 0, FN_HRTS1_N_C, 0, 0, 0,
2838 		FN_A21, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2839 		/* IP6_23_20 [4] */
2840 		FN_DU0_DB4, 0, FN_HCTS1_N_C, 0, 0, 0,
2841 		FN_A20, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2842 		/* IP6_19_16 [4] */
2843 		FN_DU0_DB3, 0, FN_HRTS0_N, 0, 0, 0, FN_A19, 0, 0, 0,
2844 		0, 0, 0, 0, 0, 0,
2845 		/* IP6_15_12 [4] */
2846 		FN_DU0_DB2, 0, FN_HCTS0_N, 0, 0, 0, FN_A18, 0, 0, 0,
2847 		0, 0, 0, 0, 0, 0,
2848 		/* IP6_11_8 [4] */
2849 		FN_DU0_DB1, 0, 0, FN_SDA4_D, FN_CAN0_TX_C, 0, FN_A17,
2850 		0, 0, 0, 0, 0, 0, 0, 0, 0,
2851 		/* IP6_7_4 [4] */
2852 		FN_DU0_DB0, 0, 0, FN_SCL4_D, FN_CAN0_RX_C, 0, FN_A16,
2853 		0, 0, 0, 0, 0, 0, 0, 0, 0,
2854 		/* IP6_3_0 [4] */
2855 		FN_DU0_DG7, 0, FN_HTX1_C, 0,  FN_PWM6_B, 0, FN_A15,
2856 		0, 0, 0, 0, 0, 0, 0, 0, 0, ))
2857 	},
2858 	{ PINMUX_CFG_REG("IPSR7", 0xE606005C, 32, 4, GROUP(
2859 		/* IP7_31_28 [4] */
2860 		FN_DU0_DISP, 0, 0, 0, FN_CAN1_RX_C, 0, 0, 0, 0, 0, 0,
2861 		0, 0, 0, 0, 0,
2862 		/* IP7_27_24 [4] */
2863 		FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, 0, FN_MSIOF2_SCK_B,
2864 		0, 0, 0, FN_DRACK0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2865 		/* IP7_23_20 [4] */
2866 		FN_DU0_EXVSYNC_DU0_VSYNC, 0, FN_MSIOF2_SYNC_B, 0,
2867 		0, 0, FN_DACK0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2868 		/* IP7_19_16 [4] */
2869 		FN_DU0_EXHSYNC_DU0_HSYNC, 0, FN_MSIOF2_TXD_B, 0,
2870 		0, 0, FN_DREQ0_N, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2871 		/* IP7_15_12 [4] */
2872 		FN_DU0_DOTCLKOUT1, 0, FN_MSIOF2_RXD_B, 0, 0, 0,
2873 		FN_CS1_N_A26, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2874 		/* IP7_11_8 [4] */
2875 		FN_DU0_DOTCLKOUT0, 0, 0, 0, 0, 0, FN_A25, 0, 0, 0, 0,
2876 		0, 0, 0, 0, 0,
2877 		/* IP7_7_4 [4] */
2878 		FN_DU0_DOTCLKIN, 0, 0, 0, 0, 0, FN_A24, 0, 0, 0,
2879 		0, 0, 0, 0, 0, 0,
2880 		/* IP7_3_0 [4] */
2881 		FN_DU0_DB7, 0, 0, 0, 0, 0, FN_A23, 0, 0,
2882 		0, 0, 0, 0, 0, 0, 0, ))
2883 	},
2884 	{ PINMUX_CFG_REG("IPSR8", 0xE6060060, 32, 4, GROUP(
2885 		/* IP8_31_28 [4] */
2886 		FN_VI1_DATA5, 0, 0, 0, FN_AVB_RXD4, FN_ETH_LINK, 0, 0, 0, 0,
2887 		0, 0, 0, 0, 0, 0,
2888 		/* IP8_27_24 [4] */
2889 		FN_VI1_DATA4, 0, 0, 0, FN_AVB_RXD3, FN_ETH_RX_ER, 0, 0, 0, 0,
2890 		0, 0, 0, 0, 0, 0,
2891 		/* IP8_23_20 [4] */
2892 		FN_VI1_DATA3, 0, 0, 0, FN_AVB_RXD2, FN_ETH_MDIO, 0, 0, 0, 0,
2893 		0, 0, 0, 0, 0, 0,
2894 		/* IP8_19_16 [4] */
2895 		FN_VI1_DATA2, 0, 0, 0, FN_AVB_RXD1, FN_ETH_RXD1, 0, 0, 0, 0,
2896 		0, 0, 0, 0, 0, 0,
2897 		/* IP8_15_12 [4] */
2898 		FN_VI1_DATA1, 0, 0, 0, FN_AVB_RXD0, FN_ETH_RXD0, 0, 0, 0, 0,
2899 		0, 0, 0, 0, 0, 0,
2900 		/* IP8_11_8 [4] */
2901 		FN_VI1_DATA0, 0, 0, 0, FN_AVB_RX_DV, FN_ETH_CRS_DV, 0, 0, 0,
2902 		0, 0, 0, 0, 0, 0, 0,
2903 		/* IP8_7_4 [4] */
2904 		FN_VI1_CLK, 0, 0, 0, FN_AVB_RX_CLK, FN_ETH_REF_CLK, 0, 0, 0,
2905 		0, 0, 0, 0, 0, 0, 0,
2906 		/* IP8_3_0 [4] */
2907 		FN_DU0_CDE, 0, 0, 0, FN_CAN1_TX_C, 0, 0, 0, 0, 0, 0, 0,
2908 		0, 0, 0, 0, ))
2909 	},
2910 	{ PINMUX_CFG_REG("IPSR9", 0xE6060064, 32, 4, GROUP(
2911 		/* IP9_31_28 [4] */
2912 		FN_VI1_DATA9, 0, 0, FN_SDA2_B, FN_AVB_TXD0, 0, 0, 0, 0, 0, 0,
2913 		0, 0, 0, 0, 0,
2914 		/* IP9_27_24 [4] */
2915 		FN_VI1_DATA8, 0, 0, FN_SCL2_B, FN_AVB_TX_EN, 0, 0, 0, 0, 0, 0,
2916 		0, 0, 0, 0, 0,
2917 		/* IP9_23_20 [4] */
2918 		FN_VI1_VSYNC_N, FN_TX0_B, FN_SDA0_C, FN_AUDIO_CLKOUT_B,
2919 		FN_AVB_TX_CLK, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2920 		/* IP9_19_16 [4] */
2921 		FN_VI1_HSYNC_N, FN_RX0_B, FN_SCL0_C, 0, FN_AVB_GTXREFCLK,
2922 		FN_ETH_MDC, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2923 		/* IP9_15_12 [4] */
2924 		FN_VI1_FIELD, FN_SDA3_A, 0, 0, FN_AVB_RX_ER, FN_ETH_TXD0, 0,
2925 		0, 0, 0, 0, 0, 0, 0, 0, 0,
2926 		/* IP9_11_8 [4] */
2927 		FN_VI1_CLKENB, FN_SCL3_A, 0, 0, FN_AVB_RXD7, FN_ETH_MAGIC, 0,
2928 		0, 0, 0, 0, 0, 0, 0, 0, 0,
2929 		/* IP9_7_4 [4] */
2930 		FN_VI1_DATA7, 0, 0, 0, FN_AVB_RXD6, FN_ETH_TX_EN, 0, 0, 0, 0,
2931 		0, 0, 0, 0, 0, 0,
2932 		/* IP9_3_0 [4] */
2933 		FN_VI1_DATA6, 0, 0, 0, FN_AVB_RXD5, FN_ETH_TXD1, 0, 0, 0, 0,
2934 		0, 0, 0, 0, 0, 0, ))
2935 	},
2936 	{ PINMUX_CFG_REG("IPSR10", 0xE6060068, 32, 4, GROUP(
2937 		/* IP10_31_28 [4] */
2938 		FN_SCL1_A, FN_RX4_A, FN_PWM5_D, FN_DU1_DR0, 0, 0,
2939 		FN_SSI_SCK6_B, FN_VI0_G0, 0, 0, 0, 0, 0, 0, 0, 0,
2940 		/* IP10_27_24 [4] */
2941 		FN_SDA0_A, FN_TX0_C, FN_IRQ5, FN_CAN_CLK_A, FN_AVB_GTX_CLK,
2942 		FN_CAN1_TX_D, FN_DVC_MUTE, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2943 		/* IP10_23_20 [4] */
2944 		FN_SCL0_A, FN_RX0_C, FN_PWM5_A, FN_TCLK1_B, FN_AVB_TXD6,
2945 		FN_CAN1_RX_D, FN_MSIOF0_SYNC_B, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2946 		/* IP10_19_16 [4] */
2947 		FN_AVB_TXD5, FN_SCIF_CLK_B, FN_AUDIO_CLKC_B, 0,
2948 		FN_SSI_SDATA1_D, 0, FN_MSIOF0_SCK_B, 0, 0, 0, 0, 0, 0, 0,
2949 		0, 0,
2950 		/* IP10_15_12 [4] */
2951 		FN_AVB_TXD4, 0, FN_AUDIO_CLKB_B, 0, FN_SSI_WS1_D, FN_TX5_F,
2952 		FN_MSIOF0_TXD_B, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2953 		/* IP10_11_8 [4] */
2954 		FN_AVB_TXD3, 0, FN_AUDIO_CLKA_B, 0, FN_SSI_SCK1_D, FN_RX5_F,
2955 		FN_MSIOF0_RXD_B, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2956 		/* IP10_7_4 [4] */
2957 		FN_VI1_DATA11, 0, 0, FN_CAN0_TX_B, FN_AVB_TXD2, 0, 0, 0, 0,
2958 		0, 0, 0, 0, 0, 0, 0,
2959 		/* IP10_3_0 [4] */
2960 		FN_VI1_DATA10, 0, 0, FN_CAN0_RX_B, FN_AVB_TXD1, 0, 0, 0, 0,
2961 		0, 0, 0, 0, 0, 0, 0, ))
2962 	},
2963 	{ PINMUX_CFG_REG("IPSR11", 0xE606006C, 32, 4, GROUP(
2964 		/* IP11_31_28 [4] */
2965 		FN_HRX1_A, FN_SCL4_A, FN_PWM6_A, FN_DU1_DG0, FN_RX0_A, 0, 0,
2966 		0, 0, 0, 0, 0, 0, 0, 0, 0,
2967 		/* IP11_27_24 [4] */
2968 		FN_MSIOF0_SS2_A, 0, 0, FN_DU1_DR7, 0,
2969 		FN_QSPI1_SSL, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2970 		/* IP11_23_20 [4] */
2971 		FN_MSIOF0_SS1_A, 0, 0, FN_DU1_DR6, 0,
2972 		FN_QSPI1_IO3, FN_SSI_SDATA8_B, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2973 		/* IP11_19_16 [4] */
2974 		FN_MSIOF0_SYNC_A, FN_PWM1_A, 0, FN_DU1_DR5,
2975 		0, FN_QSPI1_IO2, FN_SSI_SDATA7_B, 0, 0, 0, 0, 0,
2976 		0, 0, 0, 0,
2977 		/* IP11_15_12 [4] */
2978 		FN_MSIOF0_SCK_A, FN_IRQ0, 0, FN_DU1_DR4,
2979 		0, FN_QSPI1_SPCLK, FN_SSI_SCK78_B, FN_VI0_G4,
2980 		0, 0, 0, 0, 0, 0, 0, 0,
2981 		/* IP11_11_8 [4] */
2982 		FN_MSIOF0_TXD_A, FN_TX5_A, FN_SDA2_C, FN_DU1_DR3, 0,
2983 		FN_QSPI1_MISO_QSPI1_IO1, FN_SSI_WS78_B, FN_VI0_G3,
2984 		0, 0, 0, 0, 0, 0, 0, 0,
2985 		/* IP11_7_4 [4] */
2986 		FN_MSIOF0_RXD_A, FN_RX5_A, FN_SCL2_C, FN_DU1_DR2, 0,
2987 		FN_QSPI1_MOSI_QSPI1_IO0, FN_SSI_SDATA6_B, FN_VI0_G2,
2988 		0, 0, 0, 0, 0, 0, 0, 0,
2989 		/* IP11_3_0 [4] */
2990 		FN_SDA1_A, FN_TX4_A, 0, FN_DU1_DR1, 0, 0, FN_SSI_WS6_B,
2991 		FN_VI0_G1, 0, 0, 0, 0, 0, 0, 0, 0, ))
2992 	},
2993 	{ PINMUX_CFG_REG("IPSR12", 0xE6060070, 32, 4, GROUP(
2994 		/* IP12_31_28 [4] */
2995 		FN_SD2_DAT2, FN_RX2_A, 0, FN_DU1_DB0, FN_SSI_SDATA2_B, 0, 0,
2996 		0, 0, 0, 0, 0, 0, 0, 0, 0,
2997 		/* IP12_27_24 [4] */
2998 		FN_SD2_DAT1, FN_TX1_A, FN_SDA1_E, FN_DU1_DG7, FN_SSI_WS2_B,
2999 		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3000 		/* IP12_23_20 [4] */
3001 		FN_SD2_DAT0, FN_RX1_A, FN_SCL1_E, FN_DU1_DG6,
3002 		FN_SSI_SDATA1_B, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3003 		/* IP12_19_16 [4] */
3004 		FN_SD2_CMD, FN_SCIF1_SCK_A, FN_TCLK2_A, FN_DU1_DG5,
3005 		FN_SSI_SCK2_B, FN_PWM3_A, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3006 		/* IP12_15_12 [4] */
3007 		FN_SD2_CLK, FN_HSCK1, 0, FN_DU1_DG4, FN_SSI_SCK1_B, 0, 0, 0,
3008 		0, 0, 0, 0, 0, 0, 0, 0,
3009 		/* IP12_11_8 [4] */
3010 		FN_HRTS1_N_A, 0, 0, FN_DU1_DG3, FN_SSI_WS1_B, FN_IRQ1, 0, 0,
3011 		0, 0, 0, 0, 0, 0, 0, 0,
3012 		/* IP12_7_4 [4] */
3013 		FN_HCTS1_N_A, FN_PWM2_A, 0, FN_DU1_DG2, FN_REMOCON_B,
3014 		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3015 		/* IP12_3_0 [4] */
3016 		FN_HTX1_A, FN_SDA4_A, 0, FN_DU1_DG1, FN_TX0_A, 0, 0, 0, 0, 0,
3017 		0, 0, 0, 0, 0, 0, ))
3018 	},
3019 	{ PINMUX_CFG_REG("IPSR13", 0xE6060074, 32, 4, GROUP(
3020 		/* IP13_31_28 [4] */
3021 		FN_SSI_SCK5_A, 0, 0, FN_DU1_DOTCLKOUT1, 0, 0, 0, 0, 0, 0, 0,
3022 		0, 0, 0, 0, 0,
3023 		/* IP13_27_24 [4] */
3024 		FN_SDA2_A, 0, FN_MSIOF1_SYNC_B, FN_DU1_DB7, FN_AUDIO_CLKOUT_C,
3025 		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3026 		/* IP13_23_20 [4] */
3027 		FN_SCL2_A, 0, FN_MSIOF1_SCK_B, FN_DU1_DB6, FN_AUDIO_CLKC_C,
3028 		FN_SSI_SCK4_B, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3029 		/* IP13_19_16 [4] */
3030 		FN_TX3_A, FN_SDA1_C, FN_MSIOF1_TXD_B, FN_DU1_DB5,
3031 		FN_AUDIO_CLKB_C, FN_SSI_WS4_B, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3032 		/* IP13_15_12 [4] */
3033 		FN_RX3_A, FN_SCL1_C, FN_MSIOF1_RXD_B, FN_DU1_DB4,
3034 		FN_AUDIO_CLKA_C, FN_SSI_SDATA4_B, 0, 0, 0, 0, 0, 0, 0, 0,
3035 		0, 0,
3036 		/* IP13_11_8 [4] */
3037 		FN_SD2_WP, FN_SCIF3_SCK, 0, FN_DU1_DB3, FN_SSI_SDATA9_B, 0,
3038 		0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3039 		/* IP13_7_4 [4] */
3040 		FN_SD2_CD, FN_SCIF2_SCK_A, 0, FN_DU1_DB2, FN_SSI_SCK9_B, 0, 0,
3041 		0, 0, 0, 0, 0, 0, 0, 0, 0,
3042 		/* IP13_3_0 [4] */
3043 		FN_SD2_DAT3, FN_TX2_A, 0, FN_DU1_DB1, FN_SSI_WS9_B, 0, 0, 0,
3044 		0, 0, 0, 0, 0, 0, 0, 0, ))
3045 	},
3046 	{ PINMUX_CFG_REG("IPSR14", 0xE6060078, 32, 4, GROUP(
3047 		/* IP14_31_28 [4] */
3048 		FN_SSI_SDATA7_A, 0, 0, FN_IRQ8, FN_AUDIO_CLKA_D, FN_CAN_CLK_D,
3049 		FN_VI0_G5, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3050 		/* IP14_27_24 [4] */
3051 		FN_SSI_WS78_A, 0, FN_SCL4_E, FN_DU1_CDE, 0, 0, 0, 0, 0, 0, 0,
3052 		0, 0, 0, 0, 0,
3053 		/* IP14_23_20 [4] */
3054 		FN_SSI_SCK78_A, 0, FN_SDA4_E, FN_DU1_DISP, 0, 0, 0, 0, 0, 0,
3055 		0, 0, 0, 0, 0, 0,
3056 		/* IP14_19_16 [4] */
3057 		FN_SSI_SDATA6_A, 0, FN_SDA4_C, FN_DU1_EXVSYNC_DU1_VSYNC, 0, 0,
3058 		0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3059 		/* IP14_15_12 [4] */
3060 		FN_SSI_WS6_A, 0, FN_SCL4_C, FN_DU1_EXHSYNC_DU1_HSYNC, 0, 0, 0,
3061 		0, 0, 0, 0, 0, 0, 0, 0, 0,
3062 		/* IP14_11_8 [4] */
3063 		FN_SSI_SCK6_A, 0, 0, FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, 0, 0,
3064 		0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3065 		/* IP14_7_4 [4] */
3066 		FN_SSI_SDATA5_A, 0, FN_SDA3_C, FN_DU1_DOTCLKOUT0, 0, 0, 0,
3067 		0, 0, 0, 0, 0, 0, 0, 0, 0,
3068 		/* IP14_3_0 [4] */
3069 		FN_SSI_WS5_A, 0, FN_SCL3_C, FN_DU1_DOTCLKIN, 0, 0, 0, 0, 0, 0,
3070 		0, 0, 0, 0, 0, 0, ))
3071 	},
3072 	{ PINMUX_CFG_REG("IPSR15", 0xE606007C, 32, 4, GROUP(
3073 		/* IP15_31_28 [4] */
3074 		FN_SSI_WS4_A, 0, FN_AVB_PHY_INT, 0, 0, 0, FN_VI0_R5, 0, 0, 0,
3075 		0, 0, 0, 0, 0, 0,
3076 		/* IP15_27_24 [4] */
3077 		FN_SSI_SCK4_A, 0, FN_AVB_MAGIC, 0, 0, 0, FN_VI0_R4, 0, 0, 0,
3078 		0, 0, 0, 0, 0, 0,
3079 		/* IP15_23_20 [4] */
3080 		FN_SSI_SDATA3, FN_MSIOF1_SS2_A, FN_AVB_LINK, 0, FN_CAN1_TX_A,
3081 		FN_DREQ2_N, FN_VI0_R3, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3082 		/* IP15_19_16 [4] */
3083 		FN_SSI_WS34, FN_MSIOF1_SS1_A, FN_AVB_MDIO, 0, FN_CAN1_RX_A,
3084 		FN_DREQ1_N, FN_VI0_R2, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3085 		/* IP15_15_12 [4] */
3086 		FN_SSI_SCK34, FN_MSIOF1_SCK_A, FN_AVB_MDC, 0, 0, FN_DACK1,
3087 		FN_VI0_R1, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3088 		/* IP15_11_8 [4] */
3089 		FN_SSI_SDATA0_A, FN_MSIOF1_SYNC_A, FN_PWM0_C, 0, 0, 0,
3090 		FN_VI0_R0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3091 		/* IP15_7_4 [4] */
3092 		FN_SSI_WS0129_A, FN_MSIOF1_TXD_A, FN_TX5_D, 0, 0, 0,
3093 		FN_VI0_G7, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3094 		/* IP15_3_0 [4] */
3095 		FN_SSI_SCK0129_A, FN_MSIOF1_RXD_A, FN_RX5_D, 0, 0, 0,
3096 		FN_VI0_G6, 0, 0, 0, 0, 0, 0, 0, 0, 0, ))
3097 	},
3098 	{ PINMUX_CFG_REG("IPSR16", 0xE6060080, 32, 4, GROUP(
3099 		/* IP16_31_28 [4] */
3100 		FN_SSI_SDATA2_A, FN_HRTS1_N_B, 0, 0, 0, 0,
3101 		FN_VI0_DATA4_VI0_B4, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3102 		/* IP16_27_24 [4] */
3103 		FN_SSI_WS2_A, FN_HCTS1_N_B, 0, 0, 0, FN_AVB_TX_ER,
3104 		FN_VI0_DATA3_VI0_B3, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3105 		/* IP16_23_20 [4] */
3106 		FN_SSI_SCK2_A, FN_HTX1_B, 0, 0, 0, FN_AVB_TXD7,
3107 		FN_VI0_DATA2_VI0_B2, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3108 		/* IP16_19_16 [4] */
3109 		FN_SSI_SDATA1_A, FN_HRX1_B, 0, 0, 0, 0, FN_VI0_DATA1_VI0_B1,
3110 		0, 0, 0, 0, 0, 0, 0, 0, 0,
3111 		/* IP16_15_12 [4] */
3112 		FN_SSI_WS1_A, FN_TX1_B, 0, 0, FN_CAN0_TX_D,
3113 		FN_AVB_AVTP_MATCH_B, FN_VI0_DATA0_VI0_B0, 0, 0, 0, 0, 0, 0,
3114 		0, 0, 0,
3115 		/* IP16_11_8 [4] */
3116 		FN_SSI_SDATA8_A, FN_RX1_B, 0, 0, FN_CAN0_RX_D,
3117 		FN_AVB_AVTP_CAPTURE_B, FN_VI0_R7, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3118 		/* IP16_7_4 [4] */
3119 		FN_SSI_SCK1_A, FN_SCIF1_SCK_B, FN_PWM1_D, FN_IRQ9, FN_REMOCON_A,
3120 		FN_DACK2, FN_VI0_CLK, FN_AVB_COL, 0, 0, 0, 0, 0, 0, 0, 0,
3121 		/* IP16_3_0 [4] */
3122 		FN_SSI_SDATA4_A, 0, FN_AVB_CRS, 0, 0, 0, FN_VI0_R6, 0, 0, 0,
3123 		0, 0, 0, 0, 0, 0, ))
3124 	},
3125 	{ PINMUX_CFG_REG_VAR("IPSR17", 0xE6060084, 32,
3126 			     GROUP(-4, 4, 4, 4, 4, 4, 4, 4),
3127 			     GROUP(
3128 		/* IP17_31_28 [4] RESERVED */
3129 		/* IP17_27_24 [4] */
3130 		FN_AUDIO_CLKOUT_A, FN_SDA4_B, 0, 0, 0, 0,
3131 		FN_VI0_VSYNC_N, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3132 		/* IP17_23_20 [4] */
3133 		FN_AUDIO_CLKC_A, FN_SCL4_B, 0, 0, 0, 0,
3134 		FN_VI0_HSYNC_N, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3135 		/* IP17_19_16 [4] */
3136 		FN_AUDIO_CLKB_A, FN_SDA0_B, 0, 0, 0, 0,
3137 		FN_VI0_FIELD, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3138 		/* IP17_15_12 [4] */
3139 		FN_AUDIO_CLKA_A, FN_SCL0_B, 0, 0, 0, 0,
3140 		FN_VI0_CLKENB, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3141 		/* IP17_11_8 [4] */
3142 		FN_SSI_SDATA9_A, FN_SCIF2_SCK_B, FN_PWM2_D, 0, 0, 0,
3143 		FN_VI0_DATA7_VI0_B7, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3144 		/* IP17_7_4 [4] */
3145 		FN_SSI_WS9_A, FN_TX2_B, FN_SDA3_E, 0, 0, 0,
3146 		FN_VI0_DATA6_VI0_B6, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3147 		/* IP17_3_0 [4] */
3148 		FN_SSI_SCK9_A, FN_RX2_B, FN_SCL3_E, 0, 0, FN_EX_WAIT1,
3149 		FN_VI0_DATA5_VI0_B5, 0, 0, 0, 0, 0, 0, 0, 0, 0, ))
3150 	},
3151 	{ PINMUX_CFG_REG_VAR("MOD_SEL0", 0xE60600C0, 32,
3152 			     GROUP(-5, 2, -2, 2, 2, 2, -1,
3153 				   3, 3, -1, 2, 3, 3, 1),
3154 			     GROUP(
3155 		/* RESERVED [5] */
3156 		/* SEL_ADGA [2] */
3157 		FN_SEL_ADGA_0, FN_SEL_ADGA_1, FN_SEL_ADGA_2, FN_SEL_ADGA_3,
3158 		/* RESERVED [2] */
3159 		/* SEL_CANCLK [2] */
3160 		FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2,
3161 		FN_SEL_CANCLK_3,
3162 		/* SEL_CAN1 [2] */
3163 		FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
3164 		/* SEL_CAN0 [2] */
3165 		FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
3166 		/* RESERVED [1] */
3167 		/* SEL_I2C04 [3] */
3168 		FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2, FN_SEL_I2C04_3,
3169 		FN_SEL_I2C04_4, 0, 0, 0,
3170 		/* SEL_I2C03 [3] */
3171 		FN_SEL_I2C03_0, FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3,
3172 		FN_SEL_I2C03_4, 0, 0, 0,
3173 		/* RESERVED [1] */
3174 		/* SEL_I2C02 [2] */
3175 		FN_SEL_I2C02_0, FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3,
3176 		/* SEL_I2C01 [3] */
3177 		FN_SEL_I2C01_0, FN_SEL_I2C01_1, FN_SEL_I2C01_2, FN_SEL_I2C01_3,
3178 		FN_SEL_I2C01_4, 0, 0, 0,
3179 		/* SEL_I2C00 [3] */
3180 		FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2, FN_SEL_I2C00_3,
3181 		FN_SEL_I2C00_4, 0, 0, 0,
3182 		/* SEL_AVB [1] */
3183 		FN_SEL_AVB_0, FN_SEL_AVB_1, ))
3184 	},
3185 	{ PINMUX_CFG_REG_VAR("MOD_SEL1", 0xE60600C4, 32,
3186 			     GROUP(1, 3, 3, 2, 2, 1, 2, 2, 2, -1, 1, -1,
3187 				   1, 1, -2, 1, 1, -2, 2, 1),
3188 			     GROUP(
3189 		/* SEL_SCIFCLK [1] */
3190 		FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1,
3191 		/* SEL_SCIF5 [3] */
3192 		FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3,
3193 		FN_SEL_SCIF5_4, FN_SEL_SCIF5_5, 0, 0,
3194 		/* SEL_SCIF4 [3] */
3195 		FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
3196 		FN_SEL_SCIF4_4, 0, 0, 0,
3197 		/* SEL_SCIF3 [2] */
3198 		FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, 0,
3199 		/* SEL_SCIF2 [2] */
3200 		FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, 0,
3201 		/* SEL_SCIF2_CLK [1] */
3202 		FN_SEL_SCIF2_CLK_0, FN_SEL_SCIF2_CLK_1,
3203 		/* SEL_SCIF1 [2] */
3204 		FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
3205 		/* SEL_SCIF0 [2] */
3206 		FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
3207 		/* SEL_MSIOF2 [2] */
3208 		FN_SEL_MSIOF2_0, FN_SEL_MSIOF2_1, FN_SEL_MSIOF2_2, 0,
3209 		/* RESERVED [1] */
3210 		/* SEL_MSIOF1 [1] */
3211 		FN_SEL_MSIOF1_0, FN_SEL_MSIOF1_1,
3212 		/* RESERVED [1] */
3213 		/* SEL_MSIOF0 [1] */
3214 		FN_SEL_MSIOF0_0, FN_SEL_MSIOF0_1,
3215 		/* SEL_RCN [1] */
3216 		FN_SEL_RCN_0, FN_SEL_RCN_1,
3217 		/* RESERVED [2] */
3218 		/* SEL_TMU2 [1] */
3219 		FN_SEL_TMU2_0, FN_SEL_TMU2_1,
3220 		/* SEL_TMU1 [1] */
3221 		FN_SEL_TMU1_0, FN_SEL_TMU1_1,
3222 		/* RESERVED [2] */
3223 		/* SEL_HSCIF1 [2] */
3224 		FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2, 0,
3225 		/* SEL_HSCIF0 [1] */
3226 		FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, ))
3227 	},
3228 	{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE60600C8, 32,
3229 			     GROUP(-10, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2),
3230 			     GROUP(
3231 		/* RESERVED [10] */
3232 		/* SEL_ADGB [2] */
3233 		FN_SEL_ADGB_0, FN_SEL_ADGB_1, FN_SEL_ADGB_2, 0,
3234 		/* SEL_ADGC [2] */
3235 		FN_SEL_ADGC_0, FN_SEL_ADGC_1, FN_SEL_ADGC_2, 0,
3236 		/* SEL_SSI9 [2] */
3237 		FN_SEL_SSI9_0, FN_SEL_SSI9_1, 0, 0,
3238 		/* SEL_SSI8 [2] */
3239 		FN_SEL_SSI8_0, FN_SEL_SSI8_1, 0, 0,
3240 		/* SEL_SSI7 [2] */
3241 		FN_SEL_SSI7_0, FN_SEL_SSI7_1, 0, 0,
3242 		/* SEL_SSI6 [2] */
3243 		FN_SEL_SSI6_0, FN_SEL_SSI6_1, 0, 0,
3244 		/* SEL_SSI5 [2] */
3245 		FN_SEL_SSI5_0, FN_SEL_SSI5_1, 0, 0,
3246 		/* SEL_SSI4 [2] */
3247 		FN_SEL_SSI4_0, FN_SEL_SSI4_1, 0, 0,
3248 		/* SEL_SSI2 [2] */
3249 		FN_SEL_SSI2_0, FN_SEL_SSI2_1, 0, 0,
3250 		/* SEL_SSI1 [2] */
3251 		FN_SEL_SSI1_0, FN_SEL_SSI1_1, FN_SEL_SSI1_2, FN_SEL_SSI1_3,
3252 		/* SEL_SSI0 [2] */
3253 		FN_SEL_SSI0_0, FN_SEL_SSI0_1, 0, 0, ))
3254 	},
3255 	{ /* sentinel */ }
3256 };
3257 
r8a77470_pin_to_pocctrl(unsigned int pin,u32 * pocctrl)3258 static int r8a77470_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
3259 {
3260 	int bit = -EINVAL;
3261 
3262 	*pocctrl = 0xe60600b0;
3263 
3264 	if (pin >= RCAR_GP_PIN(0, 5) && pin <= RCAR_GP_PIN(0, 10))
3265 		bit = 0;
3266 
3267 	if (pin >= RCAR_GP_PIN(0, 13) && pin <= RCAR_GP_PIN(0, 22))
3268 		bit = 2;
3269 
3270 	if (pin >= RCAR_GP_PIN(4, 14) && pin <= RCAR_GP_PIN(4, 19))
3271 		bit = 1;
3272 
3273 	return bit;
3274 }
3275 
3276 static const struct pinmux_bias_reg pinmux_bias_regs[] = {
3277 	{ PINMUX_BIAS_REG("PUPR0", 0xe6060100, "N/A", 0) {
3278 		/* PUPR0 pull-up pins */
3279 		[ 0] = RCAR_GP_PIN(1, 0),	/* D0 */
3280 		[ 1] = RCAR_GP_PIN(0, 22),	/* MMC0_D7 */
3281 		[ 2] = RCAR_GP_PIN(0, 21),	/* MMC0_D6 */
3282 		[ 3] = RCAR_GP_PIN(0, 20),	/* MMC0_D5 */
3283 		[ 4] = RCAR_GP_PIN(0, 19),	/* MMC0_D4 */
3284 		[ 5] = RCAR_GP_PIN(0, 18),	/* MMC0_D3 */
3285 		[ 6] = RCAR_GP_PIN(0, 17),	/* MMC0_D2 */
3286 		[ 7] = RCAR_GP_PIN(0, 16),	/* MMC0_D1 */
3287 		[ 8] = RCAR_GP_PIN(0, 15),	/* MMC0_D0 */
3288 		[ 9] = RCAR_GP_PIN(0, 14),	/* MMC0_CMD */
3289 		[10] = RCAR_GP_PIN(0, 13),	/* MMC0_CLK */
3290 		[11] = RCAR_GP_PIN(0, 12),	/* SD0_WP */
3291 		[12] = RCAR_GP_PIN(0, 11),	/* SD0_CD */
3292 		[13] = RCAR_GP_PIN(0, 10),	/* SD0_DAT3 */
3293 		[14] = RCAR_GP_PIN(0, 9),	/* SD0_DAT2 */
3294 		[15] = RCAR_GP_PIN(0, 8),	/* SD0_DAT1 */
3295 		[16] = RCAR_GP_PIN(0, 7),	/* SD0_DAT0 */
3296 		[17] = RCAR_GP_PIN(0, 6),	/* SD0_CMD */
3297 		[18] = RCAR_GP_PIN(0, 5),	/* SD0_CLK */
3298 		[19] = RCAR_GP_PIN(0, 4),	/* CLKOUT */
3299 		[20] = PIN_NMI,			/* NMI */
3300 		[21] = RCAR_GP_PIN(0, 3),	/* USB1_OVC */
3301 		[22] = RCAR_GP_PIN(0, 2),	/* USB1_PWEN */
3302 		[23] = RCAR_GP_PIN(0, 1),	/* USB0_OVC */
3303 		[24] = RCAR_GP_PIN(0, 0),	/* USB0_PWEN */
3304 		[25] = SH_PFC_PIN_NONE,
3305 		[26] = PIN_TDO,			/* TDO */
3306 		[27] = PIN_TDI,			/* TDI */
3307 		[28] = PIN_TMS,			/* TMS */
3308 		[29] = PIN_TCK,			/* TCK */
3309 		[30] = PIN_TRST_N,		/* TRST# */
3310 		[31] = PIN_PRESETOUT_N,		/* PRESETOUT# */
3311 	} },
3312 	{ PINMUX_BIAS_REG("N/A", 0, "PUPR0", 0xe6060100) {
3313 		/* PUPR0 pull-down pins */
3314 		[ 0] = SH_PFC_PIN_NONE,
3315 		[ 1] = SH_PFC_PIN_NONE,
3316 		[ 2] = SH_PFC_PIN_NONE,
3317 		[ 3] = SH_PFC_PIN_NONE,
3318 		[ 4] = SH_PFC_PIN_NONE,
3319 		[ 5] = SH_PFC_PIN_NONE,
3320 		[ 6] = SH_PFC_PIN_NONE,
3321 		[ 7] = SH_PFC_PIN_NONE,
3322 		[ 8] = SH_PFC_PIN_NONE,
3323 		[ 9] = SH_PFC_PIN_NONE,
3324 		[10] = SH_PFC_PIN_NONE,
3325 		[11] = SH_PFC_PIN_NONE,
3326 		[12] = SH_PFC_PIN_NONE,
3327 		[13] = SH_PFC_PIN_NONE,
3328 		[14] = SH_PFC_PIN_NONE,
3329 		[15] = SH_PFC_PIN_NONE,
3330 		[16] = SH_PFC_PIN_NONE,
3331 		[17] = SH_PFC_PIN_NONE,
3332 		[18] = SH_PFC_PIN_NONE,
3333 		[19] = SH_PFC_PIN_NONE,
3334 		[20] = SH_PFC_PIN_NONE,
3335 		[21] = SH_PFC_PIN_NONE,
3336 		[22] = SH_PFC_PIN_NONE,
3337 		[23] = SH_PFC_PIN_NONE,
3338 		[24] = SH_PFC_PIN_NONE,
3339 		[25] = PIN_ASEBRK_N_ACK,	/* ASEBRK#/ACK */
3340 		[26] = SH_PFC_PIN_NONE,
3341 		[27] = SH_PFC_PIN_NONE,
3342 		[28] = SH_PFC_PIN_NONE,
3343 		[29] = SH_PFC_PIN_NONE,
3344 		[30] = SH_PFC_PIN_NONE,
3345 		[31] = SH_PFC_PIN_NONE,
3346 	} },
3347 	{ PINMUX_BIAS_REG("PUPR1", 0xe6060104, "N/A", 0) {
3348 		[ 0] = RCAR_GP_PIN(2, 9),	/* DU0_DG1 */
3349 		[ 1] = RCAR_GP_PIN(2, 8),	/* DU0_DG0 */
3350 		[ 2] = RCAR_GP_PIN(2, 7),	/* DU0_DR7 */
3351 		[ 3] = RCAR_GP_PIN(2, 6),	/* DU0_DR6 */
3352 		[ 4] = RCAR_GP_PIN(2, 5),	/* DU0_DR5 */
3353 		[ 5] = RCAR_GP_PIN(2, 4),	/* DU0_DR4 */
3354 		[ 6] = RCAR_GP_PIN(2, 3),	/* DU0_DR3 */
3355 		[ 7] = RCAR_GP_PIN(2, 2),	/* DU0_DR2 */
3356 		[ 8] = RCAR_GP_PIN(2, 1),	/* DU0_DR1 */
3357 		[ 9] = RCAR_GP_PIN(2, 0),	/* DU0_DR0 */
3358 		[10] = RCAR_GP_PIN(1, 22),	/* EX_WAIT0 */
3359 		[11] = RCAR_GP_PIN(1, 21),	/* QSPI0_SSL */
3360 		[12] = RCAR_GP_PIN(1, 20),	/* QSPI0_IO3 */
3361 		[13] = RCAR_GP_PIN(1, 19),	/* QSPI0_IO2 */
3362 		[14] = RCAR_GP_PIN(1, 18),	/* QSPI0_MISO/QSPI0_IO1 */
3363 		[15] = RCAR_GP_PIN(1, 17),	/* QSPI0_MOSI/QSPI0_IO0 */
3364 		[16] = RCAR_GP_PIN(1, 16),	/* QSPI0_SPCLK */
3365 		[17] = RCAR_GP_PIN(1, 15),	/* D15 */
3366 		[18] = RCAR_GP_PIN(1, 14),	/* D14 */
3367 		[19] = RCAR_GP_PIN(1, 13),	/* D13 */
3368 		[20] = RCAR_GP_PIN(1, 12),	/* D12 */
3369 		[21] = RCAR_GP_PIN(1, 11),	/* D11 */
3370 		[22] = RCAR_GP_PIN(1, 10),	/* D10 */
3371 		[23] = RCAR_GP_PIN(1, 9),	/* D9 */
3372 		[24] = RCAR_GP_PIN(1, 8),	/* D8 */
3373 		[25] = RCAR_GP_PIN(1, 7),	/* D7 */
3374 		[26] = RCAR_GP_PIN(1, 6),	/* D6 */
3375 		[27] = RCAR_GP_PIN(1, 5),	/* D5 */
3376 		[28] = RCAR_GP_PIN(1, 4),	/* D4 */
3377 		[29] = RCAR_GP_PIN(1, 3),	/* D3 */
3378 		[30] = RCAR_GP_PIN(1, 2),	/* D2 */
3379 		[31] = RCAR_GP_PIN(1, 1),	/* D1 */
3380 	} },
3381 	{ PINMUX_BIAS_REG("PUPR2", 0xe6060108, "N/A", 0) {
3382 		[ 0] = RCAR_GP_PIN(3, 9),	/* VI1_CLKENB */
3383 		[ 1] = RCAR_GP_PIN(3, 8),	/* VI1_DATA7 */
3384 		[ 2] = RCAR_GP_PIN(3, 7),	/* VI1_DATA6 */
3385 		[ 3] = RCAR_GP_PIN(3, 6),	/* VI1_DATA5 */
3386 		[ 4] = RCAR_GP_PIN(3, 5),	/* VI1_DATA4 */
3387 		[ 5] = RCAR_GP_PIN(3, 4),	/* VI1_DATA3 */
3388 		[ 6] = RCAR_GP_PIN(3, 3),	/* VI1_DATA2 */
3389 		[ 7] = RCAR_GP_PIN(3, 2),	/* VI1_DATA1 */
3390 		[ 8] = RCAR_GP_PIN(3, 1),	/* VI1_DATA0 */
3391 		[ 9] = RCAR_GP_PIN(3, 0),	/* VI1_CLK */
3392 		[10] = RCAR_GP_PIN(2, 31),	/* DU0_CDE */
3393 		[11] = RCAR_GP_PIN(2, 30),	/* DU0_DISP */
3394 		[12] = RCAR_GP_PIN(2, 29),	/* DU0_EXODDF/DU0_ODDF_DISP_CDE */
3395 		[13] = RCAR_GP_PIN(2, 28),	/* DU0_EXVSYNC/DU0_VSYNC */
3396 		[14] = RCAR_GP_PIN(2, 27),	/* DU0_EXHSYNC/DU0_HSYNC */
3397 		[15] = RCAR_GP_PIN(2, 26),	/* DU0_DOTCLKOUT1 */
3398 		[16] = RCAR_GP_PIN(2, 25),	/* DU0_DOTCLKOUT0 */
3399 		[17] = RCAR_GP_PIN(2, 24),	/* DU0_DOTCLKIN */
3400 		[18] = RCAR_GP_PIN(2, 23),	/* DU0_DB7 */
3401 		[19] = RCAR_GP_PIN(2, 22),	/* DU0_DB6 */
3402 		[20] = RCAR_GP_PIN(2, 21),	/* DU0_DB5 */
3403 		[21] = RCAR_GP_PIN(2, 20),	/* DU0_DB4 */
3404 		[22] = RCAR_GP_PIN(2, 19),	/* DU0_DB3 */
3405 		[23] = RCAR_GP_PIN(2, 18),	/* DU0_DB2 */
3406 		[24] = RCAR_GP_PIN(2, 17),	/* DU0_DB1 */
3407 		[25] = RCAR_GP_PIN(2, 16),	/* DU0_DB0 */
3408 		[26] = RCAR_GP_PIN(2, 15),	/* DU0_DG7 */
3409 		[27] = RCAR_GP_PIN(2, 14),	/* DU0_DG6 */
3410 		[28] = RCAR_GP_PIN(2, 13),	/* DU0_DG5 */
3411 		[29] = RCAR_GP_PIN(2, 12),	/* DU0_DG4 */
3412 		[30] = RCAR_GP_PIN(2, 11),	/* DU0_DG3 */
3413 		[31] = RCAR_GP_PIN(2, 10),	/* DU0_DG2 */
3414 	} },
3415 	{ PINMUX_BIAS_REG("PUPR3", 0xe606010c, "N/A", 0) {
3416 		[ 0] = RCAR_GP_PIN(4, 21),	/* SD2_WP */
3417 		[ 1] = RCAR_GP_PIN(4, 20),	/* SD2_CD */
3418 		[ 2] = RCAR_GP_PIN(4, 19),	/* SD2_DAT3 */
3419 		[ 3] = RCAR_GP_PIN(4, 18),	/* SD2_DAT2 */
3420 		[ 4] = RCAR_GP_PIN(4, 17),	/* SD2_DAT1 */
3421 		[ 5] = RCAR_GP_PIN(4, 16),	/* SD2_DAT0 */
3422 		[ 6] = RCAR_GP_PIN(4, 15),	/* SD2_CMD */
3423 		[ 7] = RCAR_GP_PIN(4, 14),	/* SD2_CLK */
3424 		[ 8] = RCAR_GP_PIN(4, 13),	/* HRTS1#_A */
3425 		[ 9] = RCAR_GP_PIN(4, 12),	/* HCTS1#_A */
3426 		[10] = RCAR_GP_PIN(4, 11),	/* HTX1_A */
3427 		[11] = RCAR_GP_PIN(4, 10),	/* HRX1_A */
3428 		[12] = RCAR_GP_PIN(4, 9),	/* MSIOF0_SS2_A */
3429 		[13] = RCAR_GP_PIN(4, 8),	/* MSIOF0_SS1_A */
3430 		[14] = RCAR_GP_PIN(4, 7),	/* MSIOF0_SYNC_A */
3431 		[15] = RCAR_GP_PIN(4, 6),	/* MSIOF0_SCK_A */
3432 		[16] = RCAR_GP_PIN(4, 5),	/* MSIOF0_TXD_A */
3433 		[17] = RCAR_GP_PIN(4, 4),	/* MSIOF0_RXD_A */
3434 		[18] = RCAR_GP_PIN(4, 3),	/* SDA1_A */
3435 		[19] = RCAR_GP_PIN(4, 2),	/* SCL1_A */
3436 		[20] = RCAR_GP_PIN(4, 1),	/* SDA0_A */
3437 		[21] = RCAR_GP_PIN(4, 0),	/* SCL0_A */
3438 		[22] = RCAR_GP_PIN(3, 29),	/* AVB_TXD5 */
3439 		[23] = RCAR_GP_PIN(3, 28),	/* AVB_TXD4 */
3440 		[24] = RCAR_GP_PIN(3, 27),	/* AVB_TXD3 */
3441 		[25] = RCAR_GP_PIN(3, 16),	/* VI1_DATA11 */
3442 		[26] = RCAR_GP_PIN(3, 15),	/* VI1_DATA10 */
3443 		[27] = RCAR_GP_PIN(3, 14),	/* VI1_DATA9 */
3444 		[28] = RCAR_GP_PIN(3, 13),	/* VI1_DATA8 */
3445 		[29] = RCAR_GP_PIN(3, 12),	/* VI1_VSYNC# */
3446 		[30] = RCAR_GP_PIN(3, 11),	/* VI1_HSYNC# */
3447 		[31] = RCAR_GP_PIN(3, 10),	/* VI1_FIELD */
3448 	} },
3449 	{ PINMUX_BIAS_REG("PUPR4", 0xe6060110, "N/A", 0) {
3450 		[ 0] = RCAR_GP_PIN(5, 27),	/* SSI_SDATA9_A */
3451 		[ 1] = RCAR_GP_PIN(5, 26),	/* SSI_WS9_A */
3452 		[ 2] = RCAR_GP_PIN(5, 25),	/* SSI_SCK9_A */
3453 		[ 3] = RCAR_GP_PIN(5, 24),	/* SSI_SDATA2_A */
3454 		[ 4] = RCAR_GP_PIN(5, 23),	/* SSI_WS2_A */
3455 		[ 5] = RCAR_GP_PIN(5, 22),	/* SSI_SCK2_A */
3456 		[ 6] = RCAR_GP_PIN(5, 21),	/* SSI_SDATA1_A */
3457 		[ 7] = RCAR_GP_PIN(5, 20),	/* SSI_WS1_A */
3458 		[ 8] = RCAR_GP_PIN(5, 19),	/* SSI_SDATA8_A */
3459 		[ 9] = RCAR_GP_PIN(5, 18),	/* SSI_SCK1_A */
3460 		[10] = RCAR_GP_PIN(5, 17),	/* SSI_SDATA4_A */
3461 		[11] = RCAR_GP_PIN(5, 16),	/* SSI_WS4_A */
3462 		[12] = RCAR_GP_PIN(5, 15),	/* SSI_SCK4_A */
3463 		[13] = RCAR_GP_PIN(5, 14),	/* SSI_SDATA3 */
3464 		[14] = RCAR_GP_PIN(5, 13),	/* SSI_WS34 */
3465 		[15] = RCAR_GP_PIN(5, 12),	/* SSI_SCK34 */
3466 		[16] = RCAR_GP_PIN(5, 11),	/* SSI_SDATA0_A */
3467 		[17] = RCAR_GP_PIN(5, 10),	/* SSI_WS0129_A */
3468 		[18] = RCAR_GP_PIN(5, 9),	/* SSI_SCK0129_A */
3469 		[19] = RCAR_GP_PIN(5, 8),	/* SSI_SDATA7_A */
3470 		[20] = RCAR_GP_PIN(5, 7),	/* SSI_WS78_A */
3471 		[21] = RCAR_GP_PIN(5, 6),	/* SSI_SCK78_A */
3472 		[22] = RCAR_GP_PIN(5, 5),	/* SSI_SDATA6_A */
3473 		[23] = RCAR_GP_PIN(5, 4),	/* SSI_WS6_A */
3474 		[24] = RCAR_GP_PIN(5, 3),	/* SSI_SCK6_A */
3475 		[25] = RCAR_GP_PIN(5, 2),	/* SSI_SDATA5_A */
3476 		[26] = RCAR_GP_PIN(5, 1),	/* SSI_WS5_A */
3477 		[27] = RCAR_GP_PIN(5, 0),	/* SSI_SCK5_A */
3478 		[28] = RCAR_GP_PIN(4, 25),	/* SDA2_A */
3479 		[29] = RCAR_GP_PIN(4, 24),	/* SCL2_A */
3480 		[30] = RCAR_GP_PIN(4, 23),	/* TX3_A */
3481 		[31] = RCAR_GP_PIN(4, 22),	/* RX3_A */
3482 	} },
3483 	{ PINMUX_BIAS_REG("PUPR5", 0xe6060114, "N/A", 0) {
3484 		[ 0] = SH_PFC_PIN_NONE,
3485 		[ 1] = SH_PFC_PIN_NONE,
3486 		[ 2] = SH_PFC_PIN_NONE,
3487 		[ 3] = SH_PFC_PIN_NONE,
3488 		[ 4] = SH_PFC_PIN_NONE,
3489 		[ 5] = SH_PFC_PIN_NONE,
3490 		[ 6] = SH_PFC_PIN_NONE,
3491 		[ 7] = SH_PFC_PIN_NONE,
3492 		[ 8] = SH_PFC_PIN_NONE,
3493 		[ 9] = SH_PFC_PIN_NONE,
3494 		[10] = SH_PFC_PIN_NONE,
3495 		[11] = SH_PFC_PIN_NONE,
3496 		[12] = SH_PFC_PIN_NONE,
3497 		[13] = SH_PFC_PIN_NONE,
3498 		[14] = SH_PFC_PIN_NONE,
3499 		[15] = SH_PFC_PIN_NONE,
3500 		[16] = SH_PFC_PIN_NONE,
3501 		[17] = SH_PFC_PIN_NONE,
3502 		[18] = SH_PFC_PIN_NONE,
3503 		[19] = SH_PFC_PIN_NONE,
3504 		[20] = SH_PFC_PIN_NONE,
3505 		[21] = SH_PFC_PIN_NONE,
3506 		[22] = SH_PFC_PIN_NONE,
3507 		[23] = SH_PFC_PIN_NONE,
3508 		[24] = SH_PFC_PIN_NONE,
3509 		[25] = SH_PFC_PIN_NONE,
3510 		[26] = SH_PFC_PIN_NONE,
3511 		[27] = SH_PFC_PIN_NONE,
3512 		[28] = RCAR_GP_PIN(5, 31),	/* AUDIO_CLKOUT_A */
3513 		[29] = RCAR_GP_PIN(5, 30),	/* AUDIO_CLKC_A */
3514 		[30] = RCAR_GP_PIN(5, 29),	/* AUDIO_CLKB_A */
3515 		[31] = RCAR_GP_PIN(5, 28),	/* AUDIO_CLKA_A */
3516 	} },
3517 	{ /* sentinel */ }
3518 };
3519 
3520 static const struct sh_pfc_soc_operations r8a77470_pfc_ops = {
3521 	.pin_to_pocctrl = r8a77470_pin_to_pocctrl,
3522 	.get_bias = rcar_pinmux_get_bias,
3523 	.set_bias = rcar_pinmux_set_bias,
3524 };
3525 
3526 #ifdef CONFIG_PINCTRL_PFC_R8A77470
3527 const struct sh_pfc_soc_info r8a77470_pinmux_info = {
3528 	.name = "r8a77470_pfc",
3529 	.ops = &r8a77470_pfc_ops,
3530 	.unlock_reg = 0xe6060000, /* PMMR */
3531 
3532 	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
3533 
3534 	.pins = pinmux_pins,
3535 	.nr_pins = ARRAY_SIZE(pinmux_pins),
3536 	.groups = pinmux_groups,
3537 	.nr_groups = ARRAY_SIZE(pinmux_groups),
3538 	.functions = pinmux_functions,
3539 	.nr_functions = ARRAY_SIZE(pinmux_functions),
3540 
3541 	.cfg_regs = pinmux_config_regs,
3542 	.bias_regs = pinmux_bias_regs,
3543 
3544 	.pinmux_data = pinmux_data,
3545 	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
3546 };
3547 #endif
3548