1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Pin Function Controller Support
4  *
5  * Copyright (C) 2015 Niklas Söderlund
6  */
7 #include <linux/kernel.h>
8 
9 #include "sh_pfc.h"
10 
11 #define CPU_ALL_PORT(fn, pfx, sfx)					\
12 	PORT_10(0,  fn, pfx, sfx),	PORT_90(0,  fn, pfx, sfx),	\
13 	PORT_10(100, fn, pfx##10, sfx),	PORT_10(110, fn, pfx##11, sfx),	\
14 	PORT_10(120, fn, pfx##12, sfx),	PORT_10(130, fn, pfx##13, sfx),	\
15 	PORT_10(140, fn, pfx##14, sfx), PORT_1(150, fn, pfx##150, sfx), \
16 	PORT_1(151, fn, pfx##151, sfx), PORT_1(152, fn, pfx##152, sfx), \
17 	PORT_1(153, fn, pfx##153, sfx), PORT_1(154, fn, pfx##154, sfx), \
18 	PORT_1(155, fn, pfx##155, sfx), PORT_1(156, fn, pfx##156, sfx), \
19 	PORT_1(157, fn, pfx##157, sfx), PORT_1(158, fn, pfx##158, sfx)
20 
21 #define CPU_ALL_NOGP(fn)		\
22 	PIN_NOGP(LCD3_B2, "B15", fn),	\
23 	PIN_NOGP(LCD3_B3, "C15", fn),	\
24 	PIN_NOGP(LCD3_B4, "D15", fn),	\
25 	PIN_NOGP(LCD3_B5, "B14", fn),	\
26 	PIN_NOGP(LCD3_B6, "C14", fn),	\
27 	PIN_NOGP(LCD3_B7, "D14", fn),	\
28 	PIN_NOGP(LCD3_G2, "B17", fn),	\
29 	PIN_NOGP(LCD3_G3, "C17", fn),	\
30 	PIN_NOGP(LCD3_G4, "D17", fn),	\
31 	PIN_NOGP(LCD3_G5, "B16", fn),	\
32 	PIN_NOGP(LCD3_G6, "C16", fn),	\
33 	PIN_NOGP(LCD3_G7, "D16", fn)
34 
35 enum {
36 	PINMUX_RESERVED = 0,
37 
38 	PINMUX_DATA_BEGIN,
39 	PORT_ALL(DATA),
40 	PINMUX_DATA_END,
41 
42 	PINMUX_FUNCTION_BEGIN,
43 	PORT_ALL(FN),
44 
45 	/* GPSR0 */
46 	FN_LCD3_1_0_PORT18, FN_LCD3_1_0_PORT20, FN_LCD3_1_0_PORT21,
47 	FN_LCD3_1_0_PORT22, FN_LCD3_1_0_PORT23,
48 	FN_JT_SEL, FN_ERR_RST_REQB, FN_REF_CLKO, FN_EXT_CLKI, FN_LCD3_PXCLKB,
49 
50 	/* GPSR1 */
51 	FN_LCD3_9_8_PORT38, FN_LCD3_9_8_PORT39, FN_LCD3_11_10_PORT40,
52 	FN_LCD3_11_10_PORT41, FN_LCD3_11_10_PORT42, FN_LCD3_11_10_PORT43,
53 	FN_IIC_1_0_PORT46, FN_IIC_1_0_PORT47,
54 	FN_LCD3_R0, FN_LCD3_R1, FN_LCD3_R2, FN_LCD3_R3, FN_LCD3_R4, FN_LCD3_R5,
55 	FN_IIC0_SCL, FN_IIC0_SDA, FN_SD_CKI, FN_SDI0_CKO, FN_SDI0_CKI,
56 	FN_SDI0_CMD, FN_SDI0_DATA0, FN_SDI0_DATA1, FN_SDI0_DATA2,
57 	FN_SDI0_DATA3, FN_SDI0_DATA4, FN_SDI0_DATA5, FN_SDI0_DATA6,
58 	FN_SDI0_DATA7, FN_SDI1_CKO, FN_SDI1_CKI, FN_SDI1_CMD,
59 
60 	/* GPSR2 */
61 	FN_AB_1_0_PORT71, FN_AB_1_0_PORT72, FN_AB_1_0_PORT73,
62 	FN_AB_1_0_PORT74, FN_AB_1_0_PORT75, FN_AB_1_0_PORT76,
63 	FN_AB_1_0_PORT77, FN_AB_1_0_PORT78, FN_AB_1_0_PORT79,
64 	FN_AB_1_0_PORT80, FN_AB_1_0_PORT81, FN_AB_1_0_PORT82,
65 	FN_AB_1_0_PORT83, FN_AB_1_0_PORT84, FN_AB_3_2_PORT85,
66 	FN_AB_3_2_PORT86, FN_AB_3_2_PORT87, FN_AB_3_2_PORT88,
67 	FN_AB_5_4_PORT89, FN_AB_5_4_PORT90, FN_AB_7_6_PORT91,
68 	FN_AB_7_6_PORT92, FN_AB_1_0_PORT93, FN_AB_1_0_PORT94,
69 	FN_AB_1_0_PORT95,
70 	FN_SDI1_DATA0, FN_SDI1_DATA1, FN_SDI1_DATA2, FN_SDI1_DATA3,
71 	FN_AB_CLK, FN_AB_CSB0, FN_AB_CSB1,
72 
73 	/* GPSR3 */
74 	FN_AB_13_12_PORT104, FN_AB_13_12_PORT103, FN_AB_11_10_PORT102,
75 	FN_AB_11_10_PORT101, FN_AB_11_10_PORT100, FN_AB_9_8_PORT99,
76 	FN_AB_9_8_PORT98, FN_AB_9_8_PORT97,
77 	FN_USI_1_0_PORT109, FN_USI_1_0_PORT110, FN_USI_1_0_PORT111,
78 	FN_USI_1_0_PORT112, FN_USI_3_2_PORT113, FN_USI_3_2_PORT114,
79 	FN_USI_5_4_PORT115, FN_USI_5_4_PORT116, FN_USI_5_4_PORT117,
80 	FN_USI_5_4_PORT118, FN_USI_7_6_PORT119, FN_USI_9_8_PORT120,
81 	FN_USI_9_8_PORT121,
82 	FN_AB_A20, FN_USI0_CS1, FN_USI0_CS2, FN_USI1_DI,
83 	FN_USI1_DO,
84 	FN_NTSC_CLK, FN_NTSC_DATA0, FN_NTSC_DATA1, FN_NTSC_DATA2,
85 	FN_NTSC_DATA3, FN_NTSC_DATA4,
86 
87 	/* GPRS4 */
88 	FN_HSI_1_0_PORT143, FN_HSI_1_0_PORT144, FN_HSI_1_0_PORT145,
89 	FN_HSI_1_0_PORT146, FN_HSI_1_0_PORT147, FN_HSI_1_0_PORT148,
90 	FN_HSI_1_0_PORT149, FN_HSI_1_0_PORT150,
91 	FN_UART_1_0_PORT157, FN_UART_1_0_PORT158,
92 	FN_NTSC_DATA5, FN_NTSC_DATA6, FN_NTSC_DATA7, FN_CAM_CLKO,
93 	FN_CAM_CLKI, FN_CAM_VS, FN_CAM_HS, FN_CAM_YUV0,
94 	FN_CAM_YUV1, FN_CAM_YUV2, FN_CAM_YUV3, FN_CAM_YUV4,
95 	FN_CAM_YUV5, FN_CAM_YUV6, FN_CAM_YUV7,
96 	FN_JT_TDO, FN_JT_TDOEN, FN_LOWPWR, FN_USB_VBUS, FN_UART1_RX,
97 	FN_UART1_TX,
98 
99 	/* CHG_PINSEL_LCD3 */
100 	FN_SEL_LCD3_1_0_00, FN_SEL_LCD3_1_0_01,
101 	FN_SEL_LCD3_9_8_00, FN_SEL_LCD3_9_8_10,
102 	FN_SEL_LCD3_11_10_00, FN_SEL_LCD3_11_10_01, FN_SEL_LCD3_11_10_10,
103 
104 	/* CHG_PINSEL_IIC */
105 	FN_SEL_IIC_1_0_00, FN_SEL_IIC_1_0_01,
106 
107 	/* CHG_PINSEL_AB */
108 	FN_SEL_AB_1_0_00, FN_SEL_AB_1_0_10, FN_SEL_AB_3_2_00,
109 	FN_SEL_AB_3_2_01, FN_SEL_AB_3_2_10, FN_SEL_AB_3_2_11,
110 	FN_SEL_AB_5_4_00, FN_SEL_AB_5_4_01, FN_SEL_AB_5_4_10,
111 	FN_SEL_AB_5_4_11, FN_SEL_AB_7_6_00, FN_SEL_AB_7_6_01,
112 	FN_SEL_AB_7_6_10,
113 	FN_SEL_AB_9_8_00, FN_SEL_AB_9_8_01, FN_SEL_AB_9_8_10,
114 	FN_SEL_AB_11_10_00, FN_SEL_AB_11_10_10,
115 	FN_SEL_AB_13_12_00, FN_SEL_AB_13_12_10,
116 
117 	/* CHG_PINSEL_USI */
118 	FN_SEL_USI_1_0_00, FN_SEL_USI_1_0_01,
119 	FN_SEL_USI_3_2_00, FN_SEL_USI_3_2_01,
120 	FN_SEL_USI_5_4_00, FN_SEL_USI_5_4_01,
121 	FN_SEL_USI_7_6_00, FN_SEL_USI_7_6_01,
122 	FN_SEL_USI_9_8_00, FN_SEL_USI_9_8_01,
123 
124 	/* CHG_PINSEL_HSI */
125 	FN_SEL_HSI_1_0_00, FN_SEL_HSI_1_0_01,
126 
127 	/* CHG_PINSEL_UART */
128 	FN_SEL_UART_1_0_00, FN_SEL_UART_1_0_01,
129 
130 	PINMUX_FUNCTION_END,
131 
132 	PINMUX_MARK_BEGIN,
133 
134 	/* GPSR0 */
135 	JT_SEL_MARK, ERR_RST_REQB_MARK, REF_CLKO_MARK, EXT_CLKI_MARK,
136 	LCD3_PXCLKB_MARK, SD_CKI_MARK,
137 
138 	/* GPSR1 */
139 	LCD3_R0_MARK, LCD3_R1_MARK, LCD3_R2_MARK, LCD3_R3_MARK, LCD3_R4_MARK,
140 	LCD3_R5_MARK, IIC0_SCL_MARK, IIC0_SDA_MARK, SDI0_CKO_MARK,
141 	SDI0_CKI_MARK, SDI0_CMD_MARK, SDI0_DATA0_MARK, SDI0_DATA1_MARK,
142 	SDI0_DATA2_MARK, SDI0_DATA3_MARK, SDI0_DATA4_MARK, SDI0_DATA5_MARK,
143 	SDI0_DATA6_MARK, SDI0_DATA7_MARK, SDI1_CKO_MARK, SDI1_CKI_MARK,
144 	SDI1_CMD_MARK,
145 
146 	/* GPSR2 */
147 	SDI1_DATA0_MARK, SDI1_DATA1_MARK, SDI1_DATA2_MARK, SDI1_DATA3_MARK,
148 	AB_CLK_MARK, AB_CSB0_MARK, AB_CSB1_MARK,
149 
150 	/* GPSR3 */
151 	AB_A20_MARK, USI0_CS1_MARK, USI0_CS2_MARK, USI1_DI_MARK,
152 	USI1_DO_MARK,
153 	NTSC_CLK_MARK, NTSC_DATA0_MARK, NTSC_DATA1_MARK, NTSC_DATA2_MARK,
154 	NTSC_DATA3_MARK, NTSC_DATA4_MARK,
155 
156 	/* GPSR3 */
157 	NTSC_DATA5_MARK, NTSC_DATA6_MARK, NTSC_DATA7_MARK, CAM_CLKO_MARK,
158 	CAM_CLKI_MARK, CAM_VS_MARK, CAM_HS_MARK, CAM_YUV0_MARK,
159 	CAM_YUV1_MARK, CAM_YUV2_MARK, CAM_YUV3_MARK, CAM_YUV4_MARK,
160 	CAM_YUV5_MARK, CAM_YUV6_MARK, CAM_YUV7_MARK,
161 	JT_TDO_MARK, JT_TDOEN_MARK, USB_VBUS_MARK, LOWPWR_MARK,
162 	UART1_RX_MARK, UART1_TX_MARK,
163 
164 	/* CHG_PINSEL_LCD3 */
165 	LCD3_PXCLK_MARK, LCD3_CLK_I_MARK, LCD3_HS_MARK, LCD3_VS_MARK,
166 	LCD3_DE_MARK, LCD3_R6_MARK, LCD3_R7_MARK, LCD3_G0_MARK, LCD3_G1_MARK,
167 	LCD3_G2_MARK, LCD3_G3_MARK, LCD3_G4_MARK, LCD3_G5_MARK, LCD3_G6_MARK,
168 	LCD3_G7_MARK, LCD3_B0_MARK, LCD3_B1_MARK, LCD3_B2_MARK, LCD3_B3_MARK,
169 	LCD3_B4_MARK, LCD3_B5_MARK, LCD3_B6_MARK, LCD3_B7_MARK,
170 	YUV3_CLK_O_MARK, YUV3_CLK_I_MARK, YUV3_HS_MARK, YUV3_VS_MARK,
171 	YUV3_DE_MARK, YUV3_D0_MARK, YUV3_D1_MARK, YUV3_D2_MARK, YUV3_D3_MARK,
172 	YUV3_D4_MARK, YUV3_D5_MARK, YUV3_D6_MARK, YUV3_D7_MARK, YUV3_D8_MARK,
173 	YUV3_D9_MARK, YUV3_D10_MARK, YUV3_D11_MARK, YUV3_D12_MARK,
174 	YUV3_D13_MARK, YUV3_D14_MARK, YUV3_D15_MARK,
175 	TP33_CLK_MARK, TP33_CTRL_MARK, TP33_DATA0_MARK, TP33_DATA1_MARK,
176 	TP33_DATA2_MARK, TP33_DATA3_MARK, TP33_DATA4_MARK, TP33_DATA5_MARK,
177 	TP33_DATA6_MARK, TP33_DATA7_MARK, TP33_DATA8_MARK, TP33_DATA9_MARK,
178 	TP33_DATA10_MARK, TP33_DATA11_MARK, TP33_DATA12_MARK, TP33_DATA13_MARK,
179 	TP33_DATA14_MARK, TP33_DATA15_MARK,
180 
181 	/* CHG_PINSEL_IIC */
182 	IIC1_SCL_MARK, IIC1_SDA_MARK, UART3_RX_MARK, UART3_TX_MARK,
183 
184 	/* CHG_PINSEL_AB */
185 	AB_CSB2_MARK, AB_CSB3_MARK, AB_RDB_MARK, AB_WRB_MARK,
186 	AB_WAIT_MARK, AB_ADV_MARK, AB_AD0_MARK, AB_AD1_MARK,
187 	AB_AD2_MARK, AB_AD3_MARK, AB_AD4_MARK, AB_AD5_MARK,
188 	AB_AD6_MARK, AB_AD7_MARK, AB_AD8_MARK, AB_AD9_MARK,
189 	AB_AD10_MARK, AB_AD11_MARK, AB_AD12_MARK, AB_AD13_MARK,
190 	AB_AD14_MARK, AB_AD15_MARK, AB_A17_MARK, AB_A18_MARK,
191 	AB_A19_MARK, AB_A21_MARK, AB_A22_MARK, AB_A23_MARK,
192 	AB_A24_MARK, AB_A25_MARK, AB_A26_MARK, AB_A27_MARK,
193 	AB_A28_MARK, AB_BEN0_MARK, AB_BEN1_MARK,
194 	DTV_BCLK_A_MARK, DTV_PSYNC_A_MARK, DTV_VALID_A_MARK,
195 	DTV_DATA_A_MARK,
196 	SDI2_CKO_MARK, SDI2_CKI_MARK, SDI2_CMD_MARK,
197 	SDI2_DATA0_MARK, SDI2_DATA1_MARK, SDI2_DATA2_MARK,
198 	SDI2_DATA3_MARK,
199 	CF_CSB0_MARK, CF_CSB1_MARK, CF_IORDB_MARK,
200 	CF_IOWRB_MARK, CF_IORDY_MARK, CF_RESET_MARK,
201 	CF_D00_MARK, CF_D01_MARK, CF_D02_MARK, CF_D03_MARK,
202 	CF_D04_MARK, CF_D05_MARK, CF_D06_MARK, CF_D07_MARK,
203 	CF_D08_MARK, CF_D09_MARK, CF_D10_MARK, CF_D11_MARK,
204 	CF_D12_MARK, CF_D13_MARK, CF_D14_MARK, CF_D15_MARK,
205 	CF_A00_MARK, CF_A01_MARK, CF_A02_MARK,
206 	CF_INTRQ_MARK, CF_INPACKB_MARK, CF_CDB1_MARK, CF_CDB2_MARK,
207 	USI5_CLK_A_MARK, USI5_DI_A_MARK, USI5_DO_A_MARK,
208 	USI5_CS0_A_MARK, USI5_CS1_A_MARK, USI5_CS2_A_MARK,
209 
210 	/* CHG_PINSEL_USI */
211 	USI0_CS3_MARK, USI0_CS4_MARK, USI0_CS5_MARK,
212 	USI0_CS6_MARK,
213 	USI2_CLK_MARK, USI2_DI_MARK, USI2_DO_MARK,
214 	USI2_CS0_MARK, USI2_CS1_MARK, USI2_CS2_MARK,
215 	USI3_CLK_MARK, USI3_DI_MARK, USI3_DO_MARK,
216 	USI3_CS0_MARK,
217 	USI4_CLK_MARK, USI4_DI_MARK, USI4_DO_MARK,
218 	USI4_CS0_MARK, USI4_CS1_MARK,
219 	PWM0_MARK, PWM1_MARK,
220 	DTV_BCLK_B_MARK, DTV_PSYNC_B_MARK, DTV_VALID_B_MARK,
221 	DTV_DATA_B_MARK,
222 
223 	/* CHG_PINSEL_HSI */
224 	USI5_CLK_B_MARK, USI5_DO_B_MARK, USI5_CS0_B_MARK, USI5_CS1_B_MARK,
225 	USI5_CS2_B_MARK, USI5_CS3_B_MARK, USI5_CS4_B_MARK, USI5_DI_B_MARK,
226 
227 	/* CHG_PINSEL_UART */
228 	UART1_CTSB_MARK, UART1_RTSB_MARK,
229 	UART2_RX_MARK, UART2_TX_MARK,
230 
231 	PINMUX_MARK_END,
232 };
233 
234 /*
235  * Pins not associated with a GPIO port.
236  */
237 enum {
238 	PORT_ASSIGN_LAST(),
239 	NOGP_ALL(),
240 };
241 
242 /* Expand to a list of sh_pfc_pin entries (named PORT#).
243  * NOTE: No config are recorded since the driver do not handle pinconf. */
244 #define __PIN_CFG(pn, pfx, sfx)  SH_PFC_PIN_CFG(pfx, 0)
245 #define PINMUX_EMEV_GPIO_ALL()	  CPU_ALL_PORT(__PIN_CFG, , unused)
246 
247 static const struct sh_pfc_pin pinmux_pins[] = {
248 	PINMUX_EMEV_GPIO_ALL(),
249 	PINMUX_NOGP_ALL(),
250 };
251 
252 /* Expand to a list of name_DATA, name_FN marks */
253 #define __PORT_DATA(pn, pfx, sfx)  PINMUX_DATA(PORT##pfx##_DATA, PORT##pfx##_FN)
254 #define PINMUX_EMEV_DATA_ALL()	  CPU_ALL_PORT(__PORT_DATA, , unused)
255 
256 static const u16 pinmux_data[] = {
257 	PINMUX_EMEV_DATA_ALL(), /* PINMUX_DATA(PORTN_DATA, PORTN_FN), */
258 
259 	/* GPSR0 */
260 	/* V9 */
261 	PINMUX_SINGLE(JT_SEL),
262 	/* U9 */
263 	PINMUX_SINGLE(ERR_RST_REQB),
264 	/* V8 */
265 	PINMUX_SINGLE(REF_CLKO),
266 	/* U8 */
267 	PINMUX_SINGLE(EXT_CLKI),
268 	/* B22*/
269 	PINMUX_IPSR_NOFN(LCD3_1_0_PORT18, LCD3_PXCLK, SEL_LCD3_1_0_00),
270 	PINMUX_IPSR_NOFN(LCD3_1_0_PORT18, YUV3_CLK_O, SEL_LCD3_1_0_01),
271 	/* C21 */
272 	PINMUX_SINGLE(LCD3_PXCLKB),
273 	/* A21 */
274 	PINMUX_IPSR_NOFN(LCD3_1_0_PORT20, LCD3_CLK_I, SEL_LCD3_1_0_00),
275 	PINMUX_IPSR_NOFN(LCD3_1_0_PORT20, YUV3_CLK_I, SEL_LCD3_1_0_01),
276 	/* B21 */
277 	PINMUX_IPSR_NOFN(LCD3_1_0_PORT21, LCD3_HS, SEL_LCD3_1_0_00),
278 	PINMUX_IPSR_NOFN(LCD3_1_0_PORT21, YUV3_HS, SEL_LCD3_1_0_01),
279 	/* C20 */
280 	PINMUX_IPSR_NOFN(LCD3_1_0_PORT22, LCD3_VS, SEL_LCD3_1_0_00),
281 	PINMUX_IPSR_NOFN(LCD3_1_0_PORT22, YUV3_VS, SEL_LCD3_1_0_01),
282 	/* D19 */
283 	PINMUX_IPSR_NOFN(LCD3_1_0_PORT23, LCD3_DE, SEL_LCD3_1_0_00),
284 	PINMUX_IPSR_NOFN(LCD3_1_0_PORT23, YUV3_DE, SEL_LCD3_1_0_01),
285 
286 	/* GPSR1 */
287 	/* A20 */
288 	PINMUX_SINGLE(LCD3_R0),
289 	/* B20 */
290 	PINMUX_SINGLE(LCD3_R1),
291 	/* A19 */
292 	PINMUX_SINGLE(LCD3_R2),
293 	/* B19 */
294 	PINMUX_SINGLE(LCD3_R3),
295 	/* C19 */
296 	PINMUX_SINGLE(LCD3_R4),
297 	/* B18 */
298 	PINMUX_SINGLE(LCD3_R5),
299 	/* C18 */
300 	PINMUX_IPSR_NOFN(LCD3_9_8_PORT38, LCD3_R6, SEL_LCD3_9_8_00),
301 	PINMUX_IPSR_NOFN(LCD3_9_8_PORT38, TP33_CLK, SEL_LCD3_9_8_10),
302 	/* D18 */
303 	PINMUX_IPSR_NOFN(LCD3_9_8_PORT39, LCD3_R7, SEL_LCD3_9_8_00),
304 	PINMUX_IPSR_NOFN(LCD3_9_8_PORT39, TP33_CTRL, SEL_LCD3_9_8_10),
305 	/* A18 */
306 	PINMUX_IPSR_NOFN(LCD3_11_10_PORT40, LCD3_G0, SEL_LCD3_11_10_00),
307 	PINMUX_IPSR_NOFN(LCD3_11_10_PORT40, YUV3_D0, SEL_LCD3_11_10_01),
308 	PINMUX_IPSR_NOFN(LCD3_11_10_PORT40, TP33_DATA0, SEL_LCD3_11_10_10),
309 	/* A17 */
310 	PINMUX_IPSR_NOFN(LCD3_11_10_PORT41, LCD3_G1, SEL_LCD3_11_10_00),
311 	PINMUX_IPSR_NOFN(LCD3_11_10_PORT41, YUV3_D1, SEL_LCD3_11_10_01),
312 	PINMUX_IPSR_NOFN(LCD3_11_10_PORT41, TP33_DATA1, SEL_LCD3_11_10_10),
313 	/* B17 */
314 	PINMUX_DATA(LCD3_G2_MARK, FN_SEL_LCD3_11_10_00),
315 	PINMUX_DATA(YUV3_D2_MARK, FN_SEL_LCD3_11_10_01),
316 	PINMUX_DATA(TP33_DATA2_MARK, FN_SEL_LCD3_11_10_10),
317 	/* C17 */
318 	PINMUX_DATA(LCD3_G3_MARK, FN_SEL_LCD3_11_10_00),
319 	PINMUX_DATA(YUV3_D3_MARK, FN_SEL_LCD3_11_10_01),
320 	PINMUX_DATA(TP33_DATA3_MARK, FN_SEL_LCD3_11_10_10),
321 	/* D17 */
322 	PINMUX_DATA(LCD3_G4_MARK, FN_SEL_LCD3_11_10_00),
323 	PINMUX_DATA(YUV3_D4_MARK, FN_SEL_LCD3_11_10_01),
324 	PINMUX_DATA(TP33_DATA4_MARK, FN_SEL_LCD3_11_10_10),
325 	/* B16 */
326 	PINMUX_DATA(LCD3_G5_MARK, FN_SEL_LCD3_11_10_00),
327 	PINMUX_DATA(YUV3_D5_MARK, FN_SEL_LCD3_11_10_01),
328 	PINMUX_DATA(TP33_DATA5_MARK, FN_SEL_LCD3_11_10_10),
329 	/* C16 */
330 	PINMUX_DATA(LCD3_G6_MARK, FN_SEL_LCD3_11_10_00),
331 	PINMUX_DATA(YUV3_D6_MARK, FN_SEL_LCD3_11_10_01),
332 	PINMUX_DATA(TP33_DATA6_MARK, FN_SEL_LCD3_11_10_10),
333 	/* D16 */
334 	PINMUX_DATA(LCD3_G7_MARK, FN_SEL_LCD3_11_10_00),
335 	PINMUX_DATA(YUV3_D7_MARK, FN_SEL_LCD3_11_10_01),
336 	PINMUX_DATA(TP33_DATA7_MARK, FN_SEL_LCD3_11_10_10),
337 	/* A16 */
338 	PINMUX_IPSR_NOFN(LCD3_11_10_PORT42, LCD3_B0, SEL_LCD3_11_10_00),
339 	PINMUX_IPSR_NOFN(LCD3_11_10_PORT42, YUV3_D8, SEL_LCD3_11_10_01),
340 	PINMUX_IPSR_NOFN(LCD3_11_10_PORT42, TP33_DATA8, SEL_LCD3_11_10_10),
341 	/* A15 */
342 	PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, LCD3_B1, SEL_LCD3_11_10_00),
343 	PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, YUV3_D9, SEL_LCD3_11_10_01),
344 	PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, TP33_DATA9, SEL_LCD3_11_10_10),
345 	/* B15 */
346 	PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, LCD3_B2, SEL_LCD3_11_10_00),
347 	PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, YUV3_D10, SEL_LCD3_11_10_01),
348 	PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, TP33_DATA10, SEL_LCD3_11_10_10),
349 	/* C15 */
350 	PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, LCD3_B3, SEL_LCD3_11_10_00),
351 	PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, YUV3_D11, SEL_LCD3_11_10_01),
352 	PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, TP33_DATA11, SEL_LCD3_11_10_10),
353 	/* D15 */
354 	PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, LCD3_B4, SEL_LCD3_11_10_00),
355 	PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, YUV3_D12, SEL_LCD3_11_10_01),
356 	PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, TP33_DATA12, SEL_LCD3_11_10_10),
357 	/* B14 */
358 	PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, LCD3_B5, SEL_LCD3_11_10_00),
359 	PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, YUV3_D13, SEL_LCD3_11_10_01),
360 	PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, TP33_DATA13, SEL_LCD3_11_10_10),
361 	/* C14 */
362 	PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, LCD3_B6, SEL_LCD3_11_10_00),
363 	PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, YUV3_D14, SEL_LCD3_11_10_01),
364 	PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, TP33_DATA14, SEL_LCD3_11_10_10),
365 	/* D14 */
366 	PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, LCD3_B7, SEL_LCD3_11_10_00),
367 	PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, YUV3_D15, SEL_LCD3_11_10_01),
368 	PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, TP33_DATA15, SEL_LCD3_11_10_10),
369 	/* AA9 */
370 	PINMUX_SINGLE(IIC0_SCL),
371 	/* AA8 */
372 	PINMUX_SINGLE(IIC0_SDA),
373 	/* Y9 */
374 	PINMUX_IPSR_NOFN(IIC_1_0_PORT46, IIC1_SCL, SEL_IIC_1_0_00),
375 	PINMUX_IPSR_NOFN(IIC_1_0_PORT46, UART3_RX, SEL_IIC_1_0_01),
376 	/* Y8 */
377 	PINMUX_IPSR_NOFN(IIC_1_0_PORT47, IIC1_SDA, SEL_IIC_1_0_00),
378 	PINMUX_IPSR_NOFN(IIC_1_0_PORT47, UART3_TX, SEL_IIC_1_0_01),
379 	/* AC19 */
380 	PINMUX_SINGLE(SD_CKI),
381 	/* AB18 */
382 	PINMUX_SINGLE(SDI0_CKO),
383 	/* AC18 */
384 	PINMUX_SINGLE(SDI0_CKI),
385 	/* Y12 */
386 	PINMUX_SINGLE(SDI0_CMD),
387 	/* AA13 */
388 	PINMUX_SINGLE(SDI0_DATA0),
389 	/* Y13 */
390 	PINMUX_SINGLE(SDI0_DATA1),
391 	/* AA14 */
392 	PINMUX_SINGLE(SDI0_DATA2),
393 	/* Y14 */
394 	PINMUX_SINGLE(SDI0_DATA3),
395 	/* AA15 */
396 	PINMUX_SINGLE(SDI0_DATA4),
397 	/* Y15 */
398 	PINMUX_SINGLE(SDI0_DATA5),
399 	/* AA16 */
400 	PINMUX_SINGLE(SDI0_DATA6),
401 	/* Y16 */
402 	PINMUX_SINGLE(SDI0_DATA7),
403 	/* AB22 */
404 	PINMUX_SINGLE(SDI1_CKO),
405 	/* AA23 */
406 	PINMUX_SINGLE(SDI1_CKI),
407 	/* AC21 */
408 	PINMUX_SINGLE(SDI1_CMD),
409 
410 	/* GPSR2 */
411 	/* AB21 */
412 	PINMUX_SINGLE(SDI1_DATA0),
413 	/* AB20 */
414 	PINMUX_SINGLE(SDI1_DATA1),
415 	/* AB19 */
416 	PINMUX_SINGLE(SDI1_DATA2),
417 	/* AA19 */
418 	PINMUX_SINGLE(SDI1_DATA3),
419 	/* J23 */
420 	PINMUX_SINGLE(AB_CLK),
421 	/* D21 */
422 	PINMUX_SINGLE(AB_CSB0),
423 	/* E21 */
424 	PINMUX_SINGLE(AB_CSB1),
425 	/* F20 */
426 	PINMUX_IPSR_NOFN(AB_1_0_PORT71, AB_CSB2, SEL_AB_1_0_00),
427 	PINMUX_IPSR_NOFN(AB_1_0_PORT71, CF_CSB0, SEL_AB_1_0_10),
428 	/* G20 */
429 	PINMUX_IPSR_NOFN(AB_1_0_PORT72, AB_CSB3, SEL_AB_1_0_00),
430 	PINMUX_IPSR_NOFN(AB_1_0_PORT72, CF_CSB1, SEL_AB_1_0_10),
431 	/* J20 */
432 	PINMUX_IPSR_NOFN(AB_1_0_PORT73, AB_RDB, SEL_AB_1_0_00),
433 	PINMUX_IPSR_NOFN(AB_1_0_PORT73, CF_IORDB, SEL_AB_1_0_10),
434 	/* H20 */
435 	PINMUX_IPSR_NOFN(AB_1_0_PORT74, AB_WRB, SEL_AB_1_0_00),
436 	PINMUX_IPSR_NOFN(AB_1_0_PORT74, CF_IOWRB, SEL_AB_1_0_10),
437 	/* L20 */
438 	PINMUX_IPSR_NOFN(AB_1_0_PORT75, AB_WAIT, SEL_AB_1_0_00),
439 	PINMUX_IPSR_NOFN(AB_1_0_PORT75, CF_IORDY, SEL_AB_1_0_10),
440 	/* K20 */
441 	PINMUX_IPSR_NOFN(AB_1_0_PORT76, AB_ADV, SEL_AB_1_0_00),
442 	PINMUX_IPSR_NOFN(AB_1_0_PORT76, CF_RESET, SEL_AB_1_0_10),
443 	/* C23 */
444 	PINMUX_IPSR_NOFN(AB_1_0_PORT77, AB_AD0, SEL_AB_1_0_00),
445 	PINMUX_IPSR_NOFN(AB_1_0_PORT77, CF_D00, SEL_AB_1_0_10),
446 	/* C22 */
447 	PINMUX_IPSR_NOFN(AB_1_0_PORT78, AB_AD1, SEL_AB_1_0_00),
448 	PINMUX_IPSR_NOFN(AB_1_0_PORT78, CF_D01, SEL_AB_1_0_10),
449 	/* D23 */
450 	PINMUX_IPSR_NOFN(AB_1_0_PORT79, AB_AD2, SEL_AB_1_0_00),
451 	PINMUX_IPSR_NOFN(AB_1_0_PORT79, CF_D02, SEL_AB_1_0_10),
452 	/* D22 */
453 	PINMUX_IPSR_NOFN(AB_1_0_PORT80, AB_AD3, SEL_AB_1_0_00),
454 	PINMUX_IPSR_NOFN(AB_1_0_PORT80, CF_D03, SEL_AB_1_0_10),
455 	/* E23 */
456 	PINMUX_IPSR_NOFN(AB_1_0_PORT81, AB_AD4, SEL_AB_1_0_00),
457 	PINMUX_IPSR_NOFN(AB_1_0_PORT81, CF_D04, SEL_AB_1_0_10),
458 	/* E22 */
459 	PINMUX_IPSR_NOFN(AB_1_0_PORT82, AB_AD5, SEL_AB_1_0_00),
460 	PINMUX_IPSR_NOFN(AB_1_0_PORT82, CF_D05, SEL_AB_1_0_10),
461 	/* F23 */
462 	PINMUX_IPSR_NOFN(AB_1_0_PORT83, AB_AD6, SEL_AB_1_0_00),
463 	PINMUX_IPSR_NOFN(AB_1_0_PORT83, CF_D06, SEL_AB_1_0_10),
464 	/* F22 */
465 	PINMUX_IPSR_NOFN(AB_1_0_PORT84, AB_AD7, SEL_AB_1_0_00),
466 	PINMUX_IPSR_NOFN(AB_1_0_PORT84, CF_D07, SEL_AB_1_0_10),
467 	/* F21 */
468 	PINMUX_IPSR_NOFN(AB_3_2_PORT85, AB_AD8, SEL_AB_3_2_00),
469 	PINMUX_IPSR_NOFN(AB_3_2_PORT85, DTV_BCLK_A, SEL_AB_3_2_01),
470 	PINMUX_IPSR_NOFN(AB_3_2_PORT85, CF_D08, SEL_AB_3_2_10),
471 	PINMUX_IPSR_NOFN(AB_3_2_PORT85, USI5_CLK_A, SEL_AB_3_2_11),
472 	/* G23 */
473 	PINMUX_IPSR_NOFN(AB_3_2_PORT86, AB_AD9, SEL_AB_3_2_00),
474 	PINMUX_IPSR_NOFN(AB_3_2_PORT86, DTV_PSYNC_A, SEL_AB_3_2_01),
475 	PINMUX_IPSR_NOFN(AB_3_2_PORT86, CF_D09, SEL_AB_3_2_10),
476 	PINMUX_IPSR_NOFN(AB_3_2_PORT86, USI5_DI_A, SEL_AB_3_2_11),
477 	/* G22 */
478 	PINMUX_IPSR_NOFN(AB_3_2_PORT87, AB_AD10, SEL_AB_3_2_00),
479 	PINMUX_IPSR_NOFN(AB_3_2_PORT87, DTV_VALID_A, SEL_AB_3_2_01),
480 	PINMUX_IPSR_NOFN(AB_3_2_PORT87, CF_D10, SEL_AB_3_2_10),
481 	PINMUX_IPSR_NOFN(AB_3_2_PORT87, USI5_DO_A, SEL_AB_3_2_11),
482 	/* G21 */
483 	PINMUX_IPSR_NOFN(AB_3_2_PORT88, AB_AD11, SEL_AB_3_2_00),
484 	PINMUX_IPSR_NOFN(AB_3_2_PORT88, DTV_DATA_A, SEL_AB_3_2_01),
485 	PINMUX_IPSR_NOFN(AB_3_2_PORT88, CF_D11, SEL_AB_3_2_10),
486 	PINMUX_IPSR_NOFN(AB_3_2_PORT88, USI5_CS0_A, SEL_AB_3_2_11),
487 	/* H23 */
488 	PINMUX_IPSR_NOFN(AB_5_4_PORT89, AB_AD12, SEL_AB_5_4_00),
489 	PINMUX_IPSR_NOFN(AB_5_4_PORT89, SDI2_DATA0, SEL_AB_5_4_01),
490 	PINMUX_IPSR_NOFN(AB_5_4_PORT89, CF_D12, SEL_AB_5_4_10),
491 	PINMUX_IPSR_NOFN(AB_5_4_PORT89, USI5_CS1_A, SEL_AB_5_4_11),
492 	/* H22 */
493 	PINMUX_IPSR_NOFN(AB_5_4_PORT90, AB_AD13, SEL_AB_5_4_00),
494 	PINMUX_IPSR_NOFN(AB_5_4_PORT90, SDI2_DATA1, SEL_AB_5_4_01),
495 	PINMUX_IPSR_NOFN(AB_5_4_PORT90, CF_D13, SEL_AB_5_4_10),
496 	PINMUX_IPSR_NOFN(AB_5_4_PORT90, USI5_CS2_A, SEL_AB_5_4_11),
497 	/* H21 */
498 	PINMUX_IPSR_NOFN(AB_7_6_PORT91, AB_AD14, SEL_AB_7_6_00),
499 	PINMUX_IPSR_NOFN(AB_7_6_PORT91, SDI2_DATA2, SEL_AB_7_6_01),
500 	PINMUX_IPSR_NOFN(AB_7_6_PORT91, CF_D14, SEL_AB_7_6_10),
501 	/* J22 */
502 	PINMUX_IPSR_NOFN(AB_7_6_PORT92, AB_AD15, SEL_AB_7_6_00),
503 	PINMUX_IPSR_NOFN(AB_7_6_PORT92, SDI2_DATA3, SEL_AB_7_6_01),
504 	PINMUX_IPSR_NOFN(AB_7_6_PORT92, CF_D15, SEL_AB_7_6_10),
505 	/* J21 */
506 	PINMUX_IPSR_NOFN(AB_1_0_PORT93, AB_A17, SEL_AB_1_0_00),
507 	PINMUX_IPSR_NOFN(AB_1_0_PORT93, CF_A00, SEL_AB_1_0_10),
508 	/* K21 */
509 	PINMUX_IPSR_NOFN(AB_1_0_PORT94, AB_A18, SEL_AB_1_0_00),
510 	PINMUX_IPSR_NOFN(AB_1_0_PORT94, CF_A01, SEL_AB_1_0_10),
511 	/* L21 */
512 	PINMUX_IPSR_NOFN(AB_1_0_PORT95, AB_A19, SEL_AB_1_0_00),
513 	PINMUX_IPSR_NOFN(AB_1_0_PORT95, CF_A02, SEL_AB_1_0_10),
514 
515 	/* GPSR3 */
516 	/* M21 */
517 	PINMUX_SINGLE(AB_A20),
518 	/* N21 */
519 	PINMUX_IPSR_NOFN(AB_9_8_PORT97, AB_A21, SEL_AB_9_8_00),
520 	PINMUX_IPSR_NOFN(AB_9_8_PORT97, SDI2_CKO, SEL_AB_9_8_01),
521 	PINMUX_IPSR_NOFN(AB_9_8_PORT97, CF_INTRQ, SEL_AB_9_8_10),
522 	/* M20 */
523 	PINMUX_IPSR_NOFN(AB_9_8_PORT98, AB_A22, SEL_AB_9_8_00),
524 	PINMUX_IPSR_NOFN(AB_9_8_PORT98, SDI2_CKI, SEL_AB_9_8_01),
525 	/* N20 */
526 	PINMUX_IPSR_NOFN(AB_9_8_PORT99, AB_A23, SEL_AB_9_8_00),
527 	PINMUX_IPSR_NOFN(AB_9_8_PORT99, SDI2_CMD, SEL_AB_9_8_01),
528 	/* L18 */
529 	PINMUX_IPSR_NOFN(AB_11_10_PORT100, AB_A24, SEL_AB_11_10_00),
530 	PINMUX_IPSR_NOFN(AB_11_10_PORT100, CF_INPACKB, SEL_AB_11_10_10),
531 	/* M18 */
532 	PINMUX_IPSR_NOFN(AB_11_10_PORT101, AB_A25, SEL_AB_11_10_00),
533 	PINMUX_IPSR_NOFN(AB_11_10_PORT101, CF_CDB1, SEL_AB_11_10_10),
534 	/* N18 */
535 	PINMUX_IPSR_NOFN(AB_11_10_PORT102, AB_A26, SEL_AB_11_10_00),
536 	PINMUX_IPSR_NOFN(AB_11_10_PORT102, CF_CDB2, SEL_AB_11_10_10),
537 	/* L17 */
538 	PINMUX_IPSR_NOFN(AB_13_12_PORT103, AB_A27, SEL_AB_13_12_00),
539 	PINMUX_IPSR_NOFN(AB_13_12_PORT103, AB_BEN0, SEL_AB_13_12_10),
540 	/* M17 */
541 	PINMUX_IPSR_NOFN(AB_13_12_PORT104, AB_A28, SEL_AB_13_12_00),
542 	PINMUX_IPSR_NOFN(AB_13_12_PORT104, AB_BEN1, SEL_AB_13_12_10),
543 	/* B8 */
544 	PINMUX_SINGLE(USI0_CS1),
545 	/* B9 */
546 	PINMUX_SINGLE(USI0_CS2),
547 	/* C10 */
548 	PINMUX_SINGLE(USI1_DI),
549 	/* D10 */
550 	PINMUX_SINGLE(USI1_DO),
551 	/* AB5 */
552 	PINMUX_IPSR_NOFN(USI_1_0_PORT109, USI2_CLK, SEL_USI_1_0_00),
553 	PINMUX_IPSR_NOFN(USI_1_0_PORT109, DTV_BCLK_B, SEL_USI_1_0_01),
554 	/* AA6 */
555 	PINMUX_IPSR_NOFN(USI_1_0_PORT110, USI2_DI, SEL_USI_1_0_00),
556 	PINMUX_IPSR_NOFN(USI_1_0_PORT110, DTV_PSYNC_B, SEL_USI_1_0_01),
557 	/* AA5 */
558 	PINMUX_IPSR_NOFN(USI_1_0_PORT111, USI2_DO, SEL_USI_1_0_00),
559 	PINMUX_IPSR_NOFN(USI_1_0_PORT111, DTV_VALID_B, SEL_USI_1_0_01),
560 	/* Y7 */
561 	PINMUX_IPSR_NOFN(USI_1_0_PORT112, USI2_CS0, SEL_USI_1_0_00),
562 	PINMUX_IPSR_NOFN(USI_1_0_PORT112, DTV_DATA_B, SEL_USI_1_0_01),
563 	/* AA7 */
564 	PINMUX_IPSR_NOFN(USI_3_2_PORT113, USI2_CS1, SEL_USI_3_2_00),
565 	PINMUX_IPSR_NOFN(USI_3_2_PORT113, USI4_CS0, SEL_USI_3_2_01),
566 	/* Y6 */
567 	PINMUX_IPSR_NOFN(USI_3_2_PORT114, USI2_CS2, SEL_USI_3_2_00),
568 	PINMUX_IPSR_NOFN(USI_3_2_PORT114, USI4_CS1, SEL_USI_3_2_01),
569 	/* AC5 */
570 	PINMUX_IPSR_NOFN(USI_5_4_PORT115, USI3_CLK, SEL_USI_5_4_00),
571 	PINMUX_IPSR_NOFN(USI_5_4_PORT115, USI0_CS3, SEL_USI_5_4_01),
572 	/* AC4 */
573 	PINMUX_IPSR_NOFN(USI_5_4_PORT116, USI3_DI, SEL_USI_5_4_00),
574 	PINMUX_IPSR_NOFN(USI_5_4_PORT116, USI0_CS4, SEL_USI_5_4_01),
575 	/* AC3 */
576 	PINMUX_IPSR_NOFN(USI_5_4_PORT117, USI3_DO, SEL_USI_5_4_00),
577 	PINMUX_IPSR_NOFN(USI_5_4_PORT117, USI0_CS5, SEL_USI_5_4_01),
578 	/* AB4 */
579 	PINMUX_IPSR_NOFN(USI_5_4_PORT118, USI3_CS0, SEL_USI_5_4_00),
580 	PINMUX_IPSR_NOFN(USI_5_4_PORT118, USI0_CS6, SEL_USI_5_4_01),
581 	/* AB3 */
582 	PINMUX_IPSR_NOFN(USI_7_6_PORT119, USI4_CLK, SEL_USI_7_6_01),
583 	/* AA4 */
584 	PINMUX_IPSR_NOFN(USI_9_8_PORT120, PWM0, SEL_USI_9_8_00),
585 	PINMUX_IPSR_NOFN(USI_9_8_PORT120, USI4_DI, SEL_USI_9_8_01),
586 	/* Y5 */
587 	PINMUX_IPSR_NOFN(USI_9_8_PORT121, PWM1, SEL_USI_9_8_00),
588 	PINMUX_IPSR_NOFN(USI_9_8_PORT121, USI4_DO, SEL_USI_9_8_01),
589 	/* V20 */
590 	PINMUX_SINGLE(NTSC_CLK),
591 	/* P20 */
592 	PINMUX_SINGLE(NTSC_DATA0),
593 	/* P18 */
594 	PINMUX_SINGLE(NTSC_DATA1),
595 	/* R20 */
596 	PINMUX_SINGLE(NTSC_DATA2),
597 	/* R18 */
598 	PINMUX_SINGLE(NTSC_DATA3),
599 	/* T20 */
600 	PINMUX_SINGLE(NTSC_DATA4),
601 
602 	/* GPRS3 */
603 	/* T18 */
604 	PINMUX_SINGLE(NTSC_DATA5),
605 	/* U20 */
606 	PINMUX_SINGLE(NTSC_DATA6),
607 	/* U18 */
608 	PINMUX_SINGLE(NTSC_DATA7),
609 	/* W23 */
610 	PINMUX_SINGLE(CAM_CLKO),
611 	/* Y23 */
612 	PINMUX_SINGLE(CAM_CLKI),
613 	/* W22 */
614 	PINMUX_SINGLE(CAM_VS),
615 	/* V21 */
616 	PINMUX_SINGLE(CAM_HS),
617 	/* T21 */
618 	PINMUX_SINGLE(CAM_YUV0),
619 	/* T22 */
620 	PINMUX_SINGLE(CAM_YUV1),
621 	/* T23 */
622 	PINMUX_SINGLE(CAM_YUV2),
623 	/* U21 */
624 	PINMUX_SINGLE(CAM_YUV3),
625 	/* U22 */
626 	PINMUX_SINGLE(CAM_YUV4),
627 	/* U23 */
628 	PINMUX_SINGLE(CAM_YUV5),
629 	/* V22 */
630 	PINMUX_SINGLE(CAM_YUV6),
631 	/* V23 */
632 	PINMUX_SINGLE(CAM_YUV7),
633 	/* K22 */
634 	PINMUX_IPSR_NOFN(HSI_1_0_PORT143, USI5_CLK_B, SEL_HSI_1_0_01),
635 	/* K23 */
636 	PINMUX_IPSR_NOFN(HSI_1_0_PORT144, USI5_DO_B, SEL_HSI_1_0_01),
637 	/* L23 */
638 	PINMUX_IPSR_NOFN(HSI_1_0_PORT145, USI5_CS0_B, SEL_HSI_1_0_01),
639 	/* L22 */
640 	PINMUX_IPSR_NOFN(HSI_1_0_PORT146, USI5_CS1_B, SEL_HSI_1_0_01),
641 	/* N22 */
642 	PINMUX_IPSR_NOFN(HSI_1_0_PORT147, USI5_CS2_B, SEL_HSI_1_0_01),
643 	/* N23 */
644 	PINMUX_IPSR_NOFN(HSI_1_0_PORT148, USI5_CS3_B, SEL_HSI_1_0_01),
645 	/* M23 */
646 	PINMUX_IPSR_NOFN(HSI_1_0_PORT149, USI5_CS4_B, SEL_HSI_1_0_01),
647 	/* M22 */
648 	PINMUX_IPSR_NOFN(HSI_1_0_PORT150, USI5_DI_B, SEL_HSI_1_0_01),
649 	/* D13 */
650 	PINMUX_SINGLE(JT_TDO),
651 	/* F13 */
652 	PINMUX_SINGLE(JT_TDOEN),
653 	/* AA12 */
654 	PINMUX_SINGLE(USB_VBUS),
655 	/* A12 */
656 	PINMUX_SINGLE(LOWPWR),
657 	/* Y11 */
658 	PINMUX_SINGLE(UART1_RX),
659 	/* Y10 */
660 	PINMUX_SINGLE(UART1_TX),
661 	/* AA10 */
662 	PINMUX_IPSR_NOFN(UART_1_0_PORT157, UART1_CTSB, SEL_UART_1_0_00),
663 	PINMUX_IPSR_NOFN(UART_1_0_PORT157, UART2_RX, SEL_UART_1_0_01),
664 	/* AB10 */
665 	PINMUX_IPSR_NOFN(UART_1_0_PORT158, UART1_RTSB, SEL_UART_1_0_00),
666 	PINMUX_IPSR_NOFN(UART_1_0_PORT158, UART2_TX, SEL_UART_1_0_01),
667 };
668 
669 
670 #define EMEV_MUX_PIN(name, pin, mark) \
671 	static const unsigned int name##_pins[] = { pin }; \
672 	static const unsigned int name##_mux[] = { mark##_MARK }
673 
674 /* = [ System ] =========== */
675 EMEV_MUX_PIN(err_rst_reqb, 3, ERR_RST_REQB);
676 EMEV_MUX_PIN(ref_clko, 4, REF_CLKO);
677 EMEV_MUX_PIN(ext_clki, 5, EXT_CLKI);
678 EMEV_MUX_PIN(lowpwr, 154, LOWPWR);
679 
680 /* = [ External Memory] === */
681 static const unsigned int ab_main_pins[] = {
682 	/* AB_RDB, AB_WRB */
683 	73, 74,
684 	/* AB_AD[0:15] */
685 	77, 78, 79, 80,
686 	81, 82, 83, 84,
687 	85, 86, 87, 88,
688 	89, 90, 91, 92,
689 };
690 static const unsigned int ab_main_mux[] = {
691 	AB_RDB_MARK, AB_WRB_MARK,
692 	AB_AD0_MARK, AB_AD1_MARK, AB_AD2_MARK, AB_AD3_MARK,
693 	AB_AD4_MARK, AB_AD5_MARK, AB_AD6_MARK, AB_AD7_MARK,
694 	AB_AD8_MARK, AB_AD9_MARK, AB_AD10_MARK, AB_AD11_MARK,
695 	AB_AD12_MARK, AB_AD13_MARK, AB_AD14_MARK, AB_AD15_MARK,
696 };
697 
698 EMEV_MUX_PIN(ab_clk, 68, AB_CLK);
699 EMEV_MUX_PIN(ab_csb0, 69, AB_CSB0);
700 EMEV_MUX_PIN(ab_csb1, 70, AB_CSB1);
701 EMEV_MUX_PIN(ab_csb2, 71, AB_CSB2);
702 EMEV_MUX_PIN(ab_csb3, 72, AB_CSB3);
703 EMEV_MUX_PIN(ab_wait, 75, AB_WAIT);
704 EMEV_MUX_PIN(ab_adv, 76, AB_ADV);
705 EMEV_MUX_PIN(ab_a17, 93, AB_A17);
706 EMEV_MUX_PIN(ab_a18, 94, AB_A18);
707 EMEV_MUX_PIN(ab_a19, 95, AB_A19);
708 EMEV_MUX_PIN(ab_a20, 96, AB_A20);
709 EMEV_MUX_PIN(ab_a21, 97, AB_A21);
710 EMEV_MUX_PIN(ab_a22, 98, AB_A22);
711 EMEV_MUX_PIN(ab_a23, 99, AB_A23);
712 EMEV_MUX_PIN(ab_a24, 100, AB_A24);
713 EMEV_MUX_PIN(ab_a25, 101, AB_A25);
714 EMEV_MUX_PIN(ab_a26, 102, AB_A26);
715 EMEV_MUX_PIN(ab_a27, 103, AB_A27);
716 EMEV_MUX_PIN(ab_a28, 104, AB_A28);
717 EMEV_MUX_PIN(ab_ben0, 103, AB_BEN0);
718 EMEV_MUX_PIN(ab_ben1, 104, AB_BEN1);
719 
720 /* = [ CAM ] ============== */
721 EMEV_MUX_PIN(cam_clko, 131, CAM_CLKO);
722 static const unsigned int cam_pins[] = {
723 	/* CLKI, VS, HS */
724 	132, 133, 134,
725 	/* CAM_YUV[0:7] */
726 	135, 136, 137, 138,
727 	139, 140, 141, 142,
728 };
729 static const unsigned int cam_mux[] = {
730 	CAM_CLKI_MARK, CAM_VS_MARK, CAM_HS_MARK,
731 	CAM_YUV0_MARK, CAM_YUV1_MARK, CAM_YUV2_MARK, CAM_YUV3_MARK,
732 	CAM_YUV4_MARK, CAM_YUV5_MARK, CAM_YUV6_MARK, CAM_YUV7_MARK,
733 };
734 
735 /* = [ CF ] -============== */
736 static const unsigned int cf_ctrl_pins[] = {
737 	/* CSB0, CSB1, IORDB, IOWRB, IORDY, RESET,
738 	 * A00, A01, A02, INTRQ, INPACKB, CDB1, CDB2 */
739 	71, 72, 73, 74,
740 	75, 76, 93, 94,
741 	95, 97, 100, 101,
742 	102,
743 };
744 static const unsigned int cf_ctrl_mux[] = {
745 	CF_CSB0_MARK, CF_CSB1_MARK, CF_IORDB_MARK, CF_IOWRB_MARK,
746 	CF_IORDY_MARK, CF_RESET_MARK, CF_A00_MARK, CF_A01_MARK,
747 	CF_A02_MARK, CF_INTRQ_MARK, CF_INPACKB_MARK, CF_CDB1_MARK,
748 	CF_CDB2_MARK,
749 };
750 
751 static const unsigned int cf_data_pins[] = {
752 	/* CF_D[0:15] */
753 	77, 78, 79, 80,
754 	81, 82, 83, 84,
755 	85, 86, 87, 88,
756 	89, 90, 91, 92,
757 };
758 static const unsigned int cf_data_mux[] = {
759 	CF_D00_MARK, CF_D01_MARK, CF_D02_MARK, CF_D03_MARK,
760 	CF_D04_MARK, CF_D05_MARK, CF_D06_MARK, CF_D07_MARK,
761 	CF_D08_MARK, CF_D09_MARK, CF_D10_MARK, CF_D11_MARK,
762 	CF_D12_MARK, CF_D13_MARK, CF_D14_MARK, CF_D15_MARK,
763 };
764 
765 /* = [ DTV ] ============== */
766 static const unsigned int dtv_a_pins[] = {
767 	/* BCLK, PSYNC, VALID, DATA */
768 	85, 86, 87, 88,
769 };
770 static const unsigned int dtv_a_mux[] = {
771 	DTV_BCLK_A_MARK, DTV_PSYNC_A_MARK, DTV_VALID_A_MARK, DTV_DATA_A_MARK,
772 };
773 
774 static const unsigned int dtv_b_pins[] = {
775 	/* BCLK, PSYNC, VALID, DATA */
776 	109, 110, 111, 112,
777 };
778 static const unsigned int dtv_b_mux[] = {
779 	DTV_BCLK_B_MARK, DTV_PSYNC_B_MARK, DTV_VALID_B_MARK, DTV_DATA_B_MARK,
780 };
781 
782 /* = [ IIC0 ] ============= */
783 static const unsigned int iic0_pins[] = {
784 	/* SCL, SDA */
785 	44, 45,
786 };
787 static const unsigned int iic0_mux[] = {
788 	IIC0_SCL_MARK, IIC0_SDA_MARK,
789 };
790 
791 /* = [ IIC1 ] ============= */
792 static const unsigned int iic1_pins[] = {
793 	/* SCL, SDA */
794 	46, 47,
795 };
796 static const unsigned int iic1_mux[] = {
797 	IIC1_SCL_MARK, IIC1_SDA_MARK,
798 };
799 
800 /* = [ JTAG ] ============= */
801 static const unsigned int jtag_pins[] = {
802 	/* SEL, TDO, TDOEN */
803 	2, 151, 152,
804 };
805 static const unsigned int jtag_mux[] = {
806 	JT_SEL_MARK, JT_TDO_MARK, JT_TDOEN_MARK,
807 };
808 
809 /* = [ LCD/YUV ] ========== */
810 EMEV_MUX_PIN(lcd3_pxclk, 18, LCD3_PXCLK);
811 EMEV_MUX_PIN(lcd3_pxclkb, 19, LCD3_PXCLKB);
812 EMEV_MUX_PIN(lcd3_clk_i, 20, LCD3_CLK_I);
813 
814 static const unsigned int lcd3_sync_pins[] = {
815 	/* HS, VS, DE */
816 	21, 22, 23,
817 };
818 static const unsigned int lcd3_sync_mux[] = {
819 	LCD3_HS_MARK, LCD3_VS_MARK, LCD3_DE_MARK,
820 };
821 
822 static const unsigned int lcd3_rgb888_pins[] = {
823 	/* R[0:7], G[0:7], B[0:7] */
824 	32, 33, 34, 35,
825 	36, 37, 38, 39,
826 	40, 41, PIN_LCD3_G2, PIN_LCD3_G3,
827 	PIN_LCD3_G4, PIN_LCD3_G5, PIN_LCD3_G6, PIN_LCD3_G7,
828 	42, 43, PIN_LCD3_B2, PIN_LCD3_B3,
829 	PIN_LCD3_B4, PIN_LCD3_B5, PIN_LCD3_B6, PIN_LCD3_B7
830 };
831 static const unsigned int lcd3_rgb888_mux[] = {
832 	LCD3_R0_MARK, LCD3_R1_MARK, LCD3_R2_MARK, LCD3_R3_MARK,
833 	LCD3_R4_MARK, LCD3_R5_MARK, LCD3_R6_MARK, LCD3_R7_MARK,
834 	LCD3_G0_MARK, LCD3_G1_MARK, LCD3_G2_MARK, LCD3_G3_MARK,
835 	LCD3_G4_MARK, LCD3_G5_MARK, LCD3_G6_MARK, LCD3_G7_MARK,
836 	LCD3_B0_MARK, LCD3_B1_MARK, LCD3_B2_MARK, LCD3_B3_MARK,
837 	LCD3_B4_MARK, LCD3_B5_MARK, LCD3_B6_MARK, LCD3_B7_MARK,
838 };
839 
840 EMEV_MUX_PIN(yuv3_clk_i, 20, YUV3_CLK_I);
841 static const unsigned int yuv3_pins[] = {
842 	/* CLK_O, HS, VS, DE */
843 	18, 21, 22, 23,
844 	/* YUV3_D[0:15] */
845 	40, 41, PIN_LCD3_G2, PIN_LCD3_G3,
846 	PIN_LCD3_G4, PIN_LCD3_G5, PIN_LCD3_G6, PIN_LCD3_G7,
847 	42, 43, PIN_LCD3_B2, PIN_LCD3_B3,
848 	PIN_LCD3_B4, PIN_LCD3_B5, PIN_LCD3_B6, PIN_LCD3_B7,
849 };
850 static const unsigned int yuv3_mux[] = {
851 	YUV3_CLK_O_MARK, YUV3_HS_MARK, YUV3_VS_MARK, YUV3_DE_MARK,
852 	YUV3_D0_MARK, YUV3_D1_MARK, YUV3_D2_MARK, YUV3_D3_MARK,
853 	YUV3_D4_MARK, YUV3_D5_MARK, YUV3_D6_MARK, YUV3_D7_MARK,
854 	YUV3_D8_MARK, YUV3_D9_MARK, YUV3_D10_MARK, YUV3_D11_MARK,
855 	YUV3_D12_MARK, YUV3_D13_MARK, YUV3_D14_MARK, YUV3_D15_MARK,
856 };
857 
858 /* = [ NTSC ] ============= */
859 EMEV_MUX_PIN(ntsc_clk, 122, NTSC_CLK);
860 static const unsigned int ntsc_data_pins[] = {
861 	/* NTSC_DATA[0:7] */
862 	123, 124, 125, 126,
863 	127, 128, 129, 130,
864 };
865 static const unsigned int ntsc_data_mux[] = {
866 	NTSC_DATA0_MARK, NTSC_DATA1_MARK, NTSC_DATA2_MARK, NTSC_DATA3_MARK,
867 	NTSC_DATA4_MARK, NTSC_DATA5_MARK, NTSC_DATA6_MARK, NTSC_DATA7_MARK,
868 };
869 
870 /* = [ PWM0 ] ============= */
871 EMEV_MUX_PIN(pwm0, 120, PWM0);
872 
873 /* = [ PWM1 ] ============= */
874 EMEV_MUX_PIN(pwm1, 121, PWM1);
875 
876 /* = [ SD ] =============== */
877 EMEV_MUX_PIN(sd_cki, 48, SD_CKI);
878 
879 /* = [ SDIO0 ] ============ */
880 static const unsigned int sdi0_ctrl_pins[] = {
881 	/* CKO, CKI, CMD */
882 	50, 51, 52,
883 };
884 static const unsigned int sdi0_ctrl_mux[] = {
885 	SDI0_CKO_MARK, SDI0_CKI_MARK, SDI0_CMD_MARK,
886 };
887 
888 static const unsigned int sdi0_data_pins[] = {
889 	/* SDI0_DATA[0:7] */
890 	53, 54, 55, 56,
891 	57, 58, 59, 60
892 };
893 static const unsigned int sdi0_data_mux[] = {
894 	SDI0_DATA0_MARK, SDI0_DATA1_MARK, SDI0_DATA2_MARK, SDI0_DATA3_MARK,
895 	SDI0_DATA4_MARK, SDI0_DATA5_MARK, SDI0_DATA6_MARK, SDI0_DATA7_MARK,
896 };
897 
898 /* = [ SDIO1 ] ============ */
899 static const unsigned int sdi1_ctrl_pins[] = {
900 	/* CKO, CKI, CMD */
901 	61, 62, 63,
902 };
903 static const unsigned int sdi1_ctrl_mux[] = {
904 	SDI1_CKO_MARK, SDI1_CKI_MARK, SDI1_CMD_MARK,
905 };
906 
907 static const unsigned int sdi1_data_pins[] = {
908 	/* SDI1_DATA[0:3] */
909 	64, 65, 66, 67,
910 };
911 static const unsigned int sdi1_data_mux[] = {
912 	SDI1_DATA0_MARK, SDI1_DATA1_MARK, SDI1_DATA2_MARK, SDI1_DATA3_MARK,
913 };
914 
915 /* = [ SDIO2 ] ============ */
916 static const unsigned int sdi2_ctrl_pins[] = {
917 	/* CKO, CKI, CMD */
918 	97, 98, 99,
919 };
920 static const unsigned int sdi2_ctrl_mux[] = {
921 	SDI2_CKO_MARK, SDI2_CKI_MARK, SDI2_CMD_MARK,
922 };
923 
924 static const unsigned int sdi2_data_pins[] = {
925 	/* SDI2_DATA[0:3] */
926 	89, 90, 91, 92,
927 };
928 static const unsigned int sdi2_data_mux[] = {
929 	SDI2_DATA0_MARK, SDI2_DATA1_MARK, SDI2_DATA2_MARK, SDI2_DATA3_MARK,
930 };
931 
932 /* = [ TP33 ] ============= */
933 static const unsigned int tp33_pins[] = {
934 	/* CLK, CTRL */
935 	38, 39,
936 	/* TP33_DATA[0:15] */
937 	40, 41, PIN_LCD3_G2, PIN_LCD3_G3,
938 	PIN_LCD3_G4, PIN_LCD3_G5, PIN_LCD3_G6, PIN_LCD3_G7,
939 	42, 43, PIN_LCD3_B2, PIN_LCD3_B3,
940 	PIN_LCD3_B4, PIN_LCD3_B5, PIN_LCD3_B6, PIN_LCD3_B7,
941 };
942 static const unsigned int tp33_mux[] = {
943 	TP33_CLK_MARK, TP33_CTRL_MARK,
944 	TP33_DATA0_MARK, TP33_DATA1_MARK, TP33_DATA2_MARK, TP33_DATA3_MARK,
945 	TP33_DATA4_MARK, TP33_DATA5_MARK, TP33_DATA6_MARK, TP33_DATA7_MARK,
946 	TP33_DATA8_MARK, TP33_DATA9_MARK, TP33_DATA10_MARK, TP33_DATA11_MARK,
947 	TP33_DATA12_MARK, TP33_DATA13_MARK, TP33_DATA14_MARK, TP33_DATA15_MARK,
948 };
949 
950 /* = [ UART1 ] ============ */
951 static const unsigned int uart1_data_pins[] = {
952 	/* RX, TX */
953 	155, 156,
954 };
955 static const unsigned int uart1_data_mux[] = {
956 	UART1_RX_MARK, UART1_TX_MARK,
957 };
958 
959 static const unsigned int uart1_ctrl_pins[] = {
960 	/* CTSB, RTSB */
961 	157, 158,
962 };
963 static const unsigned int uart1_ctrl_mux[] = {
964 	UART1_CTSB_MARK, UART1_RTSB_MARK,
965 };
966 
967 /* = [ UART2 ] ============ */
968 static const unsigned int uart2_data_pins[] = {
969 	/* RX, TX */
970 	157, 158,
971 };
972 static const unsigned int uart2_data_mux[] = {
973 	UART2_RX_MARK, UART2_TX_MARK,
974 };
975 
976 /* = [ UART3 ] ============ */
977 static const unsigned int uart3_data_pins[] = {
978 	/* RX, TX */
979 	46, 47,
980 };
981 static const unsigned int uart3_data_mux[] = {
982 	UART3_RX_MARK, UART3_TX_MARK,
983 };
984 
985 /* = [ USB ] ============== */
986 EMEV_MUX_PIN(usb_vbus, 153, USB_VBUS);
987 
988 /* = [ USI0 ] ============== */
989 EMEV_MUX_PIN(usi0_cs1, 105, USI0_CS1);
990 EMEV_MUX_PIN(usi0_cs2, 106, USI0_CS2);
991 EMEV_MUX_PIN(usi0_cs3, 115, USI0_CS3);
992 EMEV_MUX_PIN(usi0_cs4, 116, USI0_CS4);
993 EMEV_MUX_PIN(usi0_cs5, 117, USI0_CS5);
994 EMEV_MUX_PIN(usi0_cs6, 118, USI0_CS6);
995 
996 /* = [ USI1 ] ============== */
997 static const unsigned int usi1_pins[] = {
998 	/* DI, DO*/
999 	107, 108,
1000 };
1001 static const unsigned int usi1_mux[] = {
1002 	USI1_DI_MARK, USI1_DO_MARK,
1003 };
1004 
1005 /* = [ USI2 ] ============== */
1006 static const unsigned int usi2_pins[] = {
1007 	/* CLK, DI, DO*/
1008 	109, 110, 111,
1009 };
1010 static const unsigned int usi2_mux[] = {
1011 	USI2_CLK_MARK, USI2_DI_MARK, USI2_DO_MARK,
1012 };
1013 EMEV_MUX_PIN(usi2_cs0, 112, USI2_CS0);
1014 EMEV_MUX_PIN(usi2_cs1, 113, USI2_CS1);
1015 EMEV_MUX_PIN(usi2_cs2, 114, USI2_CS2);
1016 
1017 /* = [ USI3 ] ============== */
1018 static const unsigned int usi3_pins[] = {
1019 	/* CLK, DI, DO*/
1020 	115, 116, 117,
1021 };
1022 static const unsigned int usi3_mux[] = {
1023 	USI3_CLK_MARK, USI3_DI_MARK, USI3_DO_MARK,
1024 };
1025 EMEV_MUX_PIN(usi3_cs0, 118, USI3_CS0);
1026 
1027 /* = [ USI4 ] ============== */
1028 static const unsigned int usi4_pins[] = {
1029 	/* CLK, DI, DO*/
1030 	119, 120, 121,
1031 };
1032 static const unsigned int usi4_mux[] = {
1033 	USI4_CLK_MARK, USI4_DI_MARK, USI4_DO_MARK,
1034 };
1035 EMEV_MUX_PIN(usi4_cs0, 113, USI4_CS0);
1036 EMEV_MUX_PIN(usi4_cs1, 114, USI4_CS1);
1037 
1038 /* = [ USI5 ] ============== */
1039 static const unsigned int usi5_a_pins[] = {
1040 	/* CLK, DI, DO*/
1041 	85, 86, 87,
1042 };
1043 static const unsigned int usi5_a_mux[] = {
1044 	USI5_CLK_A_MARK, USI5_DI_A_MARK, USI5_DO_A_MARK,
1045 };
1046 EMEV_MUX_PIN(usi5_cs0_a, 88, USI5_CS0_A);
1047 EMEV_MUX_PIN(usi5_cs1_a, 89, USI5_CS1_A);
1048 EMEV_MUX_PIN(usi5_cs2_a, 90, USI5_CS2_A);
1049 
1050 static const unsigned int usi5_b_pins[] = {
1051 	/* CLK, DI, DO*/
1052 	143, 144, 150,
1053 };
1054 static const unsigned int usi5_b_mux[] = {
1055 	USI5_CLK_B_MARK, USI5_DI_B_MARK, USI5_DO_B_MARK,
1056 };
1057 EMEV_MUX_PIN(usi5_cs0_b, 145, USI5_CS0_B);
1058 EMEV_MUX_PIN(usi5_cs1_b, 146, USI5_CS1_B);
1059 EMEV_MUX_PIN(usi5_cs2_b, 147, USI5_CS2_B);
1060 EMEV_MUX_PIN(usi5_cs3_b, 148, USI5_CS3_B);
1061 EMEV_MUX_PIN(usi5_cs4_b, 149, USI5_CS4_B);
1062 
1063 static const struct sh_pfc_pin_group pinmux_groups[] = {
1064 	SH_PFC_PIN_GROUP(err_rst_reqb),
1065 	SH_PFC_PIN_GROUP(ref_clko),
1066 	SH_PFC_PIN_GROUP(ext_clki),
1067 	SH_PFC_PIN_GROUP(lowpwr),
1068 
1069 	SH_PFC_PIN_GROUP(ab_main),
1070 	SH_PFC_PIN_GROUP(ab_clk),
1071 	SH_PFC_PIN_GROUP(ab_csb0),
1072 	SH_PFC_PIN_GROUP(ab_csb1),
1073 	SH_PFC_PIN_GROUP(ab_csb2),
1074 	SH_PFC_PIN_GROUP(ab_csb3),
1075 	SH_PFC_PIN_GROUP(ab_wait),
1076 	SH_PFC_PIN_GROUP(ab_adv),
1077 	SH_PFC_PIN_GROUP(ab_a17),
1078 	SH_PFC_PIN_GROUP(ab_a18),
1079 	SH_PFC_PIN_GROUP(ab_a19),
1080 	SH_PFC_PIN_GROUP(ab_a20),
1081 	SH_PFC_PIN_GROUP(ab_a21),
1082 	SH_PFC_PIN_GROUP(ab_a22),
1083 	SH_PFC_PIN_GROUP(ab_a23),
1084 	SH_PFC_PIN_GROUP(ab_a24),
1085 	SH_PFC_PIN_GROUP(ab_a25),
1086 	SH_PFC_PIN_GROUP(ab_a26),
1087 	SH_PFC_PIN_GROUP(ab_a27),
1088 	SH_PFC_PIN_GROUP(ab_a28),
1089 	SH_PFC_PIN_GROUP(ab_ben0),
1090 	SH_PFC_PIN_GROUP(ab_ben1),
1091 
1092 	SH_PFC_PIN_GROUP(cam_clko),
1093 	SH_PFC_PIN_GROUP(cam),
1094 
1095 	SH_PFC_PIN_GROUP(cf_ctrl),
1096 	BUS_DATA_PIN_GROUP(cf_data, 8),
1097 	BUS_DATA_PIN_GROUP(cf_data, 16),
1098 
1099 	SH_PFC_PIN_GROUP(dtv_a),
1100 	SH_PFC_PIN_GROUP(dtv_b),
1101 
1102 	SH_PFC_PIN_GROUP(iic0),
1103 
1104 	SH_PFC_PIN_GROUP(iic1),
1105 
1106 	SH_PFC_PIN_GROUP(jtag),
1107 
1108 	SH_PFC_PIN_GROUP(lcd3_pxclk),
1109 	SH_PFC_PIN_GROUP(lcd3_pxclkb),
1110 	SH_PFC_PIN_GROUP(lcd3_clk_i),
1111 	SH_PFC_PIN_GROUP(lcd3_sync),
1112 	SH_PFC_PIN_GROUP(lcd3_rgb888),
1113 	SH_PFC_PIN_GROUP(yuv3_clk_i),
1114 	SH_PFC_PIN_GROUP(yuv3),
1115 
1116 	SH_PFC_PIN_GROUP(ntsc_clk),
1117 	SH_PFC_PIN_GROUP(ntsc_data),
1118 
1119 	SH_PFC_PIN_GROUP(pwm0),
1120 
1121 	SH_PFC_PIN_GROUP(pwm1),
1122 
1123 	SH_PFC_PIN_GROUP(sd_cki),
1124 
1125 	SH_PFC_PIN_GROUP(sdi0_ctrl),
1126 	BUS_DATA_PIN_GROUP(sdi0_data, 1),
1127 	BUS_DATA_PIN_GROUP(sdi0_data, 4),
1128 	BUS_DATA_PIN_GROUP(sdi0_data, 8),
1129 
1130 	SH_PFC_PIN_GROUP(sdi1_ctrl),
1131 	BUS_DATA_PIN_GROUP(sdi1_data, 1),
1132 	BUS_DATA_PIN_GROUP(sdi1_data, 4),
1133 
1134 	SH_PFC_PIN_GROUP(sdi2_ctrl),
1135 	BUS_DATA_PIN_GROUP(sdi2_data, 1),
1136 	BUS_DATA_PIN_GROUP(sdi2_data, 4),
1137 
1138 	SH_PFC_PIN_GROUP(tp33),
1139 
1140 	SH_PFC_PIN_GROUP(uart1_data),
1141 	SH_PFC_PIN_GROUP(uart1_ctrl),
1142 
1143 	SH_PFC_PIN_GROUP(uart2_data),
1144 
1145 	SH_PFC_PIN_GROUP(uart3_data),
1146 
1147 	SH_PFC_PIN_GROUP(usb_vbus),
1148 
1149 	SH_PFC_PIN_GROUP(usi0_cs1),
1150 	SH_PFC_PIN_GROUP(usi0_cs2),
1151 	SH_PFC_PIN_GROUP(usi0_cs3),
1152 	SH_PFC_PIN_GROUP(usi0_cs4),
1153 	SH_PFC_PIN_GROUP(usi0_cs5),
1154 	SH_PFC_PIN_GROUP(usi0_cs6),
1155 
1156 	SH_PFC_PIN_GROUP(usi1),
1157 
1158 	SH_PFC_PIN_GROUP(usi2),
1159 	SH_PFC_PIN_GROUP(usi2_cs0),
1160 	SH_PFC_PIN_GROUP(usi2_cs1),
1161 	SH_PFC_PIN_GROUP(usi2_cs2),
1162 
1163 	SH_PFC_PIN_GROUP(usi3),
1164 	SH_PFC_PIN_GROUP(usi3_cs0),
1165 
1166 	SH_PFC_PIN_GROUP(usi4),
1167 	SH_PFC_PIN_GROUP(usi4_cs0),
1168 	SH_PFC_PIN_GROUP(usi4_cs1),
1169 
1170 	SH_PFC_PIN_GROUP(usi5_a),
1171 	SH_PFC_PIN_GROUP(usi5_cs0_a),
1172 	SH_PFC_PIN_GROUP(usi5_cs1_a),
1173 	SH_PFC_PIN_GROUP(usi5_cs2_a),
1174 	SH_PFC_PIN_GROUP(usi5_b),
1175 	SH_PFC_PIN_GROUP(usi5_cs0_b),
1176 	SH_PFC_PIN_GROUP(usi5_cs1_b),
1177 	SH_PFC_PIN_GROUP(usi5_cs2_b),
1178 	SH_PFC_PIN_GROUP(usi5_cs3_b),
1179 	SH_PFC_PIN_GROUP(usi5_cs4_b),
1180 };
1181 
1182 static const char * const ab_groups[] = {
1183 	"ab_main",
1184 	"ab_clk",
1185 	"ab_csb0",
1186 	"ab_csb1",
1187 	"ab_csb2",
1188 	"ab_csb3",
1189 	"ab_wait",
1190 	"ab_adv",
1191 	"ab_a17",
1192 	"ab_a18",
1193 	"ab_a19",
1194 	"ab_a20",
1195 	"ab_a21",
1196 	"ab_a22",
1197 	"ab_a23",
1198 	"ab_a24",
1199 	"ab_a25",
1200 	"ab_a26",
1201 	"ab_a27",
1202 	"ab_a28",
1203 	"ab_ben0",
1204 	"ab_ben1",
1205 };
1206 
1207 static const char * const cam_groups[] = {
1208 	"cam_clko",
1209 	"cam",
1210 };
1211 
1212 static const char * const cf_groups[] = {
1213 	"cf_ctrl",
1214 	"cf_data8",
1215 	"cf_data16",
1216 };
1217 
1218 static const char * const dtv_groups[] = {
1219 	"dtv_a",
1220 	"dtv_b",
1221 };
1222 
1223 static const char * const err_rst_reqb_groups[] = {
1224 	"err_rst_reqb",
1225 };
1226 
1227 static const char * const ext_clki_groups[] = {
1228 	"ext_clki",
1229 };
1230 
1231 static const char * const iic0_groups[] = {
1232 	"iic0",
1233 };
1234 
1235 static const char * const iic1_groups[] = {
1236 	"iic1",
1237 };
1238 
1239 static const char * const jtag_groups[] = {
1240 	"jtag",
1241 };
1242 
1243 static const char * const lcd_groups[] = {
1244 	"lcd3_pxclk",
1245 	"lcd3_pxclkb",
1246 	"lcd3_clk_i",
1247 	"lcd3_sync",
1248 	"lcd3_rgb888",
1249 	"yuv3_clk_i",
1250 	"yuv3",
1251 };
1252 
1253 static const char * const lowpwr_groups[] = {
1254 	"lowpwr",
1255 };
1256 
1257 static const char * const ntsc_groups[] = {
1258 	"ntsc_clk",
1259 	"ntsc_data",
1260 };
1261 
1262 static const char * const pwm0_groups[] = {
1263 	"pwm0",
1264 };
1265 
1266 static const char * const pwm1_groups[] = {
1267 	"pwm1",
1268 };
1269 
1270 static const char * const ref_clko_groups[] = {
1271 	"ref_clko",
1272 };
1273 
1274 static const char * const sd_groups[] = {
1275 	"sd_cki",
1276 };
1277 
1278 static const char * const sdi0_groups[] = {
1279 	"sdi0_ctrl",
1280 	"sdi0_data1",
1281 	"sdi0_data4",
1282 	"sdi0_data8",
1283 };
1284 
1285 static const char * const sdi1_groups[] = {
1286 	"sdi1_ctrl",
1287 	"sdi1_data1",
1288 	"sdi1_data4",
1289 };
1290 
1291 static const char * const sdi2_groups[] = {
1292 	"sdi2_ctrl",
1293 	"sdi2_data1",
1294 	"sdi2_data4",
1295 };
1296 
1297 static const char * const tp33_groups[] = {
1298 	"tp33",
1299 };
1300 
1301 static const char * const uart1_groups[] = {
1302 	"uart1_data",
1303 	"uart1_ctrl",
1304 };
1305 
1306 static const char * const uart2_groups[] = {
1307 	"uart2_data",
1308 };
1309 
1310 static const char * const uart3_groups[] = {
1311 	"uart3_data",
1312 };
1313 
1314 static const char * const usb_groups[] = {
1315 	"usb_vbus",
1316 };
1317 
1318 static const char * const usi0_groups[] = {
1319 	"usi0_cs1",
1320 	"usi0_cs2",
1321 	"usi0_cs3",
1322 	"usi0_cs4",
1323 	"usi0_cs5",
1324 	"usi0_cs6",
1325 };
1326 
1327 static const char * const usi1_groups[] = {
1328 	"usi1",
1329 };
1330 
1331 static const char * const usi2_groups[] = {
1332 	"usi2",
1333 	"usi2_cs0",
1334 	"usi2_cs1",
1335 	"usi2_cs2",
1336 };
1337 
1338 static const char * const usi3_groups[] = {
1339 	"usi3",
1340 	"usi3_cs0",
1341 };
1342 
1343 static const char * const usi4_groups[] = {
1344 	"usi4",
1345 	"usi4_cs0",
1346 	"usi4_cs1",
1347 };
1348 
1349 static const char * const usi5_groups[] = {
1350 	"usi5_a",
1351 	"usi5_cs0_a",
1352 	"usi5_cs1_a",
1353 	"usi5_cs2_a",
1354 	"usi5_b",
1355 	"usi5_cs0_b",
1356 	"usi5_cs1_b",
1357 	"usi5_cs2_b",
1358 	"usi5_cs3_b",
1359 	"usi5_cs4_b",
1360 };
1361 
1362 static const struct sh_pfc_function pinmux_functions[] = {
1363 	SH_PFC_FUNCTION(ab),
1364 	SH_PFC_FUNCTION(cam),
1365 	SH_PFC_FUNCTION(cf),
1366 	SH_PFC_FUNCTION(dtv),
1367 	SH_PFC_FUNCTION(err_rst_reqb),
1368 	SH_PFC_FUNCTION(ext_clki),
1369 	SH_PFC_FUNCTION(iic0),
1370 	SH_PFC_FUNCTION(iic1),
1371 	SH_PFC_FUNCTION(jtag),
1372 	SH_PFC_FUNCTION(lcd),
1373 	SH_PFC_FUNCTION(lowpwr),
1374 	SH_PFC_FUNCTION(ntsc),
1375 	SH_PFC_FUNCTION(pwm0),
1376 	SH_PFC_FUNCTION(pwm1),
1377 	SH_PFC_FUNCTION(ref_clko),
1378 	SH_PFC_FUNCTION(sd),
1379 	SH_PFC_FUNCTION(sdi0),
1380 	SH_PFC_FUNCTION(sdi1),
1381 	SH_PFC_FUNCTION(sdi2),
1382 	SH_PFC_FUNCTION(tp33),
1383 	SH_PFC_FUNCTION(uart1),
1384 	SH_PFC_FUNCTION(uart2),
1385 	SH_PFC_FUNCTION(uart3),
1386 	SH_PFC_FUNCTION(usb),
1387 	SH_PFC_FUNCTION(usi0),
1388 	SH_PFC_FUNCTION(usi1),
1389 	SH_PFC_FUNCTION(usi2),
1390 	SH_PFC_FUNCTION(usi3),
1391 	SH_PFC_FUNCTION(usi4),
1392 	SH_PFC_FUNCTION(usi5),
1393 };
1394 
1395 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1396 	{ PINMUX_CFG_REG("GPSR0", 0xe0140200, 32, 1, GROUP(
1397 		0, PORT31_FN,				/* PIN: J18  */
1398 		0, PORT30_FN,				/* PIN: H18  */
1399 		0, PORT29_FN,				/* PIN: G18  */
1400 		0, PORT28_FN,				/* PIN: F18  */
1401 		0, PORT27_FN,				/* PIN: F17  */
1402 		0, PORT26_FN,				/* PIN: F16  */
1403 		0, PORT25_FN,				/* PIN: E20  */
1404 		0, PORT24_FN,				/* PIN: D20  */
1405 		FN_LCD3_1_0_PORT23, PORT23_FN,		/* PIN: D19  */
1406 		FN_LCD3_1_0_PORT22, PORT22_FN,		/* PIN: C20  */
1407 		FN_LCD3_1_0_PORT21, PORT21_FN,		/* PIN: B21  */
1408 		FN_LCD3_1_0_PORT20, PORT20_FN,		/* PIN: A21  */
1409 		FN_LCD3_PXCLKB, PORT19_FN,		/* PIN: C21  */
1410 		FN_LCD3_1_0_PORT18, PORT18_FN,		/* PIN: B22  */
1411 		0, PORT17_FN,				/* PIN: W20  */
1412 		0, PORT16_FN,				/* PIN: W21  */
1413 		0, PORT15_FN,				/* PIN: Y19  */
1414 		0, PORT14_FN,				/* PIN: Y20  */
1415 		0, PORT13_FN,				/* PIN: Y21  */
1416 		0, PORT12_FN,				/* PIN: AA20 */
1417 		0, PORT11_FN,				/* PIN: AA21 */
1418 		0, PORT10_FN,				/* PIN: AA22 */
1419 		0, PORT9_FN,				/* PIN: V15  */
1420 		0, PORT8_FN,				/* PIN: V16  */
1421 		0, PORT7_FN,				/* PIN: V17  */
1422 		0, PORT6_FN,				/* PIN: V18  */
1423 		FN_EXT_CLKI, PORT5_FN,			/* PIN: U8   */
1424 		FN_REF_CLKO, PORT4_FN,			/* PIN: V8   */
1425 		FN_ERR_RST_REQB, PORT3_FN,		/* PIN: U9   */
1426 		FN_JT_SEL, PORT2_FN,			/* PIN: V9   */
1427 		0, PORT1_FN,				/* PIN: U10  */
1428 		0, PORT0_FN,				/* PIN: V10  */
1429 		))
1430 	},
1431 	{ PINMUX_CFG_REG("GPSR1", 0xe0140204, 32, 1, GROUP(
1432 		FN_SDI1_CMD, PORT63_FN,			/* PIN: AC21 */
1433 		FN_SDI1_CKI, PORT62_FN,			/* PIN: AA23 */
1434 		FN_SDI1_CKO, PORT61_FN,			/* PIN: AB22 */
1435 		FN_SDI0_DATA7, PORT60_FN,		/* PIN: Y16  */
1436 		FN_SDI0_DATA6, PORT59_FN,		/* PIN: AA16 */
1437 		FN_SDI0_DATA5, PORT58_FN,		/* PIN: Y15  */
1438 		FN_SDI0_DATA4, PORT57_FN,		/* PIN: AA15 */
1439 		FN_SDI0_DATA3, PORT56_FN,		/* PIN: Y14  */
1440 		FN_SDI0_DATA2, PORT55_FN,		/* PIN: AA14 */
1441 		FN_SDI0_DATA1, PORT54_FN,		/* PIN: Y13  */
1442 		FN_SDI0_DATA0, PORT53_FN,		/* PIN: AA13 */
1443 		FN_SDI0_CMD, PORT52_FN,			/* PIN: Y12  */
1444 		FN_SDI0_CKI, PORT51_FN,			/* PIN: AC18 */
1445 		FN_SDI0_CKO, PORT50_FN,			/* PIN: AB18 */
1446 		0, PORT49_FN,				/* PIN: AB16 */
1447 		FN_SD_CKI, PORT48_FN,			/* PIN: AC19 */
1448 		FN_IIC_1_0_PORT47, PORT47_FN,		/* PIN: Y8   */
1449 		FN_IIC_1_0_PORT46, PORT46_FN,		/* PIN: Y9   */
1450 		FN_IIC0_SDA, PORT45_FN,			/* PIN: AA8  */
1451 		FN_IIC0_SCL, PORT44_FN,			/* PIN: AA9  */
1452 		FN_LCD3_11_10_PORT43, PORT43_FN,	/* PIN: A15  */
1453 		FN_LCD3_11_10_PORT42, PORT42_FN,	/* PIN: A16  */
1454 		FN_LCD3_11_10_PORT41, PORT41_FN,	/* PIN: A17  */
1455 		FN_LCD3_11_10_PORT40, PORT40_FN,	/* PIN: A18  */
1456 		FN_LCD3_9_8_PORT39, PORT39_FN,		/* PIN: D18  */
1457 		FN_LCD3_9_8_PORT38, PORT38_FN,		/* PIN: C18  */
1458 		FN_LCD3_R5, PORT37_FN,			/* PIN: B18  */
1459 		FN_LCD3_R4, PORT36_FN,			/* PIN: C19  */
1460 		FN_LCD3_R3, PORT35_FN,			/* PIN: B19  */
1461 		FN_LCD3_R2, PORT34_FN,			/* PIN: A19  */
1462 		FN_LCD3_R1, PORT33_FN,			/* PIN: B20  */
1463 		FN_LCD3_R0, PORT32_FN,			/* PIN: A20  */
1464 		))
1465 	},
1466 	{ PINMUX_CFG_REG("GPSR2", 0xe0140208, 32, 1, GROUP(
1467 		FN_AB_1_0_PORT95, PORT95_FN,		/* PIN: L21  */
1468 		FN_AB_1_0_PORT94, PORT94_FN,		/* PIN: K21  */
1469 		FN_AB_1_0_PORT93, PORT93_FN,		/* PIN: J21  */
1470 		FN_AB_7_6_PORT92, PORT92_FN,		/* PIN: J22  */
1471 		FN_AB_7_6_PORT91, PORT91_FN,		/* PIN: H21  */
1472 		FN_AB_5_4_PORT90, PORT90_FN,		/* PIN: H22  */
1473 		FN_AB_5_4_PORT89, PORT89_FN,		/* PIN: H23  */
1474 		FN_AB_3_2_PORT88, PORT88_FN,		/* PIN: G21  */
1475 		FN_AB_3_2_PORT87, PORT87_FN,		/* PIN: G22  */
1476 		FN_AB_3_2_PORT86, PORT86_FN,		/* PIN: G23  */
1477 		FN_AB_3_2_PORT85, PORT85_FN,		/* PIN: F21  */
1478 		FN_AB_1_0_PORT84, PORT84_FN,		/* PIN: F22  */
1479 		FN_AB_1_0_PORT83, PORT83_FN,		/* PIN: F23  */
1480 		FN_AB_1_0_PORT82, PORT82_FN,		/* PIN: E22  */
1481 		FN_AB_1_0_PORT81, PORT81_FN,		/* PIN: E23  */
1482 		FN_AB_1_0_PORT80, PORT80_FN,		/* PIN: D22  */
1483 		FN_AB_1_0_PORT79, PORT79_FN,		/* PIN: D23  */
1484 		FN_AB_1_0_PORT78, PORT78_FN,		/* PIN: C22  */
1485 		FN_AB_1_0_PORT77, PORT77_FN,		/* PIN: C23  */
1486 		FN_AB_1_0_PORT76, PORT76_FN,		/* PIN: K20  */
1487 		FN_AB_1_0_PORT75, PORT75_FN,		/* PIN: L20  */
1488 		FN_AB_1_0_PORT74, PORT74_FN,		/* PIN: H20  */
1489 		FN_AB_1_0_PORT73, PORT73_FN,		/* PIN: J20  */
1490 		FN_AB_1_0_PORT72, PORT72_FN,		/* PIN: G20  */
1491 		FN_AB_1_0_PORT71, PORT71_FN,		/* PIN: F20  */
1492 		FN_AB_CSB1, PORT70_FN,			/* PIN: E21  */
1493 		FN_AB_CSB0, PORT69_FN,			/* PIN: D21  */
1494 		FN_AB_CLK, PORT68_FN,			/* PIN: J23  */
1495 		FN_SDI1_DATA3, PORT67_FN,		/* PIN: AA19 */
1496 		FN_SDI1_DATA2, PORT66_FN,		/* PIN: AB19 */
1497 		FN_SDI1_DATA1, PORT65_FN,		/* PIN: AB20 */
1498 		FN_SDI1_DATA0, PORT64_FN,		/* PIN: AB21 */
1499 		))
1500 	},
1501 	{ PINMUX_CFG_REG("GPSR3", 0xe014020c, 32, 1, GROUP(
1502 		FN_NTSC_DATA4, PORT127_FN,		/* PIN: T20  */
1503 		FN_NTSC_DATA3, PORT126_FN,		/* PIN: R18  */
1504 		FN_NTSC_DATA2, PORT125_FN,		/* PIN: R20  */
1505 		FN_NTSC_DATA1, PORT124_FN,		/* PIN: P18  */
1506 		FN_NTSC_DATA0, PORT123_FN,		/* PIN: P20  */
1507 		FN_NTSC_CLK, PORT122_FN,		/* PIN: V20  */
1508 		FN_USI_9_8_PORT121, PORT121_FN,		/* PIN: Y5   */
1509 		FN_USI_9_8_PORT120, PORT120_FN,		/* PIN: AA4  */
1510 		FN_USI_7_6_PORT119, PORT119_FN,		/* PIN: AB3  */
1511 		FN_USI_5_4_PORT118, PORT118_FN,		/* PIN: AB4  */
1512 		FN_USI_5_4_PORT117, PORT117_FN,		/* PIN: AC3  */
1513 		FN_USI_5_4_PORT116, PORT116_FN,		/* PIN: AC4  */
1514 		FN_USI_5_4_PORT115, PORT115_FN,		/* PIN: AC5  */
1515 		FN_USI_3_2_PORT114, PORT114_FN,		/* PIN: Y6   */
1516 		FN_USI_3_2_PORT113, PORT113_FN,		/* PIN: AA7  */
1517 		FN_USI_1_0_PORT112, PORT112_FN,		/* PIN: Y7   */
1518 		FN_USI_1_0_PORT111, PORT111_FN,		/* PIN: AA5  */
1519 		FN_USI_1_0_PORT110, PORT110_FN,		/* PIN: AA6  */
1520 		FN_USI_1_0_PORT109, PORT109_FN,		/* PIN: AB5  */
1521 		FN_USI1_DO, PORT108_FN,			/* PIN: D10  */
1522 		FN_USI1_DI, PORT107_FN,			/* PIN: C10  */
1523 		FN_USI0_CS2, PORT106_FN,		/* PIN: B9   */
1524 		FN_USI0_CS1, PORT105_FN,		/* PIN: B8   */
1525 		FN_AB_13_12_PORT104, PORT104_FN,	/* PIN: M17  */
1526 		FN_AB_13_12_PORT103, PORT103_FN,	/* PIN: L17  */
1527 		FN_AB_11_10_PORT102, PORT102_FN,	/* PIN: N18  */
1528 		FN_AB_11_10_PORT101, PORT101_FN,	/* PIN: M18  */
1529 		FN_AB_11_10_PORT100, PORT100_FN,	/* PIN: L18  */
1530 		FN_AB_9_8_PORT99, PORT99_FN,		/* PIN: N20  */
1531 		FN_AB_9_8_PORT98, PORT98_FN,		/* PIN: M20  */
1532 		FN_AB_9_8_PORT97, PORT97_FN,		/* PIN: N21  */
1533 		FN_AB_A20, PORT96_FN,			/* PIN: M21  */
1534 		))
1535 	},
1536 	{ PINMUX_CFG_REG("GPSR4", 0xe0140210, 32, 1, GROUP(
1537 		0, 0,
1538 		FN_UART_1_0_PORT158, PORT158_FN,	/* PIN: AB10 */
1539 		FN_UART_1_0_PORT157, PORT157_FN,	/* PIN: AA10 */
1540 		FN_UART1_TX, PORT156_FN,		/* PIN: Y10  */
1541 		FN_UART1_RX, PORT155_FN,		/* PIN: Y11  */
1542 		FN_LOWPWR, PORT154_FN,			/* PIN: A12  */
1543 		FN_USB_VBUS, PORT153_FN,		/* PIN: AA12 */
1544 		FN_JT_TDOEN, PORT152_FN,		/* PIN: F13  */
1545 		FN_JT_TDO, PORT151_FN,			/* PIN: D13  */
1546 		FN_HSI_1_0_PORT150, PORT150_FN,		/* PIN: M22  */
1547 		FN_HSI_1_0_PORT149, PORT149_FN,		/* PIN: M23  */
1548 		FN_HSI_1_0_PORT148, PORT148_FN,		/* PIN: N23  */
1549 		FN_HSI_1_0_PORT147, PORT147_FN,		/* PIN: N22  */
1550 		FN_HSI_1_0_PORT146, PORT146_FN,		/* PIN: L22  */
1551 		FN_HSI_1_0_PORT145, PORT145_FN,		/* PIN: L23  */
1552 		FN_HSI_1_0_PORT144, PORT144_FN,		/* PIN: K23  */
1553 		FN_HSI_1_0_PORT143, PORT143_FN,		/* PIN: K22  */
1554 		FN_CAM_YUV7, PORT142_FN,		/* PIN: V23  */
1555 		FN_CAM_YUV6, PORT141_FN,		/* PIN: V22  */
1556 		FN_CAM_YUV5, PORT140_FN,		/* PIN: U23  */
1557 		FN_CAM_YUV4, PORT139_FN,		/* PIN: U22  */
1558 		FN_CAM_YUV3, PORT138_FN,		/* PIN: U21  */
1559 		FN_CAM_YUV2, PORT137_FN,		/* PIN: T23  */
1560 		FN_CAM_YUV1, PORT136_FN,		/* PIN: T22  */
1561 		FN_CAM_YUV0, PORT135_FN,		/* PIN: T21  */
1562 		FN_CAM_HS, PORT134_FN,			/* PIN: V21  */
1563 		FN_CAM_VS, PORT133_FN,			/* PIN: W22  */
1564 		FN_CAM_CLKI, PORT132_FN,		/* PIN: Y23  */
1565 		FN_CAM_CLKO, PORT131_FN,		/* PIN: W23  */
1566 		FN_NTSC_DATA7, PORT130_FN,		/* PIN: U18  */
1567 		FN_NTSC_DATA6, PORT129_FN,		/* PIN: U20  */
1568 		FN_NTSC_DATA5, PORT128_FN,		/* PIN: T18  */
1569 		))
1570 	},
1571 	{ PINMUX_CFG_REG_VAR("CHG_PINSEL_LCD3", 0xe0140284, 32,
1572 			     GROUP(-20, 2, 2, -6, 2),
1573 			     GROUP(
1574 		/* 31 - 12 RESERVED */
1575 		/* 11 - 10 */
1576 		FN_SEL_LCD3_11_10_00, FN_SEL_LCD3_11_10_01,
1577 		FN_SEL_LCD3_11_10_10, 0,
1578 		/* 9 - 8 */
1579 		FN_SEL_LCD3_9_8_00, 0, FN_SEL_LCD3_9_8_10, 0,
1580 		/* 7 - 2 RESERVED */
1581 		/* 1 - 0 */
1582 		FN_SEL_LCD3_1_0_00, FN_SEL_LCD3_1_0_01, 0, 0,
1583 		))
1584 	},
1585 	{ PINMUX_CFG_REG_VAR("CHG_PINSEL_UART", 0xe0140288, 32,
1586 			     GROUP(-30, 2),
1587 			     GROUP(
1588 		/* 31 - 2 RESERVED */
1589 		/* 1 - 0 */
1590 		FN_SEL_UART_1_0_00, FN_SEL_UART_1_0_01, 0, 0,
1591 		))
1592 	},
1593 	{ PINMUX_CFG_REG_VAR("CHG_PINSEL_IIC", 0xe014028c, 32,
1594 			     GROUP(-30, 2),
1595 			     GROUP(
1596 		/* 31 - 2 RESERVED */
1597 		/* 1 - 0 */
1598 		FN_SEL_IIC_1_0_00, FN_SEL_IIC_1_0_01, 0, 0,
1599 		))
1600 	},
1601 	{ PINMUX_CFG_REG_VAR("CHG_PINSEL_AB", 0xe0140294, 32,
1602 			     GROUP(-18, 2, 2, 2, 2, 2, 2, 2),
1603 			     GROUP(
1604 		/* 31 - 14 RESERVED */
1605 		/* 13 - 12 */
1606 		FN_SEL_AB_13_12_00, 0, FN_SEL_AB_13_12_10, 0,
1607 		/* 11 - 10 */
1608 		FN_SEL_AB_11_10_00, 0, FN_SEL_AB_11_10_10, 0,
1609 		/* 9 - 8 */
1610 		FN_SEL_AB_9_8_00, FN_SEL_AB_9_8_01, FN_SEL_AB_9_8_10, 0,
1611 		/* 7 - 6 */
1612 		FN_SEL_AB_7_6_00, FN_SEL_AB_7_6_01, FN_SEL_AB_7_6_10, 0,
1613 		/* 5 - 4 */
1614 		FN_SEL_AB_5_4_00, FN_SEL_AB_5_4_01,
1615 		FN_SEL_AB_5_4_10, FN_SEL_AB_5_4_11,
1616 		/* 3 - 2 */
1617 		FN_SEL_AB_3_2_00, FN_SEL_AB_3_2_01,
1618 		FN_SEL_AB_3_2_10, FN_SEL_AB_3_2_11,
1619 		/* 1 - 0 */
1620 		FN_SEL_AB_1_0_00, 0, FN_SEL_AB_1_0_10, 0,
1621 		))
1622 	},
1623 	{ PINMUX_CFG_REG_VAR("CHG_PINSEL_USI", 0xe0140298, 32,
1624 			     GROUP(-22, 2, 2, 2, 2, 2),
1625 			     GROUP(
1626 		/* 31 - 10 RESERVED */
1627 		/* 9 - 8 */
1628 		FN_SEL_USI_9_8_00, FN_SEL_USI_9_8_01, 0, 0,
1629 		/* 7 - 6 */
1630 		FN_SEL_USI_7_6_00, FN_SEL_USI_7_6_01, 0, 0,
1631 		/* 5 - 4 */
1632 		FN_SEL_USI_5_4_00, FN_SEL_USI_5_4_01, 0, 0,
1633 		/* 3 - 2 */
1634 		FN_SEL_USI_3_2_00, FN_SEL_USI_3_2_01, 0, 0,
1635 		/* 1 - 0 */
1636 		FN_SEL_USI_1_0_00, FN_SEL_USI_1_0_01, 0, 0,
1637 		))
1638 	},
1639 	{ PINMUX_CFG_REG_VAR("CHG_PINSEL_HSI", 0xe01402a8, 32,
1640 			     GROUP(-30, 2),
1641 			     GROUP(
1642 		/* 31 - 2 RESERVED */
1643 		/* 1 - 0 */
1644 		FN_SEL_HSI_1_0_00, FN_SEL_HSI_1_0_01, 0, 0,
1645 		))
1646 	},
1647 	{ },
1648 };
1649 
1650 const struct sh_pfc_soc_info emev2_pinmux_info = {
1651 	.name		= "emev2_pfc",
1652 
1653 	.function	= { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
1654 
1655 	.pins		= pinmux_pins,
1656 	.nr_pins	= ARRAY_SIZE(pinmux_pins),
1657 	.groups		= pinmux_groups,
1658 	.nr_groups	= ARRAY_SIZE(pinmux_groups),
1659 	.functions	= pinmux_functions,
1660 	.nr_functions	= ARRAY_SIZE(pinmux_functions),
1661 
1662 	.cfg_regs	= pinmux_config_regs,
1663 
1664 	.pinmux_data	= pinmux_data,
1665 	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
1666 };
1667