1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Pin Function Controller Support 4 * 5 * Copyright (C) 2015 Niklas Söderlund 6 */ 7 #include <linux/init.h> 8 #include <linux/kernel.h> 9 10 #include "sh_pfc.h" 11 12 #define CPU_ALL_PORT(fn, pfx, sfx) \ 13 PORT_10(0, fn, pfx, sfx), PORT_90(0, fn, pfx, sfx), \ 14 PORT_10(100, fn, pfx##10, sfx), PORT_10(110, fn, pfx##11, sfx), \ 15 PORT_10(120, fn, pfx##12, sfx), PORT_10(130, fn, pfx##13, sfx), \ 16 PORT_10(140, fn, pfx##14, sfx), PORT_1(150, fn, pfx##150, sfx), \ 17 PORT_1(151, fn, pfx##151, sfx), PORT_1(152, fn, pfx##152, sfx), \ 18 PORT_1(153, fn, pfx##153, sfx), PORT_1(154, fn, pfx##154, sfx), \ 19 PORT_1(155, fn, pfx##155, sfx), PORT_1(156, fn, pfx##156, sfx), \ 20 PORT_1(157, fn, pfx##157, sfx), PORT_1(158, fn, pfx##158, sfx) 21 22 #define CPU_ALL_NOGP(fn) \ 23 PIN_NOGP(LCD3_B2, "B15", fn), \ 24 PIN_NOGP(LCD3_B3, "C15", fn), \ 25 PIN_NOGP(LCD3_B4, "D15", fn), \ 26 PIN_NOGP(LCD3_B5, "B14", fn), \ 27 PIN_NOGP(LCD3_B6, "C14", fn), \ 28 PIN_NOGP(LCD3_B7, "D14", fn), \ 29 PIN_NOGP(LCD3_G2, "B17", fn), \ 30 PIN_NOGP(LCD3_G3, "C17", fn), \ 31 PIN_NOGP(LCD3_G4, "D17", fn), \ 32 PIN_NOGP(LCD3_G5, "B16", fn), \ 33 PIN_NOGP(LCD3_G6, "C16", fn), \ 34 PIN_NOGP(LCD3_G7, "D16", fn) 35 36 enum { 37 PINMUX_RESERVED = 0, 38 39 PINMUX_DATA_BEGIN, 40 PORT_ALL(DATA), 41 PINMUX_DATA_END, 42 43 PINMUX_FUNCTION_BEGIN, 44 PORT_ALL(FN), 45 46 /* GPSR0 */ 47 FN_LCD3_1_0_PORT18, FN_LCD3_1_0_PORT20, FN_LCD3_1_0_PORT21, 48 FN_LCD3_1_0_PORT22, FN_LCD3_1_0_PORT23, 49 FN_JT_SEL, FN_ERR_RST_REQB, FN_REF_CLKO, FN_EXT_CLKI, FN_LCD3_PXCLKB, 50 51 /* GPSR1 */ 52 FN_LCD3_9_8_PORT38, FN_LCD3_9_8_PORT39, FN_LCD3_11_10_PORT40, 53 FN_LCD3_11_10_PORT41, FN_LCD3_11_10_PORT42, FN_LCD3_11_10_PORT43, 54 FN_IIC_1_0_PORT46, FN_IIC_1_0_PORT47, 55 FN_LCD3_R0, FN_LCD3_R1, FN_LCD3_R2, FN_LCD3_R3, FN_LCD3_R4, FN_LCD3_R5, 56 FN_IIC0_SCL, FN_IIC0_SDA, FN_SD_CKI, FN_SDI0_CKO, FN_SDI0_CKI, 57 FN_SDI0_CMD, FN_SDI0_DATA0, FN_SDI0_DATA1, FN_SDI0_DATA2, 58 FN_SDI0_DATA3, FN_SDI0_DATA4, FN_SDI0_DATA5, FN_SDI0_DATA6, 59 FN_SDI0_DATA7, FN_SDI1_CKO, FN_SDI1_CKI, FN_SDI1_CMD, 60 61 /* GPSR2 */ 62 FN_AB_1_0_PORT71, FN_AB_1_0_PORT72, FN_AB_1_0_PORT73, 63 FN_AB_1_0_PORT74, FN_AB_1_0_PORT75, FN_AB_1_0_PORT76, 64 FN_AB_1_0_PORT77, FN_AB_1_0_PORT78, FN_AB_1_0_PORT79, 65 FN_AB_1_0_PORT80, FN_AB_1_0_PORT81, FN_AB_1_0_PORT82, 66 FN_AB_1_0_PORT83, FN_AB_1_0_PORT84, FN_AB_3_2_PORT85, 67 FN_AB_3_2_PORT86, FN_AB_3_2_PORT87, FN_AB_3_2_PORT88, 68 FN_AB_5_4_PORT89, FN_AB_5_4_PORT90, FN_AB_7_6_PORT91, 69 FN_AB_7_6_PORT92, FN_AB_1_0_PORT93, FN_AB_1_0_PORT94, 70 FN_AB_1_0_PORT95, 71 FN_SDI1_DATA0, FN_SDI1_DATA1, FN_SDI1_DATA2, FN_SDI1_DATA3, 72 FN_AB_CLK, FN_AB_CSB0, FN_AB_CSB1, 73 74 /* GPSR3 */ 75 FN_AB_13_12_PORT104, FN_AB_13_12_PORT103, FN_AB_11_10_PORT102, 76 FN_AB_11_10_PORT101, FN_AB_11_10_PORT100, FN_AB_9_8_PORT99, 77 FN_AB_9_8_PORT98, FN_AB_9_8_PORT97, 78 FN_USI_1_0_PORT109, FN_USI_1_0_PORT110, FN_USI_1_0_PORT111, 79 FN_USI_1_0_PORT112, FN_USI_3_2_PORT113, FN_USI_3_2_PORT114, 80 FN_USI_5_4_PORT115, FN_USI_5_4_PORT116, FN_USI_5_4_PORT117, 81 FN_USI_5_4_PORT118, FN_USI_7_6_PORT119, FN_USI_9_8_PORT120, 82 FN_USI_9_8_PORT121, 83 FN_AB_A20, FN_USI0_CS1, FN_USI0_CS2, FN_USI1_DI, 84 FN_USI1_DO, 85 FN_NTSC_CLK, FN_NTSC_DATA0, FN_NTSC_DATA1, FN_NTSC_DATA2, 86 FN_NTSC_DATA3, FN_NTSC_DATA4, 87 88 /* GPRS4 */ 89 FN_HSI_1_0_PORT143, FN_HSI_1_0_PORT144, FN_HSI_1_0_PORT145, 90 FN_HSI_1_0_PORT146, FN_HSI_1_0_PORT147, FN_HSI_1_0_PORT148, 91 FN_HSI_1_0_PORT149, FN_HSI_1_0_PORT150, 92 FN_UART_1_0_PORT157, FN_UART_1_0_PORT158, 93 FN_NTSC_DATA5, FN_NTSC_DATA6, FN_NTSC_DATA7, FN_CAM_CLKO, 94 FN_CAM_CLKI, FN_CAM_VS, FN_CAM_HS, FN_CAM_YUV0, 95 FN_CAM_YUV1, FN_CAM_YUV2, FN_CAM_YUV3, FN_CAM_YUV4, 96 FN_CAM_YUV5, FN_CAM_YUV6, FN_CAM_YUV7, 97 FN_JT_TDO, FN_JT_TDOEN, FN_LOWPWR, FN_USB_VBUS, FN_UART1_RX, 98 FN_UART1_TX, 99 100 /* CHG_PINSEL_LCD3 */ 101 FN_SEL_LCD3_1_0_00, FN_SEL_LCD3_1_0_01, 102 FN_SEL_LCD3_9_8_00, FN_SEL_LCD3_9_8_10, 103 FN_SEL_LCD3_11_10_00, FN_SEL_LCD3_11_10_01, FN_SEL_LCD3_11_10_10, 104 105 /* CHG_PINSEL_IIC */ 106 FN_SEL_IIC_1_0_00, FN_SEL_IIC_1_0_01, 107 108 /* CHG_PINSEL_AB */ 109 FN_SEL_AB_1_0_00, FN_SEL_AB_1_0_10, FN_SEL_AB_3_2_00, 110 FN_SEL_AB_3_2_01, FN_SEL_AB_3_2_10, FN_SEL_AB_3_2_11, 111 FN_SEL_AB_5_4_00, FN_SEL_AB_5_4_01, FN_SEL_AB_5_4_10, 112 FN_SEL_AB_5_4_11, FN_SEL_AB_7_6_00, FN_SEL_AB_7_6_01, 113 FN_SEL_AB_7_6_10, 114 FN_SEL_AB_9_8_00, FN_SEL_AB_9_8_01, FN_SEL_AB_9_8_10, 115 FN_SEL_AB_11_10_00, FN_SEL_AB_11_10_10, 116 FN_SEL_AB_13_12_00, FN_SEL_AB_13_12_10, 117 118 /* CHG_PINSEL_USI */ 119 FN_SEL_USI_1_0_00, FN_SEL_USI_1_0_01, 120 FN_SEL_USI_3_2_00, FN_SEL_USI_3_2_01, 121 FN_SEL_USI_5_4_00, FN_SEL_USI_5_4_01, 122 FN_SEL_USI_7_6_00, FN_SEL_USI_7_6_01, 123 FN_SEL_USI_9_8_00, FN_SEL_USI_9_8_01, 124 125 /* CHG_PINSEL_HSI */ 126 FN_SEL_HSI_1_0_00, FN_SEL_HSI_1_0_01, 127 128 /* CHG_PINSEL_UART */ 129 FN_SEL_UART_1_0_00, FN_SEL_UART_1_0_01, 130 131 PINMUX_FUNCTION_END, 132 133 PINMUX_MARK_BEGIN, 134 135 /* GPSR0 */ 136 JT_SEL_MARK, ERR_RST_REQB_MARK, REF_CLKO_MARK, EXT_CLKI_MARK, 137 LCD3_PXCLKB_MARK, SD_CKI_MARK, 138 139 /* GPSR1 */ 140 LCD3_R0_MARK, LCD3_R1_MARK, LCD3_R2_MARK, LCD3_R3_MARK, LCD3_R4_MARK, 141 LCD3_R5_MARK, IIC0_SCL_MARK, IIC0_SDA_MARK, SDI0_CKO_MARK, 142 SDI0_CKI_MARK, SDI0_CMD_MARK, SDI0_DATA0_MARK, SDI0_DATA1_MARK, 143 SDI0_DATA2_MARK, SDI0_DATA3_MARK, SDI0_DATA4_MARK, SDI0_DATA5_MARK, 144 SDI0_DATA6_MARK, SDI0_DATA7_MARK, SDI1_CKO_MARK, SDI1_CKI_MARK, 145 SDI1_CMD_MARK, 146 147 /* GPSR2 */ 148 SDI1_DATA0_MARK, SDI1_DATA1_MARK, SDI1_DATA2_MARK, SDI1_DATA3_MARK, 149 AB_CLK_MARK, AB_CSB0_MARK, AB_CSB1_MARK, 150 151 /* GPSR3 */ 152 AB_A20_MARK, USI0_CS1_MARK, USI0_CS2_MARK, USI1_DI_MARK, 153 USI1_DO_MARK, 154 NTSC_CLK_MARK, NTSC_DATA0_MARK, NTSC_DATA1_MARK, NTSC_DATA2_MARK, 155 NTSC_DATA3_MARK, NTSC_DATA4_MARK, 156 157 /* GPSR3 */ 158 NTSC_DATA5_MARK, NTSC_DATA6_MARK, NTSC_DATA7_MARK, CAM_CLKO_MARK, 159 CAM_CLKI_MARK, CAM_VS_MARK, CAM_HS_MARK, CAM_YUV0_MARK, 160 CAM_YUV1_MARK, CAM_YUV2_MARK, CAM_YUV3_MARK, CAM_YUV4_MARK, 161 CAM_YUV5_MARK, CAM_YUV6_MARK, CAM_YUV7_MARK, 162 JT_TDO_MARK, JT_TDOEN_MARK, USB_VBUS_MARK, LOWPWR_MARK, 163 UART1_RX_MARK, UART1_TX_MARK, 164 165 /* CHG_PINSEL_LCD3 */ 166 LCD3_PXCLK_MARK, LCD3_CLK_I_MARK, LCD3_HS_MARK, LCD3_VS_MARK, 167 LCD3_DE_MARK, LCD3_R6_MARK, LCD3_R7_MARK, LCD3_G0_MARK, LCD3_G1_MARK, 168 LCD3_G2_MARK, LCD3_G3_MARK, LCD3_G4_MARK, LCD3_G5_MARK, LCD3_G6_MARK, 169 LCD3_G7_MARK, LCD3_B0_MARK, LCD3_B1_MARK, LCD3_B2_MARK, LCD3_B3_MARK, 170 LCD3_B4_MARK, LCD3_B5_MARK, LCD3_B6_MARK, LCD3_B7_MARK, 171 YUV3_CLK_O_MARK, YUV3_CLK_I_MARK, YUV3_HS_MARK, YUV3_VS_MARK, 172 YUV3_DE_MARK, YUV3_D0_MARK, YUV3_D1_MARK, YUV3_D2_MARK, YUV3_D3_MARK, 173 YUV3_D4_MARK, YUV3_D5_MARK, YUV3_D6_MARK, YUV3_D7_MARK, YUV3_D8_MARK, 174 YUV3_D9_MARK, YUV3_D10_MARK, YUV3_D11_MARK, YUV3_D12_MARK, 175 YUV3_D13_MARK, YUV3_D14_MARK, YUV3_D15_MARK, 176 TP33_CLK_MARK, TP33_CTRL_MARK, TP33_DATA0_MARK, TP33_DATA1_MARK, 177 TP33_DATA2_MARK, TP33_DATA3_MARK, TP33_DATA4_MARK, TP33_DATA5_MARK, 178 TP33_DATA6_MARK, TP33_DATA7_MARK, TP33_DATA8_MARK, TP33_DATA9_MARK, 179 TP33_DATA10_MARK, TP33_DATA11_MARK, TP33_DATA12_MARK, TP33_DATA13_MARK, 180 TP33_DATA14_MARK, TP33_DATA15_MARK, 181 182 /* CHG_PINSEL_IIC */ 183 IIC1_SCL_MARK, IIC1_SDA_MARK, UART3_RX_MARK, UART3_TX_MARK, 184 185 /* CHG_PINSEL_AB */ 186 AB_CSB2_MARK, AB_CSB3_MARK, AB_RDB_MARK, AB_WRB_MARK, 187 AB_WAIT_MARK, AB_ADV_MARK, AB_AD0_MARK, AB_AD1_MARK, 188 AB_AD2_MARK, AB_AD3_MARK, AB_AD4_MARK, AB_AD5_MARK, 189 AB_AD6_MARK, AB_AD7_MARK, AB_AD8_MARK, AB_AD9_MARK, 190 AB_AD10_MARK, AB_AD11_MARK, AB_AD12_MARK, AB_AD13_MARK, 191 AB_AD14_MARK, AB_AD15_MARK, AB_A17_MARK, AB_A18_MARK, 192 AB_A19_MARK, AB_A21_MARK, AB_A22_MARK, AB_A23_MARK, 193 AB_A24_MARK, AB_A25_MARK, AB_A26_MARK, AB_A27_MARK, 194 AB_A28_MARK, AB_BEN0_MARK, AB_BEN1_MARK, 195 DTV_BCLK_A_MARK, DTV_PSYNC_A_MARK, DTV_VALID_A_MARK, 196 DTV_DATA_A_MARK, 197 SDI2_CKO_MARK, SDI2_CKI_MARK, SDI2_CMD_MARK, 198 SDI2_DATA0_MARK, SDI2_DATA1_MARK, SDI2_DATA2_MARK, 199 SDI2_DATA3_MARK, 200 CF_CSB0_MARK, CF_CSB1_MARK, CF_IORDB_MARK, 201 CF_IOWRB_MARK, CF_IORDY_MARK, CF_RESET_MARK, 202 CF_D00_MARK, CF_D01_MARK, CF_D02_MARK, CF_D03_MARK, 203 CF_D04_MARK, CF_D05_MARK, CF_D06_MARK, CF_D07_MARK, 204 CF_D08_MARK, CF_D09_MARK, CF_D10_MARK, CF_D11_MARK, 205 CF_D12_MARK, CF_D13_MARK, CF_D14_MARK, CF_D15_MARK, 206 CF_A00_MARK, CF_A01_MARK, CF_A02_MARK, 207 CF_INTRQ_MARK, CF_INPACKB_MARK, CF_CDB1_MARK, CF_CDB2_MARK, 208 USI5_CLK_A_MARK, USI5_DI_A_MARK, USI5_DO_A_MARK, 209 USI5_CS0_A_MARK, USI5_CS1_A_MARK, USI5_CS2_A_MARK, 210 211 /* CHG_PINSEL_USI */ 212 USI0_CS3_MARK, USI0_CS4_MARK, USI0_CS5_MARK, 213 USI0_CS6_MARK, 214 USI2_CLK_MARK, USI2_DI_MARK, USI2_DO_MARK, 215 USI2_CS0_MARK, USI2_CS1_MARK, USI2_CS2_MARK, 216 USI3_CLK_MARK, USI3_DI_MARK, USI3_DO_MARK, 217 USI3_CS0_MARK, 218 USI4_CLK_MARK, USI4_DI_MARK, USI4_DO_MARK, 219 USI4_CS0_MARK, USI4_CS1_MARK, 220 PWM0_MARK, PWM1_MARK, 221 DTV_BCLK_B_MARK, DTV_PSYNC_B_MARK, DTV_VALID_B_MARK, 222 DTV_DATA_B_MARK, 223 224 /* CHG_PINSEL_HSI */ 225 USI5_CLK_B_MARK, USI5_DO_B_MARK, USI5_CS0_B_MARK, USI5_CS1_B_MARK, 226 USI5_CS2_B_MARK, USI5_CS3_B_MARK, USI5_CS4_B_MARK, USI5_DI_B_MARK, 227 228 /* CHG_PINSEL_UART */ 229 UART1_CTSB_MARK, UART1_RTSB_MARK, 230 UART2_RX_MARK, UART2_TX_MARK, 231 232 PINMUX_MARK_END, 233 }; 234 235 /* 236 * Pins not associated with a GPIO port. 237 */ 238 enum { 239 PORT_ASSIGN_LAST(), 240 NOGP_ALL(), 241 }; 242 243 /* Expand to a list of sh_pfc_pin entries (named PORT#). 244 * NOTE: No config are recorded since the driver do not handle pinconf. */ 245 #define __PIN_CFG(pn, pfx, sfx) SH_PFC_PIN_CFG(pfx, 0) 246 #define PINMUX_EMEV_GPIO_ALL() CPU_ALL_PORT(__PIN_CFG, , unused) 247 248 static const struct sh_pfc_pin pinmux_pins[] = { 249 PINMUX_EMEV_GPIO_ALL(), 250 PINMUX_NOGP_ALL(), 251 }; 252 253 /* Expand to a list of name_DATA, name_FN marks */ 254 #define __PORT_DATA(pn, pfx, sfx) PINMUX_DATA(PORT##pfx##_DATA, PORT##pfx##_FN) 255 #define PINMUX_EMEV_DATA_ALL() CPU_ALL_PORT(__PORT_DATA, , unused) 256 257 static const u16 pinmux_data[] = { 258 PINMUX_EMEV_DATA_ALL(), /* PINMUX_DATA(PORTN_DATA, PORTN_FN), */ 259 260 /* GPSR0 */ 261 /* V9 */ 262 PINMUX_SINGLE(JT_SEL), 263 /* U9 */ 264 PINMUX_SINGLE(ERR_RST_REQB), 265 /* V8 */ 266 PINMUX_SINGLE(REF_CLKO), 267 /* U8 */ 268 PINMUX_SINGLE(EXT_CLKI), 269 /* B22*/ 270 PINMUX_IPSR_NOFN(LCD3_1_0_PORT18, LCD3_PXCLK, SEL_LCD3_1_0_00), 271 PINMUX_IPSR_NOFN(LCD3_1_0_PORT18, YUV3_CLK_O, SEL_LCD3_1_0_01), 272 /* C21 */ 273 PINMUX_SINGLE(LCD3_PXCLKB), 274 /* A21 */ 275 PINMUX_IPSR_NOFN(LCD3_1_0_PORT20, LCD3_CLK_I, SEL_LCD3_1_0_00), 276 PINMUX_IPSR_NOFN(LCD3_1_0_PORT20, YUV3_CLK_I, SEL_LCD3_1_0_01), 277 /* B21 */ 278 PINMUX_IPSR_NOFN(LCD3_1_0_PORT21, LCD3_HS, SEL_LCD3_1_0_00), 279 PINMUX_IPSR_NOFN(LCD3_1_0_PORT21, YUV3_HS, SEL_LCD3_1_0_01), 280 /* C20 */ 281 PINMUX_IPSR_NOFN(LCD3_1_0_PORT22, LCD3_VS, SEL_LCD3_1_0_00), 282 PINMUX_IPSR_NOFN(LCD3_1_0_PORT22, YUV3_VS, SEL_LCD3_1_0_01), 283 /* D19 */ 284 PINMUX_IPSR_NOFN(LCD3_1_0_PORT23, LCD3_DE, SEL_LCD3_1_0_00), 285 PINMUX_IPSR_NOFN(LCD3_1_0_PORT23, YUV3_DE, SEL_LCD3_1_0_01), 286 287 /* GPSR1 */ 288 /* A20 */ 289 PINMUX_SINGLE(LCD3_R0), 290 /* B20 */ 291 PINMUX_SINGLE(LCD3_R1), 292 /* A19 */ 293 PINMUX_SINGLE(LCD3_R2), 294 /* B19 */ 295 PINMUX_SINGLE(LCD3_R3), 296 /* C19 */ 297 PINMUX_SINGLE(LCD3_R4), 298 /* B18 */ 299 PINMUX_SINGLE(LCD3_R5), 300 /* C18 */ 301 PINMUX_IPSR_NOFN(LCD3_9_8_PORT38, LCD3_R6, SEL_LCD3_9_8_00), 302 PINMUX_IPSR_NOFN(LCD3_9_8_PORT38, TP33_CLK, SEL_LCD3_9_8_10), 303 /* D18 */ 304 PINMUX_IPSR_NOFN(LCD3_9_8_PORT39, LCD3_R7, SEL_LCD3_9_8_00), 305 PINMUX_IPSR_NOFN(LCD3_9_8_PORT39, TP33_CTRL, SEL_LCD3_9_8_10), 306 /* A18 */ 307 PINMUX_IPSR_NOFN(LCD3_11_10_PORT40, LCD3_G0, SEL_LCD3_11_10_00), 308 PINMUX_IPSR_NOFN(LCD3_11_10_PORT40, YUV3_D0, SEL_LCD3_11_10_01), 309 PINMUX_IPSR_NOFN(LCD3_11_10_PORT40, TP33_DATA0, SEL_LCD3_11_10_10), 310 /* A17 */ 311 PINMUX_IPSR_NOFN(LCD3_11_10_PORT41, LCD3_G1, SEL_LCD3_11_10_00), 312 PINMUX_IPSR_NOFN(LCD3_11_10_PORT41, YUV3_D1, SEL_LCD3_11_10_01), 313 PINMUX_IPSR_NOFN(LCD3_11_10_PORT41, TP33_DATA1, SEL_LCD3_11_10_10), 314 /* B17 */ 315 PINMUX_DATA(LCD3_G2_MARK, FN_SEL_LCD3_11_10_00), 316 PINMUX_DATA(YUV3_D2_MARK, FN_SEL_LCD3_11_10_01), 317 PINMUX_DATA(TP33_DATA2_MARK, FN_SEL_LCD3_11_10_10), 318 /* C17 */ 319 PINMUX_DATA(LCD3_G3_MARK, FN_SEL_LCD3_11_10_00), 320 PINMUX_DATA(YUV3_D3_MARK, FN_SEL_LCD3_11_10_01), 321 PINMUX_DATA(TP33_DATA3_MARK, FN_SEL_LCD3_11_10_10), 322 /* D17 */ 323 PINMUX_DATA(LCD3_G4_MARK, FN_SEL_LCD3_11_10_00), 324 PINMUX_DATA(YUV3_D4_MARK, FN_SEL_LCD3_11_10_01), 325 PINMUX_DATA(TP33_DATA4_MARK, FN_SEL_LCD3_11_10_10), 326 /* B16 */ 327 PINMUX_DATA(LCD3_G5_MARK, FN_SEL_LCD3_11_10_00), 328 PINMUX_DATA(YUV3_D5_MARK, FN_SEL_LCD3_11_10_01), 329 PINMUX_DATA(TP33_DATA5_MARK, FN_SEL_LCD3_11_10_10), 330 /* C16 */ 331 PINMUX_DATA(LCD3_G6_MARK, FN_SEL_LCD3_11_10_00), 332 PINMUX_DATA(YUV3_D6_MARK, FN_SEL_LCD3_11_10_01), 333 PINMUX_DATA(TP33_DATA6_MARK, FN_SEL_LCD3_11_10_10), 334 /* D16 */ 335 PINMUX_DATA(LCD3_G7_MARK, FN_SEL_LCD3_11_10_00), 336 PINMUX_DATA(YUV3_D7_MARK, FN_SEL_LCD3_11_10_01), 337 PINMUX_DATA(TP33_DATA7_MARK, FN_SEL_LCD3_11_10_10), 338 /* A16 */ 339 PINMUX_IPSR_NOFN(LCD3_11_10_PORT42, LCD3_B0, SEL_LCD3_11_10_00), 340 PINMUX_IPSR_NOFN(LCD3_11_10_PORT42, YUV3_D8, SEL_LCD3_11_10_01), 341 PINMUX_IPSR_NOFN(LCD3_11_10_PORT42, TP33_DATA8, SEL_LCD3_11_10_10), 342 /* A15 */ 343 PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, LCD3_B1, SEL_LCD3_11_10_00), 344 PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, YUV3_D9, SEL_LCD3_11_10_01), 345 PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, TP33_DATA9, SEL_LCD3_11_10_10), 346 /* B15 */ 347 PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, LCD3_B2, SEL_LCD3_11_10_00), 348 PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, YUV3_D10, SEL_LCD3_11_10_01), 349 PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, TP33_DATA10, SEL_LCD3_11_10_10), 350 /* C15 */ 351 PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, LCD3_B3, SEL_LCD3_11_10_00), 352 PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, YUV3_D11, SEL_LCD3_11_10_01), 353 PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, TP33_DATA11, SEL_LCD3_11_10_10), 354 /* D15 */ 355 PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, LCD3_B4, SEL_LCD3_11_10_00), 356 PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, YUV3_D12, SEL_LCD3_11_10_01), 357 PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, TP33_DATA12, SEL_LCD3_11_10_10), 358 /* B14 */ 359 PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, LCD3_B5, SEL_LCD3_11_10_00), 360 PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, YUV3_D13, SEL_LCD3_11_10_01), 361 PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, TP33_DATA13, SEL_LCD3_11_10_10), 362 /* C14 */ 363 PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, LCD3_B6, SEL_LCD3_11_10_00), 364 PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, YUV3_D14, SEL_LCD3_11_10_01), 365 PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, TP33_DATA14, SEL_LCD3_11_10_10), 366 /* D14 */ 367 PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, LCD3_B7, SEL_LCD3_11_10_00), 368 PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, YUV3_D15, SEL_LCD3_11_10_01), 369 PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, TP33_DATA15, SEL_LCD3_11_10_10), 370 /* AA9 */ 371 PINMUX_SINGLE(IIC0_SCL), 372 /* AA8 */ 373 PINMUX_SINGLE(IIC0_SDA), 374 /* Y9 */ 375 PINMUX_IPSR_NOFN(IIC_1_0_PORT46, IIC1_SCL, SEL_IIC_1_0_00), 376 PINMUX_IPSR_NOFN(IIC_1_0_PORT46, UART3_RX, SEL_IIC_1_0_01), 377 /* Y8 */ 378 PINMUX_IPSR_NOFN(IIC_1_0_PORT47, IIC1_SDA, SEL_IIC_1_0_00), 379 PINMUX_IPSR_NOFN(IIC_1_0_PORT47, UART3_TX, SEL_IIC_1_0_01), 380 /* AC19 */ 381 PINMUX_SINGLE(SD_CKI), 382 /* AB18 */ 383 PINMUX_SINGLE(SDI0_CKO), 384 /* AC18 */ 385 PINMUX_SINGLE(SDI0_CKI), 386 /* Y12 */ 387 PINMUX_SINGLE(SDI0_CMD), 388 /* AA13 */ 389 PINMUX_SINGLE(SDI0_DATA0), 390 /* Y13 */ 391 PINMUX_SINGLE(SDI0_DATA1), 392 /* AA14 */ 393 PINMUX_SINGLE(SDI0_DATA2), 394 /* Y14 */ 395 PINMUX_SINGLE(SDI0_DATA3), 396 /* AA15 */ 397 PINMUX_SINGLE(SDI0_DATA4), 398 /* Y15 */ 399 PINMUX_SINGLE(SDI0_DATA5), 400 /* AA16 */ 401 PINMUX_SINGLE(SDI0_DATA6), 402 /* Y16 */ 403 PINMUX_SINGLE(SDI0_DATA7), 404 /* AB22 */ 405 PINMUX_SINGLE(SDI1_CKO), 406 /* AA23 */ 407 PINMUX_SINGLE(SDI1_CKI), 408 /* AC21 */ 409 PINMUX_SINGLE(SDI1_CMD), 410 411 /* GPSR2 */ 412 /* AB21 */ 413 PINMUX_SINGLE(SDI1_DATA0), 414 /* AB20 */ 415 PINMUX_SINGLE(SDI1_DATA1), 416 /* AB19 */ 417 PINMUX_SINGLE(SDI1_DATA2), 418 /* AA19 */ 419 PINMUX_SINGLE(SDI1_DATA3), 420 /* J23 */ 421 PINMUX_SINGLE(AB_CLK), 422 /* D21 */ 423 PINMUX_SINGLE(AB_CSB0), 424 /* E21 */ 425 PINMUX_SINGLE(AB_CSB1), 426 /* F20 */ 427 PINMUX_IPSR_NOFN(AB_1_0_PORT71, AB_CSB2, SEL_AB_1_0_00), 428 PINMUX_IPSR_NOFN(AB_1_0_PORT71, CF_CSB0, SEL_AB_1_0_10), 429 /* G20 */ 430 PINMUX_IPSR_NOFN(AB_1_0_PORT72, AB_CSB3, SEL_AB_1_0_00), 431 PINMUX_IPSR_NOFN(AB_1_0_PORT72, CF_CSB1, SEL_AB_1_0_10), 432 /* J20 */ 433 PINMUX_IPSR_NOFN(AB_1_0_PORT73, AB_RDB, SEL_AB_1_0_00), 434 PINMUX_IPSR_NOFN(AB_1_0_PORT73, CF_IORDB, SEL_AB_1_0_10), 435 /* H20 */ 436 PINMUX_IPSR_NOFN(AB_1_0_PORT74, AB_WRB, SEL_AB_1_0_00), 437 PINMUX_IPSR_NOFN(AB_1_0_PORT74, CF_IOWRB, SEL_AB_1_0_10), 438 /* L20 */ 439 PINMUX_IPSR_NOFN(AB_1_0_PORT75, AB_WAIT, SEL_AB_1_0_00), 440 PINMUX_IPSR_NOFN(AB_1_0_PORT75, CF_IORDY, SEL_AB_1_0_10), 441 /* K20 */ 442 PINMUX_IPSR_NOFN(AB_1_0_PORT76, AB_ADV, SEL_AB_1_0_00), 443 PINMUX_IPSR_NOFN(AB_1_0_PORT76, CF_RESET, SEL_AB_1_0_10), 444 /* C23 */ 445 PINMUX_IPSR_NOFN(AB_1_0_PORT77, AB_AD0, SEL_AB_1_0_00), 446 PINMUX_IPSR_NOFN(AB_1_0_PORT77, CF_D00, SEL_AB_1_0_10), 447 /* C22 */ 448 PINMUX_IPSR_NOFN(AB_1_0_PORT78, AB_AD1, SEL_AB_1_0_00), 449 PINMUX_IPSR_NOFN(AB_1_0_PORT78, CF_D01, SEL_AB_1_0_10), 450 /* D23 */ 451 PINMUX_IPSR_NOFN(AB_1_0_PORT79, AB_AD2, SEL_AB_1_0_00), 452 PINMUX_IPSR_NOFN(AB_1_0_PORT79, CF_D02, SEL_AB_1_0_10), 453 /* D22 */ 454 PINMUX_IPSR_NOFN(AB_1_0_PORT80, AB_AD3, SEL_AB_1_0_00), 455 PINMUX_IPSR_NOFN(AB_1_0_PORT80, CF_D03, SEL_AB_1_0_10), 456 /* E23 */ 457 PINMUX_IPSR_NOFN(AB_1_0_PORT81, AB_AD4, SEL_AB_1_0_00), 458 PINMUX_IPSR_NOFN(AB_1_0_PORT81, CF_D04, SEL_AB_1_0_10), 459 /* E22 */ 460 PINMUX_IPSR_NOFN(AB_1_0_PORT82, AB_AD5, SEL_AB_1_0_00), 461 PINMUX_IPSR_NOFN(AB_1_0_PORT82, CF_D05, SEL_AB_1_0_10), 462 /* F23 */ 463 PINMUX_IPSR_NOFN(AB_1_0_PORT83, AB_AD6, SEL_AB_1_0_00), 464 PINMUX_IPSR_NOFN(AB_1_0_PORT83, CF_D06, SEL_AB_1_0_10), 465 /* F22 */ 466 PINMUX_IPSR_NOFN(AB_1_0_PORT84, AB_AD7, SEL_AB_1_0_00), 467 PINMUX_IPSR_NOFN(AB_1_0_PORT84, CF_D07, SEL_AB_1_0_10), 468 /* F21 */ 469 PINMUX_IPSR_NOFN(AB_3_2_PORT85, AB_AD8, SEL_AB_3_2_00), 470 PINMUX_IPSR_NOFN(AB_3_2_PORT85, DTV_BCLK_A, SEL_AB_3_2_01), 471 PINMUX_IPSR_NOFN(AB_3_2_PORT85, CF_D08, SEL_AB_3_2_10), 472 PINMUX_IPSR_NOFN(AB_3_2_PORT85, USI5_CLK_A, SEL_AB_3_2_11), 473 /* G23 */ 474 PINMUX_IPSR_NOFN(AB_3_2_PORT86, AB_AD9, SEL_AB_3_2_00), 475 PINMUX_IPSR_NOFN(AB_3_2_PORT86, DTV_PSYNC_A, SEL_AB_3_2_01), 476 PINMUX_IPSR_NOFN(AB_3_2_PORT86, CF_D09, SEL_AB_3_2_10), 477 PINMUX_IPSR_NOFN(AB_3_2_PORT86, USI5_DI_A, SEL_AB_3_2_11), 478 /* G22 */ 479 PINMUX_IPSR_NOFN(AB_3_2_PORT87, AB_AD10, SEL_AB_3_2_00), 480 PINMUX_IPSR_NOFN(AB_3_2_PORT87, DTV_VALID_A, SEL_AB_3_2_01), 481 PINMUX_IPSR_NOFN(AB_3_2_PORT87, CF_D10, SEL_AB_3_2_10), 482 PINMUX_IPSR_NOFN(AB_3_2_PORT87, USI5_DO_A, SEL_AB_3_2_11), 483 /* G21 */ 484 PINMUX_IPSR_NOFN(AB_3_2_PORT88, AB_AD11, SEL_AB_3_2_00), 485 PINMUX_IPSR_NOFN(AB_3_2_PORT88, DTV_DATA_A, SEL_AB_3_2_01), 486 PINMUX_IPSR_NOFN(AB_3_2_PORT88, CF_D11, SEL_AB_3_2_10), 487 PINMUX_IPSR_NOFN(AB_3_2_PORT88, USI5_CS0_A, SEL_AB_3_2_11), 488 /* H23 */ 489 PINMUX_IPSR_NOFN(AB_5_4_PORT89, AB_AD12, SEL_AB_5_4_00), 490 PINMUX_IPSR_NOFN(AB_5_4_PORT89, SDI2_DATA0, SEL_AB_5_4_01), 491 PINMUX_IPSR_NOFN(AB_5_4_PORT89, CF_D12, SEL_AB_5_4_10), 492 PINMUX_IPSR_NOFN(AB_5_4_PORT89, USI5_CS1_A, SEL_AB_5_4_11), 493 /* H22 */ 494 PINMUX_IPSR_NOFN(AB_5_4_PORT90, AB_AD13, SEL_AB_5_4_00), 495 PINMUX_IPSR_NOFN(AB_5_4_PORT90, SDI2_DATA1, SEL_AB_5_4_01), 496 PINMUX_IPSR_NOFN(AB_5_4_PORT90, CF_D13, SEL_AB_5_4_10), 497 PINMUX_IPSR_NOFN(AB_5_4_PORT90, USI5_CS2_A, SEL_AB_5_4_11), 498 /* H21 */ 499 PINMUX_IPSR_NOFN(AB_7_6_PORT91, AB_AD14, SEL_AB_7_6_00), 500 PINMUX_IPSR_NOFN(AB_7_6_PORT91, SDI2_DATA2, SEL_AB_7_6_01), 501 PINMUX_IPSR_NOFN(AB_7_6_PORT91, CF_D14, SEL_AB_7_6_10), 502 /* J22 */ 503 PINMUX_IPSR_NOFN(AB_7_6_PORT92, AB_AD15, SEL_AB_7_6_00), 504 PINMUX_IPSR_NOFN(AB_7_6_PORT92, SDI2_DATA3, SEL_AB_7_6_01), 505 PINMUX_IPSR_NOFN(AB_7_6_PORT92, CF_D15, SEL_AB_7_6_10), 506 /* J21 */ 507 PINMUX_IPSR_NOFN(AB_1_0_PORT93, AB_A17, SEL_AB_1_0_00), 508 PINMUX_IPSR_NOFN(AB_1_0_PORT93, CF_A00, SEL_AB_1_0_10), 509 /* K21 */ 510 PINMUX_IPSR_NOFN(AB_1_0_PORT94, AB_A18, SEL_AB_1_0_00), 511 PINMUX_IPSR_NOFN(AB_1_0_PORT94, CF_A01, SEL_AB_1_0_10), 512 /* L21 */ 513 PINMUX_IPSR_NOFN(AB_1_0_PORT95, AB_A19, SEL_AB_1_0_00), 514 PINMUX_IPSR_NOFN(AB_1_0_PORT95, CF_A02, SEL_AB_1_0_10), 515 516 /* GPSR3 */ 517 /* M21 */ 518 PINMUX_SINGLE(AB_A20), 519 /* N21 */ 520 PINMUX_IPSR_NOFN(AB_9_8_PORT97, AB_A21, SEL_AB_9_8_00), 521 PINMUX_IPSR_NOFN(AB_9_8_PORT97, SDI2_CKO, SEL_AB_9_8_01), 522 PINMUX_IPSR_NOFN(AB_9_8_PORT97, CF_INTRQ, SEL_AB_9_8_10), 523 /* M20 */ 524 PINMUX_IPSR_NOFN(AB_9_8_PORT98, AB_A22, SEL_AB_9_8_00), 525 PINMUX_IPSR_NOFN(AB_9_8_PORT98, SDI2_CKI, SEL_AB_9_8_01), 526 /* N20 */ 527 PINMUX_IPSR_NOFN(AB_9_8_PORT99, AB_A23, SEL_AB_9_8_00), 528 PINMUX_IPSR_NOFN(AB_9_8_PORT99, SDI2_CMD, SEL_AB_9_8_01), 529 /* L18 */ 530 PINMUX_IPSR_NOFN(AB_11_10_PORT100, AB_A24, SEL_AB_11_10_00), 531 PINMUX_IPSR_NOFN(AB_11_10_PORT100, CF_INPACKB, SEL_AB_11_10_10), 532 /* M18 */ 533 PINMUX_IPSR_NOFN(AB_11_10_PORT101, AB_A25, SEL_AB_11_10_00), 534 PINMUX_IPSR_NOFN(AB_11_10_PORT101, CF_CDB1, SEL_AB_11_10_10), 535 /* N18 */ 536 PINMUX_IPSR_NOFN(AB_11_10_PORT102, AB_A26, SEL_AB_11_10_00), 537 PINMUX_IPSR_NOFN(AB_11_10_PORT102, CF_CDB2, SEL_AB_11_10_10), 538 /* L17 */ 539 PINMUX_IPSR_NOFN(AB_13_12_PORT103, AB_A27, SEL_AB_13_12_00), 540 PINMUX_IPSR_NOFN(AB_13_12_PORT103, AB_BEN0, SEL_AB_13_12_10), 541 /* M17 */ 542 PINMUX_IPSR_NOFN(AB_13_12_PORT104, AB_A28, SEL_AB_13_12_00), 543 PINMUX_IPSR_NOFN(AB_13_12_PORT104, AB_BEN1, SEL_AB_13_12_10), 544 /* B8 */ 545 PINMUX_SINGLE(USI0_CS1), 546 /* B9 */ 547 PINMUX_SINGLE(USI0_CS2), 548 /* C10 */ 549 PINMUX_SINGLE(USI1_DI), 550 /* D10 */ 551 PINMUX_SINGLE(USI1_DO), 552 /* AB5 */ 553 PINMUX_IPSR_NOFN(USI_1_0_PORT109, USI2_CLK, SEL_USI_1_0_00), 554 PINMUX_IPSR_NOFN(USI_1_0_PORT109, DTV_BCLK_B, SEL_USI_1_0_01), 555 /* AA6 */ 556 PINMUX_IPSR_NOFN(USI_1_0_PORT110, USI2_DI, SEL_USI_1_0_00), 557 PINMUX_IPSR_NOFN(USI_1_0_PORT110, DTV_PSYNC_B, SEL_USI_1_0_01), 558 /* AA5 */ 559 PINMUX_IPSR_NOFN(USI_1_0_PORT111, USI2_DO, SEL_USI_1_0_00), 560 PINMUX_IPSR_NOFN(USI_1_0_PORT111, DTV_VALID_B, SEL_USI_1_0_01), 561 /* Y7 */ 562 PINMUX_IPSR_NOFN(USI_1_0_PORT112, USI2_CS0, SEL_USI_1_0_00), 563 PINMUX_IPSR_NOFN(USI_1_0_PORT112, DTV_DATA_B, SEL_USI_1_0_01), 564 /* AA7 */ 565 PINMUX_IPSR_NOFN(USI_3_2_PORT113, USI2_CS1, SEL_USI_3_2_00), 566 PINMUX_IPSR_NOFN(USI_3_2_PORT113, USI4_CS0, SEL_USI_3_2_01), 567 /* Y6 */ 568 PINMUX_IPSR_NOFN(USI_3_2_PORT114, USI2_CS2, SEL_USI_3_2_00), 569 PINMUX_IPSR_NOFN(USI_3_2_PORT114, USI4_CS1, SEL_USI_3_2_01), 570 /* AC5 */ 571 PINMUX_IPSR_NOFN(USI_5_4_PORT115, USI3_CLK, SEL_USI_5_4_00), 572 PINMUX_IPSR_NOFN(USI_5_4_PORT115, USI0_CS3, SEL_USI_5_4_01), 573 /* AC4 */ 574 PINMUX_IPSR_NOFN(USI_5_4_PORT116, USI3_DI, SEL_USI_5_4_00), 575 PINMUX_IPSR_NOFN(USI_5_4_PORT116, USI0_CS4, SEL_USI_5_4_01), 576 /* AC3 */ 577 PINMUX_IPSR_NOFN(USI_5_4_PORT117, USI3_DO, SEL_USI_5_4_00), 578 PINMUX_IPSR_NOFN(USI_5_4_PORT117, USI0_CS5, SEL_USI_5_4_01), 579 /* AB4 */ 580 PINMUX_IPSR_NOFN(USI_5_4_PORT118, USI3_CS0, SEL_USI_5_4_00), 581 PINMUX_IPSR_NOFN(USI_5_4_PORT118, USI0_CS6, SEL_USI_5_4_01), 582 /* AB3 */ 583 PINMUX_IPSR_NOFN(USI_7_6_PORT119, USI4_CLK, SEL_USI_7_6_01), 584 /* AA4 */ 585 PINMUX_IPSR_NOFN(USI_9_8_PORT120, PWM0, SEL_USI_9_8_00), 586 PINMUX_IPSR_NOFN(USI_9_8_PORT120, USI4_DI, SEL_USI_9_8_01), 587 /* Y5 */ 588 PINMUX_IPSR_NOFN(USI_9_8_PORT121, PWM1, SEL_USI_9_8_00), 589 PINMUX_IPSR_NOFN(USI_9_8_PORT121, USI4_DO, SEL_USI_9_8_01), 590 /* V20 */ 591 PINMUX_SINGLE(NTSC_CLK), 592 /* P20 */ 593 PINMUX_SINGLE(NTSC_DATA0), 594 /* P18 */ 595 PINMUX_SINGLE(NTSC_DATA1), 596 /* R20 */ 597 PINMUX_SINGLE(NTSC_DATA2), 598 /* R18 */ 599 PINMUX_SINGLE(NTSC_DATA3), 600 /* T20 */ 601 PINMUX_SINGLE(NTSC_DATA4), 602 603 /* GPRS3 */ 604 /* T18 */ 605 PINMUX_SINGLE(NTSC_DATA5), 606 /* U20 */ 607 PINMUX_SINGLE(NTSC_DATA6), 608 /* U18 */ 609 PINMUX_SINGLE(NTSC_DATA7), 610 /* W23 */ 611 PINMUX_SINGLE(CAM_CLKO), 612 /* Y23 */ 613 PINMUX_SINGLE(CAM_CLKI), 614 /* W22 */ 615 PINMUX_SINGLE(CAM_VS), 616 /* V21 */ 617 PINMUX_SINGLE(CAM_HS), 618 /* T21 */ 619 PINMUX_SINGLE(CAM_YUV0), 620 /* T22 */ 621 PINMUX_SINGLE(CAM_YUV1), 622 /* T23 */ 623 PINMUX_SINGLE(CAM_YUV2), 624 /* U21 */ 625 PINMUX_SINGLE(CAM_YUV3), 626 /* U22 */ 627 PINMUX_SINGLE(CAM_YUV4), 628 /* U23 */ 629 PINMUX_SINGLE(CAM_YUV5), 630 /* V22 */ 631 PINMUX_SINGLE(CAM_YUV6), 632 /* V23 */ 633 PINMUX_SINGLE(CAM_YUV7), 634 /* K22 */ 635 PINMUX_IPSR_NOFN(HSI_1_0_PORT143, USI5_CLK_B, SEL_HSI_1_0_01), 636 /* K23 */ 637 PINMUX_IPSR_NOFN(HSI_1_0_PORT144, USI5_DO_B, SEL_HSI_1_0_01), 638 /* L23 */ 639 PINMUX_IPSR_NOFN(HSI_1_0_PORT145, USI5_CS0_B, SEL_HSI_1_0_01), 640 /* L22 */ 641 PINMUX_IPSR_NOFN(HSI_1_0_PORT146, USI5_CS1_B, SEL_HSI_1_0_01), 642 /* N22 */ 643 PINMUX_IPSR_NOFN(HSI_1_0_PORT147, USI5_CS2_B, SEL_HSI_1_0_01), 644 /* N23 */ 645 PINMUX_IPSR_NOFN(HSI_1_0_PORT148, USI5_CS3_B, SEL_HSI_1_0_01), 646 /* M23 */ 647 PINMUX_IPSR_NOFN(HSI_1_0_PORT149, USI5_CS4_B, SEL_HSI_1_0_01), 648 /* M22 */ 649 PINMUX_IPSR_NOFN(HSI_1_0_PORT150, USI5_DI_B, SEL_HSI_1_0_01), 650 /* D13 */ 651 PINMUX_SINGLE(JT_TDO), 652 /* F13 */ 653 PINMUX_SINGLE(JT_TDOEN), 654 /* AA12 */ 655 PINMUX_SINGLE(USB_VBUS), 656 /* A12 */ 657 PINMUX_SINGLE(LOWPWR), 658 /* Y11 */ 659 PINMUX_SINGLE(UART1_RX), 660 /* Y10 */ 661 PINMUX_SINGLE(UART1_TX), 662 /* AA10 */ 663 PINMUX_IPSR_NOFN(UART_1_0_PORT157, UART1_CTSB, SEL_UART_1_0_00), 664 PINMUX_IPSR_NOFN(UART_1_0_PORT157, UART2_RX, SEL_UART_1_0_01), 665 /* AB10 */ 666 PINMUX_IPSR_NOFN(UART_1_0_PORT158, UART1_RTSB, SEL_UART_1_0_00), 667 PINMUX_IPSR_NOFN(UART_1_0_PORT158, UART2_TX, SEL_UART_1_0_01), 668 }; 669 670 671 #define EMEV_MUX_PIN(name, pin, mark) \ 672 static const unsigned int name##_pins[] = { pin }; \ 673 static const unsigned int name##_mux[] = { mark##_MARK } 674 675 /* = [ System ] =========== */ 676 EMEV_MUX_PIN(err_rst_reqb, 3, ERR_RST_REQB); 677 EMEV_MUX_PIN(ref_clko, 4, REF_CLKO); 678 EMEV_MUX_PIN(ext_clki, 5, EXT_CLKI); 679 EMEV_MUX_PIN(lowpwr, 154, LOWPWR); 680 681 /* = [ External Memory] === */ 682 static const unsigned int ab_main_pins[] = { 683 /* AB_RDB, AB_WRB */ 684 73, 74, 685 /* AB_AD[0:15] */ 686 77, 78, 79, 80, 687 81, 82, 83, 84, 688 85, 86, 87, 88, 689 89, 90, 91, 92, 690 }; 691 static const unsigned int ab_main_mux[] = { 692 AB_RDB_MARK, AB_WRB_MARK, 693 AB_AD0_MARK, AB_AD1_MARK, AB_AD2_MARK, AB_AD3_MARK, 694 AB_AD4_MARK, AB_AD5_MARK, AB_AD6_MARK, AB_AD7_MARK, 695 AB_AD8_MARK, AB_AD9_MARK, AB_AD10_MARK, AB_AD11_MARK, 696 AB_AD12_MARK, AB_AD13_MARK, AB_AD14_MARK, AB_AD15_MARK, 697 }; 698 699 EMEV_MUX_PIN(ab_clk, 68, AB_CLK); 700 EMEV_MUX_PIN(ab_csb0, 69, AB_CSB0); 701 EMEV_MUX_PIN(ab_csb1, 70, AB_CSB1); 702 EMEV_MUX_PIN(ab_csb2, 71, AB_CSB2); 703 EMEV_MUX_PIN(ab_csb3, 72, AB_CSB3); 704 EMEV_MUX_PIN(ab_wait, 75, AB_WAIT); 705 EMEV_MUX_PIN(ab_adv, 76, AB_ADV); 706 EMEV_MUX_PIN(ab_a17, 93, AB_A17); 707 EMEV_MUX_PIN(ab_a18, 94, AB_A18); 708 EMEV_MUX_PIN(ab_a19, 95, AB_A19); 709 EMEV_MUX_PIN(ab_a20, 96, AB_A20); 710 EMEV_MUX_PIN(ab_a21, 97, AB_A21); 711 EMEV_MUX_PIN(ab_a22, 98, AB_A22); 712 EMEV_MUX_PIN(ab_a23, 99, AB_A23); 713 EMEV_MUX_PIN(ab_a24, 100, AB_A24); 714 EMEV_MUX_PIN(ab_a25, 101, AB_A25); 715 EMEV_MUX_PIN(ab_a26, 102, AB_A26); 716 EMEV_MUX_PIN(ab_a27, 103, AB_A27); 717 EMEV_MUX_PIN(ab_a28, 104, AB_A28); 718 EMEV_MUX_PIN(ab_ben0, 103, AB_BEN0); 719 EMEV_MUX_PIN(ab_ben1, 104, AB_BEN1); 720 721 /* = [ CAM ] ============== */ 722 EMEV_MUX_PIN(cam_clko, 131, CAM_CLKO); 723 static const unsigned int cam_pins[] = { 724 /* CLKI, VS, HS */ 725 132, 133, 134, 726 /* CAM_YUV[0:7] */ 727 135, 136, 137, 138, 728 139, 140, 141, 142, 729 }; 730 static const unsigned int cam_mux[] = { 731 CAM_CLKI_MARK, CAM_VS_MARK, CAM_HS_MARK, 732 CAM_YUV0_MARK, CAM_YUV1_MARK, CAM_YUV2_MARK, CAM_YUV3_MARK, 733 CAM_YUV4_MARK, CAM_YUV5_MARK, CAM_YUV6_MARK, CAM_YUV7_MARK, 734 }; 735 736 /* = [ CF ] -============== */ 737 static const unsigned int cf_ctrl_pins[] = { 738 /* CSB0, CSB1, IORDB, IOWRB, IORDY, RESET, 739 * A00, A01, A02, INTRQ, INPACKB, CDB1, CDB2 */ 740 71, 72, 73, 74, 741 75, 76, 93, 94, 742 95, 97, 100, 101, 743 102, 744 }; 745 static const unsigned int cf_ctrl_mux[] = { 746 CF_CSB0_MARK, CF_CSB1_MARK, CF_IORDB_MARK, CF_IOWRB_MARK, 747 CF_IORDY_MARK, CF_RESET_MARK, CF_A00_MARK, CF_A01_MARK, 748 CF_A02_MARK, CF_INTRQ_MARK, CF_INPACKB_MARK, CF_CDB1_MARK, 749 CF_CDB2_MARK, 750 }; 751 752 static const unsigned int cf_data_pins[] = { 753 /* CF_D[0:15] */ 754 77, 78, 79, 80, 755 81, 82, 83, 84, 756 85, 86, 87, 88, 757 89, 90, 91, 92, 758 }; 759 static const unsigned int cf_data_mux[] = { 760 CF_D00_MARK, CF_D01_MARK, CF_D02_MARK, CF_D03_MARK, 761 CF_D04_MARK, CF_D05_MARK, CF_D06_MARK, CF_D07_MARK, 762 CF_D08_MARK, CF_D09_MARK, CF_D10_MARK, CF_D11_MARK, 763 CF_D12_MARK, CF_D13_MARK, CF_D14_MARK, CF_D15_MARK, 764 }; 765 766 /* = [ DTV ] ============== */ 767 static const unsigned int dtv_a_pins[] = { 768 /* BCLK, PSYNC, VALID, DATA */ 769 85, 86, 87, 88, 770 }; 771 static const unsigned int dtv_a_mux[] = { 772 DTV_BCLK_A_MARK, DTV_PSYNC_A_MARK, DTV_VALID_A_MARK, DTV_DATA_A_MARK, 773 }; 774 775 static const unsigned int dtv_b_pins[] = { 776 /* BCLK, PSYNC, VALID, DATA */ 777 109, 110, 111, 112, 778 }; 779 static const unsigned int dtv_b_mux[] = { 780 DTV_BCLK_B_MARK, DTV_PSYNC_B_MARK, DTV_VALID_B_MARK, DTV_DATA_B_MARK, 781 }; 782 783 /* = [ IIC0 ] ============= */ 784 static const unsigned int iic0_pins[] = { 785 /* SCL, SDA */ 786 44, 45, 787 }; 788 static const unsigned int iic0_mux[] = { 789 IIC0_SCL_MARK, IIC0_SDA_MARK, 790 }; 791 792 /* = [ IIC1 ] ============= */ 793 static const unsigned int iic1_pins[] = { 794 /* SCL, SDA */ 795 46, 47, 796 }; 797 static const unsigned int iic1_mux[] = { 798 IIC1_SCL_MARK, IIC1_SDA_MARK, 799 }; 800 801 /* = [ JTAG ] ============= */ 802 static const unsigned int jtag_pins[] = { 803 /* SEL, TDO, TDOEN */ 804 2, 151, 152, 805 }; 806 static const unsigned int jtag_mux[] = { 807 JT_SEL_MARK, JT_TDO_MARK, JT_TDOEN_MARK, 808 }; 809 810 /* = [ LCD/YUV ] ========== */ 811 EMEV_MUX_PIN(lcd3_pxclk, 18, LCD3_PXCLK); 812 EMEV_MUX_PIN(lcd3_pxclkb, 19, LCD3_PXCLKB); 813 EMEV_MUX_PIN(lcd3_clk_i, 20, LCD3_CLK_I); 814 815 static const unsigned int lcd3_sync_pins[] = { 816 /* HS, VS, DE */ 817 21, 22, 23, 818 }; 819 static const unsigned int lcd3_sync_mux[] = { 820 LCD3_HS_MARK, LCD3_VS_MARK, LCD3_DE_MARK, 821 }; 822 823 static const unsigned int lcd3_rgb888_pins[] = { 824 /* R[0:7], G[0:7], B[0:7] */ 825 32, 33, 34, 35, 826 36, 37, 38, 39, 827 40, 41, PIN_LCD3_G2, PIN_LCD3_G3, 828 PIN_LCD3_G4, PIN_LCD3_G5, PIN_LCD3_G6, PIN_LCD3_G7, 829 42, 43, PIN_LCD3_B2, PIN_LCD3_B3, 830 PIN_LCD3_B4, PIN_LCD3_B5, PIN_LCD3_B6, PIN_LCD3_B7 831 }; 832 static const unsigned int lcd3_rgb888_mux[] = { 833 LCD3_R0_MARK, LCD3_R1_MARK, LCD3_R2_MARK, LCD3_R3_MARK, 834 LCD3_R4_MARK, LCD3_R5_MARK, LCD3_R6_MARK, LCD3_R7_MARK, 835 LCD3_G0_MARK, LCD3_G1_MARK, LCD3_G2_MARK, LCD3_G3_MARK, 836 LCD3_G4_MARK, LCD3_G5_MARK, LCD3_G6_MARK, LCD3_G7_MARK, 837 LCD3_B0_MARK, LCD3_B1_MARK, LCD3_B2_MARK, LCD3_B3_MARK, 838 LCD3_B4_MARK, LCD3_B5_MARK, LCD3_B6_MARK, LCD3_B7_MARK, 839 }; 840 841 EMEV_MUX_PIN(yuv3_clk_i, 20, YUV3_CLK_I); 842 static const unsigned int yuv3_pins[] = { 843 /* CLK_O, HS, VS, DE */ 844 18, 21, 22, 23, 845 /* YUV3_D[0:15] */ 846 40, 41, PIN_LCD3_G2, PIN_LCD3_G3, 847 PIN_LCD3_G4, PIN_LCD3_G5, PIN_LCD3_G6, PIN_LCD3_G7, 848 42, 43, PIN_LCD3_B2, PIN_LCD3_B3, 849 PIN_LCD3_B4, PIN_LCD3_B5, PIN_LCD3_B6, PIN_LCD3_B7, 850 }; 851 static const unsigned int yuv3_mux[] = { 852 YUV3_CLK_O_MARK, YUV3_HS_MARK, YUV3_VS_MARK, YUV3_DE_MARK, 853 YUV3_D0_MARK, YUV3_D1_MARK, YUV3_D2_MARK, YUV3_D3_MARK, 854 YUV3_D4_MARK, YUV3_D5_MARK, YUV3_D6_MARK, YUV3_D7_MARK, 855 YUV3_D8_MARK, YUV3_D9_MARK, YUV3_D10_MARK, YUV3_D11_MARK, 856 YUV3_D12_MARK, YUV3_D13_MARK, YUV3_D14_MARK, YUV3_D15_MARK, 857 }; 858 859 /* = [ NTSC ] ============= */ 860 EMEV_MUX_PIN(ntsc_clk, 122, NTSC_CLK); 861 static const unsigned int ntsc_data_pins[] = { 862 /* NTSC_DATA[0:7] */ 863 123, 124, 125, 126, 864 127, 128, 129, 130, 865 }; 866 static const unsigned int ntsc_data_mux[] = { 867 NTSC_DATA0_MARK, NTSC_DATA1_MARK, NTSC_DATA2_MARK, NTSC_DATA3_MARK, 868 NTSC_DATA4_MARK, NTSC_DATA5_MARK, NTSC_DATA6_MARK, NTSC_DATA7_MARK, 869 }; 870 871 /* = [ PWM0 ] ============= */ 872 EMEV_MUX_PIN(pwm0, 120, PWM0); 873 874 /* = [ PWM1 ] ============= */ 875 EMEV_MUX_PIN(pwm1, 121, PWM1); 876 877 /* = [ SD ] =============== */ 878 EMEV_MUX_PIN(sd_cki, 48, SD_CKI); 879 880 /* = [ SDIO0 ] ============ */ 881 static const unsigned int sdi0_ctrl_pins[] = { 882 /* CKO, CKI, CMD */ 883 50, 51, 52, 884 }; 885 static const unsigned int sdi0_ctrl_mux[] = { 886 SDI0_CKO_MARK, SDI0_CKI_MARK, SDI0_CMD_MARK, 887 }; 888 889 static const unsigned int sdi0_data_pins[] = { 890 /* SDI0_DATA[0:7] */ 891 53, 54, 55, 56, 892 57, 58, 59, 60 893 }; 894 static const unsigned int sdi0_data_mux[] = { 895 SDI0_DATA0_MARK, SDI0_DATA1_MARK, SDI0_DATA2_MARK, SDI0_DATA3_MARK, 896 SDI0_DATA4_MARK, SDI0_DATA5_MARK, SDI0_DATA6_MARK, SDI0_DATA7_MARK, 897 }; 898 899 /* = [ SDIO1 ] ============ */ 900 static const unsigned int sdi1_ctrl_pins[] = { 901 /* CKO, CKI, CMD */ 902 61, 62, 63, 903 }; 904 static const unsigned int sdi1_ctrl_mux[] = { 905 SDI1_CKO_MARK, SDI1_CKI_MARK, SDI1_CMD_MARK, 906 }; 907 908 static const unsigned int sdi1_data_pins[] = { 909 /* SDI1_DATA[0:3] */ 910 64, 65, 66, 67, 911 }; 912 static const unsigned int sdi1_data_mux[] = { 913 SDI1_DATA0_MARK, SDI1_DATA1_MARK, SDI1_DATA2_MARK, SDI1_DATA3_MARK, 914 }; 915 916 /* = [ SDIO2 ] ============ */ 917 static const unsigned int sdi2_ctrl_pins[] = { 918 /* CKO, CKI, CMD */ 919 97, 98, 99, 920 }; 921 static const unsigned int sdi2_ctrl_mux[] = { 922 SDI2_CKO_MARK, SDI2_CKI_MARK, SDI2_CMD_MARK, 923 }; 924 925 static const unsigned int sdi2_data_pins[] = { 926 /* SDI2_DATA[0:3] */ 927 89, 90, 91, 92, 928 }; 929 static const unsigned int sdi2_data_mux[] = { 930 SDI2_DATA0_MARK, SDI2_DATA1_MARK, SDI2_DATA2_MARK, SDI2_DATA3_MARK, 931 }; 932 933 /* = [ TP33 ] ============= */ 934 static const unsigned int tp33_pins[] = { 935 /* CLK, CTRL */ 936 38, 39, 937 /* TP33_DATA[0:15] */ 938 40, 41, PIN_LCD3_G2, PIN_LCD3_G3, 939 PIN_LCD3_G4, PIN_LCD3_G5, PIN_LCD3_G6, PIN_LCD3_G7, 940 42, 43, PIN_LCD3_B2, PIN_LCD3_B3, 941 PIN_LCD3_B4, PIN_LCD3_B5, PIN_LCD3_B6, PIN_LCD3_B7, 942 }; 943 static const unsigned int tp33_mux[] = { 944 TP33_CLK_MARK, TP33_CTRL_MARK, 945 TP33_DATA0_MARK, TP33_DATA1_MARK, TP33_DATA2_MARK, TP33_DATA3_MARK, 946 TP33_DATA4_MARK, TP33_DATA5_MARK, TP33_DATA6_MARK, TP33_DATA7_MARK, 947 TP33_DATA8_MARK, TP33_DATA9_MARK, TP33_DATA10_MARK, TP33_DATA11_MARK, 948 TP33_DATA12_MARK, TP33_DATA13_MARK, TP33_DATA14_MARK, TP33_DATA15_MARK, 949 }; 950 951 /* = [ UART1 ] ============ */ 952 static const unsigned int uart1_data_pins[] = { 953 /* RX, TX */ 954 155, 156, 955 }; 956 static const unsigned int uart1_data_mux[] = { 957 UART1_RX_MARK, UART1_TX_MARK, 958 }; 959 960 static const unsigned int uart1_ctrl_pins[] = { 961 /* CTSB, RTSB */ 962 157, 158, 963 }; 964 static const unsigned int uart1_ctrl_mux[] = { 965 UART1_CTSB_MARK, UART1_RTSB_MARK, 966 }; 967 968 /* = [ UART2 ] ============ */ 969 static const unsigned int uart2_data_pins[] = { 970 /* RX, TX */ 971 157, 158, 972 }; 973 static const unsigned int uart2_data_mux[] = { 974 UART2_RX_MARK, UART2_TX_MARK, 975 }; 976 977 /* = [ UART3 ] ============ */ 978 static const unsigned int uart3_data_pins[] = { 979 /* RX, TX */ 980 46, 47, 981 }; 982 static const unsigned int uart3_data_mux[] = { 983 UART3_RX_MARK, UART3_TX_MARK, 984 }; 985 986 /* = [ USB ] ============== */ 987 EMEV_MUX_PIN(usb_vbus, 153, USB_VBUS); 988 989 /* = [ USI0 ] ============== */ 990 EMEV_MUX_PIN(usi0_cs1, 105, USI0_CS1); 991 EMEV_MUX_PIN(usi0_cs2, 106, USI0_CS2); 992 EMEV_MUX_PIN(usi0_cs3, 115, USI0_CS3); 993 EMEV_MUX_PIN(usi0_cs4, 116, USI0_CS4); 994 EMEV_MUX_PIN(usi0_cs5, 117, USI0_CS5); 995 EMEV_MUX_PIN(usi0_cs6, 118, USI0_CS6); 996 997 /* = [ USI1 ] ============== */ 998 static const unsigned int usi1_pins[] = { 999 /* DI, DO*/ 1000 107, 108, 1001 }; 1002 static const unsigned int usi1_mux[] = { 1003 USI1_DI_MARK, USI1_DO_MARK, 1004 }; 1005 1006 /* = [ USI2 ] ============== */ 1007 static const unsigned int usi2_pins[] = { 1008 /* CLK, DI, DO*/ 1009 109, 110, 111, 1010 }; 1011 static const unsigned int usi2_mux[] = { 1012 USI2_CLK_MARK, USI2_DI_MARK, USI2_DO_MARK, 1013 }; 1014 EMEV_MUX_PIN(usi2_cs0, 112, USI2_CS0); 1015 EMEV_MUX_PIN(usi2_cs1, 113, USI2_CS1); 1016 EMEV_MUX_PIN(usi2_cs2, 114, USI2_CS2); 1017 1018 /* = [ USI3 ] ============== */ 1019 static const unsigned int usi3_pins[] = { 1020 /* CLK, DI, DO*/ 1021 115, 116, 117, 1022 }; 1023 static const unsigned int usi3_mux[] = { 1024 USI3_CLK_MARK, USI3_DI_MARK, USI3_DO_MARK, 1025 }; 1026 EMEV_MUX_PIN(usi3_cs0, 118, USI3_CS0); 1027 1028 /* = [ USI4 ] ============== */ 1029 static const unsigned int usi4_pins[] = { 1030 /* CLK, DI, DO*/ 1031 119, 120, 121, 1032 }; 1033 static const unsigned int usi4_mux[] = { 1034 USI4_CLK_MARK, USI4_DI_MARK, USI4_DO_MARK, 1035 }; 1036 EMEV_MUX_PIN(usi4_cs0, 113, USI4_CS0); 1037 EMEV_MUX_PIN(usi4_cs1, 114, USI4_CS1); 1038 1039 /* = [ USI5 ] ============== */ 1040 static const unsigned int usi5_a_pins[] = { 1041 /* CLK, DI, DO*/ 1042 85, 86, 87, 1043 }; 1044 static const unsigned int usi5_a_mux[] = { 1045 USI5_CLK_A_MARK, USI5_DI_A_MARK, USI5_DO_A_MARK, 1046 }; 1047 EMEV_MUX_PIN(usi5_cs0_a, 88, USI5_CS0_A); 1048 EMEV_MUX_PIN(usi5_cs1_a, 89, USI5_CS1_A); 1049 EMEV_MUX_PIN(usi5_cs2_a, 90, USI5_CS2_A); 1050 1051 static const unsigned int usi5_b_pins[] = { 1052 /* CLK, DI, DO*/ 1053 143, 144, 150, 1054 }; 1055 static const unsigned int usi5_b_mux[] = { 1056 USI5_CLK_B_MARK, USI5_DI_B_MARK, USI5_DO_B_MARK, 1057 }; 1058 EMEV_MUX_PIN(usi5_cs0_b, 145, USI5_CS0_B); 1059 EMEV_MUX_PIN(usi5_cs1_b, 146, USI5_CS1_B); 1060 EMEV_MUX_PIN(usi5_cs2_b, 147, USI5_CS2_B); 1061 EMEV_MUX_PIN(usi5_cs3_b, 148, USI5_CS3_B); 1062 EMEV_MUX_PIN(usi5_cs4_b, 149, USI5_CS4_B); 1063 1064 static const struct sh_pfc_pin_group pinmux_groups[] = { 1065 SH_PFC_PIN_GROUP(err_rst_reqb), 1066 SH_PFC_PIN_GROUP(ref_clko), 1067 SH_PFC_PIN_GROUP(ext_clki), 1068 SH_PFC_PIN_GROUP(lowpwr), 1069 1070 SH_PFC_PIN_GROUP(ab_main), 1071 SH_PFC_PIN_GROUP(ab_clk), 1072 SH_PFC_PIN_GROUP(ab_csb0), 1073 SH_PFC_PIN_GROUP(ab_csb1), 1074 SH_PFC_PIN_GROUP(ab_csb2), 1075 SH_PFC_PIN_GROUP(ab_csb3), 1076 SH_PFC_PIN_GROUP(ab_wait), 1077 SH_PFC_PIN_GROUP(ab_adv), 1078 SH_PFC_PIN_GROUP(ab_a17), 1079 SH_PFC_PIN_GROUP(ab_a18), 1080 SH_PFC_PIN_GROUP(ab_a19), 1081 SH_PFC_PIN_GROUP(ab_a20), 1082 SH_PFC_PIN_GROUP(ab_a21), 1083 SH_PFC_PIN_GROUP(ab_a22), 1084 SH_PFC_PIN_GROUP(ab_a23), 1085 SH_PFC_PIN_GROUP(ab_a24), 1086 SH_PFC_PIN_GROUP(ab_a25), 1087 SH_PFC_PIN_GROUP(ab_a26), 1088 SH_PFC_PIN_GROUP(ab_a27), 1089 SH_PFC_PIN_GROUP(ab_a28), 1090 SH_PFC_PIN_GROUP(ab_ben0), 1091 SH_PFC_PIN_GROUP(ab_ben1), 1092 1093 SH_PFC_PIN_GROUP(cam_clko), 1094 SH_PFC_PIN_GROUP(cam), 1095 1096 SH_PFC_PIN_GROUP(cf_ctrl), 1097 BUS_DATA_PIN_GROUP(cf_data, 8), 1098 BUS_DATA_PIN_GROUP(cf_data, 16), 1099 1100 SH_PFC_PIN_GROUP(dtv_a), 1101 SH_PFC_PIN_GROUP(dtv_b), 1102 1103 SH_PFC_PIN_GROUP(iic0), 1104 1105 SH_PFC_PIN_GROUP(iic1), 1106 1107 SH_PFC_PIN_GROUP(jtag), 1108 1109 SH_PFC_PIN_GROUP(lcd3_pxclk), 1110 SH_PFC_PIN_GROUP(lcd3_pxclkb), 1111 SH_PFC_PIN_GROUP(lcd3_clk_i), 1112 SH_PFC_PIN_GROUP(lcd3_sync), 1113 SH_PFC_PIN_GROUP(lcd3_rgb888), 1114 SH_PFC_PIN_GROUP(yuv3_clk_i), 1115 SH_PFC_PIN_GROUP(yuv3), 1116 1117 SH_PFC_PIN_GROUP(ntsc_clk), 1118 SH_PFC_PIN_GROUP(ntsc_data), 1119 1120 SH_PFC_PIN_GROUP(pwm0), 1121 1122 SH_PFC_PIN_GROUP(pwm1), 1123 1124 SH_PFC_PIN_GROUP(sd_cki), 1125 1126 SH_PFC_PIN_GROUP(sdi0_ctrl), 1127 BUS_DATA_PIN_GROUP(sdi0_data, 1), 1128 BUS_DATA_PIN_GROUP(sdi0_data, 4), 1129 BUS_DATA_PIN_GROUP(sdi0_data, 8), 1130 1131 SH_PFC_PIN_GROUP(sdi1_ctrl), 1132 BUS_DATA_PIN_GROUP(sdi1_data, 1), 1133 BUS_DATA_PIN_GROUP(sdi1_data, 4), 1134 1135 SH_PFC_PIN_GROUP(sdi2_ctrl), 1136 BUS_DATA_PIN_GROUP(sdi2_data, 1), 1137 BUS_DATA_PIN_GROUP(sdi2_data, 4), 1138 1139 SH_PFC_PIN_GROUP(tp33), 1140 1141 SH_PFC_PIN_GROUP(uart1_data), 1142 SH_PFC_PIN_GROUP(uart1_ctrl), 1143 1144 SH_PFC_PIN_GROUP(uart2_data), 1145 1146 SH_PFC_PIN_GROUP(uart3_data), 1147 1148 SH_PFC_PIN_GROUP(usb_vbus), 1149 1150 SH_PFC_PIN_GROUP(usi0_cs1), 1151 SH_PFC_PIN_GROUP(usi0_cs2), 1152 SH_PFC_PIN_GROUP(usi0_cs3), 1153 SH_PFC_PIN_GROUP(usi0_cs4), 1154 SH_PFC_PIN_GROUP(usi0_cs5), 1155 SH_PFC_PIN_GROUP(usi0_cs6), 1156 1157 SH_PFC_PIN_GROUP(usi1), 1158 1159 SH_PFC_PIN_GROUP(usi2), 1160 SH_PFC_PIN_GROUP(usi2_cs0), 1161 SH_PFC_PIN_GROUP(usi2_cs1), 1162 SH_PFC_PIN_GROUP(usi2_cs2), 1163 1164 SH_PFC_PIN_GROUP(usi3), 1165 SH_PFC_PIN_GROUP(usi3_cs0), 1166 1167 SH_PFC_PIN_GROUP(usi4), 1168 SH_PFC_PIN_GROUP(usi4_cs0), 1169 SH_PFC_PIN_GROUP(usi4_cs1), 1170 1171 SH_PFC_PIN_GROUP(usi5_a), 1172 SH_PFC_PIN_GROUP(usi5_cs0_a), 1173 SH_PFC_PIN_GROUP(usi5_cs1_a), 1174 SH_PFC_PIN_GROUP(usi5_cs2_a), 1175 SH_PFC_PIN_GROUP(usi5_b), 1176 SH_PFC_PIN_GROUP(usi5_cs0_b), 1177 SH_PFC_PIN_GROUP(usi5_cs1_b), 1178 SH_PFC_PIN_GROUP(usi5_cs2_b), 1179 SH_PFC_PIN_GROUP(usi5_cs3_b), 1180 SH_PFC_PIN_GROUP(usi5_cs4_b), 1181 }; 1182 1183 static const char * const ab_groups[] = { 1184 "ab_main", 1185 "ab_clk", 1186 "ab_csb0", 1187 "ab_csb1", 1188 "ab_csb2", 1189 "ab_csb3", 1190 "ab_wait", 1191 "ab_adv", 1192 "ab_a17", 1193 "ab_a18", 1194 "ab_a19", 1195 "ab_a20", 1196 "ab_a21", 1197 "ab_a22", 1198 "ab_a23", 1199 "ab_a24", 1200 "ab_a25", 1201 "ab_a26", 1202 "ab_a27", 1203 "ab_a28", 1204 "ab_ben0", 1205 "ab_ben1", 1206 }; 1207 1208 static const char * const cam_groups[] = { 1209 "cam_clko", 1210 "cam", 1211 }; 1212 1213 static const char * const cf_groups[] = { 1214 "cf_ctrl", 1215 "cf_data8", 1216 "cf_data16", 1217 }; 1218 1219 static const char * const dtv_groups[] = { 1220 "dtv_a", 1221 "dtv_b", 1222 }; 1223 1224 static const char * const err_rst_reqb_groups[] = { 1225 "err_rst_reqb", 1226 }; 1227 1228 static const char * const ext_clki_groups[] = { 1229 "ext_clki", 1230 }; 1231 1232 static const char * const iic0_groups[] = { 1233 "iic0", 1234 }; 1235 1236 static const char * const iic1_groups[] = { 1237 "iic1", 1238 }; 1239 1240 static const char * const jtag_groups[] = { 1241 "jtag", 1242 }; 1243 1244 static const char * const lcd_groups[] = { 1245 "lcd3_pxclk", 1246 "lcd3_pxclkb", 1247 "lcd3_clk_i", 1248 "lcd3_sync", 1249 "lcd3_rgb888", 1250 "yuv3_clk_i", 1251 "yuv3", 1252 }; 1253 1254 static const char * const lowpwr_groups[] = { 1255 "lowpwr", 1256 }; 1257 1258 static const char * const ntsc_groups[] = { 1259 "ntsc_clk", 1260 "ntsc_data", 1261 }; 1262 1263 static const char * const pwm0_groups[] = { 1264 "pwm0", 1265 }; 1266 1267 static const char * const pwm1_groups[] = { 1268 "pwm1", 1269 }; 1270 1271 static const char * const ref_clko_groups[] = { 1272 "ref_clko", 1273 }; 1274 1275 static const char * const sd_groups[] = { 1276 "sd_cki", 1277 }; 1278 1279 static const char * const sdi0_groups[] = { 1280 "sdi0_ctrl", 1281 "sdi0_data1", 1282 "sdi0_data4", 1283 "sdi0_data8", 1284 }; 1285 1286 static const char * const sdi1_groups[] = { 1287 "sdi1_ctrl", 1288 "sdi1_data1", 1289 "sdi1_data4", 1290 }; 1291 1292 static const char * const sdi2_groups[] = { 1293 "sdi2_ctrl", 1294 "sdi2_data1", 1295 "sdi2_data4", 1296 }; 1297 1298 static const char * const tp33_groups[] = { 1299 "tp33", 1300 }; 1301 1302 static const char * const uart1_groups[] = { 1303 "uart1_data", 1304 "uart1_ctrl", 1305 }; 1306 1307 static const char * const uart2_groups[] = { 1308 "uart2_data", 1309 }; 1310 1311 static const char * const uart3_groups[] = { 1312 "uart3_data", 1313 }; 1314 1315 static const char * const usb_groups[] = { 1316 "usb_vbus", 1317 }; 1318 1319 static const char * const usi0_groups[] = { 1320 "usi0_cs1", 1321 "usi0_cs2", 1322 "usi0_cs3", 1323 "usi0_cs4", 1324 "usi0_cs5", 1325 "usi0_cs6", 1326 }; 1327 1328 static const char * const usi1_groups[] = { 1329 "usi1", 1330 }; 1331 1332 static const char * const usi2_groups[] = { 1333 "usi2", 1334 "usi2_cs0", 1335 "usi2_cs1", 1336 "usi2_cs2", 1337 }; 1338 1339 static const char * const usi3_groups[] = { 1340 "usi3", 1341 "usi3_cs0", 1342 }; 1343 1344 static const char * const usi4_groups[] = { 1345 "usi4", 1346 "usi4_cs0", 1347 "usi4_cs1", 1348 }; 1349 1350 static const char * const usi5_groups[] = { 1351 "usi5_a", 1352 "usi5_cs0_a", 1353 "usi5_cs1_a", 1354 "usi5_cs2_a", 1355 "usi5_b", 1356 "usi5_cs0_b", 1357 "usi5_cs1_b", 1358 "usi5_cs2_b", 1359 "usi5_cs3_b", 1360 "usi5_cs4_b", 1361 }; 1362 1363 static const struct sh_pfc_function pinmux_functions[] = { 1364 SH_PFC_FUNCTION(ab), 1365 SH_PFC_FUNCTION(cam), 1366 SH_PFC_FUNCTION(cf), 1367 SH_PFC_FUNCTION(dtv), 1368 SH_PFC_FUNCTION(err_rst_reqb), 1369 SH_PFC_FUNCTION(ext_clki), 1370 SH_PFC_FUNCTION(iic0), 1371 SH_PFC_FUNCTION(iic1), 1372 SH_PFC_FUNCTION(jtag), 1373 SH_PFC_FUNCTION(lcd), 1374 SH_PFC_FUNCTION(lowpwr), 1375 SH_PFC_FUNCTION(ntsc), 1376 SH_PFC_FUNCTION(pwm0), 1377 SH_PFC_FUNCTION(pwm1), 1378 SH_PFC_FUNCTION(ref_clko), 1379 SH_PFC_FUNCTION(sd), 1380 SH_PFC_FUNCTION(sdi0), 1381 SH_PFC_FUNCTION(sdi1), 1382 SH_PFC_FUNCTION(sdi2), 1383 SH_PFC_FUNCTION(tp33), 1384 SH_PFC_FUNCTION(uart1), 1385 SH_PFC_FUNCTION(uart2), 1386 SH_PFC_FUNCTION(uart3), 1387 SH_PFC_FUNCTION(usb), 1388 SH_PFC_FUNCTION(usi0), 1389 SH_PFC_FUNCTION(usi1), 1390 SH_PFC_FUNCTION(usi2), 1391 SH_PFC_FUNCTION(usi3), 1392 SH_PFC_FUNCTION(usi4), 1393 SH_PFC_FUNCTION(usi5), 1394 }; 1395 1396 static const struct pinmux_cfg_reg pinmux_config_regs[] = { 1397 { PINMUX_CFG_REG("GPSR0", 0xe0140200, 32, 1, GROUP( 1398 0, PORT31_FN, /* PIN: J18 */ 1399 0, PORT30_FN, /* PIN: H18 */ 1400 0, PORT29_FN, /* PIN: G18 */ 1401 0, PORT28_FN, /* PIN: F18 */ 1402 0, PORT27_FN, /* PIN: F17 */ 1403 0, PORT26_FN, /* PIN: F16 */ 1404 0, PORT25_FN, /* PIN: E20 */ 1405 0, PORT24_FN, /* PIN: D20 */ 1406 FN_LCD3_1_0_PORT23, PORT23_FN, /* PIN: D19 */ 1407 FN_LCD3_1_0_PORT22, PORT22_FN, /* PIN: C20 */ 1408 FN_LCD3_1_0_PORT21, PORT21_FN, /* PIN: B21 */ 1409 FN_LCD3_1_0_PORT20, PORT20_FN, /* PIN: A21 */ 1410 FN_LCD3_PXCLKB, PORT19_FN, /* PIN: C21 */ 1411 FN_LCD3_1_0_PORT18, PORT18_FN, /* PIN: B22 */ 1412 0, PORT17_FN, /* PIN: W20 */ 1413 0, PORT16_FN, /* PIN: W21 */ 1414 0, PORT15_FN, /* PIN: Y19 */ 1415 0, PORT14_FN, /* PIN: Y20 */ 1416 0, PORT13_FN, /* PIN: Y21 */ 1417 0, PORT12_FN, /* PIN: AA20 */ 1418 0, PORT11_FN, /* PIN: AA21 */ 1419 0, PORT10_FN, /* PIN: AA22 */ 1420 0, PORT9_FN, /* PIN: V15 */ 1421 0, PORT8_FN, /* PIN: V16 */ 1422 0, PORT7_FN, /* PIN: V17 */ 1423 0, PORT6_FN, /* PIN: V18 */ 1424 FN_EXT_CLKI, PORT5_FN, /* PIN: U8 */ 1425 FN_REF_CLKO, PORT4_FN, /* PIN: V8 */ 1426 FN_ERR_RST_REQB, PORT3_FN, /* PIN: U9 */ 1427 FN_JT_SEL, PORT2_FN, /* PIN: V9 */ 1428 0, PORT1_FN, /* PIN: U10 */ 1429 0, PORT0_FN, /* PIN: V10 */ 1430 )) 1431 }, 1432 { PINMUX_CFG_REG("GPSR1", 0xe0140204, 32, 1, GROUP( 1433 FN_SDI1_CMD, PORT63_FN, /* PIN: AC21 */ 1434 FN_SDI1_CKI, PORT62_FN, /* PIN: AA23 */ 1435 FN_SDI1_CKO, PORT61_FN, /* PIN: AB22 */ 1436 FN_SDI0_DATA7, PORT60_FN, /* PIN: Y16 */ 1437 FN_SDI0_DATA6, PORT59_FN, /* PIN: AA16 */ 1438 FN_SDI0_DATA5, PORT58_FN, /* PIN: Y15 */ 1439 FN_SDI0_DATA4, PORT57_FN, /* PIN: AA15 */ 1440 FN_SDI0_DATA3, PORT56_FN, /* PIN: Y14 */ 1441 FN_SDI0_DATA2, PORT55_FN, /* PIN: AA14 */ 1442 FN_SDI0_DATA1, PORT54_FN, /* PIN: Y13 */ 1443 FN_SDI0_DATA0, PORT53_FN, /* PIN: AA13 */ 1444 FN_SDI0_CMD, PORT52_FN, /* PIN: Y12 */ 1445 FN_SDI0_CKI, PORT51_FN, /* PIN: AC18 */ 1446 FN_SDI0_CKO, PORT50_FN, /* PIN: AB18 */ 1447 0, PORT49_FN, /* PIN: AB16 */ 1448 FN_SD_CKI, PORT48_FN, /* PIN: AC19 */ 1449 FN_IIC_1_0_PORT47, PORT47_FN, /* PIN: Y8 */ 1450 FN_IIC_1_0_PORT46, PORT46_FN, /* PIN: Y9 */ 1451 FN_IIC0_SDA, PORT45_FN, /* PIN: AA8 */ 1452 FN_IIC0_SCL, PORT44_FN, /* PIN: AA9 */ 1453 FN_LCD3_11_10_PORT43, PORT43_FN, /* PIN: A15 */ 1454 FN_LCD3_11_10_PORT42, PORT42_FN, /* PIN: A16 */ 1455 FN_LCD3_11_10_PORT41, PORT41_FN, /* PIN: A17 */ 1456 FN_LCD3_11_10_PORT40, PORT40_FN, /* PIN: A18 */ 1457 FN_LCD3_9_8_PORT39, PORT39_FN, /* PIN: D18 */ 1458 FN_LCD3_9_8_PORT38, PORT38_FN, /* PIN: C18 */ 1459 FN_LCD3_R5, PORT37_FN, /* PIN: B18 */ 1460 FN_LCD3_R4, PORT36_FN, /* PIN: C19 */ 1461 FN_LCD3_R3, PORT35_FN, /* PIN: B19 */ 1462 FN_LCD3_R2, PORT34_FN, /* PIN: A19 */ 1463 FN_LCD3_R1, PORT33_FN, /* PIN: B20 */ 1464 FN_LCD3_R0, PORT32_FN, /* PIN: A20 */ 1465 )) 1466 }, 1467 { PINMUX_CFG_REG("GPSR2", 0xe0140208, 32, 1, GROUP( 1468 FN_AB_1_0_PORT95, PORT95_FN, /* PIN: L21 */ 1469 FN_AB_1_0_PORT94, PORT94_FN, /* PIN: K21 */ 1470 FN_AB_1_0_PORT93, PORT93_FN, /* PIN: J21 */ 1471 FN_AB_7_6_PORT92, PORT92_FN, /* PIN: J22 */ 1472 FN_AB_7_6_PORT91, PORT91_FN, /* PIN: H21 */ 1473 FN_AB_5_4_PORT90, PORT90_FN, /* PIN: H22 */ 1474 FN_AB_5_4_PORT89, PORT89_FN, /* PIN: H23 */ 1475 FN_AB_3_2_PORT88, PORT88_FN, /* PIN: G21 */ 1476 FN_AB_3_2_PORT87, PORT87_FN, /* PIN: G22 */ 1477 FN_AB_3_2_PORT86, PORT86_FN, /* PIN: G23 */ 1478 FN_AB_3_2_PORT85, PORT85_FN, /* PIN: F21 */ 1479 FN_AB_1_0_PORT84, PORT84_FN, /* PIN: F22 */ 1480 FN_AB_1_0_PORT83, PORT83_FN, /* PIN: F23 */ 1481 FN_AB_1_0_PORT82, PORT82_FN, /* PIN: E22 */ 1482 FN_AB_1_0_PORT81, PORT81_FN, /* PIN: E23 */ 1483 FN_AB_1_0_PORT80, PORT80_FN, /* PIN: D22 */ 1484 FN_AB_1_0_PORT79, PORT79_FN, /* PIN: D23 */ 1485 FN_AB_1_0_PORT78, PORT78_FN, /* PIN: C22 */ 1486 FN_AB_1_0_PORT77, PORT77_FN, /* PIN: C23 */ 1487 FN_AB_1_0_PORT76, PORT76_FN, /* PIN: K20 */ 1488 FN_AB_1_0_PORT75, PORT75_FN, /* PIN: L20 */ 1489 FN_AB_1_0_PORT74, PORT74_FN, /* PIN: H20 */ 1490 FN_AB_1_0_PORT73, PORT73_FN, /* PIN: J20 */ 1491 FN_AB_1_0_PORT72, PORT72_FN, /* PIN: G20 */ 1492 FN_AB_1_0_PORT71, PORT71_FN, /* PIN: F20 */ 1493 FN_AB_CSB1, PORT70_FN, /* PIN: E21 */ 1494 FN_AB_CSB0, PORT69_FN, /* PIN: D21 */ 1495 FN_AB_CLK, PORT68_FN, /* PIN: J23 */ 1496 FN_SDI1_DATA3, PORT67_FN, /* PIN: AA19 */ 1497 FN_SDI1_DATA2, PORT66_FN, /* PIN: AB19 */ 1498 FN_SDI1_DATA1, PORT65_FN, /* PIN: AB20 */ 1499 FN_SDI1_DATA0, PORT64_FN, /* PIN: AB21 */ 1500 )) 1501 }, 1502 { PINMUX_CFG_REG("GPSR3", 0xe014020c, 32, 1, GROUP( 1503 FN_NTSC_DATA4, PORT127_FN, /* PIN: T20 */ 1504 FN_NTSC_DATA3, PORT126_FN, /* PIN: R18 */ 1505 FN_NTSC_DATA2, PORT125_FN, /* PIN: R20 */ 1506 FN_NTSC_DATA1, PORT124_FN, /* PIN: P18 */ 1507 FN_NTSC_DATA0, PORT123_FN, /* PIN: P20 */ 1508 FN_NTSC_CLK, PORT122_FN, /* PIN: V20 */ 1509 FN_USI_9_8_PORT121, PORT121_FN, /* PIN: Y5 */ 1510 FN_USI_9_8_PORT120, PORT120_FN, /* PIN: AA4 */ 1511 FN_USI_7_6_PORT119, PORT119_FN, /* PIN: AB3 */ 1512 FN_USI_5_4_PORT118, PORT118_FN, /* PIN: AB4 */ 1513 FN_USI_5_4_PORT117, PORT117_FN, /* PIN: AC3 */ 1514 FN_USI_5_4_PORT116, PORT116_FN, /* PIN: AC4 */ 1515 FN_USI_5_4_PORT115, PORT115_FN, /* PIN: AC5 */ 1516 FN_USI_3_2_PORT114, PORT114_FN, /* PIN: Y6 */ 1517 FN_USI_3_2_PORT113, PORT113_FN, /* PIN: AA7 */ 1518 FN_USI_1_0_PORT112, PORT112_FN, /* PIN: Y7 */ 1519 FN_USI_1_0_PORT111, PORT111_FN, /* PIN: AA5 */ 1520 FN_USI_1_0_PORT110, PORT110_FN, /* PIN: AA6 */ 1521 FN_USI_1_0_PORT109, PORT109_FN, /* PIN: AB5 */ 1522 FN_USI1_DO, PORT108_FN, /* PIN: D10 */ 1523 FN_USI1_DI, PORT107_FN, /* PIN: C10 */ 1524 FN_USI0_CS2, PORT106_FN, /* PIN: B9 */ 1525 FN_USI0_CS1, PORT105_FN, /* PIN: B8 */ 1526 FN_AB_13_12_PORT104, PORT104_FN, /* PIN: M17 */ 1527 FN_AB_13_12_PORT103, PORT103_FN, /* PIN: L17 */ 1528 FN_AB_11_10_PORT102, PORT102_FN, /* PIN: N18 */ 1529 FN_AB_11_10_PORT101, PORT101_FN, /* PIN: M18 */ 1530 FN_AB_11_10_PORT100, PORT100_FN, /* PIN: L18 */ 1531 FN_AB_9_8_PORT99, PORT99_FN, /* PIN: N20 */ 1532 FN_AB_9_8_PORT98, PORT98_FN, /* PIN: M20 */ 1533 FN_AB_9_8_PORT97, PORT97_FN, /* PIN: N21 */ 1534 FN_AB_A20, PORT96_FN, /* PIN: M21 */ 1535 )) 1536 }, 1537 { PINMUX_CFG_REG("GPSR4", 0xe0140210, 32, 1, GROUP( 1538 0, 0, 1539 FN_UART_1_0_PORT158, PORT158_FN, /* PIN: AB10 */ 1540 FN_UART_1_0_PORT157, PORT157_FN, /* PIN: AA10 */ 1541 FN_UART1_TX, PORT156_FN, /* PIN: Y10 */ 1542 FN_UART1_RX, PORT155_FN, /* PIN: Y11 */ 1543 FN_LOWPWR, PORT154_FN, /* PIN: A12 */ 1544 FN_USB_VBUS, PORT153_FN, /* PIN: AA12 */ 1545 FN_JT_TDOEN, PORT152_FN, /* PIN: F13 */ 1546 FN_JT_TDO, PORT151_FN, /* PIN: D13 */ 1547 FN_HSI_1_0_PORT150, PORT150_FN, /* PIN: M22 */ 1548 FN_HSI_1_0_PORT149, PORT149_FN, /* PIN: M23 */ 1549 FN_HSI_1_0_PORT148, PORT148_FN, /* PIN: N23 */ 1550 FN_HSI_1_0_PORT147, PORT147_FN, /* PIN: N22 */ 1551 FN_HSI_1_0_PORT146, PORT146_FN, /* PIN: L22 */ 1552 FN_HSI_1_0_PORT145, PORT145_FN, /* PIN: L23 */ 1553 FN_HSI_1_0_PORT144, PORT144_FN, /* PIN: K23 */ 1554 FN_HSI_1_0_PORT143, PORT143_FN, /* PIN: K22 */ 1555 FN_CAM_YUV7, PORT142_FN, /* PIN: V23 */ 1556 FN_CAM_YUV6, PORT141_FN, /* PIN: V22 */ 1557 FN_CAM_YUV5, PORT140_FN, /* PIN: U23 */ 1558 FN_CAM_YUV4, PORT139_FN, /* PIN: U22 */ 1559 FN_CAM_YUV3, PORT138_FN, /* PIN: U21 */ 1560 FN_CAM_YUV2, PORT137_FN, /* PIN: T23 */ 1561 FN_CAM_YUV1, PORT136_FN, /* PIN: T22 */ 1562 FN_CAM_YUV0, PORT135_FN, /* PIN: T21 */ 1563 FN_CAM_HS, PORT134_FN, /* PIN: V21 */ 1564 FN_CAM_VS, PORT133_FN, /* PIN: W22 */ 1565 FN_CAM_CLKI, PORT132_FN, /* PIN: Y23 */ 1566 FN_CAM_CLKO, PORT131_FN, /* PIN: W23 */ 1567 FN_NTSC_DATA7, PORT130_FN, /* PIN: U18 */ 1568 FN_NTSC_DATA6, PORT129_FN, /* PIN: U20 */ 1569 FN_NTSC_DATA5, PORT128_FN, /* PIN: T18 */ 1570 )) 1571 }, 1572 { PINMUX_CFG_REG_VAR("CHG_PINSEL_LCD3", 0xe0140284, 32, 1573 GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1574 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 1575 2, 2), 1576 GROUP( 1577 /* 31 - 12 */ 1578 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1579 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1580 0, 0, 0, 0, 0, 0, 0, 0, 1581 /* 11 - 10 */ 1582 FN_SEL_LCD3_11_10_00, FN_SEL_LCD3_11_10_01, 1583 FN_SEL_LCD3_11_10_10, 0, 1584 /* 9 - 8 */ 1585 FN_SEL_LCD3_9_8_00, 0, FN_SEL_LCD3_9_8_10, 0, 1586 /* 7 - 2 */ 1587 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1588 /* 1 - 0 */ 1589 FN_SEL_LCD3_1_0_00, FN_SEL_LCD3_1_0_01, 0, 0, 1590 )) 1591 }, 1592 { PINMUX_CFG_REG_VAR("CHG_PINSEL_UART", 0xe0140288, 32, 1593 GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1594 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1595 1, 1, 1, 1, 1, 1, 2), 1596 GROUP( 1597 /* 31 - 2 */ 1598 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1599 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1600 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1601 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1602 /* 1 - 0 */ 1603 FN_SEL_UART_1_0_00, FN_SEL_UART_1_0_01, 0, 0, 1604 )) 1605 }, 1606 { PINMUX_CFG_REG_VAR("CHG_PINSEL_IIC", 0xe014028c, 32, 1607 GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1608 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1609 1, 1, 1, 1, 1, 1, 2), 1610 GROUP( 1611 /* 31 - 2 */ 1612 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1613 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1614 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1615 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1616 /* 1 - 0 */ 1617 FN_SEL_IIC_1_0_00, FN_SEL_IIC_1_0_01, 0, 0, 1618 )) 1619 }, 1620 { PINMUX_CFG_REG_VAR("CHG_PINSEL_AB", 0xe0140294, 32, 1621 GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1622 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2), 1623 GROUP( 1624 /* 31 - 14 */ 1625 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1626 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1627 0, 0, 0, 0, 1628 /* 13 - 12 */ 1629 FN_SEL_AB_13_12_00, 0, FN_SEL_AB_13_12_10, 0, 1630 /* 11 - 10 */ 1631 FN_SEL_AB_11_10_00, 0, FN_SEL_AB_11_10_10, 0, 1632 /* 9 - 8 */ 1633 FN_SEL_AB_9_8_00, FN_SEL_AB_9_8_01, FN_SEL_AB_9_8_10, 0, 1634 /* 7 - 6 */ 1635 FN_SEL_AB_7_6_00, FN_SEL_AB_7_6_01, FN_SEL_AB_7_6_10, 0, 1636 /* 5 - 4 */ 1637 FN_SEL_AB_5_4_00, FN_SEL_AB_5_4_01, 1638 FN_SEL_AB_5_4_10, FN_SEL_AB_5_4_11, 1639 /* 3 - 2 */ 1640 FN_SEL_AB_3_2_00, FN_SEL_AB_3_2_01, 1641 FN_SEL_AB_3_2_10, FN_SEL_AB_3_2_11, 1642 /* 1 - 0 */ 1643 FN_SEL_AB_1_0_00, 0, FN_SEL_AB_1_0_10, 0, 1644 )) 1645 }, 1646 { PINMUX_CFG_REG_VAR("CHG_PINSEL_USI", 0xe0140298, 32, 1647 GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1648 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 1649 2, 2, 2), 1650 GROUP( 1651 /* 31 - 10 */ 1652 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1653 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1654 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1655 /* 9 - 8 */ 1656 FN_SEL_USI_9_8_00, FN_SEL_USI_9_8_01, 0, 0, 1657 /* 7 - 6 */ 1658 FN_SEL_USI_7_6_00, FN_SEL_USI_7_6_01, 0, 0, 1659 /* 5 - 4 */ 1660 FN_SEL_USI_5_4_00, FN_SEL_USI_5_4_01, 0, 0, 1661 /* 3 - 2 */ 1662 FN_SEL_USI_3_2_00, FN_SEL_USI_3_2_01, 0, 0, 1663 /* 1 - 0 */ 1664 FN_SEL_USI_1_0_00, FN_SEL_USI_1_0_01, 0, 0, 1665 )) 1666 }, 1667 { PINMUX_CFG_REG_VAR("CHG_PINSEL_HSI", 0xe01402a8, 32, 1668 GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1669 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1670 1, 1, 1, 1, 1, 1, 2), 1671 GROUP( 1672 /* 31 - 2 */ 1673 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1674 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1675 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1676 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1677 /* 1 - 0 */ 1678 FN_SEL_HSI_1_0_00, FN_SEL_HSI_1_0_01, 0, 0, 1679 )) 1680 }, 1681 { }, 1682 }; 1683 1684 const struct sh_pfc_soc_info emev2_pinmux_info = { 1685 .name = "emev2_pfc", 1686 1687 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 1688 1689 .pins = pinmux_pins, 1690 .nr_pins = ARRAY_SIZE(pinmux_pins), 1691 .groups = pinmux_groups, 1692 .nr_groups = ARRAY_SIZE(pinmux_groups), 1693 .functions = pinmux_functions, 1694 .nr_functions = ARRAY_SIZE(pinmux_functions), 1695 1696 .cfg_regs = pinmux_config_regs, 1697 1698 .pinmux_data = pinmux_data, 1699 .pinmux_data_size = ARRAY_SIZE(pinmux_data), 1700 }; 1701