1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Pin Control and GPIO driver for SuperH Pin Function Controller. 4 * 5 * Authors: Magnus Damm, Paul Mundt, Laurent Pinchart 6 * 7 * Copyright (C) 2008 Magnus Damm 8 * Copyright (C) 2009 - 2012 Paul Mundt 9 */ 10 11 #define DRV_NAME "sh-pfc" 12 13 #include <linux/bitops.h> 14 #include <linux/err.h> 15 #include <linux/errno.h> 16 #include <linux/io.h> 17 #include <linux/ioport.h> 18 #include <linux/kernel.h> 19 #include <linux/init.h> 20 #include <linux/of.h> 21 #include <linux/of_device.h> 22 #include <linux/pinctrl/machine.h> 23 #include <linux/platform_device.h> 24 #include <linux/psci.h> 25 #include <linux/slab.h> 26 #include <linux/sys_soc.h> 27 28 #include "core.h" 29 30 static int sh_pfc_map_resources(struct sh_pfc *pfc, 31 struct platform_device *pdev) 32 { 33 struct sh_pfc_window *windows; 34 unsigned int *irqs = NULL; 35 unsigned int num_windows; 36 struct resource *res; 37 unsigned int i; 38 int num_irqs; 39 40 /* Count the MEM and IRQ resources. */ 41 for (num_windows = 0;; num_windows++) { 42 res = platform_get_resource(pdev, IORESOURCE_MEM, num_windows); 43 if (!res) 44 break; 45 } 46 if (num_windows == 0) 47 return -EINVAL; 48 49 num_irqs = platform_irq_count(pdev); 50 if (num_irqs < 0) 51 return num_irqs; 52 53 /* Allocate memory windows and IRQs arrays. */ 54 windows = devm_kcalloc(pfc->dev, num_windows, sizeof(*windows), 55 GFP_KERNEL); 56 if (windows == NULL) 57 return -ENOMEM; 58 59 pfc->num_windows = num_windows; 60 pfc->windows = windows; 61 62 if (num_irqs) { 63 irqs = devm_kcalloc(pfc->dev, num_irqs, sizeof(*irqs), 64 GFP_KERNEL); 65 if (irqs == NULL) 66 return -ENOMEM; 67 68 pfc->num_irqs = num_irqs; 69 pfc->irqs = irqs; 70 } 71 72 /* Fill them. */ 73 for (i = 0; i < num_windows; i++) { 74 res = platform_get_resource(pdev, IORESOURCE_MEM, i); 75 windows->phys = res->start; 76 windows->size = resource_size(res); 77 windows->virt = devm_ioremap_resource(pfc->dev, res); 78 if (IS_ERR(windows->virt)) 79 return -ENOMEM; 80 windows++; 81 } 82 for (i = 0; i < num_irqs; i++) 83 *irqs++ = platform_get_irq(pdev, i); 84 85 return 0; 86 } 87 88 static void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc, u32 reg) 89 { 90 struct sh_pfc_window *window; 91 phys_addr_t address = reg; 92 unsigned int i; 93 94 /* scan through physical windows and convert address */ 95 for (i = 0; i < pfc->num_windows; i++) { 96 window = pfc->windows + i; 97 98 if (address < window->phys) 99 continue; 100 101 if (address >= (window->phys + window->size)) 102 continue; 103 104 return window->virt + (address - window->phys); 105 } 106 107 BUG(); 108 return NULL; 109 } 110 111 int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin) 112 { 113 unsigned int offset; 114 unsigned int i; 115 116 for (i = 0, offset = 0; i < pfc->nr_ranges; ++i) { 117 const struct sh_pfc_pin_range *range = &pfc->ranges[i]; 118 119 if (pin <= range->end) 120 return pin >= range->start 121 ? offset + pin - range->start : -1; 122 123 offset += range->end - range->start + 1; 124 } 125 126 return -EINVAL; 127 } 128 129 static int sh_pfc_enum_in_range(u16 enum_id, const struct pinmux_range *r) 130 { 131 if (enum_id < r->begin) 132 return 0; 133 134 if (enum_id > r->end) 135 return 0; 136 137 return 1; 138 } 139 140 u32 sh_pfc_read_raw_reg(void __iomem *mapped_reg, unsigned int reg_width) 141 { 142 switch (reg_width) { 143 case 8: 144 return ioread8(mapped_reg); 145 case 16: 146 return ioread16(mapped_reg); 147 case 32: 148 return ioread32(mapped_reg); 149 } 150 151 BUG(); 152 return 0; 153 } 154 155 void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned int reg_width, 156 u32 data) 157 { 158 switch (reg_width) { 159 case 8: 160 iowrite8(data, mapped_reg); 161 return; 162 case 16: 163 iowrite16(data, mapped_reg); 164 return; 165 case 32: 166 iowrite32(data, mapped_reg); 167 return; 168 } 169 170 BUG(); 171 } 172 173 u32 sh_pfc_read(struct sh_pfc *pfc, u32 reg) 174 { 175 return sh_pfc_read_raw_reg(sh_pfc_phys_to_virt(pfc, reg), 32); 176 } 177 178 static void sh_pfc_unlock_reg(struct sh_pfc *pfc, u32 reg, u32 data) 179 { 180 u32 unlock; 181 182 if (!pfc->info->unlock_reg) 183 return; 184 185 if (pfc->info->unlock_reg >= 0x80000000UL) 186 unlock = pfc->info->unlock_reg; 187 else 188 /* unlock_reg is a mask */ 189 unlock = reg & ~pfc->info->unlock_reg; 190 191 sh_pfc_write_raw_reg(sh_pfc_phys_to_virt(pfc, unlock), 32, ~data); 192 } 193 194 void sh_pfc_write(struct sh_pfc *pfc, u32 reg, u32 data) 195 { 196 sh_pfc_unlock_reg(pfc, reg, data); 197 sh_pfc_write_raw_reg(sh_pfc_phys_to_virt(pfc, reg), 32, data); 198 } 199 200 static void sh_pfc_config_reg_helper(struct sh_pfc *pfc, 201 const struct pinmux_cfg_reg *crp, 202 unsigned int in_pos, 203 void __iomem **mapped_regp, u32 *maskp, 204 unsigned int *posp) 205 { 206 unsigned int k; 207 208 *mapped_regp = sh_pfc_phys_to_virt(pfc, crp->reg); 209 210 if (crp->field_width) { 211 *maskp = (1 << crp->field_width) - 1; 212 *posp = crp->reg_width - ((in_pos + 1) * crp->field_width); 213 } else { 214 *maskp = (1 << crp->var_field_width[in_pos]) - 1; 215 *posp = crp->reg_width; 216 for (k = 0; k <= in_pos; k++) 217 *posp -= crp->var_field_width[k]; 218 } 219 } 220 221 static void sh_pfc_write_config_reg(struct sh_pfc *pfc, 222 const struct pinmux_cfg_reg *crp, 223 unsigned int field, u32 value) 224 { 225 void __iomem *mapped_reg; 226 unsigned int pos; 227 u32 mask, data; 228 229 sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos); 230 231 dev_dbg(pfc->dev, "write_reg addr = %x, value = 0x%x, field = %u, " 232 "r_width = %u, f_width = %u\n", 233 crp->reg, value, field, crp->reg_width, hweight32(mask)); 234 235 mask = ~(mask << pos); 236 value = value << pos; 237 238 data = sh_pfc_read_raw_reg(mapped_reg, crp->reg_width); 239 data &= mask; 240 data |= value; 241 242 sh_pfc_unlock_reg(pfc, crp->reg, data); 243 sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data); 244 } 245 246 static int sh_pfc_get_config_reg(struct sh_pfc *pfc, u16 enum_id, 247 const struct pinmux_cfg_reg **crp, 248 unsigned int *fieldp, u32 *valuep) 249 { 250 unsigned int k = 0; 251 252 while (1) { 253 const struct pinmux_cfg_reg *config_reg = 254 pfc->info->cfg_regs + k; 255 unsigned int r_width = config_reg->reg_width; 256 unsigned int f_width = config_reg->field_width; 257 unsigned int curr_width; 258 unsigned int bit_pos; 259 unsigned int pos = 0; 260 unsigned int m = 0; 261 262 if (!r_width) 263 break; 264 265 for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) { 266 u32 ncomb; 267 u32 n; 268 269 if (f_width) 270 curr_width = f_width; 271 else 272 curr_width = config_reg->var_field_width[m]; 273 274 ncomb = 1 << curr_width; 275 for (n = 0; n < ncomb; n++) { 276 if (config_reg->enum_ids[pos + n] == enum_id) { 277 *crp = config_reg; 278 *fieldp = m; 279 *valuep = n; 280 return 0; 281 } 282 } 283 pos += ncomb; 284 m++; 285 } 286 k++; 287 } 288 289 return -EINVAL; 290 } 291 292 static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, u16 mark, int pos, 293 u16 *enum_idp) 294 { 295 const u16 *data = pfc->info->pinmux_data; 296 unsigned int k; 297 298 if (pos) { 299 *enum_idp = data[pos + 1]; 300 return pos + 1; 301 } 302 303 for (k = 0; k < pfc->info->pinmux_data_size; k++) { 304 if (data[k] == mark) { 305 *enum_idp = data[k + 1]; 306 return k + 1; 307 } 308 } 309 310 dev_err(pfc->dev, "cannot locate data/mark enum_id for mark %d\n", 311 mark); 312 return -EINVAL; 313 } 314 315 int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type) 316 { 317 const struct pinmux_range *range; 318 int pos = 0; 319 320 switch (pinmux_type) { 321 case PINMUX_TYPE_GPIO: 322 case PINMUX_TYPE_FUNCTION: 323 range = NULL; 324 break; 325 326 #ifdef CONFIG_PINCTRL_SH_PFC_GPIO 327 case PINMUX_TYPE_OUTPUT: 328 range = &pfc->info->output; 329 break; 330 331 case PINMUX_TYPE_INPUT: 332 range = &pfc->info->input; 333 break; 334 #endif /* CONFIG_PINCTRL_SH_PFC_GPIO */ 335 336 default: 337 return -EINVAL; 338 } 339 340 /* Iterate over all the configuration fields we need to update. */ 341 while (1) { 342 const struct pinmux_cfg_reg *cr; 343 unsigned int field; 344 u16 enum_id; 345 u32 value; 346 int in_range; 347 int ret; 348 349 pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id); 350 if (pos < 0) 351 return pos; 352 353 if (!enum_id) 354 break; 355 356 /* Check if the configuration field selects a function. If it 357 * doesn't, skip the field if it's not applicable to the 358 * requested pinmux type. 359 */ 360 in_range = sh_pfc_enum_in_range(enum_id, &pfc->info->function); 361 if (!in_range) { 362 if (pinmux_type == PINMUX_TYPE_FUNCTION) { 363 /* Functions are allowed to modify all 364 * fields. 365 */ 366 in_range = 1; 367 } else if (pinmux_type != PINMUX_TYPE_GPIO) { 368 /* Input/output types can only modify fields 369 * that correspond to their respective ranges. 370 */ 371 in_range = sh_pfc_enum_in_range(enum_id, range); 372 373 /* 374 * special case pass through for fixed 375 * input-only or output-only pins without 376 * function enum register association. 377 */ 378 if (in_range && enum_id == range->force) 379 continue; 380 } 381 /* GPIOs are only allowed to modify function fields. */ 382 } 383 384 if (!in_range) 385 continue; 386 387 ret = sh_pfc_get_config_reg(pfc, enum_id, &cr, &field, &value); 388 if (ret < 0) 389 return ret; 390 391 sh_pfc_write_config_reg(pfc, cr, field, value); 392 } 393 394 return 0; 395 } 396 397 static int sh_pfc_init_ranges(struct sh_pfc *pfc) 398 { 399 struct sh_pfc_pin_range *range; 400 unsigned int nr_ranges; 401 unsigned int i; 402 403 if (pfc->info->pins[0].pin == (u16)-1) { 404 /* Pin number -1 denotes that the SoC doesn't report pin numbers 405 * in its pin arrays yet. Consider the pin numbers range as 406 * continuous and allocate a single range. 407 */ 408 pfc->nr_ranges = 1; 409 pfc->ranges = devm_kzalloc(pfc->dev, sizeof(*pfc->ranges), 410 GFP_KERNEL); 411 if (pfc->ranges == NULL) 412 return -ENOMEM; 413 414 pfc->ranges->start = 0; 415 pfc->ranges->end = pfc->info->nr_pins - 1; 416 pfc->nr_gpio_pins = pfc->info->nr_pins; 417 418 return 0; 419 } 420 421 /* Count, allocate and fill the ranges. The PFC SoC data pins array must 422 * be sorted by pin numbers, and pins without a GPIO port must come 423 * last. 424 */ 425 for (i = 1, nr_ranges = 1; i < pfc->info->nr_pins; ++i) { 426 if (pfc->info->pins[i-1].pin != pfc->info->pins[i].pin - 1) 427 nr_ranges++; 428 } 429 430 pfc->nr_ranges = nr_ranges; 431 pfc->ranges = devm_kcalloc(pfc->dev, nr_ranges, sizeof(*pfc->ranges), 432 GFP_KERNEL); 433 if (pfc->ranges == NULL) 434 return -ENOMEM; 435 436 range = pfc->ranges; 437 range->start = pfc->info->pins[0].pin; 438 439 for (i = 1; i < pfc->info->nr_pins; ++i) { 440 if (pfc->info->pins[i-1].pin == pfc->info->pins[i].pin - 1) 441 continue; 442 443 range->end = pfc->info->pins[i-1].pin; 444 if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO)) 445 pfc->nr_gpio_pins = range->end + 1; 446 447 range++; 448 range->start = pfc->info->pins[i].pin; 449 } 450 451 range->end = pfc->info->pins[i-1].pin; 452 if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO)) 453 pfc->nr_gpio_pins = range->end + 1; 454 455 return 0; 456 } 457 458 #ifdef CONFIG_OF 459 static const struct of_device_id sh_pfc_of_table[] = { 460 #ifdef CONFIG_PINCTRL_PFC_EMEV2 461 { 462 .compatible = "renesas,pfc-emev2", 463 .data = &emev2_pinmux_info, 464 }, 465 #endif 466 #ifdef CONFIG_PINCTRL_PFC_R8A73A4 467 { 468 .compatible = "renesas,pfc-r8a73a4", 469 .data = &r8a73a4_pinmux_info, 470 }, 471 #endif 472 #ifdef CONFIG_PINCTRL_PFC_R8A7740 473 { 474 .compatible = "renesas,pfc-r8a7740", 475 .data = &r8a7740_pinmux_info, 476 }, 477 #endif 478 #ifdef CONFIG_PINCTRL_PFC_R8A7742 479 { 480 .compatible = "renesas,pfc-r8a7742", 481 .data = &r8a7742_pinmux_info, 482 }, 483 #endif 484 #ifdef CONFIG_PINCTRL_PFC_R8A7743 485 { 486 .compatible = "renesas,pfc-r8a7743", 487 .data = &r8a7743_pinmux_info, 488 }, 489 #endif 490 #ifdef CONFIG_PINCTRL_PFC_R8A7744 491 { 492 .compatible = "renesas,pfc-r8a7744", 493 .data = &r8a7744_pinmux_info, 494 }, 495 #endif 496 #ifdef CONFIG_PINCTRL_PFC_R8A7745 497 { 498 .compatible = "renesas,pfc-r8a7745", 499 .data = &r8a7745_pinmux_info, 500 }, 501 #endif 502 #ifdef CONFIG_PINCTRL_PFC_R8A77470 503 { 504 .compatible = "renesas,pfc-r8a77470", 505 .data = &r8a77470_pinmux_info, 506 }, 507 #endif 508 #ifdef CONFIG_PINCTRL_PFC_R8A774A1 509 { 510 .compatible = "renesas,pfc-r8a774a1", 511 .data = &r8a774a1_pinmux_info, 512 }, 513 #endif 514 #ifdef CONFIG_PINCTRL_PFC_R8A774B1 515 { 516 .compatible = "renesas,pfc-r8a774b1", 517 .data = &r8a774b1_pinmux_info, 518 }, 519 #endif 520 #ifdef CONFIG_PINCTRL_PFC_R8A774C0 521 { 522 .compatible = "renesas,pfc-r8a774c0", 523 .data = &r8a774c0_pinmux_info, 524 }, 525 #endif 526 #ifdef CONFIG_PINCTRL_PFC_R8A774E1 527 { 528 .compatible = "renesas,pfc-r8a774e1", 529 .data = &r8a774e1_pinmux_info, 530 }, 531 #endif 532 #ifdef CONFIG_PINCTRL_PFC_R8A7778 533 { 534 .compatible = "renesas,pfc-r8a7778", 535 .data = &r8a7778_pinmux_info, 536 }, 537 #endif 538 #ifdef CONFIG_PINCTRL_PFC_R8A7779 539 { 540 .compatible = "renesas,pfc-r8a7779", 541 .data = &r8a7779_pinmux_info, 542 }, 543 #endif 544 #ifdef CONFIG_PINCTRL_PFC_R8A7790 545 { 546 .compatible = "renesas,pfc-r8a7790", 547 .data = &r8a7790_pinmux_info, 548 }, 549 #endif 550 #ifdef CONFIG_PINCTRL_PFC_R8A7791 551 { 552 .compatible = "renesas,pfc-r8a7791", 553 .data = &r8a7791_pinmux_info, 554 }, 555 #endif 556 #ifdef CONFIG_PINCTRL_PFC_R8A7792 557 { 558 .compatible = "renesas,pfc-r8a7792", 559 .data = &r8a7792_pinmux_info, 560 }, 561 #endif 562 #ifdef CONFIG_PINCTRL_PFC_R8A7793 563 { 564 .compatible = "renesas,pfc-r8a7793", 565 .data = &r8a7793_pinmux_info, 566 }, 567 #endif 568 #ifdef CONFIG_PINCTRL_PFC_R8A7794 569 { 570 .compatible = "renesas,pfc-r8a7794", 571 .data = &r8a7794_pinmux_info, 572 }, 573 #endif 574 /* 575 * Both r8a7795 entries must be present to make sanity checks work, but only 576 * the first entry is actually used. 577 * R-Car H3 ES1.x is matched using soc_device_match() instead. 578 */ 579 #ifdef CONFIG_PINCTRL_PFC_R8A77951 580 { 581 .compatible = "renesas,pfc-r8a7795", 582 .data = &r8a77951_pinmux_info, 583 }, 584 #endif 585 #ifdef CONFIG_PINCTRL_PFC_R8A77950 586 { 587 .compatible = "renesas,pfc-r8a7795", 588 .data = &r8a77950_pinmux_info, 589 }, 590 #endif 591 #ifdef CONFIG_PINCTRL_PFC_R8A77960 592 { 593 .compatible = "renesas,pfc-r8a7796", 594 .data = &r8a77960_pinmux_info, 595 }, 596 #endif 597 #ifdef CONFIG_PINCTRL_PFC_R8A77961 598 { 599 .compatible = "renesas,pfc-r8a77961", 600 .data = &r8a77961_pinmux_info, 601 }, 602 #endif 603 #ifdef CONFIG_PINCTRL_PFC_R8A77965 604 { 605 .compatible = "renesas,pfc-r8a77965", 606 .data = &r8a77965_pinmux_info, 607 }, 608 #endif 609 #ifdef CONFIG_PINCTRL_PFC_R8A77970 610 { 611 .compatible = "renesas,pfc-r8a77970", 612 .data = &r8a77970_pinmux_info, 613 }, 614 #endif 615 #ifdef CONFIG_PINCTRL_PFC_R8A77980 616 { 617 .compatible = "renesas,pfc-r8a77980", 618 .data = &r8a77980_pinmux_info, 619 }, 620 #endif 621 #ifdef CONFIG_PINCTRL_PFC_R8A77990 622 { 623 .compatible = "renesas,pfc-r8a77990", 624 .data = &r8a77990_pinmux_info, 625 }, 626 #endif 627 #ifdef CONFIG_PINCTRL_PFC_R8A77995 628 { 629 .compatible = "renesas,pfc-r8a77995", 630 .data = &r8a77995_pinmux_info, 631 }, 632 #endif 633 #ifdef CONFIG_PINCTRL_PFC_R8A779A0 634 { 635 .compatible = "renesas,pfc-r8a779a0", 636 .data = &r8a779a0_pinmux_info, 637 }, 638 #endif 639 #ifdef CONFIG_PINCTRL_PFC_R8A779F0 640 { 641 .compatible = "renesas,pfc-r8a779f0", 642 .data = &r8a779f0_pinmux_info, 643 }, 644 #endif 645 #ifdef CONFIG_PINCTRL_PFC_SH73A0 646 { 647 .compatible = "renesas,pfc-sh73a0", 648 .data = &sh73a0_pinmux_info, 649 }, 650 #endif 651 { }, 652 }; 653 #endif 654 655 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM_PSCI_FW) 656 static void sh_pfc_nop_reg(struct sh_pfc *pfc, u32 reg, unsigned int idx) 657 { 658 } 659 660 static void sh_pfc_save_reg(struct sh_pfc *pfc, u32 reg, unsigned int idx) 661 { 662 pfc->saved_regs[idx] = sh_pfc_read(pfc, reg); 663 } 664 665 static void sh_pfc_restore_reg(struct sh_pfc *pfc, u32 reg, unsigned int idx) 666 { 667 sh_pfc_write(pfc, reg, pfc->saved_regs[idx]); 668 } 669 670 static unsigned int sh_pfc_walk_regs(struct sh_pfc *pfc, 671 void (*do_reg)(struct sh_pfc *pfc, u32 reg, unsigned int idx)) 672 { 673 unsigned int i, n = 0; 674 675 if (pfc->info->cfg_regs) 676 for (i = 0; pfc->info->cfg_regs[i].reg; i++) 677 do_reg(pfc, pfc->info->cfg_regs[i].reg, n++); 678 679 if (pfc->info->drive_regs) 680 for (i = 0; pfc->info->drive_regs[i].reg; i++) 681 do_reg(pfc, pfc->info->drive_regs[i].reg, n++); 682 683 if (pfc->info->bias_regs) 684 for (i = 0; pfc->info->bias_regs[i].puen || 685 pfc->info->bias_regs[i].pud; i++) { 686 if (pfc->info->bias_regs[i].puen) 687 do_reg(pfc, pfc->info->bias_regs[i].puen, n++); 688 if (pfc->info->bias_regs[i].pud) 689 do_reg(pfc, pfc->info->bias_regs[i].pud, n++); 690 } 691 692 if (pfc->info->ioctrl_regs) 693 for (i = 0; pfc->info->ioctrl_regs[i].reg; i++) 694 do_reg(pfc, pfc->info->ioctrl_regs[i].reg, n++); 695 696 return n; 697 } 698 699 static int sh_pfc_suspend_init(struct sh_pfc *pfc) 700 { 701 unsigned int n; 702 703 /* This is the best we can do to check for the presence of PSCI */ 704 if (!psci_ops.cpu_suspend) 705 return 0; 706 707 n = sh_pfc_walk_regs(pfc, sh_pfc_nop_reg); 708 if (!n) 709 return 0; 710 711 pfc->saved_regs = devm_kmalloc_array(pfc->dev, n, 712 sizeof(*pfc->saved_regs), 713 GFP_KERNEL); 714 if (!pfc->saved_regs) 715 return -ENOMEM; 716 717 dev_dbg(pfc->dev, "Allocated space to save %u regs\n", n); 718 return 0; 719 } 720 721 static int sh_pfc_suspend_noirq(struct device *dev) 722 { 723 struct sh_pfc *pfc = dev_get_drvdata(dev); 724 725 if (pfc->saved_regs) 726 sh_pfc_walk_regs(pfc, sh_pfc_save_reg); 727 return 0; 728 } 729 730 static int sh_pfc_resume_noirq(struct device *dev) 731 { 732 struct sh_pfc *pfc = dev_get_drvdata(dev); 733 734 if (pfc->saved_regs) 735 sh_pfc_walk_regs(pfc, sh_pfc_restore_reg); 736 return 0; 737 } 738 739 static const struct dev_pm_ops sh_pfc_pm = { 740 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sh_pfc_suspend_noirq, sh_pfc_resume_noirq) 741 }; 742 #define DEV_PM_OPS &sh_pfc_pm 743 #else 744 static int sh_pfc_suspend_init(struct sh_pfc *pfc) { return 0; } 745 #define DEV_PM_OPS NULL 746 #endif /* CONFIG_PM_SLEEP && CONFIG_ARM_PSCI_FW */ 747 748 #ifdef DEBUG 749 #define SH_PFC_MAX_REGS 300 750 #define SH_PFC_MAX_ENUMS 5000 751 752 static unsigned int sh_pfc_errors __initdata; 753 static unsigned int sh_pfc_warnings __initdata; 754 static bool sh_pfc_bias_done __initdata; 755 static bool sh_pfc_drive_done __initdata; 756 static bool sh_pfc_power_done __initdata; 757 static struct { 758 u32 reg; 759 u32 bits; 760 } *sh_pfc_regs __initdata; 761 static u32 sh_pfc_num_regs __initdata; 762 static u16 *sh_pfc_enums __initdata; 763 static u32 sh_pfc_num_enums __initdata; 764 765 #define sh_pfc_err(fmt, ...) \ 766 do { \ 767 pr_err("%s: " fmt, drvname, ##__VA_ARGS__); \ 768 sh_pfc_errors++; \ 769 } while (0) 770 771 #define sh_pfc_err_once(type, fmt, ...) \ 772 do { \ 773 if (!sh_pfc_ ## type ## _done) { \ 774 sh_pfc_ ## type ## _done = true; \ 775 sh_pfc_err(fmt, ##__VA_ARGS__); \ 776 } \ 777 } while (0) 778 779 #define sh_pfc_warn(fmt, ...) \ 780 do { \ 781 pr_warn("%s: " fmt, drvname, ##__VA_ARGS__); \ 782 sh_pfc_warnings++; \ 783 } while (0) 784 785 static bool __init is0s(const u16 *enum_ids, unsigned int n) 786 { 787 unsigned int i; 788 789 for (i = 0; i < n; i++) 790 if (enum_ids[i]) 791 return false; 792 793 return true; 794 } 795 796 static bool __init same_name(const char *a, const char *b) 797 { 798 return a && b && !strcmp(a, b); 799 } 800 801 static void __init sh_pfc_check_reg(const char *drvname, u32 reg, u32 bits) 802 { 803 unsigned int i; 804 805 for (i = 0; i < sh_pfc_num_regs; i++) { 806 if (reg != sh_pfc_regs[i].reg) 807 continue; 808 809 if (bits & sh_pfc_regs[i].bits) 810 sh_pfc_err("reg 0x%x: bits 0x%x conflict\n", reg, 811 bits & sh_pfc_regs[i].bits); 812 813 sh_pfc_regs[i].bits |= bits; 814 return; 815 } 816 817 if (sh_pfc_num_regs == SH_PFC_MAX_REGS) { 818 pr_warn_once("%s: Please increase SH_PFC_MAX_REGS\n", drvname); 819 return; 820 } 821 822 sh_pfc_regs[sh_pfc_num_regs].reg = reg; 823 sh_pfc_regs[sh_pfc_num_regs].bits = bits; 824 sh_pfc_num_regs++; 825 } 826 827 static int __init sh_pfc_check_enum(const char *drvname, u16 enum_id) 828 { 829 unsigned int i; 830 831 for (i = 0; i < sh_pfc_num_enums; i++) { 832 if (enum_id == sh_pfc_enums[i]) 833 return -EINVAL; 834 } 835 836 if (sh_pfc_num_enums == SH_PFC_MAX_ENUMS) { 837 pr_warn_once("%s: Please increase SH_PFC_MAX_ENUMS\n", drvname); 838 return 0; 839 } 840 841 sh_pfc_enums[sh_pfc_num_enums++] = enum_id; 842 return 0; 843 } 844 845 static void __init sh_pfc_check_reg_enums(const char *drvname, u32 reg, 846 const u16 *enums, unsigned int n) 847 { 848 unsigned int i; 849 850 for (i = 0; i < n; i++) { 851 if (enums[i] && sh_pfc_check_enum(drvname, enums[i])) 852 sh_pfc_err("reg 0x%x enum_id %u conflict\n", reg, 853 enums[i]); 854 } 855 } 856 857 static const struct sh_pfc_pin __init *sh_pfc_find_pin( 858 const struct sh_pfc_soc_info *info, u32 reg, unsigned int pin) 859 { 860 const char *drvname = info->name; 861 unsigned int i; 862 863 if (pin == SH_PFC_PIN_NONE) 864 return NULL; 865 866 for (i = 0; i < info->nr_pins; i++) { 867 if (pin == info->pins[i].pin) 868 return &info->pins[i]; 869 } 870 871 sh_pfc_err("reg 0x%x: pin %u not found\n", reg, pin); 872 return NULL; 873 } 874 875 static void __init sh_pfc_check_cfg_reg(const char *drvname, 876 const struct pinmux_cfg_reg *cfg_reg) 877 { 878 unsigned int i, n, rw, fw; 879 880 sh_pfc_check_reg(drvname, cfg_reg->reg, 881 GENMASK(cfg_reg->reg_width - 1, 0)); 882 883 if (cfg_reg->field_width) { 884 fw = cfg_reg->field_width; 885 n = (cfg_reg->reg_width / fw) << fw; 886 /* Skip field checks (done at build time) */ 887 goto check_enum_ids; 888 } 889 890 for (i = 0, n = 0, rw = 0; (fw = cfg_reg->var_field_width[i]); i++) { 891 if (fw > 3 && is0s(&cfg_reg->enum_ids[n], 1 << fw)) 892 sh_pfc_warn("reg 0x%x: reserved field [%u:%u] can be split to reduce table size\n", 893 cfg_reg->reg, rw, rw + fw - 1); 894 n += 1 << fw; 895 rw += fw; 896 } 897 898 if (rw != cfg_reg->reg_width) 899 sh_pfc_err("reg 0x%x: var_field_width declares %u instead of %u bits\n", 900 cfg_reg->reg, rw, cfg_reg->reg_width); 901 902 if (n != cfg_reg->nr_enum_ids) 903 sh_pfc_err("reg 0x%x: enum_ids[] has %u instead of %u values\n", 904 cfg_reg->reg, cfg_reg->nr_enum_ids, n); 905 906 check_enum_ids: 907 sh_pfc_check_reg_enums(drvname, cfg_reg->reg, cfg_reg->enum_ids, n); 908 } 909 910 static void __init sh_pfc_check_drive_reg(const struct sh_pfc_soc_info *info, 911 const struct pinmux_drive_reg *drive) 912 { 913 const char *drvname = info->name; 914 const struct sh_pfc_pin *pin; 915 unsigned int i; 916 917 for (i = 0; i < ARRAY_SIZE(drive->fields); i++) { 918 const struct pinmux_drive_reg_field *field = &drive->fields[i]; 919 920 if (!field->pin && !field->offset && !field->size) 921 continue; 922 923 sh_pfc_check_reg(info->name, drive->reg, 924 GENMASK(field->offset + field->size - 1, 925 field->offset)); 926 927 pin = sh_pfc_find_pin(info, drive->reg, field->pin); 928 if (pin && !(pin->configs & SH_PFC_PIN_CFG_DRIVE_STRENGTH)) 929 sh_pfc_err("drive_reg 0x%x: field %u: pin %s lacks SH_PFC_PIN_CFG_DRIVE_STRENGTH flag\n", 930 drive->reg, i, pin->name); 931 } 932 } 933 934 static void __init sh_pfc_check_bias_reg(const struct sh_pfc_soc_info *info, 935 const struct pinmux_bias_reg *bias) 936 { 937 const char *drvname = info->name; 938 const struct sh_pfc_pin *pin; 939 unsigned int i; 940 u32 bits; 941 942 for (i = 0, bits = 0; i < ARRAY_SIZE(bias->pins); i++) 943 if (bias->pins[i] != SH_PFC_PIN_NONE) 944 bits |= BIT(i); 945 946 if (bias->puen) 947 sh_pfc_check_reg(info->name, bias->puen, bits); 948 if (bias->pud) 949 sh_pfc_check_reg(info->name, bias->pud, bits); 950 for (i = 0; i < ARRAY_SIZE(bias->pins); i++) { 951 pin = sh_pfc_find_pin(info, bias->puen, bias->pins[i]); 952 if (!pin) 953 continue; 954 955 if (bias->puen && bias->pud) { 956 /* 957 * Pull-enable and pull-up/down control registers 958 * As some SoCs have pins that support only pull-up 959 * or pull-down, we just check for one of them 960 */ 961 if (!(pin->configs & SH_PFC_PIN_CFG_PULL_UP_DOWN)) 962 sh_pfc_err("bias_reg 0x%x:%u: pin %s lacks one or more SH_PFC_PIN_CFG_PULL_* flags\n", 963 bias->puen, i, pin->name); 964 } else if (bias->puen) { 965 /* Pull-up control register only */ 966 if (!(pin->configs & SH_PFC_PIN_CFG_PULL_UP)) 967 sh_pfc_err("bias_reg 0x%x:%u: pin %s lacks SH_PFC_PIN_CFG_PULL_UP flag\n", 968 bias->puen, i, pin->name); 969 } else if (bias->pud) { 970 /* Pull-down control register only */ 971 if (!(pin->configs & SH_PFC_PIN_CFG_PULL_DOWN)) 972 sh_pfc_err("bias_reg 0x%x:%u: pin %s lacks SH_PFC_PIN_CFG_PULL_DOWN flag\n", 973 bias->pud, i, pin->name); 974 } 975 } 976 } 977 978 static void __init sh_pfc_compare_groups(const char *drvname, 979 const struct sh_pfc_pin_group *a, 980 const struct sh_pfc_pin_group *b) 981 { 982 unsigned int i; 983 size_t len; 984 985 if (same_name(a->name, b->name)) 986 sh_pfc_err("group %s: name conflict\n", a->name); 987 988 if (a->nr_pins > b->nr_pins) 989 swap(a, b); 990 991 len = a->nr_pins * sizeof(a->pins[0]); 992 for (i = 0; i <= b->nr_pins - a->nr_pins; i++) { 993 if (a->pins == b->pins + i || a->mux == b->mux + i || 994 memcmp(a->pins, b->pins + i, len) || 995 memcmp(a->mux, b->mux + i, len)) 996 continue; 997 998 if (a->nr_pins == b->nr_pins) 999 sh_pfc_warn("group %s can be an alias for %s\n", 1000 a->name, b->name); 1001 else 1002 sh_pfc_warn("group %s is a subset of %s\n", a->name, 1003 b->name); 1004 } 1005 } 1006 1007 static void __init sh_pfc_check_info(const struct sh_pfc_soc_info *info) 1008 { 1009 const struct pinmux_drive_reg *drive_regs = info->drive_regs; 1010 const struct pinmux_bias_reg *bias_regs = info->bias_regs; 1011 const char *drvname = info->name; 1012 unsigned int *refcnts; 1013 unsigned int i, j, k; 1014 1015 pr_info("sh_pfc: Checking %s\n", drvname); 1016 sh_pfc_num_regs = 0; 1017 sh_pfc_num_enums = 0; 1018 sh_pfc_bias_done = false; 1019 sh_pfc_drive_done = false; 1020 sh_pfc_power_done = false; 1021 1022 /* Check pins */ 1023 for (i = 0; i < info->nr_pins; i++) { 1024 const struct sh_pfc_pin *pin = &info->pins[i]; 1025 unsigned int x; 1026 1027 if (!pin->name) { 1028 sh_pfc_err("empty pin %u\n", i); 1029 continue; 1030 } 1031 for (j = 0; j < i; j++) { 1032 const struct sh_pfc_pin *pin2 = &info->pins[j]; 1033 1034 if (same_name(pin->name, pin2->name)) 1035 sh_pfc_err("pin %s: name conflict\n", 1036 pin->name); 1037 1038 if (pin->pin != (u16)-1 && pin->pin == pin2->pin) 1039 sh_pfc_err("pin %s/%s: pin %u conflict\n", 1040 pin->name, pin2->name, pin->pin); 1041 1042 if (pin->enum_id && pin->enum_id == pin2->enum_id) 1043 sh_pfc_err("pin %s/%s: enum_id %u conflict\n", 1044 pin->name, pin2->name, 1045 pin->enum_id); 1046 } 1047 1048 if (pin->configs & SH_PFC_PIN_CFG_PULL_UP_DOWN) { 1049 if (!info->ops || !info->ops->get_bias || 1050 !info->ops->set_bias) 1051 sh_pfc_err_once(bias, "SH_PFC_PIN_CFG_PULL_* flag set but .[gs]et_bias() not implemented\n"); 1052 1053 if (!bias_regs && 1054 (!info->ops || !info->ops->pin_to_portcr)) 1055 sh_pfc_err_once(bias, "SH_PFC_PIN_CFG_PULL_UP flag set but no bias_regs defined and .pin_to_portcr() not implemented\n"); 1056 } 1057 1058 if ((pin->configs & SH_PFC_PIN_CFG_PULL_UP_DOWN) && bias_regs) { 1059 const struct pinmux_bias_reg *bias_reg = 1060 rcar_pin_to_bias_reg(info, pin->pin, &x); 1061 1062 if (!bias_reg || 1063 ((pin->configs & SH_PFC_PIN_CFG_PULL_UP) && 1064 !bias_reg->puen)) 1065 sh_pfc_err("pin %s: SH_PFC_PIN_CFG_PULL_UP flag set but pin not in bias_regs\n", 1066 pin->name); 1067 1068 if (!bias_reg || 1069 ((pin->configs & SH_PFC_PIN_CFG_PULL_DOWN) && 1070 !bias_reg->pud)) 1071 sh_pfc_err("pin %s: SH_PFC_PIN_CFG_PULL_DOWN flag set but pin not in bias_regs\n", 1072 pin->name); 1073 } 1074 1075 if (pin->configs & SH_PFC_PIN_CFG_DRIVE_STRENGTH) { 1076 if (!drive_regs) { 1077 sh_pfc_err_once(drive, "SH_PFC_PIN_CFG_DRIVE_STRENGTH flag set but drive_regs missing\n"); 1078 } else { 1079 for (j = 0; drive_regs[j / 8].reg; j++) { 1080 if (!drive_regs[j / 8].fields[j % 8].pin && 1081 !drive_regs[j / 8].fields[j % 8].offset && 1082 !drive_regs[j / 8].fields[j % 8].size) 1083 continue; 1084 1085 if (drive_regs[j / 8].fields[j % 8].pin == pin->pin) 1086 break; 1087 } 1088 1089 if (!drive_regs[j / 8].reg) 1090 sh_pfc_err("pin %s: SH_PFC_PIN_CFG_DRIVE_STRENGTH flag set but not in drive_regs\n", 1091 pin->name); 1092 } 1093 } 1094 1095 if (pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE) { 1096 if (!info->ops || !info->ops->pin_to_pocctrl) 1097 sh_pfc_err_once(power, "SH_PFC_PIN_CFG_IO_VOLTAGE flag set but .pin_to_pocctrl() not implemented\n"); 1098 else if (info->ops->pin_to_pocctrl(pin->pin, &x) < 0) 1099 sh_pfc_err("pin %s: SH_PFC_PIN_CFG_IO_VOLTAGE set but invalid pin_to_pocctrl()\n", 1100 pin->name); 1101 } else if (info->ops && info->ops->pin_to_pocctrl && 1102 info->ops->pin_to_pocctrl(pin->pin, &x) >= 0) { 1103 sh_pfc_warn("pin %s: SH_PFC_PIN_CFG_IO_VOLTAGE not set but valid pin_to_pocctrl()\n", 1104 pin->name); 1105 } 1106 } 1107 1108 /* Check groups and functions */ 1109 refcnts = kcalloc(info->nr_groups, sizeof(*refcnts), GFP_KERNEL); 1110 if (!refcnts) 1111 return; 1112 1113 for (i = 0; i < info->nr_functions; i++) { 1114 const struct sh_pfc_function *func = &info->functions[i]; 1115 1116 if (!func->name) { 1117 sh_pfc_err("empty function %u\n", i); 1118 continue; 1119 } 1120 for (j = 0; j < i; j++) { 1121 if (same_name(func->name, info->functions[j].name)) 1122 sh_pfc_err("function %s: name conflict\n", 1123 func->name); 1124 } 1125 for (j = 0; j < func->nr_groups; j++) { 1126 for (k = 0; k < info->nr_groups; k++) { 1127 if (same_name(func->groups[j], 1128 info->groups[k].name)) { 1129 refcnts[k]++; 1130 break; 1131 } 1132 } 1133 1134 if (k == info->nr_groups) 1135 sh_pfc_err("function %s: group %s not found\n", 1136 func->name, func->groups[j]); 1137 } 1138 } 1139 1140 for (i = 0; i < info->nr_groups; i++) { 1141 const struct sh_pfc_pin_group *group = &info->groups[i]; 1142 1143 if (!group->name) { 1144 sh_pfc_err("empty group %u\n", i); 1145 continue; 1146 } 1147 for (j = 0; j < i; j++) 1148 sh_pfc_compare_groups(drvname, group, &info->groups[j]); 1149 1150 if (!refcnts[i]) 1151 sh_pfc_err("orphan group %s\n", group->name); 1152 else if (refcnts[i] > 1) 1153 sh_pfc_warn("group %s referenced by %u functions\n", 1154 group->name, refcnts[i]); 1155 } 1156 1157 kfree(refcnts); 1158 1159 /* Check config register descriptions */ 1160 for (i = 0; info->cfg_regs && info->cfg_regs[i].reg; i++) 1161 sh_pfc_check_cfg_reg(drvname, &info->cfg_regs[i]); 1162 1163 /* Check drive strength registers */ 1164 for (i = 0; drive_regs && drive_regs[i].reg; i++) 1165 sh_pfc_check_drive_reg(info, &drive_regs[i]); 1166 1167 for (i = 0; drive_regs && drive_regs[i / 8].reg; i++) { 1168 if (!drive_regs[i / 8].fields[i % 8].pin && 1169 !drive_regs[i / 8].fields[i % 8].offset && 1170 !drive_regs[i / 8].fields[i % 8].size) 1171 continue; 1172 1173 for (j = 0; j < i; j++) { 1174 if (drive_regs[i / 8].fields[i % 8].pin == 1175 drive_regs[j / 8].fields[j % 8].pin && 1176 drive_regs[j / 8].fields[j % 8].offset && 1177 drive_regs[j / 8].fields[j % 8].size) { 1178 sh_pfc_err("drive_reg 0x%x:%u/0x%x:%u: pin conflict\n", 1179 drive_regs[i / 8].reg, i % 8, 1180 drive_regs[j / 8].reg, j % 8); 1181 } 1182 } 1183 } 1184 1185 /* Check bias registers */ 1186 for (i = 0; bias_regs && (bias_regs[i].puen || bias_regs[i].pud); i++) 1187 sh_pfc_check_bias_reg(info, &bias_regs[i]); 1188 1189 for (i = 0; bias_regs && 1190 (bias_regs[i / 32].puen || bias_regs[i / 32].pud); i++) { 1191 if (bias_regs[i / 32].pins[i % 32] == SH_PFC_PIN_NONE) 1192 continue; 1193 1194 for (j = 0; j < i; j++) { 1195 if (bias_regs[i / 32].pins[i % 32] != 1196 bias_regs[j / 32].pins[j % 32]) 1197 continue; 1198 1199 if (bias_regs[i / 32].puen && bias_regs[j / 32].puen) 1200 sh_pfc_err("bias_reg 0x%x:%u/0x%x:%u: pin conflict\n", 1201 bias_regs[i / 32].puen, i % 32, 1202 bias_regs[j / 32].puen, j % 32); 1203 if (bias_regs[i / 32].pud && bias_regs[j / 32].pud) 1204 sh_pfc_err("bias_reg 0x%x:%u/0x%x:%u: pin conflict\n", 1205 bias_regs[i / 32].pud, i % 32, 1206 bias_regs[j / 32].pud, j % 32); 1207 } 1208 1209 } 1210 1211 /* Check ioctrl registers */ 1212 for (i = 0; info->ioctrl_regs && info->ioctrl_regs[i].reg; i++) 1213 sh_pfc_check_reg(drvname, info->ioctrl_regs[i].reg, U32_MAX); 1214 1215 /* Check data registers */ 1216 for (i = 0; info->data_regs && info->data_regs[i].reg; i++) { 1217 sh_pfc_check_reg(drvname, info->data_regs[i].reg, 1218 GENMASK(info->data_regs[i].reg_width - 1, 0)); 1219 sh_pfc_check_reg_enums(drvname, info->data_regs[i].reg, 1220 info->data_regs[i].enum_ids, 1221 info->data_regs[i].reg_width); 1222 } 1223 1224 #ifdef CONFIG_PINCTRL_SH_FUNC_GPIO 1225 /* Check function GPIOs */ 1226 for (i = 0; i < info->nr_func_gpios; i++) { 1227 const struct pinmux_func *func = &info->func_gpios[i]; 1228 1229 if (!func->name) { 1230 sh_pfc_err("empty function gpio %u\n", i); 1231 continue; 1232 } 1233 for (j = 0; j < i; j++) { 1234 if (same_name(func->name, info->func_gpios[j].name)) 1235 sh_pfc_err("func_gpio %s: name conflict\n", 1236 func->name); 1237 } 1238 if (sh_pfc_check_enum(drvname, func->enum_id)) 1239 sh_pfc_err("%s enum_id %u conflict\n", func->name, 1240 func->enum_id); 1241 } 1242 #endif 1243 } 1244 1245 static void __init sh_pfc_check_driver(const struct platform_driver *pdrv) 1246 { 1247 unsigned int i; 1248 1249 if (!IS_ENABLED(CONFIG_SUPERH) && 1250 !of_find_matching_node(NULL, pdrv->driver.of_match_table)) 1251 return; 1252 1253 sh_pfc_regs = kcalloc(SH_PFC_MAX_REGS, sizeof(*sh_pfc_regs), 1254 GFP_KERNEL); 1255 if (!sh_pfc_regs) 1256 return; 1257 1258 sh_pfc_enums = kcalloc(SH_PFC_MAX_ENUMS, sizeof(*sh_pfc_enums), 1259 GFP_KERNEL); 1260 if (!sh_pfc_enums) 1261 goto free_regs; 1262 1263 pr_warn("sh_pfc: Checking builtin pinmux tables\n"); 1264 1265 for (i = 0; pdrv->id_table[i].name[0]; i++) 1266 sh_pfc_check_info((void *)pdrv->id_table[i].driver_data); 1267 1268 #ifdef CONFIG_OF 1269 for (i = 0; pdrv->driver.of_match_table[i].compatible[0]; i++) 1270 sh_pfc_check_info(pdrv->driver.of_match_table[i].data); 1271 #endif 1272 1273 pr_warn("sh_pfc: Detected %u errors and %u warnings\n", sh_pfc_errors, 1274 sh_pfc_warnings); 1275 1276 kfree(sh_pfc_enums); 1277 free_regs: 1278 kfree(sh_pfc_regs); 1279 } 1280 1281 #else /* !DEBUG */ 1282 static inline void sh_pfc_check_driver(struct platform_driver *pdrv) {} 1283 #endif /* !DEBUG */ 1284 1285 #ifdef CONFIG_OF 1286 static const void *sh_pfc_quirk_match(void) 1287 { 1288 #ifdef CONFIG_PINCTRL_PFC_R8A77950 1289 const struct soc_device_attribute *match; 1290 static const struct soc_device_attribute quirks[] = { 1291 { 1292 .soc_id = "r8a7795", .revision = "ES1.*", 1293 .data = &r8a77950_pinmux_info, 1294 }, 1295 { /* sentinel */ } 1296 }; 1297 1298 match = soc_device_match(quirks); 1299 if (match) 1300 return match->data; 1301 #endif /* CONFIG_PINCTRL_PFC_R8A77950 */ 1302 1303 return NULL; 1304 } 1305 #endif /* CONFIG_OF */ 1306 1307 static int sh_pfc_probe(struct platform_device *pdev) 1308 { 1309 const struct sh_pfc_soc_info *info; 1310 struct sh_pfc *pfc; 1311 int ret; 1312 1313 #ifdef CONFIG_OF 1314 if (pdev->dev.of_node) { 1315 info = sh_pfc_quirk_match(); 1316 if (!info) 1317 info = of_device_get_match_data(&pdev->dev); 1318 } else 1319 #endif 1320 info = (const void *)platform_get_device_id(pdev)->driver_data; 1321 1322 pfc = devm_kzalloc(&pdev->dev, sizeof(*pfc), GFP_KERNEL); 1323 if (pfc == NULL) 1324 return -ENOMEM; 1325 1326 pfc->info = info; 1327 pfc->dev = &pdev->dev; 1328 1329 ret = sh_pfc_map_resources(pfc, pdev); 1330 if (unlikely(ret < 0)) 1331 return ret; 1332 1333 spin_lock_init(&pfc->lock); 1334 1335 if (info->ops && info->ops->init) { 1336 ret = info->ops->init(pfc); 1337 if (ret < 0) 1338 return ret; 1339 1340 /* .init() may have overridden pfc->info */ 1341 info = pfc->info; 1342 } 1343 1344 ret = sh_pfc_suspend_init(pfc); 1345 if (ret) 1346 return ret; 1347 1348 /* Enable dummy states for those platforms without pinctrl support */ 1349 if (!of_have_populated_dt()) 1350 pinctrl_provide_dummies(); 1351 1352 ret = sh_pfc_init_ranges(pfc); 1353 if (ret < 0) 1354 return ret; 1355 1356 /* 1357 * Initialize pinctrl bindings first 1358 */ 1359 ret = sh_pfc_register_pinctrl(pfc); 1360 if (unlikely(ret != 0)) 1361 return ret; 1362 1363 #ifdef CONFIG_PINCTRL_SH_PFC_GPIO 1364 /* 1365 * Then the GPIO chip 1366 */ 1367 ret = sh_pfc_register_gpiochip(pfc); 1368 if (unlikely(ret != 0)) { 1369 /* 1370 * If the GPIO chip fails to come up we still leave the 1371 * PFC state as it is, given that there are already 1372 * extant users of it that have succeeded by this point. 1373 */ 1374 dev_notice(pfc->dev, "failed to init GPIO chip, ignoring...\n"); 1375 } 1376 #endif 1377 1378 platform_set_drvdata(pdev, pfc); 1379 1380 dev_info(pfc->dev, "%s support registered\n", info->name); 1381 1382 return 0; 1383 } 1384 1385 static const struct platform_device_id sh_pfc_id_table[] = { 1386 #ifdef CONFIG_PINCTRL_PFC_SH7203 1387 { "pfc-sh7203", (kernel_ulong_t)&sh7203_pinmux_info }, 1388 #endif 1389 #ifdef CONFIG_PINCTRL_PFC_SH7264 1390 { "pfc-sh7264", (kernel_ulong_t)&sh7264_pinmux_info }, 1391 #endif 1392 #ifdef CONFIG_PINCTRL_PFC_SH7269 1393 { "pfc-sh7269", (kernel_ulong_t)&sh7269_pinmux_info }, 1394 #endif 1395 #ifdef CONFIG_PINCTRL_PFC_SH7720 1396 { "pfc-sh7720", (kernel_ulong_t)&sh7720_pinmux_info }, 1397 #endif 1398 #ifdef CONFIG_PINCTRL_PFC_SH7722 1399 { "pfc-sh7722", (kernel_ulong_t)&sh7722_pinmux_info }, 1400 #endif 1401 #ifdef CONFIG_PINCTRL_PFC_SH7723 1402 { "pfc-sh7723", (kernel_ulong_t)&sh7723_pinmux_info }, 1403 #endif 1404 #ifdef CONFIG_PINCTRL_PFC_SH7724 1405 { "pfc-sh7724", (kernel_ulong_t)&sh7724_pinmux_info }, 1406 #endif 1407 #ifdef CONFIG_PINCTRL_PFC_SH7734 1408 { "pfc-sh7734", (kernel_ulong_t)&sh7734_pinmux_info }, 1409 #endif 1410 #ifdef CONFIG_PINCTRL_PFC_SH7757 1411 { "pfc-sh7757", (kernel_ulong_t)&sh7757_pinmux_info }, 1412 #endif 1413 #ifdef CONFIG_PINCTRL_PFC_SH7785 1414 { "pfc-sh7785", (kernel_ulong_t)&sh7785_pinmux_info }, 1415 #endif 1416 #ifdef CONFIG_PINCTRL_PFC_SH7786 1417 { "pfc-sh7786", (kernel_ulong_t)&sh7786_pinmux_info }, 1418 #endif 1419 #ifdef CONFIG_PINCTRL_PFC_SHX3 1420 { "pfc-shx3", (kernel_ulong_t)&shx3_pinmux_info }, 1421 #endif 1422 { }, 1423 }; 1424 1425 static struct platform_driver sh_pfc_driver = { 1426 .probe = sh_pfc_probe, 1427 .id_table = sh_pfc_id_table, 1428 .driver = { 1429 .name = DRV_NAME, 1430 .of_match_table = of_match_ptr(sh_pfc_of_table), 1431 .pm = DEV_PM_OPS, 1432 }, 1433 }; 1434 1435 static int __init sh_pfc_init(void) 1436 { 1437 sh_pfc_check_driver(&sh_pfc_driver); 1438 return platform_driver_register(&sh_pfc_driver); 1439 } 1440 postcore_initcall(sh_pfc_init); 1441