1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Pin Control and GPIO driver for SuperH Pin Function Controller. 4 * 5 * Authors: Magnus Damm, Paul Mundt, Laurent Pinchart 6 * 7 * Copyright (C) 2008 Magnus Damm 8 * Copyright (C) 2009 - 2012 Paul Mundt 9 */ 10 11 #define DRV_NAME "sh-pfc" 12 13 #include <linux/bitops.h> 14 #include <linux/err.h> 15 #include <linux/errno.h> 16 #include <linux/io.h> 17 #include <linux/ioport.h> 18 #include <linux/kernel.h> 19 #include <linux/init.h> 20 #include <linux/of.h> 21 #include <linux/of_device.h> 22 #include <linux/pinctrl/machine.h> 23 #include <linux/platform_device.h> 24 #include <linux/psci.h> 25 #include <linux/slab.h> 26 #include <linux/sys_soc.h> 27 28 #include "core.h" 29 30 static int sh_pfc_map_resources(struct sh_pfc *pfc, 31 struct platform_device *pdev) 32 { 33 struct sh_pfc_window *windows; 34 unsigned int *irqs = NULL; 35 unsigned int num_windows; 36 struct resource *res; 37 unsigned int i; 38 int num_irqs; 39 40 /* Count the MEM and IRQ resources. */ 41 for (num_windows = 0;; num_windows++) { 42 res = platform_get_resource(pdev, IORESOURCE_MEM, num_windows); 43 if (!res) 44 break; 45 } 46 if (num_windows == 0) 47 return -EINVAL; 48 49 num_irqs = platform_irq_count(pdev); 50 if (num_irqs < 0) 51 return num_irqs; 52 53 /* Allocate memory windows and IRQs arrays. */ 54 windows = devm_kcalloc(pfc->dev, num_windows, sizeof(*windows), 55 GFP_KERNEL); 56 if (windows == NULL) 57 return -ENOMEM; 58 59 pfc->num_windows = num_windows; 60 pfc->windows = windows; 61 62 if (num_irqs) { 63 irqs = devm_kcalloc(pfc->dev, num_irqs, sizeof(*irqs), 64 GFP_KERNEL); 65 if (irqs == NULL) 66 return -ENOMEM; 67 68 pfc->num_irqs = num_irqs; 69 pfc->irqs = irqs; 70 } 71 72 /* Fill them. */ 73 for (i = 0; i < num_windows; i++) { 74 res = platform_get_resource(pdev, IORESOURCE_MEM, i); 75 windows->phys = res->start; 76 windows->size = resource_size(res); 77 windows->virt = devm_ioremap_resource(pfc->dev, res); 78 if (IS_ERR(windows->virt)) 79 return -ENOMEM; 80 windows++; 81 } 82 for (i = 0; i < num_irqs; i++) 83 *irqs++ = platform_get_irq(pdev, i); 84 85 return 0; 86 } 87 88 static void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc, u32 reg) 89 { 90 struct sh_pfc_window *window; 91 phys_addr_t address = reg; 92 unsigned int i; 93 94 /* scan through physical windows and convert address */ 95 for (i = 0; i < pfc->num_windows; i++) { 96 window = pfc->windows + i; 97 98 if (address < window->phys) 99 continue; 100 101 if (address >= (window->phys + window->size)) 102 continue; 103 104 return window->virt + (address - window->phys); 105 } 106 107 BUG(); 108 return NULL; 109 } 110 111 int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin) 112 { 113 unsigned int offset; 114 unsigned int i; 115 116 for (i = 0, offset = 0; i < pfc->nr_ranges; ++i) { 117 const struct sh_pfc_pin_range *range = &pfc->ranges[i]; 118 119 if (pin <= range->end) 120 return pin >= range->start 121 ? offset + pin - range->start : -1; 122 123 offset += range->end - range->start + 1; 124 } 125 126 return -EINVAL; 127 } 128 129 static int sh_pfc_enum_in_range(u16 enum_id, const struct pinmux_range *r) 130 { 131 if (enum_id < r->begin) 132 return 0; 133 134 if (enum_id > r->end) 135 return 0; 136 137 return 1; 138 } 139 140 u32 sh_pfc_read_raw_reg(void __iomem *mapped_reg, unsigned int reg_width) 141 { 142 switch (reg_width) { 143 case 8: 144 return ioread8(mapped_reg); 145 case 16: 146 return ioread16(mapped_reg); 147 case 32: 148 return ioread32(mapped_reg); 149 } 150 151 BUG(); 152 return 0; 153 } 154 155 void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned int reg_width, 156 u32 data) 157 { 158 switch (reg_width) { 159 case 8: 160 iowrite8(data, mapped_reg); 161 return; 162 case 16: 163 iowrite16(data, mapped_reg); 164 return; 165 case 32: 166 iowrite32(data, mapped_reg); 167 return; 168 } 169 170 BUG(); 171 } 172 173 u32 sh_pfc_read(struct sh_pfc *pfc, u32 reg) 174 { 175 return sh_pfc_read_raw_reg(sh_pfc_phys_to_virt(pfc, reg), 32); 176 } 177 178 void sh_pfc_write(struct sh_pfc *pfc, u32 reg, u32 data) 179 { 180 if (pfc->info->unlock_reg) 181 sh_pfc_write_raw_reg( 182 sh_pfc_phys_to_virt(pfc, pfc->info->unlock_reg), 32, 183 ~data); 184 185 sh_pfc_write_raw_reg(sh_pfc_phys_to_virt(pfc, reg), 32, data); 186 } 187 188 static void sh_pfc_config_reg_helper(struct sh_pfc *pfc, 189 const struct pinmux_cfg_reg *crp, 190 unsigned int in_pos, 191 void __iomem **mapped_regp, u32 *maskp, 192 unsigned int *posp) 193 { 194 unsigned int k; 195 196 *mapped_regp = sh_pfc_phys_to_virt(pfc, crp->reg); 197 198 if (crp->field_width) { 199 *maskp = (1 << crp->field_width) - 1; 200 *posp = crp->reg_width - ((in_pos + 1) * crp->field_width); 201 } else { 202 *maskp = (1 << crp->var_field_width[in_pos]) - 1; 203 *posp = crp->reg_width; 204 for (k = 0; k <= in_pos; k++) 205 *posp -= crp->var_field_width[k]; 206 } 207 } 208 209 static void sh_pfc_write_config_reg(struct sh_pfc *pfc, 210 const struct pinmux_cfg_reg *crp, 211 unsigned int field, u32 value) 212 { 213 void __iomem *mapped_reg; 214 unsigned int pos; 215 u32 mask, data; 216 217 sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos); 218 219 dev_dbg(pfc->dev, "write_reg addr = %x, value = 0x%x, field = %u, " 220 "r_width = %u, f_width = %u\n", 221 crp->reg, value, field, crp->reg_width, hweight32(mask)); 222 223 mask = ~(mask << pos); 224 value = value << pos; 225 226 data = sh_pfc_read_raw_reg(mapped_reg, crp->reg_width); 227 data &= mask; 228 data |= value; 229 230 if (pfc->info->unlock_reg) 231 sh_pfc_write_raw_reg( 232 sh_pfc_phys_to_virt(pfc, pfc->info->unlock_reg), 32, 233 ~data); 234 235 sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data); 236 } 237 238 static int sh_pfc_get_config_reg(struct sh_pfc *pfc, u16 enum_id, 239 const struct pinmux_cfg_reg **crp, 240 unsigned int *fieldp, u32 *valuep) 241 { 242 unsigned int k = 0; 243 244 while (1) { 245 const struct pinmux_cfg_reg *config_reg = 246 pfc->info->cfg_regs + k; 247 unsigned int r_width = config_reg->reg_width; 248 unsigned int f_width = config_reg->field_width; 249 unsigned int curr_width; 250 unsigned int bit_pos; 251 unsigned int pos = 0; 252 unsigned int m = 0; 253 254 if (!r_width) 255 break; 256 257 for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) { 258 u32 ncomb; 259 u32 n; 260 261 if (f_width) 262 curr_width = f_width; 263 else 264 curr_width = config_reg->var_field_width[m]; 265 266 ncomb = 1 << curr_width; 267 for (n = 0; n < ncomb; n++) { 268 if (config_reg->enum_ids[pos + n] == enum_id) { 269 *crp = config_reg; 270 *fieldp = m; 271 *valuep = n; 272 return 0; 273 } 274 } 275 pos += ncomb; 276 m++; 277 } 278 k++; 279 } 280 281 return -EINVAL; 282 } 283 284 static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, u16 mark, int pos, 285 u16 *enum_idp) 286 { 287 const u16 *data = pfc->info->pinmux_data; 288 unsigned int k; 289 290 if (pos) { 291 *enum_idp = data[pos + 1]; 292 return pos + 1; 293 } 294 295 for (k = 0; k < pfc->info->pinmux_data_size; k++) { 296 if (data[k] == mark) { 297 *enum_idp = data[k + 1]; 298 return k + 1; 299 } 300 } 301 302 dev_err(pfc->dev, "cannot locate data/mark enum_id for mark %d\n", 303 mark); 304 return -EINVAL; 305 } 306 307 int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type) 308 { 309 const struct pinmux_range *range; 310 int pos = 0; 311 312 switch (pinmux_type) { 313 case PINMUX_TYPE_GPIO: 314 case PINMUX_TYPE_FUNCTION: 315 range = NULL; 316 break; 317 318 case PINMUX_TYPE_OUTPUT: 319 range = &pfc->info->output; 320 break; 321 322 case PINMUX_TYPE_INPUT: 323 range = &pfc->info->input; 324 break; 325 326 default: 327 return -EINVAL; 328 } 329 330 /* Iterate over all the configuration fields we need to update. */ 331 while (1) { 332 const struct pinmux_cfg_reg *cr; 333 unsigned int field; 334 u16 enum_id; 335 u32 value; 336 int in_range; 337 int ret; 338 339 pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id); 340 if (pos < 0) 341 return pos; 342 343 if (!enum_id) 344 break; 345 346 /* Check if the configuration field selects a function. If it 347 * doesn't, skip the field if it's not applicable to the 348 * requested pinmux type. 349 */ 350 in_range = sh_pfc_enum_in_range(enum_id, &pfc->info->function); 351 if (!in_range) { 352 if (pinmux_type == PINMUX_TYPE_FUNCTION) { 353 /* Functions are allowed to modify all 354 * fields. 355 */ 356 in_range = 1; 357 } else if (pinmux_type != PINMUX_TYPE_GPIO) { 358 /* Input/output types can only modify fields 359 * that correspond to their respective ranges. 360 */ 361 in_range = sh_pfc_enum_in_range(enum_id, range); 362 363 /* 364 * special case pass through for fixed 365 * input-only or output-only pins without 366 * function enum register association. 367 */ 368 if (in_range && enum_id == range->force) 369 continue; 370 } 371 /* GPIOs are only allowed to modify function fields. */ 372 } 373 374 if (!in_range) 375 continue; 376 377 ret = sh_pfc_get_config_reg(pfc, enum_id, &cr, &field, &value); 378 if (ret < 0) 379 return ret; 380 381 sh_pfc_write_config_reg(pfc, cr, field, value); 382 } 383 384 return 0; 385 } 386 387 const struct pinmux_bias_reg * 388 sh_pfc_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin, 389 unsigned int *bit) 390 { 391 unsigned int i, j; 392 393 for (i = 0; pfc->info->bias_regs[i].puen; i++) { 394 for (j = 0; j < ARRAY_SIZE(pfc->info->bias_regs[i].pins); j++) { 395 if (pfc->info->bias_regs[i].pins[j] == pin) { 396 *bit = j; 397 return &pfc->info->bias_regs[i]; 398 } 399 } 400 } 401 402 WARN_ONCE(1, "Pin %u is not in bias info list\n", pin); 403 404 return NULL; 405 } 406 407 static int sh_pfc_init_ranges(struct sh_pfc *pfc) 408 { 409 struct sh_pfc_pin_range *range; 410 unsigned int nr_ranges; 411 unsigned int i; 412 413 if (pfc->info->pins[0].pin == (u16)-1) { 414 /* Pin number -1 denotes that the SoC doesn't report pin numbers 415 * in its pin arrays yet. Consider the pin numbers range as 416 * continuous and allocate a single range. 417 */ 418 pfc->nr_ranges = 1; 419 pfc->ranges = devm_kzalloc(pfc->dev, sizeof(*pfc->ranges), 420 GFP_KERNEL); 421 if (pfc->ranges == NULL) 422 return -ENOMEM; 423 424 pfc->ranges->start = 0; 425 pfc->ranges->end = pfc->info->nr_pins - 1; 426 pfc->nr_gpio_pins = pfc->info->nr_pins; 427 428 return 0; 429 } 430 431 /* Count, allocate and fill the ranges. The PFC SoC data pins array must 432 * be sorted by pin numbers, and pins without a GPIO port must come 433 * last. 434 */ 435 for (i = 1, nr_ranges = 1; i < pfc->info->nr_pins; ++i) { 436 if (pfc->info->pins[i-1].pin != pfc->info->pins[i].pin - 1) 437 nr_ranges++; 438 } 439 440 pfc->nr_ranges = nr_ranges; 441 pfc->ranges = devm_kcalloc(pfc->dev, nr_ranges, sizeof(*pfc->ranges), 442 GFP_KERNEL); 443 if (pfc->ranges == NULL) 444 return -ENOMEM; 445 446 range = pfc->ranges; 447 range->start = pfc->info->pins[0].pin; 448 449 for (i = 1; i < pfc->info->nr_pins; ++i) { 450 if (pfc->info->pins[i-1].pin == pfc->info->pins[i].pin - 1) 451 continue; 452 453 range->end = pfc->info->pins[i-1].pin; 454 if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO)) 455 pfc->nr_gpio_pins = range->end + 1; 456 457 range++; 458 range->start = pfc->info->pins[i].pin; 459 } 460 461 range->end = pfc->info->pins[i-1].pin; 462 if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO)) 463 pfc->nr_gpio_pins = range->end + 1; 464 465 return 0; 466 } 467 468 #ifdef CONFIG_OF 469 static const struct of_device_id sh_pfc_of_table[] = { 470 #ifdef CONFIG_PINCTRL_PFC_EMEV2 471 { 472 .compatible = "renesas,pfc-emev2", 473 .data = &emev2_pinmux_info, 474 }, 475 #endif 476 #ifdef CONFIG_PINCTRL_PFC_R8A73A4 477 { 478 .compatible = "renesas,pfc-r8a73a4", 479 .data = &r8a73a4_pinmux_info, 480 }, 481 #endif 482 #ifdef CONFIG_PINCTRL_PFC_R8A7740 483 { 484 .compatible = "renesas,pfc-r8a7740", 485 .data = &r8a7740_pinmux_info, 486 }, 487 #endif 488 #ifdef CONFIG_PINCTRL_PFC_R8A7742 489 { 490 .compatible = "renesas,pfc-r8a7742", 491 .data = &r8a7742_pinmux_info, 492 }, 493 #endif 494 #ifdef CONFIG_PINCTRL_PFC_R8A7743 495 { 496 .compatible = "renesas,pfc-r8a7743", 497 .data = &r8a7743_pinmux_info, 498 }, 499 #endif 500 #ifdef CONFIG_PINCTRL_PFC_R8A7744 501 { 502 .compatible = "renesas,pfc-r8a7744", 503 .data = &r8a7744_pinmux_info, 504 }, 505 #endif 506 #ifdef CONFIG_PINCTRL_PFC_R8A7745 507 { 508 .compatible = "renesas,pfc-r8a7745", 509 .data = &r8a7745_pinmux_info, 510 }, 511 #endif 512 #ifdef CONFIG_PINCTRL_PFC_R8A77470 513 { 514 .compatible = "renesas,pfc-r8a77470", 515 .data = &r8a77470_pinmux_info, 516 }, 517 #endif 518 #ifdef CONFIG_PINCTRL_PFC_R8A774A1 519 { 520 .compatible = "renesas,pfc-r8a774a1", 521 .data = &r8a774a1_pinmux_info, 522 }, 523 #endif 524 #ifdef CONFIG_PINCTRL_PFC_R8A774B1 525 { 526 .compatible = "renesas,pfc-r8a774b1", 527 .data = &r8a774b1_pinmux_info, 528 }, 529 #endif 530 #ifdef CONFIG_PINCTRL_PFC_R8A774C0 531 { 532 .compatible = "renesas,pfc-r8a774c0", 533 .data = &r8a774c0_pinmux_info, 534 }, 535 #endif 536 #ifdef CONFIG_PINCTRL_PFC_R8A774E1 537 { 538 .compatible = "renesas,pfc-r8a774e1", 539 .data = &r8a774e1_pinmux_info, 540 }, 541 #endif 542 #ifdef CONFIG_PINCTRL_PFC_R8A7778 543 { 544 .compatible = "renesas,pfc-r8a7778", 545 .data = &r8a7778_pinmux_info, 546 }, 547 #endif 548 #ifdef CONFIG_PINCTRL_PFC_R8A7779 549 { 550 .compatible = "renesas,pfc-r8a7779", 551 .data = &r8a7779_pinmux_info, 552 }, 553 #endif 554 #ifdef CONFIG_PINCTRL_PFC_R8A7790 555 { 556 .compatible = "renesas,pfc-r8a7790", 557 .data = &r8a7790_pinmux_info, 558 }, 559 #endif 560 #ifdef CONFIG_PINCTRL_PFC_R8A7791 561 { 562 .compatible = "renesas,pfc-r8a7791", 563 .data = &r8a7791_pinmux_info, 564 }, 565 #endif 566 #ifdef CONFIG_PINCTRL_PFC_R8A7792 567 { 568 .compatible = "renesas,pfc-r8a7792", 569 .data = &r8a7792_pinmux_info, 570 }, 571 #endif 572 #ifdef CONFIG_PINCTRL_PFC_R8A7793 573 { 574 .compatible = "renesas,pfc-r8a7793", 575 .data = &r8a7793_pinmux_info, 576 }, 577 #endif 578 #ifdef CONFIG_PINCTRL_PFC_R8A7794 579 { 580 .compatible = "renesas,pfc-r8a7794", 581 .data = &r8a7794_pinmux_info, 582 }, 583 #endif 584 /* Both r8a7795 entries must be present to make sanity checks work */ 585 #ifdef CONFIG_PINCTRL_PFC_R8A77950 586 { 587 .compatible = "renesas,pfc-r8a7795", 588 .data = &r8a77950_pinmux_info, 589 }, 590 #endif 591 #ifdef CONFIG_PINCTRL_PFC_R8A77951 592 { 593 .compatible = "renesas,pfc-r8a7795", 594 .data = &r8a77951_pinmux_info, 595 }, 596 #endif 597 #ifdef CONFIG_PINCTRL_PFC_R8A77960 598 { 599 .compatible = "renesas,pfc-r8a7796", 600 .data = &r8a77960_pinmux_info, 601 }, 602 #endif 603 #ifdef CONFIG_PINCTRL_PFC_R8A77961 604 { 605 .compatible = "renesas,pfc-r8a77961", 606 .data = &r8a77961_pinmux_info, 607 }, 608 #endif 609 #ifdef CONFIG_PINCTRL_PFC_R8A77965 610 { 611 .compatible = "renesas,pfc-r8a77965", 612 .data = &r8a77965_pinmux_info, 613 }, 614 #endif 615 #ifdef CONFIG_PINCTRL_PFC_R8A77970 616 { 617 .compatible = "renesas,pfc-r8a77970", 618 .data = &r8a77970_pinmux_info, 619 }, 620 #endif 621 #ifdef CONFIG_PINCTRL_PFC_R8A77980 622 { 623 .compatible = "renesas,pfc-r8a77980", 624 .data = &r8a77980_pinmux_info, 625 }, 626 #endif 627 #ifdef CONFIG_PINCTRL_PFC_R8A77990 628 { 629 .compatible = "renesas,pfc-r8a77990", 630 .data = &r8a77990_pinmux_info, 631 }, 632 #endif 633 #ifdef CONFIG_PINCTRL_PFC_R8A77995 634 { 635 .compatible = "renesas,pfc-r8a77995", 636 .data = &r8a77995_pinmux_info, 637 }, 638 #endif 639 #ifdef CONFIG_PINCTRL_PFC_SH73A0 640 { 641 .compatible = "renesas,pfc-sh73a0", 642 .data = &sh73a0_pinmux_info, 643 }, 644 #endif 645 { }, 646 }; 647 #endif 648 649 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM_PSCI_FW) 650 static void sh_pfc_nop_reg(struct sh_pfc *pfc, u32 reg, unsigned int idx) 651 { 652 } 653 654 static void sh_pfc_save_reg(struct sh_pfc *pfc, u32 reg, unsigned int idx) 655 { 656 pfc->saved_regs[idx] = sh_pfc_read(pfc, reg); 657 } 658 659 static void sh_pfc_restore_reg(struct sh_pfc *pfc, u32 reg, unsigned int idx) 660 { 661 sh_pfc_write(pfc, reg, pfc->saved_regs[idx]); 662 } 663 664 static unsigned int sh_pfc_walk_regs(struct sh_pfc *pfc, 665 void (*do_reg)(struct sh_pfc *pfc, u32 reg, unsigned int idx)) 666 { 667 unsigned int i, n = 0; 668 669 if (pfc->info->cfg_regs) 670 for (i = 0; pfc->info->cfg_regs[i].reg; i++) 671 do_reg(pfc, pfc->info->cfg_regs[i].reg, n++); 672 673 if (pfc->info->drive_regs) 674 for (i = 0; pfc->info->drive_regs[i].reg; i++) 675 do_reg(pfc, pfc->info->drive_regs[i].reg, n++); 676 677 if (pfc->info->bias_regs) 678 for (i = 0; pfc->info->bias_regs[i].puen; i++) { 679 do_reg(pfc, pfc->info->bias_regs[i].puen, n++); 680 if (pfc->info->bias_regs[i].pud) 681 do_reg(pfc, pfc->info->bias_regs[i].pud, n++); 682 } 683 684 if (pfc->info->ioctrl_regs) 685 for (i = 0; pfc->info->ioctrl_regs[i].reg; i++) 686 do_reg(pfc, pfc->info->ioctrl_regs[i].reg, n++); 687 688 return n; 689 } 690 691 static int sh_pfc_suspend_init(struct sh_pfc *pfc) 692 { 693 unsigned int n; 694 695 /* This is the best we can do to check for the presence of PSCI */ 696 if (!psci_ops.cpu_suspend) 697 return 0; 698 699 n = sh_pfc_walk_regs(pfc, sh_pfc_nop_reg); 700 if (!n) 701 return 0; 702 703 pfc->saved_regs = devm_kmalloc_array(pfc->dev, n, 704 sizeof(*pfc->saved_regs), 705 GFP_KERNEL); 706 if (!pfc->saved_regs) 707 return -ENOMEM; 708 709 dev_dbg(pfc->dev, "Allocated space to save %u regs\n", n); 710 return 0; 711 } 712 713 static int sh_pfc_suspend_noirq(struct device *dev) 714 { 715 struct sh_pfc *pfc = dev_get_drvdata(dev); 716 717 if (pfc->saved_regs) 718 sh_pfc_walk_regs(pfc, sh_pfc_save_reg); 719 return 0; 720 } 721 722 static int sh_pfc_resume_noirq(struct device *dev) 723 { 724 struct sh_pfc *pfc = dev_get_drvdata(dev); 725 726 if (pfc->saved_regs) 727 sh_pfc_walk_regs(pfc, sh_pfc_restore_reg); 728 return 0; 729 } 730 731 static const struct dev_pm_ops sh_pfc_pm = { 732 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sh_pfc_suspend_noirq, sh_pfc_resume_noirq) 733 }; 734 #define DEV_PM_OPS &sh_pfc_pm 735 #else 736 static int sh_pfc_suspend_init(struct sh_pfc *pfc) { return 0; } 737 #define DEV_PM_OPS NULL 738 #endif /* CONFIG_PM_SLEEP && CONFIG_ARM_PSCI_FW */ 739 740 #ifdef DEBUG 741 #define SH_PFC_MAX_REGS 300 742 #define SH_PFC_MAX_ENUMS 3000 743 744 static unsigned int sh_pfc_errors __initdata = 0; 745 static unsigned int sh_pfc_warnings __initdata = 0; 746 static u32 *sh_pfc_regs __initdata = NULL; 747 static u32 sh_pfc_num_regs __initdata = 0; 748 static u16 *sh_pfc_enums __initdata = NULL; 749 static u32 sh_pfc_num_enums __initdata = 0; 750 751 #define sh_pfc_err(fmt, ...) \ 752 do { \ 753 pr_err("%s: " fmt, drvname, ##__VA_ARGS__); \ 754 sh_pfc_errors++; \ 755 } while (0) 756 #define sh_pfc_warn(fmt, ...) \ 757 do { \ 758 pr_warn("%s: " fmt, drvname, ##__VA_ARGS__); \ 759 sh_pfc_warnings++; \ 760 } while (0) 761 762 static bool __init is0s(const u16 *enum_ids, unsigned int n) 763 { 764 unsigned int i; 765 766 for (i = 0; i < n; i++) 767 if (enum_ids[i]) 768 return false; 769 770 return true; 771 } 772 773 static bool __init same_name(const char *a, const char *b) 774 { 775 if (!a || !b) 776 return false; 777 778 return !strcmp(a, b); 779 } 780 781 static void __init sh_pfc_check_reg(const char *drvname, u32 reg) 782 { 783 unsigned int i; 784 785 for (i = 0; i < sh_pfc_num_regs; i++) 786 if (reg == sh_pfc_regs[i]) { 787 sh_pfc_err("reg 0x%x conflict\n", reg); 788 return; 789 } 790 791 if (sh_pfc_num_regs == SH_PFC_MAX_REGS) { 792 pr_warn_once("%s: Please increase SH_PFC_MAX_REGS\n", drvname); 793 return; 794 } 795 796 sh_pfc_regs[sh_pfc_num_regs++] = reg; 797 } 798 799 static int __init sh_pfc_check_enum(const char *drvname, u16 enum_id) 800 { 801 unsigned int i; 802 803 for (i = 0; i < sh_pfc_num_enums; i++) { 804 if (enum_id == sh_pfc_enums[i]) 805 return -EINVAL; 806 } 807 808 if (sh_pfc_num_enums == SH_PFC_MAX_ENUMS) { 809 pr_warn_once("%s: Please increase SH_PFC_MAX_ENUMS\n", drvname); 810 return 0; 811 } 812 813 sh_pfc_enums[sh_pfc_num_enums++] = enum_id; 814 return 0; 815 } 816 817 static void __init sh_pfc_check_reg_enums(const char *drvname, u32 reg, 818 const u16 *enums, unsigned int n) 819 { 820 unsigned int i; 821 822 for (i = 0; i < n; i++) { 823 if (enums[i] && sh_pfc_check_enum(drvname, enums[i])) 824 sh_pfc_err("reg 0x%x enum_id %u conflict\n", reg, 825 enums[i]); 826 } 827 } 828 829 static void __init sh_pfc_check_pin(const struct sh_pfc_soc_info *info, 830 u32 reg, unsigned int pin) 831 { 832 const char *drvname = info->name; 833 unsigned int i; 834 835 if (pin == SH_PFC_PIN_NONE) 836 return; 837 838 for (i = 0; i < info->nr_pins; i++) { 839 if (pin == info->pins[i].pin) 840 return; 841 } 842 843 sh_pfc_err("reg 0x%x: pin %u not found\n", reg, pin); 844 } 845 846 static void __init sh_pfc_check_cfg_reg(const char *drvname, 847 const struct pinmux_cfg_reg *cfg_reg) 848 { 849 unsigned int i, n, rw, fw; 850 851 sh_pfc_check_reg(drvname, cfg_reg->reg); 852 853 if (cfg_reg->field_width) { 854 n = cfg_reg->reg_width / cfg_reg->field_width; 855 /* Skip field checks (done at build time) */ 856 goto check_enum_ids; 857 } 858 859 for (i = 0, n = 0, rw = 0; (fw = cfg_reg->var_field_width[i]); i++) { 860 if (fw > 3 && is0s(&cfg_reg->enum_ids[n], 1 << fw)) 861 sh_pfc_warn("reg 0x%x: reserved field [%u:%u] can be split to reduce table size\n", 862 cfg_reg->reg, rw, rw + fw - 1); 863 n += 1 << fw; 864 rw += fw; 865 } 866 867 if (rw != cfg_reg->reg_width) 868 sh_pfc_err("reg 0x%x: var_field_width declares %u instead of %u bits\n", 869 cfg_reg->reg, rw, cfg_reg->reg_width); 870 871 if (n != cfg_reg->nr_enum_ids) 872 sh_pfc_err("reg 0x%x: enum_ids[] has %u instead of %u values\n", 873 cfg_reg->reg, cfg_reg->nr_enum_ids, n); 874 875 check_enum_ids: 876 sh_pfc_check_reg_enums(drvname, cfg_reg->reg, cfg_reg->enum_ids, n); 877 } 878 879 static void __init sh_pfc_check_drive_reg(const struct sh_pfc_soc_info *info, 880 const struct pinmux_drive_reg *drive) 881 { 882 const char *drvname = info->name; 883 unsigned long seen = 0, mask; 884 unsigned int i; 885 886 sh_pfc_check_reg(info->name, drive->reg); 887 for (i = 0; i < ARRAY_SIZE(drive->fields); i++) { 888 const struct pinmux_drive_reg_field *field = &drive->fields[i]; 889 890 if (!field->pin && !field->offset && !field->size) 891 continue; 892 893 mask = GENMASK(field->offset + field->size, field->offset); 894 if (mask & seen) 895 sh_pfc_err("drive_reg 0x%x: field %u overlap\n", 896 drive->reg, i); 897 seen |= mask; 898 899 sh_pfc_check_pin(info, drive->reg, field->pin); 900 } 901 } 902 903 static void __init sh_pfc_check_bias_reg(const struct sh_pfc_soc_info *info, 904 const struct pinmux_bias_reg *bias) 905 { 906 unsigned int i; 907 908 sh_pfc_check_reg(info->name, bias->puen); 909 if (bias->pud) 910 sh_pfc_check_reg(info->name, bias->pud); 911 for (i = 0; i < ARRAY_SIZE(bias->pins); i++) 912 sh_pfc_check_pin(info, bias->puen, bias->pins[i]); 913 } 914 915 static void __init sh_pfc_check_info(const struct sh_pfc_soc_info *info) 916 { 917 const char *drvname = info->name; 918 unsigned int *refcnts; 919 unsigned int i, j, k; 920 921 pr_info("Checking %s\n", drvname); 922 sh_pfc_num_regs = 0; 923 sh_pfc_num_enums = 0; 924 925 /* Check pins */ 926 for (i = 0; i < info->nr_pins; i++) { 927 const struct sh_pfc_pin *pin = &info->pins[i]; 928 929 if (!pin->name) { 930 sh_pfc_err("empty pin %u\n", i); 931 continue; 932 } 933 for (j = 0; j < i; j++) { 934 const struct sh_pfc_pin *pin2 = &info->pins[j]; 935 936 if (same_name(pin->name, pin2->name)) 937 sh_pfc_err("pin %s: name conflict\n", 938 pin->name); 939 940 if (pin->pin != (u16)-1 && pin->pin == pin2->pin) 941 sh_pfc_err("pin %s/%s: pin %u conflict\n", 942 pin->name, pin2->name, pin->pin); 943 944 if (pin->enum_id && pin->enum_id == pin2->enum_id) 945 sh_pfc_err("pin %s/%s: enum_id %u conflict\n", 946 pin->name, pin2->name, 947 pin->enum_id); 948 } 949 } 950 951 /* Check groups and functions */ 952 refcnts = kcalloc(info->nr_groups, sizeof(*refcnts), GFP_KERNEL); 953 if (!refcnts) 954 return; 955 956 for (i = 0; i < info->nr_functions; i++) { 957 const struct sh_pfc_function *func = &info->functions[i]; 958 959 if (!func->name) { 960 sh_pfc_err("empty function %u\n", i); 961 continue; 962 } 963 for (j = 0; j < i; j++) { 964 if (same_name(func->name, info->functions[j].name)) 965 sh_pfc_err("function %s: name conflict\n", 966 func->name); 967 } 968 for (j = 0; j < func->nr_groups; j++) { 969 for (k = 0; k < info->nr_groups; k++) { 970 if (same_name(func->groups[j], 971 info->groups[k].name)) { 972 refcnts[k]++; 973 break; 974 } 975 } 976 977 if (k == info->nr_groups) 978 sh_pfc_err("function %s: group %s not found\n", 979 func->name, func->groups[j]); 980 } 981 } 982 983 for (i = 0; i < info->nr_groups; i++) { 984 const struct sh_pfc_pin_group *group = &info->groups[i]; 985 986 if (!group->name) { 987 sh_pfc_err("empty group %u\n", i); 988 continue; 989 } 990 for (j = 0; j < i; j++) { 991 if (same_name(group->name, info->groups[j].name)) 992 sh_pfc_err("group %s: name conflict\n", 993 group->name); 994 } 995 if (!refcnts[i]) 996 sh_pfc_err("orphan group %s\n", group->name); 997 else if (refcnts[i] > 1) 998 sh_pfc_warn("group %s referenced by %u functions\n", 999 group->name, refcnts[i]); 1000 } 1001 1002 kfree(refcnts); 1003 1004 /* Check config register descriptions */ 1005 for (i = 0; info->cfg_regs && info->cfg_regs[i].reg; i++) 1006 sh_pfc_check_cfg_reg(drvname, &info->cfg_regs[i]); 1007 1008 /* Check drive strength registers */ 1009 for (i = 0; info->drive_regs && info->drive_regs[i].reg; i++) 1010 sh_pfc_check_drive_reg(info, &info->drive_regs[i]); 1011 1012 /* Check bias registers */ 1013 for (i = 0; info->bias_regs && info->bias_regs[i].puen; i++) 1014 sh_pfc_check_bias_reg(info, &info->bias_regs[i]); 1015 1016 /* Check ioctrl registers */ 1017 for (i = 0; info->ioctrl_regs && info->ioctrl_regs[i].reg; i++) 1018 sh_pfc_check_reg(drvname, info->ioctrl_regs[i].reg); 1019 1020 /* Check data registers */ 1021 for (i = 0; info->data_regs && info->data_regs[i].reg; i++) { 1022 sh_pfc_check_reg(drvname, info->data_regs[i].reg); 1023 sh_pfc_check_reg_enums(drvname, info->data_regs[i].reg, 1024 info->data_regs[i].enum_ids, 1025 info->data_regs[i].reg_width); 1026 } 1027 1028 #ifdef CONFIG_PINCTRL_SH_FUNC_GPIO 1029 /* Check function GPIOs */ 1030 for (i = 0; i < info->nr_func_gpios; i++) { 1031 const struct pinmux_func *func = &info->func_gpios[i]; 1032 1033 if (!func->name) { 1034 sh_pfc_err("empty function gpio %u\n", i); 1035 continue; 1036 } 1037 for (j = 0; j < i; j++) { 1038 if (same_name(func->name, info->func_gpios[j].name)) 1039 sh_pfc_err("func_gpio %s: name conflict\n", 1040 func->name); 1041 } 1042 if (sh_pfc_check_enum(drvname, func->enum_id)) 1043 sh_pfc_err("%s enum_id %u conflict\n", func->name, 1044 func->enum_id); 1045 } 1046 #endif 1047 } 1048 1049 static void __init sh_pfc_check_driver(const struct platform_driver *pdrv) 1050 { 1051 unsigned int i; 1052 1053 sh_pfc_regs = kcalloc(SH_PFC_MAX_REGS, sizeof(*sh_pfc_regs), 1054 GFP_KERNEL); 1055 if (!sh_pfc_regs) 1056 return; 1057 1058 sh_pfc_enums = kcalloc(SH_PFC_MAX_ENUMS, sizeof(*sh_pfc_enums), 1059 GFP_KERNEL); 1060 if (!sh_pfc_enums) 1061 goto free_regs; 1062 1063 pr_warn("Checking builtin pinmux tables\n"); 1064 1065 for (i = 0; pdrv->id_table[i].name[0]; i++) 1066 sh_pfc_check_info((void *)pdrv->id_table[i].driver_data); 1067 1068 #ifdef CONFIG_OF 1069 for (i = 0; pdrv->driver.of_match_table[i].compatible[0]; i++) 1070 sh_pfc_check_info(pdrv->driver.of_match_table[i].data); 1071 #endif 1072 1073 pr_warn("Detected %u errors and %u warnings\n", sh_pfc_errors, 1074 sh_pfc_warnings); 1075 1076 kfree(sh_pfc_enums); 1077 free_regs: 1078 kfree(sh_pfc_regs); 1079 } 1080 1081 #else /* !DEBUG */ 1082 static inline void sh_pfc_check_driver(struct platform_driver *pdrv) {} 1083 #endif /* !DEBUG */ 1084 1085 #ifdef CONFIG_OF 1086 static const void *sh_pfc_quirk_match(void) 1087 { 1088 #if defined(CONFIG_PINCTRL_PFC_R8A77950) || \ 1089 defined(CONFIG_PINCTRL_PFC_R8A77951) 1090 const struct soc_device_attribute *match; 1091 static const struct soc_device_attribute quirks[] = { 1092 { 1093 .soc_id = "r8a7795", .revision = "ES1.*", 1094 .data = &r8a77950_pinmux_info, 1095 }, 1096 { 1097 .soc_id = "r8a7795", 1098 .data = &r8a77951_pinmux_info, 1099 }, 1100 1101 { /* sentinel */ } 1102 }; 1103 1104 match = soc_device_match(quirks); 1105 if (match) 1106 return match->data ?: ERR_PTR(-ENODEV); 1107 #endif /* CONFIG_PINCTRL_PFC_R8A77950 || CONFIG_PINCTRL_PFC_R8A77951 */ 1108 1109 return NULL; 1110 } 1111 #endif /* CONFIG_OF */ 1112 1113 static int sh_pfc_probe(struct platform_device *pdev) 1114 { 1115 const struct sh_pfc_soc_info *info; 1116 struct sh_pfc *pfc; 1117 int ret; 1118 1119 #ifdef CONFIG_OF 1120 if (pdev->dev.of_node) { 1121 info = sh_pfc_quirk_match(); 1122 if (IS_ERR(info)) 1123 return PTR_ERR(info); 1124 1125 if (!info) 1126 info = of_device_get_match_data(&pdev->dev); 1127 } else 1128 #endif 1129 info = (const void *)platform_get_device_id(pdev)->driver_data; 1130 1131 pfc = devm_kzalloc(&pdev->dev, sizeof(*pfc), GFP_KERNEL); 1132 if (pfc == NULL) 1133 return -ENOMEM; 1134 1135 pfc->info = info; 1136 pfc->dev = &pdev->dev; 1137 1138 ret = sh_pfc_map_resources(pfc, pdev); 1139 if (unlikely(ret < 0)) 1140 return ret; 1141 1142 spin_lock_init(&pfc->lock); 1143 1144 if (info->ops && info->ops->init) { 1145 ret = info->ops->init(pfc); 1146 if (ret < 0) 1147 return ret; 1148 1149 /* .init() may have overridden pfc->info */ 1150 info = pfc->info; 1151 } 1152 1153 ret = sh_pfc_suspend_init(pfc); 1154 if (ret) 1155 return ret; 1156 1157 /* Enable dummy states for those platforms without pinctrl support */ 1158 if (!of_have_populated_dt()) 1159 pinctrl_provide_dummies(); 1160 1161 ret = sh_pfc_init_ranges(pfc); 1162 if (ret < 0) 1163 return ret; 1164 1165 /* 1166 * Initialize pinctrl bindings first 1167 */ 1168 ret = sh_pfc_register_pinctrl(pfc); 1169 if (unlikely(ret != 0)) 1170 return ret; 1171 1172 #ifdef CONFIG_PINCTRL_SH_PFC_GPIO 1173 /* 1174 * Then the GPIO chip 1175 */ 1176 ret = sh_pfc_register_gpiochip(pfc); 1177 if (unlikely(ret != 0)) { 1178 /* 1179 * If the GPIO chip fails to come up we still leave the 1180 * PFC state as it is, given that there are already 1181 * extant users of it that have succeeded by this point. 1182 */ 1183 dev_notice(pfc->dev, "failed to init GPIO chip, ignoring...\n"); 1184 } 1185 #endif 1186 1187 platform_set_drvdata(pdev, pfc); 1188 1189 dev_info(pfc->dev, "%s support registered\n", info->name); 1190 1191 return 0; 1192 } 1193 1194 static const struct platform_device_id sh_pfc_id_table[] = { 1195 #ifdef CONFIG_PINCTRL_PFC_SH7203 1196 { "pfc-sh7203", (kernel_ulong_t)&sh7203_pinmux_info }, 1197 #endif 1198 #ifdef CONFIG_PINCTRL_PFC_SH7264 1199 { "pfc-sh7264", (kernel_ulong_t)&sh7264_pinmux_info }, 1200 #endif 1201 #ifdef CONFIG_PINCTRL_PFC_SH7269 1202 { "pfc-sh7269", (kernel_ulong_t)&sh7269_pinmux_info }, 1203 #endif 1204 #ifdef CONFIG_PINCTRL_PFC_SH7720 1205 { "pfc-sh7720", (kernel_ulong_t)&sh7720_pinmux_info }, 1206 #endif 1207 #ifdef CONFIG_PINCTRL_PFC_SH7722 1208 { "pfc-sh7722", (kernel_ulong_t)&sh7722_pinmux_info }, 1209 #endif 1210 #ifdef CONFIG_PINCTRL_PFC_SH7723 1211 { "pfc-sh7723", (kernel_ulong_t)&sh7723_pinmux_info }, 1212 #endif 1213 #ifdef CONFIG_PINCTRL_PFC_SH7724 1214 { "pfc-sh7724", (kernel_ulong_t)&sh7724_pinmux_info }, 1215 #endif 1216 #ifdef CONFIG_PINCTRL_PFC_SH7734 1217 { "pfc-sh7734", (kernel_ulong_t)&sh7734_pinmux_info }, 1218 #endif 1219 #ifdef CONFIG_PINCTRL_PFC_SH7757 1220 { "pfc-sh7757", (kernel_ulong_t)&sh7757_pinmux_info }, 1221 #endif 1222 #ifdef CONFIG_PINCTRL_PFC_SH7785 1223 { "pfc-sh7785", (kernel_ulong_t)&sh7785_pinmux_info }, 1224 #endif 1225 #ifdef CONFIG_PINCTRL_PFC_SH7786 1226 { "pfc-sh7786", (kernel_ulong_t)&sh7786_pinmux_info }, 1227 #endif 1228 #ifdef CONFIG_PINCTRL_PFC_SHX3 1229 { "pfc-shx3", (kernel_ulong_t)&shx3_pinmux_info }, 1230 #endif 1231 { }, 1232 }; 1233 1234 static struct platform_driver sh_pfc_driver = { 1235 .probe = sh_pfc_probe, 1236 .id_table = sh_pfc_id_table, 1237 .driver = { 1238 .name = DRV_NAME, 1239 .of_match_table = of_match_ptr(sh_pfc_of_table), 1240 .pm = DEV_PM_OPS, 1241 }, 1242 }; 1243 1244 static int __init sh_pfc_init(void) 1245 { 1246 sh_pfc_check_driver(&sh_pfc_driver); 1247 return platform_driver_register(&sh_pfc_driver); 1248 } 1249 postcore_initcall(sh_pfc_init); 1250