1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2015, Sony Mobile Communications AB.
4  * Copyright (c) 2013, The Linux Foundation. All rights reserved.
5  */
6 
7 #include <linux/module.h>
8 #include <linux/platform_device.h>
9 #include <linux/pinctrl/pinctrl.h>
10 #include <linux/pinctrl/pinmux.h>
11 #include <linux/pinctrl/pinconf.h>
12 #include <linux/pinctrl/pinconf-generic.h>
13 #include <linux/slab.h>
14 #include <linux/regmap.h>
15 #include <linux/gpio/driver.h>
16 #include <linux/interrupt.h>
17 #include <linux/of_device.h>
18 #include <linux/of_irq.h>
19 
20 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
21 
22 #include "../core.h"
23 #include "../pinctrl-utils.h"
24 
25 /* mode */
26 #define PM8XXX_GPIO_MODE_ENABLED	BIT(0)
27 #define PM8XXX_GPIO_MODE_INPUT		0
28 #define PM8XXX_GPIO_MODE_OUTPUT		2
29 
30 /* output buffer */
31 #define PM8XXX_GPIO_PUSH_PULL		0
32 #define PM8XXX_GPIO_OPEN_DRAIN		1
33 
34 /* bias */
35 #define PM8XXX_GPIO_BIAS_PU_30		0
36 #define PM8XXX_GPIO_BIAS_PU_1P5		1
37 #define PM8XXX_GPIO_BIAS_PU_31P5	2
38 #define PM8XXX_GPIO_BIAS_PU_1P5_30	3
39 #define PM8XXX_GPIO_BIAS_PD		4
40 #define PM8XXX_GPIO_BIAS_NP		5
41 
42 /* GPIO registers */
43 #define SSBI_REG_ADDR_GPIO_BASE		0x150
44 #define SSBI_REG_ADDR_GPIO(n)		(SSBI_REG_ADDR_GPIO_BASE + n)
45 
46 #define PM8XXX_BANK_WRITE		BIT(7)
47 
48 #define PM8XXX_MAX_GPIOS               44
49 
50 #define PM8XXX_GPIO_PHYSICAL_OFFSET	1
51 
52 /* custom pinconf parameters */
53 #define PM8XXX_QCOM_DRIVE_STRENGH      (PIN_CONFIG_END + 1)
54 #define PM8XXX_QCOM_PULL_UP_STRENGTH   (PIN_CONFIG_END + 2)
55 
56 /**
57  * struct pm8xxx_pin_data - dynamic configuration for a pin
58  * @reg:               address of the control register
59  * @power_source:      logical selected voltage source, mapping in static data
60  *                     is used translate to register values
61  * @mode:              operating mode for the pin (input/output)
62  * @open_drain:        output buffer configured as open-drain (vs push-pull)
63  * @output_value:      configured output value
64  * @bias:              register view of configured bias
65  * @pull_up_strength:  placeholder for selected pull up strength
66  *                     only used to configure bias when pull up is selected
67  * @output_strength:   selector of output-strength
68  * @disable:           pin disabled / configured as tristate
69  * @function:          pinmux selector
70  * @inverted:          pin logic is inverted
71  */
72 struct pm8xxx_pin_data {
73 	unsigned reg;
74 	u8 power_source;
75 	u8 mode;
76 	bool open_drain;
77 	bool output_value;
78 	u8 bias;
79 	u8 pull_up_strength;
80 	u8 output_strength;
81 	bool disable;
82 	u8 function;
83 	bool inverted;
84 };
85 
86 struct pm8xxx_gpio {
87 	struct device *dev;
88 	struct regmap *regmap;
89 	struct pinctrl_dev *pctrl;
90 	struct gpio_chip chip;
91 
92 	struct pinctrl_desc desc;
93 	unsigned npins;
94 };
95 
96 static const struct pinconf_generic_params pm8xxx_gpio_bindings[] = {
97 	{"qcom,drive-strength",		PM8XXX_QCOM_DRIVE_STRENGH,	0},
98 	{"qcom,pull-up-strength",	PM8XXX_QCOM_PULL_UP_STRENGTH,	0},
99 };
100 
101 #ifdef CONFIG_DEBUG_FS
102 static const struct pin_config_item pm8xxx_conf_items[ARRAY_SIZE(pm8xxx_gpio_bindings)] = {
103 	PCONFDUMP(PM8XXX_QCOM_DRIVE_STRENGH, "drive-strength", NULL, true),
104 	PCONFDUMP(PM8XXX_QCOM_PULL_UP_STRENGTH,  "pull up strength", NULL, true),
105 };
106 #endif
107 
108 static const char * const pm8xxx_groups[PM8XXX_MAX_GPIOS] = {
109 	"gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", "gpio8",
110 	"gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", "gpio15",
111 	"gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", "gpio22",
112 	"gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29",
113 	"gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", "gpio36",
114 	"gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", "gpio43",
115 	"gpio44",
116 };
117 
118 static const char * const pm8xxx_gpio_functions[] = {
119 	PMIC_GPIO_FUNC_NORMAL, PMIC_GPIO_FUNC_PAIRED,
120 	PMIC_GPIO_FUNC_FUNC1, PMIC_GPIO_FUNC_FUNC2,
121 	PMIC_GPIO_FUNC_DTEST1, PMIC_GPIO_FUNC_DTEST2,
122 	PMIC_GPIO_FUNC_DTEST3, PMIC_GPIO_FUNC_DTEST4,
123 };
124 
125 static int pm8xxx_read_bank(struct pm8xxx_gpio *pctrl,
126 			    struct pm8xxx_pin_data *pin, int bank)
127 {
128 	unsigned int val = bank << 4;
129 	int ret;
130 
131 	ret = regmap_write(pctrl->regmap, pin->reg, val);
132 	if (ret) {
133 		dev_err(pctrl->dev, "failed to select bank %d\n", bank);
134 		return ret;
135 	}
136 
137 	ret = regmap_read(pctrl->regmap, pin->reg, &val);
138 	if (ret) {
139 		dev_err(pctrl->dev, "failed to read register %d\n", bank);
140 		return ret;
141 	}
142 
143 	return val;
144 }
145 
146 static int pm8xxx_write_bank(struct pm8xxx_gpio *pctrl,
147 			     struct pm8xxx_pin_data *pin,
148 			     int bank,
149 			     u8 val)
150 {
151 	int ret;
152 
153 	val |= PM8XXX_BANK_WRITE;
154 	val |= bank << 4;
155 
156 	ret = regmap_write(pctrl->regmap, pin->reg, val);
157 	if (ret)
158 		dev_err(pctrl->dev, "failed to write register\n");
159 
160 	return ret;
161 }
162 
163 static int pm8xxx_get_groups_count(struct pinctrl_dev *pctldev)
164 {
165 	struct pm8xxx_gpio *pctrl = pinctrl_dev_get_drvdata(pctldev);
166 
167 	return pctrl->npins;
168 }
169 
170 static const char *pm8xxx_get_group_name(struct pinctrl_dev *pctldev,
171 					 unsigned group)
172 {
173 	return pm8xxx_groups[group];
174 }
175 
176 
177 static int pm8xxx_get_group_pins(struct pinctrl_dev *pctldev,
178 				 unsigned group,
179 				 const unsigned **pins,
180 				 unsigned *num_pins)
181 {
182 	struct pm8xxx_gpio *pctrl = pinctrl_dev_get_drvdata(pctldev);
183 
184 	*pins = &pctrl->desc.pins[group].number;
185 	*num_pins = 1;
186 
187 	return 0;
188 }
189 
190 static const struct pinctrl_ops pm8xxx_pinctrl_ops = {
191 	.get_groups_count	= pm8xxx_get_groups_count,
192 	.get_group_name		= pm8xxx_get_group_name,
193 	.get_group_pins         = pm8xxx_get_group_pins,
194 	.dt_node_to_map		= pinconf_generic_dt_node_to_map_group,
195 	.dt_free_map		= pinctrl_utils_free_map,
196 };
197 
198 static int pm8xxx_get_functions_count(struct pinctrl_dev *pctldev)
199 {
200 	return ARRAY_SIZE(pm8xxx_gpio_functions);
201 }
202 
203 static const char *pm8xxx_get_function_name(struct pinctrl_dev *pctldev,
204 					    unsigned function)
205 {
206 	return pm8xxx_gpio_functions[function];
207 }
208 
209 static int pm8xxx_get_function_groups(struct pinctrl_dev *pctldev,
210 				      unsigned function,
211 				      const char * const **groups,
212 				      unsigned * const num_groups)
213 {
214 	struct pm8xxx_gpio *pctrl = pinctrl_dev_get_drvdata(pctldev);
215 
216 	*groups = pm8xxx_groups;
217 	*num_groups = pctrl->npins;
218 	return 0;
219 }
220 
221 static int pm8xxx_pinmux_set_mux(struct pinctrl_dev *pctldev,
222 				 unsigned function,
223 				 unsigned group)
224 {
225 	struct pm8xxx_gpio *pctrl = pinctrl_dev_get_drvdata(pctldev);
226 	struct pm8xxx_pin_data *pin = pctrl->desc.pins[group].drv_data;
227 	u8 val;
228 
229 	pin->function = function;
230 	val = pin->function << 1;
231 
232 	pm8xxx_write_bank(pctrl, pin, 4, val);
233 
234 	return 0;
235 }
236 
237 static const struct pinmux_ops pm8xxx_pinmux_ops = {
238 	.get_functions_count	= pm8xxx_get_functions_count,
239 	.get_function_name	= pm8xxx_get_function_name,
240 	.get_function_groups	= pm8xxx_get_function_groups,
241 	.set_mux		= pm8xxx_pinmux_set_mux,
242 };
243 
244 static int pm8xxx_pin_config_get(struct pinctrl_dev *pctldev,
245 				 unsigned int offset,
246 				 unsigned long *config)
247 {
248 	struct pm8xxx_gpio *pctrl = pinctrl_dev_get_drvdata(pctldev);
249 	struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
250 	unsigned param = pinconf_to_config_param(*config);
251 	unsigned arg;
252 
253 	switch (param) {
254 	case PIN_CONFIG_BIAS_DISABLE:
255 		if (pin->bias != PM8XXX_GPIO_BIAS_NP)
256 			return -EINVAL;
257 		arg = 1;
258 		break;
259 	case PIN_CONFIG_BIAS_PULL_DOWN:
260 		if (pin->bias != PM8XXX_GPIO_BIAS_PD)
261 			return -EINVAL;
262 		arg = 1;
263 		break;
264 	case PIN_CONFIG_BIAS_PULL_UP:
265 		if (pin->bias > PM8XXX_GPIO_BIAS_PU_1P5_30)
266 			return -EINVAL;
267 		arg = 1;
268 		break;
269 	case PM8XXX_QCOM_PULL_UP_STRENGTH:
270 		arg = pin->pull_up_strength;
271 		break;
272 	case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
273 		if (!pin->disable)
274 			return -EINVAL;
275 		arg = 1;
276 		break;
277 	case PIN_CONFIG_INPUT_ENABLE:
278 		if (pin->mode != PM8XXX_GPIO_MODE_INPUT)
279 			return -EINVAL;
280 		arg = 1;
281 		break;
282 	case PIN_CONFIG_OUTPUT:
283 		if (pin->mode & PM8XXX_GPIO_MODE_OUTPUT)
284 			arg = pin->output_value;
285 		else
286 			arg = 0;
287 		break;
288 	case PIN_CONFIG_POWER_SOURCE:
289 		arg = pin->power_source;
290 		break;
291 	case PM8XXX_QCOM_DRIVE_STRENGH:
292 		arg = pin->output_strength;
293 		break;
294 	case PIN_CONFIG_DRIVE_PUSH_PULL:
295 		if (pin->open_drain)
296 			return -EINVAL;
297 		arg = 1;
298 		break;
299 	case PIN_CONFIG_DRIVE_OPEN_DRAIN:
300 		if (!pin->open_drain)
301 			return -EINVAL;
302 		arg = 1;
303 		break;
304 	default:
305 		return -EINVAL;
306 	}
307 
308 	*config = pinconf_to_config_packed(param, arg);
309 
310 	return 0;
311 }
312 
313 static int pm8xxx_pin_config_set(struct pinctrl_dev *pctldev,
314 				 unsigned int offset,
315 				 unsigned long *configs,
316 				 unsigned num_configs)
317 {
318 	struct pm8xxx_gpio *pctrl = pinctrl_dev_get_drvdata(pctldev);
319 	struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
320 	unsigned param;
321 	unsigned arg;
322 	unsigned i;
323 	u8 banks = 0;
324 	u8 val;
325 
326 	for (i = 0; i < num_configs; i++) {
327 		param = pinconf_to_config_param(configs[i]);
328 		arg = pinconf_to_config_argument(configs[i]);
329 
330 		switch (param) {
331 		case PIN_CONFIG_BIAS_DISABLE:
332 			pin->bias = PM8XXX_GPIO_BIAS_NP;
333 			banks |= BIT(2);
334 			pin->disable = 0;
335 			banks |= BIT(3);
336 			break;
337 		case PIN_CONFIG_BIAS_PULL_DOWN:
338 			pin->bias = PM8XXX_GPIO_BIAS_PD;
339 			banks |= BIT(2);
340 			pin->disable = 0;
341 			banks |= BIT(3);
342 			break;
343 		case PM8XXX_QCOM_PULL_UP_STRENGTH:
344 			if (arg > PM8XXX_GPIO_BIAS_PU_1P5_30) {
345 				dev_err(pctrl->dev, "invalid pull-up strength\n");
346 				return -EINVAL;
347 			}
348 			pin->pull_up_strength = arg;
349 			fallthrough;
350 		case PIN_CONFIG_BIAS_PULL_UP:
351 			pin->bias = pin->pull_up_strength;
352 			banks |= BIT(2);
353 			pin->disable = 0;
354 			banks |= BIT(3);
355 			break;
356 		case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
357 			pin->disable = 1;
358 			banks |= BIT(3);
359 			break;
360 		case PIN_CONFIG_INPUT_ENABLE:
361 			pin->mode = PM8XXX_GPIO_MODE_INPUT;
362 			banks |= BIT(0) | BIT(1);
363 			break;
364 		case PIN_CONFIG_OUTPUT:
365 			pin->mode = PM8XXX_GPIO_MODE_OUTPUT;
366 			pin->output_value = !!arg;
367 			banks |= BIT(0) | BIT(1);
368 			break;
369 		case PIN_CONFIG_POWER_SOURCE:
370 			pin->power_source = arg;
371 			banks |= BIT(0);
372 			break;
373 		case PM8XXX_QCOM_DRIVE_STRENGH:
374 			if (arg > PMIC_GPIO_STRENGTH_LOW) {
375 				dev_err(pctrl->dev, "invalid drive strength\n");
376 				return -EINVAL;
377 			}
378 			pin->output_strength = arg;
379 			banks |= BIT(3);
380 			break;
381 		case PIN_CONFIG_DRIVE_PUSH_PULL:
382 			pin->open_drain = 0;
383 			banks |= BIT(1);
384 			break;
385 		case PIN_CONFIG_DRIVE_OPEN_DRAIN:
386 			pin->open_drain = 1;
387 			banks |= BIT(1);
388 			break;
389 		default:
390 			dev_err(pctrl->dev,
391 				"unsupported config parameter: %x\n",
392 				param);
393 			return -EINVAL;
394 		}
395 	}
396 
397 	if (banks & BIT(0)) {
398 		val = pin->power_source << 1;
399 		val |= PM8XXX_GPIO_MODE_ENABLED;
400 		pm8xxx_write_bank(pctrl, pin, 0, val);
401 	}
402 
403 	if (banks & BIT(1)) {
404 		val = pin->mode << 2;
405 		val |= pin->open_drain << 1;
406 		val |= pin->output_value;
407 		pm8xxx_write_bank(pctrl, pin, 1, val);
408 	}
409 
410 	if (banks & BIT(2)) {
411 		val = pin->bias << 1;
412 		pm8xxx_write_bank(pctrl, pin, 2, val);
413 	}
414 
415 	if (banks & BIT(3)) {
416 		val = pin->output_strength << 2;
417 		val |= pin->disable;
418 		pm8xxx_write_bank(pctrl, pin, 3, val);
419 	}
420 
421 	if (banks & BIT(4)) {
422 		val = pin->function << 1;
423 		pm8xxx_write_bank(pctrl, pin, 4, val);
424 	}
425 
426 	if (banks & BIT(5)) {
427 		val = 0;
428 		if (!pin->inverted)
429 			val |= BIT(3);
430 		pm8xxx_write_bank(pctrl, pin, 5, val);
431 	}
432 
433 	return 0;
434 }
435 
436 static const struct pinconf_ops pm8xxx_pinconf_ops = {
437 	.is_generic = true,
438 	.pin_config_group_get = pm8xxx_pin_config_get,
439 	.pin_config_group_set = pm8xxx_pin_config_set,
440 };
441 
442 static const struct pinctrl_desc pm8xxx_pinctrl_desc = {
443 	.name = "pm8xxx_gpio",
444 	.pctlops = &pm8xxx_pinctrl_ops,
445 	.pmxops = &pm8xxx_pinmux_ops,
446 	.confops = &pm8xxx_pinconf_ops,
447 	.owner = THIS_MODULE,
448 };
449 
450 static int pm8xxx_gpio_direction_input(struct gpio_chip *chip,
451 				       unsigned offset)
452 {
453 	struct pm8xxx_gpio *pctrl = gpiochip_get_data(chip);
454 	struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
455 	u8 val;
456 
457 	pin->mode = PM8XXX_GPIO_MODE_INPUT;
458 	val = pin->mode << 2;
459 
460 	pm8xxx_write_bank(pctrl, pin, 1, val);
461 
462 	return 0;
463 }
464 
465 static int pm8xxx_gpio_direction_output(struct gpio_chip *chip,
466 					unsigned offset,
467 					int value)
468 {
469 	struct pm8xxx_gpio *pctrl = gpiochip_get_data(chip);
470 	struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
471 	u8 val;
472 
473 	pin->mode = PM8XXX_GPIO_MODE_OUTPUT;
474 	pin->output_value = !!value;
475 
476 	val = pin->mode << 2;
477 	val |= pin->open_drain << 1;
478 	val |= pin->output_value;
479 
480 	pm8xxx_write_bank(pctrl, pin, 1, val);
481 
482 	return 0;
483 }
484 
485 static int pm8xxx_gpio_get(struct gpio_chip *chip, unsigned offset)
486 {
487 	struct pm8xxx_gpio *pctrl = gpiochip_get_data(chip);
488 	struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
489 	int ret, irq;
490 	bool state;
491 
492 	if (pin->mode == PM8XXX_GPIO_MODE_OUTPUT)
493 		return pin->output_value;
494 
495 	irq = chip->to_irq(chip, offset);
496 	if (irq >= 0) {
497 		ret = irq_get_irqchip_state(irq, IRQCHIP_STATE_LINE_LEVEL,
498 					    &state);
499 		if (!ret)
500 			ret = !!state;
501 	} else
502 		ret = -EINVAL;
503 
504 	return ret;
505 }
506 
507 static void pm8xxx_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
508 {
509 	struct pm8xxx_gpio *pctrl = gpiochip_get_data(chip);
510 	struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
511 	u8 val;
512 
513 	pin->output_value = !!value;
514 
515 	val = pin->mode << 2;
516 	val |= pin->open_drain << 1;
517 	val |= pin->output_value;
518 
519 	pm8xxx_write_bank(pctrl, pin, 1, val);
520 }
521 
522 static int pm8xxx_gpio_of_xlate(struct gpio_chip *chip,
523 				const struct of_phandle_args *gpio_desc,
524 				u32 *flags)
525 {
526 	if (chip->of_gpio_n_cells < 2)
527 		return -EINVAL;
528 
529 	if (flags)
530 		*flags = gpio_desc->args[1];
531 
532 	return gpio_desc->args[0] - PM8XXX_GPIO_PHYSICAL_OFFSET;
533 }
534 
535 
536 #ifdef CONFIG_DEBUG_FS
537 #include <linux/seq_file.h>
538 
539 static void pm8xxx_gpio_dbg_show_one(struct seq_file *s,
540 				  struct pinctrl_dev *pctldev,
541 				  struct gpio_chip *chip,
542 				  unsigned offset,
543 				  unsigned gpio)
544 {
545 	struct pm8xxx_gpio *pctrl = gpiochip_get_data(chip);
546 	struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
547 
548 	static const char * const modes[] = {
549 		"in", "both", "out", "off"
550 	};
551 	static const char * const biases[] = {
552 		"pull-up 30uA", "pull-up 1.5uA", "pull-up 31.5uA",
553 		"pull-up 1.5uA + 30uA boost", "pull-down 10uA", "no pull"
554 	};
555 	static const char * const buffer_types[] = {
556 		"push-pull", "open-drain"
557 	};
558 	static const char * const strengths[] = {
559 		"no", "high", "medium", "low"
560 	};
561 
562 	seq_printf(s, " gpio%-2d:", offset + PM8XXX_GPIO_PHYSICAL_OFFSET);
563 	if (pin->disable) {
564 		seq_puts(s, " ---");
565 	} else {
566 		seq_printf(s, " %-4s", modes[pin->mode]);
567 		seq_printf(s, " %-7s", pm8xxx_gpio_functions[pin->function]);
568 		seq_printf(s, " VIN%d", pin->power_source);
569 		seq_printf(s, " %-27s", biases[pin->bias]);
570 		seq_printf(s, " %-10s", buffer_types[pin->open_drain]);
571 		seq_printf(s, " %-4s", pin->output_value ? "high" : "low");
572 		seq_printf(s, " %-7s", strengths[pin->output_strength]);
573 		if (pin->inverted)
574 			seq_puts(s, " inverted");
575 	}
576 }
577 
578 static void pm8xxx_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
579 {
580 	unsigned gpio = chip->base;
581 	unsigned i;
582 
583 	for (i = 0; i < chip->ngpio; i++, gpio++) {
584 		pm8xxx_gpio_dbg_show_one(s, NULL, chip, i, gpio);
585 		seq_puts(s, "\n");
586 	}
587 }
588 
589 #else
590 #define pm8xxx_gpio_dbg_show NULL
591 #endif
592 
593 static const struct gpio_chip pm8xxx_gpio_template = {
594 	.direction_input = pm8xxx_gpio_direction_input,
595 	.direction_output = pm8xxx_gpio_direction_output,
596 	.get = pm8xxx_gpio_get,
597 	.set = pm8xxx_gpio_set,
598 	.of_xlate = pm8xxx_gpio_of_xlate,
599 	.dbg_show = pm8xxx_gpio_dbg_show,
600 	.owner = THIS_MODULE,
601 };
602 
603 static int pm8xxx_pin_populate(struct pm8xxx_gpio *pctrl,
604 			       struct pm8xxx_pin_data *pin)
605 {
606 	int val;
607 
608 	val = pm8xxx_read_bank(pctrl, pin, 0);
609 	if (val < 0)
610 		return val;
611 
612 	pin->power_source = (val >> 1) & 0x7;
613 
614 	val = pm8xxx_read_bank(pctrl, pin, 1);
615 	if (val < 0)
616 		return val;
617 
618 	pin->mode = (val >> 2) & 0x3;
619 	pin->open_drain = !!(val & BIT(1));
620 	pin->output_value = val & BIT(0);
621 
622 	val = pm8xxx_read_bank(pctrl, pin, 2);
623 	if (val < 0)
624 		return val;
625 
626 	pin->bias = (val >> 1) & 0x7;
627 	if (pin->bias <= PM8XXX_GPIO_BIAS_PU_1P5_30)
628 		pin->pull_up_strength = pin->bias;
629 	else
630 		pin->pull_up_strength = PM8XXX_GPIO_BIAS_PU_30;
631 
632 	val = pm8xxx_read_bank(pctrl, pin, 3);
633 	if (val < 0)
634 		return val;
635 
636 	pin->output_strength = (val >> 2) & 0x3;
637 	pin->disable = val & BIT(0);
638 
639 	val = pm8xxx_read_bank(pctrl, pin, 4);
640 	if (val < 0)
641 		return val;
642 
643 	pin->function = (val >> 1) & 0x7;
644 
645 	val = pm8xxx_read_bank(pctrl, pin, 5);
646 	if (val < 0)
647 		return val;
648 
649 	pin->inverted = !(val & BIT(3));
650 
651 	return 0;
652 }
653 
654 static struct irq_chip pm8xxx_irq_chip = {
655 	.name = "ssbi-gpio",
656 	.irq_mask_ack = irq_chip_mask_ack_parent,
657 	.irq_unmask = irq_chip_unmask_parent,
658 	.irq_set_type = irq_chip_set_type_parent,
659 	.flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SKIP_SET_WAKE,
660 };
661 
662 static int pm8xxx_domain_translate(struct irq_domain *domain,
663 				   struct irq_fwspec *fwspec,
664 				   unsigned long *hwirq,
665 				   unsigned int *type)
666 {
667 	struct pm8xxx_gpio *pctrl = container_of(domain->host_data,
668 						 struct pm8xxx_gpio, chip);
669 
670 	if (fwspec->param_count != 2 || fwspec->param[0] < 1 ||
671 	    fwspec->param[0] > pctrl->chip.ngpio)
672 		return -EINVAL;
673 
674 	*hwirq = fwspec->param[0] - PM8XXX_GPIO_PHYSICAL_OFFSET;
675 	*type = fwspec->param[1];
676 
677 	return 0;
678 }
679 
680 static unsigned int pm8xxx_child_offset_to_irq(struct gpio_chip *chip,
681 					       unsigned int offset)
682 {
683 	return offset + PM8XXX_GPIO_PHYSICAL_OFFSET;
684 }
685 
686 static int pm8xxx_child_to_parent_hwirq(struct gpio_chip *chip,
687 					unsigned int child_hwirq,
688 					unsigned int child_type,
689 					unsigned int *parent_hwirq,
690 					unsigned int *parent_type)
691 {
692 	*parent_hwirq = child_hwirq + 0xc0;
693 	*parent_type = child_type;
694 
695 	return 0;
696 }
697 
698 static const struct of_device_id pm8xxx_gpio_of_match[] = {
699 	{ .compatible = "qcom,pm8018-gpio", .data = (void *) 6 },
700 	{ .compatible = "qcom,pm8038-gpio", .data = (void *) 12 },
701 	{ .compatible = "qcom,pm8058-gpio", .data = (void *) 44 },
702 	{ .compatible = "qcom,pm8917-gpio", .data = (void *) 38 },
703 	{ .compatible = "qcom,pm8921-gpio", .data = (void *) 44 },
704 	{ },
705 };
706 MODULE_DEVICE_TABLE(of, pm8xxx_gpio_of_match);
707 
708 static int pm8xxx_gpio_probe(struct platform_device *pdev)
709 {
710 	struct pm8xxx_pin_data *pin_data;
711 	struct irq_domain *parent_domain;
712 	struct device_node *parent_node;
713 	struct pinctrl_pin_desc *pins;
714 	struct gpio_irq_chip *girq;
715 	struct pm8xxx_gpio *pctrl;
716 	int ret, i;
717 
718 	pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
719 	if (!pctrl)
720 		return -ENOMEM;
721 
722 	pctrl->dev = &pdev->dev;
723 	pctrl->npins = (uintptr_t) device_get_match_data(&pdev->dev);
724 
725 	pctrl->regmap = dev_get_regmap(pdev->dev.parent, NULL);
726 	if (!pctrl->regmap) {
727 		dev_err(&pdev->dev, "parent regmap unavailable\n");
728 		return -ENXIO;
729 	}
730 
731 	pctrl->desc = pm8xxx_pinctrl_desc;
732 	pctrl->desc.npins = pctrl->npins;
733 
734 	pins = devm_kcalloc(&pdev->dev,
735 			    pctrl->desc.npins,
736 			    sizeof(struct pinctrl_pin_desc),
737 			    GFP_KERNEL);
738 	if (!pins)
739 		return -ENOMEM;
740 
741 	pin_data = devm_kcalloc(&pdev->dev,
742 				pctrl->desc.npins,
743 				sizeof(struct pm8xxx_pin_data),
744 				GFP_KERNEL);
745 	if (!pin_data)
746 		return -ENOMEM;
747 
748 	for (i = 0; i < pctrl->desc.npins; i++) {
749 		pin_data[i].reg = SSBI_REG_ADDR_GPIO(i);
750 
751 		ret = pm8xxx_pin_populate(pctrl, &pin_data[i]);
752 		if (ret)
753 			return ret;
754 
755 		pins[i].number = i;
756 		pins[i].name = pm8xxx_groups[i];
757 		pins[i].drv_data = &pin_data[i];
758 	}
759 	pctrl->desc.pins = pins;
760 
761 	pctrl->desc.num_custom_params = ARRAY_SIZE(pm8xxx_gpio_bindings);
762 	pctrl->desc.custom_params = pm8xxx_gpio_bindings;
763 #ifdef CONFIG_DEBUG_FS
764 	pctrl->desc.custom_conf_items = pm8xxx_conf_items;
765 #endif
766 
767 	pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &pctrl->desc, pctrl);
768 	if (IS_ERR(pctrl->pctrl)) {
769 		dev_err(&pdev->dev, "couldn't register pm8xxx gpio driver\n");
770 		return PTR_ERR(pctrl->pctrl);
771 	}
772 
773 	pctrl->chip = pm8xxx_gpio_template;
774 	pctrl->chip.base = -1;
775 	pctrl->chip.parent = &pdev->dev;
776 	pctrl->chip.of_node = pdev->dev.of_node;
777 	pctrl->chip.of_gpio_n_cells = 2;
778 	pctrl->chip.label = dev_name(pctrl->dev);
779 	pctrl->chip.ngpio = pctrl->npins;
780 
781 	parent_node = of_irq_find_parent(pctrl->dev->of_node);
782 	if (!parent_node)
783 		return -ENXIO;
784 
785 	parent_domain = irq_find_host(parent_node);
786 	of_node_put(parent_node);
787 	if (!parent_domain)
788 		return -ENXIO;
789 
790 	girq = &pctrl->chip.irq;
791 	girq->chip = &pm8xxx_irq_chip;
792 	girq->default_type = IRQ_TYPE_NONE;
793 	girq->handler = handle_level_irq;
794 	girq->fwnode = of_node_to_fwnode(pctrl->dev->of_node);
795 	girq->parent_domain = parent_domain;
796 	girq->child_to_parent_hwirq = pm8xxx_child_to_parent_hwirq;
797 	girq->populate_parent_alloc_arg = gpiochip_populate_parent_fwspec_twocell;
798 	girq->child_offset_to_irq = pm8xxx_child_offset_to_irq;
799 	girq->child_irq_domain_ops.translate = pm8xxx_domain_translate;
800 
801 	ret = gpiochip_add_data(&pctrl->chip, pctrl);
802 	if (ret) {
803 		dev_err(&pdev->dev, "failed register gpiochip\n");
804 		return ret;
805 	}
806 
807 	/*
808 	 * For DeviceTree-supported systems, the gpio core checks the
809 	 * pinctrl's device node for the "gpio-ranges" property.
810 	 * If it is present, it takes care of adding the pin ranges
811 	 * for the driver. In this case the driver can skip ahead.
812 	 *
813 	 * In order to remain compatible with older, existing DeviceTree
814 	 * files which don't set the "gpio-ranges" property or systems that
815 	 * utilize ACPI the driver has to call gpiochip_add_pin_range().
816 	 */
817 	if (!of_property_read_bool(pctrl->dev->of_node, "gpio-ranges")) {
818 		ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev),
819 					     0, 0, pctrl->chip.ngpio);
820 		if (ret) {
821 			dev_err(pctrl->dev, "failed to add pin range\n");
822 			goto unregister_gpiochip;
823 		}
824 	}
825 
826 	platform_set_drvdata(pdev, pctrl);
827 
828 	dev_dbg(&pdev->dev, "Qualcomm pm8xxx gpio driver probed\n");
829 
830 	return 0;
831 
832 unregister_gpiochip:
833 	gpiochip_remove(&pctrl->chip);
834 
835 	return ret;
836 }
837 
838 static int pm8xxx_gpio_remove(struct platform_device *pdev)
839 {
840 	struct pm8xxx_gpio *pctrl = platform_get_drvdata(pdev);
841 
842 	gpiochip_remove(&pctrl->chip);
843 
844 	return 0;
845 }
846 
847 static struct platform_driver pm8xxx_gpio_driver = {
848 	.driver = {
849 		.name = "qcom-ssbi-gpio",
850 		.of_match_table = pm8xxx_gpio_of_match,
851 	},
852 	.probe = pm8xxx_gpio_probe,
853 	.remove = pm8xxx_gpio_remove,
854 };
855 
856 module_platform_driver(pm8xxx_gpio_driver);
857 
858 MODULE_AUTHOR("Bjorn Andersson <bjorn.andersson@sonymobile.com>");
859 MODULE_DESCRIPTION("Qualcomm PM8xxx GPIO driver");
860 MODULE_LICENSE("GPL v2");
861