1 /* 2 * Copyright (c) 2012-2014, The Linux Foundation. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 and 6 * only version 2 as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14 #include <linux/gpio/driver.h> 15 #include <linux/module.h> 16 #include <linux/of.h> 17 #include <linux/of_irq.h> 18 #include <linux/pinctrl/pinconf-generic.h> 19 #include <linux/pinctrl/pinconf.h> 20 #include <linux/pinctrl/pinmux.h> 21 #include <linux/platform_device.h> 22 #include <linux/regmap.h> 23 #include <linux/slab.h> 24 #include <linux/types.h> 25 26 #include <dt-bindings/pinctrl/qcom,pmic-mpp.h> 27 28 #include "../core.h" 29 #include "../pinctrl-utils.h" 30 31 #define PMIC_MPP_ADDRESS_RANGE 0x100 32 33 /* 34 * Pull Up Values - it indicates whether a pull-up should be 35 * applied for bidirectional mode only. The hardware ignores the 36 * configuration when operating in other modes. 37 */ 38 #define PMIC_MPP_PULL_UP_0P6KOHM 0 39 #define PMIC_MPP_PULL_UP_10KOHM 1 40 #define PMIC_MPP_PULL_UP_30KOHM 2 41 #define PMIC_MPP_PULL_UP_OPEN 3 42 43 /* type registers base address bases */ 44 #define PMIC_MPP_REG_TYPE 0x4 45 #define PMIC_MPP_REG_SUBTYPE 0x5 46 47 /* mpp peripheral type and subtype values */ 48 #define PMIC_MPP_TYPE 0x11 49 #define PMIC_MPP_SUBTYPE_4CH_NO_ANA_OUT 0x3 50 #define PMIC_MPP_SUBTYPE_ULT_4CH_NO_ANA_OUT 0x4 51 #define PMIC_MPP_SUBTYPE_4CH_NO_SINK 0x5 52 #define PMIC_MPP_SUBTYPE_ULT_4CH_NO_SINK 0x6 53 #define PMIC_MPP_SUBTYPE_4CH_FULL_FUNC 0x7 54 #define PMIC_MPP_SUBTYPE_8CH_FULL_FUNC 0xf 55 56 #define PMIC_MPP_REG_RT_STS 0x10 57 #define PMIC_MPP_REG_RT_STS_VAL_MASK 0x1 58 59 /* control register base address bases */ 60 #define PMIC_MPP_REG_MODE_CTL 0x40 61 #define PMIC_MPP_REG_DIG_VIN_CTL 0x41 62 #define PMIC_MPP_REG_DIG_PULL_CTL 0x42 63 #define PMIC_MPP_REG_DIG_IN_CTL 0x43 64 #define PMIC_MPP_REG_EN_CTL 0x46 65 #define PMIC_MPP_REG_AOUT_CTL 0x48 66 #define PMIC_MPP_REG_AIN_CTL 0x4a 67 #define PMIC_MPP_REG_SINK_CTL 0x4c 68 69 /* PMIC_MPP_REG_MODE_CTL */ 70 #define PMIC_MPP_REG_MODE_VALUE_MASK 0x1 71 #define PMIC_MPP_REG_MODE_FUNCTION_SHIFT 1 72 #define PMIC_MPP_REG_MODE_FUNCTION_MASK 0x7 73 #define PMIC_MPP_REG_MODE_DIR_SHIFT 4 74 #define PMIC_MPP_REG_MODE_DIR_MASK 0x7 75 76 /* PMIC_MPP_REG_DIG_VIN_CTL */ 77 #define PMIC_MPP_REG_VIN_SHIFT 0 78 #define PMIC_MPP_REG_VIN_MASK 0x7 79 80 /* PMIC_MPP_REG_DIG_PULL_CTL */ 81 #define PMIC_MPP_REG_PULL_SHIFT 0 82 #define PMIC_MPP_REG_PULL_MASK 0x7 83 84 /* PMIC_MPP_REG_EN_CTL */ 85 #define PMIC_MPP_REG_MASTER_EN_SHIFT 7 86 87 /* PMIC_MPP_REG_AIN_CTL */ 88 #define PMIC_MPP_REG_AIN_ROUTE_SHIFT 0 89 #define PMIC_MPP_REG_AIN_ROUTE_MASK 0x7 90 91 #define PMIC_MPP_MODE_DIGITAL_INPUT 0 92 #define PMIC_MPP_MODE_DIGITAL_OUTPUT 1 93 #define PMIC_MPP_MODE_DIGITAL_BIDIR 2 94 #define PMIC_MPP_MODE_ANALOG_BIDIR 3 95 #define PMIC_MPP_MODE_ANALOG_INPUT 4 96 #define PMIC_MPP_MODE_ANALOG_OUTPUT 5 97 #define PMIC_MPP_MODE_CURRENT_SINK 6 98 99 #define PMIC_MPP_SELECTOR_NORMAL 0 100 #define PMIC_MPP_SELECTOR_PAIRED 1 101 #define PMIC_MPP_SELECTOR_DTEST_FIRST 4 102 103 #define PMIC_MPP_PHYSICAL_OFFSET 1 104 105 /* Qualcomm specific pin configurations */ 106 #define PMIC_MPP_CONF_AMUX_ROUTE (PIN_CONFIG_END + 1) 107 #define PMIC_MPP_CONF_ANALOG_LEVEL (PIN_CONFIG_END + 2) 108 #define PMIC_MPP_CONF_DTEST_SELECTOR (PIN_CONFIG_END + 3) 109 #define PMIC_MPP_CONF_PAIRED (PIN_CONFIG_END + 4) 110 111 /** 112 * struct pmic_mpp_pad - keep current MPP settings 113 * @base: Address base in SPMI device. 114 * @irq: IRQ number which this MPP generate. 115 * @is_enabled: Set to false when MPP should be put in high Z state. 116 * @out_value: Cached pin output value. 117 * @output_enabled: Set to true if MPP output logic is enabled. 118 * @input_enabled: Set to true if MPP input buffer logic is enabled. 119 * @paired: Pin operates in paired mode 120 * @has_pullup: Pin has support to configure pullup 121 * @num_sources: Number of power-sources supported by this MPP. 122 * @power_source: Current power-source used. 123 * @amux_input: Set the source for analog input. 124 * @aout_level: Analog output level 125 * @pullup: Pullup resistor value. Valid in Bidirectional mode only. 126 * @function: See pmic_mpp_functions[]. 127 * @drive_strength: Amount of current in sink mode 128 * @dtest: DTEST route selector 129 */ 130 struct pmic_mpp_pad { 131 u16 base; 132 int irq; 133 bool is_enabled; 134 bool out_value; 135 bool output_enabled; 136 bool input_enabled; 137 bool paired; 138 bool has_pullup; 139 unsigned int num_sources; 140 unsigned int power_source; 141 unsigned int amux_input; 142 unsigned int aout_level; 143 unsigned int pullup; 144 unsigned int function; 145 unsigned int drive_strength; 146 unsigned int dtest; 147 }; 148 149 struct pmic_mpp_state { 150 struct device *dev; 151 struct regmap *map; 152 struct pinctrl_dev *ctrl; 153 struct gpio_chip chip; 154 }; 155 156 static const struct pinconf_generic_params pmic_mpp_bindings[] = { 157 {"qcom,amux-route", PMIC_MPP_CONF_AMUX_ROUTE, 0}, 158 {"qcom,analog-level", PMIC_MPP_CONF_ANALOG_LEVEL, 0}, 159 {"qcom,dtest", PMIC_MPP_CONF_DTEST_SELECTOR, 0}, 160 {"qcom,paired", PMIC_MPP_CONF_PAIRED, 0}, 161 }; 162 163 #ifdef CONFIG_DEBUG_FS 164 static const struct pin_config_item pmic_conf_items[] = { 165 PCONFDUMP(PMIC_MPP_CONF_AMUX_ROUTE, "analog mux", NULL, true), 166 PCONFDUMP(PMIC_MPP_CONF_ANALOG_LEVEL, "analog level", NULL, true), 167 PCONFDUMP(PMIC_MPP_CONF_DTEST_SELECTOR, "dtest", NULL, true), 168 PCONFDUMP(PMIC_MPP_CONF_PAIRED, "paired", NULL, false), 169 }; 170 #endif 171 172 static const char *const pmic_mpp_groups[] = { 173 "mpp1", "mpp2", "mpp3", "mpp4", "mpp5", "mpp6", "mpp7", "mpp8", 174 }; 175 176 #define PMIC_MPP_DIGITAL 0 177 #define PMIC_MPP_ANALOG 1 178 #define PMIC_MPP_SINK 2 179 180 static const char *const pmic_mpp_functions[] = { 181 "digital", "analog", "sink" 182 }; 183 184 static int pmic_mpp_read(struct pmic_mpp_state *state, 185 struct pmic_mpp_pad *pad, unsigned int addr) 186 { 187 unsigned int val; 188 int ret; 189 190 ret = regmap_read(state->map, pad->base + addr, &val); 191 if (ret < 0) 192 dev_err(state->dev, "read 0x%x failed\n", addr); 193 else 194 ret = val; 195 196 return ret; 197 } 198 199 static int pmic_mpp_write(struct pmic_mpp_state *state, 200 struct pmic_mpp_pad *pad, unsigned int addr, 201 unsigned int val) 202 { 203 int ret; 204 205 ret = regmap_write(state->map, pad->base + addr, val); 206 if (ret < 0) 207 dev_err(state->dev, "write 0x%x failed\n", addr); 208 209 return ret; 210 } 211 212 static int pmic_mpp_get_groups_count(struct pinctrl_dev *pctldev) 213 { 214 /* Every PIN is a group */ 215 return pctldev->desc->npins; 216 } 217 218 static const char *pmic_mpp_get_group_name(struct pinctrl_dev *pctldev, 219 unsigned pin) 220 { 221 return pctldev->desc->pins[pin].name; 222 } 223 224 static int pmic_mpp_get_group_pins(struct pinctrl_dev *pctldev, 225 unsigned pin, 226 const unsigned **pins, unsigned *num_pins) 227 { 228 *pins = &pctldev->desc->pins[pin].number; 229 *num_pins = 1; 230 return 0; 231 } 232 233 static const struct pinctrl_ops pmic_mpp_pinctrl_ops = { 234 .get_groups_count = pmic_mpp_get_groups_count, 235 .get_group_name = pmic_mpp_get_group_name, 236 .get_group_pins = pmic_mpp_get_group_pins, 237 .dt_node_to_map = pinconf_generic_dt_node_to_map_group, 238 .dt_free_map = pinctrl_utils_free_map, 239 }; 240 241 static int pmic_mpp_get_functions_count(struct pinctrl_dev *pctldev) 242 { 243 return ARRAY_SIZE(pmic_mpp_functions); 244 } 245 246 static const char *pmic_mpp_get_function_name(struct pinctrl_dev *pctldev, 247 unsigned function) 248 { 249 return pmic_mpp_functions[function]; 250 } 251 252 static int pmic_mpp_get_function_groups(struct pinctrl_dev *pctldev, 253 unsigned function, 254 const char *const **groups, 255 unsigned *const num_qgroups) 256 { 257 *groups = pmic_mpp_groups; 258 *num_qgroups = pctldev->desc->npins; 259 return 0; 260 } 261 262 static int pmic_mpp_write_mode_ctl(struct pmic_mpp_state *state, 263 struct pmic_mpp_pad *pad) 264 { 265 unsigned int mode; 266 unsigned int sel; 267 unsigned int val; 268 unsigned int en; 269 270 switch (pad->function) { 271 case PMIC_MPP_ANALOG: 272 if (pad->input_enabled && pad->output_enabled) 273 mode = PMIC_MPP_MODE_ANALOG_BIDIR; 274 else if (pad->input_enabled) 275 mode = PMIC_MPP_MODE_ANALOG_INPUT; 276 else 277 mode = PMIC_MPP_MODE_ANALOG_OUTPUT; 278 break; 279 case PMIC_MPP_DIGITAL: 280 if (pad->input_enabled && pad->output_enabled) 281 mode = PMIC_MPP_MODE_DIGITAL_BIDIR; 282 else if (pad->input_enabled) 283 mode = PMIC_MPP_MODE_DIGITAL_INPUT; 284 else 285 mode = PMIC_MPP_MODE_DIGITAL_OUTPUT; 286 break; 287 case PMIC_MPP_SINK: 288 default: 289 mode = PMIC_MPP_MODE_CURRENT_SINK; 290 break; 291 } 292 293 if (pad->dtest) 294 sel = PMIC_MPP_SELECTOR_DTEST_FIRST + pad->dtest - 1; 295 else if (pad->paired) 296 sel = PMIC_MPP_SELECTOR_PAIRED; 297 else 298 sel = PMIC_MPP_SELECTOR_NORMAL; 299 300 en = !!pad->out_value; 301 302 val = mode << PMIC_MPP_REG_MODE_DIR_SHIFT | 303 sel << PMIC_MPP_REG_MODE_FUNCTION_SHIFT | 304 en; 305 306 return pmic_mpp_write(state, pad, PMIC_MPP_REG_MODE_CTL, val); 307 } 308 309 static int pmic_mpp_set_mux(struct pinctrl_dev *pctldev, unsigned function, 310 unsigned pin) 311 { 312 struct pmic_mpp_state *state = pinctrl_dev_get_drvdata(pctldev); 313 struct pmic_mpp_pad *pad; 314 unsigned int val; 315 int ret; 316 317 pad = pctldev->desc->pins[pin].drv_data; 318 319 pad->function = function; 320 321 ret = pmic_mpp_write_mode_ctl(state, pad); 322 if (ret < 0) 323 return ret; 324 325 val = pad->is_enabled << PMIC_MPP_REG_MASTER_EN_SHIFT; 326 327 return pmic_mpp_write(state, pad, PMIC_MPP_REG_EN_CTL, val); 328 } 329 330 static const struct pinmux_ops pmic_mpp_pinmux_ops = { 331 .get_functions_count = pmic_mpp_get_functions_count, 332 .get_function_name = pmic_mpp_get_function_name, 333 .get_function_groups = pmic_mpp_get_function_groups, 334 .set_mux = pmic_mpp_set_mux, 335 }; 336 337 static int pmic_mpp_config_get(struct pinctrl_dev *pctldev, 338 unsigned int pin, unsigned long *config) 339 { 340 unsigned param = pinconf_to_config_param(*config); 341 struct pmic_mpp_pad *pad; 342 unsigned arg = 0; 343 344 pad = pctldev->desc->pins[pin].drv_data; 345 346 switch (param) { 347 case PIN_CONFIG_BIAS_DISABLE: 348 if (pad->pullup != PMIC_MPP_PULL_UP_OPEN) 349 return -EINVAL; 350 arg = 1; 351 break; 352 case PIN_CONFIG_BIAS_PULL_UP: 353 switch (pad->pullup) { 354 case PMIC_MPP_PULL_UP_0P6KOHM: 355 arg = 600; 356 break; 357 case PMIC_MPP_PULL_UP_10KOHM: 358 arg = 10000; 359 break; 360 case PMIC_MPP_PULL_UP_30KOHM: 361 arg = 30000; 362 break; 363 default: 364 return -EINVAL; 365 } 366 break; 367 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: 368 if (pad->is_enabled) 369 return -EINVAL; 370 arg = 1; 371 break; 372 case PIN_CONFIG_POWER_SOURCE: 373 arg = pad->power_source; 374 break; 375 case PIN_CONFIG_INPUT_ENABLE: 376 if (!pad->input_enabled) 377 return -EINVAL; 378 arg = 1; 379 break; 380 case PIN_CONFIG_OUTPUT: 381 arg = pad->out_value; 382 break; 383 case PMIC_MPP_CONF_DTEST_SELECTOR: 384 arg = pad->dtest; 385 break; 386 case PMIC_MPP_CONF_AMUX_ROUTE: 387 arg = pad->amux_input; 388 break; 389 case PMIC_MPP_CONF_PAIRED: 390 if (!pad->paired) 391 return -EINVAL; 392 arg = 1; 393 break; 394 case PIN_CONFIG_DRIVE_STRENGTH: 395 arg = pad->drive_strength; 396 break; 397 case PMIC_MPP_CONF_ANALOG_LEVEL: 398 arg = pad->aout_level; 399 break; 400 default: 401 return -EINVAL; 402 } 403 404 /* Convert register value to pinconf value */ 405 *config = pinconf_to_config_packed(param, arg); 406 return 0; 407 } 408 409 static int pmic_mpp_config_set(struct pinctrl_dev *pctldev, unsigned int pin, 410 unsigned long *configs, unsigned nconfs) 411 { 412 struct pmic_mpp_state *state = pinctrl_dev_get_drvdata(pctldev); 413 struct pmic_mpp_pad *pad; 414 unsigned param, arg; 415 unsigned int val; 416 int i, ret; 417 418 pad = pctldev->desc->pins[pin].drv_data; 419 420 /* Make it possible to enable the pin, by not setting high impedance */ 421 pad->is_enabled = true; 422 423 for (i = 0; i < nconfs; i++) { 424 param = pinconf_to_config_param(configs[i]); 425 arg = pinconf_to_config_argument(configs[i]); 426 427 switch (param) { 428 case PIN_CONFIG_BIAS_DISABLE: 429 pad->pullup = PMIC_MPP_PULL_UP_OPEN; 430 break; 431 case PIN_CONFIG_BIAS_PULL_UP: 432 switch (arg) { 433 case 600: 434 pad->pullup = PMIC_MPP_PULL_UP_0P6KOHM; 435 break; 436 case 10000: 437 pad->pullup = PMIC_MPP_PULL_UP_10KOHM; 438 break; 439 case 30000: 440 pad->pullup = PMIC_MPP_PULL_UP_30KOHM; 441 break; 442 default: 443 return -EINVAL; 444 } 445 break; 446 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: 447 pad->is_enabled = false; 448 break; 449 case PIN_CONFIG_POWER_SOURCE: 450 if (arg >= pad->num_sources) 451 return -EINVAL; 452 pad->power_source = arg; 453 break; 454 case PIN_CONFIG_INPUT_ENABLE: 455 pad->input_enabled = arg ? true : false; 456 break; 457 case PIN_CONFIG_OUTPUT: 458 pad->output_enabled = true; 459 pad->out_value = arg; 460 break; 461 case PMIC_MPP_CONF_DTEST_SELECTOR: 462 pad->dtest = arg; 463 break; 464 case PIN_CONFIG_DRIVE_STRENGTH: 465 pad->drive_strength = arg; 466 break; 467 case PMIC_MPP_CONF_AMUX_ROUTE: 468 if (arg >= PMIC_MPP_AMUX_ROUTE_ABUS4) 469 return -EINVAL; 470 pad->amux_input = arg; 471 break; 472 case PMIC_MPP_CONF_ANALOG_LEVEL: 473 pad->aout_level = arg; 474 break; 475 case PMIC_MPP_CONF_PAIRED: 476 pad->paired = !!arg; 477 break; 478 default: 479 return -EINVAL; 480 } 481 } 482 483 val = pad->power_source << PMIC_MPP_REG_VIN_SHIFT; 484 485 ret = pmic_mpp_write(state, pad, PMIC_MPP_REG_DIG_VIN_CTL, val); 486 if (ret < 0) 487 return ret; 488 489 if (pad->has_pullup) { 490 val = pad->pullup << PMIC_MPP_REG_PULL_SHIFT; 491 492 ret = pmic_mpp_write(state, pad, PMIC_MPP_REG_DIG_PULL_CTL, 493 val); 494 if (ret < 0) 495 return ret; 496 } 497 498 val = pad->amux_input & PMIC_MPP_REG_AIN_ROUTE_MASK; 499 500 ret = pmic_mpp_write(state, pad, PMIC_MPP_REG_AIN_CTL, val); 501 if (ret < 0) 502 return ret; 503 504 ret = pmic_mpp_write(state, pad, PMIC_MPP_REG_AOUT_CTL, pad->aout_level); 505 if (ret < 0) 506 return ret; 507 508 ret = pmic_mpp_write_mode_ctl(state, pad); 509 if (ret < 0) 510 return ret; 511 512 ret = pmic_mpp_write(state, pad, PMIC_MPP_REG_SINK_CTL, pad->drive_strength); 513 if (ret < 0) 514 return ret; 515 516 val = pad->is_enabled << PMIC_MPP_REG_MASTER_EN_SHIFT; 517 518 return pmic_mpp_write(state, pad, PMIC_MPP_REG_EN_CTL, val); 519 } 520 521 static void pmic_mpp_config_dbg_show(struct pinctrl_dev *pctldev, 522 struct seq_file *s, unsigned pin) 523 { 524 struct pmic_mpp_state *state = pinctrl_dev_get_drvdata(pctldev); 525 struct pmic_mpp_pad *pad; 526 int ret; 527 528 static const char *const biases[] = { 529 "0.6kOhm", "10kOhm", "30kOhm", "Disabled" 530 }; 531 532 pad = pctldev->desc->pins[pin].drv_data; 533 534 seq_printf(s, " mpp%-2d:", pin + PMIC_MPP_PHYSICAL_OFFSET); 535 536 if (!pad->is_enabled) { 537 seq_puts(s, " ---"); 538 } else { 539 540 if (pad->input_enabled) { 541 ret = pmic_mpp_read(state, pad, PMIC_MPP_REG_RT_STS); 542 if (ret < 0) 543 return; 544 545 ret &= PMIC_MPP_REG_RT_STS_VAL_MASK; 546 pad->out_value = ret; 547 } 548 549 seq_printf(s, " %-4s", pad->output_enabled ? "out" : "in"); 550 seq_printf(s, " %-7s", pmic_mpp_functions[pad->function]); 551 seq_printf(s, " vin-%d", pad->power_source); 552 seq_printf(s, " %d", pad->aout_level); 553 if (pad->has_pullup) 554 seq_printf(s, " %-8s", biases[pad->pullup]); 555 seq_printf(s, " %-4s", pad->out_value ? "high" : "low"); 556 if (pad->dtest) 557 seq_printf(s, " dtest%d", pad->dtest); 558 if (pad->paired) 559 seq_puts(s, " paired"); 560 } 561 } 562 563 static const struct pinconf_ops pmic_mpp_pinconf_ops = { 564 .is_generic = true, 565 .pin_config_group_get = pmic_mpp_config_get, 566 .pin_config_group_set = pmic_mpp_config_set, 567 .pin_config_group_dbg_show = pmic_mpp_config_dbg_show, 568 }; 569 570 static int pmic_mpp_direction_input(struct gpio_chip *chip, unsigned pin) 571 { 572 struct pmic_mpp_state *state = gpiochip_get_data(chip); 573 unsigned long config; 574 575 config = pinconf_to_config_packed(PIN_CONFIG_INPUT_ENABLE, 1); 576 577 return pmic_mpp_config_set(state->ctrl, pin, &config, 1); 578 } 579 580 static int pmic_mpp_direction_output(struct gpio_chip *chip, 581 unsigned pin, int val) 582 { 583 struct pmic_mpp_state *state = gpiochip_get_data(chip); 584 unsigned long config; 585 586 config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, val); 587 588 return pmic_mpp_config_set(state->ctrl, pin, &config, 1); 589 } 590 591 static int pmic_mpp_get(struct gpio_chip *chip, unsigned pin) 592 { 593 struct pmic_mpp_state *state = gpiochip_get_data(chip); 594 struct pmic_mpp_pad *pad; 595 int ret; 596 597 pad = state->ctrl->desc->pins[pin].drv_data; 598 599 if (pad->input_enabled) { 600 ret = pmic_mpp_read(state, pad, PMIC_MPP_REG_RT_STS); 601 if (ret < 0) 602 return ret; 603 604 pad->out_value = ret & PMIC_MPP_REG_RT_STS_VAL_MASK; 605 } 606 607 return !!pad->out_value; 608 } 609 610 static void pmic_mpp_set(struct gpio_chip *chip, unsigned pin, int value) 611 { 612 struct pmic_mpp_state *state = gpiochip_get_data(chip); 613 unsigned long config; 614 615 config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, value); 616 617 pmic_mpp_config_set(state->ctrl, pin, &config, 1); 618 } 619 620 static int pmic_mpp_of_xlate(struct gpio_chip *chip, 621 const struct of_phandle_args *gpio_desc, 622 u32 *flags) 623 { 624 if (chip->of_gpio_n_cells < 2) 625 return -EINVAL; 626 627 if (flags) 628 *flags = gpio_desc->args[1]; 629 630 return gpio_desc->args[0] - PMIC_MPP_PHYSICAL_OFFSET; 631 } 632 633 static int pmic_mpp_to_irq(struct gpio_chip *chip, unsigned pin) 634 { 635 struct pmic_mpp_state *state = gpiochip_get_data(chip); 636 struct pmic_mpp_pad *pad; 637 638 pad = state->ctrl->desc->pins[pin].drv_data; 639 640 return pad->irq; 641 } 642 643 static void pmic_mpp_dbg_show(struct seq_file *s, struct gpio_chip *chip) 644 { 645 struct pmic_mpp_state *state = gpiochip_get_data(chip); 646 unsigned i; 647 648 for (i = 0; i < chip->ngpio; i++) { 649 pmic_mpp_config_dbg_show(state->ctrl, s, i); 650 seq_puts(s, "\n"); 651 } 652 } 653 654 static const struct gpio_chip pmic_mpp_gpio_template = { 655 .direction_input = pmic_mpp_direction_input, 656 .direction_output = pmic_mpp_direction_output, 657 .get = pmic_mpp_get, 658 .set = pmic_mpp_set, 659 .request = gpiochip_generic_request, 660 .free = gpiochip_generic_free, 661 .of_xlate = pmic_mpp_of_xlate, 662 .to_irq = pmic_mpp_to_irq, 663 .dbg_show = pmic_mpp_dbg_show, 664 }; 665 666 static int pmic_mpp_populate(struct pmic_mpp_state *state, 667 struct pmic_mpp_pad *pad) 668 { 669 int type, subtype, val, dir; 670 unsigned int sel; 671 672 type = pmic_mpp_read(state, pad, PMIC_MPP_REG_TYPE); 673 if (type < 0) 674 return type; 675 676 if (type != PMIC_MPP_TYPE) { 677 dev_err(state->dev, "incorrect block type 0x%x at 0x%x\n", 678 type, pad->base); 679 return -ENODEV; 680 } 681 682 subtype = pmic_mpp_read(state, pad, PMIC_MPP_REG_SUBTYPE); 683 if (subtype < 0) 684 return subtype; 685 686 switch (subtype) { 687 case PMIC_MPP_SUBTYPE_4CH_NO_ANA_OUT: 688 case PMIC_MPP_SUBTYPE_ULT_4CH_NO_ANA_OUT: 689 case PMIC_MPP_SUBTYPE_4CH_NO_SINK: 690 case PMIC_MPP_SUBTYPE_ULT_4CH_NO_SINK: 691 case PMIC_MPP_SUBTYPE_4CH_FULL_FUNC: 692 pad->num_sources = 4; 693 break; 694 case PMIC_MPP_SUBTYPE_8CH_FULL_FUNC: 695 pad->num_sources = 8; 696 break; 697 default: 698 dev_err(state->dev, "unknown MPP type 0x%x at 0x%x\n", 699 subtype, pad->base); 700 return -ENODEV; 701 } 702 703 val = pmic_mpp_read(state, pad, PMIC_MPP_REG_MODE_CTL); 704 if (val < 0) 705 return val; 706 707 pad->out_value = val & PMIC_MPP_REG_MODE_VALUE_MASK; 708 709 dir = val >> PMIC_MPP_REG_MODE_DIR_SHIFT; 710 dir &= PMIC_MPP_REG_MODE_DIR_MASK; 711 712 switch (dir) { 713 case PMIC_MPP_MODE_DIGITAL_INPUT: 714 pad->input_enabled = true; 715 pad->output_enabled = false; 716 pad->function = PMIC_MPP_DIGITAL; 717 break; 718 case PMIC_MPP_MODE_DIGITAL_OUTPUT: 719 pad->input_enabled = false; 720 pad->output_enabled = true; 721 pad->function = PMIC_MPP_DIGITAL; 722 break; 723 case PMIC_MPP_MODE_DIGITAL_BIDIR: 724 pad->input_enabled = true; 725 pad->output_enabled = true; 726 pad->function = PMIC_MPP_DIGITAL; 727 break; 728 case PMIC_MPP_MODE_ANALOG_BIDIR: 729 pad->input_enabled = true; 730 pad->output_enabled = true; 731 pad->function = PMIC_MPP_ANALOG; 732 break; 733 case PMIC_MPP_MODE_ANALOG_INPUT: 734 pad->input_enabled = true; 735 pad->output_enabled = false; 736 pad->function = PMIC_MPP_ANALOG; 737 break; 738 case PMIC_MPP_MODE_ANALOG_OUTPUT: 739 pad->input_enabled = false; 740 pad->output_enabled = true; 741 pad->function = PMIC_MPP_ANALOG; 742 break; 743 case PMIC_MPP_MODE_CURRENT_SINK: 744 pad->input_enabled = false; 745 pad->output_enabled = true; 746 pad->function = PMIC_MPP_SINK; 747 break; 748 default: 749 dev_err(state->dev, "unknown MPP direction\n"); 750 return -ENODEV; 751 } 752 753 sel = val >> PMIC_MPP_REG_MODE_FUNCTION_SHIFT; 754 sel &= PMIC_MPP_REG_MODE_FUNCTION_MASK; 755 756 if (sel >= PMIC_MPP_SELECTOR_DTEST_FIRST) 757 pad->dtest = sel + 1; 758 else if (sel == PMIC_MPP_SELECTOR_PAIRED) 759 pad->paired = true; 760 761 val = pmic_mpp_read(state, pad, PMIC_MPP_REG_DIG_VIN_CTL); 762 if (val < 0) 763 return val; 764 765 pad->power_source = val >> PMIC_MPP_REG_VIN_SHIFT; 766 pad->power_source &= PMIC_MPP_REG_VIN_MASK; 767 768 if (subtype != PMIC_MPP_SUBTYPE_ULT_4CH_NO_ANA_OUT && 769 subtype != PMIC_MPP_SUBTYPE_ULT_4CH_NO_SINK) { 770 val = pmic_mpp_read(state, pad, PMIC_MPP_REG_DIG_PULL_CTL); 771 if (val < 0) 772 return val; 773 774 pad->pullup = val >> PMIC_MPP_REG_PULL_SHIFT; 775 pad->pullup &= PMIC_MPP_REG_PULL_MASK; 776 pad->has_pullup = true; 777 } 778 779 val = pmic_mpp_read(state, pad, PMIC_MPP_REG_AIN_CTL); 780 if (val < 0) 781 return val; 782 783 pad->amux_input = val >> PMIC_MPP_REG_AIN_ROUTE_SHIFT; 784 pad->amux_input &= PMIC_MPP_REG_AIN_ROUTE_MASK; 785 786 val = pmic_mpp_read(state, pad, PMIC_MPP_REG_SINK_CTL); 787 if (val < 0) 788 return val; 789 790 pad->drive_strength = val; 791 792 val = pmic_mpp_read(state, pad, PMIC_MPP_REG_AOUT_CTL); 793 if (val < 0) 794 return val; 795 796 pad->aout_level = val; 797 798 val = pmic_mpp_read(state, pad, PMIC_MPP_REG_EN_CTL); 799 if (val < 0) 800 return val; 801 802 pad->is_enabled = !!val; 803 804 return 0; 805 } 806 807 static int pmic_mpp_probe(struct platform_device *pdev) 808 { 809 struct device *dev = &pdev->dev; 810 struct pinctrl_pin_desc *pindesc; 811 struct pinctrl_desc *pctrldesc; 812 struct pmic_mpp_pad *pad, *pads; 813 struct pmic_mpp_state *state; 814 int ret, npins, i; 815 u32 reg; 816 817 ret = of_property_read_u32(dev->of_node, "reg", ®); 818 if (ret < 0) { 819 dev_err(dev, "missing base address"); 820 return ret; 821 } 822 823 npins = platform_irq_count(pdev); 824 if (!npins) 825 return -EINVAL; 826 if (npins < 0) 827 return npins; 828 829 BUG_ON(npins > ARRAY_SIZE(pmic_mpp_groups)); 830 831 state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL); 832 if (!state) 833 return -ENOMEM; 834 835 platform_set_drvdata(pdev, state); 836 837 state->dev = &pdev->dev; 838 state->map = dev_get_regmap(dev->parent, NULL); 839 840 pindesc = devm_kcalloc(dev, npins, sizeof(*pindesc), GFP_KERNEL); 841 if (!pindesc) 842 return -ENOMEM; 843 844 pads = devm_kcalloc(dev, npins, sizeof(*pads), GFP_KERNEL); 845 if (!pads) 846 return -ENOMEM; 847 848 pctrldesc = devm_kzalloc(dev, sizeof(*pctrldesc), GFP_KERNEL); 849 if (!pctrldesc) 850 return -ENOMEM; 851 852 pctrldesc->pctlops = &pmic_mpp_pinctrl_ops; 853 pctrldesc->pmxops = &pmic_mpp_pinmux_ops; 854 pctrldesc->confops = &pmic_mpp_pinconf_ops; 855 pctrldesc->owner = THIS_MODULE; 856 pctrldesc->name = dev_name(dev); 857 pctrldesc->pins = pindesc; 858 pctrldesc->npins = npins; 859 860 pctrldesc->num_custom_params = ARRAY_SIZE(pmic_mpp_bindings); 861 pctrldesc->custom_params = pmic_mpp_bindings; 862 #ifdef CONFIG_DEBUG_FS 863 pctrldesc->custom_conf_items = pmic_conf_items; 864 #endif 865 866 for (i = 0; i < npins; i++, pindesc++) { 867 pad = &pads[i]; 868 pindesc->drv_data = pad; 869 pindesc->number = i; 870 pindesc->name = pmic_mpp_groups[i]; 871 872 pad->irq = platform_get_irq(pdev, i); 873 if (pad->irq < 0) 874 return pad->irq; 875 876 pad->base = reg + i * PMIC_MPP_ADDRESS_RANGE; 877 878 ret = pmic_mpp_populate(state, pad); 879 if (ret < 0) 880 return ret; 881 } 882 883 state->chip = pmic_mpp_gpio_template; 884 state->chip.parent = dev; 885 state->chip.base = -1; 886 state->chip.ngpio = npins; 887 state->chip.label = dev_name(dev); 888 state->chip.of_gpio_n_cells = 2; 889 state->chip.can_sleep = false; 890 891 state->ctrl = devm_pinctrl_register(dev, pctrldesc, state); 892 if (IS_ERR(state->ctrl)) 893 return PTR_ERR(state->ctrl); 894 895 ret = gpiochip_add_data(&state->chip, state); 896 if (ret) { 897 dev_err(state->dev, "can't add gpio chip\n"); 898 return ret; 899 } 900 901 ret = gpiochip_add_pin_range(&state->chip, dev_name(dev), 0, 0, npins); 902 if (ret) { 903 dev_err(dev, "failed to add pin range\n"); 904 goto err_range; 905 } 906 907 return 0; 908 909 err_range: 910 gpiochip_remove(&state->chip); 911 return ret; 912 } 913 914 static int pmic_mpp_remove(struct platform_device *pdev) 915 { 916 struct pmic_mpp_state *state = platform_get_drvdata(pdev); 917 918 gpiochip_remove(&state->chip); 919 return 0; 920 } 921 922 static const struct of_device_id pmic_mpp_of_match[] = { 923 { .compatible = "qcom,pm8841-mpp" }, /* 4 MPP's */ 924 { .compatible = "qcom,pm8916-mpp" }, /* 4 MPP's */ 925 { .compatible = "qcom,pm8941-mpp" }, /* 8 MPP's */ 926 { .compatible = "qcom,pm8994-mpp" }, /* 8 MPP's */ 927 { .compatible = "qcom,pma8084-mpp" }, /* 8 MPP's */ 928 { .compatible = "qcom,spmi-mpp" }, /* Generic */ 929 { }, 930 }; 931 932 MODULE_DEVICE_TABLE(of, pmic_mpp_of_match); 933 934 static struct platform_driver pmic_mpp_driver = { 935 .driver = { 936 .name = "qcom-spmi-mpp", 937 .of_match_table = pmic_mpp_of_match, 938 }, 939 .probe = pmic_mpp_probe, 940 .remove = pmic_mpp_remove, 941 }; 942 943 module_platform_driver(pmic_mpp_driver); 944 945 MODULE_AUTHOR("Ivan T. Ivanov <iivanov@mm-sol.com>"); 946 MODULE_DESCRIPTION("Qualcomm SPMI PMIC MPP pin control driver"); 947 MODULE_ALIAS("platform:qcom-spmi-mpp"); 948 MODULE_LICENSE("GPL v2"); 949