1 /* 2 * Copyright (c) 2012-2014, The Linux Foundation. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 and 6 * only version 2 as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14 #include <linux/gpio.h> 15 #include <linux/module.h> 16 #include <linux/of.h> 17 #include <linux/of_irq.h> 18 #include <linux/pinctrl/pinconf-generic.h> 19 #include <linux/pinctrl/pinconf.h> 20 #include <linux/pinctrl/pinmux.h> 21 #include <linux/platform_device.h> 22 #include <linux/regmap.h> 23 #include <linux/slab.h> 24 #include <linux/types.h> 25 26 #include <dt-bindings/pinctrl/qcom,pmic-mpp.h> 27 28 #include "../core.h" 29 #include "../pinctrl-utils.h" 30 31 #define PMIC_MPP_ADDRESS_RANGE 0x100 32 33 /* 34 * Pull Up Values - it indicates whether a pull-up should be 35 * applied for bidirectional mode only. The hardware ignores the 36 * configuration when operating in other modes. 37 */ 38 #define PMIC_MPP_PULL_UP_0P6KOHM 0 39 #define PMIC_MPP_PULL_UP_10KOHM 1 40 #define PMIC_MPP_PULL_UP_30KOHM 2 41 #define PMIC_MPP_PULL_UP_OPEN 3 42 43 /* type registers base address bases */ 44 #define PMIC_MPP_REG_TYPE 0x4 45 #define PMIC_MPP_REG_SUBTYPE 0x5 46 47 /* mpp peripheral type and subtype values */ 48 #define PMIC_MPP_TYPE 0x11 49 #define PMIC_MPP_SUBTYPE_4CH_NO_ANA_OUT 0x3 50 #define PMIC_MPP_SUBTYPE_ULT_4CH_NO_ANA_OUT 0x4 51 #define PMIC_MPP_SUBTYPE_4CH_NO_SINK 0x5 52 #define PMIC_MPP_SUBTYPE_ULT_4CH_NO_SINK 0x6 53 #define PMIC_MPP_SUBTYPE_4CH_FULL_FUNC 0x7 54 #define PMIC_MPP_SUBTYPE_8CH_FULL_FUNC 0xf 55 56 #define PMIC_MPP_REG_RT_STS 0x10 57 #define PMIC_MPP_REG_RT_STS_VAL_MASK 0x1 58 59 /* control register base address bases */ 60 #define PMIC_MPP_REG_MODE_CTL 0x40 61 #define PMIC_MPP_REG_DIG_VIN_CTL 0x41 62 #define PMIC_MPP_REG_DIG_PULL_CTL 0x42 63 #define PMIC_MPP_REG_DIG_IN_CTL 0x43 64 #define PMIC_MPP_REG_EN_CTL 0x46 65 #define PMIC_MPP_REG_AOUT_CTL 0x48 66 #define PMIC_MPP_REG_AIN_CTL 0x4a 67 #define PMIC_MPP_REG_SINK_CTL 0x4c 68 69 /* PMIC_MPP_REG_MODE_CTL */ 70 #define PMIC_MPP_REG_MODE_VALUE_MASK 0x1 71 #define PMIC_MPP_REG_MODE_FUNCTION_SHIFT 1 72 #define PMIC_MPP_REG_MODE_FUNCTION_MASK 0x7 73 #define PMIC_MPP_REG_MODE_DIR_SHIFT 4 74 #define PMIC_MPP_REG_MODE_DIR_MASK 0x7 75 76 /* PMIC_MPP_REG_DIG_VIN_CTL */ 77 #define PMIC_MPP_REG_VIN_SHIFT 0 78 #define PMIC_MPP_REG_VIN_MASK 0x7 79 80 /* PMIC_MPP_REG_DIG_PULL_CTL */ 81 #define PMIC_MPP_REG_PULL_SHIFT 0 82 #define PMIC_MPP_REG_PULL_MASK 0x7 83 84 /* PMIC_MPP_REG_EN_CTL */ 85 #define PMIC_MPP_REG_MASTER_EN_SHIFT 7 86 87 /* PMIC_MPP_REG_AIN_CTL */ 88 #define PMIC_MPP_REG_AIN_ROUTE_SHIFT 0 89 #define PMIC_MPP_REG_AIN_ROUTE_MASK 0x7 90 91 #define PMIC_MPP_MODE_DIGITAL_INPUT 0 92 #define PMIC_MPP_MODE_DIGITAL_OUTPUT 1 93 #define PMIC_MPP_MODE_DIGITAL_BIDIR 2 94 #define PMIC_MPP_MODE_ANALOG_BIDIR 3 95 #define PMIC_MPP_MODE_ANALOG_INPUT 4 96 #define PMIC_MPP_MODE_ANALOG_OUTPUT 5 97 #define PMIC_MPP_MODE_CURRENT_SINK 6 98 99 #define PMIC_MPP_SELECTOR_NORMAL 0 100 #define PMIC_MPP_SELECTOR_PAIRED 1 101 #define PMIC_MPP_SELECTOR_DTEST_FIRST 4 102 103 #define PMIC_MPP_PHYSICAL_OFFSET 1 104 105 /* Qualcomm specific pin configurations */ 106 #define PMIC_MPP_CONF_AMUX_ROUTE (PIN_CONFIG_END + 1) 107 #define PMIC_MPP_CONF_ANALOG_LEVEL (PIN_CONFIG_END + 2) 108 #define PMIC_MPP_CONF_DTEST_SELECTOR (PIN_CONFIG_END + 3) 109 #define PMIC_MPP_CONF_PAIRED (PIN_CONFIG_END + 4) 110 111 /** 112 * struct pmic_mpp_pad - keep current MPP settings 113 * @base: Address base in SPMI device. 114 * @irq: IRQ number which this MPP generate. 115 * @is_enabled: Set to false when MPP should be put in high Z state. 116 * @out_value: Cached pin output value. 117 * @output_enabled: Set to true if MPP output logic is enabled. 118 * @input_enabled: Set to true if MPP input buffer logic is enabled. 119 * @paired: Pin operates in paired mode 120 * @num_sources: Number of power-sources supported by this MPP. 121 * @power_source: Current power-source used. 122 * @amux_input: Set the source for analog input. 123 * @aout_level: Analog output level 124 * @pullup: Pullup resistor value. Valid in Bidirectional mode only. 125 * @function: See pmic_mpp_functions[]. 126 * @drive_strength: Amount of current in sink mode 127 * @dtest: DTEST route selector 128 */ 129 struct pmic_mpp_pad { 130 u16 base; 131 int irq; 132 bool is_enabled; 133 bool out_value; 134 bool output_enabled; 135 bool input_enabled; 136 bool paired; 137 unsigned int num_sources; 138 unsigned int power_source; 139 unsigned int amux_input; 140 unsigned int aout_level; 141 unsigned int pullup; 142 unsigned int function; 143 unsigned int drive_strength; 144 unsigned int dtest; 145 }; 146 147 struct pmic_mpp_state { 148 struct device *dev; 149 struct regmap *map; 150 struct pinctrl_dev *ctrl; 151 struct gpio_chip chip; 152 }; 153 154 static const struct pinconf_generic_params pmic_mpp_bindings[] = { 155 {"qcom,amux-route", PMIC_MPP_CONF_AMUX_ROUTE, 0}, 156 {"qcom,analog-level", PMIC_MPP_CONF_ANALOG_LEVEL, 0}, 157 {"qcom,dtest", PMIC_MPP_CONF_DTEST_SELECTOR, 0}, 158 {"qcom,paired", PMIC_MPP_CONF_PAIRED, 0}, 159 }; 160 161 #ifdef CONFIG_DEBUG_FS 162 static const struct pin_config_item pmic_conf_items[] = { 163 PCONFDUMP(PMIC_MPP_CONF_AMUX_ROUTE, "analog mux", NULL, true), 164 PCONFDUMP(PMIC_MPP_CONF_ANALOG_LEVEL, "analog level", NULL, true), 165 PCONFDUMP(PMIC_MPP_CONF_DTEST_SELECTOR, "dtest", NULL, true), 166 PCONFDUMP(PMIC_MPP_CONF_PAIRED, "paired", NULL, false), 167 }; 168 #endif 169 170 static const char *const pmic_mpp_groups[] = { 171 "mpp1", "mpp2", "mpp3", "mpp4", "mpp5", "mpp6", "mpp7", "mpp8", 172 }; 173 174 #define PMIC_MPP_DIGITAL 0 175 #define PMIC_MPP_ANALOG 1 176 #define PMIC_MPP_SINK 2 177 178 static const char *const pmic_mpp_functions[] = { 179 "digital", "analog", "sink" 180 }; 181 182 static int pmic_mpp_read(struct pmic_mpp_state *state, 183 struct pmic_mpp_pad *pad, unsigned int addr) 184 { 185 unsigned int val; 186 int ret; 187 188 ret = regmap_read(state->map, pad->base + addr, &val); 189 if (ret < 0) 190 dev_err(state->dev, "read 0x%x failed\n", addr); 191 else 192 ret = val; 193 194 return ret; 195 } 196 197 static int pmic_mpp_write(struct pmic_mpp_state *state, 198 struct pmic_mpp_pad *pad, unsigned int addr, 199 unsigned int val) 200 { 201 int ret; 202 203 ret = regmap_write(state->map, pad->base + addr, val); 204 if (ret < 0) 205 dev_err(state->dev, "write 0x%x failed\n", addr); 206 207 return ret; 208 } 209 210 static int pmic_mpp_get_groups_count(struct pinctrl_dev *pctldev) 211 { 212 /* Every PIN is a group */ 213 return pctldev->desc->npins; 214 } 215 216 static const char *pmic_mpp_get_group_name(struct pinctrl_dev *pctldev, 217 unsigned pin) 218 { 219 return pctldev->desc->pins[pin].name; 220 } 221 222 static int pmic_mpp_get_group_pins(struct pinctrl_dev *pctldev, 223 unsigned pin, 224 const unsigned **pins, unsigned *num_pins) 225 { 226 *pins = &pctldev->desc->pins[pin].number; 227 *num_pins = 1; 228 return 0; 229 } 230 231 static const struct pinctrl_ops pmic_mpp_pinctrl_ops = { 232 .get_groups_count = pmic_mpp_get_groups_count, 233 .get_group_name = pmic_mpp_get_group_name, 234 .get_group_pins = pmic_mpp_get_group_pins, 235 .dt_node_to_map = pinconf_generic_dt_node_to_map_group, 236 .dt_free_map = pinctrl_utils_dt_free_map, 237 }; 238 239 static int pmic_mpp_get_functions_count(struct pinctrl_dev *pctldev) 240 { 241 return ARRAY_SIZE(pmic_mpp_functions); 242 } 243 244 static const char *pmic_mpp_get_function_name(struct pinctrl_dev *pctldev, 245 unsigned function) 246 { 247 return pmic_mpp_functions[function]; 248 } 249 250 static int pmic_mpp_get_function_groups(struct pinctrl_dev *pctldev, 251 unsigned function, 252 const char *const **groups, 253 unsigned *const num_qgroups) 254 { 255 *groups = pmic_mpp_groups; 256 *num_qgroups = pctldev->desc->npins; 257 return 0; 258 } 259 260 static int pmic_mpp_write_mode_ctl(struct pmic_mpp_state *state, 261 struct pmic_mpp_pad *pad) 262 { 263 unsigned int mode; 264 unsigned int sel; 265 unsigned int val; 266 unsigned int en; 267 268 switch (pad->function) { 269 case PMIC_MPP_ANALOG: 270 if (pad->input_enabled && pad->output_enabled) 271 mode = PMIC_MPP_MODE_ANALOG_BIDIR; 272 else if (pad->input_enabled) 273 mode = PMIC_MPP_MODE_ANALOG_INPUT; 274 else 275 mode = PMIC_MPP_MODE_ANALOG_OUTPUT; 276 break; 277 case PMIC_MPP_DIGITAL: 278 if (pad->input_enabled && pad->output_enabled) 279 mode = PMIC_MPP_MODE_DIGITAL_BIDIR; 280 else if (pad->input_enabled) 281 mode = PMIC_MPP_MODE_DIGITAL_INPUT; 282 else 283 mode = PMIC_MPP_MODE_DIGITAL_OUTPUT; 284 break; 285 case PMIC_MPP_SINK: 286 default: 287 mode = PMIC_MPP_MODE_CURRENT_SINK; 288 break; 289 } 290 291 if (pad->dtest) 292 sel = PMIC_MPP_SELECTOR_DTEST_FIRST + pad->dtest - 1; 293 else if (pad->paired) 294 sel = PMIC_MPP_SELECTOR_PAIRED; 295 else 296 sel = PMIC_MPP_SELECTOR_NORMAL; 297 298 en = !!pad->out_value; 299 300 val = mode << PMIC_MPP_REG_MODE_DIR_SHIFT | 301 sel << PMIC_MPP_REG_MODE_FUNCTION_SHIFT | 302 en; 303 304 return pmic_mpp_write(state, pad, PMIC_MPP_REG_MODE_CTL, val); 305 } 306 307 static int pmic_mpp_set_mux(struct pinctrl_dev *pctldev, unsigned function, 308 unsigned pin) 309 { 310 struct pmic_mpp_state *state = pinctrl_dev_get_drvdata(pctldev); 311 struct pmic_mpp_pad *pad; 312 unsigned int val; 313 int ret; 314 315 pad = pctldev->desc->pins[pin].drv_data; 316 317 pad->function = function; 318 319 ret = pmic_mpp_write_mode_ctl(state, pad); 320 321 val = pad->is_enabled << PMIC_MPP_REG_MASTER_EN_SHIFT; 322 323 return pmic_mpp_write(state, pad, PMIC_MPP_REG_EN_CTL, val); 324 } 325 326 static const struct pinmux_ops pmic_mpp_pinmux_ops = { 327 .get_functions_count = pmic_mpp_get_functions_count, 328 .get_function_name = pmic_mpp_get_function_name, 329 .get_function_groups = pmic_mpp_get_function_groups, 330 .set_mux = pmic_mpp_set_mux, 331 }; 332 333 static int pmic_mpp_config_get(struct pinctrl_dev *pctldev, 334 unsigned int pin, unsigned long *config) 335 { 336 unsigned param = pinconf_to_config_param(*config); 337 struct pmic_mpp_pad *pad; 338 unsigned arg = 0; 339 340 pad = pctldev->desc->pins[pin].drv_data; 341 342 switch (param) { 343 case PIN_CONFIG_BIAS_DISABLE: 344 arg = pad->pullup == PMIC_MPP_PULL_UP_OPEN; 345 break; 346 case PIN_CONFIG_BIAS_PULL_UP: 347 switch (pad->pullup) { 348 case PMIC_MPP_PULL_UP_OPEN: 349 arg = 0; 350 break; 351 case PMIC_MPP_PULL_UP_0P6KOHM: 352 arg = 600; 353 break; 354 case PMIC_MPP_PULL_UP_10KOHM: 355 arg = 10000; 356 break; 357 case PMIC_MPP_PULL_UP_30KOHM: 358 arg = 30000; 359 break; 360 default: 361 return -EINVAL; 362 } 363 break; 364 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: 365 arg = !pad->is_enabled; 366 break; 367 case PIN_CONFIG_POWER_SOURCE: 368 arg = pad->power_source; 369 break; 370 case PIN_CONFIG_INPUT_ENABLE: 371 arg = pad->input_enabled; 372 break; 373 case PIN_CONFIG_OUTPUT: 374 arg = pad->out_value; 375 break; 376 case PMIC_MPP_CONF_DTEST_SELECTOR: 377 arg = pad->dtest; 378 break; 379 case PMIC_MPP_CONF_AMUX_ROUTE: 380 arg = pad->amux_input; 381 break; 382 case PMIC_MPP_CONF_PAIRED: 383 arg = pad->paired; 384 break; 385 case PIN_CONFIG_DRIVE_STRENGTH: 386 arg = pad->drive_strength; 387 break; 388 case PMIC_MPP_CONF_ANALOG_LEVEL: 389 arg = pad->aout_level; 390 break; 391 default: 392 return -EINVAL; 393 } 394 395 /* Convert register value to pinconf value */ 396 *config = pinconf_to_config_packed(param, arg); 397 return 0; 398 } 399 400 static int pmic_mpp_config_set(struct pinctrl_dev *pctldev, unsigned int pin, 401 unsigned long *configs, unsigned nconfs) 402 { 403 struct pmic_mpp_state *state = pinctrl_dev_get_drvdata(pctldev); 404 struct pmic_mpp_pad *pad; 405 unsigned param, arg; 406 unsigned int val; 407 int i, ret; 408 409 pad = pctldev->desc->pins[pin].drv_data; 410 411 /* Make it possible to enable the pin, by not setting high impedance */ 412 pad->is_enabled = true; 413 414 for (i = 0; i < nconfs; i++) { 415 param = pinconf_to_config_param(configs[i]); 416 arg = pinconf_to_config_argument(configs[i]); 417 418 switch (param) { 419 case PIN_CONFIG_BIAS_DISABLE: 420 pad->pullup = PMIC_MPP_PULL_UP_OPEN; 421 break; 422 case PIN_CONFIG_BIAS_PULL_UP: 423 switch (arg) { 424 case 600: 425 pad->pullup = PMIC_MPP_PULL_UP_0P6KOHM; 426 break; 427 case 10000: 428 pad->pullup = PMIC_MPP_PULL_UP_10KOHM; 429 break; 430 case 30000: 431 pad->pullup = PMIC_MPP_PULL_UP_30KOHM; 432 break; 433 default: 434 return -EINVAL; 435 } 436 break; 437 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: 438 pad->is_enabled = false; 439 break; 440 case PIN_CONFIG_POWER_SOURCE: 441 if (arg >= pad->num_sources) 442 return -EINVAL; 443 pad->power_source = arg; 444 break; 445 case PIN_CONFIG_INPUT_ENABLE: 446 pad->input_enabled = arg ? true : false; 447 break; 448 case PIN_CONFIG_OUTPUT: 449 pad->output_enabled = true; 450 pad->out_value = arg; 451 break; 452 case PMIC_MPP_CONF_DTEST_SELECTOR: 453 pad->dtest = arg; 454 break; 455 case PIN_CONFIG_DRIVE_STRENGTH: 456 arg = pad->drive_strength; 457 break; 458 case PMIC_MPP_CONF_AMUX_ROUTE: 459 if (arg >= PMIC_MPP_AMUX_ROUTE_ABUS4) 460 return -EINVAL; 461 pad->amux_input = arg; 462 break; 463 case PMIC_MPP_CONF_ANALOG_LEVEL: 464 pad->aout_level = arg; 465 break; 466 case PMIC_MPP_CONF_PAIRED: 467 pad->paired = !!arg; 468 break; 469 default: 470 return -EINVAL; 471 } 472 } 473 474 val = pad->power_source << PMIC_MPP_REG_VIN_SHIFT; 475 476 ret = pmic_mpp_write(state, pad, PMIC_MPP_REG_DIG_VIN_CTL, val); 477 if (ret < 0) 478 return ret; 479 480 val = pad->pullup << PMIC_MPP_REG_PULL_SHIFT; 481 482 ret = pmic_mpp_write(state, pad, PMIC_MPP_REG_DIG_PULL_CTL, val); 483 if (ret < 0) 484 return ret; 485 486 val = pad->amux_input & PMIC_MPP_REG_AIN_ROUTE_MASK; 487 488 ret = pmic_mpp_write(state, pad, PMIC_MPP_REG_AIN_CTL, val); 489 if (ret < 0) 490 return ret; 491 492 ret = pmic_mpp_write(state, pad, PMIC_MPP_REG_AOUT_CTL, pad->aout_level); 493 if (ret < 0) 494 return ret; 495 496 ret = pmic_mpp_write_mode_ctl(state, pad); 497 if (ret < 0) 498 return ret; 499 500 val = pad->is_enabled << PMIC_MPP_REG_MASTER_EN_SHIFT; 501 502 return pmic_mpp_write(state, pad, PMIC_MPP_REG_EN_CTL, val); 503 } 504 505 static void pmic_mpp_config_dbg_show(struct pinctrl_dev *pctldev, 506 struct seq_file *s, unsigned pin) 507 { 508 struct pmic_mpp_state *state = pinctrl_dev_get_drvdata(pctldev); 509 struct pmic_mpp_pad *pad; 510 int ret; 511 512 static const char *const biases[] = { 513 "0.6kOhm", "10kOhm", "30kOhm", "Disabled" 514 }; 515 516 pad = pctldev->desc->pins[pin].drv_data; 517 518 seq_printf(s, " mpp%-2d:", pin + PMIC_MPP_PHYSICAL_OFFSET); 519 520 if (!pad->is_enabled) { 521 seq_puts(s, " ---"); 522 } else { 523 524 if (pad->input_enabled) { 525 ret = pmic_mpp_read(state, pad, PMIC_MPP_REG_RT_STS); 526 if (ret < 0) 527 return; 528 529 ret &= PMIC_MPP_REG_RT_STS_VAL_MASK; 530 pad->out_value = ret; 531 } 532 533 seq_printf(s, " %-4s", pad->output_enabled ? "out" : "in"); 534 seq_printf(s, " %-7s", pmic_mpp_functions[pad->function]); 535 seq_printf(s, " vin-%d", pad->power_source); 536 seq_printf(s, " %d", pad->aout_level); 537 seq_printf(s, " %-8s", biases[pad->pullup]); 538 seq_printf(s, " %-4s", pad->out_value ? "high" : "low"); 539 if (pad->dtest) 540 seq_printf(s, " dtest%d", pad->dtest); 541 if (pad->paired) 542 seq_puts(s, " paired"); 543 } 544 } 545 546 static const struct pinconf_ops pmic_mpp_pinconf_ops = { 547 .is_generic = true, 548 .pin_config_group_get = pmic_mpp_config_get, 549 .pin_config_group_set = pmic_mpp_config_set, 550 .pin_config_group_dbg_show = pmic_mpp_config_dbg_show, 551 }; 552 553 static int pmic_mpp_direction_input(struct gpio_chip *chip, unsigned pin) 554 { 555 struct pmic_mpp_state *state = gpiochip_get_data(chip); 556 unsigned long config; 557 558 config = pinconf_to_config_packed(PIN_CONFIG_INPUT_ENABLE, 1); 559 560 return pmic_mpp_config_set(state->ctrl, pin, &config, 1); 561 } 562 563 static int pmic_mpp_direction_output(struct gpio_chip *chip, 564 unsigned pin, int val) 565 { 566 struct pmic_mpp_state *state = gpiochip_get_data(chip); 567 unsigned long config; 568 569 config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, val); 570 571 return pmic_mpp_config_set(state->ctrl, pin, &config, 1); 572 } 573 574 static int pmic_mpp_get(struct gpio_chip *chip, unsigned pin) 575 { 576 struct pmic_mpp_state *state = gpiochip_get_data(chip); 577 struct pmic_mpp_pad *pad; 578 int ret; 579 580 pad = state->ctrl->desc->pins[pin].drv_data; 581 582 if (pad->input_enabled) { 583 ret = pmic_mpp_read(state, pad, PMIC_MPP_REG_RT_STS); 584 if (ret < 0) 585 return ret; 586 587 pad->out_value = ret & PMIC_MPP_REG_RT_STS_VAL_MASK; 588 } 589 590 return !!pad->out_value; 591 } 592 593 static void pmic_mpp_set(struct gpio_chip *chip, unsigned pin, int value) 594 { 595 struct pmic_mpp_state *state = gpiochip_get_data(chip); 596 unsigned long config; 597 598 config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, value); 599 600 pmic_mpp_config_set(state->ctrl, pin, &config, 1); 601 } 602 603 static int pmic_mpp_of_xlate(struct gpio_chip *chip, 604 const struct of_phandle_args *gpio_desc, 605 u32 *flags) 606 { 607 if (chip->of_gpio_n_cells < 2) 608 return -EINVAL; 609 610 if (flags) 611 *flags = gpio_desc->args[1]; 612 613 return gpio_desc->args[0] - PMIC_MPP_PHYSICAL_OFFSET; 614 } 615 616 static int pmic_mpp_to_irq(struct gpio_chip *chip, unsigned pin) 617 { 618 struct pmic_mpp_state *state = gpiochip_get_data(chip); 619 struct pmic_mpp_pad *pad; 620 621 pad = state->ctrl->desc->pins[pin].drv_data; 622 623 return pad->irq; 624 } 625 626 static void pmic_mpp_dbg_show(struct seq_file *s, struct gpio_chip *chip) 627 { 628 struct pmic_mpp_state *state = gpiochip_get_data(chip); 629 unsigned i; 630 631 for (i = 0; i < chip->ngpio; i++) { 632 pmic_mpp_config_dbg_show(state->ctrl, s, i); 633 seq_puts(s, "\n"); 634 } 635 } 636 637 static const struct gpio_chip pmic_mpp_gpio_template = { 638 .direction_input = pmic_mpp_direction_input, 639 .direction_output = pmic_mpp_direction_output, 640 .get = pmic_mpp_get, 641 .set = pmic_mpp_set, 642 .request = gpiochip_generic_request, 643 .free = gpiochip_generic_free, 644 .of_xlate = pmic_mpp_of_xlate, 645 .to_irq = pmic_mpp_to_irq, 646 .dbg_show = pmic_mpp_dbg_show, 647 }; 648 649 static int pmic_mpp_populate(struct pmic_mpp_state *state, 650 struct pmic_mpp_pad *pad) 651 { 652 int type, subtype, val, dir; 653 unsigned int sel; 654 655 type = pmic_mpp_read(state, pad, PMIC_MPP_REG_TYPE); 656 if (type < 0) 657 return type; 658 659 if (type != PMIC_MPP_TYPE) { 660 dev_err(state->dev, "incorrect block type 0x%x at 0x%x\n", 661 type, pad->base); 662 return -ENODEV; 663 } 664 665 subtype = pmic_mpp_read(state, pad, PMIC_MPP_REG_SUBTYPE); 666 if (subtype < 0) 667 return subtype; 668 669 switch (subtype) { 670 case PMIC_MPP_SUBTYPE_4CH_NO_ANA_OUT: 671 case PMIC_MPP_SUBTYPE_ULT_4CH_NO_ANA_OUT: 672 case PMIC_MPP_SUBTYPE_4CH_NO_SINK: 673 case PMIC_MPP_SUBTYPE_ULT_4CH_NO_SINK: 674 case PMIC_MPP_SUBTYPE_4CH_FULL_FUNC: 675 pad->num_sources = 4; 676 break; 677 case PMIC_MPP_SUBTYPE_8CH_FULL_FUNC: 678 pad->num_sources = 8; 679 break; 680 default: 681 dev_err(state->dev, "unknown MPP type 0x%x at 0x%x\n", 682 subtype, pad->base); 683 return -ENODEV; 684 } 685 686 val = pmic_mpp_read(state, pad, PMIC_MPP_REG_MODE_CTL); 687 if (val < 0) 688 return val; 689 690 pad->out_value = val & PMIC_MPP_REG_MODE_VALUE_MASK; 691 692 dir = val >> PMIC_MPP_REG_MODE_DIR_SHIFT; 693 dir &= PMIC_MPP_REG_MODE_DIR_MASK; 694 695 switch (dir) { 696 case PMIC_MPP_MODE_DIGITAL_INPUT: 697 pad->input_enabled = true; 698 pad->output_enabled = false; 699 pad->function = PMIC_MPP_DIGITAL; 700 break; 701 case PMIC_MPP_MODE_DIGITAL_OUTPUT: 702 pad->input_enabled = false; 703 pad->output_enabled = true; 704 pad->function = PMIC_MPP_DIGITAL; 705 break; 706 case PMIC_MPP_MODE_DIGITAL_BIDIR: 707 pad->input_enabled = true; 708 pad->output_enabled = true; 709 pad->function = PMIC_MPP_DIGITAL; 710 break; 711 case PMIC_MPP_MODE_ANALOG_BIDIR: 712 pad->input_enabled = true; 713 pad->output_enabled = true; 714 pad->function = PMIC_MPP_ANALOG; 715 break; 716 case PMIC_MPP_MODE_ANALOG_INPUT: 717 pad->input_enabled = true; 718 pad->output_enabled = false; 719 pad->function = PMIC_MPP_ANALOG; 720 break; 721 case PMIC_MPP_MODE_ANALOG_OUTPUT: 722 pad->input_enabled = false; 723 pad->output_enabled = true; 724 pad->function = PMIC_MPP_ANALOG; 725 break; 726 case PMIC_MPP_MODE_CURRENT_SINK: 727 pad->input_enabled = false; 728 pad->output_enabled = true; 729 pad->function = PMIC_MPP_SINK; 730 break; 731 default: 732 dev_err(state->dev, "unknown MPP direction\n"); 733 return -ENODEV; 734 } 735 736 sel = val >> PMIC_MPP_REG_MODE_FUNCTION_SHIFT; 737 sel &= PMIC_MPP_REG_MODE_FUNCTION_MASK; 738 739 if (sel >= PMIC_MPP_SELECTOR_DTEST_FIRST) 740 pad->dtest = sel + 1; 741 else if (sel == PMIC_MPP_SELECTOR_PAIRED) 742 pad->paired = true; 743 744 val = pmic_mpp_read(state, pad, PMIC_MPP_REG_DIG_VIN_CTL); 745 if (val < 0) 746 return val; 747 748 pad->power_source = val >> PMIC_MPP_REG_VIN_SHIFT; 749 pad->power_source &= PMIC_MPP_REG_VIN_MASK; 750 751 val = pmic_mpp_read(state, pad, PMIC_MPP_REG_DIG_PULL_CTL); 752 if (val < 0) 753 return val; 754 755 pad->pullup = val >> PMIC_MPP_REG_PULL_SHIFT; 756 pad->pullup &= PMIC_MPP_REG_PULL_MASK; 757 758 val = pmic_mpp_read(state, pad, PMIC_MPP_REG_AIN_CTL); 759 if (val < 0) 760 return val; 761 762 pad->amux_input = val >> PMIC_MPP_REG_AIN_ROUTE_SHIFT; 763 pad->amux_input &= PMIC_MPP_REG_AIN_ROUTE_MASK; 764 765 val = pmic_mpp_read(state, pad, PMIC_MPP_REG_SINK_CTL); 766 if (val < 0) 767 return val; 768 769 pad->drive_strength = val; 770 771 val = pmic_mpp_read(state, pad, PMIC_MPP_REG_AOUT_CTL); 772 if (val < 0) 773 return val; 774 775 pad->aout_level = val; 776 777 val = pmic_mpp_read(state, pad, PMIC_MPP_REG_EN_CTL); 778 if (val < 0) 779 return val; 780 781 pad->is_enabled = !!val; 782 783 return 0; 784 } 785 786 static int pmic_mpp_probe(struct platform_device *pdev) 787 { 788 struct device *dev = &pdev->dev; 789 struct pinctrl_pin_desc *pindesc; 790 struct pinctrl_desc *pctrldesc; 791 struct pmic_mpp_pad *pad, *pads; 792 struct pmic_mpp_state *state; 793 int ret, npins, i; 794 u32 reg; 795 796 ret = of_property_read_u32(dev->of_node, "reg", ®); 797 if (ret < 0) { 798 dev_err(dev, "missing base address"); 799 return ret; 800 } 801 802 npins = platform_irq_count(pdev); 803 if (!npins) 804 return -EINVAL; 805 if (npins < 0) 806 return npins; 807 808 BUG_ON(npins > ARRAY_SIZE(pmic_mpp_groups)); 809 810 state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL); 811 if (!state) 812 return -ENOMEM; 813 814 platform_set_drvdata(pdev, state); 815 816 state->dev = &pdev->dev; 817 state->map = dev_get_regmap(dev->parent, NULL); 818 819 pindesc = devm_kcalloc(dev, npins, sizeof(*pindesc), GFP_KERNEL); 820 if (!pindesc) 821 return -ENOMEM; 822 823 pads = devm_kcalloc(dev, npins, sizeof(*pads), GFP_KERNEL); 824 if (!pads) 825 return -ENOMEM; 826 827 pctrldesc = devm_kzalloc(dev, sizeof(*pctrldesc), GFP_KERNEL); 828 if (!pctrldesc) 829 return -ENOMEM; 830 831 pctrldesc->pctlops = &pmic_mpp_pinctrl_ops; 832 pctrldesc->pmxops = &pmic_mpp_pinmux_ops; 833 pctrldesc->confops = &pmic_mpp_pinconf_ops; 834 pctrldesc->owner = THIS_MODULE; 835 pctrldesc->name = dev_name(dev); 836 pctrldesc->pins = pindesc; 837 pctrldesc->npins = npins; 838 839 pctrldesc->num_custom_params = ARRAY_SIZE(pmic_mpp_bindings); 840 pctrldesc->custom_params = pmic_mpp_bindings; 841 #ifdef CONFIG_DEBUG_FS 842 pctrldesc->custom_conf_items = pmic_conf_items; 843 #endif 844 845 for (i = 0; i < npins; i++, pindesc++) { 846 pad = &pads[i]; 847 pindesc->drv_data = pad; 848 pindesc->number = i; 849 pindesc->name = pmic_mpp_groups[i]; 850 851 pad->irq = platform_get_irq(pdev, i); 852 if (pad->irq < 0) 853 return pad->irq; 854 855 pad->base = reg + i * PMIC_MPP_ADDRESS_RANGE; 856 857 ret = pmic_mpp_populate(state, pad); 858 if (ret < 0) 859 return ret; 860 } 861 862 state->chip = pmic_mpp_gpio_template; 863 state->chip.parent = dev; 864 state->chip.base = -1; 865 state->chip.ngpio = npins; 866 state->chip.label = dev_name(dev); 867 state->chip.of_gpio_n_cells = 2; 868 state->chip.can_sleep = false; 869 870 state->ctrl = pinctrl_register(pctrldesc, dev, state); 871 if (IS_ERR(state->ctrl)) 872 return PTR_ERR(state->ctrl); 873 874 ret = gpiochip_add_data(&state->chip, state); 875 if (ret) { 876 dev_err(state->dev, "can't add gpio chip\n"); 877 goto err_chip; 878 } 879 880 ret = gpiochip_add_pin_range(&state->chip, dev_name(dev), 0, 0, npins); 881 if (ret) { 882 dev_err(dev, "failed to add pin range\n"); 883 goto err_range; 884 } 885 886 return 0; 887 888 err_range: 889 gpiochip_remove(&state->chip); 890 err_chip: 891 pinctrl_unregister(state->ctrl); 892 return ret; 893 } 894 895 static int pmic_mpp_remove(struct platform_device *pdev) 896 { 897 struct pmic_mpp_state *state = platform_get_drvdata(pdev); 898 899 gpiochip_remove(&state->chip); 900 pinctrl_unregister(state->ctrl); 901 return 0; 902 } 903 904 static const struct of_device_id pmic_mpp_of_match[] = { 905 { .compatible = "qcom,pm8841-mpp" }, /* 4 MPP's */ 906 { .compatible = "qcom,pm8916-mpp" }, /* 4 MPP's */ 907 { .compatible = "qcom,pm8941-mpp" }, /* 8 MPP's */ 908 { .compatible = "qcom,pm8994-mpp" }, /* 8 MPP's */ 909 { .compatible = "qcom,pma8084-mpp" }, /* 8 MPP's */ 910 { }, 911 }; 912 913 MODULE_DEVICE_TABLE(of, pmic_mpp_of_match); 914 915 static struct platform_driver pmic_mpp_driver = { 916 .driver = { 917 .name = "qcom-spmi-mpp", 918 .of_match_table = pmic_mpp_of_match, 919 }, 920 .probe = pmic_mpp_probe, 921 .remove = pmic_mpp_remove, 922 }; 923 924 module_platform_driver(pmic_mpp_driver); 925 926 MODULE_AUTHOR("Ivan T. Ivanov <iivanov@mm-sol.com>"); 927 MODULE_DESCRIPTION("Qualcomm SPMI PMIC MPP pin control driver"); 928 MODULE_ALIAS("platform:qcom-spmi-mpp"); 929 MODULE_LICENSE("GPL v2"); 930