1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2012-2014, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/gpio/driver.h> 7 #include <linux/module.h> 8 #include <linux/of.h> 9 #include <linux/of_irq.h> 10 #include <linux/platform_device.h> 11 #include <linux/regmap.h> 12 #include <linux/seq_file.h> 13 #include <linux/slab.h> 14 #include <linux/types.h> 15 16 #include <linux/pinctrl/pinconf-generic.h> 17 #include <linux/pinctrl/pinconf.h> 18 #include <linux/pinctrl/pinmux.h> 19 20 #include <dt-bindings/pinctrl/qcom,pmic-mpp.h> 21 22 #include "../core.h" 23 #include "../pinctrl-utils.h" 24 25 #define PMIC_MPP_ADDRESS_RANGE 0x100 26 27 /* 28 * Pull Up Values - it indicates whether a pull-up should be 29 * applied for bidirectional mode only. The hardware ignores the 30 * configuration when operating in other modes. 31 */ 32 #define PMIC_MPP_PULL_UP_0P6KOHM 0 33 #define PMIC_MPP_PULL_UP_10KOHM 1 34 #define PMIC_MPP_PULL_UP_30KOHM 2 35 #define PMIC_MPP_PULL_UP_OPEN 3 36 37 /* type registers base address bases */ 38 #define PMIC_MPP_REG_TYPE 0x4 39 #define PMIC_MPP_REG_SUBTYPE 0x5 40 41 /* mpp peripheral type and subtype values */ 42 #define PMIC_MPP_TYPE 0x11 43 #define PMIC_MPP_SUBTYPE_4CH_NO_ANA_OUT 0x3 44 #define PMIC_MPP_SUBTYPE_ULT_4CH_NO_ANA_OUT 0x4 45 #define PMIC_MPP_SUBTYPE_4CH_NO_SINK 0x5 46 #define PMIC_MPP_SUBTYPE_ULT_4CH_NO_SINK 0x6 47 #define PMIC_MPP_SUBTYPE_4CH_FULL_FUNC 0x7 48 #define PMIC_MPP_SUBTYPE_8CH_FULL_FUNC 0xf 49 50 #define PMIC_MPP_REG_RT_STS 0x10 51 #define PMIC_MPP_REG_RT_STS_VAL_MASK 0x1 52 53 /* control register base address bases */ 54 #define PMIC_MPP_REG_MODE_CTL 0x40 55 #define PMIC_MPP_REG_DIG_VIN_CTL 0x41 56 #define PMIC_MPP_REG_DIG_PULL_CTL 0x42 57 #define PMIC_MPP_REG_DIG_IN_CTL 0x43 58 #define PMIC_MPP_REG_EN_CTL 0x46 59 #define PMIC_MPP_REG_AOUT_CTL 0x48 60 #define PMIC_MPP_REG_AIN_CTL 0x4a 61 #define PMIC_MPP_REG_SINK_CTL 0x4c 62 63 /* PMIC_MPP_REG_MODE_CTL */ 64 #define PMIC_MPP_REG_MODE_VALUE_MASK 0x1 65 #define PMIC_MPP_REG_MODE_FUNCTION_SHIFT 1 66 #define PMIC_MPP_REG_MODE_FUNCTION_MASK 0x7 67 #define PMIC_MPP_REG_MODE_DIR_SHIFT 4 68 #define PMIC_MPP_REG_MODE_DIR_MASK 0x7 69 70 /* PMIC_MPP_REG_DIG_VIN_CTL */ 71 #define PMIC_MPP_REG_VIN_SHIFT 0 72 #define PMIC_MPP_REG_VIN_MASK 0x7 73 74 /* PMIC_MPP_REG_DIG_PULL_CTL */ 75 #define PMIC_MPP_REG_PULL_SHIFT 0 76 #define PMIC_MPP_REG_PULL_MASK 0x7 77 78 /* PMIC_MPP_REG_EN_CTL */ 79 #define PMIC_MPP_REG_MASTER_EN_SHIFT 7 80 81 /* PMIC_MPP_REG_AIN_CTL */ 82 #define PMIC_MPP_REG_AIN_ROUTE_SHIFT 0 83 #define PMIC_MPP_REG_AIN_ROUTE_MASK 0x7 84 85 #define PMIC_MPP_MODE_DIGITAL_INPUT 0 86 #define PMIC_MPP_MODE_DIGITAL_OUTPUT 1 87 #define PMIC_MPP_MODE_DIGITAL_BIDIR 2 88 #define PMIC_MPP_MODE_ANALOG_BIDIR 3 89 #define PMIC_MPP_MODE_ANALOG_INPUT 4 90 #define PMIC_MPP_MODE_ANALOG_OUTPUT 5 91 #define PMIC_MPP_MODE_CURRENT_SINK 6 92 93 #define PMIC_MPP_SELECTOR_NORMAL 0 94 #define PMIC_MPP_SELECTOR_PAIRED 1 95 #define PMIC_MPP_SELECTOR_DTEST_FIRST 4 96 97 #define PMIC_MPP_PHYSICAL_OFFSET 1 98 99 /* Qualcomm specific pin configurations */ 100 #define PMIC_MPP_CONF_AMUX_ROUTE (PIN_CONFIG_END + 1) 101 #define PMIC_MPP_CONF_ANALOG_LEVEL (PIN_CONFIG_END + 2) 102 #define PMIC_MPP_CONF_DTEST_SELECTOR (PIN_CONFIG_END + 3) 103 #define PMIC_MPP_CONF_PAIRED (PIN_CONFIG_END + 4) 104 105 /** 106 * struct pmic_mpp_pad - keep current MPP settings 107 * @base: Address base in SPMI device. 108 * @is_enabled: Set to false when MPP should be put in high Z state. 109 * @out_value: Cached pin output value. 110 * @output_enabled: Set to true if MPP output logic is enabled. 111 * @input_enabled: Set to true if MPP input buffer logic is enabled. 112 * @paired: Pin operates in paired mode 113 * @has_pullup: Pin has support to configure pullup 114 * @num_sources: Number of power-sources supported by this MPP. 115 * @power_source: Current power-source used. 116 * @amux_input: Set the source for analog input. 117 * @aout_level: Analog output level 118 * @pullup: Pullup resistor value. Valid in Bidirectional mode only. 119 * @function: See pmic_mpp_functions[]. 120 * @drive_strength: Amount of current in sink mode 121 * @dtest: DTEST route selector 122 */ 123 struct pmic_mpp_pad { 124 u16 base; 125 bool is_enabled; 126 bool out_value; 127 bool output_enabled; 128 bool input_enabled; 129 bool paired; 130 bool has_pullup; 131 unsigned int num_sources; 132 unsigned int power_source; 133 unsigned int amux_input; 134 unsigned int aout_level; 135 unsigned int pullup; 136 unsigned int function; 137 unsigned int drive_strength; 138 unsigned int dtest; 139 }; 140 141 struct pmic_mpp_state { 142 struct device *dev; 143 struct regmap *map; 144 struct pinctrl_dev *ctrl; 145 struct gpio_chip chip; 146 struct irq_chip irq; 147 }; 148 149 static const struct pinconf_generic_params pmic_mpp_bindings[] = { 150 {"qcom,amux-route", PMIC_MPP_CONF_AMUX_ROUTE, 0}, 151 {"qcom,analog-level", PMIC_MPP_CONF_ANALOG_LEVEL, 0}, 152 {"qcom,dtest", PMIC_MPP_CONF_DTEST_SELECTOR, 0}, 153 {"qcom,paired", PMIC_MPP_CONF_PAIRED, 0}, 154 }; 155 156 #ifdef CONFIG_DEBUG_FS 157 static const struct pin_config_item pmic_conf_items[] = { 158 PCONFDUMP(PMIC_MPP_CONF_AMUX_ROUTE, "analog mux", NULL, true), 159 PCONFDUMP(PMIC_MPP_CONF_ANALOG_LEVEL, "analog level", NULL, true), 160 PCONFDUMP(PMIC_MPP_CONF_DTEST_SELECTOR, "dtest", NULL, true), 161 PCONFDUMP(PMIC_MPP_CONF_PAIRED, "paired", NULL, false), 162 }; 163 #endif 164 165 static const char *const pmic_mpp_groups[] = { 166 "mpp1", "mpp2", "mpp3", "mpp4", "mpp5", "mpp6", "mpp7", "mpp8", 167 }; 168 169 #define PMIC_MPP_DIGITAL 0 170 #define PMIC_MPP_ANALOG 1 171 #define PMIC_MPP_SINK 2 172 173 static const char *const pmic_mpp_functions[] = { 174 "digital", "analog", "sink" 175 }; 176 177 static int pmic_mpp_read(struct pmic_mpp_state *state, 178 struct pmic_mpp_pad *pad, unsigned int addr) 179 { 180 unsigned int val; 181 int ret; 182 183 ret = regmap_read(state->map, pad->base + addr, &val); 184 if (ret < 0) 185 dev_err(state->dev, "read 0x%x failed\n", addr); 186 else 187 ret = val; 188 189 return ret; 190 } 191 192 static int pmic_mpp_write(struct pmic_mpp_state *state, 193 struct pmic_mpp_pad *pad, unsigned int addr, 194 unsigned int val) 195 { 196 int ret; 197 198 ret = regmap_write(state->map, pad->base + addr, val); 199 if (ret < 0) 200 dev_err(state->dev, "write 0x%x failed\n", addr); 201 202 return ret; 203 } 204 205 static int pmic_mpp_get_groups_count(struct pinctrl_dev *pctldev) 206 { 207 /* Every PIN is a group */ 208 return pctldev->desc->npins; 209 } 210 211 static const char *pmic_mpp_get_group_name(struct pinctrl_dev *pctldev, 212 unsigned pin) 213 { 214 return pctldev->desc->pins[pin].name; 215 } 216 217 static int pmic_mpp_get_group_pins(struct pinctrl_dev *pctldev, 218 unsigned pin, 219 const unsigned **pins, unsigned *num_pins) 220 { 221 *pins = &pctldev->desc->pins[pin].number; 222 *num_pins = 1; 223 return 0; 224 } 225 226 static const struct pinctrl_ops pmic_mpp_pinctrl_ops = { 227 .get_groups_count = pmic_mpp_get_groups_count, 228 .get_group_name = pmic_mpp_get_group_name, 229 .get_group_pins = pmic_mpp_get_group_pins, 230 .dt_node_to_map = pinconf_generic_dt_node_to_map_group, 231 .dt_free_map = pinctrl_utils_free_map, 232 }; 233 234 static int pmic_mpp_get_functions_count(struct pinctrl_dev *pctldev) 235 { 236 return ARRAY_SIZE(pmic_mpp_functions); 237 } 238 239 static const char *pmic_mpp_get_function_name(struct pinctrl_dev *pctldev, 240 unsigned function) 241 { 242 return pmic_mpp_functions[function]; 243 } 244 245 static int pmic_mpp_get_function_groups(struct pinctrl_dev *pctldev, 246 unsigned function, 247 const char *const **groups, 248 unsigned *const num_qgroups) 249 { 250 *groups = pmic_mpp_groups; 251 *num_qgroups = pctldev->desc->npins; 252 return 0; 253 } 254 255 static int pmic_mpp_write_mode_ctl(struct pmic_mpp_state *state, 256 struct pmic_mpp_pad *pad) 257 { 258 unsigned int mode; 259 unsigned int sel; 260 unsigned int val; 261 unsigned int en; 262 263 switch (pad->function) { 264 case PMIC_MPP_ANALOG: 265 if (pad->input_enabled && pad->output_enabled) 266 mode = PMIC_MPP_MODE_ANALOG_BIDIR; 267 else if (pad->input_enabled) 268 mode = PMIC_MPP_MODE_ANALOG_INPUT; 269 else 270 mode = PMIC_MPP_MODE_ANALOG_OUTPUT; 271 break; 272 case PMIC_MPP_DIGITAL: 273 if (pad->input_enabled && pad->output_enabled) 274 mode = PMIC_MPP_MODE_DIGITAL_BIDIR; 275 else if (pad->input_enabled) 276 mode = PMIC_MPP_MODE_DIGITAL_INPUT; 277 else 278 mode = PMIC_MPP_MODE_DIGITAL_OUTPUT; 279 break; 280 case PMIC_MPP_SINK: 281 default: 282 mode = PMIC_MPP_MODE_CURRENT_SINK; 283 break; 284 } 285 286 if (pad->dtest) 287 sel = PMIC_MPP_SELECTOR_DTEST_FIRST + pad->dtest - 1; 288 else if (pad->paired) 289 sel = PMIC_MPP_SELECTOR_PAIRED; 290 else 291 sel = PMIC_MPP_SELECTOR_NORMAL; 292 293 en = !!pad->out_value; 294 295 val = mode << PMIC_MPP_REG_MODE_DIR_SHIFT | 296 sel << PMIC_MPP_REG_MODE_FUNCTION_SHIFT | 297 en; 298 299 return pmic_mpp_write(state, pad, PMIC_MPP_REG_MODE_CTL, val); 300 } 301 302 static int pmic_mpp_set_mux(struct pinctrl_dev *pctldev, unsigned function, 303 unsigned pin) 304 { 305 struct pmic_mpp_state *state = pinctrl_dev_get_drvdata(pctldev); 306 struct pmic_mpp_pad *pad; 307 unsigned int val; 308 int ret; 309 310 pad = pctldev->desc->pins[pin].drv_data; 311 312 pad->function = function; 313 314 ret = pmic_mpp_write_mode_ctl(state, pad); 315 if (ret < 0) 316 return ret; 317 318 val = pad->is_enabled << PMIC_MPP_REG_MASTER_EN_SHIFT; 319 320 return pmic_mpp_write(state, pad, PMIC_MPP_REG_EN_CTL, val); 321 } 322 323 static const struct pinmux_ops pmic_mpp_pinmux_ops = { 324 .get_functions_count = pmic_mpp_get_functions_count, 325 .get_function_name = pmic_mpp_get_function_name, 326 .get_function_groups = pmic_mpp_get_function_groups, 327 .set_mux = pmic_mpp_set_mux, 328 }; 329 330 static int pmic_mpp_config_get(struct pinctrl_dev *pctldev, 331 unsigned int pin, unsigned long *config) 332 { 333 unsigned param = pinconf_to_config_param(*config); 334 struct pmic_mpp_pad *pad; 335 unsigned arg = 0; 336 337 pad = pctldev->desc->pins[pin].drv_data; 338 339 switch (param) { 340 case PIN_CONFIG_BIAS_DISABLE: 341 if (pad->pullup != PMIC_MPP_PULL_UP_OPEN) 342 return -EINVAL; 343 arg = 1; 344 break; 345 case PIN_CONFIG_BIAS_PULL_UP: 346 switch (pad->pullup) { 347 case PMIC_MPP_PULL_UP_0P6KOHM: 348 arg = 600; 349 break; 350 case PMIC_MPP_PULL_UP_10KOHM: 351 arg = 10000; 352 break; 353 case PMIC_MPP_PULL_UP_30KOHM: 354 arg = 30000; 355 break; 356 default: 357 return -EINVAL; 358 } 359 break; 360 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: 361 if (pad->is_enabled) 362 return -EINVAL; 363 arg = 1; 364 break; 365 case PIN_CONFIG_POWER_SOURCE: 366 arg = pad->power_source; 367 break; 368 case PIN_CONFIG_INPUT_ENABLE: 369 if (!pad->input_enabled) 370 return -EINVAL; 371 arg = 1; 372 break; 373 case PIN_CONFIG_OUTPUT: 374 arg = pad->out_value; 375 break; 376 case PMIC_MPP_CONF_DTEST_SELECTOR: 377 arg = pad->dtest; 378 break; 379 case PMIC_MPP_CONF_AMUX_ROUTE: 380 arg = pad->amux_input; 381 break; 382 case PMIC_MPP_CONF_PAIRED: 383 if (!pad->paired) 384 return -EINVAL; 385 arg = 1; 386 break; 387 case PIN_CONFIG_DRIVE_STRENGTH: 388 arg = pad->drive_strength; 389 break; 390 case PMIC_MPP_CONF_ANALOG_LEVEL: 391 arg = pad->aout_level; 392 break; 393 default: 394 return -EINVAL; 395 } 396 397 /* Convert register value to pinconf value */ 398 *config = pinconf_to_config_packed(param, arg); 399 return 0; 400 } 401 402 static int pmic_mpp_config_set(struct pinctrl_dev *pctldev, unsigned int pin, 403 unsigned long *configs, unsigned nconfs) 404 { 405 struct pmic_mpp_state *state = pinctrl_dev_get_drvdata(pctldev); 406 struct pmic_mpp_pad *pad; 407 unsigned param, arg; 408 unsigned int val; 409 int i, ret; 410 411 pad = pctldev->desc->pins[pin].drv_data; 412 413 /* Make it possible to enable the pin, by not setting high impedance */ 414 pad->is_enabled = true; 415 416 for (i = 0; i < nconfs; i++) { 417 param = pinconf_to_config_param(configs[i]); 418 arg = pinconf_to_config_argument(configs[i]); 419 420 switch (param) { 421 case PIN_CONFIG_BIAS_DISABLE: 422 pad->pullup = PMIC_MPP_PULL_UP_OPEN; 423 break; 424 case PIN_CONFIG_BIAS_PULL_UP: 425 switch (arg) { 426 case 600: 427 pad->pullup = PMIC_MPP_PULL_UP_0P6KOHM; 428 break; 429 case 10000: 430 pad->pullup = PMIC_MPP_PULL_UP_10KOHM; 431 break; 432 case 30000: 433 pad->pullup = PMIC_MPP_PULL_UP_30KOHM; 434 break; 435 default: 436 return -EINVAL; 437 } 438 break; 439 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: 440 pad->is_enabled = false; 441 break; 442 case PIN_CONFIG_POWER_SOURCE: 443 if (arg >= pad->num_sources) 444 return -EINVAL; 445 pad->power_source = arg; 446 break; 447 case PIN_CONFIG_INPUT_ENABLE: 448 pad->input_enabled = arg ? true : false; 449 break; 450 case PIN_CONFIG_OUTPUT: 451 pad->output_enabled = true; 452 pad->out_value = arg; 453 break; 454 case PMIC_MPP_CONF_DTEST_SELECTOR: 455 pad->dtest = arg; 456 break; 457 case PIN_CONFIG_DRIVE_STRENGTH: 458 pad->drive_strength = arg; 459 break; 460 case PMIC_MPP_CONF_AMUX_ROUTE: 461 if (arg >= PMIC_MPP_AMUX_ROUTE_ABUS4) 462 return -EINVAL; 463 pad->amux_input = arg; 464 break; 465 case PMIC_MPP_CONF_ANALOG_LEVEL: 466 pad->aout_level = arg; 467 break; 468 case PMIC_MPP_CONF_PAIRED: 469 pad->paired = !!arg; 470 break; 471 default: 472 return -EINVAL; 473 } 474 } 475 476 val = pad->power_source << PMIC_MPP_REG_VIN_SHIFT; 477 478 ret = pmic_mpp_write(state, pad, PMIC_MPP_REG_DIG_VIN_CTL, val); 479 if (ret < 0) 480 return ret; 481 482 if (pad->has_pullup) { 483 val = pad->pullup << PMIC_MPP_REG_PULL_SHIFT; 484 485 ret = pmic_mpp_write(state, pad, PMIC_MPP_REG_DIG_PULL_CTL, 486 val); 487 if (ret < 0) 488 return ret; 489 } 490 491 val = pad->amux_input & PMIC_MPP_REG_AIN_ROUTE_MASK; 492 493 ret = pmic_mpp_write(state, pad, PMIC_MPP_REG_AIN_CTL, val); 494 if (ret < 0) 495 return ret; 496 497 ret = pmic_mpp_write(state, pad, PMIC_MPP_REG_AOUT_CTL, pad->aout_level); 498 if (ret < 0) 499 return ret; 500 501 ret = pmic_mpp_write_mode_ctl(state, pad); 502 if (ret < 0) 503 return ret; 504 505 ret = pmic_mpp_write(state, pad, PMIC_MPP_REG_SINK_CTL, pad->drive_strength); 506 if (ret < 0) 507 return ret; 508 509 val = pad->is_enabled << PMIC_MPP_REG_MASTER_EN_SHIFT; 510 511 return pmic_mpp_write(state, pad, PMIC_MPP_REG_EN_CTL, val); 512 } 513 514 static void pmic_mpp_config_dbg_show(struct pinctrl_dev *pctldev, 515 struct seq_file *s, unsigned pin) 516 { 517 struct pmic_mpp_state *state = pinctrl_dev_get_drvdata(pctldev); 518 struct pmic_mpp_pad *pad; 519 int ret; 520 521 static const char *const biases[] = { 522 "0.6kOhm", "10kOhm", "30kOhm", "Disabled" 523 }; 524 525 pad = pctldev->desc->pins[pin].drv_data; 526 527 seq_printf(s, " mpp%-2d:", pin + PMIC_MPP_PHYSICAL_OFFSET); 528 529 if (!pad->is_enabled) { 530 seq_puts(s, " ---"); 531 } else { 532 533 if (pad->input_enabled) { 534 ret = pmic_mpp_read(state, pad, PMIC_MPP_REG_RT_STS); 535 if (ret < 0) 536 return; 537 538 ret &= PMIC_MPP_REG_RT_STS_VAL_MASK; 539 pad->out_value = ret; 540 } 541 542 seq_printf(s, " %-4s", pad->output_enabled ? "out" : "in"); 543 seq_printf(s, " %-7s", pmic_mpp_functions[pad->function]); 544 seq_printf(s, " vin-%d", pad->power_source); 545 seq_printf(s, " %d", pad->aout_level); 546 if (pad->has_pullup) 547 seq_printf(s, " %-8s", biases[pad->pullup]); 548 seq_printf(s, " %-4s", pad->out_value ? "high" : "low"); 549 if (pad->dtest) 550 seq_printf(s, " dtest%d", pad->dtest); 551 if (pad->paired) 552 seq_puts(s, " paired"); 553 } 554 } 555 556 static const struct pinconf_ops pmic_mpp_pinconf_ops = { 557 .is_generic = true, 558 .pin_config_group_get = pmic_mpp_config_get, 559 .pin_config_group_set = pmic_mpp_config_set, 560 .pin_config_group_dbg_show = pmic_mpp_config_dbg_show, 561 }; 562 563 static int pmic_mpp_direction_input(struct gpio_chip *chip, unsigned pin) 564 { 565 struct pmic_mpp_state *state = gpiochip_get_data(chip); 566 unsigned long config; 567 568 config = pinconf_to_config_packed(PIN_CONFIG_INPUT_ENABLE, 1); 569 570 return pmic_mpp_config_set(state->ctrl, pin, &config, 1); 571 } 572 573 static int pmic_mpp_direction_output(struct gpio_chip *chip, 574 unsigned pin, int val) 575 { 576 struct pmic_mpp_state *state = gpiochip_get_data(chip); 577 unsigned long config; 578 579 config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, val); 580 581 return pmic_mpp_config_set(state->ctrl, pin, &config, 1); 582 } 583 584 static int pmic_mpp_get(struct gpio_chip *chip, unsigned pin) 585 { 586 struct pmic_mpp_state *state = gpiochip_get_data(chip); 587 struct pmic_mpp_pad *pad; 588 int ret; 589 590 pad = state->ctrl->desc->pins[pin].drv_data; 591 592 if (pad->input_enabled) { 593 ret = pmic_mpp_read(state, pad, PMIC_MPP_REG_RT_STS); 594 if (ret < 0) 595 return ret; 596 597 pad->out_value = ret & PMIC_MPP_REG_RT_STS_VAL_MASK; 598 } 599 600 return !!pad->out_value; 601 } 602 603 static void pmic_mpp_set(struct gpio_chip *chip, unsigned pin, int value) 604 { 605 struct pmic_mpp_state *state = gpiochip_get_data(chip); 606 unsigned long config; 607 608 config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, value); 609 610 pmic_mpp_config_set(state->ctrl, pin, &config, 1); 611 } 612 613 static int pmic_mpp_of_xlate(struct gpio_chip *chip, 614 const struct of_phandle_args *gpio_desc, 615 u32 *flags) 616 { 617 if (chip->of_gpio_n_cells < 2) 618 return -EINVAL; 619 620 if (flags) 621 *flags = gpio_desc->args[1]; 622 623 return gpio_desc->args[0] - PMIC_MPP_PHYSICAL_OFFSET; 624 } 625 626 static void pmic_mpp_dbg_show(struct seq_file *s, struct gpio_chip *chip) 627 { 628 struct pmic_mpp_state *state = gpiochip_get_data(chip); 629 unsigned i; 630 631 for (i = 0; i < chip->ngpio; i++) { 632 pmic_mpp_config_dbg_show(state->ctrl, s, i); 633 seq_puts(s, "\n"); 634 } 635 } 636 637 static const struct gpio_chip pmic_mpp_gpio_template = { 638 .direction_input = pmic_mpp_direction_input, 639 .direction_output = pmic_mpp_direction_output, 640 .get = pmic_mpp_get, 641 .set = pmic_mpp_set, 642 .request = gpiochip_generic_request, 643 .free = gpiochip_generic_free, 644 .of_xlate = pmic_mpp_of_xlate, 645 .dbg_show = pmic_mpp_dbg_show, 646 }; 647 648 static int pmic_mpp_populate(struct pmic_mpp_state *state, 649 struct pmic_mpp_pad *pad) 650 { 651 int type, subtype, val, dir; 652 unsigned int sel; 653 654 type = pmic_mpp_read(state, pad, PMIC_MPP_REG_TYPE); 655 if (type < 0) 656 return type; 657 658 if (type != PMIC_MPP_TYPE) { 659 dev_err(state->dev, "incorrect block type 0x%x at 0x%x\n", 660 type, pad->base); 661 return -ENODEV; 662 } 663 664 subtype = pmic_mpp_read(state, pad, PMIC_MPP_REG_SUBTYPE); 665 if (subtype < 0) 666 return subtype; 667 668 switch (subtype) { 669 case PMIC_MPP_SUBTYPE_4CH_NO_ANA_OUT: 670 case PMIC_MPP_SUBTYPE_ULT_4CH_NO_ANA_OUT: 671 case PMIC_MPP_SUBTYPE_4CH_NO_SINK: 672 case PMIC_MPP_SUBTYPE_ULT_4CH_NO_SINK: 673 case PMIC_MPP_SUBTYPE_4CH_FULL_FUNC: 674 pad->num_sources = 4; 675 break; 676 case PMIC_MPP_SUBTYPE_8CH_FULL_FUNC: 677 pad->num_sources = 8; 678 break; 679 default: 680 dev_err(state->dev, "unknown MPP type 0x%x at 0x%x\n", 681 subtype, pad->base); 682 return -ENODEV; 683 } 684 685 val = pmic_mpp_read(state, pad, PMIC_MPP_REG_MODE_CTL); 686 if (val < 0) 687 return val; 688 689 pad->out_value = val & PMIC_MPP_REG_MODE_VALUE_MASK; 690 691 dir = val >> PMIC_MPP_REG_MODE_DIR_SHIFT; 692 dir &= PMIC_MPP_REG_MODE_DIR_MASK; 693 694 switch (dir) { 695 case PMIC_MPP_MODE_DIGITAL_INPUT: 696 pad->input_enabled = true; 697 pad->output_enabled = false; 698 pad->function = PMIC_MPP_DIGITAL; 699 break; 700 case PMIC_MPP_MODE_DIGITAL_OUTPUT: 701 pad->input_enabled = false; 702 pad->output_enabled = true; 703 pad->function = PMIC_MPP_DIGITAL; 704 break; 705 case PMIC_MPP_MODE_DIGITAL_BIDIR: 706 pad->input_enabled = true; 707 pad->output_enabled = true; 708 pad->function = PMIC_MPP_DIGITAL; 709 break; 710 case PMIC_MPP_MODE_ANALOG_BIDIR: 711 pad->input_enabled = true; 712 pad->output_enabled = true; 713 pad->function = PMIC_MPP_ANALOG; 714 break; 715 case PMIC_MPP_MODE_ANALOG_INPUT: 716 pad->input_enabled = true; 717 pad->output_enabled = false; 718 pad->function = PMIC_MPP_ANALOG; 719 break; 720 case PMIC_MPP_MODE_ANALOG_OUTPUT: 721 pad->input_enabled = false; 722 pad->output_enabled = true; 723 pad->function = PMIC_MPP_ANALOG; 724 break; 725 case PMIC_MPP_MODE_CURRENT_SINK: 726 pad->input_enabled = false; 727 pad->output_enabled = true; 728 pad->function = PMIC_MPP_SINK; 729 break; 730 default: 731 dev_err(state->dev, "unknown MPP direction\n"); 732 return -ENODEV; 733 } 734 735 sel = val >> PMIC_MPP_REG_MODE_FUNCTION_SHIFT; 736 sel &= PMIC_MPP_REG_MODE_FUNCTION_MASK; 737 738 if (sel >= PMIC_MPP_SELECTOR_DTEST_FIRST) 739 pad->dtest = sel + 1; 740 else if (sel == PMIC_MPP_SELECTOR_PAIRED) 741 pad->paired = true; 742 743 val = pmic_mpp_read(state, pad, PMIC_MPP_REG_DIG_VIN_CTL); 744 if (val < 0) 745 return val; 746 747 pad->power_source = val >> PMIC_MPP_REG_VIN_SHIFT; 748 pad->power_source &= PMIC_MPP_REG_VIN_MASK; 749 750 if (subtype != PMIC_MPP_SUBTYPE_ULT_4CH_NO_ANA_OUT && 751 subtype != PMIC_MPP_SUBTYPE_ULT_4CH_NO_SINK) { 752 val = pmic_mpp_read(state, pad, PMIC_MPP_REG_DIG_PULL_CTL); 753 if (val < 0) 754 return val; 755 756 pad->pullup = val >> PMIC_MPP_REG_PULL_SHIFT; 757 pad->pullup &= PMIC_MPP_REG_PULL_MASK; 758 pad->has_pullup = true; 759 } 760 761 val = pmic_mpp_read(state, pad, PMIC_MPP_REG_AIN_CTL); 762 if (val < 0) 763 return val; 764 765 pad->amux_input = val >> PMIC_MPP_REG_AIN_ROUTE_SHIFT; 766 pad->amux_input &= PMIC_MPP_REG_AIN_ROUTE_MASK; 767 768 val = pmic_mpp_read(state, pad, PMIC_MPP_REG_SINK_CTL); 769 if (val < 0) 770 return val; 771 772 pad->drive_strength = val; 773 774 val = pmic_mpp_read(state, pad, PMIC_MPP_REG_AOUT_CTL); 775 if (val < 0) 776 return val; 777 778 pad->aout_level = val; 779 780 val = pmic_mpp_read(state, pad, PMIC_MPP_REG_EN_CTL); 781 if (val < 0) 782 return val; 783 784 pad->is_enabled = !!val; 785 786 return 0; 787 } 788 789 static int pmic_mpp_domain_translate(struct irq_domain *domain, 790 struct irq_fwspec *fwspec, 791 unsigned long *hwirq, 792 unsigned int *type) 793 { 794 struct pmic_mpp_state *state = container_of(domain->host_data, 795 struct pmic_mpp_state, 796 chip); 797 798 if (fwspec->param_count != 2 || 799 fwspec->param[0] < 1 || fwspec->param[0] > state->chip.ngpio) 800 return -EINVAL; 801 802 *hwirq = fwspec->param[0] - PMIC_MPP_PHYSICAL_OFFSET; 803 *type = fwspec->param[1]; 804 805 return 0; 806 } 807 808 static unsigned int pmic_mpp_child_offset_to_irq(struct gpio_chip *chip, 809 unsigned int offset) 810 { 811 return offset + PMIC_MPP_PHYSICAL_OFFSET; 812 } 813 814 static int pmic_mpp_child_to_parent_hwirq(struct gpio_chip *chip, 815 unsigned int child_hwirq, 816 unsigned int child_type, 817 unsigned int *parent_hwirq, 818 unsigned int *parent_type) 819 { 820 *parent_hwirq = child_hwirq + 0xc0; 821 *parent_type = child_type; 822 823 return 0; 824 } 825 826 static int pmic_mpp_probe(struct platform_device *pdev) 827 { 828 struct irq_domain *parent_domain; 829 struct device_node *parent_node; 830 struct device *dev = &pdev->dev; 831 struct pinctrl_pin_desc *pindesc; 832 struct pinctrl_desc *pctrldesc; 833 struct pmic_mpp_pad *pad, *pads; 834 struct pmic_mpp_state *state; 835 struct gpio_irq_chip *girq; 836 int ret, npins, i; 837 u32 reg; 838 839 ret = of_property_read_u32(dev->of_node, "reg", ®); 840 if (ret < 0) { 841 dev_err(dev, "missing base address"); 842 return ret; 843 } 844 845 npins = (uintptr_t) device_get_match_data(&pdev->dev); 846 847 BUG_ON(npins > ARRAY_SIZE(pmic_mpp_groups)); 848 849 state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL); 850 if (!state) 851 return -ENOMEM; 852 853 platform_set_drvdata(pdev, state); 854 855 state->dev = &pdev->dev; 856 state->map = dev_get_regmap(dev->parent, NULL); 857 858 pindesc = devm_kcalloc(dev, npins, sizeof(*pindesc), GFP_KERNEL); 859 if (!pindesc) 860 return -ENOMEM; 861 862 pads = devm_kcalloc(dev, npins, sizeof(*pads), GFP_KERNEL); 863 if (!pads) 864 return -ENOMEM; 865 866 pctrldesc = devm_kzalloc(dev, sizeof(*pctrldesc), GFP_KERNEL); 867 if (!pctrldesc) 868 return -ENOMEM; 869 870 pctrldesc->pctlops = &pmic_mpp_pinctrl_ops; 871 pctrldesc->pmxops = &pmic_mpp_pinmux_ops; 872 pctrldesc->confops = &pmic_mpp_pinconf_ops; 873 pctrldesc->owner = THIS_MODULE; 874 pctrldesc->name = dev_name(dev); 875 pctrldesc->pins = pindesc; 876 pctrldesc->npins = npins; 877 878 pctrldesc->num_custom_params = ARRAY_SIZE(pmic_mpp_bindings); 879 pctrldesc->custom_params = pmic_mpp_bindings; 880 #ifdef CONFIG_DEBUG_FS 881 pctrldesc->custom_conf_items = pmic_conf_items; 882 #endif 883 884 for (i = 0; i < npins; i++, pindesc++) { 885 pad = &pads[i]; 886 pindesc->drv_data = pad; 887 pindesc->number = i; 888 pindesc->name = pmic_mpp_groups[i]; 889 890 pad->base = reg + i * PMIC_MPP_ADDRESS_RANGE; 891 892 ret = pmic_mpp_populate(state, pad); 893 if (ret < 0) 894 return ret; 895 } 896 897 state->chip = pmic_mpp_gpio_template; 898 state->chip.parent = dev; 899 state->chip.base = -1; 900 state->chip.ngpio = npins; 901 state->chip.label = dev_name(dev); 902 state->chip.of_gpio_n_cells = 2; 903 state->chip.can_sleep = false; 904 905 state->ctrl = devm_pinctrl_register(dev, pctrldesc, state); 906 if (IS_ERR(state->ctrl)) 907 return PTR_ERR(state->ctrl); 908 909 parent_node = of_irq_find_parent(state->dev->of_node); 910 if (!parent_node) 911 return -ENXIO; 912 913 parent_domain = irq_find_host(parent_node); 914 of_node_put(parent_node); 915 if (!parent_domain) 916 return -ENXIO; 917 918 state->irq.name = "spmi-mpp", 919 state->irq.irq_ack = irq_chip_ack_parent, 920 state->irq.irq_mask = irq_chip_mask_parent, 921 state->irq.irq_unmask = irq_chip_unmask_parent, 922 state->irq.irq_set_type = irq_chip_set_type_parent, 923 state->irq.irq_set_wake = irq_chip_set_wake_parent, 924 state->irq.flags = IRQCHIP_MASK_ON_SUSPEND, 925 926 girq = &state->chip.irq; 927 girq->chip = &state->irq; 928 girq->default_type = IRQ_TYPE_NONE; 929 girq->handler = handle_level_irq; 930 girq->fwnode = dev_fwnode(state->dev); 931 girq->parent_domain = parent_domain; 932 girq->child_to_parent_hwirq = pmic_mpp_child_to_parent_hwirq; 933 girq->populate_parent_alloc_arg = gpiochip_populate_parent_fwspec_fourcell; 934 girq->child_offset_to_irq = pmic_mpp_child_offset_to_irq; 935 girq->child_irq_domain_ops.translate = pmic_mpp_domain_translate; 936 937 ret = gpiochip_add_data(&state->chip, state); 938 if (ret) { 939 dev_err(state->dev, "can't add gpio chip\n"); 940 return ret; 941 } 942 943 ret = gpiochip_add_pin_range(&state->chip, dev_name(dev), 0, 0, npins); 944 if (ret) { 945 dev_err(dev, "failed to add pin range\n"); 946 goto err_range; 947 } 948 949 return 0; 950 951 err_range: 952 gpiochip_remove(&state->chip); 953 return ret; 954 } 955 956 static int pmic_mpp_remove(struct platform_device *pdev) 957 { 958 struct pmic_mpp_state *state = platform_get_drvdata(pdev); 959 960 gpiochip_remove(&state->chip); 961 return 0; 962 } 963 964 static const struct of_device_id pmic_mpp_of_match[] = { 965 { .compatible = "qcom,pm8019-mpp", .data = (void *) 6 }, 966 { .compatible = "qcom,pm8226-mpp", .data = (void *) 8 }, 967 { .compatible = "qcom,pm8841-mpp", .data = (void *) 4 }, 968 { .compatible = "qcom,pm8916-mpp", .data = (void *) 4 }, 969 { .compatible = "qcom,pm8941-mpp", .data = (void *) 8 }, 970 { .compatible = "qcom,pm8950-mpp", .data = (void *) 4 }, 971 { .compatible = "qcom,pmi8950-mpp", .data = (void *) 4 }, 972 { .compatible = "qcom,pm8994-mpp", .data = (void *) 8 }, 973 { .compatible = "qcom,pma8084-mpp", .data = (void *) 8 }, 974 { .compatible = "qcom,pmi8994-mpp", .data = (void *) 4 }, 975 { }, 976 }; 977 978 MODULE_DEVICE_TABLE(of, pmic_mpp_of_match); 979 980 static struct platform_driver pmic_mpp_driver = { 981 .driver = { 982 .name = "qcom-spmi-mpp", 983 .of_match_table = pmic_mpp_of_match, 984 }, 985 .probe = pmic_mpp_probe, 986 .remove = pmic_mpp_remove, 987 }; 988 989 module_platform_driver(pmic_mpp_driver); 990 991 MODULE_AUTHOR("Ivan T. Ivanov <iivanov@mm-sol.com>"); 992 MODULE_DESCRIPTION("Qualcomm SPMI PMIC MPP pin control driver"); 993 MODULE_ALIAS("platform:qcom-spmi-mpp"); 994 MODULE_LICENSE("GPL v2"); 995