1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2021, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. 5 * Copyright (c) 2022, Linaro Limited 6 */ 7 8 #include <linux/module.h> 9 #include <linux/of.h> 10 #include <linux/platform_device.h> 11 #include <linux/pinctrl/pinctrl.h> 12 13 #include "pinctrl-msm.h" 14 15 #define FUNCTION(fname) \ 16 [msm_mux_##fname] = { \ 17 .name = #fname, \ 18 .groups = fname##_groups, \ 19 .ngroups = ARRAY_SIZE(fname##_groups), \ 20 } 21 22 #define REG_SIZE 0x1000 23 24 #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ 25 { \ 26 .name = "gpio" #id, \ 27 .pins = gpio##id##_pins, \ 28 .npins = (unsigned int)ARRAY_SIZE(gpio##id##_pins), \ 29 .funcs = (int[]){ \ 30 msm_mux_gpio, /* gpio mode */ \ 31 msm_mux_##f1, \ 32 msm_mux_##f2, \ 33 msm_mux_##f3, \ 34 msm_mux_##f4, \ 35 msm_mux_##f5, \ 36 msm_mux_##f6, \ 37 msm_mux_##f7, \ 38 msm_mux_##f8, \ 39 msm_mux_##f9 \ 40 }, \ 41 .nfuncs = 10, \ 42 .ctl_reg = REG_SIZE * id, \ 43 .io_reg = 0x4 + REG_SIZE * id, \ 44 .intr_cfg_reg = 0x8 + REG_SIZE * id, \ 45 .intr_status_reg = 0xc + REG_SIZE * id, \ 46 .intr_target_reg = 0x8 + REG_SIZE * id, \ 47 .mux_bit = 2, \ 48 .pull_bit = 0, \ 49 .drv_bit = 6, \ 50 .i2c_pull_bit = 13, \ 51 .egpio_enable = 12, \ 52 .egpio_present = 11, \ 53 .oe_bit = 9, \ 54 .in_bit = 0, \ 55 .out_bit = 1, \ 56 .intr_enable_bit = 0, \ 57 .intr_status_bit = 0, \ 58 .intr_target_bit = 5, \ 59 .intr_target_kpss_val = 3, \ 60 .intr_raw_status_bit = 4, \ 61 .intr_polarity_bit = 1, \ 62 .intr_detection_bit = 2, \ 63 .intr_detection_width = 2, \ 64 } 65 66 #define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \ 67 { \ 68 .name = #pg_name, \ 69 .pins = pg_name##_pins, \ 70 .npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \ 71 .ctl_reg = ctl, \ 72 .io_reg = 0, \ 73 .intr_cfg_reg = 0, \ 74 .intr_status_reg = 0, \ 75 .intr_target_reg = 0, \ 76 .mux_bit = -1, \ 77 .pull_bit = pull, \ 78 .drv_bit = drv, \ 79 .oe_bit = -1, \ 80 .in_bit = -1, \ 81 .out_bit = -1, \ 82 .intr_enable_bit = -1, \ 83 .intr_status_bit = -1, \ 84 .intr_target_bit = -1, \ 85 .intr_raw_status_bit = -1, \ 86 .intr_polarity_bit = -1, \ 87 .intr_detection_bit = -1, \ 88 .intr_detection_width = -1, \ 89 } 90 91 #define UFS_RESET(pg_name, offset) \ 92 { \ 93 .name = #pg_name, \ 94 .pins = pg_name##_pins, \ 95 .npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \ 96 .ctl_reg = offset, \ 97 .io_reg = offset + 0x4, \ 98 .intr_cfg_reg = 0, \ 99 .intr_status_reg = 0, \ 100 .intr_target_reg = 0, \ 101 .mux_bit = -1, \ 102 .pull_bit = 3, \ 103 .drv_bit = 0, \ 104 .oe_bit = -1, \ 105 .in_bit = -1, \ 106 .out_bit = 0, \ 107 .intr_enable_bit = -1, \ 108 .intr_status_bit = -1, \ 109 .intr_target_bit = -1, \ 110 .intr_raw_status_bit = -1, \ 111 .intr_polarity_bit = -1, \ 112 .intr_detection_bit = -1, \ 113 .intr_detection_width = -1, \ 114 } 115 116 static const struct pinctrl_pin_desc sm8550_pins[] = { 117 PINCTRL_PIN(0, "GPIO_0"), 118 PINCTRL_PIN(1, "GPIO_1"), 119 PINCTRL_PIN(2, "GPIO_2"), 120 PINCTRL_PIN(3, "GPIO_3"), 121 PINCTRL_PIN(4, "GPIO_4"), 122 PINCTRL_PIN(5, "GPIO_5"), 123 PINCTRL_PIN(6, "GPIO_6"), 124 PINCTRL_PIN(7, "GPIO_7"), 125 PINCTRL_PIN(8, "GPIO_8"), 126 PINCTRL_PIN(9, "GPIO_9"), 127 PINCTRL_PIN(10, "GPIO_10"), 128 PINCTRL_PIN(11, "GPIO_11"), 129 PINCTRL_PIN(12, "GPIO_12"), 130 PINCTRL_PIN(13, "GPIO_13"), 131 PINCTRL_PIN(14, "GPIO_14"), 132 PINCTRL_PIN(15, "GPIO_15"), 133 PINCTRL_PIN(16, "GPIO_16"), 134 PINCTRL_PIN(17, "GPIO_17"), 135 PINCTRL_PIN(18, "GPIO_18"), 136 PINCTRL_PIN(19, "GPIO_19"), 137 PINCTRL_PIN(20, "GPIO_20"), 138 PINCTRL_PIN(21, "GPIO_21"), 139 PINCTRL_PIN(22, "GPIO_22"), 140 PINCTRL_PIN(23, "GPIO_23"), 141 PINCTRL_PIN(24, "GPIO_24"), 142 PINCTRL_PIN(25, "GPIO_25"), 143 PINCTRL_PIN(26, "GPIO_26"), 144 PINCTRL_PIN(27, "GPIO_27"), 145 PINCTRL_PIN(28, "GPIO_28"), 146 PINCTRL_PIN(29, "GPIO_29"), 147 PINCTRL_PIN(30, "GPIO_30"), 148 PINCTRL_PIN(31, "GPIO_31"), 149 PINCTRL_PIN(32, "GPIO_32"), 150 PINCTRL_PIN(33, "GPIO_33"), 151 PINCTRL_PIN(34, "GPIO_34"), 152 PINCTRL_PIN(35, "GPIO_35"), 153 PINCTRL_PIN(36, "GPIO_36"), 154 PINCTRL_PIN(37, "GPIO_37"), 155 PINCTRL_PIN(38, "GPIO_38"), 156 PINCTRL_PIN(39, "GPIO_39"), 157 PINCTRL_PIN(40, "GPIO_40"), 158 PINCTRL_PIN(41, "GPIO_41"), 159 PINCTRL_PIN(42, "GPIO_42"), 160 PINCTRL_PIN(43, "GPIO_43"), 161 PINCTRL_PIN(44, "GPIO_44"), 162 PINCTRL_PIN(45, "GPIO_45"), 163 PINCTRL_PIN(46, "GPIO_46"), 164 PINCTRL_PIN(47, "GPIO_47"), 165 PINCTRL_PIN(48, "GPIO_48"), 166 PINCTRL_PIN(49, "GPIO_49"), 167 PINCTRL_PIN(50, "GPIO_50"), 168 PINCTRL_PIN(51, "GPIO_51"), 169 PINCTRL_PIN(52, "GPIO_52"), 170 PINCTRL_PIN(53, "GPIO_53"), 171 PINCTRL_PIN(54, "GPIO_54"), 172 PINCTRL_PIN(55, "GPIO_55"), 173 PINCTRL_PIN(56, "GPIO_56"), 174 PINCTRL_PIN(57, "GPIO_57"), 175 PINCTRL_PIN(58, "GPIO_58"), 176 PINCTRL_PIN(59, "GPIO_59"), 177 PINCTRL_PIN(60, "GPIO_60"), 178 PINCTRL_PIN(61, "GPIO_61"), 179 PINCTRL_PIN(62, "GPIO_62"), 180 PINCTRL_PIN(63, "GPIO_63"), 181 PINCTRL_PIN(64, "GPIO_64"), 182 PINCTRL_PIN(65, "GPIO_65"), 183 PINCTRL_PIN(66, "GPIO_66"), 184 PINCTRL_PIN(67, "GPIO_67"), 185 PINCTRL_PIN(68, "GPIO_68"), 186 PINCTRL_PIN(69, "GPIO_69"), 187 PINCTRL_PIN(70, "GPIO_70"), 188 PINCTRL_PIN(71, "GPIO_71"), 189 PINCTRL_PIN(72, "GPIO_72"), 190 PINCTRL_PIN(73, "GPIO_73"), 191 PINCTRL_PIN(74, "GPIO_74"), 192 PINCTRL_PIN(75, "GPIO_75"), 193 PINCTRL_PIN(76, "GPIO_76"), 194 PINCTRL_PIN(77, "GPIO_77"), 195 PINCTRL_PIN(78, "GPIO_78"), 196 PINCTRL_PIN(79, "GPIO_79"), 197 PINCTRL_PIN(80, "GPIO_80"), 198 PINCTRL_PIN(81, "GPIO_81"), 199 PINCTRL_PIN(82, "GPIO_82"), 200 PINCTRL_PIN(83, "GPIO_83"), 201 PINCTRL_PIN(84, "GPIO_84"), 202 PINCTRL_PIN(85, "GPIO_85"), 203 PINCTRL_PIN(86, "GPIO_86"), 204 PINCTRL_PIN(87, "GPIO_87"), 205 PINCTRL_PIN(88, "GPIO_88"), 206 PINCTRL_PIN(89, "GPIO_89"), 207 PINCTRL_PIN(90, "GPIO_90"), 208 PINCTRL_PIN(91, "GPIO_91"), 209 PINCTRL_PIN(92, "GPIO_92"), 210 PINCTRL_PIN(93, "GPIO_93"), 211 PINCTRL_PIN(94, "GPIO_94"), 212 PINCTRL_PIN(95, "GPIO_95"), 213 PINCTRL_PIN(96, "GPIO_96"), 214 PINCTRL_PIN(97, "GPIO_97"), 215 PINCTRL_PIN(98, "GPIO_98"), 216 PINCTRL_PIN(99, "GPIO_99"), 217 PINCTRL_PIN(100, "GPIO_100"), 218 PINCTRL_PIN(101, "GPIO_101"), 219 PINCTRL_PIN(102, "GPIO_102"), 220 PINCTRL_PIN(103, "GPIO_103"), 221 PINCTRL_PIN(104, "GPIO_104"), 222 PINCTRL_PIN(105, "GPIO_105"), 223 PINCTRL_PIN(106, "GPIO_106"), 224 PINCTRL_PIN(107, "GPIO_107"), 225 PINCTRL_PIN(108, "GPIO_108"), 226 PINCTRL_PIN(109, "GPIO_109"), 227 PINCTRL_PIN(110, "GPIO_110"), 228 PINCTRL_PIN(111, "GPIO_111"), 229 PINCTRL_PIN(112, "GPIO_112"), 230 PINCTRL_PIN(113, "GPIO_113"), 231 PINCTRL_PIN(114, "GPIO_114"), 232 PINCTRL_PIN(115, "GPIO_115"), 233 PINCTRL_PIN(116, "GPIO_116"), 234 PINCTRL_PIN(117, "GPIO_117"), 235 PINCTRL_PIN(118, "GPIO_118"), 236 PINCTRL_PIN(119, "GPIO_119"), 237 PINCTRL_PIN(120, "GPIO_120"), 238 PINCTRL_PIN(121, "GPIO_121"), 239 PINCTRL_PIN(122, "GPIO_122"), 240 PINCTRL_PIN(123, "GPIO_123"), 241 PINCTRL_PIN(124, "GPIO_124"), 242 PINCTRL_PIN(125, "GPIO_125"), 243 PINCTRL_PIN(126, "GPIO_126"), 244 PINCTRL_PIN(127, "GPIO_127"), 245 PINCTRL_PIN(128, "GPIO_128"), 246 PINCTRL_PIN(129, "GPIO_129"), 247 PINCTRL_PIN(130, "GPIO_130"), 248 PINCTRL_PIN(131, "GPIO_131"), 249 PINCTRL_PIN(132, "GPIO_132"), 250 PINCTRL_PIN(133, "GPIO_133"), 251 PINCTRL_PIN(134, "GPIO_134"), 252 PINCTRL_PIN(135, "GPIO_135"), 253 PINCTRL_PIN(136, "GPIO_136"), 254 PINCTRL_PIN(137, "GPIO_137"), 255 PINCTRL_PIN(138, "GPIO_138"), 256 PINCTRL_PIN(139, "GPIO_139"), 257 PINCTRL_PIN(140, "GPIO_140"), 258 PINCTRL_PIN(141, "GPIO_141"), 259 PINCTRL_PIN(142, "GPIO_142"), 260 PINCTRL_PIN(143, "GPIO_143"), 261 PINCTRL_PIN(144, "GPIO_144"), 262 PINCTRL_PIN(145, "GPIO_145"), 263 PINCTRL_PIN(146, "GPIO_146"), 264 PINCTRL_PIN(147, "GPIO_147"), 265 PINCTRL_PIN(148, "GPIO_148"), 266 PINCTRL_PIN(149, "GPIO_149"), 267 PINCTRL_PIN(150, "GPIO_150"), 268 PINCTRL_PIN(151, "GPIO_151"), 269 PINCTRL_PIN(152, "GPIO_152"), 270 PINCTRL_PIN(153, "GPIO_153"), 271 PINCTRL_PIN(154, "GPIO_154"), 272 PINCTRL_PIN(155, "GPIO_155"), 273 PINCTRL_PIN(156, "GPIO_156"), 274 PINCTRL_PIN(157, "GPIO_157"), 275 PINCTRL_PIN(158, "GPIO_158"), 276 PINCTRL_PIN(159, "GPIO_159"), 277 PINCTRL_PIN(160, "GPIO_160"), 278 PINCTRL_PIN(161, "GPIO_161"), 279 PINCTRL_PIN(162, "GPIO_162"), 280 PINCTRL_PIN(163, "GPIO_163"), 281 PINCTRL_PIN(164, "GPIO_164"), 282 PINCTRL_PIN(165, "GPIO_165"), 283 PINCTRL_PIN(166, "GPIO_166"), 284 PINCTRL_PIN(167, "GPIO_167"), 285 PINCTRL_PIN(168, "GPIO_168"), 286 PINCTRL_PIN(169, "GPIO_169"), 287 PINCTRL_PIN(170, "GPIO_170"), 288 PINCTRL_PIN(171, "GPIO_171"), 289 PINCTRL_PIN(172, "GPIO_172"), 290 PINCTRL_PIN(173, "GPIO_173"), 291 PINCTRL_PIN(174, "GPIO_174"), 292 PINCTRL_PIN(175, "GPIO_175"), 293 PINCTRL_PIN(176, "GPIO_176"), 294 PINCTRL_PIN(177, "GPIO_177"), 295 PINCTRL_PIN(178, "GPIO_178"), 296 PINCTRL_PIN(179, "GPIO_179"), 297 PINCTRL_PIN(180, "GPIO_180"), 298 PINCTRL_PIN(181, "GPIO_181"), 299 PINCTRL_PIN(182, "GPIO_182"), 300 PINCTRL_PIN(183, "GPIO_183"), 301 PINCTRL_PIN(184, "GPIO_184"), 302 PINCTRL_PIN(185, "GPIO_185"), 303 PINCTRL_PIN(186, "GPIO_186"), 304 PINCTRL_PIN(187, "GPIO_187"), 305 PINCTRL_PIN(188, "GPIO_188"), 306 PINCTRL_PIN(189, "GPIO_189"), 307 PINCTRL_PIN(190, "GPIO_190"), 308 PINCTRL_PIN(191, "GPIO_191"), 309 PINCTRL_PIN(192, "GPIO_192"), 310 PINCTRL_PIN(193, "GPIO_193"), 311 PINCTRL_PIN(194, "GPIO_194"), 312 PINCTRL_PIN(195, "GPIO_195"), 313 PINCTRL_PIN(196, "GPIO_196"), 314 PINCTRL_PIN(197, "GPIO_197"), 315 PINCTRL_PIN(198, "GPIO_198"), 316 PINCTRL_PIN(199, "GPIO_199"), 317 PINCTRL_PIN(200, "GPIO_200"), 318 PINCTRL_PIN(201, "GPIO_201"), 319 PINCTRL_PIN(202, "GPIO_202"), 320 PINCTRL_PIN(203, "GPIO_203"), 321 PINCTRL_PIN(204, "GPIO_204"), 322 PINCTRL_PIN(205, "GPIO_205"), 323 PINCTRL_PIN(206, "GPIO_206"), 324 PINCTRL_PIN(207, "GPIO_207"), 325 PINCTRL_PIN(208, "GPIO_208"), 326 PINCTRL_PIN(209, "GPIO_209"), 327 PINCTRL_PIN(210, "UFS_RESET"), 328 PINCTRL_PIN(211, "SDC2_CLK"), 329 PINCTRL_PIN(212, "SDC2_CMD"), 330 PINCTRL_PIN(213, "SDC2_DATA"), 331 }; 332 333 #define DECLARE_MSM_GPIO_PINS(pin) \ 334 static const unsigned int gpio##pin##_pins[] = { pin } 335 DECLARE_MSM_GPIO_PINS(0); 336 DECLARE_MSM_GPIO_PINS(1); 337 DECLARE_MSM_GPIO_PINS(2); 338 DECLARE_MSM_GPIO_PINS(3); 339 DECLARE_MSM_GPIO_PINS(4); 340 DECLARE_MSM_GPIO_PINS(5); 341 DECLARE_MSM_GPIO_PINS(6); 342 DECLARE_MSM_GPIO_PINS(7); 343 DECLARE_MSM_GPIO_PINS(8); 344 DECLARE_MSM_GPIO_PINS(9); 345 DECLARE_MSM_GPIO_PINS(10); 346 DECLARE_MSM_GPIO_PINS(11); 347 DECLARE_MSM_GPIO_PINS(12); 348 DECLARE_MSM_GPIO_PINS(13); 349 DECLARE_MSM_GPIO_PINS(14); 350 DECLARE_MSM_GPIO_PINS(15); 351 DECLARE_MSM_GPIO_PINS(16); 352 DECLARE_MSM_GPIO_PINS(17); 353 DECLARE_MSM_GPIO_PINS(18); 354 DECLARE_MSM_GPIO_PINS(19); 355 DECLARE_MSM_GPIO_PINS(20); 356 DECLARE_MSM_GPIO_PINS(21); 357 DECLARE_MSM_GPIO_PINS(22); 358 DECLARE_MSM_GPIO_PINS(23); 359 DECLARE_MSM_GPIO_PINS(24); 360 DECLARE_MSM_GPIO_PINS(25); 361 DECLARE_MSM_GPIO_PINS(26); 362 DECLARE_MSM_GPIO_PINS(27); 363 DECLARE_MSM_GPIO_PINS(28); 364 DECLARE_MSM_GPIO_PINS(29); 365 DECLARE_MSM_GPIO_PINS(30); 366 DECLARE_MSM_GPIO_PINS(31); 367 DECLARE_MSM_GPIO_PINS(32); 368 DECLARE_MSM_GPIO_PINS(33); 369 DECLARE_MSM_GPIO_PINS(34); 370 DECLARE_MSM_GPIO_PINS(35); 371 DECLARE_MSM_GPIO_PINS(36); 372 DECLARE_MSM_GPIO_PINS(37); 373 DECLARE_MSM_GPIO_PINS(38); 374 DECLARE_MSM_GPIO_PINS(39); 375 DECLARE_MSM_GPIO_PINS(40); 376 DECLARE_MSM_GPIO_PINS(41); 377 DECLARE_MSM_GPIO_PINS(42); 378 DECLARE_MSM_GPIO_PINS(43); 379 DECLARE_MSM_GPIO_PINS(44); 380 DECLARE_MSM_GPIO_PINS(45); 381 DECLARE_MSM_GPIO_PINS(46); 382 DECLARE_MSM_GPIO_PINS(47); 383 DECLARE_MSM_GPIO_PINS(48); 384 DECLARE_MSM_GPIO_PINS(49); 385 DECLARE_MSM_GPIO_PINS(50); 386 DECLARE_MSM_GPIO_PINS(51); 387 DECLARE_MSM_GPIO_PINS(52); 388 DECLARE_MSM_GPIO_PINS(53); 389 DECLARE_MSM_GPIO_PINS(54); 390 DECLARE_MSM_GPIO_PINS(55); 391 DECLARE_MSM_GPIO_PINS(56); 392 DECLARE_MSM_GPIO_PINS(57); 393 DECLARE_MSM_GPIO_PINS(58); 394 DECLARE_MSM_GPIO_PINS(59); 395 DECLARE_MSM_GPIO_PINS(60); 396 DECLARE_MSM_GPIO_PINS(61); 397 DECLARE_MSM_GPIO_PINS(62); 398 DECLARE_MSM_GPIO_PINS(63); 399 DECLARE_MSM_GPIO_PINS(64); 400 DECLARE_MSM_GPIO_PINS(65); 401 DECLARE_MSM_GPIO_PINS(66); 402 DECLARE_MSM_GPIO_PINS(67); 403 DECLARE_MSM_GPIO_PINS(68); 404 DECLARE_MSM_GPIO_PINS(69); 405 DECLARE_MSM_GPIO_PINS(70); 406 DECLARE_MSM_GPIO_PINS(71); 407 DECLARE_MSM_GPIO_PINS(72); 408 DECLARE_MSM_GPIO_PINS(73); 409 DECLARE_MSM_GPIO_PINS(74); 410 DECLARE_MSM_GPIO_PINS(75); 411 DECLARE_MSM_GPIO_PINS(76); 412 DECLARE_MSM_GPIO_PINS(77); 413 DECLARE_MSM_GPIO_PINS(78); 414 DECLARE_MSM_GPIO_PINS(79); 415 DECLARE_MSM_GPIO_PINS(80); 416 DECLARE_MSM_GPIO_PINS(81); 417 DECLARE_MSM_GPIO_PINS(82); 418 DECLARE_MSM_GPIO_PINS(83); 419 DECLARE_MSM_GPIO_PINS(84); 420 DECLARE_MSM_GPIO_PINS(85); 421 DECLARE_MSM_GPIO_PINS(86); 422 DECLARE_MSM_GPIO_PINS(87); 423 DECLARE_MSM_GPIO_PINS(88); 424 DECLARE_MSM_GPIO_PINS(89); 425 DECLARE_MSM_GPIO_PINS(90); 426 DECLARE_MSM_GPIO_PINS(91); 427 DECLARE_MSM_GPIO_PINS(92); 428 DECLARE_MSM_GPIO_PINS(93); 429 DECLARE_MSM_GPIO_PINS(94); 430 DECLARE_MSM_GPIO_PINS(95); 431 DECLARE_MSM_GPIO_PINS(96); 432 DECLARE_MSM_GPIO_PINS(97); 433 DECLARE_MSM_GPIO_PINS(98); 434 DECLARE_MSM_GPIO_PINS(99); 435 DECLARE_MSM_GPIO_PINS(100); 436 DECLARE_MSM_GPIO_PINS(101); 437 DECLARE_MSM_GPIO_PINS(102); 438 DECLARE_MSM_GPIO_PINS(103); 439 DECLARE_MSM_GPIO_PINS(104); 440 DECLARE_MSM_GPIO_PINS(105); 441 DECLARE_MSM_GPIO_PINS(106); 442 DECLARE_MSM_GPIO_PINS(107); 443 DECLARE_MSM_GPIO_PINS(108); 444 DECLARE_MSM_GPIO_PINS(109); 445 DECLARE_MSM_GPIO_PINS(110); 446 DECLARE_MSM_GPIO_PINS(111); 447 DECLARE_MSM_GPIO_PINS(112); 448 DECLARE_MSM_GPIO_PINS(113); 449 DECLARE_MSM_GPIO_PINS(114); 450 DECLARE_MSM_GPIO_PINS(115); 451 DECLARE_MSM_GPIO_PINS(116); 452 DECLARE_MSM_GPIO_PINS(117); 453 DECLARE_MSM_GPIO_PINS(118); 454 DECLARE_MSM_GPIO_PINS(119); 455 DECLARE_MSM_GPIO_PINS(120); 456 DECLARE_MSM_GPIO_PINS(121); 457 DECLARE_MSM_GPIO_PINS(122); 458 DECLARE_MSM_GPIO_PINS(123); 459 DECLARE_MSM_GPIO_PINS(124); 460 DECLARE_MSM_GPIO_PINS(125); 461 DECLARE_MSM_GPIO_PINS(126); 462 DECLARE_MSM_GPIO_PINS(127); 463 DECLARE_MSM_GPIO_PINS(128); 464 DECLARE_MSM_GPIO_PINS(129); 465 DECLARE_MSM_GPIO_PINS(130); 466 DECLARE_MSM_GPIO_PINS(131); 467 DECLARE_MSM_GPIO_PINS(132); 468 DECLARE_MSM_GPIO_PINS(133); 469 DECLARE_MSM_GPIO_PINS(134); 470 DECLARE_MSM_GPIO_PINS(135); 471 DECLARE_MSM_GPIO_PINS(136); 472 DECLARE_MSM_GPIO_PINS(137); 473 DECLARE_MSM_GPIO_PINS(138); 474 DECLARE_MSM_GPIO_PINS(139); 475 DECLARE_MSM_GPIO_PINS(140); 476 DECLARE_MSM_GPIO_PINS(141); 477 DECLARE_MSM_GPIO_PINS(142); 478 DECLARE_MSM_GPIO_PINS(143); 479 DECLARE_MSM_GPIO_PINS(144); 480 DECLARE_MSM_GPIO_PINS(145); 481 DECLARE_MSM_GPIO_PINS(146); 482 DECLARE_MSM_GPIO_PINS(147); 483 DECLARE_MSM_GPIO_PINS(148); 484 DECLARE_MSM_GPIO_PINS(149); 485 DECLARE_MSM_GPIO_PINS(150); 486 DECLARE_MSM_GPIO_PINS(151); 487 DECLARE_MSM_GPIO_PINS(152); 488 DECLARE_MSM_GPIO_PINS(153); 489 DECLARE_MSM_GPIO_PINS(154); 490 DECLARE_MSM_GPIO_PINS(155); 491 DECLARE_MSM_GPIO_PINS(156); 492 DECLARE_MSM_GPIO_PINS(157); 493 DECLARE_MSM_GPIO_PINS(158); 494 DECLARE_MSM_GPIO_PINS(159); 495 DECLARE_MSM_GPIO_PINS(160); 496 DECLARE_MSM_GPIO_PINS(161); 497 DECLARE_MSM_GPIO_PINS(162); 498 DECLARE_MSM_GPIO_PINS(163); 499 DECLARE_MSM_GPIO_PINS(164); 500 DECLARE_MSM_GPIO_PINS(165); 501 DECLARE_MSM_GPIO_PINS(166); 502 DECLARE_MSM_GPIO_PINS(167); 503 DECLARE_MSM_GPIO_PINS(168); 504 DECLARE_MSM_GPIO_PINS(169); 505 DECLARE_MSM_GPIO_PINS(170); 506 DECLARE_MSM_GPIO_PINS(171); 507 DECLARE_MSM_GPIO_PINS(172); 508 DECLARE_MSM_GPIO_PINS(173); 509 DECLARE_MSM_GPIO_PINS(174); 510 DECLARE_MSM_GPIO_PINS(175); 511 DECLARE_MSM_GPIO_PINS(176); 512 DECLARE_MSM_GPIO_PINS(177); 513 DECLARE_MSM_GPIO_PINS(178); 514 DECLARE_MSM_GPIO_PINS(179); 515 DECLARE_MSM_GPIO_PINS(180); 516 DECLARE_MSM_GPIO_PINS(181); 517 DECLARE_MSM_GPIO_PINS(182); 518 DECLARE_MSM_GPIO_PINS(183); 519 DECLARE_MSM_GPIO_PINS(184); 520 DECLARE_MSM_GPIO_PINS(185); 521 DECLARE_MSM_GPIO_PINS(186); 522 DECLARE_MSM_GPIO_PINS(187); 523 DECLARE_MSM_GPIO_PINS(188); 524 DECLARE_MSM_GPIO_PINS(189); 525 DECLARE_MSM_GPIO_PINS(190); 526 DECLARE_MSM_GPIO_PINS(191); 527 DECLARE_MSM_GPIO_PINS(192); 528 DECLARE_MSM_GPIO_PINS(193); 529 DECLARE_MSM_GPIO_PINS(194); 530 DECLARE_MSM_GPIO_PINS(195); 531 DECLARE_MSM_GPIO_PINS(196); 532 DECLARE_MSM_GPIO_PINS(197); 533 DECLARE_MSM_GPIO_PINS(198); 534 DECLARE_MSM_GPIO_PINS(199); 535 DECLARE_MSM_GPIO_PINS(200); 536 DECLARE_MSM_GPIO_PINS(201); 537 DECLARE_MSM_GPIO_PINS(202); 538 DECLARE_MSM_GPIO_PINS(203); 539 DECLARE_MSM_GPIO_PINS(204); 540 DECLARE_MSM_GPIO_PINS(205); 541 DECLARE_MSM_GPIO_PINS(206); 542 DECLARE_MSM_GPIO_PINS(207); 543 DECLARE_MSM_GPIO_PINS(208); 544 DECLARE_MSM_GPIO_PINS(209); 545 546 static const unsigned int ufs_reset_pins[] = { 210 }; 547 static const unsigned int sdc2_clk_pins[] = { 211 }; 548 static const unsigned int sdc2_cmd_pins[] = { 212 }; 549 static const unsigned int sdc2_data_pins[] = { 213 }; 550 551 enum sm8550_functions { 552 msm_mux_gpio, 553 msm_mux_aon_cci, 554 msm_mux_aoss_cti, 555 msm_mux_atest_char, 556 msm_mux_atest_usb, 557 msm_mux_audio_ext_mclk0, 558 msm_mux_audio_ext_mclk1, 559 msm_mux_audio_ref_clk, 560 msm_mux_cam_aon_mclk4, 561 msm_mux_cam_mclk, 562 msm_mux_cci_async_in, 563 msm_mux_cci_i2c_scl, 564 msm_mux_cci_i2c_sda, 565 msm_mux_cci_timer, 566 msm_mux_cmu_rng, 567 msm_mux_coex_uart1_rx, 568 msm_mux_coex_uart1_tx, 569 msm_mux_coex_uart2_rx, 570 msm_mux_coex_uart2_tx, 571 msm_mux_cri_trng, 572 msm_mux_dbg_out_clk, 573 msm_mux_ddr_bist_complete, 574 msm_mux_ddr_bist_fail, 575 msm_mux_ddr_bist_start, 576 msm_mux_ddr_bist_stop, 577 msm_mux_ddr_pxi0, 578 msm_mux_ddr_pxi1, 579 msm_mux_ddr_pxi2, 580 msm_mux_ddr_pxi3, 581 msm_mux_dp_hot, 582 msm_mux_gcc_gp1, 583 msm_mux_gcc_gp2, 584 msm_mux_gcc_gp3, 585 msm_mux_i2chub0_se0, 586 msm_mux_i2chub0_se1, 587 msm_mux_i2chub0_se2, 588 msm_mux_i2chub0_se3, 589 msm_mux_i2chub0_se4, 590 msm_mux_i2chub0_se5, 591 msm_mux_i2chub0_se6, 592 msm_mux_i2chub0_se7, 593 msm_mux_i2chub0_se8, 594 msm_mux_i2chub0_se9, 595 msm_mux_i2s0_data0, 596 msm_mux_i2s0_data1, 597 msm_mux_i2s0_sck, 598 msm_mux_i2s0_ws, 599 msm_mux_i2s1_data0, 600 msm_mux_i2s1_data1, 601 msm_mux_i2s1_sck, 602 msm_mux_i2s1_ws, 603 msm_mux_ibi_i3c, 604 msm_mux_jitter_bist, 605 msm_mux_mdp_vsync, 606 msm_mux_mdp_vsync0_out, 607 msm_mux_mdp_vsync1_out, 608 msm_mux_mdp_vsync2_out, 609 msm_mux_mdp_vsync3_out, 610 msm_mux_mdp_vsync_e, 611 msm_mux_nav_gpio0, 612 msm_mux_nav_gpio1, 613 msm_mux_nav_gpio2, 614 msm_mux_pcie0_clk_req_n, 615 msm_mux_pcie1_clk_req_n, 616 msm_mux_phase_flag, 617 msm_mux_pll_bist_sync, 618 msm_mux_pll_clk_aux, 619 msm_mux_prng_rosc0, 620 msm_mux_prng_rosc1, 621 msm_mux_prng_rosc2, 622 msm_mux_prng_rosc3, 623 msm_mux_qdss_cti, 624 msm_mux_qdss_gpio, 625 msm_mux_qlink0_enable, 626 msm_mux_qlink0_request, 627 msm_mux_qlink0_wmss, 628 msm_mux_qlink1_enable, 629 msm_mux_qlink1_request, 630 msm_mux_qlink1_wmss, 631 msm_mux_qlink2_enable, 632 msm_mux_qlink2_request, 633 msm_mux_qlink2_wmss, 634 msm_mux_qspi0, 635 msm_mux_qspi1, 636 msm_mux_qspi2, 637 msm_mux_qspi3, 638 msm_mux_qspi_clk, 639 msm_mux_qspi_cs, 640 msm_mux_qup1_se0, 641 msm_mux_qup1_se1, 642 msm_mux_qup1_se2, 643 msm_mux_qup1_se3, 644 msm_mux_qup1_se4, 645 msm_mux_qup1_se5, 646 msm_mux_qup1_se6, 647 msm_mux_qup1_se7, 648 msm_mux_qup2_se0, 649 msm_mux_qup2_se0_l0_mira, 650 msm_mux_qup2_se0_l0_mirb, 651 msm_mux_qup2_se0_l1_mira, 652 msm_mux_qup2_se0_l1_mirb, 653 msm_mux_qup2_se0_l2_mira, 654 msm_mux_qup2_se0_l2_mirb, 655 msm_mux_qup2_se0_l3_mira, 656 msm_mux_qup2_se0_l3_mirb, 657 msm_mux_qup2_se1, 658 msm_mux_qup2_se2, 659 msm_mux_qup2_se3, 660 msm_mux_qup2_se4, 661 msm_mux_qup2_se5, 662 msm_mux_qup2_se6, 663 msm_mux_qup2_se7, 664 msm_mux_resout_n, 665 msm_mux_sd_write_protect, 666 msm_mux_sdc40, 667 msm_mux_sdc41, 668 msm_mux_sdc42, 669 msm_mux_sdc43, 670 msm_mux_sdc4_clk, 671 msm_mux_sdc4_cmd, 672 msm_mux_tb_trig_sdc2, 673 msm_mux_tb_trig_sdc4, 674 msm_mux_tgu_ch0_trigout, 675 msm_mux_tgu_ch1_trigout, 676 msm_mux_tgu_ch2_trigout, 677 msm_mux_tgu_ch3_trigout, 678 msm_mux_tmess_prng0, 679 msm_mux_tmess_prng1, 680 msm_mux_tmess_prng2, 681 msm_mux_tmess_prng3, 682 msm_mux_tsense_pwm1, 683 msm_mux_tsense_pwm2, 684 msm_mux_tsense_pwm3, 685 msm_mux_uim0_clk, 686 msm_mux_uim0_data, 687 msm_mux_uim0_present, 688 msm_mux_uim0_reset, 689 msm_mux_uim1_clk, 690 msm_mux_uim1_data, 691 msm_mux_uim1_present, 692 msm_mux_uim1_reset, 693 msm_mux_usb1_hs, 694 msm_mux_usb_phy, 695 msm_mux_vfr_0, 696 msm_mux_vfr_1, 697 msm_mux_vsense_trigger_mirnat, 698 msm_mux__, 699 }; 700 701 static const char * const gpio_groups[] = { 702 "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", 703 "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", 704 "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", 705 "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", 706 "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", 707 "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", 708 "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", 709 "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", 710 "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", 711 "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", 712 "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", 713 "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", 714 "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", 715 "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", 716 "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", 717 "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", 718 "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116", 719 "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122", 720 "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128", 721 "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134", 722 "gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140", 723 "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146", 724 "gpio147", "gpio148", "gpio149", "gpio150", "gpio151", "gpio152", 725 "gpio153", "gpio154", "gpio155", "gpio156", "gpio157", "gpio158", 726 "gpio159", "gpio160", "gpio161", "gpio162", "gpio163", "gpio164", 727 "gpio165", "gpio166", "gpio167", "gpio168", "gpio169", "gpio170", 728 "gpio171", "gpio172", "gpio173", "gpio174", "gpio175", "gpio176", 729 "gpio177", "gpio178", "gpio179", "gpio180", "gpio181", "gpio182", 730 "gpio183", "gpio184", "gpio185", "gpio186", "gpio187", "gpio188", 731 "gpio189", "gpio190", "gpio191", "gpio192", "gpio193", "gpio194", 732 "gpio195", "gpio196", "gpio197", "gpio198", "gpio199", "gpio200", 733 "gpio201", "gpio202", "gpio203", "gpio204", "gpio205", "gpio206", 734 "gpio207", "gpio208", "gpio209", 735 }; 736 737 static const char * const aon_cci_groups[] = { 738 "gpio208", "gpio209", 739 }; 740 741 static const char * const aoss_cti_groups[] = { 742 "gpio44", "gpio45", "gpio46", "gpio47", 743 }; 744 745 static const char *const atest_char_groups[] = { 746 "gpio130", "gpio132", "gpio133", "gpio134", "gpio135", 747 }; 748 749 static const char *const atest_usb_groups[] = { 750 "gpio37", "gpio39", "gpio55", "gpio149", "gpio148", 751 }; 752 753 static const char *const audio_ext_mclk0_groups[] = { 754 "gpio125", 755 }; 756 757 static const char *const audio_ext_mclk1_groups[] = { 758 "gpio124", 759 }; 760 761 static const char *const audio_ref_clk_groups[] = { 762 "gpio124", 763 }; 764 765 static const char *const cam_aon_mclk4_groups[] = { 766 "gpio104", 767 }; 768 769 static const char *const cam_mclk_groups[] = { 770 "gpio100", "gpio101", "gpio102", "gpio103", 771 "gpio105", "gpio106", "gpio107", 772 }; 773 774 static const char *const cci_async_in_groups[] = { 775 "gpio71", "gpio72", "gpio109", 776 }; 777 778 static const char *const cci_i2c_scl_groups[] = { 779 "gpio111", "gpio113", "gpio115", "gpio75", "gpio1", 780 }; 781 782 static const char *const cci_i2c_sda_groups[] = { 783 "gpio110", "gpio112", "gpio114", "gpio74", "gpio0", 784 }; 785 786 static const char *const cci_timer_groups[] = { 787 "gpio116", "gpio117", "gpio118", "gpio119", "gpio120", 788 }; 789 790 static const char *const cmu_rng_groups[] = { 791 "gpio129", "gpio128", "gpio127", "gpio122", 792 }; 793 794 static const char *const coex_uart1_rx_groups[] = { 795 "gpio148", 796 }; 797 798 static const char *const coex_uart1_tx_groups[] = { 799 "gpio149", 800 }; 801 802 static const char *const coex_uart2_rx_groups[] = { 803 "gpio150", 804 }; 805 806 static const char *const coex_uart2_tx_groups[] = { 807 "gpio151", 808 }; 809 810 static const char *const cri_trng_groups[] = { 811 "gpio187", 812 }; 813 814 static const char *const dbg_out_clk_groups[] = { 815 "gpio89", 816 }; 817 818 static const char *const ddr_bist_complete_groups[] = { 819 "gpio40", 820 }; 821 822 static const char *const ddr_bist_fail_groups[] = { 823 "gpio36", 824 }; 825 826 static const char *const ddr_bist_start_groups[] = { 827 "gpio37", 828 }; 829 830 static const char *const ddr_bist_stop_groups[] = { 831 "gpio41", 832 }; 833 834 static const char *const ddr_pxi0_groups[] = { 835 "gpio51", 836 "gpio52", 837 }; 838 839 static const char *const ddr_pxi1_groups[] = { 840 "gpio40", 841 "gpio41", 842 }; 843 844 static const char *const ddr_pxi2_groups[] = { 845 "gpio45", 846 "gpio47", 847 }; 848 849 static const char *const ddr_pxi3_groups[] = { 850 "gpio43", 851 "gpio44", 852 }; 853 854 static const char *const dp_hot_groups[] = { 855 "gpio47", 856 }; 857 858 static const char *const gcc_gp1_groups[] = { 859 "gpio86", 860 "gpio134", 861 }; 862 863 static const char *const gcc_gp2_groups[] = { 864 "gpio87", 865 "gpio135", 866 }; 867 868 static const char *const gcc_gp3_groups[] = { 869 "gpio88", 870 "gpio136", 871 }; 872 873 static const char *const i2chub0_se0_groups[] = { 874 "gpio16", 875 "gpio17", 876 }; 877 878 static const char *const i2chub0_se1_groups[] = { 879 "gpio18", 880 "gpio19", 881 }; 882 883 static const char *const i2chub0_se2_groups[] = { 884 "gpio20", 885 "gpio21", 886 }; 887 888 static const char *const i2chub0_se3_groups[] = { 889 "gpio22", 890 "gpio23", 891 }; 892 893 static const char *const i2chub0_se4_groups[] = { 894 "gpio4", 895 "gpio5", 896 }; 897 898 static const char *const i2chub0_se5_groups[] = { 899 "gpio6", 900 "gpio7", 901 }; 902 903 static const char *const i2chub0_se6_groups[] = { 904 "gpio8", 905 "gpio9", 906 }; 907 908 static const char *const i2chub0_se7_groups[] = { 909 "gpio10", 910 "gpio11", 911 }; 912 913 static const char *const i2chub0_se8_groups[] = { 914 "gpio206", 915 "gpio207", 916 }; 917 918 static const char *const i2chub0_se9_groups[] = { 919 "gpio84", 920 "gpio85", 921 }; 922 923 static const char *const i2s0_data0_groups[] = { 924 "gpio127", 925 }; 926 927 static const char *const i2s0_data1_groups[] = { 928 "gpio128", 929 }; 930 931 static const char *const i2s0_sck_groups[] = { 932 "gpio126", 933 }; 934 935 static const char *const i2s0_ws_groups[] = { 936 "gpio129", 937 }; 938 939 static const char *const i2s1_data0_groups[] = { 940 "gpio122", 941 }; 942 943 static const char *const i2s1_data1_groups[] = { 944 "gpio124", 945 }; 946 947 static const char *const i2s1_sck_groups[] = { 948 "gpio121", 949 }; 950 951 static const char *const i2s1_ws_groups[] = { 952 "gpio123", 953 }; 954 955 static const char *const ibi_i3c_groups[] = { 956 "gpio0", "gpio1", "gpio28", "gpio29", "gpio32", 957 "gpio33", "gpio56", "gpio57", "gpio60", "gpio61", 958 }; 959 960 static const char *const jitter_bist_groups[] = { 961 "gpio43", 962 }; 963 964 static const char *const mdp_vsync_groups[] = { 965 "gpio86", 966 "gpio87", 967 "gpio133", 968 "gpio137", 969 }; 970 971 static const char *const mdp_vsync0_out_groups[] = { 972 "gpio86", 973 }; 974 975 static const char *const mdp_vsync1_out_groups[] = { 976 "gpio86", 977 }; 978 979 static const char *const mdp_vsync2_out_groups[] = { 980 "gpio87", 981 }; 982 983 static const char *const mdp_vsync3_out_groups[] = { 984 "gpio87", 985 }; 986 987 static const char *const mdp_vsync_e_groups[] = { 988 "gpio88", 989 }; 990 991 static const char *const nav_gpio0_groups[] = { 992 "gpio154", 993 }; 994 995 static const char *const nav_gpio1_groups[] = { 996 "gpio155", 997 }; 998 999 static const char *const nav_gpio2_groups[] = { 1000 "gpio153", 1001 }; 1002 1003 static const char *const pcie0_clk_req_n_groups[] = { 1004 "gpio95", 1005 }; 1006 1007 static const char *const pcie1_clk_req_n_groups[] = { 1008 "gpio98", 1009 }; 1010 1011 static const char *const phase_flag_groups[] = { 1012 "gpio0", "gpio2", "gpio3", "gpio10", "gpio11", "gpio12", "gpio13", "gpio59", 1013 "gpio63", "gpio64", "gpio65", "gpio67", "gpio68", "gpio69", "gpio75", "gpio76", 1014 "gpio77", "gpio79", "gpio80", "gpio81", "gpio92", "gpio83", "gpio94", "gpio95", 1015 "gpio96", "gpio97", "gpio98", "gpio99", "gpio116", "gpio117", "gpio119", "gpio120", 1016 }; 1017 1018 static const char *const pll_bist_sync_groups[] = { 1019 "gpio20", 1020 }; 1021 1022 static const char *const pll_clk_aux_groups[] = { 1023 "gpio107", 1024 }; 1025 1026 static const char *const prng_rosc0_groups[] = { 1027 "gpio186", 1028 }; 1029 1030 static const char *const prng_rosc1_groups[] = { 1031 "gpio183", 1032 }; 1033 1034 static const char *const prng_rosc2_groups[] = { 1035 "gpio182", 1036 }; 1037 1038 static const char *const prng_rosc3_groups[] = { 1039 "gpio181", 1040 }; 1041 1042 static const char *const qdss_cti_groups[] = { 1043 "gpio10", "gpio11", "gpio75", "gpio79", 1044 "gpio159", "gpio160", "gpio161", "gpio162", 1045 }; 1046 1047 static const char *const qdss_gpio_groups[] = { 1048 "gpio59", "gpio64", "gpio73", "gpio100", "gpio101", "gpio102", "gpio103", 1049 "gpio104", "gpio105", "gpio110", "gpio111", "gpio112", "gpio113", "gpio114", 1050 "gpio115", "gpio116", "gpio117", "gpio120", "gpio138", "gpio139", "gpio140", 1051 "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio148", "gpio149", 1052 "gpio150", "gpio151", "gpio152", "gpio153", "gpio154", "gpio155", "gpio156", 1053 "gpio157", 1054 }; 1055 1056 static const char *const qlink0_enable_groups[] = { 1057 "gpio157", 1058 }; 1059 1060 static const char *const qlink0_request_groups[] = { 1061 "gpio156", 1062 }; 1063 1064 static const char *const qlink0_wmss_groups[] = { 1065 "gpio158", 1066 }; 1067 1068 static const char *const qlink1_enable_groups[] = { 1069 "gpio160", 1070 }; 1071 1072 static const char *const qlink1_request_groups[] = { 1073 "gpio159", 1074 }; 1075 1076 static const char *const qlink1_wmss_groups[] = { 1077 "gpio161", 1078 }; 1079 1080 static const char *const qlink2_enable_groups[] = { 1081 "gpio163", 1082 }; 1083 1084 static const char *const qlink2_request_groups[] = { 1085 "gpio162", 1086 }; 1087 1088 static const char *const qlink2_wmss_groups[] = { 1089 "gpio164", 1090 }; 1091 1092 static const char *const qspi0_groups[] = { 1093 "gpio89", 1094 }; 1095 1096 static const char *const qspi1_groups[] = { 1097 "gpio90", 1098 }; 1099 1100 static const char *const qspi2_groups[] = { 1101 "gpio48", 1102 }; 1103 1104 static const char *const qspi3_groups[] = { 1105 "gpio49", 1106 }; 1107 1108 static const char *const qspi_clk_groups[] = { 1109 "gpio50", 1110 }; 1111 1112 static const char *const qspi_cs_groups[] = { 1113 "gpio51", "gpio91", 1114 }; 1115 1116 static const char *const qup1_se0_groups[] = { 1117 "gpio28", "gpio29", "gpio30", "gpio31", 1118 }; 1119 1120 static const char *const qup1_se1_groups[] = { 1121 "gpio32", "gpio33", "gpio34", "gpio35", 1122 }; 1123 1124 static const char *const qup1_se2_groups[] = { 1125 "gpio40", "gpio41", "gpio42", "gpio36", 1126 "gpio37", "gpio38", "gpio39", 1127 }; 1128 1129 static const char *const qup1_se3_groups[] = { 1130 "gpio40", "gpio41", "gpio42", "gpio43", 1131 }; 1132 1133 static const char *const qup1_se4_groups[] = { 1134 "gpio44", "gpio45", "gpio46", "gpio47", 1135 }; 1136 1137 static const char *const qup1_se5_groups[] = { 1138 "gpio52", "gpio53", "gpio54", "gpio55", 1139 }; 1140 1141 static const char *const qup1_se6_groups[] = { 1142 "gpio48", "gpio49", "gpio50", "gpio51", 1143 }; 1144 1145 static const char *const qup1_se7_groups[] = { 1146 "gpio24", "gpio25", "gpio26", "gpio27", 1147 }; 1148 1149 static const char *const qup2_se0_groups[] = { 1150 "gpio63", "gpio66", "gpio67", 1151 }; 1152 1153 static const char *const qup2_se0_l0_mira_groups[] = { 1154 "gpio56", 1155 }; 1156 1157 static const char *const qup2_se0_l0_mirb_groups[] = { 1158 "gpio0", 1159 }; 1160 1161 static const char *const qup2_se0_l1_mira_groups[] = { 1162 "gpio57", 1163 }; 1164 1165 static const char *const qup2_se0_l1_mirb_groups[] = { 1166 "gpio1", 1167 }; 1168 1169 static const char *const qup2_se0_l2_mira_groups[] = { 1170 "gpio58", 1171 }; 1172 1173 static const char *const qup2_se0_l2_mirb_groups[] = { 1174 "gpio109", 1175 }; 1176 1177 static const char *const qup2_se0_l3_mira_groups[] = { 1178 "gpio59", 1179 }; 1180 1181 static const char *const qup2_se0_l3_mirb_groups[] = { 1182 "gpio107", 1183 }; 1184 1185 static const char *const qup2_se1_groups[] = { 1186 "gpio60", "gpio61", "gpio62", "gpio63", 1187 }; 1188 1189 static const char *const qup2_se2_groups[] = { 1190 "gpio64", "gpio65", "gpio66", "gpio67", 1191 }; 1192 1193 static const char *const qup2_se3_groups[] = { 1194 "gpio68", "gpio69", "gpio70", "gpio71", 1195 }; 1196 1197 static const char *const qup2_se4_groups[] = { 1198 "gpio2", "gpio3", "gpio118", "gpio119", 1199 }; 1200 1201 static const char *const qup2_se5_groups[] = { 1202 "gpio80", "gpio81", "gpio82", "gpio83", 1203 }; 1204 1205 static const char *const qup2_se6_groups[] = { 1206 "gpio76", "gpio77", "gpio78", "gpio79", 1207 }; 1208 1209 static const char *const qup2_se7_groups[] = { 1210 "gpio72", "gpio106", "gpio74", "gpio75", 1211 }; 1212 1213 static const char * const resout_n_groups[] = { 1214 "gpio92", 1215 }; 1216 1217 static const char *const sd_write_protect_groups[] = { 1218 "gpio93", 1219 }; 1220 1221 static const char *const sdc40_groups[] = { 1222 "gpio89", 1223 }; 1224 1225 static const char *const sdc41_groups[] = { 1226 "gpio90", 1227 }; 1228 1229 static const char *const sdc42_groups[] = { 1230 "gpio48", 1231 }; 1232 1233 static const char *const sdc43_groups[] = { 1234 "gpio49", 1235 }; 1236 1237 static const char *const sdc4_clk_groups[] = { 1238 "gpio50", 1239 }; 1240 1241 static const char *const sdc4_cmd_groups[] = { 1242 "gpio51", 1243 }; 1244 1245 static const char * const tb_trig_sdc2_groups[] = { 1246 "gpio64", 1247 }; 1248 1249 static const char * const tb_trig_sdc4_groups[] = { 1250 "gpio91", 1251 }; 1252 1253 static const char * const tgu_ch0_trigout_groups[] = { 1254 "gpio64", 1255 }; 1256 1257 static const char * const tgu_ch1_trigout_groups[] = { 1258 "gpio65", 1259 }; 1260 1261 static const char * const tgu_ch2_trigout_groups[] = { 1262 "gpio66", 1263 }; 1264 1265 static const char * const tgu_ch3_trigout_groups[] = { 1266 "gpio67", 1267 }; 1268 1269 static const char *const tmess_prng0_groups[] = { 1270 "gpio92", 1271 }; 1272 1273 static const char *const tmess_prng1_groups[] = { 1274 "gpio94", 1275 }; 1276 1277 static const char *const tmess_prng2_groups[] = { 1278 "gpio95", 1279 }; 1280 1281 static const char *const tmess_prng3_groups[] = { 1282 "gpio96", 1283 }; 1284 1285 static const char *const tsense_pwm1_groups[] = { 1286 "gpio50", 1287 }; 1288 1289 static const char *const tsense_pwm2_groups[] = { 1290 "gpio50", 1291 }; 1292 1293 static const char *const tsense_pwm3_groups[] = { 1294 "gpio50", 1295 }; 1296 1297 static const char *const uim0_clk_groups[] = { 1298 "gpio131", 1299 }; 1300 1301 static const char *const uim0_data_groups[] = { 1302 "gpio130", 1303 }; 1304 1305 static const char *const uim0_present_groups[] = { 1306 "gpio27", 1307 }; 1308 1309 static const char *const uim0_reset_groups[] = { 1310 "gpio132", 1311 }; 1312 1313 static const char *const uim1_clk_groups[] = { 1314 "gpio135", 1315 }; 1316 1317 static const char *const uim1_data_groups[] = { 1318 "gpio134", 1319 }; 1320 1321 static const char *const uim1_present_groups[] = { 1322 "gpio26", 1323 }; 1324 1325 static const char *const uim1_reset_groups[] = { 1326 "gpio136", 1327 }; 1328 1329 static const char *const usb1_hs_groups[] = { 1330 "gpio90", 1331 }; 1332 1333 static const char *const usb_phy_groups[] = { 1334 "gpio11", 1335 "gpio48", 1336 }; 1337 1338 static const char *const vfr_0_groups[] = { 1339 "gpio150", 1340 }; 1341 1342 static const char *const vfr_1_groups[] = { 1343 "gpio155", 1344 }; 1345 1346 static const char *const vsense_trigger_mirnat_groups[] = { 1347 "gpio24", 1348 }; 1349 1350 static const struct msm_function sm8550_functions[] = { 1351 FUNCTION(gpio), 1352 FUNCTION(aon_cci), 1353 FUNCTION(aoss_cti), 1354 FUNCTION(atest_char), 1355 FUNCTION(atest_usb), 1356 FUNCTION(audio_ext_mclk0), 1357 FUNCTION(audio_ext_mclk1), 1358 FUNCTION(audio_ref_clk), 1359 FUNCTION(cam_aon_mclk4), 1360 FUNCTION(cam_mclk), 1361 FUNCTION(cci_async_in), 1362 FUNCTION(cci_i2c_scl), 1363 FUNCTION(cci_i2c_sda), 1364 FUNCTION(cci_timer), 1365 FUNCTION(cmu_rng), 1366 FUNCTION(coex_uart1_rx), 1367 FUNCTION(coex_uart1_tx), 1368 FUNCTION(coex_uart2_rx), 1369 FUNCTION(coex_uart2_tx), 1370 FUNCTION(cri_trng), 1371 FUNCTION(dbg_out_clk), 1372 FUNCTION(ddr_bist_complete), 1373 FUNCTION(ddr_bist_fail), 1374 FUNCTION(ddr_bist_start), 1375 FUNCTION(ddr_bist_stop), 1376 FUNCTION(ddr_pxi0), 1377 FUNCTION(ddr_pxi1), 1378 FUNCTION(ddr_pxi2), 1379 FUNCTION(ddr_pxi3), 1380 FUNCTION(dp_hot), 1381 FUNCTION(gcc_gp1), 1382 FUNCTION(gcc_gp2), 1383 FUNCTION(gcc_gp3), 1384 FUNCTION(i2chub0_se0), 1385 FUNCTION(i2chub0_se1), 1386 FUNCTION(i2chub0_se2), 1387 FUNCTION(i2chub0_se3), 1388 FUNCTION(i2chub0_se4), 1389 FUNCTION(i2chub0_se5), 1390 FUNCTION(i2chub0_se6), 1391 FUNCTION(i2chub0_se7), 1392 FUNCTION(i2chub0_se8), 1393 FUNCTION(i2chub0_se9), 1394 FUNCTION(i2s0_data0), 1395 FUNCTION(i2s0_data1), 1396 FUNCTION(i2s0_sck), 1397 FUNCTION(i2s0_ws), 1398 FUNCTION(i2s1_data0), 1399 FUNCTION(i2s1_data1), 1400 FUNCTION(i2s1_sck), 1401 FUNCTION(i2s1_ws), 1402 FUNCTION(ibi_i3c), 1403 FUNCTION(jitter_bist), 1404 FUNCTION(mdp_vsync), 1405 FUNCTION(mdp_vsync0_out), 1406 FUNCTION(mdp_vsync1_out), 1407 FUNCTION(mdp_vsync2_out), 1408 FUNCTION(mdp_vsync3_out), 1409 FUNCTION(mdp_vsync_e), 1410 FUNCTION(nav_gpio0), 1411 FUNCTION(nav_gpio1), 1412 FUNCTION(nav_gpio2), 1413 FUNCTION(pcie0_clk_req_n), 1414 FUNCTION(pcie1_clk_req_n), 1415 FUNCTION(phase_flag), 1416 FUNCTION(pll_bist_sync), 1417 FUNCTION(pll_clk_aux), 1418 FUNCTION(prng_rosc0), 1419 FUNCTION(prng_rosc1), 1420 FUNCTION(prng_rosc2), 1421 FUNCTION(prng_rosc3), 1422 FUNCTION(qdss_cti), 1423 FUNCTION(qdss_gpio), 1424 FUNCTION(qlink0_enable), 1425 FUNCTION(qlink0_request), 1426 FUNCTION(qlink0_wmss), 1427 FUNCTION(qlink1_enable), 1428 FUNCTION(qlink1_request), 1429 FUNCTION(qlink1_wmss), 1430 FUNCTION(qlink2_enable), 1431 FUNCTION(qlink2_request), 1432 FUNCTION(qlink2_wmss), 1433 FUNCTION(qspi0), 1434 FUNCTION(qspi1), 1435 FUNCTION(qspi2), 1436 FUNCTION(qspi3), 1437 FUNCTION(qspi_clk), 1438 FUNCTION(qspi_cs), 1439 FUNCTION(qup1_se0), 1440 FUNCTION(qup1_se1), 1441 FUNCTION(qup1_se2), 1442 FUNCTION(qup1_se3), 1443 FUNCTION(qup1_se4), 1444 FUNCTION(qup1_se5), 1445 FUNCTION(qup1_se6), 1446 FUNCTION(qup1_se7), 1447 FUNCTION(qup2_se0), 1448 FUNCTION(qup2_se0_l0_mira), 1449 FUNCTION(qup2_se0_l0_mirb), 1450 FUNCTION(qup2_se0_l1_mira), 1451 FUNCTION(qup2_se0_l1_mirb), 1452 FUNCTION(qup2_se0_l2_mira), 1453 FUNCTION(qup2_se0_l2_mirb), 1454 FUNCTION(qup2_se0_l3_mira), 1455 FUNCTION(qup2_se0_l3_mirb), 1456 FUNCTION(qup2_se1), 1457 FUNCTION(qup2_se2), 1458 FUNCTION(qup2_se3), 1459 FUNCTION(qup2_se4), 1460 FUNCTION(qup2_se5), 1461 FUNCTION(qup2_se6), 1462 FUNCTION(qup2_se7), 1463 FUNCTION(resout_n), 1464 FUNCTION(sd_write_protect), 1465 FUNCTION(sdc40), 1466 FUNCTION(sdc41), 1467 FUNCTION(sdc42), 1468 FUNCTION(sdc43), 1469 FUNCTION(sdc4_clk), 1470 FUNCTION(sdc4_cmd), 1471 FUNCTION(tb_trig_sdc2), 1472 FUNCTION(tb_trig_sdc4), 1473 FUNCTION(tgu_ch0_trigout), 1474 FUNCTION(tgu_ch1_trigout), 1475 FUNCTION(tgu_ch2_trigout), 1476 FUNCTION(tgu_ch3_trigout), 1477 FUNCTION(tmess_prng0), 1478 FUNCTION(tmess_prng1), 1479 FUNCTION(tmess_prng2), 1480 FUNCTION(tmess_prng3), 1481 FUNCTION(tsense_pwm1), 1482 FUNCTION(tsense_pwm2), 1483 FUNCTION(tsense_pwm3), 1484 FUNCTION(uim0_clk), 1485 FUNCTION(uim0_data), 1486 FUNCTION(uim0_present), 1487 FUNCTION(uim0_reset), 1488 FUNCTION(uim1_clk), 1489 FUNCTION(uim1_data), 1490 FUNCTION(uim1_present), 1491 FUNCTION(uim1_reset), 1492 FUNCTION(usb1_hs), 1493 FUNCTION(usb_phy), 1494 FUNCTION(vfr_0), 1495 FUNCTION(vfr_1), 1496 FUNCTION(vsense_trigger_mirnat), 1497 }; 1498 1499 /* 1500 * Every pin is maintained as a single group, and missing or non-existing pin 1501 * would be maintained as dummy group to synchronize pin group index with 1502 * pin descriptor registered with pinctrl core. 1503 * Clients would not be able to request these dummy pin groups. 1504 */ 1505 static const struct msm_pingroup sm8550_groups[] = { 1506 [0] = PINGROUP(0, cci_i2c_sda, qup2_se0_l0_mirb, ibi_i3c, phase_flag, _, _, _, _, _), 1507 [1] = PINGROUP(1, cci_i2c_scl, qup2_se0_l1_mirb, ibi_i3c, _, _, _, _, _, _), 1508 [2] = PINGROUP(2, qup2_se4, phase_flag, _, _, _, _, _, _, _), 1509 [3] = PINGROUP(3, qup2_se4, phase_flag, _, _, _, _, _, _, _), 1510 [4] = PINGROUP(4, i2chub0_se4, _, _, _, _, _, _, _, _), 1511 [5] = PINGROUP(5, i2chub0_se4, _, _, _, _, _, _, _, _), 1512 [6] = PINGROUP(6, i2chub0_se5, _, _, _, _, _, _, _, _), 1513 [7] = PINGROUP(7, i2chub0_se5, _, _, _, _, _, _, _, _), 1514 [8] = PINGROUP(8, i2chub0_se6, _, _, _, _, _, _, _, _), 1515 [9] = PINGROUP(9, i2chub0_se6, _, _, _, _, _, _, _, _), 1516 [10] = PINGROUP(10, i2chub0_se7, qdss_cti, phase_flag, _, _, _, _, _, _), 1517 [11] = PINGROUP(11, i2chub0_se7, usb_phy, qdss_cti, phase_flag, _, _, _, _, _), 1518 [12] = PINGROUP(12, phase_flag, _, _, _, _, _, _, _, _), 1519 [13] = PINGROUP(13, phase_flag, _, _, _, _, _, _, _, _), 1520 [14] = PINGROUP(14, _, _, _, _, _, _, _, _, _), 1521 [15] = PINGROUP(15, _, _, _, _, _, _, _, _, _), 1522 [16] = PINGROUP(16, i2chub0_se0, _, _, _, _, _, _, _, _), 1523 [17] = PINGROUP(17, i2chub0_se0, _, _, _, _, _, _, _, _), 1524 [18] = PINGROUP(18, i2chub0_se1, _, _, _, _, _, _, _, _), 1525 [19] = PINGROUP(19, i2chub0_se1, _, _, _, _, _, _, _, _), 1526 [20] = PINGROUP(20, i2chub0_se2, pll_bist_sync, _, _, _, _, _, _, _), 1527 [21] = PINGROUP(21, i2chub0_se2, _, _, _, _, _, _, _, _), 1528 [22] = PINGROUP(22, i2chub0_se3, _, _, _, _, _, _, _, _), 1529 [23] = PINGROUP(23, i2chub0_se3, _, _, _, _, _, _, _, _), 1530 [24] = PINGROUP(24, qup1_se7, vsense_trigger_mirnat, _, _, _, _, _, _, _), 1531 [25] = PINGROUP(25, qup1_se7, _, _, _, _, _, _, _, _), 1532 [26] = PINGROUP(26, qup1_se7, uim1_present, _, _, _, _, _, _, _), 1533 [27] = PINGROUP(27, qup1_se7, uim0_present, _, _, _, _, _, _, _), 1534 [28] = PINGROUP(28, qup1_se0, ibi_i3c, _, _, _, _, _, _, _), 1535 [29] = PINGROUP(29, qup1_se0, ibi_i3c, _, _, _, _, _, _, _), 1536 [30] = PINGROUP(30, qup1_se0, _, _, _, _, _, _, _, _), 1537 [31] = PINGROUP(31, qup1_se0, _, _, _, _, _, _, _, _), 1538 [32] = PINGROUP(32, qup1_se1, ibi_i3c, _, _, _, _, _, _, _), 1539 [33] = PINGROUP(33, qup1_se1, ibi_i3c, _, _, _, _, _, _, _), 1540 [34] = PINGROUP(34, qup1_se1, _, _, _, _, _, _, _, _), 1541 [35] = PINGROUP(35, qup1_se1, _, _, _, _, _, _, _, _), 1542 [36] = PINGROUP(36, qup1_se2, ddr_bist_fail, _, _, _, _, _, _, _), 1543 [37] = PINGROUP(37, qup1_se2, ddr_bist_start, _, atest_usb, _, _, _, _, _), 1544 [38] = PINGROUP(38, qup1_se2, _, _, _, _, _, _, _, _), 1545 [39] = PINGROUP(39, qup1_se2, _, atest_usb, _, _, _, _, _, _), 1546 [40] = PINGROUP(40, qup1_se3, qup1_se2, ddr_bist_complete, _, ddr_pxi1, _, _, _, _), 1547 [41] = PINGROUP(41, qup1_se3, qup1_se2, ddr_bist_stop, _, ddr_pxi1, _, _, _, _), 1548 [42] = PINGROUP(42, qup1_se3, qup1_se2, _, _, _, _, _, _, _), 1549 [43] = PINGROUP(43, qup1_se3, jitter_bist, ddr_pxi3, _, _, _, _, _, _), 1550 [44] = PINGROUP(44, qup1_se4, aoss_cti, ddr_pxi3, _, _, _, _, _, _), 1551 [45] = PINGROUP(45, qup1_se4, aoss_cti, ddr_pxi2, _, _, _, _, _, _), 1552 [46] = PINGROUP(46, qup1_se4, aoss_cti, _, _, _, _, _, _, _), 1553 [47] = PINGROUP(47, qup1_se4, aoss_cti, dp_hot, ddr_pxi2, _, _, _, _, _), 1554 [48] = PINGROUP(48, usb_phy, qup1_se6, qspi2, sdc42, _, _, _, _, _), 1555 [49] = PINGROUP(49, qup1_se6, qspi3, sdc43, _, _, _, _, _, _), 1556 [50] = PINGROUP(50, qup1_se6, qspi_clk, sdc4_clk, tsense_pwm1, tsense_pwm2, tsense_pwm3, _, _, _), 1557 [51] = PINGROUP(51, qup1_se6, qspi_cs, sdc4_cmd, ddr_pxi0, _, _, _, _, _), 1558 [52] = PINGROUP(52, _, qup1_se5, ddr_pxi0, _, _, _, _, _, _), 1559 [53] = PINGROUP(53, _, qup1_se5, _, _, _, _, _, _, _), 1560 [54] = PINGROUP(54, _, qup1_se5, _, _, _, _, _, _, _), 1561 [55] = PINGROUP(55, qup1_se5, atest_usb, _, _, _, _, _, _, _), 1562 [56] = PINGROUP(56, qup2_se0_l0_mira, ibi_i3c, _, _, _, _, _, _, _), 1563 [57] = PINGROUP(57, qup2_se0_l1_mira, ibi_i3c, _, _, _, _, _, _, _), 1564 [58] = PINGROUP(58, qup2_se0_l2_mira, _, _, _, _, _, _, _, _), 1565 [59] = PINGROUP(59, qup2_se0_l3_mira, phase_flag, _, qdss_gpio, _, _, _, _, _), 1566 [60] = PINGROUP(60, qup2_se1, ibi_i3c, _, _, _, _, _, _, _), 1567 [61] = PINGROUP(61, qup2_se1, ibi_i3c, _, _, _, _, _, _, _), 1568 [62] = PINGROUP(62, qup2_se1, _, _, _, _, _, _, _, _), 1569 [63] = PINGROUP(63, qup2_se1, qup2_se0, phase_flag, _, _, _, _, _, _), 1570 [64] = PINGROUP(64, qup2_se2, tb_trig_sdc2, phase_flag, tgu_ch0_trigout, _, qdss_gpio, _, _, _), 1571 [65] = PINGROUP(65, qup2_se2, phase_flag, tgu_ch1_trigout, _, _, _, _, _, _), 1572 [66] = PINGROUP(66, qup2_se2, qup2_se0, tgu_ch2_trigout, _, _, _, _, _, _), 1573 [67] = PINGROUP(67, qup2_se2, qup2_se0, phase_flag, tgu_ch3_trigout, _, _, _, _, _), 1574 [68] = PINGROUP(68, qup2_se3, phase_flag, _, _, _, _, _, _, _), 1575 [69] = PINGROUP(69, qup2_se3, phase_flag, _, _, _, _, _, _, _), 1576 [70] = PINGROUP(70, qup2_se3, _, _, _, _, _, _, _, _), 1577 [71] = PINGROUP(71, cci_async_in, qup2_se3, _, _, _, _, _, _, _), 1578 [72] = PINGROUP(72, cci_async_in, qup2_se7, _, _, _, _, _, _, _), 1579 [73] = PINGROUP(73, qdss_gpio, _, _, _, _, _, _, _, _), 1580 [74] = PINGROUP(74, cci_i2c_sda, qup2_se7, _, _, _, _, _, _, _), 1581 [75] = PINGROUP(75, cci_i2c_scl, qup2_se7, qdss_cti, phase_flag, _, _, _, _, _), 1582 [76] = PINGROUP(76, qup2_se6, phase_flag, _, _, _, _, _, _, _), 1583 [77] = PINGROUP(77, qup2_se6, phase_flag, _, _, _, _, _, _, _), 1584 [78] = PINGROUP(78, qup2_se6, _, _, _, _, _, _, _, _), 1585 [79] = PINGROUP(79, qup2_se6, qdss_cti, phase_flag, _, _, _, _, _, _), 1586 [80] = PINGROUP(80, qup2_se5, phase_flag, _, _, _, _, _, _, _), 1587 [81] = PINGROUP(81, qup2_se5, phase_flag, _, _, _, _, _, _, _), 1588 [82] = PINGROUP(82, qup2_se5, _, _, _, _, _, _, _, _), 1589 [83] = PINGROUP(83, qup2_se5, phase_flag, _, _, _, _, _, _, _), 1590 [84] = PINGROUP(84, i2chub0_se9, _, _, _, _, _, _, _, _), 1591 [85] = PINGROUP(85, i2chub0_se9, _, _, _, _, _, _, _, _), 1592 [86] = PINGROUP(86, mdp_vsync, mdp_vsync0_out, mdp_vsync1_out, gcc_gp1, _, _, _, _, _), 1593 [87] = PINGROUP(87, mdp_vsync, mdp_vsync2_out, mdp_vsync3_out, gcc_gp2, _, _, _, _, _), 1594 [88] = PINGROUP(88, mdp_vsync_e, gcc_gp3, _, _, _, _, _, _, _), 1595 [89] = PINGROUP(89, qspi0, sdc40, dbg_out_clk, _, _, _, _, _, _), 1596 [90] = PINGROUP(90, usb1_hs, qspi1, sdc41, _, _, _, _, _, _), 1597 [91] = PINGROUP(91, qspi_cs, tb_trig_sdc4, _, _, _, _, _, _, _), 1598 [92] = PINGROUP(92, resout_n, phase_flag, tmess_prng0, _, _, _, _, _, _), 1599 [93] = PINGROUP(93, sd_write_protect, _, _, _, _, _, _, _, _), 1600 [94] = PINGROUP(94, phase_flag, tmess_prng1, _, _, _, _, _, _, _), 1601 [95] = PINGROUP(95, pcie0_clk_req_n, phase_flag, tmess_prng2, _, _, _, _, _, _), 1602 [96] = PINGROUP(96, phase_flag, tmess_prng3, _, _, _, _, _, _, _), 1603 [97] = PINGROUP(97, phase_flag, _, _, _, _, _, _, _, _), 1604 [98] = PINGROUP(98, pcie1_clk_req_n, phase_flag, _, _, _, _, _, _, _), 1605 [99] = PINGROUP(99, phase_flag, _, _, _, _, _, _, _, _), 1606 [100] = PINGROUP(100, cam_mclk, qdss_gpio, _, _, _, _, _, _, _), 1607 [101] = PINGROUP(101, cam_mclk, qdss_gpio, _, _, _, _, _, _, _), 1608 [102] = PINGROUP(102, cam_mclk, qdss_gpio, _, _, _, _, _, _, _), 1609 [103] = PINGROUP(103, cam_mclk, qdss_gpio, _, _, _, _, _, _, _), 1610 [104] = PINGROUP(104, cam_aon_mclk4, qdss_gpio, _, _, _, _, _, _, _), 1611 [105] = PINGROUP(105, cam_mclk, qdss_gpio, _, _, _, _, _, _, _), 1612 [106] = PINGROUP(106, cam_mclk, qup2_se7, _, _, _, _, _, _, _), 1613 [107] = PINGROUP(107, cam_mclk, qup2_se0_l3_mirb, pll_clk_aux, _, _, _, _, _, _), 1614 [108] = PINGROUP(108, _, _, _, _, _, _, _, _, _), 1615 [109] = PINGROUP(109, cci_async_in, qup2_se0_l2_mirb, _, _, _, _, _, _, _), 1616 [110] = PINGROUP(110, cci_i2c_sda, qdss_gpio, _, _, _, _, _, _, _), 1617 [111] = PINGROUP(111, cci_i2c_scl, qdss_gpio, _, _, _, _, _, _, _), 1618 [112] = PINGROUP(112, cci_i2c_sda, qdss_gpio, _, _, _, _, _, _, _), 1619 [113] = PINGROUP(113, cci_i2c_scl, qdss_gpio, _, _, _, _, _, _, _), 1620 [114] = PINGROUP(114, cci_i2c_sda, qdss_gpio, _, _, _, _, _, _, _), 1621 [115] = PINGROUP(115, cci_i2c_scl, qdss_gpio, _, _, _, _, _, _, _), 1622 [116] = PINGROUP(116, cci_timer, phase_flag, _, qdss_gpio, _, _, _, _, _), 1623 [117] = PINGROUP(117, cci_timer, phase_flag, _, qdss_gpio, _, _, _, _, _), 1624 [118] = PINGROUP(118, qup2_se4, cci_timer, _, _, _, _, _, _, _), 1625 [119] = PINGROUP(119, qup2_se4, cci_timer, phase_flag, _, _, _, _, _, _), 1626 [120] = PINGROUP(120, cci_timer, phase_flag, _, qdss_gpio, _, _, _, _, _), 1627 [121] = PINGROUP(121, i2s1_sck, _, _, _, _, _, _, _, _), 1628 [122] = PINGROUP(122, i2s1_data0, cmu_rng, _, _, _, _, _, _, _), 1629 [123] = PINGROUP(123, i2s1_ws, _, _, _, _, _, _, _, _), 1630 [124] = PINGROUP(124, i2s1_data1, audio_ext_mclk1, audio_ref_clk, _, _, _, _, _, _), 1631 [125] = PINGROUP(125, audio_ext_mclk0, _, _, _, _, _, _, _, _), 1632 [126] = PINGROUP(126, i2s0_sck, _, _, _, _, _, _, _, _), 1633 [127] = PINGROUP(127, i2s0_data0, cmu_rng, _, _, _, _, _, _, _), 1634 [128] = PINGROUP(128, i2s0_data1, cmu_rng, _, _, _, _, _, _, _), 1635 [129] = PINGROUP(129, i2s0_ws, cmu_rng, _, _, _, _, _, _, _), 1636 [130] = PINGROUP(130, uim0_data, atest_char, _, _, _, _, _, _, _), 1637 [131] = PINGROUP(131, uim0_clk, _, _, _, _, _, _, _, _), 1638 [132] = PINGROUP(132, uim0_reset, atest_char, _, _, _, _, _, _, _), 1639 [133] = PINGROUP(133, mdp_vsync, atest_char, _, _, _, _, _, _, _), 1640 [134] = PINGROUP(134, uim1_data, gcc_gp1, atest_char, _, _, _, _, _, _), 1641 [135] = PINGROUP(135, uim1_clk, gcc_gp2, atest_char, _, _, _, _, _, _), 1642 [136] = PINGROUP(136, uim1_reset, gcc_gp3, _, _, _, _, _, _, _), 1643 [137] = PINGROUP(137, mdp_vsync, _, _, _, _, _, _, _, _), 1644 [138] = PINGROUP(138, _, _, qdss_gpio, _, _, _, _, _, _), 1645 [139] = PINGROUP(139, _, _, qdss_gpio, _, _, _, _, _, _), 1646 [140] = PINGROUP(140, _, _, qdss_gpio, _, _, _, _, _, _), 1647 [141] = PINGROUP(141, _, _, qdss_gpio, _, _, _, _, _, _), 1648 [142] = PINGROUP(142, _, _, qdss_gpio, _, _, _, _, _, _), 1649 [143] = PINGROUP(143, _, _, qdss_gpio, _, _, _, _, _, _), 1650 [144] = PINGROUP(144, _, _, qdss_gpio, _, _, _, _, _, _), 1651 [145] = PINGROUP(145, _, _, qdss_gpio, _, _, _, _, _, _), 1652 [146] = PINGROUP(146, _, _, _, _, _, _, _, _, _), 1653 [147] = PINGROUP(147, _, _, _, _, _, _, _, _, _), 1654 [148] = PINGROUP(148, coex_uart1_rx, qdss_gpio, atest_usb, _, _, _, _, _, _), 1655 [149] = PINGROUP(149, coex_uart1_tx, qdss_gpio, atest_usb, _, _, _, _, _, _), 1656 [150] = PINGROUP(150, coex_uart2_rx, _, vfr_0, qdss_gpio, _, _, _, _, _), 1657 [151] = PINGROUP(151, coex_uart2_tx, _, qdss_gpio, _, _, _, _, _, _), 1658 [152] = PINGROUP(152, _, qdss_gpio, _, _, _, _, _, _, _), 1659 [153] = PINGROUP(153, _, nav_gpio2, qdss_gpio, _, _, _, _, _, _), 1660 [154] = PINGROUP(154, nav_gpio0, qdss_gpio, _, _, _, _, _, _, _), 1661 [155] = PINGROUP(155, nav_gpio1, vfr_1, qdss_gpio, _, _, _, _, _, _), 1662 [156] = PINGROUP(156, qlink0_request, qdss_gpio, _, _, _, _, _, _, _), 1663 [157] = PINGROUP(157, qlink0_enable, qdss_gpio, _, _, _, _, _, _, _), 1664 [158] = PINGROUP(158, qlink0_wmss, _, _, _, _, _, _, _, _), 1665 [159] = PINGROUP(159, qlink1_request, qdss_cti, _, _, _, _, _, _, _), 1666 [160] = PINGROUP(160, qlink1_enable, qdss_cti, _, _, _, _, _, _, _), 1667 [161] = PINGROUP(161, qlink1_wmss, qdss_cti, _, _, _, _, _, _, _), 1668 [162] = PINGROUP(162, qlink2_request, qdss_cti, _, _, _, _, _, _, _), 1669 [163] = PINGROUP(163, qlink2_enable, _, _, _, _, _, _, _, _), 1670 [164] = PINGROUP(164, qlink2_wmss, _, _, _, _, _, _, _, _), 1671 [165] = PINGROUP(165, _, _, _, _, _, _, _, _, _), 1672 [166] = PINGROUP(166, _, _, _, _, _, _, _, _, _), 1673 [167] = PINGROUP(167, _, _, _, _, _, _, _, _, _), 1674 [168] = PINGROUP(168, _, _, _, _, _, _, _, _, _), 1675 [169] = PINGROUP(169, _, _, _, _, _, _, _, _, _), 1676 [170] = PINGROUP(170, _, _, _, _, _, _, _, _, _), 1677 [171] = PINGROUP(171, _, _, _, _, _, _, _, _, _), 1678 [172] = PINGROUP(172, _, _, _, _, _, _, _, _, _), 1679 [173] = PINGROUP(173, _, _, _, _, _, _, _, _, _), 1680 [174] = PINGROUP(174, _, _, _, _, _, _, _, _, _), 1681 [175] = PINGROUP(175, _, _, _, _, _, _, _, _, _), 1682 [176] = PINGROUP(176, _, _, _, _, _, _, _, _, _), 1683 [177] = PINGROUP(177, _, _, _, _, _, _, _, _, _), 1684 [178] = PINGROUP(178, _, _, _, _, _, _, _, _, _), 1685 [179] = PINGROUP(179, _, _, _, _, _, _, _, _, _), 1686 [180] = PINGROUP(180, _, _, _, _, _, _, _, _, _), 1687 [181] = PINGROUP(181, prng_rosc3, _, _, _, _, _, _, _, _), 1688 [182] = PINGROUP(182, prng_rosc2, _, _, _, _, _, _, _, _), 1689 [183] = PINGROUP(183, prng_rosc1, _, _, _, _, _, _, _, _), 1690 [184] = PINGROUP(184, _, _, _, _, _, _, _, _, _), 1691 [185] = PINGROUP(185, _, _, _, _, _, _, _, _, _), 1692 [186] = PINGROUP(186, prng_rosc0, _, _, _, _, _, _, _, _), 1693 [187] = PINGROUP(187, cri_trng, _, _, _, _, _, _, _, _), 1694 [188] = PINGROUP(188, _, _, _, _, _, _, _, _, _), 1695 [189] = PINGROUP(189, _, _, _, _, _, _, _, _, _), 1696 [190] = PINGROUP(190, _, _, _, _, _, _, _, _, _), 1697 [191] = PINGROUP(191, _, _, _, _, _, _, _, _, _), 1698 [192] = PINGROUP(192, _, _, _, _, _, _, _, _, _), 1699 [193] = PINGROUP(193, _, _, _, _, _, _, _, _, _), 1700 [194] = PINGROUP(194, _, _, _, _, _, _, _, _, _), 1701 [195] = PINGROUP(195, _, _, _, _, _, _, _, _, _), 1702 [196] = PINGROUP(196, _, _, _, _, _, _, _, _, _), 1703 [197] = PINGROUP(197, _, _, _, _, _, _, _, _, _), 1704 [198] = PINGROUP(198, _, _, _, _, _, _, _, _, _), 1705 [199] = PINGROUP(199, _, _, _, _, _, _, _, _, _), 1706 [200] = PINGROUP(200, _, _, _, _, _, _, _, _, _), 1707 [201] = PINGROUP(201, _, _, _, _, _, _, _, _, _), 1708 [202] = PINGROUP(202, _, _, _, _, _, _, _, _, _), 1709 [203] = PINGROUP(203, _, _, _, _, _, _, _, _, _), 1710 [204] = PINGROUP(204, _, _, _, _, _, _, _, _, _), 1711 [205] = PINGROUP(205, _, _, _, _, _, _, _, _, _), 1712 [206] = PINGROUP(206, i2chub0_se8, _, _, _, _, _, _, _, _), 1713 [207] = PINGROUP(207, i2chub0_se8, _, _, _, _, _, _, _, _), 1714 [208] = PINGROUP(208, aon_cci, _, _, _, _, _, _, _, _), 1715 [209] = PINGROUP(209, aon_cci, _, _, _, _, _, _, _, _), 1716 [210] = UFS_RESET(ufs_reset, 0xde000), 1717 [211] = SDC_QDSD_PINGROUP(sdc2_clk, 0xd6000, 14, 6), 1718 [212] = SDC_QDSD_PINGROUP(sdc2_cmd, 0xd6000, 11, 3), 1719 [213] = SDC_QDSD_PINGROUP(sdc2_data, 0xd6000, 9, 0), 1720 }; 1721 1722 static const struct msm_gpio_wakeirq_map sm8550_pdc_map[] = { 1723 { 0, 118 }, { 2, 90 }, { 3, 101 }, { 8, 60 }, { 9, 67 }, 1724 { 11, 103 }, { 14, 136 }, { 15, 78 }, { 16, 138 }, { 17, 80 }, 1725 { 18, 71 }, { 19, 59 }, { 25, 57 }, { 26, 74 }, { 27, 76 }, 1726 { 28, 62 }, { 31, 88 }, { 32, 63 }, { 35, 124 }, { 39, 92 }, 1727 { 40, 77 }, { 41, 83 }, { 43, 86 }, { 44, 75 }, { 45, 93 }, 1728 { 46, 96 }, { 47, 64 }, { 48, 110 }, { 51, 89 }, { 55, 95 }, 1729 { 56, 68 }, { 59, 87 }, { 60, 65 }, { 62, 100 }, { 63, 81 }, 1730 { 67, 79 }, { 71, 102 }, { 73, 82 }, { 75, 72 }, { 79, 140 }, 1731 { 82, 105 }, { 83, 104 }, { 84, 126 }, { 85, 142 }, { 86, 106 }, 1732 { 87, 107 }, { 88, 61 }, { 89, 111 }, { 95, 108 }, { 96, 109 }, 1733 { 98, 97 }, { 99, 58 }, { 107, 139 }, { 119, 94 }, { 120, 135 }, 1734 { 133, 52 }, { 137, 84 }, { 148, 66 }, { 150, 73 }, { 153, 70 }, 1735 { 154, 53 }, { 155, 69 }, { 156, 54 }, { 159, 55 }, { 162, 56 }, 1736 { 166, 116 }, { 169, 119 }, { 171, 120 }, { 172, 85 }, { 174, 98 }, 1737 { 176, 112 }, { 177, 51 }, { 181, 114 }, { 182, 115 }, { 185, 117 }, 1738 { 187, 91 }, { 188, 123 }, { 190, 127 }, { 191, 113 }, { 192, 128 }, 1739 { 193, 129 }, { 196, 133 }, { 197, 134 }, { 198, 50 }, { 199, 99 }, 1740 { 200, 49 }, { 201, 48 }, { 203, 125 }, { 205, 141 }, { 206, 137 }, 1741 { 207, 47 }, { 208, 121 }, { 209, 122 }, 1742 }; 1743 1744 static const struct msm_pinctrl_soc_data sm8550_tlmm = { 1745 .pins = sm8550_pins, 1746 .npins = ARRAY_SIZE(sm8550_pins), 1747 .functions = sm8550_functions, 1748 .nfunctions = ARRAY_SIZE(sm8550_functions), 1749 .groups = sm8550_groups, 1750 .ngroups = ARRAY_SIZE(sm8550_groups), 1751 .ngpios = 211, 1752 .wakeirq_map = sm8550_pdc_map, 1753 .nwakeirq_map = ARRAY_SIZE(sm8550_pdc_map), 1754 .egpio_func = 9, 1755 }; 1756 1757 static int sm8550_tlmm_probe(struct platform_device *pdev) 1758 { 1759 return msm_pinctrl_probe(pdev, &sm8550_tlmm); 1760 } 1761 1762 static const struct of_device_id sm8550_tlmm_of_match[] = { 1763 { .compatible = "qcom,sm8550-tlmm", }, 1764 {}, 1765 }; 1766 1767 static struct platform_driver sm8550_tlmm_driver = { 1768 .driver = { 1769 .name = "sm8550-tlmm", 1770 .of_match_table = sm8550_tlmm_of_match, 1771 }, 1772 .probe = sm8550_tlmm_probe, 1773 .remove = msm_pinctrl_remove, 1774 }; 1775 1776 static int __init sm8550_tlmm_init(void) 1777 { 1778 return platform_driver_register(&sm8550_tlmm_driver); 1779 } 1780 arch_initcall(sm8550_tlmm_init); 1781 1782 static void __exit sm8550_tlmm_exit(void) 1783 { 1784 platform_driver_unregister(&sm8550_tlmm_driver); 1785 } 1786 module_exit(sm8550_tlmm_exit); 1787 1788 MODULE_DESCRIPTION("QTI SM8550 TLMM driver"); 1789 MODULE_LICENSE("GPL"); 1790 MODULE_DEVICE_TABLE(of, sm8550_tlmm_of_match); 1791