1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
4  * Copyright (c) 2021, Linaro Limited
5  */
6 
7 #include <linux/module.h>
8 #include <linux/of.h>
9 #include <linux/platform_device.h>
10 #include <linux/pinctrl/pinctrl.h>
11 
12 #include "pinctrl-msm.h"
13 
14 #define FUNCTION(fname)			                \
15 	[msm_mux_##fname] = {		                \
16 		.name = #fname,				\
17 		.groups = fname##_groups,               \
18 		.ngroups = ARRAY_SIZE(fname##_groups),	\
19 	}
20 
21 #define REG_SIZE 0x1000
22 
23 #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9)	\
24 	{					        \
25 		.name = "gpio" #id,			\
26 		.pins = gpio##id##_pins,		\
27 		.npins = (unsigned int)ARRAY_SIZE(gpio##id##_pins),	\
28 		.funcs = (int[]){			\
29 			msm_mux_gpio, /* gpio mode */	\
30 			msm_mux_##f1,			\
31 			msm_mux_##f2,			\
32 			msm_mux_##f3,			\
33 			msm_mux_##f4,			\
34 			msm_mux_##f5,			\
35 			msm_mux_##f6,			\
36 			msm_mux_##f7,			\
37 			msm_mux_##f8,			\
38 			msm_mux_##f9			\
39 		},				        \
40 		.nfuncs = 10,				\
41 		.ctl_reg = REG_SIZE * id,			\
42 		.io_reg = 0x4 + REG_SIZE * id,		\
43 		.intr_cfg_reg = 0x8 + REG_SIZE * id,		\
44 		.intr_status_reg = 0xc + REG_SIZE * id,	\
45 		.intr_target_reg = 0x8 + REG_SIZE * id,	\
46 		.mux_bit = 2,			\
47 		.pull_bit = 0,			\
48 		.drv_bit = 6,			\
49 		.oe_bit = 9,			\
50 		.in_bit = 0,			\
51 		.out_bit = 1,			\
52 		.intr_enable_bit = 0,		\
53 		.intr_status_bit = 0,		\
54 		.intr_target_bit = 5,		\
55 		.intr_target_kpss_val = 3,	\
56 		.intr_raw_status_bit = 4,	\
57 		.intr_polarity_bit = 1,		\
58 		.intr_detection_bit = 2,	\
59 		.intr_detection_width = 2,	\
60 	}
61 
62 #define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv)	\
63 	{					        \
64 		.name = #pg_name,			\
65 		.pins = pg_name##_pins,			\
66 		.npins = (unsigned int)ARRAY_SIZE(pg_name##_pins),	\
67 		.ctl_reg = ctl,				\
68 		.io_reg = 0,				\
69 		.intr_cfg_reg = 0,			\
70 		.intr_status_reg = 0,			\
71 		.intr_target_reg = 0,			\
72 		.mux_bit = -1,				\
73 		.pull_bit = pull,			\
74 		.drv_bit = drv,				\
75 		.oe_bit = -1,				\
76 		.in_bit = -1,				\
77 		.out_bit = -1,				\
78 		.intr_enable_bit = -1,			\
79 		.intr_status_bit = -1,			\
80 		.intr_target_bit = -1,			\
81 		.intr_raw_status_bit = -1,		\
82 		.intr_polarity_bit = -1,		\
83 		.intr_detection_bit = -1,		\
84 		.intr_detection_width = -1,		\
85 	}
86 
87 #define UFS_RESET(pg_name, offset)				\
88 	{					        \
89 		.name = #pg_name,			\
90 		.pins = pg_name##_pins,			\
91 		.npins = (unsigned int)ARRAY_SIZE(pg_name##_pins),	\
92 		.ctl_reg = offset,			\
93 		.io_reg = offset + 0x4,			\
94 		.intr_cfg_reg = 0,			\
95 		.intr_status_reg = 0,			\
96 		.intr_target_reg = 0,			\
97 		.mux_bit = -1,				\
98 		.pull_bit = 3,				\
99 		.drv_bit = 0,				\
100 		.oe_bit = -1,				\
101 		.in_bit = -1,				\
102 		.out_bit = 0,				\
103 		.intr_enable_bit = -1,			\
104 		.intr_status_bit = -1,			\
105 		.intr_target_bit = -1,			\
106 		.intr_raw_status_bit = -1,		\
107 		.intr_polarity_bit = -1,		\
108 		.intr_detection_bit = -1,		\
109 		.intr_detection_width = -1,		\
110 	}
111 
112 static const struct pinctrl_pin_desc sm8450_pins[] = {
113 	PINCTRL_PIN(0, "GPIO_0"),
114 	PINCTRL_PIN(1, "GPIO_1"),
115 	PINCTRL_PIN(2, "GPIO_2"),
116 	PINCTRL_PIN(3, "GPIO_3"),
117 	PINCTRL_PIN(4, "GPIO_4"),
118 	PINCTRL_PIN(5, "GPIO_5"),
119 	PINCTRL_PIN(6, "GPIO_6"),
120 	PINCTRL_PIN(7, "GPIO_7"),
121 	PINCTRL_PIN(8, "GPIO_8"),
122 	PINCTRL_PIN(9, "GPIO_9"),
123 	PINCTRL_PIN(10, "GPIO_10"),
124 	PINCTRL_PIN(11, "GPIO_11"),
125 	PINCTRL_PIN(12, "GPIO_12"),
126 	PINCTRL_PIN(13, "GPIO_13"),
127 	PINCTRL_PIN(14, "GPIO_14"),
128 	PINCTRL_PIN(15, "GPIO_15"),
129 	PINCTRL_PIN(16, "GPIO_16"),
130 	PINCTRL_PIN(17, "GPIO_17"),
131 	PINCTRL_PIN(18, "GPIO_18"),
132 	PINCTRL_PIN(19, "GPIO_19"),
133 	PINCTRL_PIN(20, "GPIO_20"),
134 	PINCTRL_PIN(21, "GPIO_21"),
135 	PINCTRL_PIN(22, "GPIO_22"),
136 	PINCTRL_PIN(23, "GPIO_23"),
137 	PINCTRL_PIN(24, "GPIO_24"),
138 	PINCTRL_PIN(25, "GPIO_25"),
139 	PINCTRL_PIN(26, "GPIO_26"),
140 	PINCTRL_PIN(27, "GPIO_27"),
141 	PINCTRL_PIN(28, "GPIO_28"),
142 	PINCTRL_PIN(29, "GPIO_29"),
143 	PINCTRL_PIN(30, "GPIO_30"),
144 	PINCTRL_PIN(31, "GPIO_31"),
145 	PINCTRL_PIN(32, "GPIO_32"),
146 	PINCTRL_PIN(33, "GPIO_33"),
147 	PINCTRL_PIN(34, "GPIO_34"),
148 	PINCTRL_PIN(35, "GPIO_35"),
149 	PINCTRL_PIN(36, "GPIO_36"),
150 	PINCTRL_PIN(37, "GPIO_37"),
151 	PINCTRL_PIN(38, "GPIO_38"),
152 	PINCTRL_PIN(39, "GPIO_39"),
153 	PINCTRL_PIN(40, "GPIO_40"),
154 	PINCTRL_PIN(41, "GPIO_41"),
155 	PINCTRL_PIN(42, "GPIO_42"),
156 	PINCTRL_PIN(43, "GPIO_43"),
157 	PINCTRL_PIN(44, "GPIO_44"),
158 	PINCTRL_PIN(45, "GPIO_45"),
159 	PINCTRL_PIN(46, "GPIO_46"),
160 	PINCTRL_PIN(47, "GPIO_47"),
161 	PINCTRL_PIN(48, "GPIO_48"),
162 	PINCTRL_PIN(49, "GPIO_49"),
163 	PINCTRL_PIN(50, "GPIO_50"),
164 	PINCTRL_PIN(51, "GPIO_51"),
165 	PINCTRL_PIN(52, "GPIO_52"),
166 	PINCTRL_PIN(53, "GPIO_53"),
167 	PINCTRL_PIN(54, "GPIO_54"),
168 	PINCTRL_PIN(55, "GPIO_55"),
169 	PINCTRL_PIN(56, "GPIO_56"),
170 	PINCTRL_PIN(57, "GPIO_57"),
171 	PINCTRL_PIN(58, "GPIO_58"),
172 	PINCTRL_PIN(59, "GPIO_59"),
173 	PINCTRL_PIN(60, "GPIO_60"),
174 	PINCTRL_PIN(61, "GPIO_61"),
175 	PINCTRL_PIN(62, "GPIO_62"),
176 	PINCTRL_PIN(63, "GPIO_63"),
177 	PINCTRL_PIN(64, "GPIO_64"),
178 	PINCTRL_PIN(65, "GPIO_65"),
179 	PINCTRL_PIN(66, "GPIO_66"),
180 	PINCTRL_PIN(67, "GPIO_67"),
181 	PINCTRL_PIN(68, "GPIO_68"),
182 	PINCTRL_PIN(69, "GPIO_69"),
183 	PINCTRL_PIN(70, "GPIO_70"),
184 	PINCTRL_PIN(71, "GPIO_71"),
185 	PINCTRL_PIN(72, "GPIO_72"),
186 	PINCTRL_PIN(73, "GPIO_73"),
187 	PINCTRL_PIN(74, "GPIO_74"),
188 	PINCTRL_PIN(75, "GPIO_75"),
189 	PINCTRL_PIN(76, "GPIO_76"),
190 	PINCTRL_PIN(77, "GPIO_77"),
191 	PINCTRL_PIN(78, "GPIO_78"),
192 	PINCTRL_PIN(79, "GPIO_79"),
193 	PINCTRL_PIN(80, "GPIO_80"),
194 	PINCTRL_PIN(81, "GPIO_81"),
195 	PINCTRL_PIN(82, "GPIO_82"),
196 	PINCTRL_PIN(83, "GPIO_83"),
197 	PINCTRL_PIN(84, "GPIO_84"),
198 	PINCTRL_PIN(85, "GPIO_85"),
199 	PINCTRL_PIN(86, "GPIO_86"),
200 	PINCTRL_PIN(87, "GPIO_87"),
201 	PINCTRL_PIN(88, "GPIO_88"),
202 	PINCTRL_PIN(89, "GPIO_89"),
203 	PINCTRL_PIN(90, "GPIO_90"),
204 	PINCTRL_PIN(91, "GPIO_91"),
205 	PINCTRL_PIN(92, "GPIO_92"),
206 	PINCTRL_PIN(93, "GPIO_93"),
207 	PINCTRL_PIN(94, "GPIO_94"),
208 	PINCTRL_PIN(95, "GPIO_95"),
209 	PINCTRL_PIN(96, "GPIO_96"),
210 	PINCTRL_PIN(97, "GPIO_97"),
211 	PINCTRL_PIN(98, "GPIO_98"),
212 	PINCTRL_PIN(99, "GPIO_99"),
213 	PINCTRL_PIN(100, "GPIO_100"),
214 	PINCTRL_PIN(101, "GPIO_101"),
215 	PINCTRL_PIN(102, "GPIO_102"),
216 	PINCTRL_PIN(103, "GPIO_103"),
217 	PINCTRL_PIN(104, "GPIO_104"),
218 	PINCTRL_PIN(105, "GPIO_105"),
219 	PINCTRL_PIN(106, "GPIO_106"),
220 	PINCTRL_PIN(107, "GPIO_107"),
221 	PINCTRL_PIN(108, "GPIO_108"),
222 	PINCTRL_PIN(109, "GPIO_109"),
223 	PINCTRL_PIN(110, "GPIO_110"),
224 	PINCTRL_PIN(111, "GPIO_111"),
225 	PINCTRL_PIN(112, "GPIO_112"),
226 	PINCTRL_PIN(113, "GPIO_113"),
227 	PINCTRL_PIN(114, "GPIO_114"),
228 	PINCTRL_PIN(115, "GPIO_115"),
229 	PINCTRL_PIN(116, "GPIO_116"),
230 	PINCTRL_PIN(117, "GPIO_117"),
231 	PINCTRL_PIN(118, "GPIO_118"),
232 	PINCTRL_PIN(119, "GPIO_119"),
233 	PINCTRL_PIN(120, "GPIO_120"),
234 	PINCTRL_PIN(121, "GPIO_121"),
235 	PINCTRL_PIN(122, "GPIO_122"),
236 	PINCTRL_PIN(123, "GPIO_123"),
237 	PINCTRL_PIN(124, "GPIO_124"),
238 	PINCTRL_PIN(125, "GPIO_125"),
239 	PINCTRL_PIN(126, "GPIO_126"),
240 	PINCTRL_PIN(127, "GPIO_127"),
241 	PINCTRL_PIN(128, "GPIO_128"),
242 	PINCTRL_PIN(129, "GPIO_129"),
243 	PINCTRL_PIN(130, "GPIO_130"),
244 	PINCTRL_PIN(131, "GPIO_131"),
245 	PINCTRL_PIN(132, "GPIO_132"),
246 	PINCTRL_PIN(133, "GPIO_133"),
247 	PINCTRL_PIN(134, "GPIO_134"),
248 	PINCTRL_PIN(135, "GPIO_135"),
249 	PINCTRL_PIN(136, "GPIO_136"),
250 	PINCTRL_PIN(137, "GPIO_137"),
251 	PINCTRL_PIN(138, "GPIO_138"),
252 	PINCTRL_PIN(139, "GPIO_139"),
253 	PINCTRL_PIN(140, "GPIO_140"),
254 	PINCTRL_PIN(141, "GPIO_141"),
255 	PINCTRL_PIN(142, "GPIO_142"),
256 	PINCTRL_PIN(143, "GPIO_143"),
257 	PINCTRL_PIN(144, "GPIO_144"),
258 	PINCTRL_PIN(145, "GPIO_145"),
259 	PINCTRL_PIN(146, "GPIO_146"),
260 	PINCTRL_PIN(147, "GPIO_147"),
261 	PINCTRL_PIN(148, "GPIO_148"),
262 	PINCTRL_PIN(149, "GPIO_149"),
263 	PINCTRL_PIN(150, "GPIO_150"),
264 	PINCTRL_PIN(151, "GPIO_151"),
265 	PINCTRL_PIN(152, "GPIO_152"),
266 	PINCTRL_PIN(153, "GPIO_153"),
267 	PINCTRL_PIN(154, "GPIO_154"),
268 	PINCTRL_PIN(155, "GPIO_155"),
269 	PINCTRL_PIN(156, "GPIO_156"),
270 	PINCTRL_PIN(157, "GPIO_157"),
271 	PINCTRL_PIN(158, "GPIO_158"),
272 	PINCTRL_PIN(159, "GPIO_159"),
273 	PINCTRL_PIN(160, "GPIO_160"),
274 	PINCTRL_PIN(161, "GPIO_161"),
275 	PINCTRL_PIN(162, "GPIO_162"),
276 	PINCTRL_PIN(163, "GPIO_163"),
277 	PINCTRL_PIN(164, "GPIO_164"),
278 	PINCTRL_PIN(165, "GPIO_165"),
279 	PINCTRL_PIN(166, "GPIO_166"),
280 	PINCTRL_PIN(167, "GPIO_167"),
281 	PINCTRL_PIN(168, "GPIO_168"),
282 	PINCTRL_PIN(169, "GPIO_169"),
283 	PINCTRL_PIN(170, "GPIO_170"),
284 	PINCTRL_PIN(171, "GPIO_171"),
285 	PINCTRL_PIN(172, "GPIO_172"),
286 	PINCTRL_PIN(173, "GPIO_173"),
287 	PINCTRL_PIN(174, "GPIO_174"),
288 	PINCTRL_PIN(175, "GPIO_175"),
289 	PINCTRL_PIN(176, "GPIO_176"),
290 	PINCTRL_PIN(177, "GPIO_177"),
291 	PINCTRL_PIN(178, "GPIO_178"),
292 	PINCTRL_PIN(179, "GPIO_179"),
293 	PINCTRL_PIN(180, "GPIO_180"),
294 	PINCTRL_PIN(181, "GPIO_181"),
295 	PINCTRL_PIN(182, "GPIO_182"),
296 	PINCTRL_PIN(183, "GPIO_183"),
297 	PINCTRL_PIN(184, "GPIO_184"),
298 	PINCTRL_PIN(185, "GPIO_185"),
299 	PINCTRL_PIN(186, "GPIO_186"),
300 	PINCTRL_PIN(187, "GPIO_187"),
301 	PINCTRL_PIN(188, "GPIO_188"),
302 	PINCTRL_PIN(189, "GPIO_189"),
303 	PINCTRL_PIN(190, "GPIO_190"),
304 	PINCTRL_PIN(191, "GPIO_191"),
305 	PINCTRL_PIN(192, "GPIO_192"),
306 	PINCTRL_PIN(193, "GPIO_193"),
307 	PINCTRL_PIN(194, "GPIO_194"),
308 	PINCTRL_PIN(195, "GPIO_195"),
309 	PINCTRL_PIN(196, "GPIO_196"),
310 	PINCTRL_PIN(197, "GPIO_197"),
311 	PINCTRL_PIN(198, "GPIO_198"),
312 	PINCTRL_PIN(199, "GPIO_199"),
313 	PINCTRL_PIN(200, "GPIO_200"),
314 	PINCTRL_PIN(201, "GPIO_201"),
315 	PINCTRL_PIN(202, "GPIO_202"),
316 	PINCTRL_PIN(203, "GPIO_203"),
317 	PINCTRL_PIN(204, "GPIO_204"),
318 	PINCTRL_PIN(205, "GPIO_205"),
319 	PINCTRL_PIN(206, "GPIO_206"),
320 	PINCTRL_PIN(207, "GPIO_207"),
321 	PINCTRL_PIN(208, "GPIO_208"),
322 	PINCTRL_PIN(209, "GPIO_209"),
323 	PINCTRL_PIN(210, "UFS_RESET"),
324 	PINCTRL_PIN(211, "SDC2_CLK"),
325 	PINCTRL_PIN(212, "SDC2_CMD"),
326 	PINCTRL_PIN(213, "SDC2_DATA"),
327 };
328 
329 #define DECLARE_MSM_GPIO_PINS(pin) \
330 	static const unsigned int gpio##pin##_pins[] = { pin }
331 DECLARE_MSM_GPIO_PINS(0);
332 DECLARE_MSM_GPIO_PINS(1);
333 DECLARE_MSM_GPIO_PINS(2);
334 DECLARE_MSM_GPIO_PINS(3);
335 DECLARE_MSM_GPIO_PINS(4);
336 DECLARE_MSM_GPIO_PINS(5);
337 DECLARE_MSM_GPIO_PINS(6);
338 DECLARE_MSM_GPIO_PINS(7);
339 DECLARE_MSM_GPIO_PINS(8);
340 DECLARE_MSM_GPIO_PINS(9);
341 DECLARE_MSM_GPIO_PINS(10);
342 DECLARE_MSM_GPIO_PINS(11);
343 DECLARE_MSM_GPIO_PINS(12);
344 DECLARE_MSM_GPIO_PINS(13);
345 DECLARE_MSM_GPIO_PINS(14);
346 DECLARE_MSM_GPIO_PINS(15);
347 DECLARE_MSM_GPIO_PINS(16);
348 DECLARE_MSM_GPIO_PINS(17);
349 DECLARE_MSM_GPIO_PINS(18);
350 DECLARE_MSM_GPIO_PINS(19);
351 DECLARE_MSM_GPIO_PINS(20);
352 DECLARE_MSM_GPIO_PINS(21);
353 DECLARE_MSM_GPIO_PINS(22);
354 DECLARE_MSM_GPIO_PINS(23);
355 DECLARE_MSM_GPIO_PINS(24);
356 DECLARE_MSM_GPIO_PINS(25);
357 DECLARE_MSM_GPIO_PINS(26);
358 DECLARE_MSM_GPIO_PINS(27);
359 DECLARE_MSM_GPIO_PINS(28);
360 DECLARE_MSM_GPIO_PINS(29);
361 DECLARE_MSM_GPIO_PINS(30);
362 DECLARE_MSM_GPIO_PINS(31);
363 DECLARE_MSM_GPIO_PINS(32);
364 DECLARE_MSM_GPIO_PINS(33);
365 DECLARE_MSM_GPIO_PINS(34);
366 DECLARE_MSM_GPIO_PINS(35);
367 DECLARE_MSM_GPIO_PINS(36);
368 DECLARE_MSM_GPIO_PINS(37);
369 DECLARE_MSM_GPIO_PINS(38);
370 DECLARE_MSM_GPIO_PINS(39);
371 DECLARE_MSM_GPIO_PINS(40);
372 DECLARE_MSM_GPIO_PINS(41);
373 DECLARE_MSM_GPIO_PINS(42);
374 DECLARE_MSM_GPIO_PINS(43);
375 DECLARE_MSM_GPIO_PINS(44);
376 DECLARE_MSM_GPIO_PINS(45);
377 DECLARE_MSM_GPIO_PINS(46);
378 DECLARE_MSM_GPIO_PINS(47);
379 DECLARE_MSM_GPIO_PINS(48);
380 DECLARE_MSM_GPIO_PINS(49);
381 DECLARE_MSM_GPIO_PINS(50);
382 DECLARE_MSM_GPIO_PINS(51);
383 DECLARE_MSM_GPIO_PINS(52);
384 DECLARE_MSM_GPIO_PINS(53);
385 DECLARE_MSM_GPIO_PINS(54);
386 DECLARE_MSM_GPIO_PINS(55);
387 DECLARE_MSM_GPIO_PINS(56);
388 DECLARE_MSM_GPIO_PINS(57);
389 DECLARE_MSM_GPIO_PINS(58);
390 DECLARE_MSM_GPIO_PINS(59);
391 DECLARE_MSM_GPIO_PINS(60);
392 DECLARE_MSM_GPIO_PINS(61);
393 DECLARE_MSM_GPIO_PINS(62);
394 DECLARE_MSM_GPIO_PINS(63);
395 DECLARE_MSM_GPIO_PINS(64);
396 DECLARE_MSM_GPIO_PINS(65);
397 DECLARE_MSM_GPIO_PINS(66);
398 DECLARE_MSM_GPIO_PINS(67);
399 DECLARE_MSM_GPIO_PINS(68);
400 DECLARE_MSM_GPIO_PINS(69);
401 DECLARE_MSM_GPIO_PINS(70);
402 DECLARE_MSM_GPIO_PINS(71);
403 DECLARE_MSM_GPIO_PINS(72);
404 DECLARE_MSM_GPIO_PINS(73);
405 DECLARE_MSM_GPIO_PINS(74);
406 DECLARE_MSM_GPIO_PINS(75);
407 DECLARE_MSM_GPIO_PINS(76);
408 DECLARE_MSM_GPIO_PINS(77);
409 DECLARE_MSM_GPIO_PINS(78);
410 DECLARE_MSM_GPIO_PINS(79);
411 DECLARE_MSM_GPIO_PINS(80);
412 DECLARE_MSM_GPIO_PINS(81);
413 DECLARE_MSM_GPIO_PINS(82);
414 DECLARE_MSM_GPIO_PINS(83);
415 DECLARE_MSM_GPIO_PINS(84);
416 DECLARE_MSM_GPIO_PINS(85);
417 DECLARE_MSM_GPIO_PINS(86);
418 DECLARE_MSM_GPIO_PINS(87);
419 DECLARE_MSM_GPIO_PINS(88);
420 DECLARE_MSM_GPIO_PINS(89);
421 DECLARE_MSM_GPIO_PINS(90);
422 DECLARE_MSM_GPIO_PINS(91);
423 DECLARE_MSM_GPIO_PINS(92);
424 DECLARE_MSM_GPIO_PINS(93);
425 DECLARE_MSM_GPIO_PINS(94);
426 DECLARE_MSM_GPIO_PINS(95);
427 DECLARE_MSM_GPIO_PINS(96);
428 DECLARE_MSM_GPIO_PINS(97);
429 DECLARE_MSM_GPIO_PINS(98);
430 DECLARE_MSM_GPIO_PINS(99);
431 DECLARE_MSM_GPIO_PINS(100);
432 DECLARE_MSM_GPIO_PINS(101);
433 DECLARE_MSM_GPIO_PINS(102);
434 DECLARE_MSM_GPIO_PINS(103);
435 DECLARE_MSM_GPIO_PINS(104);
436 DECLARE_MSM_GPIO_PINS(105);
437 DECLARE_MSM_GPIO_PINS(106);
438 DECLARE_MSM_GPIO_PINS(107);
439 DECLARE_MSM_GPIO_PINS(108);
440 DECLARE_MSM_GPIO_PINS(109);
441 DECLARE_MSM_GPIO_PINS(110);
442 DECLARE_MSM_GPIO_PINS(111);
443 DECLARE_MSM_GPIO_PINS(112);
444 DECLARE_MSM_GPIO_PINS(113);
445 DECLARE_MSM_GPIO_PINS(114);
446 DECLARE_MSM_GPIO_PINS(115);
447 DECLARE_MSM_GPIO_PINS(116);
448 DECLARE_MSM_GPIO_PINS(117);
449 DECLARE_MSM_GPIO_PINS(118);
450 DECLARE_MSM_GPIO_PINS(119);
451 DECLARE_MSM_GPIO_PINS(120);
452 DECLARE_MSM_GPIO_PINS(121);
453 DECLARE_MSM_GPIO_PINS(122);
454 DECLARE_MSM_GPIO_PINS(123);
455 DECLARE_MSM_GPIO_PINS(124);
456 DECLARE_MSM_GPIO_PINS(125);
457 DECLARE_MSM_GPIO_PINS(126);
458 DECLARE_MSM_GPIO_PINS(127);
459 DECLARE_MSM_GPIO_PINS(128);
460 DECLARE_MSM_GPIO_PINS(129);
461 DECLARE_MSM_GPIO_PINS(130);
462 DECLARE_MSM_GPIO_PINS(131);
463 DECLARE_MSM_GPIO_PINS(132);
464 DECLARE_MSM_GPIO_PINS(133);
465 DECLARE_MSM_GPIO_PINS(134);
466 DECLARE_MSM_GPIO_PINS(135);
467 DECLARE_MSM_GPIO_PINS(136);
468 DECLARE_MSM_GPIO_PINS(137);
469 DECLARE_MSM_GPIO_PINS(138);
470 DECLARE_MSM_GPIO_PINS(139);
471 DECLARE_MSM_GPIO_PINS(140);
472 DECLARE_MSM_GPIO_PINS(141);
473 DECLARE_MSM_GPIO_PINS(142);
474 DECLARE_MSM_GPIO_PINS(143);
475 DECLARE_MSM_GPIO_PINS(144);
476 DECLARE_MSM_GPIO_PINS(145);
477 DECLARE_MSM_GPIO_PINS(146);
478 DECLARE_MSM_GPIO_PINS(147);
479 DECLARE_MSM_GPIO_PINS(148);
480 DECLARE_MSM_GPIO_PINS(149);
481 DECLARE_MSM_GPIO_PINS(150);
482 DECLARE_MSM_GPIO_PINS(151);
483 DECLARE_MSM_GPIO_PINS(152);
484 DECLARE_MSM_GPIO_PINS(153);
485 DECLARE_MSM_GPIO_PINS(154);
486 DECLARE_MSM_GPIO_PINS(155);
487 DECLARE_MSM_GPIO_PINS(156);
488 DECLARE_MSM_GPIO_PINS(157);
489 DECLARE_MSM_GPIO_PINS(158);
490 DECLARE_MSM_GPIO_PINS(159);
491 DECLARE_MSM_GPIO_PINS(160);
492 DECLARE_MSM_GPIO_PINS(161);
493 DECLARE_MSM_GPIO_PINS(162);
494 DECLARE_MSM_GPIO_PINS(163);
495 DECLARE_MSM_GPIO_PINS(164);
496 DECLARE_MSM_GPIO_PINS(165);
497 DECLARE_MSM_GPIO_PINS(166);
498 DECLARE_MSM_GPIO_PINS(167);
499 DECLARE_MSM_GPIO_PINS(168);
500 DECLARE_MSM_GPIO_PINS(169);
501 DECLARE_MSM_GPIO_PINS(170);
502 DECLARE_MSM_GPIO_PINS(171);
503 DECLARE_MSM_GPIO_PINS(172);
504 DECLARE_MSM_GPIO_PINS(173);
505 DECLARE_MSM_GPIO_PINS(174);
506 DECLARE_MSM_GPIO_PINS(175);
507 DECLARE_MSM_GPIO_PINS(176);
508 DECLARE_MSM_GPIO_PINS(177);
509 DECLARE_MSM_GPIO_PINS(178);
510 DECLARE_MSM_GPIO_PINS(179);
511 DECLARE_MSM_GPIO_PINS(180);
512 DECLARE_MSM_GPIO_PINS(181);
513 DECLARE_MSM_GPIO_PINS(182);
514 DECLARE_MSM_GPIO_PINS(183);
515 DECLARE_MSM_GPIO_PINS(184);
516 DECLARE_MSM_GPIO_PINS(185);
517 DECLARE_MSM_GPIO_PINS(186);
518 DECLARE_MSM_GPIO_PINS(187);
519 DECLARE_MSM_GPIO_PINS(188);
520 DECLARE_MSM_GPIO_PINS(189);
521 DECLARE_MSM_GPIO_PINS(190);
522 DECLARE_MSM_GPIO_PINS(191);
523 DECLARE_MSM_GPIO_PINS(192);
524 DECLARE_MSM_GPIO_PINS(193);
525 DECLARE_MSM_GPIO_PINS(194);
526 DECLARE_MSM_GPIO_PINS(195);
527 DECLARE_MSM_GPIO_PINS(196);
528 DECLARE_MSM_GPIO_PINS(197);
529 DECLARE_MSM_GPIO_PINS(198);
530 DECLARE_MSM_GPIO_PINS(199);
531 DECLARE_MSM_GPIO_PINS(200);
532 DECLARE_MSM_GPIO_PINS(201);
533 DECLARE_MSM_GPIO_PINS(202);
534 DECLARE_MSM_GPIO_PINS(203);
535 DECLARE_MSM_GPIO_PINS(204);
536 DECLARE_MSM_GPIO_PINS(205);
537 DECLARE_MSM_GPIO_PINS(206);
538 DECLARE_MSM_GPIO_PINS(207);
539 DECLARE_MSM_GPIO_PINS(208);
540 DECLARE_MSM_GPIO_PINS(209);
541 
542 static const unsigned int ufs_reset_pins[] = { 210 };
543 static const unsigned int sdc2_clk_pins[] = { 211 };
544 static const unsigned int sdc2_cmd_pins[] = { 212 };
545 static const unsigned int sdc2_data_pins[] = { 213 };
546 
547 enum sm8450_functions {
548 	msm_mux_gpio,
549 	msm_mux_aon_cam,
550 	msm_mux_atest_char,
551 	msm_mux_atest_usb,
552 	msm_mux_audio_ref,
553 	msm_mux_cam_mclk,
554 	msm_mux_cci_async,
555 	msm_mux_cci_i2c,
556 	msm_mux_cci_timer,
557 	msm_mux_cmu_rng,
558 	msm_mux_coex_uart1,
559 	msm_mux_coex_uart2,
560 	msm_mux_cri_trng,
561 	msm_mux_cri_trng0,
562 	msm_mux_cri_trng1,
563 	msm_mux_dbg_out,
564 	msm_mux_ddr_bist,
565 	msm_mux_ddr_pxi0,
566 	msm_mux_ddr_pxi1,
567 	msm_mux_ddr_pxi2,
568 	msm_mux_ddr_pxi3,
569 	msm_mux_dp_hot,
570 	msm_mux_gcc_gp1,
571 	msm_mux_gcc_gp2,
572 	msm_mux_gcc_gp3,
573 	msm_mux_ibi_i3c,
574 	msm_mux_jitter_bist,
575 	msm_mux_mdp_vsync,
576 	msm_mux_mdp_vsync0,
577 	msm_mux_mdp_vsync1,
578 	msm_mux_mdp_vsync2,
579 	msm_mux_mdp_vsync3,
580 	msm_mux_mi2s0_data0,
581 	msm_mux_mi2s0_data1,
582 	msm_mux_mi2s0_sck,
583 	msm_mux_mi2s0_ws,
584 	msm_mux_mi2s2_data0,
585 	msm_mux_mi2s2_data1,
586 	msm_mux_mi2s2_sck,
587 	msm_mux_mi2s2_ws,
588 	msm_mux_mss_grfc0,
589 	msm_mux_mss_grfc1,
590 	msm_mux_mss_grfc10,
591 	msm_mux_mss_grfc11,
592 	msm_mux_mss_grfc12,
593 	msm_mux_mss_grfc2,
594 	msm_mux_mss_grfc3,
595 	msm_mux_mss_grfc4,
596 	msm_mux_mss_grfc5,
597 	msm_mux_mss_grfc6,
598 	msm_mux_mss_grfc7,
599 	msm_mux_mss_grfc8,
600 	msm_mux_mss_grfc9,
601 	msm_mux_nav,
602 	msm_mux_pcie0_clkreqn,
603 	msm_mux_pcie1_clkreqn,
604 	msm_mux_phase_flag,
605 	msm_mux_pll_bist,
606 	msm_mux_pll_clk,
607 	msm_mux_pri_mi2s,
608 	msm_mux_prng_rosc,
609 	msm_mux_qdss_cti,
610 	msm_mux_qdss_gpio,
611 	msm_mux_qlink0_enable,
612 	msm_mux_qlink0_request,
613 	msm_mux_qlink0_wmss,
614 	msm_mux_qlink1_enable,
615 	msm_mux_qlink1_request,
616 	msm_mux_qlink1_wmss,
617 	msm_mux_qlink2_enable,
618 	msm_mux_qlink2_request,
619 	msm_mux_qlink2_wmss,
620 	msm_mux_qspi0,
621 	msm_mux_qspi1,
622 	msm_mux_qspi2,
623 	msm_mux_qspi3,
624 	msm_mux_qspi_clk,
625 	msm_mux_qspi_cs,
626 	msm_mux_qup0,
627 	msm_mux_qup1,
628 	msm_mux_qup10,
629 	msm_mux_qup11,
630 	msm_mux_qup12,
631 	msm_mux_qup13,
632 	msm_mux_qup14,
633 	msm_mux_qup15,
634 	msm_mux_qup16,
635 	msm_mux_qup17,
636 	msm_mux_qup18,
637 	msm_mux_qup19,
638 	msm_mux_qup2,
639 	msm_mux_qup20,
640 	msm_mux_qup21,
641 	msm_mux_qup3,
642 	msm_mux_qup4,
643 	msm_mux_qup5,
644 	msm_mux_qup6,
645 	msm_mux_qup7,
646 	msm_mux_qup8,
647 	msm_mux_qup9,
648 	msm_mux_qup_l4,
649 	msm_mux_qup_l5,
650 	msm_mux_qup_l6,
651 	msm_mux_sd_write,
652 	msm_mux_sdc40,
653 	msm_mux_sdc41,
654 	msm_mux_sdc42,
655 	msm_mux_sdc43,
656 	msm_mux_sdc4_clk,
657 	msm_mux_sdc4_cmd,
658 	msm_mux_sec_mi2s,
659 	msm_mux_tb_trig,
660 	msm_mux_tgu_ch0,
661 	msm_mux_tgu_ch1,
662 	msm_mux_tgu_ch2,
663 	msm_mux_tgu_ch3,
664 	msm_mux_tmess_prng0,
665 	msm_mux_tmess_prng1,
666 	msm_mux_tmess_prng2,
667 	msm_mux_tmess_prng3,
668 	msm_mux_tsense_pwm1,
669 	msm_mux_tsense_pwm2,
670 	msm_mux_uim0_clk,
671 	msm_mux_uim0_data,
672 	msm_mux_uim0_present,
673 	msm_mux_uim0_reset,
674 	msm_mux_uim1_clk,
675 	msm_mux_uim1_data,
676 	msm_mux_uim1_present,
677 	msm_mux_uim1_reset,
678 	msm_mux_usb2phy_ac,
679 	msm_mux_usb_phy,
680 	msm_mux_vfr_0,
681 	msm_mux_vfr_1,
682 	msm_mux_vsense_trigger,
683 	msm_mux__,
684 };
685 
686 static const char * const gpio_groups[] = {
687 	"gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
688 	"gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
689 	"gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
690 	"gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
691 	"gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
692 	"gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
693 	"gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
694 	"gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
695 	"gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
696 	"gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70",
697 	"gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77",
698 	"gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84",
699 	"gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91",
700 	"gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98",
701 	"gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104",
702 	"gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110",
703 	"gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116",
704 	"gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122",
705 	"gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128",
706 	"gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134",
707 	"gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140",
708 	"gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146",
709 	"gpio147", "gpio148", "gpio149", "gpio150", "gpio151", "gpio152",
710 	"gpio153", "gpio154", "gpio155", "gpio156", "gpio157", "gpio158",
711 	"gpio159", "gpio160", "gpio161", "gpio162", "gpio163", "gpio164",
712 	"gpio165", "gpio166", "gpio167", "gpio168", "gpio169", "gpio170",
713 	"gpio171", "gpio172", "gpio173", "gpio174", "gpio175", "gpio176",
714 	"gpio177", "gpio178", "gpio179", "gpio180", "gpio181", "gpio182",
715 	"gpio183", "gpio184", "gpio185", "gpio186", "gpio187", "gpio188",
716 	"gpio189", "gpio190", "gpio191", "gpio192", "gpio193", "gpio194",
717 	"gpio195", "gpio196", "gpio197", "gpio198", "gpio199", "gpio200",
718 	"gpio201", "gpio202", "gpio203", "gpio204", "gpio205", "gpio206",
719 	"gpio207", "gpio208", "gpio209",
720 };
721 
722 static const char * const aon_cam_groups[] = {
723 	"gpio108",
724 };
725 
726 static const char * const atest_char_groups[] = {
727 	"gpio86", "gpio87", "gpio88", "gpio89", "gpio90",
728 };
729 
730 static const char * const atest_usb_groups[] = {
731 	"gpio37", "gpio39", "gpio55", "gpio148", "gpio149",
732 };
733 
734 static const char * const audio_ref_groups[] = {
735 	"gpio124",
736 };
737 
738 static const char * const cam_mclk_groups[] = {
739 	"gpio100", "gpio101", "gpio102", "gpio103", "gpio104", "gpio105", "gpio106", "gpio107",
740 };
741 
742 static const char * const cci_async_groups[] = {
743 	"gpio109", "gpio119", "gpio120",
744 };
745 
746 static const char * const cci_i2c_groups[] = {
747 	"gpio110", "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio208", "gpio209",
748 };
749 
750 static const char * const cci_timer_groups[] = {
751 	"gpio116", "gpio117", "gpio118", "gpio119", "gpio120",
752 };
753 
754 static const char * const cmu_rng_groups[] = {
755 	"gpio94", "gpio95", "gpio96", "gpio97",
756 };
757 
758 static const char * const coex_uart1_groups[] = {
759 	"gpio148", "gpio149",
760 };
761 
762 static const char * const coex_uart2_groups[] = {
763 	"gpio150", "gpio151",
764 };
765 
766 static const char * const cri_trng_groups[] = {
767 	"gpio99",
768 };
769 
770 static const char * const cri_trng0_groups[] = {
771 	"gpio71",
772 };
773 
774 static const char * const cri_trng1_groups[] = {
775 	"gpio72",
776 };
777 
778 static const char * const dbg_out_groups[] = {
779 	"gpio9",
780 };
781 
782 static const char * const ddr_bist_groups[] = {
783 	"gpio36", "gpio37", "gpio40", "gpio41",
784 };
785 
786 static const char * const ddr_pxi0_groups[] = {
787 	"gpio51", "gpio52",
788 };
789 
790 static const char * const ddr_pxi1_groups[] = {
791 	"gpio40", "gpio41",
792 };
793 
794 static const char * const ddr_pxi2_groups[] = {
795 	"gpio45", "gpio47",
796 };
797 
798 static const char * const ddr_pxi3_groups[] = {
799 	"gpio43", "gpio44",
800 };
801 
802 static const char * const dp_hot_groups[] = {
803 	"gpio47",
804 };
805 
806 static const char * const gcc_gp1_groups[] = {
807 	"gpio86", "gpio134",
808 };
809 
810 static const char * const gcc_gp2_groups[] = {
811 	"gpio87", "gpio135",
812 };
813 
814 static const char * const gcc_gp3_groups[] = {
815 	"gpio88", "gpio136",
816 };
817 
818 static const char * const ibi_i3c_groups[] = {
819 	"gpio28", "gpio29", "gpio32", "gpio33", "gpio56", "gpio57", "gpio60", "gpio61",
820 };
821 
822 static const char * const jitter_bist_groups[] = {
823 	"gpio24",
824 };
825 
826 static const char * const mdp_vsync_groups[] = {
827 	"gpio46", "gpio47", "gpio86", "gpio87", "gpio88",
828 };
829 
830 static const char * const mdp_vsync0_groups[] = {
831 	"gpio86",
832 };
833 
834 static const char * const mdp_vsync1_groups[] = {
835 	"gpio86",
836 };
837 
838 static const char * const mdp_vsync2_groups[] = {
839 	"gpio87",
840 };
841 
842 static const char * const mdp_vsync3_groups[] = {
843 	"gpio87",
844 };
845 
846 static const char * const mi2s0_data0_groups[] = {
847 	"gpio127",
848 };
849 
850 static const char * const mi2s0_data1_groups[] = {
851 	"gpio128",
852 };
853 
854 static const char * const mi2s0_sck_groups[] = {
855 	"gpio126",
856 };
857 
858 static const char * const mi2s0_ws_groups[] = {
859 	"gpio129",
860 };
861 
862 static const char * const mi2s2_data0_groups[] = {
863 	"gpio122",
864 };
865 
866 static const char * const mi2s2_data1_groups[] = {
867 	"gpio124",
868 };
869 
870 static const char * const mi2s2_sck_groups[] = {
871 	"gpio121",
872 };
873 
874 static const char * const mi2s2_ws_groups[] = {
875 	"gpio123",
876 };
877 
878 static const char * const mss_grfc0_groups[] = {
879 	"gpio138", "gpio153",
880 };
881 
882 static const char * const mss_grfc1_groups[] = {
883 	"gpio139",
884 };
885 
886 static const char * const mss_grfc10_groups[] = {
887 	"gpio150",
888 };
889 
890 static const char * const mss_grfc11_groups[] = {
891 	"gpio151",
892 };
893 
894 static const char * const mss_grfc12_groups[] = {
895 	"gpio152",
896 };
897 
898 static const char * const mss_grfc2_groups[] = {
899 	"gpio140",
900 };
901 
902 static const char * const mss_grfc3_groups[] = {
903 	"gpio141",
904 };
905 
906 static const char * const mss_grfc4_groups[] = {
907 	"gpio142",
908 };
909 
910 static const char * const mss_grfc5_groups[] = {
911 	"gpio143",
912 };
913 
914 static const char * const mss_grfc6_groups[] = {
915 	"gpio144",
916 };
917 
918 static const char * const mss_grfc7_groups[] = {
919 	"gpio145",
920 };
921 
922 static const char * const mss_grfc8_groups[] = {
923 	"gpio146",
924 };
925 
926 static const char * const mss_grfc9_groups[] = {
927 	"gpio147",
928 };
929 
930 static const char * const nav_groups[] = {
931 	"gpio153", "gpio154", "gpio155",
932 };
933 
934 static const char * const pcie0_clkreqn_groups[] = {
935 	"gpio95",
936 };
937 
938 static const char * const pcie1_clkreqn_groups[] = {
939 	"gpio98",
940 };
941 
942 static const char * const phase_flag_groups[] = {
943 	"gpio4", "gpio5", "gpio6", "gpio7", "gpio10", "gpio11", "gpio12", "gpio13",
944 	"gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio25", "gpio26",
945 	"gpio76", "gpio77", "gpio78", "gpio79", "gpio81", "gpio82", "gpio83", "gpio92",
946 	"gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", "gpio99",
947 };
948 
949 static const char * const pll_bist_groups[] = {
950 	"gpio20",
951 };
952 
953 static const char * const pll_clk_groups[] = {
954 	"gpio107",
955 };
956 
957 static const char * const pri_mi2s_groups[] = {
958 	"gpio125",
959 };
960 
961 static const char * const prng_rosc_groups[] = {
962 	"gpio73", "gpio75", "gpio81", "gpio83",  "gpio81",
963 };
964 
965 static const char * const qdss_cti_groups[] = {
966 	"gpio2", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", "gpio85", "gpio93",
967 };
968 
969 static const char * const qdss_gpio_groups[] = {
970 	"gpio100", "gpio101", "gpio102", "gpio103", "gpio104", "gpio105", "gpio106", "gpio107",
971 	"gpio110", "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio117", "gpio118",
972 	"gpio119", "gpio120", "gpio188", "gpio189", "gpio190", "gpio191", "gpio192", "gpio193",
973 	"gpio194", "gpio195", "gpio196", "gpio197", "gpio198", "gpio199", "gpio200", "gpio201",
974 	"gpio202", "gpio203", "gpio204", "gpio205",
975 };
976 
977 static const char * const qlink0_enable_groups[] = {
978 	"gpio157",
979 };
980 
981 static const char * const qlink0_request_groups[] = {
982 	"gpio156",
983 };
984 
985 static const char * const qlink0_wmss_groups[] = {
986 	"gpio158",
987 };
988 
989 static const char * const qlink1_enable_groups[] = {
990 	"gpio160",
991 };
992 
993 static const char * const qlink1_request_groups[] = {
994 	"gpio159",
995 };
996 
997 static const char * const qlink1_wmss_groups[] = {
998 	"gpio161",
999 };
1000 
1001 static const char * const qlink2_enable_groups[] = {
1002 	"gpio163",
1003 };
1004 
1005 static const char * const qlink2_request_groups[] = {
1006 	"gpio162",
1007 };
1008 
1009 static const char * const qlink2_wmss_groups[] = {
1010 	"gpio164",
1011 };
1012 
1013 static const char * const qspi0_groups[] = {
1014 	"gpio52",
1015 };
1016 
1017 static const char * const qspi1_groups[] = {
1018 	"gpio53",
1019 };
1020 
1021 static const char * const qspi2_groups[] = {
1022 	"gpio48",
1023 };
1024 
1025 static const char * const qspi3_groups[] = {
1026 	"gpio49",
1027 };
1028 
1029 static const char * const qspi_clk_groups[] = {
1030 	"gpio50",
1031 };
1032 
1033 static const char * const qspi_cs_groups[] = {
1034 	"gpio51", "gpio54",
1035 };
1036 
1037 static const char * const qup0_groups[] = {
1038 	"gpio0", "gpio1", "gpio2", "gpio3",
1039 };
1040 
1041 static const char * const qup1_groups[] = {
1042 	"gpio4", "gpio5", "gpio6", "gpio7",
1043 };
1044 
1045 static const char * const qup10_groups[] = {
1046 	"gpio36", "gpio37", "gpio38", "gpio39",
1047 };
1048 
1049 static const char * const qup11_groups[] = {
1050 	"gpio40", "gpio41", "gpio42", "gpio43",
1051 };
1052 
1053 static const char * const qup12_groups[] = {
1054 	"gpio44", "gpio45", "gpio46", "gpio47",
1055 };
1056 
1057 static const char * const qup13_groups[] = {
1058 	"gpio48", "gpio49", "gpio50", "gpio51",
1059 };
1060 
1061 static const char * const qup14_groups[] = {
1062 	"gpio52", "gpio53", "gpio54", "gpio55",
1063 };
1064 
1065 static const char * const qup15_groups[] = {
1066 	"gpio56", "gpio57", "gpio58", "gpio59",
1067 };
1068 
1069 static const char * const qup16_groups[] = {
1070 	"gpio60", "gpio61", "gpio62", "gpio63",
1071 };
1072 
1073 static const char * const qup17_groups[] = {
1074 	"gpio64", "gpio65", "gpio66", "gpio67",
1075 };
1076 
1077 static const char * const qup18_groups[] = {
1078 	"gpio68", "gpio69", "gpio70", "gpio71",
1079 };
1080 
1081 static const char * const qup19_groups[] = {
1082 	"gpio72", "gpio73", "gpio74", "gpio75",
1083 };
1084 
1085 static const char * const qup2_groups[] = {
1086 	"gpio8", "gpio9", "gpio10", "gpio11",
1087 };
1088 
1089 static const char * const qup20_groups[] = {
1090 	"gpio76", "gpio77", "gpio78", "gpio79",
1091 };
1092 
1093 static const char * const qup21_groups[] = {
1094 	"gpio80", "gpio81", "gpio82", "gpio83",
1095 };
1096 
1097 static const char * const qup3_groups[] = {
1098 	"gpio12", "gpio13", "gpio14", "gpio15",
1099 };
1100 
1101 static const char * const qup4_groups[] = {
1102 	"gpio16", "gpio17", "gpio18", "gpio19",
1103 };
1104 
1105 static const char * const qup5_groups[] = {
1106 	"gpio84", "gpio85", "gpio206", "gpio207",
1107 };
1108 
1109 static const char * const qup6_groups[] = {
1110 	"gpio20", "gpio21", "gpio22", "gpio23",
1111 };
1112 
1113 static const char * const qup7_groups[] = {
1114 	"gpio24", "gpio25", "gpio26", "gpio27",
1115 };
1116 
1117 static const char * const qup8_groups[] = {
1118 	"gpio28", "gpio29", "gpio30", "gpio31",
1119 };
1120 
1121 static const char * const qup9_groups[] = {
1122 	"gpio32", "gpio33", "gpio34", "gpio35",
1123 };
1124 
1125 static const char * const qup_l4_groups[] = {
1126 	"gpio24", "gpio40", "gpio58", "gpio63",
1127 };
1128 
1129 static const char * const qup_l5_groups[] = {
1130 	"gpio25", "gpio41", "gpio59", "gpio66",
1131 };
1132 
1133 static const char * const qup_l6_groups[] = {
1134 	"gpio26", "gpio42", "gpio62", "gpio67",
1135 };
1136 
1137 static const char * const sd_write_groups[] = {
1138 	"gpio93",
1139 };
1140 
1141 static const char * const sdc40_groups[] = {
1142 	"gpio52",
1143 };
1144 
1145 static const char * const sdc41_groups[] = {
1146 	"gpio53",
1147 };
1148 
1149 static const char * const sdc42_groups[] = {
1150 	"gpio48",
1151 };
1152 
1153 static const char * const sdc43_groups[] = {
1154 	"gpio49",
1155 };
1156 
1157 static const char * const sdc4_clk_groups[] = {
1158 	"gpio50",
1159 };
1160 
1161 static const char * const sdc4_cmd_groups[] = {
1162 	"gpio51",
1163 };
1164 
1165 static const char * const sec_mi2s_groups[] = {
1166 	"gpio124",
1167 };
1168 
1169 static const char * const tb_trig_groups[] = {
1170 	"gpio64", "gpio137",
1171 };
1172 
1173 static const char * const tgu_ch0_groups[] = {
1174 	"gpio64",
1175 };
1176 
1177 static const char * const tgu_ch1_groups[] = {
1178 	"gpio65",
1179 };
1180 
1181 static const char * const tgu_ch2_groups[] = {
1182 	"gpio66",
1183 };
1184 
1185 static const char * const tgu_ch3_groups[] = {
1186 	"gpio67",
1187 };
1188 
1189 static const char * const tmess_prng0_groups[] = {
1190 	"gpio80",
1191 };
1192 
1193 static const char * const tmess_prng1_groups[] = {
1194 	"gpio79",
1195 };
1196 
1197 static const char * const tmess_prng2_groups[] = {
1198 	"gpio77",
1199 };
1200 
1201 static const char * const tmess_prng3_groups[] = {
1202 	"gpio76",
1203 };
1204 
1205 static const char * const tsense_pwm1_groups[] = {
1206 	"gpio91",
1207 };
1208 
1209 static const char * const tsense_pwm2_groups[] = {
1210 	"gpio91",
1211 };
1212 
1213 static const char * const uim0_clk_groups[] = {
1214 	"gpio131",
1215 };
1216 
1217 static const char * const uim0_data_groups[] = {
1218 	"gpio130",
1219 };
1220 
1221 static const char * const uim0_present_groups[] = {
1222 	"gpio133",
1223 };
1224 
1225 static const char * const uim0_reset_groups[] = {
1226 	"gpio132",
1227 };
1228 
1229 static const char * const uim1_clk_groups[] = {
1230 	"gpio135",
1231 };
1232 
1233 static const char * const uim1_data_groups[] = {
1234 	"gpio134",
1235 };
1236 
1237 static const char * const uim1_present_groups[] = {
1238 	"gpio137",
1239 };
1240 
1241 static const char * const uim1_reset_groups[] = {
1242 	"gpio136",
1243 };
1244 
1245 static const char * const usb2phy_ac_groups[] = {
1246 	"gpio90",
1247 };
1248 
1249 static const char * const usb_phy_groups[] = {
1250 	"gpio91",
1251 };
1252 
1253 static const char * const vfr_0_groups[] = {
1254 	"gpio89",
1255 };
1256 
1257 static const char * const vfr_1_groups[] = {
1258 	"gpio155",
1259 };
1260 
1261 static const char * const vsense_trigger_groups[] = {
1262 	"gpio18",
1263 };
1264 
1265 static const struct msm_function sm8450_functions[] = {
1266 	FUNCTION(gpio),
1267 	FUNCTION(aon_cam),
1268 	FUNCTION(atest_char),
1269 	FUNCTION(atest_usb),
1270 	FUNCTION(audio_ref),
1271 	FUNCTION(cam_mclk),
1272 	FUNCTION(cci_async),
1273 	FUNCTION(cci_i2c),
1274 	FUNCTION(cci_timer),
1275 	FUNCTION(cmu_rng),
1276 	FUNCTION(coex_uart1),
1277 	FUNCTION(coex_uart2),
1278 	FUNCTION(cri_trng),
1279 	FUNCTION(cri_trng0),
1280 	FUNCTION(cri_trng1),
1281 	FUNCTION(dbg_out),
1282 	FUNCTION(ddr_bist),
1283 	FUNCTION(ddr_pxi0),
1284 	FUNCTION(ddr_pxi1),
1285 	FUNCTION(ddr_pxi2),
1286 	FUNCTION(ddr_pxi3),
1287 	FUNCTION(dp_hot),
1288 	FUNCTION(gcc_gp1),
1289 	FUNCTION(gcc_gp2),
1290 	FUNCTION(gcc_gp3),
1291 	FUNCTION(ibi_i3c),
1292 	FUNCTION(jitter_bist),
1293 	FUNCTION(mdp_vsync),
1294 	FUNCTION(mdp_vsync0),
1295 	FUNCTION(mdp_vsync1),
1296 	FUNCTION(mdp_vsync2),
1297 	FUNCTION(mdp_vsync3),
1298 	FUNCTION(mi2s0_data0),
1299 	FUNCTION(mi2s0_data1),
1300 	FUNCTION(mi2s0_sck),
1301 	FUNCTION(mi2s0_ws),
1302 	FUNCTION(mi2s2_data0),
1303 	FUNCTION(mi2s2_data1),
1304 	FUNCTION(mi2s2_sck),
1305 	FUNCTION(mi2s2_ws),
1306 	FUNCTION(mss_grfc0),
1307 	FUNCTION(mss_grfc1),
1308 	FUNCTION(mss_grfc10),
1309 	FUNCTION(mss_grfc11),
1310 	FUNCTION(mss_grfc12),
1311 	FUNCTION(mss_grfc2),
1312 	FUNCTION(mss_grfc3),
1313 	FUNCTION(mss_grfc4),
1314 	FUNCTION(mss_grfc5),
1315 	FUNCTION(mss_grfc6),
1316 	FUNCTION(mss_grfc7),
1317 	FUNCTION(mss_grfc8),
1318 	FUNCTION(mss_grfc9),
1319 	FUNCTION(nav),
1320 	FUNCTION(pcie0_clkreqn),
1321 	FUNCTION(pcie1_clkreqn),
1322 	FUNCTION(phase_flag),
1323 	FUNCTION(pll_bist),
1324 	FUNCTION(pll_clk),
1325 	FUNCTION(pri_mi2s),
1326 	FUNCTION(prng_rosc),
1327 	FUNCTION(qdss_cti),
1328 	FUNCTION(qdss_gpio),
1329 	FUNCTION(qlink0_enable),
1330 	FUNCTION(qlink0_request),
1331 	FUNCTION(qlink0_wmss),
1332 	FUNCTION(qlink1_enable),
1333 	FUNCTION(qlink1_request),
1334 	FUNCTION(qlink1_wmss),
1335 	FUNCTION(qlink2_enable),
1336 	FUNCTION(qlink2_request),
1337 	FUNCTION(qlink2_wmss),
1338 	FUNCTION(qspi0),
1339 	FUNCTION(qspi1),
1340 	FUNCTION(qspi2),
1341 	FUNCTION(qspi3),
1342 	FUNCTION(qspi_clk),
1343 	FUNCTION(qspi_cs),
1344 	FUNCTION(qup0),
1345 	FUNCTION(qup1),
1346 	FUNCTION(qup10),
1347 	FUNCTION(qup11),
1348 	FUNCTION(qup12),
1349 	FUNCTION(qup13),
1350 	FUNCTION(qup14),
1351 	FUNCTION(qup15),
1352 	FUNCTION(qup16),
1353 	FUNCTION(qup17),
1354 	FUNCTION(qup18),
1355 	FUNCTION(qup19),
1356 	FUNCTION(qup2),
1357 	FUNCTION(qup20),
1358 	FUNCTION(qup21),
1359 	FUNCTION(qup3),
1360 	FUNCTION(qup4),
1361 	FUNCTION(qup5),
1362 	FUNCTION(qup6),
1363 	FUNCTION(qup7),
1364 	FUNCTION(qup8),
1365 	FUNCTION(qup9),
1366 	FUNCTION(qup_l4),
1367 	FUNCTION(qup_l5),
1368 	FUNCTION(qup_l6),
1369 	FUNCTION(sd_write),
1370 	FUNCTION(sdc40),
1371 	FUNCTION(sdc41),
1372 	FUNCTION(sdc42),
1373 	FUNCTION(sdc43),
1374 	FUNCTION(sdc4_clk),
1375 	FUNCTION(sdc4_cmd),
1376 	FUNCTION(sec_mi2s),
1377 	FUNCTION(tb_trig),
1378 	FUNCTION(tgu_ch0),
1379 	FUNCTION(tgu_ch1),
1380 	FUNCTION(tgu_ch2),
1381 	FUNCTION(tgu_ch3),
1382 	FUNCTION(tmess_prng0),
1383 	FUNCTION(tmess_prng1),
1384 	FUNCTION(tmess_prng2),
1385 	FUNCTION(tmess_prng3),
1386 	FUNCTION(tsense_pwm1),
1387 	FUNCTION(tsense_pwm2),
1388 	FUNCTION(uim0_clk),
1389 	FUNCTION(uim0_data),
1390 	FUNCTION(uim0_present),
1391 	FUNCTION(uim0_reset),
1392 	FUNCTION(uim1_clk),
1393 	FUNCTION(uim1_data),
1394 	FUNCTION(uim1_present),
1395 	FUNCTION(uim1_reset),
1396 	FUNCTION(usb2phy_ac),
1397 	FUNCTION(usb_phy),
1398 	FUNCTION(vfr_0),
1399 	FUNCTION(vfr_1),
1400 	FUNCTION(vsense_trigger),
1401 };
1402 
1403 /* Every pin is maintained as a single group, and missing or non-existing pin
1404  * would be maintained as dummy group to synchronize pin group index with
1405  * pin descriptor registered with pinctrl core.
1406  * Clients would not be able to request these dummy pin groups.
1407  */
1408 static const struct msm_pingroup sm8450_groups[] = {
1409 	[0] = PINGROUP(0, qup0, _, _, _, _, _, _, _, _),
1410 	[1] = PINGROUP(1, qup0, _, _, _, _, _, _, _, _),
1411 	[2] = PINGROUP(2, qup0, qdss_cti, _, _, _, _, _, _, _),
1412 	[3] = PINGROUP(3, qup0, _, _, _, _, _, _, _, _),
1413 	[4] = PINGROUP(4, qup1, phase_flag, _, _, _, _, _, _, _),
1414 	[5] = PINGROUP(5, qup1, phase_flag, _, _, _, _, _, _, _),
1415 	[6] = PINGROUP(6, qup1, phase_flag, _, _, _, _, _, _, _),
1416 	[7] = PINGROUP(7, qup1, phase_flag, _, _, _, _, _, _, _),
1417 	[8] = PINGROUP(8, qup2, _, _, _, _, _, _, _, _),
1418 	[9] = PINGROUP(9, qup2, dbg_out, _, _, _, _, _, _, _),
1419 	[10] = PINGROUP(10, qup2, phase_flag, _, _, _, _, _, _, _),
1420 	[11] = PINGROUP(11, qup2, phase_flag, _, _, _, _, _, _, _),
1421 	[12] = PINGROUP(12, qup3, phase_flag, _, _, _, _, _, _, _),
1422 	[13] = PINGROUP(13, qup3, phase_flag, _, _, _, _, _, _, _),
1423 	[14] = PINGROUP(14, qup3, phase_flag, _, _, _, _, _, _, _),
1424 	[15] = PINGROUP(15, qup3, phase_flag, _, _, _, _, _, _, _),
1425 	[16] = PINGROUP(16, qup4, phase_flag, _, _, _, _, _, _, _),
1426 	[17] = PINGROUP(17, qup4, phase_flag, _, _, _, _, _, _, _),
1427 	[18] = PINGROUP(18, qup4, phase_flag, _, vsense_trigger, _, _, _, _, _),
1428 	[19] = PINGROUP(19, qup4, phase_flag, _, _, _, _, _, _, _),
1429 	[20] = PINGROUP(20, qup6, pll_bist, _, _, _, _, _, _, _),
1430 	[21] = PINGROUP(21, qup6, _, _, _, _, _, _, _, _),
1431 	[22] = PINGROUP(22, qup6, _, _, _, _, _, _, _, _),
1432 	[23] = PINGROUP(23, qup6, _, _, _, _, _, _, _, _),
1433 	[24] = PINGROUP(24, qup7, qup_l4, jitter_bist, _, _, _, _, _, _),
1434 	[25] = PINGROUP(25, qup7, qup_l5, phase_flag, _, _, _, _, _, _),
1435 	[26] = PINGROUP(26, qup7, qup_l6, phase_flag, _, _, _, _, _, _),
1436 	[27] = PINGROUP(27, qup7, _, _, _, _, _, _, _, _),
1437 	[28] = PINGROUP(28, qup8, ibi_i3c, _, _, _, _, _, _, _),
1438 	[29] = PINGROUP(29, qup8, ibi_i3c, _, _, _, _, _, _, _),
1439 	[30] = PINGROUP(30, qup8, _, _, _, _, _, _, _, _),
1440 	[31] = PINGROUP(31, qup8, _, _, _, _, _, _, _, _),
1441 	[32] = PINGROUP(32, qup9, ibi_i3c, _, _, _, _, _, _, _),
1442 	[33] = PINGROUP(33, qup9, ibi_i3c, _, _, _, _, _, _, _),
1443 	[34] = PINGROUP(34, qup9, _, _, _, _, _, _, _, _),
1444 	[35] = PINGROUP(35, qup9, _, _, _, _, _, _, _, _),
1445 	[36] = PINGROUP(36, qup10, ddr_bist, _, _, _, _, _, _, _),
1446 	[37] = PINGROUP(37, qup10, ddr_bist, atest_usb, _, _, _, _, _, _),
1447 	[38] = PINGROUP(38, qup10, _, _, _, _, _, _, _, _),
1448 	[39] = PINGROUP(39, qup10, atest_usb, _, _, _, _, _, _, _),
1449 	[40] = PINGROUP(40, qup11, qup_l4, ddr_bist, ddr_pxi1, _, _, _, _, _),
1450 	[41] = PINGROUP(41, qup11, qup_l5, ddr_bist, ddr_pxi1, _, _, _, _, _),
1451 	[42] = PINGROUP(42, qup11, qup_l6, _, _, _, _, _, _, _),
1452 	[43] = PINGROUP(43, qup11, ddr_pxi3, _, _, _, _, _, _, _),
1453 	[44] = PINGROUP(44, qup12, ddr_pxi3, _, _, _, _, _, _, _),
1454 	[45] = PINGROUP(45, qup12, ddr_pxi2, _, _, _, _, _, _, _),
1455 	[46] = PINGROUP(46, qup12, mdp_vsync, _, _, _, _, _, _, _),
1456 	[47] = PINGROUP(47, qup12, dp_hot, mdp_vsync, ddr_pxi2, _, _, _, _, _),
1457 	[48] = PINGROUP(48, qup13, qspi2, sdc42, _, _, _, _, _, _),
1458 	[49] = PINGROUP(49, qup13, qspi3, sdc43, _, _, _, _, _, _),
1459 	[50] = PINGROUP(50, qup13, qspi_clk, sdc4_clk, _, _, _, _, _, _),
1460 	[51] = PINGROUP(51, qup13, qspi_cs, sdc4_cmd, ddr_pxi0, _, _, _, _, _),
1461 	[52] = PINGROUP(52, qup14, qspi0, sdc40, ddr_pxi0, _, _, _, _, _),
1462 	[53] = PINGROUP(53, qup14, qspi1, sdc41, _, _, _, _, _, _),
1463 	[54] = PINGROUP(54, qup14, qspi_cs, _, _, _, _, _, _, _),
1464 	[55] = PINGROUP(55, qup14, atest_usb, _, _, _, _, _, _, _),
1465 	[56] = PINGROUP(56, qup15, ibi_i3c, _, _, _, _, _, _, _),
1466 	[57] = PINGROUP(57, qup15, ibi_i3c, _, _, _, _, _, _, _),
1467 	[58] = PINGROUP(58, qup15, qup_l4, _, _, _, _, _, _, _),
1468 	[59] = PINGROUP(59, qup15, qup_l5, _, _, _, _, _, _, _),
1469 	[60] = PINGROUP(60, qup16, ibi_i3c, _, _, _, _, _, _, _),
1470 	[61] = PINGROUP(61, qup16, ibi_i3c, _, _, _, _, _, _, _),
1471 	[62] = PINGROUP(62, qup16, qup_l6, _, _, _, _, _, _, _),
1472 	[63] = PINGROUP(63, qup16, qup_l4, _, _, _, _, _, _, _),
1473 	[64] = PINGROUP(64, qup17, tb_trig, tgu_ch0, _, _, _, _, _, _),
1474 	[65] = PINGROUP(65, qup17, tgu_ch1, _, _, _, _, _, _, _),
1475 	[66] = PINGROUP(66, qup17, qup_l5, tgu_ch2, _, _, _, _, _, _),
1476 	[67] = PINGROUP(67, qup17, qup_l6, tgu_ch3, _, _, _, _, _, _),
1477 	[68] = PINGROUP(68, qup18, _, _, _, _, _, _, _, _),
1478 	[69] = PINGROUP(69, qup18, _, _, _, _, _, _, _, _),
1479 	[70] = PINGROUP(70, qup18, _, _, _, _, _, _, _, _),
1480 	[71] = PINGROUP(71, qup18, cri_trng0, _, _, _, _, _, _, _),
1481 	[72] = PINGROUP(72, qup19, cri_trng1, _, _, _, _, _, _, _),
1482 	[73] = PINGROUP(73, qup19, prng_rosc, _, _, _, _, _, _, _),
1483 	[74] = PINGROUP(74, qup19, _, _, _, _, _, _, _, _),
1484 	[75] = PINGROUP(75, qup19, prng_rosc, _, _, _, _, _, _, _),
1485 	[76] = PINGROUP(76, qup20, phase_flag, tmess_prng3, _, _, _, _, _, _),
1486 	[77] = PINGROUP(77, qup20, phase_flag, tmess_prng2, _, _, _, _,	_, _),
1487 	[78] = PINGROUP(78, qup20, phase_flag, _, _, _, _, _, _, _),
1488 	[79] = PINGROUP(79, qup20, phase_flag, tmess_prng1, _, _, _, _,	_, _),
1489 	[80] = PINGROUP(80, qup21, qdss_cti, phase_flag, tmess_prng0, _, _, _, _, _),
1490 	[81] = PINGROUP(81, qup21, qdss_cti, phase_flag, prng_rosc, _, _, _, _, _),
1491 	[82] = PINGROUP(82, qup21, qdss_cti, phase_flag, _, _, _, _, _, _),
1492 	[83] = PINGROUP(83, qup21, qdss_cti, phase_flag, prng_rosc, _, _, _, _, _),
1493 	[84] = PINGROUP(84, qup5, qdss_cti, _, _, _, _, _, _, _),
1494 	[85] = PINGROUP(85, qup5, qdss_cti, _, _, _, _, _, _, _),
1495 	[86] = PINGROUP(86, mdp_vsync, mdp_vsync0, mdp_vsync1, gcc_gp1, atest_char, _, _, _, _),
1496 	[87] = PINGROUP(87, mdp_vsync, mdp_vsync2, mdp_vsync3, gcc_gp2, atest_char, _, _, _, _),
1497 	[88] = PINGROUP(88, mdp_vsync, gcc_gp3, atest_char, _, _, _, _, _, _),
1498 	[89] = PINGROUP(89, vfr_0, atest_char, _, _, _, _, _, _, _),
1499 	[90] = PINGROUP(90, usb2phy_ac, atest_char, _, _, _, _, _, _, _),
1500 	[91] = PINGROUP(91, usb_phy, tsense_pwm1, tsense_pwm2, _, _, _, _, _, _),
1501 	[92] = PINGROUP(92, phase_flag, _, _, _, _, _, _, _, _),
1502 	[93] = PINGROUP(93, sd_write, qdss_cti, phase_flag, _, _, _, _, _, _),
1503 	[94] = PINGROUP(94, cmu_rng, phase_flag, _, _, _, _, _, _, _),
1504 	[95] = PINGROUP(95, pcie0_clkreqn, cmu_rng, phase_flag, _, _, _, _, _, _),
1505 	[96] = PINGROUP(96, cmu_rng, phase_flag, _, _, _, _, _, _, _),
1506 	[97] = PINGROUP(97, cmu_rng, phase_flag, _, _, _, _, _, _, _),
1507 	[98] = PINGROUP(98, pcie1_clkreqn, phase_flag, _, _, _, _, _, _, _),
1508 	[99] = PINGROUP(99, phase_flag, cri_trng, _, _, _, _, _, _, _),
1509 	[100] = PINGROUP(100, cam_mclk, qdss_gpio, _, _, _, _, _, _, _),
1510 	[101] = PINGROUP(101, cam_mclk, qdss_gpio, _, _, _, _, _, _, _),
1511 	[102] = PINGROUP(102, cam_mclk, qdss_gpio, _, _, _, _, _, _, _),
1512 	[103] = PINGROUP(103, cam_mclk, qdss_gpio, _, _, _, _, _, _, _),
1513 	[104] = PINGROUP(104, cam_mclk, qdss_gpio, _, _, _, _, _, _, _),
1514 	[105] = PINGROUP(105, cam_mclk, qdss_gpio, _, _, _, _, _, _, _),
1515 	[106] = PINGROUP(106, cam_mclk, qdss_gpio, _, _, _, _, _, _, _),
1516 	[107] = PINGROUP(107, cam_mclk, qdss_gpio, pll_clk, _, _, _, _, _, _),
1517 	[108] = PINGROUP(108, aon_cam, _, _, _, _, _, _, _, _),
1518 	[109] = PINGROUP(109, cci_async, _, _, _, _, _, _, _, _),
1519 	[110] = PINGROUP(110, cci_i2c, qdss_gpio, _, _, _, _, _, _, _),
1520 	[111] = PINGROUP(111, cci_i2c, qdss_gpio, _, _, _, _, _, _, _),
1521 	[112] = PINGROUP(112, cci_i2c, qdss_gpio, _, _, _, _, _, _, _),
1522 	[113] = PINGROUP(113, cci_i2c, qdss_gpio, _, _, _, _, _, _, _),
1523 	[114] = PINGROUP(114, cci_i2c, qdss_gpio, _, _, _, _, _, _, _),
1524 	[115] = PINGROUP(115, cci_i2c, qdss_gpio, _, _, _, _, _, _, _),
1525 	[116] = PINGROUP(116, cci_timer, _, _, _, _, _, _, _, _),
1526 	[117] = PINGROUP(117, cci_timer, qdss_gpio, _, _, _, _, _, _, _),
1527 	[118] = PINGROUP(118, cci_timer, qdss_gpio, _, _, _, _, _, _, _),
1528 	[119] = PINGROUP(119, cci_timer, cci_async, qdss_gpio, _, _, _, _, _, _),
1529 	[120] = PINGROUP(120, cci_timer, cci_async, qdss_gpio, _, _, _, _, _, _),
1530 	[121] = PINGROUP(121, mi2s2_sck, _, _, _, _, _, _, _, _),
1531 	[122] = PINGROUP(122, mi2s2_data0, _, _, _, _, _, _, _, _),
1532 	[123] = PINGROUP(123, mi2s2_ws, _, _, _, _, _, _, _, _),
1533 	[124] = PINGROUP(124, mi2s2_data1, sec_mi2s, audio_ref, _, _, _, _, _, _),
1534 	[125] = PINGROUP(125, pri_mi2s, _, _, _, _, _, _, _, _),
1535 	[126] = PINGROUP(126, mi2s0_sck, _, _, _, _, _, _, _, _),
1536 	[127] = PINGROUP(127, mi2s0_data0, _, _, _, _, _, _, _, _),
1537 	[128] = PINGROUP(128, mi2s0_data1, _, _, _, _, _, _, _, _),
1538 	[129] = PINGROUP(129, mi2s0_ws, _, _, _, _, _, _, _, _),
1539 	[130] = PINGROUP(130, uim0_data, _, _, _, _, _, _, _, _),
1540 	[131] = PINGROUP(131, uim0_clk, _, _, _, _, _, _, _, _),
1541 	[132] = PINGROUP(132, uim0_reset, _, _, _, _, _, _, _, _),
1542 	[133] = PINGROUP(133, uim0_present, _, _, _, _, _, _, _, _),
1543 	[134] = PINGROUP(134, uim1_data, gcc_gp1, _, _, _, _, _, _, _),
1544 	[135] = PINGROUP(135, uim1_clk, gcc_gp2, _, _, _, _, _, _, _),
1545 	[136] = PINGROUP(136, uim1_reset, gcc_gp3, _, _, _, _, _, _, _),
1546 	[137] = PINGROUP(137, uim1_present, tb_trig, _, _, _, _, _, _,  _),
1547 	[138] = PINGROUP(138, _, mss_grfc0, _, _, _, _, _, _, _),
1548 	[139] = PINGROUP(139, _, mss_grfc1, _, _, _, _, _, _, _),
1549 	[140] = PINGROUP(140, _, mss_grfc2, _, _, _, _, _, _, _),
1550 	[141] = PINGROUP(141, _, mss_grfc3, _, _, _, _, _, _, _),
1551 	[142] = PINGROUP(142, _, mss_grfc4, _, _, _, _, _, _, _),
1552 	[143] = PINGROUP(143, _, mss_grfc5, _, _, _, _, _, _, _),
1553 	[144] = PINGROUP(144, _, mss_grfc6, _, _, _, _, _, _, _),
1554 	[145] = PINGROUP(145, _, mss_grfc7, _, _, _, _, _, _, _),
1555 	[146] = PINGROUP(146, _, mss_grfc8, _, _, _, _, _, _, _),
1556 	[147] = PINGROUP(147, _, mss_grfc9, _, _, _, _, _, _, _),
1557 	[148] = PINGROUP(148, coex_uart1, atest_usb, _, _, _, _, _, _, _),
1558 	[149] = PINGROUP(149, coex_uart1, atest_usb, _, _, _, _, _, _, _),
1559 	[150] = PINGROUP(150, coex_uart2, mss_grfc10, _, _, _, _, _, _, _),
1560 	[151] = PINGROUP(151, coex_uart2, mss_grfc11, _, _, _, _, _, _, _),
1561 	[152] = PINGROUP(152, mss_grfc12, _, _, _, _, _, _, _, _),
1562 	[153] = PINGROUP(153, mss_grfc0, nav, _, _, _, _, _, _, _),
1563 	[154] = PINGROUP(154, nav, _, _, _, _, _, _, _, _),
1564 	[155] = PINGROUP(155, nav, vfr_1, _, _, _, _, _, _, _),
1565 	[156] = PINGROUP(156, qlink0_request, _, _, _, _, _, _, _, _),
1566 	[157] = PINGROUP(157, qlink0_enable, _, _, _, _, _, _, _, _),
1567 	[158] = PINGROUP(158, qlink0_wmss, _, _, _, _, _, _, _, _),
1568 	[159] = PINGROUP(159, qlink1_request, _, _, _, _, _, _, _, _),
1569 	[160] = PINGROUP(160, qlink1_enable, _, _, _, _, _, _, _, _),
1570 	[161] = PINGROUP(161, qlink1_wmss, _, _, _, _, _, _, _, _),
1571 	[162] = PINGROUP(162, qlink2_request, _, _, _, _, _, _, _, _),
1572 	[163] = PINGROUP(163, qlink2_enable, _, _, _, _, _, _, _, _),
1573 	[164] = PINGROUP(164, qlink2_wmss, _, _, _, _, _, _, _, _),
1574 	[165] = PINGROUP(165, _, _, _, _, _, _, _, _, _),
1575 	[166] = PINGROUP(166, _, _, _, _, _, _, _, _, _),
1576 	[167] = PINGROUP(167, _, _, _, _, _, _, _, _, _),
1577 	[168] = PINGROUP(168, _, _, _, _, _, _, _, _, _),
1578 	[169] = PINGROUP(169, _, _, _, _, _, _, _, _, _),
1579 	[170] = PINGROUP(170, _, _, _, _, _, _, _, _, _),
1580 	[171] = PINGROUP(171, _, _, _, _, _, _, _, _, _),
1581 	[172] = PINGROUP(172, _, _, _, _, _, _, _, _, _),
1582 	[173] = PINGROUP(173, _, _, _, _, _, _, _, _, _),
1583 	[174] = PINGROUP(174, _, _, _, _, _, _, _, _, _),
1584 	[175] = PINGROUP(175, _, _, _, _, _, _, _, _, _),
1585 	[176] = PINGROUP(176, _, _, _, _, _, _, _, _, _),
1586 	[177] = PINGROUP(177, _, _, _, _, _, _, _, _, _),
1587 	[178] = PINGROUP(178, _, _, _, _, _, _, _, _, _),
1588 	[179] = PINGROUP(179, _, _, _, _, _, _, _, _, _),
1589 	[180] = PINGROUP(180, _, _, _, _, _, _, _, _, _),
1590 	[181] = PINGROUP(181, _, _, _, _, _, _, _, _, _),
1591 	[182] = PINGROUP(182, _, _, _, _, _, _, _, _, _),
1592 	[183] = PINGROUP(183, _, _, _, _, _, _, _, _, _),
1593 	[184] = PINGROUP(184, _, _, _, _, _, _, _, _, _),
1594 	[185] = PINGROUP(185, _, _, _, _, _, _, _, _, _),
1595 	[186] = PINGROUP(186, _, _, _, _, _, _, _, _, _),
1596 	[187] = PINGROUP(187, _, _, _, _, _, _, _, _, _),
1597 	[188] = PINGROUP(188, _, qdss_gpio, _, _, _, _, _, _, _),
1598 	[189] = PINGROUP(189, _, qdss_gpio, _, _, _, _, _, _, _),
1599 	[190] = PINGROUP(190, qdss_gpio, _, _, _, _, _, _, _, _),
1600 	[191] = PINGROUP(191, qdss_gpio, _, _, _, _, _, _, _, _),
1601 	[192] = PINGROUP(192, _, qdss_gpio, _, _, _, _, _, _, _),
1602 	[193] = PINGROUP(193, _, qdss_gpio, _, _, _, _, _, _, _),
1603 	[194] = PINGROUP(194, _, qdss_gpio, _, _, _, _, _, _, _),
1604 	[195] = PINGROUP(195, _, qdss_gpio, _, _, _, _, _, _, _),
1605 	[196] = PINGROUP(196, _, qdss_gpio, _, _, _, _, _, _, _),
1606 	[197] = PINGROUP(197, _, qdss_gpio, _, _, _, _, _, _, _),
1607 	[198] = PINGROUP(198, _, qdss_gpio, _, _, _, _, _, _, _),
1608 	[199] = PINGROUP(199, _, qdss_gpio, _, _, _, _, _, _, _),
1609 	[200] = PINGROUP(200, _, qdss_gpio, _, _, _, _, _, _, _),
1610 	[201] = PINGROUP(201, _, qdss_gpio, _, _, _, _, _, _, _),
1611 	[202] = PINGROUP(202, qdss_gpio, _, _, _, _, _, _, _, _),
1612 	[203] = PINGROUP(203, qdss_gpio, _, _, _, _, _, _, _, _),
1613 	[204] = PINGROUP(204, qdss_gpio, _, _, _, _, _, _, _, _),
1614 	[205] = PINGROUP(205, qdss_gpio, _, _, _, _, _, _, _, _),
1615 	[206] = PINGROUP(206, qup5, _, _, _, _, _, _, _, _),
1616 	[207] = PINGROUP(207, qup5, _, _, _, _, _, _, _, _),
1617 	[208] = PINGROUP(208, cci_i2c, _, _, _, _, _, _, _, _),
1618 	[209] = PINGROUP(209, cci_i2c, _, _, _, _, _, _, _, _),
1619 	[210] = UFS_RESET(ufs_reset, 0xde000),
1620 	[211] = SDC_QDSD_PINGROUP(sdc2_clk, 0xd6000, 14, 6),
1621 	[212] = SDC_QDSD_PINGROUP(sdc2_cmd, 0xd6000, 11, 3),
1622 	[213] = SDC_QDSD_PINGROUP(sdc2_data, 0xd6000, 9, 0),
1623 };
1624 
1625 static const struct msm_gpio_wakeirq_map sm8450_pdc_map[] = {
1626 	{ 2, 70 }, { 3, 77 }, { 7, 52 }, { 8, 108 }, { 10, 128 }, { 11, 53 },
1627 	{ 12, 129 }, { 13, 130 }, { 14, 131 }, { 15, 67 }, { 19, 69 }, { 21, 132 },
1628 	{ 23, 54 }, { 26, 56 }, { 27, 71 }, { 28, 57 }, { 31, 55 }, { 32, 58 },
1629 	{ 34, 72 }, { 35, 43 }, { 36, 78 }, { 38, 79 }, { 39, 62 }, { 40, 80 },
1630 	{ 41, 133 }, { 43, 81 }, { 44, 87 }, { 45, 134 }, { 46, 66 }, { 47, 63 },
1631 	{ 50, 88 }, { 51, 89 }, { 55, 90 }, { 56, 59 }, { 59, 82 }, { 60, 60 },
1632 	{ 62, 135 }, { 63, 91 }, { 66, 136 }, { 67, 44 }, { 69, 137 }, { 71, 97 },
1633 	{ 75, 73 }, { 79, 74 }, { 80, 96 }, { 81, 98 }, { 82, 45 }, { 83, 99 },
1634 	{ 84, 94 }, { 85, 100 }, { 86, 101 }, { 87, 102 }, { 88, 92 }, { 89, 83 },
1635 	{ 90, 84 }, { 91, 85 }, { 92, 46 }, { 95, 103 }, { 96, 104 }, { 98, 105 },
1636 	{ 99, 106 }, { 115, 95 }, { 116, 76 }, { 117, 75 }, { 118, 86 }, { 119, 93 },
1637 	{ 133, 47 }, { 137, 42 }, { 148, 61 }, { 150, 68 }, { 153, 65 }, { 154, 48 },
1638 	{ 155, 49 }, { 156, 64 }, { 159, 50 }, { 162, 51 }, { 166, 111 }, { 169, 114 },
1639 	{ 171, 115 }, { 172, 116 }, { 174, 117 }, { 176, 107 }, { 181, 109 },
1640 	{ 182, 110 }, { 185, 112 }, { 187, 113 }, { 188, 118 }, { 190, 122 },
1641 	{ 192, 123 }, { 195, 124 }, { 201, 119 }, { 203, 120 }, { 205, 121 },
1642 };
1643 
1644 static const struct msm_pinctrl_soc_data sm8450_tlmm = {
1645 	.pins = sm8450_pins,
1646 	.npins = ARRAY_SIZE(sm8450_pins),
1647 	.functions = sm8450_functions,
1648 	.nfunctions = ARRAY_SIZE(sm8450_functions),
1649 	.groups = sm8450_groups,
1650 	.ngroups = ARRAY_SIZE(sm8450_groups),
1651 	.ngpios = 211,
1652 	.wakeirq_map = sm8450_pdc_map,
1653 	.nwakeirq_map = ARRAY_SIZE(sm8450_pdc_map),
1654 };
1655 
1656 static int sm8450_tlmm_probe(struct platform_device *pdev)
1657 {
1658 	return msm_pinctrl_probe(pdev, &sm8450_tlmm);
1659 }
1660 
1661 static const struct of_device_id sm8450_tlmm_of_match[] = {
1662 	{ .compatible = "qcom,sm8450-tlmm", },
1663 	{ },
1664 };
1665 
1666 static struct platform_driver sm8450_tlmm_driver = {
1667 	.driver = {
1668 		.name = "sm8450-tlmm",
1669 		.of_match_table = sm8450_tlmm_of_match,
1670 	},
1671 	.probe = sm8450_tlmm_probe,
1672 	.remove = msm_pinctrl_remove,
1673 };
1674 
1675 static int __init sm8450_tlmm_init(void)
1676 {
1677 	return platform_driver_register(&sm8450_tlmm_driver);
1678 }
1679 arch_initcall(sm8450_tlmm_init);
1680 
1681 static void __exit sm8450_tlmm_exit(void)
1682 {
1683 	platform_driver_unregister(&sm8450_tlmm_driver);
1684 }
1685 module_exit(sm8450_tlmm_exit);
1686 
1687 MODULE_DESCRIPTION("QTI SM8450 TLMM driver");
1688 MODULE_LICENSE("GPL v2");
1689 MODULE_DEVICE_TABLE(of, sm8450_tlmm_of_match);
1690