1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2018, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2023, Danila Tikhonov <danila@jiaxyga.com> 5 */ 6 7 #include <linux/module.h> 8 #include <linux/of.h> 9 #include <linux/platform_device.h> 10 #include <linux/pinctrl/pinctrl.h> 11 12 #include "pinctrl-msm.h" 13 14 static const char * const sm7150_tiles[] = { 15 "north", 16 "south", 17 "west", 18 }; 19 20 enum { 21 NORTH, 22 SOUTH, 23 WEST 24 }; 25 26 #define FUNCTION(fname) \ 27 [msm_mux_##fname] = { \ 28 .name = #fname, \ 29 .groups = fname##_groups, \ 30 .ngroups = ARRAY_SIZE(fname##_groups), \ 31 } 32 33 #define REG_SIZE 0x1000 34 35 #define PINGROUP(id, _tile, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ 36 { \ 37 .name = "gpio" #id, \ 38 .pins = gpio##id##_pins, \ 39 .npins = ARRAY_SIZE(gpio##id##_pins), \ 40 .funcs = (int[]){ \ 41 msm_mux_gpio, /* gpio mode */ \ 42 msm_mux_##f1, \ 43 msm_mux_##f2, \ 44 msm_mux_##f3, \ 45 msm_mux_##f4, \ 46 msm_mux_##f5, \ 47 msm_mux_##f6, \ 48 msm_mux_##f7, \ 49 msm_mux_##f8, \ 50 msm_mux_##f9 \ 51 }, \ 52 .nfuncs = 10, \ 53 .ctl_reg = REG_SIZE * id, \ 54 .io_reg = 0x4 + REG_SIZE * id, \ 55 .intr_cfg_reg = 0x8 + REG_SIZE * id, \ 56 .intr_status_reg = 0xc + REG_SIZE * id, \ 57 .intr_target_reg = 0x8 + REG_SIZE * id, \ 58 .tile = _tile, \ 59 .mux_bit = 2, \ 60 .pull_bit = 0, \ 61 .drv_bit = 6, \ 62 .oe_bit = 9, \ 63 .in_bit = 0, \ 64 .out_bit = 1, \ 65 .intr_enable_bit = 0, \ 66 .intr_status_bit = 0, \ 67 .intr_target_bit = 5, \ 68 .intr_target_kpss_val = 3, \ 69 .intr_raw_status_bit = 4, \ 70 .intr_polarity_bit = 1, \ 71 .intr_detection_bit = 2, \ 72 .intr_detection_width = 2, \ 73 } 74 75 #define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \ 76 { \ 77 .name = #pg_name, \ 78 .pins = pg_name##_pins, \ 79 .npins = ARRAY_SIZE(pg_name##_pins), \ 80 .ctl_reg = ctl, \ 81 .io_reg = 0, \ 82 .intr_cfg_reg = 0, \ 83 .intr_status_reg = 0, \ 84 .intr_target_reg = 0, \ 85 .tile = SOUTH, \ 86 .mux_bit = -1, \ 87 .pull_bit = pull, \ 88 .drv_bit = drv, \ 89 .oe_bit = -1, \ 90 .in_bit = -1, \ 91 .out_bit = -1, \ 92 .intr_enable_bit = -1, \ 93 .intr_status_bit = -1, \ 94 .intr_target_bit = -1, \ 95 .intr_raw_status_bit = -1, \ 96 .intr_polarity_bit = -1, \ 97 .intr_detection_bit = -1, \ 98 .intr_detection_width = -1, \ 99 } 100 101 #define UFS_RESET(pg_name, offset) \ 102 { \ 103 .name = #pg_name, \ 104 .pins = pg_name##_pins, \ 105 .npins = ARRAY_SIZE(pg_name##_pins), \ 106 .ctl_reg = offset, \ 107 .io_reg = offset + 0x4, \ 108 .intr_cfg_reg = 0, \ 109 .intr_status_reg = 0, \ 110 .intr_target_reg = 0, \ 111 .tile = SOUTH, \ 112 .mux_bit = -1, \ 113 .pull_bit = 3, \ 114 .drv_bit = 0, \ 115 .oe_bit = -1, \ 116 .in_bit = -1, \ 117 .out_bit = 0, \ 118 .intr_enable_bit = -1, \ 119 .intr_status_bit = -1, \ 120 .intr_target_bit = -1, \ 121 .intr_raw_status_bit = -1, \ 122 .intr_polarity_bit = -1, \ 123 .intr_detection_bit = -1, \ 124 .intr_detection_width = -1, \ 125 } 126 127 static const struct pinctrl_pin_desc sm7150_pins[] = { 128 PINCTRL_PIN(0, "GPIO_0"), 129 PINCTRL_PIN(1, "GPIO_1"), 130 PINCTRL_PIN(2, "GPIO_2"), 131 PINCTRL_PIN(3, "GPIO_3"), 132 PINCTRL_PIN(4, "GPIO_4"), 133 PINCTRL_PIN(5, "GPIO_5"), 134 PINCTRL_PIN(6, "GPIO_6"), 135 PINCTRL_PIN(7, "GPIO_7"), 136 PINCTRL_PIN(8, "GPIO_8"), 137 PINCTRL_PIN(9, "GPIO_9"), 138 PINCTRL_PIN(10, "GPIO_10"), 139 PINCTRL_PIN(11, "GPIO_11"), 140 PINCTRL_PIN(12, "GPIO_12"), 141 PINCTRL_PIN(13, "GPIO_13"), 142 PINCTRL_PIN(14, "GPIO_14"), 143 PINCTRL_PIN(15, "GPIO_15"), 144 PINCTRL_PIN(16, "GPIO_16"), 145 PINCTRL_PIN(17, "GPIO_17"), 146 PINCTRL_PIN(18, "GPIO_18"), 147 PINCTRL_PIN(19, "GPIO_19"), 148 PINCTRL_PIN(20, "GPIO_20"), 149 PINCTRL_PIN(21, "GPIO_21"), 150 PINCTRL_PIN(22, "GPIO_22"), 151 PINCTRL_PIN(23, "GPIO_23"), 152 PINCTRL_PIN(24, "GPIO_24"), 153 PINCTRL_PIN(25, "GPIO_25"), 154 PINCTRL_PIN(26, "GPIO_26"), 155 PINCTRL_PIN(27, "GPIO_27"), 156 PINCTRL_PIN(28, "GPIO_28"), 157 PINCTRL_PIN(29, "GPIO_29"), 158 PINCTRL_PIN(30, "GPIO_30"), 159 PINCTRL_PIN(31, "GPIO_31"), 160 PINCTRL_PIN(32, "GPIO_32"), 161 PINCTRL_PIN(33, "GPIO_33"), 162 PINCTRL_PIN(34, "GPIO_34"), 163 PINCTRL_PIN(35, "GPIO_35"), 164 PINCTRL_PIN(36, "GPIO_36"), 165 PINCTRL_PIN(37, "GPIO_37"), 166 PINCTRL_PIN(38, "GPIO_38"), 167 PINCTRL_PIN(39, "GPIO_39"), 168 PINCTRL_PIN(40, "GPIO_40"), 169 PINCTRL_PIN(41, "GPIO_41"), 170 PINCTRL_PIN(42, "GPIO_42"), 171 PINCTRL_PIN(43, "GPIO_43"), 172 PINCTRL_PIN(44, "GPIO_44"), 173 PINCTRL_PIN(45, "GPIO_45"), 174 PINCTRL_PIN(46, "GPIO_46"), 175 PINCTRL_PIN(47, "GPIO_47"), 176 PINCTRL_PIN(48, "GPIO_48"), 177 PINCTRL_PIN(49, "GPIO_49"), 178 PINCTRL_PIN(50, "GPIO_50"), 179 PINCTRL_PIN(51, "GPIO_51"), 180 PINCTRL_PIN(52, "GPIO_52"), 181 PINCTRL_PIN(53, "GPIO_53"), 182 PINCTRL_PIN(54, "GPIO_54"), 183 PINCTRL_PIN(55, "GPIO_55"), 184 PINCTRL_PIN(56, "GPIO_56"), 185 PINCTRL_PIN(57, "GPIO_57"), 186 PINCTRL_PIN(58, "GPIO_58"), 187 PINCTRL_PIN(59, "GPIO_59"), 188 PINCTRL_PIN(60, "GPIO_60"), 189 PINCTRL_PIN(61, "GPIO_61"), 190 PINCTRL_PIN(62, "GPIO_62"), 191 PINCTRL_PIN(63, "GPIO_63"), 192 PINCTRL_PIN(64, "GPIO_64"), 193 PINCTRL_PIN(65, "GPIO_65"), 194 PINCTRL_PIN(66, "GPIO_66"), 195 PINCTRL_PIN(67, "GPIO_67"), 196 PINCTRL_PIN(68, "GPIO_68"), 197 PINCTRL_PIN(69, "GPIO_69"), 198 PINCTRL_PIN(70, "GPIO_70"), 199 PINCTRL_PIN(71, "GPIO_71"), 200 PINCTRL_PIN(72, "GPIO_72"), 201 PINCTRL_PIN(73, "GPIO_73"), 202 PINCTRL_PIN(74, "GPIO_74"), 203 PINCTRL_PIN(75, "GPIO_75"), 204 PINCTRL_PIN(76, "GPIO_76"), 205 PINCTRL_PIN(77, "GPIO_77"), 206 PINCTRL_PIN(78, "GPIO_78"), 207 PINCTRL_PIN(79, "GPIO_79"), 208 PINCTRL_PIN(80, "GPIO_80"), 209 PINCTRL_PIN(81, "GPIO_81"), 210 PINCTRL_PIN(82, "GPIO_82"), 211 PINCTRL_PIN(83, "GPIO_83"), 212 PINCTRL_PIN(84, "GPIO_84"), 213 PINCTRL_PIN(85, "GPIO_85"), 214 PINCTRL_PIN(86, "GPIO_86"), 215 PINCTRL_PIN(87, "GPIO_87"), 216 PINCTRL_PIN(88, "GPIO_88"), 217 PINCTRL_PIN(89, "GPIO_89"), 218 PINCTRL_PIN(90, "GPIO_90"), 219 PINCTRL_PIN(91, "GPIO_91"), 220 PINCTRL_PIN(92, "GPIO_92"), 221 PINCTRL_PIN(93, "GPIO_93"), 222 PINCTRL_PIN(94, "GPIO_94"), 223 PINCTRL_PIN(95, "GPIO_95"), 224 PINCTRL_PIN(96, "GPIO_96"), 225 PINCTRL_PIN(97, "GPIO_97"), 226 PINCTRL_PIN(98, "GPIO_98"), 227 PINCTRL_PIN(99, "GPIO_99"), 228 PINCTRL_PIN(100, "GPIO_100"), 229 PINCTRL_PIN(101, "GPIO_101"), 230 PINCTRL_PIN(102, "GPIO_102"), 231 PINCTRL_PIN(103, "GPIO_103"), 232 PINCTRL_PIN(104, "GPIO_104"), 233 PINCTRL_PIN(105, "GPIO_105"), 234 PINCTRL_PIN(106, "GPIO_106"), 235 PINCTRL_PIN(107, "GPIO_107"), 236 PINCTRL_PIN(108, "GPIO_108"), 237 PINCTRL_PIN(109, "GPIO_109"), 238 PINCTRL_PIN(110, "GPIO_110"), 239 PINCTRL_PIN(111, "GPIO_111"), 240 PINCTRL_PIN(112, "GPIO_112"), 241 PINCTRL_PIN(113, "GPIO_113"), 242 PINCTRL_PIN(114, "GPIO_114"), 243 PINCTRL_PIN(115, "GPIO_115"), 244 PINCTRL_PIN(116, "GPIO_116"), 245 PINCTRL_PIN(117, "GPIO_117"), 246 PINCTRL_PIN(118, "GPIO_118"), 247 PINCTRL_PIN(119, "UFS_RESET"), 248 PINCTRL_PIN(120, "SDC1_RCLK"), 249 PINCTRL_PIN(121, "SDC1_CLK"), 250 PINCTRL_PIN(122, "SDC1_CMD"), 251 PINCTRL_PIN(123, "SDC1_DATA"), 252 PINCTRL_PIN(124, "SDC2_CLK"), 253 PINCTRL_PIN(125, "SDC2_CMD"), 254 PINCTRL_PIN(126, "SDC2_DATA"), 255 256 }; 257 258 #define DECLARE_MSM_GPIO_PINS(pin) \ 259 static const unsigned int gpio##pin##_pins[] = { pin } 260 DECLARE_MSM_GPIO_PINS(0); 261 DECLARE_MSM_GPIO_PINS(1); 262 DECLARE_MSM_GPIO_PINS(2); 263 DECLARE_MSM_GPIO_PINS(3); 264 DECLARE_MSM_GPIO_PINS(4); 265 DECLARE_MSM_GPIO_PINS(5); 266 DECLARE_MSM_GPIO_PINS(6); 267 DECLARE_MSM_GPIO_PINS(7); 268 DECLARE_MSM_GPIO_PINS(8); 269 DECLARE_MSM_GPIO_PINS(9); 270 DECLARE_MSM_GPIO_PINS(10); 271 DECLARE_MSM_GPIO_PINS(11); 272 DECLARE_MSM_GPIO_PINS(12); 273 DECLARE_MSM_GPIO_PINS(13); 274 DECLARE_MSM_GPIO_PINS(14); 275 DECLARE_MSM_GPIO_PINS(15); 276 DECLARE_MSM_GPIO_PINS(16); 277 DECLARE_MSM_GPIO_PINS(17); 278 DECLARE_MSM_GPIO_PINS(18); 279 DECLARE_MSM_GPIO_PINS(19); 280 DECLARE_MSM_GPIO_PINS(20); 281 DECLARE_MSM_GPIO_PINS(21); 282 DECLARE_MSM_GPIO_PINS(22); 283 DECLARE_MSM_GPIO_PINS(23); 284 DECLARE_MSM_GPIO_PINS(24); 285 DECLARE_MSM_GPIO_PINS(25); 286 DECLARE_MSM_GPIO_PINS(26); 287 DECLARE_MSM_GPIO_PINS(27); 288 DECLARE_MSM_GPIO_PINS(28); 289 DECLARE_MSM_GPIO_PINS(29); 290 DECLARE_MSM_GPIO_PINS(30); 291 DECLARE_MSM_GPIO_PINS(31); 292 DECLARE_MSM_GPIO_PINS(32); 293 DECLARE_MSM_GPIO_PINS(33); 294 DECLARE_MSM_GPIO_PINS(34); 295 DECLARE_MSM_GPIO_PINS(35); 296 DECLARE_MSM_GPIO_PINS(36); 297 DECLARE_MSM_GPIO_PINS(37); 298 DECLARE_MSM_GPIO_PINS(38); 299 DECLARE_MSM_GPIO_PINS(39); 300 DECLARE_MSM_GPIO_PINS(40); 301 DECLARE_MSM_GPIO_PINS(41); 302 DECLARE_MSM_GPIO_PINS(42); 303 DECLARE_MSM_GPIO_PINS(43); 304 DECLARE_MSM_GPIO_PINS(44); 305 DECLARE_MSM_GPIO_PINS(45); 306 DECLARE_MSM_GPIO_PINS(46); 307 DECLARE_MSM_GPIO_PINS(47); 308 DECLARE_MSM_GPIO_PINS(48); 309 DECLARE_MSM_GPIO_PINS(49); 310 DECLARE_MSM_GPIO_PINS(50); 311 DECLARE_MSM_GPIO_PINS(51); 312 DECLARE_MSM_GPIO_PINS(52); 313 DECLARE_MSM_GPIO_PINS(53); 314 DECLARE_MSM_GPIO_PINS(54); 315 DECLARE_MSM_GPIO_PINS(55); 316 DECLARE_MSM_GPIO_PINS(56); 317 DECLARE_MSM_GPIO_PINS(57); 318 DECLARE_MSM_GPIO_PINS(58); 319 DECLARE_MSM_GPIO_PINS(59); 320 DECLARE_MSM_GPIO_PINS(60); 321 DECLARE_MSM_GPIO_PINS(61); 322 DECLARE_MSM_GPIO_PINS(62); 323 DECLARE_MSM_GPIO_PINS(63); 324 DECLARE_MSM_GPIO_PINS(64); 325 DECLARE_MSM_GPIO_PINS(65); 326 DECLARE_MSM_GPIO_PINS(66); 327 DECLARE_MSM_GPIO_PINS(67); 328 DECLARE_MSM_GPIO_PINS(68); 329 DECLARE_MSM_GPIO_PINS(69); 330 DECLARE_MSM_GPIO_PINS(70); 331 DECLARE_MSM_GPIO_PINS(71); 332 DECLARE_MSM_GPIO_PINS(72); 333 DECLARE_MSM_GPIO_PINS(73); 334 DECLARE_MSM_GPIO_PINS(74); 335 DECLARE_MSM_GPIO_PINS(75); 336 DECLARE_MSM_GPIO_PINS(76); 337 DECLARE_MSM_GPIO_PINS(77); 338 DECLARE_MSM_GPIO_PINS(78); 339 DECLARE_MSM_GPIO_PINS(79); 340 DECLARE_MSM_GPIO_PINS(80); 341 DECLARE_MSM_GPIO_PINS(81); 342 DECLARE_MSM_GPIO_PINS(82); 343 DECLARE_MSM_GPIO_PINS(83); 344 DECLARE_MSM_GPIO_PINS(84); 345 DECLARE_MSM_GPIO_PINS(85); 346 DECLARE_MSM_GPIO_PINS(86); 347 DECLARE_MSM_GPIO_PINS(87); 348 DECLARE_MSM_GPIO_PINS(88); 349 DECLARE_MSM_GPIO_PINS(89); 350 DECLARE_MSM_GPIO_PINS(90); 351 DECLARE_MSM_GPIO_PINS(91); 352 DECLARE_MSM_GPIO_PINS(92); 353 DECLARE_MSM_GPIO_PINS(93); 354 DECLARE_MSM_GPIO_PINS(94); 355 DECLARE_MSM_GPIO_PINS(95); 356 DECLARE_MSM_GPIO_PINS(96); 357 DECLARE_MSM_GPIO_PINS(97); 358 DECLARE_MSM_GPIO_PINS(98); 359 DECLARE_MSM_GPIO_PINS(99); 360 DECLARE_MSM_GPIO_PINS(100); 361 DECLARE_MSM_GPIO_PINS(101); 362 DECLARE_MSM_GPIO_PINS(102); 363 DECLARE_MSM_GPIO_PINS(103); 364 DECLARE_MSM_GPIO_PINS(104); 365 DECLARE_MSM_GPIO_PINS(105); 366 DECLARE_MSM_GPIO_PINS(106); 367 DECLARE_MSM_GPIO_PINS(107); 368 DECLARE_MSM_GPIO_PINS(108); 369 DECLARE_MSM_GPIO_PINS(109); 370 DECLARE_MSM_GPIO_PINS(110); 371 DECLARE_MSM_GPIO_PINS(111); 372 DECLARE_MSM_GPIO_PINS(112); 373 DECLARE_MSM_GPIO_PINS(113); 374 DECLARE_MSM_GPIO_PINS(114); 375 DECLARE_MSM_GPIO_PINS(115); 376 DECLARE_MSM_GPIO_PINS(116); 377 DECLARE_MSM_GPIO_PINS(117); 378 DECLARE_MSM_GPIO_PINS(118); 379 380 static const unsigned int ufs_reset_pins[] = { 119 }; 381 static const unsigned int sdc1_rclk_pins[] = { 120 }; 382 static const unsigned int sdc1_clk_pins[] = { 121 }; 383 static const unsigned int sdc1_cmd_pins[] = { 122 }; 384 static const unsigned int sdc1_data_pins[] = { 123 }; 385 static const unsigned int sdc2_clk_pins[] = { 124 }; 386 static const unsigned int sdc2_cmd_pins[] = { 125 }; 387 static const unsigned int sdc2_data_pins[] = { 126 }; 388 389 enum sm7150_functions { 390 msm_mux_gpio, 391 msm_mux_adsp_ext, 392 msm_mux_agera_pll, 393 msm_mux_aoss_cti, 394 msm_mux_atest_char, 395 msm_mux_atest_tsens, 396 msm_mux_atest_tsens2, 397 msm_mux_atest_usb1, 398 msm_mux_atest_usb2, 399 msm_mux_cam_mclk, 400 msm_mux_cci_async, 401 msm_mux_cci_i2c, 402 msm_mux_cci_timer0, 403 msm_mux_cci_timer1, 404 msm_mux_cci_timer2, 405 msm_mux_cci_timer3, 406 msm_mux_cci_timer4, 407 msm_mux_dbg_out, 408 msm_mux_ddr_bist, 409 msm_mux_ddr_pxi0, 410 msm_mux_ddr_pxi1, 411 msm_mux_ddr_pxi2, 412 msm_mux_ddr_pxi3, 413 msm_mux_edp_hot, 414 msm_mux_edp_lcd, 415 msm_mux_gcc_gp1, 416 msm_mux_gcc_gp2, 417 msm_mux_gcc_gp3, 418 msm_mux_gp_pdm0, 419 msm_mux_gp_pdm1, 420 msm_mux_gp_pdm2, 421 msm_mux_gps_tx, 422 msm_mux_jitter_bist, 423 msm_mux_ldo_en, 424 msm_mux_ldo_update, 425 msm_mux_m_voc, 426 msm_mux_mdp_vsync, 427 msm_mux_mdp_vsync0, 428 msm_mux_mdp_vsync1, 429 msm_mux_mdp_vsync2, 430 msm_mux_mdp_vsync3, 431 msm_mux_mss_lte, 432 msm_mux_nav_pps_in, 433 msm_mux_nav_pps_out, 434 msm_mux_pa_indicator, 435 msm_mux_pci_e, 436 msm_mux_phase_flag, 437 msm_mux_pll_bist, 438 msm_mux_pll_bypassnl, 439 msm_mux_pll_reset, 440 msm_mux_pri_mi2s, 441 msm_mux_pri_mi2s_ws, 442 msm_mux_prng_rosc, 443 msm_mux_qdss, 444 msm_mux_qdss_cti, 445 msm_mux_qlink_enable, 446 msm_mux_qlink_request, 447 msm_mux_qua_mi2s, 448 msm_mux_qup00, 449 msm_mux_qup01, 450 msm_mux_qup02, 451 msm_mux_qup03, 452 msm_mux_qup04, 453 msm_mux_qup10, 454 msm_mux_qup11, 455 msm_mux_qup12, 456 msm_mux_qup13, 457 msm_mux_qup14, 458 msm_mux_qup15, 459 msm_mux_sd_write, 460 msm_mux_sdc40, 461 msm_mux_sdc41, 462 msm_mux_sdc42, 463 msm_mux_sdc43, 464 msm_mux_sdc4_clk, 465 msm_mux_sdc4_cmd, 466 msm_mux_sec_mi2s, 467 msm_mux_ter_mi2s, 468 msm_mux_tgu_ch0, 469 msm_mux_tgu_ch1, 470 msm_mux_tgu_ch2, 471 msm_mux_tgu_ch3, 472 msm_mux_tsif1_clk, 473 msm_mux_tsif1_data, 474 msm_mux_tsif1_en, 475 msm_mux_tsif1_error, 476 msm_mux_tsif1_sync, 477 msm_mux_tsif2_clk, 478 msm_mux_tsif2_data, 479 msm_mux_tsif2_en, 480 msm_mux_tsif2_error, 481 msm_mux_tsif2_sync, 482 msm_mux_uim1_clk, 483 msm_mux_uim1_data, 484 msm_mux_uim1_present, 485 msm_mux_uim1_reset, 486 msm_mux_uim2_clk, 487 msm_mux_uim2_data, 488 msm_mux_uim2_present, 489 msm_mux_uim2_reset, 490 msm_mux_uim_batt, 491 msm_mux_usb_phy, 492 msm_mux_vfr_1, 493 msm_mux_vsense_trigger, 494 msm_mux_wlan1_adc0, 495 msm_mux_wlan1_adc1, 496 msm_mux_wlan2_adc0, 497 msm_mux_wlan2_adc1, 498 msm_mux_wsa_clk, 499 msm_mux_wsa_data, 500 msm_mux__, 501 }; 502 503 static const char * const gpio_groups[] = { 504 "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", 505 "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", 506 "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", 507 "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", 508 "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", 509 "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", 510 "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", 511 "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", 512 "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", 513 "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", 514 "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", 515 "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", 516 "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", 517 "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", 518 "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", 519 "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", 520 "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116", 521 "gpio117", "gpio118", 522 }; 523 524 static const char * const adsp_ext_groups[] = { 525 "gpio87", 526 }; 527 528 static const char * const agera_pll_groups[] = { 529 "gpio28", 530 }; 531 532 static const char * const aoss_cti_groups[] = { 533 "gpio85", 534 }; 535 536 static const char * const atest_char_groups[] = { 537 "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", 538 }; 539 540 static const char * const atest_tsens_groups[] = { 541 "gpio29", 542 }; 543 544 static const char * const atest_tsens2_groups[] = { 545 "gpio7", 546 }; 547 548 static const char * const atest_usb1_groups[] = { 549 "gpio7", "gpio10", "gpio11", "gpio39", "gpio44", 550 }; 551 552 static const char * const atest_usb2_groups[] = { 553 "gpio51", "gpio52", "gpio53", "gpio54", "gpio55" 554 }; 555 556 static const char * const cam_mclk_groups[] = { 557 "gpio13", "gpio14", "gpio15", "gpio16", 558 }; 559 560 static const char * const cci_async_groups[] = { 561 "gpio24", "gpio25", "gpio26", 562 }; 563 564 static const char * const cci_i2c_groups[] = { 565 "gpio17", "gpio18", "gpio19", "gpio20", "gpio27", "gpio28", 566 }; 567 568 static const char * const cci_timer0_groups[] = { 569 "gpio21", 570 }; 571 572 static const char * const cci_timer1_groups[] = { 573 "gpio22", 574 }; 575 576 static const char * const cci_timer2_groups[] = { 577 "gpio23", 578 }; 579 580 static const char * const cci_timer3_groups[] = { 581 "gpio24", 582 }; 583 584 static const char * const cci_timer4_groups[] = { 585 "gpio25", 586 }; 587 588 static const char * const dbg_out_groups[] = { 589 "gpio3", 590 }; 591 592 static const char * const ddr_bist_groups[] = { 593 "gpio7", "gpio8", "gpio9", "gpio10", 594 }; 595 596 static const char * const ddr_pxi0_groups[] = { 597 "gpio6", "gpio7", 598 }; 599 600 static const char * const ddr_pxi1_groups[] = { 601 "gpio39", "gpio44", 602 }; 603 604 static const char * const ddr_pxi2_groups[] = { 605 "gpio10", "gpio11", 606 }; 607 608 static const char * const ddr_pxi3_groups[] = { 609 "gpio12", "gpio13", 610 }; 611 612 static const char * const edp_hot_groups[] = { 613 "gpio85", 614 }; 615 616 static const char * const edp_lcd_groups[] = { 617 "gpio11", 618 }; 619 620 static const char * const gcc_gp1_groups[] = { 621 "gpio48", "gpio56", 622 }; 623 624 static const char * const gcc_gp2_groups[] = { 625 "gpio21", 626 }; 627 628 static const char * const gcc_gp3_groups[] = { 629 "gpio22", 630 }; 631 632 static const char * const gp_pdm0_groups[] = { 633 "gpio37", "gpio68", 634 }; 635 636 static const char * const gp_pdm1_groups[] = { 637 "gpio8", "gpio50", 638 }; 639 640 static const char * const gp_pdm2_groups[] = { 641 "gpio57", 642 }; 643 644 static const char * const gps_tx_groups[] = { 645 "gpio83", "gpio84", "gpio107", "gpio109", 646 }; 647 648 static const char * const jitter_bist_groups[] = { 649 "gpio26", 650 }; 651 652 static const char * const ldo_en_groups[] = { 653 "gpio70", 654 }; 655 656 static const char * const ldo_update_groups[] = { 657 "gpio71", 658 }; 659 660 static const char * const m_voc_groups[] = { 661 "gpio12", 662 }; 663 664 static const char * const mdp_vsync_groups[] = { 665 "gpio10", "gpio11", "gpio12", "gpio70", "gpio71", 666 }; 667 668 static const char * const mdp_vsync0_groups[] = { 669 "gpio63", 670 }; 671 672 static const char * const mdp_vsync1_groups[] = { 673 "gpio63", 674 }; 675 676 static const char * const mdp_vsync2_groups[] = { 677 "gpio63", 678 }; 679 680 static const char * const mdp_vsync3_groups[] = { 681 "gpio63", 682 }; 683 684 static const char * const mss_lte_groups[] = { 685 "gpio108", "gpio109", 686 }; 687 688 static const char * const nav_pps_in_groups[] = { 689 "gpio83", "gpio84", "gpio107", 690 }; 691 692 static const char * const nav_pps_out_groups[] = { 693 "gpio83", "gpio84", "gpio107", 694 }; 695 696 static const char * const pa_indicator_groups[] = { 697 "gpio99", 698 }; 699 700 static const char * const pci_e_groups[] = { 701 "gpio66", "gpio67", "gpio68", 702 }; 703 704 static const char * const phase_flag_groups[] = { 705 "gpio0", "gpio1", "gpio2", "gpio6", "gpio7", "gpio10", "gpio11", 706 "gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17", "gpio24", 707 "gpio25", "gpio26", "gpio27", "gpio28", "gpio29", "gpio30", "gpio35", 708 "gpio36", "gpio37", "gpio38", "gpio39", "gpio43", "gpio44", "gpio56", 709 "gpio57", "gpio60", "gpio61", "gpio62", 710 }; 711 712 static const char * const pll_bist_groups[] = { 713 "gpio27", 714 }; 715 716 static const char * const pll_bypassnl_groups[] = { 717 "gpio13", 718 }; 719 720 static const char * const pll_reset_groups[] = { 721 "gpio14", 722 }; 723 724 static const char * const pri_mi2s_groups[] = { 725 "gpio49", "gpio51", "gpio52", 726 }; 727 728 static const char * const pri_mi2s_ws_groups[] = { 729 "gpio50", 730 }; 731 732 static const char * const prng_rosc_groups[] = { 733 "gpio72", 734 }; 735 736 static const char * const qdss_groups[] = { 737 "gpio13", "gpio86", "gpio14", "gpio87", "gpio15", "gpio88", "gpio16", 738 "gpio89", "gpio17", "gpio90", "gpio18", "gpio91", "gpio19", "gpio34", 739 "gpio20", "gpio35", "gpio21", "gpio53", "gpio22", "gpio30", "gpio23", 740 "gpio54", "gpio24", "gpio55", "gpio25", "gpio57", "gpio26", "gpio31", 741 "gpio27", "gpio56", "gpio28", "gpio36", "gpio29", "gpio37", "gpio93", 742 "gpio104", 743 }; 744 745 static const char * const qdss_cti_groups[] = { 746 "gpio4", "gpio5", "gpio32", "gpio44", "gpio45", "gpio63", 747 }; 748 749 static const char * const qlink_enable_groups[] = { 750 "gpio97", 751 }; 752 753 static const char * const qlink_request_groups[] = { 754 "gpio96", 755 }; 756 757 static const char * const qua_mi2s_groups[] = { 758 "gpio58", 759 }; 760 761 static const char * const qup00_groups[] = { 762 "gpio49", "gpio50", "gpio51", "gpio52", "gpio57", "gpio58", 763 }; 764 765 static const char * const qup01_groups[] = { 766 "gpio0", "gpio1", "gpio2", "gpio3", "gpio12", "gpio37", 767 }; 768 769 static const char * const qup02_groups[] = { 770 "gpio34", "gpio35", 771 }; 772 773 static const char * const qup03_groups[] = { 774 "gpio38", "gpio39", "gpio40", "gpio41", 775 }; 776 777 static const char * const qup04_groups[] = { 778 "gpio53", "gpio54", "gpio55", "gpio56", 779 }; 780 781 static const char * const qup10_groups[] = { 782 "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", "gpio64", "gpio65", 783 }; 784 785 static const char * const qup11_groups[] = { 786 "gpio6", "gpio7", "gpio8", "gpio9", 787 }; 788 789 static const char * const qup12_groups[] = { 790 "gpio42", "gpio43", "gpio44", "gpio45", 791 }; 792 793 static const char * const qup13_groups[] = { 794 "gpio46", "gpio47", 795 }; 796 797 static const char * const qup14_groups[] = { 798 "gpio110", "gpio111", "gpio112", "gpio113", 799 }; 800 801 static const char * const qup15_groups[] = { 802 "gpio92", "gpio101", "gpio102", "gpio103", 803 }; 804 805 static const char * const sd_write_groups[] = { 806 "gpio33", 807 }; 808 809 static const char * const sdc40_groups[] = { 810 "gpio69", 811 }; 812 813 static const char * const sdc41_groups[] = { 814 "gpio68", 815 }; 816 817 static const char * const sdc42_groups[] = { 818 "gpio67", 819 }; 820 821 static const char * const sdc43_groups[] = { 822 "gpio65", 823 }; 824 825 static const char * const sdc4_clk_groups[] = { 826 "gpio66", 827 }; 828 829 static const char * const sdc4_cmd_groups[] = { 830 "gpio64", 831 }; 832 833 static const char * const sec_mi2s_groups[] = { 834 "gpio57", 835 }; 836 837 static const char * const ter_mi2s_groups[] = { 838 "gpio53", "gpio54", "gpio55", "gpio56", 839 }; 840 841 static const char * const tgu_ch0_groups[] = { 842 "gpio63", 843 }; 844 845 static const char * const tgu_ch1_groups[] = { 846 "gpio64", 847 }; 848 849 static const char * const tgu_ch2_groups[] = { 850 "gpio65", 851 }; 852 853 static const char * const tgu_ch3_groups[] = { 854 "gpio62", 855 }; 856 857 static const char * const tsif1_clk_groups[] = { 858 "gpio62", 859 }; 860 861 static const char * const tsif1_data_groups[] = { 862 "gpio64", 863 }; 864 865 static const char * const tsif1_en_groups[] = { 866 "gpio63", 867 }; 868 869 static const char * const tsif1_error_groups[] = { 870 "gpio60", 871 }; 872 873 static const char * const tsif1_sync_groups[] = { 874 "gpio61", 875 }; 876 877 static const char * const tsif2_clk_groups[] = { 878 "gpio66", 879 }; 880 881 static const char * const tsif2_data_groups[] = { 882 "gpio68", 883 }; 884 885 static const char * const tsif2_en_groups[] = { 886 "gpio67", 887 }; 888 889 static const char * const tsif2_error_groups[] = { 890 "gpio65", 891 }; 892 893 static const char * const tsif2_sync_groups[] = { 894 "gpio69", 895 }; 896 897 static const char * const uim1_clk_groups[] = { 898 "gpio80", 899 }; 900 901 static const char * const uim1_data_groups[] = { 902 "gpio79", 903 }; 904 905 static const char * const uim1_present_groups[] = { 906 "gpio82", 907 }; 908 909 static const char * const uim1_reset_groups[] = { 910 "gpio81", 911 }; 912 913 static const char * const uim2_clk_groups[] = { 914 "gpio76", 915 }; 916 917 static const char * const uim2_data_groups[] = { 918 "gpio75", 919 }; 920 921 static const char * const uim2_present_groups[] = { 922 "gpio78", 923 }; 924 925 static const char * const uim2_reset_groups[] = { 926 "gpio77", 927 }; 928 929 static const char * const uim_batt_groups[] = { 930 "gpio85", 931 }; 932 933 static const char * const usb_phy_groups[] = { 934 "gpio104", 935 }; 936 937 static const char * const vfr_1_groups[] = { 938 "gpio65", 939 }; 940 941 static const char * const vsense_trigger_groups[] = { 942 "gpio7", 943 }; 944 945 static const char * const wlan1_adc0_groups[] = { 946 "gpio39", 947 }; 948 949 static const char * const wlan1_adc1_groups[] = { 950 "gpio44", 951 }; 952 953 static const char * const wlan2_adc0_groups[] = { 954 "gpio11", 955 }; 956 957 static const char * const wlan2_adc1_groups[] = { 958 "gpio10", 959 }; 960 961 static const char * const wsa_clk_groups[] = { 962 "gpio49", 963 }; 964 965 static const char * const wsa_data_groups[] = { 966 "gpio50", 967 }; 968 969 static const struct msm_function sm7150_functions[] = { 970 FUNCTION(gpio), 971 FUNCTION(adsp_ext), 972 FUNCTION(agera_pll), 973 FUNCTION(aoss_cti), 974 FUNCTION(atest_char), 975 FUNCTION(atest_tsens), 976 FUNCTION(atest_tsens2), 977 FUNCTION(atest_usb1), 978 FUNCTION(atest_usb2), 979 FUNCTION(cam_mclk), 980 FUNCTION(cci_async), 981 FUNCTION(cci_i2c), 982 FUNCTION(cci_timer0), 983 FUNCTION(cci_timer1), 984 FUNCTION(cci_timer2), 985 FUNCTION(cci_timer3), 986 FUNCTION(cci_timer4), 987 FUNCTION(dbg_out), 988 FUNCTION(ddr_bist), 989 FUNCTION(ddr_pxi0), 990 FUNCTION(ddr_pxi1), 991 FUNCTION(ddr_pxi2), 992 FUNCTION(ddr_pxi3), 993 FUNCTION(edp_hot), 994 FUNCTION(edp_lcd), 995 FUNCTION(gcc_gp1), 996 FUNCTION(gcc_gp2), 997 FUNCTION(gcc_gp3), 998 FUNCTION(gp_pdm0), 999 FUNCTION(gp_pdm1), 1000 FUNCTION(gp_pdm2), 1001 FUNCTION(gps_tx), 1002 FUNCTION(jitter_bist), 1003 FUNCTION(ldo_en), 1004 FUNCTION(ldo_update), 1005 FUNCTION(m_voc), 1006 FUNCTION(mdp_vsync), 1007 FUNCTION(mdp_vsync0), 1008 FUNCTION(mdp_vsync1), 1009 FUNCTION(mdp_vsync2), 1010 FUNCTION(mdp_vsync3), 1011 FUNCTION(mss_lte), 1012 FUNCTION(nav_pps_in), 1013 FUNCTION(nav_pps_out), 1014 FUNCTION(pa_indicator), 1015 FUNCTION(pci_e), 1016 FUNCTION(phase_flag), 1017 FUNCTION(pll_bist), 1018 FUNCTION(pll_bypassnl), 1019 FUNCTION(pll_reset), 1020 FUNCTION(pri_mi2s), 1021 FUNCTION(pri_mi2s_ws), 1022 FUNCTION(prng_rosc), 1023 FUNCTION(qdss_cti), 1024 FUNCTION(qdss), 1025 FUNCTION(qlink_enable), 1026 FUNCTION(qlink_request), 1027 FUNCTION(qua_mi2s), 1028 FUNCTION(qup00), 1029 FUNCTION(qup01), 1030 FUNCTION(qup02), 1031 FUNCTION(qup03), 1032 FUNCTION(qup04), 1033 FUNCTION(qup10), 1034 FUNCTION(qup11), 1035 FUNCTION(qup12), 1036 FUNCTION(qup13), 1037 FUNCTION(qup14), 1038 FUNCTION(qup15), 1039 FUNCTION(sd_write), 1040 FUNCTION(sdc40), 1041 FUNCTION(sdc41), 1042 FUNCTION(sdc42), 1043 FUNCTION(sdc43), 1044 FUNCTION(sdc4_clk), 1045 FUNCTION(sdc4_cmd), 1046 FUNCTION(sec_mi2s), 1047 FUNCTION(ter_mi2s), 1048 FUNCTION(tgu_ch0), 1049 FUNCTION(tgu_ch1), 1050 FUNCTION(tgu_ch2), 1051 FUNCTION(tgu_ch3), 1052 FUNCTION(tsif1_clk), 1053 FUNCTION(tsif1_data), 1054 FUNCTION(tsif1_en), 1055 FUNCTION(tsif1_error), 1056 FUNCTION(tsif1_sync), 1057 FUNCTION(tsif2_clk), 1058 FUNCTION(tsif2_data), 1059 FUNCTION(tsif2_en), 1060 FUNCTION(tsif2_error), 1061 FUNCTION(tsif2_sync), 1062 FUNCTION(uim1_clk), 1063 FUNCTION(uim1_data), 1064 FUNCTION(uim1_present), 1065 FUNCTION(uim1_reset), 1066 FUNCTION(uim2_clk), 1067 FUNCTION(uim2_data), 1068 FUNCTION(uim2_present), 1069 FUNCTION(uim2_reset), 1070 FUNCTION(uim_batt), 1071 FUNCTION(usb_phy), 1072 FUNCTION(vfr_1), 1073 FUNCTION(vsense_trigger), 1074 FUNCTION(wlan1_adc0), 1075 FUNCTION(wlan1_adc1), 1076 FUNCTION(wlan2_adc0), 1077 FUNCTION(wlan2_adc1), 1078 FUNCTION(wsa_clk), 1079 FUNCTION(wsa_data), 1080 }; 1081 1082 /* 1083 * Every pin is maintained as a single group, and missing or non-existing pin 1084 * would be maintained as dummy group to synchronize pin group index with 1085 * pin descriptor registered with pinctrl core. 1086 * Clients would not be able to request these dummy pin groups. 1087 */ 1088 static const struct msm_pingroup sm7150_groups[] = { 1089 [0] = PINGROUP(0, SOUTH, qup01, _, phase_flag, _, _, _, _, _, _), 1090 [1] = PINGROUP(1, SOUTH, qup01, _, phase_flag, _, _, _, _, _, _), 1091 [2] = PINGROUP(2, SOUTH, qup01, _, phase_flag, _, _, _, _, _, _), 1092 [3] = PINGROUP(3, SOUTH, qup01, dbg_out, _, _, _, _, _, _, _), 1093 [4] = PINGROUP(4, NORTH, _, qdss_cti, _, _, _, _, _, _, _), 1094 [5] = PINGROUP(5, NORTH, _, qdss_cti, _, _, _, _, _, _, _), 1095 [6] = PINGROUP(6, NORTH, qup11, _, phase_flag, ddr_pxi0, _, _, _, _, _), 1096 [7] = PINGROUP(7, NORTH, qup11, ddr_bist, _, phase_flag, atest_tsens2, vsense_trigger, atest_usb1, ddr_pxi0, _), 1097 [8] = PINGROUP(8, NORTH, qup11, gp_pdm1, ddr_bist, _, _, _, _, _, _), 1098 [9] = PINGROUP(9, NORTH, qup11, ddr_bist, _, _, _, _, _, _, _), 1099 [10] = PINGROUP(10, NORTH, mdp_vsync, ddr_bist, _, phase_flag, wlan2_adc1, atest_usb1, ddr_pxi2, _, _), 1100 [11] = PINGROUP(11, NORTH, mdp_vsync, edp_lcd, _, phase_flag, wlan2_adc0, atest_usb1, ddr_pxi2, _, _), 1101 [12] = PINGROUP(12, SOUTH, mdp_vsync, m_voc, qup01, _, phase_flag, ddr_pxi3, _, _, _), 1102 [13] = PINGROUP(13, SOUTH, cam_mclk, pll_bypassnl, _, phase_flag, qdss, ddr_pxi3, _, _, _), 1103 [14] = PINGROUP(14, SOUTH, cam_mclk, pll_reset, _, phase_flag, qdss, _, _, _, _), 1104 [15] = PINGROUP(15, SOUTH, cam_mclk, _, phase_flag, qdss, _, _, _, _, _), 1105 [16] = PINGROUP(16, SOUTH, cam_mclk, _, phase_flag, qdss, _, _, _, _, _), 1106 [17] = PINGROUP(17, SOUTH, cci_i2c, _, phase_flag, qdss, _, _, _, _, _), 1107 [18] = PINGROUP(18, SOUTH, cci_i2c, qdss, _, _, _, _, _, _, _), 1108 [19] = PINGROUP(19, SOUTH, cci_i2c, qdss, _, _, _, _, _, _, _), 1109 [20] = PINGROUP(20, SOUTH, cci_i2c, qdss, _, _, _, _, _, _, _), 1110 [21] = PINGROUP(21, SOUTH, cci_timer0, gcc_gp2, _, qdss, _, _, _, _, _), 1111 [22] = PINGROUP(22, SOUTH, cci_timer1, gcc_gp3, _, qdss, _, _, _, _, _), 1112 [23] = PINGROUP(23, SOUTH, cci_timer2, qdss, _, _, _, _, _, _, _), 1113 [24] = PINGROUP(24, SOUTH, cci_timer3, cci_async, _, phase_flag, qdss, _, _, _, _), 1114 [25] = PINGROUP(25, SOUTH, cci_timer4, cci_async, _, phase_flag, qdss, _, _, _, _), 1115 [26] = PINGROUP(26, SOUTH, cci_async, jitter_bist, _, phase_flag, qdss, _, _, _, _), 1116 [27] = PINGROUP(27, SOUTH, cci_i2c, pll_bist, _, phase_flag, qdss, _, _, _, _), 1117 [28] = PINGROUP(28, SOUTH, cci_i2c, agera_pll, _, phase_flag, qdss, _, _, _, _), 1118 [29] = PINGROUP(29, NORTH, _, _, phase_flag, qdss, atest_tsens, _, _, _, _), 1119 [30] = PINGROUP(30, SOUTH, _, phase_flag, qdss, _, _, _, _, _, _), 1120 [31] = PINGROUP(31, WEST, _, qdss, _, _, _, _, _, _, _), 1121 [32] = PINGROUP(32, NORTH, qdss_cti, _, _, _, _, _, _, _, _), 1122 [33] = PINGROUP(33, NORTH, sd_write, _, _, _, _, _, _, _, _), 1123 [34] = PINGROUP(34, SOUTH, qup02, qdss, _, _, _, _, _, _, _), 1124 [35] = PINGROUP(35, SOUTH, qup02, _, phase_flag, qdss, _, _, _, _, _), 1125 [36] = PINGROUP(36, SOUTH, _, phase_flag, qdss, _, _, _, _, _, _), 1126 [37] = PINGROUP(37, SOUTH, qup01, gp_pdm0, _, phase_flag, qdss, _, _, _, _), 1127 [38] = PINGROUP(38, SOUTH, qup03, _, phase_flag, _, _, _, _, _, _), 1128 [39] = PINGROUP(39, SOUTH, qup03, _, phase_flag, _, wlan1_adc0, atest_usb1, ddr_pxi1, _, _), 1129 [40] = PINGROUP(40, SOUTH, qup03, _, _, _, _, _, _, _, _), 1130 [41] = PINGROUP(41, SOUTH, qup03, _, _, _, _, _, _, _, _), 1131 [42] = PINGROUP(42, NORTH, qup12, _, _, _, _, _, _, _, _), 1132 [43] = PINGROUP(43, NORTH, qup12, _, phase_flag, _, _, _, _, _, _), 1133 [44] = PINGROUP(44, NORTH, qup12, _, phase_flag, qdss_cti, _, wlan1_adc1, atest_usb1, ddr_pxi1, _), 1134 [45] = PINGROUP(45, NORTH, qup12, qdss_cti, _, _, _, _, _, _, _), 1135 [46] = PINGROUP(46, NORTH, qup13, _, _, _, _, _, _, _, _), 1136 [47] = PINGROUP(47, NORTH, qup13, _, _, _, _, _, _, _, _), 1137 [48] = PINGROUP(48, WEST, gcc_gp1, _, _, _, _, _, _, _, _), 1138 [49] = PINGROUP(49, WEST, pri_mi2s, qup00, wsa_clk, _, _, _, _, _, _), 1139 [50] = PINGROUP(50, WEST, pri_mi2s_ws, qup00, wsa_data, gp_pdm1, _, _, _, _, _), 1140 [51] = PINGROUP(51, WEST, pri_mi2s, qup00, atest_usb2, _, _, _, _, _, _), 1141 [52] = PINGROUP(52, WEST, pri_mi2s, qup00, atest_usb2, _, _, _, _, _, _), 1142 [53] = PINGROUP(53, WEST, ter_mi2s, qup04, qdss, atest_usb2, _, _, _, _, _), 1143 [54] = PINGROUP(54, WEST, ter_mi2s, qup04, qdss, atest_usb2, _, _, _, _, _), 1144 [55] = PINGROUP(55, WEST, ter_mi2s, qup04, qdss, atest_usb2, _, _, _, _, _), 1145 [56] = PINGROUP(56, WEST, ter_mi2s, qup04, gcc_gp1, _, phase_flag, qdss, _, _, _), 1146 [57] = PINGROUP(57, WEST, sec_mi2s, qup00, gp_pdm2, _, phase_flag, qdss, _, _, _), 1147 [58] = PINGROUP(58, WEST, qua_mi2s, qup00, _, _, _, _, _, _, _), 1148 [59] = PINGROUP(59, NORTH, qup10, _, _, _, _, _, _, _, _), 1149 [60] = PINGROUP(60, NORTH, qup10, tsif1_error, _, phase_flag, _, _, _, _, _), 1150 [61] = PINGROUP(61, NORTH, qup10, tsif1_sync, _, phase_flag, _, _, _, _, _), 1151 [62] = PINGROUP(62, NORTH, qup10, tsif1_clk, tgu_ch3, _, phase_flag, _, _, _, _), 1152 [63] = PINGROUP(63, NORTH, tsif1_en, mdp_vsync0, qup10, mdp_vsync1, mdp_vsync2, mdp_vsync3, tgu_ch0, qdss_cti, _), 1153 [64] = PINGROUP(64, NORTH, tsif1_data, sdc4_cmd, qup10, tgu_ch1, _, _, _, _, _), 1154 [65] = PINGROUP(65, NORTH, tsif2_error, sdc43, qup10, vfr_1, tgu_ch2, _, _, _, _), 1155 [66] = PINGROUP(66, NORTH, tsif2_clk, sdc4_clk, pci_e, _, _, _, _, _, _), 1156 [67] = PINGROUP(67, NORTH, tsif2_en, sdc42, pci_e, _, _, _, _, _, _), 1157 [68] = PINGROUP(68, NORTH, tsif2_data, sdc41, pci_e, gp_pdm0, _, _, _, _, _), 1158 [69] = PINGROUP(69, NORTH, tsif2_sync, sdc40, _, _, _, _, _, _, _), 1159 [70] = PINGROUP(70, NORTH, _, _, mdp_vsync, ldo_en, _, _, _, _, _), 1160 [71] = PINGROUP(71, NORTH, _, mdp_vsync, ldo_update, _, _, _, _, _, _), 1161 [72] = PINGROUP(72, NORTH, prng_rosc, _, _, _, _, _, _, _, _), 1162 [73] = PINGROUP(73, NORTH, _, _, _, _, _, _, _, _, _), 1163 [74] = PINGROUP(74, WEST, _, _, _, _, _, _, _, _, _), 1164 [75] = PINGROUP(75, WEST, uim2_data, _, _, _, _, _, _, _, _), 1165 [76] = PINGROUP(76, WEST, uim2_clk, _, _, _, _, _, _, _, _), 1166 [77] = PINGROUP(77, WEST, uim2_reset, _, _, _, _, _, _, _, _), 1167 [78] = PINGROUP(78, WEST, uim2_present, _, _, _, _, _, _, _, _), 1168 [79] = PINGROUP(79, WEST, uim1_data, _, _, _, _, _, _, _, _), 1169 [80] = PINGROUP(80, WEST, uim1_clk, _, _, _, _, _, _, _, _), 1170 [81] = PINGROUP(81, WEST, uim1_reset, _, _, _, _, _, _, _, _), 1171 [82] = PINGROUP(82, WEST, uim1_present, _, _, _, _, _, _, _, _), 1172 [83] = PINGROUP(83, WEST, _, nav_pps_in, nav_pps_out, gps_tx, _, _, _, _, _), 1173 [84] = PINGROUP(84, WEST, _, nav_pps_in, nav_pps_out, gps_tx, _, _, _, _, _), 1174 [85] = PINGROUP(85, WEST, uim_batt, edp_hot, aoss_cti, _, _, _, _, _, _), 1175 [86] = PINGROUP(86, NORTH, qdss, atest_char, _, _, _, _, _, _, _), 1176 [87] = PINGROUP(87, NORTH, adsp_ext, qdss, atest_char, _, _, _, _, _, _), 1177 [88] = PINGROUP(88, NORTH, qdss, atest_char, _, _, _, _, _, _, _), 1178 [89] = PINGROUP(89, NORTH, qdss, atest_char, _, _, _, _, _, _, _), 1179 [90] = PINGROUP(90, NORTH, qdss, atest_char, _, _, _, _, _, _, _), 1180 [91] = PINGROUP(91, NORTH, qdss, _, _, _, _, _, _, _, _), 1181 [92] = PINGROUP(92, NORTH, _, _, qup15, _, _, _, _, _, _), 1182 [93] = PINGROUP(93, NORTH, qdss, _, _, _, _, _, _, _, _), 1183 [94] = PINGROUP(94, SOUTH, _, _, _, _, _, _, _, _, _), 1184 [95] = PINGROUP(95, WEST, _, _, _, _, _, _, _, _, _), 1185 [96] = PINGROUP(96, WEST, qlink_request, _, _, _, _, _, _, _, _), 1186 [97] = PINGROUP(97, WEST, qlink_enable, _, _, _, _, _, _, _, _), 1187 [98] = PINGROUP(98, WEST, _, _, _, _, _, _, _, _, _), 1188 [99] = PINGROUP(99, WEST, _, pa_indicator, _, _, _, _, _, _, _), 1189 [100] = PINGROUP(100, WEST, _, _, _, _, _, _, _, _, _), 1190 [101] = PINGROUP(101, NORTH, _, _, qup15, _, _, _, _, _, _), 1191 [102] = PINGROUP(102, NORTH, _, _, qup15, _, _, _, _, _, _), 1192 [103] = PINGROUP(103, NORTH, _, qup15, _, _, _, _, _, _, _), 1193 [104] = PINGROUP(104, WEST, usb_phy, _, qdss, _, _, _, _, _, _), 1194 [105] = PINGROUP(105, NORTH, _, _, _, _, _, _, _, _, _), 1195 [106] = PINGROUP(106, NORTH, _, _, _, _, _, _, _, _, _), 1196 [107] = PINGROUP(107, WEST, _, nav_pps_in, nav_pps_out, gps_tx, _, _, _, _, _), 1197 [108] = PINGROUP(108, SOUTH, mss_lte, _, _, _, _, _, _, _, _), 1198 [109] = PINGROUP(109, SOUTH, mss_lte, gps_tx, _, _, _, _, _, _, _), 1199 [110] = PINGROUP(110, NORTH, _, _, qup14, _, _, _, _, _, _), 1200 [111] = PINGROUP(111, NORTH, _, _, qup14, _, _, _, _, _, _), 1201 [112] = PINGROUP(112, NORTH, _, qup14, _, _, _, _, _, _, _), 1202 [113] = PINGROUP(113, NORTH, _, qup14, _, _, _, _, _, _, _), 1203 [114] = PINGROUP(114, NORTH, _, _, _, _, _, _, _, _, _), 1204 [115] = PINGROUP(115, NORTH, _, _, _, _, _, _, _, _, _), 1205 [116] = PINGROUP(116, NORTH, _, _, _, _, _, _, _, _, _), 1206 [117] = PINGROUP(117, NORTH, _, _, _, _, _, _, _, _, _), 1207 [118] = PINGROUP(118, NORTH, _, _, _, _, _, _, _, _, _), 1208 [119] = UFS_RESET(ufs_reset, 0x9f000), 1209 [120] = SDC_QDSD_PINGROUP(sdc1_rclk, 0x9a000, 15, 0), 1210 [121] = SDC_QDSD_PINGROUP(sdc1_clk, 0x9a000, 13, 6), 1211 [122] = SDC_QDSD_PINGROUP(sdc1_cmd, 0x9a000, 11, 3), 1212 [123] = SDC_QDSD_PINGROUP(sdc1_data, 0x9a000, 9, 0), 1213 [124] = SDC_QDSD_PINGROUP(sdc2_clk, 0x98000, 14, 6), 1214 [125] = SDC_QDSD_PINGROUP(sdc2_cmd, 0x98000, 11, 3), 1215 [126] = SDC_QDSD_PINGROUP(sdc2_data, 0x98000, 9, 0), 1216 }; 1217 1218 static const struct msm_gpio_wakeirq_map sm7150_pdc_map[] = { 1219 {0, 40}, {3, 50}, {4, 42}, {5, 70}, {6, 41}, {9, 57}, 1220 {10, 80}, {11, 51}, {22, 90}, {24, 61}, {26, 52}, {30, 56}, 1221 {31, 33}, {32, 81}, {33, 62}, {34, 43}, {36, 91}, {37, 53}, 1222 {38, 63}, {39, 72}, {41, 101}, {42, 35}, {43, 34}, {45, 73}, 1223 {47, 82}, {48, 36}, {49, 37}, {50, 38}, {52, 39}, {53, 102}, 1224 {55, 92}, {56, 45}, {57, 46}, {58, 83}, {59, 47}, {62, 48}, 1225 {64, 74}, {65, 44}, {66, 93}, {67, 49}, {68, 55}, {69, 32}, 1226 {70, 54}, {73, 64}, {74, 71}, {78, 31}, {82, 30}, {84, 58}, 1227 {85, 103}, {86, 59}, {87, 60}, {88, 65}, {89, 66}, {90, 67}, 1228 {91, 68}, {92, 69}, {93, 75}, {94, 84}, {95, 94}, {96, 76}, 1229 {98, 77}, {101, 78}, {104, 99}, {109, 104}, {110, 79}, {113, 85}, 1230 }; 1231 1232 static const struct msm_pinctrl_soc_data sm7150_tlmm = { 1233 .pins = sm7150_pins, 1234 .npins = ARRAY_SIZE(sm7150_pins), 1235 .functions = sm7150_functions, 1236 .nfunctions = ARRAY_SIZE(sm7150_functions), 1237 .groups = sm7150_groups, 1238 .ngroups = ARRAY_SIZE(sm7150_groups), 1239 .ngpios = 120, 1240 .tiles = sm7150_tiles, 1241 .ntiles = ARRAY_SIZE(sm7150_tiles), 1242 .wakeirq_map = sm7150_pdc_map, 1243 .nwakeirq_map = ARRAY_SIZE(sm7150_pdc_map), 1244 .wakeirq_dual_edge_errata = true, 1245 }; 1246 1247 static int sm7150_tlmm_probe(struct platform_device *pdev) 1248 { 1249 return msm_pinctrl_probe(pdev, &sm7150_tlmm); 1250 } 1251 1252 static const struct of_device_id sm7150_tlmm_of_match[] = { 1253 { .compatible = "qcom,sm7150-tlmm", }, 1254 { }, 1255 }; 1256 1257 static struct platform_driver sm7150_tlmm_driver = { 1258 .driver = { 1259 .name = "sm7150-tlmm", 1260 .pm = &msm_pinctrl_dev_pm_ops, 1261 .of_match_table = sm7150_tlmm_of_match, 1262 }, 1263 .probe = sm7150_tlmm_probe, 1264 .remove = msm_pinctrl_remove, 1265 }; 1266 1267 static int __init sm7150_tlmm_init(void) 1268 { 1269 return platform_driver_register(&sm7150_tlmm_driver); 1270 } 1271 arch_initcall(sm7150_tlmm_init); 1272 1273 static void __exit sm7150_tlmm_exit(void) 1274 { 1275 platform_driver_unregister(&sm7150_tlmm_driver); 1276 } 1277 module_exit(sm7150_tlmm_exit); 1278 1279 MODULE_DESCRIPTION("Qualcomm SM7150 TLMM driver"); 1280 MODULE_LICENSE("GPL"); 1281