1 //SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 
3 #include <linux/module.h>
4 #include <linux/of.h>
5 #include <linux/platform_device.h>
6 #include <linux/pinctrl/pinctrl.h>
7 
8 #include "pinctrl-msm.h"
9 
10 static const char * const sm6125_tiles[] = {
11 	"south",
12 	"east",
13 	"west"
14 };
15 
16 enum {
17 	SOUTH,
18 	EAST,
19 	WEST
20 };
21 
22 #define FUNCTION(fname)					\
23 	[msm_mux_##fname] = {				\
24 		.name = #fname,				\
25 		.groups = fname##_groups,		\
26 		.ngroups = ARRAY_SIZE(fname##_groups),	\
27 	}
28 
29 #define PINGROUP(id, _tile, f1, f2, f3, f4, f5, f6, f7, f8, f9)	\
30 	{						\
31 		.name = "gpio" #id,			\
32 		.pins = gpio##id##_pins,		\
33 		.npins = (unsigned int)ARRAY_SIZE(gpio##id##_pins),	\
34 		.funcs = (int[]){			\
35 			msm_mux_gpio, /* gpio mode */	\
36 			msm_mux_##f1,			\
37 			msm_mux_##f2,			\
38 			msm_mux_##f3,			\
39 			msm_mux_##f4,			\
40 			msm_mux_##f5,			\
41 			msm_mux_##f6,			\
42 			msm_mux_##f7,			\
43 			msm_mux_##f8,			\
44 			msm_mux_##f9			\
45 		},					\
46 		.nfuncs = 10,				\
47 		.ctl_reg = 0x1000 * id,		\
48 		.io_reg = 0x4 + 0x1000 * id,		\
49 		.intr_cfg_reg = 0x8 + 0x1000 * id,	\
50 		.intr_status_reg = 0xc + 0x1000 * id,	\
51 		.intr_target_reg = 0x8 + 0x1000 * id,	\
52 		.tile = _tile,			\
53 		.mux_bit = 2,			\
54 		.pull_bit = 0,			\
55 		.drv_bit = 6,			\
56 		.oe_bit = 9,			\
57 		.in_bit = 0,			\
58 		.out_bit = 1,			\
59 		.intr_enable_bit = 0,		\
60 		.intr_status_bit = 0,		\
61 		.intr_target_bit = 5,		\
62 		.intr_target_kpss_val = 3,	\
63 		.intr_raw_status_bit = 4,	\
64 		.intr_polarity_bit = 1,		\
65 		.intr_detection_bit = 2,	\
66 		.intr_detection_width = 2,	\
67 	}
68 
69 #define SDC_QDSD_PINGROUP(pg_name, _tile, ctl, pull, drv)	\
70 	{						\
71 		.name = #pg_name,			\
72 		.pins = pg_name##_pins,			\
73 		.npins = (unsigned int)ARRAY_SIZE(pg_name##_pins),	\
74 		.ctl_reg = ctl,				\
75 		.io_reg = 0,				\
76 		.intr_cfg_reg = 0,			\
77 		.intr_status_reg = 0,			\
78 		.intr_target_reg = 0,			\
79 		.tile = _tile,				\
80 		.mux_bit = -1,				\
81 		.pull_bit = pull,			\
82 		.drv_bit = drv,				\
83 		.oe_bit = -1,				\
84 		.in_bit = -1,				\
85 		.out_bit = -1,				\
86 		.intr_enable_bit = -1,			\
87 		.intr_status_bit = -1,			\
88 		.intr_target_bit = -1,			\
89 		.intr_raw_status_bit = -1,		\
90 		.intr_polarity_bit = -1,		\
91 		.intr_detection_bit = -1,		\
92 		.intr_detection_width = -1,		\
93 	}
94 
95 #define UFS_RESET(pg_name, offset)				\
96 	{						\
97 		.name = #pg_name,			\
98 		.pins = pg_name##_pins,			\
99 		.npins = (unsigned int)ARRAY_SIZE(pg_name##_pins),	\
100 		.ctl_reg = offset,			\
101 		.io_reg = offset + 0x4,			\
102 		.intr_cfg_reg = 0,			\
103 		.intr_status_reg = 0,			\
104 		.intr_target_reg = 0,			\
105 		.tile = WEST,				\
106 		.mux_bit = -1,				\
107 		.pull_bit = 3,				\
108 		.drv_bit = 0,				\
109 		.oe_bit = -1,				\
110 		.in_bit = -1,				\
111 		.out_bit = 0,				\
112 		.intr_enable_bit = -1,			\
113 		.intr_status_bit = -1,			\
114 		.intr_target_bit = -1,			\
115 		.intr_raw_status_bit = -1,		\
116 		.intr_polarity_bit = -1,		\
117 		.intr_detection_bit = -1,		\
118 		.intr_detection_width = -1,		\
119 	}
120 static const struct pinctrl_pin_desc sm6125_pins[] = {
121 	PINCTRL_PIN(0, "GPIO_0"),
122 	PINCTRL_PIN(1, "GPIO_1"),
123 	PINCTRL_PIN(2, "GPIO_2"),
124 	PINCTRL_PIN(3, "GPIO_3"),
125 	PINCTRL_PIN(4, "GPIO_4"),
126 	PINCTRL_PIN(5, "GPIO_5"),
127 	PINCTRL_PIN(6, "GPIO_6"),
128 	PINCTRL_PIN(7, "GPIO_7"),
129 	PINCTRL_PIN(8, "GPIO_8"),
130 	PINCTRL_PIN(9, "GPIO_9"),
131 	PINCTRL_PIN(10, "GPIO_10"),
132 	PINCTRL_PIN(11, "GPIO_11"),
133 	PINCTRL_PIN(12, "GPIO_12"),
134 	PINCTRL_PIN(13, "GPIO_13"),
135 	PINCTRL_PIN(14, "GPIO_14"),
136 	PINCTRL_PIN(15, "GPIO_15"),
137 	PINCTRL_PIN(16, "GPIO_16"),
138 	PINCTRL_PIN(17, "GPIO_17"),
139 	PINCTRL_PIN(18, "GPIO_18"),
140 	PINCTRL_PIN(19, "GPIO_19"),
141 	PINCTRL_PIN(20, "GPIO_20"),
142 	PINCTRL_PIN(21, "GPIO_21"),
143 	PINCTRL_PIN(22, "GPIO_22"),
144 	PINCTRL_PIN(23, "GPIO_23"),
145 	PINCTRL_PIN(24, "GPIO_24"),
146 	PINCTRL_PIN(25, "GPIO_25"),
147 	PINCTRL_PIN(26, "GPIO_26"),
148 	PINCTRL_PIN(27, "GPIO_27"),
149 	PINCTRL_PIN(28, "GPIO_28"),
150 	PINCTRL_PIN(29, "GPIO_29"),
151 	PINCTRL_PIN(30, "GPIO_30"),
152 	PINCTRL_PIN(31, "GPIO_31"),
153 	PINCTRL_PIN(32, "GPIO_32"),
154 	PINCTRL_PIN(33, "GPIO_33"),
155 	PINCTRL_PIN(34, "GPIO_34"),
156 	PINCTRL_PIN(35, "GPIO_35"),
157 	PINCTRL_PIN(36, "GPIO_36"),
158 	PINCTRL_PIN(37, "GPIO_37"),
159 	PINCTRL_PIN(38, "GPIO_38"),
160 	PINCTRL_PIN(39, "GPIO_39"),
161 	PINCTRL_PIN(40, "GPIO_40"),
162 	PINCTRL_PIN(41, "GPIO_41"),
163 	PINCTRL_PIN(42, "GPIO_42"),
164 	PINCTRL_PIN(43, "GPIO_43"),
165 	PINCTRL_PIN(44, "GPIO_44"),
166 	PINCTRL_PIN(45, "GPIO_45"),
167 	PINCTRL_PIN(46, "GPIO_46"),
168 	PINCTRL_PIN(47, "GPIO_47"),
169 	PINCTRL_PIN(48, "GPIO_48"),
170 	PINCTRL_PIN(49, "GPIO_49"),
171 	PINCTRL_PIN(50, "GPIO_50"),
172 	PINCTRL_PIN(51, "GPIO_51"),
173 	PINCTRL_PIN(52, "GPIO_52"),
174 	PINCTRL_PIN(53, "GPIO_53"),
175 	PINCTRL_PIN(54, "GPIO_54"),
176 	PINCTRL_PIN(55, "GPIO_55"),
177 	PINCTRL_PIN(56, "GPIO_56"),
178 	PINCTRL_PIN(57, "GPIO_57"),
179 	PINCTRL_PIN(58, "GPIO_58"),
180 	PINCTRL_PIN(59, "GPIO_59"),
181 	PINCTRL_PIN(60, "GPIO_60"),
182 	PINCTRL_PIN(61, "GPIO_61"),
183 	PINCTRL_PIN(62, "GPIO_62"),
184 	PINCTRL_PIN(63, "GPIO_63"),
185 	PINCTRL_PIN(64, "GPIO_64"),
186 	PINCTRL_PIN(65, "GPIO_65"),
187 	PINCTRL_PIN(66, "GPIO_66"),
188 	PINCTRL_PIN(67, "GPIO_67"),
189 	PINCTRL_PIN(68, "GPIO_68"),
190 	PINCTRL_PIN(69, "GPIO_69"),
191 	PINCTRL_PIN(70, "GPIO_70"),
192 	PINCTRL_PIN(71, "GPIO_71"),
193 	PINCTRL_PIN(72, "GPIO_72"),
194 	PINCTRL_PIN(73, "GPIO_73"),
195 	PINCTRL_PIN(74, "GPIO_74"),
196 	PINCTRL_PIN(75, "GPIO_75"),
197 	PINCTRL_PIN(76, "GPIO_76"),
198 	PINCTRL_PIN(77, "GPIO_77"),
199 	PINCTRL_PIN(78, "GPIO_78"),
200 	PINCTRL_PIN(79, "GPIO_79"),
201 	PINCTRL_PIN(80, "GPIO_80"),
202 	PINCTRL_PIN(81, "GPIO_81"),
203 	PINCTRL_PIN(82, "GPIO_82"),
204 	PINCTRL_PIN(83, "GPIO_83"),
205 	PINCTRL_PIN(84, "GPIO_84"),
206 	PINCTRL_PIN(85, "GPIO_85"),
207 	PINCTRL_PIN(86, "GPIO_86"),
208 	PINCTRL_PIN(87, "GPIO_87"),
209 	PINCTRL_PIN(88, "GPIO_88"),
210 	PINCTRL_PIN(89, "GPIO_89"),
211 	PINCTRL_PIN(90, "GPIO_90"),
212 	PINCTRL_PIN(91, "GPIO_91"),
213 	PINCTRL_PIN(92, "GPIO_92"),
214 	PINCTRL_PIN(93, "GPIO_93"),
215 	PINCTRL_PIN(94, "GPIO_94"),
216 	PINCTRL_PIN(95, "GPIO_95"),
217 	PINCTRL_PIN(96, "GPIO_96"),
218 	PINCTRL_PIN(97, "GPIO_97"),
219 	PINCTRL_PIN(98, "GPIO_98"),
220 	PINCTRL_PIN(99, "GPIO_99"),
221 	PINCTRL_PIN(100, "GPIO_100"),
222 	PINCTRL_PIN(101, "GPIO_101"),
223 	PINCTRL_PIN(102, "GPIO_102"),
224 	PINCTRL_PIN(103, "GPIO_103"),
225 	PINCTRL_PIN(104, "GPIO_104"),
226 	PINCTRL_PIN(105, "GPIO_105"),
227 	PINCTRL_PIN(106, "GPIO_106"),
228 	PINCTRL_PIN(107, "GPIO_107"),
229 	PINCTRL_PIN(108, "GPIO_108"),
230 	PINCTRL_PIN(109, "GPIO_109"),
231 	PINCTRL_PIN(110, "GPIO_110"),
232 	PINCTRL_PIN(111, "GPIO_111"),
233 	PINCTRL_PIN(112, "GPIO_112"),
234 	PINCTRL_PIN(113, "GPIO_113"),
235 	PINCTRL_PIN(114, "GPIO_114"),
236 	PINCTRL_PIN(115, "GPIO_115"),
237 	PINCTRL_PIN(116, "GPIO_116"),
238 	PINCTRL_PIN(117, "GPIO_117"),
239 	PINCTRL_PIN(118, "GPIO_118"),
240 	PINCTRL_PIN(119, "GPIO_119"),
241 	PINCTRL_PIN(120, "GPIO_120"),
242 	PINCTRL_PIN(121, "GPIO_121"),
243 	PINCTRL_PIN(122, "GPIO_122"),
244 	PINCTRL_PIN(123, "GPIO_123"),
245 	PINCTRL_PIN(124, "GPIO_124"),
246 	PINCTRL_PIN(125, "GPIO_125"),
247 	PINCTRL_PIN(126, "GPIO_126"),
248 	PINCTRL_PIN(127, "GPIO_127"),
249 	PINCTRL_PIN(128, "GPIO_128"),
250 	PINCTRL_PIN(129, "GPIO_129"),
251 	PINCTRL_PIN(130, "GPIO_130"),
252 	PINCTRL_PIN(131, "GPIO_131"),
253 	PINCTRL_PIN(132, "GPIO_132"),
254 	PINCTRL_PIN(133, "UFS_RESET"),
255 	PINCTRL_PIN(134, "SDC1_RCLK"),
256 	PINCTRL_PIN(135, "SDC1_CLK"),
257 	PINCTRL_PIN(136, "SDC1_CMD"),
258 	PINCTRL_PIN(137, "SDC1_DATA"),
259 	PINCTRL_PIN(138, "SDC2_CLK"),
260 	PINCTRL_PIN(139, "SDC2_CMD"),
261 	PINCTRL_PIN(140, "SDC2_DATA"),
262 };
263 
264 #define DECLARE_MSM_GPIO_PINS(pin) \
265 	static const unsigned int gpio##pin##_pins[] = { pin }
266 DECLARE_MSM_GPIO_PINS(0);
267 DECLARE_MSM_GPIO_PINS(1);
268 DECLARE_MSM_GPIO_PINS(2);
269 DECLARE_MSM_GPIO_PINS(3);
270 DECLARE_MSM_GPIO_PINS(4);
271 DECLARE_MSM_GPIO_PINS(5);
272 DECLARE_MSM_GPIO_PINS(6);
273 DECLARE_MSM_GPIO_PINS(7);
274 DECLARE_MSM_GPIO_PINS(8);
275 DECLARE_MSM_GPIO_PINS(9);
276 DECLARE_MSM_GPIO_PINS(10);
277 DECLARE_MSM_GPIO_PINS(11);
278 DECLARE_MSM_GPIO_PINS(12);
279 DECLARE_MSM_GPIO_PINS(13);
280 DECLARE_MSM_GPIO_PINS(14);
281 DECLARE_MSM_GPIO_PINS(15);
282 DECLARE_MSM_GPIO_PINS(16);
283 DECLARE_MSM_GPIO_PINS(17);
284 DECLARE_MSM_GPIO_PINS(18);
285 DECLARE_MSM_GPIO_PINS(19);
286 DECLARE_MSM_GPIO_PINS(20);
287 DECLARE_MSM_GPIO_PINS(21);
288 DECLARE_MSM_GPIO_PINS(22);
289 DECLARE_MSM_GPIO_PINS(23);
290 DECLARE_MSM_GPIO_PINS(24);
291 DECLARE_MSM_GPIO_PINS(25);
292 DECLARE_MSM_GPIO_PINS(26);
293 DECLARE_MSM_GPIO_PINS(27);
294 DECLARE_MSM_GPIO_PINS(28);
295 DECLARE_MSM_GPIO_PINS(29);
296 DECLARE_MSM_GPIO_PINS(30);
297 DECLARE_MSM_GPIO_PINS(31);
298 DECLARE_MSM_GPIO_PINS(32);
299 DECLARE_MSM_GPIO_PINS(33);
300 DECLARE_MSM_GPIO_PINS(34);
301 DECLARE_MSM_GPIO_PINS(35);
302 DECLARE_MSM_GPIO_PINS(36);
303 DECLARE_MSM_GPIO_PINS(37);
304 DECLARE_MSM_GPIO_PINS(38);
305 DECLARE_MSM_GPIO_PINS(39);
306 DECLARE_MSM_GPIO_PINS(40);
307 DECLARE_MSM_GPIO_PINS(41);
308 DECLARE_MSM_GPIO_PINS(42);
309 DECLARE_MSM_GPIO_PINS(43);
310 DECLARE_MSM_GPIO_PINS(44);
311 DECLARE_MSM_GPIO_PINS(45);
312 DECLARE_MSM_GPIO_PINS(46);
313 DECLARE_MSM_GPIO_PINS(47);
314 DECLARE_MSM_GPIO_PINS(48);
315 DECLARE_MSM_GPIO_PINS(49);
316 DECLARE_MSM_GPIO_PINS(50);
317 DECLARE_MSM_GPIO_PINS(51);
318 DECLARE_MSM_GPIO_PINS(52);
319 DECLARE_MSM_GPIO_PINS(53);
320 DECLARE_MSM_GPIO_PINS(54);
321 DECLARE_MSM_GPIO_PINS(55);
322 DECLARE_MSM_GPIO_PINS(56);
323 DECLARE_MSM_GPIO_PINS(57);
324 DECLARE_MSM_GPIO_PINS(58);
325 DECLARE_MSM_GPIO_PINS(59);
326 DECLARE_MSM_GPIO_PINS(60);
327 DECLARE_MSM_GPIO_PINS(61);
328 DECLARE_MSM_GPIO_PINS(62);
329 DECLARE_MSM_GPIO_PINS(63);
330 DECLARE_MSM_GPIO_PINS(64);
331 DECLARE_MSM_GPIO_PINS(65);
332 DECLARE_MSM_GPIO_PINS(66);
333 DECLARE_MSM_GPIO_PINS(67);
334 DECLARE_MSM_GPIO_PINS(68);
335 DECLARE_MSM_GPIO_PINS(69);
336 DECLARE_MSM_GPIO_PINS(70);
337 DECLARE_MSM_GPIO_PINS(71);
338 DECLARE_MSM_GPIO_PINS(72);
339 DECLARE_MSM_GPIO_PINS(73);
340 DECLARE_MSM_GPIO_PINS(74);
341 DECLARE_MSM_GPIO_PINS(75);
342 DECLARE_MSM_GPIO_PINS(76);
343 DECLARE_MSM_GPIO_PINS(77);
344 DECLARE_MSM_GPIO_PINS(78);
345 DECLARE_MSM_GPIO_PINS(79);
346 DECLARE_MSM_GPIO_PINS(80);
347 DECLARE_MSM_GPIO_PINS(81);
348 DECLARE_MSM_GPIO_PINS(82);
349 DECLARE_MSM_GPIO_PINS(83);
350 DECLARE_MSM_GPIO_PINS(84);
351 DECLARE_MSM_GPIO_PINS(85);
352 DECLARE_MSM_GPIO_PINS(86);
353 DECLARE_MSM_GPIO_PINS(87);
354 DECLARE_MSM_GPIO_PINS(88);
355 DECLARE_MSM_GPIO_PINS(89);
356 DECLARE_MSM_GPIO_PINS(90);
357 DECLARE_MSM_GPIO_PINS(91);
358 DECLARE_MSM_GPIO_PINS(92);
359 DECLARE_MSM_GPIO_PINS(93);
360 DECLARE_MSM_GPIO_PINS(94);
361 DECLARE_MSM_GPIO_PINS(95);
362 DECLARE_MSM_GPIO_PINS(96);
363 DECLARE_MSM_GPIO_PINS(97);
364 DECLARE_MSM_GPIO_PINS(98);
365 DECLARE_MSM_GPIO_PINS(99);
366 DECLARE_MSM_GPIO_PINS(100);
367 DECLARE_MSM_GPIO_PINS(101);
368 DECLARE_MSM_GPIO_PINS(102);
369 DECLARE_MSM_GPIO_PINS(103);
370 DECLARE_MSM_GPIO_PINS(104);
371 DECLARE_MSM_GPIO_PINS(105);
372 DECLARE_MSM_GPIO_PINS(106);
373 DECLARE_MSM_GPIO_PINS(107);
374 DECLARE_MSM_GPIO_PINS(108);
375 DECLARE_MSM_GPIO_PINS(109);
376 DECLARE_MSM_GPIO_PINS(110);
377 DECLARE_MSM_GPIO_PINS(111);
378 DECLARE_MSM_GPIO_PINS(112);
379 DECLARE_MSM_GPIO_PINS(113);
380 DECLARE_MSM_GPIO_PINS(114);
381 DECLARE_MSM_GPIO_PINS(115);
382 DECLARE_MSM_GPIO_PINS(116);
383 DECLARE_MSM_GPIO_PINS(117);
384 DECLARE_MSM_GPIO_PINS(118);
385 DECLARE_MSM_GPIO_PINS(119);
386 DECLARE_MSM_GPIO_PINS(120);
387 DECLARE_MSM_GPIO_PINS(121);
388 DECLARE_MSM_GPIO_PINS(122);
389 DECLARE_MSM_GPIO_PINS(123);
390 DECLARE_MSM_GPIO_PINS(124);
391 DECLARE_MSM_GPIO_PINS(125);
392 DECLARE_MSM_GPIO_PINS(126);
393 DECLARE_MSM_GPIO_PINS(127);
394 DECLARE_MSM_GPIO_PINS(128);
395 DECLARE_MSM_GPIO_PINS(129);
396 DECLARE_MSM_GPIO_PINS(130);
397 DECLARE_MSM_GPIO_PINS(131);
398 DECLARE_MSM_GPIO_PINS(132);
399 
400 static const unsigned int ufs_reset_pins[] = { 133 };
401 static const unsigned int sdc1_rclk_pins[] = { 134 };
402 static const unsigned int sdc1_clk_pins[] = { 135 };
403 static const unsigned int sdc1_cmd_pins[] = { 136 };
404 static const unsigned int sdc1_data_pins[] = { 137 };
405 static const unsigned int sdc2_clk_pins[] = { 138 };
406 static const unsigned int sdc2_cmd_pins[] = { 139 };
407 static const unsigned int sdc2_data_pins[] = { 140 };
408 
409 
410 enum sm6125_functions {
411 	msm_mux_qup00,
412 	msm_mux_gpio,
413 	msm_mux_qdss,
414 	msm_mux_qup01,
415 	msm_mux_qup02,
416 	msm_mux_ddr_pxi0,
417 	msm_mux_ddr_bist,
418 	msm_mux_atest_tsens2,
419 	msm_mux_vsense_trigger,
420 	msm_mux_atest_usb1,
421 	msm_mux_gp_pdm1,
422 	msm_mux_phase_flag,
423 	msm_mux_dbg_out,
424 	msm_mux_qup14,
425 	msm_mux_atest_usb11,
426 	msm_mux_ddr_pxi2,
427 	msm_mux_atest_usb10,
428 	msm_mux_jitter_bist,
429 	msm_mux_ddr_pxi3,
430 	msm_mux_pll_bypassnl,
431 	msm_mux_pll_bist,
432 	msm_mux_qup03,
433 	msm_mux_pll_reset,
434 	msm_mux_agera_pll,
435 	msm_mux_qdss_cti,
436 	msm_mux_qup04,
437 	msm_mux_wlan2_adc1,
438 	msm_mux_wlan2_adc0,
439 	msm_mux_wsa_clk,
440 	msm_mux_qup13,
441 	msm_mux_ter_mi2s,
442 	msm_mux_wsa_data,
443 	msm_mux_qup10,
444 	msm_mux_gcc_gp3,
445 	msm_mux_qup12,
446 	msm_mux_sd_write,
447 	msm_mux_qup11,
448 	msm_mux_cam_mclk,
449 	msm_mux_atest_tsens,
450 	msm_mux_cci_i2c,
451 	msm_mux_cci_timer2,
452 	msm_mux_cci_timer1,
453 	msm_mux_gcc_gp2,
454 	msm_mux_cci_async,
455 	msm_mux_cci_timer4,
456 	msm_mux_cci_timer0,
457 	msm_mux_gcc_gp1,
458 	msm_mux_cci_timer3,
459 	msm_mux_wlan1_adc1,
460 	msm_mux_wlan1_adc0,
461 	msm_mux_qlink_request,
462 	msm_mux_qlink_enable,
463 	msm_mux_pa_indicator,
464 	msm_mux_nav_pps,
465 	msm_mux_gps_tx,
466 	msm_mux_gp_pdm0,
467 	msm_mux_atest_usb13,
468 	msm_mux_ddr_pxi1,
469 	msm_mux_atest_usb12,
470 	msm_mux_cri_trng0,
471 	msm_mux_cri_trng,
472 	msm_mux_cri_trng1,
473 	msm_mux_gp_pdm2,
474 	msm_mux_sp_cmu,
475 	msm_mux_atest_usb2,
476 	msm_mux_atest_usb23,
477 	msm_mux_uim2_data,
478 	msm_mux_uim2_clk,
479 	msm_mux_uim2_reset,
480 	msm_mux_atest_usb22,
481 	msm_mux_uim2_present,
482 	msm_mux_atest_usb21,
483 	msm_mux_uim1_data,
484 	msm_mux_atest_usb20,
485 	msm_mux_uim1_clk,
486 	msm_mux_uim1_reset,
487 	msm_mux_uim1_present,
488 	msm_mux_mdp_vsync,
489 	msm_mux_copy_gp,
490 	msm_mux_tsense_pwm,
491 	msm_mux_mpm_pwr,
492 	msm_mux_tgu_ch3,
493 	msm_mux_mdp_vsync0,
494 	msm_mux_mdp_vsync1,
495 	msm_mux_mdp_vsync2,
496 	msm_mux_mdp_vsync3,
497 	msm_mux_mdp_vsync4,
498 	msm_mux_mdp_vsync5,
499 	msm_mux_tgu_ch0,
500 	msm_mux_tgu_ch1,
501 	msm_mux_atest_char1,
502 	msm_mux_vfr_1,
503 	msm_mux_tgu_ch2,
504 	msm_mux_atest_char0,
505 	msm_mux_atest_char2,
506 	msm_mux_atest_char3,
507 	msm_mux_ldo_en,
508 	msm_mux_ldo_update,
509 	msm_mux_prng_rosc,
510 	msm_mux_dp_hot,
511 	msm_mux_debug_hot,
512 	msm_mux_copy_phase,
513 	msm_mux_usb_phy,
514 	msm_mux_atest_char,
515 	msm_mux_unused1,
516 	msm_mux_qua_mi2s,
517 	msm_mux_mss_lte,
518 	msm_mux_swr_tx,
519 	msm_mux_aud_sb,
520 	msm_mux_unused2,
521 	msm_mux_swr_rx,
522 	msm_mux_edp_hot,
523 	msm_mux_audio_ref,
524 	msm_mux_pri_mi2s,
525 	msm_mux_pri_mi2s_ws,
526 	msm_mux_adsp_ext,
527 	msm_mux_edp_lcd,
528 	msm_mux_mclk2,
529 	msm_mux_m_voc,
530 	msm_mux_mclk1,
531 	msm_mux_qca_sb,
532 	msm_mux_qui_mi2s,
533 	msm_mux_dmic0_clk,
534 	msm_mux_sec_mi2s,
535 	msm_mux_dmic0_data,
536 	msm_mux_dmic1_clk,
537 	msm_mux_dmic1_data,
538 	msm_mux__,
539 };
540 
541 static const char * const qup00_groups[] = {
542 	"gpio0", "gpio1", "gpio2", "gpio3",
543 };
544 static const char * const gpio_groups[] = {
545 	"gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
546 	"gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
547 	"gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
548 	"gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
549 	"gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
550 	"gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
551 	"gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
552 	"gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
553 	"gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
554 	"gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70",
555 	"gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77",
556 	"gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84",
557 	"gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91",
558 	"gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98",
559 	"gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104",
560 	"gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110",
561 	"gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116",
562 	"gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122",
563 	"gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128",
564 	"gpio129", "gpio130", "gpio131", "gpio132",
565 };
566 static const char * const qdss_groups[] = {
567 	"gpio0", "gpio1", "gpio2", "gpio3", "gpio20", "gpio21", "gpio34", "gpio35",
568 	"gpio36", "gpio42", "gpio41", "gpio43", "gpio44", "gpio45", "gpio46",
569 	"gpio47", "gpio48", "gpio49", "gpio80", "gpio81", "gpio82", "gpio83",
570 	"gpio84", "gpio85", "gpio86", "gpio91", "gpio92", "gpio94", "gpio96",
571 	"gpio100", "gpio102", "gpio114", "gpio115", "gpio116", "gpio117", "gpio118",
572 };
573 static const char * const qup01_groups[] = {
574 	"gpio4", "gpio5",
575 };
576 static const char * const qup02_groups[] = {
577 	"gpio6", "gpio7", "gpio8", "gpio9",
578 };
579 static const char * const ddr_pxi0_groups[] = {
580 	"gpio6", "gpio7",
581 };
582 static const char * const ddr_bist_groups[] = {
583 	"gpio7", "gpio8", "gpio9", "gpio10",
584 };
585 static const char * const atest_tsens2_groups[] = {
586 	"gpio7",
587 };
588 static const char * const vsense_trigger_groups[] = {
589 	"gpio7",
590 };
591 static const char * const atest_usb1_groups[] = {
592 	"gpio7",
593 };
594 static const char * const gp_pdm1_groups[] = {
595 	"gpio8", "gpio65",
596 };
597 static const char * const phase_flag_groups[] = {
598 	"gpio8", "gpio9", "gpio23", "gpio24", "gpio25", "gpio26", "gpio28",
599 	"gpio29", "gpio30", "gpio53", "gpio54", "gpio55", "gpio56", "gpio57",
600 	"gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio80", "gpio81",
601 	"gpio82", "gpio83", "gpio84", "gpio88", "gpio89", "gpio91", "gpio93",
602 	"gpio98", "gpio129", "gpio130", "gpio131",
603 };
604 static const char * const dbg_out_groups[] = {
605 	"gpio9",
606 };
607 static const char * const qup14_groups[] = {
608 	"gpio10", "gpio11", "gpio12", "gpio13",
609 };
610 static const char * const atest_usb11_groups[] = {
611 	"gpio10",
612 };
613 static const char * const ddr_pxi2_groups[] = {
614 	"gpio10", "gpio11",
615 };
616 static const char * const atest_usb10_groups[] = {
617 	"gpio11",
618 };
619 static const char * const jitter_bist_groups[] = {
620 	"gpio12", "gpio31",
621 };
622 static const char * const ddr_pxi3_groups[] = {
623 	"gpio12", "gpio13",
624 };
625 static const char * const pll_bypassnl_groups[] = {
626 	"gpio13",
627 };
628 static const char * const pll_bist_groups[] = {
629 	"gpio13", "gpio32",
630 };
631 static const char * const qup03_groups[] = {
632 	"gpio14", "gpio15",
633 };
634 static const char * const pll_reset_groups[] = {
635 	"gpio14",
636 };
637 static const char * const agera_pll_groups[] = {
638 	"gpio14", "gpio33",
639 };
640 static const char * const qdss_cti_groups[] = {
641 	"gpio14", "gpio15", "gpio95", "gpio101", "gpio106", "gpio107",
642 	"gpio110", "gpio111",
643 };
644 static const char * const qup04_groups[] = {
645 	"gpio16", "gpio17",
646 };
647 static const char * const wlan2_adc1_groups[] = {
648 	"gpio16",
649 };
650 static const char * const wlan2_adc0_groups[] = {
651 	"gpio17",
652 };
653 static const char * const wsa_clk_groups[] = {
654 	"gpio18",
655 };
656 static const char * const qup13_groups[] = {
657 	"gpio18", "gpio19", "gpio20", "gpio21",
658 };
659 static const char * const ter_mi2s_groups[] = {
660 	"gpio18", "gpio19", "gpio20", "gpio21",
661 };
662 static const char * const wsa_data_groups[] = {
663 	"gpio19",
664 };
665 static const char * const qup10_groups[] = {
666 	"gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27",
667 };
668 static const char * const gcc_gp3_groups[] = {
669 	"gpio22", "gpio58",
670 };
671 static const char * const qup12_groups[] = {
672 	"gpio28", "gpio29",
673 };
674 static const char * const sd_write_groups[] = {
675 	"gpio29",
676 };
677 static const char * const qup11_groups[] = {
678 	"gpio30", "gpio31", "gpio32", "gpio33",
679 };
680 static const char * const cam_mclk_groups[] = {
681 	"gpio34", "gpio35", "gpio36", "gpio44",
682 };
683 static const char * const atest_tsens_groups[] = {
684 	"gpio34",
685 };
686 static const char * const cci_i2c_groups[] = {
687 	"gpio37", "gpio38", "gpio39", "gpio40",
688 };
689 static const char * const cci_timer2_groups[] = {
690 	"gpio42",
691 };
692 static const char * const cci_timer1_groups[] = {
693 	"gpio43",
694 };
695 static const char * const gcc_gp2_groups[] = {
696 	"gpio43", "gpio44",
697 };
698 static const char * const cci_async_groups[] = {
699 	"gpio44", "gpio47", "gpio48",
700 };
701 static const char * const cci_timer4_groups[] = {
702 	"gpio44",
703 };
704 static const char * const cci_timer0_groups[] = {
705 	"gpio45",
706 };
707 static const char * const gcc_gp1_groups[] = {
708 	"gpio45", "gpio46",
709 };
710 static const char * const cci_timer3_groups[] = {
711 	"gpio46",
712 };
713 static const char * const wlan1_adc1_groups[] = {
714 	"gpio47",
715 };
716 static const char * const wlan1_adc0_groups[] = {
717 	"gpio48",
718 };
719 static const char * const qlink_request_groups[] = {
720 	"gpio50",
721 };
722 static const char * const qlink_enable_groups[] = {
723 	"gpio51",
724 };
725 static const char * const pa_indicator_groups[] = {
726 	"gpio52",
727 };
728 static const char * const nav_pps_groups[] = {
729 	"gpio52", "gpio55", "gpio56", "gpio58",
730 	"gpio59",
731 };
732 static const char * const gps_tx_groups[] = {
733 	"gpio52", "gpio53", "gpio55", "gpio56", "gpio58", "gpio59",
734 };
735 static const char * const gp_pdm0_groups[] = {
736 	"gpio53", "gpio94",
737 };
738 static const char * const atest_usb13_groups[] = {
739 	"gpio53",
740 };
741 static const char * const ddr_pxi1_groups[] = {
742 	"gpio53", "gpio54",
743 };
744 static const char * const atest_usb12_groups[] = {
745 	"gpio54",
746 };
747 static const char * const cri_trng0_groups[] = {
748 	"gpio59",
749 };
750 static const char * const cri_trng_groups[] = {
751 	"gpio60",
752 };
753 static const char * const cri_trng1_groups[] = {
754 	"gpio61",
755 };
756 static const char * const gp_pdm2_groups[] = {
757 	"gpio62", "gpio78",
758 };
759 static const char * const sp_cmu_groups[] = {
760 	"gpio63",
761 };
762 static const char * const atest_usb2_groups[] = {
763 	"gpio66",
764 };
765 static const char * const atest_usb23_groups[] = {
766 	"gpio67",
767 };
768 static const char * const uim2_data_groups[] = {
769 	"gpio72",
770 };
771 static const char * const uim2_clk_groups[] = {
772 	"gpio73",
773 };
774 static const char * const uim2_reset_groups[] = {
775 	"gpio74",
776 };
777 static const char * const atest_usb22_groups[] = {
778 	"gpio74",
779 };
780 static const char * const uim2_present_groups[] = {
781 	"gpio75",
782 };
783 static const char * const atest_usb21_groups[] = {
784 	"gpio75",
785 };
786 static const char * const uim1_data_groups[] = {
787 	"gpio76",
788 };
789 static const char * const atest_usb20_groups[] = {
790 	"gpio76",
791 };
792 static const char * const uim1_clk_groups[] = {
793 	"gpio77",
794 };
795 static const char * const uim1_reset_groups[] = {
796 	"gpio78",
797 };
798 static const char * const uim1_present_groups[] = {
799 	"gpio79",
800 };
801 static const char * const mdp_vsync_groups[] = {
802 	"gpio80", "gpio81", "gpio82", "gpio89", "gpio96", "gpio97",
803 };
804 static const char * const copy_gp_groups[] = {
805 	"gpio85",
806 };
807 static const char * const tsense_pwm_groups[] = {
808 	"gpio87",
809 };
810 static const char * const mpm_pwr_groups[] = {
811 	"gpio88",
812 };
813 static const char * const tgu_ch3_groups[] = {
814 	"gpio88",
815 };
816 static const char * const mdp_vsync0_groups[] = {
817 	"gpio89",
818 };
819 static const char * const mdp_vsync1_groups[] = {
820 	"gpio89",
821 };
822 static const char * const mdp_vsync2_groups[] = {
823 	"gpio89",
824 };
825 static const char * const mdp_vsync3_groups[] = {
826 	"gpio89",
827 };
828 static const char * const mdp_vsync4_groups[] = {
829 	"gpio89",
830 };
831 static const char * const mdp_vsync5_groups[] = {
832 	"gpio89",
833 };
834 static const char * const tgu_ch0_groups[] = {
835 	"gpio89",
836 };
837 static const char * const tgu_ch1_groups[] = {
838 	"gpio90",
839 };
840 static const char * const atest_char1_groups[] = {
841 	"gpio90",
842 };
843 static const char * const vfr_1_groups[] = {
844 	"gpio91",
845 };
846 static const char * const tgu_ch2_groups[] = {
847 	"gpio91",
848 };
849 static const char * const atest_char0_groups[] = {
850 	"gpio92",
851 };
852 static const char * const atest_char2_groups[] = {
853 	"gpio93",
854 };
855 static const char * const atest_char3_groups[] = {
856 	"gpio94",
857 };
858 static const char * const ldo_en_groups[] = {
859 	"gpio96",
860 };
861 static const char * const ldo_update_groups[] = {
862 	"gpio97",
863 };
864 static const char * const prng_rosc_groups[] = {
865 	"gpio98", "gpio100",
866 };
867 static const char * const dp_hot_groups[] = {
868 	"gpio100",
869 };
870 static const char * const debug_hot_groups[] = {
871 	"gpio101",
872 };
873 static const char * const copy_phase_groups[] = {
874 	"gpio101",
875 };
876 static const char * const usb_phy_groups[] = {
877 	"gpio102",
878 };
879 static const char * const atest_char_groups[] = {
880 	"gpio102",
881 };
882 static const char * const unused1_groups[] = {
883 	"gpio104",
884 };
885 static const char * const qua_mi2s_groups[] = {
886 	"gpio104", "gpio106", "gpio107", "gpio108", "gpio110", "gpio111",
887 };
888 static const char * const mss_lte_groups[] = {
889 	"gpio105", "gpio109",
890 };
891 static const char * const swr_tx_groups[] = {
892 	"gpio106", "gpio107", "gpio108", "gpio109",
893 };
894 static const char * const aud_sb_groups[] = {
895 	"gpio106", "gpio107", "gpio108", "gpio109",
896 };
897 static const char * const unused2_groups[] = {
898 	"gpio109",
899 };
900 static const char * const swr_rx_groups[] = {
901 	"gpio110", "gpio111", "gpio112",
902 };
903 static const char * const edp_hot_groups[] = {
904 	"gpio111",
905 };
906 static const char * const audio_ref_groups[] = {
907 	"gpio112",
908 };
909 static const char * const pri_mi2s_groups[] = {
910 	"gpio113", "gpio115", "gpio116",
911 };
912 static const char * const pri_mi2s_ws_groups[] = {
913 	"gpio114",
914 };
915 static const char * const adsp_ext_groups[] = {
916 	"gpio116",
917 };
918 static const char * const edp_lcd_groups[] = {
919 	"gpio117",
920 };
921 static const char * const mclk2_groups[] = {
922 	"gpio118",
923 };
924 static const char * const m_voc_groups[] = {
925 	"gpio118",
926 };
927 static const char * const mclk1_groups[] = {
928 	"gpio119",
929 };
930 static const char * const qca_sb_groups[] = {
931 	"gpio121", "gpio122",
932 };
933 static const char * const qui_mi2s_groups[] = {
934 	"gpio121", "gpio122", "gpio123", "gpio124",
935 };
936 static const char * const dmic0_clk_groups[] = {
937 	"gpio125",
938 };
939 static const char * const sec_mi2s_groups[] = {
940 	"gpio125", "gpio126", "gpio127", "gpio128",
941 };
942 static const char * const dmic0_data_groups[] = {
943 	"gpio126",
944 };
945 static const char * const dmic1_clk_groups[] = {
946 	"gpio127",
947 };
948 static const char * const dmic1_data_groups[] = {
949 	"gpio128",
950 };
951 
952 static const struct msm_function sm6125_functions[] = {
953 	FUNCTION(qup00),
954 	FUNCTION(gpio),
955 	FUNCTION(qdss),
956 	FUNCTION(qup01),
957 	FUNCTION(qup02),
958 	FUNCTION(ddr_pxi0),
959 	FUNCTION(ddr_bist),
960 	FUNCTION(atest_tsens2),
961 	FUNCTION(vsense_trigger),
962 	FUNCTION(atest_usb1),
963 	FUNCTION(gp_pdm1),
964 	FUNCTION(phase_flag),
965 	FUNCTION(dbg_out),
966 	FUNCTION(qup14),
967 	FUNCTION(atest_usb11),
968 	FUNCTION(ddr_pxi2),
969 	FUNCTION(atest_usb10),
970 	FUNCTION(jitter_bist),
971 	FUNCTION(ddr_pxi3),
972 	FUNCTION(pll_bypassnl),
973 	FUNCTION(pll_bist),
974 	FUNCTION(qup03),
975 	FUNCTION(pll_reset),
976 	FUNCTION(agera_pll),
977 	FUNCTION(qdss_cti),
978 	FUNCTION(qup04),
979 	FUNCTION(wlan2_adc1),
980 	FUNCTION(wlan2_adc0),
981 	FUNCTION(wsa_clk),
982 	FUNCTION(qup13),
983 	FUNCTION(ter_mi2s),
984 	FUNCTION(wsa_data),
985 	FUNCTION(qup10),
986 	FUNCTION(gcc_gp3),
987 	FUNCTION(qup12),
988 	FUNCTION(sd_write),
989 	FUNCTION(qup11),
990 	FUNCTION(cam_mclk),
991 	FUNCTION(atest_tsens),
992 	FUNCTION(cci_i2c),
993 	FUNCTION(cci_timer2),
994 	FUNCTION(cci_timer1),
995 	FUNCTION(gcc_gp2),
996 	FUNCTION(cci_async),
997 	FUNCTION(cci_timer4),
998 	FUNCTION(cci_timer0),
999 	FUNCTION(gcc_gp1),
1000 	FUNCTION(cci_timer3),
1001 	FUNCTION(wlan1_adc1),
1002 	FUNCTION(wlan1_adc0),
1003 	FUNCTION(qlink_request),
1004 	FUNCTION(qlink_enable),
1005 	FUNCTION(pa_indicator),
1006 	FUNCTION(nav_pps),
1007 	FUNCTION(gps_tx),
1008 	FUNCTION(gp_pdm0),
1009 	FUNCTION(atest_usb13),
1010 	FUNCTION(ddr_pxi1),
1011 	FUNCTION(atest_usb12),
1012 	FUNCTION(cri_trng0),
1013 	FUNCTION(cri_trng),
1014 	FUNCTION(cri_trng1),
1015 	FUNCTION(gp_pdm2),
1016 	FUNCTION(sp_cmu),
1017 	FUNCTION(atest_usb2),
1018 	FUNCTION(atest_usb23),
1019 	FUNCTION(uim2_data),
1020 	FUNCTION(uim2_clk),
1021 	FUNCTION(uim2_reset),
1022 	FUNCTION(atest_usb22),
1023 	FUNCTION(uim2_present),
1024 	FUNCTION(atest_usb21),
1025 	FUNCTION(uim1_data),
1026 	FUNCTION(atest_usb20),
1027 	FUNCTION(uim1_clk),
1028 	FUNCTION(uim1_reset),
1029 	FUNCTION(uim1_present),
1030 	FUNCTION(mdp_vsync),
1031 	FUNCTION(copy_gp),
1032 	FUNCTION(tsense_pwm),
1033 	FUNCTION(mpm_pwr),
1034 	FUNCTION(tgu_ch3),
1035 	FUNCTION(mdp_vsync0),
1036 	FUNCTION(mdp_vsync1),
1037 	FUNCTION(mdp_vsync2),
1038 	FUNCTION(mdp_vsync3),
1039 	FUNCTION(mdp_vsync4),
1040 	FUNCTION(mdp_vsync5),
1041 	FUNCTION(tgu_ch0),
1042 	FUNCTION(tgu_ch1),
1043 	FUNCTION(atest_char1),
1044 	FUNCTION(vfr_1),
1045 	FUNCTION(tgu_ch2),
1046 	FUNCTION(atest_char0),
1047 	FUNCTION(atest_char2),
1048 	FUNCTION(atest_char3),
1049 	FUNCTION(ldo_en),
1050 	FUNCTION(ldo_update),
1051 	FUNCTION(prng_rosc),
1052 	FUNCTION(dp_hot),
1053 	FUNCTION(debug_hot),
1054 	FUNCTION(copy_phase),
1055 	FUNCTION(usb_phy),
1056 	FUNCTION(atest_char),
1057 	FUNCTION(unused1),
1058 	FUNCTION(qua_mi2s),
1059 	FUNCTION(mss_lte),
1060 	FUNCTION(swr_tx),
1061 	FUNCTION(aud_sb),
1062 	FUNCTION(unused2),
1063 	FUNCTION(swr_rx),
1064 	FUNCTION(edp_hot),
1065 	FUNCTION(audio_ref),
1066 	FUNCTION(pri_mi2s),
1067 	FUNCTION(pri_mi2s_ws),
1068 	FUNCTION(adsp_ext),
1069 	FUNCTION(edp_lcd),
1070 	FUNCTION(mclk2),
1071 	FUNCTION(m_voc),
1072 	FUNCTION(mclk1),
1073 	FUNCTION(qca_sb),
1074 	FUNCTION(qui_mi2s),
1075 	FUNCTION(dmic0_clk),
1076 	FUNCTION(sec_mi2s),
1077 	FUNCTION(dmic0_data),
1078 	FUNCTION(dmic1_clk),
1079 	FUNCTION(dmic1_data),
1080 };
1081 
1082  /*
1083  * Every pin is maintained as a single group, and missing or non-existing pin
1084  * would be maintained as dummy group to synchronize pin group index with
1085  * pin descriptor registered with pinctrl core.
1086  * Clients would not be able to request these dummy pin groups.
1087  */
1088 static const struct msm_pingroup sm6125_groups[] = {
1089 	[0] = PINGROUP(0, WEST, qup00, _, qdss, _, _, _, _, _, _),
1090 	[1] = PINGROUP(1, WEST, qup00, _, qdss, _, _, _, _, _, _),
1091 	[2] = PINGROUP(2, WEST, qup00, _, qdss, _, _, _, _, _, _),
1092 	[3] = PINGROUP(3, WEST, qup00, _, qdss, _, _, _, _, _, _),
1093 	[4] = PINGROUP(4, WEST, qup01, _, _, _, _, _, _, _, _),
1094 	[5] = PINGROUP(5, WEST, qup01, _, _, _, _, _, _, _, _),
1095 	[6] = PINGROUP(6, WEST, qup02, ddr_pxi0, _, _, _, _, _, _, _),
1096 	[7] = PINGROUP(7, WEST, qup02, ddr_bist, atest_tsens2, vsense_trigger, atest_usb1, ddr_pxi0, _, _, _),
1097 	[8] = PINGROUP(8, WEST, qup02, gp_pdm1, ddr_bist, _, phase_flag, _, _, _, _),
1098 	[9] = PINGROUP(9, WEST, qup02, ddr_bist, dbg_out, phase_flag, _, _, _, _, _),
1099 	[10] = PINGROUP(10, EAST, qup14, ddr_bist, atest_usb11, ddr_pxi2, _, _, _, _, _),
1100 	[11] = PINGROUP(11, EAST, qup14, atest_usb10, ddr_pxi2, _, _, _, _, _, _),
1101 	[12] = PINGROUP(12, EAST, qup14, jitter_bist, ddr_pxi3, _, _, _, _, _, _),
1102 	[13] = PINGROUP(13, EAST, qup14, pll_bypassnl, pll_bist, _, ddr_pxi3, _, _, _, _),
1103 	[14] = PINGROUP(14, WEST, qup03, qup03, pll_reset, agera_pll, _, qdss_cti, _, _, _),
1104 	[15] = PINGROUP(15, WEST, qup03, qup03, qdss_cti, _, _, _, _, _, _),
1105 	[16] = PINGROUP(16, WEST, qup04, qup04, _, wlan2_adc1, _, _, _, _, _),
1106 	[17] = PINGROUP(17, WEST, qup04, qup04, _, wlan2_adc0, _, _, _, _, _),
1107 	[18] = PINGROUP(18, EAST, wsa_clk, qup13, ter_mi2s, _, _, _, _, _, _),
1108 	[19] = PINGROUP(19, EAST, wsa_data, qup13, ter_mi2s, _, _, _, _, _, _),
1109 	[20] = PINGROUP(20, EAST, qup13, ter_mi2s, qdss, _, _, _, _, _, _),
1110 	[21] = PINGROUP(21, EAST, qup13, ter_mi2s, _, qdss, _, _, _, _, _),
1111 	[22] = PINGROUP(22, WEST, qup10, gcc_gp3, _, _, _, _, _, _, _),
1112 	[23] = PINGROUP(23, WEST, qup10, _, phase_flag, _, _, _, _, _, _),
1113 	[24] = PINGROUP(24, WEST, qup10, _, phase_flag, _, _, _, _, _, _),
1114 	[25] = PINGROUP(25, WEST, qup10, _, phase_flag, _, _, _, _, _, _),
1115 	[26] = PINGROUP(26, WEST, qup10, _, phase_flag, _, _, _, _, _, _),
1116 	[27] = PINGROUP(27, WEST, qup10, _, _, _, _, _, _, _, _),
1117 	[28] = PINGROUP(28, WEST, qup12, _, phase_flag, _, _, _, _, _, _),
1118 	[29] = PINGROUP(29, WEST, qup12, sd_write, _, phase_flag, _, _, _, _, _),
1119 	[30] = PINGROUP(30, WEST, qup11, _, phase_flag, _, _, _, _, _, _),
1120 	[31] = PINGROUP(31, WEST, qup11, jitter_bist, _, _, _, _, _, _, _),
1121 	[32] = PINGROUP(32, WEST, qup11, pll_bist, _, _, _, _, _, _, _),
1122 	[33] = PINGROUP(33, WEST, qup11, agera_pll, _, _, _, _, _, _, _),
1123 	[34] = PINGROUP(34, SOUTH, cam_mclk, _, qdss, atest_tsens, _, _, _, _, _),
1124 	[35] = PINGROUP(35, SOUTH, cam_mclk, _, qdss, _, _, _, _, _, _),
1125 	[36] = PINGROUP(36, SOUTH, cam_mclk, _, qdss, _, _, _, _, _, _),
1126 	[37] = PINGROUP(37, SOUTH, cci_i2c, _, _, _, _, _, _, _, _),
1127 	[38] = PINGROUP(38, EAST, cci_i2c, _, _, _, _, _, _, _, _),
1128 	[39] = PINGROUP(39, EAST, cci_i2c, _, _, _, _, _, _, _, _),
1129 	[40] = PINGROUP(40, EAST, cci_i2c, _, _, _, _, _, _, _, _),
1130 	[41] = PINGROUP(41, EAST, _, qdss, _, _, _, _, _, _, _),
1131 	[42] = PINGROUP(42, EAST, cci_timer2, _, qdss, _, _, _, _, _, _),
1132 	[43] = PINGROUP(43, EAST, cci_timer1, _, gcc_gp2, _, qdss, _, _, _, _),
1133 	[44] = PINGROUP(44, SOUTH, cci_async, cci_timer4, _, gcc_gp2, _, qdss, cam_mclk, _, _),
1134 	[45] = PINGROUP(45, SOUTH, cci_timer0, _, gcc_gp1, qdss, _, _, _, _, _),
1135 	[46] = PINGROUP(46, SOUTH, cci_timer3, _, gcc_gp1, _, qdss, _, _, _, _),
1136 	[47] = PINGROUP(47, SOUTH, cci_async, _, qdss, wlan1_adc1, _, _, _, _, _),
1137 	[48] = PINGROUP(48, SOUTH, cci_async, _, qdss, wlan1_adc0, _, _, _, _, _),
1138 	[49] = PINGROUP(49, SOUTH, qdss, _, _, _, _, _, _, _, _),
1139 	[50] = PINGROUP(50, SOUTH, qlink_request, _, _, _, _, _, _, _, _),
1140 	[51] = PINGROUP(51, SOUTH, qlink_enable, _, _, _, _, _, _, _, _),
1141 	[52] = PINGROUP(52, SOUTH, pa_indicator, nav_pps, nav_pps, gps_tx, _, _, _, _, _),
1142 	[53] = PINGROUP(53, SOUTH, _, gps_tx, gp_pdm0, _, phase_flag, atest_usb13, ddr_pxi1, _, _),
1143 	[54] = PINGROUP(54, SOUTH, _, _, phase_flag, atest_usb12, ddr_pxi1, _, _, _, _),
1144 	[55] = PINGROUP(55, SOUTH, _, nav_pps, nav_pps, gps_tx, _, phase_flag, _, _, _),
1145 	[56] = PINGROUP(56, SOUTH, _, nav_pps, gps_tx, nav_pps, phase_flag, _, _, _, _),
1146 	[57] = PINGROUP(57, SOUTH, _, phase_flag, _, _, _, _, _, _, _),
1147 	[58] = PINGROUP(58, SOUTH, _, nav_pps, nav_pps, gps_tx, gcc_gp3, _, phase_flag, _, _),
1148 	[59] = PINGROUP(59, SOUTH, _, nav_pps, nav_pps, gps_tx, cri_trng0, _, phase_flag, _, _),
1149 	[60] = PINGROUP(60, SOUTH, _, cri_trng, _, phase_flag, _, _, _, _, _),
1150 	[61] = PINGROUP(61, SOUTH, _, cri_trng1, _, phase_flag, _, _, _, _, _),
1151 	[62] = PINGROUP(62, SOUTH, _, _, gp_pdm2, _, phase_flag, _, _, _, _),
1152 	[63] = PINGROUP(63, SOUTH, _, sp_cmu, _, _, _, _, _, _, _),
1153 	[64] = PINGROUP(64, SOUTH, _, _, _, _, _, _, _, _, _),
1154 	[65] = PINGROUP(65, SOUTH, _, gp_pdm1, _, _, _, _, _, _, _),
1155 	[66] = PINGROUP(66, SOUTH, _, _, atest_usb2, _, _, _, _, _, _),
1156 	[67] = PINGROUP(67, SOUTH, _, _, atest_usb23, _, _, _, _, _, _),
1157 	[68] = PINGROUP(68, SOUTH, _, _, _, _, _, _, _, _, _),
1158 	[69] = PINGROUP(69, SOUTH, _, _, _, _, _, _, _, _, _),
1159 	[70] = PINGROUP(70, SOUTH, _, _, _, _, _, _, _, _, _),
1160 	[71] = PINGROUP(71, SOUTH, _, _, _, _, _, _, _, _, _),
1161 	[72] = PINGROUP(72, SOUTH, uim2_data, _, _, _, _, _, _, _, _),
1162 	[73] = PINGROUP(73, SOUTH, uim2_clk, _, _, _, _, _, _, _, _),
1163 	[74] = PINGROUP(74, SOUTH, uim2_reset, _, atest_usb22, _, _, _, _, _, _),
1164 	[75] = PINGROUP(75, SOUTH, uim2_present, _, atest_usb21, _, _, _, _, _, _),
1165 	[76] = PINGROUP(76, SOUTH, uim1_data, _, atest_usb20, _, _, _, _, _, _),
1166 	[77] = PINGROUP(77, SOUTH, uim1_clk, _, _, _, _, _, _, _, _),
1167 	[78] = PINGROUP(78, SOUTH, uim1_reset, gp_pdm2, _, _, _, _, _, _, _),
1168 	[79] = PINGROUP(79, SOUTH, uim1_present, _, _, _, _, _, _, _, _),
1169 	[80] = PINGROUP(80, SOUTH, mdp_vsync, _, phase_flag, qdss, _, _, _, _, _),
1170 	[81] = PINGROUP(81, SOUTH, mdp_vsync, _, phase_flag, qdss, _, _, _, _, _),
1171 	[82] = PINGROUP(82, SOUTH, mdp_vsync, _, phase_flag, qdss, _, _, _, _, _),
1172 	[83] = PINGROUP(83, SOUTH, _, phase_flag, qdss, _, _, _, _, _, _),
1173 	[84] = PINGROUP(84, SOUTH, _, phase_flag, qdss, _, _, _, _, _, _),
1174 	[85] = PINGROUP(85, SOUTH, copy_gp, _, qdss, _, _, _, _, _, _),
1175 	[86] = PINGROUP(86, SOUTH, _, qdss, _, _, _, _, _, _, _),
1176 	[87] = PINGROUP(87, WEST, tsense_pwm, _, _, _, _, _, _, _, _),
1177 	[88] = PINGROUP(88, WEST, mpm_pwr, tgu_ch3, _, phase_flag, _, _, _, _, _),
1178 	[89] = PINGROUP(89, WEST, mdp_vsync, mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3, mdp_vsync4, mdp_vsync5, tgu_ch0, _),
1179 	[90] = PINGROUP(90, WEST, tgu_ch1, atest_char1, _, _, _, _, _, _, _),
1180 	[91] = PINGROUP(91, WEST, vfr_1, tgu_ch2, _, phase_flag, qdss, _, _, _, _),
1181 	[92] = PINGROUP(92, WEST, qdss, atest_char0, _, _, _, _, _, _, _),
1182 	[93] = PINGROUP(93, WEST, _, phase_flag, atest_char2, _, _, _, _, _, _),
1183 	[94] = PINGROUP(94, SOUTH, gp_pdm0, _, qdss, atest_char3, _, _, _, _, _),
1184 	[95] = PINGROUP(95, SOUTH, qdss_cti, _, _, _, _, _, _, _, _),
1185 	[96] = PINGROUP(96, SOUTH, mdp_vsync, ldo_en, qdss, _, _, _, _, _, _),
1186 	[97] = PINGROUP(97, SOUTH, mdp_vsync, ldo_update, _, _, _, _, _, _, _),
1187 	[98] = PINGROUP(98, SOUTH, _, phase_flag, prng_rosc, _, _, _, _, _, _),
1188 	[99] = PINGROUP(99, SOUTH, _, _, _, _, _, _, _, _, _),
1189 	[100] = PINGROUP(100, SOUTH, dp_hot, prng_rosc, qdss, _, _, _, _, _, _),
1190 	[101] = PINGROUP(101, SOUTH, debug_hot, copy_phase, qdss_cti, _, _, _, _, _, _),
1191 	[102] = PINGROUP(102, SOUTH, usb_phy, _, qdss, atest_char, _, _, _, _, _),
1192 	[103] = PINGROUP(103, SOUTH, _, _, _, _, _, _, _, _, _),
1193 	[104] = PINGROUP(104, EAST, unused1, _, qua_mi2s, _, _, _, _, _, _),
1194 	[105] = PINGROUP(105, EAST, mss_lte, _, _, _, _, _, _, _, _),
1195 	[106] = PINGROUP(106, EAST, swr_tx, aud_sb, qua_mi2s, _, qdss_cti, _, _, _, _),
1196 	[107] = PINGROUP(107, EAST, swr_tx, aud_sb, qua_mi2s, _, qdss_cti, _, _, _, _),
1197 	[108] = PINGROUP(108, EAST, swr_tx, aud_sb, qua_mi2s, _, _, _, _, _, _),
1198 	[109] = PINGROUP(109, EAST, swr_tx, aud_sb, unused2, _, mss_lte, _, _, _, _),
1199 	[110] = PINGROUP(110, EAST, swr_rx, qua_mi2s, _, qdss_cti, _, _, _, _, _),
1200 	[111] = PINGROUP(111, EAST, swr_rx, qua_mi2s, edp_hot, _, qdss_cti, _, _, _, _),
1201 	[112] = PINGROUP(112, EAST, swr_rx, audio_ref, _, _, _, _, _, _, _),
1202 	[113] = PINGROUP(113, EAST, pri_mi2s, _, _, _, _, _, _, _, _),
1203 	[114] = PINGROUP(114, EAST, pri_mi2s_ws, qdss, _, _, _, _, _, _, _),
1204 	[115] = PINGROUP(115, EAST, pri_mi2s, qdss, _, _, _, _, _, _, _),
1205 	[116] = PINGROUP(116, EAST, pri_mi2s, adsp_ext, qdss, _, _, _, _, _, _),
1206 	[117] = PINGROUP(117, SOUTH, edp_lcd, qdss, _, _, _, _, _, _, _),
1207 	[118] = PINGROUP(118, SOUTH, mclk2, m_voc, qdss, _, _, _, _, _, _),
1208 	[119] = PINGROUP(119, SOUTH, mclk1, _, _, _, _, _, _, _, _),
1209 	[120] = PINGROUP(120, SOUTH, _, _, _, _, _, _, _, _, _),
1210 	[121] = PINGROUP(121, EAST, qca_sb, qui_mi2s, _, _, _, _, _, _, _),
1211 	[122] = PINGROUP(122, EAST, qca_sb, qui_mi2s, _, _, _, _, _, _, _),
1212 	[123] = PINGROUP(123, EAST, qui_mi2s, _, _, _, _, _, _, _, _),
1213 	[124] = PINGROUP(124, EAST, qui_mi2s, _, _, _, _, _, _, _, _),
1214 	[125] = PINGROUP(125, EAST, dmic0_clk, sec_mi2s, _, _, _, _, _, _, _),
1215 	[126] = PINGROUP(126, EAST, dmic0_data, sec_mi2s, _, _, _, _, _, _, _),
1216 	[127] = PINGROUP(127, EAST, dmic1_clk, sec_mi2s, _, _, _, _, _, _, _),
1217 	[128] = PINGROUP(128, EAST, dmic1_data, sec_mi2s, _, _, _, _, _, _, _),
1218 	[129] = PINGROUP(129, SOUTH, _, phase_flag, _, _, _, _, _, _, _),
1219 	[130] = PINGROUP(130, SOUTH, phase_flag, _, _, _, _, _, _, _, _),
1220 	[131] = PINGROUP(131, SOUTH, phase_flag, _, _, _, _, _, _, _, _),
1221 	[132] = PINGROUP(132, SOUTH, _, _, _, _, _, _, _, _, _),
1222 	[133] = UFS_RESET(ufs_reset, 0x190000),
1223 	[134] = SDC_QDSD_PINGROUP(sdc1_rclk, WEST, 0x18d000, 15, 0),
1224 	[135] = SDC_QDSD_PINGROUP(sdc1_clk, WEST, 0x18d000, 13, 6),
1225 	[136] = SDC_QDSD_PINGROUP(sdc1_cmd, WEST, 0x18d000, 11, 3),
1226 	[137] = SDC_QDSD_PINGROUP(sdc1_data, WEST, 0x18d000, 9, 0),
1227 	[138] = SDC_QDSD_PINGROUP(sdc2_clk, SOUTH, 0x58b000, 14, 6),
1228 	[139] = SDC_QDSD_PINGROUP(sdc2_cmd, SOUTH, 0x58b000, 11, 3),
1229 	[140] = SDC_QDSD_PINGROUP(sdc2_data, SOUTH, 0x58b000, 9, 0),
1230 };
1231 
1232 static const struct msm_pinctrl_soc_data sm6125_tlmm = {
1233 	.pins = sm6125_pins,
1234 	.npins = ARRAY_SIZE(sm6125_pins),
1235 	.functions = sm6125_functions,
1236 	.nfunctions = ARRAY_SIZE(sm6125_functions),
1237 	.groups = sm6125_groups,
1238 	.ngroups = ARRAY_SIZE(sm6125_groups),
1239 	.ngpios = 134,
1240 	.tiles = sm6125_tiles,
1241 	.ntiles = ARRAY_SIZE(sm6125_tiles),
1242 };
1243 
1244 static int sm6125_tlmm_probe(struct platform_device *pdev)
1245 {
1246 	return msm_pinctrl_probe(pdev, &sm6125_tlmm);
1247 }
1248 
1249 static const struct of_device_id sm6125_tlmm_of_match[] = {
1250 	{ .compatible = "qcom,sm6125-tlmm", },
1251 	{ },
1252 };
1253 
1254 static struct platform_driver sm6125_tlmm_driver = {
1255 	.driver = {
1256 		.name = "sm6125-tlmm",
1257 		.of_match_table = sm6125_tlmm_of_match,
1258 	},
1259 	.probe = sm6125_tlmm_probe,
1260 	.remove = msm_pinctrl_remove,
1261 };
1262 
1263 static int __init sm6125_tlmm_init(void)
1264 {
1265 	return platform_driver_register(&sm6125_tlmm_driver);
1266 }
1267 arch_initcall(sm6125_tlmm_init);
1268 
1269 static void __exit sm6125_tlmm_exit(void)
1270 {
1271 	platform_driver_unregister(&sm6125_tlmm_driver);
1272 }
1273 module_exit(sm6125_tlmm_exit);
1274 
1275 MODULE_DESCRIPTION("QTI sm6125 TLMM driver");
1276 MODULE_LICENSE("GPL v2");
1277 MODULE_DEVICE_TABLE(of, sm6125_tlmm_of_match);
1278