1*0f936752SRohit Agarwal // SPDX-License-Identifier: GPL-2.0-only 2*0f936752SRohit Agarwal /* 3*0f936752SRohit Agarwal * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 4*0f936752SRohit Agarwal */ 5*0f936752SRohit Agarwal 6*0f936752SRohit Agarwal #include <linux/module.h> 7*0f936752SRohit Agarwal #include <linux/of.h> 8*0f936752SRohit Agarwal #include <linux/of_device.h> 9*0f936752SRohit Agarwal #include <linux/platform_device.h> 10*0f936752SRohit Agarwal #include "pinctrl-msm.h" 11*0f936752SRohit Agarwal 12*0f936752SRohit Agarwal #define REG_BASE 0x100000 13*0f936752SRohit Agarwal #define REG_SIZE 0x1000 14*0f936752SRohit Agarwal 15*0f936752SRohit Agarwal #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10) \ 16*0f936752SRohit Agarwal { \ 17*0f936752SRohit Agarwal .grp = PINCTRL_PINGROUP("gpio"#id, gpio##id##_pins, \ 18*0f936752SRohit Agarwal (unsigned int)ARRAY_SIZE(gpio##id##_pins)), \ 19*0f936752SRohit Agarwal .ctl_reg = REG_BASE + REG_SIZE * id, \ 20*0f936752SRohit Agarwal .io_reg = REG_BASE + 0x4 + REG_SIZE * id, \ 21*0f936752SRohit Agarwal .intr_cfg_reg = REG_BASE + 0x8 + REG_SIZE * id, \ 22*0f936752SRohit Agarwal .intr_status_reg = REG_BASE + 0xc + REG_SIZE * id, \ 23*0f936752SRohit Agarwal .intr_target_reg = REG_BASE + 0x8 + REG_SIZE * id, \ 24*0f936752SRohit Agarwal .mux_bit = 2, \ 25*0f936752SRohit Agarwal .pull_bit = 0, \ 26*0f936752SRohit Agarwal .drv_bit = 6, \ 27*0f936752SRohit Agarwal .egpio_enable = 12, \ 28*0f936752SRohit Agarwal .egpio_present = 11, \ 29*0f936752SRohit Agarwal .oe_bit = 9, \ 30*0f936752SRohit Agarwal .in_bit = 0, \ 31*0f936752SRohit Agarwal .out_bit = 1, \ 32*0f936752SRohit Agarwal .intr_enable_bit = 0, \ 33*0f936752SRohit Agarwal .intr_status_bit = 0, \ 34*0f936752SRohit Agarwal .intr_target_bit = 5, \ 35*0f936752SRohit Agarwal .intr_target_kpss_val = 3, \ 36*0f936752SRohit Agarwal .intr_raw_status_bit = 4, \ 37*0f936752SRohit Agarwal .intr_polarity_bit = 1, \ 38*0f936752SRohit Agarwal .intr_detection_bit = 2, \ 39*0f936752SRohit Agarwal .intr_detection_width = 2, \ 40*0f936752SRohit Agarwal .funcs = (int[]){ \ 41*0f936752SRohit Agarwal msm_mux_gpio, /* gpio mode */ \ 42*0f936752SRohit Agarwal msm_mux_##f1, \ 43*0f936752SRohit Agarwal msm_mux_##f2, \ 44*0f936752SRohit Agarwal msm_mux_##f3, \ 45*0f936752SRohit Agarwal msm_mux_##f4, \ 46*0f936752SRohit Agarwal msm_mux_##f5, \ 47*0f936752SRohit Agarwal msm_mux_##f6, \ 48*0f936752SRohit Agarwal msm_mux_##f7, \ 49*0f936752SRohit Agarwal msm_mux_##f8, \ 50*0f936752SRohit Agarwal msm_mux_##f9, \ 51*0f936752SRohit Agarwal msm_mux_##f10 \ 52*0f936752SRohit Agarwal }, \ 53*0f936752SRohit Agarwal .nfuncs = 11, \ 54*0f936752SRohit Agarwal } 55*0f936752SRohit Agarwal 56*0f936752SRohit Agarwal #define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \ 57*0f936752SRohit Agarwal { \ 58*0f936752SRohit Agarwal .grp = PINCTRL_PINGROUP(#pg_name, pg_name##_pins, \ 59*0f936752SRohit Agarwal (unsigned int)ARRAY_SIZE(pg_name##_pins)), \ 60*0f936752SRohit Agarwal .ctl_reg = ctl, \ 61*0f936752SRohit Agarwal .io_reg = 0, \ 62*0f936752SRohit Agarwal .intr_cfg_reg = 0, \ 63*0f936752SRohit Agarwal .intr_status_reg = 0, \ 64*0f936752SRohit Agarwal .intr_target_reg = 0, \ 65*0f936752SRohit Agarwal .mux_bit = -1, \ 66*0f936752SRohit Agarwal .pull_bit = pull, \ 67*0f936752SRohit Agarwal .drv_bit = drv, \ 68*0f936752SRohit Agarwal .oe_bit = -1, \ 69*0f936752SRohit Agarwal .in_bit = -1, \ 70*0f936752SRohit Agarwal .out_bit = -1, \ 71*0f936752SRohit Agarwal .intr_enable_bit = -1, \ 72*0f936752SRohit Agarwal .intr_status_bit = -1, \ 73*0f936752SRohit Agarwal .intr_target_bit = -1, \ 74*0f936752SRohit Agarwal .intr_raw_status_bit = -1, \ 75*0f936752SRohit Agarwal .intr_polarity_bit = -1, \ 76*0f936752SRohit Agarwal .intr_detection_bit = -1, \ 77*0f936752SRohit Agarwal .intr_detection_width = -1, \ 78*0f936752SRohit Agarwal } 79*0f936752SRohit Agarwal 80*0f936752SRohit Agarwal static const struct pinctrl_pin_desc sdx75_pins[] = { 81*0f936752SRohit Agarwal PINCTRL_PIN(0, "GPIO_0"), 82*0f936752SRohit Agarwal PINCTRL_PIN(1, "GPIO_1"), 83*0f936752SRohit Agarwal PINCTRL_PIN(2, "GPIO_2"), 84*0f936752SRohit Agarwal PINCTRL_PIN(3, "GPIO_3"), 85*0f936752SRohit Agarwal PINCTRL_PIN(4, "GPIO_4"), 86*0f936752SRohit Agarwal PINCTRL_PIN(5, "GPIO_5"), 87*0f936752SRohit Agarwal PINCTRL_PIN(6, "GPIO_6"), 88*0f936752SRohit Agarwal PINCTRL_PIN(7, "GPIO_7"), 89*0f936752SRohit Agarwal PINCTRL_PIN(8, "GPIO_8"), 90*0f936752SRohit Agarwal PINCTRL_PIN(9, "GPIO_9"), 91*0f936752SRohit Agarwal PINCTRL_PIN(10, "GPIO_10"), 92*0f936752SRohit Agarwal PINCTRL_PIN(11, "GPIO_11"), 93*0f936752SRohit Agarwal PINCTRL_PIN(12, "GPIO_12"), 94*0f936752SRohit Agarwal PINCTRL_PIN(13, "GPIO_13"), 95*0f936752SRohit Agarwal PINCTRL_PIN(14, "GPIO_14"), 96*0f936752SRohit Agarwal PINCTRL_PIN(15, "GPIO_15"), 97*0f936752SRohit Agarwal PINCTRL_PIN(16, "GPIO_16"), 98*0f936752SRohit Agarwal PINCTRL_PIN(17, "GPIO_17"), 99*0f936752SRohit Agarwal PINCTRL_PIN(18, "GPIO_18"), 100*0f936752SRohit Agarwal PINCTRL_PIN(19, "GPIO_19"), 101*0f936752SRohit Agarwal PINCTRL_PIN(20, "GPIO_20"), 102*0f936752SRohit Agarwal PINCTRL_PIN(21, "GPIO_21"), 103*0f936752SRohit Agarwal PINCTRL_PIN(22, "GPIO_22"), 104*0f936752SRohit Agarwal PINCTRL_PIN(23, "GPIO_23"), 105*0f936752SRohit Agarwal PINCTRL_PIN(24, "GPIO_24"), 106*0f936752SRohit Agarwal PINCTRL_PIN(25, "GPIO_25"), 107*0f936752SRohit Agarwal PINCTRL_PIN(26, "GPIO_26"), 108*0f936752SRohit Agarwal PINCTRL_PIN(27, "GPIO_27"), 109*0f936752SRohit Agarwal PINCTRL_PIN(28, "GPIO_28"), 110*0f936752SRohit Agarwal PINCTRL_PIN(29, "GPIO_29"), 111*0f936752SRohit Agarwal PINCTRL_PIN(30, "GPIO_30"), 112*0f936752SRohit Agarwal PINCTRL_PIN(31, "GPIO_31"), 113*0f936752SRohit Agarwal PINCTRL_PIN(32, "GPIO_32"), 114*0f936752SRohit Agarwal PINCTRL_PIN(33, "GPIO_33"), 115*0f936752SRohit Agarwal PINCTRL_PIN(34, "GPIO_34"), 116*0f936752SRohit Agarwal PINCTRL_PIN(35, "GPIO_35"), 117*0f936752SRohit Agarwal PINCTRL_PIN(36, "GPIO_36"), 118*0f936752SRohit Agarwal PINCTRL_PIN(37, "GPIO_37"), 119*0f936752SRohit Agarwal PINCTRL_PIN(38, "GPIO_38"), 120*0f936752SRohit Agarwal PINCTRL_PIN(39, "GPIO_39"), 121*0f936752SRohit Agarwal PINCTRL_PIN(40, "GPIO_40"), 122*0f936752SRohit Agarwal PINCTRL_PIN(41, "GPIO_41"), 123*0f936752SRohit Agarwal PINCTRL_PIN(42, "GPIO_42"), 124*0f936752SRohit Agarwal PINCTRL_PIN(43, "GPIO_43"), 125*0f936752SRohit Agarwal PINCTRL_PIN(44, "GPIO_44"), 126*0f936752SRohit Agarwal PINCTRL_PIN(45, "GPIO_45"), 127*0f936752SRohit Agarwal PINCTRL_PIN(46, "GPIO_46"), 128*0f936752SRohit Agarwal PINCTRL_PIN(47, "GPIO_47"), 129*0f936752SRohit Agarwal PINCTRL_PIN(48, "GPIO_48"), 130*0f936752SRohit Agarwal PINCTRL_PIN(49, "GPIO_49"), 131*0f936752SRohit Agarwal PINCTRL_PIN(50, "GPIO_50"), 132*0f936752SRohit Agarwal PINCTRL_PIN(51, "GPIO_51"), 133*0f936752SRohit Agarwal PINCTRL_PIN(52, "GPIO_52"), 134*0f936752SRohit Agarwal PINCTRL_PIN(53, "GPIO_53"), 135*0f936752SRohit Agarwal PINCTRL_PIN(54, "GPIO_54"), 136*0f936752SRohit Agarwal PINCTRL_PIN(55, "GPIO_55"), 137*0f936752SRohit Agarwal PINCTRL_PIN(56, "GPIO_56"), 138*0f936752SRohit Agarwal PINCTRL_PIN(57, "GPIO_57"), 139*0f936752SRohit Agarwal PINCTRL_PIN(58, "GPIO_58"), 140*0f936752SRohit Agarwal PINCTRL_PIN(59, "GPIO_59"), 141*0f936752SRohit Agarwal PINCTRL_PIN(60, "GPIO_60"), 142*0f936752SRohit Agarwal PINCTRL_PIN(61, "GPIO_61"), 143*0f936752SRohit Agarwal PINCTRL_PIN(62, "GPIO_62"), 144*0f936752SRohit Agarwal PINCTRL_PIN(63, "GPIO_63"), 145*0f936752SRohit Agarwal PINCTRL_PIN(64, "GPIO_64"), 146*0f936752SRohit Agarwal PINCTRL_PIN(65, "GPIO_65"), 147*0f936752SRohit Agarwal PINCTRL_PIN(66, "GPIO_66"), 148*0f936752SRohit Agarwal PINCTRL_PIN(67, "GPIO_67"), 149*0f936752SRohit Agarwal PINCTRL_PIN(68, "GPIO_68"), 150*0f936752SRohit Agarwal PINCTRL_PIN(69, "GPIO_69"), 151*0f936752SRohit Agarwal PINCTRL_PIN(70, "GPIO_70"), 152*0f936752SRohit Agarwal PINCTRL_PIN(71, "GPIO_71"), 153*0f936752SRohit Agarwal PINCTRL_PIN(72, "GPIO_72"), 154*0f936752SRohit Agarwal PINCTRL_PIN(73, "GPIO_73"), 155*0f936752SRohit Agarwal PINCTRL_PIN(74, "GPIO_74"), 156*0f936752SRohit Agarwal PINCTRL_PIN(75, "GPIO_75"), 157*0f936752SRohit Agarwal PINCTRL_PIN(76, "GPIO_76"), 158*0f936752SRohit Agarwal PINCTRL_PIN(77, "GPIO_77"), 159*0f936752SRohit Agarwal PINCTRL_PIN(78, "GPIO_78"), 160*0f936752SRohit Agarwal PINCTRL_PIN(79, "GPIO_79"), 161*0f936752SRohit Agarwal PINCTRL_PIN(80, "GPIO_80"), 162*0f936752SRohit Agarwal PINCTRL_PIN(81, "GPIO_81"), 163*0f936752SRohit Agarwal PINCTRL_PIN(82, "GPIO_82"), 164*0f936752SRohit Agarwal PINCTRL_PIN(83, "GPIO_83"), 165*0f936752SRohit Agarwal PINCTRL_PIN(84, "GPIO_84"), 166*0f936752SRohit Agarwal PINCTRL_PIN(85, "GPIO_85"), 167*0f936752SRohit Agarwal PINCTRL_PIN(86, "GPIO_86"), 168*0f936752SRohit Agarwal PINCTRL_PIN(87, "GPIO_87"), 169*0f936752SRohit Agarwal PINCTRL_PIN(88, "GPIO_88"), 170*0f936752SRohit Agarwal PINCTRL_PIN(89, "GPIO_89"), 171*0f936752SRohit Agarwal PINCTRL_PIN(90, "GPIO_90"), 172*0f936752SRohit Agarwal PINCTRL_PIN(91, "GPIO_91"), 173*0f936752SRohit Agarwal PINCTRL_PIN(92, "GPIO_92"), 174*0f936752SRohit Agarwal PINCTRL_PIN(93, "GPIO_93"), 175*0f936752SRohit Agarwal PINCTRL_PIN(94, "GPIO_94"), 176*0f936752SRohit Agarwal PINCTRL_PIN(95, "GPIO_95"), 177*0f936752SRohit Agarwal PINCTRL_PIN(96, "GPIO_96"), 178*0f936752SRohit Agarwal PINCTRL_PIN(97, "GPIO_97"), 179*0f936752SRohit Agarwal PINCTRL_PIN(98, "GPIO_98"), 180*0f936752SRohit Agarwal PINCTRL_PIN(99, "GPIO_99"), 181*0f936752SRohit Agarwal PINCTRL_PIN(100, "GPIO_100"), 182*0f936752SRohit Agarwal PINCTRL_PIN(101, "GPIO_101"), 183*0f936752SRohit Agarwal PINCTRL_PIN(102, "GPIO_102"), 184*0f936752SRohit Agarwal PINCTRL_PIN(103, "GPIO_103"), 185*0f936752SRohit Agarwal PINCTRL_PIN(104, "GPIO_104"), 186*0f936752SRohit Agarwal PINCTRL_PIN(105, "GPIO_105"), 187*0f936752SRohit Agarwal PINCTRL_PIN(106, "GPIO_106"), 188*0f936752SRohit Agarwal PINCTRL_PIN(107, "GPIO_107"), 189*0f936752SRohit Agarwal PINCTRL_PIN(108, "GPIO_108"), 190*0f936752SRohit Agarwal PINCTRL_PIN(109, "GPIO_109"), 191*0f936752SRohit Agarwal PINCTRL_PIN(110, "GPIO_110"), 192*0f936752SRohit Agarwal PINCTRL_PIN(111, "GPIO_111"), 193*0f936752SRohit Agarwal PINCTRL_PIN(112, "GPIO_112"), 194*0f936752SRohit Agarwal PINCTRL_PIN(113, "GPIO_113"), 195*0f936752SRohit Agarwal PINCTRL_PIN(114, "GPIO_114"), 196*0f936752SRohit Agarwal PINCTRL_PIN(115, "GPIO_115"), 197*0f936752SRohit Agarwal PINCTRL_PIN(116, "GPIO_116"), 198*0f936752SRohit Agarwal PINCTRL_PIN(117, "GPIO_117"), 199*0f936752SRohit Agarwal PINCTRL_PIN(118, "GPIO_118"), 200*0f936752SRohit Agarwal PINCTRL_PIN(119, "GPIO_119"), 201*0f936752SRohit Agarwal PINCTRL_PIN(120, "GPIO_120"), 202*0f936752SRohit Agarwal PINCTRL_PIN(121, "GPIO_121"), 203*0f936752SRohit Agarwal PINCTRL_PIN(122, "GPIO_122"), 204*0f936752SRohit Agarwal PINCTRL_PIN(123, "GPIO_123"), 205*0f936752SRohit Agarwal PINCTRL_PIN(124, "GPIO_124"), 206*0f936752SRohit Agarwal PINCTRL_PIN(125, "GPIO_125"), 207*0f936752SRohit Agarwal PINCTRL_PIN(126, "GPIO_126"), 208*0f936752SRohit Agarwal PINCTRL_PIN(127, "GPIO_127"), 209*0f936752SRohit Agarwal PINCTRL_PIN(128, "GPIO_128"), 210*0f936752SRohit Agarwal PINCTRL_PIN(129, "GPIO_129"), 211*0f936752SRohit Agarwal PINCTRL_PIN(130, "GPIO_130"), 212*0f936752SRohit Agarwal PINCTRL_PIN(131, "GPIO_131"), 213*0f936752SRohit Agarwal PINCTRL_PIN(132, "GPIO_132"), 214*0f936752SRohit Agarwal PINCTRL_PIN(133, "SDC1_RCLK"), 215*0f936752SRohit Agarwal PINCTRL_PIN(134, "SDC1_CLK"), 216*0f936752SRohit Agarwal PINCTRL_PIN(135, "SDC1_CMD"), 217*0f936752SRohit Agarwal PINCTRL_PIN(136, "SDC1_DATA"), 218*0f936752SRohit Agarwal PINCTRL_PIN(137, "SDC2_CLK"), 219*0f936752SRohit Agarwal PINCTRL_PIN(138, "SDC2_CMD"), 220*0f936752SRohit Agarwal PINCTRL_PIN(139, "SDC2_DATA"), 221*0f936752SRohit Agarwal }; 222*0f936752SRohit Agarwal 223*0f936752SRohit Agarwal #define DECLARE_MSM_GPIO_PINS(pin) \ 224*0f936752SRohit Agarwal static const unsigned int gpio##pin##_pins[] = {pin} 225*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(0); 226*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(1); 227*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(2); 228*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(3); 229*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(4); 230*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(5); 231*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(6); 232*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(7); 233*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(8); 234*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(9); 235*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(10); 236*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(11); 237*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(12); 238*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(13); 239*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(14); 240*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(15); 241*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(16); 242*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(17); 243*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(18); 244*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(19); 245*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(20); 246*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(21); 247*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(22); 248*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(23); 249*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(24); 250*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(25); 251*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(26); 252*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(27); 253*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(28); 254*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(29); 255*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(30); 256*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(31); 257*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(32); 258*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(33); 259*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(34); 260*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(35); 261*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(36); 262*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(37); 263*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(38); 264*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(39); 265*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(40); 266*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(41); 267*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(42); 268*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(43); 269*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(44); 270*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(45); 271*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(46); 272*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(47); 273*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(48); 274*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(49); 275*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(50); 276*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(51); 277*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(52); 278*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(53); 279*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(54); 280*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(55); 281*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(56); 282*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(57); 283*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(58); 284*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(59); 285*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(60); 286*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(61); 287*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(62); 288*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(63); 289*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(64); 290*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(65); 291*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(66); 292*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(67); 293*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(68); 294*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(69); 295*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(70); 296*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(71); 297*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(72); 298*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(73); 299*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(74); 300*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(75); 301*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(76); 302*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(77); 303*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(78); 304*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(79); 305*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(80); 306*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(81); 307*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(82); 308*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(83); 309*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(84); 310*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(85); 311*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(86); 312*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(87); 313*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(88); 314*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(89); 315*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(90); 316*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(91); 317*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(92); 318*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(93); 319*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(94); 320*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(95); 321*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(96); 322*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(97); 323*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(98); 324*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(99); 325*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(100); 326*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(101); 327*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(102); 328*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(103); 329*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(104); 330*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(105); 331*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(106); 332*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(107); 333*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(108); 334*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(109); 335*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(110); 336*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(111); 337*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(112); 338*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(113); 339*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(114); 340*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(115); 341*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(116); 342*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(117); 343*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(118); 344*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(119); 345*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(120); 346*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(121); 347*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(122); 348*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(123); 349*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(124); 350*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(125); 351*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(126); 352*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(127); 353*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(128); 354*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(129); 355*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(130); 356*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(131); 357*0f936752SRohit Agarwal DECLARE_MSM_GPIO_PINS(132); 358*0f936752SRohit Agarwal 359*0f936752SRohit Agarwal static const unsigned int sdc1_rclk_pins[] = {133}; 360*0f936752SRohit Agarwal static const unsigned int sdc1_clk_pins[] = {134}; 361*0f936752SRohit Agarwal static const unsigned int sdc1_cmd_pins[] = {135}; 362*0f936752SRohit Agarwal static const unsigned int sdc1_data_pins[] = {136}; 363*0f936752SRohit Agarwal static const unsigned int sdc2_clk_pins[] = {137}; 364*0f936752SRohit Agarwal static const unsigned int sdc2_cmd_pins[] = {138}; 365*0f936752SRohit Agarwal static const unsigned int sdc2_data_pins[] = {139}; 366*0f936752SRohit Agarwal 367*0f936752SRohit Agarwal enum sdx75_functions { 368*0f936752SRohit Agarwal msm_mux_adsp_ext, 369*0f936752SRohit Agarwal msm_mux_atest_char, 370*0f936752SRohit Agarwal msm_mux_audio_ref_clk, 371*0f936752SRohit Agarwal msm_mux_bimc_dte, 372*0f936752SRohit Agarwal msm_mux_char_exec, 373*0f936752SRohit Agarwal msm_mux_coex_uart2, 374*0f936752SRohit Agarwal msm_mux_coex_uart, 375*0f936752SRohit Agarwal msm_mux_cri_trng, 376*0f936752SRohit Agarwal msm_mux_cri_trng0, 377*0f936752SRohit Agarwal msm_mux_cri_trng1, 378*0f936752SRohit Agarwal msm_mux_dbg_out_clk, 379*0f936752SRohit Agarwal msm_mux_ddr_bist, 380*0f936752SRohit Agarwal msm_mux_ddr_pxi0, 381*0f936752SRohit Agarwal msm_mux_ebi0_wrcdc, 382*0f936752SRohit Agarwal msm_mux_ebi2_a, 383*0f936752SRohit Agarwal msm_mux_ebi2_lcd, 384*0f936752SRohit Agarwal msm_mux_ebi2_lcd_te, 385*0f936752SRohit Agarwal msm_mux_emac0_mcg, 386*0f936752SRohit Agarwal msm_mux_emac0_ptp, 387*0f936752SRohit Agarwal msm_mux_emac1_mcg, 388*0f936752SRohit Agarwal msm_mux_emac1_ptp, 389*0f936752SRohit Agarwal msm_mux_emac_cdc, 390*0f936752SRohit Agarwal msm_mux_emac_pps_in, 391*0f936752SRohit Agarwal msm_mux_eth0_mdc, 392*0f936752SRohit Agarwal msm_mux_eth0_mdio, 393*0f936752SRohit Agarwal msm_mux_eth1_mdc, 394*0f936752SRohit Agarwal msm_mux_eth1_mdio, 395*0f936752SRohit Agarwal msm_mux_ext_dbg, 396*0f936752SRohit Agarwal msm_mux_gcc_125_clk, 397*0f936752SRohit Agarwal msm_mux_gcc_gp1_clk, 398*0f936752SRohit Agarwal msm_mux_gcc_gp2_clk, 399*0f936752SRohit Agarwal msm_mux_gcc_gp3_clk, 400*0f936752SRohit Agarwal msm_mux_gcc_plltest, 401*0f936752SRohit Agarwal msm_mux_gpio, 402*0f936752SRohit Agarwal msm_mux_i2s_mclk, 403*0f936752SRohit Agarwal msm_mux_jitter_bist, 404*0f936752SRohit Agarwal msm_mux_ldo_en, 405*0f936752SRohit Agarwal msm_mux_ldo_update, 406*0f936752SRohit Agarwal msm_mux_m_voc, 407*0f936752SRohit Agarwal msm_mux_mgpi_clk, 408*0f936752SRohit Agarwal msm_mux_native_char, 409*0f936752SRohit Agarwal msm_mux_native_tsens, 410*0f936752SRohit Agarwal msm_mux_native_tsense, 411*0f936752SRohit Agarwal msm_mux_nav_dr_sync, 412*0f936752SRohit Agarwal msm_mux_nav_gpio, 413*0f936752SRohit Agarwal msm_mux_pa_indicator, 414*0f936752SRohit Agarwal msm_mux_pci_e, 415*0f936752SRohit Agarwal msm_mux_pcie0_clkreq_n, 416*0f936752SRohit Agarwal msm_mux_pcie1_clkreq_n, 417*0f936752SRohit Agarwal msm_mux_pcie2_clkreq_n, 418*0f936752SRohit Agarwal msm_mux_pll_bist_sync, 419*0f936752SRohit Agarwal msm_mux_pll_clk_aux, 420*0f936752SRohit Agarwal msm_mux_pll_ref_clk, 421*0f936752SRohit Agarwal msm_mux_pri_mi2s, 422*0f936752SRohit Agarwal msm_mux_prng_rosc, 423*0f936752SRohit Agarwal msm_mux_qdss_cti, 424*0f936752SRohit Agarwal msm_mux_qdss_gpio, 425*0f936752SRohit Agarwal msm_mux_qlink0_b_en, 426*0f936752SRohit Agarwal msm_mux_qlink0_b_req, 427*0f936752SRohit Agarwal msm_mux_qlink0_l_en, 428*0f936752SRohit Agarwal msm_mux_qlink0_l_req, 429*0f936752SRohit Agarwal msm_mux_qlink0_wmss, 430*0f936752SRohit Agarwal msm_mux_qlink1_l_en, 431*0f936752SRohit Agarwal msm_mux_qlink1_l_req, 432*0f936752SRohit Agarwal msm_mux_qlink1_wmss, 433*0f936752SRohit Agarwal msm_mux_qup_se0, 434*0f936752SRohit Agarwal msm_mux_qup_se1_l2_mira, 435*0f936752SRohit Agarwal msm_mux_qup_se1_l2_mirb, 436*0f936752SRohit Agarwal msm_mux_qup_se1_l3_mira, 437*0f936752SRohit Agarwal msm_mux_qup_se1_l3_mirb, 438*0f936752SRohit Agarwal msm_mux_qup_se2, 439*0f936752SRohit Agarwal msm_mux_qup_se3, 440*0f936752SRohit Agarwal msm_mux_qup_se4, 441*0f936752SRohit Agarwal msm_mux_qup_se5, 442*0f936752SRohit Agarwal msm_mux_qup_se6, 443*0f936752SRohit Agarwal msm_mux_qup_se7, 444*0f936752SRohit Agarwal msm_mux_qup_se8, 445*0f936752SRohit Agarwal msm_mux_rgmii_rx_ctl, 446*0f936752SRohit Agarwal msm_mux_rgmii_rxc, 447*0f936752SRohit Agarwal msm_mux_rgmii_rxd, 448*0f936752SRohit Agarwal msm_mux_rgmii_tx_ctl, 449*0f936752SRohit Agarwal msm_mux_rgmii_txc, 450*0f936752SRohit Agarwal msm_mux_rgmii_txd, 451*0f936752SRohit Agarwal msm_mux_sd_card, 452*0f936752SRohit Agarwal msm_mux_sdc1_tb, 453*0f936752SRohit Agarwal msm_mux_sdc2_tb_trig, 454*0f936752SRohit Agarwal msm_mux_sec_mi2s, 455*0f936752SRohit Agarwal msm_mux_sgmii_phy_intr0_n, 456*0f936752SRohit Agarwal msm_mux_sgmii_phy_intr1_n, 457*0f936752SRohit Agarwal msm_mux_spmi_coex, 458*0f936752SRohit Agarwal msm_mux_spmi_vgi, 459*0f936752SRohit Agarwal msm_mux_tgu_ch0_trigout, 460*0f936752SRohit Agarwal msm_mux_tmess_prng0, 461*0f936752SRohit Agarwal msm_mux_tmess_prng1, 462*0f936752SRohit Agarwal msm_mux_tmess_prng2, 463*0f936752SRohit Agarwal msm_mux_tmess_prng3, 464*0f936752SRohit Agarwal msm_mux_tri_mi2s, 465*0f936752SRohit Agarwal msm_mux_uim1_clk, 466*0f936752SRohit Agarwal msm_mux_uim1_data, 467*0f936752SRohit Agarwal msm_mux_uim1_present, 468*0f936752SRohit Agarwal msm_mux_uim1_reset, 469*0f936752SRohit Agarwal msm_mux_uim2_clk, 470*0f936752SRohit Agarwal msm_mux_uim2_data, 471*0f936752SRohit Agarwal msm_mux_uim2_present, 472*0f936752SRohit Agarwal msm_mux_uim2_reset, 473*0f936752SRohit Agarwal msm_mux_usb2phy_ac_en, 474*0f936752SRohit Agarwal msm_mux_vsense_trigger_mirnat, 475*0f936752SRohit Agarwal msm_mux__, 476*0f936752SRohit Agarwal }; 477*0f936752SRohit Agarwal 478*0f936752SRohit Agarwal static const char *const gpio_groups[] = { 479*0f936752SRohit Agarwal "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", 480*0f936752SRohit Agarwal "gpio7", "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", 481*0f936752SRohit Agarwal "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", 482*0f936752SRohit Agarwal "gpio21", "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", 483*0f936752SRohit Agarwal "gpio28", "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", 484*0f936752SRohit Agarwal "gpio35", "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", 485*0f936752SRohit Agarwal "gpio42", "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", 486*0f936752SRohit Agarwal "gpio49", "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", 487*0f936752SRohit Agarwal "gpio56", "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", 488*0f936752SRohit Agarwal "gpio63", "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", 489*0f936752SRohit Agarwal "gpio70", "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", 490*0f936752SRohit Agarwal "gpio77", "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", 491*0f936752SRohit Agarwal "gpio84", "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", 492*0f936752SRohit Agarwal "gpio91", "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", 493*0f936752SRohit Agarwal "gpio98", "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", 494*0f936752SRohit Agarwal "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", "gpio111", 495*0f936752SRohit Agarwal "gpio112", "gpio113", "gpio114", "gpio115", "gpio116", "gpio117", "gpio118", 496*0f936752SRohit Agarwal "gpio119", "gpio120", "gpio121", "gpio122", "gpio123", "gpio124", "gpio125", 497*0f936752SRohit Agarwal "gpio126", "gpio127", "gpio128", "gpio129", "gpio130", "gpio131", "gpio132", 498*0f936752SRohit Agarwal }; 499*0f936752SRohit Agarwal static const char *const adsp_ext_groups[] = { 500*0f936752SRohit Agarwal "gpio59", "gpio68", 501*0f936752SRohit Agarwal }; 502*0f936752SRohit Agarwal static const char *const atest_char_groups[] = { 503*0f936752SRohit Agarwal "gpio24", "gpio25", "gpio26", "gpio41", "gpio63", 504*0f936752SRohit Agarwal }; 505*0f936752SRohit Agarwal static const char *const audio_ref_clk_groups[] = { 506*0f936752SRohit Agarwal "gpio126", 507*0f936752SRohit Agarwal }; 508*0f936752SRohit Agarwal static const char *const bimc_dte_groups[] = { 509*0f936752SRohit Agarwal "gpio14", "gpio15", "gpio61", "gpio59", 510*0f936752SRohit Agarwal }; 511*0f936752SRohit Agarwal static const char *const char_exec_groups[] = { 512*0f936752SRohit Agarwal "gpio6", "gpio7", 513*0f936752SRohit Agarwal }; 514*0f936752SRohit Agarwal static const char *const coex_uart2_groups[] = { 515*0f936752SRohit Agarwal "gpio48", "gpio49", "gpio90", "gpio91", 516*0f936752SRohit Agarwal }; 517*0f936752SRohit Agarwal static const char *const coex_uart_groups[] = { 518*0f936752SRohit Agarwal "gpio46", "gpio47", 519*0f936752SRohit Agarwal }; 520*0f936752SRohit Agarwal static const char *const cri_trng_groups[] = { 521*0f936752SRohit Agarwal "gpio36", 522*0f936752SRohit Agarwal }; 523*0f936752SRohit Agarwal static const char *const cri_trng0_groups[] = { 524*0f936752SRohit Agarwal "gpio31", 525*0f936752SRohit Agarwal }; 526*0f936752SRohit Agarwal static const char *const cri_trng1_groups[] = { 527*0f936752SRohit Agarwal "gpio32", 528*0f936752SRohit Agarwal }; 529*0f936752SRohit Agarwal static const char *const dbg_out_clk_groups[] = { 530*0f936752SRohit Agarwal "gpio26", 531*0f936752SRohit Agarwal }; 532*0f936752SRohit Agarwal static const char *const ddr_bist_groups[] = { 533*0f936752SRohit Agarwal "gpio46", "gpio47", "gpio48", "gpio49", 534*0f936752SRohit Agarwal }; 535*0f936752SRohit Agarwal static const char *const ddr_pxi0_groups[] = { 536*0f936752SRohit Agarwal "gpio45", "gpio46", 537*0f936752SRohit Agarwal }; 538*0f936752SRohit Agarwal static const char *const ebi0_wrcdc_groups[] = { 539*0f936752SRohit Agarwal "gpio0", "gpio2", 540*0f936752SRohit Agarwal }; 541*0f936752SRohit Agarwal static const char *const ebi2_a_groups[] = { 542*0f936752SRohit Agarwal "gpio100", 543*0f936752SRohit Agarwal }; 544*0f936752SRohit Agarwal static const char *const ebi2_lcd_groups[] = { 545*0f936752SRohit Agarwal "gpio99", "gpio101", 546*0f936752SRohit Agarwal }; 547*0f936752SRohit Agarwal static const char *const ebi2_lcd_te_groups[] = { 548*0f936752SRohit Agarwal "gpio98", 549*0f936752SRohit Agarwal }; 550*0f936752SRohit Agarwal static const char *const emac0_mcg_groups[] = { 551*0f936752SRohit Agarwal "gpio83", "gpio84", "gpio85", "gpio89", 552*0f936752SRohit Agarwal }; 553*0f936752SRohit Agarwal static const char *const emac0_ptp_groups[] = { 554*0f936752SRohit Agarwal "gpio35", "gpio83", "gpio84", "gpio85", "gpio89", "gpio119", "gpio123", 555*0f936752SRohit Agarwal }; 556*0f936752SRohit Agarwal static const char *const emac1_mcg_groups[] = { 557*0f936752SRohit Agarwal "gpio90", "gpio92", "gpio93", "gpio122", 558*0f936752SRohit Agarwal }; 559*0f936752SRohit Agarwal static const char *const emac1_ptp_groups[] = { 560*0f936752SRohit Agarwal "gpio112", "gpio113", "gpio114", "gpio115", 561*0f936752SRohit Agarwal }; 562*0f936752SRohit Agarwal static const char *const emac_cdc_groups[] = { 563*0f936752SRohit Agarwal "gpio38", "gpio39", 564*0f936752SRohit Agarwal }; 565*0f936752SRohit Agarwal static const char *const emac_pps_in_groups[] = { 566*0f936752SRohit Agarwal "gpio127", 567*0f936752SRohit Agarwal }; 568*0f936752SRohit Agarwal static const char *const eth0_mdc_groups[] = { 569*0f936752SRohit Agarwal "gpio94", 570*0f936752SRohit Agarwal }; 571*0f936752SRohit Agarwal static const char *const eth0_mdio_groups[] = { 572*0f936752SRohit Agarwal "gpio95", 573*0f936752SRohit Agarwal }; 574*0f936752SRohit Agarwal static const char *const eth1_mdc_groups[] = { 575*0f936752SRohit Agarwal "gpio106", 576*0f936752SRohit Agarwal }; 577*0f936752SRohit Agarwal static const char *const eth1_mdio_groups[] = { 578*0f936752SRohit Agarwal "gpio107", 579*0f936752SRohit Agarwal }; 580*0f936752SRohit Agarwal static const char *const ext_dbg_groups[] = { 581*0f936752SRohit Agarwal "gpio12", "gpio13", "gpio14", "gpio15", 582*0f936752SRohit Agarwal }; 583*0f936752SRohit Agarwal static const char *const gcc_125_clk_groups[] = { 584*0f936752SRohit Agarwal "gpio25", 585*0f936752SRohit Agarwal }; 586*0f936752SRohit Agarwal static const char *const gcc_gp1_clk_groups[] = { 587*0f936752SRohit Agarwal "gpio39", 588*0f936752SRohit Agarwal }; 589*0f936752SRohit Agarwal static const char *const gcc_gp2_clk_groups[] = { 590*0f936752SRohit Agarwal "gpio40", 591*0f936752SRohit Agarwal }; 592*0f936752SRohit Agarwal static const char *const gcc_gp3_clk_groups[] = { 593*0f936752SRohit Agarwal "gpio41", 594*0f936752SRohit Agarwal }; 595*0f936752SRohit Agarwal static const char *const gcc_plltest_groups[] = { 596*0f936752SRohit Agarwal "gpio81", "gpio82", 597*0f936752SRohit Agarwal }; 598*0f936752SRohit Agarwal static const char *const i2s_mclk_groups[] = { 599*0f936752SRohit Agarwal "gpio74", 600*0f936752SRohit Agarwal }; 601*0f936752SRohit Agarwal static const char *const jitter_bist_groups[] = { 602*0f936752SRohit Agarwal "gpio41", 603*0f936752SRohit Agarwal }; 604*0f936752SRohit Agarwal static const char *const ldo_en_groups[] = { 605*0f936752SRohit Agarwal "gpio8", 606*0f936752SRohit Agarwal }; 607*0f936752SRohit Agarwal static const char *const ldo_update_groups[] = { 608*0f936752SRohit Agarwal "gpio62", 609*0f936752SRohit Agarwal }; 610*0f936752SRohit Agarwal static const char *const m_voc_groups[] = { 611*0f936752SRohit Agarwal "gpio62", "gpio63", "gpio64", "gpio65", "gpio71", 612*0f936752SRohit Agarwal }; 613*0f936752SRohit Agarwal static const char *const mgpi_clk_groups[] = { 614*0f936752SRohit Agarwal "gpio39", "gpio40", 615*0f936752SRohit Agarwal }; 616*0f936752SRohit Agarwal static const char *const native_char_groups[] = { 617*0f936752SRohit Agarwal "gpio29", "gpio33", "gpio57", "gpio66", "gpio67", 618*0f936752SRohit Agarwal }; 619*0f936752SRohit Agarwal static const char *const native_tsens_groups[] = { 620*0f936752SRohit Agarwal "gpio38", 621*0f936752SRohit Agarwal }; 622*0f936752SRohit Agarwal static const char *const native_tsense_groups[] = { 623*0f936752SRohit Agarwal "gpio64", "gpio76", 624*0f936752SRohit Agarwal }; 625*0f936752SRohit Agarwal static const char *const nav_dr_sync_groups[] = { 626*0f936752SRohit Agarwal "gpio36", 627*0f936752SRohit Agarwal }; 628*0f936752SRohit Agarwal static const char *const nav_gpio_groups[] = { 629*0f936752SRohit Agarwal "gpio35", "gpio36", "gpio104", 630*0f936752SRohit Agarwal }; 631*0f936752SRohit Agarwal static const char *const pa_indicator_groups[] = { 632*0f936752SRohit Agarwal "gpio58", 633*0f936752SRohit Agarwal }; 634*0f936752SRohit Agarwal static const char *const pci_e_groups[] = { 635*0f936752SRohit Agarwal "gpio42", 636*0f936752SRohit Agarwal }; 637*0f936752SRohit Agarwal static const char *const pcie0_clkreq_n_groups[] = { 638*0f936752SRohit Agarwal "gpio43", 639*0f936752SRohit Agarwal }; 640*0f936752SRohit Agarwal static const char *const pcie1_clkreq_n_groups[] = { 641*0f936752SRohit Agarwal "gpio124", 642*0f936752SRohit Agarwal }; 643*0f936752SRohit Agarwal static const char *const pcie2_clkreq_n_groups[] = { 644*0f936752SRohit Agarwal "gpio121", 645*0f936752SRohit Agarwal }; 646*0f936752SRohit Agarwal static const char *const pll_bist_sync_groups[] = { 647*0f936752SRohit Agarwal "gpio38", 648*0f936752SRohit Agarwal }; 649*0f936752SRohit Agarwal static const char *const pll_clk_aux_groups[] = { 650*0f936752SRohit Agarwal "gpio40", 651*0f936752SRohit Agarwal }; 652*0f936752SRohit Agarwal static const char *const pll_ref_clk_groups[] = { 653*0f936752SRohit Agarwal "gpio37", 654*0f936752SRohit Agarwal }; 655*0f936752SRohit Agarwal static const char *const pri_mi2s_groups[] = { 656*0f936752SRohit Agarwal "gpio16", "gpio17", "gpio18", "gpio19", 657*0f936752SRohit Agarwal }; 658*0f936752SRohit Agarwal static const char *const prng_rosc_groups[] = { 659*0f936752SRohit Agarwal "gpio27", "gpio36", "gpio37", "gpio38", 660*0f936752SRohit Agarwal }; 661*0f936752SRohit Agarwal static const char *const qdss_cti_groups[] = { 662*0f936752SRohit Agarwal "gpio16", "gpio17", "gpio52", "gpio53", "gpio56", 663*0f936752SRohit Agarwal "gpio57", "gpio59", "gpio60", "gpio78", "gpio79", 664*0f936752SRohit Agarwal }; 665*0f936752SRohit Agarwal static const char *const qdss_gpio_groups[] = { 666*0f936752SRohit Agarwal "gpio82", "gpio83", "gpio84", "gpio85", "gpio94", 667*0f936752SRohit Agarwal "gpio95", "gpio96", "gpio97", "gpio110", "gpio111", 668*0f936752SRohit Agarwal "gpio112", "gpio113", "gpio114", "gpio115", "gpio116", 669*0f936752SRohit Agarwal "gpio117", "gpio118", "gpio119", 670*0f936752SRohit Agarwal }; 671*0f936752SRohit Agarwal static const char *const qlink0_b_en_groups[] = { 672*0f936752SRohit Agarwal "gpio40", 673*0f936752SRohit Agarwal }; 674*0f936752SRohit Agarwal static const char *const qlink0_b_req_groups[] = { 675*0f936752SRohit Agarwal "gpio41", 676*0f936752SRohit Agarwal }; 677*0f936752SRohit Agarwal static const char *const qlink0_l_en_groups[] = { 678*0f936752SRohit Agarwal "gpio37", 679*0f936752SRohit Agarwal }; 680*0f936752SRohit Agarwal static const char *const qlink0_l_req_groups[] = { 681*0f936752SRohit Agarwal "gpio38", 682*0f936752SRohit Agarwal }; 683*0f936752SRohit Agarwal static const char *const qlink0_wmss_groups[] = { 684*0f936752SRohit Agarwal "gpio39", 685*0f936752SRohit Agarwal }; 686*0f936752SRohit Agarwal static const char *const qlink1_l_en_groups[] = { 687*0f936752SRohit Agarwal "gpio26", 688*0f936752SRohit Agarwal }; 689*0f936752SRohit Agarwal static const char *const qlink1_l_req_groups[] = { 690*0f936752SRohit Agarwal "gpio27", 691*0f936752SRohit Agarwal }; 692*0f936752SRohit Agarwal static const char *const qlink1_wmss_groups[] = { 693*0f936752SRohit Agarwal "gpio28", 694*0f936752SRohit Agarwal }; 695*0f936752SRohit Agarwal static const char *const qup_se0_groups[] = { 696*0f936752SRohit Agarwal "gpio8", "gpio9", "gpio10", "gpio11", 697*0f936752SRohit Agarwal }; 698*0f936752SRohit Agarwal static const char *const qup_se1_l2_mira_groups[] = { 699*0f936752SRohit Agarwal "gpio12", 700*0f936752SRohit Agarwal }; 701*0f936752SRohit Agarwal static const char *const qup_se1_l2_mirb_groups[] = { 702*0f936752SRohit Agarwal "gpio16", 703*0f936752SRohit Agarwal }; 704*0f936752SRohit Agarwal static const char *const qup_se1_l3_mira_groups[] = { 705*0f936752SRohit Agarwal "gpio13", 706*0f936752SRohit Agarwal }; 707*0f936752SRohit Agarwal static const char *const qup_se1_l3_mirb_groups[] = { 708*0f936752SRohit Agarwal "gpio17", 709*0f936752SRohit Agarwal }; 710*0f936752SRohit Agarwal static const char *const qup_se2_groups[] = { 711*0f936752SRohit Agarwal "gpio14", "gpio15", "gpio16", "gpio17", 712*0f936752SRohit Agarwal }; 713*0f936752SRohit Agarwal static const char *const qup_se3_groups[] = { 714*0f936752SRohit Agarwal "gpio52", "gpio53", "gpio54", "gpio55", 715*0f936752SRohit Agarwal }; 716*0f936752SRohit Agarwal static const char *const qup_se4_groups[] = { 717*0f936752SRohit Agarwal "gpio64", "gpio65", 718*0f936752SRohit Agarwal }; 719*0f936752SRohit Agarwal static const char *const qup_se5_groups[] = { 720*0f936752SRohit Agarwal "gpio110", "gpio111", 721*0f936752SRohit Agarwal }; 722*0f936752SRohit Agarwal static const char *const qup_se6_groups[] = { 723*0f936752SRohit Agarwal "gpio112", "gpio113", "gpio114", "gpio115", 724*0f936752SRohit Agarwal }; 725*0f936752SRohit Agarwal static const char *const qup_se7_groups[] = { 726*0f936752SRohit Agarwal "gpio116", "gpio117", "gpio118", "gpio119", 727*0f936752SRohit Agarwal }; 728*0f936752SRohit Agarwal static const char *const qup_se8_groups[] = { 729*0f936752SRohit Agarwal "gpio124", "gpio125", 730*0f936752SRohit Agarwal }; 731*0f936752SRohit Agarwal static const char *const rgmii_rx_ctl_groups[] = { 732*0f936752SRohit Agarwal "gpio93", 733*0f936752SRohit Agarwal }; 734*0f936752SRohit Agarwal static const char *const rgmii_rxc_groups[] = { 735*0f936752SRohit Agarwal "gpio88", 736*0f936752SRohit Agarwal }; 737*0f936752SRohit Agarwal static const char *const rgmii_rxd_groups[] = { 738*0f936752SRohit Agarwal "gpio89", "gpio90", "gpio91", "gpio92", 739*0f936752SRohit Agarwal }; 740*0f936752SRohit Agarwal static const char *const rgmii_tx_ctl_groups[] = { 741*0f936752SRohit Agarwal "gpio87", 742*0f936752SRohit Agarwal }; 743*0f936752SRohit Agarwal static const char *const rgmii_txc_groups[] = { 744*0f936752SRohit Agarwal "gpio82", 745*0f936752SRohit Agarwal }; 746*0f936752SRohit Agarwal static const char *const rgmii_txd_groups[] = { 747*0f936752SRohit Agarwal "gpio83", "gpio84", "gpio85", "gpio86", 748*0f936752SRohit Agarwal }; 749*0f936752SRohit Agarwal static const char *const sd_card_groups[] = { 750*0f936752SRohit Agarwal "gpio105", 751*0f936752SRohit Agarwal }; 752*0f936752SRohit Agarwal static const char *const sdc1_tb_groups[] = { 753*0f936752SRohit Agarwal "gpio84", "gpio130", 754*0f936752SRohit Agarwal }; 755*0f936752SRohit Agarwal static const char *const sdc2_tb_trig_groups[] = { 756*0f936752SRohit Agarwal "gpio129", 757*0f936752SRohit Agarwal }; 758*0f936752SRohit Agarwal static const char *const sec_mi2s_groups[] = { 759*0f936752SRohit Agarwal "gpio20", "gpio21", "gpio22", "gpio23", 760*0f936752SRohit Agarwal }; 761*0f936752SRohit Agarwal static const char *const sgmii_phy_intr0_n_groups[] = { 762*0f936752SRohit Agarwal "gpio97", 763*0f936752SRohit Agarwal }; 764*0f936752SRohit Agarwal static const char *const sgmii_phy_intr1_n_groups[] = { 765*0f936752SRohit Agarwal "gpio109", 766*0f936752SRohit Agarwal }; 767*0f936752SRohit Agarwal static const char *const spmi_coex_groups[] = { 768*0f936752SRohit Agarwal "gpio48", "gpio49", 769*0f936752SRohit Agarwal }; 770*0f936752SRohit Agarwal static const char *const spmi_vgi_groups[] = { 771*0f936752SRohit Agarwal "gpio50", "gpio51", 772*0f936752SRohit Agarwal }; 773*0f936752SRohit Agarwal static const char *const tgu_ch0_trigout_groups[] = { 774*0f936752SRohit Agarwal "gpio55", 775*0f936752SRohit Agarwal }; 776*0f936752SRohit Agarwal static const char *const tmess_prng0_groups[] = { 777*0f936752SRohit Agarwal "gpio28", 778*0f936752SRohit Agarwal }; 779*0f936752SRohit Agarwal static const char *const tmess_prng1_groups[] = { 780*0f936752SRohit Agarwal "gpio29", 781*0f936752SRohit Agarwal }; 782*0f936752SRohit Agarwal static const char *const tmess_prng2_groups[] = { 783*0f936752SRohit Agarwal "gpio30", 784*0f936752SRohit Agarwal }; 785*0f936752SRohit Agarwal static const char *const tmess_prng3_groups[] = { 786*0f936752SRohit Agarwal "gpio31", 787*0f936752SRohit Agarwal }; 788*0f936752SRohit Agarwal static const char *const tri_mi2s_groups[] = { 789*0f936752SRohit Agarwal "gpio98", "gpio99", "gpio100", "gpio101", 790*0f936752SRohit Agarwal }; 791*0f936752SRohit Agarwal static const char *const uim1_clk_groups[] = { 792*0f936752SRohit Agarwal "gpio7", 793*0f936752SRohit Agarwal }; 794*0f936752SRohit Agarwal static const char *const uim1_data_groups[] = { 795*0f936752SRohit Agarwal "gpio4", 796*0f936752SRohit Agarwal }; 797*0f936752SRohit Agarwal static const char *const uim1_present_groups[] = { 798*0f936752SRohit Agarwal "gpio5", 799*0f936752SRohit Agarwal }; 800*0f936752SRohit Agarwal static const char *const uim1_reset_groups[] = { 801*0f936752SRohit Agarwal "gpio6", 802*0f936752SRohit Agarwal }; 803*0f936752SRohit Agarwal static const char *const uim2_clk_groups[] = { 804*0f936752SRohit Agarwal "gpio3", 805*0f936752SRohit Agarwal }; 806*0f936752SRohit Agarwal static const char *const uim2_data_groups[] = { 807*0f936752SRohit Agarwal "gpio0", 808*0f936752SRohit Agarwal }; 809*0f936752SRohit Agarwal static const char *const uim2_present_groups[] = { 810*0f936752SRohit Agarwal "gpio1", 811*0f936752SRohit Agarwal }; 812*0f936752SRohit Agarwal static const char *const uim2_reset_groups[] = { 813*0f936752SRohit Agarwal "gpio2", 814*0f936752SRohit Agarwal }; 815*0f936752SRohit Agarwal static const char *const usb2phy_ac_en_groups[] = { 816*0f936752SRohit Agarwal "gpio80", 817*0f936752SRohit Agarwal }; 818*0f936752SRohit Agarwal static const char *const vsense_trigger_mirnat_groups[] = { 819*0f936752SRohit Agarwal "gpio37", 820*0f936752SRohit Agarwal }; 821*0f936752SRohit Agarwal 822*0f936752SRohit Agarwal static const struct pinfunction sdx75_functions[] = { 823*0f936752SRohit Agarwal MSM_PIN_FUNCTION(adsp_ext), 824*0f936752SRohit Agarwal MSM_PIN_FUNCTION(atest_char), 825*0f936752SRohit Agarwal MSM_PIN_FUNCTION(audio_ref_clk), 826*0f936752SRohit Agarwal MSM_PIN_FUNCTION(bimc_dte), 827*0f936752SRohit Agarwal MSM_PIN_FUNCTION(char_exec), 828*0f936752SRohit Agarwal MSM_PIN_FUNCTION(coex_uart2), 829*0f936752SRohit Agarwal MSM_PIN_FUNCTION(coex_uart), 830*0f936752SRohit Agarwal MSM_PIN_FUNCTION(cri_trng), 831*0f936752SRohit Agarwal MSM_PIN_FUNCTION(cri_trng0), 832*0f936752SRohit Agarwal MSM_PIN_FUNCTION(cri_trng1), 833*0f936752SRohit Agarwal MSM_PIN_FUNCTION(dbg_out_clk), 834*0f936752SRohit Agarwal MSM_PIN_FUNCTION(ddr_bist), 835*0f936752SRohit Agarwal MSM_PIN_FUNCTION(ddr_pxi0), 836*0f936752SRohit Agarwal MSM_PIN_FUNCTION(ebi0_wrcdc), 837*0f936752SRohit Agarwal MSM_PIN_FUNCTION(ebi2_a), 838*0f936752SRohit Agarwal MSM_PIN_FUNCTION(ebi2_lcd), 839*0f936752SRohit Agarwal MSM_PIN_FUNCTION(ebi2_lcd_te), 840*0f936752SRohit Agarwal MSM_PIN_FUNCTION(emac0_mcg), 841*0f936752SRohit Agarwal MSM_PIN_FUNCTION(emac0_ptp), 842*0f936752SRohit Agarwal MSM_PIN_FUNCTION(emac1_mcg), 843*0f936752SRohit Agarwal MSM_PIN_FUNCTION(emac1_ptp), 844*0f936752SRohit Agarwal MSM_PIN_FUNCTION(emac_cdc), 845*0f936752SRohit Agarwal MSM_PIN_FUNCTION(emac_pps_in), 846*0f936752SRohit Agarwal MSM_PIN_FUNCTION(eth0_mdc), 847*0f936752SRohit Agarwal MSM_PIN_FUNCTION(eth0_mdio), 848*0f936752SRohit Agarwal MSM_PIN_FUNCTION(eth1_mdc), 849*0f936752SRohit Agarwal MSM_PIN_FUNCTION(eth1_mdio), 850*0f936752SRohit Agarwal MSM_PIN_FUNCTION(ext_dbg), 851*0f936752SRohit Agarwal MSM_PIN_FUNCTION(gcc_125_clk), 852*0f936752SRohit Agarwal MSM_PIN_FUNCTION(gcc_gp1_clk), 853*0f936752SRohit Agarwal MSM_PIN_FUNCTION(gcc_gp2_clk), 854*0f936752SRohit Agarwal MSM_PIN_FUNCTION(gcc_gp3_clk), 855*0f936752SRohit Agarwal MSM_PIN_FUNCTION(gcc_plltest), 856*0f936752SRohit Agarwal MSM_PIN_FUNCTION(gpio), 857*0f936752SRohit Agarwal MSM_PIN_FUNCTION(i2s_mclk), 858*0f936752SRohit Agarwal MSM_PIN_FUNCTION(jitter_bist), 859*0f936752SRohit Agarwal MSM_PIN_FUNCTION(ldo_en), 860*0f936752SRohit Agarwal MSM_PIN_FUNCTION(ldo_update), 861*0f936752SRohit Agarwal MSM_PIN_FUNCTION(m_voc), 862*0f936752SRohit Agarwal MSM_PIN_FUNCTION(mgpi_clk), 863*0f936752SRohit Agarwal MSM_PIN_FUNCTION(native_char), 864*0f936752SRohit Agarwal MSM_PIN_FUNCTION(native_tsens), 865*0f936752SRohit Agarwal MSM_PIN_FUNCTION(native_tsense), 866*0f936752SRohit Agarwal MSM_PIN_FUNCTION(nav_dr_sync), 867*0f936752SRohit Agarwal MSM_PIN_FUNCTION(nav_gpio), 868*0f936752SRohit Agarwal MSM_PIN_FUNCTION(pa_indicator), 869*0f936752SRohit Agarwal MSM_PIN_FUNCTION(pci_e), 870*0f936752SRohit Agarwal MSM_PIN_FUNCTION(pcie0_clkreq_n), 871*0f936752SRohit Agarwal MSM_PIN_FUNCTION(pcie1_clkreq_n), 872*0f936752SRohit Agarwal MSM_PIN_FUNCTION(pcie2_clkreq_n), 873*0f936752SRohit Agarwal MSM_PIN_FUNCTION(pll_bist_sync), 874*0f936752SRohit Agarwal MSM_PIN_FUNCTION(pll_clk_aux), 875*0f936752SRohit Agarwal MSM_PIN_FUNCTION(pll_ref_clk), 876*0f936752SRohit Agarwal MSM_PIN_FUNCTION(pri_mi2s), 877*0f936752SRohit Agarwal MSM_PIN_FUNCTION(prng_rosc), 878*0f936752SRohit Agarwal MSM_PIN_FUNCTION(qdss_cti), 879*0f936752SRohit Agarwal MSM_PIN_FUNCTION(qdss_gpio), 880*0f936752SRohit Agarwal MSM_PIN_FUNCTION(qlink0_b_en), 881*0f936752SRohit Agarwal MSM_PIN_FUNCTION(qlink0_b_req), 882*0f936752SRohit Agarwal MSM_PIN_FUNCTION(qlink0_l_en), 883*0f936752SRohit Agarwal MSM_PIN_FUNCTION(qlink0_l_req), 884*0f936752SRohit Agarwal MSM_PIN_FUNCTION(qlink1_l_en), 885*0f936752SRohit Agarwal MSM_PIN_FUNCTION(qlink1_l_req), 886*0f936752SRohit Agarwal MSM_PIN_FUNCTION(qlink0_wmss), 887*0f936752SRohit Agarwal MSM_PIN_FUNCTION(qlink1_wmss), 888*0f936752SRohit Agarwal MSM_PIN_FUNCTION(qup_se0), 889*0f936752SRohit Agarwal MSM_PIN_FUNCTION(qup_se1_l2_mira), 890*0f936752SRohit Agarwal MSM_PIN_FUNCTION(qup_se1_l2_mirb), 891*0f936752SRohit Agarwal MSM_PIN_FUNCTION(qup_se1_l3_mira), 892*0f936752SRohit Agarwal MSM_PIN_FUNCTION(qup_se1_l3_mirb), 893*0f936752SRohit Agarwal MSM_PIN_FUNCTION(qup_se2), 894*0f936752SRohit Agarwal MSM_PIN_FUNCTION(qup_se3), 895*0f936752SRohit Agarwal MSM_PIN_FUNCTION(qup_se4), 896*0f936752SRohit Agarwal MSM_PIN_FUNCTION(qup_se5), 897*0f936752SRohit Agarwal MSM_PIN_FUNCTION(qup_se6), 898*0f936752SRohit Agarwal MSM_PIN_FUNCTION(qup_se7), 899*0f936752SRohit Agarwal MSM_PIN_FUNCTION(qup_se8), 900*0f936752SRohit Agarwal MSM_PIN_FUNCTION(rgmii_rx_ctl), 901*0f936752SRohit Agarwal MSM_PIN_FUNCTION(rgmii_rxc), 902*0f936752SRohit Agarwal MSM_PIN_FUNCTION(rgmii_rxd), 903*0f936752SRohit Agarwal MSM_PIN_FUNCTION(rgmii_tx_ctl), 904*0f936752SRohit Agarwal MSM_PIN_FUNCTION(rgmii_txc), 905*0f936752SRohit Agarwal MSM_PIN_FUNCTION(rgmii_txd), 906*0f936752SRohit Agarwal MSM_PIN_FUNCTION(sd_card), 907*0f936752SRohit Agarwal MSM_PIN_FUNCTION(sdc1_tb), 908*0f936752SRohit Agarwal MSM_PIN_FUNCTION(sdc2_tb_trig), 909*0f936752SRohit Agarwal MSM_PIN_FUNCTION(sec_mi2s), 910*0f936752SRohit Agarwal MSM_PIN_FUNCTION(sgmii_phy_intr0_n), 911*0f936752SRohit Agarwal MSM_PIN_FUNCTION(sgmii_phy_intr1_n), 912*0f936752SRohit Agarwal MSM_PIN_FUNCTION(spmi_coex), 913*0f936752SRohit Agarwal MSM_PIN_FUNCTION(spmi_vgi), 914*0f936752SRohit Agarwal MSM_PIN_FUNCTION(tgu_ch0_trigout), 915*0f936752SRohit Agarwal MSM_PIN_FUNCTION(tmess_prng0), 916*0f936752SRohit Agarwal MSM_PIN_FUNCTION(tmess_prng1), 917*0f936752SRohit Agarwal MSM_PIN_FUNCTION(tmess_prng2), 918*0f936752SRohit Agarwal MSM_PIN_FUNCTION(tmess_prng3), 919*0f936752SRohit Agarwal MSM_PIN_FUNCTION(tri_mi2s), 920*0f936752SRohit Agarwal MSM_PIN_FUNCTION(uim1_clk), 921*0f936752SRohit Agarwal MSM_PIN_FUNCTION(uim1_data), 922*0f936752SRohit Agarwal MSM_PIN_FUNCTION(uim1_present), 923*0f936752SRohit Agarwal MSM_PIN_FUNCTION(uim1_reset), 924*0f936752SRohit Agarwal MSM_PIN_FUNCTION(uim2_clk), 925*0f936752SRohit Agarwal MSM_PIN_FUNCTION(uim2_data), 926*0f936752SRohit Agarwal MSM_PIN_FUNCTION(uim2_present), 927*0f936752SRohit Agarwal MSM_PIN_FUNCTION(uim2_reset), 928*0f936752SRohit Agarwal MSM_PIN_FUNCTION(usb2phy_ac_en), 929*0f936752SRohit Agarwal MSM_PIN_FUNCTION(vsense_trigger_mirnat), 930*0f936752SRohit Agarwal }; 931*0f936752SRohit Agarwal 932*0f936752SRohit Agarwal static const struct msm_pingroup sdx75_groups[] = { 933*0f936752SRohit Agarwal [0] = PINGROUP(0, uim2_data, ebi0_wrcdc, _, _, _, _, _, _, _, _), 934*0f936752SRohit Agarwal [1] = PINGROUP(1, uim2_present, _, _, _, _, _, _, _, _, _), 935*0f936752SRohit Agarwal [2] = PINGROUP(2, uim2_reset, ebi0_wrcdc, _, _, _, _, _, _, _, _), 936*0f936752SRohit Agarwal [3] = PINGROUP(3, uim2_clk, _, _, _, _, _, _, _, _, _), 937*0f936752SRohit Agarwal [4] = PINGROUP(4, uim1_data, _, _, _, _, _, _, _, _, _), 938*0f936752SRohit Agarwal [5] = PINGROUP(5, uim1_present, _, _, _, _, _, _, _, _, _), 939*0f936752SRohit Agarwal [6] = PINGROUP(6, uim1_reset, char_exec, _, _, _, _, _, _, _, _), 940*0f936752SRohit Agarwal [7] = PINGROUP(7, uim1_clk, char_exec, _, _, _, _, _, _, _, _), 941*0f936752SRohit Agarwal [8] = PINGROUP(8, qup_se0, ldo_en, _, _, _, _, _, _, _, _), 942*0f936752SRohit Agarwal [9] = PINGROUP(9, qup_se0, _, _, _, _, _, _, _, _, _), 943*0f936752SRohit Agarwal [10] = PINGROUP(10, qup_se0, _, _, _, _, _, _, _, _, _), 944*0f936752SRohit Agarwal [11] = PINGROUP(11, qup_se0, _, _, _, _, _, _, _, _, _), 945*0f936752SRohit Agarwal [12] = PINGROUP(12, qup_se1_l2_mira, ext_dbg, _, _, _, _, _, _, _, _), 946*0f936752SRohit Agarwal [13] = PINGROUP(13, qup_se1_l3_mira, ext_dbg, _, _, _, _, _, _, _, _), 947*0f936752SRohit Agarwal [14] = PINGROUP(14, qup_se2, ext_dbg, bimc_dte, _, _, _, _, _, _, _), 948*0f936752SRohit Agarwal [15] = PINGROUP(15, qup_se2, ext_dbg, bimc_dte, _, _, _, _, _, _, _), 949*0f936752SRohit Agarwal [16] = PINGROUP(16, pri_mi2s, qup_se2, qup_se1_l2_mirb, qdss_cti, qdss_cti, _, _, _, _, _), 950*0f936752SRohit Agarwal [17] = PINGROUP(17, pri_mi2s, qup_se2, qup_se1_l3_mirb, qdss_cti, qdss_cti, _, _, _, _, _), 951*0f936752SRohit Agarwal [18] = PINGROUP(18, pri_mi2s, _, _, _, _, _, _, _, _, _), 952*0f936752SRohit Agarwal [19] = PINGROUP(19, pri_mi2s, _, _, _, _, _, _, _, _, _), 953*0f936752SRohit Agarwal [20] = PINGROUP(20, sec_mi2s, _, _, _, _, _, _, _, _, _), 954*0f936752SRohit Agarwal [21] = PINGROUP(21, sec_mi2s, _, _, _, _, _, _, _, _, _), 955*0f936752SRohit Agarwal [22] = PINGROUP(22, sec_mi2s, _, _, _, _, _, _, _, _, _), 956*0f936752SRohit Agarwal [23] = PINGROUP(23, sec_mi2s, _, _, _, _, _, _, _, _, _), 957*0f936752SRohit Agarwal [24] = PINGROUP(24, _, atest_char, _, _, _, _, _, _, _, _), 958*0f936752SRohit Agarwal [25] = PINGROUP(25, gcc_125_clk, _, atest_char, _, _, _, _, _, _, _), 959*0f936752SRohit Agarwal [26] = PINGROUP(26, _, _, qlink1_l_en, dbg_out_clk, atest_char, _, _, _, _, _), 960*0f936752SRohit Agarwal [27] = PINGROUP(27, _, _, qlink1_l_req, prng_rosc, _, _, _, _, _, _), 961*0f936752SRohit Agarwal [28] = PINGROUP(28, _, qlink1_wmss, tmess_prng0, _, _, _, _, _, _, _), 962*0f936752SRohit Agarwal [29] = PINGROUP(29, _, _, _, native_char, tmess_prng1, _, _, _, _, _), 963*0f936752SRohit Agarwal [30] = PINGROUP(30, _, _, _, tmess_prng2, _, _, _, _, _, _), 964*0f936752SRohit Agarwal [31] = PINGROUP(31, _, _, cri_trng0, _, tmess_prng3, _, _, _, _, _), 965*0f936752SRohit Agarwal [32] = PINGROUP(32, _, _, cri_trng1, _, _, _, _, _, _, _), 966*0f936752SRohit Agarwal [33] = PINGROUP(33, _, _, native_char, _, _, _, _, _, _, _), 967*0f936752SRohit Agarwal [34] = PINGROUP(34, _, _, _, _, _, _, _, _, _, _), 968*0f936752SRohit Agarwal [35] = PINGROUP(35, nav_gpio, emac0_ptp, emac0_ptp, _, _, _, _, _, _, _), 969*0f936752SRohit Agarwal [36] = PINGROUP(36, nav_gpio, nav_dr_sync, nav_gpio, cri_trng, prng_rosc, _, _, _, _, _), 970*0f936752SRohit Agarwal [37] = PINGROUP(37, qlink0_l_en, _, pll_ref_clk, prng_rosc, vsense_trigger_mirnat, _, _, _, _, _), 971*0f936752SRohit Agarwal [38] = PINGROUP(38, qlink0_l_req, _, pll_bist_sync, prng_rosc, _, emac_cdc, _, native_tsens, _, _), 972*0f936752SRohit Agarwal [39] = PINGROUP(39, qlink0_wmss, _, mgpi_clk, gcc_gp1_clk, _, emac_cdc, _, _, _, _), 973*0f936752SRohit Agarwal [40] = PINGROUP(40, qlink0_b_en, _, mgpi_clk, pll_clk_aux, gcc_gp2_clk, _, _, _, _, _), 974*0f936752SRohit Agarwal [41] = PINGROUP(41, qlink0_b_req, _, jitter_bist, gcc_gp3_clk, _, _, atest_char, _, _, _), 975*0f936752SRohit Agarwal [42] = PINGROUP(42, pci_e, _, _, _, _, _, _, _, _, _), 976*0f936752SRohit Agarwal [43] = PINGROUP(43, pcie0_clkreq_n, _, _, _, _, _, _, _, _, _), 977*0f936752SRohit Agarwal [44] = PINGROUP(44, _, _, _, _, _, _, _, _, _, _), 978*0f936752SRohit Agarwal [45] = PINGROUP(45, ddr_pxi0, _, _, _, _, _, _, _, _, _), 979*0f936752SRohit Agarwal [46] = PINGROUP(46, coex_uart, ddr_bist, ddr_pxi0, _, _, _, _, _, _, _), 980*0f936752SRohit Agarwal [47] = PINGROUP(47, coex_uart, ddr_bist, _, _, _, _, _, _, _, _), 981*0f936752SRohit Agarwal [48] = PINGROUP(48, coex_uart2, spmi_coex, ddr_bist, _, _, _, _, _, _, _), 982*0f936752SRohit Agarwal [49] = PINGROUP(49, coex_uart2, spmi_coex, ddr_bist, _, _, _, _, _, _, _), 983*0f936752SRohit Agarwal [50] = PINGROUP(50, spmi_vgi, _, _, _, _, _, _, _, _, _), 984*0f936752SRohit Agarwal [51] = PINGROUP(51, spmi_vgi, _, _, _, _, _, _, _, _, _), 985*0f936752SRohit Agarwal [52] = PINGROUP(52, qup_se3, qdss_cti, qdss_cti, _, _, _, _, _, _, _), 986*0f936752SRohit Agarwal [53] = PINGROUP(53, qup_se3, qdss_cti, qdss_cti, _, _, _, _, _, _, _), 987*0f936752SRohit Agarwal [54] = PINGROUP(54, qup_se3, _, _, _, _, _, _, _, _, _), 988*0f936752SRohit Agarwal [55] = PINGROUP(55, qup_se3, tgu_ch0_trigout, _, _, _, _, _, _, _, _), 989*0f936752SRohit Agarwal [56] = PINGROUP(56, qdss_cti, qdss_cti, _, _, _, _, _, _, _, _), 990*0f936752SRohit Agarwal [57] = PINGROUP(57, qdss_cti, qdss_cti, _, native_char, _, _, _, _, _, _), 991*0f936752SRohit Agarwal [58] = PINGROUP(58, _, pa_indicator, _, _, _, _, _, _, _, _), 992*0f936752SRohit Agarwal [59] = PINGROUP(59, adsp_ext, qdss_cti, _, bimc_dte, _, _, _, _, _, _), 993*0f936752SRohit Agarwal [60] = PINGROUP(60, qdss_cti, _, _, _, _, _, _, _, _, _), 994*0f936752SRohit Agarwal [61] = PINGROUP(61, _, bimc_dte, _, _, _, _, _, _, _, _), 995*0f936752SRohit Agarwal [62] = PINGROUP(62, m_voc, ldo_update, _, _, _, _, _, _, _, _), 996*0f936752SRohit Agarwal [63] = PINGROUP(63, m_voc, _, atest_char, _, _, _, _, _, _, _), 997*0f936752SRohit Agarwal [64] = PINGROUP(64, qup_se4, m_voc, _, native_tsense, _, _, _, _, _, _), 998*0f936752SRohit Agarwal [65] = PINGROUP(65, qup_se4, m_voc, _, _, _, _, _, _, _, _), 999*0f936752SRohit Agarwal [66] = PINGROUP(66, _, native_char, _, _, _, _, _, _, _, _), 1000*0f936752SRohit Agarwal [67] = PINGROUP(67, _, native_char, _, _, _, _, _, _, _, _), 1001*0f936752SRohit Agarwal [68] = PINGROUP(68, adsp_ext, _, _, _, _, _, _, _, _, _), 1002*0f936752SRohit Agarwal [69] = PINGROUP(69, _, _, _, _, _, _, _, _, _, _), 1003*0f936752SRohit Agarwal [70] = PINGROUP(70, _, _, _, _, _, _, _, _, _, _), 1004*0f936752SRohit Agarwal [71] = PINGROUP(71, m_voc, _, _, _, _, _, _, _, _, _), 1005*0f936752SRohit Agarwal [72] = PINGROUP(72, _, _, _, _, _, _, _, _, _, _), 1006*0f936752SRohit Agarwal [73] = PINGROUP(73, _, _, _, _, _, _, _, _, _, _), 1007*0f936752SRohit Agarwal [74] = PINGROUP(74, i2s_mclk, _, _, _, _, _, _, _, _, _), 1008*0f936752SRohit Agarwal [75] = PINGROUP(75, _, _, _, _, _, _, _, _, _, _), 1009*0f936752SRohit Agarwal [76] = PINGROUP(76, native_tsense, _, _, _, _, _, _, _, _, _), 1010*0f936752SRohit Agarwal [77] = PINGROUP(77, _, _, _, _, _, _, _, _, _, _), 1011*0f936752SRohit Agarwal [78] = PINGROUP(78, qdss_cti, qdss_cti, _, _, _, _, _, _, _, _), 1012*0f936752SRohit Agarwal [79] = PINGROUP(79, qdss_cti, qdss_cti, _, _, _, _, _, _, _, _), 1013*0f936752SRohit Agarwal [80] = PINGROUP(80, usb2phy_ac_en, _, _, _, _, _, _, _, _, _), 1014*0f936752SRohit Agarwal [81] = PINGROUP(81, gcc_plltest, _, _, _, _, _, _, _, _, _), 1015*0f936752SRohit Agarwal [82] = PINGROUP(82, rgmii_txc, gcc_plltest, qdss_gpio, _, _, _, _, _, _, _), 1016*0f936752SRohit Agarwal [83] = PINGROUP(83, rgmii_txd, emac0_ptp, emac0_ptp, emac0_mcg, qdss_gpio, _, _, _, _, _), 1017*0f936752SRohit Agarwal [84] = PINGROUP(84, rgmii_txd, emac0_ptp, emac0_mcg, qdss_gpio, _, sdc1_tb, _, _, _, _), 1018*0f936752SRohit Agarwal [85] = PINGROUP(85, rgmii_txd, emac0_ptp, emac0_mcg, qdss_gpio, _, _, _, _, _, _), 1019*0f936752SRohit Agarwal [86] = PINGROUP(86, rgmii_txd, _, _, _, _, _, _, _, _, _), 1020*0f936752SRohit Agarwal [87] = PINGROUP(87, rgmii_tx_ctl, _, _, _, _, _, _, _, _, _), 1021*0f936752SRohit Agarwal [88] = PINGROUP(88, rgmii_rxc, _, _, _, _, _, _, _, _, _), 1022*0f936752SRohit Agarwal [89] = PINGROUP(89, rgmii_rxd, emac0_ptp, emac0_ptp, emac0_mcg, _, _, _, _, _, _), 1023*0f936752SRohit Agarwal [90] = PINGROUP(90, rgmii_rxd, coex_uart2, emac1_mcg, _, _, _, _, _, _, _), 1024*0f936752SRohit Agarwal [91] = PINGROUP(91, rgmii_rxd, coex_uart2, _, _, _, _, _, _, _, _), 1025*0f936752SRohit Agarwal [92] = PINGROUP(92, rgmii_rxd, emac1_mcg, _, _, _, _, _, _, _, _), 1026*0f936752SRohit Agarwal [93] = PINGROUP(93, rgmii_rx_ctl, emac1_mcg, _, _, _, _, _, _, _, _), 1027*0f936752SRohit Agarwal [94] = PINGROUP(94, eth0_mdc, qdss_gpio, _, _, _, _, _, _, _, _), 1028*0f936752SRohit Agarwal [95] = PINGROUP(95, eth0_mdio, qdss_gpio, _, _, _, _, _, _, _, _), 1029*0f936752SRohit Agarwal [96] = PINGROUP(96, qdss_gpio, _, _, _, _, _, _, _, _, _), 1030*0f936752SRohit Agarwal [97] = PINGROUP(97, sgmii_phy_intr0_n, _, qdss_gpio, _, _, _, _, _, _, _), 1031*0f936752SRohit Agarwal [98] = PINGROUP(98, tri_mi2s, ebi2_lcd_te, _, _, _, _, _, _, _, _), 1032*0f936752SRohit Agarwal [99] = PINGROUP(99, tri_mi2s, ebi2_lcd, _, _, _, _, _, _, _, _), 1033*0f936752SRohit Agarwal [100] = PINGROUP(100, tri_mi2s, ebi2_a, _, _, _, _, _, _, _, _), 1034*0f936752SRohit Agarwal [101] = PINGROUP(101, tri_mi2s, ebi2_lcd, _, _, _, _, _, _, _, _), 1035*0f936752SRohit Agarwal [102] = PINGROUP(102, _, _, _, _, _, _, _, _, _, _), 1036*0f936752SRohit Agarwal [103] = PINGROUP(103, _, _, _, _, _, _, _, _, _, _), 1037*0f936752SRohit Agarwal [104] = PINGROUP(104, nav_gpio, _, _, _, _, _, _, _, _, _), 1038*0f936752SRohit Agarwal [105] = PINGROUP(105, sd_card, _, _, _, _, _, _, _, _, _), 1039*0f936752SRohit Agarwal [106] = PINGROUP(106, eth1_mdc, _, _, _, _, _, _, _, _, _), 1040*0f936752SRohit Agarwal [107] = PINGROUP(107, eth1_mdio, _, _, _, _, _, _, _, _, _), 1041*0f936752SRohit Agarwal [108] = PINGROUP(108, _, _, _, _, _, _, _, _, _, _), 1042*0f936752SRohit Agarwal [109] = PINGROUP(109, sgmii_phy_intr1_n, _, _, _, _, _, _, _, _, _), 1043*0f936752SRohit Agarwal [110] = PINGROUP(110, qup_se5, qdss_gpio, _, _, _, _, _, _, _, _), 1044*0f936752SRohit Agarwal [111] = PINGROUP(111, qup_se5, qdss_gpio, _, _, _, _, _, _, _, _), 1045*0f936752SRohit Agarwal [112] = PINGROUP(112, qup_se6, emac1_ptp, emac1_ptp, qdss_gpio, _, _, _, _, _, _), 1046*0f936752SRohit Agarwal [113] = PINGROUP(113, qup_se6, emac1_ptp, emac1_ptp, qdss_gpio, _, _, _, _, _, _), 1047*0f936752SRohit Agarwal [114] = PINGROUP(114, qup_se6, emac1_ptp, emac1_ptp, qdss_gpio, _, _, _, _, _, _), 1048*0f936752SRohit Agarwal [115] = PINGROUP(115, qup_se6, emac1_ptp, emac1_ptp, qdss_gpio, _, _, _, _, _, _), 1049*0f936752SRohit Agarwal [116] = PINGROUP(116, qup_se7, qdss_gpio, _, _, _, _, _, _, _, _), 1050*0f936752SRohit Agarwal [117] = PINGROUP(117, qup_se7, qdss_gpio, _, _, _, _, _, _, _, _), 1051*0f936752SRohit Agarwal [118] = PINGROUP(118, qup_se7, qdss_gpio, _, _, _, _, _, _, _, _), 1052*0f936752SRohit Agarwal [119] = PINGROUP(119, qup_se7, emac0_ptp, qdss_gpio, _, _, _, _, _, _, _), 1053*0f936752SRohit Agarwal [120] = PINGROUP(120, _, _, _, _, _, _, _, _, _, _), 1054*0f936752SRohit Agarwal [121] = PINGROUP(121, pcie2_clkreq_n, _, _, _, _, _, _, _, _, _), 1055*0f936752SRohit Agarwal [122] = PINGROUP(122, emac1_mcg, _, _, _, _, _, _, _, _, _), 1056*0f936752SRohit Agarwal [123] = PINGROUP(123, emac0_ptp, emac0_ptp, emac0_ptp, emac0_ptp, _, _, _, _, _, _), 1057*0f936752SRohit Agarwal [124] = PINGROUP(124, pcie1_clkreq_n, qup_se8, _, _, _, _, _, _, _, _), 1058*0f936752SRohit Agarwal [125] = PINGROUP(125, qup_se8, _, _, _, _, _, _, _, _, _), 1059*0f936752SRohit Agarwal [126] = PINGROUP(126, audio_ref_clk, _, _, _, _, _, _, _, _, _), 1060*0f936752SRohit Agarwal [127] = PINGROUP(127, emac_pps_in, _, _, _, _, _, _, _, _, _), 1061*0f936752SRohit Agarwal [128] = PINGROUP(128, _, _, _, _, _, _, _, _, _, _), 1062*0f936752SRohit Agarwal [129] = PINGROUP(129, sdc2_tb_trig, _, _, _, _, _, _, _, _, _), 1063*0f936752SRohit Agarwal [130] = PINGROUP(130, sdc1_tb, _, _, _, _, _, _, _, _, _), 1064*0f936752SRohit Agarwal [131] = PINGROUP(131, _, _, _, _, _, _, _, _, _, _), 1065*0f936752SRohit Agarwal [132] = PINGROUP(132, _, _, _, _, _, _, _, _, _, _), 1066*0f936752SRohit Agarwal [133] = SDC_QDSD_PINGROUP(sdc1_rclk, 0x19a000, 16, 0), 1067*0f936752SRohit Agarwal [134] = SDC_QDSD_PINGROUP(sdc1_clk, 0x19a000, 14, 6), 1068*0f936752SRohit Agarwal [135] = SDC_QDSD_PINGROUP(sdc1_cmd, 0x19a000, 11, 3), 1069*0f936752SRohit Agarwal [136] = SDC_QDSD_PINGROUP(sdc1_data, 0x19a000, 9, 0), 1070*0f936752SRohit Agarwal [137] = SDC_QDSD_PINGROUP(sdc2_clk, 0x19b000, 14, 6), 1071*0f936752SRohit Agarwal [138] = SDC_QDSD_PINGROUP(sdc2_cmd, 0x19b000, 11, 3), 1072*0f936752SRohit Agarwal [139] = SDC_QDSD_PINGROUP(sdc2_data, 0x19b000, 9, 0), 1073*0f936752SRohit Agarwal }; 1074*0f936752SRohit Agarwal 1075*0f936752SRohit Agarwal static const struct msm_gpio_wakeirq_map sdx75_pdc_map[] = { 1076*0f936752SRohit Agarwal { 1, 57 }, { 2, 91 }, {5, 52 }, { 6, 109 }, { 9, 129 }, { 11, 62 }, 1077*0f936752SRohit Agarwal { 13, 84 }, { 15, 87 }, { 17, 88 }, { 18, 89 }, { 19, 90 }, { 20, 92 }, 1078*0f936752SRohit Agarwal { 21, 93 }, { 22, 94 }, { 23, 95 }, { 25, 96 }, { 27, 97 }, { 35, 58 }, 1079*0f936752SRohit Agarwal { 36, 53 }, { 38, 98 }, { 39, 99 }, { 40, 100 }, { 41, 101 }, { 42, 54 }, 1080*0f936752SRohit Agarwal { 43, 56 }, { 44, 71 }, { 46, 60 }, { 47, 61 }, { 49, 47 }, { 50, 126 }, 1081*0f936752SRohit Agarwal { 51, 55 }, { 52, 102 }, { 53, 141 }, { 54, 104 }, { 55, 105 }, { 56, 106 }, 1082*0f936752SRohit Agarwal { 57, 107 }, { 59, 108 }, { 60, 110 }, { 62, 111 }, { 63, 112 }, { 64, 113 }, 1083*0f936752SRohit Agarwal { 65, 114 }, { 67, 115 }, { 68, 116 }, { 69, 117 }, { 70, 118 }, { 71, 119 }, 1084*0f936752SRohit Agarwal { 72, 120 }, { 75, 121 }, { 76, 122 }, { 78, 123 }, { 79, 124 }, { 80, 125 }, 1085*0f936752SRohit Agarwal { 81, 50 }, { 85, 127 }, { 87, 128 }, { 91, 130 }, { 92, 131 }, { 93, 132 }, 1086*0f936752SRohit Agarwal { 94, 133 }, { 95, 134 }, { 97, 135 }, { 98, 136 }, { 101, 64 }, { 103, 51 }, 1087*0f936752SRohit Agarwal { 105, 65 }, { 106, 66 }, { 107, 67 }, { 108, 68 }, { 109, 69 }, { 111, 70 }, 1088*0f936752SRohit Agarwal { 113, 59 }, { 115, 72 }, { 116, 73 }, { 117, 74 }, { 118, 75 }, { 119, 76 }, 1089*0f936752SRohit Agarwal { 120, 77 }, { 121, 78 }, { 123, 79 }, { 124, 80 }, { 125, 63 }, { 127, 81 }, 1090*0f936752SRohit Agarwal { 128, 82 }, { 129, 83 }, { 130, 85 }, { 132, 86 }, 1091*0f936752SRohit Agarwal }; 1092*0f936752SRohit Agarwal 1093*0f936752SRohit Agarwal static const struct msm_pinctrl_soc_data sdx75_pinctrl = { 1094*0f936752SRohit Agarwal .pins = sdx75_pins, 1095*0f936752SRohit Agarwal .npins = ARRAY_SIZE(sdx75_pins), 1096*0f936752SRohit Agarwal .functions = sdx75_functions, 1097*0f936752SRohit Agarwal .nfunctions = ARRAY_SIZE(sdx75_functions), 1098*0f936752SRohit Agarwal .groups = sdx75_groups, 1099*0f936752SRohit Agarwal .ngroups = ARRAY_SIZE(sdx75_groups), 1100*0f936752SRohit Agarwal .ngpios = 133, 1101*0f936752SRohit Agarwal .wakeirq_map = sdx75_pdc_map, 1102*0f936752SRohit Agarwal .nwakeirq_map = ARRAY_SIZE(sdx75_pdc_map), 1103*0f936752SRohit Agarwal }; 1104*0f936752SRohit Agarwal 1105*0f936752SRohit Agarwal static const struct of_device_id sdx75_pinctrl_of_match[] = { 1106*0f936752SRohit Agarwal { .compatible = "qcom,sdx75-tlmm", .data = &sdx75_pinctrl }, 1107*0f936752SRohit Agarwal { } 1108*0f936752SRohit Agarwal }; 1109*0f936752SRohit Agarwal MODULE_DEVICE_TABLE(of, sdx75_pinctrl_of_match); 1110*0f936752SRohit Agarwal 1111*0f936752SRohit Agarwal static int sdx75_pinctrl_probe(struct platform_device *pdev) 1112*0f936752SRohit Agarwal { 1113*0f936752SRohit Agarwal const struct msm_pinctrl_soc_data *pinctrl_data; 1114*0f936752SRohit Agarwal 1115*0f936752SRohit Agarwal pinctrl_data = of_device_get_match_data(&pdev->dev); 1116*0f936752SRohit Agarwal if (!pinctrl_data) 1117*0f936752SRohit Agarwal return -EINVAL; 1118*0f936752SRohit Agarwal 1119*0f936752SRohit Agarwal return msm_pinctrl_probe(pdev, pinctrl_data); 1120*0f936752SRohit Agarwal } 1121*0f936752SRohit Agarwal 1122*0f936752SRohit Agarwal static struct platform_driver sdx75_pinctrl_driver = { 1123*0f936752SRohit Agarwal .driver = { 1124*0f936752SRohit Agarwal .name = "sdx75-tlmm", 1125*0f936752SRohit Agarwal .of_match_table = sdx75_pinctrl_of_match, 1126*0f936752SRohit Agarwal }, 1127*0f936752SRohit Agarwal .probe = sdx75_pinctrl_probe, 1128*0f936752SRohit Agarwal .remove = msm_pinctrl_remove, 1129*0f936752SRohit Agarwal }; 1130*0f936752SRohit Agarwal 1131*0f936752SRohit Agarwal static int __init sdx75_pinctrl_init(void) 1132*0f936752SRohit Agarwal { 1133*0f936752SRohit Agarwal return platform_driver_register(&sdx75_pinctrl_driver); 1134*0f936752SRohit Agarwal } 1135*0f936752SRohit Agarwal arch_initcall(sdx75_pinctrl_init); 1136*0f936752SRohit Agarwal 1137*0f936752SRohit Agarwal static void __exit sdx75_pinctrl_exit(void) 1138*0f936752SRohit Agarwal { 1139*0f936752SRohit Agarwal platform_driver_unregister(&sdx75_pinctrl_driver); 1140*0f936752SRohit Agarwal } 1141*0f936752SRohit Agarwal module_exit(sdx75_pinctrl_exit); 1142*0f936752SRohit Agarwal 1143*0f936752SRohit Agarwal MODULE_DESCRIPTION("QTI sdx75 pinctrl driver"); 1144*0f936752SRohit Agarwal MODULE_LICENSE("GPL"); 1145