1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6 #include <linux/module.h> 7 #include <linux/of.h> 8 #include <linux/platform_device.h> 9 #include <linux/pinctrl/pinctrl.h> 10 11 #include "pinctrl-msm.h" 12 13 #define FUNCTION(fname) \ 14 [msm_mux_##fname] = { \ 15 .name = #fname, \ 16 .groups = fname##_groups, \ 17 .ngroups = ARRAY_SIZE(fname##_groups), \ 18 } 19 20 #define REG_BASE 0x0 21 #define REG_SIZE 0x1000 22 #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ 23 { \ 24 .name = "gpio" #id, \ 25 .pins = gpio##id##_pins, \ 26 .npins = (unsigned int)ARRAY_SIZE(gpio##id##_pins), \ 27 .funcs = (int[]){ \ 28 msm_mux_gpio, /* gpio mode */ \ 29 msm_mux_##f1, \ 30 msm_mux_##f2, \ 31 msm_mux_##f3, \ 32 msm_mux_##f4, \ 33 msm_mux_##f5, \ 34 msm_mux_##f6, \ 35 msm_mux_##f7, \ 36 msm_mux_##f8, \ 37 msm_mux_##f9 \ 38 }, \ 39 .nfuncs = 10, \ 40 .ctl_reg = REG_BASE + REG_SIZE * id, \ 41 .io_reg = REG_BASE + 0x4 + REG_SIZE * id, \ 42 .intr_cfg_reg = REG_BASE + 0x8 + REG_SIZE * id, \ 43 .intr_status_reg = REG_BASE + 0xc + REG_SIZE * id, \ 44 .intr_target_reg = REG_BASE + 0x8 + REG_SIZE * id, \ 45 .mux_bit = 2, \ 46 .pull_bit = 0, \ 47 .drv_bit = 6, \ 48 .oe_bit = 9, \ 49 .in_bit = 0, \ 50 .out_bit = 1, \ 51 .intr_enable_bit = 0, \ 52 .intr_status_bit = 0, \ 53 .intr_target_bit = 5, \ 54 .intr_target_kpss_val = 3, \ 55 .intr_raw_status_bit = 4, \ 56 .intr_polarity_bit = 1, \ 57 .intr_detection_bit = 2, \ 58 .intr_detection_width = 2, \ 59 } 60 61 #define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \ 62 { \ 63 .name = #pg_name, \ 64 .pins = pg_name##_pins, \ 65 .npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \ 66 .ctl_reg = ctl, \ 67 .io_reg = 0, \ 68 .intr_cfg_reg = 0, \ 69 .intr_status_reg = 0, \ 70 .intr_target_reg = 0, \ 71 .mux_bit = -1, \ 72 .pull_bit = pull, \ 73 .drv_bit = drv, \ 74 .oe_bit = -1, \ 75 .in_bit = -1, \ 76 .out_bit = -1, \ 77 .intr_enable_bit = -1, \ 78 .intr_status_bit = -1, \ 79 .intr_target_bit = -1, \ 80 .intr_raw_status_bit = -1, \ 81 .intr_polarity_bit = -1, \ 82 .intr_detection_bit = -1, \ 83 .intr_detection_width = -1, \ 84 } 85 86 #define UFS_RESET(pg_name, offset) \ 87 { \ 88 .name = #pg_name, \ 89 .pins = pg_name##_pins, \ 90 .npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \ 91 .ctl_reg = offset, \ 92 .io_reg = offset + 0x4, \ 93 .intr_cfg_reg = 0, \ 94 .intr_status_reg = 0, \ 95 .intr_target_reg = 0, \ 96 .mux_bit = -1, \ 97 .pull_bit = 3, \ 98 .drv_bit = 0, \ 99 .oe_bit = -1, \ 100 .in_bit = -1, \ 101 .out_bit = 0, \ 102 .intr_enable_bit = -1, \ 103 .intr_status_bit = -1, \ 104 .intr_target_bit = -1, \ 105 .intr_raw_status_bit = -1, \ 106 .intr_polarity_bit = -1, \ 107 .intr_detection_bit = -1, \ 108 .intr_detection_width = -1, \ 109 } 110 111 static const struct pinctrl_pin_desc sdx65_pins[] = { 112 PINCTRL_PIN(0, "GPIO_0"), 113 PINCTRL_PIN(1, "GPIO_1"), 114 PINCTRL_PIN(2, "GPIO_2"), 115 PINCTRL_PIN(3, "GPIO_3"), 116 PINCTRL_PIN(4, "GPIO_4"), 117 PINCTRL_PIN(5, "GPIO_5"), 118 PINCTRL_PIN(6, "GPIO_6"), 119 PINCTRL_PIN(7, "GPIO_7"), 120 PINCTRL_PIN(8, "GPIO_8"), 121 PINCTRL_PIN(9, "GPIO_9"), 122 PINCTRL_PIN(10, "GPIO_10"), 123 PINCTRL_PIN(11, "GPIO_11"), 124 PINCTRL_PIN(12, "GPIO_12"), 125 PINCTRL_PIN(13, "GPIO_13"), 126 PINCTRL_PIN(14, "GPIO_14"), 127 PINCTRL_PIN(15, "GPIO_15"), 128 PINCTRL_PIN(16, "GPIO_16"), 129 PINCTRL_PIN(17, "GPIO_17"), 130 PINCTRL_PIN(18, "GPIO_18"), 131 PINCTRL_PIN(19, "GPIO_19"), 132 PINCTRL_PIN(20, "GPIO_20"), 133 PINCTRL_PIN(21, "GPIO_21"), 134 PINCTRL_PIN(22, "GPIO_22"), 135 PINCTRL_PIN(23, "GPIO_23"), 136 PINCTRL_PIN(24, "GPIO_24"), 137 PINCTRL_PIN(25, "GPIO_25"), 138 PINCTRL_PIN(26, "GPIO_26"), 139 PINCTRL_PIN(27, "GPIO_27"), 140 PINCTRL_PIN(28, "GPIO_28"), 141 PINCTRL_PIN(29, "GPIO_29"), 142 PINCTRL_PIN(30, "GPIO_30"), 143 PINCTRL_PIN(31, "GPIO_31"), 144 PINCTRL_PIN(32, "GPIO_32"), 145 PINCTRL_PIN(33, "GPIO_33"), 146 PINCTRL_PIN(34, "GPIO_34"), 147 PINCTRL_PIN(35, "GPIO_35"), 148 PINCTRL_PIN(36, "GPIO_36"), 149 PINCTRL_PIN(37, "GPIO_37"), 150 PINCTRL_PIN(38, "GPIO_38"), 151 PINCTRL_PIN(39, "GPIO_39"), 152 PINCTRL_PIN(40, "GPIO_40"), 153 PINCTRL_PIN(41, "GPIO_41"), 154 PINCTRL_PIN(42, "GPIO_42"), 155 PINCTRL_PIN(43, "GPIO_43"), 156 PINCTRL_PIN(44, "GPIO_44"), 157 PINCTRL_PIN(45, "GPIO_45"), 158 PINCTRL_PIN(46, "GPIO_46"), 159 PINCTRL_PIN(47, "GPIO_47"), 160 PINCTRL_PIN(48, "GPIO_48"), 161 PINCTRL_PIN(49, "GPIO_49"), 162 PINCTRL_PIN(50, "GPIO_50"), 163 PINCTRL_PIN(51, "GPIO_51"), 164 PINCTRL_PIN(52, "GPIO_52"), 165 PINCTRL_PIN(53, "GPIO_53"), 166 PINCTRL_PIN(54, "GPIO_54"), 167 PINCTRL_PIN(55, "GPIO_55"), 168 PINCTRL_PIN(56, "GPIO_56"), 169 PINCTRL_PIN(57, "GPIO_57"), 170 PINCTRL_PIN(58, "GPIO_58"), 171 PINCTRL_PIN(59, "GPIO_59"), 172 PINCTRL_PIN(60, "GPIO_60"), 173 PINCTRL_PIN(61, "GPIO_61"), 174 PINCTRL_PIN(62, "GPIO_62"), 175 PINCTRL_PIN(63, "GPIO_63"), 176 PINCTRL_PIN(64, "GPIO_64"), 177 PINCTRL_PIN(65, "GPIO_65"), 178 PINCTRL_PIN(66, "GPIO_66"), 179 PINCTRL_PIN(67, "GPIO_67"), 180 PINCTRL_PIN(68, "GPIO_68"), 181 PINCTRL_PIN(69, "GPIO_69"), 182 PINCTRL_PIN(70, "GPIO_70"), 183 PINCTRL_PIN(71, "GPIO_71"), 184 PINCTRL_PIN(72, "GPIO_72"), 185 PINCTRL_PIN(73, "GPIO_73"), 186 PINCTRL_PIN(74, "GPIO_74"), 187 PINCTRL_PIN(75, "GPIO_75"), 188 PINCTRL_PIN(76, "GPIO_76"), 189 PINCTRL_PIN(77, "GPIO_77"), 190 PINCTRL_PIN(78, "GPIO_78"), 191 PINCTRL_PIN(79, "GPIO_79"), 192 PINCTRL_PIN(80, "GPIO_80"), 193 PINCTRL_PIN(81, "GPIO_81"), 194 PINCTRL_PIN(82, "GPIO_82"), 195 PINCTRL_PIN(83, "GPIO_83"), 196 PINCTRL_PIN(84, "GPIO_84"), 197 PINCTRL_PIN(85, "GPIO_85"), 198 PINCTRL_PIN(86, "GPIO_86"), 199 PINCTRL_PIN(87, "GPIO_87"), 200 PINCTRL_PIN(88, "GPIO_88"), 201 PINCTRL_PIN(89, "GPIO_89"), 202 PINCTRL_PIN(90, "GPIO_90"), 203 PINCTRL_PIN(91, "GPIO_91"), 204 PINCTRL_PIN(92, "GPIO_92"), 205 PINCTRL_PIN(93, "GPIO_93"), 206 PINCTRL_PIN(94, "GPIO_94"), 207 PINCTRL_PIN(95, "GPIO_95"), 208 PINCTRL_PIN(96, "GPIO_96"), 209 PINCTRL_PIN(97, "GPIO_97"), 210 PINCTRL_PIN(98, "GPIO_98"), 211 PINCTRL_PIN(99, "GPIO_99"), 212 PINCTRL_PIN(100, "GPIO_100"), 213 PINCTRL_PIN(101, "GPIO_101"), 214 PINCTRL_PIN(102, "GPIO_102"), 215 PINCTRL_PIN(103, "GPIO_103"), 216 PINCTRL_PIN(104, "GPIO_104"), 217 PINCTRL_PIN(105, "GPIO_105"), 218 PINCTRL_PIN(106, "GPIO_106"), 219 PINCTRL_PIN(107, "GPIO_107"), 220 PINCTRL_PIN(108, "UFS_RESET"), 221 PINCTRL_PIN(109, "SDC1_RCLK"), 222 PINCTRL_PIN(110, "SDC1_CLK"), 223 PINCTRL_PIN(111, "SDC1_CMD"), 224 PINCTRL_PIN(112, "SDC1_DATA"), 225 }; 226 227 #define DECLARE_MSM_GPIO_PINS(pin) \ 228 static const unsigned int gpio##pin##_pins[] = { pin } 229 DECLARE_MSM_GPIO_PINS(0); 230 DECLARE_MSM_GPIO_PINS(1); 231 DECLARE_MSM_GPIO_PINS(2); 232 DECLARE_MSM_GPIO_PINS(3); 233 DECLARE_MSM_GPIO_PINS(4); 234 DECLARE_MSM_GPIO_PINS(5); 235 DECLARE_MSM_GPIO_PINS(6); 236 DECLARE_MSM_GPIO_PINS(7); 237 DECLARE_MSM_GPIO_PINS(8); 238 DECLARE_MSM_GPIO_PINS(9); 239 DECLARE_MSM_GPIO_PINS(10); 240 DECLARE_MSM_GPIO_PINS(11); 241 DECLARE_MSM_GPIO_PINS(12); 242 DECLARE_MSM_GPIO_PINS(13); 243 DECLARE_MSM_GPIO_PINS(14); 244 DECLARE_MSM_GPIO_PINS(15); 245 DECLARE_MSM_GPIO_PINS(16); 246 DECLARE_MSM_GPIO_PINS(17); 247 DECLARE_MSM_GPIO_PINS(18); 248 DECLARE_MSM_GPIO_PINS(19); 249 DECLARE_MSM_GPIO_PINS(20); 250 DECLARE_MSM_GPIO_PINS(21); 251 DECLARE_MSM_GPIO_PINS(22); 252 DECLARE_MSM_GPIO_PINS(23); 253 DECLARE_MSM_GPIO_PINS(24); 254 DECLARE_MSM_GPIO_PINS(25); 255 DECLARE_MSM_GPIO_PINS(26); 256 DECLARE_MSM_GPIO_PINS(27); 257 DECLARE_MSM_GPIO_PINS(28); 258 DECLARE_MSM_GPIO_PINS(29); 259 DECLARE_MSM_GPIO_PINS(30); 260 DECLARE_MSM_GPIO_PINS(31); 261 DECLARE_MSM_GPIO_PINS(32); 262 DECLARE_MSM_GPIO_PINS(33); 263 DECLARE_MSM_GPIO_PINS(34); 264 DECLARE_MSM_GPIO_PINS(35); 265 DECLARE_MSM_GPIO_PINS(36); 266 DECLARE_MSM_GPIO_PINS(37); 267 DECLARE_MSM_GPIO_PINS(38); 268 DECLARE_MSM_GPIO_PINS(39); 269 DECLARE_MSM_GPIO_PINS(40); 270 DECLARE_MSM_GPIO_PINS(41); 271 DECLARE_MSM_GPIO_PINS(42); 272 DECLARE_MSM_GPIO_PINS(43); 273 DECLARE_MSM_GPIO_PINS(44); 274 DECLARE_MSM_GPIO_PINS(45); 275 DECLARE_MSM_GPIO_PINS(46); 276 DECLARE_MSM_GPIO_PINS(47); 277 DECLARE_MSM_GPIO_PINS(48); 278 DECLARE_MSM_GPIO_PINS(49); 279 DECLARE_MSM_GPIO_PINS(50); 280 DECLARE_MSM_GPIO_PINS(51); 281 DECLARE_MSM_GPIO_PINS(52); 282 DECLARE_MSM_GPIO_PINS(53); 283 DECLARE_MSM_GPIO_PINS(54); 284 DECLARE_MSM_GPIO_PINS(55); 285 DECLARE_MSM_GPIO_PINS(56); 286 DECLARE_MSM_GPIO_PINS(57); 287 DECLARE_MSM_GPIO_PINS(58); 288 DECLARE_MSM_GPIO_PINS(59); 289 DECLARE_MSM_GPIO_PINS(60); 290 DECLARE_MSM_GPIO_PINS(61); 291 DECLARE_MSM_GPIO_PINS(62); 292 DECLARE_MSM_GPIO_PINS(63); 293 DECLARE_MSM_GPIO_PINS(64); 294 DECLARE_MSM_GPIO_PINS(65); 295 DECLARE_MSM_GPIO_PINS(66); 296 DECLARE_MSM_GPIO_PINS(67); 297 DECLARE_MSM_GPIO_PINS(68); 298 DECLARE_MSM_GPIO_PINS(69); 299 DECLARE_MSM_GPIO_PINS(70); 300 DECLARE_MSM_GPIO_PINS(71); 301 DECLARE_MSM_GPIO_PINS(72); 302 DECLARE_MSM_GPIO_PINS(73); 303 DECLARE_MSM_GPIO_PINS(74); 304 DECLARE_MSM_GPIO_PINS(75); 305 DECLARE_MSM_GPIO_PINS(76); 306 DECLARE_MSM_GPIO_PINS(77); 307 DECLARE_MSM_GPIO_PINS(78); 308 DECLARE_MSM_GPIO_PINS(79); 309 DECLARE_MSM_GPIO_PINS(80); 310 DECLARE_MSM_GPIO_PINS(81); 311 DECLARE_MSM_GPIO_PINS(82); 312 DECLARE_MSM_GPIO_PINS(83); 313 DECLARE_MSM_GPIO_PINS(84); 314 DECLARE_MSM_GPIO_PINS(85); 315 DECLARE_MSM_GPIO_PINS(86); 316 DECLARE_MSM_GPIO_PINS(87); 317 DECLARE_MSM_GPIO_PINS(88); 318 DECLARE_MSM_GPIO_PINS(89); 319 DECLARE_MSM_GPIO_PINS(90); 320 DECLARE_MSM_GPIO_PINS(91); 321 DECLARE_MSM_GPIO_PINS(92); 322 DECLARE_MSM_GPIO_PINS(93); 323 DECLARE_MSM_GPIO_PINS(94); 324 DECLARE_MSM_GPIO_PINS(95); 325 DECLARE_MSM_GPIO_PINS(96); 326 DECLARE_MSM_GPIO_PINS(97); 327 DECLARE_MSM_GPIO_PINS(98); 328 DECLARE_MSM_GPIO_PINS(99); 329 DECLARE_MSM_GPIO_PINS(100); 330 DECLARE_MSM_GPIO_PINS(101); 331 DECLARE_MSM_GPIO_PINS(102); 332 DECLARE_MSM_GPIO_PINS(103); 333 DECLARE_MSM_GPIO_PINS(104); 334 DECLARE_MSM_GPIO_PINS(105); 335 DECLARE_MSM_GPIO_PINS(106); 336 DECLARE_MSM_GPIO_PINS(107); 337 338 static const unsigned int ufs_reset_pins[] = { 108 }; 339 static const unsigned int sdc1_rclk_pins[] = { 109 }; 340 static const unsigned int sdc1_clk_pins[] = { 110 }; 341 static const unsigned int sdc1_cmd_pins[] = { 111 }; 342 static const unsigned int sdc1_data_pins[] = { 112 }; 343 344 enum sdx65_functions { 345 msm_mux_qlink0_wmss, 346 msm_mux_adsp_ext, 347 msm_mux_atest_char, 348 msm_mux_atest_char0, 349 msm_mux_atest_char1, 350 msm_mux_atest_char2, 351 msm_mux_atest_char3, 352 msm_mux_audio_ref, 353 msm_mux_bimc_dte0, 354 msm_mux_bimc_dte1, 355 msm_mux_blsp_i2c1, 356 msm_mux_blsp_i2c2, 357 msm_mux_blsp_i2c3, 358 msm_mux_blsp_i2c4, 359 msm_mux_blsp_spi1, 360 msm_mux_blsp_spi2, 361 msm_mux_blsp_spi3, 362 msm_mux_blsp_spi4, 363 msm_mux_blsp_uart1, 364 msm_mux_blsp_uart2, 365 msm_mux_blsp_uart3, 366 msm_mux_blsp_uart4, 367 msm_mux_char_exec, 368 msm_mux_coex_uart, 369 msm_mux_coex_uart2, 370 msm_mux_cri_trng, 371 msm_mux_cri_trng0, 372 msm_mux_cri_trng1, 373 msm_mux_dbg_out, 374 msm_mux_ddr_bist, 375 msm_mux_ddr_pxi0, 376 msm_mux_ebi0_wrcdc, 377 msm_mux_ebi2_a, 378 msm_mux_ebi2_lcd, 379 msm_mux_ext_dbg, 380 msm_mux_gcc_gp1, 381 msm_mux_gcc_gp2, 382 msm_mux_gcc_gp3, 383 msm_mux_gcc_plltest, 384 msm_mux_gpio, 385 msm_mux_i2s_mclk, 386 msm_mux_jitter_bist, 387 msm_mux_ldo_en, 388 msm_mux_ldo_update, 389 msm_mux_m_voc, 390 msm_mux_mgpi_clk, 391 msm_mux_native_char, 392 msm_mux_native_tsens, 393 msm_mux_native_tsense, 394 msm_mux_nav_gpio, 395 msm_mux_pa_indicator, 396 msm_mux_pci_e, 397 msm_mux_pcie_clkreq, 398 msm_mux_pll_bist, 399 msm_mux_pll_ref, 400 msm_mux_pri_mi2s, 401 msm_mux_pri_mi2s_ws, 402 msm_mux_prng_rosc, 403 msm_mux_qdss_cti, 404 msm_mux_qdss_gpio, 405 msm_mux_qlink0_en, 406 msm_mux_qlink0_req, 407 msm_mux_qlink1_en, 408 msm_mux_qlink1_req, 409 msm_mux_qlink1_wmss, 410 msm_mux_qlink2_en, 411 msm_mux_qlink2_req, 412 msm_mux_qlink2_wmss, 413 msm_mux_sdc1_tb, 414 msm_mux_sec_mi2s, 415 msm_mux_spmi_coex, 416 msm_mux_spmi_vgi, 417 msm_mux_tgu_ch0, 418 msm_mux_uim1_clk, 419 msm_mux_uim1_data, 420 msm_mux_uim1_present, 421 msm_mux_uim1_reset, 422 msm_mux_uim2_clk, 423 msm_mux_uim2_data, 424 msm_mux_uim2_present, 425 msm_mux_uim2_reset, 426 msm_mux_usb2phy_ac, 427 msm_mux_vsense_trigger, 428 msm_mux__, 429 }; 430 431 static const char * const gpio_groups[] = { 432 "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", 433 "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", 434 "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", 435 "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", 436 "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", 437 "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", 438 "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", 439 "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", 440 "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", 441 "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", 442 "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", 443 "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", 444 "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", 445 "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", 446 "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", 447 "gpio105", "gpio106", "gpio107", 448 }; 449 static const char * const uim2_data_groups[] = { 450 "gpio0", 451 }; 452 static const char * const blsp_uart1_groups[] = { 453 "gpio0", "gpio1", "gpio2", "gpio3", "gpio48", "gpio49", "gpio80", 454 "gpio81", 455 }; 456 static const char * const ebi0_wrcdc_groups[] = { 457 "gpio0", "gpio2", 458 }; 459 static const char * const uim2_present_groups[] = { 460 "gpio1", 461 }; 462 static const char * const uim2_reset_groups[] = { 463 "gpio2", 464 }; 465 static const char * const blsp_i2c1_groups[] = { 466 "gpio2", "gpio3", "gpio82", "gpio83", 467 }; 468 static const char * const uim2_clk_groups[] = { 469 "gpio3", 470 }; 471 static const char * const blsp_spi2_groups[] = { 472 "gpio4", "gpio5", "gpio6", "gpio7", "gpio23", "gpio47", "gpio62", 473 }; 474 static const char * const blsp_uart2_groups[] = { 475 "gpio4", "gpio5", "gpio6", "gpio7", "gpio63", "gpio64", "gpio65", 476 "gpio66", 477 }; 478 static const char * const blsp_i2c2_groups[] = { 479 "gpio6", "gpio7", "gpio65", "gpio66", 480 }; 481 static const char * const char_exec_groups[] = { 482 "gpio6", "gpio7", 483 }; 484 static const char * const qdss_gpio_groups[] = { 485 "gpio4", "gpio5", "gpio6", "gpio7", "gpio12", "gpio13", 486 "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", 487 "gpio33", "gpio42", "gpio63", "gpio64", "gpio65", "gpio66", 488 }; 489 static const char * const blsp_spi3_groups[] = { 490 "gpio8", "gpio9", "gpio10", "gpio11", "gpio23", "gpio47", "gpio62", 491 }; 492 static const char * const blsp_uart3_groups[] = { 493 "gpio8", "gpio9", "gpio10", "gpio11", 494 }; 495 static const char * const ext_dbg_groups[] = { 496 "gpio8", "gpio9", "gpio10", "gpio11", 497 }; 498 static const char * const ldo_en_groups[] = { 499 "gpio8", 500 }; 501 static const char * const blsp_i2c3_groups[] = { 502 "gpio10", "gpio11", 503 }; 504 static const char * const gcc_gp3_groups[] = { 505 "gpio11", 506 }; 507 static const char * const pri_mi2s_ws_groups[] = { 508 "gpio12", 509 }; 510 static const char * const pri_mi2s_groups[] = { 511 "gpio13", "gpio14", "gpio15", 512 }; 513 static const char * const vsense_trigger_groups[] = { 514 "gpio13", 515 }; 516 static const char * const native_tsens_groups[] = { 517 "gpio14", 518 }; 519 static const char * const bimc_dte0_groups[] = { 520 "gpio14", "gpio59", 521 }; 522 static const char * const bimc_dte1_groups[] = { 523 "gpio15", "gpio61", 524 }; 525 static const char * const sec_mi2s_groups[] = { 526 "gpio16", "gpio17", "gpio18", "gpio19", 527 }; 528 static const char * const blsp_spi4_groups[] = { 529 "gpio16", "gpio17", "gpio18", "gpio19", "gpio23", "gpio47", "gpio62", 530 }; 531 static const char * const blsp_uart4_groups[] = { 532 "gpio16", "gpio17", "gpio18", "gpio19", "gpio22", "gpio23", "gpio48", 533 "gpio49", 534 }; 535 static const char * const qdss_cti_groups[] = { 536 "gpio16", "gpio16", "gpio17", "gpio17", "gpio54", "gpio54", "gpio55", 537 "gpio55", "gpio59", "gpio60", "gpio65", "gpio65", "gpio66", "gpio66", 538 "gpio94", "gpio94", "gpio95", "gpio95", 539 }; 540 static const char * const blsp_i2c4_groups[] = { 541 "gpio18", "gpio19", "gpio84", "gpio85", 542 }; 543 static const char * const gcc_gp1_groups[] = { 544 "gpio18", 545 }; 546 static const char * const jitter_bist_groups[] = { 547 "gpio19", 548 }; 549 static const char * const gcc_gp2_groups[] = { 550 "gpio19", 551 }; 552 static const char * const pll_bist_groups[] = { 553 "gpio22", 554 }; 555 static const char * const blsp_spi1_groups[] = { 556 "gpio23", "gpio47", "gpio62", "gpio80", "gpio81", "gpio82", "gpio83", 557 }; 558 static const char * const adsp_ext_groups[] = { 559 "gpio24", "gpio25", 560 }; 561 static const char * const qlink0_wmss_groups[] = { 562 "gpio28", 563 }; 564 static const char * const native_tsense_groups[] = { 565 "gpio29", "gpio72", 566 }; 567 static const char * const nav_gpio_groups[] = { 568 "gpio31", "gpio32", 569 }; 570 static const char * const pll_ref_groups[] = { 571 "gpio32", 572 }; 573 static const char * const pa_indicator_groups[] = { 574 "gpio33", 575 }; 576 static const char * const qlink0_en_groups[] = { 577 "gpio34", 578 }; 579 static const char * const qlink0_req_groups[] = { 580 "gpio35", 581 }; 582 static const char * const dbg_out_groups[] = { 583 "gpio35", 584 }; 585 static const char * const cri_trng_groups[] = { 586 "gpio36", 587 }; 588 static const char * const prng_rosc_groups[] = { 589 "gpio38", 590 }; 591 static const char * const cri_trng0_groups[] = { 592 "gpio40", 593 }; 594 static const char * const cri_trng1_groups[] = { 595 "gpio41", 596 }; 597 static const char * const coex_uart_groups[] = { 598 "gpio44", "gpio45", 599 }; 600 static const char * const ddr_pxi0_groups[] = { 601 "gpio45", "gpio46", 602 }; 603 static const char * const m_voc_groups[] = { 604 "gpio46", "gpio48", "gpio49", "gpio59", "gpio60", 605 }; 606 static const char * const ddr_bist_groups[] = { 607 "gpio46", "gpio47", "gpio48", "gpio49", 608 }; 609 static const char * const pci_e_groups[] = { 610 "gpio53", 611 }; 612 static const char * const tgu_ch0_groups[] = { 613 "gpio55", 614 }; 615 static const char * const pcie_clkreq_groups[] = { 616 "gpio56", 617 }; 618 static const char * const native_char_groups[] = { 619 "gpio26", "gpio29", "gpio33", "gpio42", "gpio57", 620 }; 621 static const char * const mgpi_clk_groups[] = { 622 "gpio61", "gpio71", 623 }; 624 static const char * const qlink2_wmss_groups[] = { 625 "gpio61", 626 }; 627 static const char * const i2s_mclk_groups[] = { 628 "gpio62", 629 }; 630 static const char * const audio_ref_groups[] = { 631 "gpio62", 632 }; 633 static const char * const ldo_update_groups[] = { 634 "gpio62", 635 }; 636 static const char * const atest_char_groups[] = { 637 "gpio63", 638 }; 639 static const char * const atest_char3_groups[] = { 640 "gpio64", 641 }; 642 static const char * const atest_char2_groups[] = { 643 "gpio65", 644 }; 645 static const char * const atest_char1_groups[] = { 646 "gpio66", 647 }; 648 static const char * const uim1_data_groups[] = { 649 "gpio67", 650 }; 651 static const char * const atest_char0_groups[] = { 652 "gpio67", 653 }; 654 static const char * const uim1_present_groups[] = { 655 "gpio68", 656 }; 657 static const char * const uim1_reset_groups[] = { 658 "gpio69", 659 }; 660 static const char * const uim1_clk_groups[] = { 661 "gpio70", 662 }; 663 static const char * const qlink2_en_groups[] = { 664 "gpio71", 665 }; 666 static const char * const qlink1_en_groups[] = { 667 "gpio72", 668 }; 669 static const char * const qlink1_req_groups[] = { 670 "gpio73", 671 }; 672 static const char * const qlink1_wmss_groups[] = { 673 "gpio74", 674 }; 675 static const char * const coex_uart2_groups[] = { 676 "gpio75", "gpio76", "gpio102", "gpio103", 677 }; 678 static const char * const spmi_coex_groups[] = { 679 "gpio75", "gpio76", 680 }; 681 static const char * const qlink2_req_groups[] = { 682 "gpio77", 683 }; 684 static const char * const spmi_vgi_groups[] = { 685 "gpio78", "gpio79", 686 }; 687 static const char * const gcc_plltest_groups[] = { 688 "gpio81", "gpio82", 689 }; 690 static const char * const ebi2_lcd_groups[] = { 691 "gpio84", "gpio85", "gpio90", 692 }; 693 static const char * const ebi2_a_groups[] = { 694 "gpio89", 695 }; 696 static const char * const usb2phy_ac_groups[] = { 697 "gpio93", 698 }; 699 static const char * const sdc1_tb_groups[] = { 700 "gpio106", 701 }; 702 703 static const struct msm_function sdx65_functions[] = { 704 FUNCTION(qlink0_wmss), 705 FUNCTION(adsp_ext), 706 FUNCTION(atest_char), 707 FUNCTION(atest_char0), 708 FUNCTION(atest_char1), 709 FUNCTION(atest_char2), 710 FUNCTION(atest_char3), 711 FUNCTION(audio_ref), 712 FUNCTION(bimc_dte0), 713 FUNCTION(bimc_dte1), 714 FUNCTION(blsp_i2c1), 715 FUNCTION(blsp_i2c2), 716 FUNCTION(blsp_i2c3), 717 FUNCTION(blsp_i2c4), 718 FUNCTION(blsp_spi1), 719 FUNCTION(blsp_spi2), 720 FUNCTION(blsp_spi3), 721 FUNCTION(blsp_spi4), 722 FUNCTION(blsp_uart1), 723 FUNCTION(blsp_uart2), 724 FUNCTION(blsp_uart3), 725 FUNCTION(blsp_uart4), 726 FUNCTION(char_exec), 727 FUNCTION(coex_uart), 728 FUNCTION(coex_uart2), 729 FUNCTION(cri_trng), 730 FUNCTION(cri_trng0), 731 FUNCTION(cri_trng1), 732 FUNCTION(dbg_out), 733 FUNCTION(ddr_bist), 734 FUNCTION(ddr_pxi0), 735 FUNCTION(ebi0_wrcdc), 736 FUNCTION(ebi2_a), 737 FUNCTION(ebi2_lcd), 738 FUNCTION(ext_dbg), 739 FUNCTION(gcc_gp1), 740 FUNCTION(gcc_gp2), 741 FUNCTION(gcc_gp3), 742 FUNCTION(gcc_plltest), 743 FUNCTION(gpio), 744 FUNCTION(i2s_mclk), 745 FUNCTION(jitter_bist), 746 FUNCTION(ldo_en), 747 FUNCTION(ldo_update), 748 FUNCTION(m_voc), 749 FUNCTION(mgpi_clk), 750 FUNCTION(native_char), 751 FUNCTION(native_tsens), 752 FUNCTION(native_tsense), 753 FUNCTION(nav_gpio), 754 FUNCTION(pa_indicator), 755 FUNCTION(pci_e), 756 FUNCTION(pcie_clkreq), 757 FUNCTION(pll_bist), 758 FUNCTION(pll_ref), 759 FUNCTION(pri_mi2s), 760 FUNCTION(pri_mi2s_ws), 761 FUNCTION(prng_rosc), 762 FUNCTION(qdss_cti), 763 FUNCTION(qdss_gpio), 764 FUNCTION(qlink0_en), 765 FUNCTION(qlink0_req), 766 FUNCTION(qlink1_en), 767 FUNCTION(qlink1_req), 768 FUNCTION(qlink1_wmss), 769 FUNCTION(qlink2_en), 770 FUNCTION(qlink2_req), 771 FUNCTION(qlink2_wmss), 772 FUNCTION(sdc1_tb), 773 FUNCTION(sec_mi2s), 774 FUNCTION(spmi_coex), 775 FUNCTION(spmi_vgi), 776 FUNCTION(tgu_ch0), 777 FUNCTION(uim1_clk), 778 FUNCTION(uim1_data), 779 FUNCTION(uim1_present), 780 FUNCTION(uim1_reset), 781 FUNCTION(uim2_clk), 782 FUNCTION(uim2_data), 783 FUNCTION(uim2_present), 784 FUNCTION(uim2_reset), 785 FUNCTION(usb2phy_ac), 786 FUNCTION(vsense_trigger), 787 }; 788 789 /* Every pin is maintained as a single group, and missing or non-existing pin 790 * would be maintained as dummy group to synchronize pin group index with 791 * pin descriptor registered with pinctrl core. 792 * Clients would not be able to request these dummy pin groups. 793 */ 794 static const struct msm_pingroup sdx65_groups[] = { 795 [0] = PINGROUP(0, uim2_data, blsp_uart1, ebi0_wrcdc, _, _, _, _, _, _), 796 [1] = PINGROUP(1, uim2_present, blsp_uart1, _, _, _, _, _, _, _), 797 [2] = PINGROUP(2, uim2_reset, blsp_uart1, blsp_i2c1, ebi0_wrcdc, _, _, _, _, _), 798 [3] = PINGROUP(3, uim2_clk, blsp_uart1, blsp_i2c1, _, _, _, _, _, _), 799 [4] = PINGROUP(4, blsp_spi2, blsp_uart2, _, qdss_gpio, _, _, _, _, _), 800 [5] = PINGROUP(5, blsp_spi2, blsp_uart2, _, qdss_gpio, _, _, _, _, _), 801 [6] = PINGROUP(6, blsp_spi2, blsp_uart2, blsp_i2c2, char_exec, _, qdss_gpio, _, _, _), 802 [7] = PINGROUP(7, blsp_spi2, blsp_uart2, blsp_i2c2, char_exec, _, qdss_gpio, _, _, _), 803 [8] = PINGROUP(8, blsp_spi3, blsp_uart3, ext_dbg, ldo_en, _, _, _, _, _), 804 [9] = PINGROUP(9, blsp_spi3, blsp_uart3, ext_dbg, _, _, _, _, _, _), 805 [10] = PINGROUP(10, blsp_spi3, blsp_uart3, blsp_i2c3, ext_dbg, _, _, _, _, _), 806 [11] = PINGROUP(11, blsp_spi3, blsp_uart3, blsp_i2c3, ext_dbg, gcc_gp3, _, _, _, _), 807 [12] = PINGROUP(12, pri_mi2s_ws, _, qdss_gpio, _, _, _, _, _, _), 808 [13] = PINGROUP(13, pri_mi2s, _, qdss_gpio, vsense_trigger, _, _, _, _, _), 809 [14] = PINGROUP(14, pri_mi2s, _, _, qdss_gpio, native_tsens, bimc_dte0, _, _, _), 810 [15] = PINGROUP(15, pri_mi2s, _, _, qdss_gpio, bimc_dte1, _, _, _, _), 811 [16] = PINGROUP(16, sec_mi2s, blsp_spi4, blsp_uart4, qdss_cti, qdss_cti, _, _, qdss_gpio, _), 812 [17] = PINGROUP(17, sec_mi2s, blsp_spi4, blsp_uart4, qdss_cti, qdss_cti, _, qdss_gpio, _, _), 813 [18] = PINGROUP(18, sec_mi2s, blsp_spi4, blsp_uart4, blsp_i2c4, gcc_gp1, qdss_gpio, _, _, _), 814 [19] = PINGROUP(19, sec_mi2s, blsp_spi4, blsp_uart4, blsp_i2c4, jitter_bist, gcc_gp2, _, qdss_gpio, _), 815 [20] = PINGROUP(20, _, _, _, _, _, _, _, _, _), 816 [21] = PINGROUP(21, _, _, _, _, _, _, _, _, _), 817 [22] = PINGROUP(22, blsp_uart4, pll_bist, _, _, _, _, _, _, _), 818 [23] = PINGROUP(23, blsp_uart4, blsp_spi2, blsp_spi1, blsp_spi3, blsp_spi4, _, _, _, _), 819 [24] = PINGROUP(24, adsp_ext, _, _, _, _, _, _, _, _), 820 [25] = PINGROUP(25, adsp_ext, _, _, _, _, _, _, _, _), 821 [26] = PINGROUP(26, _, _, _, native_char, _, _, _, _, _), 822 [27] = PINGROUP(27, _, _, _, _, _, _, _, _, _), 823 [28] = PINGROUP(28, qlink0_wmss, _, _, _, _, _, _, _, _), 824 [29] = PINGROUP(29, _, _, _, native_tsense, native_char, _, _, _, _), 825 [30] = PINGROUP(30, _, _, _, _, _, _, _, _, _), 826 [31] = PINGROUP(31, nav_gpio, _, _, _, _, _, _, _, _), 827 [32] = PINGROUP(32, nav_gpio, pll_ref, _, _, _, _, _, _, _), 828 [33] = PINGROUP(33, _, pa_indicator, qdss_gpio, native_char, _, _, _, _, _), 829 [34] = PINGROUP(34, qlink0_en, _, _, _, _, _, _, _, _), 830 [35] = PINGROUP(35, qlink0_req, dbg_out, _, _, _, _, _, _, _), 831 [36] = PINGROUP(36, _, _, cri_trng, _, _, _, _, _, _), 832 [37] = PINGROUP(37, _, _, _, _, _, _, _, _, _), 833 [38] = PINGROUP(38, _, _, prng_rosc, _, _, _, _, _, _), 834 [39] = PINGROUP(39, _, _, _, _, _, _, _, _, _), 835 [40] = PINGROUP(40, _, _, cri_trng0, _, _, _, _, _, _), 836 [41] = PINGROUP(41, _, _, cri_trng1, _, _, _, _, _, _), 837 [42] = PINGROUP(42, _, qdss_gpio, native_char, _, _, _, _, _, _), 838 [43] = PINGROUP(43, _, _, _, _, _, _, _, _, _), 839 [44] = PINGROUP(44, coex_uart, _, _, _, _, _, _, _, _), 840 [45] = PINGROUP(45, coex_uart, ddr_pxi0, _, _, _, _, _, _, _), 841 [46] = PINGROUP(46, m_voc, ddr_bist, ddr_pxi0, _, _, _, _, _, _), 842 [47] = PINGROUP(47, ddr_bist, blsp_spi1, blsp_spi2, blsp_spi3, blsp_spi4, _, _, _, _), 843 [48] = PINGROUP(48, m_voc, blsp_uart1, blsp_uart4, ddr_bist, _, _, _, _, _), 844 [49] = PINGROUP(49, m_voc, blsp_uart1, blsp_uart4, ddr_bist, _, _, _, _, _), 845 [50] = PINGROUP(50, _, _, _, _, _, _, _, _, _), 846 [51] = PINGROUP(51, _, _, _, _, _, _, _, _, _), 847 [52] = PINGROUP(52, _, _, _, _, _, _, _, _, _), 848 [53] = PINGROUP(53, pci_e, _, _, _, _, _, _, _, _), 849 [54] = PINGROUP(54, qdss_cti, qdss_cti, _, _, _, _, _, _, _), 850 [55] = PINGROUP(55, qdss_cti, qdss_cti, tgu_ch0, _, _, _, _, _, _), 851 [56] = PINGROUP(56, pcie_clkreq, _, _, _, _, _, _, _, _), 852 [57] = PINGROUP(57, _, native_char, _, _, _, _, _, _, _), 853 [58] = PINGROUP(58, _, _, _, _, _, _, _, _, _), 854 [59] = PINGROUP(59, qdss_cti, m_voc, bimc_dte0, _, _, _, _, _, _), 855 [60] = PINGROUP(60, qdss_cti, _, m_voc, _, _, _, _, _, _), 856 [61] = PINGROUP(61, mgpi_clk, qlink2_wmss, bimc_dte1, _, _, _, _, _, _), 857 [62] = PINGROUP(62, i2s_mclk, audio_ref, blsp_spi1, blsp_spi2, blsp_spi3, blsp_spi4, ldo_update, _, _), 858 [63] = PINGROUP(63, blsp_uart2, _, qdss_gpio, atest_char, _, _, _, _, _), 859 [64] = PINGROUP(64, blsp_uart2, qdss_gpio, atest_char3, _, _, _, _, _, _), 860 [65] = PINGROUP(65, blsp_uart2, blsp_i2c2, qdss_cti, qdss_cti, _, qdss_gpio, atest_char2, _, _), 861 [66] = PINGROUP(66, blsp_uart2, blsp_i2c2, qdss_cti, qdss_cti, qdss_gpio, atest_char1, _, _, _), 862 [67] = PINGROUP(67, uim1_data, atest_char0, _, _, _, _, _, _, _), 863 [68] = PINGROUP(68, uim1_present, _, _, _, _, _, _, _, _), 864 [69] = PINGROUP(69, uim1_reset, _, _, _, _, _, _, _, _), 865 [70] = PINGROUP(70, uim1_clk, _, _, _, _, _, _, _, _), 866 [71] = PINGROUP(71, mgpi_clk, qlink2_en, _, _, _, _, _, _, _), 867 [72] = PINGROUP(72, qlink1_en, _, native_tsense, _, _, _, _, _, _), 868 [73] = PINGROUP(73, qlink1_req, _, _, _, _, _, _, _, _), 869 [74] = PINGROUP(74, qlink1_wmss, _, _, _, _, _, _, _, _), 870 [75] = PINGROUP(75, coex_uart2, spmi_coex, _, _, _, _, _, _, _), 871 [76] = PINGROUP(76, coex_uart2, spmi_coex, _, _, _, _, _, _, _), 872 [77] = PINGROUP(77, _, qlink2_req, _, _, _, _, _, _, _), 873 [78] = PINGROUP(78, spmi_vgi, _, _, _, _, _, _, _, _), 874 [79] = PINGROUP(79, spmi_vgi, _, _, _, _, _, _, _, _), 875 [80] = PINGROUP(80, _, blsp_spi1, _, blsp_uart1, _, _, _, _, _), 876 [81] = PINGROUP(81, _, blsp_spi1, _, blsp_uart1, gcc_plltest, _, _, _, _), 877 [82] = PINGROUP(82, _, blsp_spi1, _, blsp_i2c1, gcc_plltest, _, _, _, _), 878 [83] = PINGROUP(83, _, blsp_spi1, _, blsp_i2c1, _, _, _, _, _), 879 [84] = PINGROUP(84, _, ebi2_lcd, _, blsp_i2c4, _, _, _, _, _), 880 [85] = PINGROUP(85, _, ebi2_lcd, _, blsp_i2c4, _, _, _, _, _), 881 [86] = PINGROUP(86, _, _, _, _, _, _, _, _, _), 882 [87] = PINGROUP(87, _, _, _, _, _, _, _, _, _), 883 [88] = PINGROUP(88, _, _, _, _, _, _, _, _, _), 884 [89] = PINGROUP(89, _, _, _, _, ebi2_a, _, _, _, _), 885 [90] = PINGROUP(90, _, _, _, _, ebi2_lcd, _, _, _, _), 886 [91] = PINGROUP(91, _, _, _, _, _, _, _, _, _), 887 [92] = PINGROUP(92, _, _, _, _, _, _, _, _, _), 888 [93] = PINGROUP(93, _, _, usb2phy_ac, _, _, _, _, _, _), 889 [94] = PINGROUP(94, qdss_cti, qdss_cti, _, _, _, _, _, _, _), 890 [95] = PINGROUP(95, qdss_cti, qdss_cti, _, _, _, _, _, _, _), 891 [96] = PINGROUP(96, _, _, _, _, _, _, _, _, _), 892 [97] = PINGROUP(97, _, _, _, _, _, _, _, _, _), 893 [98] = PINGROUP(98, _, _, _, _, _, _, _, _, _), 894 [99] = PINGROUP(99, _, _, _, _, _, _, _, _, _), 895 [100] = PINGROUP(100, _, _, _, _, _, _, _, _, _), 896 [101] = PINGROUP(101, _, _, _, _, _, _, _, _, _), 897 [102] = PINGROUP(102, _, _, coex_uart2, _, _, _, _, _, _), 898 [103] = PINGROUP(103, _, _, coex_uart2, _, _, _, _, _, _), 899 [104] = PINGROUP(104, _, _, _, _, _, _, _, _, _), 900 [105] = PINGROUP(105, _, _, _, _, _, _, _, _, _), 901 [106] = PINGROUP(106, sdc1_tb, _, _, _, _, _, _, _, _), 902 [107] = PINGROUP(107, _, _, _, _, _, _, _, _, _), 903 [108] = UFS_RESET(ufs_reset, 0x0), 904 [109] = SDC_QDSD_PINGROUP(sdc1_rclk, 0x9a000, 15, 0), 905 [110] = SDC_QDSD_PINGROUP(sdc1_clk, 0x9a000, 13, 6), 906 [111] = SDC_QDSD_PINGROUP(sdc1_cmd, 0x9a000, 11, 3), 907 [112] = SDC_QDSD_PINGROUP(sdc1_data, 0x9a000, 9, 0), 908 }; 909 910 static const struct msm_gpio_wakeirq_map sdx65_pdc_map[] = { 911 {1, 20}, {2, 21}, {5, 22}, {6, 23}, {9, 24}, {10, 25}, 912 {11, 26}, {12, 27}, {13, 28}, {14, 29}, {15, 30}, {16, 31}, 913 {17, 32}, {18, 33}, {19, 34}, {21, 35}, {22, 36}, {23, 70}, 914 {24, 37}, {25, 38}, {35, 40}, {43, 41}, {46, 44}, {48, 45}, 915 {49, 57}, {50, 46}, {52, 47}, {54, 49}, {55, 50}, {60, 53}, 916 {61, 54}, {64, 55}, {65, 81}, {68, 56}, {71, 58}, {73, 59}, 917 {77, 77}, {81, 65}, {83, 63}, {84, 64}, {86, 66}, {88, 67}, 918 {89, 68}, {90, 69}, {93, 71}, {94, 72}, {95, 73}, {96, 74}, 919 {99, 75}, {103, 78}, {104, 79} 920 }; 921 922 static const struct msm_pinctrl_soc_data sdx65_pinctrl = { 923 .pins = sdx65_pins, 924 .npins = ARRAY_SIZE(sdx65_pins), 925 .functions = sdx65_functions, 926 .nfunctions = ARRAY_SIZE(sdx65_functions), 927 .groups = sdx65_groups, 928 .ngroups = ARRAY_SIZE(sdx65_groups), 929 .ngpios = 109, 930 .wakeirq_map = sdx65_pdc_map, 931 .nwakeirq_map = ARRAY_SIZE(sdx65_pdc_map), 932 }; 933 934 static int sdx65_pinctrl_probe(struct platform_device *pdev) 935 { 936 return msm_pinctrl_probe(pdev, &sdx65_pinctrl); 937 } 938 939 static const struct of_device_id sdx65_pinctrl_of_match[] = { 940 { .compatible = "qcom,sdx65-tlmm", }, 941 { }, 942 }; 943 944 static struct platform_driver sdx65_pinctrl_driver = { 945 .driver = { 946 .name = "sdx65-tlmm", 947 .of_match_table = sdx65_pinctrl_of_match, 948 }, 949 .probe = sdx65_pinctrl_probe, 950 .remove = msm_pinctrl_remove, 951 }; 952 953 static int __init sdx65_pinctrl_init(void) 954 { 955 return platform_driver_register(&sdx65_pinctrl_driver); 956 } 957 arch_initcall(sdx65_pinctrl_init); 958 959 static void __exit sdx65_pinctrl_exit(void) 960 { 961 platform_driver_unregister(&sdx65_pinctrl_driver); 962 } 963 module_exit(sdx65_pinctrl_exit); 964 965 MODULE_DESCRIPTION("QTI sdx65 pinctrl driver"); 966 MODULE_LICENSE("GPL v2"); 967 MODULE_DEVICE_TABLE(of, sdx65_pinctrl_of_match); 968