1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
4  */
5 
6 #include <linux/module.h>
7 #include <linux/of.h>
8 #include <linux/platform_device.h>
9 #include <linux/pinctrl/pinctrl.h>
10 
11 #include "pinctrl-msm.h"
12 
13 #define FUNCTION(fname)			                \
14 	[msm_mux_##fname] = {		                \
15 		.name = #fname,				\
16 		.groups = fname##_groups,               \
17 		.ngroups = ARRAY_SIZE(fname##_groups),	\
18 	}
19 
20 #define REG_SIZE 0x1000
21 
22 #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9)	\
23 	{					        \
24 		.name = "gpio" #id,			\
25 		.pins = gpio##id##_pins,		\
26 		.npins = (unsigned int)ARRAY_SIZE(gpio##id##_pins),	\
27 		.funcs = (int[]){			\
28 			msm_mux_gpio, /* gpio mode */	\
29 			msm_mux_##f1,			\
30 			msm_mux_##f2,			\
31 			msm_mux_##f3,			\
32 			msm_mux_##f4,			\
33 			msm_mux_##f5,			\
34 			msm_mux_##f6,			\
35 			msm_mux_##f7,			\
36 			msm_mux_##f8,			\
37 			msm_mux_##f9			\
38 		},				        \
39 		.nfuncs = 10,				\
40 		.ctl_reg = REG_SIZE * id,			\
41 		.io_reg = 0x4 + REG_SIZE * id,		\
42 		.intr_cfg_reg = 0x8 + REG_SIZE * id,		\
43 		.intr_status_reg = 0xc + REG_SIZE * id,	\
44 		.intr_target_reg = 0x8 + REG_SIZE * id,	\
45 		.mux_bit = 2,			\
46 		.pull_bit = 0,			\
47 		.drv_bit = 6,			\
48 		.oe_bit = 9,			\
49 		.in_bit = 0,			\
50 		.out_bit = 1,			\
51 		.intr_enable_bit = 0,		\
52 		.intr_status_bit = 0,		\
53 		.intr_target_bit = 5,		\
54 		.intr_target_kpss_val = 3,	\
55 		.intr_raw_status_bit = 4,	\
56 		.intr_polarity_bit = 1,		\
57 		.intr_detection_bit = 2,	\
58 		.intr_detection_width = 2,	\
59 	}
60 
61 #define SDC_PINGROUP(pg_name, ctl, pull, drv)	\
62 	{					        \
63 		.name = #pg_name,			\
64 		.pins = pg_name##_pins,			\
65 		.npins = (unsigned int)ARRAY_SIZE(pg_name##_pins),	\
66 		.ctl_reg = ctl,				\
67 		.io_reg = 0,				\
68 		.intr_cfg_reg = 0,			\
69 		.intr_status_reg = 0,			\
70 		.intr_target_reg = 0,			\
71 		.mux_bit = -1,				\
72 		.pull_bit = pull,			\
73 		.drv_bit = drv,				\
74 		.oe_bit = -1,				\
75 		.in_bit = -1,				\
76 		.out_bit = -1,				\
77 		.intr_enable_bit = -1,			\
78 		.intr_status_bit = -1,			\
79 		.intr_target_bit = -1,			\
80 		.intr_raw_status_bit = -1,		\
81 		.intr_polarity_bit = -1,		\
82 		.intr_detection_bit = -1,		\
83 		.intr_detection_width = -1,		\
84 	}
85 
86 static const struct pinctrl_pin_desc sdx55_pins[] = {
87 	PINCTRL_PIN(0, "GPIO_0"),
88 	PINCTRL_PIN(1, "GPIO_1"),
89 	PINCTRL_PIN(2, "GPIO_2"),
90 	PINCTRL_PIN(3, "GPIO_3"),
91 	PINCTRL_PIN(4, "GPIO_4"),
92 	PINCTRL_PIN(5, "GPIO_5"),
93 	PINCTRL_PIN(6, "GPIO_6"),
94 	PINCTRL_PIN(7, "GPIO_7"),
95 	PINCTRL_PIN(8, "GPIO_8"),
96 	PINCTRL_PIN(9, "GPIO_9"),
97 	PINCTRL_PIN(10, "GPIO_10"),
98 	PINCTRL_PIN(11, "GPIO_11"),
99 	PINCTRL_PIN(12, "GPIO_12"),
100 	PINCTRL_PIN(13, "GPIO_13"),
101 	PINCTRL_PIN(14, "GPIO_14"),
102 	PINCTRL_PIN(15, "GPIO_15"),
103 	PINCTRL_PIN(16, "GPIO_16"),
104 	PINCTRL_PIN(17, "GPIO_17"),
105 	PINCTRL_PIN(18, "GPIO_18"),
106 	PINCTRL_PIN(19, "GPIO_19"),
107 	PINCTRL_PIN(20, "GPIO_20"),
108 	PINCTRL_PIN(21, "GPIO_21"),
109 	PINCTRL_PIN(22, "GPIO_22"),
110 	PINCTRL_PIN(23, "GPIO_23"),
111 	PINCTRL_PIN(24, "GPIO_24"),
112 	PINCTRL_PIN(25, "GPIO_25"),
113 	PINCTRL_PIN(26, "GPIO_26"),
114 	PINCTRL_PIN(27, "GPIO_27"),
115 	PINCTRL_PIN(28, "GPIO_28"),
116 	PINCTRL_PIN(29, "GPIO_29"),
117 	PINCTRL_PIN(30, "GPIO_30"),
118 	PINCTRL_PIN(31, "GPIO_31"),
119 	PINCTRL_PIN(32, "GPIO_32"),
120 	PINCTRL_PIN(33, "GPIO_33"),
121 	PINCTRL_PIN(34, "GPIO_34"),
122 	PINCTRL_PIN(35, "GPIO_35"),
123 	PINCTRL_PIN(36, "GPIO_36"),
124 	PINCTRL_PIN(37, "GPIO_37"),
125 	PINCTRL_PIN(38, "GPIO_38"),
126 	PINCTRL_PIN(39, "GPIO_39"),
127 	PINCTRL_PIN(40, "GPIO_40"),
128 	PINCTRL_PIN(41, "GPIO_41"),
129 	PINCTRL_PIN(42, "GPIO_42"),
130 	PINCTRL_PIN(43, "GPIO_43"),
131 	PINCTRL_PIN(44, "GPIO_44"),
132 	PINCTRL_PIN(45, "GPIO_45"),
133 	PINCTRL_PIN(46, "GPIO_46"),
134 	PINCTRL_PIN(47, "GPIO_47"),
135 	PINCTRL_PIN(48, "GPIO_48"),
136 	PINCTRL_PIN(49, "GPIO_49"),
137 	PINCTRL_PIN(50, "GPIO_50"),
138 	PINCTRL_PIN(51, "GPIO_51"),
139 	PINCTRL_PIN(52, "GPIO_52"),
140 	PINCTRL_PIN(53, "GPIO_53"),
141 	PINCTRL_PIN(54, "GPIO_54"),
142 	PINCTRL_PIN(55, "GPIO_55"),
143 	PINCTRL_PIN(56, "GPIO_56"),
144 	PINCTRL_PIN(57, "GPIO_57"),
145 	PINCTRL_PIN(58, "GPIO_58"),
146 	PINCTRL_PIN(59, "GPIO_59"),
147 	PINCTRL_PIN(60, "GPIO_60"),
148 	PINCTRL_PIN(61, "GPIO_61"),
149 	PINCTRL_PIN(62, "GPIO_62"),
150 	PINCTRL_PIN(63, "GPIO_63"),
151 	PINCTRL_PIN(64, "GPIO_64"),
152 	PINCTRL_PIN(65, "GPIO_65"),
153 	PINCTRL_PIN(66, "GPIO_66"),
154 	PINCTRL_PIN(67, "GPIO_67"),
155 	PINCTRL_PIN(68, "GPIO_68"),
156 	PINCTRL_PIN(69, "GPIO_69"),
157 	PINCTRL_PIN(70, "GPIO_70"),
158 	PINCTRL_PIN(71, "GPIO_71"),
159 	PINCTRL_PIN(72, "GPIO_72"),
160 	PINCTRL_PIN(73, "GPIO_73"),
161 	PINCTRL_PIN(74, "GPIO_74"),
162 	PINCTRL_PIN(75, "GPIO_75"),
163 	PINCTRL_PIN(76, "GPIO_76"),
164 	PINCTRL_PIN(77, "GPIO_77"),
165 	PINCTRL_PIN(78, "GPIO_78"),
166 	PINCTRL_PIN(79, "GPIO_79"),
167 	PINCTRL_PIN(80, "GPIO_80"),
168 	PINCTRL_PIN(81, "GPIO_81"),
169 	PINCTRL_PIN(82, "GPIO_82"),
170 	PINCTRL_PIN(83, "GPIO_83"),
171 	PINCTRL_PIN(84, "GPIO_84"),
172 	PINCTRL_PIN(85, "GPIO_85"),
173 	PINCTRL_PIN(86, "GPIO_86"),
174 	PINCTRL_PIN(87, "GPIO_87"),
175 	PINCTRL_PIN(88, "GPIO_88"),
176 	PINCTRL_PIN(89, "GPIO_89"),
177 	PINCTRL_PIN(90, "GPIO_90"),
178 	PINCTRL_PIN(91, "GPIO_91"),
179 	PINCTRL_PIN(92, "GPIO_92"),
180 	PINCTRL_PIN(93, "GPIO_93"),
181 	PINCTRL_PIN(94, "GPIO_94"),
182 	PINCTRL_PIN(95, "GPIO_95"),
183 	PINCTRL_PIN(96, "GPIO_96"),
184 	PINCTRL_PIN(97, "GPIO_97"),
185 	PINCTRL_PIN(98, "GPIO_98"),
186 	PINCTRL_PIN(99, "GPIO_99"),
187 	PINCTRL_PIN(100, "GPIO_100"),
188 	PINCTRL_PIN(101, "GPIO_101"),
189 	PINCTRL_PIN(102, "GPIO_102"),
190 	PINCTRL_PIN(103, "GPIO_103"),
191 	PINCTRL_PIN(104, "GPIO_104"),
192 	PINCTRL_PIN(105, "GPIO_105"),
193 	PINCTRL_PIN(106, "GPIO_106"),
194 	PINCTRL_PIN(107, "GPIO_107"),
195 	PINCTRL_PIN(108, "SDC1_RCLK"),
196 	PINCTRL_PIN(109, "SDC1_CLK"),
197 	PINCTRL_PIN(110, "SDC1_CMD"),
198 	PINCTRL_PIN(111, "SDC1_DATA"),
199 };
200 
201 #define DECLARE_MSM_GPIO_PINS(pin) \
202 	static const unsigned int gpio##pin##_pins[] = { pin }
203 DECLARE_MSM_GPIO_PINS(0);
204 DECLARE_MSM_GPIO_PINS(1);
205 DECLARE_MSM_GPIO_PINS(2);
206 DECLARE_MSM_GPIO_PINS(3);
207 DECLARE_MSM_GPIO_PINS(4);
208 DECLARE_MSM_GPIO_PINS(5);
209 DECLARE_MSM_GPIO_PINS(6);
210 DECLARE_MSM_GPIO_PINS(7);
211 DECLARE_MSM_GPIO_PINS(8);
212 DECLARE_MSM_GPIO_PINS(9);
213 DECLARE_MSM_GPIO_PINS(10);
214 DECLARE_MSM_GPIO_PINS(11);
215 DECLARE_MSM_GPIO_PINS(12);
216 DECLARE_MSM_GPIO_PINS(13);
217 DECLARE_MSM_GPIO_PINS(14);
218 DECLARE_MSM_GPIO_PINS(15);
219 DECLARE_MSM_GPIO_PINS(16);
220 DECLARE_MSM_GPIO_PINS(17);
221 DECLARE_MSM_GPIO_PINS(18);
222 DECLARE_MSM_GPIO_PINS(19);
223 DECLARE_MSM_GPIO_PINS(20);
224 DECLARE_MSM_GPIO_PINS(21);
225 DECLARE_MSM_GPIO_PINS(22);
226 DECLARE_MSM_GPIO_PINS(23);
227 DECLARE_MSM_GPIO_PINS(24);
228 DECLARE_MSM_GPIO_PINS(25);
229 DECLARE_MSM_GPIO_PINS(26);
230 DECLARE_MSM_GPIO_PINS(27);
231 DECLARE_MSM_GPIO_PINS(28);
232 DECLARE_MSM_GPIO_PINS(29);
233 DECLARE_MSM_GPIO_PINS(30);
234 DECLARE_MSM_GPIO_PINS(31);
235 DECLARE_MSM_GPIO_PINS(32);
236 DECLARE_MSM_GPIO_PINS(33);
237 DECLARE_MSM_GPIO_PINS(34);
238 DECLARE_MSM_GPIO_PINS(35);
239 DECLARE_MSM_GPIO_PINS(36);
240 DECLARE_MSM_GPIO_PINS(37);
241 DECLARE_MSM_GPIO_PINS(38);
242 DECLARE_MSM_GPIO_PINS(39);
243 DECLARE_MSM_GPIO_PINS(40);
244 DECLARE_MSM_GPIO_PINS(41);
245 DECLARE_MSM_GPIO_PINS(42);
246 DECLARE_MSM_GPIO_PINS(43);
247 DECLARE_MSM_GPIO_PINS(44);
248 DECLARE_MSM_GPIO_PINS(45);
249 DECLARE_MSM_GPIO_PINS(46);
250 DECLARE_MSM_GPIO_PINS(47);
251 DECLARE_MSM_GPIO_PINS(48);
252 DECLARE_MSM_GPIO_PINS(49);
253 DECLARE_MSM_GPIO_PINS(50);
254 DECLARE_MSM_GPIO_PINS(51);
255 DECLARE_MSM_GPIO_PINS(52);
256 DECLARE_MSM_GPIO_PINS(53);
257 DECLARE_MSM_GPIO_PINS(54);
258 DECLARE_MSM_GPIO_PINS(55);
259 DECLARE_MSM_GPIO_PINS(56);
260 DECLARE_MSM_GPIO_PINS(57);
261 DECLARE_MSM_GPIO_PINS(58);
262 DECLARE_MSM_GPIO_PINS(59);
263 DECLARE_MSM_GPIO_PINS(60);
264 DECLARE_MSM_GPIO_PINS(61);
265 DECLARE_MSM_GPIO_PINS(62);
266 DECLARE_MSM_GPIO_PINS(63);
267 DECLARE_MSM_GPIO_PINS(64);
268 DECLARE_MSM_GPIO_PINS(65);
269 DECLARE_MSM_GPIO_PINS(66);
270 DECLARE_MSM_GPIO_PINS(67);
271 DECLARE_MSM_GPIO_PINS(68);
272 DECLARE_MSM_GPIO_PINS(69);
273 DECLARE_MSM_GPIO_PINS(70);
274 DECLARE_MSM_GPIO_PINS(71);
275 DECLARE_MSM_GPIO_PINS(72);
276 DECLARE_MSM_GPIO_PINS(73);
277 DECLARE_MSM_GPIO_PINS(74);
278 DECLARE_MSM_GPIO_PINS(75);
279 DECLARE_MSM_GPIO_PINS(76);
280 DECLARE_MSM_GPIO_PINS(77);
281 DECLARE_MSM_GPIO_PINS(78);
282 DECLARE_MSM_GPIO_PINS(79);
283 DECLARE_MSM_GPIO_PINS(80);
284 DECLARE_MSM_GPIO_PINS(81);
285 DECLARE_MSM_GPIO_PINS(82);
286 DECLARE_MSM_GPIO_PINS(83);
287 DECLARE_MSM_GPIO_PINS(84);
288 DECLARE_MSM_GPIO_PINS(85);
289 DECLARE_MSM_GPIO_PINS(86);
290 DECLARE_MSM_GPIO_PINS(87);
291 DECLARE_MSM_GPIO_PINS(88);
292 DECLARE_MSM_GPIO_PINS(89);
293 DECLARE_MSM_GPIO_PINS(90);
294 DECLARE_MSM_GPIO_PINS(91);
295 DECLARE_MSM_GPIO_PINS(92);
296 DECLARE_MSM_GPIO_PINS(93);
297 DECLARE_MSM_GPIO_PINS(94);
298 DECLARE_MSM_GPIO_PINS(95);
299 DECLARE_MSM_GPIO_PINS(96);
300 DECLARE_MSM_GPIO_PINS(97);
301 DECLARE_MSM_GPIO_PINS(98);
302 DECLARE_MSM_GPIO_PINS(99);
303 DECLARE_MSM_GPIO_PINS(100);
304 DECLARE_MSM_GPIO_PINS(101);
305 DECLARE_MSM_GPIO_PINS(102);
306 DECLARE_MSM_GPIO_PINS(103);
307 DECLARE_MSM_GPIO_PINS(104);
308 DECLARE_MSM_GPIO_PINS(105);
309 DECLARE_MSM_GPIO_PINS(106);
310 DECLARE_MSM_GPIO_PINS(107);
311 
312 static const unsigned int sdc1_rclk_pins[] = { 108 };
313 static const unsigned int sdc1_clk_pins[] = { 109 };
314 static const unsigned int sdc1_cmd_pins[] = { 110 };
315 static const unsigned int sdc1_data_pins[] = { 111 };
316 
317 enum sdx55_functions {
318 	msm_mux_adsp_ext,
319 	msm_mux_atest,
320 	msm_mux_audio_ref,
321 	msm_mux_bimc_dte0,
322 	msm_mux_bimc_dte1,
323 	msm_mux_blsp_i2c1,
324 	msm_mux_blsp_i2c2,
325 	msm_mux_blsp_i2c3,
326 	msm_mux_blsp_i2c4,
327 	msm_mux_blsp_spi1,
328 	msm_mux_blsp_spi2,
329 	msm_mux_blsp_spi3,
330 	msm_mux_blsp_spi4,
331 	msm_mux_blsp_uart1,
332 	msm_mux_blsp_uart2,
333 	msm_mux_blsp_uart3,
334 	msm_mux_blsp_uart4,
335 	msm_mux_char_exec,
336 	msm_mux_coex_uart,
337 	msm_mux_coex_uart2,
338 	msm_mux_cri_trng,
339 	msm_mux_cri_trng0,
340 	msm_mux_cri_trng1,
341 	msm_mux_dbg_out,
342 	msm_mux_ddr_bist,
343 	msm_mux_ddr_pxi0,
344 	msm_mux_ebi0_wrcdc,
345 	msm_mux_ebi2_a,
346 	msm_mux_ebi2_lcd,
347 	msm_mux_emac_gcc0,
348 	msm_mux_emac_gcc1,
349 	msm_mux_emac_pps0,
350 	msm_mux_emac_pps1,
351 	msm_mux_ext_dbg,
352 	msm_mux_gcc_gp1,
353 	msm_mux_gcc_gp2,
354 	msm_mux_gcc_gp3,
355 	msm_mux_gcc_plltest,
356 	msm_mux_gpio,
357 	msm_mux_i2s_mclk,
358 	msm_mux_jitter_bist,
359 	msm_mux_ldo_en,
360 	msm_mux_ldo_update,
361 	msm_mux_mgpi_clk,
362 	msm_mux_m_voc,
363 	msm_mux_native_char,
364 	msm_mux_native_char0,
365 	msm_mux_native_char1,
366 	msm_mux_native_char2,
367 	msm_mux_native_char3,
368 	msm_mux_native_tsens,
369 	msm_mux_native_tsense,
370 	msm_mux_nav_gpio,
371 	msm_mux_pa_indicator,
372 	msm_mux_pcie_clkreq,
373 	msm_mux_pci_e,
374 	msm_mux_pll_bist,
375 	msm_mux_pll_ref,
376 	msm_mux_pll_test,
377 	msm_mux_pri_mi2s,
378 	msm_mux_prng_rosc,
379 	msm_mux_qdss_cti,
380 	msm_mux_qdss_gpio,
381 	msm_mux_qdss_stm,
382 	msm_mux_qlink0_en,
383 	msm_mux_qlink0_req,
384 	msm_mux_qlink0_wmss,
385 	msm_mux_qlink1_en,
386 	msm_mux_qlink1_req,
387 	msm_mux_qlink1_wmss,
388 	msm_mux_spmi_coex,
389 	msm_mux_sec_mi2s,
390 	msm_mux_spmi_vgi,
391 	msm_mux_tgu_ch0,
392 	msm_mux_uim1_clk,
393 	msm_mux_uim1_data,
394 	msm_mux_uim1_present,
395 	msm_mux_uim1_reset,
396 	msm_mux_uim2_clk,
397 	msm_mux_uim2_data,
398 	msm_mux_uim2_present,
399 	msm_mux_uim2_reset,
400 	msm_mux_usb2phy_ac,
401 	msm_mux_vsense_trigger,
402 	msm_mux__,
403 };
404 
405 static const char * const gpio_groups[] = {
406 	"gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
407 	"gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
408 	"gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
409 	"gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
410 	"gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
411 	"gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
412 	"gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
413 	"gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
414 	"gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
415 	"gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70",
416 	"gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77",
417 	"gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84",
418 	"gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91",
419 	"gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98",
420 	"gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104",
421 	"gpio105", "gpio106", "gpio107",
422 };
423 
424 static const char * const qdss_stm_groups[] = {
425 	"gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", "gpio12", "gpio13",
426 	"gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", "gpio22",
427 	"gpio23", "gpio44", "gpio45", "gpio52", "gpio53", "gpio56", "gpio57", "gpio61", "gpio62",
428 	"gpio63", "gpio64", "gpio65", "gpio66",
429 };
430 
431 static const char * const ddr_pxi0_groups[] = {
432 	"gpio45", "gpio46",
433 };
434 
435 static const char * const m_voc_groups[] = {
436 	"gpio46", "gpio48", "gpio49", "gpio59", "gpio60",
437 };
438 
439 static const char * const ddr_bist_groups[] = {
440 	"gpio46", "gpio47", "gpio48", "gpio49",
441 };
442 
443 static const char * const blsp_spi1_groups[] = {
444 	"gpio52", "gpio62", "gpio71", "gpio80", "gpio81", "gpio82", "gpio83",
445 };
446 
447 static const char * const pci_e_groups[] = {
448 	"gpio53",
449 };
450 
451 static const char * const tgu_ch0_groups[] = {
452 	"gpio55",
453 };
454 
455 static const char * const pcie_clkreq_groups[] = {
456 	"gpio56",
457 };
458 
459 static const char * const mgpi_clk_groups[] = {
460 	"gpio61", "gpio71",
461 };
462 
463 static const char * const i2s_mclk_groups[] = {
464 	"gpio62",
465 };
466 
467 static const char * const audio_ref_groups[] = {
468 	"gpio62",
469 };
470 
471 static const char * const ldo_update_groups[] = {
472 	"gpio62",
473 };
474 
475 static const char * const atest_groups[] = {
476 	"gpio63",  "gpio64", "gpio65", "gpio66", "gpio67",
477 };
478 
479 static const char * const uim1_data_groups[] = {
480 	"gpio67",
481 };
482 
483 static const char * const uim1_present_groups[] = {
484 	"gpio68",
485 };
486 
487 static const char * const uim1_reset_groups[] = {
488 	"gpio69",
489 };
490 
491 static const char * const uim1_clk_groups[] = {
492 	"gpio70",
493 };
494 
495 static const char * const qlink1_en_groups[] = {
496 	"gpio72",
497 };
498 
499 static const char * const qlink1_req_groups[] = {
500 	"gpio73",
501 };
502 
503 static const char * const qlink1_wmss_groups[] = {
504 	"gpio74",
505 };
506 
507 static const char * const coex_uart2_groups[] = {
508 	"gpio75", "gpio76",
509 };
510 
511 static const char * const spmi_vgi_groups[] = {
512 	"gpio78", "gpio79",
513 };
514 
515 static const char * const gcc_plltest_groups[] = {
516 	"gpio81", "gpio82",
517 };
518 
519 static const char * const usb2phy_ac_groups[] = {
520 	"gpio93",
521 };
522 
523 static const char * const emac_pps1_groups[] = {
524 	"gpio95",
525 };
526 
527 static const char * const emac_pps0_groups[] = {
528 	"gpio106",
529 };
530 
531 static const char * const uim2_data_groups[] = {
532 	"gpio0",
533 };
534 
535 static const char * const ebi0_wrcdc_groups[] = {
536 	"gpio0", "gpio2",
537 };
538 
539 static const char * const uim2_present_groups[] = {
540 	"gpio1",
541 };
542 
543 static const char * const blsp_uart1_groups[] = {
544 	"gpio0", "gpio1", "gpio2", "gpio3", "gpio20", "gpio21", "gpio22",
545 	"gpio23",
546 };
547 
548 static const char * const uim2_reset_groups[] = {
549 	"gpio2",
550 };
551 
552 static const char * const blsp_i2c1_groups[] = {
553 	"gpio2", "gpio3", "gpio82", "gpio83",
554 };
555 
556 static const char * const uim2_clk_groups[] = {
557 	"gpio3",
558 };
559 
560 static const char * const blsp_spi2_groups[] = {
561 	"gpio4", "gpio5", "gpio6", "gpio7", "gpio52", "gpio62", "gpio71",
562 };
563 
564 static const char * const blsp_uart2_groups[] = {
565 	"gpio4", "gpio5", "gpio6", "gpio7", "gpio63", "gpio64", "gpio65",
566 	"gpio66",
567 };
568 
569 static const char * const blsp_i2c2_groups[] = {
570 	"gpio6", "gpio7", "gpio65", "gpio66",
571 };
572 
573 static const char * const char_exec_groups[] = {
574 	"gpio6", "gpio7",
575 };
576 
577 static const char * const pri_mi2s_groups[] = {
578 	"gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
579 	"gpio15",
580 };
581 
582 static const char * const blsp_spi3_groups[] = {
583 	"gpio8", "gpio9", "gpio10", "gpio11", "gpio52", "gpio62", "gpio71",
584 };
585 
586 static const char * const blsp_uart3_groups[] = {
587 	"gpio8", "gpio9", "gpio10", "gpio11",
588 };
589 
590 static const char * const ext_dbg_groups[] = {
591 	"gpio8", "gpio9", "gpio10", "gpio11",
592 };
593 
594 static const char * const ldo_en_groups[] = {
595 	"gpio8",
596 };
597 
598 static const char * const blsp_i2c3_groups[] = {
599 	"gpio10", "gpio11",
600 };
601 
602 static const char * const gcc_gp3_groups[] = {
603 	"gpio11",
604 };
605 
606 static const char * const emac_gcc1_groups[] = {
607 	"gpio14",
608 };
609 
610 static const char * const bimc_dte0_groups[] = {
611 	"gpio14", "gpio59",
612 };
613 
614 static const char * const native_tsens_groups[] = {
615 	"gpio14",
616 };
617 
618 static const char * const vsense_trigger_groups[] = {
619 	"gpio14",
620 };
621 
622 static const char * const emac_gcc0_groups[] = {
623 	"gpio15",
624 };
625 
626 static const char * const bimc_dte1_groups[] = {
627 	"gpio15", "gpio61",
628 };
629 
630 static const char * const sec_mi2s_groups[] = {
631 	"gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", "gpio22",
632 	"gpio23",
633 };
634 
635 static const char * const blsp_spi4_groups[] = {
636 	"gpio16", "gpio17", "gpio18", "gpio19", "gpio52", "gpio62", "gpio71",
637 };
638 
639 static const char * const blsp_uart4_groups[] = {
640 	"gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", "gpio22",
641 	"gpio23",
642 };
643 
644 static const char * const qdss_cti_groups[] = {
645 	"gpio16", "gpio16", "gpio17", "gpio17", "gpio22", "gpio22", "gpio23",
646 	"gpio23", "gpio54", "gpio54", "gpio55", "gpio55", "gpio59", "gpio60",
647 	"gpio94", "gpio94", "gpio95", "gpio95",
648 };
649 
650 static const char * const blsp_i2c4_groups[] = {
651 	"gpio18", "gpio19", "gpio78", "gpio79",
652 };
653 
654 static const char * const gcc_gp1_groups[] = {
655 	"gpio18",
656 };
657 
658 static const char * const jitter_bist_groups[] = {
659 	"gpio19",
660 };
661 
662 static const char * const gcc_gp2_groups[] = {
663 	"gpio19",
664 };
665 
666 static const char * const ebi2_a_groups[] = {
667 	"gpio20",
668 };
669 
670 static const char * const ebi2_lcd_groups[] = {
671 	"gpio21", "gpio22", "gpio23",
672 };
673 
674 static const char * const pll_bist_groups[] = {
675 	"gpio22",
676 };
677 
678 static const char * const adsp_ext_groups[] = {
679 	"gpio24", "gpio25",
680 };
681 
682 static const char * const native_char_groups[] = {
683 	"gpio26",
684 };
685 
686 static const char * const qlink0_wmss_groups[] = {
687 	"gpio28",
688 };
689 
690 static const char * const native_char3_groups[] = {
691 	"gpio28",
692 };
693 
694 static const char * const native_char2_groups[] = {
695 	"gpio29",
696 };
697 
698 static const char * const native_tsense_groups[] = {
699 	"gpio29",
700 };
701 
702 static const char * const nav_gpio_groups[] = {
703 	"gpio31", "gpio32", "gpio76",
704 };
705 
706 static const char * const pll_ref_groups[] = {
707 	"gpio32",
708 };
709 
710 static const char * const pa_indicator_groups[] = {
711 	"gpio33",
712 };
713 
714 static const char * const native_char0_groups[] = {
715 	"gpio33",
716 };
717 
718 static const char * const qlink0_en_groups[] = {
719 	"gpio34",
720 };
721 
722 static const char * const qlink0_req_groups[] = {
723 	"gpio35",
724 };
725 
726 static const char * const pll_test_groups[] = {
727 	"gpio35",
728 };
729 
730 static const char * const cri_trng_groups[] = {
731 	"gpio36",
732 };
733 
734 static const char * const dbg_out_groups[] = {
735 	"gpio36",
736 };
737 
738 static const char * const prng_rosc_groups[] = {
739 	"gpio38",
740 };
741 
742 static const char * const cri_trng0_groups[] = {
743 	"gpio40",
744 };
745 
746 static const char * const cri_trng1_groups[] = {
747 	"gpio41",
748 };
749 
750 static const char * const qdss_gpio_groups[] = {
751 	"gpio4", "gpio5", "gpio6", "gpio7",
752 	"gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19",
753 	"gpio42", "gpio61", "gpio63", "gpio64", "gpio65", "gpio66",
754 };
755 
756 static const char * const native_char1_groups[] = {
757 	"gpio42",
758 };
759 
760 static const char * const coex_uart_groups[] = {
761 	"gpio44", "gpio45",
762 };
763 
764 static const char * const spmi_coex_groups[] = {
765 	"gpio44", "gpio45",
766 };
767 
768 static const struct msm_function sdx55_functions[] = {
769 	FUNCTION(adsp_ext),
770 	FUNCTION(atest),
771 	FUNCTION(audio_ref),
772 	FUNCTION(bimc_dte0),
773 	FUNCTION(bimc_dte1),
774 	FUNCTION(blsp_i2c1),
775 	FUNCTION(blsp_i2c2),
776 	FUNCTION(blsp_i2c3),
777 	FUNCTION(blsp_i2c4),
778 	FUNCTION(blsp_spi1),
779 	FUNCTION(blsp_spi2),
780 	FUNCTION(blsp_spi3),
781 	FUNCTION(blsp_spi4),
782 	FUNCTION(blsp_uart1),
783 	FUNCTION(blsp_uart2),
784 	FUNCTION(blsp_uart3),
785 	FUNCTION(blsp_uart4),
786 	FUNCTION(char_exec),
787 	FUNCTION(coex_uart),
788 	FUNCTION(coex_uart2),
789 	FUNCTION(cri_trng),
790 	FUNCTION(cri_trng0),
791 	FUNCTION(cri_trng1),
792 	FUNCTION(dbg_out),
793 	FUNCTION(ddr_bist),
794 	FUNCTION(ddr_pxi0),
795 	FUNCTION(ebi0_wrcdc),
796 	FUNCTION(ebi2_a),
797 	FUNCTION(ebi2_lcd),
798 	FUNCTION(emac_gcc0),
799 	FUNCTION(emac_gcc1),
800 	FUNCTION(emac_pps0),
801 	FUNCTION(emac_pps1),
802 	FUNCTION(ext_dbg),
803 	FUNCTION(gcc_gp1),
804 	FUNCTION(gcc_gp2),
805 	FUNCTION(gcc_gp3),
806 	FUNCTION(gcc_plltest),
807 	FUNCTION(gpio),
808 	FUNCTION(i2s_mclk),
809 	FUNCTION(jitter_bist),
810 	FUNCTION(ldo_en),
811 	FUNCTION(ldo_update),
812 	FUNCTION(mgpi_clk),
813 	FUNCTION(m_voc),
814 	FUNCTION(native_char),
815 	FUNCTION(native_char0),
816 	FUNCTION(native_char1),
817 	FUNCTION(native_char2),
818 	FUNCTION(native_char3),
819 	FUNCTION(native_tsens),
820 	FUNCTION(native_tsense),
821 	FUNCTION(nav_gpio),
822 	FUNCTION(pa_indicator),
823 	FUNCTION(pcie_clkreq),
824 	FUNCTION(pci_e),
825 	FUNCTION(pll_bist),
826 	FUNCTION(pll_ref),
827 	FUNCTION(pll_test),
828 	FUNCTION(pri_mi2s),
829 	FUNCTION(prng_rosc),
830 	FUNCTION(qdss_cti),
831 	FUNCTION(qdss_gpio),
832 	FUNCTION(qdss_stm),
833 	FUNCTION(qlink0_en),
834 	FUNCTION(qlink0_req),
835 	FUNCTION(qlink0_wmss),
836 	FUNCTION(qlink1_en),
837 	FUNCTION(qlink1_req),
838 	FUNCTION(qlink1_wmss),
839 	FUNCTION(spmi_coex),
840 	FUNCTION(sec_mi2s),
841 	FUNCTION(spmi_vgi),
842 	FUNCTION(tgu_ch0),
843 	FUNCTION(uim1_clk),
844 	FUNCTION(uim1_data),
845 	FUNCTION(uim1_present),
846 	FUNCTION(uim1_reset),
847 	FUNCTION(uim2_clk),
848 	FUNCTION(uim2_data),
849 	FUNCTION(uim2_present),
850 	FUNCTION(uim2_reset),
851 	FUNCTION(usb2phy_ac),
852 	FUNCTION(vsense_trigger),
853 };
854 
855 /* Every pin is maintained as a single group, and missing or non-existing pin
856  * would be maintained as dummy group to synchronize pin group index with
857  * pin descriptor registered with pinctrl core.
858  * Clients would not be able to request these dummy pin groups.
859  */
860 static const struct msm_pingroup sdx55_groups[] = {
861 	[0] = PINGROUP(0, uim2_data, blsp_uart1, qdss_stm, ebi0_wrcdc, _, _, _, _, _),
862 	[1] = PINGROUP(1, uim2_present, blsp_uart1, qdss_stm, _, _, _, _, _, _),
863 	[2] = PINGROUP(2, uim2_reset, blsp_uart1, blsp_i2c1, qdss_stm, ebi0_wrcdc, _, _, _, _),
864 	[3] = PINGROUP(3, uim2_clk, blsp_uart1, blsp_i2c1, qdss_stm, _, _, _, _, _),
865 	[4] = PINGROUP(4, blsp_spi2, blsp_uart2, _, qdss_stm, qdss_gpio, _, _, _, _),
866 	[5] = PINGROUP(5, blsp_spi2, blsp_uart2, _, qdss_stm, qdss_gpio, _, _, _, _),
867 	[6] = PINGROUP(6, blsp_spi2, blsp_uart2, blsp_i2c2, char_exec, _, qdss_stm, qdss_gpio, _, _),
868 	[7] = PINGROUP(7, blsp_spi2, blsp_uart2, blsp_i2c2, char_exec, _, qdss_stm, qdss_gpio, _, _),
869 	[8] = PINGROUP(8, pri_mi2s, blsp_spi3, blsp_uart3, ext_dbg, ldo_en, _, _, _, _),
870 	[9] = PINGROUP(9, pri_mi2s, blsp_spi3, blsp_uart3, ext_dbg, _, _, _, _, _),
871 	[10] = PINGROUP(10, pri_mi2s, blsp_spi3, blsp_uart3, blsp_i2c3, ext_dbg, _, _, _, _),
872 	[11] = PINGROUP(11, pri_mi2s, blsp_spi3, blsp_uart3, blsp_i2c3, ext_dbg, gcc_gp3, _, _, _),
873 	[12] = PINGROUP(12, pri_mi2s, _, qdss_stm, qdss_gpio, _, _, _, _, _),
874 	[13] = PINGROUP(13, pri_mi2s, _, qdss_stm, qdss_gpio, _, _, _, _, _),
875 	[14] = PINGROUP(14, pri_mi2s, emac_gcc1, _, _, qdss_stm, qdss_gpio, bimc_dte0, native_tsens, vsense_trigger),
876 	[15] = PINGROUP(15, pri_mi2s, emac_gcc0, _, _, qdss_stm, qdss_gpio, bimc_dte1, _, _),
877 	[16] = PINGROUP(16, sec_mi2s, blsp_spi4, blsp_uart4, qdss_cti, qdss_cti, _, _, qdss_stm, qdss_gpio),
878 	[17] = PINGROUP(17, sec_mi2s, blsp_spi4, blsp_uart4, qdss_cti, qdss_cti, _, qdss_stm, qdss_gpio, _),
879 	[18] = PINGROUP(18, sec_mi2s, blsp_spi4, blsp_uart4, blsp_i2c4, gcc_gp1, qdss_stm, qdss_gpio, _, _),
880 	[19] = PINGROUP(19, sec_mi2s, blsp_spi4, blsp_uart4, blsp_i2c4, jitter_bist, gcc_gp2, _, qdss_stm, qdss_gpio),
881 	[20] = PINGROUP(20, sec_mi2s, ebi2_a, blsp_uart1, blsp_uart4, qdss_stm, _, _, _, _),
882 	[21] = PINGROUP(21, sec_mi2s, ebi2_lcd, blsp_uart1, blsp_uart4, _, qdss_stm, _, _, _),
883 	[22] = PINGROUP(22, sec_mi2s, ebi2_lcd, blsp_uart1, qdss_cti, qdss_cti, blsp_uart4, pll_bist, _, qdss_stm),
884 	[23] = PINGROUP(23, sec_mi2s, ebi2_lcd, qdss_cti, qdss_cti, blsp_uart1, blsp_uart4, qdss_stm, _, _),
885 	[24] = PINGROUP(24, adsp_ext, _, _, _, _, _, _, _, _),
886 	[25] = PINGROUP(25, adsp_ext, _, _, _, _, _, _, _, _),
887 	[26] = PINGROUP(26, _, _, _, native_char, _, _, _, _, _),
888 	[27] = PINGROUP(27, _, _, _, _, _, _, _, _, _),
889 	[28] = PINGROUP(28, qlink0_wmss, _, native_char3, _, _, _, _, _, _),
890 	[29] = PINGROUP(29, _, _, _, native_char2, native_tsense, _, _, _, _),
891 	[30] = PINGROUP(30, _, _, _, _, _, _, _, _, _),
892 	[31] = PINGROUP(31, nav_gpio, _, _, _, _, _, _, _, _),
893 	[32] = PINGROUP(32, nav_gpio, pll_ref, _, _, _, _, _, _, _),
894 	[33] = PINGROUP(33, _, pa_indicator, native_char0, _, _, _, _, _, _),
895 	[34] = PINGROUP(34, qlink0_en, _, _, _, _, _, _, _, _),
896 	[35] = PINGROUP(35, qlink0_req, pll_test, _, _, _, _, _, _, _),
897 	[36] = PINGROUP(36, _, _, cri_trng, dbg_out, _, _, _, _, _),
898 	[37] = PINGROUP(37, _, _, _, _, _, _, _, _, _),
899 	[38] = PINGROUP(38, _, _, prng_rosc, _, _, _, _, _, _),
900 	[39] = PINGROUP(39, _, _, _, _, _, _, _, _, _),
901 	[40] = PINGROUP(40, _, _, cri_trng0, _, _, _, _, _, _),
902 	[41] = PINGROUP(41, _, _, cri_trng1, _, _, _, _, _, _),
903 	[42] = PINGROUP(42, _, qdss_gpio, native_char1, _, _, _, _, _, _),
904 	[43] = PINGROUP(43, _, _, _, _, _, _, _, _, _),
905 	[44] = PINGROUP(44, coex_uart, spmi_coex, _, qdss_stm, _, _, _, _, _),
906 	[45] = PINGROUP(45, coex_uart, spmi_coex, qdss_stm, ddr_pxi0, _, _, _, _, _),
907 	[46] = PINGROUP(46, m_voc, ddr_bist, ddr_pxi0, _, _, _, _, _, _),
908 	[47] = PINGROUP(47, ddr_bist, _, _, _, _, _, _, _, _),
909 	[48] = PINGROUP(48, m_voc, ddr_bist, _, _, _, _, _, _, _),
910 	[49] = PINGROUP(49, m_voc, ddr_bist, _, _, _, _, _, _, _),
911 	[50] = PINGROUP(50, _, _, _, _, _, _, _, _, _),
912 	[51] = PINGROUP(51, _, _, _, _, _, _, _, _, _),
913 	[52] = PINGROUP(52, blsp_spi2, blsp_spi1, blsp_spi3, blsp_spi4, _, _, qdss_stm, _, _),
914 	[53] = PINGROUP(53, pci_e, _, _, qdss_stm, _, _, _, _, _),
915 	[54] = PINGROUP(54, qdss_cti, qdss_cti, _, _, _, _, _, _, _),
916 	[55] = PINGROUP(55, qdss_cti, qdss_cti, tgu_ch0, _, _, _, _, _, _),
917 	[56] = PINGROUP(56, pcie_clkreq, _, qdss_stm, _, _, _, _, _, _),
918 	[57] = PINGROUP(57, _, qdss_stm, _, _, _, _, _, _, _),
919 	[58] = PINGROUP(58, _, _, _, _, _, _, _, _, _),
920 	[59] = PINGROUP(59, qdss_cti, m_voc, bimc_dte0, _, _, _, _, _, _),
921 	[60] = PINGROUP(60, qdss_cti, _, m_voc, _, _, _, _, _, _),
922 	[61] = PINGROUP(61, mgpi_clk, qdss_stm, qdss_gpio, bimc_dte1, _, _, _, _, _),
923 	[62] = PINGROUP(62, i2s_mclk, audio_ref, blsp_spi1, blsp_spi2, blsp_spi3, blsp_spi4, ldo_update, qdss_stm, _),
924 	[63] = PINGROUP(63, blsp_uart2, _, qdss_stm, qdss_gpio, atest, _, _, _, _),
925 	[64] = PINGROUP(64, blsp_uart2, qdss_stm, qdss_gpio, atest, _, _, _, _, _),
926 	[65] = PINGROUP(65, blsp_uart2, blsp_i2c2, _, qdss_stm, qdss_gpio, atest, _, _, _),
927 	[66] = PINGROUP(66, blsp_uart2, blsp_i2c2, qdss_stm, qdss_gpio, atest, _, _, _, _),
928 	[67] = PINGROUP(67, uim1_data, atest, _, _, _, _, _, _, _),
929 	[68] = PINGROUP(68, uim1_present, _, _, _, _, _, _, _, _),
930 	[69] = PINGROUP(69, uim1_reset, _, _, _, _, _, _, _, _),
931 	[70] = PINGROUP(70, uim1_clk, _, _, _, _, _, _, _, _),
932 	[71] = PINGROUP(71, mgpi_clk, blsp_spi1, blsp_spi2, blsp_spi3, blsp_spi4, _, _, _, _),
933 	[72] = PINGROUP(72, qlink1_en, _, _, _, _, _, _, _, _),
934 	[73] = PINGROUP(73, qlink1_req, _, _, _, _, _, _, _, _),
935 	[74] = PINGROUP(74, qlink1_wmss, _, _, _, _, _, _, _, _),
936 	[75] = PINGROUP(75, coex_uart2, _, _, _, _, _, _, _, _),
937 	[76] = PINGROUP(76, coex_uart2, nav_gpio, _, _, _, _, _, _, _),
938 	[77] = PINGROUP(77, _, _, _, _, _, _, _, _, _),
939 	[78] = PINGROUP(78, spmi_vgi, blsp_i2c4, _, _, _, _, _, _, _),
940 	[79] = PINGROUP(79, spmi_vgi, blsp_i2c4, _, _, _, _, _, _, _),
941 	[80] = PINGROUP(80, _, blsp_spi1, _, _, _, _, _, _, _),
942 	[81] = PINGROUP(81, _, blsp_spi1, _, gcc_plltest, _, _, _, _, _),
943 	[82] = PINGROUP(82, _, blsp_spi1, _, blsp_i2c1, gcc_plltest, _, _, _, _),
944 	[83] = PINGROUP(83, _, blsp_spi1, _, blsp_i2c1, _, _, _, _, _),
945 	[84] = PINGROUP(84, _, _, _, _, _, _, _, _, _),
946 	[85] = PINGROUP(85, _, _, _, _, _, _, _, _, _),
947 	[86] = PINGROUP(86, _, _, _, _, _, _, _, _, _),
948 	[87] = PINGROUP(87, _, _, _, _, _, _, _, _, _),
949 	[88] = PINGROUP(88, _, _, _, _, _, _, _, _, _),
950 	[89] = PINGROUP(89, _, _, _, _, _, _, _, _, _),
951 	[90] = PINGROUP(90, _, _, _, _, _, _, _, _, _),
952 	[91] = PINGROUP(91, _, _, _, _, _, _, _, _, _),
953 	[92] = PINGROUP(92, _, _, _, _, _, _, _, _, _),
954 	[93] = PINGROUP(93, _, _, usb2phy_ac, _, _, _, _, _, _),
955 	[94] = PINGROUP(94, qdss_cti, qdss_cti, _, _, _, _, _, _, _),
956 	[95] = PINGROUP(95, qdss_cti, qdss_cti, emac_pps1, _, _, _, _, _, _),
957 	[96] = PINGROUP(96, _, _, _, _, _, _, _, _, _),
958 	[97] = PINGROUP(97, _, _, _, _, _, _, _, _, _),
959 	[98] = PINGROUP(98, _, _, _, _, _, _, _, _, _),
960 	[99] = PINGROUP(99, _, _, _, _, _, _, _, _, _),
961 	[100] = PINGROUP(100, _, _, _, _, _, _, _, _, _),
962 	[101] = PINGROUP(101, _, _, _, _, _, _, _, _, _),
963 	[102] = PINGROUP(102, _, _, _, _, _, _, _, _, _),
964 	[103] = PINGROUP(103, _, _, _, _, _, _, _, _, _),
965 	[104] = PINGROUP(104, _, _, _, _, _, _, _, _, _),
966 	[105] = PINGROUP(105, _, _, _, _, _, _, _, _, _),
967 	[106] = PINGROUP(106, emac_pps0, _, _, _, _, _, _, _, _),
968 	[107] = PINGROUP(107, _, _, _, _, _, _, _, _, _),
969 	[109] = SDC_PINGROUP(sdc1_rclk, 0x9a000, 15, 0),
970 	[110] = SDC_PINGROUP(sdc1_clk, 0x9a000, 13, 6),
971 	[111] = SDC_PINGROUP(sdc1_cmd, 0x9a000, 11, 3),
972 	[112] = SDC_PINGROUP(sdc1_data, 0x9a000, 9, 0),
973 };
974 
975 static const struct msm_pinctrl_soc_data sdx55_pinctrl = {
976 	.pins = sdx55_pins,
977 	.npins = ARRAY_SIZE(sdx55_pins),
978 	.functions = sdx55_functions,
979 	.nfunctions = ARRAY_SIZE(sdx55_functions),
980 	.groups = sdx55_groups,
981 	.ngroups = ARRAY_SIZE(sdx55_groups),
982 	.ngpios = 108,
983 };
984 
985 static int sdx55_pinctrl_probe(struct platform_device *pdev)
986 {
987 	return msm_pinctrl_probe(pdev, &sdx55_pinctrl);
988 }
989 
990 static const struct of_device_id sdx55_pinctrl_of_match[] = {
991 	{ .compatible = "qcom,sdx55-pinctrl", },
992 	{ },
993 };
994 
995 static struct platform_driver sdx55_pinctrl_driver = {
996 	.driver = {
997 		.name = "sdx55-pinctrl",
998 		.of_match_table = sdx55_pinctrl_of_match,
999 	},
1000 	.probe = sdx55_pinctrl_probe,
1001 	.remove = msm_pinctrl_remove,
1002 };
1003 
1004 static int __init sdx55_pinctrl_init(void)
1005 {
1006 	return platform_driver_register(&sdx55_pinctrl_driver);
1007 }
1008 arch_initcall(sdx55_pinctrl_init);
1009 
1010 static void __exit sdx55_pinctrl_exit(void)
1011 {
1012 	platform_driver_unregister(&sdx55_pinctrl_driver);
1013 }
1014 module_exit(sdx55_pinctrl_exit);
1015 
1016 MODULE_DESCRIPTION("QTI sdx55 pinctrl driver");
1017 MODULE_LICENSE("GPL v2");
1018 MODULE_DEVICE_TABLE(of, sdx55_pinctrl_of_match);
1019