1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
4  * Copyright (c) 2022, Richard Acayan. All rights reserved.
5  */
6 
7 #include <linux/module.h>
8 #include <linux/of.h>
9 #include <linux/platform_device.h>
10 #include <linux/pinctrl/pinctrl.h>
11 
12 #include "pinctrl-msm.h"
13 
14 #define FUNCTION(fname)					\
15 	[msm_mux_##fname] = {				\
16 		.name = #fname,				\
17 		.groups = fname##_groups,		\
18 		.ngroups = ARRAY_SIZE(fname##_groups),	\
19 	}
20 
21 #define NORTH	0x00500000
22 #define SOUTH	0x00900000
23 #define WEST	0x00100000
24 
25 #define REG_SIZE 0x1000
26 #define PINGROUP(id, base, f1, f2, f3, f4, f5, f6, f7, f8, f9)	\
27 	{						\
28 		.name = "gpio" #id,			\
29 		.pins = gpio##id##_pins,		\
30 		.npins = ARRAY_SIZE(gpio##id##_pins),	\
31 		.funcs = (int[]){			\
32 			msm_mux_gpio, /* gpio mode */	\
33 			msm_mux_##f1,			\
34 			msm_mux_##f2,			\
35 			msm_mux_##f3,			\
36 			msm_mux_##f4,			\
37 			msm_mux_##f5,			\
38 			msm_mux_##f6,			\
39 			msm_mux_##f7,			\
40 			msm_mux_##f8,			\
41 			msm_mux_##f9			\
42 		},					\
43 		.nfuncs = 10,				\
44 		.ctl_reg = base + REG_SIZE * id,		\
45 		.io_reg = base + 0x4 + REG_SIZE * id,		\
46 		.intr_cfg_reg = base + 0x8 + REG_SIZE * id,	\
47 		.intr_status_reg = base + 0xc + REG_SIZE * id,	\
48 		.intr_target_reg = base + 0x8 + REG_SIZE * id,	\
49 		.mux_bit = 2,			\
50 		.pull_bit = 0,			\
51 		.drv_bit = 6,			\
52 		.oe_bit = 9,			\
53 		.in_bit = 0,			\
54 		.out_bit = 1,			\
55 		.intr_enable_bit = 0,		\
56 		.intr_status_bit = 0,		\
57 		.intr_target_bit = 5,		\
58 		.intr_target_kpss_val = 3,	\
59 		.intr_raw_status_bit = 4,	\
60 		.intr_polarity_bit = 1,		\
61 		.intr_detection_bit = 2,	\
62 		.intr_detection_width = 2,	\
63 	}
64 
65 /*
66  * A dummy pingroup is a pin group that cannot be assigned a function and has
67  * no registers to control or monitor it.
68  */
69 #define PINGROUP_DUMMY(id)				\
70 	{						\
71 		.name = "gpio" #id,			\
72 		.pins = gpio##id##_pins,		\
73 		.npins = ARRAY_SIZE(gpio##id##_pins),	\
74 		.ctl_reg = 0,				\
75 		.io_reg = 0,				\
76 		.intr_cfg_reg = 0,			\
77 		.intr_status_reg = 0,			\
78 		.intr_target_reg = 0,			\
79 		.mux_bit = -1,				\
80 		.pull_bit = -1,				\
81 		.drv_bit = -1,				\
82 		.oe_bit = -1,				\
83 		.in_bit = -1,				\
84 		.out_bit = -1,				\
85 		.intr_enable_bit = -1,			\
86 		.intr_status_bit = -1,			\
87 		.intr_target_bit = -1,			\
88 		.intr_raw_status_bit = -1,		\
89 		.intr_polarity_bit = -1,		\
90 		.intr_detection_bit = -1,		\
91 		.intr_detection_width = -1,		\
92 	}
93 
94 #define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv)	\
95 	{						\
96 		.name = #pg_name,			\
97 		.pins = pg_name##_pins,			\
98 		.npins = ARRAY_SIZE(pg_name##_pins),	\
99 		.ctl_reg = ctl,				\
100 		.io_reg = 0,				\
101 		.intr_cfg_reg = 0,			\
102 		.intr_status_reg = 0,			\
103 		.intr_target_reg = 0,			\
104 		.mux_bit = -1,				\
105 		.pull_bit = pull,			\
106 		.drv_bit = drv,				\
107 		.oe_bit = -1,				\
108 		.in_bit = -1,				\
109 		.out_bit = -1,				\
110 		.intr_enable_bit = -1,			\
111 		.intr_status_bit = -1,			\
112 		.intr_target_bit = -1,			\
113 		.intr_raw_status_bit = -1,		\
114 		.intr_polarity_bit = -1,		\
115 		.intr_detection_bit = -1,		\
116 		.intr_detection_width = -1,		\
117 	}
118 
119 #define UFS_RESET(pg_name, offset)				\
120 	{						\
121 		.name = #pg_name,			\
122 		.pins = pg_name##_pins,			\
123 		.npins = ARRAY_SIZE(pg_name##_pins),	\
124 		.ctl_reg = offset,			\
125 		.io_reg = offset + 0x4,			\
126 		.intr_cfg_reg = 0,			\
127 		.intr_status_reg = 0,			\
128 		.intr_target_reg = 0,			\
129 		.mux_bit = -1,				\
130 		.pull_bit = 3,				\
131 		.drv_bit = 0,				\
132 		.oe_bit = -1,				\
133 		.in_bit = -1,				\
134 		.out_bit = 0,				\
135 		.intr_enable_bit = -1,			\
136 		.intr_status_bit = -1,			\
137 		.intr_target_bit = -1,			\
138 		.intr_raw_status_bit = -1,		\
139 		.intr_polarity_bit = -1,		\
140 		.intr_detection_bit = -1,		\
141 		.intr_detection_width = -1,		\
142 	}
143 
144 static const struct pinctrl_pin_desc sdm670_pins[] = {
145 	PINCTRL_PIN(0, "GPIO_0"),
146 	PINCTRL_PIN(1, "GPIO_1"),
147 	PINCTRL_PIN(2, "GPIO_2"),
148 	PINCTRL_PIN(3, "GPIO_3"),
149 	PINCTRL_PIN(4, "GPIO_4"),
150 	PINCTRL_PIN(5, "GPIO_5"),
151 	PINCTRL_PIN(6, "GPIO_6"),
152 	PINCTRL_PIN(7, "GPIO_7"),
153 	PINCTRL_PIN(8, "GPIO_8"),
154 	PINCTRL_PIN(9, "GPIO_9"),
155 	PINCTRL_PIN(10, "GPIO_10"),
156 	PINCTRL_PIN(11, "GPIO_11"),
157 	PINCTRL_PIN(12, "GPIO_12"),
158 	PINCTRL_PIN(13, "GPIO_13"),
159 	PINCTRL_PIN(14, "GPIO_14"),
160 	PINCTRL_PIN(15, "GPIO_15"),
161 	PINCTRL_PIN(16, "GPIO_16"),
162 	PINCTRL_PIN(17, "GPIO_17"),
163 	PINCTRL_PIN(18, "GPIO_18"),
164 	PINCTRL_PIN(19, "GPIO_19"),
165 	PINCTRL_PIN(20, "GPIO_20"),
166 	PINCTRL_PIN(21, "GPIO_21"),
167 	PINCTRL_PIN(22, "GPIO_22"),
168 	PINCTRL_PIN(23, "GPIO_23"),
169 	PINCTRL_PIN(24, "GPIO_24"),
170 	PINCTRL_PIN(25, "GPIO_25"),
171 	PINCTRL_PIN(26, "GPIO_26"),
172 	PINCTRL_PIN(27, "GPIO_27"),
173 	PINCTRL_PIN(28, "GPIO_28"),
174 	PINCTRL_PIN(29, "GPIO_29"),
175 	PINCTRL_PIN(30, "GPIO_30"),
176 	PINCTRL_PIN(31, "GPIO_31"),
177 	PINCTRL_PIN(32, "GPIO_32"),
178 	PINCTRL_PIN(33, "GPIO_33"),
179 	PINCTRL_PIN(34, "GPIO_34"),
180 	PINCTRL_PIN(35, "GPIO_35"),
181 	PINCTRL_PIN(36, "GPIO_36"),
182 	PINCTRL_PIN(37, "GPIO_37"),
183 	PINCTRL_PIN(38, "GPIO_38"),
184 	PINCTRL_PIN(39, "GPIO_39"),
185 	PINCTRL_PIN(40, "GPIO_40"),
186 	PINCTRL_PIN(41, "GPIO_41"),
187 	PINCTRL_PIN(42, "GPIO_42"),
188 	PINCTRL_PIN(43, "GPIO_43"),
189 	PINCTRL_PIN(44, "GPIO_44"),
190 	PINCTRL_PIN(45, "GPIO_45"),
191 	PINCTRL_PIN(46, "GPIO_46"),
192 	PINCTRL_PIN(47, "GPIO_47"),
193 	PINCTRL_PIN(48, "GPIO_48"),
194 	PINCTRL_PIN(49, "GPIO_49"),
195 	PINCTRL_PIN(50, "GPIO_50"),
196 	PINCTRL_PIN(51, "GPIO_51"),
197 	PINCTRL_PIN(52, "GPIO_52"),
198 	PINCTRL_PIN(53, "GPIO_53"),
199 	PINCTRL_PIN(54, "GPIO_54"),
200 	PINCTRL_PIN(55, "GPIO_55"),
201 	PINCTRL_PIN(56, "GPIO_56"),
202 	PINCTRL_PIN(57, "GPIO_57"),
203 	PINCTRL_PIN(58, "GPIO_58"),
204 	PINCTRL_PIN(59, "GPIO_59"),
205 	PINCTRL_PIN(60, "GPIO_60"),
206 	PINCTRL_PIN(61, "GPIO_61"),
207 	PINCTRL_PIN(62, "GPIO_62"),
208 	PINCTRL_PIN(63, "GPIO_63"),
209 	PINCTRL_PIN(64, "GPIO_64"),
210 	PINCTRL_PIN(65, "GPIO_65"),
211 	PINCTRL_PIN(66, "GPIO_66"),
212 	PINCTRL_PIN(67, "GPIO_67"),
213 	PINCTRL_PIN(68, "GPIO_68"),
214 	PINCTRL_PIN(69, "GPIO_69"),
215 	PINCTRL_PIN(70, "GPIO_70"),
216 	PINCTRL_PIN(71, "GPIO_71"),
217 	PINCTRL_PIN(72, "GPIO_72"),
218 	PINCTRL_PIN(73, "GPIO_73"),
219 	PINCTRL_PIN(74, "GPIO_74"),
220 	PINCTRL_PIN(75, "GPIO_75"),
221 	PINCTRL_PIN(76, "GPIO_76"),
222 	PINCTRL_PIN(77, "GPIO_77"),
223 	PINCTRL_PIN(78, "GPIO_78"),
224 	PINCTRL_PIN(79, "GPIO_79"),
225 	PINCTRL_PIN(80, "GPIO_80"),
226 	PINCTRL_PIN(81, "GPIO_81"),
227 	PINCTRL_PIN(82, "GPIO_82"),
228 	PINCTRL_PIN(83, "GPIO_83"),
229 	PINCTRL_PIN(84, "GPIO_84"),
230 	PINCTRL_PIN(85, "GPIO_85"),
231 	PINCTRL_PIN(86, "GPIO_86"),
232 	PINCTRL_PIN(87, "GPIO_87"),
233 	PINCTRL_PIN(88, "GPIO_88"),
234 	PINCTRL_PIN(89, "GPIO_89"),
235 	PINCTRL_PIN(90, "GPIO_90"),
236 	PINCTRL_PIN(91, "GPIO_91"),
237 	PINCTRL_PIN(92, "GPIO_92"),
238 	PINCTRL_PIN(93, "GPIO_93"),
239 	PINCTRL_PIN(94, "GPIO_94"),
240 	PINCTRL_PIN(95, "GPIO_95"),
241 	PINCTRL_PIN(96, "GPIO_96"),
242 	PINCTRL_PIN(97, "GPIO_97"),
243 	PINCTRL_PIN(98, "GPIO_98"),
244 	PINCTRL_PIN(99, "GPIO_99"),
245 	PINCTRL_PIN(100, "GPIO_100"),
246 	PINCTRL_PIN(101, "GPIO_101"),
247 	PINCTRL_PIN(102, "GPIO_102"),
248 	PINCTRL_PIN(103, "GPIO_103"),
249 	PINCTRL_PIN(104, "GPIO_104"),
250 	PINCTRL_PIN(105, "GPIO_105"),
251 	PINCTRL_PIN(106, "GPIO_106"),
252 	PINCTRL_PIN(107, "GPIO_107"),
253 	PINCTRL_PIN(108, "GPIO_108"),
254 	PINCTRL_PIN(109, "GPIO_109"),
255 	PINCTRL_PIN(110, "GPIO_110"),
256 	PINCTRL_PIN(111, "GPIO_111"),
257 	PINCTRL_PIN(112, "GPIO_112"),
258 	PINCTRL_PIN(113, "GPIO_113"),
259 	PINCTRL_PIN(114, "GPIO_114"),
260 	PINCTRL_PIN(115, "GPIO_115"),
261 	PINCTRL_PIN(116, "GPIO_116"),
262 	PINCTRL_PIN(117, "GPIO_117"),
263 	PINCTRL_PIN(118, "GPIO_118"),
264 	PINCTRL_PIN(119, "GPIO_119"),
265 	PINCTRL_PIN(120, "GPIO_120"),
266 	PINCTRL_PIN(121, "GPIO_121"),
267 	PINCTRL_PIN(122, "GPIO_122"),
268 	PINCTRL_PIN(123, "GPIO_123"),
269 	PINCTRL_PIN(124, "GPIO_124"),
270 	PINCTRL_PIN(125, "GPIO_125"),
271 	PINCTRL_PIN(126, "GPIO_126"),
272 	PINCTRL_PIN(127, "GPIO_127"),
273 	PINCTRL_PIN(128, "GPIO_128"),
274 	PINCTRL_PIN(129, "GPIO_129"),
275 	PINCTRL_PIN(130, "GPIO_130"),
276 	PINCTRL_PIN(131, "GPIO_131"),
277 	PINCTRL_PIN(132, "GPIO_132"),
278 	PINCTRL_PIN(133, "GPIO_133"),
279 	PINCTRL_PIN(134, "GPIO_134"),
280 	PINCTRL_PIN(135, "GPIO_135"),
281 	PINCTRL_PIN(136, "GPIO_136"),
282 	PINCTRL_PIN(137, "GPIO_137"),
283 	PINCTRL_PIN(138, "GPIO_138"),
284 	PINCTRL_PIN(139, "GPIO_139"),
285 	PINCTRL_PIN(140, "GPIO_140"),
286 	PINCTRL_PIN(141, "GPIO_141"),
287 	PINCTRL_PIN(142, "GPIO_142"),
288 	PINCTRL_PIN(143, "GPIO_143"),
289 	PINCTRL_PIN(144, "GPIO_144"),
290 	PINCTRL_PIN(145, "GPIO_145"),
291 	PINCTRL_PIN(146, "GPIO_146"),
292 	PINCTRL_PIN(147, "GPIO_147"),
293 	PINCTRL_PIN(148, "GPIO_148"),
294 	PINCTRL_PIN(149, "GPIO_149"),
295 	PINCTRL_PIN(150, "UFS_RESET"),
296 	PINCTRL_PIN(151, "SDC1_RCLK"),
297 	PINCTRL_PIN(152, "SDC1_CLK"),
298 	PINCTRL_PIN(153, "SDC1_CMD"),
299 	PINCTRL_PIN(154, "SDC1_DATA"),
300 	PINCTRL_PIN(155, "SDC2_CLK"),
301 	PINCTRL_PIN(156, "SDC2_CMD"),
302 	PINCTRL_PIN(157, "SDC2_DATA"),
303 };
304 
305 #define DECLARE_MSM_GPIO_PINS(pin) \
306 	static const unsigned int gpio##pin##_pins[] = { pin }
307 DECLARE_MSM_GPIO_PINS(0);
308 DECLARE_MSM_GPIO_PINS(1);
309 DECLARE_MSM_GPIO_PINS(2);
310 DECLARE_MSM_GPIO_PINS(3);
311 DECLARE_MSM_GPIO_PINS(4);
312 DECLARE_MSM_GPIO_PINS(5);
313 DECLARE_MSM_GPIO_PINS(6);
314 DECLARE_MSM_GPIO_PINS(7);
315 DECLARE_MSM_GPIO_PINS(8);
316 DECLARE_MSM_GPIO_PINS(9);
317 DECLARE_MSM_GPIO_PINS(10);
318 DECLARE_MSM_GPIO_PINS(11);
319 DECLARE_MSM_GPIO_PINS(12);
320 DECLARE_MSM_GPIO_PINS(13);
321 DECLARE_MSM_GPIO_PINS(14);
322 DECLARE_MSM_GPIO_PINS(15);
323 DECLARE_MSM_GPIO_PINS(16);
324 DECLARE_MSM_GPIO_PINS(17);
325 DECLARE_MSM_GPIO_PINS(18);
326 DECLARE_MSM_GPIO_PINS(19);
327 DECLARE_MSM_GPIO_PINS(20);
328 DECLARE_MSM_GPIO_PINS(21);
329 DECLARE_MSM_GPIO_PINS(22);
330 DECLARE_MSM_GPIO_PINS(23);
331 DECLARE_MSM_GPIO_PINS(24);
332 DECLARE_MSM_GPIO_PINS(25);
333 DECLARE_MSM_GPIO_PINS(26);
334 DECLARE_MSM_GPIO_PINS(27);
335 DECLARE_MSM_GPIO_PINS(28);
336 DECLARE_MSM_GPIO_PINS(29);
337 DECLARE_MSM_GPIO_PINS(30);
338 DECLARE_MSM_GPIO_PINS(31);
339 DECLARE_MSM_GPIO_PINS(32);
340 DECLARE_MSM_GPIO_PINS(33);
341 DECLARE_MSM_GPIO_PINS(34);
342 DECLARE_MSM_GPIO_PINS(35);
343 DECLARE_MSM_GPIO_PINS(36);
344 DECLARE_MSM_GPIO_PINS(37);
345 DECLARE_MSM_GPIO_PINS(38);
346 DECLARE_MSM_GPIO_PINS(39);
347 DECLARE_MSM_GPIO_PINS(40);
348 DECLARE_MSM_GPIO_PINS(41);
349 DECLARE_MSM_GPIO_PINS(42);
350 DECLARE_MSM_GPIO_PINS(43);
351 DECLARE_MSM_GPIO_PINS(44);
352 DECLARE_MSM_GPIO_PINS(45);
353 DECLARE_MSM_GPIO_PINS(46);
354 DECLARE_MSM_GPIO_PINS(47);
355 DECLARE_MSM_GPIO_PINS(48);
356 DECLARE_MSM_GPIO_PINS(49);
357 DECLARE_MSM_GPIO_PINS(50);
358 DECLARE_MSM_GPIO_PINS(51);
359 DECLARE_MSM_GPIO_PINS(52);
360 DECLARE_MSM_GPIO_PINS(53);
361 DECLARE_MSM_GPIO_PINS(54);
362 DECLARE_MSM_GPIO_PINS(55);
363 DECLARE_MSM_GPIO_PINS(56);
364 DECLARE_MSM_GPIO_PINS(57);
365 DECLARE_MSM_GPIO_PINS(58);
366 DECLARE_MSM_GPIO_PINS(59);
367 DECLARE_MSM_GPIO_PINS(60);
368 DECLARE_MSM_GPIO_PINS(61);
369 DECLARE_MSM_GPIO_PINS(62);
370 DECLARE_MSM_GPIO_PINS(63);
371 DECLARE_MSM_GPIO_PINS(64);
372 DECLARE_MSM_GPIO_PINS(65);
373 DECLARE_MSM_GPIO_PINS(66);
374 DECLARE_MSM_GPIO_PINS(67);
375 DECLARE_MSM_GPIO_PINS(68);
376 DECLARE_MSM_GPIO_PINS(69);
377 DECLARE_MSM_GPIO_PINS(70);
378 DECLARE_MSM_GPIO_PINS(71);
379 DECLARE_MSM_GPIO_PINS(72);
380 DECLARE_MSM_GPIO_PINS(73);
381 DECLARE_MSM_GPIO_PINS(74);
382 DECLARE_MSM_GPIO_PINS(75);
383 DECLARE_MSM_GPIO_PINS(76);
384 DECLARE_MSM_GPIO_PINS(77);
385 DECLARE_MSM_GPIO_PINS(78);
386 DECLARE_MSM_GPIO_PINS(79);
387 DECLARE_MSM_GPIO_PINS(80);
388 DECLARE_MSM_GPIO_PINS(81);
389 DECLARE_MSM_GPIO_PINS(82);
390 DECLARE_MSM_GPIO_PINS(83);
391 DECLARE_MSM_GPIO_PINS(84);
392 DECLARE_MSM_GPIO_PINS(85);
393 DECLARE_MSM_GPIO_PINS(86);
394 DECLARE_MSM_GPIO_PINS(87);
395 DECLARE_MSM_GPIO_PINS(88);
396 DECLARE_MSM_GPIO_PINS(89);
397 DECLARE_MSM_GPIO_PINS(90);
398 DECLARE_MSM_GPIO_PINS(91);
399 DECLARE_MSM_GPIO_PINS(92);
400 DECLARE_MSM_GPIO_PINS(93);
401 DECLARE_MSM_GPIO_PINS(94);
402 DECLARE_MSM_GPIO_PINS(95);
403 DECLARE_MSM_GPIO_PINS(96);
404 DECLARE_MSM_GPIO_PINS(97);
405 DECLARE_MSM_GPIO_PINS(98);
406 DECLARE_MSM_GPIO_PINS(99);
407 DECLARE_MSM_GPIO_PINS(100);
408 DECLARE_MSM_GPIO_PINS(101);
409 DECLARE_MSM_GPIO_PINS(102);
410 DECLARE_MSM_GPIO_PINS(103);
411 DECLARE_MSM_GPIO_PINS(104);
412 DECLARE_MSM_GPIO_PINS(105);
413 DECLARE_MSM_GPIO_PINS(106);
414 DECLARE_MSM_GPIO_PINS(107);
415 DECLARE_MSM_GPIO_PINS(108);
416 DECLARE_MSM_GPIO_PINS(109);
417 DECLARE_MSM_GPIO_PINS(110);
418 DECLARE_MSM_GPIO_PINS(111);
419 DECLARE_MSM_GPIO_PINS(112);
420 DECLARE_MSM_GPIO_PINS(113);
421 DECLARE_MSM_GPIO_PINS(114);
422 DECLARE_MSM_GPIO_PINS(115);
423 DECLARE_MSM_GPIO_PINS(116);
424 DECLARE_MSM_GPIO_PINS(117);
425 DECLARE_MSM_GPIO_PINS(118);
426 DECLARE_MSM_GPIO_PINS(119);
427 DECLARE_MSM_GPIO_PINS(120);
428 DECLARE_MSM_GPIO_PINS(121);
429 DECLARE_MSM_GPIO_PINS(122);
430 DECLARE_MSM_GPIO_PINS(123);
431 DECLARE_MSM_GPIO_PINS(124);
432 DECLARE_MSM_GPIO_PINS(125);
433 DECLARE_MSM_GPIO_PINS(126);
434 DECLARE_MSM_GPIO_PINS(127);
435 DECLARE_MSM_GPIO_PINS(128);
436 DECLARE_MSM_GPIO_PINS(129);
437 DECLARE_MSM_GPIO_PINS(130);
438 DECLARE_MSM_GPIO_PINS(131);
439 DECLARE_MSM_GPIO_PINS(132);
440 DECLARE_MSM_GPIO_PINS(133);
441 DECLARE_MSM_GPIO_PINS(134);
442 DECLARE_MSM_GPIO_PINS(135);
443 DECLARE_MSM_GPIO_PINS(136);
444 DECLARE_MSM_GPIO_PINS(137);
445 DECLARE_MSM_GPIO_PINS(138);
446 DECLARE_MSM_GPIO_PINS(139);
447 DECLARE_MSM_GPIO_PINS(140);
448 DECLARE_MSM_GPIO_PINS(141);
449 DECLARE_MSM_GPIO_PINS(142);
450 DECLARE_MSM_GPIO_PINS(143);
451 DECLARE_MSM_GPIO_PINS(144);
452 DECLARE_MSM_GPIO_PINS(145);
453 DECLARE_MSM_GPIO_PINS(146);
454 DECLARE_MSM_GPIO_PINS(147);
455 DECLARE_MSM_GPIO_PINS(148);
456 DECLARE_MSM_GPIO_PINS(149);
457 
458 static const unsigned int ufs_reset_pins[] = { 150 };
459 static const unsigned int sdc1_rclk_pins[] = { 151 };
460 static const unsigned int sdc1_clk_pins[] = { 152 };
461 static const unsigned int sdc1_cmd_pins[] = { 153 };
462 static const unsigned int sdc1_data_pins[] = { 154 };
463 static const unsigned int sdc2_clk_pins[] = { 155 };
464 static const unsigned int sdc2_cmd_pins[] = { 156 };
465 static const unsigned int sdc2_data_pins[] = { 157 };
466 
467 enum sdm670_functions {
468 	msm_mux_gpio,
469 	msm_mux_adsp_ext,
470 	msm_mux_agera_pll,
471 	msm_mux_atest_char,
472 	msm_mux_atest_tsens,
473 	msm_mux_atest_tsens2,
474 	msm_mux_atest_usb1,
475 	msm_mux_atest_usb10,
476 	msm_mux_atest_usb11,
477 	msm_mux_atest_usb12,
478 	msm_mux_atest_usb13,
479 	msm_mux_atest_usb2,
480 	msm_mux_atest_usb20,
481 	msm_mux_atest_usb21,
482 	msm_mux_atest_usb22,
483 	msm_mux_atest_usb23,
484 	msm_mux_cam_mclk,
485 	msm_mux_cci_async,
486 	msm_mux_cci_i2c,
487 	msm_mux_cci_timer0,
488 	msm_mux_cci_timer1,
489 	msm_mux_cci_timer2,
490 	msm_mux_cci_timer3,
491 	msm_mux_cci_timer4,
492 	msm_mux_copy_gp,
493 	msm_mux_copy_phase,
494 	msm_mux_dbg_out,
495 	msm_mux_ddr_bist,
496 	msm_mux_ddr_pxi0,
497 	msm_mux_ddr_pxi1,
498 	msm_mux_ddr_pxi2,
499 	msm_mux_ddr_pxi3,
500 	msm_mux_edp_hot,
501 	msm_mux_edp_lcd,
502 	msm_mux_gcc_gp1,
503 	msm_mux_gcc_gp2,
504 	msm_mux_gcc_gp3,
505 	msm_mux_gp_pdm0,
506 	msm_mux_gp_pdm1,
507 	msm_mux_gp_pdm2,
508 	msm_mux_gps_tx,
509 	msm_mux_jitter_bist,
510 	msm_mux_ldo_en,
511 	msm_mux_ldo_update,
512 	msm_mux_lpass_slimbus,
513 	msm_mux_m_voc,
514 	msm_mux_mdp_vsync,
515 	msm_mux_mdp_vsync0,
516 	msm_mux_mdp_vsync1,
517 	msm_mux_mdp_vsync2,
518 	msm_mux_mdp_vsync3,
519 	msm_mux_mss_lte,
520 	msm_mux_nav_pps,
521 	msm_mux_pa_indicator,
522 	msm_mux_pci_e0,
523 	msm_mux_pci_e1,
524 	msm_mux_phase_flag,
525 	msm_mux_pll_bist,
526 	msm_mux_pll_bypassnl,
527 	msm_mux_pll_reset,
528 	msm_mux_pri_mi2s,
529 	msm_mux_pri_mi2s_ws,
530 	msm_mux_prng_rosc,
531 	msm_mux_qdss_cti,
532 	msm_mux_qdss,
533 	msm_mux_qlink_enable,
534 	msm_mux_qlink_request,
535 	msm_mux_qua_mi2s,
536 	msm_mux_qup0,
537 	msm_mux_qup1,
538 	msm_mux_qup10,
539 	msm_mux_qup11,
540 	msm_mux_qup12,
541 	msm_mux_qup13,
542 	msm_mux_qup14,
543 	msm_mux_qup15,
544 	msm_mux_qup2,
545 	msm_mux_qup3,
546 	msm_mux_qup4,
547 	msm_mux_qup5,
548 	msm_mux_qup6,
549 	msm_mux_qup7,
550 	msm_mux_qup8,
551 	msm_mux_qup9,
552 	msm_mux_qup_l4,
553 	msm_mux_qup_l5,
554 	msm_mux_qup_l6,
555 	msm_mux_sd_write,
556 	msm_mux_sdc4_clk,
557 	msm_mux_sdc4_cmd,
558 	msm_mux_sdc4_data,
559 	msm_mux_sec_mi2s,
560 	msm_mux_ter_mi2s,
561 	msm_mux_tgu_ch0,
562 	msm_mux_tgu_ch1,
563 	msm_mux_tgu_ch2,
564 	msm_mux_tgu_ch3,
565 	msm_mux_tsif1_clk,
566 	msm_mux_tsif1_data,
567 	msm_mux_tsif1_en,
568 	msm_mux_tsif1_error,
569 	msm_mux_tsif1_sync,
570 	msm_mux_tsif2_clk,
571 	msm_mux_tsif2_data,
572 	msm_mux_tsif2_en,
573 	msm_mux_tsif2_error,
574 	msm_mux_tsif2_sync,
575 	msm_mux_uim1_clk,
576 	msm_mux_uim1_data,
577 	msm_mux_uim1_present,
578 	msm_mux_uim1_reset,
579 	msm_mux_uim2_clk,
580 	msm_mux_uim2_data,
581 	msm_mux_uim2_present,
582 	msm_mux_uim2_reset,
583 	msm_mux_uim_batt,
584 	msm_mux_usb_phy,
585 	msm_mux_vfr_1,
586 	msm_mux_vsense_trigger,
587 	msm_mux_wlan1_adc0,
588 	msm_mux_wlan1_adc1,
589 	msm_mux_wlan2_adc0,
590 	msm_mux_wlan2_adc1,
591 	msm_mux_wsa_clk,
592 	msm_mux_wsa_data,
593 	msm_mux__,
594 };
595 
596 static const char * const gpio_groups[] = {
597 	"gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
598 	"gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
599 	"gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
600 	"gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
601 	"gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
602 	"gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
603 	"gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
604 	"gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
605 	"gpio57", "gpio65", "gpio66", "gpio67", "gpio68", "gpio75", "gpio76",
606 	"gpio77", "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83",
607 	"gpio84", "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90",
608 	"gpio91", "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97",
609 	"gpio98", "gpio99", "gpio100", "gpio101", "gpio102", "gpio103",
610 	"gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110",
611 	"gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116",
612 	"gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122",
613 	"gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128",
614 	"gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134",
615 	"gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140",
616 	"gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146",
617 	"gpio147", "gpio148", "gpio149",
618 };
619 static const char * const qup0_groups[] = {
620 	"gpio0", "gpio1", "gpio2", "gpio3",
621 };
622 static const char * const qup9_groups[] = {
623 	"gpio4", "gpio5", "gpio6", "gpio7",
624 };
625 static const char * const qdss_cti_groups[] = {
626 	"gpio4", "gpio5", "gpio51", "gpio52", "gpio90", "gpio91",
627 };
628 static const char * const ddr_pxi0_groups[] = {
629 	"gpio6", "gpio7",
630 };
631 static const char * const ddr_bist_groups[] = {
632 	"gpio7", "gpio8", "gpio9", "gpio10",
633 };
634 static const char * const atest_tsens2_groups[] = {
635 	"gpio7",
636 };
637 static const char * const vsense_trigger_groups[] = {
638 	"gpio7",
639 };
640 static const char * const atest_usb1_groups[] = {
641 	"gpio7",
642 };
643 static const char * const qup_l4_groups[] = {
644 	"gpio8", "gpio35", "gpio75", "gpio105", "gpio123",
645 };
646 static const char * const gp_pdm1_groups[] = {
647 	"gpio8", "gpio66",
648 };
649 static const char * const qup_l5_groups[] = {
650 	"gpio9", "gpio36", "gpio76", "gpio106", "gpio124",
651 };
652 static const char * const mdp_vsync_groups[] = {
653 	"gpio10", "gpio11", "gpio12", "gpio97", "gpio98",
654 };
655 static const char * const qup_l6_groups[] = {
656 	"gpio10", "gpio37", "gpio77", "gpio107", "gpio125",
657 };
658 static const char * const wlan2_adc1_groups[] = {
659 	"gpio10",
660 };
661 static const char * const atest_usb11_groups[] = {
662 	"gpio10",
663 };
664 static const char * const ddr_pxi2_groups[] = {
665 	"gpio10", "gpio11",
666 };
667 static const char * const edp_lcd_groups[] = {
668 	"gpio11",
669 };
670 static const char * const dbg_out_groups[] = {
671 	"gpio11",
672 };
673 static const char * const wlan2_adc0_groups[] = {
674 	"gpio11",
675 };
676 static const char * const atest_usb10_groups[] = {
677 	"gpio11",
678 };
679 static const char * const m_voc_groups[] = {
680 	"gpio12",
681 };
682 static const char * const tsif1_sync_groups[] = {
683 	"gpio12",
684 };
685 static const char * const ddr_pxi3_groups[] = {
686 	"gpio12", "gpio13",
687 };
688 static const char * const cam_mclk_groups[] = {
689 	"gpio13", "gpio14", "gpio15", "gpio16",
690 };
691 static const char * const pll_bypassnl_groups[] = {
692 	"gpio13",
693 };
694 static const char * const qdss_groups[] = {
695 	"gpio13", "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19",
696 	"gpio20", "gpio21", "gpio22", "gpio23", "gpio24", "gpio25", "gpio26",
697 	"gpio27", "gpio28", "gpio29", "gpio30", "gpio41", "gpio42", "gpio43",
698 	"gpio44", "gpio75", "gpio76", "gpio77", "gpio79", "gpio80", "gpio93",
699 	"gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122",
700 	"gpio123", "gpio124",
701 };
702 static const char * const pll_reset_groups[] = {
703 	"gpio14",
704 };
705 static const char * const cci_i2c_groups[] = {
706 	"gpio17", "gpio18", "gpio19", "gpio20",
707 };
708 static const char * const qup1_groups[] = {
709 	"gpio17", "gpio18", "gpio19", "gpio20",
710 };
711 static const char * const cci_timer0_groups[] = {
712 	"gpio21",
713 };
714 static const char * const gcc_gp2_groups[] = {
715 	"gpio21",
716 };
717 static const char * const cci_timer1_groups[] = {
718 	"gpio22",
719 };
720 static const char * const gcc_gp3_groups[] = {
721 	"gpio22",
722 };
723 static const char * const cci_timer2_groups[] = {
724 	"gpio23",
725 };
726 static const char * const cci_timer3_groups[] = {
727 	"gpio24",
728 };
729 static const char * const cci_async_groups[] = {
730 	"gpio24", "gpio25", "gpio26",
731 };
732 static const char * const cci_timer4_groups[] = {
733 	"gpio25",
734 };
735 static const char * const jitter_bist_groups[] = {
736 	"gpio26", "gpio35",
737 };
738 static const char * const qup2_groups[] = {
739 	"gpio27", "gpio28", "gpio29", "gpio30",
740 };
741 static const char * const pll_bist_groups[] = {
742 	"gpio27", "gpio36",
743 };
744 static const char * const agera_pll_groups[] = {
745 	"gpio28", "gpio37",
746 };
747 static const char * const atest_tsens_groups[] = {
748 	"gpio29",
749 };
750 static const char * const phase_flag_groups[] = {
751 	"gpio29", "gpio30", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
752 	"gpio57", "gpio75", "gpio76", "gpio77", "gpio89", "gpio90", "gpio96",
753 	"gpio99", "gpio100", "gpio101", "gpio137", "gpio138", "gpio139",
754 	"gpio140", "gpio141", "gpio142", "gpio143",
755 };
756 static const char * const qup11_groups[] = {
757 	"gpio31", "gpio32", "gpio33", "gpio34",
758 };
759 static const char * const qup14_groups[] = {
760 	"gpio31", "gpio32", "gpio33", "gpio34",
761 };
762 static const char * const pci_e0_groups[] = {
763 	"gpio35", "gpio36",
764 };
765 static const char * const usb_phy_groups[] = {
766 	"gpio38",
767 };
768 static const char * const lpass_slimbus_groups[] = {
769 	"gpio39",
770 };
771 static const char * const sd_write_groups[] = {
772 	"gpio40",
773 };
774 static const char * const tsif1_error_groups[] = {
775 	"gpio40",
776 };
777 static const char * const qup3_groups[] = {
778 	"gpio41", "gpio42", "gpio43", "gpio44",
779 };
780 static const char * const qup6_groups[] = {
781 	"gpio45", "gpio46", "gpio47", "gpio48",
782 };
783 static const char * const qup12_groups[] = {
784 	"gpio49", "gpio50", "gpio51", "gpio52",
785 };
786 static const char * const qup10_groups[] = {
787 	"gpio53", "gpio54", "gpio55", "gpio56",
788 };
789 static const char * const gp_pdm0_groups[] = {
790 	"gpio54", "gpio95",
791 };
792 static const char * const wlan1_adc1_groups[] = {
793 	"gpio54",
794 };
795 static const char * const atest_usb13_groups[] = {
796 	"gpio54",
797 };
798 static const char * const ddr_pxi1_groups[] = {
799 	"gpio54", "gpio55",
800 };
801 static const char * const wlan1_adc0_groups[] = {
802 	"gpio55",
803 };
804 static const char * const atest_usb12_groups[] = {
805 	"gpio55",
806 };
807 static const char * const qua_mi2s_groups[] = {
808 	"gpio57",
809 };
810 static const char * const gcc_gp1_groups[] = {
811 	"gpio57", "gpio78",
812 };
813 static const char * const pri_mi2s_groups[] = {
814 	"gpio65", "gpio67", "gpio68",
815 };
816 static const char * const qup8_groups[] = {
817 	"gpio65", "gpio66", "gpio67", "gpio68",
818 };
819 static const char * const wsa_clk_groups[] = {
820 	"gpio65",
821 };
822 static const char * const pri_mi2s_ws_groups[] = {
823 	"gpio66",
824 };
825 static const char * const wsa_data_groups[] = {
826 	"gpio66",
827 };
828 static const char * const atest_usb2_groups[] = {
829 	"gpio67",
830 };
831 static const char * const atest_usb23_groups[] = {
832 	"gpio68",
833 };
834 static const char * const ter_mi2s_groups[] = {
835 	"gpio75", "gpio76", "gpio77", "gpio78",
836 };
837 static const char * const atest_usb22_groups[] = {
838 	"gpio75",
839 };
840 static const char * const atest_usb21_groups[] = {
841 	"gpio76",
842 };
843 static const char * const atest_usb20_groups[] = {
844 	"gpio77",
845 };
846 static const char * const sec_mi2s_groups[] = {
847 	"gpio79", "gpio80", "gpio81", "gpio82", "gpio83",
848 };
849 static const char * const gp_pdm2_groups[] = {
850 	"gpio79",
851 };
852 static const char * const qup15_groups[] = {
853 	"gpio81", "gpio82", "gpio83", "gpio84",
854 };
855 static const char * const qup5_groups[] = {
856 	"gpio85", "gpio86", "gpio87", "gpio88",
857 };
858 static const char * const copy_gp_groups[] = {
859 	"gpio86",
860 };
861 static const char * const tsif1_clk_groups[] = {
862 	"gpio89",
863 };
864 static const char * const qup4_groups[] = {
865 	"gpio89", "gpio90", "gpio91", "gpio92",
866 };
867 static const char * const tgu_ch3_groups[] = {
868 	"gpio89",
869 };
870 static const char * const tsif1_en_groups[] = {
871 	"gpio90",
872 };
873 static const char * const mdp_vsync0_groups[] = {
874 	"gpio90",
875 };
876 static const char * const mdp_vsync1_groups[] = {
877 	"gpio90",
878 };
879 static const char * const mdp_vsync2_groups[] = {
880 	"gpio90",
881 };
882 static const char * const mdp_vsync3_groups[] = {
883 	"gpio90",
884 };
885 static const char * const tgu_ch0_groups[] = {
886 	"gpio90",
887 };
888 static const char * const tsif1_data_groups[] = {
889 	"gpio91",
890 };
891 static const char * const sdc4_cmd_groups[] = {
892 	"gpio91",
893 };
894 static const char * const tgu_ch1_groups[] = {
895 	"gpio91",
896 };
897 static const char * const tsif2_error_groups[] = {
898 	"gpio92",
899 };
900 static const char * const vfr_1_groups[] = {
901 	"gpio92",
902 };
903 static const char * const tgu_ch2_groups[] = {
904 	"gpio92",
905 };
906 static const char * const sdc4_data_groups[] = {
907 	"gpio92", "gpio94", "gpio95", "gpio96",
908 };
909 static const char * const tsif2_clk_groups[] = {
910 	"gpio93",
911 };
912 static const char * const sdc4_clk_groups[] = {
913 	"gpio93",
914 };
915 static const char * const qup7_groups[] = {
916 	"gpio93", "gpio94", "gpio95", "gpio96",
917 };
918 static const char * const tsif2_en_groups[] = {
919 	"gpio94",
920 };
921 static const char * const tsif2_data_groups[] = {
922 	"gpio95",
923 };
924 static const char * const tsif2_sync_groups[] = {
925 	"gpio96",
926 };
927 static const char * const ldo_en_groups[] = {
928 	"gpio97",
929 };
930 static const char * const ldo_update_groups[] = {
931 	"gpio98",
932 };
933 static const char * const prng_rosc_groups[] = {
934 	"gpio99", "gpio102",
935 };
936 static const char * const pci_e1_groups[] = {
937 	"gpio102", "gpio103",
938 };
939 static const char * const copy_phase_groups[] = {
940 	"gpio103",
941 };
942 static const char * const uim2_data_groups[] = {
943 	"gpio105",
944 };
945 static const char * const qup13_groups[] = {
946 	"gpio105", "gpio106", "gpio107", "gpio108",
947 };
948 static const char * const uim2_clk_groups[] = {
949 	"gpio106",
950 };
951 static const char * const uim2_reset_groups[] = {
952 	"gpio107",
953 };
954 static const char * const uim2_present_groups[] = {
955 	"gpio108",
956 };
957 static const char * const uim1_data_groups[] = {
958 	"gpio109",
959 };
960 static const char * const uim1_clk_groups[] = {
961 	"gpio110",
962 };
963 static const char * const uim1_reset_groups[] = {
964 	"gpio111",
965 };
966 static const char * const uim1_present_groups[] = {
967 	"gpio112",
968 };
969 static const char * const uim_batt_groups[] = {
970 	"gpio113",
971 };
972 static const char * const edp_hot_groups[] = {
973 	"gpio113",
974 };
975 static const char * const nav_pps_groups[] = {
976 	"gpio114", "gpio114", "gpio115", "gpio115", "gpio128", "gpio128",
977 	"gpio129", "gpio129", "gpio143", "gpio143",
978 };
979 static const char * const gps_tx_groups[] = {
980 	"gpio114", "gpio115", "gpio128", "gpio129", "gpio143", "gpio145",
981 };
982 static const char * const atest_char_groups[] = {
983 	"gpio117", "gpio118", "gpio119", "gpio120", "gpio121",
984 };
985 static const char * const adsp_ext_groups[] = {
986 	"gpio118",
987 };
988 static const char * const qlink_request_groups[] = {
989 	"gpio130",
990 };
991 static const char * const qlink_enable_groups[] = {
992 	"gpio131",
993 };
994 static const char * const pa_indicator_groups[] = {
995 	"gpio135",
996 };
997 static const char * const mss_lte_groups[] = {
998 	"gpio144", "gpio145",
999 };
1000 
1001 static const struct msm_function sdm670_functions[] = {
1002 	FUNCTION(gpio),
1003 	FUNCTION(adsp_ext),
1004 	FUNCTION(agera_pll),
1005 	FUNCTION(atest_char),
1006 	FUNCTION(atest_tsens),
1007 	FUNCTION(atest_tsens2),
1008 	FUNCTION(atest_usb1),
1009 	FUNCTION(atest_usb10),
1010 	FUNCTION(atest_usb11),
1011 	FUNCTION(atest_usb12),
1012 	FUNCTION(atest_usb13),
1013 	FUNCTION(atest_usb2),
1014 	FUNCTION(atest_usb20),
1015 	FUNCTION(atest_usb21),
1016 	FUNCTION(atest_usb22),
1017 	FUNCTION(atest_usb23),
1018 	FUNCTION(cam_mclk),
1019 	FUNCTION(cci_async),
1020 	FUNCTION(cci_i2c),
1021 	FUNCTION(cci_timer0),
1022 	FUNCTION(cci_timer1),
1023 	FUNCTION(cci_timer2),
1024 	FUNCTION(cci_timer3),
1025 	FUNCTION(cci_timer4),
1026 	FUNCTION(copy_gp),
1027 	FUNCTION(copy_phase),
1028 	FUNCTION(dbg_out),
1029 	FUNCTION(ddr_bist),
1030 	FUNCTION(ddr_pxi0),
1031 	FUNCTION(ddr_pxi1),
1032 	FUNCTION(ddr_pxi2),
1033 	FUNCTION(ddr_pxi3),
1034 	FUNCTION(edp_hot),
1035 	FUNCTION(edp_lcd),
1036 	FUNCTION(gcc_gp1),
1037 	FUNCTION(gcc_gp2),
1038 	FUNCTION(gcc_gp3),
1039 	FUNCTION(gp_pdm0),
1040 	FUNCTION(gp_pdm1),
1041 	FUNCTION(gp_pdm2),
1042 	FUNCTION(gps_tx),
1043 	FUNCTION(jitter_bist),
1044 	FUNCTION(ldo_en),
1045 	FUNCTION(ldo_update),
1046 	FUNCTION(lpass_slimbus),
1047 	FUNCTION(m_voc),
1048 	FUNCTION(mdp_vsync),
1049 	FUNCTION(mdp_vsync0),
1050 	FUNCTION(mdp_vsync1),
1051 	FUNCTION(mdp_vsync2),
1052 	FUNCTION(mdp_vsync3),
1053 	FUNCTION(mss_lte),
1054 	FUNCTION(nav_pps),
1055 	FUNCTION(pa_indicator),
1056 	FUNCTION(pci_e0),
1057 	FUNCTION(pci_e1),
1058 	FUNCTION(phase_flag),
1059 	FUNCTION(pll_bist),
1060 	FUNCTION(pll_bypassnl),
1061 	FUNCTION(pll_reset),
1062 	FUNCTION(pri_mi2s),
1063 	FUNCTION(pri_mi2s_ws),
1064 	FUNCTION(prng_rosc),
1065 	FUNCTION(qdss_cti),
1066 	FUNCTION(qdss),
1067 	FUNCTION(qlink_enable),
1068 	FUNCTION(qlink_request),
1069 	FUNCTION(qua_mi2s),
1070 	FUNCTION(qup0),
1071 	FUNCTION(qup1),
1072 	FUNCTION(qup10),
1073 	FUNCTION(qup11),
1074 	FUNCTION(qup12),
1075 	FUNCTION(qup13),
1076 	FUNCTION(qup14),
1077 	FUNCTION(qup15),
1078 	FUNCTION(qup2),
1079 	FUNCTION(qup3),
1080 	FUNCTION(qup4),
1081 	FUNCTION(qup5),
1082 	FUNCTION(qup6),
1083 	FUNCTION(qup7),
1084 	FUNCTION(qup8),
1085 	FUNCTION(qup9),
1086 	FUNCTION(qup_l4),
1087 	FUNCTION(qup_l5),
1088 	FUNCTION(qup_l6),
1089 	FUNCTION(sdc4_clk),
1090 	FUNCTION(sdc4_cmd),
1091 	FUNCTION(sdc4_data),
1092 	FUNCTION(sd_write),
1093 	FUNCTION(sec_mi2s),
1094 	FUNCTION(ter_mi2s),
1095 	FUNCTION(tgu_ch0),
1096 	FUNCTION(tgu_ch1),
1097 	FUNCTION(tgu_ch2),
1098 	FUNCTION(tgu_ch3),
1099 	FUNCTION(tsif1_clk),
1100 	FUNCTION(tsif1_data),
1101 	FUNCTION(tsif1_en),
1102 	FUNCTION(tsif1_error),
1103 	FUNCTION(tsif1_sync),
1104 	FUNCTION(tsif2_clk),
1105 	FUNCTION(tsif2_data),
1106 	FUNCTION(tsif2_en),
1107 	FUNCTION(tsif2_error),
1108 	FUNCTION(tsif2_sync),
1109 	FUNCTION(uim1_clk),
1110 	FUNCTION(uim1_data),
1111 	FUNCTION(uim1_present),
1112 	FUNCTION(uim1_reset),
1113 	FUNCTION(uim2_clk),
1114 	FUNCTION(uim2_data),
1115 	FUNCTION(uim2_present),
1116 	FUNCTION(uim2_reset),
1117 	FUNCTION(uim_batt),
1118 	FUNCTION(usb_phy),
1119 	FUNCTION(vfr_1),
1120 	FUNCTION(vsense_trigger),
1121 	FUNCTION(wlan1_adc0),
1122 	FUNCTION(wlan1_adc1),
1123 	FUNCTION(wlan2_adc0),
1124 	FUNCTION(wlan2_adc1),
1125 	FUNCTION(wsa_clk),
1126 	FUNCTION(wsa_data),
1127 };
1128 
1129 /*
1130  * Each pin is individually controlled by its own group and gpios that cannot
1131  * be requested are represented by the PINGROUP_DUMMY macro so that the group
1132  * numbers and names correspond to their respective gpio. These dummy pins do
1133  * not have a valid set of pinfuncs or a valid ctl_reg and should not be
1134  * requested.
1135  */
1136 static const struct msm_pingroup sdm670_groups[] = {
1137 	PINGROUP(0, SOUTH, qup0, _, _, _, _, _, _, _, _),
1138 	PINGROUP(1, SOUTH, qup0, _, _, _, _, _, _, _, _),
1139 	PINGROUP(2, SOUTH, qup0, _, _, _, _, _, _, _, _),
1140 	PINGROUP(3, SOUTH, qup0, _, _, _, _, _, _, _, _),
1141 	PINGROUP(4, NORTH, qup9, qdss_cti, _, _, _, _, _, _, _),
1142 	PINGROUP(5, NORTH, qup9, qdss_cti, _, _, _, _, _, _, _),
1143 	PINGROUP(6, NORTH, qup9, _, ddr_pxi0, _, _, _, _, _, _),
1144 	PINGROUP(7, NORTH, qup9, ddr_bist, _, atest_tsens2, vsense_trigger, atest_usb1, ddr_pxi0, _, _),
1145 	PINGROUP(8, WEST, qup_l4, gp_pdm1, ddr_bist, _, _, _, _, _, _),
1146 	PINGROUP(9, WEST, qup_l5, ddr_bist, _, _, _, _, _, _, _),
1147 	PINGROUP(10, NORTH, mdp_vsync, qup_l6, ddr_bist, wlan2_adc1, atest_usb11, ddr_pxi2, _, _, _),
1148 	PINGROUP(11, NORTH, mdp_vsync, edp_lcd, dbg_out, wlan2_adc0, atest_usb10, ddr_pxi2, _, _, _),
1149 	PINGROUP(12, SOUTH, mdp_vsync, m_voc, tsif1_sync, ddr_pxi3, _, _, _, _, _),
1150 	PINGROUP(13, WEST, cam_mclk, pll_bypassnl, qdss, ddr_pxi3, _, _, _, _, _),
1151 	PINGROUP(14, WEST, cam_mclk, pll_reset, qdss, _, _, _, _, _, _),
1152 	PINGROUP(15, WEST, cam_mclk, qdss, _, _, _, _, _, _, _),
1153 	PINGROUP(16, WEST, cam_mclk, qdss, _, _, _, _, _, _, _),
1154 	PINGROUP(17, WEST, cci_i2c, qup1, qdss, _, _, _, _, _, _),
1155 	PINGROUP(18, WEST, cci_i2c, qup1, _, qdss, _, _, _, _, _),
1156 	PINGROUP(19, WEST, cci_i2c, qup1, _, qdss, _, _, _, _, _),
1157 	PINGROUP(20, WEST, cci_i2c, qup1, _, qdss, _, _, _, _, _),
1158 	PINGROUP(21, WEST, cci_timer0, gcc_gp2, qdss, _, _, _, _, _, _),
1159 	PINGROUP(22, WEST, cci_timer1, gcc_gp3, qdss, _, _, _, _, _, _),
1160 	PINGROUP(23, WEST, cci_timer2, qdss, _, _, _, _, _, _, _),
1161 	PINGROUP(24, WEST, cci_timer3, cci_async, qdss, _, _, _, _, _, _),
1162 	PINGROUP(25, WEST, cci_timer4, cci_async, qdss, _, _, _, _, _, _),
1163 	PINGROUP(26, WEST, cci_async, qdss, jitter_bist, _, _, _, _, _, _),
1164 	PINGROUP(27, WEST, qup2, qdss, pll_bist, _, _, _, _, _, _),
1165 	PINGROUP(28, WEST, qup2, qdss, agera_pll, _, _, _, _, _, _),
1166 	PINGROUP(29, WEST, qup2, _, phase_flag, qdss, atest_tsens, _, _, _, _),
1167 	PINGROUP(30, WEST, qup2, phase_flag, qdss, _, _, _, _, _, _),
1168 	PINGROUP(31, WEST, qup11, qup14, _, _, _, _, _, _, _),
1169 	PINGROUP(32, WEST, qup11, qup14, _, _, _, _, _, _, _),
1170 	PINGROUP(33, WEST, qup11, qup14, _, _, _, _, _, _, _),
1171 	PINGROUP(34, WEST, qup11, qup14, _, _, _, _, _, _, _),
1172 	PINGROUP(35, NORTH, pci_e0, qup_l4, jitter_bist, _, _, _, _, _, _),
1173 	PINGROUP(36, NORTH, pci_e0, qup_l5, pll_bist, _, _, _, _, _, _),
1174 	PINGROUP(37, NORTH, qup_l6, agera_pll, _, _, _, _, _, _, _),
1175 	PINGROUP(38, NORTH, usb_phy, _, _, _, _, _, _, _, _),
1176 	PINGROUP(39, NORTH, lpass_slimbus, _, _, _, _, _, _, _, _),
1177 	PINGROUP(40, NORTH, sd_write, tsif1_error, _, _, _, _, _, _, _),
1178 	PINGROUP(41, SOUTH, qup3, _, qdss, _, _, _, _, _, _),
1179 	PINGROUP(42, SOUTH, qup3, _, qdss, _, _, _, _, _, _),
1180 	PINGROUP(43, SOUTH, qup3, _, qdss, _, _, _, _, _, _),
1181 	PINGROUP(44, SOUTH, qup3, _, qdss, _, _, _, _, _, _),
1182 	PINGROUP(45, SOUTH, qup6, _, _, _, _, _, _, _, _),
1183 	PINGROUP(46, SOUTH, qup6, _, _, _, _, _, _, _, _),
1184 	PINGROUP(47, SOUTH, qup6, _, _, _, _, _, _, _, _),
1185 	PINGROUP(48, SOUTH, qup6, _, _, _, _, _, _, _, _),
1186 	PINGROUP(49, NORTH, qup12, _, _, _, _, _, _, _, _),
1187 	PINGROUP(50, NORTH, qup12, _, _, _, _, _, _, _, _),
1188 	PINGROUP(51, NORTH, qup12, qdss_cti, _, _, _, _, _, _, _),
1189 	PINGROUP(52, NORTH, qup12, phase_flag, qdss_cti, _, _, _, _, _, _),
1190 	PINGROUP(53, NORTH, qup10, phase_flag, _, _, _, _, _, _, _),
1191 	PINGROUP(54, NORTH, qup10, gp_pdm0, phase_flag, _, wlan1_adc1, atest_usb13, ddr_pxi1, _, _),
1192 	PINGROUP(55, NORTH, qup10, phase_flag, _, wlan1_adc0, atest_usb12, ddr_pxi1, _, _, _),
1193 	PINGROUP(56, NORTH, qup10, phase_flag, _, _, _, _, _, _, _),
1194 	PINGROUP(57, NORTH, qua_mi2s, gcc_gp1, phase_flag, _, _, _, _, _, _),
1195 	PINGROUP_DUMMY(58),
1196 	PINGROUP_DUMMY(59),
1197 	PINGROUP_DUMMY(60),
1198 	PINGROUP_DUMMY(61),
1199 	PINGROUP_DUMMY(62),
1200 	PINGROUP_DUMMY(63),
1201 	PINGROUP_DUMMY(64),
1202 	PINGROUP(65, NORTH, pri_mi2s, qup8, wsa_clk, _, _, _, _, _, _),
1203 	PINGROUP(66, NORTH, pri_mi2s_ws, qup8, wsa_data, gp_pdm1, _, _, _, _, _),
1204 	PINGROUP(67, NORTH, pri_mi2s, qup8, _, atest_usb2, _, _, _, _, _),
1205 	PINGROUP(68, NORTH, pri_mi2s, qup8, _, atest_usb23, _, _, _, _, _),
1206 	PINGROUP_DUMMY(69),
1207 	PINGROUP_DUMMY(70),
1208 	PINGROUP_DUMMY(71),
1209 	PINGROUP_DUMMY(72),
1210 	PINGROUP_DUMMY(73),
1211 	PINGROUP_DUMMY(74),
1212 	PINGROUP(75, NORTH, ter_mi2s, phase_flag, qdss, atest_usb22, qup_l4, _, _, _, _),
1213 	PINGROUP(76, NORTH, ter_mi2s, phase_flag, qdss, atest_usb21, qup_l5, _, _, _, _),
1214 	PINGROUP(77, NORTH, ter_mi2s, phase_flag, qdss, atest_usb20, qup_l6, _, _, _, _),
1215 	PINGROUP(78, NORTH, ter_mi2s, gcc_gp1, _, _, _, _, _, _, _),
1216 	PINGROUP(79, NORTH, sec_mi2s, gp_pdm2, _, qdss, _, _, _, _, _),
1217 	PINGROUP(80, NORTH, sec_mi2s, _, qdss, _, _, _, _, _, _),
1218 	PINGROUP(81, NORTH, sec_mi2s, qup15, _, _, _, _, _, _, _),
1219 	PINGROUP(82, NORTH, sec_mi2s, qup15, _, _, _, _, _, _, _),
1220 	PINGROUP(83, NORTH, sec_mi2s, qup15, _, _, _, _, _, _, _),
1221 	PINGROUP(84, NORTH, qup15, _, _, _, _, _, _, _, _),
1222 	PINGROUP(85, SOUTH, qup5, _, _, _, _, _, _, _, _),
1223 	PINGROUP(86, SOUTH, qup5, copy_gp, _, _, _, _, _, _, _),
1224 	PINGROUP(87, SOUTH, qup5, _, _, _, _, _, _, _, _),
1225 	PINGROUP(88, SOUTH, qup5, _, _, _, _, _, _, _, _),
1226 	PINGROUP(89, SOUTH, tsif1_clk, qup4, tgu_ch3, phase_flag, _, _, _, _, _),
1227 	PINGROUP(90, SOUTH, tsif1_en, mdp_vsync0, qup4, mdp_vsync1, mdp_vsync2, mdp_vsync3, tgu_ch0, phase_flag, qdss_cti),
1228 	PINGROUP(91, SOUTH, tsif1_data, sdc4_cmd, qup4, tgu_ch1, _, qdss_cti, _, _, _),
1229 	PINGROUP(92, SOUTH, tsif2_error, sdc4_data, qup4, vfr_1, tgu_ch2, _, _, _, _),
1230 	PINGROUP(93, SOUTH, tsif2_clk, sdc4_clk, qup7, _, qdss, _, _, _, _),
1231 	PINGROUP(94, SOUTH, tsif2_en, sdc4_data, qup7, _, _, _, _, _, _),
1232 	PINGROUP(95, SOUTH, tsif2_data, sdc4_data, qup7, gp_pdm0, _, _, _, _, _),
1233 	PINGROUP(96, SOUTH, tsif2_sync, sdc4_data, qup7, phase_flag, _, _, _, _, _),
1234 	PINGROUP(97, WEST, _, _, mdp_vsync, ldo_en, _, _, _, _, _),
1235 	PINGROUP(98, WEST, _, mdp_vsync, ldo_update, _, _, _, _, _, _),
1236 	PINGROUP(99, NORTH, phase_flag, prng_rosc, _, _, _, _, _, _, _),
1237 	PINGROUP(100, WEST, phase_flag, _, _, _, _, _, _, _, _),
1238 	PINGROUP(101, WEST, _, phase_flag, _, _, _, _, _, _, _),
1239 	PINGROUP(102, WEST, pci_e1, prng_rosc, _, _, _, _, _, _, _),
1240 	PINGROUP(103, WEST, pci_e1, copy_phase, _, _, _, _, _, _, _),
1241 	PINGROUP_DUMMY(104),
1242 	PINGROUP(105, NORTH, uim2_data, qup13, qup_l4, _, _, _, _, _, _),
1243 	PINGROUP(106, NORTH, uim2_clk, qup13, qup_l5, _, _, _, _, _, _),
1244 	PINGROUP(107, NORTH, uim2_reset, qup13, qup_l6, _, _, _, _, _, _),
1245 	PINGROUP(108, NORTH, uim2_present, qup13, _, _, _, _, _, _, _),
1246 	PINGROUP(109, NORTH, uim1_data, _, _, _, _, _, _, _, _),
1247 	PINGROUP(110, NORTH, uim1_clk, _, _, _, _, _, _, _, _),
1248 	PINGROUP(111, NORTH, uim1_reset, _, _, _, _, _, _, _, _),
1249 	PINGROUP(112, NORTH, uim1_present, _, _, _, _, _, _, _, _),
1250 	PINGROUP(113, NORTH, uim_batt, edp_hot, _, _, _, _, _, _, _),
1251 	PINGROUP(114, WEST, _, nav_pps, nav_pps, gps_tx, _, _, _, _, _),
1252 	PINGROUP(115, WEST, _, nav_pps, nav_pps, gps_tx, _, _, _, _, _),
1253 	PINGROUP(116, SOUTH, _, _, _, _, _, _, _, _, _),
1254 	PINGROUP(117, NORTH, _, qdss, atest_char, _, _, _, _, _, _),
1255 	PINGROUP(118, NORTH, adsp_ext, _, qdss, atest_char, _, _, _, _, _),
1256 	PINGROUP(119, NORTH, _, qdss, atest_char, _, _, _, _, _, _),
1257 	PINGROUP(120, NORTH, _, qdss, atest_char, _, _, _, _, _, _),
1258 	PINGROUP(121, NORTH, _, qdss, atest_char, _, _, _, _, _, _),
1259 	PINGROUP(122, NORTH, _, qdss, _, _, _, _, _, _, _),
1260 	PINGROUP(123, NORTH, qup_l4, _, qdss, _, _, _, _, _, _),
1261 	PINGROUP(124, NORTH, qup_l5, _, qdss, _, _, _, _, _, _),
1262 	PINGROUP(125, NORTH, qup_l6, _, _, _, _, _, _, _, _),
1263 	PINGROUP(126, NORTH, _, _, _, _, _, _, _, _, _),
1264 	PINGROUP(127, WEST, _, _, _, _, _, _, _, _, _),
1265 	PINGROUP(128, WEST, nav_pps, nav_pps, gps_tx, _, _, _, _, _, _),
1266 	PINGROUP(129, WEST, nav_pps, nav_pps, gps_tx, _, _, _, _, _, _),
1267 	PINGROUP(130, WEST, qlink_request, _, _, _, _, _, _, _, _),
1268 	PINGROUP(131, WEST, qlink_enable, _, _, _, _, _, _, _, _),
1269 	PINGROUP(132, WEST, _, _, _, _, _, _, _, _, _),
1270 	PINGROUP(133, NORTH, _, _, _, _, _, _, _, _, _),
1271 	PINGROUP(134, NORTH, _, _, _, _, _, _, _, _, _),
1272 	PINGROUP(135, WEST, _, pa_indicator, _, _, _, _, _, _, _),
1273 	PINGROUP(136, WEST, _, _, _, _, _, _, _, _, _),
1274 	PINGROUP(137, WEST, _, _, phase_flag, _, _, _, _, _, _),
1275 	PINGROUP(138, WEST, _, _, phase_flag, _, _, _, _, _, _),
1276 	PINGROUP(139, WEST, _, phase_flag, _, _, _, _, _, _, _),
1277 	PINGROUP(140, WEST, _, _, phase_flag, _, _, _, _, _, _),
1278 	PINGROUP(141, WEST, _, phase_flag, _, _, _, _, _, _, _),
1279 	PINGROUP(142, WEST, _, phase_flag, _, _, _, _, _, _, _),
1280 	PINGROUP(143, WEST, _, nav_pps, nav_pps, gps_tx, phase_flag, _, _, _, _),
1281 	PINGROUP(144, SOUTH, mss_lte, _, _, _, _, _, _, _, _),
1282 	PINGROUP(145, SOUTH, mss_lte, gps_tx, _, _, _, _, _, _, _),
1283 	PINGROUP(146, WEST, _, _, _, _, _, _, _, _, _),
1284 	PINGROUP(147, WEST, _, _, _, _, _, _, _, _, _),
1285 	PINGROUP(148, WEST, _, _, _, _, _, _, _, _, _),
1286 	PINGROUP(149, WEST, _, _, _, _, _, _, _, _, _),
1287 	UFS_RESET(ufs_reset, 0x99d000),
1288 	SDC_QDSD_PINGROUP(sdc1_rclk, 0x99000, 15, 0),
1289 	SDC_QDSD_PINGROUP(sdc1_clk, 0x99000, 13, 6),
1290 	SDC_QDSD_PINGROUP(sdc1_cmd, 0x99000, 11, 3),
1291 	SDC_QDSD_PINGROUP(sdc1_data, 0x99000, 9, 0),
1292 	SDC_QDSD_PINGROUP(sdc2_clk, 0x9a000, 14, 6),
1293 	SDC_QDSD_PINGROUP(sdc2_cmd, 0x9a000, 11, 3),
1294 	SDC_QDSD_PINGROUP(sdc2_data, 0x9a000, 9, 0),
1295 };
1296 
1297 static const int sdm670_reserved_gpios[] = {
1298 	58, 59, 60, 61, 62, 63, 64, 69, 70, 71, 72, 73, 74, 104, -1
1299 };
1300 
1301 static const struct msm_pinctrl_soc_data sdm670_pinctrl = {
1302 	.pins = sdm670_pins,
1303 	.npins = ARRAY_SIZE(sdm670_pins),
1304 	.functions = sdm670_functions,
1305 	.nfunctions = ARRAY_SIZE(sdm670_functions),
1306 	.groups = sdm670_groups,
1307 	.ngroups = ARRAY_SIZE(sdm670_groups),
1308 	.ngpios = 151,
1309 	.reserved_gpios = sdm670_reserved_gpios,
1310 };
1311 
1312 static int sdm670_pinctrl_probe(struct platform_device *pdev)
1313 {
1314 	return msm_pinctrl_probe(pdev, &sdm670_pinctrl);
1315 }
1316 
1317 static const struct of_device_id sdm670_pinctrl_of_match[] = {
1318 	{ .compatible = "qcom,sdm670-tlmm", },
1319 	{ },
1320 };
1321 MODULE_DEVICE_TABLE(of, sdm670_pinctrl_of_match);
1322 
1323 static struct platform_driver sdm670_pinctrl_driver = {
1324 	.driver = {
1325 		.name = "sdm670-pinctrl",
1326 		.of_match_table = sdm670_pinctrl_of_match,
1327 	},
1328 	.probe = sdm670_pinctrl_probe,
1329 	.remove = msm_pinctrl_remove,
1330 };
1331 
1332 static int __init sdm670_pinctrl_init(void)
1333 {
1334 	return platform_driver_register(&sdm670_pinctrl_driver);
1335 }
1336 arch_initcall(sdm670_pinctrl_init);
1337 
1338 static void __exit sdm670_pinctrl_exit(void)
1339 {
1340 	platform_driver_unregister(&sdm670_pinctrl_driver);
1341 }
1342 module_exit(sdm670_pinctrl_exit);
1343 
1344 MODULE_DESCRIPTION("Qualcomm SDM670 TLMM pinctrl driver");
1345 MODULE_LICENSE("GPL");
1346