1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 4 * Copyright (c) 2023, Linaro Limited 5 */ 6 7 #include <linux/module.h> 8 #include <linux/of.h> 9 #include <linux/platform_device.h> 10 #include <linux/pinctrl/pinctrl.h> 11 12 #include "pinctrl-msm.h" 13 14 #define FUNCTION(fname) \ 15 [msm_mux_##fname] = { \ 16 .name = #fname, \ 17 .groups = fname##_groups, \ 18 .ngroups = ARRAY_SIZE(fname##_groups), \ 19 } 20 21 #define REG_BASE 0x100000 22 #define REG_SIZE 0x1000 23 #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9)\ 24 { \ 25 .name = "gpio" #id, \ 26 .pins = gpio##id##_pins, \ 27 .npins = (unsigned int)ARRAY_SIZE(gpio##id##_pins), \ 28 .funcs = (int[]){ \ 29 msm_mux_gpio, /* gpio mode */ \ 30 msm_mux_##f1, \ 31 msm_mux_##f2, \ 32 msm_mux_##f3, \ 33 msm_mux_##f4, \ 34 msm_mux_##f5, \ 35 msm_mux_##f6, \ 36 msm_mux_##f7, \ 37 msm_mux_##f8, \ 38 msm_mux_##f9 \ 39 }, \ 40 .nfuncs = 10, \ 41 .ctl_reg = REG_BASE + REG_SIZE * id, \ 42 .io_reg = REG_BASE + 0x4 + REG_SIZE * id, \ 43 .intr_cfg_reg = REG_BASE + 0x8 + REG_SIZE * id, \ 44 .intr_status_reg = REG_BASE + 0xc + REG_SIZE * id, \ 45 .intr_target_reg = REG_BASE + 0x8 + REG_SIZE * id, \ 46 .mux_bit = 2, \ 47 .pull_bit = 0, \ 48 .drv_bit = 6, \ 49 .egpio_enable = 12, \ 50 .egpio_present = 11, \ 51 .oe_bit = 9, \ 52 .in_bit = 0, \ 53 .out_bit = 1, \ 54 .intr_enable_bit = 0, \ 55 .intr_status_bit = 0, \ 56 .intr_target_bit = 5, \ 57 .intr_target_kpss_val = 3, \ 58 .intr_raw_status_bit = 4, \ 59 .intr_polarity_bit = 1, \ 60 .intr_detection_bit = 2, \ 61 .intr_detection_width = 2, \ 62 } 63 64 #define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \ 65 { \ 66 .name = #pg_name, \ 67 .pins = pg_name##_pins, \ 68 .npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \ 69 .ctl_reg = ctl, \ 70 .io_reg = 0, \ 71 .intr_cfg_reg = 0, \ 72 .intr_status_reg = 0, \ 73 .intr_target_reg = 0, \ 74 .mux_bit = -1, \ 75 .pull_bit = pull, \ 76 .drv_bit = drv, \ 77 .oe_bit = -1, \ 78 .in_bit = -1, \ 79 .out_bit = -1, \ 80 .intr_enable_bit = -1, \ 81 .intr_status_bit = -1, \ 82 .intr_target_bit = -1, \ 83 .intr_raw_status_bit = -1, \ 84 .intr_polarity_bit = -1, \ 85 .intr_detection_bit = -1, \ 86 .intr_detection_width = -1, \ 87 } 88 89 #define UFS_RESET(pg_name, offset) \ 90 { \ 91 .name = #pg_name, \ 92 .pins = pg_name##_pins, \ 93 .npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \ 94 .ctl_reg = offset, \ 95 .io_reg = offset + 0x4, \ 96 .intr_cfg_reg = 0, \ 97 .intr_status_reg = 0, \ 98 .intr_target_reg = 0, \ 99 .mux_bit = -1, \ 100 .pull_bit = 3, \ 101 .drv_bit = 0, \ 102 .oe_bit = -1, \ 103 .in_bit = -1, \ 104 .out_bit = 0, \ 105 .intr_enable_bit = -1, \ 106 .intr_status_bit = -1, \ 107 .intr_target_bit = -1, \ 108 .intr_raw_status_bit = -1, \ 109 .intr_polarity_bit = -1, \ 110 .intr_detection_bit = -1, \ 111 .intr_detection_width = -1, \ 112 } 113 114 #define QUP_I3C(qup_mode, qup_offset) \ 115 { \ 116 .mode = qup_mode, \ 117 .offset = qup_offset, \ 118 } 119 120 #define QUP_I3C_6_MODE_OFFSET 0xAF000 121 #define QUP_I3C_7_MODE_OFFSET 0xB0000 122 #define QUP_I3C_13_MODE_OFFSET 0xB1000 123 #define QUP_I3C_14_MODE_OFFSET 0xB2000 124 125 static const struct pinctrl_pin_desc sa8775p_pins[] = { 126 PINCTRL_PIN(0, "GPIO_0"), 127 PINCTRL_PIN(1, "GPIO_1"), 128 PINCTRL_PIN(2, "GPIO_2"), 129 PINCTRL_PIN(3, "GPIO_3"), 130 PINCTRL_PIN(4, "GPIO_4"), 131 PINCTRL_PIN(5, "GPIO_5"), 132 PINCTRL_PIN(6, "GPIO_6"), 133 PINCTRL_PIN(7, "GPIO_7"), 134 PINCTRL_PIN(8, "GPIO_8"), 135 PINCTRL_PIN(9, "GPIO_9"), 136 PINCTRL_PIN(10, "GPIO_10"), 137 PINCTRL_PIN(11, "GPIO_11"), 138 PINCTRL_PIN(12, "GPIO_12"), 139 PINCTRL_PIN(13, "GPIO_13"), 140 PINCTRL_PIN(14, "GPIO_14"), 141 PINCTRL_PIN(15, "GPIO_15"), 142 PINCTRL_PIN(16, "GPIO_16"), 143 PINCTRL_PIN(17, "GPIO_17"), 144 PINCTRL_PIN(18, "GPIO_18"), 145 PINCTRL_PIN(19, "GPIO_19"), 146 PINCTRL_PIN(20, "GPIO_20"), 147 PINCTRL_PIN(21, "GPIO_21"), 148 PINCTRL_PIN(22, "GPIO_22"), 149 PINCTRL_PIN(23, "GPIO_23"), 150 PINCTRL_PIN(24, "GPIO_24"), 151 PINCTRL_PIN(25, "GPIO_25"), 152 PINCTRL_PIN(26, "GPIO_26"), 153 PINCTRL_PIN(27, "GPIO_27"), 154 PINCTRL_PIN(28, "GPIO_28"), 155 PINCTRL_PIN(29, "GPIO_29"), 156 PINCTRL_PIN(30, "GPIO_30"), 157 PINCTRL_PIN(31, "GPIO_31"), 158 PINCTRL_PIN(32, "GPIO_32"), 159 PINCTRL_PIN(33, "GPIO_33"), 160 PINCTRL_PIN(34, "GPIO_34"), 161 PINCTRL_PIN(35, "GPIO_35"), 162 PINCTRL_PIN(36, "GPIO_36"), 163 PINCTRL_PIN(37, "GPIO_37"), 164 PINCTRL_PIN(38, "GPIO_38"), 165 PINCTRL_PIN(39, "GPIO_39"), 166 PINCTRL_PIN(40, "GPIO_40"), 167 PINCTRL_PIN(41, "GPIO_41"), 168 PINCTRL_PIN(42, "GPIO_42"), 169 PINCTRL_PIN(43, "GPIO_43"), 170 PINCTRL_PIN(44, "GPIO_44"), 171 PINCTRL_PIN(45, "GPIO_45"), 172 PINCTRL_PIN(46, "GPIO_46"), 173 PINCTRL_PIN(47, "GPIO_47"), 174 PINCTRL_PIN(48, "GPIO_48"), 175 PINCTRL_PIN(49, "GPIO_49"), 176 PINCTRL_PIN(50, "GPIO_50"), 177 PINCTRL_PIN(51, "GPIO_51"), 178 PINCTRL_PIN(52, "GPIO_52"), 179 PINCTRL_PIN(53, "GPIO_53"), 180 PINCTRL_PIN(54, "GPIO_54"), 181 PINCTRL_PIN(55, "GPIO_55"), 182 PINCTRL_PIN(56, "GPIO_56"), 183 PINCTRL_PIN(57, "GPIO_57"), 184 PINCTRL_PIN(58, "GPIO_58"), 185 PINCTRL_PIN(59, "GPIO_59"), 186 PINCTRL_PIN(60, "GPIO_60"), 187 PINCTRL_PIN(61, "GPIO_61"), 188 PINCTRL_PIN(62, "GPIO_62"), 189 PINCTRL_PIN(63, "GPIO_63"), 190 PINCTRL_PIN(64, "GPIO_64"), 191 PINCTRL_PIN(65, "GPIO_65"), 192 PINCTRL_PIN(66, "GPIO_66"), 193 PINCTRL_PIN(67, "GPIO_67"), 194 PINCTRL_PIN(68, "GPIO_68"), 195 PINCTRL_PIN(69, "GPIO_69"), 196 PINCTRL_PIN(70, "GPIO_70"), 197 PINCTRL_PIN(71, "GPIO_71"), 198 PINCTRL_PIN(72, "GPIO_72"), 199 PINCTRL_PIN(73, "GPIO_73"), 200 PINCTRL_PIN(74, "GPIO_74"), 201 PINCTRL_PIN(75, "GPIO_75"), 202 PINCTRL_PIN(76, "GPIO_76"), 203 PINCTRL_PIN(77, "GPIO_77"), 204 PINCTRL_PIN(78, "GPIO_78"), 205 PINCTRL_PIN(79, "GPIO_79"), 206 PINCTRL_PIN(80, "GPIO_80"), 207 PINCTRL_PIN(81, "GPIO_81"), 208 PINCTRL_PIN(82, "GPIO_82"), 209 PINCTRL_PIN(83, "GPIO_83"), 210 PINCTRL_PIN(84, "GPIO_84"), 211 PINCTRL_PIN(85, "GPIO_85"), 212 PINCTRL_PIN(86, "GPIO_86"), 213 PINCTRL_PIN(87, "GPIO_87"), 214 PINCTRL_PIN(88, "GPIO_88"), 215 PINCTRL_PIN(89, "GPIO_89"), 216 PINCTRL_PIN(90, "GPIO_90"), 217 PINCTRL_PIN(91, "GPIO_91"), 218 PINCTRL_PIN(92, "GPIO_92"), 219 PINCTRL_PIN(93, "GPIO_93"), 220 PINCTRL_PIN(94, "GPIO_94"), 221 PINCTRL_PIN(95, "GPIO_95"), 222 PINCTRL_PIN(96, "GPIO_96"), 223 PINCTRL_PIN(97, "GPIO_97"), 224 PINCTRL_PIN(98, "GPIO_98"), 225 PINCTRL_PIN(99, "GPIO_99"), 226 PINCTRL_PIN(100, "GPIO_100"), 227 PINCTRL_PIN(101, "GPIO_101"), 228 PINCTRL_PIN(102, "GPIO_102"), 229 PINCTRL_PIN(103, "GPIO_103"), 230 PINCTRL_PIN(104, "GPIO_104"), 231 PINCTRL_PIN(105, "GPIO_105"), 232 PINCTRL_PIN(106, "GPIO_106"), 233 PINCTRL_PIN(107, "GPIO_107"), 234 PINCTRL_PIN(108, "GPIO_108"), 235 PINCTRL_PIN(109, "GPIO_109"), 236 PINCTRL_PIN(110, "GPIO_110"), 237 PINCTRL_PIN(111, "GPIO_111"), 238 PINCTRL_PIN(112, "GPIO_112"), 239 PINCTRL_PIN(113, "GPIO_113"), 240 PINCTRL_PIN(114, "GPIO_114"), 241 PINCTRL_PIN(115, "GPIO_115"), 242 PINCTRL_PIN(116, "GPIO_116"), 243 PINCTRL_PIN(117, "GPIO_117"), 244 PINCTRL_PIN(118, "GPIO_118"), 245 PINCTRL_PIN(119, "GPIO_119"), 246 PINCTRL_PIN(120, "GPIO_120"), 247 PINCTRL_PIN(121, "GPIO_121"), 248 PINCTRL_PIN(122, "GPIO_122"), 249 PINCTRL_PIN(123, "GPIO_123"), 250 PINCTRL_PIN(124, "GPIO_124"), 251 PINCTRL_PIN(125, "GPIO_125"), 252 PINCTRL_PIN(126, "GPIO_126"), 253 PINCTRL_PIN(127, "GPIO_127"), 254 PINCTRL_PIN(128, "GPIO_128"), 255 PINCTRL_PIN(129, "GPIO_129"), 256 PINCTRL_PIN(130, "GPIO_130"), 257 PINCTRL_PIN(131, "GPIO_131"), 258 PINCTRL_PIN(132, "GPIO_132"), 259 PINCTRL_PIN(133, "GPIO_133"), 260 PINCTRL_PIN(134, "GPIO_134"), 261 PINCTRL_PIN(135, "GPIO_135"), 262 PINCTRL_PIN(136, "GPIO_136"), 263 PINCTRL_PIN(137, "GPIO_137"), 264 PINCTRL_PIN(138, "GPIO_138"), 265 PINCTRL_PIN(139, "GPIO_139"), 266 PINCTRL_PIN(140, "GPIO_140"), 267 PINCTRL_PIN(141, "GPIO_141"), 268 PINCTRL_PIN(142, "GPIO_142"), 269 PINCTRL_PIN(143, "GPIO_143"), 270 PINCTRL_PIN(144, "GPIO_144"), 271 PINCTRL_PIN(145, "GPIO_145"), 272 PINCTRL_PIN(146, "GPIO_146"), 273 PINCTRL_PIN(147, "GPIO_147"), 274 PINCTRL_PIN(148, "GPIO_148"), 275 PINCTRL_PIN(149, "UFS_RESET"), 276 PINCTRL_PIN(150, "SDC1_RCLK"), 277 PINCTRL_PIN(151, "SDC1_CLK"), 278 PINCTRL_PIN(152, "SDC1_CMD"), 279 PINCTRL_PIN(153, "SDC1_DATA"), 280 }; 281 282 #define DECLARE_MSM_GPIO_PINS(pin) \ 283 static const unsigned int gpio##pin##_pins[] = { pin } 284 DECLARE_MSM_GPIO_PINS(0); 285 DECLARE_MSM_GPIO_PINS(1); 286 DECLARE_MSM_GPIO_PINS(2); 287 DECLARE_MSM_GPIO_PINS(3); 288 DECLARE_MSM_GPIO_PINS(4); 289 DECLARE_MSM_GPIO_PINS(5); 290 DECLARE_MSM_GPIO_PINS(6); 291 DECLARE_MSM_GPIO_PINS(7); 292 DECLARE_MSM_GPIO_PINS(8); 293 DECLARE_MSM_GPIO_PINS(9); 294 DECLARE_MSM_GPIO_PINS(10); 295 DECLARE_MSM_GPIO_PINS(11); 296 DECLARE_MSM_GPIO_PINS(12); 297 DECLARE_MSM_GPIO_PINS(13); 298 DECLARE_MSM_GPIO_PINS(14); 299 DECLARE_MSM_GPIO_PINS(15); 300 DECLARE_MSM_GPIO_PINS(16); 301 DECLARE_MSM_GPIO_PINS(17); 302 DECLARE_MSM_GPIO_PINS(18); 303 DECLARE_MSM_GPIO_PINS(19); 304 DECLARE_MSM_GPIO_PINS(20); 305 DECLARE_MSM_GPIO_PINS(21); 306 DECLARE_MSM_GPIO_PINS(22); 307 DECLARE_MSM_GPIO_PINS(23); 308 DECLARE_MSM_GPIO_PINS(24); 309 DECLARE_MSM_GPIO_PINS(25); 310 DECLARE_MSM_GPIO_PINS(26); 311 DECLARE_MSM_GPIO_PINS(27); 312 DECLARE_MSM_GPIO_PINS(28); 313 DECLARE_MSM_GPIO_PINS(29); 314 DECLARE_MSM_GPIO_PINS(30); 315 DECLARE_MSM_GPIO_PINS(31); 316 DECLARE_MSM_GPIO_PINS(32); 317 DECLARE_MSM_GPIO_PINS(33); 318 DECLARE_MSM_GPIO_PINS(34); 319 DECLARE_MSM_GPIO_PINS(35); 320 DECLARE_MSM_GPIO_PINS(36); 321 DECLARE_MSM_GPIO_PINS(37); 322 DECLARE_MSM_GPIO_PINS(38); 323 DECLARE_MSM_GPIO_PINS(39); 324 DECLARE_MSM_GPIO_PINS(40); 325 DECLARE_MSM_GPIO_PINS(41); 326 DECLARE_MSM_GPIO_PINS(42); 327 DECLARE_MSM_GPIO_PINS(43); 328 DECLARE_MSM_GPIO_PINS(44); 329 DECLARE_MSM_GPIO_PINS(45); 330 DECLARE_MSM_GPIO_PINS(46); 331 DECLARE_MSM_GPIO_PINS(47); 332 DECLARE_MSM_GPIO_PINS(48); 333 DECLARE_MSM_GPIO_PINS(49); 334 DECLARE_MSM_GPIO_PINS(50); 335 DECLARE_MSM_GPIO_PINS(51); 336 DECLARE_MSM_GPIO_PINS(52); 337 DECLARE_MSM_GPIO_PINS(53); 338 DECLARE_MSM_GPIO_PINS(54); 339 DECLARE_MSM_GPIO_PINS(55); 340 DECLARE_MSM_GPIO_PINS(56); 341 DECLARE_MSM_GPIO_PINS(57); 342 DECLARE_MSM_GPIO_PINS(58); 343 DECLARE_MSM_GPIO_PINS(59); 344 DECLARE_MSM_GPIO_PINS(60); 345 DECLARE_MSM_GPIO_PINS(61); 346 DECLARE_MSM_GPIO_PINS(62); 347 DECLARE_MSM_GPIO_PINS(63); 348 DECLARE_MSM_GPIO_PINS(64); 349 DECLARE_MSM_GPIO_PINS(65); 350 DECLARE_MSM_GPIO_PINS(66); 351 DECLARE_MSM_GPIO_PINS(67); 352 DECLARE_MSM_GPIO_PINS(68); 353 DECLARE_MSM_GPIO_PINS(69); 354 DECLARE_MSM_GPIO_PINS(70); 355 DECLARE_MSM_GPIO_PINS(71); 356 DECLARE_MSM_GPIO_PINS(72); 357 DECLARE_MSM_GPIO_PINS(73); 358 DECLARE_MSM_GPIO_PINS(74); 359 DECLARE_MSM_GPIO_PINS(75); 360 DECLARE_MSM_GPIO_PINS(76); 361 DECLARE_MSM_GPIO_PINS(77); 362 DECLARE_MSM_GPIO_PINS(78); 363 DECLARE_MSM_GPIO_PINS(79); 364 DECLARE_MSM_GPIO_PINS(80); 365 DECLARE_MSM_GPIO_PINS(81); 366 DECLARE_MSM_GPIO_PINS(82); 367 DECLARE_MSM_GPIO_PINS(83); 368 DECLARE_MSM_GPIO_PINS(84); 369 DECLARE_MSM_GPIO_PINS(85); 370 DECLARE_MSM_GPIO_PINS(86); 371 DECLARE_MSM_GPIO_PINS(87); 372 DECLARE_MSM_GPIO_PINS(88); 373 DECLARE_MSM_GPIO_PINS(89); 374 DECLARE_MSM_GPIO_PINS(90); 375 DECLARE_MSM_GPIO_PINS(91); 376 DECLARE_MSM_GPIO_PINS(92); 377 DECLARE_MSM_GPIO_PINS(93); 378 DECLARE_MSM_GPIO_PINS(94); 379 DECLARE_MSM_GPIO_PINS(95); 380 DECLARE_MSM_GPIO_PINS(96); 381 DECLARE_MSM_GPIO_PINS(97); 382 DECLARE_MSM_GPIO_PINS(98); 383 DECLARE_MSM_GPIO_PINS(99); 384 DECLARE_MSM_GPIO_PINS(100); 385 DECLARE_MSM_GPIO_PINS(101); 386 DECLARE_MSM_GPIO_PINS(102); 387 DECLARE_MSM_GPIO_PINS(103); 388 DECLARE_MSM_GPIO_PINS(104); 389 DECLARE_MSM_GPIO_PINS(105); 390 DECLARE_MSM_GPIO_PINS(106); 391 DECLARE_MSM_GPIO_PINS(107); 392 DECLARE_MSM_GPIO_PINS(108); 393 DECLARE_MSM_GPIO_PINS(109); 394 DECLARE_MSM_GPIO_PINS(110); 395 DECLARE_MSM_GPIO_PINS(111); 396 DECLARE_MSM_GPIO_PINS(112); 397 DECLARE_MSM_GPIO_PINS(113); 398 DECLARE_MSM_GPIO_PINS(114); 399 DECLARE_MSM_GPIO_PINS(115); 400 DECLARE_MSM_GPIO_PINS(116); 401 DECLARE_MSM_GPIO_PINS(117); 402 DECLARE_MSM_GPIO_PINS(118); 403 DECLARE_MSM_GPIO_PINS(119); 404 DECLARE_MSM_GPIO_PINS(120); 405 DECLARE_MSM_GPIO_PINS(121); 406 DECLARE_MSM_GPIO_PINS(122); 407 DECLARE_MSM_GPIO_PINS(123); 408 DECLARE_MSM_GPIO_PINS(124); 409 DECLARE_MSM_GPIO_PINS(125); 410 DECLARE_MSM_GPIO_PINS(126); 411 DECLARE_MSM_GPIO_PINS(127); 412 DECLARE_MSM_GPIO_PINS(128); 413 DECLARE_MSM_GPIO_PINS(129); 414 DECLARE_MSM_GPIO_PINS(130); 415 DECLARE_MSM_GPIO_PINS(131); 416 DECLARE_MSM_GPIO_PINS(132); 417 DECLARE_MSM_GPIO_PINS(133); 418 DECLARE_MSM_GPIO_PINS(134); 419 DECLARE_MSM_GPIO_PINS(135); 420 DECLARE_MSM_GPIO_PINS(136); 421 DECLARE_MSM_GPIO_PINS(137); 422 DECLARE_MSM_GPIO_PINS(138); 423 DECLARE_MSM_GPIO_PINS(139); 424 DECLARE_MSM_GPIO_PINS(140); 425 DECLARE_MSM_GPIO_PINS(141); 426 DECLARE_MSM_GPIO_PINS(142); 427 DECLARE_MSM_GPIO_PINS(143); 428 DECLARE_MSM_GPIO_PINS(144); 429 DECLARE_MSM_GPIO_PINS(145); 430 DECLARE_MSM_GPIO_PINS(146); 431 DECLARE_MSM_GPIO_PINS(147); 432 DECLARE_MSM_GPIO_PINS(148); 433 434 static const unsigned int ufs_reset_pins[] = { 149 }; 435 static const unsigned int sdc1_rclk_pins[] = { 150 }; 436 static const unsigned int sdc1_clk_pins[] = { 151 }; 437 static const unsigned int sdc1_cmd_pins[] = { 152 }; 438 static const unsigned int sdc1_data_pins[] = { 153 }; 439 440 enum sa8775p_functions { 441 msm_mux_gpio, 442 msm_mux_atest_char, 443 msm_mux_atest_usb2, 444 msm_mux_audio_ref, 445 msm_mux_cam_mclk, 446 msm_mux_cci_async, 447 msm_mux_cci_i2c, 448 msm_mux_cci_timer0, 449 msm_mux_cci_timer1, 450 msm_mux_cci_timer2, 451 msm_mux_cci_timer3, 452 msm_mux_cci_timer4, 453 msm_mux_cci_timer5, 454 msm_mux_cci_timer6, 455 msm_mux_cci_timer7, 456 msm_mux_cci_timer8, 457 msm_mux_cci_timer9, 458 msm_mux_cri_trng, 459 msm_mux_cri_trng0, 460 msm_mux_cri_trng1, 461 msm_mux_dbg_out, 462 msm_mux_ddr_bist, 463 msm_mux_ddr_pxi0, 464 msm_mux_ddr_pxi1, 465 msm_mux_ddr_pxi2, 466 msm_mux_ddr_pxi3, 467 msm_mux_ddr_pxi4, 468 msm_mux_ddr_pxi5, 469 msm_mux_edp0_hot, 470 msm_mux_edp0_lcd, 471 msm_mux_edp1_hot, 472 msm_mux_edp1_lcd, 473 msm_mux_edp2_hot, 474 msm_mux_edp2_lcd, 475 msm_mux_edp3_hot, 476 msm_mux_edp3_lcd, 477 msm_mux_emac0_mcg0, 478 msm_mux_emac0_mcg1, 479 msm_mux_emac0_mcg2, 480 msm_mux_emac0_mcg3, 481 msm_mux_emac0_mdc, 482 msm_mux_emac0_mdio, 483 msm_mux_emac0_ptp_aux, 484 msm_mux_emac0_ptp_pps, 485 msm_mux_emac1_mcg0, 486 msm_mux_emac1_mcg1, 487 msm_mux_emac1_mcg2, 488 msm_mux_emac1_mcg3, 489 msm_mux_emac1_mdc, 490 msm_mux_emac1_mdio, 491 msm_mux_emac1_ptp_aux, 492 msm_mux_emac1_ptp_pps, 493 msm_mux_gcc_gp1, 494 msm_mux_gcc_gp2, 495 msm_mux_gcc_gp3, 496 msm_mux_gcc_gp4, 497 msm_mux_gcc_gp5, 498 msm_mux_hs0_mi2s, 499 msm_mux_hs1_mi2s, 500 msm_mux_hs2_mi2s, 501 msm_mux_ibi_i3c, 502 msm_mux_jitter_bist, 503 msm_mux_mdp0_vsync0, 504 msm_mux_mdp0_vsync1, 505 msm_mux_mdp0_vsync2, 506 msm_mux_mdp0_vsync3, 507 msm_mux_mdp0_vsync4, 508 msm_mux_mdp0_vsync5, 509 msm_mux_mdp0_vsync6, 510 msm_mux_mdp0_vsync7, 511 msm_mux_mdp0_vsync8, 512 msm_mux_mdp1_vsync0, 513 msm_mux_mdp1_vsync1, 514 msm_mux_mdp1_vsync2, 515 msm_mux_mdp1_vsync3, 516 msm_mux_mdp1_vsync4, 517 msm_mux_mdp1_vsync5, 518 msm_mux_mdp1_vsync6, 519 msm_mux_mdp1_vsync7, 520 msm_mux_mdp1_vsync8, 521 msm_mux_mdp_vsync, 522 msm_mux_mi2s1_data0, 523 msm_mux_mi2s1_data1, 524 msm_mux_mi2s1_sck, 525 msm_mux_mi2s1_ws, 526 msm_mux_mi2s2_data0, 527 msm_mux_mi2s2_data1, 528 msm_mux_mi2s2_sck, 529 msm_mux_mi2s2_ws, 530 msm_mux_mi2s_mclk0, 531 msm_mux_mi2s_mclk1, 532 msm_mux_pcie0_clkreq, 533 msm_mux_pcie1_clkreq, 534 msm_mux_phase_flag, 535 msm_mux_pll_bist, 536 msm_mux_pll_clk, 537 msm_mux_prng_rosc0, 538 msm_mux_prng_rosc1, 539 msm_mux_prng_rosc2, 540 msm_mux_prng_rosc3, 541 msm_mux_qdss_cti, 542 msm_mux_qdss_gpio, 543 msm_mux_qup0_se0, 544 msm_mux_qup0_se1, 545 msm_mux_qup0_se2, 546 msm_mux_qup0_se3, 547 msm_mux_qup0_se4, 548 msm_mux_qup0_se5, 549 msm_mux_qup1_se0, 550 msm_mux_qup1_se1, 551 msm_mux_qup1_se2, 552 msm_mux_qup1_se3, 553 msm_mux_qup1_se4, 554 msm_mux_qup1_se5, 555 msm_mux_qup1_se6, 556 msm_mux_qup2_se0, 557 msm_mux_qup2_se1, 558 msm_mux_qup2_se2, 559 msm_mux_qup2_se3, 560 msm_mux_qup2_se4, 561 msm_mux_qup2_se5, 562 msm_mux_qup2_se6, 563 msm_mux_qup3_se0, 564 msm_mux_sail_top, 565 msm_mux_sailss_emac0, 566 msm_mux_sailss_ospi, 567 msm_mux_sgmii_phy, 568 msm_mux_tb_trig, 569 msm_mux_tgu_ch0, 570 msm_mux_tgu_ch1, 571 msm_mux_tgu_ch2, 572 msm_mux_tgu_ch3, 573 msm_mux_tgu_ch4, 574 msm_mux_tgu_ch5, 575 msm_mux_tsense_pwm1, 576 msm_mux_tsense_pwm2, 577 msm_mux_tsense_pwm3, 578 msm_mux_tsense_pwm4, 579 msm_mux_usb2phy_ac, 580 msm_mux_vsense_trigger, 581 msm_mux__, 582 }; 583 584 static const char * const gpio_groups[] = { 585 "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", 586 "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", 587 "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", 588 "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", 589 "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", 590 "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", 591 "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", 592 "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", 593 "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", 594 "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", 595 "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", 596 "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", 597 "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", 598 "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", 599 "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", 600 "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", 601 "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116", 602 "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122", 603 "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128", 604 "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134", 605 "gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140", 606 "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146", 607 "gpio147", "gpio148", 608 }; 609 610 static const char * const atest_char_groups[] = { 611 "gpio27", "gpio58", "gpio59", "gpio89", "gpio90", 612 }; 613 614 static const char * const atest_usb2_groups[] = { 615 "gpio58", "gpio59", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", 616 "gpio91", "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", 617 "gpio105", 618 }; 619 620 static const char * const audio_ref_groups[] = { 621 "gpio113", 622 }; 623 624 static const char * const cam_mclk_groups[] = { 625 "gpio72", "gpio73", "gpio74", "gpio75", 626 }; 627 628 static const char * const cci_async_groups[] = { 629 "gpio50", "gpio66", "gpio68", "gpio69", "gpio70", "gpio71", 630 }; 631 632 static const char * const cci_i2c_groups[] = { 633 "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", "gpio57", "gpio58", 634 "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", "gpio64", "gpio65", 635 "gpio66", "gpio67", 636 }; 637 638 static const char * const cci_timer0_groups[] = { 639 "gpio68", 640 }; 641 642 static const char * const cci_timer1_groups[] = { 643 "gpio69", 644 }; 645 646 static const char * const cci_timer2_groups[] = { 647 "gpio70", 648 }; 649 650 static const char * const cci_timer3_groups[] = { 651 "gpio71", 652 }; 653 654 static const char * const cci_timer4_groups[] = { 655 "gpio52", 656 }; 657 658 static const char * const cci_timer5_groups[] = { 659 "gpio53", 660 }; 661 662 static const char * const cci_timer6_groups[] = { 663 "gpio54", 664 }; 665 666 static const char * const cci_timer7_groups[] = { 667 "gpio55", 668 }; 669 670 static const char * const cci_timer8_groups[] = { 671 "gpio56", 672 }; 673 674 static const char * const cci_timer9_groups[] = { 675 "gpio57", 676 }; 677 678 static const char * const cri_trng_groups[] = { 679 "gpio99", 680 }; 681 682 static const char * const cri_trng0_groups[] = { 683 "gpio97", 684 }; 685 686 static const char * const cri_trng1_groups[] = { 687 "gpio98", 688 }; 689 690 static const char * const dbg_out_groups[] = { 691 "gpio144", 692 }; 693 694 static const char * const ddr_bist_groups[] = { 695 "gpio56", "gpio57", "gpio58", "gpio59", 696 }; 697 698 static const char * const ddr_pxi0_groups[] = { 699 "gpio33", "gpio34", 700 }; 701 702 static const char * const ddr_pxi1_groups[] = { 703 "gpio52", "gpio53", 704 }; 705 706 static const char * const ddr_pxi2_groups[] = { 707 "gpio55", "gpio86", 708 }; 709 710 static const char * const ddr_pxi3_groups[] = { 711 "gpio87", "gpio88", 712 }; 713 714 static const char * const ddr_pxi4_groups[] = { 715 "gpio89", "gpio90", 716 }; 717 718 static const char * const ddr_pxi5_groups[] = { 719 "gpio118", "gpio119", 720 }; 721 722 static const char * const edp0_hot_groups[] = { 723 "gpio101", 724 }; 725 726 static const char * const edp0_lcd_groups[] = { 727 "gpio44", 728 }; 729 730 static const char * const edp1_hot_groups[] = { 731 "gpio102", 732 }; 733 734 static const char * const edp1_lcd_groups[] = { 735 "gpio45", 736 }; 737 738 static const char * const edp2_hot_groups[] = { 739 "gpio104", 740 }; 741 742 static const char * const edp2_lcd_groups[] = { 743 "gpio48", 744 }; 745 746 static const char * const edp3_hot_groups[] = { 747 "gpio103", 748 }; 749 750 static const char * const edp3_lcd_groups[] = { 751 "gpio49", 752 }; 753 754 static const char * const emac0_mcg0_groups[] = { 755 "gpio12", 756 }; 757 758 static const char * const emac0_mcg1_groups[] = { 759 "gpio13", 760 }; 761 762 static const char * const emac0_mcg2_groups[] = { 763 "gpio14", 764 }; 765 766 static const char * const emac0_mcg3_groups[] = { 767 "gpio15", 768 }; 769 770 static const char * const emac0_mdc_groups[] = { 771 "gpio8", 772 }; 773 774 static const char * const emac0_mdio_groups[] = { 775 "gpio9", 776 }; 777 778 static const char * const emac0_ptp_aux_groups[] = { 779 "gpio6", "gpio10", "gpio11", "gpio12", 780 }; 781 782 static const char * const emac0_ptp_pps_groups[] = { 783 "gpio6", "gpio10", "gpio11", "gpio12", 784 }; 785 786 static const char * const emac1_mcg0_groups[] = { 787 "gpio16", 788 789 }; 790 791 static const char * const emac1_mcg1_groups[] = { 792 "gpio17", 793 }; 794 795 static const char * const emac1_mcg2_groups[] = { 796 "gpio18", 797 }; 798 799 static const char * const emac1_mcg3_groups[] = { 800 "gpio19", 801 }; 802 803 static const char * const emac1_mdc_groups[] = { 804 "gpio20", 805 }; 806 807 static const char * const emac1_mdio_groups[] = { 808 "gpio21", 809 }; 810 811 static const char * const emac1_ptp_aux_groups[] = { 812 "gpio6", "gpio10", "gpio11", "gpio12", 813 }; 814 815 static const char * const emac1_ptp_pps_groups[] = { 816 "gpio6", "gpio10", "gpio11", "gpio12", 817 }; 818 819 static const char * const gcc_gp1_groups[] = { 820 "gpio51", "gpio82", 821 }; 822 823 static const char * const gcc_gp2_groups[] = { 824 "gpio52", "gpio83", 825 }; 826 827 static const char * const gcc_gp3_groups[] = { 828 "gpio53", "gpio84", 829 }; 830 831 static const char * const gcc_gp4_groups[] = { 832 "gpio33", "gpio55", 833 }; 834 835 static const char * const gcc_gp5_groups[] = { 836 "gpio34", "gpio42", 837 }; 838 839 static const char * const hs0_mi2s_groups[] = { 840 "gpio114", "gpio115", "gpio116", "gpio117", 841 }; 842 843 static const char * const hs1_mi2s_groups[] = { 844 "gpio118", "gpio119", "gpio120", "gpio121", 845 }; 846 847 static const char * const hs2_mi2s_groups[] = { 848 "gpio122", "gpio123", "gpio124", "gpio125", 849 }; 850 851 static const char * const ibi_i3c_groups[] = { 852 "gpio40", "gpio41", "gpio42", "gpio43", "gpio80", "gpio81", "gpio84", 853 "gpio85", 854 }; 855 856 static const char * const jitter_bist_groups[] = { 857 "gpio86", 858 }; 859 860 static const char * const mdp0_vsync0_groups[] = { 861 "gpio57", 862 }; 863 864 static const char * const mdp0_vsync1_groups[] = { 865 "gpio58", 866 }; 867 868 static const char * const mdp0_vsync2_groups[] = { 869 "gpio59", 870 }; 871 872 static const char * const mdp0_vsync3_groups[] = { 873 "gpio80", 874 }; 875 876 static const char * const mdp0_vsync4_groups[] = { 877 "gpio81", 878 }; 879 880 static const char * const mdp0_vsync5_groups[] = { 881 "gpio91", 882 }; 883 884 static const char * const mdp0_vsync6_groups[] = { 885 "gpio92", 886 }; 887 888 static const char * const mdp0_vsync7_groups[] = { 889 "gpio93", 890 }; 891 892 static const char * const mdp0_vsync8_groups[] = { 893 "gpio94", 894 }; 895 896 static const char * const mdp1_vsync0_groups[] = { 897 "gpio40", 898 }; 899 900 static const char * const mdp1_vsync1_groups[] = { 901 "gpio41", 902 }; 903 904 static const char * const mdp1_vsync2_groups[] = { 905 "gpio42", 906 }; 907 908 static const char * const mdp1_vsync3_groups[] = { 909 "gpio43", 910 }; 911 912 static const char * const mdp1_vsync4_groups[] = { 913 "gpio46", 914 }; 915 916 static const char * const mdp1_vsync5_groups[] = { 917 "gpio47", 918 }; 919 920 static const char * const mdp1_vsync6_groups[] = { 921 "gpio51", 922 }; 923 924 static const char * const mdp1_vsync7_groups[] = { 925 "gpio52", 926 }; 927 928 static const char * const mdp1_vsync8_groups[] = { 929 "gpio50", 930 }; 931 932 static const char * const mdp_vsync_groups[] = { 933 "gpio82", "gpio83", "gpio84", 934 }; 935 936 static const char * const mi2s1_data0_groups[] = { 937 "gpio108", 938 }; 939 940 static const char * const mi2s1_data1_groups[] = { 941 "gpio109", 942 }; 943 944 static const char * const mi2s1_sck_groups[] = { 945 "gpio106", 946 }; 947 948 static const char * const mi2s1_ws_groups[] = { 949 "gpio107", 950 }; 951 952 static const char * const mi2s2_data0_groups[] = { 953 "gpio112", 954 }; 955 956 static const char * const mi2s2_data1_groups[] = { 957 "gpio113", 958 }; 959 960 static const char * const mi2s2_sck_groups[] = { 961 "gpio110", 962 }; 963 964 static const char * const mi2s2_ws_groups[] = { 965 "gpio111", 966 }; 967 968 static const char * const mi2s_mclk0_groups[] = { 969 "gpio105", 970 }; 971 972 static const char * const mi2s_mclk1_groups[] = { 973 "gpio117", 974 }; 975 976 static const char * const pcie0_clkreq_groups[] = { 977 "gpio1", 978 }; 979 980 static const char * const pcie1_clkreq_groups[] = { 981 "gpio3", 982 }; 983 984 static const char * const phase_flag_groups[] = { 985 "gpio25", "gpio26", "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", 986 "gpio32", "gpio35", "gpio36", "gpio37", "gpio38", "gpio39", "gpio56", 987 "gpio57", "gpio98", "gpio99", "gpio106", "gpio107", "gpio108", 988 "gpio109", "gpio110", "gpio111", "gpio112", "gpio113", "gpio114", 989 "gpio120", "gpio121", "gpio122", "gpio123", "gpio124", "gpio125", 990 }; 991 992 static const char * const pll_bist_groups[] = { 993 "gpio114", 994 }; 995 996 static const char * const pll_clk_groups[] = { 997 "gpio87", 998 }; 999 1000 static const char * const prng_rosc0_groups[] = { 1001 "gpio101", 1002 }; 1003 1004 static const char * const prng_rosc1_groups[] = { 1005 "gpio102", 1006 }; 1007 1008 static const char * const prng_rosc2_groups[] = { 1009 "gpio103", 1010 }; 1011 1012 static const char * const prng_rosc3_groups[] = { 1013 "gpio104", 1014 }; 1015 1016 static const char * const qdss_cti_groups[] = { 1017 "gpio26", "gpio27", "gpio38", "gpio39", "gpio48", "gpio49", "gpio50", 1018 "gpio51", 1019 }; 1020 1021 static const char * const qdss_gpio_groups[] = { 1022 "gpio20", "gpio21", "gpio22", "gpio23", "gpio24", "gpio25", "gpio28", 1023 "gpio29", "gpio30", "gpio31", "gpio60", "gpio61", "gpio62", "gpio63", 1024 "gpio64", "gpio65", "gpio66", "gpio67", "gpio105", "gpio106", "gpio107", 1025 "gpio108", "gpio109", "gpio110", "gpio111", "gpio112", "gpio113", 1026 "gpio114", "gpio115", "gpio116", "gpio117", "gpio118", "gpio119", 1027 "gpio120", "gpio121", "gpio122", 1028 }; 1029 1030 static const char * const qup0_se0_groups[] = { 1031 "gpio20", "gpio21", "gpio22", "gpio23", 1032 }; 1033 1034 static const char * const qup0_se1_groups[] = { 1035 "gpio24", "gpio25", "gpio26", "gpio27", 1036 }; 1037 1038 static const char * const qup0_se2_groups[] = { 1039 "gpio36", "gpio37", "gpio38", "gpio39", 1040 }; 1041 1042 static const char * const qup0_se3_groups[] = { 1043 "gpio28", "gpio29", "gpio30", "gpio31", 1044 }; 1045 1046 static const char * const qup0_se4_groups[] = { 1047 "gpio32", "gpio33", "gpio34", "gpio35", 1048 }; 1049 1050 static const char * const qup0_se5_groups[] = { 1051 "gpio36", "gpio37", "gpio38", "gpio39", 1052 }; 1053 1054 static const char * const qup1_se0_groups[] = { 1055 "gpio40", "gpio41", "gpio42", "gpio43", 1056 }; 1057 1058 static const char * const qup1_se1_groups[] = { 1059 "gpio40", "gpio41", "gpio42", "gpio43", 1060 }; 1061 1062 static const char * const qup1_se2_groups[] = { 1063 "gpio44", "gpio45", "gpio46", "gpio47", 1064 }; 1065 1066 static const char * const qup1_se3_groups[] = { 1067 "gpio44", "gpio45", "gpio46", "gpio47", 1068 }; 1069 1070 static const char * const qup1_se4_groups[] = { 1071 "gpio48", "gpio49", "gpio50", "gpio51", 1072 }; 1073 1074 static const char * const qup1_se5_groups[] = { 1075 "gpio52", "gpio53", "gpio54", "gpio55", 1076 }; 1077 1078 static const char * const qup1_se6_groups[] = { 1079 "gpio56", "gpio56", "gpio57", "gpio57", 1080 }; 1081 1082 static const char * const qup2_se0_groups[] = { 1083 "gpio80", "gpio81", "gpio82", "gpio83", 1084 }; 1085 1086 static const char * const qup2_se1_groups[] = { 1087 "gpio84", "gpio85", "gpio99", "gpio100", 1088 }; 1089 1090 static const char * const qup2_se2_groups[] = { 1091 "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", 1092 }; 1093 1094 static const char * const qup2_se3_groups[] = { 1095 "gpio91", "gpio92", "gpio93", "gpio94", 1096 }; 1097 1098 static const char * const qup2_se4_groups[] = { 1099 "gpio95", "gpio96", "gpio97", "gpio98", 1100 }; 1101 1102 static const char * const qup2_se5_groups[] = { 1103 "gpio84", "gpio85", "gpio99", "gpio100", 1104 }; 1105 1106 static const char * const qup2_se6_groups[] = { 1107 "gpio95", "gpio96", "gpio97", "gpio98", 1108 }; 1109 1110 static const char * const qup3_se0_groups[] = { 1111 "gpio13", "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", 1112 }; 1113 1114 static const char * const sail_top_groups[] = { 1115 "gpio13", "gpio14", "gpio15", "gpio16", 1116 }; 1117 1118 static const char * const sailss_emac0_groups[] = { 1119 "gpio18", "gpio19", 1120 }; 1121 1122 static const char * const sailss_ospi_groups[] = { 1123 "gpio18", "gpio19", 1124 }; 1125 1126 static const char * const sgmii_phy_groups[] = { 1127 "gpio7", "gpio26", 1128 }; 1129 1130 static const char * const tb_trig_groups[] = { 1131 "gpio17", "gpio17", 1132 }; 1133 1134 static const char * const tgu_ch0_groups[] = { 1135 "gpio46", 1136 }; 1137 1138 static const char * const tgu_ch1_groups[] = { 1139 "gpio47", 1140 }; 1141 1142 static const char * const tgu_ch2_groups[] = { 1143 "gpio36", 1144 }; 1145 1146 static const char * const tgu_ch3_groups[] = { 1147 "gpio37", 1148 }; 1149 1150 static const char * const tgu_ch4_groups[] = { 1151 "gpio38", 1152 }; 1153 1154 static const char * const tgu_ch5_groups[] = { 1155 "gpio39", 1156 }; 1157 1158 static const char * const tsense_pwm1_groups[] = { 1159 "gpio104", 1160 }; 1161 1162 static const char * const tsense_pwm2_groups[] = { 1163 "gpio103", 1164 }; 1165 1166 static const char * const tsense_pwm3_groups[] = { 1167 "gpio102", 1168 }; 1169 1170 static const char * const tsense_pwm4_groups[] = { 1171 "gpio101", 1172 }; 1173 1174 static const char * const usb2phy_ac_groups[] = { 1175 "gpio10", "gpio11", "gpio12", 1176 }; 1177 1178 static const char * const vsense_trigger_groups[] = { 1179 "gpio111", 1180 }; 1181 1182 static const struct msm_function sa8775p_functions[] = { 1183 FUNCTION(gpio), 1184 FUNCTION(atest_char), 1185 FUNCTION(atest_usb2), 1186 FUNCTION(audio_ref), 1187 FUNCTION(cam_mclk), 1188 FUNCTION(cci_async), 1189 FUNCTION(cci_i2c), 1190 FUNCTION(cci_timer0), 1191 FUNCTION(cci_timer1), 1192 FUNCTION(cci_timer2), 1193 FUNCTION(cci_timer3), 1194 FUNCTION(cci_timer4), 1195 FUNCTION(cci_timer5), 1196 FUNCTION(cci_timer6), 1197 FUNCTION(cci_timer7), 1198 FUNCTION(cci_timer8), 1199 FUNCTION(cci_timer9), 1200 FUNCTION(cri_trng), 1201 FUNCTION(cri_trng0), 1202 FUNCTION(cri_trng1), 1203 FUNCTION(dbg_out), 1204 FUNCTION(ddr_bist), 1205 FUNCTION(ddr_pxi0), 1206 FUNCTION(ddr_pxi1), 1207 FUNCTION(ddr_pxi2), 1208 FUNCTION(ddr_pxi3), 1209 FUNCTION(ddr_pxi4), 1210 FUNCTION(ddr_pxi5), 1211 FUNCTION(edp0_hot), 1212 FUNCTION(edp0_lcd), 1213 FUNCTION(edp1_hot), 1214 FUNCTION(edp1_lcd), 1215 FUNCTION(edp2_hot), 1216 FUNCTION(edp2_lcd), 1217 FUNCTION(edp3_hot), 1218 FUNCTION(edp3_lcd), 1219 FUNCTION(emac0_mcg0), 1220 FUNCTION(emac0_mcg1), 1221 FUNCTION(emac0_mcg2), 1222 FUNCTION(emac0_mcg3), 1223 FUNCTION(emac0_mdc), 1224 FUNCTION(emac0_mdio), 1225 FUNCTION(emac0_ptp_aux), 1226 FUNCTION(emac0_ptp_pps), 1227 FUNCTION(emac1_mcg0), 1228 FUNCTION(emac1_mcg1), 1229 FUNCTION(emac1_mcg2), 1230 FUNCTION(emac1_mcg3), 1231 FUNCTION(emac1_mdc), 1232 FUNCTION(emac1_mdio), 1233 FUNCTION(emac1_ptp_aux), 1234 FUNCTION(emac1_ptp_pps), 1235 FUNCTION(gcc_gp1), 1236 FUNCTION(gcc_gp2), 1237 FUNCTION(gcc_gp3), 1238 FUNCTION(gcc_gp4), 1239 FUNCTION(gcc_gp5), 1240 FUNCTION(hs0_mi2s), 1241 FUNCTION(hs1_mi2s), 1242 FUNCTION(hs2_mi2s), 1243 FUNCTION(ibi_i3c), 1244 FUNCTION(jitter_bist), 1245 FUNCTION(mdp0_vsync0), 1246 FUNCTION(mdp0_vsync1), 1247 FUNCTION(mdp0_vsync2), 1248 FUNCTION(mdp0_vsync3), 1249 FUNCTION(mdp0_vsync4), 1250 FUNCTION(mdp0_vsync5), 1251 FUNCTION(mdp0_vsync6), 1252 FUNCTION(mdp0_vsync7), 1253 FUNCTION(mdp0_vsync8), 1254 FUNCTION(mdp1_vsync0), 1255 FUNCTION(mdp1_vsync1), 1256 FUNCTION(mdp1_vsync2), 1257 FUNCTION(mdp1_vsync3), 1258 FUNCTION(mdp1_vsync4), 1259 FUNCTION(mdp1_vsync5), 1260 FUNCTION(mdp1_vsync6), 1261 FUNCTION(mdp1_vsync7), 1262 FUNCTION(mdp1_vsync8), 1263 FUNCTION(mdp_vsync), 1264 FUNCTION(mi2s1_data0), 1265 FUNCTION(mi2s1_data1), 1266 FUNCTION(mi2s1_sck), 1267 FUNCTION(mi2s1_ws), 1268 FUNCTION(mi2s2_data0), 1269 FUNCTION(mi2s2_data1), 1270 FUNCTION(mi2s2_sck), 1271 FUNCTION(mi2s2_ws), 1272 FUNCTION(mi2s_mclk0), 1273 FUNCTION(mi2s_mclk1), 1274 FUNCTION(pcie0_clkreq), 1275 FUNCTION(pcie1_clkreq), 1276 FUNCTION(phase_flag), 1277 FUNCTION(pll_bist), 1278 FUNCTION(pll_clk), 1279 FUNCTION(prng_rosc0), 1280 FUNCTION(prng_rosc1), 1281 FUNCTION(prng_rosc2), 1282 FUNCTION(prng_rosc3), 1283 FUNCTION(qdss_cti), 1284 FUNCTION(qdss_gpio), 1285 FUNCTION(qup0_se0), 1286 FUNCTION(qup0_se1), 1287 FUNCTION(qup0_se2), 1288 FUNCTION(qup0_se3), 1289 FUNCTION(qup0_se4), 1290 FUNCTION(qup0_se5), 1291 FUNCTION(qup1_se0), 1292 FUNCTION(qup1_se1), 1293 FUNCTION(qup1_se2), 1294 FUNCTION(qup1_se3), 1295 FUNCTION(qup1_se4), 1296 FUNCTION(qup1_se5), 1297 FUNCTION(qup1_se6), 1298 FUNCTION(qup2_se0), 1299 FUNCTION(qup2_se1), 1300 FUNCTION(qup2_se2), 1301 FUNCTION(qup2_se3), 1302 FUNCTION(qup2_se4), 1303 FUNCTION(qup2_se5), 1304 FUNCTION(qup2_se6), 1305 FUNCTION(qup3_se0), 1306 FUNCTION(sail_top), 1307 FUNCTION(sailss_emac0), 1308 FUNCTION(sailss_ospi), 1309 FUNCTION(sgmii_phy), 1310 FUNCTION(tb_trig), 1311 FUNCTION(tgu_ch0), 1312 FUNCTION(tgu_ch1), 1313 FUNCTION(tgu_ch2), 1314 FUNCTION(tgu_ch3), 1315 FUNCTION(tgu_ch4), 1316 FUNCTION(tgu_ch5), 1317 FUNCTION(tsense_pwm1), 1318 FUNCTION(tsense_pwm2), 1319 FUNCTION(tsense_pwm3), 1320 FUNCTION(tsense_pwm4), 1321 FUNCTION(usb2phy_ac), 1322 FUNCTION(vsense_trigger), 1323 }; 1324 1325 /* 1326 * Every pin is maintained as a single group, and missing or non-existing pin 1327 * would be maintained as dummy group to synchronize pin group index with 1328 * pin descriptor registered with pinctrl core. 1329 * Clients would not be able to request these dummy pin groups. 1330 */ 1331 static const struct msm_pingroup sa8775p_groups[] = { 1332 [0] = PINGROUP(0, _, _, _, _, _, _, _, _, _), 1333 [1] = PINGROUP(1, pcie0_clkreq, _, _, _, _, _, _, _, _), 1334 [2] = PINGROUP(2, _, _, _, _, _, _, _, _, _), 1335 [3] = PINGROUP(3, pcie1_clkreq, _, _, _, _, _, _, _, _), 1336 [4] = PINGROUP(4, _, _, _, _, _, _, _, _, _), 1337 [5] = PINGROUP(5, _, _, _, _, _, _, _, _, _), 1338 [6] = PINGROUP(6, emac0_ptp_aux, emac0_ptp_pps, emac1_ptp_aux, emac1_ptp_pps, 1339 _, _, _, _, _), 1340 [7] = PINGROUP(7, sgmii_phy, _, _, _, _, _, _, _, _), 1341 [8] = PINGROUP(8, emac0_mdc, _, _, _, _, _, _, _, _), 1342 [9] = PINGROUP(9, emac0_mdio, _, _, _, _, _, _, _, _), 1343 [10] = PINGROUP(10, usb2phy_ac, emac0_ptp_aux, emac0_ptp_pps, emac1_ptp_aux, emac1_ptp_pps, 1344 _, _, _, _), 1345 [11] = PINGROUP(11, usb2phy_ac, emac0_ptp_aux, emac0_ptp_pps, emac1_ptp_aux, emac1_ptp_pps, 1346 _, _, _, _), 1347 [12] = PINGROUP(12, usb2phy_ac, emac0_ptp_aux, emac0_ptp_pps, emac1_ptp_aux, emac1_ptp_pps, 1348 emac0_mcg0, _, _, _), 1349 [13] = PINGROUP(13, qup3_se0, emac0_mcg1, _, _, sail_top, _, _, _, _), 1350 [14] = PINGROUP(14, qup3_se0, emac0_mcg2, _, _, sail_top, _, _, _, _), 1351 [15] = PINGROUP(15, qup3_se0, emac0_mcg3, _, _, sail_top, _, _, _, _), 1352 [16] = PINGROUP(16, qup3_se0, emac1_mcg0, _, _, sail_top, _, _, _, _), 1353 [17] = PINGROUP(17, qup3_se0, tb_trig, tb_trig, emac1_mcg1, _, _, _, _, _), 1354 [18] = PINGROUP(18, qup3_se0, emac1_mcg2, _, _, sailss_ospi, sailss_emac0, _, _, _), 1355 [19] = PINGROUP(19, qup3_se0, emac1_mcg3, _, _, sailss_ospi, sailss_emac0, _, _, _), 1356 [20] = PINGROUP(20, qup0_se0, emac1_mdc, qdss_gpio, _, _, _, _, _, _), 1357 [21] = PINGROUP(21, qup0_se0, emac1_mdio, qdss_gpio, _, _, _, _, _, _), 1358 [22] = PINGROUP(22, qup0_se0, qdss_gpio, _, _, _, _, _, _, _), 1359 [23] = PINGROUP(23, qup0_se0, qdss_gpio, _, _, _, _, _, _, _), 1360 [24] = PINGROUP(24, qup0_se1, qdss_gpio, _, _, _, _, _, _, _), 1361 [25] = PINGROUP(25, qup0_se1, phase_flag, _, qdss_gpio, _, _, _, _, _), 1362 [26] = PINGROUP(26, sgmii_phy, qup0_se1, qdss_cti, phase_flag, _, _, _, _, _), 1363 [27] = PINGROUP(27, qup0_se1, qdss_cti, phase_flag, _, atest_char, _, _, _, _), 1364 [28] = PINGROUP(28, qup0_se3, phase_flag, _, qdss_gpio, _, _, _, _, _), 1365 [29] = PINGROUP(29, qup0_se3, phase_flag, _, qdss_gpio, _, _, _, _, _), 1366 [30] = PINGROUP(30, qup0_se3, phase_flag, _, qdss_gpio, _, _, _, _, _), 1367 [31] = PINGROUP(31, qup0_se3, phase_flag, _, qdss_gpio, _, _, _, _, _), 1368 [32] = PINGROUP(32, qup0_se4, phase_flag, _, _, _, _, _, _, _), 1369 [33] = PINGROUP(33, qup0_se4, gcc_gp4, _, ddr_pxi0, _, _, _, _, _), 1370 [34] = PINGROUP(34, qup0_se4, gcc_gp5, _, ddr_pxi0, _, _, _, _, _), 1371 [35] = PINGROUP(35, qup0_se4, phase_flag, _, _, _, _, _, _, _), 1372 [36] = PINGROUP(36, qup0_se2, qup0_se5, phase_flag, tgu_ch2, _, _, _, _, _), 1373 [37] = PINGROUP(37, qup0_se2, qup0_se5, phase_flag, tgu_ch3, _, _, _, _, _), 1374 [38] = PINGROUP(38, qup0_se5, qup0_se2, qdss_cti, phase_flag, tgu_ch4, _, _, _, _), 1375 [39] = PINGROUP(39, qup0_se5, qup0_se2, qdss_cti, phase_flag, tgu_ch5, _, _, _, _), 1376 [40] = PINGROUP(40, qup1_se0, qup1_se1, ibi_i3c, mdp1_vsync0, _, _, _, _, _), 1377 [41] = PINGROUP(41, qup1_se0, qup1_se1, ibi_i3c, mdp1_vsync1, _, _, _, _, _), 1378 [42] = PINGROUP(42, qup1_se1, qup1_se0, ibi_i3c, mdp1_vsync2, gcc_gp5, _, _, _, _), 1379 [43] = PINGROUP(43, qup1_se1, qup1_se0, ibi_i3c, mdp1_vsync3, _, _, _, _, _), 1380 [44] = PINGROUP(44, qup1_se2, qup1_se3, edp0_lcd, _, _, _, _, _, _), 1381 [45] = PINGROUP(45, qup1_se2, qup1_se3, edp1_lcd, _, _, _, _, _, _), 1382 [46] = PINGROUP(46, qup1_se3, qup1_se2, mdp1_vsync4, tgu_ch0, _, _, _, _, _), 1383 [47] = PINGROUP(47, qup1_se3, qup1_se2, mdp1_vsync5, tgu_ch1, _, _, _, _, _), 1384 [48] = PINGROUP(48, qup1_se4, qdss_cti, edp2_lcd, _, _, _, _, _, _), 1385 [49] = PINGROUP(49, qup1_se4, qdss_cti, edp3_lcd, _, _, _, _, _, _), 1386 [50] = PINGROUP(50, qup1_se4, cci_async, qdss_cti, mdp1_vsync8, _, _, _, _, _), 1387 [51] = PINGROUP(51, qup1_se4, qdss_cti, mdp1_vsync6, gcc_gp1, _, _, _, _, _), 1388 [52] = PINGROUP(52, qup1_se5, cci_timer4, cci_i2c, mdp1_vsync7, gcc_gp2, _, ddr_pxi1, _, _), 1389 [53] = PINGROUP(53, qup1_se5, cci_timer5, cci_i2c, gcc_gp3, _, ddr_pxi1, _, _, _), 1390 [54] = PINGROUP(54, qup1_se5, cci_timer6, cci_i2c, _, _, _, _, _, _), 1391 [55] = PINGROUP(55, qup1_se5, cci_timer7, cci_i2c, gcc_gp4, _, ddr_pxi2, _, _, _), 1392 [56] = PINGROUP(56, qup1_se6, qup1_se6, cci_timer8, cci_i2c, phase_flag, 1393 ddr_bist, _, _, _), 1394 [57] = PINGROUP(57, qup1_se6, qup1_se6, cci_timer9, cci_i2c, mdp0_vsync0, 1395 phase_flag, ddr_bist, _, _), 1396 [58] = PINGROUP(58, cci_i2c, mdp0_vsync1, ddr_bist, _, atest_usb2, atest_char, _, _, _), 1397 [59] = PINGROUP(59, cci_i2c, mdp0_vsync2, ddr_bist, _, atest_usb2, atest_char, _, _, _), 1398 [60] = PINGROUP(60, cci_i2c, qdss_gpio, _, _, _, _, _, _, _), 1399 [61] = PINGROUP(61, cci_i2c, qdss_gpio, _, _, _, _, _, _, _), 1400 [62] = PINGROUP(62, cci_i2c, qdss_gpio, _, _, _, _, _, _, _), 1401 [63] = PINGROUP(63, cci_i2c, qdss_gpio, _, _, _, _, _, _, _), 1402 [64] = PINGROUP(64, cci_i2c, qdss_gpio, _, _, _, _, _, _, _), 1403 [65] = PINGROUP(65, cci_i2c, qdss_gpio, _, _, _, _, _, _, _), 1404 [66] = PINGROUP(66, cci_i2c, cci_async, qdss_gpio, _, _, _, _, _, _), 1405 [67] = PINGROUP(67, cci_i2c, qdss_gpio, _, _, _, _, _, _, _), 1406 [68] = PINGROUP(68, cci_timer0, cci_async, _, _, _, _, _, _, _), 1407 [69] = PINGROUP(69, cci_timer1, cci_async, _, _, _, _, _, _, _), 1408 [70] = PINGROUP(70, cci_timer2, cci_async, _, _, _, _, _, _, _), 1409 [71] = PINGROUP(71, cci_timer3, cci_async, _, _, _, _, _, _, _), 1410 [72] = PINGROUP(72, cam_mclk, _, _, _, _, _, _, _, _), 1411 [73] = PINGROUP(73, cam_mclk, _, _, _, _, _, _, _, _), 1412 [74] = PINGROUP(74, cam_mclk, _, _, _, _, _, _, _, _), 1413 [75] = PINGROUP(75, cam_mclk, _, _, _, _, _, _, _, _), 1414 [76] = PINGROUP(76, _, _, _, _, _, _, _, _, _), 1415 [77] = PINGROUP(77, _, _, _, _, _, _, _, _, _), 1416 [78] = PINGROUP(78, _, _, _, _, _, _, _, _, _), 1417 [79] = PINGROUP(79, _, _, _, _, _, _, _, _, _), 1418 [80] = PINGROUP(80, qup2_se0, ibi_i3c, mdp0_vsync3, _, _, _, _, _, _), 1419 [81] = PINGROUP(81, qup2_se0, ibi_i3c, mdp0_vsync4, _, _, _, _, _, _), 1420 [82] = PINGROUP(82, qup2_se0, mdp_vsync, gcc_gp1, _, _, _, _, _, _), 1421 [83] = PINGROUP(83, qup2_se0, mdp_vsync, gcc_gp2, _, _, _, _, _, _), 1422 [84] = PINGROUP(84, qup2_se1, qup2_se5, ibi_i3c, mdp_vsync, gcc_gp3, _, _, _, _), 1423 [85] = PINGROUP(85, qup2_se1, qup2_se5, ibi_i3c, _, _, _, _, _, _), 1424 [86] = PINGROUP(86, qup2_se2, jitter_bist, atest_usb2, ddr_pxi2, _, _, _, _, _), 1425 [87] = PINGROUP(87, qup2_se2, pll_clk, atest_usb2, ddr_pxi3, _, _, _, _, _), 1426 [88] = PINGROUP(88, qup2_se2, _, atest_usb2, ddr_pxi3, _, _, _, _, _), 1427 [89] = PINGROUP(89, qup2_se2, _, atest_usb2, ddr_pxi4, atest_char, _, _, _, _), 1428 [90] = PINGROUP(90, qup2_se2, _, atest_usb2, ddr_pxi4, atest_char, _, _, _, _), 1429 [91] = PINGROUP(91, qup2_se3, mdp0_vsync5, _, atest_usb2, _, _, _, _, _), 1430 [92] = PINGROUP(92, qup2_se3, mdp0_vsync6, _, atest_usb2, _, _, _, _, _), 1431 [93] = PINGROUP(93, qup2_se3, mdp0_vsync7, _, atest_usb2, _, _, _, _, _), 1432 [94] = PINGROUP(94, qup2_se3, mdp0_vsync8, _, atest_usb2, _, _, _, _, _), 1433 [95] = PINGROUP(95, qup2_se4, qup2_se6, _, atest_usb2, _, _, _, _, _), 1434 [96] = PINGROUP(96, qup2_se4, qup2_se6, _, atest_usb2, _, _, _, _, _), 1435 [97] = PINGROUP(97, qup2_se6, qup2_se4, cri_trng0, _, atest_usb2, _, _, _, _), 1436 [98] = PINGROUP(98, qup2_se6, qup2_se4, phase_flag, cri_trng1, _, _, _, _, _), 1437 [99] = PINGROUP(99, qup2_se5, qup2_se1, phase_flag, cri_trng, _, _, _, _, _), 1438 [100] = PINGROUP(100, qup2_se5, qup2_se1, _, _, _, _, _, _, _), 1439 [101] = PINGROUP(101, edp0_hot, prng_rosc0, tsense_pwm4, _, _, _, _, _, _), 1440 [102] = PINGROUP(102, edp1_hot, prng_rosc1, tsense_pwm3, _, _, _, _, _, _), 1441 [103] = PINGROUP(103, edp3_hot, prng_rosc2, tsense_pwm2, _, _, _, _, _, _), 1442 [104] = PINGROUP(104, edp2_hot, prng_rosc3, tsense_pwm1, _, _, _, _, _, _), 1443 [105] = PINGROUP(105, mi2s_mclk0, _, qdss_gpio, atest_usb2, _, _, _, _, _), 1444 [106] = PINGROUP(106, mi2s1_sck, phase_flag, _, qdss_gpio, _, _, _, _, _), 1445 [107] = PINGROUP(107, mi2s1_ws, phase_flag, _, qdss_gpio, _, _, _, _, _), 1446 [108] = PINGROUP(108, mi2s1_data0, phase_flag, _, qdss_gpio, _, _, _, _, _), 1447 [109] = PINGROUP(109, mi2s1_data1, phase_flag, _, qdss_gpio, _, _, _, _, _), 1448 [110] = PINGROUP(110, mi2s2_sck, phase_flag, _, qdss_gpio, _, _, _, _, _), 1449 [111] = PINGROUP(111, mi2s2_ws, phase_flag, _, qdss_gpio, vsense_trigger, _, _, _, _), 1450 [112] = PINGROUP(112, mi2s2_data0, phase_flag, _, qdss_gpio, _, _, _, _, _), 1451 [113] = PINGROUP(113, mi2s2_data1, audio_ref, phase_flag, _, qdss_gpio, _, _, _, _), 1452 [114] = PINGROUP(114, hs0_mi2s, pll_bist, phase_flag, _, qdss_gpio, _, _, _, _), 1453 [115] = PINGROUP(115, hs0_mi2s, _, qdss_gpio, _, _, _, _, _, _), 1454 [116] = PINGROUP(116, hs0_mi2s, _, qdss_gpio, _, _, _, _, _, _), 1455 [117] = PINGROUP(117, hs0_mi2s, mi2s_mclk1, _, qdss_gpio, _, _, _, _, _), 1456 [118] = PINGROUP(118, hs1_mi2s, _, qdss_gpio, ddr_pxi5, _, _, _, _, _), 1457 [119] = PINGROUP(119, hs1_mi2s, _, qdss_gpio, ddr_pxi5, _, _, _, _, _), 1458 [120] = PINGROUP(120, hs1_mi2s, phase_flag, _, qdss_gpio, _, _, _, _, _), 1459 [121] = PINGROUP(121, hs1_mi2s, phase_flag, _, qdss_gpio, _, _, _, _, _), 1460 [122] = PINGROUP(122, hs2_mi2s, phase_flag, _, qdss_gpio, _, _, _, _, _), 1461 [123] = PINGROUP(123, hs2_mi2s, phase_flag, _, _, _, _, _, _, _), 1462 [124] = PINGROUP(124, hs2_mi2s, phase_flag, _, _, _, _, _, _, _), 1463 [125] = PINGROUP(125, hs2_mi2s, phase_flag, _, _, _, _, _, _, _), 1464 [126] = PINGROUP(126, _, _, _, _, _, _, _, _, _), 1465 [127] = PINGROUP(127, _, _, _, _, _, _, _, _, _), 1466 [128] = PINGROUP(128, _, _, _, _, _, _, _, _, _), 1467 [129] = PINGROUP(129, _, _, _, _, _, _, _, _, _), 1468 [130] = PINGROUP(130, _, _, _, _, _, _, _, _, _), 1469 [131] = PINGROUP(131, _, _, _, _, _, _, _, _, _), 1470 [132] = PINGROUP(132, _, _, _, _, _, _, _, _, _), 1471 [133] = PINGROUP(133, _, _, _, _, _, _, _, _, _), 1472 [134] = PINGROUP(134, _, _, _, _, _, _, _, _, _), 1473 [135] = PINGROUP(135, _, _, _, _, _, _, _, _, _), 1474 [136] = PINGROUP(136, _, _, _, _, _, _, _, _, _), 1475 [137] = PINGROUP(137, _, _, _, _, _, _, _, _, _), 1476 [138] = PINGROUP(138, _, _, _, _, _, _, _, _, _), 1477 [139] = PINGROUP(139, _, _, _, _, _, _, _, _, _), 1478 [140] = PINGROUP(140, _, _, _, _, _, _, _, _, _), 1479 [141] = PINGROUP(141, _, _, _, _, _, _, _, _, _), 1480 [142] = PINGROUP(142, _, _, _, _, _, _, _, _, _), 1481 [143] = PINGROUP(143, _, _, _, _, _, _, _, _, _), 1482 [144] = PINGROUP(144, dbg_out, _, _, _, _, _, _, _, _), 1483 [145] = PINGROUP(145, _, _, _, _, _, _, _, _, _), 1484 [146] = PINGROUP(146, _, _, _, _, _, _, _, _, _), 1485 [147] = PINGROUP(147, _, _, _, _, _, _, _, _, _), 1486 [148] = PINGROUP(148, _, _, _, _, _, _, _, _, _), 1487 [149] = UFS_RESET(ufs_reset, 0x1a2000), 1488 [150] = SDC_QDSD_PINGROUP(sdc1_rclk, 0x199000, 15, 0), 1489 [151] = SDC_QDSD_PINGROUP(sdc1_clk, 0x199000, 13, 6), 1490 [152] = SDC_QDSD_PINGROUP(sdc1_cmd, 0x199000, 11, 3), 1491 [153] = SDC_QDSD_PINGROUP(sdc1_data, 0x199000, 9, 0), 1492 }; 1493 1494 static const struct msm_pinctrl_soc_data sa8775p_pinctrl = { 1495 .pins = sa8775p_pins, 1496 .npins = ARRAY_SIZE(sa8775p_pins), 1497 .functions = sa8775p_functions, 1498 .nfunctions = ARRAY_SIZE(sa8775p_functions), 1499 .groups = sa8775p_groups, 1500 .ngroups = ARRAY_SIZE(sa8775p_groups), 1501 .ngpios = 150, 1502 }; 1503 1504 static int sa8775p_pinctrl_probe(struct platform_device *pdev) 1505 { 1506 return msm_pinctrl_probe(pdev, &sa8775p_pinctrl); 1507 } 1508 1509 static const struct of_device_id sa8775p_pinctrl_of_match[] = { 1510 { .compatible = "qcom,sa8775p-tlmm", }, 1511 { }, 1512 }; 1513 MODULE_DEVICE_TABLE(of, sa8775p_pinctrl_of_match); 1514 1515 static struct platform_driver sa8775p_pinctrl_driver = { 1516 .driver = { 1517 .name = "sa8775p-tlmm", 1518 .of_match_table = sa8775p_pinctrl_of_match, 1519 }, 1520 .probe = sa8775p_pinctrl_probe, 1521 .remove = msm_pinctrl_remove, 1522 }; 1523 1524 static int __init sa8775p_pinctrl_init(void) 1525 { 1526 return platform_driver_register(&sa8775p_pinctrl_driver); 1527 } 1528 arch_initcall(sa8775p_pinctrl_init); 1529 1530 static void __exit sa8775p_pinctrl_exit(void) 1531 { 1532 platform_driver_unregister(&sa8775p_pinctrl_driver); 1533 } 1534 module_exit(sa8775p_pinctrl_exit); 1535 1536 MODULE_DESCRIPTION("QTI SA8775P pinctrl driver"); 1537 MODULE_LICENSE("GPL"); 1538