1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (c) 2013, Sony Mobile Communications AB.
4  */
5 #ifndef __PINCTRL_MSM_H__
6 #define __PINCTRL_MSM_H__
7 
8 #include <linux/pm.h>
9 #include <linux/types.h>
10 
11 struct platform_device;
12 
13 struct pinctrl_pin_desc;
14 
15 /**
16  * struct msm_function - a pinmux function
17  * @name:    Name of the pinmux function.
18  * @groups:  List of pingroups for this function.
19  * @ngroups: Number of entries in @groups.
20  */
21 struct msm_function {
22 	const char *name;
23 	const char * const *groups;
24 	unsigned ngroups;
25 };
26 
27 /**
28  * struct msm_pingroup - Qualcomm pingroup definition
29  * @name:                 Name of the pingroup.
30  * @pins:	          A list of pins assigned to this pingroup.
31  * @npins:	          Number of entries in @pins.
32  * @funcs:                A list of pinmux functions that can be selected for
33  *                        this group. The index of the selected function is used
34  *                        for programming the function selector.
35  *                        Entries should be indices into the groups list of the
36  *                        struct msm_pinctrl_soc_data.
37  * @ctl_reg:              Offset of the register holding control bits for this group.
38  * @io_reg:               Offset of the register holding input/output bits for this group.
39  * @intr_cfg_reg:         Offset of the register holding interrupt configuration bits.
40  * @intr_status_reg:      Offset of the register holding the status bits for this group.
41  * @intr_target_reg:      Offset of the register specifying routing of the interrupts
42  *                        from this group.
43  * @mux_bit:              Offset in @ctl_reg for the pinmux function selection.
44  * @pull_bit:             Offset in @ctl_reg for the bias configuration.
45  * @drv_bit:              Offset in @ctl_reg for the drive strength configuration.
46  * @od_bit:               Offset in @ctl_reg for controlling open drain.
47  * @oe_bit:               Offset in @ctl_reg for controlling output enable.
48  * @in_bit:               Offset in @io_reg for the input bit value.
49  * @out_bit:              Offset in @io_reg for the output bit value.
50  * @intr_enable_bit:      Offset in @intr_cfg_reg for enabling the interrupt for this group.
51  * @intr_status_bit:      Offset in @intr_status_reg for reading and acking the interrupt
52  *                        status.
53  * @intr_target_bit:      Offset in @intr_target_reg for configuring the interrupt routing.
54  * @intr_target_kpss_val: Value in @intr_target_bit for specifying that the interrupt from
55  *                        this gpio should get routed to the KPSS processor.
56  * @intr_raw_status_bit:  Offset in @intr_cfg_reg for the raw status bit.
57  * @intr_polarity_bit:    Offset in @intr_cfg_reg for specifying polarity of the interrupt.
58  * @intr_detection_bit:   Offset in @intr_cfg_reg for specifying interrupt type.
59  * @intr_detection_width: Number of bits used for specifying interrupt type,
60  *                        Should be 2 for SoCs that can detect both edges in hardware,
61  *                        otherwise 1.
62  */
63 struct msm_pingroup {
64 	const char *name;
65 	const unsigned *pins;
66 	unsigned npins;
67 
68 	unsigned *funcs;
69 	unsigned nfuncs;
70 
71 	u32 ctl_reg;
72 	u32 io_reg;
73 	u32 intr_cfg_reg;
74 	u32 intr_status_reg;
75 	u32 intr_target_reg;
76 
77 	unsigned int tile:2;
78 
79 	unsigned mux_bit:5;
80 
81 	unsigned pull_bit:5;
82 	unsigned drv_bit:5;
83 
84 	unsigned od_bit:5;
85 	unsigned egpio_enable:5;
86 	unsigned egpio_present:5;
87 	unsigned oe_bit:5;
88 	unsigned in_bit:5;
89 	unsigned out_bit:5;
90 
91 	unsigned intr_enable_bit:5;
92 	unsigned intr_status_bit:5;
93 	unsigned intr_ack_high:1;
94 
95 	unsigned intr_target_bit:5;
96 	unsigned intr_target_kpss_val:5;
97 	unsigned intr_raw_status_bit:5;
98 	unsigned intr_polarity_bit:5;
99 	unsigned intr_detection_bit:5;
100 	unsigned intr_detection_width:5;
101 };
102 
103 /**
104  * struct msm_gpio_wakeirq_map - Map of GPIOs and their wakeup pins
105  * @gpio:          The GPIOs that are wakeup capable
106  * @wakeirq:       The interrupt at the always-on interrupt controller
107  */
108 struct msm_gpio_wakeirq_map {
109 	unsigned int gpio;
110 	unsigned int wakeirq;
111 };
112 
113 /**
114  * struct msm_pinctrl_soc_data - Qualcomm pin controller driver configuration
115  * @pins:	    An array describing all pins the pin controller affects.
116  * @npins:	    The number of entries in @pins.
117  * @functions:	    An array describing all mux functions the SoC supports.
118  * @nfunctions:	    The number of entries in @functions.
119  * @groups:	    An array describing all pin groups the pin SoC supports.
120  * @ngroups:	    The numbmer of entries in @groups.
121  * @ngpio:	    The number of pingroups the driver should expose as GPIOs.
122  * @pull_no_keeper: The SoC does not support keeper bias.
123  * @wakeirq_map:    The map of wakeup capable GPIOs and the pin at PDC/MPM
124  * @nwakeirq_map:   The number of entries in @wakeirq_map
125  * @wakeirq_dual_edge_errata: If true then GPIOs using the wakeirq_map need
126  *                            to be aware that their parent can't handle dual
127  *                            edge interrupts.
128  * @gpio_func: Which function number is GPIO (usually 0).
129  * @egpio_func: If non-zero then this SoC supports eGPIO. Even though in
130  *              hardware this is a mux 1-level above the TLMM, we'll treat
131  *              it as if this is just another mux state of the TLMM. Since
132  *              it doesn't really map to hardware, we'll allocate a virtual
133  *              function number for eGPIO and any time we see that function
134  *              number used we'll treat it as a request to mux away from
135  *              our TLMM towards another owner.
136  */
137 struct msm_pinctrl_soc_data {
138 	const struct pinctrl_pin_desc *pins;
139 	unsigned npins;
140 	const struct msm_function *functions;
141 	unsigned nfunctions;
142 	const struct msm_pingroup *groups;
143 	unsigned ngroups;
144 	unsigned ngpios;
145 	bool pull_no_keeper;
146 	const char *const *tiles;
147 	unsigned int ntiles;
148 	const int *reserved_gpios;
149 	const struct msm_gpio_wakeirq_map *wakeirq_map;
150 	unsigned int nwakeirq_map;
151 	bool wakeirq_dual_edge_errata;
152 	unsigned int gpio_func;
153 	unsigned int egpio_func;
154 };
155 
156 extern const struct dev_pm_ops msm_pinctrl_dev_pm_ops;
157 
158 int msm_pinctrl_probe(struct platform_device *pdev,
159 		      const struct msm_pinctrl_soc_data *soc_data);
160 int msm_pinctrl_remove(struct platform_device *pdev);
161 
162 #endif
163