1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2013, Sony Mobile Communications AB. 4 */ 5 #ifndef __PINCTRL_MSM_H__ 6 #define __PINCTRL_MSM_H__ 7 8 #include <linux/pm.h> 9 #include <linux/types.h> 10 11 #include <linux/pinctrl/pinctrl.h> 12 13 struct platform_device; 14 15 struct pinctrl_pin_desc; 16 17 #define APQ_PIN_FUNCTION(fname) \ 18 [APQ_MUX_##fname] = PINCTRL_PINFUNCTION(#fname, \ 19 fname##_groups, \ 20 ARRAY_SIZE(fname##_groups)) 21 22 #define IPQ_PIN_FUNCTION(fname) \ 23 [IPQ_MUX_##fname] = PINCTRL_PINFUNCTION(#fname, \ 24 fname##_groups, \ 25 ARRAY_SIZE(fname##_groups)) 26 27 #define MSM_PIN_FUNCTION(fname) \ 28 [msm_mux_##fname] = PINCTRL_PINFUNCTION(#fname, \ 29 fname##_groups, \ 30 ARRAY_SIZE(fname##_groups)) 31 32 #define QCA_PIN_FUNCTION(fname) \ 33 [qca_mux_##fname] = PINCTRL_PINFUNCTION(#fname, \ 34 fname##_groups, \ 35 ARRAY_SIZE(fname##_groups)) 36 37 /** 38 * struct msm_pingroup - Qualcomm pingroup definition 39 * @grp: Generic data of the pin group (name and pins) 40 * @funcs: A list of pinmux functions that can be selected for 41 * this group. The index of the selected function is used 42 * for programming the function selector. 43 * Entries should be indices into the groups list of the 44 * struct msm_pinctrl_soc_data. 45 * @ctl_reg: Offset of the register holding control bits for this group. 46 * @io_reg: Offset of the register holding input/output bits for this group. 47 * @intr_cfg_reg: Offset of the register holding interrupt configuration bits. 48 * @intr_status_reg: Offset of the register holding the status bits for this group. 49 * @intr_target_reg: Offset of the register specifying routing of the interrupts 50 * from this group. 51 * @mux_bit: Offset in @ctl_reg for the pinmux function selection. 52 * @pull_bit: Offset in @ctl_reg for the bias configuration. 53 * @drv_bit: Offset in @ctl_reg for the drive strength configuration. 54 * @od_bit: Offset in @ctl_reg for controlling open drain. 55 * @oe_bit: Offset in @ctl_reg for controlling output enable. 56 * @in_bit: Offset in @io_reg for the input bit value. 57 * @out_bit: Offset in @io_reg for the output bit value. 58 * @intr_enable_bit: Offset in @intr_cfg_reg for enabling the interrupt for this group. 59 * @intr_status_bit: Offset in @intr_status_reg for reading and acking the interrupt 60 * status. 61 * @intr_target_bit: Offset in @intr_target_reg for configuring the interrupt routing. 62 * @intr_target_kpss_val: Value in @intr_target_bit for specifying that the interrupt from 63 * this gpio should get routed to the KPSS processor. 64 * @intr_raw_status_bit: Offset in @intr_cfg_reg for the raw status bit. 65 * @intr_polarity_bit: Offset in @intr_cfg_reg for specifying polarity of the interrupt. 66 * @intr_detection_bit: Offset in @intr_cfg_reg for specifying interrupt type. 67 * @intr_detection_width: Number of bits used for specifying interrupt type, 68 * Should be 2 for SoCs that can detect both edges in hardware, 69 * otherwise 1. 70 */ 71 struct msm_pingroup { 72 struct pingroup grp; 73 74 unsigned *funcs; 75 unsigned nfuncs; 76 77 u32 ctl_reg; 78 u32 io_reg; 79 u32 intr_cfg_reg; 80 u32 intr_status_reg; 81 u32 intr_target_reg; 82 83 unsigned int tile:2; 84 85 unsigned mux_bit:5; 86 87 unsigned pull_bit:5; 88 unsigned drv_bit:5; 89 unsigned i2c_pull_bit:5; 90 91 unsigned od_bit:5; 92 unsigned egpio_enable:5; 93 unsigned egpio_present:5; 94 unsigned oe_bit:5; 95 unsigned in_bit:5; 96 unsigned out_bit:5; 97 98 unsigned intr_enable_bit:5; 99 unsigned intr_status_bit:5; 100 unsigned intr_ack_high:1; 101 102 unsigned intr_target_bit:5; 103 unsigned intr_target_kpss_val:5; 104 unsigned intr_raw_status_bit:5; 105 unsigned intr_polarity_bit:5; 106 unsigned intr_detection_bit:5; 107 unsigned intr_detection_width:5; 108 }; 109 110 /** 111 * struct msm_gpio_wakeirq_map - Map of GPIOs and their wakeup pins 112 * @gpio: The GPIOs that are wakeup capable 113 * @wakeirq: The interrupt at the always-on interrupt controller 114 */ 115 struct msm_gpio_wakeirq_map { 116 unsigned int gpio; 117 unsigned int wakeirq; 118 }; 119 120 /** 121 * struct msm_pinctrl_soc_data - Qualcomm pin controller driver configuration 122 * @pins: An array describing all pins the pin controller affects. 123 * @npins: The number of entries in @pins. 124 * @functions: An array describing all mux functions the SoC supports. 125 * @nfunctions: The number of entries in @functions. 126 * @groups: An array describing all pin groups the pin SoC supports. 127 * @ngroups: The numbmer of entries in @groups. 128 * @ngpio: The number of pingroups the driver should expose as GPIOs. 129 * @pull_no_keeper: The SoC does not support keeper bias. 130 * @wakeirq_map: The map of wakeup capable GPIOs and the pin at PDC/MPM 131 * @nwakeirq_map: The number of entries in @wakeirq_map 132 * @wakeirq_dual_edge_errata: If true then GPIOs using the wakeirq_map need 133 * to be aware that their parent can't handle dual 134 * edge interrupts. 135 * @gpio_func: Which function number is GPIO (usually 0). 136 * @egpio_func: If non-zero then this SoC supports eGPIO. Even though in 137 * hardware this is a mux 1-level above the TLMM, we'll treat 138 * it as if this is just another mux state of the TLMM. Since 139 * it doesn't really map to hardware, we'll allocate a virtual 140 * function number for eGPIO and any time we see that function 141 * number used we'll treat it as a request to mux away from 142 * our TLMM towards another owner. 143 */ 144 struct msm_pinctrl_soc_data { 145 const struct pinctrl_pin_desc *pins; 146 unsigned npins; 147 const struct pinfunction *functions; 148 unsigned nfunctions; 149 const struct msm_pingroup *groups; 150 unsigned ngroups; 151 unsigned ngpios; 152 bool pull_no_keeper; 153 const char *const *tiles; 154 unsigned int ntiles; 155 const int *reserved_gpios; 156 const struct msm_gpio_wakeirq_map *wakeirq_map; 157 unsigned int nwakeirq_map; 158 bool wakeirq_dual_edge_errata; 159 unsigned int gpio_func; 160 unsigned int egpio_func; 161 }; 162 163 extern const struct dev_pm_ops msm_pinctrl_dev_pm_ops; 164 165 int msm_pinctrl_probe(struct platform_device *pdev, 166 const struct msm_pinctrl_soc_data *soc_data); 167 int msm_pinctrl_remove(struct platform_device *pdev); 168 169 #endif 170