1 /* 2 * Copyright (c) 2013, Sony Mobile Communications AB. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 and 6 * only version 2 as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 #ifndef __PINCTRL_MSM_H__ 14 #define __PINCTRL_MSM_H__ 15 16 struct pinctrl_pin_desc; 17 18 /** 19 * struct msm_function - a pinmux function 20 * @name: Name of the pinmux function. 21 * @groups: List of pingroups for this function. 22 * @ngroups: Number of entries in @groups. 23 */ 24 struct msm_function { 25 const char *name; 26 const char * const *groups; 27 unsigned ngroups; 28 }; 29 30 /** 31 * struct msm_pingroup - Qualcomm pingroup definition 32 * @name: Name of the pingroup. 33 * @pins: A list of pins assigned to this pingroup. 34 * @npins: Number of entries in @pins. 35 * @funcs: A list of pinmux functions that can be selected for 36 * this group. The index of the selected function is used 37 * for programming the function selector. 38 * Entries should be indices into the groups list of the 39 * struct msm_pinctrl_soc_data. 40 * @ctl_reg: Offset of the register holding control bits for this group. 41 * @io_reg: Offset of the register holding input/output bits for this group. 42 * @intr_cfg_reg: Offset of the register holding interrupt configuration bits. 43 * @intr_status_reg: Offset of the register holding the status bits for this group. 44 * @intr_target_reg: Offset of the register specifying routing of the interrupts 45 * from this group. 46 * @mux_bit: Offset in @ctl_reg for the pinmux function selection. 47 * @pull_bit: Offset in @ctl_reg for the bias configuration. 48 * @drv_bit: Offset in @ctl_reg for the drive strength configuration. 49 * @oe_bit: Offset in @ctl_reg for controlling output enable. 50 * @in_bit: Offset in @io_reg for the input bit value. 51 * @out_bit: Offset in @io_reg for the output bit value. 52 * @intr_enable_bit: Offset in @intr_cfg_reg for enabling the interrupt for this group. 53 * @intr_status_bit: Offset in @intr_status_reg for reading and acking the interrupt 54 * status. 55 * @intr_target_bit: Offset in @intr_target_reg for configuring the interrupt routing. 56 * @intr_target_kpss_val: Value in @intr_target_bit for specifying that the interrupt from 57 * this gpio should get routed to the KPSS processor. 58 * @intr_raw_status_bit: Offset in @intr_cfg_reg for the raw status bit. 59 * @intr_polarity_bit: Offset in @intr_cfg_reg for specifying polarity of the interrupt. 60 * @intr_detection_bit: Offset in @intr_cfg_reg for specifying interrupt type. 61 * @intr_detection_width: Number of bits used for specifying interrupt type, 62 * Should be 2 for SoCs that can detect both edges in hardware, 63 * otherwise 1. 64 */ 65 struct msm_pingroup { 66 const char *name; 67 const unsigned *pins; 68 unsigned npins; 69 70 unsigned *funcs; 71 unsigned nfuncs; 72 73 u32 ctl_reg; 74 u32 io_reg; 75 u32 intr_cfg_reg; 76 u32 intr_status_reg; 77 u32 intr_target_reg; 78 79 unsigned mux_bit:5; 80 81 unsigned pull_bit:5; 82 unsigned drv_bit:5; 83 84 unsigned oe_bit:5; 85 unsigned in_bit:5; 86 unsigned out_bit:5; 87 88 unsigned intr_enable_bit:5; 89 unsigned intr_status_bit:5; 90 unsigned intr_ack_high:1; 91 92 unsigned intr_target_bit:5; 93 unsigned intr_target_kpss_val:5; 94 unsigned intr_raw_status_bit:5; 95 unsigned intr_polarity_bit:5; 96 unsigned intr_detection_bit:5; 97 unsigned intr_detection_width:5; 98 }; 99 100 /** 101 * struct msm_pinctrl_soc_data - Qualcomm pin controller driver configuration 102 * @pins: An array describing all pins the pin controller affects. 103 * @npins: The number of entries in @pins. 104 * @functions: An array describing all mux functions the SoC supports. 105 * @nfunctions: The number of entries in @functions. 106 * @groups: An array describing all pin groups the pin SoC supports. 107 * @ngroups: The numbmer of entries in @groups. 108 * @ngpio: The number of pingroups the driver should expose as GPIOs. 109 */ 110 struct msm_pinctrl_soc_data { 111 const struct pinctrl_pin_desc *pins; 112 unsigned npins; 113 const struct msm_function *functions; 114 unsigned nfunctions; 115 const struct msm_pingroup *groups; 116 unsigned ngroups; 117 unsigned ngpios; 118 }; 119 120 int msm_pinctrl_probe(struct platform_device *pdev, 121 const struct msm_pinctrl_soc_data *soc_data); 122 int msm_pinctrl_remove(struct platform_device *pdev); 123 124 #endif 125