1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2013, Sony Mobile Communications AB.
4  * Copyright (c) 2013, The Linux Foundation. All rights reserved.
5  */
6 
7 #include <linux/delay.h>
8 #include <linux/err.h>
9 #include <linux/io.h>
10 #include <linux/module.h>
11 #include <linux/of.h>
12 #include <linux/platform_device.h>
13 #include <linux/pinctrl/machine.h>
14 #include <linux/pinctrl/pinctrl.h>
15 #include <linux/pinctrl/pinmux.h>
16 #include <linux/pinctrl/pinconf.h>
17 #include <linux/pinctrl/pinconf-generic.h>
18 #include <linux/slab.h>
19 #include <linux/gpio/driver.h>
20 #include <linux/interrupt.h>
21 #include <linux/spinlock.h>
22 #include <linux/reboot.h>
23 #include <linux/pm.h>
24 #include <linux/log2.h>
25 
26 #include "../core.h"
27 #include "../pinconf.h"
28 #include "pinctrl-msm.h"
29 #include "../pinctrl-utils.h"
30 
31 #define MAX_NR_GPIO 300
32 #define MAX_NR_TILES 4
33 #define PS_HOLD_OFFSET 0x820
34 
35 /**
36  * struct msm_pinctrl - state for a pinctrl-msm device
37  * @dev:            device handle.
38  * @pctrl:          pinctrl handle.
39  * @chip:           gpiochip handle.
40  * @restart_nb:     restart notifier block.
41  * @irq:            parent irq for the TLMM irq_chip.
42  * @lock:           Spinlock to protect register resources as well
43  *                  as msm_pinctrl data structures.
44  * @enabled_irqs:   Bitmap of currently enabled irqs.
45  * @dual_edge_irqs: Bitmap of irqs that need sw emulated dual edge
46  *                  detection.
47  * @soc;            Reference to soc_data of platform specific data.
48  * @regs:           Base addresses for the TLMM tiles.
49  */
50 struct msm_pinctrl {
51 	struct device *dev;
52 	struct pinctrl_dev *pctrl;
53 	struct gpio_chip chip;
54 	struct pinctrl_desc desc;
55 	struct notifier_block restart_nb;
56 
57 	struct irq_chip irq_chip;
58 	int irq;
59 
60 	raw_spinlock_t lock;
61 
62 	DECLARE_BITMAP(dual_edge_irqs, MAX_NR_GPIO);
63 	DECLARE_BITMAP(enabled_irqs, MAX_NR_GPIO);
64 
65 	const struct msm_pinctrl_soc_data *soc;
66 	void __iomem *regs[MAX_NR_TILES];
67 };
68 
69 #define MSM_ACCESSOR(name) \
70 static u32 msm_readl_##name(struct msm_pinctrl *pctrl, \
71 			    const struct msm_pingroup *g) \
72 { \
73 	return readl(pctrl->regs[g->tile] + g->name##_reg); \
74 } \
75 static void msm_writel_##name(u32 val, struct msm_pinctrl *pctrl, \
76 			      const struct msm_pingroup *g) \
77 { \
78 	writel(val, pctrl->regs[g->tile] + g->name##_reg); \
79 }
80 
81 MSM_ACCESSOR(ctl)
82 MSM_ACCESSOR(io)
83 MSM_ACCESSOR(intr_cfg)
84 MSM_ACCESSOR(intr_status)
85 MSM_ACCESSOR(intr_target)
86 
87 static int msm_get_groups_count(struct pinctrl_dev *pctldev)
88 {
89 	struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
90 
91 	return pctrl->soc->ngroups;
92 }
93 
94 static const char *msm_get_group_name(struct pinctrl_dev *pctldev,
95 				      unsigned group)
96 {
97 	struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
98 
99 	return pctrl->soc->groups[group].name;
100 }
101 
102 static int msm_get_group_pins(struct pinctrl_dev *pctldev,
103 			      unsigned group,
104 			      const unsigned **pins,
105 			      unsigned *num_pins)
106 {
107 	struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
108 
109 	*pins = pctrl->soc->groups[group].pins;
110 	*num_pins = pctrl->soc->groups[group].npins;
111 	return 0;
112 }
113 
114 static const struct pinctrl_ops msm_pinctrl_ops = {
115 	.get_groups_count	= msm_get_groups_count,
116 	.get_group_name		= msm_get_group_name,
117 	.get_group_pins		= msm_get_group_pins,
118 	.dt_node_to_map		= pinconf_generic_dt_node_to_map_group,
119 	.dt_free_map		= pinctrl_utils_free_map,
120 };
121 
122 static int msm_pinmux_request(struct pinctrl_dev *pctldev, unsigned offset)
123 {
124 	struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
125 	struct gpio_chip *chip = &pctrl->chip;
126 
127 	return gpiochip_line_is_valid(chip, offset) ? 0 : -EINVAL;
128 }
129 
130 static int msm_get_functions_count(struct pinctrl_dev *pctldev)
131 {
132 	struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
133 
134 	return pctrl->soc->nfunctions;
135 }
136 
137 static const char *msm_get_function_name(struct pinctrl_dev *pctldev,
138 					 unsigned function)
139 {
140 	struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
141 
142 	return pctrl->soc->functions[function].name;
143 }
144 
145 static int msm_get_function_groups(struct pinctrl_dev *pctldev,
146 				   unsigned function,
147 				   const char * const **groups,
148 				   unsigned * const num_groups)
149 {
150 	struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
151 
152 	*groups = pctrl->soc->functions[function].groups;
153 	*num_groups = pctrl->soc->functions[function].ngroups;
154 	return 0;
155 }
156 
157 static int msm_pinmux_set_mux(struct pinctrl_dev *pctldev,
158 			      unsigned function,
159 			      unsigned group)
160 {
161 	struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
162 	const struct msm_pingroup *g;
163 	unsigned long flags;
164 	u32 val, mask;
165 	int i;
166 
167 	g = &pctrl->soc->groups[group];
168 	mask = GENMASK(g->mux_bit + order_base_2(g->nfuncs) - 1, g->mux_bit);
169 
170 	for (i = 0; i < g->nfuncs; i++) {
171 		if (g->funcs[i] == function)
172 			break;
173 	}
174 
175 	if (WARN_ON(i == g->nfuncs))
176 		return -EINVAL;
177 
178 	raw_spin_lock_irqsave(&pctrl->lock, flags);
179 
180 	val = msm_readl_ctl(pctrl, g);
181 	val &= ~mask;
182 	val |= i << g->mux_bit;
183 	msm_writel_ctl(val, pctrl, g);
184 
185 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
186 
187 	return 0;
188 }
189 
190 static int msm_pinmux_request_gpio(struct pinctrl_dev *pctldev,
191 				   struct pinctrl_gpio_range *range,
192 				   unsigned offset)
193 {
194 	struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
195 	const struct msm_pingroup *g = &pctrl->soc->groups[offset];
196 
197 	/* No funcs? Probably ACPI so can't do anything here */
198 	if (!g->nfuncs)
199 		return 0;
200 
201 	/* For now assume function 0 is GPIO because it always is */
202 	return msm_pinmux_set_mux(pctldev, g->funcs[0], offset);
203 }
204 
205 static const struct pinmux_ops msm_pinmux_ops = {
206 	.request		= msm_pinmux_request,
207 	.get_functions_count	= msm_get_functions_count,
208 	.get_function_name	= msm_get_function_name,
209 	.get_function_groups	= msm_get_function_groups,
210 	.gpio_request_enable	= msm_pinmux_request_gpio,
211 	.set_mux		= msm_pinmux_set_mux,
212 };
213 
214 static int msm_config_reg(struct msm_pinctrl *pctrl,
215 			  const struct msm_pingroup *g,
216 			  unsigned param,
217 			  unsigned *mask,
218 			  unsigned *bit)
219 {
220 	switch (param) {
221 	case PIN_CONFIG_BIAS_DISABLE:
222 	case PIN_CONFIG_BIAS_PULL_DOWN:
223 	case PIN_CONFIG_BIAS_BUS_HOLD:
224 	case PIN_CONFIG_BIAS_PULL_UP:
225 		*bit = g->pull_bit;
226 		*mask = 3;
227 		break;
228 	case PIN_CONFIG_DRIVE_STRENGTH:
229 		*bit = g->drv_bit;
230 		*mask = 7;
231 		break;
232 	case PIN_CONFIG_OUTPUT:
233 	case PIN_CONFIG_INPUT_ENABLE:
234 		*bit = g->oe_bit;
235 		*mask = 1;
236 		break;
237 	default:
238 		return -ENOTSUPP;
239 	}
240 
241 	return 0;
242 }
243 
244 #define MSM_NO_PULL		0
245 #define MSM_PULL_DOWN		1
246 #define MSM_KEEPER		2
247 #define MSM_PULL_UP_NO_KEEPER	2
248 #define MSM_PULL_UP		3
249 
250 static unsigned msm_regval_to_drive(u32 val)
251 {
252 	return (val + 1) * 2;
253 }
254 
255 static int msm_config_group_get(struct pinctrl_dev *pctldev,
256 				unsigned int group,
257 				unsigned long *config)
258 {
259 	const struct msm_pingroup *g;
260 	struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
261 	unsigned param = pinconf_to_config_param(*config);
262 	unsigned mask;
263 	unsigned arg;
264 	unsigned bit;
265 	int ret;
266 	u32 val;
267 
268 	g = &pctrl->soc->groups[group];
269 
270 	ret = msm_config_reg(pctrl, g, param, &mask, &bit);
271 	if (ret < 0)
272 		return ret;
273 
274 	val = msm_readl_ctl(pctrl, g);
275 	arg = (val >> bit) & mask;
276 
277 	/* Convert register value to pinconf value */
278 	switch (param) {
279 	case PIN_CONFIG_BIAS_DISABLE:
280 		if (arg != MSM_NO_PULL)
281 			return -EINVAL;
282 		arg = 1;
283 		break;
284 	case PIN_CONFIG_BIAS_PULL_DOWN:
285 		if (arg != MSM_PULL_DOWN)
286 			return -EINVAL;
287 		arg = 1;
288 		break;
289 	case PIN_CONFIG_BIAS_BUS_HOLD:
290 		if (pctrl->soc->pull_no_keeper)
291 			return -ENOTSUPP;
292 
293 		if (arg != MSM_KEEPER)
294 			return -EINVAL;
295 		arg = 1;
296 		break;
297 	case PIN_CONFIG_BIAS_PULL_UP:
298 		if (pctrl->soc->pull_no_keeper)
299 			arg = arg == MSM_PULL_UP_NO_KEEPER;
300 		else
301 			arg = arg == MSM_PULL_UP;
302 		if (!arg)
303 			return -EINVAL;
304 		break;
305 	case PIN_CONFIG_DRIVE_STRENGTH:
306 		arg = msm_regval_to_drive(arg);
307 		break;
308 	case PIN_CONFIG_OUTPUT:
309 		/* Pin is not output */
310 		if (!arg)
311 			return -EINVAL;
312 
313 		val = msm_readl_io(pctrl, g);
314 		arg = !!(val & BIT(g->in_bit));
315 		break;
316 	case PIN_CONFIG_INPUT_ENABLE:
317 		/* Pin is output */
318 		if (arg)
319 			return -EINVAL;
320 		arg = 1;
321 		break;
322 	default:
323 		return -ENOTSUPP;
324 	}
325 
326 	*config = pinconf_to_config_packed(param, arg);
327 
328 	return 0;
329 }
330 
331 static int msm_config_group_set(struct pinctrl_dev *pctldev,
332 				unsigned group,
333 				unsigned long *configs,
334 				unsigned num_configs)
335 {
336 	const struct msm_pingroup *g;
337 	struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
338 	unsigned long flags;
339 	unsigned param;
340 	unsigned mask;
341 	unsigned arg;
342 	unsigned bit;
343 	int ret;
344 	u32 val;
345 	int i;
346 
347 	g = &pctrl->soc->groups[group];
348 
349 	for (i = 0; i < num_configs; i++) {
350 		param = pinconf_to_config_param(configs[i]);
351 		arg = pinconf_to_config_argument(configs[i]);
352 
353 		ret = msm_config_reg(pctrl, g, param, &mask, &bit);
354 		if (ret < 0)
355 			return ret;
356 
357 		/* Convert pinconf values to register values */
358 		switch (param) {
359 		case PIN_CONFIG_BIAS_DISABLE:
360 			arg = MSM_NO_PULL;
361 			break;
362 		case PIN_CONFIG_BIAS_PULL_DOWN:
363 			arg = MSM_PULL_DOWN;
364 			break;
365 		case PIN_CONFIG_BIAS_BUS_HOLD:
366 			if (pctrl->soc->pull_no_keeper)
367 				return -ENOTSUPP;
368 
369 			arg = MSM_KEEPER;
370 			break;
371 		case PIN_CONFIG_BIAS_PULL_UP:
372 			if (pctrl->soc->pull_no_keeper)
373 				arg = MSM_PULL_UP_NO_KEEPER;
374 			else
375 				arg = MSM_PULL_UP;
376 			break;
377 		case PIN_CONFIG_DRIVE_STRENGTH:
378 			/* Check for invalid values */
379 			if (arg > 16 || arg < 2 || (arg % 2) != 0)
380 				arg = -1;
381 			else
382 				arg = (arg / 2) - 1;
383 			break;
384 		case PIN_CONFIG_OUTPUT:
385 			/* set output value */
386 			raw_spin_lock_irqsave(&pctrl->lock, flags);
387 			val = msm_readl_io(pctrl, g);
388 			if (arg)
389 				val |= BIT(g->out_bit);
390 			else
391 				val &= ~BIT(g->out_bit);
392 			msm_writel_io(val, pctrl, g);
393 			raw_spin_unlock_irqrestore(&pctrl->lock, flags);
394 
395 			/* enable output */
396 			arg = 1;
397 			break;
398 		case PIN_CONFIG_INPUT_ENABLE:
399 			/* disable output */
400 			arg = 0;
401 			break;
402 		default:
403 			dev_err(pctrl->dev, "Unsupported config parameter: %x\n",
404 				param);
405 			return -EINVAL;
406 		}
407 
408 		/* Range-check user-supplied value */
409 		if (arg & ~mask) {
410 			dev_err(pctrl->dev, "config %x: %x is invalid\n", param, arg);
411 			return -EINVAL;
412 		}
413 
414 		raw_spin_lock_irqsave(&pctrl->lock, flags);
415 		val = msm_readl_ctl(pctrl, g);
416 		val &= ~(mask << bit);
417 		val |= arg << bit;
418 		msm_writel_ctl(val, pctrl, g);
419 		raw_spin_unlock_irqrestore(&pctrl->lock, flags);
420 	}
421 
422 	return 0;
423 }
424 
425 static const struct pinconf_ops msm_pinconf_ops = {
426 	.is_generic		= true,
427 	.pin_config_group_get	= msm_config_group_get,
428 	.pin_config_group_set	= msm_config_group_set,
429 };
430 
431 static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
432 {
433 	const struct msm_pingroup *g;
434 	struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
435 	unsigned long flags;
436 	u32 val;
437 
438 	g = &pctrl->soc->groups[offset];
439 
440 	raw_spin_lock_irqsave(&pctrl->lock, flags);
441 
442 	val = msm_readl_ctl(pctrl, g);
443 	val &= ~BIT(g->oe_bit);
444 	msm_writel_ctl(val, pctrl, g);
445 
446 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
447 
448 	return 0;
449 }
450 
451 static int msm_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value)
452 {
453 	const struct msm_pingroup *g;
454 	struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
455 	unsigned long flags;
456 	u32 val;
457 
458 	g = &pctrl->soc->groups[offset];
459 
460 	raw_spin_lock_irqsave(&pctrl->lock, flags);
461 
462 	val = msm_readl_io(pctrl, g);
463 	if (value)
464 		val |= BIT(g->out_bit);
465 	else
466 		val &= ~BIT(g->out_bit);
467 	msm_writel_io(val, pctrl, g);
468 
469 	val = msm_readl_ctl(pctrl, g);
470 	val |= BIT(g->oe_bit);
471 	msm_writel_ctl(val, pctrl, g);
472 
473 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
474 
475 	return 0;
476 }
477 
478 static int msm_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
479 {
480 	struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
481 	const struct msm_pingroup *g;
482 	u32 val;
483 
484 	g = &pctrl->soc->groups[offset];
485 
486 	val = msm_readl_ctl(pctrl, g);
487 
488 	/* 0 = output, 1 = input */
489 	return val & BIT(g->oe_bit) ? 0 : 1;
490 }
491 
492 static int msm_gpio_get(struct gpio_chip *chip, unsigned offset)
493 {
494 	const struct msm_pingroup *g;
495 	struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
496 	u32 val;
497 
498 	g = &pctrl->soc->groups[offset];
499 
500 	val = msm_readl_io(pctrl, g);
501 	return !!(val & BIT(g->in_bit));
502 }
503 
504 static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
505 {
506 	const struct msm_pingroup *g;
507 	struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
508 	unsigned long flags;
509 	u32 val;
510 
511 	g = &pctrl->soc->groups[offset];
512 
513 	raw_spin_lock_irqsave(&pctrl->lock, flags);
514 
515 	val = msm_readl_io(pctrl, g);
516 	if (value)
517 		val |= BIT(g->out_bit);
518 	else
519 		val &= ~BIT(g->out_bit);
520 	msm_writel_io(val, pctrl, g);
521 
522 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
523 }
524 
525 #ifdef CONFIG_DEBUG_FS
526 #include <linux/seq_file.h>
527 
528 static void msm_gpio_dbg_show_one(struct seq_file *s,
529 				  struct pinctrl_dev *pctldev,
530 				  struct gpio_chip *chip,
531 				  unsigned offset,
532 				  unsigned gpio)
533 {
534 	const struct msm_pingroup *g;
535 	struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
536 	unsigned func;
537 	int is_out;
538 	int drive;
539 	int pull;
540 	int val;
541 	u32 ctl_reg, io_reg;
542 
543 	static const char * const pulls_keeper[] = {
544 		"no pull",
545 		"pull down",
546 		"keeper",
547 		"pull up"
548 	};
549 
550 	static const char * const pulls_no_keeper[] = {
551 		"no pull",
552 		"pull down",
553 		"pull up",
554 	};
555 
556 	if (!gpiochip_line_is_valid(chip, offset))
557 		return;
558 
559 	g = &pctrl->soc->groups[offset];
560 	ctl_reg = msm_readl_ctl(pctrl, g);
561 	io_reg = msm_readl_io(pctrl, g);
562 
563 	is_out = !!(ctl_reg & BIT(g->oe_bit));
564 	func = (ctl_reg >> g->mux_bit) & 7;
565 	drive = (ctl_reg >> g->drv_bit) & 7;
566 	pull = (ctl_reg >> g->pull_bit) & 3;
567 
568 	if (is_out)
569 		val = !!(io_reg & BIT(g->out_bit));
570 	else
571 		val = !!(io_reg & BIT(g->in_bit));
572 
573 	seq_printf(s, " %-8s: %-3s", g->name, is_out ? "out" : "in");
574 	seq_printf(s, " %-4s func%d", val ? "high" : "low", func);
575 	seq_printf(s, " %dmA", msm_regval_to_drive(drive));
576 	if (pctrl->soc->pull_no_keeper)
577 		seq_printf(s, " %s", pulls_no_keeper[pull]);
578 	else
579 		seq_printf(s, " %s", pulls_keeper[pull]);
580 	seq_puts(s, "\n");
581 }
582 
583 static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
584 {
585 	unsigned gpio = chip->base;
586 	unsigned i;
587 
588 	for (i = 0; i < chip->ngpio; i++, gpio++)
589 		msm_gpio_dbg_show_one(s, NULL, chip, i, gpio);
590 }
591 
592 #else
593 #define msm_gpio_dbg_show NULL
594 #endif
595 
596 static int msm_gpio_init_valid_mask(struct gpio_chip *gc,
597 				    unsigned long *valid_mask,
598 				    unsigned int ngpios)
599 {
600 	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
601 	int ret;
602 	unsigned int len, i;
603 	const int *reserved = pctrl->soc->reserved_gpios;
604 	u16 *tmp;
605 
606 	/* Driver provided reserved list overrides DT and ACPI */
607 	if (reserved) {
608 		bitmap_fill(valid_mask, ngpios);
609 		for (i = 0; reserved[i] >= 0; i++) {
610 			if (i >= ngpios || reserved[i] >= ngpios) {
611 				dev_err(pctrl->dev, "invalid list of reserved GPIOs\n");
612 				return -EINVAL;
613 			}
614 			clear_bit(reserved[i], valid_mask);
615 		}
616 
617 		return 0;
618 	}
619 
620 	/* The number of GPIOs in the ACPI tables */
621 	len = ret = device_property_count_u16(pctrl->dev, "gpios");
622 	if (ret < 0)
623 		return 0;
624 
625 	if (ret > ngpios)
626 		return -EINVAL;
627 
628 	tmp = kmalloc_array(len, sizeof(*tmp), GFP_KERNEL);
629 	if (!tmp)
630 		return -ENOMEM;
631 
632 	ret = device_property_read_u16_array(pctrl->dev, "gpios", tmp, len);
633 	if (ret < 0) {
634 		dev_err(pctrl->dev, "could not read list of GPIOs\n");
635 		goto out;
636 	}
637 
638 	bitmap_zero(valid_mask, ngpios);
639 	for (i = 0; i < len; i++)
640 		set_bit(tmp[i], valid_mask);
641 
642 out:
643 	kfree(tmp);
644 	return ret;
645 }
646 
647 static const struct gpio_chip msm_gpio_template = {
648 	.direction_input  = msm_gpio_direction_input,
649 	.direction_output = msm_gpio_direction_output,
650 	.get_direction    = msm_gpio_get_direction,
651 	.get              = msm_gpio_get,
652 	.set              = msm_gpio_set,
653 	.request          = gpiochip_generic_request,
654 	.free             = gpiochip_generic_free,
655 	.dbg_show         = msm_gpio_dbg_show,
656 };
657 
658 /* For dual-edge interrupts in software, since some hardware has no
659  * such support:
660  *
661  * At appropriate moments, this function may be called to flip the polarity
662  * settings of both-edge irq lines to try and catch the next edge.
663  *
664  * The attempt is considered successful if:
665  * - the status bit goes high, indicating that an edge was caught, or
666  * - the input value of the gpio doesn't change during the attempt.
667  * If the value changes twice during the process, that would cause the first
668  * test to fail but would force the second, as two opposite
669  * transitions would cause a detection no matter the polarity setting.
670  *
671  * The do-loop tries to sledge-hammer closed the timing hole between
672  * the initial value-read and the polarity-write - if the line value changes
673  * during that window, an interrupt is lost, the new polarity setting is
674  * incorrect, and the first success test will fail, causing a retry.
675  *
676  * Algorithm comes from Google's msmgpio driver.
677  */
678 static void msm_gpio_update_dual_edge_pos(struct msm_pinctrl *pctrl,
679 					  const struct msm_pingroup *g,
680 					  struct irq_data *d)
681 {
682 	int loop_limit = 100;
683 	unsigned val, val2, intstat;
684 	unsigned pol;
685 
686 	do {
687 		val = msm_readl_io(pctrl, g) & BIT(g->in_bit);
688 
689 		pol = msm_readl_intr_cfg(pctrl, g);
690 		pol ^= BIT(g->intr_polarity_bit);
691 		msm_writel_intr_cfg(val, pctrl, g);
692 
693 		val2 = msm_readl_io(pctrl, g) & BIT(g->in_bit);
694 		intstat = msm_readl_intr_status(pctrl, g);
695 		if (intstat || (val == val2))
696 			return;
697 	} while (loop_limit-- > 0);
698 	dev_err(pctrl->dev, "dual-edge irq failed to stabilize, %#08x != %#08x\n",
699 		val, val2);
700 }
701 
702 static void msm_gpio_irq_mask(struct irq_data *d)
703 {
704 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
705 	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
706 	const struct msm_pingroup *g;
707 	unsigned long flags;
708 	u32 val;
709 
710 	g = &pctrl->soc->groups[d->hwirq];
711 
712 	raw_spin_lock_irqsave(&pctrl->lock, flags);
713 
714 	val = msm_readl_intr_cfg(pctrl, g);
715 	/*
716 	 * There are two bits that control interrupt forwarding to the CPU. The
717 	 * RAW_STATUS_EN bit causes the level or edge sensed on the line to be
718 	 * latched into the interrupt status register when the hardware detects
719 	 * an irq that it's configured for (either edge for edge type or level
720 	 * for level type irq). The 'non-raw' status enable bit causes the
721 	 * hardware to assert the summary interrupt to the CPU if the latched
722 	 * status bit is set. There's a bug though, the edge detection logic
723 	 * seems to have a problem where toggling the RAW_STATUS_EN bit may
724 	 * cause the status bit to latch spuriously when there isn't any edge
725 	 * so we can't touch that bit for edge type irqs and we have to keep
726 	 * the bit set anyway so that edges are latched while the line is masked.
727 	 *
728 	 * To make matters more complicated, leaving the RAW_STATUS_EN bit
729 	 * enabled all the time causes level interrupts to re-latch into the
730 	 * status register because the level is still present on the line after
731 	 * we ack it. We clear the raw status enable bit during mask here and
732 	 * set the bit on unmask so the interrupt can't latch into the hardware
733 	 * while it's masked.
734 	 */
735 	if (irqd_get_trigger_type(d) & IRQ_TYPE_LEVEL_MASK)
736 		val &= ~BIT(g->intr_raw_status_bit);
737 
738 	val &= ~BIT(g->intr_enable_bit);
739 	msm_writel_intr_cfg(val, pctrl, g);
740 
741 	clear_bit(d->hwirq, pctrl->enabled_irqs);
742 
743 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
744 }
745 
746 static void msm_gpio_irq_clear_unmask(struct irq_data *d, bool status_clear)
747 {
748 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
749 	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
750 	const struct msm_pingroup *g;
751 	unsigned long flags;
752 	u32 val;
753 
754 	g = &pctrl->soc->groups[d->hwirq];
755 
756 	raw_spin_lock_irqsave(&pctrl->lock, flags);
757 
758 	if (status_clear) {
759 		/*
760 		 * clear the interrupt status bit before unmask to avoid
761 		 * any erroneous interrupts that would have got latched
762 		 * when the interrupt is not in use.
763 		 */
764 		val = msm_readl_intr_status(pctrl, g);
765 		val &= ~BIT(g->intr_status_bit);
766 		msm_writel_intr_status(val, pctrl, g);
767 	}
768 
769 	val = msm_readl_intr_cfg(pctrl, g);
770 	val |= BIT(g->intr_raw_status_bit);
771 	val |= BIT(g->intr_enable_bit);
772 	msm_writel_intr_cfg(val, pctrl, g);
773 
774 	set_bit(d->hwirq, pctrl->enabled_irqs);
775 
776 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
777 }
778 
779 static void msm_gpio_irq_enable(struct irq_data *d)
780 {
781 
782 	msm_gpio_irq_clear_unmask(d, true);
783 }
784 
785 static void msm_gpio_irq_unmask(struct irq_data *d)
786 {
787 	msm_gpio_irq_clear_unmask(d, false);
788 }
789 
790 static void msm_gpio_irq_ack(struct irq_data *d)
791 {
792 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
793 	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
794 	const struct msm_pingroup *g;
795 	unsigned long flags;
796 	u32 val;
797 
798 	g = &pctrl->soc->groups[d->hwirq];
799 
800 	raw_spin_lock_irqsave(&pctrl->lock, flags);
801 
802 	val = msm_readl_intr_status(pctrl, g);
803 	if (g->intr_ack_high)
804 		val |= BIT(g->intr_status_bit);
805 	else
806 		val &= ~BIT(g->intr_status_bit);
807 	msm_writel_intr_status(val, pctrl, g);
808 
809 	if (test_bit(d->hwirq, pctrl->dual_edge_irqs))
810 		msm_gpio_update_dual_edge_pos(pctrl, g, d);
811 
812 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
813 }
814 
815 static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type)
816 {
817 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
818 	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
819 	const struct msm_pingroup *g;
820 	unsigned long flags;
821 	u32 val;
822 
823 	g = &pctrl->soc->groups[d->hwirq];
824 
825 	raw_spin_lock_irqsave(&pctrl->lock, flags);
826 
827 	/*
828 	 * For hw without possibility of detecting both edges
829 	 */
830 	if (g->intr_detection_width == 1 && type == IRQ_TYPE_EDGE_BOTH)
831 		set_bit(d->hwirq, pctrl->dual_edge_irqs);
832 	else
833 		clear_bit(d->hwirq, pctrl->dual_edge_irqs);
834 
835 	/* Route interrupts to application cpu */
836 	val = msm_readl_intr_target(pctrl, g);
837 	val &= ~(7 << g->intr_target_bit);
838 	val |= g->intr_target_kpss_val << g->intr_target_bit;
839 	msm_writel_intr_target(val, pctrl, g);
840 
841 	/* Update configuration for gpio.
842 	 * RAW_STATUS_EN is left on for all gpio irqs. Due to the
843 	 * internal circuitry of TLMM, toggling the RAW_STATUS
844 	 * could cause the INTR_STATUS to be set for EDGE interrupts.
845 	 */
846 	val = msm_readl_intr_cfg(pctrl, g);
847 	val |= BIT(g->intr_raw_status_bit);
848 	if (g->intr_detection_width == 2) {
849 		val &= ~(3 << g->intr_detection_bit);
850 		val &= ~(1 << g->intr_polarity_bit);
851 		switch (type) {
852 		case IRQ_TYPE_EDGE_RISING:
853 			val |= 1 << g->intr_detection_bit;
854 			val |= BIT(g->intr_polarity_bit);
855 			break;
856 		case IRQ_TYPE_EDGE_FALLING:
857 			val |= 2 << g->intr_detection_bit;
858 			val |= BIT(g->intr_polarity_bit);
859 			break;
860 		case IRQ_TYPE_EDGE_BOTH:
861 			val |= 3 << g->intr_detection_bit;
862 			val |= BIT(g->intr_polarity_bit);
863 			break;
864 		case IRQ_TYPE_LEVEL_LOW:
865 			break;
866 		case IRQ_TYPE_LEVEL_HIGH:
867 			val |= BIT(g->intr_polarity_bit);
868 			break;
869 		}
870 	} else if (g->intr_detection_width == 1) {
871 		val &= ~(1 << g->intr_detection_bit);
872 		val &= ~(1 << g->intr_polarity_bit);
873 		switch (type) {
874 		case IRQ_TYPE_EDGE_RISING:
875 			val |= BIT(g->intr_detection_bit);
876 			val |= BIT(g->intr_polarity_bit);
877 			break;
878 		case IRQ_TYPE_EDGE_FALLING:
879 			val |= BIT(g->intr_detection_bit);
880 			break;
881 		case IRQ_TYPE_EDGE_BOTH:
882 			val |= BIT(g->intr_detection_bit);
883 			val |= BIT(g->intr_polarity_bit);
884 			break;
885 		case IRQ_TYPE_LEVEL_LOW:
886 			break;
887 		case IRQ_TYPE_LEVEL_HIGH:
888 			val |= BIT(g->intr_polarity_bit);
889 			break;
890 		}
891 	} else {
892 		BUG();
893 	}
894 	msm_writel_intr_cfg(val, pctrl, g);
895 
896 	if (test_bit(d->hwirq, pctrl->dual_edge_irqs))
897 		msm_gpio_update_dual_edge_pos(pctrl, g, d);
898 
899 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
900 
901 	if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
902 		irq_set_handler_locked(d, handle_level_irq);
903 	else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
904 		irq_set_handler_locked(d, handle_edge_irq);
905 
906 	return 0;
907 }
908 
909 static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
910 {
911 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
912 	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
913 	unsigned long flags;
914 
915 	raw_spin_lock_irqsave(&pctrl->lock, flags);
916 
917 	irq_set_irq_wake(pctrl->irq, on);
918 
919 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
920 
921 	return 0;
922 }
923 
924 static int msm_gpio_irq_reqres(struct irq_data *d)
925 {
926 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
927 	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
928 	int ret;
929 
930 	if (!try_module_get(gc->owner))
931 		return -ENODEV;
932 
933 	ret = msm_pinmux_request_gpio(pctrl->pctrl, NULL, d->hwirq);
934 	if (ret)
935 		goto out;
936 	msm_gpio_direction_input(gc, d->hwirq);
937 
938 	if (gpiochip_lock_as_irq(gc, d->hwirq)) {
939 		dev_err(gc->parent,
940 			"unable to lock HW IRQ %lu for IRQ\n",
941 			d->hwirq);
942 		ret = -EINVAL;
943 		goto out;
944 	}
945 	return 0;
946 out:
947 	module_put(gc->owner);
948 	return ret;
949 }
950 
951 static void msm_gpio_irq_relres(struct irq_data *d)
952 {
953 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
954 
955 	gpiochip_unlock_as_irq(gc, d->hwirq);
956 	module_put(gc->owner);
957 }
958 
959 static void msm_gpio_irq_handler(struct irq_desc *desc)
960 {
961 	struct gpio_chip *gc = irq_desc_get_handler_data(desc);
962 	const struct msm_pingroup *g;
963 	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
964 	struct irq_chip *chip = irq_desc_get_chip(desc);
965 	int irq_pin;
966 	int handled = 0;
967 	u32 val;
968 	int i;
969 
970 	chained_irq_enter(chip, desc);
971 
972 	/*
973 	 * Each pin has it's own IRQ status register, so use
974 	 * enabled_irq bitmap to limit the number of reads.
975 	 */
976 	for_each_set_bit(i, pctrl->enabled_irqs, pctrl->chip.ngpio) {
977 		g = &pctrl->soc->groups[i];
978 		val = msm_readl_intr_status(pctrl, g);
979 		if (val & BIT(g->intr_status_bit)) {
980 			irq_pin = irq_find_mapping(gc->irq.domain, i);
981 			generic_handle_irq(irq_pin);
982 			handled++;
983 		}
984 	}
985 
986 	/* No interrupts were flagged */
987 	if (handled == 0)
988 		handle_bad_irq(desc);
989 
990 	chained_irq_exit(chip, desc);
991 }
992 
993 static bool msm_gpio_needs_valid_mask(struct msm_pinctrl *pctrl)
994 {
995 	if (pctrl->soc->reserved_gpios)
996 		return true;
997 
998 	return device_property_count_u16(pctrl->dev, "gpios") > 0;
999 }
1000 
1001 static int msm_gpio_init(struct msm_pinctrl *pctrl)
1002 {
1003 	struct gpio_chip *chip;
1004 	struct gpio_irq_chip *girq;
1005 	int ret;
1006 	unsigned ngpio = pctrl->soc->ngpios;
1007 
1008 	if (WARN_ON(ngpio > MAX_NR_GPIO))
1009 		return -EINVAL;
1010 
1011 	chip = &pctrl->chip;
1012 	chip->base = -1;
1013 	chip->ngpio = ngpio;
1014 	chip->label = dev_name(pctrl->dev);
1015 	chip->parent = pctrl->dev;
1016 	chip->owner = THIS_MODULE;
1017 	chip->of_node = pctrl->dev->of_node;
1018 	if (msm_gpio_needs_valid_mask(pctrl))
1019 		chip->init_valid_mask = msm_gpio_init_valid_mask;
1020 
1021 	pctrl->irq_chip.name = "msmgpio";
1022 	pctrl->irq_chip.irq_enable = msm_gpio_irq_enable;
1023 	pctrl->irq_chip.irq_mask = msm_gpio_irq_mask;
1024 	pctrl->irq_chip.irq_unmask = msm_gpio_irq_unmask;
1025 	pctrl->irq_chip.irq_ack = msm_gpio_irq_ack;
1026 	pctrl->irq_chip.irq_set_type = msm_gpio_irq_set_type;
1027 	pctrl->irq_chip.irq_set_wake = msm_gpio_irq_set_wake;
1028 	pctrl->irq_chip.irq_request_resources = msm_gpio_irq_reqres;
1029 	pctrl->irq_chip.irq_release_resources = msm_gpio_irq_relres;
1030 
1031 	girq = &chip->irq;
1032 	girq->chip = &pctrl->irq_chip;
1033 	girq->parent_handler = msm_gpio_irq_handler;
1034 	girq->num_parents = 1;
1035 	girq->parents = devm_kcalloc(pctrl->dev, 1, sizeof(*girq->parents),
1036 				     GFP_KERNEL);
1037 	if (!girq->parents)
1038 		return -ENOMEM;
1039 	girq->default_type = IRQ_TYPE_NONE;
1040 	girq->handler = handle_bad_irq;
1041 	girq->parents[0] = pctrl->irq;
1042 
1043 	ret = gpiochip_add_data(&pctrl->chip, pctrl);
1044 	if (ret) {
1045 		dev_err(pctrl->dev, "Failed register gpiochip\n");
1046 		return ret;
1047 	}
1048 
1049 	/*
1050 	 * For DeviceTree-supported systems, the gpio core checks the
1051 	 * pinctrl's device node for the "gpio-ranges" property.
1052 	 * If it is present, it takes care of adding the pin ranges
1053 	 * for the driver. In this case the driver can skip ahead.
1054 	 *
1055 	 * In order to remain compatible with older, existing DeviceTree
1056 	 * files which don't set the "gpio-ranges" property or systems that
1057 	 * utilize ACPI the driver has to call gpiochip_add_pin_range().
1058 	 */
1059 	if (!of_property_read_bool(pctrl->dev->of_node, "gpio-ranges")) {
1060 		ret = gpiochip_add_pin_range(&pctrl->chip,
1061 			dev_name(pctrl->dev), 0, 0, chip->ngpio);
1062 		if (ret) {
1063 			dev_err(pctrl->dev, "Failed to add pin range\n");
1064 			gpiochip_remove(&pctrl->chip);
1065 			return ret;
1066 		}
1067 	}
1068 
1069 	return 0;
1070 }
1071 
1072 static int msm_ps_hold_restart(struct notifier_block *nb, unsigned long action,
1073 			       void *data)
1074 {
1075 	struct msm_pinctrl *pctrl = container_of(nb, struct msm_pinctrl, restart_nb);
1076 
1077 	writel(0, pctrl->regs[0] + PS_HOLD_OFFSET);
1078 	mdelay(1000);
1079 	return NOTIFY_DONE;
1080 }
1081 
1082 static struct msm_pinctrl *poweroff_pctrl;
1083 
1084 static void msm_ps_hold_poweroff(void)
1085 {
1086 	msm_ps_hold_restart(&poweroff_pctrl->restart_nb, 0, NULL);
1087 }
1088 
1089 static void msm_pinctrl_setup_pm_reset(struct msm_pinctrl *pctrl)
1090 {
1091 	int i;
1092 	const struct msm_function *func = pctrl->soc->functions;
1093 
1094 	for (i = 0; i < pctrl->soc->nfunctions; i++)
1095 		if (!strcmp(func[i].name, "ps_hold")) {
1096 			pctrl->restart_nb.notifier_call = msm_ps_hold_restart;
1097 			pctrl->restart_nb.priority = 128;
1098 			if (register_restart_handler(&pctrl->restart_nb))
1099 				dev_err(pctrl->dev,
1100 					"failed to setup restart handler.\n");
1101 			poweroff_pctrl = pctrl;
1102 			pm_power_off = msm_ps_hold_poweroff;
1103 			break;
1104 		}
1105 }
1106 
1107 static __maybe_unused int msm_pinctrl_suspend(struct device *dev)
1108 {
1109 	struct msm_pinctrl *pctrl = dev_get_drvdata(dev);
1110 
1111 	return pinctrl_force_sleep(pctrl->pctrl);
1112 }
1113 
1114 static __maybe_unused int msm_pinctrl_resume(struct device *dev)
1115 {
1116 	struct msm_pinctrl *pctrl = dev_get_drvdata(dev);
1117 
1118 	return pinctrl_force_default(pctrl->pctrl);
1119 }
1120 
1121 SIMPLE_DEV_PM_OPS(msm_pinctrl_dev_pm_ops, msm_pinctrl_suspend,
1122 		  msm_pinctrl_resume);
1123 
1124 EXPORT_SYMBOL(msm_pinctrl_dev_pm_ops);
1125 
1126 int msm_pinctrl_probe(struct platform_device *pdev,
1127 		      const struct msm_pinctrl_soc_data *soc_data)
1128 {
1129 	struct msm_pinctrl *pctrl;
1130 	struct resource *res;
1131 	int ret;
1132 	int i;
1133 
1134 	pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
1135 	if (!pctrl)
1136 		return -ENOMEM;
1137 
1138 	pctrl->dev = &pdev->dev;
1139 	pctrl->soc = soc_data;
1140 	pctrl->chip = msm_gpio_template;
1141 
1142 	raw_spin_lock_init(&pctrl->lock);
1143 
1144 	if (soc_data->tiles) {
1145 		for (i = 0; i < soc_data->ntiles; i++) {
1146 			res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1147 							   soc_data->tiles[i]);
1148 			pctrl->regs[i] = devm_ioremap_resource(&pdev->dev, res);
1149 			if (IS_ERR(pctrl->regs[i]))
1150 				return PTR_ERR(pctrl->regs[i]);
1151 		}
1152 	} else {
1153 		res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1154 		pctrl->regs[0] = devm_ioremap_resource(&pdev->dev, res);
1155 		if (IS_ERR(pctrl->regs[0]))
1156 			return PTR_ERR(pctrl->regs[0]);
1157 	}
1158 
1159 	msm_pinctrl_setup_pm_reset(pctrl);
1160 
1161 	pctrl->irq = platform_get_irq(pdev, 0);
1162 	if (pctrl->irq < 0)
1163 		return pctrl->irq;
1164 
1165 	pctrl->desc.owner = THIS_MODULE;
1166 	pctrl->desc.pctlops = &msm_pinctrl_ops;
1167 	pctrl->desc.pmxops = &msm_pinmux_ops;
1168 	pctrl->desc.confops = &msm_pinconf_ops;
1169 	pctrl->desc.name = dev_name(&pdev->dev);
1170 	pctrl->desc.pins = pctrl->soc->pins;
1171 	pctrl->desc.npins = pctrl->soc->npins;
1172 
1173 	pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &pctrl->desc, pctrl);
1174 	if (IS_ERR(pctrl->pctrl)) {
1175 		dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
1176 		return PTR_ERR(pctrl->pctrl);
1177 	}
1178 
1179 	ret = msm_gpio_init(pctrl);
1180 	if (ret)
1181 		return ret;
1182 
1183 	platform_set_drvdata(pdev, pctrl);
1184 
1185 	dev_dbg(&pdev->dev, "Probed Qualcomm pinctrl driver\n");
1186 
1187 	return 0;
1188 }
1189 EXPORT_SYMBOL(msm_pinctrl_probe);
1190 
1191 int msm_pinctrl_remove(struct platform_device *pdev)
1192 {
1193 	struct msm_pinctrl *pctrl = platform_get_drvdata(pdev);
1194 
1195 	gpiochip_remove(&pctrl->chip);
1196 
1197 	unregister_restart_handler(&pctrl->restart_nb);
1198 
1199 	return 0;
1200 }
1201 EXPORT_SYMBOL(msm_pinctrl_remove);
1202 
1203