1 /* 2 * Copyright (c) 2013, Sony Mobile Communications AB. 3 * Copyright (c) 2013, The Linux Foundation. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 and 7 * only version 2 as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 */ 14 15 #include <linux/delay.h> 16 #include <linux/err.h> 17 #include <linux/io.h> 18 #include <linux/module.h> 19 #include <linux/of.h> 20 #include <linux/platform_device.h> 21 #include <linux/pinctrl/machine.h> 22 #include <linux/pinctrl/pinctrl.h> 23 #include <linux/pinctrl/pinmux.h> 24 #include <linux/pinctrl/pinconf.h> 25 #include <linux/pinctrl/pinconf-generic.h> 26 #include <linux/slab.h> 27 #include <linux/gpio.h> 28 #include <linux/interrupt.h> 29 #include <linux/spinlock.h> 30 #include <linux/reboot.h> 31 #include <linux/pm.h> 32 #include <linux/log2.h> 33 34 #include "../core.h" 35 #include "../pinconf.h" 36 #include "pinctrl-msm.h" 37 #include "../pinctrl-utils.h" 38 39 #define MAX_NR_GPIO 300 40 #define PS_HOLD_OFFSET 0x820 41 42 /** 43 * struct msm_pinctrl - state for a pinctrl-msm device 44 * @dev: device handle. 45 * @pctrl: pinctrl handle. 46 * @chip: gpiochip handle. 47 * @restart_nb: restart notifier block. 48 * @irq: parent irq for the TLMM irq_chip. 49 * @lock: Spinlock to protect register resources as well 50 * as msm_pinctrl data structures. 51 * @enabled_irqs: Bitmap of currently enabled irqs. 52 * @dual_edge_irqs: Bitmap of irqs that need sw emulated dual edge 53 * detection. 54 * @soc; Reference to soc_data of platform specific data. 55 * @regs: Base address for the TLMM register map. 56 */ 57 struct msm_pinctrl { 58 struct device *dev; 59 struct pinctrl_dev *pctrl; 60 struct gpio_chip chip; 61 struct notifier_block restart_nb; 62 int irq; 63 64 raw_spinlock_t lock; 65 66 DECLARE_BITMAP(dual_edge_irqs, MAX_NR_GPIO); 67 DECLARE_BITMAP(enabled_irqs, MAX_NR_GPIO); 68 69 const struct msm_pinctrl_soc_data *soc; 70 void __iomem *regs; 71 }; 72 73 static int msm_get_groups_count(struct pinctrl_dev *pctldev) 74 { 75 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 76 77 return pctrl->soc->ngroups; 78 } 79 80 static const char *msm_get_group_name(struct pinctrl_dev *pctldev, 81 unsigned group) 82 { 83 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 84 85 return pctrl->soc->groups[group].name; 86 } 87 88 static int msm_get_group_pins(struct pinctrl_dev *pctldev, 89 unsigned group, 90 const unsigned **pins, 91 unsigned *num_pins) 92 { 93 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 94 95 *pins = pctrl->soc->groups[group].pins; 96 *num_pins = pctrl->soc->groups[group].npins; 97 return 0; 98 } 99 100 static const struct pinctrl_ops msm_pinctrl_ops = { 101 .get_groups_count = msm_get_groups_count, 102 .get_group_name = msm_get_group_name, 103 .get_group_pins = msm_get_group_pins, 104 .dt_node_to_map = pinconf_generic_dt_node_to_map_group, 105 .dt_free_map = pinctrl_utils_free_map, 106 }; 107 108 static int msm_get_functions_count(struct pinctrl_dev *pctldev) 109 { 110 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 111 112 return pctrl->soc->nfunctions; 113 } 114 115 static const char *msm_get_function_name(struct pinctrl_dev *pctldev, 116 unsigned function) 117 { 118 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 119 120 return pctrl->soc->functions[function].name; 121 } 122 123 static int msm_get_function_groups(struct pinctrl_dev *pctldev, 124 unsigned function, 125 const char * const **groups, 126 unsigned * const num_groups) 127 { 128 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 129 130 *groups = pctrl->soc->functions[function].groups; 131 *num_groups = pctrl->soc->functions[function].ngroups; 132 return 0; 133 } 134 135 static int msm_pinmux_set_mux(struct pinctrl_dev *pctldev, 136 unsigned function, 137 unsigned group) 138 { 139 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 140 const struct msm_pingroup *g; 141 unsigned long flags; 142 u32 val, mask; 143 int i; 144 145 g = &pctrl->soc->groups[group]; 146 mask = GENMASK(g->mux_bit + order_base_2(g->nfuncs) - 1, g->mux_bit); 147 148 for (i = 0; i < g->nfuncs; i++) { 149 if (g->funcs[i] == function) 150 break; 151 } 152 153 if (WARN_ON(i == g->nfuncs)) 154 return -EINVAL; 155 156 raw_spin_lock_irqsave(&pctrl->lock, flags); 157 158 val = readl(pctrl->regs + g->ctl_reg); 159 val &= ~mask; 160 val |= i << g->mux_bit; 161 writel(val, pctrl->regs + g->ctl_reg); 162 163 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 164 165 return 0; 166 } 167 168 static const struct pinmux_ops msm_pinmux_ops = { 169 .get_functions_count = msm_get_functions_count, 170 .get_function_name = msm_get_function_name, 171 .get_function_groups = msm_get_function_groups, 172 .set_mux = msm_pinmux_set_mux, 173 }; 174 175 static int msm_config_reg(struct msm_pinctrl *pctrl, 176 const struct msm_pingroup *g, 177 unsigned param, 178 unsigned *mask, 179 unsigned *bit) 180 { 181 switch (param) { 182 case PIN_CONFIG_BIAS_DISABLE: 183 case PIN_CONFIG_BIAS_PULL_DOWN: 184 case PIN_CONFIG_BIAS_BUS_HOLD: 185 case PIN_CONFIG_BIAS_PULL_UP: 186 *bit = g->pull_bit; 187 *mask = 3; 188 break; 189 case PIN_CONFIG_DRIVE_STRENGTH: 190 *bit = g->drv_bit; 191 *mask = 7; 192 break; 193 case PIN_CONFIG_OUTPUT: 194 case PIN_CONFIG_INPUT_ENABLE: 195 *bit = g->oe_bit; 196 *mask = 1; 197 break; 198 default: 199 return -ENOTSUPP; 200 } 201 202 return 0; 203 } 204 205 #define MSM_NO_PULL 0 206 #define MSM_PULL_DOWN 1 207 #define MSM_KEEPER 2 208 #define MSM_PULL_UP_NO_KEEPER 2 209 #define MSM_PULL_UP 3 210 211 static unsigned msm_regval_to_drive(u32 val) 212 { 213 return (val + 1) * 2; 214 } 215 216 static int msm_config_group_get(struct pinctrl_dev *pctldev, 217 unsigned int group, 218 unsigned long *config) 219 { 220 const struct msm_pingroup *g; 221 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 222 unsigned param = pinconf_to_config_param(*config); 223 unsigned mask; 224 unsigned arg; 225 unsigned bit; 226 int ret; 227 u32 val; 228 229 g = &pctrl->soc->groups[group]; 230 231 ret = msm_config_reg(pctrl, g, param, &mask, &bit); 232 if (ret < 0) 233 return ret; 234 235 val = readl(pctrl->regs + g->ctl_reg); 236 arg = (val >> bit) & mask; 237 238 /* Convert register value to pinconf value */ 239 switch (param) { 240 case PIN_CONFIG_BIAS_DISABLE: 241 arg = arg == MSM_NO_PULL; 242 break; 243 case PIN_CONFIG_BIAS_PULL_DOWN: 244 arg = arg == MSM_PULL_DOWN; 245 break; 246 case PIN_CONFIG_BIAS_BUS_HOLD: 247 if (pctrl->soc->pull_no_keeper) 248 return -ENOTSUPP; 249 250 arg = arg == MSM_KEEPER; 251 break; 252 case PIN_CONFIG_BIAS_PULL_UP: 253 if (pctrl->soc->pull_no_keeper) 254 arg = arg == MSM_PULL_UP_NO_KEEPER; 255 else 256 arg = arg == MSM_PULL_UP; 257 break; 258 case PIN_CONFIG_DRIVE_STRENGTH: 259 arg = msm_regval_to_drive(arg); 260 break; 261 case PIN_CONFIG_OUTPUT: 262 /* Pin is not output */ 263 if (!arg) 264 return -EINVAL; 265 266 val = readl(pctrl->regs + g->io_reg); 267 arg = !!(val & BIT(g->in_bit)); 268 break; 269 case PIN_CONFIG_INPUT_ENABLE: 270 /* Pin is output */ 271 if (arg) 272 return -EINVAL; 273 arg = 1; 274 break; 275 default: 276 return -ENOTSUPP; 277 } 278 279 *config = pinconf_to_config_packed(param, arg); 280 281 return 0; 282 } 283 284 static int msm_config_group_set(struct pinctrl_dev *pctldev, 285 unsigned group, 286 unsigned long *configs, 287 unsigned num_configs) 288 { 289 const struct msm_pingroup *g; 290 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 291 unsigned long flags; 292 unsigned param; 293 unsigned mask; 294 unsigned arg; 295 unsigned bit; 296 int ret; 297 u32 val; 298 int i; 299 300 g = &pctrl->soc->groups[group]; 301 302 for (i = 0; i < num_configs; i++) { 303 param = pinconf_to_config_param(configs[i]); 304 arg = pinconf_to_config_argument(configs[i]); 305 306 ret = msm_config_reg(pctrl, g, param, &mask, &bit); 307 if (ret < 0) 308 return ret; 309 310 /* Convert pinconf values to register values */ 311 switch (param) { 312 case PIN_CONFIG_BIAS_DISABLE: 313 arg = MSM_NO_PULL; 314 break; 315 case PIN_CONFIG_BIAS_PULL_DOWN: 316 arg = MSM_PULL_DOWN; 317 break; 318 case PIN_CONFIG_BIAS_BUS_HOLD: 319 if (pctrl->soc->pull_no_keeper) 320 return -ENOTSUPP; 321 322 arg = MSM_KEEPER; 323 break; 324 case PIN_CONFIG_BIAS_PULL_UP: 325 if (pctrl->soc->pull_no_keeper) 326 arg = MSM_PULL_UP_NO_KEEPER; 327 else 328 arg = MSM_PULL_UP; 329 break; 330 case PIN_CONFIG_DRIVE_STRENGTH: 331 /* Check for invalid values */ 332 if (arg > 16 || arg < 2 || (arg % 2) != 0) 333 arg = -1; 334 else 335 arg = (arg / 2) - 1; 336 break; 337 case PIN_CONFIG_OUTPUT: 338 /* set output value */ 339 raw_spin_lock_irqsave(&pctrl->lock, flags); 340 val = readl(pctrl->regs + g->io_reg); 341 if (arg) 342 val |= BIT(g->out_bit); 343 else 344 val &= ~BIT(g->out_bit); 345 writel(val, pctrl->regs + g->io_reg); 346 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 347 348 /* enable output */ 349 arg = 1; 350 break; 351 case PIN_CONFIG_INPUT_ENABLE: 352 /* disable output */ 353 arg = 0; 354 break; 355 default: 356 dev_err(pctrl->dev, "Unsupported config parameter: %x\n", 357 param); 358 return -EINVAL; 359 } 360 361 /* Range-check user-supplied value */ 362 if (arg & ~mask) { 363 dev_err(pctrl->dev, "config %x: %x is invalid\n", param, arg); 364 return -EINVAL; 365 } 366 367 raw_spin_lock_irqsave(&pctrl->lock, flags); 368 val = readl(pctrl->regs + g->ctl_reg); 369 val &= ~(mask << bit); 370 val |= arg << bit; 371 writel(val, pctrl->regs + g->ctl_reg); 372 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 373 } 374 375 return 0; 376 } 377 378 static const struct pinconf_ops msm_pinconf_ops = { 379 .is_generic = true, 380 .pin_config_group_get = msm_config_group_get, 381 .pin_config_group_set = msm_config_group_set, 382 }; 383 384 static struct pinctrl_desc msm_pinctrl_desc = { 385 .pctlops = &msm_pinctrl_ops, 386 .pmxops = &msm_pinmux_ops, 387 .confops = &msm_pinconf_ops, 388 .owner = THIS_MODULE, 389 }; 390 391 static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 392 { 393 const struct msm_pingroup *g; 394 struct msm_pinctrl *pctrl = gpiochip_get_data(chip); 395 unsigned long flags; 396 u32 val; 397 398 g = &pctrl->soc->groups[offset]; 399 400 raw_spin_lock_irqsave(&pctrl->lock, flags); 401 402 val = readl(pctrl->regs + g->ctl_reg); 403 val &= ~BIT(g->oe_bit); 404 writel(val, pctrl->regs + g->ctl_reg); 405 406 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 407 408 return 0; 409 } 410 411 static int msm_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value) 412 { 413 const struct msm_pingroup *g; 414 struct msm_pinctrl *pctrl = gpiochip_get_data(chip); 415 unsigned long flags; 416 u32 val; 417 418 g = &pctrl->soc->groups[offset]; 419 420 raw_spin_lock_irqsave(&pctrl->lock, flags); 421 422 val = readl(pctrl->regs + g->io_reg); 423 if (value) 424 val |= BIT(g->out_bit); 425 else 426 val &= ~BIT(g->out_bit); 427 writel(val, pctrl->regs + g->io_reg); 428 429 val = readl(pctrl->regs + g->ctl_reg); 430 val |= BIT(g->oe_bit); 431 writel(val, pctrl->regs + g->ctl_reg); 432 433 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 434 435 return 0; 436 } 437 438 static int msm_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 439 { 440 struct msm_pinctrl *pctrl = gpiochip_get_data(chip); 441 const struct msm_pingroup *g; 442 u32 val; 443 444 g = &pctrl->soc->groups[offset]; 445 446 val = readl(pctrl->regs + g->ctl_reg); 447 448 /* 0 = output, 1 = input */ 449 return val & BIT(g->oe_bit) ? 0 : 1; 450 } 451 452 static int msm_gpio_get(struct gpio_chip *chip, unsigned offset) 453 { 454 const struct msm_pingroup *g; 455 struct msm_pinctrl *pctrl = gpiochip_get_data(chip); 456 u32 val; 457 458 g = &pctrl->soc->groups[offset]; 459 460 val = readl(pctrl->regs + g->io_reg); 461 return !!(val & BIT(g->in_bit)); 462 } 463 464 static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 465 { 466 const struct msm_pingroup *g; 467 struct msm_pinctrl *pctrl = gpiochip_get_data(chip); 468 unsigned long flags; 469 u32 val; 470 471 g = &pctrl->soc->groups[offset]; 472 473 raw_spin_lock_irqsave(&pctrl->lock, flags); 474 475 val = readl(pctrl->regs + g->io_reg); 476 if (value) 477 val |= BIT(g->out_bit); 478 else 479 val &= ~BIT(g->out_bit); 480 writel(val, pctrl->regs + g->io_reg); 481 482 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 483 } 484 485 #ifdef CONFIG_DEBUG_FS 486 #include <linux/seq_file.h> 487 488 static void msm_gpio_dbg_show_one(struct seq_file *s, 489 struct pinctrl_dev *pctldev, 490 struct gpio_chip *chip, 491 unsigned offset, 492 unsigned gpio) 493 { 494 const struct msm_pingroup *g; 495 struct msm_pinctrl *pctrl = gpiochip_get_data(chip); 496 unsigned func; 497 int is_out; 498 int drive; 499 int pull; 500 u32 ctl_reg; 501 502 static const char * const pulls[] = { 503 "no pull", 504 "pull down", 505 "keeper", 506 "pull up" 507 }; 508 509 g = &pctrl->soc->groups[offset]; 510 ctl_reg = readl(pctrl->regs + g->ctl_reg); 511 512 is_out = !!(ctl_reg & BIT(g->oe_bit)); 513 func = (ctl_reg >> g->mux_bit) & 7; 514 drive = (ctl_reg >> g->drv_bit) & 7; 515 pull = (ctl_reg >> g->pull_bit) & 3; 516 517 seq_printf(s, " %-8s: %-3s %d", g->name, is_out ? "out" : "in", func); 518 seq_printf(s, " %dmA", msm_regval_to_drive(drive)); 519 seq_printf(s, " %s", pulls[pull]); 520 } 521 522 static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) 523 { 524 unsigned gpio = chip->base; 525 unsigned i; 526 527 for (i = 0; i < chip->ngpio; i++, gpio++) { 528 msm_gpio_dbg_show_one(s, NULL, chip, i, gpio); 529 seq_puts(s, "\n"); 530 } 531 } 532 533 #else 534 #define msm_gpio_dbg_show NULL 535 #endif 536 537 static const struct gpio_chip msm_gpio_template = { 538 .direction_input = msm_gpio_direction_input, 539 .direction_output = msm_gpio_direction_output, 540 .get_direction = msm_gpio_get_direction, 541 .get = msm_gpio_get, 542 .set = msm_gpio_set, 543 .request = gpiochip_generic_request, 544 .free = gpiochip_generic_free, 545 .dbg_show = msm_gpio_dbg_show, 546 }; 547 548 /* For dual-edge interrupts in software, since some hardware has no 549 * such support: 550 * 551 * At appropriate moments, this function may be called to flip the polarity 552 * settings of both-edge irq lines to try and catch the next edge. 553 * 554 * The attempt is considered successful if: 555 * - the status bit goes high, indicating that an edge was caught, or 556 * - the input value of the gpio doesn't change during the attempt. 557 * If the value changes twice during the process, that would cause the first 558 * test to fail but would force the second, as two opposite 559 * transitions would cause a detection no matter the polarity setting. 560 * 561 * The do-loop tries to sledge-hammer closed the timing hole between 562 * the initial value-read and the polarity-write - if the line value changes 563 * during that window, an interrupt is lost, the new polarity setting is 564 * incorrect, and the first success test will fail, causing a retry. 565 * 566 * Algorithm comes from Google's msmgpio driver. 567 */ 568 static void msm_gpio_update_dual_edge_pos(struct msm_pinctrl *pctrl, 569 const struct msm_pingroup *g, 570 struct irq_data *d) 571 { 572 int loop_limit = 100; 573 unsigned val, val2, intstat; 574 unsigned pol; 575 576 do { 577 val = readl(pctrl->regs + g->io_reg) & BIT(g->in_bit); 578 579 pol = readl(pctrl->regs + g->intr_cfg_reg); 580 pol ^= BIT(g->intr_polarity_bit); 581 writel(pol, pctrl->regs + g->intr_cfg_reg); 582 583 val2 = readl(pctrl->regs + g->io_reg) & BIT(g->in_bit); 584 intstat = readl(pctrl->regs + g->intr_status_reg); 585 if (intstat || (val == val2)) 586 return; 587 } while (loop_limit-- > 0); 588 dev_err(pctrl->dev, "dual-edge irq failed to stabilize, %#08x != %#08x\n", 589 val, val2); 590 } 591 592 static void msm_gpio_irq_mask(struct irq_data *d) 593 { 594 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 595 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); 596 const struct msm_pingroup *g; 597 unsigned long flags; 598 u32 val; 599 600 g = &pctrl->soc->groups[d->hwirq]; 601 602 raw_spin_lock_irqsave(&pctrl->lock, flags); 603 604 val = readl(pctrl->regs + g->intr_cfg_reg); 605 val &= ~BIT(g->intr_enable_bit); 606 writel(val, pctrl->regs + g->intr_cfg_reg); 607 608 clear_bit(d->hwirq, pctrl->enabled_irqs); 609 610 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 611 } 612 613 static void msm_gpio_irq_unmask(struct irq_data *d) 614 { 615 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 616 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); 617 const struct msm_pingroup *g; 618 unsigned long flags; 619 u32 val; 620 621 g = &pctrl->soc->groups[d->hwirq]; 622 623 raw_spin_lock_irqsave(&pctrl->lock, flags); 624 625 val = readl(pctrl->regs + g->intr_cfg_reg); 626 val |= BIT(g->intr_enable_bit); 627 writel(val, pctrl->regs + g->intr_cfg_reg); 628 629 set_bit(d->hwirq, pctrl->enabled_irqs); 630 631 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 632 } 633 634 static void msm_gpio_irq_ack(struct irq_data *d) 635 { 636 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 637 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); 638 const struct msm_pingroup *g; 639 unsigned long flags; 640 u32 val; 641 642 g = &pctrl->soc->groups[d->hwirq]; 643 644 raw_spin_lock_irqsave(&pctrl->lock, flags); 645 646 val = readl(pctrl->regs + g->intr_status_reg); 647 if (g->intr_ack_high) 648 val |= BIT(g->intr_status_bit); 649 else 650 val &= ~BIT(g->intr_status_bit); 651 writel(val, pctrl->regs + g->intr_status_reg); 652 653 if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) 654 msm_gpio_update_dual_edge_pos(pctrl, g, d); 655 656 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 657 } 658 659 static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type) 660 { 661 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 662 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); 663 const struct msm_pingroup *g; 664 unsigned long flags; 665 u32 val; 666 667 g = &pctrl->soc->groups[d->hwirq]; 668 669 raw_spin_lock_irqsave(&pctrl->lock, flags); 670 671 /* 672 * For hw without possibility of detecting both edges 673 */ 674 if (g->intr_detection_width == 1 && type == IRQ_TYPE_EDGE_BOTH) 675 set_bit(d->hwirq, pctrl->dual_edge_irqs); 676 else 677 clear_bit(d->hwirq, pctrl->dual_edge_irqs); 678 679 /* Route interrupts to application cpu */ 680 val = readl(pctrl->regs + g->intr_target_reg); 681 val &= ~(7 << g->intr_target_bit); 682 val |= g->intr_target_kpss_val << g->intr_target_bit; 683 writel(val, pctrl->regs + g->intr_target_reg); 684 685 /* Update configuration for gpio. 686 * RAW_STATUS_EN is left on for all gpio irqs. Due to the 687 * internal circuitry of TLMM, toggling the RAW_STATUS 688 * could cause the INTR_STATUS to be set for EDGE interrupts. 689 */ 690 val = readl(pctrl->regs + g->intr_cfg_reg); 691 val |= BIT(g->intr_raw_status_bit); 692 if (g->intr_detection_width == 2) { 693 val &= ~(3 << g->intr_detection_bit); 694 val &= ~(1 << g->intr_polarity_bit); 695 switch (type) { 696 case IRQ_TYPE_EDGE_RISING: 697 val |= 1 << g->intr_detection_bit; 698 val |= BIT(g->intr_polarity_bit); 699 break; 700 case IRQ_TYPE_EDGE_FALLING: 701 val |= 2 << g->intr_detection_bit; 702 val |= BIT(g->intr_polarity_bit); 703 break; 704 case IRQ_TYPE_EDGE_BOTH: 705 val |= 3 << g->intr_detection_bit; 706 val |= BIT(g->intr_polarity_bit); 707 break; 708 case IRQ_TYPE_LEVEL_LOW: 709 break; 710 case IRQ_TYPE_LEVEL_HIGH: 711 val |= BIT(g->intr_polarity_bit); 712 break; 713 } 714 } else if (g->intr_detection_width == 1) { 715 val &= ~(1 << g->intr_detection_bit); 716 val &= ~(1 << g->intr_polarity_bit); 717 switch (type) { 718 case IRQ_TYPE_EDGE_RISING: 719 val |= BIT(g->intr_detection_bit); 720 val |= BIT(g->intr_polarity_bit); 721 break; 722 case IRQ_TYPE_EDGE_FALLING: 723 val |= BIT(g->intr_detection_bit); 724 break; 725 case IRQ_TYPE_EDGE_BOTH: 726 val |= BIT(g->intr_detection_bit); 727 val |= BIT(g->intr_polarity_bit); 728 break; 729 case IRQ_TYPE_LEVEL_LOW: 730 break; 731 case IRQ_TYPE_LEVEL_HIGH: 732 val |= BIT(g->intr_polarity_bit); 733 break; 734 } 735 } else { 736 BUG(); 737 } 738 writel(val, pctrl->regs + g->intr_cfg_reg); 739 740 if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) 741 msm_gpio_update_dual_edge_pos(pctrl, g, d); 742 743 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 744 745 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) 746 irq_set_handler_locked(d, handle_level_irq); 747 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) 748 irq_set_handler_locked(d, handle_edge_irq); 749 750 return 0; 751 } 752 753 static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on) 754 { 755 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 756 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); 757 unsigned long flags; 758 759 raw_spin_lock_irqsave(&pctrl->lock, flags); 760 761 irq_set_irq_wake(pctrl->irq, on); 762 763 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 764 765 return 0; 766 } 767 768 static struct irq_chip msm_gpio_irq_chip = { 769 .name = "msmgpio", 770 .irq_mask = msm_gpio_irq_mask, 771 .irq_unmask = msm_gpio_irq_unmask, 772 .irq_ack = msm_gpio_irq_ack, 773 .irq_set_type = msm_gpio_irq_set_type, 774 .irq_set_wake = msm_gpio_irq_set_wake, 775 }; 776 777 static void msm_gpio_irq_handler(struct irq_desc *desc) 778 { 779 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 780 const struct msm_pingroup *g; 781 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); 782 struct irq_chip *chip = irq_desc_get_chip(desc); 783 int irq_pin; 784 int handled = 0; 785 u32 val; 786 int i; 787 788 chained_irq_enter(chip, desc); 789 790 /* 791 * Each pin has it's own IRQ status register, so use 792 * enabled_irq bitmap to limit the number of reads. 793 */ 794 for_each_set_bit(i, pctrl->enabled_irqs, pctrl->chip.ngpio) { 795 g = &pctrl->soc->groups[i]; 796 val = readl(pctrl->regs + g->intr_status_reg); 797 if (val & BIT(g->intr_status_bit)) { 798 irq_pin = irq_find_mapping(gc->irqdomain, i); 799 generic_handle_irq(irq_pin); 800 handled++; 801 } 802 } 803 804 /* No interrupts were flagged */ 805 if (handled == 0) 806 handle_bad_irq(desc); 807 808 chained_irq_exit(chip, desc); 809 } 810 811 static int msm_gpio_init(struct msm_pinctrl *pctrl) 812 { 813 struct gpio_chip *chip; 814 int ret; 815 unsigned ngpio = pctrl->soc->ngpios; 816 817 if (WARN_ON(ngpio > MAX_NR_GPIO)) 818 return -EINVAL; 819 820 chip = &pctrl->chip; 821 chip->base = 0; 822 chip->ngpio = ngpio; 823 chip->label = dev_name(pctrl->dev); 824 chip->parent = pctrl->dev; 825 chip->owner = THIS_MODULE; 826 chip->of_node = pctrl->dev->of_node; 827 828 ret = gpiochip_add_data(&pctrl->chip, pctrl); 829 if (ret) { 830 dev_err(pctrl->dev, "Failed register gpiochip\n"); 831 return ret; 832 } 833 834 ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), 0, 0, chip->ngpio); 835 if (ret) { 836 dev_err(pctrl->dev, "Failed to add pin range\n"); 837 gpiochip_remove(&pctrl->chip); 838 return ret; 839 } 840 841 ret = gpiochip_irqchip_add(chip, 842 &msm_gpio_irq_chip, 843 0, 844 handle_edge_irq, 845 IRQ_TYPE_NONE); 846 if (ret) { 847 dev_err(pctrl->dev, "Failed to add irqchip to gpiochip\n"); 848 gpiochip_remove(&pctrl->chip); 849 return -ENOSYS; 850 } 851 852 gpiochip_set_chained_irqchip(chip, &msm_gpio_irq_chip, pctrl->irq, 853 msm_gpio_irq_handler); 854 855 return 0; 856 } 857 858 static int msm_ps_hold_restart(struct notifier_block *nb, unsigned long action, 859 void *data) 860 { 861 struct msm_pinctrl *pctrl = container_of(nb, struct msm_pinctrl, restart_nb); 862 863 writel(0, pctrl->regs + PS_HOLD_OFFSET); 864 mdelay(1000); 865 return NOTIFY_DONE; 866 } 867 868 static struct msm_pinctrl *poweroff_pctrl; 869 870 static void msm_ps_hold_poweroff(void) 871 { 872 msm_ps_hold_restart(&poweroff_pctrl->restart_nb, 0, NULL); 873 } 874 875 static void msm_pinctrl_setup_pm_reset(struct msm_pinctrl *pctrl) 876 { 877 int i; 878 const struct msm_function *func = pctrl->soc->functions; 879 880 for (i = 0; i < pctrl->soc->nfunctions; i++) 881 if (!strcmp(func[i].name, "ps_hold")) { 882 pctrl->restart_nb.notifier_call = msm_ps_hold_restart; 883 pctrl->restart_nb.priority = 128; 884 if (register_restart_handler(&pctrl->restart_nb)) 885 dev_err(pctrl->dev, 886 "failed to setup restart handler.\n"); 887 poweroff_pctrl = pctrl; 888 pm_power_off = msm_ps_hold_poweroff; 889 break; 890 } 891 } 892 893 int msm_pinctrl_probe(struct platform_device *pdev, 894 const struct msm_pinctrl_soc_data *soc_data) 895 { 896 struct msm_pinctrl *pctrl; 897 struct resource *res; 898 int ret; 899 900 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); 901 if (!pctrl) { 902 dev_err(&pdev->dev, "Can't allocate msm_pinctrl\n"); 903 return -ENOMEM; 904 } 905 pctrl->dev = &pdev->dev; 906 pctrl->soc = soc_data; 907 pctrl->chip = msm_gpio_template; 908 909 raw_spin_lock_init(&pctrl->lock); 910 911 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 912 pctrl->regs = devm_ioremap_resource(&pdev->dev, res); 913 if (IS_ERR(pctrl->regs)) 914 return PTR_ERR(pctrl->regs); 915 916 msm_pinctrl_setup_pm_reset(pctrl); 917 918 pctrl->irq = platform_get_irq(pdev, 0); 919 if (pctrl->irq < 0) { 920 dev_err(&pdev->dev, "No interrupt defined for msmgpio\n"); 921 return pctrl->irq; 922 } 923 924 msm_pinctrl_desc.name = dev_name(&pdev->dev); 925 msm_pinctrl_desc.pins = pctrl->soc->pins; 926 msm_pinctrl_desc.npins = pctrl->soc->npins; 927 pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &msm_pinctrl_desc, 928 pctrl); 929 if (IS_ERR(pctrl->pctrl)) { 930 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); 931 return PTR_ERR(pctrl->pctrl); 932 } 933 934 ret = msm_gpio_init(pctrl); 935 if (ret) 936 return ret; 937 938 platform_set_drvdata(pdev, pctrl); 939 940 dev_dbg(&pdev->dev, "Probed Qualcomm pinctrl driver\n"); 941 942 return 0; 943 } 944 EXPORT_SYMBOL(msm_pinctrl_probe); 945 946 int msm_pinctrl_remove(struct platform_device *pdev) 947 { 948 struct msm_pinctrl *pctrl = platform_get_drvdata(pdev); 949 950 gpiochip_remove(&pctrl->chip); 951 952 unregister_restart_handler(&pctrl->restart_nb); 953 954 return 0; 955 } 956 EXPORT_SYMBOL(msm_pinctrl_remove); 957 958