1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2013, Sony Mobile Communications AB.
4  * Copyright (c) 2013, The Linux Foundation. All rights reserved.
5  */
6 
7 #include <linux/delay.h>
8 #include <linux/err.h>
9 #include <linux/gpio/driver.h>
10 #include <linux/interrupt.h>
11 #include <linux/io.h>
12 #include <linux/log2.h>
13 #include <linux/module.h>
14 #include <linux/of.h>
15 #include <linux/platform_device.h>
16 #include <linux/pm.h>
17 #include <linux/firmware/qcom/qcom_scm.h>
18 #include <linux/reboot.h>
19 #include <linux/seq_file.h>
20 #include <linux/slab.h>
21 #include <linux/spinlock.h>
22 
23 #include <linux/pinctrl/machine.h>
24 #include <linux/pinctrl/pinconf-generic.h>
25 #include <linux/pinctrl/pinconf.h>
26 #include <linux/pinctrl/pinmux.h>
27 
28 #include <linux/soc/qcom/irq.h>
29 
30 #include "../core.h"
31 #include "../pinconf.h"
32 #include "../pinctrl-utils.h"
33 
34 #include "pinctrl-msm.h"
35 
36 #define MAX_NR_GPIO 300
37 #define MAX_NR_TILES 4
38 #define PS_HOLD_OFFSET 0x820
39 
40 /**
41  * struct msm_pinctrl - state for a pinctrl-msm device
42  * @dev:            device handle.
43  * @pctrl:          pinctrl handle.
44  * @chip:           gpiochip handle.
45  * @desc:           pin controller descriptor
46  * @restart_nb:     restart notifier block.
47  * @irq:            parent irq for the TLMM irq_chip.
48  * @intr_target_use_scm: route irq to application cpu using scm calls
49  * @lock:           Spinlock to protect register resources as well
50  *                  as msm_pinctrl data structures.
51  * @enabled_irqs:   Bitmap of currently enabled irqs.
52  * @dual_edge_irqs: Bitmap of irqs that need sw emulated dual edge
53  *                  detection.
54  * @skip_wake_irqs: Skip IRQs that are handled by wakeup interrupt controller
55  * @disabled_for_mux: These IRQs were disabled because we muxed away.
56  * @ever_gpio:      This bit is set the first time we mux a pin to gpio_func.
57  * @soc:            Reference to soc_data of platform specific data.
58  * @regs:           Base addresses for the TLMM tiles.
59  * @phys_base:      Physical base address
60  */
61 struct msm_pinctrl {
62 	struct device *dev;
63 	struct pinctrl_dev *pctrl;
64 	struct gpio_chip chip;
65 	struct pinctrl_desc desc;
66 	struct notifier_block restart_nb;
67 
68 	int irq;
69 
70 	bool intr_target_use_scm;
71 
72 	raw_spinlock_t lock;
73 
74 	DECLARE_BITMAP(dual_edge_irqs, MAX_NR_GPIO);
75 	DECLARE_BITMAP(enabled_irqs, MAX_NR_GPIO);
76 	DECLARE_BITMAP(skip_wake_irqs, MAX_NR_GPIO);
77 	DECLARE_BITMAP(disabled_for_mux, MAX_NR_GPIO);
78 	DECLARE_BITMAP(ever_gpio, MAX_NR_GPIO);
79 
80 	const struct msm_pinctrl_soc_data *soc;
81 	void __iomem *regs[MAX_NR_TILES];
82 	u32 phys_base[MAX_NR_TILES];
83 };
84 
85 #define MSM_ACCESSOR(name) \
86 static u32 msm_readl_##name(struct msm_pinctrl *pctrl, \
87 			    const struct msm_pingroup *g) \
88 { \
89 	return readl(pctrl->regs[g->tile] + g->name##_reg); \
90 } \
91 static void msm_writel_##name(u32 val, struct msm_pinctrl *pctrl, \
92 			      const struct msm_pingroup *g) \
93 { \
94 	writel(val, pctrl->regs[g->tile] + g->name##_reg); \
95 }
96 
97 MSM_ACCESSOR(ctl)
98 MSM_ACCESSOR(io)
99 MSM_ACCESSOR(intr_cfg)
100 MSM_ACCESSOR(intr_status)
101 MSM_ACCESSOR(intr_target)
102 
103 static void msm_ack_intr_status(struct msm_pinctrl *pctrl,
104 				const struct msm_pingroup *g)
105 {
106 	u32 val = g->intr_ack_high ? BIT(g->intr_status_bit) : 0;
107 
108 	msm_writel_intr_status(val, pctrl, g);
109 }
110 
111 static int msm_get_groups_count(struct pinctrl_dev *pctldev)
112 {
113 	struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
114 
115 	return pctrl->soc->ngroups;
116 }
117 
118 static const char *msm_get_group_name(struct pinctrl_dev *pctldev,
119 				      unsigned group)
120 {
121 	struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
122 
123 	return pctrl->soc->groups[group].grp.name;
124 }
125 
126 static int msm_get_group_pins(struct pinctrl_dev *pctldev,
127 			      unsigned group,
128 			      const unsigned **pins,
129 			      unsigned *num_pins)
130 {
131 	struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
132 
133 	*pins = pctrl->soc->groups[group].grp.pins;
134 	*num_pins = pctrl->soc->groups[group].grp.npins;
135 	return 0;
136 }
137 
138 static const struct pinctrl_ops msm_pinctrl_ops = {
139 	.get_groups_count	= msm_get_groups_count,
140 	.get_group_name		= msm_get_group_name,
141 	.get_group_pins		= msm_get_group_pins,
142 	.dt_node_to_map		= pinconf_generic_dt_node_to_map_group,
143 	.dt_free_map		= pinctrl_utils_free_map,
144 };
145 
146 static int msm_pinmux_request(struct pinctrl_dev *pctldev, unsigned offset)
147 {
148 	struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
149 	struct gpio_chip *chip = &pctrl->chip;
150 
151 	return gpiochip_line_is_valid(chip, offset) ? 0 : -EINVAL;
152 }
153 
154 static int msm_get_functions_count(struct pinctrl_dev *pctldev)
155 {
156 	struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
157 
158 	return pctrl->soc->nfunctions;
159 }
160 
161 static const char *msm_get_function_name(struct pinctrl_dev *pctldev,
162 					 unsigned function)
163 {
164 	struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
165 
166 	return pctrl->soc->functions[function].name;
167 }
168 
169 static int msm_get_function_groups(struct pinctrl_dev *pctldev,
170 				   unsigned function,
171 				   const char * const **groups,
172 				   unsigned * const num_groups)
173 {
174 	struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
175 
176 	*groups = pctrl->soc->functions[function].groups;
177 	*num_groups = pctrl->soc->functions[function].ngroups;
178 	return 0;
179 }
180 
181 static int msm_pinmux_set_mux(struct pinctrl_dev *pctldev,
182 			      unsigned function,
183 			      unsigned group)
184 {
185 	struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
186 	struct gpio_chip *gc = &pctrl->chip;
187 	unsigned int irq = irq_find_mapping(gc->irq.domain, group);
188 	struct irq_data *d = irq_get_irq_data(irq);
189 	unsigned int gpio_func = pctrl->soc->gpio_func;
190 	unsigned int egpio_func = pctrl->soc->egpio_func;
191 	const struct msm_pingroup *g;
192 	unsigned long flags;
193 	u32 val, mask;
194 	int i;
195 
196 	g = &pctrl->soc->groups[group];
197 	mask = GENMASK(g->mux_bit + order_base_2(g->nfuncs) - 1, g->mux_bit);
198 
199 	for (i = 0; i < g->nfuncs; i++) {
200 		if (g->funcs[i] == function)
201 			break;
202 	}
203 
204 	if (WARN_ON(i == g->nfuncs))
205 		return -EINVAL;
206 
207 	/*
208 	 * If an GPIO interrupt is setup on this pin then we need special
209 	 * handling.  Specifically interrupt detection logic will still see
210 	 * the pin twiddle even when we're muxed away.
211 	 *
212 	 * When we see a pin with an interrupt setup on it then we'll disable
213 	 * (mask) interrupts on it when we mux away until we mux back.  Note
214 	 * that disable_irq() refcounts and interrupts are disabled as long as
215 	 * at least one disable_irq() has been called.
216 	 */
217 	if (d && i != gpio_func &&
218 	    !test_and_set_bit(d->hwirq, pctrl->disabled_for_mux))
219 		disable_irq(irq);
220 
221 	raw_spin_lock_irqsave(&pctrl->lock, flags);
222 
223 	val = msm_readl_ctl(pctrl, g);
224 
225 	/*
226 	 * If this is the first time muxing to GPIO and the direction is
227 	 * output, make sure that we're not going to be glitching the pin
228 	 * by reading the current state of the pin and setting it as the
229 	 * output.
230 	 */
231 	if (i == gpio_func && (val & BIT(g->oe_bit)) &&
232 	    !test_and_set_bit(group, pctrl->ever_gpio)) {
233 		u32 io_val = msm_readl_io(pctrl, g);
234 
235 		if (io_val & BIT(g->in_bit)) {
236 			if (!(io_val & BIT(g->out_bit)))
237 				msm_writel_io(io_val | BIT(g->out_bit), pctrl, g);
238 		} else {
239 			if (io_val & BIT(g->out_bit))
240 				msm_writel_io(io_val & ~BIT(g->out_bit), pctrl, g);
241 		}
242 	}
243 
244 	if (egpio_func && i == egpio_func) {
245 		if (val & BIT(g->egpio_present))
246 			val &= ~BIT(g->egpio_enable);
247 	} else {
248 		val &= ~mask;
249 		val |= i << g->mux_bit;
250 		/* Claim ownership of pin if egpio capable */
251 		if (egpio_func && val & BIT(g->egpio_present))
252 			val |= BIT(g->egpio_enable);
253 	}
254 
255 	msm_writel_ctl(val, pctrl, g);
256 
257 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
258 
259 	if (d && i == gpio_func &&
260 	    test_and_clear_bit(d->hwirq, pctrl->disabled_for_mux)) {
261 		/*
262 		 * Clear interrupts detected while not GPIO since we only
263 		 * masked things.
264 		 */
265 		if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs))
266 			irq_chip_set_parent_state(d, IRQCHIP_STATE_PENDING, false);
267 		else
268 			msm_ack_intr_status(pctrl, g);
269 
270 		enable_irq(irq);
271 	}
272 
273 	return 0;
274 }
275 
276 static int msm_pinmux_request_gpio(struct pinctrl_dev *pctldev,
277 				   struct pinctrl_gpio_range *range,
278 				   unsigned offset)
279 {
280 	struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
281 	const struct msm_pingroup *g = &pctrl->soc->groups[offset];
282 
283 	/* No funcs? Probably ACPI so can't do anything here */
284 	if (!g->nfuncs)
285 		return 0;
286 
287 	return msm_pinmux_set_mux(pctldev, g->funcs[pctrl->soc->gpio_func], offset);
288 }
289 
290 static const struct pinmux_ops msm_pinmux_ops = {
291 	.request		= msm_pinmux_request,
292 	.get_functions_count	= msm_get_functions_count,
293 	.get_function_name	= msm_get_function_name,
294 	.get_function_groups	= msm_get_function_groups,
295 	.gpio_request_enable	= msm_pinmux_request_gpio,
296 	.set_mux		= msm_pinmux_set_mux,
297 };
298 
299 static int msm_config_reg(struct msm_pinctrl *pctrl,
300 			  const struct msm_pingroup *g,
301 			  unsigned param,
302 			  unsigned *mask,
303 			  unsigned *bit)
304 {
305 	switch (param) {
306 	case PIN_CONFIG_BIAS_DISABLE:
307 	case PIN_CONFIG_BIAS_PULL_DOWN:
308 	case PIN_CONFIG_BIAS_BUS_HOLD:
309 	case PIN_CONFIG_BIAS_PULL_UP:
310 		*bit = g->pull_bit;
311 		*mask = 3;
312 		if (g->i2c_pull_bit)
313 			*mask |= BIT(g->i2c_pull_bit) >> *bit;
314 		break;
315 	case PIN_CONFIG_DRIVE_OPEN_DRAIN:
316 		*bit = g->od_bit;
317 		*mask = 1;
318 		break;
319 	case PIN_CONFIG_DRIVE_STRENGTH:
320 		*bit = g->drv_bit;
321 		*mask = 7;
322 		break;
323 	case PIN_CONFIG_OUTPUT:
324 	case PIN_CONFIG_INPUT_ENABLE:
325 	case PIN_CONFIG_OUTPUT_ENABLE:
326 		*bit = g->oe_bit;
327 		*mask = 1;
328 		break;
329 	default:
330 		return -ENOTSUPP;
331 	}
332 
333 	return 0;
334 }
335 
336 #define MSM_NO_PULL		0
337 #define MSM_PULL_DOWN		1
338 #define MSM_KEEPER		2
339 #define MSM_PULL_UP_NO_KEEPER	2
340 #define MSM_PULL_UP		3
341 #define MSM_I2C_STRONG_PULL_UP	2200
342 
343 static unsigned msm_regval_to_drive(u32 val)
344 {
345 	return (val + 1) * 2;
346 }
347 
348 static int msm_config_group_get(struct pinctrl_dev *pctldev,
349 				unsigned int group,
350 				unsigned long *config)
351 {
352 	const struct msm_pingroup *g;
353 	struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
354 	unsigned param = pinconf_to_config_param(*config);
355 	unsigned mask;
356 	unsigned arg;
357 	unsigned bit;
358 	int ret;
359 	u32 val;
360 
361 	g = &pctrl->soc->groups[group];
362 
363 	ret = msm_config_reg(pctrl, g, param, &mask, &bit);
364 	if (ret < 0)
365 		return ret;
366 
367 	val = msm_readl_ctl(pctrl, g);
368 	arg = (val >> bit) & mask;
369 
370 	/* Convert register value to pinconf value */
371 	switch (param) {
372 	case PIN_CONFIG_BIAS_DISABLE:
373 		if (arg != MSM_NO_PULL)
374 			return -EINVAL;
375 		arg = 1;
376 		break;
377 	case PIN_CONFIG_BIAS_PULL_DOWN:
378 		if (arg != MSM_PULL_DOWN)
379 			return -EINVAL;
380 		arg = 1;
381 		break;
382 	case PIN_CONFIG_BIAS_BUS_HOLD:
383 		if (pctrl->soc->pull_no_keeper)
384 			return -ENOTSUPP;
385 
386 		if (arg != MSM_KEEPER)
387 			return -EINVAL;
388 		arg = 1;
389 		break;
390 	case PIN_CONFIG_BIAS_PULL_UP:
391 		if (pctrl->soc->pull_no_keeper)
392 			arg = arg == MSM_PULL_UP_NO_KEEPER;
393 		else if (arg & BIT(g->i2c_pull_bit))
394 			arg = MSM_I2C_STRONG_PULL_UP;
395 		else
396 			arg = arg == MSM_PULL_UP;
397 		if (!arg)
398 			return -EINVAL;
399 		break;
400 	case PIN_CONFIG_DRIVE_OPEN_DRAIN:
401 		/* Pin is not open-drain */
402 		if (!arg)
403 			return -EINVAL;
404 		arg = 1;
405 		break;
406 	case PIN_CONFIG_DRIVE_STRENGTH:
407 		arg = msm_regval_to_drive(arg);
408 		break;
409 	case PIN_CONFIG_OUTPUT:
410 		/* Pin is not output */
411 		if (!arg)
412 			return -EINVAL;
413 
414 		val = msm_readl_io(pctrl, g);
415 		arg = !!(val & BIT(g->in_bit));
416 		break;
417 	case PIN_CONFIG_OUTPUT_ENABLE:
418 		if (!arg)
419 			return -EINVAL;
420 		break;
421 	default:
422 		return -ENOTSUPP;
423 	}
424 
425 	*config = pinconf_to_config_packed(param, arg);
426 
427 	return 0;
428 }
429 
430 static int msm_config_group_set(struct pinctrl_dev *pctldev,
431 				unsigned group,
432 				unsigned long *configs,
433 				unsigned num_configs)
434 {
435 	const struct msm_pingroup *g;
436 	struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
437 	unsigned long flags;
438 	unsigned param;
439 	unsigned mask;
440 	unsigned arg;
441 	unsigned bit;
442 	int ret;
443 	u32 val;
444 	int i;
445 
446 	g = &pctrl->soc->groups[group];
447 
448 	for (i = 0; i < num_configs; i++) {
449 		param = pinconf_to_config_param(configs[i]);
450 		arg = pinconf_to_config_argument(configs[i]);
451 
452 		ret = msm_config_reg(pctrl, g, param, &mask, &bit);
453 		if (ret < 0)
454 			return ret;
455 
456 		/* Convert pinconf values to register values */
457 		switch (param) {
458 		case PIN_CONFIG_BIAS_DISABLE:
459 			arg = MSM_NO_PULL;
460 			break;
461 		case PIN_CONFIG_BIAS_PULL_DOWN:
462 			arg = MSM_PULL_DOWN;
463 			break;
464 		case PIN_CONFIG_BIAS_BUS_HOLD:
465 			if (pctrl->soc->pull_no_keeper)
466 				return -ENOTSUPP;
467 
468 			arg = MSM_KEEPER;
469 			break;
470 		case PIN_CONFIG_BIAS_PULL_UP:
471 			if (pctrl->soc->pull_no_keeper)
472 				arg = MSM_PULL_UP_NO_KEEPER;
473 			else if (g->i2c_pull_bit && arg == MSM_I2C_STRONG_PULL_UP)
474 				arg = BIT(g->i2c_pull_bit) | MSM_PULL_UP;
475 			else
476 				arg = MSM_PULL_UP;
477 			break;
478 		case PIN_CONFIG_DRIVE_OPEN_DRAIN:
479 			arg = 1;
480 			break;
481 		case PIN_CONFIG_DRIVE_STRENGTH:
482 			/* Check for invalid values */
483 			if (arg > 16 || arg < 2 || (arg % 2) != 0)
484 				arg = -1;
485 			else
486 				arg = (arg / 2) - 1;
487 			break;
488 		case PIN_CONFIG_OUTPUT:
489 			/* set output value */
490 			raw_spin_lock_irqsave(&pctrl->lock, flags);
491 			val = msm_readl_io(pctrl, g);
492 			if (arg)
493 				val |= BIT(g->out_bit);
494 			else
495 				val &= ~BIT(g->out_bit);
496 			msm_writel_io(val, pctrl, g);
497 			raw_spin_unlock_irqrestore(&pctrl->lock, flags);
498 
499 			/* enable output */
500 			arg = 1;
501 			break;
502 		case PIN_CONFIG_INPUT_ENABLE:
503 			/*
504 			 * According to pinctrl documentation this should
505 			 * actually be a no-op.
506 			 *
507 			 * The docs are explicit that "this does not affect
508 			 * the pin's ability to drive output" but what we do
509 			 * here is to modify the output enable bit. Thus, to
510 			 * follow the docs we should remove that.
511 			 *
512 			 * The docs say that we should enable any relevant
513 			 * input buffer, but TLMM there is no input buffer that
514 			 * can be enabled/disabled. It's always on.
515 			 *
516 			 * The points above, explain why this _should_ be a
517 			 * no-op. However, for historical reasons and to
518 			 * support old device trees, we'll violate the docs
519 			 * and still affect the output.
520 			 *
521 			 * It should further be noted that this old historical
522 			 * behavior actually overrides arg to 0. That means
523 			 * that "input-enable" and "input-disable" in a device
524 			 * tree would _both_ disable the output. We'll
525 			 * continue to preserve this behavior as well since
526 			 * we have no other use for this attribute.
527 			 */
528 			arg = 0;
529 			break;
530 		case PIN_CONFIG_OUTPUT_ENABLE:
531 			arg = !!arg;
532 			break;
533 		default:
534 			dev_err(pctrl->dev, "Unsupported config parameter: %x\n",
535 				param);
536 			return -EINVAL;
537 		}
538 
539 		/* Range-check user-supplied value */
540 		if (arg & ~mask) {
541 			dev_err(pctrl->dev, "config %x: %x is invalid\n", param, arg);
542 			return -EINVAL;
543 		}
544 
545 		raw_spin_lock_irqsave(&pctrl->lock, flags);
546 		val = msm_readl_ctl(pctrl, g);
547 		val &= ~(mask << bit);
548 		val |= arg << bit;
549 		msm_writel_ctl(val, pctrl, g);
550 		raw_spin_unlock_irqrestore(&pctrl->lock, flags);
551 	}
552 
553 	return 0;
554 }
555 
556 static const struct pinconf_ops msm_pinconf_ops = {
557 	.is_generic		= true,
558 	.pin_config_group_get	= msm_config_group_get,
559 	.pin_config_group_set	= msm_config_group_set,
560 };
561 
562 static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
563 {
564 	const struct msm_pingroup *g;
565 	struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
566 	unsigned long flags;
567 	u32 val;
568 
569 	g = &pctrl->soc->groups[offset];
570 
571 	raw_spin_lock_irqsave(&pctrl->lock, flags);
572 
573 	val = msm_readl_ctl(pctrl, g);
574 	val &= ~BIT(g->oe_bit);
575 	msm_writel_ctl(val, pctrl, g);
576 
577 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
578 
579 	return 0;
580 }
581 
582 static int msm_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value)
583 {
584 	const struct msm_pingroup *g;
585 	struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
586 	unsigned long flags;
587 	u32 val;
588 
589 	g = &pctrl->soc->groups[offset];
590 
591 	raw_spin_lock_irqsave(&pctrl->lock, flags);
592 
593 	val = msm_readl_io(pctrl, g);
594 	if (value)
595 		val |= BIT(g->out_bit);
596 	else
597 		val &= ~BIT(g->out_bit);
598 	msm_writel_io(val, pctrl, g);
599 
600 	val = msm_readl_ctl(pctrl, g);
601 	val |= BIT(g->oe_bit);
602 	msm_writel_ctl(val, pctrl, g);
603 
604 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
605 
606 	return 0;
607 }
608 
609 static int msm_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
610 {
611 	struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
612 	const struct msm_pingroup *g;
613 	u32 val;
614 
615 	g = &pctrl->soc->groups[offset];
616 
617 	val = msm_readl_ctl(pctrl, g);
618 
619 	return val & BIT(g->oe_bit) ? GPIO_LINE_DIRECTION_OUT :
620 				      GPIO_LINE_DIRECTION_IN;
621 }
622 
623 static int msm_gpio_get(struct gpio_chip *chip, unsigned offset)
624 {
625 	const struct msm_pingroup *g;
626 	struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
627 	u32 val;
628 
629 	g = &pctrl->soc->groups[offset];
630 
631 	val = msm_readl_io(pctrl, g);
632 	return !!(val & BIT(g->in_bit));
633 }
634 
635 static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
636 {
637 	const struct msm_pingroup *g;
638 	struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
639 	unsigned long flags;
640 	u32 val;
641 
642 	g = &pctrl->soc->groups[offset];
643 
644 	raw_spin_lock_irqsave(&pctrl->lock, flags);
645 
646 	val = msm_readl_io(pctrl, g);
647 	if (value)
648 		val |= BIT(g->out_bit);
649 	else
650 		val &= ~BIT(g->out_bit);
651 	msm_writel_io(val, pctrl, g);
652 
653 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
654 }
655 
656 #ifdef CONFIG_DEBUG_FS
657 
658 static void msm_gpio_dbg_show_one(struct seq_file *s,
659 				  struct pinctrl_dev *pctldev,
660 				  struct gpio_chip *chip,
661 				  unsigned offset,
662 				  unsigned gpio)
663 {
664 	const struct msm_pingroup *g;
665 	struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
666 	unsigned func;
667 	int is_out;
668 	int drive;
669 	int pull;
670 	int val;
671 	int egpio_enable;
672 	u32 ctl_reg, io_reg;
673 
674 	static const char * const pulls_keeper[] = {
675 		"no pull",
676 		"pull down",
677 		"keeper",
678 		"pull up"
679 	};
680 
681 	static const char * const pulls_no_keeper[] = {
682 		"no pull",
683 		"pull down",
684 		"pull up",
685 	};
686 
687 	if (!gpiochip_line_is_valid(chip, offset))
688 		return;
689 
690 	g = &pctrl->soc->groups[offset];
691 	ctl_reg = msm_readl_ctl(pctrl, g);
692 	io_reg = msm_readl_io(pctrl, g);
693 
694 	is_out = !!(ctl_reg & BIT(g->oe_bit));
695 	func = (ctl_reg >> g->mux_bit) & 7;
696 	drive = (ctl_reg >> g->drv_bit) & 7;
697 	pull = (ctl_reg >> g->pull_bit) & 3;
698 	egpio_enable = 0;
699 	if (pctrl->soc->egpio_func && ctl_reg & BIT(g->egpio_present))
700 		egpio_enable = !(ctl_reg & BIT(g->egpio_enable));
701 
702 	if (is_out)
703 		val = !!(io_reg & BIT(g->out_bit));
704 	else
705 		val = !!(io_reg & BIT(g->in_bit));
706 
707 	if (egpio_enable) {
708 		seq_printf(s, " %-8s: egpio\n", g->grp.name);
709 		return;
710 	}
711 
712 	seq_printf(s, " %-8s: %-3s", g->grp.name, is_out ? "out" : "in");
713 	seq_printf(s, " %-4s func%d", val ? "high" : "low", func);
714 	seq_printf(s, " %dmA", msm_regval_to_drive(drive));
715 	if (pctrl->soc->pull_no_keeper)
716 		seq_printf(s, " %s", pulls_no_keeper[pull]);
717 	else
718 		seq_printf(s, " %s", pulls_keeper[pull]);
719 	seq_puts(s, "\n");
720 }
721 
722 static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
723 {
724 	unsigned gpio = chip->base;
725 	unsigned i;
726 
727 	for (i = 0; i < chip->ngpio; i++, gpio++)
728 		msm_gpio_dbg_show_one(s, NULL, chip, i, gpio);
729 }
730 
731 #else
732 #define msm_gpio_dbg_show NULL
733 #endif
734 
735 static int msm_gpio_init_valid_mask(struct gpio_chip *gc,
736 				    unsigned long *valid_mask,
737 				    unsigned int ngpios)
738 {
739 	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
740 	int ret;
741 	unsigned int len, i;
742 	const int *reserved = pctrl->soc->reserved_gpios;
743 	u16 *tmp;
744 
745 	/* Remove driver-provided reserved GPIOs from valid_mask */
746 	if (reserved) {
747 		for (i = 0; reserved[i] >= 0; i++) {
748 			if (i >= ngpios || reserved[i] >= ngpios) {
749 				dev_err(pctrl->dev, "invalid list of reserved GPIOs\n");
750 				return -EINVAL;
751 			}
752 			clear_bit(reserved[i], valid_mask);
753 		}
754 
755 		return 0;
756 	}
757 
758 	/* The number of GPIOs in the ACPI tables */
759 	len = ret = device_property_count_u16(pctrl->dev, "gpios");
760 	if (ret < 0)
761 		return 0;
762 
763 	if (ret > ngpios)
764 		return -EINVAL;
765 
766 	tmp = kmalloc_array(len, sizeof(*tmp), GFP_KERNEL);
767 	if (!tmp)
768 		return -ENOMEM;
769 
770 	ret = device_property_read_u16_array(pctrl->dev, "gpios", tmp, len);
771 	if (ret < 0) {
772 		dev_err(pctrl->dev, "could not read list of GPIOs\n");
773 		goto out;
774 	}
775 
776 	bitmap_zero(valid_mask, ngpios);
777 	for (i = 0; i < len; i++)
778 		set_bit(tmp[i], valid_mask);
779 
780 out:
781 	kfree(tmp);
782 	return ret;
783 }
784 
785 static const struct gpio_chip msm_gpio_template = {
786 	.direction_input  = msm_gpio_direction_input,
787 	.direction_output = msm_gpio_direction_output,
788 	.get_direction    = msm_gpio_get_direction,
789 	.get              = msm_gpio_get,
790 	.set              = msm_gpio_set,
791 	.request          = gpiochip_generic_request,
792 	.free             = gpiochip_generic_free,
793 	.dbg_show         = msm_gpio_dbg_show,
794 };
795 
796 /* For dual-edge interrupts in software, since some hardware has no
797  * such support:
798  *
799  * At appropriate moments, this function may be called to flip the polarity
800  * settings of both-edge irq lines to try and catch the next edge.
801  *
802  * The attempt is considered successful if:
803  * - the status bit goes high, indicating that an edge was caught, or
804  * - the input value of the gpio doesn't change during the attempt.
805  * If the value changes twice during the process, that would cause the first
806  * test to fail but would force the second, as two opposite
807  * transitions would cause a detection no matter the polarity setting.
808  *
809  * The do-loop tries to sledge-hammer closed the timing hole between
810  * the initial value-read and the polarity-write - if the line value changes
811  * during that window, an interrupt is lost, the new polarity setting is
812  * incorrect, and the first success test will fail, causing a retry.
813  *
814  * Algorithm comes from Google's msmgpio driver.
815  */
816 static void msm_gpio_update_dual_edge_pos(struct msm_pinctrl *pctrl,
817 					  const struct msm_pingroup *g,
818 					  struct irq_data *d)
819 {
820 	int loop_limit = 100;
821 	unsigned val, val2, intstat;
822 	unsigned pol;
823 
824 	do {
825 		val = msm_readl_io(pctrl, g) & BIT(g->in_bit);
826 
827 		pol = msm_readl_intr_cfg(pctrl, g);
828 		pol ^= BIT(g->intr_polarity_bit);
829 		msm_writel_intr_cfg(pol, pctrl, g);
830 
831 		val2 = msm_readl_io(pctrl, g) & BIT(g->in_bit);
832 		intstat = msm_readl_intr_status(pctrl, g);
833 		if (intstat || (val == val2))
834 			return;
835 	} while (loop_limit-- > 0);
836 	dev_err(pctrl->dev, "dual-edge irq failed to stabilize, %#08x != %#08x\n",
837 		val, val2);
838 }
839 
840 static void msm_gpio_irq_mask(struct irq_data *d)
841 {
842 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
843 	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
844 	const struct msm_pingroup *g;
845 	unsigned long flags;
846 	u32 val;
847 
848 	if (d->parent_data)
849 		irq_chip_mask_parent(d);
850 
851 	if (test_bit(d->hwirq, pctrl->skip_wake_irqs))
852 		return;
853 
854 	g = &pctrl->soc->groups[d->hwirq];
855 
856 	raw_spin_lock_irqsave(&pctrl->lock, flags);
857 
858 	val = msm_readl_intr_cfg(pctrl, g);
859 	/*
860 	 * There are two bits that control interrupt forwarding to the CPU. The
861 	 * RAW_STATUS_EN bit causes the level or edge sensed on the line to be
862 	 * latched into the interrupt status register when the hardware detects
863 	 * an irq that it's configured for (either edge for edge type or level
864 	 * for level type irq). The 'non-raw' status enable bit causes the
865 	 * hardware to assert the summary interrupt to the CPU if the latched
866 	 * status bit is set. There's a bug though, the edge detection logic
867 	 * seems to have a problem where toggling the RAW_STATUS_EN bit may
868 	 * cause the status bit to latch spuriously when there isn't any edge
869 	 * so we can't touch that bit for edge type irqs and we have to keep
870 	 * the bit set anyway so that edges are latched while the line is masked.
871 	 *
872 	 * To make matters more complicated, leaving the RAW_STATUS_EN bit
873 	 * enabled all the time causes level interrupts to re-latch into the
874 	 * status register because the level is still present on the line after
875 	 * we ack it. We clear the raw status enable bit during mask here and
876 	 * set the bit on unmask so the interrupt can't latch into the hardware
877 	 * while it's masked.
878 	 */
879 	if (irqd_get_trigger_type(d) & IRQ_TYPE_LEVEL_MASK)
880 		val &= ~BIT(g->intr_raw_status_bit);
881 
882 	val &= ~BIT(g->intr_enable_bit);
883 	msm_writel_intr_cfg(val, pctrl, g);
884 
885 	clear_bit(d->hwirq, pctrl->enabled_irqs);
886 
887 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
888 }
889 
890 static void msm_gpio_irq_unmask(struct irq_data *d)
891 {
892 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
893 	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
894 	const struct msm_pingroup *g;
895 	unsigned long flags;
896 	u32 val;
897 
898 	if (d->parent_data)
899 		irq_chip_unmask_parent(d);
900 
901 	if (test_bit(d->hwirq, pctrl->skip_wake_irqs))
902 		return;
903 
904 	g = &pctrl->soc->groups[d->hwirq];
905 
906 	raw_spin_lock_irqsave(&pctrl->lock, flags);
907 
908 	val = msm_readl_intr_cfg(pctrl, g);
909 	val |= BIT(g->intr_raw_status_bit);
910 	val |= BIT(g->intr_enable_bit);
911 	msm_writel_intr_cfg(val, pctrl, g);
912 
913 	set_bit(d->hwirq, pctrl->enabled_irqs);
914 
915 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
916 }
917 
918 static void msm_gpio_irq_enable(struct irq_data *d)
919 {
920 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
921 	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
922 
923 	gpiochip_enable_irq(gc, d->hwirq);
924 
925 	if (d->parent_data)
926 		irq_chip_enable_parent(d);
927 
928 	if (!test_bit(d->hwirq, pctrl->skip_wake_irqs))
929 		msm_gpio_irq_unmask(d);
930 }
931 
932 static void msm_gpio_irq_disable(struct irq_data *d)
933 {
934 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
935 	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
936 
937 	if (d->parent_data)
938 		irq_chip_disable_parent(d);
939 
940 	if (!test_bit(d->hwirq, pctrl->skip_wake_irqs))
941 		msm_gpio_irq_mask(d);
942 
943 	gpiochip_disable_irq(gc, d->hwirq);
944 }
945 
946 /**
947  * msm_gpio_update_dual_edge_parent() - Prime next edge for IRQs handled by parent.
948  * @d: The irq dta.
949  *
950  * This is much like msm_gpio_update_dual_edge_pos() but for IRQs that are
951  * normally handled by the parent irqchip.  The logic here is slightly
952  * different due to what's easy to do with our parent, but in principle it's
953  * the same.
954  */
955 static void msm_gpio_update_dual_edge_parent(struct irq_data *d)
956 {
957 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
958 	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
959 	const struct msm_pingroup *g = &pctrl->soc->groups[d->hwirq];
960 	int loop_limit = 100;
961 	unsigned int val;
962 	unsigned int type;
963 
964 	/* Read the value and make a guess about what edge we need to catch */
965 	val = msm_readl_io(pctrl, g) & BIT(g->in_bit);
966 	type = val ? IRQ_TYPE_EDGE_FALLING : IRQ_TYPE_EDGE_RISING;
967 
968 	do {
969 		/* Set the parent to catch the next edge */
970 		irq_chip_set_type_parent(d, type);
971 
972 		/*
973 		 * Possibly the line changed between when we last read "val"
974 		 * (and decided what edge we needed) and when set the edge.
975 		 * If the value didn't change (or changed and then changed
976 		 * back) then we're done.
977 		 */
978 		val = msm_readl_io(pctrl, g) & BIT(g->in_bit);
979 		if (type == IRQ_TYPE_EDGE_RISING) {
980 			if (!val)
981 				return;
982 			type = IRQ_TYPE_EDGE_FALLING;
983 		} else if (type == IRQ_TYPE_EDGE_FALLING) {
984 			if (val)
985 				return;
986 			type = IRQ_TYPE_EDGE_RISING;
987 		}
988 	} while (loop_limit-- > 0);
989 	dev_warn_once(pctrl->dev, "dual-edge irq failed to stabilize\n");
990 }
991 
992 static void msm_gpio_irq_ack(struct irq_data *d)
993 {
994 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
995 	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
996 	const struct msm_pingroup *g;
997 	unsigned long flags;
998 
999 	if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) {
1000 		if (test_bit(d->hwirq, pctrl->dual_edge_irqs))
1001 			msm_gpio_update_dual_edge_parent(d);
1002 		return;
1003 	}
1004 
1005 	g = &pctrl->soc->groups[d->hwirq];
1006 
1007 	raw_spin_lock_irqsave(&pctrl->lock, flags);
1008 
1009 	msm_ack_intr_status(pctrl, g);
1010 
1011 	if (test_bit(d->hwirq, pctrl->dual_edge_irqs))
1012 		msm_gpio_update_dual_edge_pos(pctrl, g, d);
1013 
1014 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
1015 }
1016 
1017 static void msm_gpio_irq_eoi(struct irq_data *d)
1018 {
1019 	d = d->parent_data;
1020 
1021 	if (d)
1022 		d->chip->irq_eoi(d);
1023 }
1024 
1025 static bool msm_gpio_needs_dual_edge_parent_workaround(struct irq_data *d,
1026 						       unsigned int type)
1027 {
1028 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1029 	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
1030 
1031 	return type == IRQ_TYPE_EDGE_BOTH &&
1032 	       pctrl->soc->wakeirq_dual_edge_errata && d->parent_data &&
1033 	       test_bit(d->hwirq, pctrl->skip_wake_irqs);
1034 }
1035 
1036 static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type)
1037 {
1038 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1039 	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
1040 	const struct msm_pingroup *g;
1041 	unsigned long flags;
1042 	bool was_enabled;
1043 	u32 val;
1044 
1045 	if (msm_gpio_needs_dual_edge_parent_workaround(d, type)) {
1046 		set_bit(d->hwirq, pctrl->dual_edge_irqs);
1047 		irq_set_handler_locked(d, handle_fasteoi_ack_irq);
1048 		msm_gpio_update_dual_edge_parent(d);
1049 		return 0;
1050 	}
1051 
1052 	if (d->parent_data)
1053 		irq_chip_set_type_parent(d, type);
1054 
1055 	if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) {
1056 		clear_bit(d->hwirq, pctrl->dual_edge_irqs);
1057 		irq_set_handler_locked(d, handle_fasteoi_irq);
1058 		return 0;
1059 	}
1060 
1061 	g = &pctrl->soc->groups[d->hwirq];
1062 
1063 	raw_spin_lock_irqsave(&pctrl->lock, flags);
1064 
1065 	/*
1066 	 * For hw without possibility of detecting both edges
1067 	 */
1068 	if (g->intr_detection_width == 1 && type == IRQ_TYPE_EDGE_BOTH)
1069 		set_bit(d->hwirq, pctrl->dual_edge_irqs);
1070 	else
1071 		clear_bit(d->hwirq, pctrl->dual_edge_irqs);
1072 
1073 	/* Route interrupts to application cpu.
1074 	 * With intr_target_use_scm interrupts are routed to
1075 	 * application cpu using scm calls.
1076 	 */
1077 	if (pctrl->intr_target_use_scm) {
1078 		u32 addr = pctrl->phys_base[0] + g->intr_target_reg;
1079 		int ret;
1080 
1081 		qcom_scm_io_readl(addr, &val);
1082 
1083 		val &= ~(7 << g->intr_target_bit);
1084 		val |= g->intr_target_kpss_val << g->intr_target_bit;
1085 
1086 		ret = qcom_scm_io_writel(addr, val);
1087 		if (ret)
1088 			dev_err(pctrl->dev,
1089 				"Failed routing %lu interrupt to Apps proc",
1090 				d->hwirq);
1091 	} else {
1092 		val = msm_readl_intr_target(pctrl, g);
1093 		val &= ~(7 << g->intr_target_bit);
1094 		val |= g->intr_target_kpss_val << g->intr_target_bit;
1095 		msm_writel_intr_target(val, pctrl, g);
1096 	}
1097 
1098 	/* Update configuration for gpio.
1099 	 * RAW_STATUS_EN is left on for all gpio irqs. Due to the
1100 	 * internal circuitry of TLMM, toggling the RAW_STATUS
1101 	 * could cause the INTR_STATUS to be set for EDGE interrupts.
1102 	 */
1103 	val = msm_readl_intr_cfg(pctrl, g);
1104 	was_enabled = val & BIT(g->intr_raw_status_bit);
1105 	val |= BIT(g->intr_raw_status_bit);
1106 	if (g->intr_detection_width == 2) {
1107 		val &= ~(3 << g->intr_detection_bit);
1108 		val &= ~(1 << g->intr_polarity_bit);
1109 		switch (type) {
1110 		case IRQ_TYPE_EDGE_RISING:
1111 			val |= 1 << g->intr_detection_bit;
1112 			val |= BIT(g->intr_polarity_bit);
1113 			break;
1114 		case IRQ_TYPE_EDGE_FALLING:
1115 			val |= 2 << g->intr_detection_bit;
1116 			val |= BIT(g->intr_polarity_bit);
1117 			break;
1118 		case IRQ_TYPE_EDGE_BOTH:
1119 			val |= 3 << g->intr_detection_bit;
1120 			val |= BIT(g->intr_polarity_bit);
1121 			break;
1122 		case IRQ_TYPE_LEVEL_LOW:
1123 			break;
1124 		case IRQ_TYPE_LEVEL_HIGH:
1125 			val |= BIT(g->intr_polarity_bit);
1126 			break;
1127 		}
1128 	} else if (g->intr_detection_width == 1) {
1129 		val &= ~(1 << g->intr_detection_bit);
1130 		val &= ~(1 << g->intr_polarity_bit);
1131 		switch (type) {
1132 		case IRQ_TYPE_EDGE_RISING:
1133 			val |= BIT(g->intr_detection_bit);
1134 			val |= BIT(g->intr_polarity_bit);
1135 			break;
1136 		case IRQ_TYPE_EDGE_FALLING:
1137 			val |= BIT(g->intr_detection_bit);
1138 			break;
1139 		case IRQ_TYPE_EDGE_BOTH:
1140 			val |= BIT(g->intr_detection_bit);
1141 			val |= BIT(g->intr_polarity_bit);
1142 			break;
1143 		case IRQ_TYPE_LEVEL_LOW:
1144 			break;
1145 		case IRQ_TYPE_LEVEL_HIGH:
1146 			val |= BIT(g->intr_polarity_bit);
1147 			break;
1148 		}
1149 	} else {
1150 		BUG();
1151 	}
1152 	msm_writel_intr_cfg(val, pctrl, g);
1153 
1154 	/*
1155 	 * The first time we set RAW_STATUS_EN it could trigger an interrupt.
1156 	 * Clear the interrupt.  This is safe because we have
1157 	 * IRQCHIP_SET_TYPE_MASKED.
1158 	 */
1159 	if (!was_enabled)
1160 		msm_ack_intr_status(pctrl, g);
1161 
1162 	if (test_bit(d->hwirq, pctrl->dual_edge_irqs))
1163 		msm_gpio_update_dual_edge_pos(pctrl, g, d);
1164 
1165 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
1166 
1167 	if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
1168 		irq_set_handler_locked(d, handle_level_irq);
1169 	else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
1170 		irq_set_handler_locked(d, handle_edge_irq);
1171 
1172 	return 0;
1173 }
1174 
1175 static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
1176 {
1177 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1178 	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
1179 
1180 	/*
1181 	 * While they may not wake up when the TLMM is powered off,
1182 	 * some GPIOs would like to wakeup the system from suspend
1183 	 * when TLMM is powered on. To allow that, enable the GPIO
1184 	 * summary line to be wakeup capable at GIC.
1185 	 */
1186 	if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs))
1187 		return irq_chip_set_wake_parent(d, on);
1188 
1189 	return irq_set_irq_wake(pctrl->irq, on);
1190 }
1191 
1192 static int msm_gpio_irq_reqres(struct irq_data *d)
1193 {
1194 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1195 	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
1196 	int ret;
1197 
1198 	if (!try_module_get(gc->owner))
1199 		return -ENODEV;
1200 
1201 	ret = msm_pinmux_request_gpio(pctrl->pctrl, NULL, d->hwirq);
1202 	if (ret)
1203 		goto out;
1204 	msm_gpio_direction_input(gc, d->hwirq);
1205 
1206 	if (gpiochip_lock_as_irq(gc, d->hwirq)) {
1207 		dev_err(gc->parent,
1208 			"unable to lock HW IRQ %lu for IRQ\n",
1209 			d->hwirq);
1210 		ret = -EINVAL;
1211 		goto out;
1212 	}
1213 
1214 	/*
1215 	 * The disable / clear-enable workaround we do in msm_pinmux_set_mux()
1216 	 * only works if disable is not lazy since we only clear any bogus
1217 	 * interrupt in hardware. Explicitly mark the interrupt as UNLAZY.
1218 	 */
1219 	irq_set_status_flags(d->irq, IRQ_DISABLE_UNLAZY);
1220 
1221 	return 0;
1222 out:
1223 	module_put(gc->owner);
1224 	return ret;
1225 }
1226 
1227 static void msm_gpio_irq_relres(struct irq_data *d)
1228 {
1229 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1230 
1231 	gpiochip_unlock_as_irq(gc, d->hwirq);
1232 	module_put(gc->owner);
1233 }
1234 
1235 static int msm_gpio_irq_set_affinity(struct irq_data *d,
1236 				const struct cpumask *dest, bool force)
1237 {
1238 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1239 	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
1240 
1241 	if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs))
1242 		return irq_chip_set_affinity_parent(d, dest, force);
1243 
1244 	return -EINVAL;
1245 }
1246 
1247 static int msm_gpio_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)
1248 {
1249 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1250 	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
1251 
1252 	if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs))
1253 		return irq_chip_set_vcpu_affinity_parent(d, vcpu_info);
1254 
1255 	return -EINVAL;
1256 }
1257 
1258 static void msm_gpio_irq_handler(struct irq_desc *desc)
1259 {
1260 	struct gpio_chip *gc = irq_desc_get_handler_data(desc);
1261 	const struct msm_pingroup *g;
1262 	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
1263 	struct irq_chip *chip = irq_desc_get_chip(desc);
1264 	int handled = 0;
1265 	u32 val;
1266 	int i;
1267 
1268 	chained_irq_enter(chip, desc);
1269 
1270 	/*
1271 	 * Each pin has it's own IRQ status register, so use
1272 	 * enabled_irq bitmap to limit the number of reads.
1273 	 */
1274 	for_each_set_bit(i, pctrl->enabled_irqs, pctrl->chip.ngpio) {
1275 		g = &pctrl->soc->groups[i];
1276 		val = msm_readl_intr_status(pctrl, g);
1277 		if (val & BIT(g->intr_status_bit)) {
1278 			generic_handle_domain_irq(gc->irq.domain, i);
1279 			handled++;
1280 		}
1281 	}
1282 
1283 	/* No interrupts were flagged */
1284 	if (handled == 0)
1285 		handle_bad_irq(desc);
1286 
1287 	chained_irq_exit(chip, desc);
1288 }
1289 
1290 static int msm_gpio_wakeirq(struct gpio_chip *gc,
1291 			    unsigned int child,
1292 			    unsigned int child_type,
1293 			    unsigned int *parent,
1294 			    unsigned int *parent_type)
1295 {
1296 	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
1297 	const struct msm_gpio_wakeirq_map *map;
1298 	int i;
1299 
1300 	*parent = GPIO_NO_WAKE_IRQ;
1301 	*parent_type = IRQ_TYPE_EDGE_RISING;
1302 
1303 	for (i = 0; i < pctrl->soc->nwakeirq_map; i++) {
1304 		map = &pctrl->soc->wakeirq_map[i];
1305 		if (map->gpio == child) {
1306 			*parent = map->wakeirq;
1307 			break;
1308 		}
1309 	}
1310 
1311 	return 0;
1312 }
1313 
1314 static bool msm_gpio_needs_valid_mask(struct msm_pinctrl *pctrl)
1315 {
1316 	if (pctrl->soc->reserved_gpios)
1317 		return true;
1318 
1319 	return device_property_count_u16(pctrl->dev, "gpios") > 0;
1320 }
1321 
1322 static const struct irq_chip msm_gpio_irq_chip = {
1323 	.name			= "msmgpio",
1324 	.irq_enable		= msm_gpio_irq_enable,
1325 	.irq_disable		= msm_gpio_irq_disable,
1326 	.irq_mask		= msm_gpio_irq_mask,
1327 	.irq_unmask		= msm_gpio_irq_unmask,
1328 	.irq_ack		= msm_gpio_irq_ack,
1329 	.irq_eoi		= msm_gpio_irq_eoi,
1330 	.irq_set_type		= msm_gpio_irq_set_type,
1331 	.irq_set_wake		= msm_gpio_irq_set_wake,
1332 	.irq_request_resources	= msm_gpio_irq_reqres,
1333 	.irq_release_resources	= msm_gpio_irq_relres,
1334 	.irq_set_affinity	= msm_gpio_irq_set_affinity,
1335 	.irq_set_vcpu_affinity	= msm_gpio_irq_set_vcpu_affinity,
1336 	.flags			= (IRQCHIP_MASK_ON_SUSPEND |
1337 				   IRQCHIP_SET_TYPE_MASKED |
1338 				   IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND |
1339 				   IRQCHIP_IMMUTABLE),
1340 };
1341 
1342 static int msm_gpio_init(struct msm_pinctrl *pctrl)
1343 {
1344 	struct gpio_chip *chip;
1345 	struct gpio_irq_chip *girq;
1346 	int i, ret;
1347 	unsigned gpio, ngpio = pctrl->soc->ngpios;
1348 	struct device_node *np;
1349 	bool skip;
1350 
1351 	if (WARN_ON(ngpio > MAX_NR_GPIO))
1352 		return -EINVAL;
1353 
1354 	chip = &pctrl->chip;
1355 	chip->base = -1;
1356 	chip->ngpio = ngpio;
1357 	chip->label = dev_name(pctrl->dev);
1358 	chip->parent = pctrl->dev;
1359 	chip->owner = THIS_MODULE;
1360 	if (msm_gpio_needs_valid_mask(pctrl))
1361 		chip->init_valid_mask = msm_gpio_init_valid_mask;
1362 
1363 	np = of_parse_phandle(pctrl->dev->of_node, "wakeup-parent", 0);
1364 	if (np) {
1365 		chip->irq.parent_domain = irq_find_matching_host(np,
1366 						 DOMAIN_BUS_WAKEUP);
1367 		of_node_put(np);
1368 		if (!chip->irq.parent_domain)
1369 			return -EPROBE_DEFER;
1370 		chip->irq.child_to_parent_hwirq = msm_gpio_wakeirq;
1371 		/*
1372 		 * Let's skip handling the GPIOs, if the parent irqchip
1373 		 * is handling the direct connect IRQ of the GPIO.
1374 		 */
1375 		skip = irq_domain_qcom_handle_wakeup(chip->irq.parent_domain);
1376 		for (i = 0; skip && i < pctrl->soc->nwakeirq_map; i++) {
1377 			gpio = pctrl->soc->wakeirq_map[i].gpio;
1378 			set_bit(gpio, pctrl->skip_wake_irqs);
1379 		}
1380 	}
1381 
1382 	girq = &chip->irq;
1383 	gpio_irq_chip_set_chip(girq, &msm_gpio_irq_chip);
1384 	girq->parent_handler = msm_gpio_irq_handler;
1385 	girq->fwnode = dev_fwnode(pctrl->dev);
1386 	girq->num_parents = 1;
1387 	girq->parents = devm_kcalloc(pctrl->dev, 1, sizeof(*girq->parents),
1388 				     GFP_KERNEL);
1389 	if (!girq->parents)
1390 		return -ENOMEM;
1391 	girq->default_type = IRQ_TYPE_NONE;
1392 	girq->handler = handle_bad_irq;
1393 	girq->parents[0] = pctrl->irq;
1394 
1395 	ret = gpiochip_add_data(&pctrl->chip, pctrl);
1396 	if (ret) {
1397 		dev_err(pctrl->dev, "Failed register gpiochip\n");
1398 		return ret;
1399 	}
1400 
1401 	/*
1402 	 * For DeviceTree-supported systems, the gpio core checks the
1403 	 * pinctrl's device node for the "gpio-ranges" property.
1404 	 * If it is present, it takes care of adding the pin ranges
1405 	 * for the driver. In this case the driver can skip ahead.
1406 	 *
1407 	 * In order to remain compatible with older, existing DeviceTree
1408 	 * files which don't set the "gpio-ranges" property or systems that
1409 	 * utilize ACPI the driver has to call gpiochip_add_pin_range().
1410 	 */
1411 	if (!of_property_read_bool(pctrl->dev->of_node, "gpio-ranges")) {
1412 		ret = gpiochip_add_pin_range(&pctrl->chip,
1413 			dev_name(pctrl->dev), 0, 0, chip->ngpio);
1414 		if (ret) {
1415 			dev_err(pctrl->dev, "Failed to add pin range\n");
1416 			gpiochip_remove(&pctrl->chip);
1417 			return ret;
1418 		}
1419 	}
1420 
1421 	return 0;
1422 }
1423 
1424 static int msm_ps_hold_restart(struct notifier_block *nb, unsigned long action,
1425 			       void *data)
1426 {
1427 	struct msm_pinctrl *pctrl = container_of(nb, struct msm_pinctrl, restart_nb);
1428 
1429 	writel(0, pctrl->regs[0] + PS_HOLD_OFFSET);
1430 	mdelay(1000);
1431 	return NOTIFY_DONE;
1432 }
1433 
1434 static struct msm_pinctrl *poweroff_pctrl;
1435 
1436 static void msm_ps_hold_poweroff(void)
1437 {
1438 	msm_ps_hold_restart(&poweroff_pctrl->restart_nb, 0, NULL);
1439 }
1440 
1441 static void msm_pinctrl_setup_pm_reset(struct msm_pinctrl *pctrl)
1442 {
1443 	int i;
1444 	const struct pinfunction *func = pctrl->soc->functions;
1445 
1446 	for (i = 0; i < pctrl->soc->nfunctions; i++)
1447 		if (!strcmp(func[i].name, "ps_hold")) {
1448 			pctrl->restart_nb.notifier_call = msm_ps_hold_restart;
1449 			pctrl->restart_nb.priority = 128;
1450 			if (register_restart_handler(&pctrl->restart_nb))
1451 				dev_err(pctrl->dev,
1452 					"failed to setup restart handler.\n");
1453 			poweroff_pctrl = pctrl;
1454 			pm_power_off = msm_ps_hold_poweroff;
1455 			break;
1456 		}
1457 }
1458 
1459 static __maybe_unused int msm_pinctrl_suspend(struct device *dev)
1460 {
1461 	struct msm_pinctrl *pctrl = dev_get_drvdata(dev);
1462 
1463 	return pinctrl_force_sleep(pctrl->pctrl);
1464 }
1465 
1466 static __maybe_unused int msm_pinctrl_resume(struct device *dev)
1467 {
1468 	struct msm_pinctrl *pctrl = dev_get_drvdata(dev);
1469 
1470 	return pinctrl_force_default(pctrl->pctrl);
1471 }
1472 
1473 SIMPLE_DEV_PM_OPS(msm_pinctrl_dev_pm_ops, msm_pinctrl_suspend,
1474 		  msm_pinctrl_resume);
1475 
1476 EXPORT_SYMBOL(msm_pinctrl_dev_pm_ops);
1477 
1478 int msm_pinctrl_probe(struct platform_device *pdev,
1479 		      const struct msm_pinctrl_soc_data *soc_data)
1480 {
1481 	struct msm_pinctrl *pctrl;
1482 	struct resource *res;
1483 	int ret;
1484 	int i;
1485 
1486 	pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
1487 	if (!pctrl)
1488 		return -ENOMEM;
1489 
1490 	pctrl->dev = &pdev->dev;
1491 	pctrl->soc = soc_data;
1492 	pctrl->chip = msm_gpio_template;
1493 	pctrl->intr_target_use_scm = of_device_is_compatible(
1494 					pctrl->dev->of_node,
1495 					"qcom,ipq8064-pinctrl");
1496 
1497 	raw_spin_lock_init(&pctrl->lock);
1498 
1499 	if (soc_data->tiles) {
1500 		for (i = 0; i < soc_data->ntiles; i++) {
1501 			res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1502 							   soc_data->tiles[i]);
1503 			pctrl->regs[i] = devm_ioremap_resource(&pdev->dev, res);
1504 			if (IS_ERR(pctrl->regs[i]))
1505 				return PTR_ERR(pctrl->regs[i]);
1506 		}
1507 	} else {
1508 		pctrl->regs[0] = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1509 		if (IS_ERR(pctrl->regs[0]))
1510 			return PTR_ERR(pctrl->regs[0]);
1511 
1512 		pctrl->phys_base[0] = res->start;
1513 	}
1514 
1515 	msm_pinctrl_setup_pm_reset(pctrl);
1516 
1517 	pctrl->irq = platform_get_irq(pdev, 0);
1518 	if (pctrl->irq < 0)
1519 		return pctrl->irq;
1520 
1521 	pctrl->desc.owner = THIS_MODULE;
1522 	pctrl->desc.pctlops = &msm_pinctrl_ops;
1523 	pctrl->desc.pmxops = &msm_pinmux_ops;
1524 	pctrl->desc.confops = &msm_pinconf_ops;
1525 	pctrl->desc.name = dev_name(&pdev->dev);
1526 	pctrl->desc.pins = pctrl->soc->pins;
1527 	pctrl->desc.npins = pctrl->soc->npins;
1528 
1529 	pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &pctrl->desc, pctrl);
1530 	if (IS_ERR(pctrl->pctrl)) {
1531 		dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
1532 		return PTR_ERR(pctrl->pctrl);
1533 	}
1534 
1535 	ret = msm_gpio_init(pctrl);
1536 	if (ret)
1537 		return ret;
1538 
1539 	platform_set_drvdata(pdev, pctrl);
1540 
1541 	dev_dbg(&pdev->dev, "Probed Qualcomm pinctrl driver\n");
1542 
1543 	return 0;
1544 }
1545 EXPORT_SYMBOL(msm_pinctrl_probe);
1546 
1547 int msm_pinctrl_remove(struct platform_device *pdev)
1548 {
1549 	struct msm_pinctrl *pctrl = platform_get_drvdata(pdev);
1550 
1551 	gpiochip_remove(&pctrl->chip);
1552 
1553 	unregister_restart_handler(&pctrl->restart_nb);
1554 
1555 	return 0;
1556 }
1557 EXPORT_SYMBOL(msm_pinctrl_remove);
1558 
1559 MODULE_DESCRIPTION("Qualcomm Technologies, Inc. TLMM driver");
1560 MODULE_LICENSE("GPL v2");
1561