1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2013, Sony Mobile Communications AB. 4 * Copyright (c) 2013, The Linux Foundation. All rights reserved. 5 */ 6 7 #include <linux/delay.h> 8 #include <linux/err.h> 9 #include <linux/io.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/platform_device.h> 13 #include <linux/pinctrl/machine.h> 14 #include <linux/pinctrl/pinctrl.h> 15 #include <linux/pinctrl/pinmux.h> 16 #include <linux/pinctrl/pinconf.h> 17 #include <linux/pinctrl/pinconf-generic.h> 18 #include <linux/slab.h> 19 #include <linux/gpio/driver.h> 20 #include <linux/interrupt.h> 21 #include <linux/spinlock.h> 22 #include <linux/reboot.h> 23 #include <linux/pm.h> 24 #include <linux/log2.h> 25 26 #include "../core.h" 27 #include "../pinconf.h" 28 #include "pinctrl-msm.h" 29 #include "../pinctrl-utils.h" 30 31 #define MAX_NR_GPIO 300 32 #define MAX_NR_TILES 4 33 #define PS_HOLD_OFFSET 0x820 34 35 /** 36 * struct msm_pinctrl - state for a pinctrl-msm device 37 * @dev: device handle. 38 * @pctrl: pinctrl handle. 39 * @chip: gpiochip handle. 40 * @restart_nb: restart notifier block. 41 * @irq: parent irq for the TLMM irq_chip. 42 * @lock: Spinlock to protect register resources as well 43 * as msm_pinctrl data structures. 44 * @enabled_irqs: Bitmap of currently enabled irqs. 45 * @dual_edge_irqs: Bitmap of irqs that need sw emulated dual edge 46 * detection. 47 * @soc; Reference to soc_data of platform specific data. 48 * @regs: Base addresses for the TLMM tiles. 49 */ 50 struct msm_pinctrl { 51 struct device *dev; 52 struct pinctrl_dev *pctrl; 53 struct gpio_chip chip; 54 struct pinctrl_desc desc; 55 struct notifier_block restart_nb; 56 57 struct irq_chip irq_chip; 58 int irq; 59 60 raw_spinlock_t lock; 61 62 DECLARE_BITMAP(dual_edge_irqs, MAX_NR_GPIO); 63 DECLARE_BITMAP(enabled_irqs, MAX_NR_GPIO); 64 65 const struct msm_pinctrl_soc_data *soc; 66 void __iomem *regs[MAX_NR_TILES]; 67 }; 68 69 #define MSM_ACCESSOR(name) \ 70 static u32 msm_readl_##name(struct msm_pinctrl *pctrl, \ 71 const struct msm_pingroup *g) \ 72 { \ 73 return readl(pctrl->regs[g->tile] + g->name##_reg); \ 74 } \ 75 static void msm_writel_##name(u32 val, struct msm_pinctrl *pctrl, \ 76 const struct msm_pingroup *g) \ 77 { \ 78 writel(val, pctrl->regs[g->tile] + g->name##_reg); \ 79 } 80 81 MSM_ACCESSOR(ctl) 82 MSM_ACCESSOR(io) 83 MSM_ACCESSOR(intr_cfg) 84 MSM_ACCESSOR(intr_status) 85 MSM_ACCESSOR(intr_target) 86 87 static int msm_get_groups_count(struct pinctrl_dev *pctldev) 88 { 89 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 90 91 return pctrl->soc->ngroups; 92 } 93 94 static const char *msm_get_group_name(struct pinctrl_dev *pctldev, 95 unsigned group) 96 { 97 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 98 99 return pctrl->soc->groups[group].name; 100 } 101 102 static int msm_get_group_pins(struct pinctrl_dev *pctldev, 103 unsigned group, 104 const unsigned **pins, 105 unsigned *num_pins) 106 { 107 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 108 109 *pins = pctrl->soc->groups[group].pins; 110 *num_pins = pctrl->soc->groups[group].npins; 111 return 0; 112 } 113 114 static const struct pinctrl_ops msm_pinctrl_ops = { 115 .get_groups_count = msm_get_groups_count, 116 .get_group_name = msm_get_group_name, 117 .get_group_pins = msm_get_group_pins, 118 .dt_node_to_map = pinconf_generic_dt_node_to_map_group, 119 .dt_free_map = pinctrl_utils_free_map, 120 }; 121 122 static int msm_pinmux_request(struct pinctrl_dev *pctldev, unsigned offset) 123 { 124 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 125 struct gpio_chip *chip = &pctrl->chip; 126 127 return gpiochip_line_is_valid(chip, offset) ? 0 : -EINVAL; 128 } 129 130 static int msm_get_functions_count(struct pinctrl_dev *pctldev) 131 { 132 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 133 134 return pctrl->soc->nfunctions; 135 } 136 137 static const char *msm_get_function_name(struct pinctrl_dev *pctldev, 138 unsigned function) 139 { 140 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 141 142 return pctrl->soc->functions[function].name; 143 } 144 145 static int msm_get_function_groups(struct pinctrl_dev *pctldev, 146 unsigned function, 147 const char * const **groups, 148 unsigned * const num_groups) 149 { 150 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 151 152 *groups = pctrl->soc->functions[function].groups; 153 *num_groups = pctrl->soc->functions[function].ngroups; 154 return 0; 155 } 156 157 static int msm_pinmux_set_mux(struct pinctrl_dev *pctldev, 158 unsigned function, 159 unsigned group) 160 { 161 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 162 const struct msm_pingroup *g; 163 unsigned long flags; 164 u32 val, mask; 165 int i; 166 167 g = &pctrl->soc->groups[group]; 168 mask = GENMASK(g->mux_bit + order_base_2(g->nfuncs) - 1, g->mux_bit); 169 170 for (i = 0; i < g->nfuncs; i++) { 171 if (g->funcs[i] == function) 172 break; 173 } 174 175 if (WARN_ON(i == g->nfuncs)) 176 return -EINVAL; 177 178 raw_spin_lock_irqsave(&pctrl->lock, flags); 179 180 val = msm_readl_ctl(pctrl, g); 181 val &= ~mask; 182 val |= i << g->mux_bit; 183 msm_writel_ctl(val, pctrl, g); 184 185 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 186 187 return 0; 188 } 189 190 static int msm_pinmux_request_gpio(struct pinctrl_dev *pctldev, 191 struct pinctrl_gpio_range *range, 192 unsigned offset) 193 { 194 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 195 const struct msm_pingroup *g = &pctrl->soc->groups[offset]; 196 197 /* No funcs? Probably ACPI so can't do anything here */ 198 if (!g->nfuncs) 199 return 0; 200 201 /* For now assume function 0 is GPIO because it always is */ 202 return msm_pinmux_set_mux(pctldev, g->funcs[0], offset); 203 } 204 205 static const struct pinmux_ops msm_pinmux_ops = { 206 .request = msm_pinmux_request, 207 .get_functions_count = msm_get_functions_count, 208 .get_function_name = msm_get_function_name, 209 .get_function_groups = msm_get_function_groups, 210 .gpio_request_enable = msm_pinmux_request_gpio, 211 .set_mux = msm_pinmux_set_mux, 212 }; 213 214 static int msm_config_reg(struct msm_pinctrl *pctrl, 215 const struct msm_pingroup *g, 216 unsigned param, 217 unsigned *mask, 218 unsigned *bit) 219 { 220 switch (param) { 221 case PIN_CONFIG_BIAS_DISABLE: 222 case PIN_CONFIG_BIAS_PULL_DOWN: 223 case PIN_CONFIG_BIAS_BUS_HOLD: 224 case PIN_CONFIG_BIAS_PULL_UP: 225 *bit = g->pull_bit; 226 *mask = 3; 227 break; 228 case PIN_CONFIG_DRIVE_STRENGTH: 229 *bit = g->drv_bit; 230 *mask = 7; 231 break; 232 case PIN_CONFIG_OUTPUT: 233 case PIN_CONFIG_INPUT_ENABLE: 234 *bit = g->oe_bit; 235 *mask = 1; 236 break; 237 default: 238 return -ENOTSUPP; 239 } 240 241 return 0; 242 } 243 244 #define MSM_NO_PULL 0 245 #define MSM_PULL_DOWN 1 246 #define MSM_KEEPER 2 247 #define MSM_PULL_UP_NO_KEEPER 2 248 #define MSM_PULL_UP 3 249 250 static unsigned msm_regval_to_drive(u32 val) 251 { 252 return (val + 1) * 2; 253 } 254 255 static int msm_config_group_get(struct pinctrl_dev *pctldev, 256 unsigned int group, 257 unsigned long *config) 258 { 259 const struct msm_pingroup *g; 260 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 261 unsigned param = pinconf_to_config_param(*config); 262 unsigned mask; 263 unsigned arg; 264 unsigned bit; 265 int ret; 266 u32 val; 267 268 g = &pctrl->soc->groups[group]; 269 270 ret = msm_config_reg(pctrl, g, param, &mask, &bit); 271 if (ret < 0) 272 return ret; 273 274 val = msm_readl_ctl(pctrl, g); 275 arg = (val >> bit) & mask; 276 277 /* Convert register value to pinconf value */ 278 switch (param) { 279 case PIN_CONFIG_BIAS_DISABLE: 280 if (arg != MSM_NO_PULL) 281 return -EINVAL; 282 arg = 1; 283 break; 284 case PIN_CONFIG_BIAS_PULL_DOWN: 285 if (arg != MSM_PULL_DOWN) 286 return -EINVAL; 287 arg = 1; 288 break; 289 case PIN_CONFIG_BIAS_BUS_HOLD: 290 if (pctrl->soc->pull_no_keeper) 291 return -ENOTSUPP; 292 293 if (arg != MSM_KEEPER) 294 return -EINVAL; 295 arg = 1; 296 break; 297 case PIN_CONFIG_BIAS_PULL_UP: 298 if (pctrl->soc->pull_no_keeper) 299 arg = arg == MSM_PULL_UP_NO_KEEPER; 300 else 301 arg = arg == MSM_PULL_UP; 302 if (!arg) 303 return -EINVAL; 304 break; 305 case PIN_CONFIG_DRIVE_STRENGTH: 306 arg = msm_regval_to_drive(arg); 307 break; 308 case PIN_CONFIG_OUTPUT: 309 /* Pin is not output */ 310 if (!arg) 311 return -EINVAL; 312 313 val = msm_readl_io(pctrl, g); 314 arg = !!(val & BIT(g->in_bit)); 315 break; 316 case PIN_CONFIG_INPUT_ENABLE: 317 /* Pin is output */ 318 if (arg) 319 return -EINVAL; 320 arg = 1; 321 break; 322 default: 323 return -ENOTSUPP; 324 } 325 326 *config = pinconf_to_config_packed(param, arg); 327 328 return 0; 329 } 330 331 static int msm_config_group_set(struct pinctrl_dev *pctldev, 332 unsigned group, 333 unsigned long *configs, 334 unsigned num_configs) 335 { 336 const struct msm_pingroup *g; 337 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 338 unsigned long flags; 339 unsigned param; 340 unsigned mask; 341 unsigned arg; 342 unsigned bit; 343 int ret; 344 u32 val; 345 int i; 346 347 g = &pctrl->soc->groups[group]; 348 349 for (i = 0; i < num_configs; i++) { 350 param = pinconf_to_config_param(configs[i]); 351 arg = pinconf_to_config_argument(configs[i]); 352 353 ret = msm_config_reg(pctrl, g, param, &mask, &bit); 354 if (ret < 0) 355 return ret; 356 357 /* Convert pinconf values to register values */ 358 switch (param) { 359 case PIN_CONFIG_BIAS_DISABLE: 360 arg = MSM_NO_PULL; 361 break; 362 case PIN_CONFIG_BIAS_PULL_DOWN: 363 arg = MSM_PULL_DOWN; 364 break; 365 case PIN_CONFIG_BIAS_BUS_HOLD: 366 if (pctrl->soc->pull_no_keeper) 367 return -ENOTSUPP; 368 369 arg = MSM_KEEPER; 370 break; 371 case PIN_CONFIG_BIAS_PULL_UP: 372 if (pctrl->soc->pull_no_keeper) 373 arg = MSM_PULL_UP_NO_KEEPER; 374 else 375 arg = MSM_PULL_UP; 376 break; 377 case PIN_CONFIG_DRIVE_STRENGTH: 378 /* Check for invalid values */ 379 if (arg > 16 || arg < 2 || (arg % 2) != 0) 380 arg = -1; 381 else 382 arg = (arg / 2) - 1; 383 break; 384 case PIN_CONFIG_OUTPUT: 385 /* set output value */ 386 raw_spin_lock_irqsave(&pctrl->lock, flags); 387 val = msm_readl_io(pctrl, g); 388 if (arg) 389 val |= BIT(g->out_bit); 390 else 391 val &= ~BIT(g->out_bit); 392 msm_writel_io(val, pctrl, g); 393 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 394 395 /* enable output */ 396 arg = 1; 397 break; 398 case PIN_CONFIG_INPUT_ENABLE: 399 /* disable output */ 400 arg = 0; 401 break; 402 default: 403 dev_err(pctrl->dev, "Unsupported config parameter: %x\n", 404 param); 405 return -EINVAL; 406 } 407 408 /* Range-check user-supplied value */ 409 if (arg & ~mask) { 410 dev_err(pctrl->dev, "config %x: %x is invalid\n", param, arg); 411 return -EINVAL; 412 } 413 414 raw_spin_lock_irqsave(&pctrl->lock, flags); 415 val = msm_readl_ctl(pctrl, g); 416 val &= ~(mask << bit); 417 val |= arg << bit; 418 msm_writel_ctl(val, pctrl, g); 419 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 420 } 421 422 return 0; 423 } 424 425 static const struct pinconf_ops msm_pinconf_ops = { 426 .is_generic = true, 427 .pin_config_group_get = msm_config_group_get, 428 .pin_config_group_set = msm_config_group_set, 429 }; 430 431 static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 432 { 433 const struct msm_pingroup *g; 434 struct msm_pinctrl *pctrl = gpiochip_get_data(chip); 435 unsigned long flags; 436 u32 val; 437 438 g = &pctrl->soc->groups[offset]; 439 440 raw_spin_lock_irqsave(&pctrl->lock, flags); 441 442 val = msm_readl_ctl(pctrl, g); 443 val &= ~BIT(g->oe_bit); 444 msm_writel_ctl(val, pctrl, g); 445 446 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 447 448 return 0; 449 } 450 451 static int msm_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value) 452 { 453 const struct msm_pingroup *g; 454 struct msm_pinctrl *pctrl = gpiochip_get_data(chip); 455 unsigned long flags; 456 u32 val; 457 458 g = &pctrl->soc->groups[offset]; 459 460 raw_spin_lock_irqsave(&pctrl->lock, flags); 461 462 val = msm_readl_io(pctrl, g); 463 if (value) 464 val |= BIT(g->out_bit); 465 else 466 val &= ~BIT(g->out_bit); 467 msm_writel_io(val, pctrl, g); 468 469 val = msm_readl_ctl(pctrl, g); 470 val |= BIT(g->oe_bit); 471 msm_writel_ctl(val, pctrl, g); 472 473 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 474 475 return 0; 476 } 477 478 static int msm_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 479 { 480 struct msm_pinctrl *pctrl = gpiochip_get_data(chip); 481 const struct msm_pingroup *g; 482 u32 val; 483 484 g = &pctrl->soc->groups[offset]; 485 486 val = msm_readl_ctl(pctrl, g); 487 488 /* 0 = output, 1 = input */ 489 return val & BIT(g->oe_bit) ? 0 : 1; 490 } 491 492 static int msm_gpio_get(struct gpio_chip *chip, unsigned offset) 493 { 494 const struct msm_pingroup *g; 495 struct msm_pinctrl *pctrl = gpiochip_get_data(chip); 496 u32 val; 497 498 g = &pctrl->soc->groups[offset]; 499 500 val = msm_readl_io(pctrl, g); 501 return !!(val & BIT(g->in_bit)); 502 } 503 504 static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 505 { 506 const struct msm_pingroup *g; 507 struct msm_pinctrl *pctrl = gpiochip_get_data(chip); 508 unsigned long flags; 509 u32 val; 510 511 g = &pctrl->soc->groups[offset]; 512 513 raw_spin_lock_irqsave(&pctrl->lock, flags); 514 515 val = msm_readl_io(pctrl, g); 516 if (value) 517 val |= BIT(g->out_bit); 518 else 519 val &= ~BIT(g->out_bit); 520 msm_writel_io(val, pctrl, g); 521 522 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 523 } 524 525 #ifdef CONFIG_DEBUG_FS 526 #include <linux/seq_file.h> 527 528 static void msm_gpio_dbg_show_one(struct seq_file *s, 529 struct pinctrl_dev *pctldev, 530 struct gpio_chip *chip, 531 unsigned offset, 532 unsigned gpio) 533 { 534 const struct msm_pingroup *g; 535 struct msm_pinctrl *pctrl = gpiochip_get_data(chip); 536 unsigned func; 537 int is_out; 538 int drive; 539 int pull; 540 int val; 541 u32 ctl_reg, io_reg; 542 543 static const char * const pulls_keeper[] = { 544 "no pull", 545 "pull down", 546 "keeper", 547 "pull up" 548 }; 549 550 static const char * const pulls_no_keeper[] = { 551 "no pull", 552 "pull down", 553 "pull up", 554 }; 555 556 if (!gpiochip_line_is_valid(chip, offset)) 557 return; 558 559 g = &pctrl->soc->groups[offset]; 560 ctl_reg = msm_readl_ctl(pctrl, g); 561 io_reg = msm_readl_io(pctrl, g); 562 563 is_out = !!(ctl_reg & BIT(g->oe_bit)); 564 func = (ctl_reg >> g->mux_bit) & 7; 565 drive = (ctl_reg >> g->drv_bit) & 7; 566 pull = (ctl_reg >> g->pull_bit) & 3; 567 568 if (is_out) 569 val = !!(io_reg & BIT(g->out_bit)); 570 else 571 val = !!(io_reg & BIT(g->in_bit)); 572 573 seq_printf(s, " %-8s: %-3s", g->name, is_out ? "out" : "in"); 574 seq_printf(s, " %-4s func%d", val ? "high" : "low", func); 575 seq_printf(s, " %dmA", msm_regval_to_drive(drive)); 576 if (pctrl->soc->pull_no_keeper) 577 seq_printf(s, " %s", pulls_no_keeper[pull]); 578 else 579 seq_printf(s, " %s", pulls_keeper[pull]); 580 seq_puts(s, "\n"); 581 } 582 583 static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) 584 { 585 unsigned gpio = chip->base; 586 unsigned i; 587 588 for (i = 0; i < chip->ngpio; i++, gpio++) 589 msm_gpio_dbg_show_one(s, NULL, chip, i, gpio); 590 } 591 592 #else 593 #define msm_gpio_dbg_show NULL 594 #endif 595 596 static int msm_gpio_init_valid_mask(struct gpio_chip *chip) 597 { 598 struct msm_pinctrl *pctrl = gpiochip_get_data(chip); 599 int ret; 600 unsigned int len, i; 601 unsigned int max_gpios = pctrl->soc->ngpios; 602 u16 *tmp; 603 604 /* The number of GPIOs in the ACPI tables */ 605 len = ret = device_property_read_u16_array(pctrl->dev, "gpios", NULL, 606 0); 607 if (ret < 0) 608 return 0; 609 610 if (ret > max_gpios) 611 return -EINVAL; 612 613 tmp = kmalloc_array(len, sizeof(*tmp), GFP_KERNEL); 614 if (!tmp) 615 return -ENOMEM; 616 617 ret = device_property_read_u16_array(pctrl->dev, "gpios", tmp, len); 618 if (ret < 0) { 619 dev_err(pctrl->dev, "could not read list of GPIOs\n"); 620 goto out; 621 } 622 623 bitmap_zero(chip->valid_mask, max_gpios); 624 for (i = 0; i < len; i++) 625 set_bit(tmp[i], chip->valid_mask); 626 627 out: 628 kfree(tmp); 629 return ret; 630 } 631 632 static const struct gpio_chip msm_gpio_template = { 633 .direction_input = msm_gpio_direction_input, 634 .direction_output = msm_gpio_direction_output, 635 .get_direction = msm_gpio_get_direction, 636 .get = msm_gpio_get, 637 .set = msm_gpio_set, 638 .request = gpiochip_generic_request, 639 .free = gpiochip_generic_free, 640 .dbg_show = msm_gpio_dbg_show, 641 .init_valid_mask = msm_gpio_init_valid_mask, 642 }; 643 644 /* For dual-edge interrupts in software, since some hardware has no 645 * such support: 646 * 647 * At appropriate moments, this function may be called to flip the polarity 648 * settings of both-edge irq lines to try and catch the next edge. 649 * 650 * The attempt is considered successful if: 651 * - the status bit goes high, indicating that an edge was caught, or 652 * - the input value of the gpio doesn't change during the attempt. 653 * If the value changes twice during the process, that would cause the first 654 * test to fail but would force the second, as two opposite 655 * transitions would cause a detection no matter the polarity setting. 656 * 657 * The do-loop tries to sledge-hammer closed the timing hole between 658 * the initial value-read and the polarity-write - if the line value changes 659 * during that window, an interrupt is lost, the new polarity setting is 660 * incorrect, and the first success test will fail, causing a retry. 661 * 662 * Algorithm comes from Google's msmgpio driver. 663 */ 664 static void msm_gpio_update_dual_edge_pos(struct msm_pinctrl *pctrl, 665 const struct msm_pingroup *g, 666 struct irq_data *d) 667 { 668 int loop_limit = 100; 669 unsigned val, val2, intstat; 670 unsigned pol; 671 672 do { 673 val = msm_readl_io(pctrl, g) & BIT(g->in_bit); 674 675 pol = msm_readl_intr_cfg(pctrl, g); 676 pol ^= BIT(g->intr_polarity_bit); 677 msm_writel_intr_cfg(val, pctrl, g); 678 679 val2 = msm_readl_io(pctrl, g) & BIT(g->in_bit); 680 intstat = msm_readl_intr_status(pctrl, g); 681 if (intstat || (val == val2)) 682 return; 683 } while (loop_limit-- > 0); 684 dev_err(pctrl->dev, "dual-edge irq failed to stabilize, %#08x != %#08x\n", 685 val, val2); 686 } 687 688 static void msm_gpio_irq_mask(struct irq_data *d) 689 { 690 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 691 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); 692 const struct msm_pingroup *g; 693 unsigned long flags; 694 u32 val; 695 696 g = &pctrl->soc->groups[d->hwirq]; 697 698 raw_spin_lock_irqsave(&pctrl->lock, flags); 699 700 val = msm_readl_intr_cfg(pctrl, g); 701 /* 702 * There are two bits that control interrupt forwarding to the CPU. The 703 * RAW_STATUS_EN bit causes the level or edge sensed on the line to be 704 * latched into the interrupt status register when the hardware detects 705 * an irq that it's configured for (either edge for edge type or level 706 * for level type irq). The 'non-raw' status enable bit causes the 707 * hardware to assert the summary interrupt to the CPU if the latched 708 * status bit is set. There's a bug though, the edge detection logic 709 * seems to have a problem where toggling the RAW_STATUS_EN bit may 710 * cause the status bit to latch spuriously when there isn't any edge 711 * so we can't touch that bit for edge type irqs and we have to keep 712 * the bit set anyway so that edges are latched while the line is masked. 713 * 714 * To make matters more complicated, leaving the RAW_STATUS_EN bit 715 * enabled all the time causes level interrupts to re-latch into the 716 * status register because the level is still present on the line after 717 * we ack it. We clear the raw status enable bit during mask here and 718 * set the bit on unmask so the interrupt can't latch into the hardware 719 * while it's masked. 720 */ 721 if (irqd_get_trigger_type(d) & IRQ_TYPE_LEVEL_MASK) 722 val &= ~BIT(g->intr_raw_status_bit); 723 724 val &= ~BIT(g->intr_enable_bit); 725 msm_writel_intr_cfg(val, pctrl, g); 726 727 clear_bit(d->hwirq, pctrl->enabled_irqs); 728 729 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 730 } 731 732 static void msm_gpio_irq_unmask(struct irq_data *d) 733 { 734 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 735 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); 736 const struct msm_pingroup *g; 737 unsigned long flags; 738 u32 val; 739 740 g = &pctrl->soc->groups[d->hwirq]; 741 742 raw_spin_lock_irqsave(&pctrl->lock, flags); 743 744 val = msm_readl_intr_cfg(pctrl, g); 745 val |= BIT(g->intr_raw_status_bit); 746 val |= BIT(g->intr_enable_bit); 747 msm_writel_intr_cfg(val, pctrl, g); 748 749 set_bit(d->hwirq, pctrl->enabled_irqs); 750 751 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 752 } 753 754 static void msm_gpio_irq_ack(struct irq_data *d) 755 { 756 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 757 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); 758 const struct msm_pingroup *g; 759 unsigned long flags; 760 u32 val; 761 762 g = &pctrl->soc->groups[d->hwirq]; 763 764 raw_spin_lock_irqsave(&pctrl->lock, flags); 765 766 val = msm_readl_intr_status(pctrl, g); 767 if (g->intr_ack_high) 768 val |= BIT(g->intr_status_bit); 769 else 770 val &= ~BIT(g->intr_status_bit); 771 msm_writel_intr_status(val, pctrl, g); 772 773 if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) 774 msm_gpio_update_dual_edge_pos(pctrl, g, d); 775 776 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 777 } 778 779 static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type) 780 { 781 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 782 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); 783 const struct msm_pingroup *g; 784 unsigned long flags; 785 u32 val; 786 787 g = &pctrl->soc->groups[d->hwirq]; 788 789 raw_spin_lock_irqsave(&pctrl->lock, flags); 790 791 /* 792 * For hw without possibility of detecting both edges 793 */ 794 if (g->intr_detection_width == 1 && type == IRQ_TYPE_EDGE_BOTH) 795 set_bit(d->hwirq, pctrl->dual_edge_irqs); 796 else 797 clear_bit(d->hwirq, pctrl->dual_edge_irqs); 798 799 /* Route interrupts to application cpu */ 800 val = msm_readl_intr_target(pctrl, g); 801 val &= ~(7 << g->intr_target_bit); 802 val |= g->intr_target_kpss_val << g->intr_target_bit; 803 msm_writel_intr_target(val, pctrl, g); 804 805 /* Update configuration for gpio. 806 * RAW_STATUS_EN is left on for all gpio irqs. Due to the 807 * internal circuitry of TLMM, toggling the RAW_STATUS 808 * could cause the INTR_STATUS to be set for EDGE interrupts. 809 */ 810 val = msm_readl_intr_cfg(pctrl, g); 811 val |= BIT(g->intr_raw_status_bit); 812 if (g->intr_detection_width == 2) { 813 val &= ~(3 << g->intr_detection_bit); 814 val &= ~(1 << g->intr_polarity_bit); 815 switch (type) { 816 case IRQ_TYPE_EDGE_RISING: 817 val |= 1 << g->intr_detection_bit; 818 val |= BIT(g->intr_polarity_bit); 819 break; 820 case IRQ_TYPE_EDGE_FALLING: 821 val |= 2 << g->intr_detection_bit; 822 val |= BIT(g->intr_polarity_bit); 823 break; 824 case IRQ_TYPE_EDGE_BOTH: 825 val |= 3 << g->intr_detection_bit; 826 val |= BIT(g->intr_polarity_bit); 827 break; 828 case IRQ_TYPE_LEVEL_LOW: 829 break; 830 case IRQ_TYPE_LEVEL_HIGH: 831 val |= BIT(g->intr_polarity_bit); 832 break; 833 } 834 } else if (g->intr_detection_width == 1) { 835 val &= ~(1 << g->intr_detection_bit); 836 val &= ~(1 << g->intr_polarity_bit); 837 switch (type) { 838 case IRQ_TYPE_EDGE_RISING: 839 val |= BIT(g->intr_detection_bit); 840 val |= BIT(g->intr_polarity_bit); 841 break; 842 case IRQ_TYPE_EDGE_FALLING: 843 val |= BIT(g->intr_detection_bit); 844 break; 845 case IRQ_TYPE_EDGE_BOTH: 846 val |= BIT(g->intr_detection_bit); 847 val |= BIT(g->intr_polarity_bit); 848 break; 849 case IRQ_TYPE_LEVEL_LOW: 850 break; 851 case IRQ_TYPE_LEVEL_HIGH: 852 val |= BIT(g->intr_polarity_bit); 853 break; 854 } 855 } else { 856 BUG(); 857 } 858 msm_writel_intr_cfg(val, pctrl, g); 859 860 if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) 861 msm_gpio_update_dual_edge_pos(pctrl, g, d); 862 863 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 864 865 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) 866 irq_set_handler_locked(d, handle_level_irq); 867 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) 868 irq_set_handler_locked(d, handle_edge_irq); 869 870 return 0; 871 } 872 873 static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on) 874 { 875 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 876 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); 877 unsigned long flags; 878 879 raw_spin_lock_irqsave(&pctrl->lock, flags); 880 881 irq_set_irq_wake(pctrl->irq, on); 882 883 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 884 885 return 0; 886 } 887 888 static int msm_gpio_irq_reqres(struct irq_data *d) 889 { 890 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 891 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); 892 int ret; 893 894 if (!try_module_get(gc->owner)) 895 return -ENODEV; 896 897 ret = msm_pinmux_request_gpio(pctrl->pctrl, NULL, d->hwirq); 898 if (ret) 899 goto out; 900 msm_gpio_direction_input(gc, d->hwirq); 901 902 if (gpiochip_lock_as_irq(gc, d->hwirq)) { 903 dev_err(gc->parent, 904 "unable to lock HW IRQ %lu for IRQ\n", 905 d->hwirq); 906 ret = -EINVAL; 907 goto out; 908 } 909 return 0; 910 out: 911 module_put(gc->owner); 912 return ret; 913 } 914 915 static void msm_gpio_irq_relres(struct irq_data *d) 916 { 917 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 918 919 gpiochip_unlock_as_irq(gc, d->hwirq); 920 module_put(gc->owner); 921 } 922 923 static void msm_gpio_irq_handler(struct irq_desc *desc) 924 { 925 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 926 const struct msm_pingroup *g; 927 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); 928 struct irq_chip *chip = irq_desc_get_chip(desc); 929 int irq_pin; 930 int handled = 0; 931 u32 val; 932 int i; 933 934 chained_irq_enter(chip, desc); 935 936 /* 937 * Each pin has it's own IRQ status register, so use 938 * enabled_irq bitmap to limit the number of reads. 939 */ 940 for_each_set_bit(i, pctrl->enabled_irqs, pctrl->chip.ngpio) { 941 g = &pctrl->soc->groups[i]; 942 val = msm_readl_intr_status(pctrl, g); 943 if (val & BIT(g->intr_status_bit)) { 944 irq_pin = irq_find_mapping(gc->irq.domain, i); 945 generic_handle_irq(irq_pin); 946 handled++; 947 } 948 } 949 950 /* No interrupts were flagged */ 951 if (handled == 0) 952 handle_bad_irq(desc); 953 954 chained_irq_exit(chip, desc); 955 } 956 957 static bool msm_gpio_needs_valid_mask(struct msm_pinctrl *pctrl) 958 { 959 return device_property_read_u16_array(pctrl->dev, "gpios", NULL, 0) > 0; 960 } 961 962 static int msm_gpio_init(struct msm_pinctrl *pctrl) 963 { 964 struct gpio_chip *chip; 965 int ret; 966 unsigned ngpio = pctrl->soc->ngpios; 967 968 if (WARN_ON(ngpio > MAX_NR_GPIO)) 969 return -EINVAL; 970 971 chip = &pctrl->chip; 972 chip->base = -1; 973 chip->ngpio = ngpio; 974 chip->label = dev_name(pctrl->dev); 975 chip->parent = pctrl->dev; 976 chip->owner = THIS_MODULE; 977 chip->of_node = pctrl->dev->of_node; 978 chip->need_valid_mask = msm_gpio_needs_valid_mask(pctrl); 979 980 pctrl->irq_chip.name = "msmgpio"; 981 pctrl->irq_chip.irq_mask = msm_gpio_irq_mask; 982 pctrl->irq_chip.irq_unmask = msm_gpio_irq_unmask; 983 pctrl->irq_chip.irq_ack = msm_gpio_irq_ack; 984 pctrl->irq_chip.irq_set_type = msm_gpio_irq_set_type; 985 pctrl->irq_chip.irq_set_wake = msm_gpio_irq_set_wake; 986 pctrl->irq_chip.irq_request_resources = msm_gpio_irq_reqres; 987 pctrl->irq_chip.irq_release_resources = msm_gpio_irq_relres; 988 989 ret = gpiochip_add_data(&pctrl->chip, pctrl); 990 if (ret) { 991 dev_err(pctrl->dev, "Failed register gpiochip\n"); 992 return ret; 993 } 994 995 /* 996 * For DeviceTree-supported systems, the gpio core checks the 997 * pinctrl's device node for the "gpio-ranges" property. 998 * If it is present, it takes care of adding the pin ranges 999 * for the driver. In this case the driver can skip ahead. 1000 * 1001 * In order to remain compatible with older, existing DeviceTree 1002 * files which don't set the "gpio-ranges" property or systems that 1003 * utilize ACPI the driver has to call gpiochip_add_pin_range(). 1004 */ 1005 if (!of_property_read_bool(pctrl->dev->of_node, "gpio-ranges")) { 1006 ret = gpiochip_add_pin_range(&pctrl->chip, 1007 dev_name(pctrl->dev), 0, 0, chip->ngpio); 1008 if (ret) { 1009 dev_err(pctrl->dev, "Failed to add pin range\n"); 1010 gpiochip_remove(&pctrl->chip); 1011 return ret; 1012 } 1013 } 1014 1015 ret = gpiochip_irqchip_add(chip, 1016 &pctrl->irq_chip, 1017 0, 1018 handle_edge_irq, 1019 IRQ_TYPE_NONE); 1020 if (ret) { 1021 dev_err(pctrl->dev, "Failed to add irqchip to gpiochip\n"); 1022 gpiochip_remove(&pctrl->chip); 1023 return -ENOSYS; 1024 } 1025 1026 gpiochip_set_chained_irqchip(chip, &pctrl->irq_chip, pctrl->irq, 1027 msm_gpio_irq_handler); 1028 1029 return 0; 1030 } 1031 1032 static int msm_ps_hold_restart(struct notifier_block *nb, unsigned long action, 1033 void *data) 1034 { 1035 struct msm_pinctrl *pctrl = container_of(nb, struct msm_pinctrl, restart_nb); 1036 1037 writel(0, pctrl->regs[0] + PS_HOLD_OFFSET); 1038 mdelay(1000); 1039 return NOTIFY_DONE; 1040 } 1041 1042 static struct msm_pinctrl *poweroff_pctrl; 1043 1044 static void msm_ps_hold_poweroff(void) 1045 { 1046 msm_ps_hold_restart(&poweroff_pctrl->restart_nb, 0, NULL); 1047 } 1048 1049 static void msm_pinctrl_setup_pm_reset(struct msm_pinctrl *pctrl) 1050 { 1051 int i; 1052 const struct msm_function *func = pctrl->soc->functions; 1053 1054 for (i = 0; i < pctrl->soc->nfunctions; i++) 1055 if (!strcmp(func[i].name, "ps_hold")) { 1056 pctrl->restart_nb.notifier_call = msm_ps_hold_restart; 1057 pctrl->restart_nb.priority = 128; 1058 if (register_restart_handler(&pctrl->restart_nb)) 1059 dev_err(pctrl->dev, 1060 "failed to setup restart handler.\n"); 1061 poweroff_pctrl = pctrl; 1062 pm_power_off = msm_ps_hold_poweroff; 1063 break; 1064 } 1065 } 1066 1067 static __maybe_unused int msm_pinctrl_suspend(struct device *dev) 1068 { 1069 struct msm_pinctrl *pctrl = dev_get_drvdata(dev); 1070 1071 return pinctrl_force_sleep(pctrl->pctrl); 1072 } 1073 1074 static __maybe_unused int msm_pinctrl_resume(struct device *dev) 1075 { 1076 struct msm_pinctrl *pctrl = dev_get_drvdata(dev); 1077 1078 return pinctrl_force_default(pctrl->pctrl); 1079 } 1080 1081 SIMPLE_DEV_PM_OPS(msm_pinctrl_dev_pm_ops, msm_pinctrl_suspend, 1082 msm_pinctrl_resume); 1083 1084 EXPORT_SYMBOL(msm_pinctrl_dev_pm_ops); 1085 1086 int msm_pinctrl_probe(struct platform_device *pdev, 1087 const struct msm_pinctrl_soc_data *soc_data) 1088 { 1089 struct msm_pinctrl *pctrl; 1090 struct resource *res; 1091 int ret; 1092 int i; 1093 1094 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); 1095 if (!pctrl) 1096 return -ENOMEM; 1097 1098 pctrl->dev = &pdev->dev; 1099 pctrl->soc = soc_data; 1100 pctrl->chip = msm_gpio_template; 1101 1102 raw_spin_lock_init(&pctrl->lock); 1103 1104 if (soc_data->tiles) { 1105 for (i = 0; i < soc_data->ntiles; i++) { 1106 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 1107 soc_data->tiles[i]); 1108 pctrl->regs[i] = devm_ioremap_resource(&pdev->dev, res); 1109 if (IS_ERR(pctrl->regs[i])) 1110 return PTR_ERR(pctrl->regs[i]); 1111 } 1112 } else { 1113 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1114 pctrl->regs[0] = devm_ioremap_resource(&pdev->dev, res); 1115 if (IS_ERR(pctrl->regs[0])) 1116 return PTR_ERR(pctrl->regs[0]); 1117 } 1118 1119 msm_pinctrl_setup_pm_reset(pctrl); 1120 1121 pctrl->irq = platform_get_irq(pdev, 0); 1122 if (pctrl->irq < 0) { 1123 dev_err(&pdev->dev, "No interrupt defined for msmgpio\n"); 1124 return pctrl->irq; 1125 } 1126 1127 pctrl->desc.owner = THIS_MODULE; 1128 pctrl->desc.pctlops = &msm_pinctrl_ops; 1129 pctrl->desc.pmxops = &msm_pinmux_ops; 1130 pctrl->desc.confops = &msm_pinconf_ops; 1131 pctrl->desc.name = dev_name(&pdev->dev); 1132 pctrl->desc.pins = pctrl->soc->pins; 1133 pctrl->desc.npins = pctrl->soc->npins; 1134 1135 pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &pctrl->desc, pctrl); 1136 if (IS_ERR(pctrl->pctrl)) { 1137 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); 1138 return PTR_ERR(pctrl->pctrl); 1139 } 1140 1141 ret = msm_gpio_init(pctrl); 1142 if (ret) 1143 return ret; 1144 1145 platform_set_drvdata(pdev, pctrl); 1146 1147 dev_dbg(&pdev->dev, "Probed Qualcomm pinctrl driver\n"); 1148 1149 return 0; 1150 } 1151 EXPORT_SYMBOL(msm_pinctrl_probe); 1152 1153 int msm_pinctrl_remove(struct platform_device *pdev) 1154 { 1155 struct msm_pinctrl *pctrl = platform_get_drvdata(pdev); 1156 1157 gpiochip_remove(&pctrl->chip); 1158 1159 unregister_restart_handler(&pctrl->restart_nb); 1160 1161 return 0; 1162 } 1163 EXPORT_SYMBOL(msm_pinctrl_remove); 1164 1165