1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2013, Sony Mobile Communications AB.
4  * Copyright (c) 2013, The Linux Foundation. All rights reserved.
5  */
6 
7 #include <linux/delay.h>
8 #include <linux/err.h>
9 #include <linux/io.h>
10 #include <linux/module.h>
11 #include <linux/of.h>
12 #include <linux/platform_device.h>
13 #include <linux/pinctrl/machine.h>
14 #include <linux/pinctrl/pinctrl.h>
15 #include <linux/pinctrl/pinmux.h>
16 #include <linux/pinctrl/pinconf.h>
17 #include <linux/pinctrl/pinconf-generic.h>
18 #include <linux/slab.h>
19 #include <linux/gpio/driver.h>
20 #include <linux/interrupt.h>
21 #include <linux/spinlock.h>
22 #include <linux/reboot.h>
23 #include <linux/pm.h>
24 #include <linux/log2.h>
25 #include <linux/qcom_scm.h>
26 
27 #include <linux/soc/qcom/irq.h>
28 
29 #include "../core.h"
30 #include "../pinconf.h"
31 #include "pinctrl-msm.h"
32 #include "../pinctrl-utils.h"
33 
34 #define MAX_NR_GPIO 300
35 #define MAX_NR_TILES 4
36 #define PS_HOLD_OFFSET 0x820
37 
38 /**
39  * struct msm_pinctrl - state for a pinctrl-msm device
40  * @dev:            device handle.
41  * @pctrl:          pinctrl handle.
42  * @chip:           gpiochip handle.
43  * @desc:           pin controller descriptor
44  * @restart_nb:     restart notifier block.
45  * @irq_chip:       irq chip information
46  * @irq:            parent irq for the TLMM irq_chip.
47  * @intr_target_use_scm: route irq to application cpu using scm calls
48  * @lock:           Spinlock to protect register resources as well
49  *                  as msm_pinctrl data structures.
50  * @enabled_irqs:   Bitmap of currently enabled irqs.
51  * @dual_edge_irqs: Bitmap of irqs that need sw emulated dual edge
52  *                  detection.
53  * @skip_wake_irqs: Skip IRQs that are handled by wakeup interrupt controller
54  * @disabled_for_mux: These IRQs were disabled because we muxed away.
55  * @soc:            Reference to soc_data of platform specific data.
56  * @regs:           Base addresses for the TLMM tiles.
57  * @phys_base:      Physical base address
58  */
59 struct msm_pinctrl {
60 	struct device *dev;
61 	struct pinctrl_dev *pctrl;
62 	struct gpio_chip chip;
63 	struct pinctrl_desc desc;
64 	struct notifier_block restart_nb;
65 
66 	struct irq_chip irq_chip;
67 	int irq;
68 
69 	bool intr_target_use_scm;
70 
71 	raw_spinlock_t lock;
72 
73 	DECLARE_BITMAP(dual_edge_irqs, MAX_NR_GPIO);
74 	DECLARE_BITMAP(enabled_irqs, MAX_NR_GPIO);
75 	DECLARE_BITMAP(skip_wake_irqs, MAX_NR_GPIO);
76 	DECLARE_BITMAP(disabled_for_mux, MAX_NR_GPIO);
77 
78 	const struct msm_pinctrl_soc_data *soc;
79 	void __iomem *regs[MAX_NR_TILES];
80 	u32 phys_base[MAX_NR_TILES];
81 };
82 
83 #define MSM_ACCESSOR(name) \
84 static u32 msm_readl_##name(struct msm_pinctrl *pctrl, \
85 			    const struct msm_pingroup *g) \
86 { \
87 	return readl(pctrl->regs[g->tile] + g->name##_reg); \
88 } \
89 static void msm_writel_##name(u32 val, struct msm_pinctrl *pctrl, \
90 			      const struct msm_pingroup *g) \
91 { \
92 	writel(val, pctrl->regs[g->tile] + g->name##_reg); \
93 }
94 
95 MSM_ACCESSOR(ctl)
96 MSM_ACCESSOR(io)
97 MSM_ACCESSOR(intr_cfg)
98 MSM_ACCESSOR(intr_status)
99 MSM_ACCESSOR(intr_target)
100 
101 static void msm_ack_intr_status(struct msm_pinctrl *pctrl,
102 				const struct msm_pingroup *g)
103 {
104 	u32 val = g->intr_ack_high ? BIT(g->intr_status_bit) : 0;
105 
106 	msm_writel_intr_status(val, pctrl, g);
107 }
108 
109 static int msm_get_groups_count(struct pinctrl_dev *pctldev)
110 {
111 	struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
112 
113 	return pctrl->soc->ngroups;
114 }
115 
116 static const char *msm_get_group_name(struct pinctrl_dev *pctldev,
117 				      unsigned group)
118 {
119 	struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
120 
121 	return pctrl->soc->groups[group].name;
122 }
123 
124 static int msm_get_group_pins(struct pinctrl_dev *pctldev,
125 			      unsigned group,
126 			      const unsigned **pins,
127 			      unsigned *num_pins)
128 {
129 	struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
130 
131 	*pins = pctrl->soc->groups[group].pins;
132 	*num_pins = pctrl->soc->groups[group].npins;
133 	return 0;
134 }
135 
136 static const struct pinctrl_ops msm_pinctrl_ops = {
137 	.get_groups_count	= msm_get_groups_count,
138 	.get_group_name		= msm_get_group_name,
139 	.get_group_pins		= msm_get_group_pins,
140 	.dt_node_to_map		= pinconf_generic_dt_node_to_map_group,
141 	.dt_free_map		= pinctrl_utils_free_map,
142 };
143 
144 static int msm_pinmux_request(struct pinctrl_dev *pctldev, unsigned offset)
145 {
146 	struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
147 	struct gpio_chip *chip = &pctrl->chip;
148 
149 	return gpiochip_line_is_valid(chip, offset) ? 0 : -EINVAL;
150 }
151 
152 static int msm_get_functions_count(struct pinctrl_dev *pctldev)
153 {
154 	struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
155 
156 	return pctrl->soc->nfunctions;
157 }
158 
159 static const char *msm_get_function_name(struct pinctrl_dev *pctldev,
160 					 unsigned function)
161 {
162 	struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
163 
164 	return pctrl->soc->functions[function].name;
165 }
166 
167 static int msm_get_function_groups(struct pinctrl_dev *pctldev,
168 				   unsigned function,
169 				   const char * const **groups,
170 				   unsigned * const num_groups)
171 {
172 	struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
173 
174 	*groups = pctrl->soc->functions[function].groups;
175 	*num_groups = pctrl->soc->functions[function].ngroups;
176 	return 0;
177 }
178 
179 static int msm_pinmux_set_mux(struct pinctrl_dev *pctldev,
180 			      unsigned function,
181 			      unsigned group)
182 {
183 	struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
184 	struct gpio_chip *gc = &pctrl->chip;
185 	unsigned int irq = irq_find_mapping(gc->irq.domain, group);
186 	struct irq_data *d = irq_get_irq_data(irq);
187 	unsigned int gpio_func = pctrl->soc->gpio_func;
188 	const struct msm_pingroup *g;
189 	unsigned long flags;
190 	u32 val, mask;
191 	int i;
192 
193 	g = &pctrl->soc->groups[group];
194 	mask = GENMASK(g->mux_bit + order_base_2(g->nfuncs) - 1, g->mux_bit);
195 
196 	for (i = 0; i < g->nfuncs; i++) {
197 		if (g->funcs[i] == function)
198 			break;
199 	}
200 
201 	if (WARN_ON(i == g->nfuncs))
202 		return -EINVAL;
203 
204 	/*
205 	 * If an GPIO interrupt is setup on this pin then we need special
206 	 * handling.  Specifically interrupt detection logic will still see
207 	 * the pin twiddle even when we're muxed away.
208 	 *
209 	 * When we see a pin with an interrupt setup on it then we'll disable
210 	 * (mask) interrupts on it when we mux away until we mux back.  Note
211 	 * that disable_irq() refcounts and interrupts are disabled as long as
212 	 * at least one disable_irq() has been called.
213 	 */
214 	if (d && i != gpio_func &&
215 	    !test_and_set_bit(d->hwirq, pctrl->disabled_for_mux))
216 		disable_irq(irq);
217 
218 	raw_spin_lock_irqsave(&pctrl->lock, flags);
219 
220 	val = msm_readl_ctl(pctrl, g);
221 	val &= ~mask;
222 	val |= i << g->mux_bit;
223 	msm_writel_ctl(val, pctrl, g);
224 
225 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
226 
227 	if (d && i == gpio_func &&
228 	    test_and_clear_bit(d->hwirq, pctrl->disabled_for_mux)) {
229 		/*
230 		 * Clear interrupts detected while not GPIO since we only
231 		 * masked things.
232 		 */
233 		if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs))
234 			irq_chip_set_parent_state(d, IRQCHIP_STATE_PENDING, false);
235 		else
236 			msm_ack_intr_status(pctrl, g);
237 
238 		enable_irq(irq);
239 	}
240 
241 	return 0;
242 }
243 
244 static int msm_pinmux_request_gpio(struct pinctrl_dev *pctldev,
245 				   struct pinctrl_gpio_range *range,
246 				   unsigned offset)
247 {
248 	struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
249 	const struct msm_pingroup *g = &pctrl->soc->groups[offset];
250 
251 	/* No funcs? Probably ACPI so can't do anything here */
252 	if (!g->nfuncs)
253 		return 0;
254 
255 	return msm_pinmux_set_mux(pctldev, g->funcs[pctrl->soc->gpio_func], offset);
256 }
257 
258 static const struct pinmux_ops msm_pinmux_ops = {
259 	.request		= msm_pinmux_request,
260 	.get_functions_count	= msm_get_functions_count,
261 	.get_function_name	= msm_get_function_name,
262 	.get_function_groups	= msm_get_function_groups,
263 	.gpio_request_enable	= msm_pinmux_request_gpio,
264 	.set_mux		= msm_pinmux_set_mux,
265 };
266 
267 static int msm_config_reg(struct msm_pinctrl *pctrl,
268 			  const struct msm_pingroup *g,
269 			  unsigned param,
270 			  unsigned *mask,
271 			  unsigned *bit)
272 {
273 	switch (param) {
274 	case PIN_CONFIG_BIAS_DISABLE:
275 	case PIN_CONFIG_BIAS_PULL_DOWN:
276 	case PIN_CONFIG_BIAS_BUS_HOLD:
277 	case PIN_CONFIG_BIAS_PULL_UP:
278 		*bit = g->pull_bit;
279 		*mask = 3;
280 		break;
281 	case PIN_CONFIG_DRIVE_OPEN_DRAIN:
282 		*bit = g->od_bit;
283 		*mask = 1;
284 		break;
285 	case PIN_CONFIG_DRIVE_STRENGTH:
286 		*bit = g->drv_bit;
287 		*mask = 7;
288 		break;
289 	case PIN_CONFIG_OUTPUT:
290 	case PIN_CONFIG_INPUT_ENABLE:
291 		*bit = g->oe_bit;
292 		*mask = 1;
293 		break;
294 	default:
295 		return -ENOTSUPP;
296 	}
297 
298 	return 0;
299 }
300 
301 #define MSM_NO_PULL		0
302 #define MSM_PULL_DOWN		1
303 #define MSM_KEEPER		2
304 #define MSM_PULL_UP_NO_KEEPER	2
305 #define MSM_PULL_UP		3
306 
307 static unsigned msm_regval_to_drive(u32 val)
308 {
309 	return (val + 1) * 2;
310 }
311 
312 static int msm_config_group_get(struct pinctrl_dev *pctldev,
313 				unsigned int group,
314 				unsigned long *config)
315 {
316 	const struct msm_pingroup *g;
317 	struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
318 	unsigned param = pinconf_to_config_param(*config);
319 	unsigned mask;
320 	unsigned arg;
321 	unsigned bit;
322 	int ret;
323 	u32 val;
324 
325 	g = &pctrl->soc->groups[group];
326 
327 	ret = msm_config_reg(pctrl, g, param, &mask, &bit);
328 	if (ret < 0)
329 		return ret;
330 
331 	val = msm_readl_ctl(pctrl, g);
332 	arg = (val >> bit) & mask;
333 
334 	/* Convert register value to pinconf value */
335 	switch (param) {
336 	case PIN_CONFIG_BIAS_DISABLE:
337 		if (arg != MSM_NO_PULL)
338 			return -EINVAL;
339 		arg = 1;
340 		break;
341 	case PIN_CONFIG_BIAS_PULL_DOWN:
342 		if (arg != MSM_PULL_DOWN)
343 			return -EINVAL;
344 		arg = 1;
345 		break;
346 	case PIN_CONFIG_BIAS_BUS_HOLD:
347 		if (pctrl->soc->pull_no_keeper)
348 			return -ENOTSUPP;
349 
350 		if (arg != MSM_KEEPER)
351 			return -EINVAL;
352 		arg = 1;
353 		break;
354 	case PIN_CONFIG_BIAS_PULL_UP:
355 		if (pctrl->soc->pull_no_keeper)
356 			arg = arg == MSM_PULL_UP_NO_KEEPER;
357 		else
358 			arg = arg == MSM_PULL_UP;
359 		if (!arg)
360 			return -EINVAL;
361 		break;
362 	case PIN_CONFIG_DRIVE_OPEN_DRAIN:
363 		/* Pin is not open-drain */
364 		if (!arg)
365 			return -EINVAL;
366 		arg = 1;
367 		break;
368 	case PIN_CONFIG_DRIVE_STRENGTH:
369 		arg = msm_regval_to_drive(arg);
370 		break;
371 	case PIN_CONFIG_OUTPUT:
372 		/* Pin is not output */
373 		if (!arg)
374 			return -EINVAL;
375 
376 		val = msm_readl_io(pctrl, g);
377 		arg = !!(val & BIT(g->in_bit));
378 		break;
379 	case PIN_CONFIG_INPUT_ENABLE:
380 		/* Pin is output */
381 		if (arg)
382 			return -EINVAL;
383 		arg = 1;
384 		break;
385 	default:
386 		return -ENOTSUPP;
387 	}
388 
389 	*config = pinconf_to_config_packed(param, arg);
390 
391 	return 0;
392 }
393 
394 static int msm_config_group_set(struct pinctrl_dev *pctldev,
395 				unsigned group,
396 				unsigned long *configs,
397 				unsigned num_configs)
398 {
399 	const struct msm_pingroup *g;
400 	struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
401 	unsigned long flags;
402 	unsigned param;
403 	unsigned mask;
404 	unsigned arg;
405 	unsigned bit;
406 	int ret;
407 	u32 val;
408 	int i;
409 
410 	g = &pctrl->soc->groups[group];
411 
412 	for (i = 0; i < num_configs; i++) {
413 		param = pinconf_to_config_param(configs[i]);
414 		arg = pinconf_to_config_argument(configs[i]);
415 
416 		ret = msm_config_reg(pctrl, g, param, &mask, &bit);
417 		if (ret < 0)
418 			return ret;
419 
420 		/* Convert pinconf values to register values */
421 		switch (param) {
422 		case PIN_CONFIG_BIAS_DISABLE:
423 			arg = MSM_NO_PULL;
424 			break;
425 		case PIN_CONFIG_BIAS_PULL_DOWN:
426 			arg = MSM_PULL_DOWN;
427 			break;
428 		case PIN_CONFIG_BIAS_BUS_HOLD:
429 			if (pctrl->soc->pull_no_keeper)
430 				return -ENOTSUPP;
431 
432 			arg = MSM_KEEPER;
433 			break;
434 		case PIN_CONFIG_BIAS_PULL_UP:
435 			if (pctrl->soc->pull_no_keeper)
436 				arg = MSM_PULL_UP_NO_KEEPER;
437 			else
438 				arg = MSM_PULL_UP;
439 			break;
440 		case PIN_CONFIG_DRIVE_OPEN_DRAIN:
441 			arg = 1;
442 			break;
443 		case PIN_CONFIG_DRIVE_STRENGTH:
444 			/* Check for invalid values */
445 			if (arg > 16 || arg < 2 || (arg % 2) != 0)
446 				arg = -1;
447 			else
448 				arg = (arg / 2) - 1;
449 			break;
450 		case PIN_CONFIG_OUTPUT:
451 			/* set output value */
452 			raw_spin_lock_irqsave(&pctrl->lock, flags);
453 			val = msm_readl_io(pctrl, g);
454 			if (arg)
455 				val |= BIT(g->out_bit);
456 			else
457 				val &= ~BIT(g->out_bit);
458 			msm_writel_io(val, pctrl, g);
459 			raw_spin_unlock_irqrestore(&pctrl->lock, flags);
460 
461 			/* enable output */
462 			arg = 1;
463 			break;
464 		case PIN_CONFIG_INPUT_ENABLE:
465 			/* disable output */
466 			arg = 0;
467 			break;
468 		default:
469 			dev_err(pctrl->dev, "Unsupported config parameter: %x\n",
470 				param);
471 			return -EINVAL;
472 		}
473 
474 		/* Range-check user-supplied value */
475 		if (arg & ~mask) {
476 			dev_err(pctrl->dev, "config %x: %x is invalid\n", param, arg);
477 			return -EINVAL;
478 		}
479 
480 		raw_spin_lock_irqsave(&pctrl->lock, flags);
481 		val = msm_readl_ctl(pctrl, g);
482 		val &= ~(mask << bit);
483 		val |= arg << bit;
484 		msm_writel_ctl(val, pctrl, g);
485 		raw_spin_unlock_irqrestore(&pctrl->lock, flags);
486 	}
487 
488 	return 0;
489 }
490 
491 static const struct pinconf_ops msm_pinconf_ops = {
492 	.is_generic		= true,
493 	.pin_config_group_get	= msm_config_group_get,
494 	.pin_config_group_set	= msm_config_group_set,
495 };
496 
497 static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
498 {
499 	const struct msm_pingroup *g;
500 	struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
501 	unsigned long flags;
502 	u32 val;
503 
504 	g = &pctrl->soc->groups[offset];
505 
506 	raw_spin_lock_irqsave(&pctrl->lock, flags);
507 
508 	val = msm_readl_ctl(pctrl, g);
509 	val &= ~BIT(g->oe_bit);
510 	msm_writel_ctl(val, pctrl, g);
511 
512 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
513 
514 	return 0;
515 }
516 
517 static int msm_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value)
518 {
519 	const struct msm_pingroup *g;
520 	struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
521 	unsigned long flags;
522 	u32 val;
523 
524 	g = &pctrl->soc->groups[offset];
525 
526 	raw_spin_lock_irqsave(&pctrl->lock, flags);
527 
528 	val = msm_readl_io(pctrl, g);
529 	if (value)
530 		val |= BIT(g->out_bit);
531 	else
532 		val &= ~BIT(g->out_bit);
533 	msm_writel_io(val, pctrl, g);
534 
535 	val = msm_readl_ctl(pctrl, g);
536 	val |= BIT(g->oe_bit);
537 	msm_writel_ctl(val, pctrl, g);
538 
539 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
540 
541 	return 0;
542 }
543 
544 static int msm_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
545 {
546 	struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
547 	const struct msm_pingroup *g;
548 	u32 val;
549 
550 	g = &pctrl->soc->groups[offset];
551 
552 	val = msm_readl_ctl(pctrl, g);
553 
554 	return val & BIT(g->oe_bit) ? GPIO_LINE_DIRECTION_OUT :
555 				      GPIO_LINE_DIRECTION_IN;
556 }
557 
558 static int msm_gpio_get(struct gpio_chip *chip, unsigned offset)
559 {
560 	const struct msm_pingroup *g;
561 	struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
562 	u32 val;
563 
564 	g = &pctrl->soc->groups[offset];
565 
566 	val = msm_readl_io(pctrl, g);
567 	return !!(val & BIT(g->in_bit));
568 }
569 
570 static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
571 {
572 	const struct msm_pingroup *g;
573 	struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
574 	unsigned long flags;
575 	u32 val;
576 
577 	g = &pctrl->soc->groups[offset];
578 
579 	raw_spin_lock_irqsave(&pctrl->lock, flags);
580 
581 	val = msm_readl_io(pctrl, g);
582 	if (value)
583 		val |= BIT(g->out_bit);
584 	else
585 		val &= ~BIT(g->out_bit);
586 	msm_writel_io(val, pctrl, g);
587 
588 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
589 }
590 
591 #ifdef CONFIG_DEBUG_FS
592 #include <linux/seq_file.h>
593 
594 static void msm_gpio_dbg_show_one(struct seq_file *s,
595 				  struct pinctrl_dev *pctldev,
596 				  struct gpio_chip *chip,
597 				  unsigned offset,
598 				  unsigned gpio)
599 {
600 	const struct msm_pingroup *g;
601 	struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
602 	unsigned func;
603 	int is_out;
604 	int drive;
605 	int pull;
606 	int val;
607 	u32 ctl_reg, io_reg;
608 
609 	static const char * const pulls_keeper[] = {
610 		"no pull",
611 		"pull down",
612 		"keeper",
613 		"pull up"
614 	};
615 
616 	static const char * const pulls_no_keeper[] = {
617 		"no pull",
618 		"pull down",
619 		"pull up",
620 	};
621 
622 	if (!gpiochip_line_is_valid(chip, offset))
623 		return;
624 
625 	g = &pctrl->soc->groups[offset];
626 	ctl_reg = msm_readl_ctl(pctrl, g);
627 	io_reg = msm_readl_io(pctrl, g);
628 
629 	is_out = !!(ctl_reg & BIT(g->oe_bit));
630 	func = (ctl_reg >> g->mux_bit) & 7;
631 	drive = (ctl_reg >> g->drv_bit) & 7;
632 	pull = (ctl_reg >> g->pull_bit) & 3;
633 
634 	if (is_out)
635 		val = !!(io_reg & BIT(g->out_bit));
636 	else
637 		val = !!(io_reg & BIT(g->in_bit));
638 
639 	seq_printf(s, " %-8s: %-3s", g->name, is_out ? "out" : "in");
640 	seq_printf(s, " %-4s func%d", val ? "high" : "low", func);
641 	seq_printf(s, " %dmA", msm_regval_to_drive(drive));
642 	if (pctrl->soc->pull_no_keeper)
643 		seq_printf(s, " %s", pulls_no_keeper[pull]);
644 	else
645 		seq_printf(s, " %s", pulls_keeper[pull]);
646 	seq_puts(s, "\n");
647 }
648 
649 static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
650 {
651 	unsigned gpio = chip->base;
652 	unsigned i;
653 
654 	for (i = 0; i < chip->ngpio; i++, gpio++)
655 		msm_gpio_dbg_show_one(s, NULL, chip, i, gpio);
656 }
657 
658 #else
659 #define msm_gpio_dbg_show NULL
660 #endif
661 
662 static int msm_gpio_init_valid_mask(struct gpio_chip *gc,
663 				    unsigned long *valid_mask,
664 				    unsigned int ngpios)
665 {
666 	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
667 	int ret;
668 	unsigned int len, i;
669 	const int *reserved = pctrl->soc->reserved_gpios;
670 	u16 *tmp;
671 
672 	/* Driver provided reserved list overrides DT and ACPI */
673 	if (reserved) {
674 		bitmap_fill(valid_mask, ngpios);
675 		for (i = 0; reserved[i] >= 0; i++) {
676 			if (i >= ngpios || reserved[i] >= ngpios) {
677 				dev_err(pctrl->dev, "invalid list of reserved GPIOs\n");
678 				return -EINVAL;
679 			}
680 			clear_bit(reserved[i], valid_mask);
681 		}
682 
683 		return 0;
684 	}
685 
686 	/* The number of GPIOs in the ACPI tables */
687 	len = ret = device_property_count_u16(pctrl->dev, "gpios");
688 	if (ret < 0)
689 		return 0;
690 
691 	if (ret > ngpios)
692 		return -EINVAL;
693 
694 	tmp = kmalloc_array(len, sizeof(*tmp), GFP_KERNEL);
695 	if (!tmp)
696 		return -ENOMEM;
697 
698 	ret = device_property_read_u16_array(pctrl->dev, "gpios", tmp, len);
699 	if (ret < 0) {
700 		dev_err(pctrl->dev, "could not read list of GPIOs\n");
701 		goto out;
702 	}
703 
704 	bitmap_zero(valid_mask, ngpios);
705 	for (i = 0; i < len; i++)
706 		set_bit(tmp[i], valid_mask);
707 
708 out:
709 	kfree(tmp);
710 	return ret;
711 }
712 
713 static const struct gpio_chip msm_gpio_template = {
714 	.direction_input  = msm_gpio_direction_input,
715 	.direction_output = msm_gpio_direction_output,
716 	.get_direction    = msm_gpio_get_direction,
717 	.get              = msm_gpio_get,
718 	.set              = msm_gpio_set,
719 	.request          = gpiochip_generic_request,
720 	.free             = gpiochip_generic_free,
721 	.dbg_show         = msm_gpio_dbg_show,
722 };
723 
724 /* For dual-edge interrupts in software, since some hardware has no
725  * such support:
726  *
727  * At appropriate moments, this function may be called to flip the polarity
728  * settings of both-edge irq lines to try and catch the next edge.
729  *
730  * The attempt is considered successful if:
731  * - the status bit goes high, indicating that an edge was caught, or
732  * - the input value of the gpio doesn't change during the attempt.
733  * If the value changes twice during the process, that would cause the first
734  * test to fail but would force the second, as two opposite
735  * transitions would cause a detection no matter the polarity setting.
736  *
737  * The do-loop tries to sledge-hammer closed the timing hole between
738  * the initial value-read and the polarity-write - if the line value changes
739  * during that window, an interrupt is lost, the new polarity setting is
740  * incorrect, and the first success test will fail, causing a retry.
741  *
742  * Algorithm comes from Google's msmgpio driver.
743  */
744 static void msm_gpio_update_dual_edge_pos(struct msm_pinctrl *pctrl,
745 					  const struct msm_pingroup *g,
746 					  struct irq_data *d)
747 {
748 	int loop_limit = 100;
749 	unsigned val, val2, intstat;
750 	unsigned pol;
751 
752 	do {
753 		val = msm_readl_io(pctrl, g) & BIT(g->in_bit);
754 
755 		pol = msm_readl_intr_cfg(pctrl, g);
756 		pol ^= BIT(g->intr_polarity_bit);
757 		msm_writel_intr_cfg(pol, pctrl, g);
758 
759 		val2 = msm_readl_io(pctrl, g) & BIT(g->in_bit);
760 		intstat = msm_readl_intr_status(pctrl, g);
761 		if (intstat || (val == val2))
762 			return;
763 	} while (loop_limit-- > 0);
764 	dev_err(pctrl->dev, "dual-edge irq failed to stabilize, %#08x != %#08x\n",
765 		val, val2);
766 }
767 
768 static void msm_gpio_irq_mask(struct irq_data *d)
769 {
770 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
771 	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
772 	const struct msm_pingroup *g;
773 	unsigned long flags;
774 	u32 val;
775 
776 	if (d->parent_data)
777 		irq_chip_mask_parent(d);
778 
779 	if (test_bit(d->hwirq, pctrl->skip_wake_irqs))
780 		return;
781 
782 	g = &pctrl->soc->groups[d->hwirq];
783 
784 	raw_spin_lock_irqsave(&pctrl->lock, flags);
785 
786 	val = msm_readl_intr_cfg(pctrl, g);
787 	/*
788 	 * There are two bits that control interrupt forwarding to the CPU. The
789 	 * RAW_STATUS_EN bit causes the level or edge sensed on the line to be
790 	 * latched into the interrupt status register when the hardware detects
791 	 * an irq that it's configured for (either edge for edge type or level
792 	 * for level type irq). The 'non-raw' status enable bit causes the
793 	 * hardware to assert the summary interrupt to the CPU if the latched
794 	 * status bit is set. There's a bug though, the edge detection logic
795 	 * seems to have a problem where toggling the RAW_STATUS_EN bit may
796 	 * cause the status bit to latch spuriously when there isn't any edge
797 	 * so we can't touch that bit for edge type irqs and we have to keep
798 	 * the bit set anyway so that edges are latched while the line is masked.
799 	 *
800 	 * To make matters more complicated, leaving the RAW_STATUS_EN bit
801 	 * enabled all the time causes level interrupts to re-latch into the
802 	 * status register because the level is still present on the line after
803 	 * we ack it. We clear the raw status enable bit during mask here and
804 	 * set the bit on unmask so the interrupt can't latch into the hardware
805 	 * while it's masked.
806 	 */
807 	if (irqd_get_trigger_type(d) & IRQ_TYPE_LEVEL_MASK)
808 		val &= ~BIT(g->intr_raw_status_bit);
809 
810 	val &= ~BIT(g->intr_enable_bit);
811 	msm_writel_intr_cfg(val, pctrl, g);
812 
813 	clear_bit(d->hwirq, pctrl->enabled_irqs);
814 
815 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
816 }
817 
818 static void msm_gpio_irq_unmask(struct irq_data *d)
819 {
820 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
821 	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
822 	const struct msm_pingroup *g;
823 	unsigned long flags;
824 	u32 val;
825 
826 	if (d->parent_data)
827 		irq_chip_unmask_parent(d);
828 
829 	if (test_bit(d->hwirq, pctrl->skip_wake_irqs))
830 		return;
831 
832 	g = &pctrl->soc->groups[d->hwirq];
833 
834 	raw_spin_lock_irqsave(&pctrl->lock, flags);
835 
836 	val = msm_readl_intr_cfg(pctrl, g);
837 	val |= BIT(g->intr_raw_status_bit);
838 	val |= BIT(g->intr_enable_bit);
839 	msm_writel_intr_cfg(val, pctrl, g);
840 
841 	set_bit(d->hwirq, pctrl->enabled_irqs);
842 
843 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
844 }
845 
846 static void msm_gpio_irq_enable(struct irq_data *d)
847 {
848 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
849 	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
850 
851 	if (d->parent_data)
852 		irq_chip_enable_parent(d);
853 
854 	if (!test_bit(d->hwirq, pctrl->skip_wake_irqs))
855 		msm_gpio_irq_unmask(d);
856 }
857 
858 static void msm_gpio_irq_disable(struct irq_data *d)
859 {
860 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
861 	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
862 
863 	if (d->parent_data)
864 		irq_chip_disable_parent(d);
865 
866 	if (!test_bit(d->hwirq, pctrl->skip_wake_irqs))
867 		msm_gpio_irq_mask(d);
868 }
869 
870 /**
871  * msm_gpio_update_dual_edge_parent() - Prime next edge for IRQs handled by parent.
872  * @d: The irq dta.
873  *
874  * This is much like msm_gpio_update_dual_edge_pos() but for IRQs that are
875  * normally handled by the parent irqchip.  The logic here is slightly
876  * different due to what's easy to do with our parent, but in principle it's
877  * the same.
878  */
879 static void msm_gpio_update_dual_edge_parent(struct irq_data *d)
880 {
881 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
882 	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
883 	const struct msm_pingroup *g = &pctrl->soc->groups[d->hwirq];
884 	int loop_limit = 100;
885 	unsigned int val;
886 	unsigned int type;
887 
888 	/* Read the value and make a guess about what edge we need to catch */
889 	val = msm_readl_io(pctrl, g) & BIT(g->in_bit);
890 	type = val ? IRQ_TYPE_EDGE_FALLING : IRQ_TYPE_EDGE_RISING;
891 
892 	do {
893 		/* Set the parent to catch the next edge */
894 		irq_chip_set_type_parent(d, type);
895 
896 		/*
897 		 * Possibly the line changed between when we last read "val"
898 		 * (and decided what edge we needed) and when set the edge.
899 		 * If the value didn't change (or changed and then changed
900 		 * back) then we're done.
901 		 */
902 		val = msm_readl_io(pctrl, g) & BIT(g->in_bit);
903 		if (type == IRQ_TYPE_EDGE_RISING) {
904 			if (!val)
905 				return;
906 			type = IRQ_TYPE_EDGE_FALLING;
907 		} else if (type == IRQ_TYPE_EDGE_FALLING) {
908 			if (val)
909 				return;
910 			type = IRQ_TYPE_EDGE_RISING;
911 		}
912 	} while (loop_limit-- > 0);
913 	dev_warn_once(pctrl->dev, "dual-edge irq failed to stabilize\n");
914 }
915 
916 static void msm_gpio_irq_ack(struct irq_data *d)
917 {
918 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
919 	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
920 	const struct msm_pingroup *g;
921 	unsigned long flags;
922 
923 	if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) {
924 		if (test_bit(d->hwirq, pctrl->dual_edge_irqs))
925 			msm_gpio_update_dual_edge_parent(d);
926 		return;
927 	}
928 
929 	g = &pctrl->soc->groups[d->hwirq];
930 
931 	raw_spin_lock_irqsave(&pctrl->lock, flags);
932 
933 	msm_ack_intr_status(pctrl, g);
934 
935 	if (test_bit(d->hwirq, pctrl->dual_edge_irqs))
936 		msm_gpio_update_dual_edge_pos(pctrl, g, d);
937 
938 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
939 }
940 
941 static bool msm_gpio_needs_dual_edge_parent_workaround(struct irq_data *d,
942 						       unsigned int type)
943 {
944 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
945 	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
946 
947 	return type == IRQ_TYPE_EDGE_BOTH &&
948 	       pctrl->soc->wakeirq_dual_edge_errata && d->parent_data &&
949 	       test_bit(d->hwirq, pctrl->skip_wake_irqs);
950 }
951 
952 static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type)
953 {
954 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
955 	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
956 	const struct msm_pingroup *g;
957 	unsigned long flags;
958 	bool was_enabled;
959 	u32 val;
960 
961 	if (msm_gpio_needs_dual_edge_parent_workaround(d, type)) {
962 		set_bit(d->hwirq, pctrl->dual_edge_irqs);
963 		irq_set_handler_locked(d, handle_fasteoi_ack_irq);
964 		msm_gpio_update_dual_edge_parent(d);
965 		return 0;
966 	}
967 
968 	if (d->parent_data)
969 		irq_chip_set_type_parent(d, type);
970 
971 	if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) {
972 		clear_bit(d->hwirq, pctrl->dual_edge_irqs);
973 		irq_set_handler_locked(d, handle_fasteoi_irq);
974 		return 0;
975 	}
976 
977 	g = &pctrl->soc->groups[d->hwirq];
978 
979 	raw_spin_lock_irqsave(&pctrl->lock, flags);
980 
981 	/*
982 	 * For hw without possibility of detecting both edges
983 	 */
984 	if (g->intr_detection_width == 1 && type == IRQ_TYPE_EDGE_BOTH)
985 		set_bit(d->hwirq, pctrl->dual_edge_irqs);
986 	else
987 		clear_bit(d->hwirq, pctrl->dual_edge_irqs);
988 
989 	/* Route interrupts to application cpu.
990 	 * With intr_target_use_scm interrupts are routed to
991 	 * application cpu using scm calls.
992 	 */
993 	if (pctrl->intr_target_use_scm) {
994 		u32 addr = pctrl->phys_base[0] + g->intr_target_reg;
995 		int ret;
996 
997 		qcom_scm_io_readl(addr, &val);
998 
999 		val &= ~(7 << g->intr_target_bit);
1000 		val |= g->intr_target_kpss_val << g->intr_target_bit;
1001 
1002 		ret = qcom_scm_io_writel(addr, val);
1003 		if (ret)
1004 			dev_err(pctrl->dev,
1005 				"Failed routing %lu interrupt to Apps proc",
1006 				d->hwirq);
1007 	} else {
1008 		val = msm_readl_intr_target(pctrl, g);
1009 		val &= ~(7 << g->intr_target_bit);
1010 		val |= g->intr_target_kpss_val << g->intr_target_bit;
1011 		msm_writel_intr_target(val, pctrl, g);
1012 	}
1013 
1014 	/* Update configuration for gpio.
1015 	 * RAW_STATUS_EN is left on for all gpio irqs. Due to the
1016 	 * internal circuitry of TLMM, toggling the RAW_STATUS
1017 	 * could cause the INTR_STATUS to be set for EDGE interrupts.
1018 	 */
1019 	val = msm_readl_intr_cfg(pctrl, g);
1020 	was_enabled = val & BIT(g->intr_raw_status_bit);
1021 	val |= BIT(g->intr_raw_status_bit);
1022 	if (g->intr_detection_width == 2) {
1023 		val &= ~(3 << g->intr_detection_bit);
1024 		val &= ~(1 << g->intr_polarity_bit);
1025 		switch (type) {
1026 		case IRQ_TYPE_EDGE_RISING:
1027 			val |= 1 << g->intr_detection_bit;
1028 			val |= BIT(g->intr_polarity_bit);
1029 			break;
1030 		case IRQ_TYPE_EDGE_FALLING:
1031 			val |= 2 << g->intr_detection_bit;
1032 			val |= BIT(g->intr_polarity_bit);
1033 			break;
1034 		case IRQ_TYPE_EDGE_BOTH:
1035 			val |= 3 << g->intr_detection_bit;
1036 			val |= BIT(g->intr_polarity_bit);
1037 			break;
1038 		case IRQ_TYPE_LEVEL_LOW:
1039 			break;
1040 		case IRQ_TYPE_LEVEL_HIGH:
1041 			val |= BIT(g->intr_polarity_bit);
1042 			break;
1043 		}
1044 	} else if (g->intr_detection_width == 1) {
1045 		val &= ~(1 << g->intr_detection_bit);
1046 		val &= ~(1 << g->intr_polarity_bit);
1047 		switch (type) {
1048 		case IRQ_TYPE_EDGE_RISING:
1049 			val |= BIT(g->intr_detection_bit);
1050 			val |= BIT(g->intr_polarity_bit);
1051 			break;
1052 		case IRQ_TYPE_EDGE_FALLING:
1053 			val |= BIT(g->intr_detection_bit);
1054 			break;
1055 		case IRQ_TYPE_EDGE_BOTH:
1056 			val |= BIT(g->intr_detection_bit);
1057 			val |= BIT(g->intr_polarity_bit);
1058 			break;
1059 		case IRQ_TYPE_LEVEL_LOW:
1060 			break;
1061 		case IRQ_TYPE_LEVEL_HIGH:
1062 			val |= BIT(g->intr_polarity_bit);
1063 			break;
1064 		}
1065 	} else {
1066 		BUG();
1067 	}
1068 	msm_writel_intr_cfg(val, pctrl, g);
1069 
1070 	/*
1071 	 * The first time we set RAW_STATUS_EN it could trigger an interrupt.
1072 	 * Clear the interrupt.  This is safe because we have
1073 	 * IRQCHIP_SET_TYPE_MASKED.
1074 	 */
1075 	if (!was_enabled)
1076 		msm_ack_intr_status(pctrl, g);
1077 
1078 	if (test_bit(d->hwirq, pctrl->dual_edge_irqs))
1079 		msm_gpio_update_dual_edge_pos(pctrl, g, d);
1080 
1081 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
1082 
1083 	if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
1084 		irq_set_handler_locked(d, handle_level_irq);
1085 	else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
1086 		irq_set_handler_locked(d, handle_edge_irq);
1087 
1088 	return 0;
1089 }
1090 
1091 static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
1092 {
1093 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1094 	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
1095 
1096 	/*
1097 	 * While they may not wake up when the TLMM is powered off,
1098 	 * some GPIOs would like to wakeup the system from suspend
1099 	 * when TLMM is powered on. To allow that, enable the GPIO
1100 	 * summary line to be wakeup capable at GIC.
1101 	 */
1102 	if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs))
1103 		return irq_chip_set_wake_parent(d, on);
1104 
1105 	return irq_set_irq_wake(pctrl->irq, on);
1106 }
1107 
1108 static int msm_gpio_irq_reqres(struct irq_data *d)
1109 {
1110 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1111 	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
1112 	int ret;
1113 
1114 	if (!try_module_get(gc->owner))
1115 		return -ENODEV;
1116 
1117 	ret = msm_pinmux_request_gpio(pctrl->pctrl, NULL, d->hwirq);
1118 	if (ret)
1119 		goto out;
1120 	msm_gpio_direction_input(gc, d->hwirq);
1121 
1122 	if (gpiochip_lock_as_irq(gc, d->hwirq)) {
1123 		dev_err(gc->parent,
1124 			"unable to lock HW IRQ %lu for IRQ\n",
1125 			d->hwirq);
1126 		ret = -EINVAL;
1127 		goto out;
1128 	}
1129 
1130 	/*
1131 	 * The disable / clear-enable workaround we do in msm_pinmux_set_mux()
1132 	 * only works if disable is not lazy since we only clear any bogus
1133 	 * interrupt in hardware. Explicitly mark the interrupt as UNLAZY.
1134 	 */
1135 	irq_set_status_flags(d->irq, IRQ_DISABLE_UNLAZY);
1136 
1137 	return 0;
1138 out:
1139 	module_put(gc->owner);
1140 	return ret;
1141 }
1142 
1143 static void msm_gpio_irq_relres(struct irq_data *d)
1144 {
1145 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1146 
1147 	gpiochip_unlock_as_irq(gc, d->hwirq);
1148 	module_put(gc->owner);
1149 }
1150 
1151 static int msm_gpio_irq_set_affinity(struct irq_data *d,
1152 				const struct cpumask *dest, bool force)
1153 {
1154 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1155 	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
1156 
1157 	if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs))
1158 		return irq_chip_set_affinity_parent(d, dest, force);
1159 
1160 	return 0;
1161 }
1162 
1163 static int msm_gpio_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)
1164 {
1165 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1166 	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
1167 
1168 	if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs))
1169 		return irq_chip_set_vcpu_affinity_parent(d, vcpu_info);
1170 
1171 	return 0;
1172 }
1173 
1174 static void msm_gpio_irq_handler(struct irq_desc *desc)
1175 {
1176 	struct gpio_chip *gc = irq_desc_get_handler_data(desc);
1177 	const struct msm_pingroup *g;
1178 	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
1179 	struct irq_chip *chip = irq_desc_get_chip(desc);
1180 	int handled = 0;
1181 	u32 val;
1182 	int i;
1183 
1184 	chained_irq_enter(chip, desc);
1185 
1186 	/*
1187 	 * Each pin has it's own IRQ status register, so use
1188 	 * enabled_irq bitmap to limit the number of reads.
1189 	 */
1190 	for_each_set_bit(i, pctrl->enabled_irqs, pctrl->chip.ngpio) {
1191 		g = &pctrl->soc->groups[i];
1192 		val = msm_readl_intr_status(pctrl, g);
1193 		if (val & BIT(g->intr_status_bit)) {
1194 			generic_handle_domain_irq(gc->irq.domain, i);
1195 			handled++;
1196 		}
1197 	}
1198 
1199 	/* No interrupts were flagged */
1200 	if (handled == 0)
1201 		handle_bad_irq(desc);
1202 
1203 	chained_irq_exit(chip, desc);
1204 }
1205 
1206 static int msm_gpio_wakeirq(struct gpio_chip *gc,
1207 			    unsigned int child,
1208 			    unsigned int child_type,
1209 			    unsigned int *parent,
1210 			    unsigned int *parent_type)
1211 {
1212 	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
1213 	const struct msm_gpio_wakeirq_map *map;
1214 	int i;
1215 
1216 	*parent = GPIO_NO_WAKE_IRQ;
1217 	*parent_type = IRQ_TYPE_EDGE_RISING;
1218 
1219 	for (i = 0; i < pctrl->soc->nwakeirq_map; i++) {
1220 		map = &pctrl->soc->wakeirq_map[i];
1221 		if (map->gpio == child) {
1222 			*parent = map->wakeirq;
1223 			break;
1224 		}
1225 	}
1226 
1227 	return 0;
1228 }
1229 
1230 static bool msm_gpio_needs_valid_mask(struct msm_pinctrl *pctrl)
1231 {
1232 	if (pctrl->soc->reserved_gpios)
1233 		return true;
1234 
1235 	return device_property_count_u16(pctrl->dev, "gpios") > 0;
1236 }
1237 
1238 static int msm_gpio_init(struct msm_pinctrl *pctrl)
1239 {
1240 	struct gpio_chip *chip;
1241 	struct gpio_irq_chip *girq;
1242 	int i, ret;
1243 	unsigned gpio, ngpio = pctrl->soc->ngpios;
1244 	struct device_node *np;
1245 	bool skip;
1246 
1247 	if (WARN_ON(ngpio > MAX_NR_GPIO))
1248 		return -EINVAL;
1249 
1250 	chip = &pctrl->chip;
1251 	chip->base = -1;
1252 	chip->ngpio = ngpio;
1253 	chip->label = dev_name(pctrl->dev);
1254 	chip->parent = pctrl->dev;
1255 	chip->owner = THIS_MODULE;
1256 	chip->of_node = pctrl->dev->of_node;
1257 	if (msm_gpio_needs_valid_mask(pctrl))
1258 		chip->init_valid_mask = msm_gpio_init_valid_mask;
1259 
1260 	pctrl->irq_chip.name = "msmgpio";
1261 	pctrl->irq_chip.irq_enable = msm_gpio_irq_enable;
1262 	pctrl->irq_chip.irq_disable = msm_gpio_irq_disable;
1263 	pctrl->irq_chip.irq_mask = msm_gpio_irq_mask;
1264 	pctrl->irq_chip.irq_unmask = msm_gpio_irq_unmask;
1265 	pctrl->irq_chip.irq_ack = msm_gpio_irq_ack;
1266 	pctrl->irq_chip.irq_set_type = msm_gpio_irq_set_type;
1267 	pctrl->irq_chip.irq_set_wake = msm_gpio_irq_set_wake;
1268 	pctrl->irq_chip.irq_request_resources = msm_gpio_irq_reqres;
1269 	pctrl->irq_chip.irq_release_resources = msm_gpio_irq_relres;
1270 	pctrl->irq_chip.irq_set_affinity = msm_gpio_irq_set_affinity;
1271 	pctrl->irq_chip.irq_set_vcpu_affinity = msm_gpio_irq_set_vcpu_affinity;
1272 	pctrl->irq_chip.flags = IRQCHIP_MASK_ON_SUSPEND |
1273 				IRQCHIP_SET_TYPE_MASKED |
1274 				IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND;
1275 
1276 	np = of_parse_phandle(pctrl->dev->of_node, "wakeup-parent", 0);
1277 	if (np) {
1278 		chip->irq.parent_domain = irq_find_matching_host(np,
1279 						 DOMAIN_BUS_WAKEUP);
1280 		of_node_put(np);
1281 		if (!chip->irq.parent_domain)
1282 			return -EPROBE_DEFER;
1283 		chip->irq.child_to_parent_hwirq = msm_gpio_wakeirq;
1284 		pctrl->irq_chip.irq_eoi = irq_chip_eoi_parent;
1285 		/*
1286 		 * Let's skip handling the GPIOs, if the parent irqchip
1287 		 * is handling the direct connect IRQ of the GPIO.
1288 		 */
1289 		skip = irq_domain_qcom_handle_wakeup(chip->irq.parent_domain);
1290 		for (i = 0; skip && i < pctrl->soc->nwakeirq_map; i++) {
1291 			gpio = pctrl->soc->wakeirq_map[i].gpio;
1292 			set_bit(gpio, pctrl->skip_wake_irqs);
1293 		}
1294 	}
1295 
1296 	girq = &chip->irq;
1297 	girq->chip = &pctrl->irq_chip;
1298 	girq->parent_handler = msm_gpio_irq_handler;
1299 	girq->fwnode = pctrl->dev->fwnode;
1300 	girq->num_parents = 1;
1301 	girq->parents = devm_kcalloc(pctrl->dev, 1, sizeof(*girq->parents),
1302 				     GFP_KERNEL);
1303 	if (!girq->parents)
1304 		return -ENOMEM;
1305 	girq->default_type = IRQ_TYPE_NONE;
1306 	girq->handler = handle_bad_irq;
1307 	girq->parents[0] = pctrl->irq;
1308 
1309 	ret = gpiochip_add_data(&pctrl->chip, pctrl);
1310 	if (ret) {
1311 		dev_err(pctrl->dev, "Failed register gpiochip\n");
1312 		return ret;
1313 	}
1314 
1315 	/*
1316 	 * For DeviceTree-supported systems, the gpio core checks the
1317 	 * pinctrl's device node for the "gpio-ranges" property.
1318 	 * If it is present, it takes care of adding the pin ranges
1319 	 * for the driver. In this case the driver can skip ahead.
1320 	 *
1321 	 * In order to remain compatible with older, existing DeviceTree
1322 	 * files which don't set the "gpio-ranges" property or systems that
1323 	 * utilize ACPI the driver has to call gpiochip_add_pin_range().
1324 	 */
1325 	if (!of_property_read_bool(pctrl->dev->of_node, "gpio-ranges")) {
1326 		ret = gpiochip_add_pin_range(&pctrl->chip,
1327 			dev_name(pctrl->dev), 0, 0, chip->ngpio);
1328 		if (ret) {
1329 			dev_err(pctrl->dev, "Failed to add pin range\n");
1330 			gpiochip_remove(&pctrl->chip);
1331 			return ret;
1332 		}
1333 	}
1334 
1335 	return 0;
1336 }
1337 
1338 static int msm_ps_hold_restart(struct notifier_block *nb, unsigned long action,
1339 			       void *data)
1340 {
1341 	struct msm_pinctrl *pctrl = container_of(nb, struct msm_pinctrl, restart_nb);
1342 
1343 	writel(0, pctrl->regs[0] + PS_HOLD_OFFSET);
1344 	mdelay(1000);
1345 	return NOTIFY_DONE;
1346 }
1347 
1348 static struct msm_pinctrl *poweroff_pctrl;
1349 
1350 static void msm_ps_hold_poweroff(void)
1351 {
1352 	msm_ps_hold_restart(&poweroff_pctrl->restart_nb, 0, NULL);
1353 }
1354 
1355 static void msm_pinctrl_setup_pm_reset(struct msm_pinctrl *pctrl)
1356 {
1357 	int i;
1358 	const struct msm_function *func = pctrl->soc->functions;
1359 
1360 	for (i = 0; i < pctrl->soc->nfunctions; i++)
1361 		if (!strcmp(func[i].name, "ps_hold")) {
1362 			pctrl->restart_nb.notifier_call = msm_ps_hold_restart;
1363 			pctrl->restart_nb.priority = 128;
1364 			if (register_restart_handler(&pctrl->restart_nb))
1365 				dev_err(pctrl->dev,
1366 					"failed to setup restart handler.\n");
1367 			poweroff_pctrl = pctrl;
1368 			pm_power_off = msm_ps_hold_poweroff;
1369 			break;
1370 		}
1371 }
1372 
1373 static __maybe_unused int msm_pinctrl_suspend(struct device *dev)
1374 {
1375 	struct msm_pinctrl *pctrl = dev_get_drvdata(dev);
1376 
1377 	return pinctrl_force_sleep(pctrl->pctrl);
1378 }
1379 
1380 static __maybe_unused int msm_pinctrl_resume(struct device *dev)
1381 {
1382 	struct msm_pinctrl *pctrl = dev_get_drvdata(dev);
1383 
1384 	return pinctrl_force_default(pctrl->pctrl);
1385 }
1386 
1387 SIMPLE_DEV_PM_OPS(msm_pinctrl_dev_pm_ops, msm_pinctrl_suspend,
1388 		  msm_pinctrl_resume);
1389 
1390 EXPORT_SYMBOL(msm_pinctrl_dev_pm_ops);
1391 
1392 int msm_pinctrl_probe(struct platform_device *pdev,
1393 		      const struct msm_pinctrl_soc_data *soc_data)
1394 {
1395 	struct msm_pinctrl *pctrl;
1396 	struct resource *res;
1397 	int ret;
1398 	int i;
1399 
1400 	pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
1401 	if (!pctrl)
1402 		return -ENOMEM;
1403 
1404 	pctrl->dev = &pdev->dev;
1405 	pctrl->soc = soc_data;
1406 	pctrl->chip = msm_gpio_template;
1407 	pctrl->intr_target_use_scm = of_device_is_compatible(
1408 					pctrl->dev->of_node,
1409 					"qcom,ipq8064-pinctrl");
1410 
1411 	raw_spin_lock_init(&pctrl->lock);
1412 
1413 	if (soc_data->tiles) {
1414 		for (i = 0; i < soc_data->ntiles; i++) {
1415 			res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1416 							   soc_data->tiles[i]);
1417 			pctrl->regs[i] = devm_ioremap_resource(&pdev->dev, res);
1418 			if (IS_ERR(pctrl->regs[i]))
1419 				return PTR_ERR(pctrl->regs[i]);
1420 		}
1421 	} else {
1422 		res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1423 		pctrl->regs[0] = devm_ioremap_resource(&pdev->dev, res);
1424 		if (IS_ERR(pctrl->regs[0]))
1425 			return PTR_ERR(pctrl->regs[0]);
1426 
1427 		pctrl->phys_base[0] = res->start;
1428 	}
1429 
1430 	msm_pinctrl_setup_pm_reset(pctrl);
1431 
1432 	pctrl->irq = platform_get_irq(pdev, 0);
1433 	if (pctrl->irq < 0)
1434 		return pctrl->irq;
1435 
1436 	pctrl->desc.owner = THIS_MODULE;
1437 	pctrl->desc.pctlops = &msm_pinctrl_ops;
1438 	pctrl->desc.pmxops = &msm_pinmux_ops;
1439 	pctrl->desc.confops = &msm_pinconf_ops;
1440 	pctrl->desc.name = dev_name(&pdev->dev);
1441 	pctrl->desc.pins = pctrl->soc->pins;
1442 	pctrl->desc.npins = pctrl->soc->npins;
1443 
1444 	pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &pctrl->desc, pctrl);
1445 	if (IS_ERR(pctrl->pctrl)) {
1446 		dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
1447 		return PTR_ERR(pctrl->pctrl);
1448 	}
1449 
1450 	ret = msm_gpio_init(pctrl);
1451 	if (ret)
1452 		return ret;
1453 
1454 	platform_set_drvdata(pdev, pctrl);
1455 
1456 	dev_dbg(&pdev->dev, "Probed Qualcomm pinctrl driver\n");
1457 
1458 	return 0;
1459 }
1460 EXPORT_SYMBOL(msm_pinctrl_probe);
1461 
1462 int msm_pinctrl_remove(struct platform_device *pdev)
1463 {
1464 	struct msm_pinctrl *pctrl = platform_get_drvdata(pdev);
1465 
1466 	gpiochip_remove(&pctrl->chip);
1467 
1468 	unregister_restart_handler(&pctrl->restart_nb);
1469 
1470 	return 0;
1471 }
1472 EXPORT_SYMBOL(msm_pinctrl_remove);
1473 
1474 MODULE_DESCRIPTION("Qualcomm Technologies, Inc. TLMM driver");
1475 MODULE_LICENSE("GPL v2");
1476