1 /* 2 * Copyright (c) 2013, Sony Mobile Communications AB. 3 * Copyright (c) 2013, The Linux Foundation. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 and 7 * only version 2 as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 */ 14 15 #include <linux/delay.h> 16 #include <linux/err.h> 17 #include <linux/io.h> 18 #include <linux/module.h> 19 #include <linux/of.h> 20 #include <linux/platform_device.h> 21 #include <linux/pinctrl/machine.h> 22 #include <linux/pinctrl/pinctrl.h> 23 #include <linux/pinctrl/pinmux.h> 24 #include <linux/pinctrl/pinconf.h> 25 #include <linux/pinctrl/pinconf-generic.h> 26 #include <linux/slab.h> 27 #include <linux/gpio.h> 28 #include <linux/interrupt.h> 29 #include <linux/spinlock.h> 30 #include <linux/reboot.h> 31 #include <linux/pm.h> 32 #include <linux/log2.h> 33 34 #include "../core.h" 35 #include "../pinconf.h" 36 #include "pinctrl-msm.h" 37 #include "../pinctrl-utils.h" 38 39 #define MAX_NR_GPIO 300 40 #define PS_HOLD_OFFSET 0x820 41 42 /** 43 * struct msm_pinctrl - state for a pinctrl-msm device 44 * @dev: device handle. 45 * @pctrl: pinctrl handle. 46 * @chip: gpiochip handle. 47 * @restart_nb: restart notifier block. 48 * @irq: parent irq for the TLMM irq_chip. 49 * @lock: Spinlock to protect register resources as well 50 * as msm_pinctrl data structures. 51 * @enabled_irqs: Bitmap of currently enabled irqs. 52 * @dual_edge_irqs: Bitmap of irqs that need sw emulated dual edge 53 * detection. 54 * @soc; Reference to soc_data of platform specific data. 55 * @regs: Base address for the TLMM register map. 56 */ 57 struct msm_pinctrl { 58 struct device *dev; 59 struct pinctrl_dev *pctrl; 60 struct gpio_chip chip; 61 struct pinctrl_desc desc; 62 struct notifier_block restart_nb; 63 64 struct irq_chip irq_chip; 65 int irq; 66 67 raw_spinlock_t lock; 68 69 DECLARE_BITMAP(dual_edge_irqs, MAX_NR_GPIO); 70 DECLARE_BITMAP(enabled_irqs, MAX_NR_GPIO); 71 72 const struct msm_pinctrl_soc_data *soc; 73 void __iomem *regs; 74 }; 75 76 static int msm_get_groups_count(struct pinctrl_dev *pctldev) 77 { 78 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 79 80 return pctrl->soc->ngroups; 81 } 82 83 static const char *msm_get_group_name(struct pinctrl_dev *pctldev, 84 unsigned group) 85 { 86 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 87 88 return pctrl->soc->groups[group].name; 89 } 90 91 static int msm_get_group_pins(struct pinctrl_dev *pctldev, 92 unsigned group, 93 const unsigned **pins, 94 unsigned *num_pins) 95 { 96 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 97 98 *pins = pctrl->soc->groups[group].pins; 99 *num_pins = pctrl->soc->groups[group].npins; 100 return 0; 101 } 102 103 static const struct pinctrl_ops msm_pinctrl_ops = { 104 .get_groups_count = msm_get_groups_count, 105 .get_group_name = msm_get_group_name, 106 .get_group_pins = msm_get_group_pins, 107 .dt_node_to_map = pinconf_generic_dt_node_to_map_group, 108 .dt_free_map = pinctrl_utils_free_map, 109 }; 110 111 static int msm_pinmux_request(struct pinctrl_dev *pctldev, unsigned offset) 112 { 113 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 114 struct gpio_chip *chip = &pctrl->chip; 115 116 return gpiochip_line_is_valid(chip, offset) ? 0 : -EINVAL; 117 } 118 119 static int msm_get_functions_count(struct pinctrl_dev *pctldev) 120 { 121 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 122 123 return pctrl->soc->nfunctions; 124 } 125 126 static const char *msm_get_function_name(struct pinctrl_dev *pctldev, 127 unsigned function) 128 { 129 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 130 131 return pctrl->soc->functions[function].name; 132 } 133 134 static int msm_get_function_groups(struct pinctrl_dev *pctldev, 135 unsigned function, 136 const char * const **groups, 137 unsigned * const num_groups) 138 { 139 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 140 141 *groups = pctrl->soc->functions[function].groups; 142 *num_groups = pctrl->soc->functions[function].ngroups; 143 return 0; 144 } 145 146 static int msm_pinmux_set_mux(struct pinctrl_dev *pctldev, 147 unsigned function, 148 unsigned group) 149 { 150 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 151 const struct msm_pingroup *g; 152 unsigned long flags; 153 u32 val, mask; 154 int i; 155 156 g = &pctrl->soc->groups[group]; 157 mask = GENMASK(g->mux_bit + order_base_2(g->nfuncs) - 1, g->mux_bit); 158 159 for (i = 0; i < g->nfuncs; i++) { 160 if (g->funcs[i] == function) 161 break; 162 } 163 164 if (WARN_ON(i == g->nfuncs)) 165 return -EINVAL; 166 167 raw_spin_lock_irqsave(&pctrl->lock, flags); 168 169 val = readl(pctrl->regs + g->ctl_reg); 170 val &= ~mask; 171 val |= i << g->mux_bit; 172 writel(val, pctrl->regs + g->ctl_reg); 173 174 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 175 176 return 0; 177 } 178 179 static const struct pinmux_ops msm_pinmux_ops = { 180 .request = msm_pinmux_request, 181 .get_functions_count = msm_get_functions_count, 182 .get_function_name = msm_get_function_name, 183 .get_function_groups = msm_get_function_groups, 184 .set_mux = msm_pinmux_set_mux, 185 }; 186 187 static int msm_config_reg(struct msm_pinctrl *pctrl, 188 const struct msm_pingroup *g, 189 unsigned param, 190 unsigned *mask, 191 unsigned *bit) 192 { 193 switch (param) { 194 case PIN_CONFIG_BIAS_DISABLE: 195 case PIN_CONFIG_BIAS_PULL_DOWN: 196 case PIN_CONFIG_BIAS_BUS_HOLD: 197 case PIN_CONFIG_BIAS_PULL_UP: 198 *bit = g->pull_bit; 199 *mask = 3; 200 break; 201 case PIN_CONFIG_DRIVE_STRENGTH: 202 *bit = g->drv_bit; 203 *mask = 7; 204 break; 205 case PIN_CONFIG_OUTPUT: 206 case PIN_CONFIG_INPUT_ENABLE: 207 *bit = g->oe_bit; 208 *mask = 1; 209 break; 210 default: 211 return -ENOTSUPP; 212 } 213 214 return 0; 215 } 216 217 #define MSM_NO_PULL 0 218 #define MSM_PULL_DOWN 1 219 #define MSM_KEEPER 2 220 #define MSM_PULL_UP_NO_KEEPER 2 221 #define MSM_PULL_UP 3 222 223 static unsigned msm_regval_to_drive(u32 val) 224 { 225 return (val + 1) * 2; 226 } 227 228 static int msm_config_group_get(struct pinctrl_dev *pctldev, 229 unsigned int group, 230 unsigned long *config) 231 { 232 const struct msm_pingroup *g; 233 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 234 unsigned param = pinconf_to_config_param(*config); 235 unsigned mask; 236 unsigned arg; 237 unsigned bit; 238 int ret; 239 u32 val; 240 241 g = &pctrl->soc->groups[group]; 242 243 ret = msm_config_reg(pctrl, g, param, &mask, &bit); 244 if (ret < 0) 245 return ret; 246 247 val = readl(pctrl->regs + g->ctl_reg); 248 arg = (val >> bit) & mask; 249 250 /* Convert register value to pinconf value */ 251 switch (param) { 252 case PIN_CONFIG_BIAS_DISABLE: 253 arg = arg == MSM_NO_PULL; 254 break; 255 case PIN_CONFIG_BIAS_PULL_DOWN: 256 arg = arg == MSM_PULL_DOWN; 257 break; 258 case PIN_CONFIG_BIAS_BUS_HOLD: 259 if (pctrl->soc->pull_no_keeper) 260 return -ENOTSUPP; 261 262 arg = arg == MSM_KEEPER; 263 break; 264 case PIN_CONFIG_BIAS_PULL_UP: 265 if (pctrl->soc->pull_no_keeper) 266 arg = arg == MSM_PULL_UP_NO_KEEPER; 267 else 268 arg = arg == MSM_PULL_UP; 269 break; 270 case PIN_CONFIG_DRIVE_STRENGTH: 271 arg = msm_regval_to_drive(arg); 272 break; 273 case PIN_CONFIG_OUTPUT: 274 /* Pin is not output */ 275 if (!arg) 276 return -EINVAL; 277 278 val = readl(pctrl->regs + g->io_reg); 279 arg = !!(val & BIT(g->in_bit)); 280 break; 281 case PIN_CONFIG_INPUT_ENABLE: 282 /* Pin is output */ 283 if (arg) 284 return -EINVAL; 285 arg = 1; 286 break; 287 default: 288 return -ENOTSUPP; 289 } 290 291 *config = pinconf_to_config_packed(param, arg); 292 293 return 0; 294 } 295 296 static int msm_config_group_set(struct pinctrl_dev *pctldev, 297 unsigned group, 298 unsigned long *configs, 299 unsigned num_configs) 300 { 301 const struct msm_pingroup *g; 302 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 303 unsigned long flags; 304 unsigned param; 305 unsigned mask; 306 unsigned arg; 307 unsigned bit; 308 int ret; 309 u32 val; 310 int i; 311 312 g = &pctrl->soc->groups[group]; 313 314 for (i = 0; i < num_configs; i++) { 315 param = pinconf_to_config_param(configs[i]); 316 arg = pinconf_to_config_argument(configs[i]); 317 318 ret = msm_config_reg(pctrl, g, param, &mask, &bit); 319 if (ret < 0) 320 return ret; 321 322 /* Convert pinconf values to register values */ 323 switch (param) { 324 case PIN_CONFIG_BIAS_DISABLE: 325 arg = MSM_NO_PULL; 326 break; 327 case PIN_CONFIG_BIAS_PULL_DOWN: 328 arg = MSM_PULL_DOWN; 329 break; 330 case PIN_CONFIG_BIAS_BUS_HOLD: 331 if (pctrl->soc->pull_no_keeper) 332 return -ENOTSUPP; 333 334 arg = MSM_KEEPER; 335 break; 336 case PIN_CONFIG_BIAS_PULL_UP: 337 if (pctrl->soc->pull_no_keeper) 338 arg = MSM_PULL_UP_NO_KEEPER; 339 else 340 arg = MSM_PULL_UP; 341 break; 342 case PIN_CONFIG_DRIVE_STRENGTH: 343 /* Check for invalid values */ 344 if (arg > 16 || arg < 2 || (arg % 2) != 0) 345 arg = -1; 346 else 347 arg = (arg / 2) - 1; 348 break; 349 case PIN_CONFIG_OUTPUT: 350 /* set output value */ 351 raw_spin_lock_irqsave(&pctrl->lock, flags); 352 val = readl(pctrl->regs + g->io_reg); 353 if (arg) 354 val |= BIT(g->out_bit); 355 else 356 val &= ~BIT(g->out_bit); 357 writel(val, pctrl->regs + g->io_reg); 358 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 359 360 /* enable output */ 361 arg = 1; 362 break; 363 case PIN_CONFIG_INPUT_ENABLE: 364 /* disable output */ 365 arg = 0; 366 break; 367 default: 368 dev_err(pctrl->dev, "Unsupported config parameter: %x\n", 369 param); 370 return -EINVAL; 371 } 372 373 /* Range-check user-supplied value */ 374 if (arg & ~mask) { 375 dev_err(pctrl->dev, "config %x: %x is invalid\n", param, arg); 376 return -EINVAL; 377 } 378 379 raw_spin_lock_irqsave(&pctrl->lock, flags); 380 val = readl(pctrl->regs + g->ctl_reg); 381 val &= ~(mask << bit); 382 val |= arg << bit; 383 writel(val, pctrl->regs + g->ctl_reg); 384 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 385 } 386 387 return 0; 388 } 389 390 static const struct pinconf_ops msm_pinconf_ops = { 391 .is_generic = true, 392 .pin_config_group_get = msm_config_group_get, 393 .pin_config_group_set = msm_config_group_set, 394 }; 395 396 static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 397 { 398 const struct msm_pingroup *g; 399 struct msm_pinctrl *pctrl = gpiochip_get_data(chip); 400 unsigned long flags; 401 u32 val; 402 403 g = &pctrl->soc->groups[offset]; 404 405 raw_spin_lock_irqsave(&pctrl->lock, flags); 406 407 val = readl(pctrl->regs + g->ctl_reg); 408 val &= ~BIT(g->oe_bit); 409 writel(val, pctrl->regs + g->ctl_reg); 410 411 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 412 413 return 0; 414 } 415 416 static int msm_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value) 417 { 418 const struct msm_pingroup *g; 419 struct msm_pinctrl *pctrl = gpiochip_get_data(chip); 420 unsigned long flags; 421 u32 val; 422 423 g = &pctrl->soc->groups[offset]; 424 425 raw_spin_lock_irqsave(&pctrl->lock, flags); 426 427 val = readl(pctrl->regs + g->io_reg); 428 if (value) 429 val |= BIT(g->out_bit); 430 else 431 val &= ~BIT(g->out_bit); 432 writel(val, pctrl->regs + g->io_reg); 433 434 val = readl(pctrl->regs + g->ctl_reg); 435 val |= BIT(g->oe_bit); 436 writel(val, pctrl->regs + g->ctl_reg); 437 438 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 439 440 return 0; 441 } 442 443 static int msm_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 444 { 445 struct msm_pinctrl *pctrl = gpiochip_get_data(chip); 446 const struct msm_pingroup *g; 447 u32 val; 448 449 g = &pctrl->soc->groups[offset]; 450 451 val = readl(pctrl->regs + g->ctl_reg); 452 453 /* 0 = output, 1 = input */ 454 return val & BIT(g->oe_bit) ? 0 : 1; 455 } 456 457 static int msm_gpio_get(struct gpio_chip *chip, unsigned offset) 458 { 459 const struct msm_pingroup *g; 460 struct msm_pinctrl *pctrl = gpiochip_get_data(chip); 461 u32 val; 462 463 g = &pctrl->soc->groups[offset]; 464 465 val = readl(pctrl->regs + g->io_reg); 466 return !!(val & BIT(g->in_bit)); 467 } 468 469 static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 470 { 471 const struct msm_pingroup *g; 472 struct msm_pinctrl *pctrl = gpiochip_get_data(chip); 473 unsigned long flags; 474 u32 val; 475 476 g = &pctrl->soc->groups[offset]; 477 478 raw_spin_lock_irqsave(&pctrl->lock, flags); 479 480 val = readl(pctrl->regs + g->io_reg); 481 if (value) 482 val |= BIT(g->out_bit); 483 else 484 val &= ~BIT(g->out_bit); 485 writel(val, pctrl->regs + g->io_reg); 486 487 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 488 } 489 490 #ifdef CONFIG_DEBUG_FS 491 #include <linux/seq_file.h> 492 493 static void msm_gpio_dbg_show_one(struct seq_file *s, 494 struct pinctrl_dev *pctldev, 495 struct gpio_chip *chip, 496 unsigned offset, 497 unsigned gpio) 498 { 499 const struct msm_pingroup *g; 500 struct msm_pinctrl *pctrl = gpiochip_get_data(chip); 501 unsigned func; 502 int is_out; 503 int drive; 504 int pull; 505 int val; 506 u32 ctl_reg, io_reg; 507 508 static const char * const pulls_keeper[] = { 509 "no pull", 510 "pull down", 511 "keeper", 512 "pull up" 513 }; 514 515 static const char * const pulls_no_keeper[] = { 516 "no pull", 517 "pull down", 518 "pull up", 519 }; 520 521 if (!gpiochip_line_is_valid(chip, offset)) 522 return; 523 524 g = &pctrl->soc->groups[offset]; 525 ctl_reg = readl(pctrl->regs + g->ctl_reg); 526 io_reg = readl(pctrl->regs + g->io_reg); 527 528 is_out = !!(ctl_reg & BIT(g->oe_bit)); 529 func = (ctl_reg >> g->mux_bit) & 7; 530 drive = (ctl_reg >> g->drv_bit) & 7; 531 pull = (ctl_reg >> g->pull_bit) & 3; 532 533 if (is_out) 534 val = !!(io_reg & BIT(g->out_bit)); 535 else 536 val = !!(io_reg & BIT(g->in_bit)); 537 538 seq_printf(s, " %-8s: %-3s", g->name, is_out ? "out" : "in"); 539 seq_printf(s, " %-4s func%d", val ? "high" : "low", func); 540 seq_printf(s, " %dmA", msm_regval_to_drive(drive)); 541 if (pctrl->soc->pull_no_keeper) 542 seq_printf(s, " %s", pulls_no_keeper[pull]); 543 else 544 seq_printf(s, " %s", pulls_keeper[pull]); 545 seq_puts(s, "\n"); 546 } 547 548 static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) 549 { 550 unsigned gpio = chip->base; 551 unsigned i; 552 553 for (i = 0; i < chip->ngpio; i++, gpio++) 554 msm_gpio_dbg_show_one(s, NULL, chip, i, gpio); 555 } 556 557 #else 558 #define msm_gpio_dbg_show NULL 559 #endif 560 561 static const struct gpio_chip msm_gpio_template = { 562 .direction_input = msm_gpio_direction_input, 563 .direction_output = msm_gpio_direction_output, 564 .get_direction = msm_gpio_get_direction, 565 .get = msm_gpio_get, 566 .set = msm_gpio_set, 567 .request = gpiochip_generic_request, 568 .free = gpiochip_generic_free, 569 .dbg_show = msm_gpio_dbg_show, 570 }; 571 572 /* For dual-edge interrupts in software, since some hardware has no 573 * such support: 574 * 575 * At appropriate moments, this function may be called to flip the polarity 576 * settings of both-edge irq lines to try and catch the next edge. 577 * 578 * The attempt is considered successful if: 579 * - the status bit goes high, indicating that an edge was caught, or 580 * - the input value of the gpio doesn't change during the attempt. 581 * If the value changes twice during the process, that would cause the first 582 * test to fail but would force the second, as two opposite 583 * transitions would cause a detection no matter the polarity setting. 584 * 585 * The do-loop tries to sledge-hammer closed the timing hole between 586 * the initial value-read and the polarity-write - if the line value changes 587 * during that window, an interrupt is lost, the new polarity setting is 588 * incorrect, and the first success test will fail, causing a retry. 589 * 590 * Algorithm comes from Google's msmgpio driver. 591 */ 592 static void msm_gpio_update_dual_edge_pos(struct msm_pinctrl *pctrl, 593 const struct msm_pingroup *g, 594 struct irq_data *d) 595 { 596 int loop_limit = 100; 597 unsigned val, val2, intstat; 598 unsigned pol; 599 600 do { 601 val = readl(pctrl->regs + g->io_reg) & BIT(g->in_bit); 602 603 pol = readl(pctrl->regs + g->intr_cfg_reg); 604 pol ^= BIT(g->intr_polarity_bit); 605 writel(pol, pctrl->regs + g->intr_cfg_reg); 606 607 val2 = readl(pctrl->regs + g->io_reg) & BIT(g->in_bit); 608 intstat = readl(pctrl->regs + g->intr_status_reg); 609 if (intstat || (val == val2)) 610 return; 611 } while (loop_limit-- > 0); 612 dev_err(pctrl->dev, "dual-edge irq failed to stabilize, %#08x != %#08x\n", 613 val, val2); 614 } 615 616 static void msm_gpio_irq_mask(struct irq_data *d) 617 { 618 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 619 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); 620 const struct msm_pingroup *g; 621 unsigned long flags; 622 u32 val; 623 624 g = &pctrl->soc->groups[d->hwirq]; 625 626 raw_spin_lock_irqsave(&pctrl->lock, flags); 627 628 val = readl(pctrl->regs + g->intr_cfg_reg); 629 val &= ~BIT(g->intr_enable_bit); 630 writel(val, pctrl->regs + g->intr_cfg_reg); 631 632 clear_bit(d->hwirq, pctrl->enabled_irqs); 633 634 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 635 } 636 637 static void msm_gpio_irq_unmask(struct irq_data *d) 638 { 639 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 640 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); 641 const struct msm_pingroup *g; 642 unsigned long flags; 643 u32 val; 644 645 g = &pctrl->soc->groups[d->hwirq]; 646 647 raw_spin_lock_irqsave(&pctrl->lock, flags); 648 649 val = readl(pctrl->regs + g->intr_cfg_reg); 650 val |= BIT(g->intr_enable_bit); 651 writel(val, pctrl->regs + g->intr_cfg_reg); 652 653 set_bit(d->hwirq, pctrl->enabled_irqs); 654 655 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 656 } 657 658 static void msm_gpio_irq_ack(struct irq_data *d) 659 { 660 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 661 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); 662 const struct msm_pingroup *g; 663 unsigned long flags; 664 u32 val; 665 666 g = &pctrl->soc->groups[d->hwirq]; 667 668 raw_spin_lock_irqsave(&pctrl->lock, flags); 669 670 val = readl(pctrl->regs + g->intr_status_reg); 671 if (g->intr_ack_high) 672 val |= BIT(g->intr_status_bit); 673 else 674 val &= ~BIT(g->intr_status_bit); 675 writel(val, pctrl->regs + g->intr_status_reg); 676 677 if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) 678 msm_gpio_update_dual_edge_pos(pctrl, g, d); 679 680 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 681 } 682 683 static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type) 684 { 685 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 686 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); 687 const struct msm_pingroup *g; 688 unsigned long flags; 689 u32 val; 690 691 g = &pctrl->soc->groups[d->hwirq]; 692 693 raw_spin_lock_irqsave(&pctrl->lock, flags); 694 695 /* 696 * For hw without possibility of detecting both edges 697 */ 698 if (g->intr_detection_width == 1 && type == IRQ_TYPE_EDGE_BOTH) 699 set_bit(d->hwirq, pctrl->dual_edge_irqs); 700 else 701 clear_bit(d->hwirq, pctrl->dual_edge_irqs); 702 703 /* Route interrupts to application cpu */ 704 val = readl(pctrl->regs + g->intr_target_reg); 705 val &= ~(7 << g->intr_target_bit); 706 val |= g->intr_target_kpss_val << g->intr_target_bit; 707 writel(val, pctrl->regs + g->intr_target_reg); 708 709 /* Update configuration for gpio. 710 * RAW_STATUS_EN is left on for all gpio irqs. Due to the 711 * internal circuitry of TLMM, toggling the RAW_STATUS 712 * could cause the INTR_STATUS to be set for EDGE interrupts. 713 */ 714 val = readl(pctrl->regs + g->intr_cfg_reg); 715 val |= BIT(g->intr_raw_status_bit); 716 if (g->intr_detection_width == 2) { 717 val &= ~(3 << g->intr_detection_bit); 718 val &= ~(1 << g->intr_polarity_bit); 719 switch (type) { 720 case IRQ_TYPE_EDGE_RISING: 721 val |= 1 << g->intr_detection_bit; 722 val |= BIT(g->intr_polarity_bit); 723 break; 724 case IRQ_TYPE_EDGE_FALLING: 725 val |= 2 << g->intr_detection_bit; 726 val |= BIT(g->intr_polarity_bit); 727 break; 728 case IRQ_TYPE_EDGE_BOTH: 729 val |= 3 << g->intr_detection_bit; 730 val |= BIT(g->intr_polarity_bit); 731 break; 732 case IRQ_TYPE_LEVEL_LOW: 733 break; 734 case IRQ_TYPE_LEVEL_HIGH: 735 val |= BIT(g->intr_polarity_bit); 736 break; 737 } 738 } else if (g->intr_detection_width == 1) { 739 val &= ~(1 << g->intr_detection_bit); 740 val &= ~(1 << g->intr_polarity_bit); 741 switch (type) { 742 case IRQ_TYPE_EDGE_RISING: 743 val |= BIT(g->intr_detection_bit); 744 val |= BIT(g->intr_polarity_bit); 745 break; 746 case IRQ_TYPE_EDGE_FALLING: 747 val |= BIT(g->intr_detection_bit); 748 break; 749 case IRQ_TYPE_EDGE_BOTH: 750 val |= BIT(g->intr_detection_bit); 751 val |= BIT(g->intr_polarity_bit); 752 break; 753 case IRQ_TYPE_LEVEL_LOW: 754 break; 755 case IRQ_TYPE_LEVEL_HIGH: 756 val |= BIT(g->intr_polarity_bit); 757 break; 758 } 759 } else { 760 BUG(); 761 } 762 writel(val, pctrl->regs + g->intr_cfg_reg); 763 764 if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) 765 msm_gpio_update_dual_edge_pos(pctrl, g, d); 766 767 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 768 769 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) 770 irq_set_handler_locked(d, handle_level_irq); 771 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) 772 irq_set_handler_locked(d, handle_edge_irq); 773 774 return 0; 775 } 776 777 static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on) 778 { 779 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 780 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); 781 unsigned long flags; 782 783 raw_spin_lock_irqsave(&pctrl->lock, flags); 784 785 irq_set_irq_wake(pctrl->irq, on); 786 787 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 788 789 return 0; 790 } 791 792 static void msm_gpio_irq_handler(struct irq_desc *desc) 793 { 794 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 795 const struct msm_pingroup *g; 796 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); 797 struct irq_chip *chip = irq_desc_get_chip(desc); 798 int irq_pin; 799 int handled = 0; 800 u32 val; 801 int i; 802 803 chained_irq_enter(chip, desc); 804 805 /* 806 * Each pin has it's own IRQ status register, so use 807 * enabled_irq bitmap to limit the number of reads. 808 */ 809 for_each_set_bit(i, pctrl->enabled_irqs, pctrl->chip.ngpio) { 810 g = &pctrl->soc->groups[i]; 811 val = readl(pctrl->regs + g->intr_status_reg); 812 if (val & BIT(g->intr_status_bit)) { 813 irq_pin = irq_find_mapping(gc->irq.domain, i); 814 generic_handle_irq(irq_pin); 815 handled++; 816 } 817 } 818 819 /* No interrupts were flagged */ 820 if (handled == 0) 821 handle_bad_irq(desc); 822 823 chained_irq_exit(chip, desc); 824 } 825 826 static int msm_gpio_init_valid_mask(struct gpio_chip *chip, 827 struct msm_pinctrl *pctrl) 828 { 829 int ret; 830 unsigned int len, i; 831 unsigned int max_gpios = pctrl->soc->ngpios; 832 u16 *tmp; 833 834 /* The number of GPIOs in the ACPI tables */ 835 len = ret = device_property_read_u16_array(pctrl->dev, "gpios", NULL, 0); 836 if (ret < 0) 837 return 0; 838 839 if (ret > max_gpios) 840 return -EINVAL; 841 842 tmp = kmalloc_array(len, sizeof(*tmp), GFP_KERNEL); 843 if (!tmp) 844 return -ENOMEM; 845 846 ret = device_property_read_u16_array(pctrl->dev, "gpios", tmp, len); 847 if (ret < 0) { 848 dev_err(pctrl->dev, "could not read list of GPIOs\n"); 849 goto out; 850 } 851 852 bitmap_zero(chip->valid_mask, max_gpios); 853 for (i = 0; i < len; i++) 854 set_bit(tmp[i], chip->valid_mask); 855 856 out: 857 kfree(tmp); 858 return ret; 859 } 860 861 static bool msm_gpio_needs_valid_mask(struct msm_pinctrl *pctrl) 862 { 863 return device_property_read_u16_array(pctrl->dev, "gpios", NULL, 0) > 0; 864 } 865 866 static int msm_gpio_init(struct msm_pinctrl *pctrl) 867 { 868 struct gpio_chip *chip; 869 int ret; 870 unsigned ngpio = pctrl->soc->ngpios; 871 872 if (WARN_ON(ngpio > MAX_NR_GPIO)) 873 return -EINVAL; 874 875 chip = &pctrl->chip; 876 chip->base = -1; 877 chip->ngpio = ngpio; 878 chip->label = dev_name(pctrl->dev); 879 chip->parent = pctrl->dev; 880 chip->owner = THIS_MODULE; 881 chip->of_node = pctrl->dev->of_node; 882 chip->need_valid_mask = msm_gpio_needs_valid_mask(pctrl); 883 884 pctrl->irq_chip.name = "msmgpio"; 885 pctrl->irq_chip.irq_mask = msm_gpio_irq_mask; 886 pctrl->irq_chip.irq_unmask = msm_gpio_irq_unmask; 887 pctrl->irq_chip.irq_ack = msm_gpio_irq_ack; 888 pctrl->irq_chip.irq_set_type = msm_gpio_irq_set_type; 889 pctrl->irq_chip.irq_set_wake = msm_gpio_irq_set_wake; 890 891 ret = gpiochip_add_data(&pctrl->chip, pctrl); 892 if (ret) { 893 dev_err(pctrl->dev, "Failed register gpiochip\n"); 894 return ret; 895 } 896 897 ret = msm_gpio_init_valid_mask(chip, pctrl); 898 if (ret) { 899 dev_err(pctrl->dev, "Failed to setup irq valid bits\n"); 900 gpiochip_remove(&pctrl->chip); 901 return ret; 902 } 903 904 /* 905 * For DeviceTree-supported systems, the gpio core checks the 906 * pinctrl's device node for the "gpio-ranges" property. 907 * If it is present, it takes care of adding the pin ranges 908 * for the driver. In this case the driver can skip ahead. 909 * 910 * In order to remain compatible with older, existing DeviceTree 911 * files which don't set the "gpio-ranges" property or systems that 912 * utilize ACPI the driver has to call gpiochip_add_pin_range(). 913 */ 914 if (!of_property_read_bool(pctrl->dev->of_node, "gpio-ranges")) { 915 ret = gpiochip_add_pin_range(&pctrl->chip, 916 dev_name(pctrl->dev), 0, 0, chip->ngpio); 917 if (ret) { 918 dev_err(pctrl->dev, "Failed to add pin range\n"); 919 gpiochip_remove(&pctrl->chip); 920 return ret; 921 } 922 } 923 924 ret = gpiochip_irqchip_add(chip, 925 &pctrl->irq_chip, 926 0, 927 handle_edge_irq, 928 IRQ_TYPE_NONE); 929 if (ret) { 930 dev_err(pctrl->dev, "Failed to add irqchip to gpiochip\n"); 931 gpiochip_remove(&pctrl->chip); 932 return -ENOSYS; 933 } 934 935 gpiochip_set_chained_irqchip(chip, &pctrl->irq_chip, pctrl->irq, 936 msm_gpio_irq_handler); 937 938 return 0; 939 } 940 941 static int msm_ps_hold_restart(struct notifier_block *nb, unsigned long action, 942 void *data) 943 { 944 struct msm_pinctrl *pctrl = container_of(nb, struct msm_pinctrl, restart_nb); 945 946 writel(0, pctrl->regs + PS_HOLD_OFFSET); 947 mdelay(1000); 948 return NOTIFY_DONE; 949 } 950 951 static struct msm_pinctrl *poweroff_pctrl; 952 953 static void msm_ps_hold_poweroff(void) 954 { 955 msm_ps_hold_restart(&poweroff_pctrl->restart_nb, 0, NULL); 956 } 957 958 static void msm_pinctrl_setup_pm_reset(struct msm_pinctrl *pctrl) 959 { 960 int i; 961 const struct msm_function *func = pctrl->soc->functions; 962 963 for (i = 0; i < pctrl->soc->nfunctions; i++) 964 if (!strcmp(func[i].name, "ps_hold")) { 965 pctrl->restart_nb.notifier_call = msm_ps_hold_restart; 966 pctrl->restart_nb.priority = 128; 967 if (register_restart_handler(&pctrl->restart_nb)) 968 dev_err(pctrl->dev, 969 "failed to setup restart handler.\n"); 970 poweroff_pctrl = pctrl; 971 pm_power_off = msm_ps_hold_poweroff; 972 break; 973 } 974 } 975 976 int msm_pinctrl_probe(struct platform_device *pdev, 977 const struct msm_pinctrl_soc_data *soc_data) 978 { 979 struct msm_pinctrl *pctrl; 980 struct resource *res; 981 int ret; 982 983 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); 984 if (!pctrl) 985 return -ENOMEM; 986 987 pctrl->dev = &pdev->dev; 988 pctrl->soc = soc_data; 989 pctrl->chip = msm_gpio_template; 990 991 raw_spin_lock_init(&pctrl->lock); 992 993 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 994 pctrl->regs = devm_ioremap_resource(&pdev->dev, res); 995 if (IS_ERR(pctrl->regs)) 996 return PTR_ERR(pctrl->regs); 997 998 msm_pinctrl_setup_pm_reset(pctrl); 999 1000 pctrl->irq = platform_get_irq(pdev, 0); 1001 if (pctrl->irq < 0) { 1002 dev_err(&pdev->dev, "No interrupt defined for msmgpio\n"); 1003 return pctrl->irq; 1004 } 1005 1006 pctrl->desc.owner = THIS_MODULE; 1007 pctrl->desc.pctlops = &msm_pinctrl_ops; 1008 pctrl->desc.pmxops = &msm_pinmux_ops; 1009 pctrl->desc.confops = &msm_pinconf_ops; 1010 pctrl->desc.name = dev_name(&pdev->dev); 1011 pctrl->desc.pins = pctrl->soc->pins; 1012 pctrl->desc.npins = pctrl->soc->npins; 1013 1014 pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &pctrl->desc, pctrl); 1015 if (IS_ERR(pctrl->pctrl)) { 1016 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); 1017 return PTR_ERR(pctrl->pctrl); 1018 } 1019 1020 ret = msm_gpio_init(pctrl); 1021 if (ret) 1022 return ret; 1023 1024 platform_set_drvdata(pdev, pctrl); 1025 1026 dev_dbg(&pdev->dev, "Probed Qualcomm pinctrl driver\n"); 1027 1028 return 0; 1029 } 1030 EXPORT_SYMBOL(msm_pinctrl_probe); 1031 1032 int msm_pinctrl_remove(struct platform_device *pdev) 1033 { 1034 struct msm_pinctrl *pctrl = platform_get_drvdata(pdev); 1035 1036 gpiochip_remove(&pctrl->chip); 1037 1038 unregister_restart_handler(&pctrl->restart_nb); 1039 1040 return 0; 1041 } 1042 EXPORT_SYMBOL(msm_pinctrl_remove); 1043 1044