1 /* 2 * Copyright (c) 2013, Sony Mobile Communications AB. 3 * Copyright (c) 2013, The Linux Foundation. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 and 7 * only version 2 as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 */ 14 15 #include <linux/delay.h> 16 #include <linux/err.h> 17 #include <linux/io.h> 18 #include <linux/module.h> 19 #include <linux/of.h> 20 #include <linux/platform_device.h> 21 #include <linux/pinctrl/machine.h> 22 #include <linux/pinctrl/pinctrl.h> 23 #include <linux/pinctrl/pinmux.h> 24 #include <linux/pinctrl/pinconf.h> 25 #include <linux/pinctrl/pinconf-generic.h> 26 #include <linux/slab.h> 27 #include <linux/gpio.h> 28 #include <linux/interrupt.h> 29 #include <linux/spinlock.h> 30 #include <linux/reboot.h> 31 #include <linux/pm.h> 32 33 #include "../core.h" 34 #include "../pinconf.h" 35 #include "pinctrl-msm.h" 36 #include "../pinctrl-utils.h" 37 38 #define MAX_NR_GPIO 300 39 #define PS_HOLD_OFFSET 0x820 40 41 /** 42 * struct msm_pinctrl - state for a pinctrl-msm device 43 * @dev: device handle. 44 * @pctrl: pinctrl handle. 45 * @chip: gpiochip handle. 46 * @restart_nb: restart notifier block. 47 * @irq: parent irq for the TLMM irq_chip. 48 * @lock: Spinlock to protect register resources as well 49 * as msm_pinctrl data structures. 50 * @enabled_irqs: Bitmap of currently enabled irqs. 51 * @dual_edge_irqs: Bitmap of irqs that need sw emulated dual edge 52 * detection. 53 * @soc; Reference to soc_data of platform specific data. 54 * @regs: Base address for the TLMM register map. 55 */ 56 struct msm_pinctrl { 57 struct device *dev; 58 struct pinctrl_dev *pctrl; 59 struct gpio_chip chip; 60 struct notifier_block restart_nb; 61 int irq; 62 63 spinlock_t lock; 64 65 DECLARE_BITMAP(dual_edge_irqs, MAX_NR_GPIO); 66 DECLARE_BITMAP(enabled_irqs, MAX_NR_GPIO); 67 68 const struct msm_pinctrl_soc_data *soc; 69 void __iomem *regs; 70 }; 71 72 static inline struct msm_pinctrl *to_msm_pinctrl(struct gpio_chip *gc) 73 { 74 return container_of(gc, struct msm_pinctrl, chip); 75 } 76 77 static int msm_get_groups_count(struct pinctrl_dev *pctldev) 78 { 79 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 80 81 return pctrl->soc->ngroups; 82 } 83 84 static const char *msm_get_group_name(struct pinctrl_dev *pctldev, 85 unsigned group) 86 { 87 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 88 89 return pctrl->soc->groups[group].name; 90 } 91 92 static int msm_get_group_pins(struct pinctrl_dev *pctldev, 93 unsigned group, 94 const unsigned **pins, 95 unsigned *num_pins) 96 { 97 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 98 99 *pins = pctrl->soc->groups[group].pins; 100 *num_pins = pctrl->soc->groups[group].npins; 101 return 0; 102 } 103 104 static const struct pinctrl_ops msm_pinctrl_ops = { 105 .get_groups_count = msm_get_groups_count, 106 .get_group_name = msm_get_group_name, 107 .get_group_pins = msm_get_group_pins, 108 .dt_node_to_map = pinconf_generic_dt_node_to_map_group, 109 .dt_free_map = pinctrl_utils_dt_free_map, 110 }; 111 112 static int msm_get_functions_count(struct pinctrl_dev *pctldev) 113 { 114 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 115 116 return pctrl->soc->nfunctions; 117 } 118 119 static const char *msm_get_function_name(struct pinctrl_dev *pctldev, 120 unsigned function) 121 { 122 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 123 124 return pctrl->soc->functions[function].name; 125 } 126 127 static int msm_get_function_groups(struct pinctrl_dev *pctldev, 128 unsigned function, 129 const char * const **groups, 130 unsigned * const num_groups) 131 { 132 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 133 134 *groups = pctrl->soc->functions[function].groups; 135 *num_groups = pctrl->soc->functions[function].ngroups; 136 return 0; 137 } 138 139 static int msm_pinmux_set_mux(struct pinctrl_dev *pctldev, 140 unsigned function, 141 unsigned group) 142 { 143 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 144 const struct msm_pingroup *g; 145 unsigned long flags; 146 u32 val; 147 int i; 148 149 g = &pctrl->soc->groups[group]; 150 151 for (i = 0; i < g->nfuncs; i++) { 152 if (g->funcs[i] == function) 153 break; 154 } 155 156 if (WARN_ON(i == g->nfuncs)) 157 return -EINVAL; 158 159 spin_lock_irqsave(&pctrl->lock, flags); 160 161 val = readl(pctrl->regs + g->ctl_reg); 162 val &= ~(0x7 << g->mux_bit); 163 val |= i << g->mux_bit; 164 writel(val, pctrl->regs + g->ctl_reg); 165 166 spin_unlock_irqrestore(&pctrl->lock, flags); 167 168 return 0; 169 } 170 171 static const struct pinmux_ops msm_pinmux_ops = { 172 .get_functions_count = msm_get_functions_count, 173 .get_function_name = msm_get_function_name, 174 .get_function_groups = msm_get_function_groups, 175 .set_mux = msm_pinmux_set_mux, 176 }; 177 178 static int msm_config_reg(struct msm_pinctrl *pctrl, 179 const struct msm_pingroup *g, 180 unsigned param, 181 unsigned *mask, 182 unsigned *bit) 183 { 184 switch (param) { 185 case PIN_CONFIG_BIAS_DISABLE: 186 case PIN_CONFIG_BIAS_PULL_DOWN: 187 case PIN_CONFIG_BIAS_BUS_HOLD: 188 case PIN_CONFIG_BIAS_PULL_UP: 189 *bit = g->pull_bit; 190 *mask = 3; 191 break; 192 case PIN_CONFIG_DRIVE_STRENGTH: 193 *bit = g->drv_bit; 194 *mask = 7; 195 break; 196 case PIN_CONFIG_OUTPUT: 197 case PIN_CONFIG_INPUT_ENABLE: 198 *bit = g->oe_bit; 199 *mask = 1; 200 break; 201 default: 202 return -ENOTSUPP; 203 } 204 205 return 0; 206 } 207 208 #define MSM_NO_PULL 0 209 #define MSM_PULL_DOWN 1 210 #define MSM_KEEPER 2 211 #define MSM_PULL_UP 3 212 213 static unsigned msm_regval_to_drive(u32 val) 214 { 215 return (val + 1) * 2; 216 } 217 218 static int msm_config_group_get(struct pinctrl_dev *pctldev, 219 unsigned int group, 220 unsigned long *config) 221 { 222 const struct msm_pingroup *g; 223 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 224 unsigned param = pinconf_to_config_param(*config); 225 unsigned mask; 226 unsigned arg; 227 unsigned bit; 228 int ret; 229 u32 val; 230 231 g = &pctrl->soc->groups[group]; 232 233 ret = msm_config_reg(pctrl, g, param, &mask, &bit); 234 if (ret < 0) 235 return ret; 236 237 val = readl(pctrl->regs + g->ctl_reg); 238 arg = (val >> bit) & mask; 239 240 /* Convert register value to pinconf value */ 241 switch (param) { 242 case PIN_CONFIG_BIAS_DISABLE: 243 arg = arg == MSM_NO_PULL; 244 break; 245 case PIN_CONFIG_BIAS_PULL_DOWN: 246 arg = arg == MSM_PULL_DOWN; 247 break; 248 case PIN_CONFIG_BIAS_BUS_HOLD: 249 arg = arg == MSM_KEEPER; 250 break; 251 case PIN_CONFIG_BIAS_PULL_UP: 252 arg = arg == MSM_PULL_UP; 253 break; 254 case PIN_CONFIG_DRIVE_STRENGTH: 255 arg = msm_regval_to_drive(arg); 256 break; 257 case PIN_CONFIG_OUTPUT: 258 /* Pin is not output */ 259 if (!arg) 260 return -EINVAL; 261 262 val = readl(pctrl->regs + g->io_reg); 263 arg = !!(val & BIT(g->in_bit)); 264 break; 265 case PIN_CONFIG_INPUT_ENABLE: 266 /* Pin is output */ 267 if (arg) 268 return -EINVAL; 269 arg = 1; 270 break; 271 default: 272 return -ENOTSUPP; 273 } 274 275 *config = pinconf_to_config_packed(param, arg); 276 277 return 0; 278 } 279 280 static int msm_config_group_set(struct pinctrl_dev *pctldev, 281 unsigned group, 282 unsigned long *configs, 283 unsigned num_configs) 284 { 285 const struct msm_pingroup *g; 286 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 287 unsigned long flags; 288 unsigned param; 289 unsigned mask; 290 unsigned arg; 291 unsigned bit; 292 int ret; 293 u32 val; 294 int i; 295 296 g = &pctrl->soc->groups[group]; 297 298 for (i = 0; i < num_configs; i++) { 299 param = pinconf_to_config_param(configs[i]); 300 arg = pinconf_to_config_argument(configs[i]); 301 302 ret = msm_config_reg(pctrl, g, param, &mask, &bit); 303 if (ret < 0) 304 return ret; 305 306 /* Convert pinconf values to register values */ 307 switch (param) { 308 case PIN_CONFIG_BIAS_DISABLE: 309 arg = MSM_NO_PULL; 310 break; 311 case PIN_CONFIG_BIAS_PULL_DOWN: 312 arg = MSM_PULL_DOWN; 313 break; 314 case PIN_CONFIG_BIAS_BUS_HOLD: 315 arg = MSM_KEEPER; 316 break; 317 case PIN_CONFIG_BIAS_PULL_UP: 318 arg = MSM_PULL_UP; 319 break; 320 case PIN_CONFIG_DRIVE_STRENGTH: 321 /* Check for invalid values */ 322 if (arg > 16 || arg < 2 || (arg % 2) != 0) 323 arg = -1; 324 else 325 arg = (arg / 2) - 1; 326 break; 327 case PIN_CONFIG_OUTPUT: 328 /* set output value */ 329 spin_lock_irqsave(&pctrl->lock, flags); 330 val = readl(pctrl->regs + g->io_reg); 331 if (arg) 332 val |= BIT(g->out_bit); 333 else 334 val &= ~BIT(g->out_bit); 335 writel(val, pctrl->regs + g->io_reg); 336 spin_unlock_irqrestore(&pctrl->lock, flags); 337 338 /* enable output */ 339 arg = 1; 340 break; 341 case PIN_CONFIG_INPUT_ENABLE: 342 /* disable output */ 343 arg = 0; 344 break; 345 default: 346 dev_err(pctrl->dev, "Unsupported config parameter: %x\n", 347 param); 348 return -EINVAL; 349 } 350 351 /* Range-check user-supplied value */ 352 if (arg & ~mask) { 353 dev_err(pctrl->dev, "config %x: %x is invalid\n", param, arg); 354 return -EINVAL; 355 } 356 357 spin_lock_irqsave(&pctrl->lock, flags); 358 val = readl(pctrl->regs + g->ctl_reg); 359 val &= ~(mask << bit); 360 val |= arg << bit; 361 writel(val, pctrl->regs + g->ctl_reg); 362 spin_unlock_irqrestore(&pctrl->lock, flags); 363 } 364 365 return 0; 366 } 367 368 static const struct pinconf_ops msm_pinconf_ops = { 369 .is_generic = true, 370 .pin_config_group_get = msm_config_group_get, 371 .pin_config_group_set = msm_config_group_set, 372 }; 373 374 static struct pinctrl_desc msm_pinctrl_desc = { 375 .pctlops = &msm_pinctrl_ops, 376 .pmxops = &msm_pinmux_ops, 377 .confops = &msm_pinconf_ops, 378 .owner = THIS_MODULE, 379 }; 380 381 static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 382 { 383 const struct msm_pingroup *g; 384 struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip); 385 unsigned long flags; 386 u32 val; 387 388 g = &pctrl->soc->groups[offset]; 389 390 spin_lock_irqsave(&pctrl->lock, flags); 391 392 val = readl(pctrl->regs + g->ctl_reg); 393 val &= ~BIT(g->oe_bit); 394 writel(val, pctrl->regs + g->ctl_reg); 395 396 spin_unlock_irqrestore(&pctrl->lock, flags); 397 398 return 0; 399 } 400 401 static int msm_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value) 402 { 403 const struct msm_pingroup *g; 404 struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip); 405 unsigned long flags; 406 u32 val; 407 408 g = &pctrl->soc->groups[offset]; 409 410 spin_lock_irqsave(&pctrl->lock, flags); 411 412 val = readl(pctrl->regs + g->io_reg); 413 if (value) 414 val |= BIT(g->out_bit); 415 else 416 val &= ~BIT(g->out_bit); 417 writel(val, pctrl->regs + g->io_reg); 418 419 val = readl(pctrl->regs + g->ctl_reg); 420 val |= BIT(g->oe_bit); 421 writel(val, pctrl->regs + g->ctl_reg); 422 423 spin_unlock_irqrestore(&pctrl->lock, flags); 424 425 return 0; 426 } 427 428 static int msm_gpio_get(struct gpio_chip *chip, unsigned offset) 429 { 430 const struct msm_pingroup *g; 431 struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip); 432 u32 val; 433 434 g = &pctrl->soc->groups[offset]; 435 436 val = readl(pctrl->regs + g->io_reg); 437 return !!(val & BIT(g->in_bit)); 438 } 439 440 static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 441 { 442 const struct msm_pingroup *g; 443 struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip); 444 unsigned long flags; 445 u32 val; 446 447 g = &pctrl->soc->groups[offset]; 448 449 spin_lock_irqsave(&pctrl->lock, flags); 450 451 val = readl(pctrl->regs + g->io_reg); 452 if (value) 453 val |= BIT(g->out_bit); 454 else 455 val &= ~BIT(g->out_bit); 456 writel(val, pctrl->regs + g->io_reg); 457 458 spin_unlock_irqrestore(&pctrl->lock, flags); 459 } 460 461 static int msm_gpio_request(struct gpio_chip *chip, unsigned offset) 462 { 463 int gpio = chip->base + offset; 464 return pinctrl_request_gpio(gpio); 465 } 466 467 static void msm_gpio_free(struct gpio_chip *chip, unsigned offset) 468 { 469 int gpio = chip->base + offset; 470 return pinctrl_free_gpio(gpio); 471 } 472 473 #ifdef CONFIG_DEBUG_FS 474 #include <linux/seq_file.h> 475 476 static void msm_gpio_dbg_show_one(struct seq_file *s, 477 struct pinctrl_dev *pctldev, 478 struct gpio_chip *chip, 479 unsigned offset, 480 unsigned gpio) 481 { 482 const struct msm_pingroup *g; 483 struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip); 484 unsigned func; 485 int is_out; 486 int drive; 487 int pull; 488 u32 ctl_reg; 489 490 static const char * const pulls[] = { 491 "no pull", 492 "pull down", 493 "keeper", 494 "pull up" 495 }; 496 497 g = &pctrl->soc->groups[offset]; 498 ctl_reg = readl(pctrl->regs + g->ctl_reg); 499 500 is_out = !!(ctl_reg & BIT(g->oe_bit)); 501 func = (ctl_reg >> g->mux_bit) & 7; 502 drive = (ctl_reg >> g->drv_bit) & 7; 503 pull = (ctl_reg >> g->pull_bit) & 3; 504 505 seq_printf(s, " %-8s: %-3s %d", g->name, is_out ? "out" : "in", func); 506 seq_printf(s, " %dmA", msm_regval_to_drive(drive)); 507 seq_printf(s, " %s", pulls[pull]); 508 } 509 510 static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) 511 { 512 unsigned gpio = chip->base; 513 unsigned i; 514 515 for (i = 0; i < chip->ngpio; i++, gpio++) { 516 msm_gpio_dbg_show_one(s, NULL, chip, i, gpio); 517 seq_puts(s, "\n"); 518 } 519 } 520 521 #else 522 #define msm_gpio_dbg_show NULL 523 #endif 524 525 static struct gpio_chip msm_gpio_template = { 526 .direction_input = msm_gpio_direction_input, 527 .direction_output = msm_gpio_direction_output, 528 .get = msm_gpio_get, 529 .set = msm_gpio_set, 530 .request = msm_gpio_request, 531 .free = msm_gpio_free, 532 .dbg_show = msm_gpio_dbg_show, 533 }; 534 535 /* For dual-edge interrupts in software, since some hardware has no 536 * such support: 537 * 538 * At appropriate moments, this function may be called to flip the polarity 539 * settings of both-edge irq lines to try and catch the next edge. 540 * 541 * The attempt is considered successful if: 542 * - the status bit goes high, indicating that an edge was caught, or 543 * - the input value of the gpio doesn't change during the attempt. 544 * If the value changes twice during the process, that would cause the first 545 * test to fail but would force the second, as two opposite 546 * transitions would cause a detection no matter the polarity setting. 547 * 548 * The do-loop tries to sledge-hammer closed the timing hole between 549 * the initial value-read and the polarity-write - if the line value changes 550 * during that window, an interrupt is lost, the new polarity setting is 551 * incorrect, and the first success test will fail, causing a retry. 552 * 553 * Algorithm comes from Google's msmgpio driver. 554 */ 555 static void msm_gpio_update_dual_edge_pos(struct msm_pinctrl *pctrl, 556 const struct msm_pingroup *g, 557 struct irq_data *d) 558 { 559 int loop_limit = 100; 560 unsigned val, val2, intstat; 561 unsigned pol; 562 563 do { 564 val = readl(pctrl->regs + g->io_reg) & BIT(g->in_bit); 565 566 pol = readl(pctrl->regs + g->intr_cfg_reg); 567 pol ^= BIT(g->intr_polarity_bit); 568 writel(pol, pctrl->regs + g->intr_cfg_reg); 569 570 val2 = readl(pctrl->regs + g->io_reg) & BIT(g->in_bit); 571 intstat = readl(pctrl->regs + g->intr_status_reg); 572 if (intstat || (val == val2)) 573 return; 574 } while (loop_limit-- > 0); 575 dev_err(pctrl->dev, "dual-edge irq failed to stabilize, %#08x != %#08x\n", 576 val, val2); 577 } 578 579 static void msm_gpio_irq_mask(struct irq_data *d) 580 { 581 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 582 struct msm_pinctrl *pctrl = to_msm_pinctrl(gc); 583 const struct msm_pingroup *g; 584 unsigned long flags; 585 u32 val; 586 587 g = &pctrl->soc->groups[d->hwirq]; 588 589 spin_lock_irqsave(&pctrl->lock, flags); 590 591 val = readl(pctrl->regs + g->intr_cfg_reg); 592 val &= ~BIT(g->intr_enable_bit); 593 writel(val, pctrl->regs + g->intr_cfg_reg); 594 595 clear_bit(d->hwirq, pctrl->enabled_irqs); 596 597 spin_unlock_irqrestore(&pctrl->lock, flags); 598 } 599 600 static void msm_gpio_irq_unmask(struct irq_data *d) 601 { 602 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 603 struct msm_pinctrl *pctrl = to_msm_pinctrl(gc); 604 const struct msm_pingroup *g; 605 unsigned long flags; 606 u32 val; 607 608 g = &pctrl->soc->groups[d->hwirq]; 609 610 spin_lock_irqsave(&pctrl->lock, flags); 611 612 val = readl(pctrl->regs + g->intr_status_reg); 613 val &= ~BIT(g->intr_status_bit); 614 writel(val, pctrl->regs + g->intr_status_reg); 615 616 val = readl(pctrl->regs + g->intr_cfg_reg); 617 val |= BIT(g->intr_enable_bit); 618 writel(val, pctrl->regs + g->intr_cfg_reg); 619 620 set_bit(d->hwirq, pctrl->enabled_irqs); 621 622 spin_unlock_irqrestore(&pctrl->lock, flags); 623 } 624 625 static void msm_gpio_irq_ack(struct irq_data *d) 626 { 627 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 628 struct msm_pinctrl *pctrl = to_msm_pinctrl(gc); 629 const struct msm_pingroup *g; 630 unsigned long flags; 631 u32 val; 632 633 g = &pctrl->soc->groups[d->hwirq]; 634 635 spin_lock_irqsave(&pctrl->lock, flags); 636 637 val = readl(pctrl->regs + g->intr_status_reg); 638 if (g->intr_ack_high) 639 val |= BIT(g->intr_status_bit); 640 else 641 val &= ~BIT(g->intr_status_bit); 642 writel(val, pctrl->regs + g->intr_status_reg); 643 644 if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) 645 msm_gpio_update_dual_edge_pos(pctrl, g, d); 646 647 spin_unlock_irqrestore(&pctrl->lock, flags); 648 } 649 650 static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type) 651 { 652 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 653 struct msm_pinctrl *pctrl = to_msm_pinctrl(gc); 654 const struct msm_pingroup *g; 655 unsigned long flags; 656 u32 val; 657 658 g = &pctrl->soc->groups[d->hwirq]; 659 660 spin_lock_irqsave(&pctrl->lock, flags); 661 662 /* 663 * For hw without possibility of detecting both edges 664 */ 665 if (g->intr_detection_width == 1 && type == IRQ_TYPE_EDGE_BOTH) 666 set_bit(d->hwirq, pctrl->dual_edge_irqs); 667 else 668 clear_bit(d->hwirq, pctrl->dual_edge_irqs); 669 670 /* Route interrupts to application cpu */ 671 val = readl(pctrl->regs + g->intr_target_reg); 672 val &= ~(7 << g->intr_target_bit); 673 val |= g->intr_target_kpss_val << g->intr_target_bit; 674 writel(val, pctrl->regs + g->intr_target_reg); 675 676 /* Update configuration for gpio. 677 * RAW_STATUS_EN is left on for all gpio irqs. Due to the 678 * internal circuitry of TLMM, toggling the RAW_STATUS 679 * could cause the INTR_STATUS to be set for EDGE interrupts. 680 */ 681 val = readl(pctrl->regs + g->intr_cfg_reg); 682 val |= BIT(g->intr_raw_status_bit); 683 if (g->intr_detection_width == 2) { 684 val &= ~(3 << g->intr_detection_bit); 685 val &= ~(1 << g->intr_polarity_bit); 686 switch (type) { 687 case IRQ_TYPE_EDGE_RISING: 688 val |= 1 << g->intr_detection_bit; 689 val |= BIT(g->intr_polarity_bit); 690 break; 691 case IRQ_TYPE_EDGE_FALLING: 692 val |= 2 << g->intr_detection_bit; 693 val |= BIT(g->intr_polarity_bit); 694 break; 695 case IRQ_TYPE_EDGE_BOTH: 696 val |= 3 << g->intr_detection_bit; 697 val |= BIT(g->intr_polarity_bit); 698 break; 699 case IRQ_TYPE_LEVEL_LOW: 700 break; 701 case IRQ_TYPE_LEVEL_HIGH: 702 val |= BIT(g->intr_polarity_bit); 703 break; 704 } 705 } else if (g->intr_detection_width == 1) { 706 val &= ~(1 << g->intr_detection_bit); 707 val &= ~(1 << g->intr_polarity_bit); 708 switch (type) { 709 case IRQ_TYPE_EDGE_RISING: 710 val |= BIT(g->intr_detection_bit); 711 val |= BIT(g->intr_polarity_bit); 712 break; 713 case IRQ_TYPE_EDGE_FALLING: 714 val |= BIT(g->intr_detection_bit); 715 break; 716 case IRQ_TYPE_EDGE_BOTH: 717 val |= BIT(g->intr_detection_bit); 718 val |= BIT(g->intr_polarity_bit); 719 break; 720 case IRQ_TYPE_LEVEL_LOW: 721 break; 722 case IRQ_TYPE_LEVEL_HIGH: 723 val |= BIT(g->intr_polarity_bit); 724 break; 725 } 726 } else { 727 BUG(); 728 } 729 writel(val, pctrl->regs + g->intr_cfg_reg); 730 731 if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) 732 msm_gpio_update_dual_edge_pos(pctrl, g, d); 733 734 spin_unlock_irqrestore(&pctrl->lock, flags); 735 736 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) 737 irq_set_handler_locked(d, handle_level_irq); 738 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) 739 irq_set_handler_locked(d, handle_edge_irq); 740 741 return 0; 742 } 743 744 static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on) 745 { 746 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 747 struct msm_pinctrl *pctrl = to_msm_pinctrl(gc); 748 unsigned long flags; 749 750 spin_lock_irqsave(&pctrl->lock, flags); 751 752 irq_set_irq_wake(pctrl->irq, on); 753 754 spin_unlock_irqrestore(&pctrl->lock, flags); 755 756 return 0; 757 } 758 759 static struct irq_chip msm_gpio_irq_chip = { 760 .name = "msmgpio", 761 .irq_mask = msm_gpio_irq_mask, 762 .irq_unmask = msm_gpio_irq_unmask, 763 .irq_ack = msm_gpio_irq_ack, 764 .irq_set_type = msm_gpio_irq_set_type, 765 .irq_set_wake = msm_gpio_irq_set_wake, 766 }; 767 768 static void msm_gpio_irq_handler(struct irq_desc *desc) 769 { 770 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 771 const struct msm_pingroup *g; 772 struct msm_pinctrl *pctrl = to_msm_pinctrl(gc); 773 struct irq_chip *chip = irq_desc_get_chip(desc); 774 int irq_pin; 775 int handled = 0; 776 u32 val; 777 int i; 778 779 chained_irq_enter(chip, desc); 780 781 /* 782 * Each pin has it's own IRQ status register, so use 783 * enabled_irq bitmap to limit the number of reads. 784 */ 785 for_each_set_bit(i, pctrl->enabled_irqs, pctrl->chip.ngpio) { 786 g = &pctrl->soc->groups[i]; 787 val = readl(pctrl->regs + g->intr_status_reg); 788 if (val & BIT(g->intr_status_bit)) { 789 irq_pin = irq_find_mapping(gc->irqdomain, i); 790 generic_handle_irq(irq_pin); 791 handled++; 792 } 793 } 794 795 /* No interrupts were flagged */ 796 if (handled == 0) 797 handle_bad_irq(desc); 798 799 chained_irq_exit(chip, desc); 800 } 801 802 static int msm_gpio_init(struct msm_pinctrl *pctrl) 803 { 804 struct gpio_chip *chip; 805 int ret; 806 unsigned ngpio = pctrl->soc->ngpios; 807 808 if (WARN_ON(ngpio > MAX_NR_GPIO)) 809 return -EINVAL; 810 811 chip = &pctrl->chip; 812 chip->base = 0; 813 chip->ngpio = ngpio; 814 chip->label = dev_name(pctrl->dev); 815 chip->dev = pctrl->dev; 816 chip->owner = THIS_MODULE; 817 chip->of_node = pctrl->dev->of_node; 818 819 ret = gpiochip_add(&pctrl->chip); 820 if (ret) { 821 dev_err(pctrl->dev, "Failed register gpiochip\n"); 822 return ret; 823 } 824 825 ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), 0, 0, chip->ngpio); 826 if (ret) { 827 dev_err(pctrl->dev, "Failed to add pin range\n"); 828 gpiochip_remove(&pctrl->chip); 829 return ret; 830 } 831 832 ret = gpiochip_irqchip_add(chip, 833 &msm_gpio_irq_chip, 834 0, 835 handle_edge_irq, 836 IRQ_TYPE_NONE); 837 if (ret) { 838 dev_err(pctrl->dev, "Failed to add irqchip to gpiochip\n"); 839 gpiochip_remove(&pctrl->chip); 840 return -ENOSYS; 841 } 842 843 gpiochip_set_chained_irqchip(chip, &msm_gpio_irq_chip, pctrl->irq, 844 msm_gpio_irq_handler); 845 846 return 0; 847 } 848 849 static int msm_ps_hold_restart(struct notifier_block *nb, unsigned long action, 850 void *data) 851 { 852 struct msm_pinctrl *pctrl = container_of(nb, struct msm_pinctrl, restart_nb); 853 854 writel(0, pctrl->regs + PS_HOLD_OFFSET); 855 mdelay(1000); 856 return NOTIFY_DONE; 857 } 858 859 static struct msm_pinctrl *poweroff_pctrl; 860 861 static void msm_ps_hold_poweroff(void) 862 { 863 msm_ps_hold_restart(&poweroff_pctrl->restart_nb, 0, NULL); 864 } 865 866 static void msm_pinctrl_setup_pm_reset(struct msm_pinctrl *pctrl) 867 { 868 int i; 869 const struct msm_function *func = pctrl->soc->functions; 870 871 for (i = 0; i < pctrl->soc->nfunctions; i++) 872 if (!strcmp(func[i].name, "ps_hold")) { 873 pctrl->restart_nb.notifier_call = msm_ps_hold_restart; 874 pctrl->restart_nb.priority = 128; 875 if (register_restart_handler(&pctrl->restart_nb)) 876 dev_err(pctrl->dev, 877 "failed to setup restart handler.\n"); 878 poweroff_pctrl = pctrl; 879 pm_power_off = msm_ps_hold_poweroff; 880 break; 881 } 882 } 883 884 int msm_pinctrl_probe(struct platform_device *pdev, 885 const struct msm_pinctrl_soc_data *soc_data) 886 { 887 struct msm_pinctrl *pctrl; 888 struct resource *res; 889 int ret; 890 891 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); 892 if (!pctrl) { 893 dev_err(&pdev->dev, "Can't allocate msm_pinctrl\n"); 894 return -ENOMEM; 895 } 896 pctrl->dev = &pdev->dev; 897 pctrl->soc = soc_data; 898 pctrl->chip = msm_gpio_template; 899 900 spin_lock_init(&pctrl->lock); 901 902 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 903 pctrl->regs = devm_ioremap_resource(&pdev->dev, res); 904 if (IS_ERR(pctrl->regs)) 905 return PTR_ERR(pctrl->regs); 906 907 msm_pinctrl_setup_pm_reset(pctrl); 908 909 pctrl->irq = platform_get_irq(pdev, 0); 910 if (pctrl->irq < 0) { 911 dev_err(&pdev->dev, "No interrupt defined for msmgpio\n"); 912 return pctrl->irq; 913 } 914 915 msm_pinctrl_desc.name = dev_name(&pdev->dev); 916 msm_pinctrl_desc.pins = pctrl->soc->pins; 917 msm_pinctrl_desc.npins = pctrl->soc->npins; 918 pctrl->pctrl = pinctrl_register(&msm_pinctrl_desc, &pdev->dev, pctrl); 919 if (IS_ERR(pctrl->pctrl)) { 920 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); 921 return PTR_ERR(pctrl->pctrl); 922 } 923 924 ret = msm_gpio_init(pctrl); 925 if (ret) { 926 pinctrl_unregister(pctrl->pctrl); 927 return ret; 928 } 929 930 platform_set_drvdata(pdev, pctrl); 931 932 dev_dbg(&pdev->dev, "Probed Qualcomm pinctrl driver\n"); 933 934 return 0; 935 } 936 EXPORT_SYMBOL(msm_pinctrl_probe); 937 938 int msm_pinctrl_remove(struct platform_device *pdev) 939 { 940 struct msm_pinctrl *pctrl = platform_get_drvdata(pdev); 941 942 gpiochip_remove(&pctrl->chip); 943 pinctrl_unregister(pctrl->pctrl); 944 945 unregister_restart_handler(&pctrl->restart_nb); 946 947 return 0; 948 } 949 EXPORT_SYMBOL(msm_pinctrl_remove); 950 951