1 /* 2 * Copyright (c) 2013, Sony Mobile Communications AB. 3 * Copyright (c) 2013, The Linux Foundation. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 and 7 * only version 2 as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 */ 14 15 #include <linux/delay.h> 16 #include <linux/err.h> 17 #include <linux/io.h> 18 #include <linux/module.h> 19 #include <linux/of.h> 20 #include <linux/platform_device.h> 21 #include <linux/pinctrl/machine.h> 22 #include <linux/pinctrl/pinctrl.h> 23 #include <linux/pinctrl/pinmux.h> 24 #include <linux/pinctrl/pinconf.h> 25 #include <linux/pinctrl/pinconf-generic.h> 26 #include <linux/slab.h> 27 #include <linux/gpio.h> 28 #include <linux/interrupt.h> 29 #include <linux/spinlock.h> 30 #include <linux/reboot.h> 31 #include <linux/pm.h> 32 #include <linux/log2.h> 33 34 #include "../core.h" 35 #include "../pinconf.h" 36 #include "pinctrl-msm.h" 37 #include "../pinctrl-utils.h" 38 39 #define MAX_NR_GPIO 300 40 #define PS_HOLD_OFFSET 0x820 41 42 /** 43 * struct msm_pinctrl - state for a pinctrl-msm device 44 * @dev: device handle. 45 * @pctrl: pinctrl handle. 46 * @chip: gpiochip handle. 47 * @restart_nb: restart notifier block. 48 * @irq: parent irq for the TLMM irq_chip. 49 * @lock: Spinlock to protect register resources as well 50 * as msm_pinctrl data structures. 51 * @enabled_irqs: Bitmap of currently enabled irqs. 52 * @dual_edge_irqs: Bitmap of irqs that need sw emulated dual edge 53 * detection. 54 * @soc; Reference to soc_data of platform specific data. 55 * @regs: Base address for the TLMM register map. 56 */ 57 struct msm_pinctrl { 58 struct device *dev; 59 struct pinctrl_dev *pctrl; 60 struct gpio_chip chip; 61 struct pinctrl_desc desc; 62 struct notifier_block restart_nb; 63 64 struct irq_chip irq_chip; 65 int irq; 66 67 raw_spinlock_t lock; 68 69 DECLARE_BITMAP(dual_edge_irqs, MAX_NR_GPIO); 70 DECLARE_BITMAP(enabled_irqs, MAX_NR_GPIO); 71 72 const struct msm_pinctrl_soc_data *soc; 73 void __iomem *regs; 74 }; 75 76 static int msm_get_groups_count(struct pinctrl_dev *pctldev) 77 { 78 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 79 80 return pctrl->soc->ngroups; 81 } 82 83 static const char *msm_get_group_name(struct pinctrl_dev *pctldev, 84 unsigned group) 85 { 86 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 87 88 return pctrl->soc->groups[group].name; 89 } 90 91 static int msm_get_group_pins(struct pinctrl_dev *pctldev, 92 unsigned group, 93 const unsigned **pins, 94 unsigned *num_pins) 95 { 96 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 97 98 *pins = pctrl->soc->groups[group].pins; 99 *num_pins = pctrl->soc->groups[group].npins; 100 return 0; 101 } 102 103 static const struct pinctrl_ops msm_pinctrl_ops = { 104 .get_groups_count = msm_get_groups_count, 105 .get_group_name = msm_get_group_name, 106 .get_group_pins = msm_get_group_pins, 107 .dt_node_to_map = pinconf_generic_dt_node_to_map_group, 108 .dt_free_map = pinctrl_utils_free_map, 109 }; 110 111 static int msm_pinmux_request(struct pinctrl_dev *pctldev, unsigned offset) 112 { 113 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 114 struct gpio_chip *chip = &pctrl->chip; 115 116 return gpiochip_line_is_valid(chip, offset) ? 0 : -EINVAL; 117 } 118 119 static int msm_get_functions_count(struct pinctrl_dev *pctldev) 120 { 121 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 122 123 return pctrl->soc->nfunctions; 124 } 125 126 static const char *msm_get_function_name(struct pinctrl_dev *pctldev, 127 unsigned function) 128 { 129 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 130 131 return pctrl->soc->functions[function].name; 132 } 133 134 static int msm_get_function_groups(struct pinctrl_dev *pctldev, 135 unsigned function, 136 const char * const **groups, 137 unsigned * const num_groups) 138 { 139 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 140 141 *groups = pctrl->soc->functions[function].groups; 142 *num_groups = pctrl->soc->functions[function].ngroups; 143 return 0; 144 } 145 146 static int msm_pinmux_set_mux(struct pinctrl_dev *pctldev, 147 unsigned function, 148 unsigned group) 149 { 150 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 151 const struct msm_pingroup *g; 152 unsigned long flags; 153 u32 val, mask; 154 int i; 155 156 g = &pctrl->soc->groups[group]; 157 mask = GENMASK(g->mux_bit + order_base_2(g->nfuncs) - 1, g->mux_bit); 158 159 for (i = 0; i < g->nfuncs; i++) { 160 if (g->funcs[i] == function) 161 break; 162 } 163 164 if (WARN_ON(i == g->nfuncs)) 165 return -EINVAL; 166 167 raw_spin_lock_irqsave(&pctrl->lock, flags); 168 169 val = readl(pctrl->regs + g->ctl_reg); 170 val &= ~mask; 171 val |= i << g->mux_bit; 172 writel(val, pctrl->regs + g->ctl_reg); 173 174 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 175 176 return 0; 177 } 178 179 static const struct pinmux_ops msm_pinmux_ops = { 180 .request = msm_pinmux_request, 181 .get_functions_count = msm_get_functions_count, 182 .get_function_name = msm_get_function_name, 183 .get_function_groups = msm_get_function_groups, 184 .set_mux = msm_pinmux_set_mux, 185 }; 186 187 static int msm_config_reg(struct msm_pinctrl *pctrl, 188 const struct msm_pingroup *g, 189 unsigned param, 190 unsigned *mask, 191 unsigned *bit) 192 { 193 switch (param) { 194 case PIN_CONFIG_BIAS_DISABLE: 195 case PIN_CONFIG_BIAS_PULL_DOWN: 196 case PIN_CONFIG_BIAS_BUS_HOLD: 197 case PIN_CONFIG_BIAS_PULL_UP: 198 *bit = g->pull_bit; 199 *mask = 3; 200 break; 201 case PIN_CONFIG_DRIVE_STRENGTH: 202 *bit = g->drv_bit; 203 *mask = 7; 204 break; 205 case PIN_CONFIG_OUTPUT: 206 case PIN_CONFIG_INPUT_ENABLE: 207 *bit = g->oe_bit; 208 *mask = 1; 209 break; 210 default: 211 return -ENOTSUPP; 212 } 213 214 return 0; 215 } 216 217 #define MSM_NO_PULL 0 218 #define MSM_PULL_DOWN 1 219 #define MSM_KEEPER 2 220 #define MSM_PULL_UP_NO_KEEPER 2 221 #define MSM_PULL_UP 3 222 223 static unsigned msm_regval_to_drive(u32 val) 224 { 225 return (val + 1) * 2; 226 } 227 228 static int msm_config_group_get(struct pinctrl_dev *pctldev, 229 unsigned int group, 230 unsigned long *config) 231 { 232 const struct msm_pingroup *g; 233 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 234 unsigned param = pinconf_to_config_param(*config); 235 unsigned mask; 236 unsigned arg; 237 unsigned bit; 238 int ret; 239 u32 val; 240 241 g = &pctrl->soc->groups[group]; 242 243 ret = msm_config_reg(pctrl, g, param, &mask, &bit); 244 if (ret < 0) 245 return ret; 246 247 val = readl(pctrl->regs + g->ctl_reg); 248 arg = (val >> bit) & mask; 249 250 /* Convert register value to pinconf value */ 251 switch (param) { 252 case PIN_CONFIG_BIAS_DISABLE: 253 if (arg != MSM_NO_PULL) 254 return -EINVAL; 255 arg = 1; 256 break; 257 case PIN_CONFIG_BIAS_PULL_DOWN: 258 if (arg != MSM_PULL_DOWN) 259 return -EINVAL; 260 arg = 1; 261 break; 262 case PIN_CONFIG_BIAS_BUS_HOLD: 263 if (pctrl->soc->pull_no_keeper) 264 return -ENOTSUPP; 265 266 if (arg != MSM_KEEPER) 267 return -EINVAL; 268 arg = 1; 269 break; 270 case PIN_CONFIG_BIAS_PULL_UP: 271 if (pctrl->soc->pull_no_keeper) 272 arg = arg == MSM_PULL_UP_NO_KEEPER; 273 else 274 arg = arg == MSM_PULL_UP; 275 if (!arg) 276 return -EINVAL; 277 break; 278 case PIN_CONFIG_DRIVE_STRENGTH: 279 arg = msm_regval_to_drive(arg); 280 break; 281 case PIN_CONFIG_OUTPUT: 282 /* Pin is not output */ 283 if (!arg) 284 return -EINVAL; 285 286 val = readl(pctrl->regs + g->io_reg); 287 arg = !!(val & BIT(g->in_bit)); 288 break; 289 case PIN_CONFIG_INPUT_ENABLE: 290 /* Pin is output */ 291 if (arg) 292 return -EINVAL; 293 arg = 1; 294 break; 295 default: 296 return -ENOTSUPP; 297 } 298 299 *config = pinconf_to_config_packed(param, arg); 300 301 return 0; 302 } 303 304 static int msm_config_group_set(struct pinctrl_dev *pctldev, 305 unsigned group, 306 unsigned long *configs, 307 unsigned num_configs) 308 { 309 const struct msm_pingroup *g; 310 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 311 unsigned long flags; 312 unsigned param; 313 unsigned mask; 314 unsigned arg; 315 unsigned bit; 316 int ret; 317 u32 val; 318 int i; 319 320 g = &pctrl->soc->groups[group]; 321 322 for (i = 0; i < num_configs; i++) { 323 param = pinconf_to_config_param(configs[i]); 324 arg = pinconf_to_config_argument(configs[i]); 325 326 ret = msm_config_reg(pctrl, g, param, &mask, &bit); 327 if (ret < 0) 328 return ret; 329 330 /* Convert pinconf values to register values */ 331 switch (param) { 332 case PIN_CONFIG_BIAS_DISABLE: 333 arg = MSM_NO_PULL; 334 break; 335 case PIN_CONFIG_BIAS_PULL_DOWN: 336 arg = MSM_PULL_DOWN; 337 break; 338 case PIN_CONFIG_BIAS_BUS_HOLD: 339 if (pctrl->soc->pull_no_keeper) 340 return -ENOTSUPP; 341 342 arg = MSM_KEEPER; 343 break; 344 case PIN_CONFIG_BIAS_PULL_UP: 345 if (pctrl->soc->pull_no_keeper) 346 arg = MSM_PULL_UP_NO_KEEPER; 347 else 348 arg = MSM_PULL_UP; 349 break; 350 case PIN_CONFIG_DRIVE_STRENGTH: 351 /* Check for invalid values */ 352 if (arg > 16 || arg < 2 || (arg % 2) != 0) 353 arg = -1; 354 else 355 arg = (arg / 2) - 1; 356 break; 357 case PIN_CONFIG_OUTPUT: 358 /* set output value */ 359 raw_spin_lock_irqsave(&pctrl->lock, flags); 360 val = readl(pctrl->regs + g->io_reg); 361 if (arg) 362 val |= BIT(g->out_bit); 363 else 364 val &= ~BIT(g->out_bit); 365 writel(val, pctrl->regs + g->io_reg); 366 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 367 368 /* enable output */ 369 arg = 1; 370 break; 371 case PIN_CONFIG_INPUT_ENABLE: 372 /* disable output */ 373 arg = 0; 374 break; 375 default: 376 dev_err(pctrl->dev, "Unsupported config parameter: %x\n", 377 param); 378 return -EINVAL; 379 } 380 381 /* Range-check user-supplied value */ 382 if (arg & ~mask) { 383 dev_err(pctrl->dev, "config %x: %x is invalid\n", param, arg); 384 return -EINVAL; 385 } 386 387 raw_spin_lock_irqsave(&pctrl->lock, flags); 388 val = readl(pctrl->regs + g->ctl_reg); 389 val &= ~(mask << bit); 390 val |= arg << bit; 391 writel(val, pctrl->regs + g->ctl_reg); 392 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 393 } 394 395 return 0; 396 } 397 398 static const struct pinconf_ops msm_pinconf_ops = { 399 .is_generic = true, 400 .pin_config_group_get = msm_config_group_get, 401 .pin_config_group_set = msm_config_group_set, 402 }; 403 404 static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 405 { 406 const struct msm_pingroup *g; 407 struct msm_pinctrl *pctrl = gpiochip_get_data(chip); 408 unsigned long flags; 409 u32 val; 410 411 g = &pctrl->soc->groups[offset]; 412 413 raw_spin_lock_irqsave(&pctrl->lock, flags); 414 415 val = readl(pctrl->regs + g->ctl_reg); 416 val &= ~BIT(g->oe_bit); 417 writel(val, pctrl->regs + g->ctl_reg); 418 419 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 420 421 return 0; 422 } 423 424 static int msm_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value) 425 { 426 const struct msm_pingroup *g; 427 struct msm_pinctrl *pctrl = gpiochip_get_data(chip); 428 unsigned long flags; 429 u32 val; 430 431 g = &pctrl->soc->groups[offset]; 432 433 raw_spin_lock_irqsave(&pctrl->lock, flags); 434 435 val = readl(pctrl->regs + g->io_reg); 436 if (value) 437 val |= BIT(g->out_bit); 438 else 439 val &= ~BIT(g->out_bit); 440 writel(val, pctrl->regs + g->io_reg); 441 442 val = readl(pctrl->regs + g->ctl_reg); 443 val |= BIT(g->oe_bit); 444 writel(val, pctrl->regs + g->ctl_reg); 445 446 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 447 448 return 0; 449 } 450 451 static int msm_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 452 { 453 struct msm_pinctrl *pctrl = gpiochip_get_data(chip); 454 const struct msm_pingroup *g; 455 u32 val; 456 457 g = &pctrl->soc->groups[offset]; 458 459 val = readl(pctrl->regs + g->ctl_reg); 460 461 /* 0 = output, 1 = input */ 462 return val & BIT(g->oe_bit) ? 0 : 1; 463 } 464 465 static int msm_gpio_get(struct gpio_chip *chip, unsigned offset) 466 { 467 const struct msm_pingroup *g; 468 struct msm_pinctrl *pctrl = gpiochip_get_data(chip); 469 u32 val; 470 471 g = &pctrl->soc->groups[offset]; 472 473 val = readl(pctrl->regs + g->io_reg); 474 return !!(val & BIT(g->in_bit)); 475 } 476 477 static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 478 { 479 const struct msm_pingroup *g; 480 struct msm_pinctrl *pctrl = gpiochip_get_data(chip); 481 unsigned long flags; 482 u32 val; 483 484 g = &pctrl->soc->groups[offset]; 485 486 raw_spin_lock_irqsave(&pctrl->lock, flags); 487 488 val = readl(pctrl->regs + g->io_reg); 489 if (value) 490 val |= BIT(g->out_bit); 491 else 492 val &= ~BIT(g->out_bit); 493 writel(val, pctrl->regs + g->io_reg); 494 495 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 496 } 497 498 #ifdef CONFIG_DEBUG_FS 499 #include <linux/seq_file.h> 500 501 static void msm_gpio_dbg_show_one(struct seq_file *s, 502 struct pinctrl_dev *pctldev, 503 struct gpio_chip *chip, 504 unsigned offset, 505 unsigned gpio) 506 { 507 const struct msm_pingroup *g; 508 struct msm_pinctrl *pctrl = gpiochip_get_data(chip); 509 unsigned func; 510 int is_out; 511 int drive; 512 int pull; 513 int val; 514 u32 ctl_reg, io_reg; 515 516 static const char * const pulls_keeper[] = { 517 "no pull", 518 "pull down", 519 "keeper", 520 "pull up" 521 }; 522 523 static const char * const pulls_no_keeper[] = { 524 "no pull", 525 "pull down", 526 "pull up", 527 }; 528 529 if (!gpiochip_line_is_valid(chip, offset)) 530 return; 531 532 g = &pctrl->soc->groups[offset]; 533 ctl_reg = readl(pctrl->regs + g->ctl_reg); 534 io_reg = readl(pctrl->regs + g->io_reg); 535 536 is_out = !!(ctl_reg & BIT(g->oe_bit)); 537 func = (ctl_reg >> g->mux_bit) & 7; 538 drive = (ctl_reg >> g->drv_bit) & 7; 539 pull = (ctl_reg >> g->pull_bit) & 3; 540 541 if (is_out) 542 val = !!(io_reg & BIT(g->out_bit)); 543 else 544 val = !!(io_reg & BIT(g->in_bit)); 545 546 seq_printf(s, " %-8s: %-3s", g->name, is_out ? "out" : "in"); 547 seq_printf(s, " %-4s func%d", val ? "high" : "low", func); 548 seq_printf(s, " %dmA", msm_regval_to_drive(drive)); 549 if (pctrl->soc->pull_no_keeper) 550 seq_printf(s, " %s", pulls_no_keeper[pull]); 551 else 552 seq_printf(s, " %s", pulls_keeper[pull]); 553 seq_puts(s, "\n"); 554 } 555 556 static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) 557 { 558 unsigned gpio = chip->base; 559 unsigned i; 560 561 for (i = 0; i < chip->ngpio; i++, gpio++) 562 msm_gpio_dbg_show_one(s, NULL, chip, i, gpio); 563 } 564 565 #else 566 #define msm_gpio_dbg_show NULL 567 #endif 568 569 static const struct gpio_chip msm_gpio_template = { 570 .direction_input = msm_gpio_direction_input, 571 .direction_output = msm_gpio_direction_output, 572 .get_direction = msm_gpio_get_direction, 573 .get = msm_gpio_get, 574 .set = msm_gpio_set, 575 .request = gpiochip_generic_request, 576 .free = gpiochip_generic_free, 577 .dbg_show = msm_gpio_dbg_show, 578 }; 579 580 /* For dual-edge interrupts in software, since some hardware has no 581 * such support: 582 * 583 * At appropriate moments, this function may be called to flip the polarity 584 * settings of both-edge irq lines to try and catch the next edge. 585 * 586 * The attempt is considered successful if: 587 * - the status bit goes high, indicating that an edge was caught, or 588 * - the input value of the gpio doesn't change during the attempt. 589 * If the value changes twice during the process, that would cause the first 590 * test to fail but would force the second, as two opposite 591 * transitions would cause a detection no matter the polarity setting. 592 * 593 * The do-loop tries to sledge-hammer closed the timing hole between 594 * the initial value-read and the polarity-write - if the line value changes 595 * during that window, an interrupt is lost, the new polarity setting is 596 * incorrect, and the first success test will fail, causing a retry. 597 * 598 * Algorithm comes from Google's msmgpio driver. 599 */ 600 static void msm_gpio_update_dual_edge_pos(struct msm_pinctrl *pctrl, 601 const struct msm_pingroup *g, 602 struct irq_data *d) 603 { 604 int loop_limit = 100; 605 unsigned val, val2, intstat; 606 unsigned pol; 607 608 do { 609 val = readl(pctrl->regs + g->io_reg) & BIT(g->in_bit); 610 611 pol = readl(pctrl->regs + g->intr_cfg_reg); 612 pol ^= BIT(g->intr_polarity_bit); 613 writel(pol, pctrl->regs + g->intr_cfg_reg); 614 615 val2 = readl(pctrl->regs + g->io_reg) & BIT(g->in_bit); 616 intstat = readl(pctrl->regs + g->intr_status_reg); 617 if (intstat || (val == val2)) 618 return; 619 } while (loop_limit-- > 0); 620 dev_err(pctrl->dev, "dual-edge irq failed to stabilize, %#08x != %#08x\n", 621 val, val2); 622 } 623 624 static void msm_gpio_irq_mask(struct irq_data *d) 625 { 626 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 627 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); 628 const struct msm_pingroup *g; 629 unsigned long flags; 630 u32 val; 631 632 g = &pctrl->soc->groups[d->hwirq]; 633 634 raw_spin_lock_irqsave(&pctrl->lock, flags); 635 636 val = readl(pctrl->regs + g->intr_cfg_reg); 637 /* 638 * There are two bits that control interrupt forwarding to the CPU. The 639 * RAW_STATUS_EN bit causes the level or edge sensed on the line to be 640 * latched into the interrupt status register when the hardware detects 641 * an irq that it's configured for (either edge for edge type or level 642 * for level type irq). The 'non-raw' status enable bit causes the 643 * hardware to assert the summary interrupt to the CPU if the latched 644 * status bit is set. There's a bug though, the edge detection logic 645 * seems to have a problem where toggling the RAW_STATUS_EN bit may 646 * cause the status bit to latch spuriously when there isn't any edge 647 * so we can't touch that bit for edge type irqs and we have to keep 648 * the bit set anyway so that edges are latched while the line is masked. 649 * 650 * To make matters more complicated, leaving the RAW_STATUS_EN bit 651 * enabled all the time causes level interrupts to re-latch into the 652 * status register because the level is still present on the line after 653 * we ack it. We clear the raw status enable bit during mask here and 654 * set the bit on unmask so the interrupt can't latch into the hardware 655 * while it's masked. 656 */ 657 if (irqd_get_trigger_type(d) & IRQ_TYPE_LEVEL_MASK) 658 val &= ~BIT(g->intr_raw_status_bit); 659 660 val &= ~BIT(g->intr_enable_bit); 661 writel(val, pctrl->regs + g->intr_cfg_reg); 662 663 clear_bit(d->hwirq, pctrl->enabled_irqs); 664 665 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 666 } 667 668 static void msm_gpio_irq_unmask(struct irq_data *d) 669 { 670 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 671 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); 672 const struct msm_pingroup *g; 673 unsigned long flags; 674 u32 val; 675 676 g = &pctrl->soc->groups[d->hwirq]; 677 678 raw_spin_lock_irqsave(&pctrl->lock, flags); 679 680 val = readl(pctrl->regs + g->intr_cfg_reg); 681 val |= BIT(g->intr_raw_status_bit); 682 val |= BIT(g->intr_enable_bit); 683 writel(val, pctrl->regs + g->intr_cfg_reg); 684 685 set_bit(d->hwirq, pctrl->enabled_irqs); 686 687 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 688 } 689 690 static void msm_gpio_irq_ack(struct irq_data *d) 691 { 692 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 693 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); 694 const struct msm_pingroup *g; 695 unsigned long flags; 696 u32 val; 697 698 g = &pctrl->soc->groups[d->hwirq]; 699 700 raw_spin_lock_irqsave(&pctrl->lock, flags); 701 702 val = readl(pctrl->regs + g->intr_status_reg); 703 if (g->intr_ack_high) 704 val |= BIT(g->intr_status_bit); 705 else 706 val &= ~BIT(g->intr_status_bit); 707 writel(val, pctrl->regs + g->intr_status_reg); 708 709 if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) 710 msm_gpio_update_dual_edge_pos(pctrl, g, d); 711 712 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 713 } 714 715 static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type) 716 { 717 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 718 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); 719 const struct msm_pingroup *g; 720 unsigned long flags; 721 u32 val; 722 723 g = &pctrl->soc->groups[d->hwirq]; 724 725 raw_spin_lock_irqsave(&pctrl->lock, flags); 726 727 /* 728 * For hw without possibility of detecting both edges 729 */ 730 if (g->intr_detection_width == 1 && type == IRQ_TYPE_EDGE_BOTH) 731 set_bit(d->hwirq, pctrl->dual_edge_irqs); 732 else 733 clear_bit(d->hwirq, pctrl->dual_edge_irqs); 734 735 /* Route interrupts to application cpu */ 736 val = readl(pctrl->regs + g->intr_target_reg); 737 val &= ~(7 << g->intr_target_bit); 738 val |= g->intr_target_kpss_val << g->intr_target_bit; 739 writel(val, pctrl->regs + g->intr_target_reg); 740 741 /* Update configuration for gpio. 742 * RAW_STATUS_EN is left on for all gpio irqs. Due to the 743 * internal circuitry of TLMM, toggling the RAW_STATUS 744 * could cause the INTR_STATUS to be set for EDGE interrupts. 745 */ 746 val = readl(pctrl->regs + g->intr_cfg_reg); 747 val |= BIT(g->intr_raw_status_bit); 748 if (g->intr_detection_width == 2) { 749 val &= ~(3 << g->intr_detection_bit); 750 val &= ~(1 << g->intr_polarity_bit); 751 switch (type) { 752 case IRQ_TYPE_EDGE_RISING: 753 val |= 1 << g->intr_detection_bit; 754 val |= BIT(g->intr_polarity_bit); 755 break; 756 case IRQ_TYPE_EDGE_FALLING: 757 val |= 2 << g->intr_detection_bit; 758 val |= BIT(g->intr_polarity_bit); 759 break; 760 case IRQ_TYPE_EDGE_BOTH: 761 val |= 3 << g->intr_detection_bit; 762 val |= BIT(g->intr_polarity_bit); 763 break; 764 case IRQ_TYPE_LEVEL_LOW: 765 break; 766 case IRQ_TYPE_LEVEL_HIGH: 767 val |= BIT(g->intr_polarity_bit); 768 break; 769 } 770 } else if (g->intr_detection_width == 1) { 771 val &= ~(1 << g->intr_detection_bit); 772 val &= ~(1 << g->intr_polarity_bit); 773 switch (type) { 774 case IRQ_TYPE_EDGE_RISING: 775 val |= BIT(g->intr_detection_bit); 776 val |= BIT(g->intr_polarity_bit); 777 break; 778 case IRQ_TYPE_EDGE_FALLING: 779 val |= BIT(g->intr_detection_bit); 780 break; 781 case IRQ_TYPE_EDGE_BOTH: 782 val |= BIT(g->intr_detection_bit); 783 val |= BIT(g->intr_polarity_bit); 784 break; 785 case IRQ_TYPE_LEVEL_LOW: 786 break; 787 case IRQ_TYPE_LEVEL_HIGH: 788 val |= BIT(g->intr_polarity_bit); 789 break; 790 } 791 } else { 792 BUG(); 793 } 794 writel(val, pctrl->regs + g->intr_cfg_reg); 795 796 if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) 797 msm_gpio_update_dual_edge_pos(pctrl, g, d); 798 799 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 800 801 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) 802 irq_set_handler_locked(d, handle_level_irq); 803 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) 804 irq_set_handler_locked(d, handle_edge_irq); 805 806 return 0; 807 } 808 809 static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on) 810 { 811 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 812 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); 813 unsigned long flags; 814 815 raw_spin_lock_irqsave(&pctrl->lock, flags); 816 817 irq_set_irq_wake(pctrl->irq, on); 818 819 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 820 821 return 0; 822 } 823 824 static void msm_gpio_irq_handler(struct irq_desc *desc) 825 { 826 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 827 const struct msm_pingroup *g; 828 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); 829 struct irq_chip *chip = irq_desc_get_chip(desc); 830 int irq_pin; 831 int handled = 0; 832 u32 val; 833 int i; 834 835 chained_irq_enter(chip, desc); 836 837 /* 838 * Each pin has it's own IRQ status register, so use 839 * enabled_irq bitmap to limit the number of reads. 840 */ 841 for_each_set_bit(i, pctrl->enabled_irqs, pctrl->chip.ngpio) { 842 g = &pctrl->soc->groups[i]; 843 val = readl(pctrl->regs + g->intr_status_reg); 844 if (val & BIT(g->intr_status_bit)) { 845 irq_pin = irq_find_mapping(gc->irq.domain, i); 846 generic_handle_irq(irq_pin); 847 handled++; 848 } 849 } 850 851 /* No interrupts were flagged */ 852 if (handled == 0) 853 handle_bad_irq(desc); 854 855 chained_irq_exit(chip, desc); 856 } 857 858 static int msm_gpio_init_valid_mask(struct gpio_chip *chip, 859 struct msm_pinctrl *pctrl) 860 { 861 int ret; 862 unsigned int len, i; 863 unsigned int max_gpios = pctrl->soc->ngpios; 864 u16 *tmp; 865 866 /* The number of GPIOs in the ACPI tables */ 867 len = ret = device_property_read_u16_array(pctrl->dev, "gpios", NULL, 0); 868 if (ret < 0) 869 return 0; 870 871 if (ret > max_gpios) 872 return -EINVAL; 873 874 tmp = kmalloc_array(len, sizeof(*tmp), GFP_KERNEL); 875 if (!tmp) 876 return -ENOMEM; 877 878 ret = device_property_read_u16_array(pctrl->dev, "gpios", tmp, len); 879 if (ret < 0) { 880 dev_err(pctrl->dev, "could not read list of GPIOs\n"); 881 goto out; 882 } 883 884 bitmap_zero(chip->valid_mask, max_gpios); 885 for (i = 0; i < len; i++) 886 set_bit(tmp[i], chip->valid_mask); 887 888 out: 889 kfree(tmp); 890 return ret; 891 } 892 893 static bool msm_gpio_needs_valid_mask(struct msm_pinctrl *pctrl) 894 { 895 return device_property_read_u16_array(pctrl->dev, "gpios", NULL, 0) > 0; 896 } 897 898 static int msm_gpio_init(struct msm_pinctrl *pctrl) 899 { 900 struct gpio_chip *chip; 901 int ret; 902 unsigned ngpio = pctrl->soc->ngpios; 903 904 if (WARN_ON(ngpio > MAX_NR_GPIO)) 905 return -EINVAL; 906 907 chip = &pctrl->chip; 908 chip->base = -1; 909 chip->ngpio = ngpio; 910 chip->label = dev_name(pctrl->dev); 911 chip->parent = pctrl->dev; 912 chip->owner = THIS_MODULE; 913 chip->of_node = pctrl->dev->of_node; 914 chip->need_valid_mask = msm_gpio_needs_valid_mask(pctrl); 915 916 pctrl->irq_chip.name = "msmgpio"; 917 pctrl->irq_chip.irq_mask = msm_gpio_irq_mask; 918 pctrl->irq_chip.irq_unmask = msm_gpio_irq_unmask; 919 pctrl->irq_chip.irq_ack = msm_gpio_irq_ack; 920 pctrl->irq_chip.irq_set_type = msm_gpio_irq_set_type; 921 pctrl->irq_chip.irq_set_wake = msm_gpio_irq_set_wake; 922 923 ret = gpiochip_add_data(&pctrl->chip, pctrl); 924 if (ret) { 925 dev_err(pctrl->dev, "Failed register gpiochip\n"); 926 return ret; 927 } 928 929 ret = msm_gpio_init_valid_mask(chip, pctrl); 930 if (ret) { 931 dev_err(pctrl->dev, "Failed to setup irq valid bits\n"); 932 gpiochip_remove(&pctrl->chip); 933 return ret; 934 } 935 936 /* 937 * For DeviceTree-supported systems, the gpio core checks the 938 * pinctrl's device node for the "gpio-ranges" property. 939 * If it is present, it takes care of adding the pin ranges 940 * for the driver. In this case the driver can skip ahead. 941 * 942 * In order to remain compatible with older, existing DeviceTree 943 * files which don't set the "gpio-ranges" property or systems that 944 * utilize ACPI the driver has to call gpiochip_add_pin_range(). 945 */ 946 if (!of_property_read_bool(pctrl->dev->of_node, "gpio-ranges")) { 947 ret = gpiochip_add_pin_range(&pctrl->chip, 948 dev_name(pctrl->dev), 0, 0, chip->ngpio); 949 if (ret) { 950 dev_err(pctrl->dev, "Failed to add pin range\n"); 951 gpiochip_remove(&pctrl->chip); 952 return ret; 953 } 954 } 955 956 ret = gpiochip_irqchip_add(chip, 957 &pctrl->irq_chip, 958 0, 959 handle_edge_irq, 960 IRQ_TYPE_NONE); 961 if (ret) { 962 dev_err(pctrl->dev, "Failed to add irqchip to gpiochip\n"); 963 gpiochip_remove(&pctrl->chip); 964 return -ENOSYS; 965 } 966 967 gpiochip_set_chained_irqchip(chip, &pctrl->irq_chip, pctrl->irq, 968 msm_gpio_irq_handler); 969 970 return 0; 971 } 972 973 static int msm_ps_hold_restart(struct notifier_block *nb, unsigned long action, 974 void *data) 975 { 976 struct msm_pinctrl *pctrl = container_of(nb, struct msm_pinctrl, restart_nb); 977 978 writel(0, pctrl->regs + PS_HOLD_OFFSET); 979 mdelay(1000); 980 return NOTIFY_DONE; 981 } 982 983 static struct msm_pinctrl *poweroff_pctrl; 984 985 static void msm_ps_hold_poweroff(void) 986 { 987 msm_ps_hold_restart(&poweroff_pctrl->restart_nb, 0, NULL); 988 } 989 990 static void msm_pinctrl_setup_pm_reset(struct msm_pinctrl *pctrl) 991 { 992 int i; 993 const struct msm_function *func = pctrl->soc->functions; 994 995 for (i = 0; i < pctrl->soc->nfunctions; i++) 996 if (!strcmp(func[i].name, "ps_hold")) { 997 pctrl->restart_nb.notifier_call = msm_ps_hold_restart; 998 pctrl->restart_nb.priority = 128; 999 if (register_restart_handler(&pctrl->restart_nb)) 1000 dev_err(pctrl->dev, 1001 "failed to setup restart handler.\n"); 1002 poweroff_pctrl = pctrl; 1003 pm_power_off = msm_ps_hold_poweroff; 1004 break; 1005 } 1006 } 1007 1008 int msm_pinctrl_probe(struct platform_device *pdev, 1009 const struct msm_pinctrl_soc_data *soc_data) 1010 { 1011 struct msm_pinctrl *pctrl; 1012 struct resource *res; 1013 int ret; 1014 1015 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); 1016 if (!pctrl) 1017 return -ENOMEM; 1018 1019 pctrl->dev = &pdev->dev; 1020 pctrl->soc = soc_data; 1021 pctrl->chip = msm_gpio_template; 1022 1023 raw_spin_lock_init(&pctrl->lock); 1024 1025 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1026 pctrl->regs = devm_ioremap_resource(&pdev->dev, res); 1027 if (IS_ERR(pctrl->regs)) 1028 return PTR_ERR(pctrl->regs); 1029 1030 msm_pinctrl_setup_pm_reset(pctrl); 1031 1032 pctrl->irq = platform_get_irq(pdev, 0); 1033 if (pctrl->irq < 0) { 1034 dev_err(&pdev->dev, "No interrupt defined for msmgpio\n"); 1035 return pctrl->irq; 1036 } 1037 1038 pctrl->desc.owner = THIS_MODULE; 1039 pctrl->desc.pctlops = &msm_pinctrl_ops; 1040 pctrl->desc.pmxops = &msm_pinmux_ops; 1041 pctrl->desc.confops = &msm_pinconf_ops; 1042 pctrl->desc.name = dev_name(&pdev->dev); 1043 pctrl->desc.pins = pctrl->soc->pins; 1044 pctrl->desc.npins = pctrl->soc->npins; 1045 1046 pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &pctrl->desc, pctrl); 1047 if (IS_ERR(pctrl->pctrl)) { 1048 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); 1049 return PTR_ERR(pctrl->pctrl); 1050 } 1051 1052 ret = msm_gpio_init(pctrl); 1053 if (ret) 1054 return ret; 1055 1056 platform_set_drvdata(pdev, pctrl); 1057 1058 dev_dbg(&pdev->dev, "Probed Qualcomm pinctrl driver\n"); 1059 1060 return 0; 1061 } 1062 EXPORT_SYMBOL(msm_pinctrl_probe); 1063 1064 int msm_pinctrl_remove(struct platform_device *pdev) 1065 { 1066 struct msm_pinctrl *pctrl = platform_get_drvdata(pdev); 1067 1068 gpiochip_remove(&pctrl->chip); 1069 1070 unregister_restart_handler(&pctrl->restart_nb); 1071 1072 return 0; 1073 } 1074 EXPORT_SYMBOL(msm_pinctrl_remove); 1075 1076