1 /*
2  * Copyright (c) 2013, Sony Mobile Communications AB.
3  * Copyright (c) 2013, The Linux Foundation. All rights reserved.
4  *
5  * This program is free software; you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License version 2 and
7  * only version 2 as published by the Free Software Foundation.
8  *
9  * This program is distributed in the hope that it will be useful,
10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12  * GNU General Public License for more details.
13  */
14 
15 #include <linux/delay.h>
16 #include <linux/err.h>
17 #include <linux/io.h>
18 #include <linux/module.h>
19 #include <linux/of.h>
20 #include <linux/platform_device.h>
21 #include <linux/pinctrl/machine.h>
22 #include <linux/pinctrl/pinctrl.h>
23 #include <linux/pinctrl/pinmux.h>
24 #include <linux/pinctrl/pinconf.h>
25 #include <linux/pinctrl/pinconf-generic.h>
26 #include <linux/slab.h>
27 #include <linux/gpio/driver.h>
28 #include <linux/interrupt.h>
29 #include <linux/spinlock.h>
30 #include <linux/reboot.h>
31 #include <linux/pm.h>
32 #include <linux/log2.h>
33 
34 #include "../core.h"
35 #include "../pinconf.h"
36 #include "pinctrl-msm.h"
37 #include "../pinctrl-utils.h"
38 
39 #define MAX_NR_GPIO 300
40 #define MAX_NR_TILES 4
41 #define PS_HOLD_OFFSET 0x820
42 
43 /**
44  * struct msm_pinctrl - state for a pinctrl-msm device
45  * @dev:            device handle.
46  * @pctrl:          pinctrl handle.
47  * @chip:           gpiochip handle.
48  * @restart_nb:     restart notifier block.
49  * @irq:            parent irq for the TLMM irq_chip.
50  * @lock:           Spinlock to protect register resources as well
51  *                  as msm_pinctrl data structures.
52  * @enabled_irqs:   Bitmap of currently enabled irqs.
53  * @dual_edge_irqs: Bitmap of irqs that need sw emulated dual edge
54  *                  detection.
55  * @soc;            Reference to soc_data of platform specific data.
56  * @regs:           Base addresses for the TLMM tiles.
57  */
58 struct msm_pinctrl {
59 	struct device *dev;
60 	struct pinctrl_dev *pctrl;
61 	struct gpio_chip chip;
62 	struct pinctrl_desc desc;
63 	struct notifier_block restart_nb;
64 
65 	struct irq_chip irq_chip;
66 	int irq;
67 
68 	raw_spinlock_t lock;
69 
70 	DECLARE_BITMAP(dual_edge_irqs, MAX_NR_GPIO);
71 	DECLARE_BITMAP(enabled_irqs, MAX_NR_GPIO);
72 
73 	const struct msm_pinctrl_soc_data *soc;
74 	void __iomem *regs[MAX_NR_TILES];
75 };
76 
77 #define MSM_ACCESSOR(name) \
78 static u32 msm_readl_##name(struct msm_pinctrl *pctrl, \
79 			    const struct msm_pingroup *g) \
80 { \
81 	return readl(pctrl->regs[g->tile] + g->name##_reg); \
82 } \
83 static void msm_writel_##name(u32 val, struct msm_pinctrl *pctrl, \
84 			      const struct msm_pingroup *g) \
85 { \
86 	writel(val, pctrl->regs[g->tile] + g->name##_reg); \
87 }
88 
89 MSM_ACCESSOR(ctl)
90 MSM_ACCESSOR(io)
91 MSM_ACCESSOR(intr_cfg)
92 MSM_ACCESSOR(intr_status)
93 MSM_ACCESSOR(intr_target)
94 
95 static int msm_get_groups_count(struct pinctrl_dev *pctldev)
96 {
97 	struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
98 
99 	return pctrl->soc->ngroups;
100 }
101 
102 static const char *msm_get_group_name(struct pinctrl_dev *pctldev,
103 				      unsigned group)
104 {
105 	struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
106 
107 	return pctrl->soc->groups[group].name;
108 }
109 
110 static int msm_get_group_pins(struct pinctrl_dev *pctldev,
111 			      unsigned group,
112 			      const unsigned **pins,
113 			      unsigned *num_pins)
114 {
115 	struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
116 
117 	*pins = pctrl->soc->groups[group].pins;
118 	*num_pins = pctrl->soc->groups[group].npins;
119 	return 0;
120 }
121 
122 static const struct pinctrl_ops msm_pinctrl_ops = {
123 	.get_groups_count	= msm_get_groups_count,
124 	.get_group_name		= msm_get_group_name,
125 	.get_group_pins		= msm_get_group_pins,
126 	.dt_node_to_map		= pinconf_generic_dt_node_to_map_group,
127 	.dt_free_map		= pinctrl_utils_free_map,
128 };
129 
130 static int msm_pinmux_request(struct pinctrl_dev *pctldev, unsigned offset)
131 {
132 	struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
133 	struct gpio_chip *chip = &pctrl->chip;
134 
135 	return gpiochip_line_is_valid(chip, offset) ? 0 : -EINVAL;
136 }
137 
138 static int msm_get_functions_count(struct pinctrl_dev *pctldev)
139 {
140 	struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
141 
142 	return pctrl->soc->nfunctions;
143 }
144 
145 static const char *msm_get_function_name(struct pinctrl_dev *pctldev,
146 					 unsigned function)
147 {
148 	struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
149 
150 	return pctrl->soc->functions[function].name;
151 }
152 
153 static int msm_get_function_groups(struct pinctrl_dev *pctldev,
154 				   unsigned function,
155 				   const char * const **groups,
156 				   unsigned * const num_groups)
157 {
158 	struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
159 
160 	*groups = pctrl->soc->functions[function].groups;
161 	*num_groups = pctrl->soc->functions[function].ngroups;
162 	return 0;
163 }
164 
165 static int msm_pinmux_set_mux(struct pinctrl_dev *pctldev,
166 			      unsigned function,
167 			      unsigned group)
168 {
169 	struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
170 	const struct msm_pingroup *g;
171 	unsigned long flags;
172 	u32 val, mask;
173 	int i;
174 
175 	g = &pctrl->soc->groups[group];
176 	mask = GENMASK(g->mux_bit + order_base_2(g->nfuncs) - 1, g->mux_bit);
177 
178 	for (i = 0; i < g->nfuncs; i++) {
179 		if (g->funcs[i] == function)
180 			break;
181 	}
182 
183 	if (WARN_ON(i == g->nfuncs))
184 		return -EINVAL;
185 
186 	raw_spin_lock_irqsave(&pctrl->lock, flags);
187 
188 	val = msm_readl_ctl(pctrl, g);
189 	val &= ~mask;
190 	val |= i << g->mux_bit;
191 	msm_writel_ctl(val, pctrl, g);
192 
193 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
194 
195 	return 0;
196 }
197 
198 static int msm_pinmux_request_gpio(struct pinctrl_dev *pctldev,
199 				   struct pinctrl_gpio_range *range,
200 				   unsigned offset)
201 {
202 	struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
203 	const struct msm_pingroup *g = &pctrl->soc->groups[offset];
204 
205 	/* No funcs? Probably ACPI so can't do anything here */
206 	if (!g->nfuncs)
207 		return 0;
208 
209 	/* For now assume function 0 is GPIO because it always is */
210 	return msm_pinmux_set_mux(pctldev, g->funcs[0], offset);
211 }
212 
213 static const struct pinmux_ops msm_pinmux_ops = {
214 	.request		= msm_pinmux_request,
215 	.get_functions_count	= msm_get_functions_count,
216 	.get_function_name	= msm_get_function_name,
217 	.get_function_groups	= msm_get_function_groups,
218 	.gpio_request_enable	= msm_pinmux_request_gpio,
219 	.set_mux		= msm_pinmux_set_mux,
220 };
221 
222 static int msm_config_reg(struct msm_pinctrl *pctrl,
223 			  const struct msm_pingroup *g,
224 			  unsigned param,
225 			  unsigned *mask,
226 			  unsigned *bit)
227 {
228 	switch (param) {
229 	case PIN_CONFIG_BIAS_DISABLE:
230 	case PIN_CONFIG_BIAS_PULL_DOWN:
231 	case PIN_CONFIG_BIAS_BUS_HOLD:
232 	case PIN_CONFIG_BIAS_PULL_UP:
233 		*bit = g->pull_bit;
234 		*mask = 3;
235 		break;
236 	case PIN_CONFIG_DRIVE_STRENGTH:
237 		*bit = g->drv_bit;
238 		*mask = 7;
239 		break;
240 	case PIN_CONFIG_OUTPUT:
241 	case PIN_CONFIG_INPUT_ENABLE:
242 		*bit = g->oe_bit;
243 		*mask = 1;
244 		break;
245 	default:
246 		return -ENOTSUPP;
247 	}
248 
249 	return 0;
250 }
251 
252 #define MSM_NO_PULL		0
253 #define MSM_PULL_DOWN		1
254 #define MSM_KEEPER		2
255 #define MSM_PULL_UP_NO_KEEPER	2
256 #define MSM_PULL_UP		3
257 
258 static unsigned msm_regval_to_drive(u32 val)
259 {
260 	return (val + 1) * 2;
261 }
262 
263 static int msm_config_group_get(struct pinctrl_dev *pctldev,
264 				unsigned int group,
265 				unsigned long *config)
266 {
267 	const struct msm_pingroup *g;
268 	struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
269 	unsigned param = pinconf_to_config_param(*config);
270 	unsigned mask;
271 	unsigned arg;
272 	unsigned bit;
273 	int ret;
274 	u32 val;
275 
276 	g = &pctrl->soc->groups[group];
277 
278 	ret = msm_config_reg(pctrl, g, param, &mask, &bit);
279 	if (ret < 0)
280 		return ret;
281 
282 	val = msm_readl_ctl(pctrl, g);
283 	arg = (val >> bit) & mask;
284 
285 	/* Convert register value to pinconf value */
286 	switch (param) {
287 	case PIN_CONFIG_BIAS_DISABLE:
288 		if (arg != MSM_NO_PULL)
289 			return -EINVAL;
290 		arg = 1;
291 		break;
292 	case PIN_CONFIG_BIAS_PULL_DOWN:
293 		if (arg != MSM_PULL_DOWN)
294 			return -EINVAL;
295 		arg = 1;
296 		break;
297 	case PIN_CONFIG_BIAS_BUS_HOLD:
298 		if (pctrl->soc->pull_no_keeper)
299 			return -ENOTSUPP;
300 
301 		if (arg != MSM_KEEPER)
302 			return -EINVAL;
303 		arg = 1;
304 		break;
305 	case PIN_CONFIG_BIAS_PULL_UP:
306 		if (pctrl->soc->pull_no_keeper)
307 			arg = arg == MSM_PULL_UP_NO_KEEPER;
308 		else
309 			arg = arg == MSM_PULL_UP;
310 		if (!arg)
311 			return -EINVAL;
312 		break;
313 	case PIN_CONFIG_DRIVE_STRENGTH:
314 		arg = msm_regval_to_drive(arg);
315 		break;
316 	case PIN_CONFIG_OUTPUT:
317 		/* Pin is not output */
318 		if (!arg)
319 			return -EINVAL;
320 
321 		val = msm_readl_io(pctrl, g);
322 		arg = !!(val & BIT(g->in_bit));
323 		break;
324 	case PIN_CONFIG_INPUT_ENABLE:
325 		/* Pin is output */
326 		if (arg)
327 			return -EINVAL;
328 		arg = 1;
329 		break;
330 	default:
331 		return -ENOTSUPP;
332 	}
333 
334 	*config = pinconf_to_config_packed(param, arg);
335 
336 	return 0;
337 }
338 
339 static int msm_config_group_set(struct pinctrl_dev *pctldev,
340 				unsigned group,
341 				unsigned long *configs,
342 				unsigned num_configs)
343 {
344 	const struct msm_pingroup *g;
345 	struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
346 	unsigned long flags;
347 	unsigned param;
348 	unsigned mask;
349 	unsigned arg;
350 	unsigned bit;
351 	int ret;
352 	u32 val;
353 	int i;
354 
355 	g = &pctrl->soc->groups[group];
356 
357 	for (i = 0; i < num_configs; i++) {
358 		param = pinconf_to_config_param(configs[i]);
359 		arg = pinconf_to_config_argument(configs[i]);
360 
361 		ret = msm_config_reg(pctrl, g, param, &mask, &bit);
362 		if (ret < 0)
363 			return ret;
364 
365 		/* Convert pinconf values to register values */
366 		switch (param) {
367 		case PIN_CONFIG_BIAS_DISABLE:
368 			arg = MSM_NO_PULL;
369 			break;
370 		case PIN_CONFIG_BIAS_PULL_DOWN:
371 			arg = MSM_PULL_DOWN;
372 			break;
373 		case PIN_CONFIG_BIAS_BUS_HOLD:
374 			if (pctrl->soc->pull_no_keeper)
375 				return -ENOTSUPP;
376 
377 			arg = MSM_KEEPER;
378 			break;
379 		case PIN_CONFIG_BIAS_PULL_UP:
380 			if (pctrl->soc->pull_no_keeper)
381 				arg = MSM_PULL_UP_NO_KEEPER;
382 			else
383 				arg = MSM_PULL_UP;
384 			break;
385 		case PIN_CONFIG_DRIVE_STRENGTH:
386 			/* Check for invalid values */
387 			if (arg > 16 || arg < 2 || (arg % 2) != 0)
388 				arg = -1;
389 			else
390 				arg = (arg / 2) - 1;
391 			break;
392 		case PIN_CONFIG_OUTPUT:
393 			/* set output value */
394 			raw_spin_lock_irqsave(&pctrl->lock, flags);
395 			val = msm_readl_io(pctrl, g);
396 			if (arg)
397 				val |= BIT(g->out_bit);
398 			else
399 				val &= ~BIT(g->out_bit);
400 			msm_writel_io(val, pctrl, g);
401 			raw_spin_unlock_irqrestore(&pctrl->lock, flags);
402 
403 			/* enable output */
404 			arg = 1;
405 			break;
406 		case PIN_CONFIG_INPUT_ENABLE:
407 			/* disable output */
408 			arg = 0;
409 			break;
410 		default:
411 			dev_err(pctrl->dev, "Unsupported config parameter: %x\n",
412 				param);
413 			return -EINVAL;
414 		}
415 
416 		/* Range-check user-supplied value */
417 		if (arg & ~mask) {
418 			dev_err(pctrl->dev, "config %x: %x is invalid\n", param, arg);
419 			return -EINVAL;
420 		}
421 
422 		raw_spin_lock_irqsave(&pctrl->lock, flags);
423 		val = msm_readl_ctl(pctrl, g);
424 		val &= ~(mask << bit);
425 		val |= arg << bit;
426 		msm_writel_ctl(val, pctrl, g);
427 		raw_spin_unlock_irqrestore(&pctrl->lock, flags);
428 	}
429 
430 	return 0;
431 }
432 
433 static const struct pinconf_ops msm_pinconf_ops = {
434 	.is_generic		= true,
435 	.pin_config_group_get	= msm_config_group_get,
436 	.pin_config_group_set	= msm_config_group_set,
437 };
438 
439 static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
440 {
441 	const struct msm_pingroup *g;
442 	struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
443 	unsigned long flags;
444 	u32 val;
445 
446 	g = &pctrl->soc->groups[offset];
447 
448 	raw_spin_lock_irqsave(&pctrl->lock, flags);
449 
450 	val = msm_readl_ctl(pctrl, g);
451 	val &= ~BIT(g->oe_bit);
452 	msm_writel_ctl(val, pctrl, g);
453 
454 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
455 
456 	return 0;
457 }
458 
459 static int msm_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value)
460 {
461 	const struct msm_pingroup *g;
462 	struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
463 	unsigned long flags;
464 	u32 val;
465 
466 	g = &pctrl->soc->groups[offset];
467 
468 	raw_spin_lock_irqsave(&pctrl->lock, flags);
469 
470 	val = msm_readl_io(pctrl, g);
471 	if (value)
472 		val |= BIT(g->out_bit);
473 	else
474 		val &= ~BIT(g->out_bit);
475 	msm_writel_io(val, pctrl, g);
476 
477 	val = msm_readl_ctl(pctrl, g);
478 	val |= BIT(g->oe_bit);
479 	msm_writel_ctl(val, pctrl, g);
480 
481 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
482 
483 	return 0;
484 }
485 
486 static int msm_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
487 {
488 	struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
489 	const struct msm_pingroup *g;
490 	u32 val;
491 
492 	g = &pctrl->soc->groups[offset];
493 
494 	val = msm_readl_ctl(pctrl, g);
495 
496 	/* 0 = output, 1 = input */
497 	return val & BIT(g->oe_bit) ? 0 : 1;
498 }
499 
500 static int msm_gpio_get(struct gpio_chip *chip, unsigned offset)
501 {
502 	const struct msm_pingroup *g;
503 	struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
504 	u32 val;
505 
506 	g = &pctrl->soc->groups[offset];
507 
508 	val = msm_readl_io(pctrl, g);
509 	return !!(val & BIT(g->in_bit));
510 }
511 
512 static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
513 {
514 	const struct msm_pingroup *g;
515 	struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
516 	unsigned long flags;
517 	u32 val;
518 
519 	g = &pctrl->soc->groups[offset];
520 
521 	raw_spin_lock_irqsave(&pctrl->lock, flags);
522 
523 	val = msm_readl_io(pctrl, g);
524 	if (value)
525 		val |= BIT(g->out_bit);
526 	else
527 		val &= ~BIT(g->out_bit);
528 	msm_writel_io(val, pctrl, g);
529 
530 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
531 }
532 
533 #ifdef CONFIG_DEBUG_FS
534 #include <linux/seq_file.h>
535 
536 static void msm_gpio_dbg_show_one(struct seq_file *s,
537 				  struct pinctrl_dev *pctldev,
538 				  struct gpio_chip *chip,
539 				  unsigned offset,
540 				  unsigned gpio)
541 {
542 	const struct msm_pingroup *g;
543 	struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
544 	unsigned func;
545 	int is_out;
546 	int drive;
547 	int pull;
548 	int val;
549 	u32 ctl_reg, io_reg;
550 
551 	static const char * const pulls_keeper[] = {
552 		"no pull",
553 		"pull down",
554 		"keeper",
555 		"pull up"
556 	};
557 
558 	static const char * const pulls_no_keeper[] = {
559 		"no pull",
560 		"pull down",
561 		"pull up",
562 	};
563 
564 	if (!gpiochip_line_is_valid(chip, offset))
565 		return;
566 
567 	g = &pctrl->soc->groups[offset];
568 	ctl_reg = msm_readl_ctl(pctrl, g);
569 	io_reg = msm_readl_io(pctrl, g);
570 
571 	is_out = !!(ctl_reg & BIT(g->oe_bit));
572 	func = (ctl_reg >> g->mux_bit) & 7;
573 	drive = (ctl_reg >> g->drv_bit) & 7;
574 	pull = (ctl_reg >> g->pull_bit) & 3;
575 
576 	if (is_out)
577 		val = !!(io_reg & BIT(g->out_bit));
578 	else
579 		val = !!(io_reg & BIT(g->in_bit));
580 
581 	seq_printf(s, " %-8s: %-3s", g->name, is_out ? "out" : "in");
582 	seq_printf(s, " %-4s func%d", val ? "high" : "low", func);
583 	seq_printf(s, " %dmA", msm_regval_to_drive(drive));
584 	if (pctrl->soc->pull_no_keeper)
585 		seq_printf(s, " %s", pulls_no_keeper[pull]);
586 	else
587 		seq_printf(s, " %s", pulls_keeper[pull]);
588 	seq_puts(s, "\n");
589 }
590 
591 static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
592 {
593 	unsigned gpio = chip->base;
594 	unsigned i;
595 
596 	for (i = 0; i < chip->ngpio; i++, gpio++)
597 		msm_gpio_dbg_show_one(s, NULL, chip, i, gpio);
598 }
599 
600 #else
601 #define msm_gpio_dbg_show NULL
602 #endif
603 
604 static int msm_gpio_init_valid_mask(struct gpio_chip *chip)
605 {
606 	struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
607 	int ret;
608 	unsigned int len, i;
609 	unsigned int max_gpios = pctrl->soc->ngpios;
610 	u16 *tmp;
611 
612 	/* The number of GPIOs in the ACPI tables */
613 	len = ret = device_property_read_u16_array(pctrl->dev, "gpios", NULL,
614 						   0);
615 	if (ret < 0)
616 		return 0;
617 
618 	if (ret > max_gpios)
619 		return -EINVAL;
620 
621 	tmp = kmalloc_array(len, sizeof(*tmp), GFP_KERNEL);
622 	if (!tmp)
623 		return -ENOMEM;
624 
625 	ret = device_property_read_u16_array(pctrl->dev, "gpios", tmp, len);
626 	if (ret < 0) {
627 		dev_err(pctrl->dev, "could not read list of GPIOs\n");
628 		goto out;
629 	}
630 
631 	bitmap_zero(chip->valid_mask, max_gpios);
632 	for (i = 0; i < len; i++)
633 		set_bit(tmp[i], chip->valid_mask);
634 
635 out:
636 	kfree(tmp);
637 	return ret;
638 }
639 
640 static const struct gpio_chip msm_gpio_template = {
641 	.direction_input  = msm_gpio_direction_input,
642 	.direction_output = msm_gpio_direction_output,
643 	.get_direction    = msm_gpio_get_direction,
644 	.get              = msm_gpio_get,
645 	.set              = msm_gpio_set,
646 	.request          = gpiochip_generic_request,
647 	.free             = gpiochip_generic_free,
648 	.dbg_show         = msm_gpio_dbg_show,
649 	.init_valid_mask  = msm_gpio_init_valid_mask,
650 };
651 
652 /* For dual-edge interrupts in software, since some hardware has no
653  * such support:
654  *
655  * At appropriate moments, this function may be called to flip the polarity
656  * settings of both-edge irq lines to try and catch the next edge.
657  *
658  * The attempt is considered successful if:
659  * - the status bit goes high, indicating that an edge was caught, or
660  * - the input value of the gpio doesn't change during the attempt.
661  * If the value changes twice during the process, that would cause the first
662  * test to fail but would force the second, as two opposite
663  * transitions would cause a detection no matter the polarity setting.
664  *
665  * The do-loop tries to sledge-hammer closed the timing hole between
666  * the initial value-read and the polarity-write - if the line value changes
667  * during that window, an interrupt is lost, the new polarity setting is
668  * incorrect, and the first success test will fail, causing a retry.
669  *
670  * Algorithm comes from Google's msmgpio driver.
671  */
672 static void msm_gpio_update_dual_edge_pos(struct msm_pinctrl *pctrl,
673 					  const struct msm_pingroup *g,
674 					  struct irq_data *d)
675 {
676 	int loop_limit = 100;
677 	unsigned val, val2, intstat;
678 	unsigned pol;
679 
680 	do {
681 		val = msm_readl_io(pctrl, g) & BIT(g->in_bit);
682 
683 		pol = msm_readl_intr_cfg(pctrl, g);
684 		pol ^= BIT(g->intr_polarity_bit);
685 		msm_writel_intr_cfg(val, pctrl, g);
686 
687 		val2 = msm_readl_io(pctrl, g) & BIT(g->in_bit);
688 		intstat = msm_readl_intr_status(pctrl, g);
689 		if (intstat || (val == val2))
690 			return;
691 	} while (loop_limit-- > 0);
692 	dev_err(pctrl->dev, "dual-edge irq failed to stabilize, %#08x != %#08x\n",
693 		val, val2);
694 }
695 
696 static void msm_gpio_irq_mask(struct irq_data *d)
697 {
698 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
699 	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
700 	const struct msm_pingroup *g;
701 	unsigned long flags;
702 	u32 val;
703 
704 	g = &pctrl->soc->groups[d->hwirq];
705 
706 	raw_spin_lock_irqsave(&pctrl->lock, flags);
707 
708 	val = msm_readl_intr_cfg(pctrl, g);
709 	/*
710 	 * There are two bits that control interrupt forwarding to the CPU. The
711 	 * RAW_STATUS_EN bit causes the level or edge sensed on the line to be
712 	 * latched into the interrupt status register when the hardware detects
713 	 * an irq that it's configured for (either edge for edge type or level
714 	 * for level type irq). The 'non-raw' status enable bit causes the
715 	 * hardware to assert the summary interrupt to the CPU if the latched
716 	 * status bit is set. There's a bug though, the edge detection logic
717 	 * seems to have a problem where toggling the RAW_STATUS_EN bit may
718 	 * cause the status bit to latch spuriously when there isn't any edge
719 	 * so we can't touch that bit for edge type irqs and we have to keep
720 	 * the bit set anyway so that edges are latched while the line is masked.
721 	 *
722 	 * To make matters more complicated, leaving the RAW_STATUS_EN bit
723 	 * enabled all the time causes level interrupts to re-latch into the
724 	 * status register because the level is still present on the line after
725 	 * we ack it. We clear the raw status enable bit during mask here and
726 	 * set the bit on unmask so the interrupt can't latch into the hardware
727 	 * while it's masked.
728 	 */
729 	if (irqd_get_trigger_type(d) & IRQ_TYPE_LEVEL_MASK)
730 		val &= ~BIT(g->intr_raw_status_bit);
731 
732 	val &= ~BIT(g->intr_enable_bit);
733 	msm_writel_intr_cfg(val, pctrl, g);
734 
735 	clear_bit(d->hwirq, pctrl->enabled_irqs);
736 
737 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
738 }
739 
740 static void msm_gpio_irq_unmask(struct irq_data *d)
741 {
742 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
743 	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
744 	const struct msm_pingroup *g;
745 	unsigned long flags;
746 	u32 val;
747 
748 	g = &pctrl->soc->groups[d->hwirq];
749 
750 	raw_spin_lock_irqsave(&pctrl->lock, flags);
751 
752 	val = msm_readl_intr_cfg(pctrl, g);
753 	val |= BIT(g->intr_raw_status_bit);
754 	val |= BIT(g->intr_enable_bit);
755 	msm_writel_intr_cfg(val, pctrl, g);
756 
757 	set_bit(d->hwirq, pctrl->enabled_irqs);
758 
759 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
760 }
761 
762 static void msm_gpio_irq_ack(struct irq_data *d)
763 {
764 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
765 	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
766 	const struct msm_pingroup *g;
767 	unsigned long flags;
768 	u32 val;
769 
770 	g = &pctrl->soc->groups[d->hwirq];
771 
772 	raw_spin_lock_irqsave(&pctrl->lock, flags);
773 
774 	val = msm_readl_intr_status(pctrl, g);
775 	if (g->intr_ack_high)
776 		val |= BIT(g->intr_status_bit);
777 	else
778 		val &= ~BIT(g->intr_status_bit);
779 	msm_writel_intr_status(val, pctrl, g);
780 
781 	if (test_bit(d->hwirq, pctrl->dual_edge_irqs))
782 		msm_gpio_update_dual_edge_pos(pctrl, g, d);
783 
784 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
785 }
786 
787 static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type)
788 {
789 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
790 	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
791 	const struct msm_pingroup *g;
792 	unsigned long flags;
793 	u32 val;
794 
795 	g = &pctrl->soc->groups[d->hwirq];
796 
797 	raw_spin_lock_irqsave(&pctrl->lock, flags);
798 
799 	/*
800 	 * For hw without possibility of detecting both edges
801 	 */
802 	if (g->intr_detection_width == 1 && type == IRQ_TYPE_EDGE_BOTH)
803 		set_bit(d->hwirq, pctrl->dual_edge_irqs);
804 	else
805 		clear_bit(d->hwirq, pctrl->dual_edge_irqs);
806 
807 	/* Route interrupts to application cpu */
808 	val = msm_readl_intr_target(pctrl, g);
809 	val &= ~(7 << g->intr_target_bit);
810 	val |= g->intr_target_kpss_val << g->intr_target_bit;
811 	msm_writel_intr_target(val, pctrl, g);
812 
813 	/* Update configuration for gpio.
814 	 * RAW_STATUS_EN is left on for all gpio irqs. Due to the
815 	 * internal circuitry of TLMM, toggling the RAW_STATUS
816 	 * could cause the INTR_STATUS to be set for EDGE interrupts.
817 	 */
818 	val = msm_readl_intr_cfg(pctrl, g);
819 	val |= BIT(g->intr_raw_status_bit);
820 	if (g->intr_detection_width == 2) {
821 		val &= ~(3 << g->intr_detection_bit);
822 		val &= ~(1 << g->intr_polarity_bit);
823 		switch (type) {
824 		case IRQ_TYPE_EDGE_RISING:
825 			val |= 1 << g->intr_detection_bit;
826 			val |= BIT(g->intr_polarity_bit);
827 			break;
828 		case IRQ_TYPE_EDGE_FALLING:
829 			val |= 2 << g->intr_detection_bit;
830 			val |= BIT(g->intr_polarity_bit);
831 			break;
832 		case IRQ_TYPE_EDGE_BOTH:
833 			val |= 3 << g->intr_detection_bit;
834 			val |= BIT(g->intr_polarity_bit);
835 			break;
836 		case IRQ_TYPE_LEVEL_LOW:
837 			break;
838 		case IRQ_TYPE_LEVEL_HIGH:
839 			val |= BIT(g->intr_polarity_bit);
840 			break;
841 		}
842 	} else if (g->intr_detection_width == 1) {
843 		val &= ~(1 << g->intr_detection_bit);
844 		val &= ~(1 << g->intr_polarity_bit);
845 		switch (type) {
846 		case IRQ_TYPE_EDGE_RISING:
847 			val |= BIT(g->intr_detection_bit);
848 			val |= BIT(g->intr_polarity_bit);
849 			break;
850 		case IRQ_TYPE_EDGE_FALLING:
851 			val |= BIT(g->intr_detection_bit);
852 			break;
853 		case IRQ_TYPE_EDGE_BOTH:
854 			val |= BIT(g->intr_detection_bit);
855 			val |= BIT(g->intr_polarity_bit);
856 			break;
857 		case IRQ_TYPE_LEVEL_LOW:
858 			break;
859 		case IRQ_TYPE_LEVEL_HIGH:
860 			val |= BIT(g->intr_polarity_bit);
861 			break;
862 		}
863 	} else {
864 		BUG();
865 	}
866 	msm_writel_intr_cfg(val, pctrl, g);
867 
868 	if (test_bit(d->hwirq, pctrl->dual_edge_irqs))
869 		msm_gpio_update_dual_edge_pos(pctrl, g, d);
870 
871 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
872 
873 	if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
874 		irq_set_handler_locked(d, handle_level_irq);
875 	else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
876 		irq_set_handler_locked(d, handle_edge_irq);
877 
878 	return 0;
879 }
880 
881 static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
882 {
883 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
884 	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
885 	unsigned long flags;
886 
887 	raw_spin_lock_irqsave(&pctrl->lock, flags);
888 
889 	irq_set_irq_wake(pctrl->irq, on);
890 
891 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
892 
893 	return 0;
894 }
895 
896 static int msm_gpio_irq_reqres(struct irq_data *d)
897 {
898 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
899 	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
900 	int ret;
901 
902 	if (!try_module_get(gc->owner))
903 		return -ENODEV;
904 
905 	ret = msm_pinmux_request_gpio(pctrl->pctrl, NULL, d->hwirq);
906 	if (ret)
907 		goto out;
908 	msm_gpio_direction_input(gc, d->hwirq);
909 
910 	if (gpiochip_lock_as_irq(gc, d->hwirq)) {
911 		dev_err(gc->parent,
912 			"unable to lock HW IRQ %lu for IRQ\n",
913 			d->hwirq);
914 		ret = -EINVAL;
915 		goto out;
916 	}
917 	return 0;
918 out:
919 	module_put(gc->owner);
920 	return ret;
921 }
922 
923 static void msm_gpio_irq_relres(struct irq_data *d)
924 {
925 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
926 
927 	gpiochip_unlock_as_irq(gc, d->hwirq);
928 	module_put(gc->owner);
929 }
930 
931 static void msm_gpio_irq_handler(struct irq_desc *desc)
932 {
933 	struct gpio_chip *gc = irq_desc_get_handler_data(desc);
934 	const struct msm_pingroup *g;
935 	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
936 	struct irq_chip *chip = irq_desc_get_chip(desc);
937 	int irq_pin;
938 	int handled = 0;
939 	u32 val;
940 	int i;
941 
942 	chained_irq_enter(chip, desc);
943 
944 	/*
945 	 * Each pin has it's own IRQ status register, so use
946 	 * enabled_irq bitmap to limit the number of reads.
947 	 */
948 	for_each_set_bit(i, pctrl->enabled_irqs, pctrl->chip.ngpio) {
949 		g = &pctrl->soc->groups[i];
950 		val = msm_readl_intr_status(pctrl, g);
951 		if (val & BIT(g->intr_status_bit)) {
952 			irq_pin = irq_find_mapping(gc->irq.domain, i);
953 			generic_handle_irq(irq_pin);
954 			handled++;
955 		}
956 	}
957 
958 	/* No interrupts were flagged */
959 	if (handled == 0)
960 		handle_bad_irq(desc);
961 
962 	chained_irq_exit(chip, desc);
963 }
964 
965 static bool msm_gpio_needs_valid_mask(struct msm_pinctrl *pctrl)
966 {
967 	return device_property_read_u16_array(pctrl->dev, "gpios", NULL, 0) > 0;
968 }
969 
970 static int msm_gpio_init(struct msm_pinctrl *pctrl)
971 {
972 	struct gpio_chip *chip;
973 	int ret;
974 	unsigned ngpio = pctrl->soc->ngpios;
975 
976 	if (WARN_ON(ngpio > MAX_NR_GPIO))
977 		return -EINVAL;
978 
979 	chip = &pctrl->chip;
980 	chip->base = -1;
981 	chip->ngpio = ngpio;
982 	chip->label = dev_name(pctrl->dev);
983 	chip->parent = pctrl->dev;
984 	chip->owner = THIS_MODULE;
985 	chip->of_node = pctrl->dev->of_node;
986 	chip->need_valid_mask = msm_gpio_needs_valid_mask(pctrl);
987 
988 	pctrl->irq_chip.name = "msmgpio";
989 	pctrl->irq_chip.irq_mask = msm_gpio_irq_mask;
990 	pctrl->irq_chip.irq_unmask = msm_gpio_irq_unmask;
991 	pctrl->irq_chip.irq_ack = msm_gpio_irq_ack;
992 	pctrl->irq_chip.irq_set_type = msm_gpio_irq_set_type;
993 	pctrl->irq_chip.irq_set_wake = msm_gpio_irq_set_wake;
994 	pctrl->irq_chip.irq_request_resources = msm_gpio_irq_reqres;
995 	pctrl->irq_chip.irq_release_resources = msm_gpio_irq_relres;
996 
997 	ret = gpiochip_add_data(&pctrl->chip, pctrl);
998 	if (ret) {
999 		dev_err(pctrl->dev, "Failed register gpiochip\n");
1000 		return ret;
1001 	}
1002 
1003 	/*
1004 	 * For DeviceTree-supported systems, the gpio core checks the
1005 	 * pinctrl's device node for the "gpio-ranges" property.
1006 	 * If it is present, it takes care of adding the pin ranges
1007 	 * for the driver. In this case the driver can skip ahead.
1008 	 *
1009 	 * In order to remain compatible with older, existing DeviceTree
1010 	 * files which don't set the "gpio-ranges" property or systems that
1011 	 * utilize ACPI the driver has to call gpiochip_add_pin_range().
1012 	 */
1013 	if (!of_property_read_bool(pctrl->dev->of_node, "gpio-ranges")) {
1014 		ret = gpiochip_add_pin_range(&pctrl->chip,
1015 			dev_name(pctrl->dev), 0, 0, chip->ngpio);
1016 		if (ret) {
1017 			dev_err(pctrl->dev, "Failed to add pin range\n");
1018 			gpiochip_remove(&pctrl->chip);
1019 			return ret;
1020 		}
1021 	}
1022 
1023 	ret = gpiochip_irqchip_add(chip,
1024 				   &pctrl->irq_chip,
1025 				   0,
1026 				   handle_edge_irq,
1027 				   IRQ_TYPE_NONE);
1028 	if (ret) {
1029 		dev_err(pctrl->dev, "Failed to add irqchip to gpiochip\n");
1030 		gpiochip_remove(&pctrl->chip);
1031 		return -ENOSYS;
1032 	}
1033 
1034 	gpiochip_set_chained_irqchip(chip, &pctrl->irq_chip, pctrl->irq,
1035 				     msm_gpio_irq_handler);
1036 
1037 	return 0;
1038 }
1039 
1040 static int msm_ps_hold_restart(struct notifier_block *nb, unsigned long action,
1041 			       void *data)
1042 {
1043 	struct msm_pinctrl *pctrl = container_of(nb, struct msm_pinctrl, restart_nb);
1044 
1045 	writel(0, pctrl->regs[0] + PS_HOLD_OFFSET);
1046 	mdelay(1000);
1047 	return NOTIFY_DONE;
1048 }
1049 
1050 static struct msm_pinctrl *poweroff_pctrl;
1051 
1052 static void msm_ps_hold_poweroff(void)
1053 {
1054 	msm_ps_hold_restart(&poweroff_pctrl->restart_nb, 0, NULL);
1055 }
1056 
1057 static void msm_pinctrl_setup_pm_reset(struct msm_pinctrl *pctrl)
1058 {
1059 	int i;
1060 	const struct msm_function *func = pctrl->soc->functions;
1061 
1062 	for (i = 0; i < pctrl->soc->nfunctions; i++)
1063 		if (!strcmp(func[i].name, "ps_hold")) {
1064 			pctrl->restart_nb.notifier_call = msm_ps_hold_restart;
1065 			pctrl->restart_nb.priority = 128;
1066 			if (register_restart_handler(&pctrl->restart_nb))
1067 				dev_err(pctrl->dev,
1068 					"failed to setup restart handler.\n");
1069 			poweroff_pctrl = pctrl;
1070 			pm_power_off = msm_ps_hold_poweroff;
1071 			break;
1072 		}
1073 }
1074 
1075 static __maybe_unused int msm_pinctrl_suspend(struct device *dev)
1076 {
1077 	struct msm_pinctrl *pctrl = dev_get_drvdata(dev);
1078 
1079 	return pinctrl_force_sleep(pctrl->pctrl);
1080 }
1081 
1082 static __maybe_unused int msm_pinctrl_resume(struct device *dev)
1083 {
1084 	struct msm_pinctrl *pctrl = dev_get_drvdata(dev);
1085 
1086 	return pinctrl_force_default(pctrl->pctrl);
1087 }
1088 
1089 SIMPLE_DEV_PM_OPS(msm_pinctrl_dev_pm_ops, msm_pinctrl_suspend,
1090 		  msm_pinctrl_resume);
1091 
1092 EXPORT_SYMBOL(msm_pinctrl_dev_pm_ops);
1093 
1094 int msm_pinctrl_probe(struct platform_device *pdev,
1095 		      const struct msm_pinctrl_soc_data *soc_data)
1096 {
1097 	struct msm_pinctrl *pctrl;
1098 	struct resource *res;
1099 	int ret;
1100 	int i;
1101 
1102 	pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
1103 	if (!pctrl)
1104 		return -ENOMEM;
1105 
1106 	pctrl->dev = &pdev->dev;
1107 	pctrl->soc = soc_data;
1108 	pctrl->chip = msm_gpio_template;
1109 
1110 	raw_spin_lock_init(&pctrl->lock);
1111 
1112 	if (soc_data->tiles) {
1113 		for (i = 0; i < soc_data->ntiles; i++) {
1114 			res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1115 							   soc_data->tiles[i]);
1116 			pctrl->regs[i] = devm_ioremap_resource(&pdev->dev, res);
1117 			if (IS_ERR(pctrl->regs[i]))
1118 				return PTR_ERR(pctrl->regs[i]);
1119 		}
1120 	} else {
1121 		res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1122 		pctrl->regs[0] = devm_ioremap_resource(&pdev->dev, res);
1123 		if (IS_ERR(pctrl->regs[0]))
1124 			return PTR_ERR(pctrl->regs[0]);
1125 	}
1126 
1127 	msm_pinctrl_setup_pm_reset(pctrl);
1128 
1129 	pctrl->irq = platform_get_irq(pdev, 0);
1130 	if (pctrl->irq < 0) {
1131 		dev_err(&pdev->dev, "No interrupt defined for msmgpio\n");
1132 		return pctrl->irq;
1133 	}
1134 
1135 	pctrl->desc.owner = THIS_MODULE;
1136 	pctrl->desc.pctlops = &msm_pinctrl_ops;
1137 	pctrl->desc.pmxops = &msm_pinmux_ops;
1138 	pctrl->desc.confops = &msm_pinconf_ops;
1139 	pctrl->desc.name = dev_name(&pdev->dev);
1140 	pctrl->desc.pins = pctrl->soc->pins;
1141 	pctrl->desc.npins = pctrl->soc->npins;
1142 
1143 	pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &pctrl->desc, pctrl);
1144 	if (IS_ERR(pctrl->pctrl)) {
1145 		dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
1146 		return PTR_ERR(pctrl->pctrl);
1147 	}
1148 
1149 	ret = msm_gpio_init(pctrl);
1150 	if (ret)
1151 		return ret;
1152 
1153 	platform_set_drvdata(pdev, pctrl);
1154 
1155 	dev_dbg(&pdev->dev, "Probed Qualcomm pinctrl driver\n");
1156 
1157 	return 0;
1158 }
1159 EXPORT_SYMBOL(msm_pinctrl_probe);
1160 
1161 int msm_pinctrl_remove(struct platform_device *pdev)
1162 {
1163 	struct msm_pinctrl *pctrl = platform_get_drvdata(pdev);
1164 
1165 	gpiochip_remove(&pctrl->chip);
1166 
1167 	unregister_restart_handler(&pctrl->restart_nb);
1168 
1169 	return 0;
1170 }
1171 EXPORT_SYMBOL(msm_pinctrl_remove);
1172 
1173