1 /* 2 * Copyright (c) 2013, Sony Mobile Communications AB. 3 * Copyright (c) 2013, The Linux Foundation. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 and 7 * only version 2 as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 */ 14 15 #include <linux/delay.h> 16 #include <linux/err.h> 17 #include <linux/io.h> 18 #include <linux/module.h> 19 #include <linux/of.h> 20 #include <linux/platform_device.h> 21 #include <linux/pinctrl/machine.h> 22 #include <linux/pinctrl/pinctrl.h> 23 #include <linux/pinctrl/pinmux.h> 24 #include <linux/pinctrl/pinconf.h> 25 #include <linux/pinctrl/pinconf-generic.h> 26 #include <linux/slab.h> 27 #include <linux/gpio.h> 28 #include <linux/interrupt.h> 29 #include <linux/spinlock.h> 30 #include <linux/reboot.h> 31 #include <linux/pm.h> 32 #include <linux/log2.h> 33 34 #include "../core.h" 35 #include "../pinconf.h" 36 #include "pinctrl-msm.h" 37 #include "../pinctrl-utils.h" 38 39 #define MAX_NR_GPIO 300 40 #define PS_HOLD_OFFSET 0x820 41 42 /** 43 * struct msm_pinctrl - state for a pinctrl-msm device 44 * @dev: device handle. 45 * @pctrl: pinctrl handle. 46 * @chip: gpiochip handle. 47 * @restart_nb: restart notifier block. 48 * @irq: parent irq for the TLMM irq_chip. 49 * @lock: Spinlock to protect register resources as well 50 * as msm_pinctrl data structures. 51 * @enabled_irqs: Bitmap of currently enabled irqs. 52 * @dual_edge_irqs: Bitmap of irqs that need sw emulated dual edge 53 * detection. 54 * @soc; Reference to soc_data of platform specific data. 55 * @regs: Base address for the TLMM register map. 56 */ 57 struct msm_pinctrl { 58 struct device *dev; 59 struct pinctrl_dev *pctrl; 60 struct gpio_chip chip; 61 struct notifier_block restart_nb; 62 int irq; 63 64 raw_spinlock_t lock; 65 66 DECLARE_BITMAP(dual_edge_irqs, MAX_NR_GPIO); 67 DECLARE_BITMAP(enabled_irqs, MAX_NR_GPIO); 68 69 const struct msm_pinctrl_soc_data *soc; 70 void __iomem *regs; 71 }; 72 73 static int msm_get_groups_count(struct pinctrl_dev *pctldev) 74 { 75 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 76 77 return pctrl->soc->ngroups; 78 } 79 80 static const char *msm_get_group_name(struct pinctrl_dev *pctldev, 81 unsigned group) 82 { 83 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 84 85 return pctrl->soc->groups[group].name; 86 } 87 88 static int msm_get_group_pins(struct pinctrl_dev *pctldev, 89 unsigned group, 90 const unsigned **pins, 91 unsigned *num_pins) 92 { 93 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 94 95 *pins = pctrl->soc->groups[group].pins; 96 *num_pins = pctrl->soc->groups[group].npins; 97 return 0; 98 } 99 100 static const struct pinctrl_ops msm_pinctrl_ops = { 101 .get_groups_count = msm_get_groups_count, 102 .get_group_name = msm_get_group_name, 103 .get_group_pins = msm_get_group_pins, 104 .dt_node_to_map = pinconf_generic_dt_node_to_map_group, 105 .dt_free_map = pinctrl_utils_free_map, 106 }; 107 108 static int msm_pinmux_request(struct pinctrl_dev *pctldev, unsigned offset) 109 { 110 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 111 struct gpio_chip *chip = &pctrl->chip; 112 113 return gpiochip_line_is_valid(chip, offset) ? 0 : -EINVAL; 114 } 115 116 static int msm_get_functions_count(struct pinctrl_dev *pctldev) 117 { 118 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 119 120 return pctrl->soc->nfunctions; 121 } 122 123 static const char *msm_get_function_name(struct pinctrl_dev *pctldev, 124 unsigned function) 125 { 126 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 127 128 return pctrl->soc->functions[function].name; 129 } 130 131 static int msm_get_function_groups(struct pinctrl_dev *pctldev, 132 unsigned function, 133 const char * const **groups, 134 unsigned * const num_groups) 135 { 136 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 137 138 *groups = pctrl->soc->functions[function].groups; 139 *num_groups = pctrl->soc->functions[function].ngroups; 140 return 0; 141 } 142 143 static int msm_pinmux_set_mux(struct pinctrl_dev *pctldev, 144 unsigned function, 145 unsigned group) 146 { 147 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 148 const struct msm_pingroup *g; 149 unsigned long flags; 150 u32 val, mask; 151 int i; 152 153 g = &pctrl->soc->groups[group]; 154 mask = GENMASK(g->mux_bit + order_base_2(g->nfuncs) - 1, g->mux_bit); 155 156 for (i = 0; i < g->nfuncs; i++) { 157 if (g->funcs[i] == function) 158 break; 159 } 160 161 if (WARN_ON(i == g->nfuncs)) 162 return -EINVAL; 163 164 raw_spin_lock_irqsave(&pctrl->lock, flags); 165 166 val = readl(pctrl->regs + g->ctl_reg); 167 val &= ~mask; 168 val |= i << g->mux_bit; 169 writel(val, pctrl->regs + g->ctl_reg); 170 171 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 172 173 return 0; 174 } 175 176 static const struct pinmux_ops msm_pinmux_ops = { 177 .request = msm_pinmux_request, 178 .get_functions_count = msm_get_functions_count, 179 .get_function_name = msm_get_function_name, 180 .get_function_groups = msm_get_function_groups, 181 .set_mux = msm_pinmux_set_mux, 182 }; 183 184 static int msm_config_reg(struct msm_pinctrl *pctrl, 185 const struct msm_pingroup *g, 186 unsigned param, 187 unsigned *mask, 188 unsigned *bit) 189 { 190 switch (param) { 191 case PIN_CONFIG_BIAS_DISABLE: 192 case PIN_CONFIG_BIAS_PULL_DOWN: 193 case PIN_CONFIG_BIAS_BUS_HOLD: 194 case PIN_CONFIG_BIAS_PULL_UP: 195 *bit = g->pull_bit; 196 *mask = 3; 197 break; 198 case PIN_CONFIG_DRIVE_STRENGTH: 199 *bit = g->drv_bit; 200 *mask = 7; 201 break; 202 case PIN_CONFIG_OUTPUT: 203 case PIN_CONFIG_INPUT_ENABLE: 204 *bit = g->oe_bit; 205 *mask = 1; 206 break; 207 default: 208 return -ENOTSUPP; 209 } 210 211 return 0; 212 } 213 214 #define MSM_NO_PULL 0 215 #define MSM_PULL_DOWN 1 216 #define MSM_KEEPER 2 217 #define MSM_PULL_UP_NO_KEEPER 2 218 #define MSM_PULL_UP 3 219 220 static unsigned msm_regval_to_drive(u32 val) 221 { 222 return (val + 1) * 2; 223 } 224 225 static int msm_config_group_get(struct pinctrl_dev *pctldev, 226 unsigned int group, 227 unsigned long *config) 228 { 229 const struct msm_pingroup *g; 230 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 231 unsigned param = pinconf_to_config_param(*config); 232 unsigned mask; 233 unsigned arg; 234 unsigned bit; 235 int ret; 236 u32 val; 237 238 g = &pctrl->soc->groups[group]; 239 240 ret = msm_config_reg(pctrl, g, param, &mask, &bit); 241 if (ret < 0) 242 return ret; 243 244 val = readl(pctrl->regs + g->ctl_reg); 245 arg = (val >> bit) & mask; 246 247 /* Convert register value to pinconf value */ 248 switch (param) { 249 case PIN_CONFIG_BIAS_DISABLE: 250 arg = arg == MSM_NO_PULL; 251 break; 252 case PIN_CONFIG_BIAS_PULL_DOWN: 253 arg = arg == MSM_PULL_DOWN; 254 break; 255 case PIN_CONFIG_BIAS_BUS_HOLD: 256 if (pctrl->soc->pull_no_keeper) 257 return -ENOTSUPP; 258 259 arg = arg == MSM_KEEPER; 260 break; 261 case PIN_CONFIG_BIAS_PULL_UP: 262 if (pctrl->soc->pull_no_keeper) 263 arg = arg == MSM_PULL_UP_NO_KEEPER; 264 else 265 arg = arg == MSM_PULL_UP; 266 break; 267 case PIN_CONFIG_DRIVE_STRENGTH: 268 arg = msm_regval_to_drive(arg); 269 break; 270 case PIN_CONFIG_OUTPUT: 271 /* Pin is not output */ 272 if (!arg) 273 return -EINVAL; 274 275 val = readl(pctrl->regs + g->io_reg); 276 arg = !!(val & BIT(g->in_bit)); 277 break; 278 case PIN_CONFIG_INPUT_ENABLE: 279 /* Pin is output */ 280 if (arg) 281 return -EINVAL; 282 arg = 1; 283 break; 284 default: 285 return -ENOTSUPP; 286 } 287 288 *config = pinconf_to_config_packed(param, arg); 289 290 return 0; 291 } 292 293 static int msm_config_group_set(struct pinctrl_dev *pctldev, 294 unsigned group, 295 unsigned long *configs, 296 unsigned num_configs) 297 { 298 const struct msm_pingroup *g; 299 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 300 unsigned long flags; 301 unsigned param; 302 unsigned mask; 303 unsigned arg; 304 unsigned bit; 305 int ret; 306 u32 val; 307 int i; 308 309 g = &pctrl->soc->groups[group]; 310 311 for (i = 0; i < num_configs; i++) { 312 param = pinconf_to_config_param(configs[i]); 313 arg = pinconf_to_config_argument(configs[i]); 314 315 ret = msm_config_reg(pctrl, g, param, &mask, &bit); 316 if (ret < 0) 317 return ret; 318 319 /* Convert pinconf values to register values */ 320 switch (param) { 321 case PIN_CONFIG_BIAS_DISABLE: 322 arg = MSM_NO_PULL; 323 break; 324 case PIN_CONFIG_BIAS_PULL_DOWN: 325 arg = MSM_PULL_DOWN; 326 break; 327 case PIN_CONFIG_BIAS_BUS_HOLD: 328 if (pctrl->soc->pull_no_keeper) 329 return -ENOTSUPP; 330 331 arg = MSM_KEEPER; 332 break; 333 case PIN_CONFIG_BIAS_PULL_UP: 334 if (pctrl->soc->pull_no_keeper) 335 arg = MSM_PULL_UP_NO_KEEPER; 336 else 337 arg = MSM_PULL_UP; 338 break; 339 case PIN_CONFIG_DRIVE_STRENGTH: 340 /* Check for invalid values */ 341 if (arg > 16 || arg < 2 || (arg % 2) != 0) 342 arg = -1; 343 else 344 arg = (arg / 2) - 1; 345 break; 346 case PIN_CONFIG_OUTPUT: 347 /* set output value */ 348 raw_spin_lock_irqsave(&pctrl->lock, flags); 349 val = readl(pctrl->regs + g->io_reg); 350 if (arg) 351 val |= BIT(g->out_bit); 352 else 353 val &= ~BIT(g->out_bit); 354 writel(val, pctrl->regs + g->io_reg); 355 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 356 357 /* enable output */ 358 arg = 1; 359 break; 360 case PIN_CONFIG_INPUT_ENABLE: 361 /* disable output */ 362 arg = 0; 363 break; 364 default: 365 dev_err(pctrl->dev, "Unsupported config parameter: %x\n", 366 param); 367 return -EINVAL; 368 } 369 370 /* Range-check user-supplied value */ 371 if (arg & ~mask) { 372 dev_err(pctrl->dev, "config %x: %x is invalid\n", param, arg); 373 return -EINVAL; 374 } 375 376 raw_spin_lock_irqsave(&pctrl->lock, flags); 377 val = readl(pctrl->regs + g->ctl_reg); 378 val &= ~(mask << bit); 379 val |= arg << bit; 380 writel(val, pctrl->regs + g->ctl_reg); 381 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 382 } 383 384 return 0; 385 } 386 387 static const struct pinconf_ops msm_pinconf_ops = { 388 .is_generic = true, 389 .pin_config_group_get = msm_config_group_get, 390 .pin_config_group_set = msm_config_group_set, 391 }; 392 393 static struct pinctrl_desc msm_pinctrl_desc = { 394 .pctlops = &msm_pinctrl_ops, 395 .pmxops = &msm_pinmux_ops, 396 .confops = &msm_pinconf_ops, 397 .owner = THIS_MODULE, 398 }; 399 400 static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 401 { 402 const struct msm_pingroup *g; 403 struct msm_pinctrl *pctrl = gpiochip_get_data(chip); 404 unsigned long flags; 405 u32 val; 406 407 g = &pctrl->soc->groups[offset]; 408 409 raw_spin_lock_irqsave(&pctrl->lock, flags); 410 411 val = readl(pctrl->regs + g->ctl_reg); 412 val &= ~BIT(g->oe_bit); 413 writel(val, pctrl->regs + g->ctl_reg); 414 415 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 416 417 return 0; 418 } 419 420 static int msm_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value) 421 { 422 const struct msm_pingroup *g; 423 struct msm_pinctrl *pctrl = gpiochip_get_data(chip); 424 unsigned long flags; 425 u32 val; 426 427 g = &pctrl->soc->groups[offset]; 428 429 raw_spin_lock_irqsave(&pctrl->lock, flags); 430 431 val = readl(pctrl->regs + g->io_reg); 432 if (value) 433 val |= BIT(g->out_bit); 434 else 435 val &= ~BIT(g->out_bit); 436 writel(val, pctrl->regs + g->io_reg); 437 438 val = readl(pctrl->regs + g->ctl_reg); 439 val |= BIT(g->oe_bit); 440 writel(val, pctrl->regs + g->ctl_reg); 441 442 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 443 444 return 0; 445 } 446 447 static int msm_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 448 { 449 struct msm_pinctrl *pctrl = gpiochip_get_data(chip); 450 const struct msm_pingroup *g; 451 u32 val; 452 453 g = &pctrl->soc->groups[offset]; 454 455 val = readl(pctrl->regs + g->ctl_reg); 456 457 /* 0 = output, 1 = input */ 458 return val & BIT(g->oe_bit) ? 0 : 1; 459 } 460 461 static int msm_gpio_get(struct gpio_chip *chip, unsigned offset) 462 { 463 const struct msm_pingroup *g; 464 struct msm_pinctrl *pctrl = gpiochip_get_data(chip); 465 u32 val; 466 467 g = &pctrl->soc->groups[offset]; 468 469 val = readl(pctrl->regs + g->io_reg); 470 return !!(val & BIT(g->in_bit)); 471 } 472 473 static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 474 { 475 const struct msm_pingroup *g; 476 struct msm_pinctrl *pctrl = gpiochip_get_data(chip); 477 unsigned long flags; 478 u32 val; 479 480 g = &pctrl->soc->groups[offset]; 481 482 raw_spin_lock_irqsave(&pctrl->lock, flags); 483 484 val = readl(pctrl->regs + g->io_reg); 485 if (value) 486 val |= BIT(g->out_bit); 487 else 488 val &= ~BIT(g->out_bit); 489 writel(val, pctrl->regs + g->io_reg); 490 491 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 492 } 493 494 #ifdef CONFIG_DEBUG_FS 495 #include <linux/seq_file.h> 496 497 static void msm_gpio_dbg_show_one(struct seq_file *s, 498 struct pinctrl_dev *pctldev, 499 struct gpio_chip *chip, 500 unsigned offset, 501 unsigned gpio) 502 { 503 const struct msm_pingroup *g; 504 struct msm_pinctrl *pctrl = gpiochip_get_data(chip); 505 unsigned func; 506 int is_out; 507 int drive; 508 int pull; 509 u32 ctl_reg; 510 511 static const char * const pulls[] = { 512 "no pull", 513 "pull down", 514 "keeper", 515 "pull up" 516 }; 517 518 if (!gpiochip_line_is_valid(chip, offset)) 519 return; 520 521 g = &pctrl->soc->groups[offset]; 522 ctl_reg = readl(pctrl->regs + g->ctl_reg); 523 524 is_out = !!(ctl_reg & BIT(g->oe_bit)); 525 func = (ctl_reg >> g->mux_bit) & 7; 526 drive = (ctl_reg >> g->drv_bit) & 7; 527 pull = (ctl_reg >> g->pull_bit) & 3; 528 529 seq_printf(s, " %-8s: %-3s %d", g->name, is_out ? "out" : "in", func); 530 seq_printf(s, " %dmA", msm_regval_to_drive(drive)); 531 seq_printf(s, " %s", pulls[pull]); 532 seq_puts(s, "\n"); 533 } 534 535 static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) 536 { 537 unsigned gpio = chip->base; 538 unsigned i; 539 540 for (i = 0; i < chip->ngpio; i++, gpio++) 541 msm_gpio_dbg_show_one(s, NULL, chip, i, gpio); 542 } 543 544 #else 545 #define msm_gpio_dbg_show NULL 546 #endif 547 548 static const struct gpio_chip msm_gpio_template = { 549 .direction_input = msm_gpio_direction_input, 550 .direction_output = msm_gpio_direction_output, 551 .get_direction = msm_gpio_get_direction, 552 .get = msm_gpio_get, 553 .set = msm_gpio_set, 554 .request = gpiochip_generic_request, 555 .free = gpiochip_generic_free, 556 .dbg_show = msm_gpio_dbg_show, 557 }; 558 559 /* For dual-edge interrupts in software, since some hardware has no 560 * such support: 561 * 562 * At appropriate moments, this function may be called to flip the polarity 563 * settings of both-edge irq lines to try and catch the next edge. 564 * 565 * The attempt is considered successful if: 566 * - the status bit goes high, indicating that an edge was caught, or 567 * - the input value of the gpio doesn't change during the attempt. 568 * If the value changes twice during the process, that would cause the first 569 * test to fail but would force the second, as two opposite 570 * transitions would cause a detection no matter the polarity setting. 571 * 572 * The do-loop tries to sledge-hammer closed the timing hole between 573 * the initial value-read and the polarity-write - if the line value changes 574 * during that window, an interrupt is lost, the new polarity setting is 575 * incorrect, and the first success test will fail, causing a retry. 576 * 577 * Algorithm comes from Google's msmgpio driver. 578 */ 579 static void msm_gpio_update_dual_edge_pos(struct msm_pinctrl *pctrl, 580 const struct msm_pingroup *g, 581 struct irq_data *d) 582 { 583 int loop_limit = 100; 584 unsigned val, val2, intstat; 585 unsigned pol; 586 587 do { 588 val = readl(pctrl->regs + g->io_reg) & BIT(g->in_bit); 589 590 pol = readl(pctrl->regs + g->intr_cfg_reg); 591 pol ^= BIT(g->intr_polarity_bit); 592 writel(pol, pctrl->regs + g->intr_cfg_reg); 593 594 val2 = readl(pctrl->regs + g->io_reg) & BIT(g->in_bit); 595 intstat = readl(pctrl->regs + g->intr_status_reg); 596 if (intstat || (val == val2)) 597 return; 598 } while (loop_limit-- > 0); 599 dev_err(pctrl->dev, "dual-edge irq failed to stabilize, %#08x != %#08x\n", 600 val, val2); 601 } 602 603 static void msm_gpio_irq_mask(struct irq_data *d) 604 { 605 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 606 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); 607 const struct msm_pingroup *g; 608 unsigned long flags; 609 u32 val; 610 611 g = &pctrl->soc->groups[d->hwirq]; 612 613 raw_spin_lock_irqsave(&pctrl->lock, flags); 614 615 val = readl(pctrl->regs + g->intr_cfg_reg); 616 val &= ~BIT(g->intr_enable_bit); 617 writel(val, pctrl->regs + g->intr_cfg_reg); 618 619 clear_bit(d->hwirq, pctrl->enabled_irqs); 620 621 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 622 } 623 624 static void msm_gpio_irq_unmask(struct irq_data *d) 625 { 626 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 627 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); 628 const struct msm_pingroup *g; 629 unsigned long flags; 630 u32 val; 631 632 g = &pctrl->soc->groups[d->hwirq]; 633 634 raw_spin_lock_irqsave(&pctrl->lock, flags); 635 636 val = readl(pctrl->regs + g->intr_cfg_reg); 637 val |= BIT(g->intr_enable_bit); 638 writel(val, pctrl->regs + g->intr_cfg_reg); 639 640 set_bit(d->hwirq, pctrl->enabled_irqs); 641 642 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 643 } 644 645 static void msm_gpio_irq_ack(struct irq_data *d) 646 { 647 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 648 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); 649 const struct msm_pingroup *g; 650 unsigned long flags; 651 u32 val; 652 653 g = &pctrl->soc->groups[d->hwirq]; 654 655 raw_spin_lock_irqsave(&pctrl->lock, flags); 656 657 val = readl(pctrl->regs + g->intr_status_reg); 658 if (g->intr_ack_high) 659 val |= BIT(g->intr_status_bit); 660 else 661 val &= ~BIT(g->intr_status_bit); 662 writel(val, pctrl->regs + g->intr_status_reg); 663 664 if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) 665 msm_gpio_update_dual_edge_pos(pctrl, g, d); 666 667 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 668 } 669 670 static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type) 671 { 672 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 673 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); 674 const struct msm_pingroup *g; 675 unsigned long flags; 676 u32 val; 677 678 g = &pctrl->soc->groups[d->hwirq]; 679 680 raw_spin_lock_irqsave(&pctrl->lock, flags); 681 682 /* 683 * For hw without possibility of detecting both edges 684 */ 685 if (g->intr_detection_width == 1 && type == IRQ_TYPE_EDGE_BOTH) 686 set_bit(d->hwirq, pctrl->dual_edge_irqs); 687 else 688 clear_bit(d->hwirq, pctrl->dual_edge_irqs); 689 690 /* Route interrupts to application cpu */ 691 val = readl(pctrl->regs + g->intr_target_reg); 692 val &= ~(7 << g->intr_target_bit); 693 val |= g->intr_target_kpss_val << g->intr_target_bit; 694 writel(val, pctrl->regs + g->intr_target_reg); 695 696 /* Update configuration for gpio. 697 * RAW_STATUS_EN is left on for all gpio irqs. Due to the 698 * internal circuitry of TLMM, toggling the RAW_STATUS 699 * could cause the INTR_STATUS to be set for EDGE interrupts. 700 */ 701 val = readl(pctrl->regs + g->intr_cfg_reg); 702 val |= BIT(g->intr_raw_status_bit); 703 if (g->intr_detection_width == 2) { 704 val &= ~(3 << g->intr_detection_bit); 705 val &= ~(1 << g->intr_polarity_bit); 706 switch (type) { 707 case IRQ_TYPE_EDGE_RISING: 708 val |= 1 << g->intr_detection_bit; 709 val |= BIT(g->intr_polarity_bit); 710 break; 711 case IRQ_TYPE_EDGE_FALLING: 712 val |= 2 << g->intr_detection_bit; 713 val |= BIT(g->intr_polarity_bit); 714 break; 715 case IRQ_TYPE_EDGE_BOTH: 716 val |= 3 << g->intr_detection_bit; 717 val |= BIT(g->intr_polarity_bit); 718 break; 719 case IRQ_TYPE_LEVEL_LOW: 720 break; 721 case IRQ_TYPE_LEVEL_HIGH: 722 val |= BIT(g->intr_polarity_bit); 723 break; 724 } 725 } else if (g->intr_detection_width == 1) { 726 val &= ~(1 << g->intr_detection_bit); 727 val &= ~(1 << g->intr_polarity_bit); 728 switch (type) { 729 case IRQ_TYPE_EDGE_RISING: 730 val |= BIT(g->intr_detection_bit); 731 val |= BIT(g->intr_polarity_bit); 732 break; 733 case IRQ_TYPE_EDGE_FALLING: 734 val |= BIT(g->intr_detection_bit); 735 break; 736 case IRQ_TYPE_EDGE_BOTH: 737 val |= BIT(g->intr_detection_bit); 738 val |= BIT(g->intr_polarity_bit); 739 break; 740 case IRQ_TYPE_LEVEL_LOW: 741 break; 742 case IRQ_TYPE_LEVEL_HIGH: 743 val |= BIT(g->intr_polarity_bit); 744 break; 745 } 746 } else { 747 BUG(); 748 } 749 writel(val, pctrl->regs + g->intr_cfg_reg); 750 751 if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) 752 msm_gpio_update_dual_edge_pos(pctrl, g, d); 753 754 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 755 756 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) 757 irq_set_handler_locked(d, handle_level_irq); 758 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) 759 irq_set_handler_locked(d, handle_edge_irq); 760 761 return 0; 762 } 763 764 static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on) 765 { 766 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 767 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); 768 unsigned long flags; 769 770 raw_spin_lock_irqsave(&pctrl->lock, flags); 771 772 irq_set_irq_wake(pctrl->irq, on); 773 774 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 775 776 return 0; 777 } 778 779 static struct irq_chip msm_gpio_irq_chip = { 780 .name = "msmgpio", 781 .irq_mask = msm_gpio_irq_mask, 782 .irq_unmask = msm_gpio_irq_unmask, 783 .irq_ack = msm_gpio_irq_ack, 784 .irq_set_type = msm_gpio_irq_set_type, 785 .irq_set_wake = msm_gpio_irq_set_wake, 786 }; 787 788 static void msm_gpio_irq_handler(struct irq_desc *desc) 789 { 790 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 791 const struct msm_pingroup *g; 792 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); 793 struct irq_chip *chip = irq_desc_get_chip(desc); 794 int irq_pin; 795 int handled = 0; 796 u32 val; 797 int i; 798 799 chained_irq_enter(chip, desc); 800 801 /* 802 * Each pin has it's own IRQ status register, so use 803 * enabled_irq bitmap to limit the number of reads. 804 */ 805 for_each_set_bit(i, pctrl->enabled_irqs, pctrl->chip.ngpio) { 806 g = &pctrl->soc->groups[i]; 807 val = readl(pctrl->regs + g->intr_status_reg); 808 if (val & BIT(g->intr_status_bit)) { 809 irq_pin = irq_find_mapping(gc->irq.domain, i); 810 generic_handle_irq(irq_pin); 811 handled++; 812 } 813 } 814 815 /* No interrupts were flagged */ 816 if (handled == 0) 817 handle_bad_irq(desc); 818 819 chained_irq_exit(chip, desc); 820 } 821 822 static int msm_gpio_init_valid_mask(struct gpio_chip *chip, 823 struct msm_pinctrl *pctrl) 824 { 825 int ret; 826 unsigned int len, i; 827 unsigned int max_gpios = pctrl->soc->ngpios; 828 u16 *tmp; 829 830 /* The number of GPIOs in the ACPI tables */ 831 len = ret = device_property_read_u16_array(pctrl->dev, "gpios", NULL, 0); 832 if (ret < 0) 833 return 0; 834 835 if (ret > max_gpios) 836 return -EINVAL; 837 838 tmp = kmalloc_array(len, sizeof(*tmp), GFP_KERNEL); 839 if (!tmp) 840 return -ENOMEM; 841 842 ret = device_property_read_u16_array(pctrl->dev, "gpios", tmp, len); 843 if (ret < 0) { 844 dev_err(pctrl->dev, "could not read list of GPIOs\n"); 845 goto out; 846 } 847 848 bitmap_zero(chip->valid_mask, max_gpios); 849 for (i = 0; i < len; i++) 850 set_bit(tmp[i], chip->valid_mask); 851 852 out: 853 kfree(tmp); 854 return ret; 855 } 856 857 static bool msm_gpio_needs_valid_mask(struct msm_pinctrl *pctrl) 858 { 859 return device_property_read_u16_array(pctrl->dev, "gpios", NULL, 0) > 0; 860 } 861 862 static int msm_gpio_init(struct msm_pinctrl *pctrl) 863 { 864 struct gpio_chip *chip; 865 int ret; 866 unsigned ngpio = pctrl->soc->ngpios; 867 868 if (WARN_ON(ngpio > MAX_NR_GPIO)) 869 return -EINVAL; 870 871 chip = &pctrl->chip; 872 chip->base = -1; 873 chip->ngpio = ngpio; 874 chip->label = dev_name(pctrl->dev); 875 chip->parent = pctrl->dev; 876 chip->owner = THIS_MODULE; 877 chip->of_node = pctrl->dev->of_node; 878 chip->need_valid_mask = msm_gpio_needs_valid_mask(pctrl); 879 880 ret = gpiochip_add_data(&pctrl->chip, pctrl); 881 if (ret) { 882 dev_err(pctrl->dev, "Failed register gpiochip\n"); 883 return ret; 884 } 885 886 ret = msm_gpio_init_valid_mask(chip, pctrl); 887 if (ret) { 888 dev_err(pctrl->dev, "Failed to setup irq valid bits\n"); 889 gpiochip_remove(&pctrl->chip); 890 return ret; 891 } 892 893 ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), 0, 0, chip->ngpio); 894 if (ret) { 895 dev_err(pctrl->dev, "Failed to add pin range\n"); 896 gpiochip_remove(&pctrl->chip); 897 return ret; 898 } 899 900 ret = gpiochip_irqchip_add(chip, 901 &msm_gpio_irq_chip, 902 0, 903 handle_edge_irq, 904 IRQ_TYPE_NONE); 905 if (ret) { 906 dev_err(pctrl->dev, "Failed to add irqchip to gpiochip\n"); 907 gpiochip_remove(&pctrl->chip); 908 return -ENOSYS; 909 } 910 911 gpiochip_set_chained_irqchip(chip, &msm_gpio_irq_chip, pctrl->irq, 912 msm_gpio_irq_handler); 913 914 return 0; 915 } 916 917 static int msm_ps_hold_restart(struct notifier_block *nb, unsigned long action, 918 void *data) 919 { 920 struct msm_pinctrl *pctrl = container_of(nb, struct msm_pinctrl, restart_nb); 921 922 writel(0, pctrl->regs + PS_HOLD_OFFSET); 923 mdelay(1000); 924 return NOTIFY_DONE; 925 } 926 927 static struct msm_pinctrl *poweroff_pctrl; 928 929 static void msm_ps_hold_poweroff(void) 930 { 931 msm_ps_hold_restart(&poweroff_pctrl->restart_nb, 0, NULL); 932 } 933 934 static void msm_pinctrl_setup_pm_reset(struct msm_pinctrl *pctrl) 935 { 936 int i; 937 const struct msm_function *func = pctrl->soc->functions; 938 939 for (i = 0; i < pctrl->soc->nfunctions; i++) 940 if (!strcmp(func[i].name, "ps_hold")) { 941 pctrl->restart_nb.notifier_call = msm_ps_hold_restart; 942 pctrl->restart_nb.priority = 128; 943 if (register_restart_handler(&pctrl->restart_nb)) 944 dev_err(pctrl->dev, 945 "failed to setup restart handler.\n"); 946 poweroff_pctrl = pctrl; 947 pm_power_off = msm_ps_hold_poweroff; 948 break; 949 } 950 } 951 952 int msm_pinctrl_probe(struct platform_device *pdev, 953 const struct msm_pinctrl_soc_data *soc_data) 954 { 955 struct msm_pinctrl *pctrl; 956 struct resource *res; 957 int ret; 958 959 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); 960 if (!pctrl) 961 return -ENOMEM; 962 963 pctrl->dev = &pdev->dev; 964 pctrl->soc = soc_data; 965 pctrl->chip = msm_gpio_template; 966 967 raw_spin_lock_init(&pctrl->lock); 968 969 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 970 pctrl->regs = devm_ioremap_resource(&pdev->dev, res); 971 if (IS_ERR(pctrl->regs)) 972 return PTR_ERR(pctrl->regs); 973 974 msm_pinctrl_setup_pm_reset(pctrl); 975 976 pctrl->irq = platform_get_irq(pdev, 0); 977 if (pctrl->irq < 0) { 978 dev_err(&pdev->dev, "No interrupt defined for msmgpio\n"); 979 return pctrl->irq; 980 } 981 982 msm_pinctrl_desc.name = dev_name(&pdev->dev); 983 msm_pinctrl_desc.pins = pctrl->soc->pins; 984 msm_pinctrl_desc.npins = pctrl->soc->npins; 985 pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &msm_pinctrl_desc, 986 pctrl); 987 if (IS_ERR(pctrl->pctrl)) { 988 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); 989 return PTR_ERR(pctrl->pctrl); 990 } 991 992 ret = msm_gpio_init(pctrl); 993 if (ret) 994 return ret; 995 996 platform_set_drvdata(pdev, pctrl); 997 998 dev_dbg(&pdev->dev, "Probed Qualcomm pinctrl driver\n"); 999 1000 return 0; 1001 } 1002 EXPORT_SYMBOL(msm_pinctrl_probe); 1003 1004 int msm_pinctrl_remove(struct platform_device *pdev) 1005 { 1006 struct msm_pinctrl *pctrl = platform_get_drvdata(pdev); 1007 1008 gpiochip_remove(&pctrl->chip); 1009 1010 unregister_restart_handler(&pctrl->restart_nb); 1011 1012 return 0; 1013 } 1014 EXPORT_SYMBOL(msm_pinctrl_remove); 1015 1016