1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
4  * Copyright (c) 2020 Linaro Ltd.
5  */
6 
7 #include <linux/bitfield.h>
8 #include <linux/clk.h>
9 #include <linux/gpio/driver.h>
10 #include <linux/module.h>
11 #include <linux/of_device.h>
12 #include <linux/seq_file.h>
13 
14 #include <linux/pinctrl/pinconf-generic.h>
15 #include <linux/pinctrl/pinconf.h>
16 #include <linux/pinctrl/pinmux.h>
17 
18 #include "../pinctrl-utils.h"
19 
20 #include "pinctrl-lpass-lpi.h"
21 
22 #define MAX_LPI_NUM_CLKS	2
23 
24 struct lpi_pinctrl {
25 	struct device *dev;
26 	struct pinctrl_dev *ctrl;
27 	struct gpio_chip chip;
28 	struct pinctrl_desc desc;
29 	char __iomem *tlmm_base;
30 	char __iomem *slew_base;
31 	struct clk_bulk_data clks[MAX_LPI_NUM_CLKS];
32 	struct mutex slew_access_lock;
33 	const struct lpi_pinctrl_variant_data *data;
34 };
35 
36 static int lpi_gpio_read(struct lpi_pinctrl *state, unsigned int pin,
37 			 unsigned int addr)
38 {
39 	return ioread32(state->tlmm_base + LPI_TLMM_REG_OFFSET * pin + addr);
40 }
41 
42 static int lpi_gpio_write(struct lpi_pinctrl *state, unsigned int pin,
43 			  unsigned int addr, unsigned int val)
44 {
45 	iowrite32(val, state->tlmm_base + LPI_TLMM_REG_OFFSET * pin + addr);
46 
47 	return 0;
48 }
49 
50 static const struct pinctrl_ops lpi_gpio_pinctrl_ops = {
51 	.get_groups_count	= pinctrl_generic_get_group_count,
52 	.get_group_name		= pinctrl_generic_get_group_name,
53 	.get_group_pins		= pinctrl_generic_get_group_pins,
54 	.dt_node_to_map		= pinconf_generic_dt_node_to_map_group,
55 	.dt_free_map		= pinctrl_utils_free_map,
56 };
57 
58 static int lpi_gpio_get_functions_count(struct pinctrl_dev *pctldev)
59 {
60 	struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
61 
62 	return pctrl->data->nfunctions;
63 }
64 
65 static const char *lpi_gpio_get_function_name(struct pinctrl_dev *pctldev,
66 					      unsigned int function)
67 {
68 	struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
69 
70 	return pctrl->data->functions[function].name;
71 }
72 
73 static int lpi_gpio_get_function_groups(struct pinctrl_dev *pctldev,
74 					unsigned int function,
75 					const char *const **groups,
76 					unsigned *const num_qgroups)
77 {
78 	struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
79 
80 	*groups = pctrl->data->functions[function].groups;
81 	*num_qgroups = pctrl->data->functions[function].ngroups;
82 
83 	return 0;
84 }
85 
86 static int lpi_gpio_set_mux(struct pinctrl_dev *pctldev, unsigned int function,
87 			    unsigned int group_num)
88 {
89 	struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
90 	const struct lpi_pingroup *g = &pctrl->data->groups[group_num];
91 	u32 val;
92 	int i, pin = g->pin;
93 
94 	for (i = 0; i < g->nfuncs; i++) {
95 		if (g->funcs[i] == function)
96 			break;
97 	}
98 
99 	if (WARN_ON(i == g->nfuncs))
100 		return -EINVAL;
101 
102 	val = lpi_gpio_read(pctrl, pin, LPI_GPIO_CFG_REG);
103 	u32p_replace_bits(&val, i, LPI_GPIO_FUNCTION_MASK);
104 	lpi_gpio_write(pctrl, pin, LPI_GPIO_CFG_REG, val);
105 
106 	return 0;
107 }
108 
109 static const struct pinmux_ops lpi_gpio_pinmux_ops = {
110 	.get_functions_count	= lpi_gpio_get_functions_count,
111 	.get_function_name	= lpi_gpio_get_function_name,
112 	.get_function_groups	= lpi_gpio_get_function_groups,
113 	.set_mux		= lpi_gpio_set_mux,
114 };
115 
116 static int lpi_config_get(struct pinctrl_dev *pctldev,
117 			  unsigned int pin, unsigned long *config)
118 {
119 	unsigned int param = pinconf_to_config_param(*config);
120 	struct lpi_pinctrl *state = dev_get_drvdata(pctldev->dev);
121 	unsigned int arg = 0;
122 	int is_out;
123 	int pull;
124 	u32 ctl_reg;
125 
126 	ctl_reg = lpi_gpio_read(state, pin, LPI_GPIO_CFG_REG);
127 	is_out = ctl_reg & LPI_GPIO_OE_MASK;
128 	pull = FIELD_GET(LPI_GPIO_PULL_MASK, ctl_reg);
129 
130 	switch (param) {
131 	case PIN_CONFIG_BIAS_DISABLE:
132 		if (pull == LPI_GPIO_BIAS_DISABLE)
133 			arg = 1;
134 		break;
135 	case PIN_CONFIG_BIAS_PULL_DOWN:
136 		if (pull == LPI_GPIO_PULL_DOWN)
137 			arg = 1;
138 		break;
139 	case PIN_CONFIG_BIAS_BUS_HOLD:
140 		if (pull == LPI_GPIO_KEEPER)
141 			arg = 1;
142 		break;
143 	case PIN_CONFIG_BIAS_PULL_UP:
144 		if (pull == LPI_GPIO_PULL_UP)
145 			arg = 1;
146 		break;
147 	case PIN_CONFIG_INPUT_ENABLE:
148 	case PIN_CONFIG_OUTPUT:
149 		if (is_out)
150 			arg = 1;
151 		break;
152 	default:
153 		return -EINVAL;
154 	}
155 
156 	*config = pinconf_to_config_packed(param, arg);
157 	return 0;
158 }
159 
160 static int lpi_config_set(struct pinctrl_dev *pctldev, unsigned int group,
161 			  unsigned long *configs, unsigned int nconfs)
162 {
163 	struct lpi_pinctrl *pctrl = dev_get_drvdata(pctldev->dev);
164 	unsigned int param, arg, pullup = LPI_GPIO_BIAS_DISABLE, strength = 2;
165 	bool value, output_enabled = false;
166 	const struct lpi_pingroup *g;
167 	unsigned long sval;
168 	int i, slew_offset;
169 	u32 val;
170 
171 	g = &pctrl->data->groups[group];
172 	for (i = 0; i < nconfs; i++) {
173 		param = pinconf_to_config_param(configs[i]);
174 		arg = pinconf_to_config_argument(configs[i]);
175 
176 		switch (param) {
177 		case PIN_CONFIG_BIAS_DISABLE:
178 			pullup = LPI_GPIO_BIAS_DISABLE;
179 			break;
180 		case PIN_CONFIG_BIAS_PULL_DOWN:
181 			pullup = LPI_GPIO_PULL_DOWN;
182 			break;
183 		case PIN_CONFIG_BIAS_BUS_HOLD:
184 			pullup = LPI_GPIO_KEEPER;
185 			break;
186 		case PIN_CONFIG_BIAS_PULL_UP:
187 			pullup = LPI_GPIO_PULL_UP;
188 			break;
189 		case PIN_CONFIG_INPUT_ENABLE:
190 			output_enabled = false;
191 			break;
192 		case PIN_CONFIG_OUTPUT:
193 			output_enabled = true;
194 			value = arg;
195 			break;
196 		case PIN_CONFIG_DRIVE_STRENGTH:
197 			strength = arg;
198 			break;
199 		case PIN_CONFIG_SLEW_RATE:
200 			if (arg > LPI_SLEW_RATE_MAX) {
201 				dev_err(pctldev->dev, "invalid slew rate %u for pin: %d\n",
202 					arg, group);
203 				return -EINVAL;
204 			}
205 
206 			slew_offset = g->slew_offset;
207 			if (slew_offset == LPI_NO_SLEW)
208 				break;
209 
210 			mutex_lock(&pctrl->slew_access_lock);
211 
212 			sval = ioread32(pctrl->slew_base + LPI_SLEW_RATE_CTL_REG);
213 			sval &= ~(LPI_SLEW_RATE_MASK << slew_offset);
214 			sval |= arg << slew_offset;
215 			iowrite32(sval, pctrl->slew_base + LPI_SLEW_RATE_CTL_REG);
216 
217 			mutex_unlock(&pctrl->slew_access_lock);
218 			break;
219 		default:
220 			return -EINVAL;
221 		}
222 	}
223 
224 	val = lpi_gpio_read(pctrl, group, LPI_GPIO_CFG_REG);
225 
226 	u32p_replace_bits(&val, pullup, LPI_GPIO_PULL_MASK);
227 	u32p_replace_bits(&val, LPI_GPIO_DS_TO_VAL(strength),
228 			  LPI_GPIO_OUT_STRENGTH_MASK);
229 	u32p_replace_bits(&val, output_enabled, LPI_GPIO_OE_MASK);
230 
231 	lpi_gpio_write(pctrl, group, LPI_GPIO_CFG_REG, val);
232 
233 	if (output_enabled) {
234 		val = u32_encode_bits(value ? 1 : 0, LPI_GPIO_VALUE_OUT_MASK);
235 		lpi_gpio_write(pctrl, group, LPI_GPIO_VALUE_REG, val);
236 	}
237 
238 	return 0;
239 }
240 
241 static const struct pinconf_ops lpi_gpio_pinconf_ops = {
242 	.is_generic			= true,
243 	.pin_config_group_get		= lpi_config_get,
244 	.pin_config_group_set		= lpi_config_set,
245 };
246 
247 static int lpi_gpio_direction_input(struct gpio_chip *chip, unsigned int pin)
248 {
249 	struct lpi_pinctrl *state = gpiochip_get_data(chip);
250 	unsigned long config;
251 
252 	config = pinconf_to_config_packed(PIN_CONFIG_INPUT_ENABLE, 1);
253 
254 	return lpi_config_set(state->ctrl, pin, &config, 1);
255 }
256 
257 static int lpi_gpio_direction_output(struct gpio_chip *chip,
258 				     unsigned int pin, int val)
259 {
260 	struct lpi_pinctrl *state = gpiochip_get_data(chip);
261 	unsigned long config;
262 
263 	config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, val);
264 
265 	return lpi_config_set(state->ctrl, pin, &config, 1);
266 }
267 
268 static int lpi_gpio_get(struct gpio_chip *chip, unsigned int pin)
269 {
270 	struct lpi_pinctrl *state = gpiochip_get_data(chip);
271 
272 	return lpi_gpio_read(state, pin, LPI_GPIO_VALUE_REG) &
273 		LPI_GPIO_VALUE_IN_MASK;
274 }
275 
276 static void lpi_gpio_set(struct gpio_chip *chip, unsigned int pin, int value)
277 {
278 	struct lpi_pinctrl *state = gpiochip_get_data(chip);
279 	unsigned long config;
280 
281 	config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, value);
282 
283 	lpi_config_set(state->ctrl, pin, &config, 1);
284 }
285 
286 #ifdef CONFIG_DEBUG_FS
287 #include <linux/seq_file.h>
288 
289 static unsigned int lpi_regval_to_drive(u32 val)
290 {
291 	return (val + 1) * 2;
292 }
293 
294 static void lpi_gpio_dbg_show_one(struct seq_file *s,
295 				  struct pinctrl_dev *pctldev,
296 				  struct gpio_chip *chip,
297 				  unsigned int offset,
298 				  unsigned int gpio)
299 {
300 	struct lpi_pinctrl *state = gpiochip_get_data(chip);
301 	struct pinctrl_pin_desc pindesc;
302 	unsigned int func;
303 	int is_out;
304 	int drive;
305 	int pull;
306 	u32 ctl_reg;
307 
308 	static const char * const pulls[] = {
309 		"no pull",
310 		"pull down",
311 		"keeper",
312 		"pull up"
313 	};
314 
315 	pctldev = pctldev ? : state->ctrl;
316 	pindesc = pctldev->desc->pins[offset];
317 	ctl_reg = lpi_gpio_read(state, offset, LPI_GPIO_CFG_REG);
318 	is_out = ctl_reg & LPI_GPIO_OE_MASK;
319 
320 	func = FIELD_GET(LPI_GPIO_FUNCTION_MASK, ctl_reg);
321 	drive = FIELD_GET(LPI_GPIO_OUT_STRENGTH_MASK, ctl_reg);
322 	pull = FIELD_GET(LPI_GPIO_PULL_MASK, ctl_reg);
323 
324 	seq_printf(s, " %-8s: %-3s %d", pindesc.name, is_out ? "out" : "in", func);
325 	seq_printf(s, " %dmA", lpi_regval_to_drive(drive));
326 	seq_printf(s, " %s", pulls[pull]);
327 }
328 
329 static void lpi_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
330 {
331 	unsigned int gpio = chip->base;
332 	unsigned int i;
333 
334 	for (i = 0; i < chip->ngpio; i++, gpio++) {
335 		lpi_gpio_dbg_show_one(s, NULL, chip, i, gpio);
336 		seq_puts(s, "\n");
337 	}
338 }
339 
340 #else
341 #define lpi_gpio_dbg_show NULL
342 #endif
343 
344 static const struct gpio_chip lpi_gpio_template = {
345 	.direction_input	= lpi_gpio_direction_input,
346 	.direction_output	= lpi_gpio_direction_output,
347 	.get			= lpi_gpio_get,
348 	.set			= lpi_gpio_set,
349 	.request		= gpiochip_generic_request,
350 	.free			= gpiochip_generic_free,
351 	.dbg_show		= lpi_gpio_dbg_show,
352 };
353 
354 static int lpi_build_pin_desc_groups(struct lpi_pinctrl *pctrl)
355 {
356 	int i, ret;
357 
358 	for (i = 0; i < pctrl->data->npins; i++) {
359 		const struct pinctrl_pin_desc *pin_info = pctrl->desc.pins + i;
360 
361 		ret = pinctrl_generic_add_group(pctrl->ctrl, pin_info->name,
362 						  (int *)&pin_info->number, 1, NULL);
363 		if (ret < 0)
364 			goto err_pinctrl;
365 	}
366 
367 	return 0;
368 
369 err_pinctrl:
370 	for (; i > 0; i--)
371 		pinctrl_generic_remove_group(pctrl->ctrl, i - 1);
372 
373 	return ret;
374 }
375 
376 int lpi_pinctrl_probe(struct platform_device *pdev)
377 {
378 	const struct lpi_pinctrl_variant_data *data;
379 	struct device *dev = &pdev->dev;
380 	struct lpi_pinctrl *pctrl;
381 	int ret;
382 
383 	pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL);
384 	if (!pctrl)
385 		return -ENOMEM;
386 
387 	platform_set_drvdata(pdev, pctrl);
388 
389 	data = of_device_get_match_data(dev);
390 	if (!data)
391 		return -EINVAL;
392 
393 	pctrl->data = data;
394 	pctrl->dev = &pdev->dev;
395 
396 	pctrl->clks[0].id = "core";
397 	pctrl->clks[1].id = "audio";
398 
399 	pctrl->tlmm_base = devm_platform_ioremap_resource(pdev, 0);
400 	if (IS_ERR(pctrl->tlmm_base))
401 		return dev_err_probe(dev, PTR_ERR(pctrl->tlmm_base),
402 				     "TLMM resource not provided\n");
403 
404 	pctrl->slew_base = devm_platform_ioremap_resource(pdev, 1);
405 	if (IS_ERR(pctrl->slew_base))
406 		return dev_err_probe(dev, PTR_ERR(pctrl->slew_base),
407 				     "Slew resource not provided\n");
408 
409 	if (of_property_read_bool(dev->of_node, "qcom,adsp-bypass-mode"))
410 		ret = devm_clk_bulk_get_optional(dev, MAX_LPI_NUM_CLKS, pctrl->clks);
411 	else
412 		ret = devm_clk_bulk_get(dev, MAX_LPI_NUM_CLKS, pctrl->clks);
413 
414 	if (ret)
415 		return ret;
416 
417 	ret = clk_bulk_prepare_enable(MAX_LPI_NUM_CLKS, pctrl->clks);
418 	if (ret)
419 		return dev_err_probe(dev, ret, "Can't enable clocks\n");
420 
421 	pctrl->desc.pctlops = &lpi_gpio_pinctrl_ops;
422 	pctrl->desc.pmxops = &lpi_gpio_pinmux_ops;
423 	pctrl->desc.confops = &lpi_gpio_pinconf_ops;
424 	pctrl->desc.owner = THIS_MODULE;
425 	pctrl->desc.name = dev_name(dev);
426 	pctrl->desc.pins = data->pins;
427 	pctrl->desc.npins = data->npins;
428 	pctrl->chip = lpi_gpio_template;
429 	pctrl->chip.parent = dev;
430 	pctrl->chip.base = -1;
431 	pctrl->chip.ngpio = data->npins;
432 	pctrl->chip.label = dev_name(dev);
433 	pctrl->chip.of_gpio_n_cells = 2;
434 	pctrl->chip.can_sleep = false;
435 
436 	mutex_init(&pctrl->slew_access_lock);
437 
438 	pctrl->ctrl = devm_pinctrl_register(dev, &pctrl->desc, pctrl);
439 	if (IS_ERR(pctrl->ctrl)) {
440 		ret = PTR_ERR(pctrl->ctrl);
441 		dev_err(dev, "failed to add pin controller\n");
442 		goto err_pinctrl;
443 	}
444 
445 	ret = lpi_build_pin_desc_groups(pctrl);
446 	if (ret)
447 		goto err_pinctrl;
448 
449 	ret = devm_gpiochip_add_data(dev, &pctrl->chip, pctrl);
450 	if (ret) {
451 		dev_err(pctrl->dev, "can't add gpio chip\n");
452 		goto err_pinctrl;
453 	}
454 
455 	return 0;
456 
457 err_pinctrl:
458 	mutex_destroy(&pctrl->slew_access_lock);
459 	clk_bulk_disable_unprepare(MAX_LPI_NUM_CLKS, pctrl->clks);
460 
461 	return ret;
462 }
463 EXPORT_SYMBOL_GPL(lpi_pinctrl_probe);
464 
465 int lpi_pinctrl_remove(struct platform_device *pdev)
466 {
467 	struct lpi_pinctrl *pctrl = platform_get_drvdata(pdev);
468 	int i;
469 
470 	mutex_destroy(&pctrl->slew_access_lock);
471 	clk_bulk_disable_unprepare(MAX_LPI_NUM_CLKS, pctrl->clks);
472 
473 	for (i = 0; i < pctrl->data->npins; i++)
474 		pinctrl_generic_remove_group(pctrl->ctrl, i);
475 
476 	return 0;
477 }
478 EXPORT_SYMBOL_GPL(lpi_pinctrl_remove);
479 
480 MODULE_DESCRIPTION("QTI LPI GPIO pin control driver");
481 MODULE_LICENSE("GPL");
482