1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
4  * Copyright (c) 2020 Linaro Ltd.
5  */
6 
7 #include <linux/bitfield.h>
8 #include <linux/clk.h>
9 #include <linux/gpio/driver.h>
10 #include <linux/module.h>
11 #include <linux/of.h>
12 #include <linux/platform_device.h>
13 #include <linux/seq_file.h>
14 
15 #include <linux/pinctrl/pinconf-generic.h>
16 #include <linux/pinctrl/pinconf.h>
17 #include <linux/pinctrl/pinmux.h>
18 
19 #include "../pinctrl-utils.h"
20 
21 #include "pinctrl-lpass-lpi.h"
22 
23 #define MAX_NR_GPIO		23
24 #define GPIO_FUNC		0
25 #define MAX_LPI_NUM_CLKS	2
26 
27 struct lpi_pinctrl {
28 	struct device *dev;
29 	struct pinctrl_dev *ctrl;
30 	struct gpio_chip chip;
31 	struct pinctrl_desc desc;
32 	char __iomem *tlmm_base;
33 	char __iomem *slew_base;
34 	struct clk_bulk_data clks[MAX_LPI_NUM_CLKS];
35 	struct mutex slew_access_lock;
36 	DECLARE_BITMAP(ever_gpio, MAX_NR_GPIO);
37 	const struct lpi_pinctrl_variant_data *data;
38 };
39 
40 static int lpi_gpio_read(struct lpi_pinctrl *state, unsigned int pin,
41 			 unsigned int addr)
42 {
43 	return ioread32(state->tlmm_base + LPI_TLMM_REG_OFFSET * pin + addr);
44 }
45 
46 static int lpi_gpio_write(struct lpi_pinctrl *state, unsigned int pin,
47 			  unsigned int addr, unsigned int val)
48 {
49 	iowrite32(val, state->tlmm_base + LPI_TLMM_REG_OFFSET * pin + addr);
50 
51 	return 0;
52 }
53 
54 static const struct pinctrl_ops lpi_gpio_pinctrl_ops = {
55 	.get_groups_count	= pinctrl_generic_get_group_count,
56 	.get_group_name		= pinctrl_generic_get_group_name,
57 	.get_group_pins		= pinctrl_generic_get_group_pins,
58 	.dt_node_to_map		= pinconf_generic_dt_node_to_map_group,
59 	.dt_free_map		= pinctrl_utils_free_map,
60 };
61 
62 static int lpi_gpio_get_functions_count(struct pinctrl_dev *pctldev)
63 {
64 	struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
65 
66 	return pctrl->data->nfunctions;
67 }
68 
69 static const char *lpi_gpio_get_function_name(struct pinctrl_dev *pctldev,
70 					      unsigned int function)
71 {
72 	struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
73 
74 	return pctrl->data->functions[function].name;
75 }
76 
77 static int lpi_gpio_get_function_groups(struct pinctrl_dev *pctldev,
78 					unsigned int function,
79 					const char *const **groups,
80 					unsigned *const num_qgroups)
81 {
82 	struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
83 
84 	*groups = pctrl->data->functions[function].groups;
85 	*num_qgroups = pctrl->data->functions[function].ngroups;
86 
87 	return 0;
88 }
89 
90 static int lpi_gpio_set_mux(struct pinctrl_dev *pctldev, unsigned int function,
91 			    unsigned int group)
92 {
93 	struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
94 	const struct lpi_pingroup *g = &pctrl->data->groups[group];
95 	u32 val;
96 	int i, pin = g->pin;
97 
98 	for (i = 0; i < g->nfuncs; i++) {
99 		if (g->funcs[i] == function)
100 			break;
101 	}
102 
103 	if (WARN_ON(i == g->nfuncs))
104 		return -EINVAL;
105 
106 	val = lpi_gpio_read(pctrl, pin, LPI_GPIO_CFG_REG);
107 
108 	/*
109 	 * If this is the first time muxing to GPIO and the direction is
110 	 * output, make sure that we're not going to be glitching the pin
111 	 * by reading the current state of the pin and setting it as the
112 	 * output.
113 	 */
114 	if (i == GPIO_FUNC && (val & LPI_GPIO_OE_MASK) &&
115 	    !test_and_set_bit(group, pctrl->ever_gpio)) {
116 		u32 io_val = lpi_gpio_read(pctrl, group, LPI_GPIO_VALUE_REG);
117 
118 		if (io_val & LPI_GPIO_VALUE_IN_MASK) {
119 			if (!(io_val & LPI_GPIO_VALUE_OUT_MASK))
120 				lpi_gpio_write(pctrl, group, LPI_GPIO_VALUE_REG,
121 					       io_val | LPI_GPIO_VALUE_OUT_MASK);
122 		} else {
123 			if (io_val & LPI_GPIO_VALUE_OUT_MASK)
124 				lpi_gpio_write(pctrl, group, LPI_GPIO_VALUE_REG,
125 					       io_val & ~LPI_GPIO_VALUE_OUT_MASK);
126 		}
127 	}
128 
129 	u32p_replace_bits(&val, i, LPI_GPIO_FUNCTION_MASK);
130 	lpi_gpio_write(pctrl, pin, LPI_GPIO_CFG_REG, val);
131 
132 	return 0;
133 }
134 
135 static const struct pinmux_ops lpi_gpio_pinmux_ops = {
136 	.get_functions_count	= lpi_gpio_get_functions_count,
137 	.get_function_name	= lpi_gpio_get_function_name,
138 	.get_function_groups	= lpi_gpio_get_function_groups,
139 	.set_mux		= lpi_gpio_set_mux,
140 };
141 
142 static int lpi_config_get(struct pinctrl_dev *pctldev,
143 			  unsigned int pin, unsigned long *config)
144 {
145 	unsigned int param = pinconf_to_config_param(*config);
146 	struct lpi_pinctrl *state = dev_get_drvdata(pctldev->dev);
147 	unsigned int arg = 0;
148 	int is_out;
149 	int pull;
150 	u32 ctl_reg;
151 
152 	ctl_reg = lpi_gpio_read(state, pin, LPI_GPIO_CFG_REG);
153 	is_out = ctl_reg & LPI_GPIO_OE_MASK;
154 	pull = FIELD_GET(LPI_GPIO_PULL_MASK, ctl_reg);
155 
156 	switch (param) {
157 	case PIN_CONFIG_BIAS_DISABLE:
158 		if (pull == LPI_GPIO_BIAS_DISABLE)
159 			arg = 1;
160 		break;
161 	case PIN_CONFIG_BIAS_PULL_DOWN:
162 		if (pull == LPI_GPIO_PULL_DOWN)
163 			arg = 1;
164 		break;
165 	case PIN_CONFIG_BIAS_BUS_HOLD:
166 		if (pull == LPI_GPIO_KEEPER)
167 			arg = 1;
168 		break;
169 	case PIN_CONFIG_BIAS_PULL_UP:
170 		if (pull == LPI_GPIO_PULL_UP)
171 			arg = 1;
172 		break;
173 	case PIN_CONFIG_INPUT_ENABLE:
174 	case PIN_CONFIG_OUTPUT:
175 		if (is_out)
176 			arg = 1;
177 		break;
178 	default:
179 		return -EINVAL;
180 	}
181 
182 	*config = pinconf_to_config_packed(param, arg);
183 	return 0;
184 }
185 
186 static int lpi_config_set(struct pinctrl_dev *pctldev, unsigned int group,
187 			  unsigned long *configs, unsigned int nconfs)
188 {
189 	struct lpi_pinctrl *pctrl = dev_get_drvdata(pctldev->dev);
190 	unsigned int param, arg, pullup = LPI_GPIO_BIAS_DISABLE, strength = 2;
191 	bool value, output_enabled = false;
192 	const struct lpi_pingroup *g;
193 	unsigned long sval;
194 	int i, slew_offset;
195 	u32 val;
196 
197 	g = &pctrl->data->groups[group];
198 	for (i = 0; i < nconfs; i++) {
199 		param = pinconf_to_config_param(configs[i]);
200 		arg = pinconf_to_config_argument(configs[i]);
201 
202 		switch (param) {
203 		case PIN_CONFIG_BIAS_DISABLE:
204 			pullup = LPI_GPIO_BIAS_DISABLE;
205 			break;
206 		case PIN_CONFIG_BIAS_PULL_DOWN:
207 			pullup = LPI_GPIO_PULL_DOWN;
208 			break;
209 		case PIN_CONFIG_BIAS_BUS_HOLD:
210 			pullup = LPI_GPIO_KEEPER;
211 			break;
212 		case PIN_CONFIG_BIAS_PULL_UP:
213 			pullup = LPI_GPIO_PULL_UP;
214 			break;
215 		case PIN_CONFIG_INPUT_ENABLE:
216 			output_enabled = false;
217 			break;
218 		case PIN_CONFIG_OUTPUT:
219 			output_enabled = true;
220 			value = arg;
221 			break;
222 		case PIN_CONFIG_DRIVE_STRENGTH:
223 			strength = arg;
224 			break;
225 		case PIN_CONFIG_SLEW_RATE:
226 			if (arg > LPI_SLEW_RATE_MAX) {
227 				dev_err(pctldev->dev, "invalid slew rate %u for pin: %d\n",
228 					arg, group);
229 				return -EINVAL;
230 			}
231 
232 			slew_offset = g->slew_offset;
233 			if (slew_offset == LPI_NO_SLEW)
234 				break;
235 
236 			mutex_lock(&pctrl->slew_access_lock);
237 
238 			sval = ioread32(pctrl->slew_base + LPI_SLEW_RATE_CTL_REG);
239 			sval &= ~(LPI_SLEW_RATE_MASK << slew_offset);
240 			sval |= arg << slew_offset;
241 			iowrite32(sval, pctrl->slew_base + LPI_SLEW_RATE_CTL_REG);
242 
243 			mutex_unlock(&pctrl->slew_access_lock);
244 			break;
245 		default:
246 			return -EINVAL;
247 		}
248 	}
249 
250 	/*
251 	 * As per Hardware Programming Guide, when configuring pin as output,
252 	 * set the pin value before setting output-enable (OE).
253 	 */
254 	if (output_enabled) {
255 		val = u32_encode_bits(value ? 1 : 0, LPI_GPIO_VALUE_OUT_MASK);
256 		lpi_gpio_write(pctrl, group, LPI_GPIO_VALUE_REG, val);
257 	}
258 
259 	val = lpi_gpio_read(pctrl, group, LPI_GPIO_CFG_REG);
260 
261 	u32p_replace_bits(&val, pullup, LPI_GPIO_PULL_MASK);
262 	u32p_replace_bits(&val, LPI_GPIO_DS_TO_VAL(strength),
263 			  LPI_GPIO_OUT_STRENGTH_MASK);
264 	u32p_replace_bits(&val, output_enabled, LPI_GPIO_OE_MASK);
265 
266 	lpi_gpio_write(pctrl, group, LPI_GPIO_CFG_REG, val);
267 
268 	return 0;
269 }
270 
271 static const struct pinconf_ops lpi_gpio_pinconf_ops = {
272 	.is_generic			= true,
273 	.pin_config_group_get		= lpi_config_get,
274 	.pin_config_group_set		= lpi_config_set,
275 };
276 
277 static int lpi_gpio_direction_input(struct gpio_chip *chip, unsigned int pin)
278 {
279 	struct lpi_pinctrl *state = gpiochip_get_data(chip);
280 	unsigned long config;
281 
282 	config = pinconf_to_config_packed(PIN_CONFIG_INPUT_ENABLE, 1);
283 
284 	return lpi_config_set(state->ctrl, pin, &config, 1);
285 }
286 
287 static int lpi_gpio_direction_output(struct gpio_chip *chip,
288 				     unsigned int pin, int val)
289 {
290 	struct lpi_pinctrl *state = gpiochip_get_data(chip);
291 	unsigned long config;
292 
293 	config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, val);
294 
295 	return lpi_config_set(state->ctrl, pin, &config, 1);
296 }
297 
298 static int lpi_gpio_get(struct gpio_chip *chip, unsigned int pin)
299 {
300 	struct lpi_pinctrl *state = gpiochip_get_data(chip);
301 
302 	return lpi_gpio_read(state, pin, LPI_GPIO_VALUE_REG) &
303 		LPI_GPIO_VALUE_IN_MASK;
304 }
305 
306 static void lpi_gpio_set(struct gpio_chip *chip, unsigned int pin, int value)
307 {
308 	struct lpi_pinctrl *state = gpiochip_get_data(chip);
309 	unsigned long config;
310 
311 	config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, value);
312 
313 	lpi_config_set(state->ctrl, pin, &config, 1);
314 }
315 
316 #ifdef CONFIG_DEBUG_FS
317 #include <linux/seq_file.h>
318 
319 static unsigned int lpi_regval_to_drive(u32 val)
320 {
321 	return (val + 1) * 2;
322 }
323 
324 static void lpi_gpio_dbg_show_one(struct seq_file *s,
325 				  struct pinctrl_dev *pctldev,
326 				  struct gpio_chip *chip,
327 				  unsigned int offset,
328 				  unsigned int gpio)
329 {
330 	struct lpi_pinctrl *state = gpiochip_get_data(chip);
331 	struct pinctrl_pin_desc pindesc;
332 	unsigned int func;
333 	int is_out;
334 	int drive;
335 	int pull;
336 	u32 ctl_reg;
337 
338 	static const char * const pulls[] = {
339 		"no pull",
340 		"pull down",
341 		"keeper",
342 		"pull up"
343 	};
344 
345 	pctldev = pctldev ? : state->ctrl;
346 	pindesc = pctldev->desc->pins[offset];
347 	ctl_reg = lpi_gpio_read(state, offset, LPI_GPIO_CFG_REG);
348 	is_out = ctl_reg & LPI_GPIO_OE_MASK;
349 
350 	func = FIELD_GET(LPI_GPIO_FUNCTION_MASK, ctl_reg);
351 	drive = FIELD_GET(LPI_GPIO_OUT_STRENGTH_MASK, ctl_reg);
352 	pull = FIELD_GET(LPI_GPIO_PULL_MASK, ctl_reg);
353 
354 	seq_printf(s, " %-8s: %-3s %d", pindesc.name, is_out ? "out" : "in", func);
355 	seq_printf(s, " %dmA", lpi_regval_to_drive(drive));
356 	seq_printf(s, " %s", pulls[pull]);
357 }
358 
359 static void lpi_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
360 {
361 	unsigned int gpio = chip->base;
362 	unsigned int i;
363 
364 	for (i = 0; i < chip->ngpio; i++, gpio++) {
365 		lpi_gpio_dbg_show_one(s, NULL, chip, i, gpio);
366 		seq_puts(s, "\n");
367 	}
368 }
369 
370 #else
371 #define lpi_gpio_dbg_show NULL
372 #endif
373 
374 static const struct gpio_chip lpi_gpio_template = {
375 	.direction_input	= lpi_gpio_direction_input,
376 	.direction_output	= lpi_gpio_direction_output,
377 	.get			= lpi_gpio_get,
378 	.set			= lpi_gpio_set,
379 	.request		= gpiochip_generic_request,
380 	.free			= gpiochip_generic_free,
381 	.dbg_show		= lpi_gpio_dbg_show,
382 };
383 
384 static int lpi_build_pin_desc_groups(struct lpi_pinctrl *pctrl)
385 {
386 	int i, ret;
387 
388 	for (i = 0; i < pctrl->data->npins; i++) {
389 		const struct pinctrl_pin_desc *pin_info = pctrl->desc.pins + i;
390 
391 		ret = pinctrl_generic_add_group(pctrl->ctrl, pin_info->name,
392 						  (int *)&pin_info->number, 1, NULL);
393 		if (ret < 0)
394 			goto err_pinctrl;
395 	}
396 
397 	return 0;
398 
399 err_pinctrl:
400 	for (; i > 0; i--)
401 		pinctrl_generic_remove_group(pctrl->ctrl, i - 1);
402 
403 	return ret;
404 }
405 
406 int lpi_pinctrl_probe(struct platform_device *pdev)
407 {
408 	const struct lpi_pinctrl_variant_data *data;
409 	struct device *dev = &pdev->dev;
410 	struct lpi_pinctrl *pctrl;
411 	int ret;
412 
413 	pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL);
414 	if (!pctrl)
415 		return -ENOMEM;
416 
417 	platform_set_drvdata(pdev, pctrl);
418 
419 	data = of_device_get_match_data(dev);
420 	if (!data)
421 		return -EINVAL;
422 
423 	if (WARN_ON(data->npins > MAX_NR_GPIO))
424 		return -EINVAL;
425 
426 	pctrl->data = data;
427 	pctrl->dev = &pdev->dev;
428 
429 	pctrl->clks[0].id = "core";
430 	pctrl->clks[1].id = "audio";
431 
432 	pctrl->tlmm_base = devm_platform_ioremap_resource(pdev, 0);
433 	if (IS_ERR(pctrl->tlmm_base))
434 		return dev_err_probe(dev, PTR_ERR(pctrl->tlmm_base),
435 				     "TLMM resource not provided\n");
436 
437 	pctrl->slew_base = devm_platform_ioremap_resource(pdev, 1);
438 	if (IS_ERR(pctrl->slew_base))
439 		return dev_err_probe(dev, PTR_ERR(pctrl->slew_base),
440 				     "Slew resource not provided\n");
441 
442 	ret = devm_clk_bulk_get_optional(dev, MAX_LPI_NUM_CLKS, pctrl->clks);
443 	if (ret)
444 		return ret;
445 
446 	ret = clk_bulk_prepare_enable(MAX_LPI_NUM_CLKS, pctrl->clks);
447 	if (ret)
448 		return dev_err_probe(dev, ret, "Can't enable clocks\n");
449 
450 	pctrl->desc.pctlops = &lpi_gpio_pinctrl_ops;
451 	pctrl->desc.pmxops = &lpi_gpio_pinmux_ops;
452 	pctrl->desc.confops = &lpi_gpio_pinconf_ops;
453 	pctrl->desc.owner = THIS_MODULE;
454 	pctrl->desc.name = dev_name(dev);
455 	pctrl->desc.pins = data->pins;
456 	pctrl->desc.npins = data->npins;
457 	pctrl->chip = lpi_gpio_template;
458 	pctrl->chip.parent = dev;
459 	pctrl->chip.base = -1;
460 	pctrl->chip.ngpio = data->npins;
461 	pctrl->chip.label = dev_name(dev);
462 	pctrl->chip.can_sleep = false;
463 
464 	mutex_init(&pctrl->slew_access_lock);
465 
466 	pctrl->ctrl = devm_pinctrl_register(dev, &pctrl->desc, pctrl);
467 	if (IS_ERR(pctrl->ctrl)) {
468 		ret = PTR_ERR(pctrl->ctrl);
469 		dev_err(dev, "failed to add pin controller\n");
470 		goto err_pinctrl;
471 	}
472 
473 	ret = lpi_build_pin_desc_groups(pctrl);
474 	if (ret)
475 		goto err_pinctrl;
476 
477 	ret = devm_gpiochip_add_data(dev, &pctrl->chip, pctrl);
478 	if (ret) {
479 		dev_err(pctrl->dev, "can't add gpio chip\n");
480 		goto err_pinctrl;
481 	}
482 
483 	return 0;
484 
485 err_pinctrl:
486 	mutex_destroy(&pctrl->slew_access_lock);
487 	clk_bulk_disable_unprepare(MAX_LPI_NUM_CLKS, pctrl->clks);
488 
489 	return ret;
490 }
491 EXPORT_SYMBOL_GPL(lpi_pinctrl_probe);
492 
493 int lpi_pinctrl_remove(struct platform_device *pdev)
494 {
495 	struct lpi_pinctrl *pctrl = platform_get_drvdata(pdev);
496 	int i;
497 
498 	mutex_destroy(&pctrl->slew_access_lock);
499 	clk_bulk_disable_unprepare(MAX_LPI_NUM_CLKS, pctrl->clks);
500 
501 	for (i = 0; i < pctrl->data->npins; i++)
502 		pinctrl_generic_remove_group(pctrl->ctrl, i);
503 
504 	return 0;
505 }
506 EXPORT_SYMBOL_GPL(lpi_pinctrl_remove);
507 
508 MODULE_DESCRIPTION("QTI LPI GPIO pin control driver");
509 MODULE_LICENSE("GPL");
510